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JUNE 20, 1979 



CR-78 



CR-78 



SERVICE NOTES 



Panel no. 255 
(072-235) 



Pots . 

LYE 6 B 001 - 10 KB 

( 029 - 410 ) 



Pot. 

EVHCOAP25B14 

(026-021) 



Switch 
SRMIOIC 
( 001 - 242 ) ■ 

Knob no. 44 
(016-044) _ 



Knob No . 48 
( 016 - 048 ) 



Pot . 

LYE6B001-50KB 

(029-411) 



Pot . 

BVHCOAP25B15 

(026-024) 

Knob No. 45 
(016-043) 



LED SIP-1 31B — I 
(red) 

(019-013) 



Swith 
SUP55 
(001-241) 
I^ob No. 80 
( 016 - 080 ) 



'Switch 

SDG5P 

(001-215) lOOV 
(001-216) 117V 

(001-217) 220/240V 
Knob No. 81 
_ (016-081) 




Switch 
SRA202B 
(001-244) 



LED SLP-151B red 
(019-013) 



Switch — 

SRM1025 

(001-245) 



P Switch 
SLR- 5 25 
(001-245) 



Switch 

SLR-825 

( o /I /C ^ 

\ WW_L — J 

Knob No. 67 
(016-067) _ 

Switch 
SLR-522 
(001-231) 



Switch 
KCA10057 
(001-273) 



Switch 

KCA10057 

(001-273) 



Switch 

SLR-522 

(001-251) 



Cabinet No. 115 
(081-113) 



Base (foot) No. 20 
( 111 - 020 ) 



Switch 

SUEA2 

(001-259) 



Switch 

SUEB2 (001-240) Buttons 



8'16'COMBI TRIGGER OUT START/STOP VARIATION 



I — uu 
HIGH IMP 





CM] 







Switch HSW0572-01-050 
(001-206) 



Jacks SG7622 #8 (009-012) 



(016-008) G-ray 
(016-085) White 
(016-086) Red 
(016-087) Green 
(016-088) Yellow 
(016-089) Blue 



Printed in Japan Jul. '82 E-2 



LOGIC SYMBOL 



F4013 





CONNECTION DIAGRAM 



DIP (TOP VIEW) 


'L 


7 '^''dd 






Q, Qj 






CP, 




-'ll 


Cot Ci>2 






^1 C02 


□ ,o 


eC 


3di 02 




< 


''SS Sp2 





NOTE; 

The Flatpak version has the same 
pinouts (Connection Diagram) as the 
Dual In-line Package. 



F4013 TRUTH TABLES 



SYNCHRONOUS 

INPUTS 


OUTPUTS 


CP D 


Qn+1 Qn-M 


-T L 

S H 


L H 

H L 



Conditions: Sp = Cq = LOW 



ASYNCHRONOUS 

INPUTS 


OUTPUTS 


Sd Cq 


Q Cl 


L H 

H L 

H H 


L H 

H L 

L L 



L » LOW Level 

H “HIGH Level 
S " Positive-Going Transition 

X “ Don't Care 

Qfi +1 “ State After Clock Positive Transition 



F4001 QUAD 2-INPUT NOR GATE 



F4001 

LOGIC AND CONNECTION DIAGRAM 

DIP (TOP VIEW) 



'^DD 

fJ 1 fh] R [J] [L] rn Y] 





LfeJ L<^ 


r 





LE [ij UJ bJ hJ lij LzJ 

^ss 



SN74LS174. 



SN74LS175. F40175 



SN54174, SN54LS174, SN54S174 . . . J OR W PACKAGE 
SN74174, SN74LS174, SN74S174 . . . J OR N PACKAGE 
(TOP VIEW) 



Vcc 60 60 SO SO 40 40 CLOCK 



mjij 


m 


n 


m 


m 


m 


mioi 


■ 


1 


1 


|B 


] 


c 

L. D Q - 

-C >CK 
CLEAR 


i 


B 


c 


L-,’ 

AR 

CK< > 


7±z 

CLEAR 
-< >CK 
f- D 0 

C 


] 




i 


wm 


iJ 


3 




NT 


0 


1 


line 



CLEAR 10 1D 20 20 30 30 GNO 



DECODERS/DEMULTIPIEXERS 



SN54LS138, SN54S138 . . . J OR W PACKAGE 
SN74LS138, SN74S138 . . . J OR N PACKAGE 
(TOP VIEW) 



V2 Y3 Y4 Y5 Y6^ 










LS138, S138 




DATA 

OUTPUTS 



LS138, S138 
FUNCTION TA8LE 



INPUTS 


OUTPUTS 


ENABLE 


SELECT 


G1 


G2* 


C 


B 


A 


YO 


Y1 


< 

to 


Y3 


Y4 


Y5 


Y6 


Y7 


X 


H 


X 


X 


X 


H 


H 


H 


H 


H 


H 


H 


H 


L 


X 


X 


X 


X 


H 


H 


H 


H 


H 


H 


H 


H 


H 


L 


L 


L 


L 


L 


H 


H 


H 


H 


H 


H 


H 


H 


L 


L 


L 


H 


H 


L 


H 


H 


H 


H 


H 


H 


H 


L 


L 


H 


L 


H 


H 


L 


H 


H 


H 


H 


H 


H 


L 


L 


H 


H 


H 


H 


H 


L 


H 


H 


H 


H 


H 


L 


H 


L 


L 


H 


H 


H 


H 


L 


H 


H 


H 


H 


L 


H 


L 


H 


H 


H 


H 


H 


H 


L 


H 


H 


H 


L 


H 


H 


L 


H 


H 


H 


H 


H 


H 


L 


H 


H 


L 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


L 



•G2 = G2A t G2B 

H = high level, L “ low level, X - irrelevant 



SN54175, SN54LS175, SN54S175 . . . J OR W PACKAGE 
SN74175, SN74LS175, SN74S175 . . . J OR N PACKAGE 
(TOP VIEW) 




NOTE: 

In using F40175 , 



refer to note 
on page 8. 

QUADRUPLE D-TYPE FLIP-FLOPS 



FUNCTION TABLE 
(EACH FLIP-FLOP) 



1 INPUTS 1 


1 OUTPUTS 1 


i CLEAR CLOCK 


D 


Q 


Qt 


L 


X 


X 


L 


H 


H 


t 


H 


H 


L 


H 


t 


L 


L 


H 


H 


L 


X 


Qo 





H “ high level (steady state) 

L low level (steady state) 

X • irrelevant 

t • transition from low to high level 
CXq » the level of Q before the indicated steady-state 
input conditions were established. 

^ “ '175, 'LSI 75, and *S 1 75 only 



HEX INVERTERS 



Vcc &A 6Y 5A 5Y 4A 4Y 

f— 1 r— 1 -t— t f— 4 i— -I r—t r-|-j 

1[>J 1[>J 

hukuki 



ULUTBliJIiJIiJ-lif 

1A IV 2A 2V 3A 3Y GND 



SNS404 (J) 
SN54H04 (J) 
SNB4L04 (J) 
SN54LS04 U, W) 
SN54S04 U.W) 



SN7404 (J, N) 
SN74H04 (J, N) 
SN74L04 (J, N) 
SN74LS04 (J, N) 
SN74S04 (J, N) 



QUADRUPLE 2-INPUT 
POSITIVE-NANO GATES 




SN54(X) (J) SN74(X) (J. N) 

SN54HCX) (J) SN74HOO (J, N) 

SN54LQ0 (J) SN74L00 (J, N) 

SN54LS(X) (J, W) SN74LS00 (J, N) 

SNS4S00(J,W) SN74S00(J,N) 



Roland 
















CR-78 



JUNE 20, 1979 



CR-78 BLOCK DIAGRAM 




f 

( 



/' 



I 



( 



( 



2 










JUNE 20, 1979 



SPECIFICATIONS 

OUTPUT IMPEDANCE 

H: 220k ohms L: 10k ohms 

OUTPUT LEVEL 

H: 3»5Vpp into 220k 

L: 5»5'^PP into 10k 
(VOL. ACC. max) 

TRIGGER: +15 V 

EXT. CLOCK 

+5V +15V 

min. 5nis in length 
POWER OONSIMPTIOK 
9W (117V) 

15W (220/240V) 

DIMERS lOKS 

500(W)x.280(D)x250(H) mm 
11.8 X 11.0 X 8.1 in 
NET WEIGHT 

5.5Kg 12.1 Ihs 



TmcW 






Oi)T 



Rear Boa^ 

cowbi il>"f 



^Vsf L 



^T.CLOCK 



OUT PUT 
H14-H tfilA/' 






\Ja.Y'\ _j° 

lOok^B), 



9 /O U /Z 



-Ci ^ ^ 



/<2f» 3! 



IZ340 Pi 

<S5 ^ 4-2) 

76 ^ 74 s ^ £0 



? lO 
AvTo <t 



I 

I 

n 20 i 

2/7 




s T 



iiiiiin 

iiiiiir 




OP-105 



n n 



28 2fJ2L2S 



L0(t(C Boad (q-L-9 



Ti?iHpe 

IN OoT LED 
3 4- 20 2/ 




PI ( -5V ) 



SGA 0.125A 
(008-022) 



CEE T50mA 
(008-053) 



VI? 104- 
Accent 



EXT. CLOCK CIRCUIT: 
inciependent of OP-104 
S/N up to 780699, mounted 
on OP-129. 



/ €r 



jL cb 
+y p 

S 

20 Ti>L 



26 2S2i62i242fr 
tS ^ -5 +15 



li 

LXi > 



/3 cYoyr 
2/ 8 "ooT 
22 MBm 
32 



6/4-6$ 3943 4/42 43 ^ 



13?_ 



iuSES RATING 



l/R Bead 

op-103 



/ 

f- 


Out 


2 

7- 




3 

7i 


BO 


4- 

7- 


cr 


S 


MB 


& 


Tb 


7 




& 

9-^ 


Add 



MA78/40S 



M76m 



i a 
\jJ S 



E2 ( Jl5V ) 



SGA lA 
(008-026) 



CEE T 25 0mA 
(008-060) 



F3 ( +5V ) 



SGA 0.5A 
(008-024) 



E4 ( prim. ) 



SGA 0.5A 
(008-024) 



CEE T400mA CEE T250mA 
(008-062) (008-060) 


















CR-78 CIRCUITS TIMING DIAGRAM 



//PD8048 



CR-78 



(Top V iew) 



JUNE 20, 1979 



One chip michrocomputer //PD8048C— 015 



CPl(Mster osc reset, 
TO (Master output) — 
Decoder 0-5, 9 



Decoder 7 

Decoder 8 

Decoder 11-14 
( 6 , 10 = H level , 



Decoder 



Decoder 



Decoder 



PROGRAM off mode 



Decoder 10 



WRITE Switch 



12 and 13| are output only 
PROGRAM on mode 



after "START") 



Other pins' condition are the same as shown in "off". 



TO 
XTAL 1 




The )tPD 8048 is an 8-hit parallel computer fabricated on a single sillicon 
chip. The 8048 contains a Ik x 8 ROM program memory, a 64 x 8 RAM memo- 
ry, 27 I/O lines, an 8-hit timer/counter and clock circuits. 

Used in the CR-78 is a uPD80480-015 version in which the programs and 
data dedicated to the CR-78 are stored in program memory. 



Power on 



Initiation 



CR-78 Flowchart 



Plow Chart 



Onset of a measure ? 



PROGRAM RHYTHM 'SELECTOR 



k : — 1 cycle — )l 



k — 1 cycle — ^ 
3ms 



PROGRAM RHYTHM SELECTOR 



Decoder 0 
Decoder 1 



Decoder 



Decoder 



Decoder 4 



Decoder 5 
Decoder Z 
Decoder 7 
Decoder 8 
Decoder 9 
Decoder To 

Decoder 11 
Decoder 12 
Decoder 13 

Decoder 14 
Decoder 15 



OFE ' 



PROGRAM RYHTM SELECTOR 



MAIHJ . VARI . EE reset 



WALTZ-SWING 
FOX TROT-RHUMBA 
ROCK-DISCO 
MEASURE, M.VARI. A/B 



VARIATION 

IKSTRMNT.SELCT. PRGRM- 



PROGRAM. CLEAR 
CANCEL 



WRITE EE reset 



EXT. RAM enable 



IC116 latch 



IC112, IC113 latch 



10114 latch 
IC115 latch 



no connection 



!<« — 1 cycle ^ 

10ms ( TEMPO full clockwise) 



— 1 cycle 



Prepare the next data 



Read CANCEL SWITCH 
( Group H ) 



START/STOP SWITCH 
T1 ? 



MASTER OSCILLATOR 



WRITE SWITCH 
INT ? 



MASTER OSCILLATOR 



Output data to 



Read VARIATION SWITCH 



Read SWITCHES: 

A to G groups 



Read SWITCHES: 

PROGRAM and INSTRUMENT 

Write Rhythm patterns into RAM 



VOICING and LED circuits 



4 











JUNE 20, 1979 




CIRCUIT DESCRIPTION 

The CR-78 is a computerized rhythm machine whose 
rhythms are controlled by the resident computer 
through internally stored programs. Rhythms 
other than stored can be programed as desired by 
using the built-in expansion ROM and RAMs. Sequen- 
tial program order is outlined in the flow chart 
and the timing diagram shows relationship among 
principal, circuits waveforms. ( see previous page ) 
The following description is composed of two sec- 
tions: General Introduction and Detailed func- 
tion. Title numbers refer to those in flow chart. 

GENERAL INTRODUCTION 

1. POWER ON 

When power is first applied, two oscillators 
start oscillation: MASTER OSCILLATOR, determines 

rhythm tempo, ranging from 5Hz to lOOHz ; 

CLOCK GENERATOR, generates timing pulses for the 
8048 in each step cycle. 

2. 2B. SWITCH BANNING 

Even in the stop mede, the computer needs to 
store a data on switching status so as to output 
rhythm patterns immediately after the START/STOP 
switch is depressed. And also a status data is 

needed at the beginning of a measure. 

The switch reading to obtain a switch set-up data 
is refereed to as switch scanning. 

From Port 2 of 8048, signals are routed through 
the Decoders IC107 and IC108, and the switch 
matrix to Port 1. Combination of two port's pins 
according to switch settings becomes a data on 
switch status. After a rhythm runs, scanning is 
done onee for each measure. 

3. PROCESSING and PREPARING DATA 

The 8048 prepares the next data according to the 
internal program based on switch scanning data. 

4. SCANNING CANCEL VOISE SWITCH 

Since switch scanning is performed once for one 
measure during rhythm rimning, switching during 
the measure is effective in the subsequent meas- 
ure. However, "CANCEL VOICE" is scanned every 
cycle to cancel the unwanted voice at once when- 
ever it is specified. 



5. SENSING START/STOP SWITCHING 

As long as Tl, the START/STOP sensing input 
terminal of jiPD8048 is kept low, the program 
routine is not allowed to break loop through 
1-5, returning to 1. When the START/STOP 
switch is pushed while a rythm stops, Tl is 
pulled to high to start a rhythm and falls 
to low when the START/STOP is pushed again.(stop) 

6. SENSING MASTER OUTPUT PALLING 

Although each circuit operates its given task 
in sequence under the control of timing pulses 
from the CLOCK GENERATOR, each program step must 
keep pace with oscillation of the master osc. 
(rhythm tempo) by sensing the falls and rises 
of waveforms of the master oscillator. 

A program step proceeds to the next step when 
the master's trailing edge goes to negative. 

7. SENSING WRITE SWITCHING 

When the WRITE switch is tapped, the write hold 
circuit IC118 is set, applying high level to 
INT, and causing program routine to jump to 7B. 

7B. WRITING PROGRAM RHYTHM 

Scanning signals from 6 and 7 of the decoder IC- 
108 tell the computer which position of INSTRU- 
MENT and which PROGRAM push switch is selected. 
Then the data on PROGRAM rhythm are stored into 
the RAMs IC102 and IC103 under the control of a 
program from the ROM IC104. The RAMs provide 
memory size for two measures for each voice. 

8. SENSING MASTER RISING 

The computer executes a program, synchronizing 
its step with a rhythm tempo. As soon as TO 
receives the rise of a master square, 8048 
starts to produce rhythm patterns by sending 
data and control signals out from Port 1 and 2. 

9. OUTPUTTING DATA 

The Port 1 this time serves as an output port, 
feeding data for rhythm patterns (VOICES) and 
LEDs (TRACK) to the ,latehes IC112-IC116 which 
selectively latch them in sequence under the 
control of signals coming from the Port 2 
through the Decoder IC107. The computer per- 
forms the entire loop once for one cycle of 
master oscillator and 48 times per measure. 



CR-78 



FUNCTION -Detail- 



1 . POWER ON 

Resetting of the START/STOP fli- 
flop IC109A inhibits a rhythm from 
running by holding Tl of ^PD8048 at 
low level until the START/STOP 
switch is first tapped. 

When power is on, since the both 
pins 12 and 13 of IClllA are 
grounded momentarily, its output 
(pin 11 ) level swings to high re- 
setting the RS flip flop IC109A 
which in turn develops high out- 
put at pin 2f setting Tl level to 
low (through Q5-Q7, IC117A and Qll). 
Pins 12 and 13 of IClll will go 
positive as C103 charges, but IC- 
109A output is kept high until the 
START/STOP switch is depressed. 



IC109 I^in 4 

FF reset 



IC109 Pin 2 

FF Q 



Q7 Emitter 



ICIOI 8048 Tl 



IClll Pin 4 
(Master reset pulse) 



Q1 Collector 
(Master Ocillator) 




2. NO DETAIL 



2B. SWITCH SCANNING 



Switch scanning cycle initiates to 
generate internally programed 
binary signals from the Port 2, 
P24-P27, feeding them to IC108, 
binary-to-hexadecimal decoder, 
from which decoded signals are 
routed to respective switch groups. 
Prom the decoder only one pin out- 
puts negative going pulse while the 
rest pins output H, and the next 
pin outputs H with the rest L. 

These outputs of signals occur in 
sequence within a time interval of 
microseconds and repeats over and 



ICIOI IC108 




over again every few milliseconds 
until the START/STOP switch is depressed to run 
the rhythm. After running, scanning siganls are 
outputed once at the onset of a measure. 

This means that changing of any switch setting 
during a measure is ignored by the computer 



In MANUAL mode, VARIATION change during a 
measure is enabled at the beginning of the 
next measure by holding that changing in- 
formation until the next scanning is per- 
formed. 



unless switch setting is kept unchanged until 
the next scanning. 

Similarly, changing the MEASURE of VARIATION in 
AUTO mode will be made into effective only after 
previousely specified measure (s) has passed. 



For this purpose the MANUAL VARI hold 
circuit is used which consists of IC119. 
When the START/STOP switch is pressed while 
a rhythm stops, the RS flip flop IC119 
(pins 1-6) is reset by a pulse from 0 of 
IC108, switching pin 3 to H and pin 6 to L„ 



5 





Depressing the MANUAL 
switch during rhythm run- 
ning sets the FD IC119A/B, 
holding pin 6 or pin 13 
at H. When a master out- 
put goes low, a scanning 
pulse is generated from 4 
of 10108^ after inverted 
by 10121^ it is NANDed 
with pin 13 input, causing 
pin 11 to develop a 
negative going pulse 
which is detected by the 
8048 through Pl6, this is 
MANUAL "ON" information. 




IC119 Pin 6(13) (F 
IC119 Pin 12 




Switch 

Scanning 

Pulse 



IC119 Pin 11 




After scanning, a reset 
pulse is applied from 0 
of IC108 to pin 2 through 
the NAND circuit IC119D. 



3. NO DETAIL 

4. NO DETAIL 




5. SENSING START/STOP SWITCHING 



However, if the FADE IN or FADE OUT switch is in 



The START/STOP FF IC109A receives a positive 
going pulse each time the START/STOP switch is 
pushed, switching its output H or L and 
holding it until the next push is made. 

Pushing the START/STOP switch applies a posi- 
tive pulse to pin '3 of the START/STOP FF 10- 
109A causing it to have a high or low output 
until the START/STOP switch is pressed again. 
The output from the FF is applied through Q5,Q6 
and OP-100 to pin 6 of the comparator IC117A 
which provides a reference voltage at pin 5. 
When an input to pin 6 of the comparator 
exceeds the reference voltage of pin 5, the 
comparator senses it, sending output to; 

1. T1 of 8048 to start the rhythm, 

2. the master oscillator and 8 and 16 beat 
dividers IC109B and ICllO through the one shot 
pulse generator IClll (pins 1-6) to reset them 
and to synchronize their starts. 

When the voltage at pin 6 of the comparator 
drops below the reference voltage, low out- 
put is applied to T1 to stop the rhythm. 



closed position, voltage swing at T1 is delayed 
behind START/STOP switching due to the time con- 
stant in the fade circuit . (detailed later) 

6. MASTER OSCILLATOR 

The master oscillator output waveform has a duty 
ratio of over 50%. 

When the WRITE switch is tapped, the WRITE FF IC- 
118 is set, applying high output to INT pin of 
8048 which will go low when the master output 
falls. This is a "WRITE ON" information to the 
computer, upon receiving the "write on" infor- 
mation, switch scanning pulses are sent from 0, 

7, 9 and 10 of the decoders and associated 
data are memorized into external RAMs IC102 and 
IC103. The circuit configuration and function 
of the WRITE FF are much the same as in the 
MANUAL FF except for reset timing. 

As shown in the figure, whenever the write 

switch is tapped, as long as it is occured during - 
master's high level period, information is rec- I 
ognized by the computer when the master output 



CR-78 



JUNE 20, 1979 



falls, however, if the write switch is 
tapped during low level period, it is 
treated as it is occured during the next 
high level period, and then, sound is 
reproduced, being delayed by ^ cycle of 
the master oscillator. 

The longer high level period of the master 
oscillator waveform is intended to com- 
pensate for delayed timing of key opera- 



Master Oscillator 
IC107 Pin -14 , 9 



IC120 Pin 10 



I4--INT FF reset- 



WRITE 

SW 



Store 



WRITE 

SW 



Store 



7. NO DETAIL 



7B. WRITING PROGRAM RHYTHM 



As described in section 6, when the write switch 
is tapped during a measure, information on 
PROGRAM rhythm are stored in RAMs at the sbsequent 
master square trailing edge, and INT of 8048 
receives H input from the write hold circuit which 
consists of IC118 which functions in the same way 
as in the MANUAL VARI.( in this case reset pulse 
is fed from pin 14 or 9 of IC107). 

When the write switch is depressed during a measure, 
H level is applied at INT pin and is held until 
master falls, this is "write on" information, and 
the computer detects through switch scanning 
(pulses from 6 and 7 of IC108) which of PROGRAM 
switches and which position of INSTRUMENT switch 
is selected. 

The selected INSTRUMENT is first stored into RAM, 
then rhythm patterns are stored. 

When the same instrument has been addressed in 
the RAM track, rhythm patterns being written are 
added to the patterns previously stored in the RAM 
and will not be stored in another track independ- 
ently . 

Required bit numbers for two measures are: 

4 (PROGRAM) X 4 (INSTRUMENT) x 96 steps (48 x 2) 

= 1536 bits . 

Data transfer to/from RAMs and ROM are performed 
as follows: 

ALE (Address Latch Enable) 

This signal occurs once for 15 Clock Generator 
frequency , that is, 250kHz, and latches address 
being output ed from DB, through internal program, 
delivering the latched signals to RAMs and ROM. 

ROM (IC104) 

Program memory addressed by the address signals 
from the lateches IC105 , IC106 and P20 and P21 is 
fetched when PSEN is low at 2B and 7B of the flow- 
chart . 



RAM (IC102, IC103) 

Stored data are read when RD is low 
at 2B and 7B of the flow chart. 
Information are stored when WR is low 
at 7B of the flow chart. 



CYCLE TIMING FOR EXTERNAL 
DATA MEMORY (RAM) WRITE/READ 



ADDRESS READ WRITE 

T i/o'y address ADDKKSS y>ORT I/O 



CYCLE TIMING FOR EXTERNAL 
PROGRAM MEMORY (ROM) READ 



ADDRESS INSTRUCTION 



6 





JUNE 20, 1979 



CR-78 



8. 9. DATA OUTPUT 

- LATCH CIRCUITS - 

When the program proceeds at data output 
routine, Port 1 this time acts as an out- 
put port since it is a bidirectional port, 
representing the data through internal 
program memory or external ROM and RAMs,data 
are sent from P10-P17 to IC112-IC116 latch 
circuits whose clock input pins receive 
latch signals from port 2 via decoder 1C107. 
When a latch pulse goes positive while a 
data signal is fed onto the clock pin, the 
data is latched and sent to the VOICING 
circuit or LED. When the latched data is 
for voicing, it is applied after inverted 
and amplified by a buffer. 

There are three kinds of latched outputs, 
as the master output goes negative, Qs and 
Qs of IC112— IC114 are cleared, maintaining 
their pulse lengths almost the same as the 
master wave length. 

On the other hand, Qs of IC115 and IC116 
are held L until the next latch signal 
comes since these clear pins of ICII5 and 
IC116 are not connected to the master oscil- 
lator output. 

Note: since the time interval between pulses 
within the arrows marked by * is 70ps, they 
are considered to occur at the same time. 




Latch Signal 

ICIO7 , 11-14 11 1 1- 





1 


\ 1 


Data Signal 


1 

i 


1 t 


Port 1, P10-P17 




■ ^rni rr 

1 1 


Latched Signal Q 


1 


! i 



ICII2-ICII4 
Latched Signal Q 

ICII2-ICII3 



Latched Signal Q 
IC115-IC116 no clear 
input 

Master Oscillator 



ii 



I 

I 



- EADE and ACCENT = 

As described in section 4, the EADE circuits on OP-100 
are enabled when the EADE IN and/or EADE OUT swithches 
are turned on to make the rhythm sounds gradually loud- 
er (VCA) as a rhythm starts and to stop the rhythm (Tl) 
as sounds die away. 

These timings are determined by the RC constants in the 
EADE circuits. 

Accent pulses are also affected by the EADE circuits 
in amplitude ratio and are mixed with the sound control 
voltage in the summing amp. IC117 from which incorpo- 
rate control voltages are sent to the VCA on the VG-11 
to control rhythm voliune . 



- SOUND KILLER 

These circuits "kill" undesired sounds 
resulted from transient voltages on their 
way to output : 

1. When power is on, Q512 on the VG-11 is 
not supplied enough collector voltage to 
amplify a input signal until C558 charges 
to some extent. 

2. When power is off, C558 discharges 
through Q535 and Q532 on the VG-11, 
grounding pin 1 of VCA IC502. 

3. The circuit comosed of Q12 and QI3 on 
the GL-9 is identical and functions in 
the same manner as the circuits described 
above, but is used to protect the RAMs 
and to prevent disorderly running of 
8048 . 



MC14069BCP 

DIP (TOP VIEW) 



BA662 



Vdd 



R R R M in in 



^ L{>J 



□■"[iJ Lil LiJ LU LiJ LzJ 

Vss 



TOP VIEW 



OUTPUT 0C 
-INPUT® C 

+iNPufr®c 




8)+V 

0 OUTPUT 
-INPUT 
3® +INPUT 




5 -V 
9 i- V 



PIN CONFIGURATION 



AtC 


1 


24 


Z)'tc 


AeC 


2 


23 


□ a. 


AsC 


3 


22 


□ Asl’l 


A.i: 


4 


21 




AtC 


5 


20 


3cs/we 


AtC 


6 2708/2704 


19 


3 'to 


AlC 


7 


IS 


PROGRAM 


ILSBI AoC 


B 


17 


^07 IMSBl 


asBi OoC 


9 


16 


□ O6 


OtC 


10 


15 


□ os 


0? [I 


n 


14 


□ 04 




12 


13 


□ 



NOTEI: PIN 22 MUST BE CONNECTED 
TO Vss POflTHE27M. 



PIN NAMES 



, Ao A, 


i ADDRESS INPUTS 


1 0, Os 


: DATA OUTPUTS/INPUTS 


1 cS/WE ’ 


CHIP SELECT/WRITE ENABLE INPUT 



BLOCK DIAGRAM 



AM2708P 




PIN CONNECTION DURING READ OR PROGRAM 



PIN NUMBER 



j MODE 


DATA I/O 
9 11. 

13 17 


ADDRESS 
INPUTS 
1 8, 

22. 23 


"T 

i Vss 
: 12 


1 PROGRAM . 
1 18 


Vdd 

19 


1 

I CS/WE 
1 20 


! — 

: Vbs 
21 


Vcc 

24 


HEAD 


Dmji 


A(n 


GNO 


1 GNO 


H2 


1 Va 


' -5 




DESELECT 


HIGH IMPEDANCE 


DON'T CARE 


GND 


' GND 


t12 


j V|H 


: '5 


+5 


i PROGRAM 


0|N 


A|N 


GND 


PULSED 

26V 


+ 12 


! V|HW 

1 


: -5 


+5 



;iPD5101C-E 



PIN CONFIGURATION LOGIC SYMBOL 



A 3 IZ 


1 22 


Z ''cc 




A 7 CZ 


2 21 


□ a. _ 


A, 


A,IZ 


3 20 


!□ A'VV 


Ap 


AoLZ 


4 19 


Z CE1 


A 4 


MZ 


5 18 


Z 00 — 


A^ 


A.CI 

A 7 C: 


6 17 

7 16 


1 CE2 

Z DO, 


^6 

A? 

Dl, DC 


GND [;l; 


8 15 


Zoi. _ 


Dip DO 


0 ',C= 

DO, d 


9 14 

10 13 


Z DO, — 

Z 01, 


Dtj DO 

DI 4 DO 

OD 


Olj d 


11 12 


Zoo, 


R/w CE 2 cn 

‘"T — 'r""B 



TRUTH TABLE 



CE, 


CE, 


OD 


R/W 


Din 


Output 


Mode 


H 


X 


X 


X 


X 


High 2 


Not Selected 


X 


L 


X 


X 


X 


Hi^Z 


Not Selected 


X 


X 


H 


H 


X 


High Z 


Output Disabled 


L 


H 


H 


L 


X 


High Z 


Write 


L 


H 


L 


L 


X 


0|N 


Write 


L 


H 


L 


H 


X 


OouT 


Read 



BLOCK DIAGRAM 




A 5 Ag A, 

©0© 



O =• PIN NUMBERS 



7 














JUNE 20, 1979 



GL-9A(142-009A) 

(Etch mask 052-438A) 
Serial No. 780700-821050 
Use GL-9B for replacement 






Serial no. up to 780699 



Serial no. up to 780699 



G-L-9 Circuit Board is the same 
as G-L-9A except for portion 
shown left and following 
parts are attached on the 
foil side. 



oooo 



R202, R201, R105, 0105 



For the decoder (IC112, 115 > 115,116) two 
kinds of logic IC are available ; 

TTL (741S175, or equiv. ) and CMOS (74C175 
14175 , or equiv.). 

When CMOS type is used as a replacement 
for TTL, pin 1 of IC115 and ICII 6 must be 
connected to +5V supply through a lOk-ohm 
as shown in below right (R212, R215) . 

When TTL is used, the 10k ohms resistors 
become optional. 



TTf^fOL^ 



batte; 



ict04- 



ICll' 



000000 000000 







-<13Eg^ 



BOSSANOVA 









SAMBA 




A MAMBO 
B CHA CHA 




A BEGUINE 
B RHIMBA 




SUEB2 

001-240 


.r~ 

/ 


SLR--322 

001-231 


£_ 

C ? 7 i 


RHYTHM A/B 
























lOrUr 

toil 



«ii 



lC; 

:c?£j. 

iCfp! 

y.wfjj 



I Hli 



B W Itilpj^^ it I 

a •■Miiwfn 
Nl M fl H i tk W 



MJJ 



^ I' 1 7 7 j 



l.ifM- 

-fltflr 



ro MC/4^/3 & 



Kmmo3 /^PDSIDIc 



MCHH75, 



ZShlOtS 



StS6% 



A«*nt 



RS-17 (148-017) 

(Etch mask 052-446) 
view from foil side 



VARIATION 

auto/manual 



SLR-322 

( 001 - 231 ) 



SURA2 

( 001 - 239 ) 



/f. 

o3>| , 

o-o- • V 

00 ^ 

oo 

O 0 I ' 

oo " # 

oo '= " i 

O 0LZ.i* , ^ ■ ■”■„ : * 



7 . .-“^r li^***-- T / 

f '* ””"-; 

: :f r 



PK06RAM RHVTHH 



■ 



ROCK- 1 



ROCK- 2 



T o*Cl>- /2>lf 



ROCK - 3 



ROCK - 4- 



OISCO- 1 



DISCO. 2 



CANCEL 



SI6H- 



S105 



CR-78 



GL-9B (142-009B) 

(Etch mask 052-438B) 

Serial No. 821051 and higher 



JUNE 20, 1979 



ST/sp 































Jacks SG7622 #8 (009-012) 




JUNE 20, 1979 

VG-11A (143-011 A) (Etch mask 052-437A) 
Serial No. 780700 and higher 



0P-<2<> 



IC501 MC14069 
IC502 BA662 

IC505 UA78M05 
IC504 UA78M15 

IC505 JOA78L05 



2SC900-B 

2SC1815-GR 

2SC828-R(NZ) 

2SA1015-Y 

1S1588 



-f?OM (nL) OF 9 



OP-129 (149-129) 

Serial No. up to 780699 



Components on foil side 

VG-11 - R645, 0592 

VG-llA- D533 



EXT. OLOCK circuit is arranged 
OP-129 independently of OP-104 



write 
fir , 
V/«ir \ 
ST/Sp 



In the dotted lines 
shown are circuit g) 

configuration and ^ 

components of ^ ^ 

VG-11 (S/N up to 780699), remainnings 
are almost the same as those on VG-llA 
which can replace the YG-11. 



OP-103A (149-103A) 
(Etch mask 052-447 A) 
view from foil side 



Moot 



Connector 
cable assy 
no . 166 



0P-104A (149-104A) 
(Etch mask 052-464) 
Serial No. 780700 
and higher 





1 







f 

( 



I 



12 























JUNE 20, 1979 



( ADJUSTMENT & CHECKING 

f 

1. MASTER OSCILLATOR PREQUEECY (RHYTHM TEMPO) 

Connect an oscilloscope to Q1 collector or pin 76 on G-L-9. 
1-1. Set TEMPO knob to full clockwise position (10). 

Adjust VRIOI for T = 10ms. 

1-2. Turn the TEMPO control fully counterclockwise. 

Adjust VR102 for T = 10ms. 

" Bottom half must he perfectly square. 




good no good 



2. PALE TIME 

To he adjusted after step 1 is finished. 

With rhythm (may he SAMBA-B ) running, turn TEMPO fully 
clockwise . 

Set PADE OUT to SHORT. 

Depress START/STOP button. 

2-1. When sound becomes inaudible, count the number of 
LED flashes until the LED stays on steadily. 

Pactory set ranges 4 (1.5sec) to 66 (2.4sec). 

2-2. To adjust, turn VR103 on G-L-9. 

3. RHYTHM VOICE 

Pigures in the table at the right show factory standard 
and may be slightly deviated for personal taste or to 
meet frequency response of an amplifier being used. 



CR-78 





15 





PARTS LIST 



081-113 


Cabinet no. 117 


111-020 


Base no. 20 (foot) 


072-235 


Panel no. 235 


076-356 


Name plate no. 356 
rear OUTPUT -COMB I. 


076-367 


Name plate no. 367 
rear EXT. CLOCK-WRITE 


061-218 


Chassis no. 218 front 


061-219 


Chassis no . 219 main ' 


061-220 


Chassis no. 220 rear 


061-234 


Chassis no . 234 


061-235 


Chassis no. 235 sub 


061-236 


Chassis no. 236 sub 




KNOBS . BUTTONS 


016-043 


Knob no. 43 TEMPO 


016-04^ 


no. 44 FILL. MEASURE. 
INSTRUMENT. ACCENT 


016-080 


No. 80 CLEAR. CANCEL 


016-081 


No. 81 power switch 


016-048 


No . 48 slider 


016-067 


No. 67 MEMORY- ALL 


016-008 


Button No. 8 gray 


016-085 


No. 85 white 


016-086 


No. 86 red 


016-087 


No. 87 green 


016-088 


No. 88 yellow 


016-089 


No. 89 blue 



COILS. TRAJISFORMERS 



ICs 

179-022 }iPL8048C-015 computer 

There are some versions of 8048. 
Each has an exclusive resident 
program. 

Specify 8048C-015 for the CR-78 
replacement . 

179-023 M2708P-023 ROM 

020-181 ^PD5101C-E RAM 

020-141 *74LS175N (TTL) 

020-196 *14175B or 74C175 (MOS) 

*refer to GL-9A parts layout 

020-064 )iPC4558 

020-180 74LS174R 

020-138 74LS138E 

020-124 74LS04R 

020-120 741SOON 

020-084 MC14069BCP 

020-041 MC14013BCP 

020-169 MC14001BCP 

020-160 BA-662B VGA 

020-073 }iA78M15 regulator +15V 

020-197 pA78M05 or ^7805 +5V 

020-198 yiA78L05 -5V 



DIODES 

018-059 1S1588 

018- 082 ¥-02 bridge 1.5A 

019- 013 SLP-131B LED red 



022-030 


Coil no. '30 


45niH 




022-031 


no. 31 


IR 


001-215 


022-033 


no . 35 


3R 700mH 


001-216 


022-124N 


PT no.l24H 


lOOV 


001-217 


022-124C 


PT no. 124c 


117V 


001-273 


022-124D 


PT no.l24D 
TRANSISTORS 


220/24OV 


001-206 

001-243 

001-242 

001-239 


017-105 


2SA1015-1 




001-240 


017-106 


2SC1815-GR 




001-231 


017-021 


2SC900-F 




001-245 


017-046 


2SC828-R (NZ) 


for noise 


001-246 

001-241 

001-244 



SWITCHES 

Power SDG-5P lOOV 
SDG-5P 117V 
SDG-5P 220/240V 
ECA10037 keyboard 
HSW-0372-01-030 slide 8,16, COMBI 
SRM1025 rotary MEASURE 
SRMIOIC rotary FILL IN 
SUFA2 push gang ROCK-DISCO 2 
SUFB2 push gang WALTZ- 
SLR322 lever Rhythm A/B. AUTO/MANU. 
SLR323 lever FADE IN/OUT 
SLR823 lever MEMO/PLAY/ALL 
SUF53 Ipush gang CLEAR. CANCEL VOICE 
SRA202B rotary INSTRUMENT 



CR-78 



PCBs 

j 143-OllA VC-llA(etch mask 052-437A) 

I42-OO9B CL-9B (052-438B) 

148-014 RS-14 (WALTZ-) (052-445) 

148-015A RS-15A (VAR I. MEASURE) 
-(052-444A) 

148- 017 RS-17 (PROGRAM. ROCK-) 

i (052-446) 

i 149-lOOA OP-IOOA (052-449A) 

149- IO3A OP-IO3A (052-447A) 

149-IO4A 0P-104A (052-464) 

(use IO4A as a replacement 
for OP-129 ) 

I For the replacement, use PCBs 

listed above, interchangeable 
improved versions. 

POTENTIOMETERS 

026-024 EVHCOAP25B15 100KB TEMPO 
026-021 EVHC0AP24B14 10KB ACCENT 
I 029-410 LYE6B001-10KB VOL. ADD VOICE 

029-411 LYE6BOOI-5OKB BALANCE 

Trimmers 

028-001 EVTR4A00 (SRI9) 500 

' 028-003 EVTR4A00 (SRI9) 5K 

028-004 EVTR4A00 (SR19) lOK 

028-005 EVTR4A00 (SRI9) 20K 

028-006 EVTR4A00 (SRI9) 50K 

028-007 EVTR4A00 (SRl9)l00K 

CAPACITORS 

032-095 0.47mfd 35V K tant. 

035-109 ECQM6103KZ 600V polyester 

FUSES. FUSE CLIP 

008-024 SGA 0.5A prim, sec +5V 100/II7V 

008-026 SGA lA sec +15V IOO/II7V 

008-022 SGA 0.125A sec -5V 100.117V 

008-053 CEE T50mA sec -5V 220/240V 

008-060 CEE T250mA sec +I5V 220/240V 

008-062 CEE T400mA sec +5V 220/240V 

008—060 CEE T250mA prim/sec +I5V 

220/24OV 

012-003 Clip TF-758 



JUNE 20, 1979 

MISCELLANEOUS 

009-012 Jack SG7622 
IC Sockets 

012-040 ICC3O-O4O-35OG 40-pin 

012-041 ICC3O-O24-35OG 24-pin 

012-042 ICC3O-O22-35OG 22-pin 

O47-OO3 Line cord strain relief BU4801 

047-023 Cord clamp 1702B 

120-001 long nut (spacer/stand off) 
no.l 3x1 0mm 



( 

PARTS ORDERING INFORMATION 

When ordering parts, be sure to 
include the following 
information: 

1. Model and Serial Number ( 

2 . Part Number 

3. Part Name 

If the necessity for a non-listed 
part arises, please write 
describing the parts location and 
function as well as model and 
serial number of the unit. / 



< 

( 



16 




REQHARaEABLE BATTERY CHMQE 



CR-78 



MANUAL CHANGE INFORMATION 



4E-100AA (5.6V) to 


S-SB3 (3.6V) 








Serial no . 


Serial no . 








up to 862899 


872900 and higher 




ADJUSTMENT page 15 




(no name is given on the 


(name is definitely printed on 


CORRECTION 


1-2. T = 10ms 


- 200ms 


face of the battery) 


the face) 




2-1. 4 to 55 


- 4 to 



with 4R~1Q0AA 



with E-SB' 




D109 is removed at the factory 
to increase charging current . 
However, there are some products 
having D109 on the market. 



N-SB3 being lower in voltage 
can be sufficiently charged 
regardless of D109 existance 
which protects IC102 and IC- 
103 against high voltage 
during an absence of N-SB3. 



juj-iirrea part designation 
not denoted or misprinted 
on the service notes. 



REMOVE D109 on the first ocassion 



(after D109 removed) 



2. Eeve 



turn on the power t 



switch with 4E-100AA 
BISCOEEEGTED. 

HIGtHER voltage will 
ruin IC102 and IC103 



2 . Contrary to B109, B221 
and R237 are harmful to 
E-SB3, remove them be- 
^ fore installing E-SB3. 



iOuT 



ret 03 . 



IC504 



Battery 

4N-100AA 



iBattery^vVw 
4E100AA . 



IC503