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Sineties 


MOS SILICON GATE 
2500 SERIES 

METAL GATE 2000 
AND 2400 SERIES 


SECTION 
1 
2 
3 


TABLE OF CONTENTS 


TITLE 


Silicon Gate Technology 


Designing with Silicon Gate; MOS/TTL Interface 
2500 Series MOS Silicon Gate Specifications 


2501 
2502/2503/2504 
2505/2512 
2506/2507/2517 


. 2508 


2509/2510/2511 
2513/2514 


2516 

2518/2519 
2521/2522 
2524/2525 


Fully Decoded, 256X1 Static Random Access Memory 
1024-Bit Capacity Multiplexed Dynamic Shift Registers 
512 and 1024 Bit Recirculating Dynamic Shift Registers 
Dual 100-Bit Dynamic Shift Registers 

Fully Decoded, 1024X1 Dynamic Random Access Memory 
Tri-State Output, Dual 50-100-200 Bit Static Shift Registers 
High-Speed 64X7X5 Character Generator, 512X5 Static 
Read-Only Memory 

High-Speed 64X6X8 Static Character Generator 

Hex 32-Hex 40-Bit Static Shift Registers 

Dual 128-132 Bit Static Shift Registers 

512 and 1024 Bit Recirculating Dynamic Shift Registers 


2000/2400 Metal Gate MOS Specifications 


2001 
2002 
2003 
2004 
2005 
2010 
2400 Series 


Dual 16-Bit Static Shift Register 

Dual 25-Bit Static Shift Register 

Dual 32-Bit Static Shift Register 

Dual 50-Bit Static Shift Register 

Dual 100-Bit Static Shift Register 

Dual 100-Bit Static Shift Register DC to 3 MHz 

Fully Decoded 1024 and 2048-Bit Static Read-Only Memori 


MOS SURE 883 Program 


MOS/ROM Programming Software Information 

2400 Series Static Read-Only Memories 

2513 Static Character Generator and 2514 Static Read-Only Memory 
2516 Static Character Generator 


Linear and Digital Product Information 
Linear Product Line (Bipolar) 
Digital Product Line (Bipolar) 


Signetics Sales Offices 


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25% to 50% recycled paper 


Copyright 1971 


SIGNETICS CORPORATION 


IMPORTANT NOTICE 


This handbook contains information on new products recently announced. Although 
believed to be accurate, this preliminary data is subject to change without notice. 


Signetics Corp. cannot assume responsibility for any circuits shown or represent that 
they are free from patent infringement. 


SECTION 


SILICON GATE 
TECHNOLOGY 


SILICON GATE TECHNOLOGY 


WHY SILICON GATE TECHNOLOGY? 


INTRODUCTION 


There are many MOS processes available today, ranging from 
high threshold, 1-1-1 orientation silicon, P-MOSTs to the 
less common dielectrically isolated, complementary MOS, ion 
implanted, silicon nitride, and silicon gate monolithic circuit. 
The problems which arise for MOS manufacturers and users 
can be summarized many times as one question: Which 
technology? 


In this section, a brief comparison of the available MOS 
technologies is made. This is followed by a description of the 


P Channel 
1-1-1 Crystal, Metal 
Gate 
1-0-0 Crystal, Metal 
Gate 
Nitride 
Silicon Gate, (111) 
Crystal 
lon Impl. (Metal Gate) 
Low Threshold 
Approach 
Self Aligned Gate 
N Channel 


Complementary 


SILICON GATE PROCESS 
FABRICATION SEQUENCE 


Basic process flow is illustrated in Figure 2. Using this chart 
as a guide, the process can be described as follows. 


STEPA 

The wafers are thoroughly inspected, cleaned, oxidized 
and masked to delineate the area where the drain, 
source and channel will eventually be formed. The gate 
dielectric is then grown. Both the initial oxide and the 
gate dielectric can be grown in any manner, to any de- 
sired thickness, without affecting junction character- 
istics. The initial oxide thickness is normally chosen to 


PROCESS RANKING 


silicon gate process flow sequence and a comparison of its 
advantages and disadvantages. 


MOS TECHNOLOGIES 


The numbers of MOS technologies available are numerous 
and each has its cwn advantages and disadvantages. Figure 1 
shows a process ranking for some of the major technologies 
now available. The processes are weighted on five different 
factors: speed, chip area, power dissipation, bipolar compat- 
ibility and cost. The Silicon Gate Process which ranks 
highest forms the basis for the 2500 Series. 


COMPATIBILITY | COST 


FIGURE 1. 


minimize poly-to-substrate capacitance, maximize 
poly-to-substrate parasitic field turn-on voltage and 
thin enough to minimize the step over which metal 
lines may eventually have to travel. 


STEP B 

The poly-crystalline silicon is deposited, a masking 
oxide is formed and the sandwich is then masked and 
etched to delineate the gate structure and the drain- 
source beds. The quality, cleanliness and thickness 
uniformity of the deposited poly is important. Also 
delineating the poly-crystalline lines is a critical step, 
since some of these lines determine the channel length 
of the completed MOS transistors. 


SILICON GATE TECHNOLOGY 


STEP C STEP E 

Boron is deposited to dope the poly-crystalline silicon Contacts are opened and metallization is deposited, 
and to form the Pt beds for source and drain. The delineated and sintered. The metallization is fairly 
doping of the poly lines and P* beds is straightforward standard. As with the metal gate processes which 
and virtually any clean source of boron can be used. may have high oxide steps, care must be taken with 
Because the pre-deposited poly-silicon gate is used to the silicon gate process to minimize the height of the 
mask the boron diffusion, the gate,source and drain are steps over which metal must travel in order to mi 
automatically self aligned. imize metal microcracking problem 

STEP D A multi-layered protective glass is deposited over the 
A clean layer of oxide is deposited over the entire finished structure and holes are opened to the bonding 
wafer to passivate the P+ beds and provide isolation pads to give the final cross-section shown in Figure 3. 
between poly-silicon and metal lines. Deposition of Glass passivation is mandatory, even with the silicon 
the passivating oxide requires strict control over the gate process, to protect the aluminum metalization 
cleanliness of the deposition system to minimize oxide from mechanical abrasion and particulate contamina- 
defects and contamination. tion. 


SILICON GATE PROCESS FLOW 


| om =m eae = 
ee him 


Y-CRYSTALLINE 
SILICON DEPOSITION 


oa 
HELL 


STEP C: P+ BED DOPING 


STEP E: ALUMINUM METALIZATION PATTERN 


i 


| 


ai | 


FIGURE 2. 


FINAL DEVICE CROSS — SECTION 


4a 
Saint se 


FIGURE 3. 


SILICON GATE TECHNOLOGY 


ADVANTAGES AND DISADVANTAGES 
OF SILICON GATE 


The silicon gate process has a number of advantages which 
make it attractive for the production of complex, high density 
circuits. Before expanding on these advantages, we will first 
explore two of the more prominent disadvantages of the 
process: 


Ratio Versus Ratioless 

Because of the self-aligned gate feature, the parasitic 
drain-to-source capacitance is small. In designing dy- 
namic shift registers, it is advantageous to design ‘‘ratio- 
less’ devices where parasitic capacitance is used to 
momentarily store charge. Using silicon gate, a ratio- 
less type design is not feasible, so the more area con- 
suming ratio type must be used. However, the silicon 
gate ratio design is competitive in size with the metal 
gate ratioless version, since area is saved by the smaller 
gate area (no need for alignment tolerance allowance), 
plus the use of the poly-silicon as a interconnecting 
layer. 


Additional Depositions 

Silicon gate processing requires more deposition steps 
than is required by standard metal gate processes. 
However, these processes can be easily controlled using 
modern, automated deposition equipment and built- 
in process control monitors. 


The potential disadvantages of the silicon gate process are 
outweighted by the following advantages. 
Low Threshold Voltage 
Doped poly-silicon, used in place of the usual alu- 
minum gate electrode, yields threshold voltages typ- 
ically around -2.0 volts. This low threshold voltage is 
obtained using 1-1-1 orientation silicon, so the corre- 
sponding parasitic field turn-on voltage is still very 
high. 
High Gain 
The gain of the silicon gate device is high since 1-1-1 
orientation is used as the starting material. Gain is typ- 
ically higher than low threshold voltage devices fabri- 
cated on 1-0-0 silicon because of higher carrier mobil- 
ity. 
Low Power 
The silicon gate device dissipates less power: 


(1) Because of its low threshold it operates with 
lower power supply voltages. 

(2) Its self-aligned gate essentially eliminates over- 
lap of the gate over the drain, so the capacitive 
load on the clock drive is less. 


High Speed 

High speeds are obtained because of low threshold 
voltages, high gain and low gate capacitance. 
Minimum Area 

The poly-crystalline silicon layer provides yet another 
“half-layer’’ of interconnection. We call it a “‘half- 


layer’’ since the crossing of poly-silicon over Pt beds 
is not allowed. Shallow junctions allow close Pt bed 
spacings and the self-aligned gate feature means no 
mask alignment tolerances are needed to register the 
gate to the Pt beds. In addition, direct contact of 
poly-to-substrate allows further area reduction. 


To illustrate the size advantages, consider Figure 4. 
The 2005 and 2510 are both dual 100-bit static shift 
registers. However, the silicon gate 2510 is 15 percent 
smaller than its metal gate equivalent. Not only is it 
smaller but it has additional functions such as recir- 
culate logic, tri-state outputs, TTL compatibility and 
an on-chip clock generator. The silicon gate 2511 
Dual 200-Bit Static Shift Register, offers twice the 
number of bits as the metal gate 2005 plus four ad- 
ditional functions in only 36 percent more area. 


SIZE COMPARISON OF DICE 


PART 


Dual 100 Bit S.S.R. 12 

; | 

2005 (Metal Gate) 8,190mi 
Dual 100 Bit S.S.R. 


(Silicon Gate) 


Dual 200 Bit S.S.R. 
(Silicon Gate) 


6,970mil2 


FIGURE 4. 


High Yield 

The process of forming the gate oxide at the first 
stage of wafer fabrication and coating with a protec- 
tive layer of silicon inherently gives higher yields. In 
addition, the ability to compact a given circuit function 
into a smaller area gives a lower probability that a 
processing defect will occur on a die. This is especially 
true since the decrease in area does not come at the 
expense of masking tolerances. The higher yields result 
in lower costs. 


Process Flexibility 

The silicon process gate is compatible with other MOS 
technologies. lon implantation can be used to adjust 
thresholds and/or minimize gate-to-drain capacitance. 
Gate dielectrics can easily be changed without affecting 
junction characteristics, and C-MOST and N-MOST 
can easily be adapted to silicon gate processing. 

Low Cost Packaging 

Because the gate dielectric is protected by poly-silicon 
and the overlying layers of oxides, it is possible to 
reliably package silicon gate devices in silicone pack- 
ages. Cross-sections of metal gate and silicon gate 
devices are shown in Figure 5, The metal gate devices 
are protected by two layers: aluminum metallization 
and glass passivation. On the other hand, the silicon 
gate device is protected by four layers: (1) thick poly- 


SILICON GATE TECHNOLOGY 


LOW COST PACKAGING (Cont'd) The silicon gate process is a technology whichgives all of the 
. advantages needed to fabricate the next generation of cir- 
crystalline silicon (impervious to most harmful con- cuits: high packing density, high speed, low power and low 
taminants). (2) thick clean oxide, (3) a passivated di- cost. Because of these characteristics, silicon gate MOS tech- 
electric which also serves as a sodium barrier and, (4) nology has become an industry standard for state-of-the-art 

a multi-layered protective glass. MOS LSI designs. 


METAL GATE PROCESS 


ata ponent GLASS PASSIVATION 
tl ea 
nn. Le 


N-TYPE SILICON 
SUBSTRATE 


Aint 


————— 
——— 
SSS 
—>_>__Z= 


SIGNETICS SILICON GATE PROCESS 


Then 


SiNOtics 


SECTION 
DESIGNING WITH SILICON GATE 


MOS/TTL INTERFACE 


10 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


DESIGNING WITH SILICON GATE 


INTRODUCTION 


Large scale, bipolar compatible MOS integrated circuits are 
now available to the systems designer because of the unique 
benefits of Signetics’ Silicon Gate Technology. Using com- 
plex MOS functions to form major systems blocks, joined 
and controlled by today’s wide variety of low cost TTL and 
DTL MSI and SSI functions, economical state-of-the-art 
systems are being produced with ease and efficiency. 


THE SILICON GATE MOS 
BIPOLAR COMBINATION 


Silicon Gate MOS - Bipolar designs offer the best of both 
worlds. MOS designs are most efficient when providing large, 
medium-speed arrays of identical cells, such as required for 
long serial shift registers, large Random Access Memories 
(RAMs) and large Read-Only-Memories (ROMs). 


Bipolar designs are most efficient when providing high-speed 
connective logic functions (gates), small parallel registers, 
and small specialized logic combinations such as adders, com- 
parators, counters, decoders, and power drivers. 


MOS-BIPOLAR COMPATIBILITY 


Today’s systems are designed to utilize the benefits of both 
MOS and bipolar technology for maximum performance at 
minimum cost. Signetics recognizes the benefits of direct 
MOS-Bipolar interfacing and has created the Silicon Gate 
2500 Series MOS with the express purpose of providing 
MOS density and bipolar compatibility. 


INPUT INTERFACE 


All 2500 series devices are manufactured with the P-channel 
enhancement mode silicon gate process. A typical data input 
structure is shown in Figure 1. 


OUTPUT 


FIGURE 1 


The input transistor exhibits the transfer curve shown in 
Figure 2. The device is fully OFF at -1.8 volts or less (Vgs) 
and fully ON at -3.5 volts or more. To simplify the inter- 
facing of TTL and 2500 Series devices, the source voltage 
for the input transistor is specified at +5.0 volts. In practice, 
this point is tied to the +5.0 volt TTL Vcc supply. The re- 
quired MOS input levels are then specified as positive levels 
referenced to the TTL ground. 


11 


Series 2500 Input Thresholds 
“0” Input Voltage = Viz =+1.05 maximum@ 


Vcc = 5V 
“1"" Input Voltage = Vip = +3.2V minimum @ 
Vec = 5V 


The input levels are specified assuming Vcc is 
exactly +5.0V. The allowable Vcc tolerance is 
+5%, however any variation in actual Vcc will 
be tracked directly by the input threshold point. 


Example (a): +5% Vcc 
@ Vcc= +5.25V 
ViL = 1.3V max. 
Vin = +3.45V minimum 


Example (b): -5% Vcc 
@Vcc = +4.75V 
Vit = 0.8V max. 
Vin = +2.95V minimum 


2 
mi 
° 
2 
- 
3 
> 


Vigs (VOLTS) 
FIGURE 2 
In actual practice, tying the TTL Vac to the MOS Vcc 


will ensure maximum noise margin since the TTL output 
levels and MOS input thresholds will track. 


54/7400 TTL 


Figure 3(a) and (b) show a typical 7400 Series gate circuit 
and transfer characteristic. 


FIGURE 3(a) 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


54/7400 TTL 


Vec =5V + 5% 


uw 
@ 
ro 
mr) 
co) 
> 
2 
3 


* EXTERNAL 10K 
PULL-UP RESISTOR 


FIGURE 4 


INPUT VOLTAGE 


8000 TTL 


Figure 5 illustrates a typical 8800 series output structure. 


FIGURE 3(b) 


The output structure shown in Figure3(a) is normally specified 
as follows: 


@ Voc = t5V +5% 
VoL = +0.4V maximum @ 16 mA sink 
VOH = +2.4V minimum @ 400 yA source 


MOS devices require only negligible D.C. input current (ap- 
proximately 1A), so the current available from the TTL 
output is of no interest for steady state conditions. Vo, _ is 
perfectly compatible with the MOS offering at least 400mV 
of noise margin in the O state. Voy however, is not suffi- 
cient to guarantee a 1 level to the MOS input since the TTL 
VOM allows a Vec - Voy separation of as much as 2.85V 


Voc = 5.25V, Voy = +2.4V; 5.25V - 2.4V = 2.85V). chasis 
Assuming a common Vcc, this results in a virtual Voy The 8800 series circuit typically offers an unloaded output 
of 2.15V, far too low for MOS. In practice, the TTL Voy voltage separated from Vcc by one Vpgo. Therefore the out- 
will track Vcc, rather than the opposite case just noted. put level driving MOS will always be approximately 0.75V — 
Also Voy will be higher than +2.4 at 1uA IE. However, higher than the preceeding example for 7400 series circuits 
the TTL circuit is tested and guaranteed as in the example. — resulting in at least 550mV 1 level noise margin under any 
conditions. Noise margin at 0 level is 400 mV, the same as 
The 7400 TTL output structure will typically provide a in the case of 7400 TTL. 
VOH approximately 1.5V (two Vie drops) below Vcc. 
When the MOS and TTL Vcc are tied, a 300mV noise Signetics guarantees 8000 Series TTL (See figure 6) VOH at 
margin (1.8V - 1.5V = 0.3V) is obtained. If Vcc is not tied 3.6V @ 10uA. Under worst case conditions, this results in 
common, the worst case typical noise margin is a negative a minimum guaranteed 0 level noise margin of 400mV for 
200mV. In other words, a satisfactory 1 input level cannot tied Vcc. If the MOS and TTL Vcc are not tied (may vary 
be assured, even under typical conditions. independently), worst case guaranteed noise margin is 


-150mV. This configuration requires a pull-up resistor. 
TO ASSURE A SATISFACTORY 1 OUTPUT LEVEL 


FROM SERIES 7400 IN DRIVING SERIES 2500 MOS, AN WHEN Vc¢c’S ARE TIED COMMON, SERIES 8000 TTL 
EXTERNAL PULL-UP RESISTOR SHOULD BE CON- IN FIGURE 6 WILL INTERFACE DIRECTLY WITH 
NECTED FROM THE OUTPUT TO Vcc AS SHOWN IN SERIES 2500 MOS, WITHOUT THE NEED FOR AN Ex- 
FIGURE 4. . TERNAL PULL-UP RESISTOR. 


12 


DESIGNING WITH SILICON GATE # MOS/TTL INTERFACE 


GATES FLIP-FLOPS 

8808 Single 8-Input NAND Gate 

8815 Dual 4-Input NOR Gate 

8816 Dual 4-Input NAND Gate Dual Master-Slave J-K Binary 
8840 Dual Expandable AND-OR-INVERT Gate Dual Master-Slave J-K Binary 


8848 Expandable AND-OR-INVERT Gate Dual Master-Slave J-K Binary 
8870 ‘Triple 3-Input NAND Gate DC Clocked J-K Binary 
8875 Triple 3-input NOR Gate Dual J-K Binary 
8880 Quad 2-Input NAND Gate Dual J-K Binary 
8885 Quad 2-Input NOR Gate High Speed J-K Binary 
“See Note Below 
FIGURE 6 


*For devices not listed,addan external pull-up resistor as in the 7400 example(Fig. 4). 


DTL/UTILOGIC ® those noted for Series 800 circuits. 

ree ; ; ; WHEN Vcc’S ARE COMMON, SERIES 2500 MOS MAY 
Logic forms utilizing an internal passive pull-up iesistat BE DIRECTLY DRIVEN BY SERIES 600 DTL AND 
(such .as DTL) will interface directly with 2500 Series MOS. SERIES 300 UTILOGIC CIRCUITS WITHOUT THE NEED 
Utilogic is guaranteed to provide output levels equivalent to FOR AN EXTERNAL PULL-UP RESISTOR. 


2500 SERIES MOS-TTL INPUT CONSIDERATIONS (TTL Level data and clock inputs) 


WORST CASE WORST CASE 
GUAR. GUAR. 
1 LEVEL O LEVEL 
NOISE MARGIN NOISE MARGIN 


EXTERNAL 
DRIVING DEVICE PULL-UP 


RESISTOR (6) 


Common Vcc 
8000(1) Series TTL not req. 
8000(2) Series TTL 10K 
7400 Series TTL 10K 
600 Series DTL (3) not req. 
600 Series DTL (4) not req. 
300 Series Utilogic (3) not req 
300 Series Utilogic (4) not req. 


Independent Vcc 


All TTL 10K 400 
600 Series DTL (3) not req, 150 (5) 
600 Series DTL (4) not req. 150 (5) 
300 Series Utilogic 10K (7) 150 (5) 
NOTES: FIGURE 7 
(1) From List in Figure 6 


(2) Not listed in Figure 6 

(3) Passive Pull-up (resistor), 10% power supply 

(4) — Active Pull-up, +10% power supply 

(5) Use +5% DTL or Utilogic power supply to maintain 400 mV noise margin 


(6) From driving output to Voc 
(7) Certain Series 300 devices utilize a passive pull-up and require no external pull-up. 


13 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


OUTPUT INTERFACE 


TTL/DTL INPUT STRUCTURES 


Standard TTL circuits employ the input structure shown in 
Figure 8. 


TYPICAL TTL INPUT STRUCTURE 


CLAMP OR 
SUBSTRATE 
DIODE 


= GND 


FIGURE 8 


DTL circuits employ the structure shown in Figure 9. 


TYPICAL DTL INPUT STRUCTURE 


FIGURE 9 


2500 SERIES OUTPUT STRUCTURES 


Four basic types of output structures are used in the 2500 
series: 
1. Bare drain 


2. Internal resistor pull-down 
3. Push-pull 
4. Three-state 


See Figure 10. 
TYPICAL 2500 SERIES OUTPUT CIRCUITS 


+Vcc +Vcc +Voc 


of 


Vpp 


(A) BARE DRAIN (B) RESISTOR PULL-DOWN (C) PUSH-PULL 


FIGURE 10 


14 


BARE DRAIN: 


The bare drain output is the simplest structure and requires 
an external pull-down resistor. Bare drain is used where 
several outputs are to be tied together in a WIRED-OR 
configuration as shown in Figure 11. 


WIRED-OR CONFIGURATION OF 
TWO BARE DRAIN DEVICES 


OTL/TTL 


O $V (Vpp) 


FIGURE 11 


The external resistor is chosen to sink the 1.6mA required 
by a TTL gate. In Figure 11, a 3.3K resistor is tied to the 
Vpp supply. The output voltage will be +0.4V or less de- 
pending on the actual Io, of the TTL input. 


When the bare drain device is ON, it represents approx- 
imately 500 ohms. For the circuit of Figure 9, Voy is ap- 
proximately +3.7V — more than sufficient to drive a TTL or 
DTL gate. Bare drain 2500 devices are listed in Figure 12. 


BARE DRAIN SERIES 2500 DEVICES 


FIGURE 12 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


RESISTOR PULL-DOWN 


The second type of output has a pull-down resistor on the 
chip. The 2507 and 2517 are examples of this. The 2517 
has a 20K ohm internal resistor for interfacing with MOS. 


Resistor pull-down series 2500 devices are listed in Figure 13. 
The 2507 hasa7.5Kohm resistor, and if used in the WIRED- 
OR configuration with another 2507 output, will drive TTL 
directly as shown in Figure 14. 


RESISTOR PULL-DOWN SERIES 2500 DEVICES 


2507 7.5K 


2517 = 20K 


FIGURE 13 


PARALLEL CONFIGURATION 
FOR 2507's 


OTL/TTL 


FIGURE 14 


PUSH-PULL 


The third type of output structure used in the 2500 Series 
is the push-pull circuit shown in Figure 10c. In the push-pull 
configuration, the gates of the two output devices are driven 
from complementary signals such that only one device is ON 
at atime. When the upper device is ON, the output is tied to 
Vcc through approximately 500 ohms. When the lower 
device in ON, the output is tied to Vpp through 500 ohms. 


6 


The advantage of this circuit is that no additional power is 
dissipated in either state. Both states have low impedance 
to the power supplies. Push-Pull output series 2500 devices 
are listed in Figure 15. 


PUSH-PULL OUTPUT SERIES 2500 DEVICES 


2521 
2522 


FIGURE 15 


THREE-STATE 


A disadvantage of the push-pull circuit is that paralleling of 
the outputs is not possible because two low impedance 
devices would be ON simultaneously directly across the 
power supplies. To avoid this condition, a three-state out- 
put is used. The third state is an open output configuration 
where both devices are OFF and is accomplished by using 
an OUTPUT ENABLE line tied to the gates of both output 
devices as shown in Figure 16. Three-state series 2500 devices 
are listed in Figure 17. | 


DTL/TTL 


OUTPUT ENABLE 


FIGURE 16 


THREE-STATE SERIES 2500 DEVICES 


2510 2513 


2511 2514 


FIGURE 17 


Figure 18 summarizes the output configurations used on the 
2500 Series circuits. 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


OUTPUT CONSIDERATIONS FOR 2500 LINE 


PRODUCT 


NUMBER 


2501 
2502 
2503 
2504 


2505/2524 


2506 
2507 
2508 
2509 
2510 
2511 


2512/2525 


2513 
2514 
2516 
2517 


DESCRIPTION 


256 x 1 Static RAM 

256 x 4 Dynamic Shift Register 
512 x 2 Dynamic Shift Register 
1024 x 1 Dynamic Shift Register 
512 x 1 Dynamic Shift Register 
100 x 2 Dynamic Shift Register 
100 x 2 Dynamic Shift Register 
1024 x 1 Dynamic RAM 

50 x 2 Static Shift Register 

100 x 2 Static Shift Register 

200 x 2 Static Shift Register 
1024 x 1 Dynamic Shift Register 
64 x 7 x 5 Character Generator 
512 x 5 ROM 

64 x 6 x 8 Character Generator 
100 x 2 Dynamic Shift Register 


OUTPUT 
STRUCTURE. 


3-State 

Bare Drain 
Bare Drain 
Bare Drain 
Bare Drain 
Bare Drain 
7.5K Resistor 
Bare Drain 
3-State 
3-State 
3-State 

Bare Drain 
3-State 
3-State 
3-State 

20K Resistor 


TO DRIVE 
ONE TTL/DTL 
USE* 


Direct 
3.0K 
3.0K 
3.0K 
3.0K 
3.0K 
6.8K 
6.8K 
Direct 
Direct 
Direct 
3.0K 
Direct 
Direct 
Direct 
3.3K 


2518 32 x 6 Static Shift Register 
2519 40 x 6 Static Shift Register 


2521. 128 x 2 Static Shift Register 
2522 132 x 2 Static Shift Register 


Bare Drain 6.8K 
Bare Drain 6.8K 
Push~Pull Direct 
Push-Pull Direct 


“NOTE: Values are given for the maximum value of pull-down resistor ,output to Vopb- 


FIGURE 18 


“OR” TYING OUTPUTS 


The characteristics of the four types of output structures 
differ when tied together. A basic feature of MOS is that the 
design limitation on output ““OR"’ing is related to the output 
voltage levels required and the RC time constant of the 
resulting network. 


BARE DRAIN 


The number of bare drain devices which can be tied together 
is limited by the output time constant and the Voy level 
required. 


Switching time for the pull-down condition is determined 
by the load resistor Rpp and load capacitance C; . The MOS 
pull-up device is turned off and does not contribute to the 
negative going time constant. See Figure 19. 


Cy_ is comprised of wiring capacitance (Cy) and output 
capacitance (COyT) from each of the paralleled outputs. 


As the number of paralleled devices increases, the value of 
Rpp must be decreased to maintain speed. 


When driving loads having significant input capacitance, Cy 
should be increased accordingly. 


16 


-"- 
| 


° 
Cc 
4 


cr 7 

| | 

I I 

wk aki 
Te Te, 
| | 
+ + 


FIGURE 19 


As Rpp is decreased, Voy decreases since the impedance of 
Q1 when ON (approx. 500 ohms) will ratio with Rpp to pro- 
duce Voy: If Rpp is reduced too far, the output voltage will 
be insufficient to turn off the TTL gate being driven. 


Figure 20 gives the recommended value of Rpp as a_func- 
tion of fan-out for 2500 series bare drain devices. 


DESIGNING WITH SILICON GATE # MOS/TTL INTERFACE 


FIGURE 20 


* For te= 50ns 


Figure 20 assumes 10pF of wiring capacitance and 5pF per 
output. It should be noted that when the MOS device is OFF, 
the TTL input current of 1.6mA is sunk to -5V. When set up 
for a fanout of 5, the 1.6mA from the TTL gate will bring 
the output to only -2.7V. In actuality the input clamp or 
substrate diode of the TTL gate will turn on and clamp the 
output to -1.0V. The diode will supply the additional current 
(approximately 1.9mA). 


INTERNAL PULL-DOWN 


When 2500 Series devices with internal pull-down resistors 
are paralleled, the equivalent resistance Rpp is the parallel 
combination of all the internal resistors. A chart of the 
equivalent resistance, output time constant and Voy for the 
2507 with a 7.5K internal pull-down resistor is shown in 
Figure 21. 


FIGURE 21 


PUSH-PULL OUTPUTS 


Push-Pull outputs allow low rise and fall times but cannot 
be paralleled because it would then be possible to have both 
a push and a pull device on at the same time resulting ina 
low impedance between the power supplies (and indeter- 
minate output level). 


THREE STATE OUTPUTS 


The three state output is designed to take advantage of push 
pull drive capability plus the ability to OR the outputs. 


The third (or open) state is used when the chip is unselected. 
The selected output is free to drive the load without being 
affected by the other outputs tied to the bus. 


Output rise and fall times for the WIRED OR configuration 
of three-state devices is a function of the ON resistance of 
the individual pull-up and pull-down devices together with 
the load capacitance. 


17 


A CLOCK DRIVER FOR 2500 SERIES MOS 


In order to obtain optimum performance from MOS de- 
vices, they must be provided with clock signals of the proper 
amplitude, shape and timing. This section will present a 
simple clock generator and driver scheme suitable for use 
with 2500 Series MOS devices. 


NOTE: The following devices employ on-chip clock gen 
erators and may be driven directly by TTL gates: 


2509 2510 2511 2518 2519 2521 2522 


The clock driver must provide relatively large voltage swings 
for the clock lines. In the case of 2500 Series MOS, the clock 
signal must swing from +5V to -12V. And it must providea 
clean waveform having reasonable rise and fall times (under 
40 ns.) and lack of positive overshoot. 


IMPROPER CLOCK WAVEFORMS 


Some common examples of improper clocking are shown in 
Figures 23, 24, and 25. 


IDEAL CLOCK WAVEFORM 
NOTE: . 
An ideal clock driving waveform. 


FIGURE 22 


POSITIVE OVERSHOOT 
NOTE: . 
Shows an overshoot occurring on the positive going 
transition of clock. This has the effect of forward 
biasing the substrate diode and must be avoided to 
prevent erratic behavior in the driven device. 


FIGURE 23 


INSUFFICIENT POSITIVE LEVEL 
NOTE: 
Shows the clock never returns to 5V (0 reference) to 
turn the input device OFF. This clock can sometimes 
appear to be functional. Data may toggle through a 
shift register, but will not be stored. 


FIGURE 24 


CROSS- COUPLED CLOCKS 
NOTE: 
Shows cross-coupling between two clock drivers 
usually caused by lack of clamping or non-active 
(high-impedance) switching in the positive direction. 


FIGURE 25 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


The positive overshoots illustrated in Figure 23 and Figure 25 
are the most common sources of clock driving trouble. When 
the clock line goes positive relative to the circuit substrate 
(Vcc) by more than approximately 0.3V, the substrate diode 
may become forward biased. When this occurs, device opera- 
tion may become erratic. And because the forward character- 
istics of the substrate diode may be different for different 
processing techniques, a clock driver may work properly 
with one device but not with another. 


A properly designed driver utilizing level clamping will pre 
vent the overshoot problem. 


THE DRIVER OUTPUT STRUCTURE 


Figures 26, 27, and 28 show possible output driver struc- 
tures togéther with their advantages and disadvantages. 


RESISTOR PULL-UP, POOR NOISE IMMUNITY, AND 
SLOW RISE TIME 


FIGURE 26 


PUSH-PULL, SLOW RISE AND FALL TIME 


ie 


12. (ACCEPTABLE) 
FIGURE 27 


COMPLEMENTARY, EXCELLENT NOISE IMMUNITY, 
FAST RISE AND FALL TIME 


ut 


12. (BEST) 
FIGURE 28 


18 


The driver circuit recommended here (Figure 29) utilizes a 
complementary output structure to obtain maximum noise 
immunity and fast rise and fall time under heavy capacitive 
load. It is capacitively coupled to the TTL clock generator. 
Resistor Rq is required only when operating at a clock 
frequency of lower than 750 KHz. This resistor shifts the 
response of the driver input circuit toward the lower fre- 
quencies by lengthening the input time constant. One clock 
driver is required for each clock phase. 


NOTES: 
Q,4, Qg 2N2222, Heat Sink Required 


Qo, Q3 2N2905, Heat Sink Required 
Cy, Co 100pF 

D,, 02° 1N914 

Ry. Ro. Rg 330hms 


Ra 2.2K (Required onty for 
operation below 750K Hz) 


(FROM TTL) 


FIGURE 29 


GENERATING MULTIPLE PHASES 


The 2500 Series MOS devices which require high level clocks 
also require more than one phase. The dynamic shift regis- 
ters require two phases and the 2508 dynamic RAM requires 
four phases. 


TWO PHASE SYSTEM 


The clock generator in Figure 30 produces alternate pulses - 
the width of which are one quarter of the input clock period 
(assuming a square wave clock). See Figure 32. 


TWO PHASE TTL CLOCK GENERATOR 


Vec 


SYSTEM 
CLOCK 


U DISABLE 


FIGURE 30 


When required, the clock pulse widths can be varied by using 
one-shot multivibrators such as the 8162 or 74121. Each 
phase width can be varied independently (the limiting factor 
being the clock period), see Figure 31(a), or a single one- 
shot ahead of the clock generator will change both phases 
simultaneously. See Figure 31(b) . 


SiNGTiCS ERRATA- MOS HANDBOOK 


Figure 29, Page 18— The correct Clock Driver Circuit is shown below. 


R4 
SIN 
(FROM TTL) 


Q4, Qqg 2N2905, Heat Sink Required 

Q9, Q3 2N2222, Heat Sink Required 

C4, Co 100pF 

Dj, Dg 1N914 

R4, Ro, R3 33 Ohm 

Rg 2.2K Ohm (Required only for operation 
below 750KHz) 


DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE 


METHOD OF PROVIDING INDEPENDENTLY 
VARIABLE CLOCK PHASES 


TWO PHASE CLOCK 
GENERATOR WAVEFORMS 


TWO PHASE 
CLOCK CLOCK 
OSCILLATOR GENERATOR 


FIGURE 31(a) 


METHOD OF PROVIDING 
VARIABLE CLOCK PHASES 


TWO PHASE 
CLOCK ONE SHOT verore 
OSCILLATOR MV GENERATOR 


FIGURE 31(b) FIGURE 32 


FOUR PHASE SYSTEM 
The circuit shown in Figure 33(a) and (b) can be used to generate four phase clock signals for the 2508 1024 RAM. 


DIVIDE-BY-12 SYNCHRONOUS COUNTER 


CLOCK IN 


(25 MHz) 


FIGURE 33(a) 


19 


DESIGNING WITH SILICON GATE #® MOS/TTL INTERFACE 


FOUR PHASE SYSTEM 


FOUR PHASE DECODER 


480ns 
e- 80ns 


Pa (gj eS oa 


FIGURE 33(b) 


Figure 34 shows typical clock input capacitances for 2500 
Series devices. The number of similar devices which can be 
driven by one clock driver is indicated. 


DEVICE ee DRIVEN (INCLUDES 
CAPACITANCE 
(oF) ALLOWANCE FOR 
WIRING CAPACITANCE) 


<2MHz (1) 2-4MHz (2) 


(1) Drive capacity 1200pF 


(2) Drive capacity 750pF 


FIGURE 34 


SiNCtiES - 


21 


SECTION 


2500 SERIES MOS SILICON 
GATE. SPECIFICATIONS 


3 


22 


Siotics 


FULLY DECODED, 256 X1 STATIC 
RANDOM ACCESS MEMORY 


2901 


DESCRIPTION 


The Signetics 2500 Series 256 x 1 Random Access Memory 
employs enhancement mode P-channel MOS devices inte- 
grated on a single monolithic chip. It is fully decoded, per- 
mitting the use of a 16-pin dual in-line package. Complete 
static operation requires no clocking. 


FEATURES 


@e FULLY DECODED ADDRESS 

@ ACCESS TIME — 1.0us GUARANTEED 

@ POWER DISSIPATION -1.6mW/BIT MAXIMUM 
DURING ACCESS 

e STANDBY POWER DISSIPATION — 50 uW/BIT 

DTL AND TTL COMPATIBLE 

@ CHIP SELECT AND OUTPUT WIRED-OR CAPABILITY 
FOR EASY EXPANSION 

@ STANDARD 16-PIN DIP SILICONE PACKAGE 

@ SIGNETICS P-MOS SILICON GATE PROCESS 
TECHNOLOGY 

® Vcc = t5V, Vop = -7, Vp = -10V RECOMMENDED 

® Vpp AND Vp MAY BE TIED FOR SINGLE NEGATIVE 
POWER SUPPLY (-9V RECOMMENDED) 


@ GUARANTEED OPERATION WITH 3V Vpp-Vp 
SEPARATION 


APPLICATIONS 


SMALL BUFFER STORES 
SMALL CORE MEMORY REPLACEMENT 
BIPOLAR COMPATIBLE DATA STORAGE 


SILICONE PACKAGING 


Low cost silicone DIP packaging is implemented and reli- 
ability is assured by the use of Signetics unique silicon gate 
MOS process technology. Unlike the standard metal gate 
MOS process the silicon material over the gate oxide passi- 
vates the MOS transistors, and the deposited dielectric 
material over the silicon gate-oxide-substrate structure pro- 
vides an ion barrier. In addition, Signetics proprietary sur- 
face passivation and silicone packaging techniques result in 
an MOS circuit with inherent high reliability and demon- 
strating superior moisture resistance, mechanical shock and 
ionic contamination barriers. 


PROCESS TECHNOLOGY 


The use of Signetics’ unique Silicon Gate Low Threshold 
Process allows the design and production of higher per- 
formance MOS circuits and provides higher functional 
density on a chip than other MOS technologies. 


23 


SILICON GATE MOS 2500 SERIES 


BIPOLAR COMPATIBILITY 


All inputs of the 2501 can be driven directly by standard 
bipolar integrated circuits (TTL, DTL, etc.). The data out- 
put buffers are capable of sinking a minimum of 2.0 mA, 
sufficient to drive one standard TTL load. 


POWER DISSIPATION 


The maximum power dissipation of 1.6mW/bit is required 
only during Read or Write. For standby operation, 50uW/bit 
is obtained by removing Vp and reducing Vpp to —2.0V. 
Removal of Vp alone will cut power dissipation by a factor 
of 1.5. 


SPECIAL FEATURE 


The outputs of the 2501 are effectively open circuited when 
the device is not selected (logic 1 on chip select). This fea- 
ture allows OR-Tying for memory expansion, 


PART IDENTIFICATION TABLE 


TYPE | PACKAGE __| OP.TEMP.RANGE 
| 25018 | 16-pin Silicone DIP 0°C. to+70°C. 


PIN CONFIGURATION (Top View) 


B PACKAGE 


. Address 6 
. Address 8 . R/W 

. Address 7 . Data Out 
Vo . Data Out 
Vec . Datatn 

. Address 5 . Address 4 
. Address 1 . Address 2 
Vop . Address 3 


. Chip Select 


1 
2 
3 
4. 
5. 
6 
7 
8. 


SIGNETICS SILICON GATE MOS 2501 


MAXIMUM GUARANTEED RATINGS (1) 


Operating Temperature O°C to +70°C 
Storage Temperature -65°C to +150°C 
All Input or Output Voltages with 

Respect to the Most Positive Supply 

Voltage, Vcc +0.3V to -20V 
Supply Voltages Vpp and Vp with 

Respect to Vcc -18V 
Power Dissipation at Ta = 70°C 640mW 


NOTES: 
1. Stresses above those listed under ‘‘Maximum Guaranteed Rating’ 
may cause permanent damage to the device. This is a stress rating 


DC CHARACTERISTICS 
(Tp = 0°C to 70°C, Veg = +5V (8) , Vpp = -7+ 5% 


Input Load Current 

(Ail Input Pins) 
Output Leakage Current 
Power Supply Current, Vpp 


Power Supply Current, Vp 
Power Supply Current, Vpp 


Power Supply Current, Vp 


»Vp =-10V+ 5% unless otherwise specified. 


24 


only and functional operation of the device at these or at any 
other condition above those indicated in the operational sections 
of this specification is not implied. 


. For operating at elevated temperatures the device must be . 


derated based on a +150°C maximum junction temperature and 
a thermal resistance of 150°C/W junction to ambient. 


. All inputs are protected against static charge. 
. Parameters are valid over operating temperature range unless 


specified. 


. All voltage measurements are referenced to ground. 
. Manufacturer reserves the right to make design and process 


changes and improvements. 


_ Typical vatues are at +25°C and nominal supply voltages. 
A Vec tolerance is +5%. Any variation in actual Vec will be 


tracked directly by V; Lo Vin and Vou which are stated for 
a Vec of exactly 5 volts. 


See notes above) 


CONDITIONS 


VIN = 0.0V; Ta = +25 C 


VOUT = 0.0V, Chip Select 
Input = +3.3V, Tp, = +25°C 


lo, =0.0mMA Ta, = +25°C 
Vpp = Vp =-9V 


SIGNETICS SILICON GATE MOS 2501 


SWITCHING CHARACTERISTICS 
Guaranteed Limits Ta =+25°C , Voc = +5V (8) , Vpp = -7V4.5% , Vp = -10V+5% except as noted. 


READ CYCLE WRITE CYCLE 


SYMBOL TEST LIMITS (usec) MAX SYMBOL TEST LIMITS (usec) MIN. 
[Resa 


BLOCK DIAGRAM 


PULSE GENERATOR 


256-BIT RAM PLANE 


X ADDRESS DECODE 
X LINE DRIVERS 


DATA PULSE 
MODEL 203 
DATA GEN. CH2 
OuT 


EXT. —ND 
cock §=P stock 


NOTES: 

1. Each clock time is split into a Read followed by a Write. Read 
and Write times can be varied by adjustment of the “‘delay’”’ and DATAINIZO 
“width’' controls of the pulse generator. 

. Data generator produces a 256-bit block of data, 32 bits repeated 
8 times. ‘‘PCM’’ mode used so data can be changed in 32 bits of 
the 2501 from one cycle to the next. 

3. All inputs to the 2501 are standard TTL outputs with Vec = 
+5V +5%. 

. Access time is measured between A1 (least significant address 
input) and points 1 and 2. 

5. Vpop =Vpb = —-9V 


CONDITIONS OF TEST 


Input pulse amplitudes: 0 to +5V, Input pulse rise and fall times: < 10 nsec. Speed measurements referenced to 1.5V levels. 
Output load is 1 TTL gate; measurements made at output of TTL gate (tog < 10 nsec) 


READ CYCLE (For Measurement Purpose Only) WRITE CYCLE (For Measurement Purpose Only) 


DATA IN 
OuTPUTS 


25 


SIGNETICS SILICON GATE MOS 2501 


TYPICAL CHARACTERISTICS ‘”? 


ACCESS TIME VERSUS ACCESS TIME VERSUS 
LOAD CAPACITANCE TEMPERATURE 


1500 
1000 
600 
0 

0 sO 100 180 200 


LOAD CAPACITANCE (pF) 


ACCESS TIME (nSEC) 


ACCESS TIME (nSEC) 


TEMPERATURE (°C) 


TYPICAL ACCESS TIME AND POWER DISSIPATION POWER SUPPLY CURRENT VERSUS 
VERSUS SINGLE POWER SUPPLY VOLTAGE POWER SUPPLY VOLTAGE 


1000 


500 


ACCESS TIME (ns) 
POWER DISSIPATION (mW) 
POWER SUPPLY CURRENT tmA) 


Vec—-Vp (Vv) Vec - POWER SUPPLY VOLTAGE (Vi 


OUTPUT CURRENT VERSUS TYPICAL ACCESS TIME VERSUS 
TEMPERATURE SUPPLY VOLTAGES 


Voo =Vp : -9 


s- MAXIMUM 
Vout 70 46Vv 


LLOWABLE 
‘i DISSIPATION 
16 


OUTPUT CURRENT Isink (mA) 
Vcc - VolV) 


E «OPERATION OUTSIDE 
E “TYPICAL OPERATING 
| AREA” IS NOT RECOMMENDED, 


() Vpp - -7V. Vp = -10V 
TEMPERATURE (°C) (2) Vop - Vp = -9V Vcc - YoptV) 


(1) NOTE: For all typical curves, Vec = 5V, Vop ==7V, Vp =710V, Ta = +25°C (unless otherwise noted). 


26 


TYPICAL CHARACTERISTICS (Cont'd) 


OUTPUT CURRENT VERSUS 
SUPPLY VOLTAGE 


TYPICAL @ 
Vpp*Yo 
Vec = +5V 
Tp = 25°C 


OUTPUT CURRENT (mA) 


SUPPLY VOLTAGE (Vop = Vp) (VOLTS) 


APPLICATION INFORMATION 
OPERATION 


The 2501 is a 256 x 1 Random Access Memory element. It 
is fully decoded and provides control for Read/Write and 
Chip Select modes. The operation of this element is des- 
cribed below. 


ADDRESSING 


An 8-bit address code will select any one of 256 bits for 
either Read or Write operation. All address input logic levels 
are compatible with standard bipolar TTL or DTL logic 
levels. 


READ 


A logic ‘0’ level (“OV) applied to the R/W control will 
result in a Read operation. This can be presented to the R/W 
control simultaneously or before application of an address 
code. !n this mode the information from the memory: will 
be available on the outputs less than psec later than the appli- 
cation of an address code. Note that there is no need to re- 
write the data into the memory after a read operation since 
the read is non-destructive. 


27 


SIGNETICS SILICON GATE MOS 2501 


WRITE 


A “Write” command is a logic ‘‘1” (2+3.3V) level to the 
R/W control. This should be presented-to the chip no sooner 
than 300 nsec after the application of an address code. This 
time delay is necessary for proper address decoding. This 
“Write’’ command has to be present for at least 400 nsec to 
insure that the information is written into the memory. The 
“Write’’ command should be off (i.e., memory should be in 
“‘Read”’ mode) by the time the address code is changed. The 
input data should be present for at least the last 300 nsec of 
the ‘Write’ command. 


CHIP SELECT 


The memory array is inhibited with the application of a logic 
“1 (24+3.3V) to the Chip Select control. This will render 
both R/W and Data Input leads ineffective and will stop in- 
formation transfer through the output buffer. The address 
decoder, however, will not be inhibited. This feature allows 
an effective increase in memory speed. (See below) The out- 
put leads are open while the memory array is inhibited. This 
allows OR-Tying of many memory arrays. 


RANDOM ACCESS MEMORY 


Arbitrary size memories can be built by tying appropriate 
numbers of 2501's together. Figure 1 shows a block di- 
agram of a memory system containing 256 N words by M 
bits. For example, if the memory size were 4096 words by 
12 bits, N = 16 and M = 12. Thus the number of 2501's 
required is M x N = 192. The address inputs A, through 
Ag are common to all the rows. Inputs Cy, through Cy 
provide the column select and are wired to the Chip Select 
inputs of the 2501’s. For the example of the 4096 word 
memory, a 12-bit address must be specified. The first 8 
bits would drive inputs Aq through Ag directly. The re- 
maining 4 bits would have to be decoded externally into 
the 16 lines required for the 16 columns. A block diagram 
of the 4096 x 12 memory is shown in Figure 2. Any 
number of 2501's can be OR-tied together, however, access 
time is affected by capacitive loading (approximately 1 
nsec/pF). Each 2501 output represents 7 pF (typical) of 
loading, but the amount of stray capacitance contributed 
by the printed circuit board wiring can vary greatly and 
must be determined for each application. Figure 3 shows 
two different bit line organizations where the capacitive 
load that must be driven by the 2501 is reduced by employ- 
ing logic gates to perform the OR-ing function. The organi- 
zation of Figure 3b results in the minimum load capac- 
itance but requires more gates per bit line than other 
organizations. 


SEQUENTIAL MEMORY 


On applications such as program memory or table lookup, 
where memory operations are highly sequentia!, but non- 
synchronous, the memory may be organized for a faster 


SIGNETICS SILICON GATE MOS 2501 


eee 


SEQUENTIAL MEMORY (Cont'd) 


average memory cycle than in the true random access case. 
This involves using the fact that access may be made 
through the chip select input in 0.2 usec (typically) where 
a typical access time if one of the address inputs (A-Ag) 
changes, is 0.8 psec. For the case of the 4096 word memory 
organized in this fashion information can be read out at an 
average access time of 0.25 usec since access is made through 
the Chip Select input 15/16 of the time. 


LOW POWER OPERATION 


Another feature of this memory element is its capability 
of operating at very low standby power levels. The only 
time the element has to dissipate full power (~1.6mW/bit) 
is when it is exercised by either ‘Write’ or ‘‘Read’’ opera- 
tion. In the standby mode, when the chip will only store 
information, but does not need to be accessed, the periph- 
eral power supply (Vp) is completely shut off. This will 
immediately cut the total power drain by a factor of 1.5. 


M=#BITS 
256N = # WORDS 


FIGURE 1. ORGANIZATION OF 2501's INTO LARGER MEMORY 


DATA REGISTER 


ADDRESS REGISTER 


BIT LINE 
192 2501's OUTPUTS 
REQUIRED 


FIGURE 2. ORGANIZATION OF 4096 WORD BY 12-BIT MEMORY 


SIGNETICS SILICON GATE MOS 2501 


fo es Fe fe eel 


P| i 
i ee ee 
A SR 


a. Combination of wire-O Ring and logic-ORing of 2501's 


b. Logic-ORing of 2501's 


FIGURE 3. BIT LINE ORGANIZATIONS TO MINIMIZE CAPACITIVE LOAD—4096 WORDS 


PACKAGE MAXIMUM POWER DISSIPATION PACKAGE INFORMATION 


B PACKAGE 


LEAD #1 


pa a 
021 .110 2 je--- G88 


015 .090 


MAXIMUM POWER DISSIPATION (mW) 


233 : ! . : ©) i: i 


NOTES: 
1, Lead Material: Alloy 42 or equivalent 
2. Body Material: Silicone molded 
@) Tolerances non cumulative 
@) Signetics symbol denotes Lead #1 
©) Lead spacing shall be measured within this zone 
AMBIENT TEMPERATURE (‘C) 6. Body dimensions do not include molding flash 


29 


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JILVINAHOS LINDYID 


LOSZ SOW ALVD NOOITIS SOILANDIS 


1024 BIT CAPACITY MULTIPLEXED 
DYNAMIC SHIFT REGISTERS 


2902 
2903 
2904 


Si Netics 


SILICON GATE MOS 2500 SERIES 


DESCRIPTION BIPOLAR COMPATIBILITY 

These Signetics 2500 Series 1024-bit multiplexed dynamic The data inputs of these registers can be driven directly by 
shift registers consist of enhancement mode P-channel MOS standard bipolar integrated (TTL, DTL, etc.) or by MOS 
devices integrated on a single monolithic chip. Due to on- circuits. The bare drain output stage provides driving capa- 
chip multiplexing, the data rate is twice the clock rate. bility for both MOS and bipolar integrated circuits (one 


standard TTL load). 


FEATURES | PIN CONFIGURATIONS (Top View) 

@ 10 MHz TYPICAL DATA RATE 

@ THREE CONFIGURATIONS—QUAD 256, DUAL 512, 
SINGLE 1024 

@ LOW POWER DISSIPATION—40 uW/bit at 1 MHz 
DATA RATE 

@ LOW CLOCK CAPACITANCE-—140 pF 

@ TTL, DTL COMPATIBLE 

@ STANDARD PACKAGES - 8 LEAD TO-99, 8-PIN 
AND 16-PIN SILICONE DUAL IN-LINE PACKAGE 

@ SIGNETICS P-MOS SILICON GATE PROCESS 
AND SILICONE PACKAGING TECHNOLOGIES 


1. 
2. 
3. 
4. 
5. 
6. 
7. 
‘8. 


APPLICATIONS 

LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST BUFFER MEMORIES 

CRT REFRESH MEMORIES 

DELAY LINE MEMORY REPLACEMENT 


PROCESS TECHNOLOGY 

Use of low threshold silicon gate technology allows high 
speed (10 MHz typical)while reducing power dissipation and 
and clock input capacitance dramatically as compared to 
conventional technologies. 

The use of low voltage circuitry minimizes power dissi- 
pation and facilitates interfacing with bipolar integrated 
circuits. 


SILICONE PACKAGING 


Low cost silicone DIP packaging is implemented and reli- 
ability is assured by the use of Signetics unique silicon gate 
MOS process technology. Unlike the standard metal gate 
MOS process, the silicon material over the gate oxide passi- 
vates the MOS transistors, and the deposited dielectric mate- 
rial over the silicon gate-oxide-substrate structure provides 


PART IDENTIFICATION TABLE 


FUNCTION PACKAGE 


an ion barrier. In addition, Signetics proprietary surface 2502B ‘Quad 256-bit 16-Pin DIP 
passivation and silicone packaging techniques result in an 2503TA Dual 512-bit TO-99 
MOS circuit with inherent high reliability and demonstrat - 2503V Dual 512-bit 8-Pin DIP 
ing superior moisture resistance, mechanical shock and ionic 2504TA Single 1024-bit TO-99 
contamination barriers. 2504V Single 1024-bit 8-Pin DIP 


31 


SIGNETICS SILICON GATE MOS 2502, 2503, 2504 


MAXIMUM SIGNETICS GUARANTEED RATINGS(1) 


Operating Ambient Temperature(2) 0°C to +70°C 
Storage Temperature -65°C to + 150°C POWER DISSIPATION VERSUS DATA RATE 
Power Dissipation(2) at T, = 70°C 

TA and V Package 535mW 

B Package 640mW 


Data and Clock Input Voltages 
and Supply Voltages with 
respect to Voc (3) +0.3V to -20V 


NOTES: 

1. Stresses above those listed under ‘‘“Maximum Guaranteed Rating” 
may cause permanent damage to the device. This is a stress rating 
only and functional operation of the device at these or at any 
other condition above those indicated in the operational sections 
of this specification is not implied. 

2. For operating at elevated temperatures the device must be 
derated based on a +150°C maximum junction temperature and 
a thermal resistance of 150°C/W (TA and V package)or 125° C/W 
(B package). 

3. All inputs are protected against static charge. 

4. Parameters are valid over operating temperature range unless 
specified. 

5. Alt voltage measurements are referenced to ground. 

6. Manufacturer reserving the right to make design and process 
changes and improvements. 

7. Typical values at +25°C and nominal supply voitages. 

8. Voc tolerance is +5%, Any variation in actual Vec will be 
tracked directly by Vv; L: Vin and Vou which are stated for 
a Vec of exactly 5 volts. 


POWER DISSIPATION (mW) 


DATA RATE (MHz) 


DC CHARACTERISTICS 
Ta= 0°C to +70°C; Vpp = -5V £5%; Voc = +5V (8) unless otherwise noted. (See Notes 4,5,6,7). 


Input Load Current Vin = Vcc to Vpp. Ta = 25°C 


Vol = V2 = -10V 


Output Leakage Current 7 
Vout = 9.0V, Ta = 25°C 


Clock Leakage Current Vitec = —10V , Ta= 25°C 


Outputs at logic ‘0 4 MHz data 


rate,61 = #2 = 85ns continuous 


Power Supply Current ; 
operation, Vjpc= —12V 


Ta = 25°C 
Input ‘‘Low”’’ Voltage 
Input ‘’High’”’ Voltage 
Clock Input “‘High’’ Voltage 


Clock Input ‘““‘Low” Voltage 


32 


SIGNETICS SILICON GATE MOS 2502, 2503, 


CONDITIONS OF TEST 
Input rise and fall times: 10 nsec. Output load is 1 TTL gate. 


BIT N+ 10° BITN+2 


as Pe RATE—enl 


TIMING DIAGRAM 


*tw and tog same for p2 
**N=256 for 2502, N = 512 for ree 
2503, N = 1024 for 2504 AS BEY a IN GIT 2 


DATA OUT 


ah 


AC CHARACTERISTICS 
Ta = 25°C, Vpp = -5V #5%; Voc = +5V (8); Vi_c= —11V , (See notes 4, 5, 6, 7). 


Frequency Clock Rep Rate 
Frequency Data Rep Rate 
Clock Pulse Width 
Clock Pulse Delay 
Clock Pulse Transition 
Data Write Time (Setup) 
Data in Overlap 
Data Out 
Input Capacitance 3 @ 1 MHz 25 mV p-p 
Output Capacitance S @ 1 MHz 25 mV p-p 
Clock Capacitance @ 1 MHz 25 mV p-p 


2504 


Output “Low” Voltage 3 Vv Ri =3k, depends on R; and TTL Gate 


Output “‘High”’ Voltage 
Driving MOS 
Output “High” Voltage 
Driving TTL 


R, = 5.6k 


R, = 3k 


1, 
‘ 


Figure 1 is a simplified illustration of the timing of a 4-bit multiplexed register showing input output relationships with 
respect to the clock. If data enters the register at ¢1 time, it exits at 1 time, (beginning on $1 ’s negative going edge and 
ending on the succeeding 2's negative going edge). 


33 


SIGNETICS SILICON GATE MOS 2502, 2503, 2504 


POWER DISSIPATION/BIT 
VERSUS SUPPLY VOLTAGE 


: 
é 
4 
g 
[Vec- Voo! (VOLTS) 
POWER DISSIPATION/BIT 
VERSUS TEMPERATURE 
1.0 
= 
= 
3 
0.8 E 
06 5 
j : 
° é 
& o« 2 
é = 
=) 
= 
a 
0.2 = 
3 
Z 
rt) 
0 10 20 30 40 50 60 70 
TEMPERATURE (°C) 
CLOCK AMPLITUDE V, 
VERSUS MAXIMUM DATA RATE 
H 
F 
< 
6 
5 
7 
z 
CLOCK AMPLITUDE (VOLTS p-p) 
NOTE: 


Conditions for T ypical Curves; Veco = t5V.Vpp= ~5V,04 PW and$opyw=85ns, 


34 


POWER DISSIPATION/BIT 
VERSUS CLOCK AMPLITUDE 


0.8 
06 


04 


POWER DISSIPATION (m\WW/BIT) 


0.2 


CLOCK AMPLITUDE (VOLTS p-p) 


MAXIMUM ALLOWABLE POWER DISSIPATION 
VERSUS AMBIENT TEMPERATURE 


1000 


800 


600 


200 


TEMPERATURE (°C) 


MINIMUM OPERATING DATA RATE 
VERSUS TEMPERATURE 


DATA RATE (Hz) 


TEMPERATURE (°C) 


Vg =11V, Ta=25 °C, foata=10MHz unless otherwise noted. 


SIGNETICS SILICON GATE MOS 2502, 2503, 2504 


APPLICATIONS INFORMATION 


DTL/TTL/MOS INTERFACES 


4-266 BIT REGISTER 


i 
ered 


NOTE: When interfacing MOS to MOS output resistors should be 4.7K min 


WRITE/RECIRCULATE LOGIC 


48IT, 2. INPUT DIGITAL 
MULTIPLEXER 

4-266 BIT 
REGISTER 


pipes UPR 
 OTLTTL 
‘ 


9 


O 
are 
O 


Writes 
recincurate © 


Tote ec cso rr eee 
t 


ALL RESISTORS 3K 5% 


35 


SIGNETICS SILICON GATE MOS 2502, 2503, 2504 


CIRCUIT SCHEMATIC 


, 
4 
\ 
) 
L 
‘ 
\ 
' 
' 
! 
' 
! 
' 
' 
t 
! 
| 
' 
4 
! 


1. N= 1024 on 2504 
2. N= 512 on 2503 schematic for second register same as above. 
3. N = 256 on 2502 schematic for second, third and fourth registers same as above. 


PACKAGE INFORMATION 


TA PACKAGE B PACKAGE 


ae DIA. LEAD #1 


.052 * | 
.044 


bad 


021 
 -'015 


NOTES: 
1. Lead Material: Alloy 42 or equivalent ,tinned 
NOTES: 2. Body Material: Silicone molded 
. Lead Material: Kovar or equivatent - gold plated (©) Tolerances non cumulative 
. Body Material: Eyelet, kovar or equivalent - gold @ Signetics symbol denotes Lead #1 
plated glass body . ee . 

. Lid Material: Nickel, weld seal ‘) Lead spacing shali be measured within this zone 

6. Body dimensions do not include molding flash 


SiNCtics 


36 


V PACKAGE 


NOTES: 
1. Lead Material: Alloy 42 or equivalent, tinned 


2. Body Material: Silicone Molded 

@ Tolerances Non-Cumulative 

Signetics Symbol Denotes Lead =1 

6) Lead Spacing shall be Measured within this Zone 
6. Body Dimensions do not include Molding Flash 


SqNCtcS 


DESCRIPTION 


These Signetics 2500 Series 512 and 1024 bit recirculating 
dynamic shift registers consist of enhancement mode 
P-channel MOS devices integrated on a single monolithic 
chip. Internal recirculation logic plus write and read 
controls, together with two chip select controls are included 
on the chip. 


FEATURES 


@ HIGH FREQUENCY OPERATION-—3MHz TYPICAL 


CLOCK RATE 


@ SINGLE 512, SINGLE 1024 

@ TTL, DTL COMPATIBLE 

@ 2-CHIP SELECT CONTROLS FOR XY MATRIX 
SELECTION 

@ WRITE AND READ CONTROLS INCLUDED 


@ LOW POWER DISSIPATION—150uW/bit at 1 MHz 


LOW CLOCK CAPACITANCE-—80pF for 512, 160pF 
for 1024 Bits 


@ +5, -5V POWER SUPPLIES 


@ STANDARD PACKAGE-10 LEAD TO-100 


@ SIGNETICS P-MOS SILICON GATE PROCESS 
TECHNOLOGY 


APPLICATIONS 

FAST ACCESS SWAPPING MEMORY SYSTEMS 
LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST BUFFER MEMORIES 

CRT REFRESH MEMORIES 

DELAY LINE MEMORY REPLACEMENT 
DRUM MEMORY REPLACEMENT 


PROCESS TECHNOLOGY 


Use of low threshold silicon gate technology allows high 
speed (3MHz typical) while reducing power dissipation and 
clock input capacitance dramatically as compared to other 
technologies. The use of low voltage circuitry minimizes 
power dissipation and facilitates interfacing with bipolar 
integrated circuits. 


BI POLAR COMPATIBILITY 


The signal inputs of these registers can be driven directly by 
standard bipolar integrated (TTL, DTL, etc.) or by MOS 
circuits. The bare drain output stage provides driving 
capability for both MOS and bipolar integrated circuits 
(one standard TTL load). 


912 AND 1024 BIT RECIRCULATING 
DYNAMIC SHIFT REGISTERS 


37 


2905 
2512 


SILICON GATE MOS 2500 SERIES 


PIN CONFIGURATION (Top View) 
K PACKAGE 


1. Select 1 

2. Write 

3. Input 

4. $4 Output Clock 


6. $9 Input Clock 
7. Output 

8. Read 

9. Select 2 


10.V, 


5. Vcc D 


BLOCK DIAGRAM 


N 512 or 1024 ‘0’ - OV, ‘1’ - +5V. 
When S1 or S2 ts ‘0’ Data Recirculates 
When S11 and S2 are ‘1’ see truth table 


TRUTH TABLE 


WRITE | READ | FUNCTION 


Recirculate, Output is ‘0’ 


Recirculate, Output is Data 
Write Mode, Output is ‘0’ 
Read/Write, Output is Data 


PART IDENTIFICATION TABLE 


PARTNO. | BITLENGTH | PACKAGE — 
2505K 512 10 pin TO - 100 
2512K 1024 


10 pin TO - 100 
MAXIMUM GUARANTEED RATINGS (1) 


O°C to +70°C 
-65°C to + 150°C 


Operating Ambient Temperature (2) 
Storage Temperature 


Power Dissipation (2) 535mW@T p> 70°C 
Data and Clock Input Voltages 

and Supply Voltages with 

respect to Vcc + 0.3V to - 20V 


SIGNETICS SILICON GATE MOS 2505, 2512 


NOTES: 5. Parameters are valid over operating temperature range unless 
1. Stresses above those listed under ‘‘Maximum Guaranteed Rating” otherwise specified. 
May cause permanent damage to the device. This is a stress rating 6. All voltage measurements are referenced to ground. 
only and functional operation of the device at these or at any 7. Manufacturer reserves the right to make design and process 
other condition above those indicated in the operational sections changes and improvements. 
of this specification is not implied. 8. Typical values are at +25 °C and nominal supply voltages, 
2. For operating at elevated temperatures the device must be 9. Vec tolerance is 5%. Any variation in actual Vec will be 
derated based on a +150 C maximum junction temperature and tracked directly by Vv; L* vy H and Vou which are stated for 
a thermal resistance of 150°C/W junction to ambient. a Vcc of exactly 5 voits. 
3. All inputs are protected against static charge. 10. Vo, is a function of the input characteristics of the driven 
4. See ‘Minimum Operating Frequency” graph for low limits on TTL/DTL gate !o, and Vc_amp and the value of the pull- 
data rep, rate. down resistor (R__). 


DC CHARACTERISTICS TA = 0 C to +70 C;Voc= +5V (9) ; Vpp = —5V +5% unless otherwise noted. 


SYMBOL TEST 


Output Leakage Current rs V 52 =-12V, 
out ~~5.5V: Tp = 


Clock Leakage Current 


Power Supply Current: 2505 Continuous Operation; 
6 pW = 150nS, 1MHz 
2512 


Input “High” Voltage 
Clock Input “Low” Voitage 


Clock Input ‘High’ Voltage 


I 

Input ‘Low’ Voltage 
Vitc 
VIHC 


TIMING DIAGRAM 


4-BiIT RECIRCULATING SHIFT REGISTER 


ets | sit2 | ets | sire | ots | sits | oit7 | sits | aire | sitio | eit11| ert12 | BIT 13 NOTE 1: (WRITE cycle) 


The positive and negative going 


OUTPUT +5 edge of the "’ W ", “S1", “S2” 
CLOCK ¢, = 10 controls are coincident with the 
| | negative going edge of the input 
INPUT 5 clock (¢5). The ‘‘Read’’ control 
CLOCKo2 =—s__49 may be either ‘’1’’ or ‘’0"' 


NOTE 2: (RECIRCULATE cycle) 


Data recirculates if one or more 
of the following control lines are 
"0"; S1, S2 and W Read may 
be either ‘1°’ or ‘‘O" 


"0" 


+5V o 1” | 
INT cay . iN 4 


| | DATA DATA 
DATA OUT a DATA [OUT 2 QUT 3} DATA 


OUT 1 OuT4 
| | | NOTE 3: (READ cycle) 
WRITE +5V 
Be ee The positive going edge of the 


| | | | “Read”, 'S1"’, “‘S2’' controls are 
coincident with the negative edge 

Tocitie beak ooo Po ee ee of the output clock (44). The 
negative going edge of R, S1, S2 

| | | | is coincident with the negative 


READ Te Te a Oe going edge of either clock pulse 


=e succeeding the last desired data 
NOTE i NOTE 2. NOTE 3: f : 
WRITE CYCLE [Rec euincevere READ CYCLE | ou tee ce WwW may be either 
1° or “O 
Figure 1 


Figure 1 is a simplified illustration of the timing of a 4-bit recirculating shift register showing the 3 basic modes of operation. 


38 


SIGNETICS SILICON GATE MOS 25085, 2512 


CONDITIONS OF TEST 
Input rise and fall times: 10 nsec Output load is 1 TTL gate 


TIMING DIAGRAM 


SELECT 2 
0 


' ’ 
t ' 
6 
READ | \ 


NOTE: N=512 for 2505, N=1024 for 2512 


‘SYMBOL TEST 


Clock Data Rep Rate M 


Clock Pulse Width 
Clock Pulse Delay 10 
f 


Clock Pulse Transition 
| tow | Data Write (Setup) Time 


Data to Clock Hold Time 


Clock to Data Out Delay 


Clock to ‘‘Read’’ or 
“Chip Select” or ‘‘Write” 
Timing 


E 
yn 
0) 
re) 


tR-;tcs+ | - Clock to “Read” or 
tw + “Chip Select” or ‘‘Write” 
Timing 
Cin | Input Capacitance | 
Cout 


Cin 
Cy Clock Capacitance 
2505 
2512 
Output ‘‘Low” Voltage 
VoH! Output “High’”’ Voltage Ri = 3.0K; 1 TTL Load 
Driving 1 TTL Load (1p = 100A) 


VOH2 Output ‘‘High’’ Voltage V Ri = 5.6K; Cy = 10 pF 
Driving MOS 


Hz 
pF 
pF 


Ri = 3.0K; 1 TTL Load 
(lL = 1.6mA) Note 10 


< 


SIGNETICS SILICON GATE MOS 2505, 2512 


CHARACTERISTICS CURVES 


POWER DISSIPATION/BIT 
VERSUS SUPPLY VOLTAGE 


= 
g 
= 
: 

SUPPLY VOLTAGE (Vcc Vpp) (VOLTS) 

MAXIMUM CLOCK RATE 

VERSUS CLOCK AMPLITUDE 

é 


CLOCK AMPLITUDE (Vg (VOLTS) 


MAXIMUM PACKAGE POWER DISSIPATION 


VERSUS TEMPERATURE 


WY 


Aa 


MAXIMUM PACKAGE POWER DISSIPATION(mW) 


TEMPERATURE ( C) 


NOTE: 


POWER DISSIPATION/BIT 
VERSUS CLOCK RATE 


POWER DISSIPATION PER BIT {uW) 


CLOCK RATE (MHz) 


POWER DISSIPATION/BIT 
VERSUS TEMPERATURE 


POWER DISSIPATION PER BIT (.W) 


TEMPERATURE (’C) 


MINIMUM OPERATING 
CLOCK FREQUENCY 


MINIMUM CLOCK FREQUENCY (Hz) 


TEMPERATURE ( C) 


Conditions for Typical Curves = Vog=t8V, Vpp=—5V, Clock Duty Cycle=35°C, fo, «=2.5MHz, Vop-p716V; Spy =180ns, T ,=25°C 


unless otherwise noted 


40 


SIGNETICS SILICON GATE MOS 2505, 2512 


APPLICATIONS DATA — 


TTL/DTL/MOS INTERFACES 


NBIT SHIFT 
a], REGISTER) 


inal 


READ Sy 


8250 + 8890's 


Y DECODER 


aiulnal 
eh Gt 
ee 


1. Outputs common for each plane 4. All 2's common 
2. All inputs common for each plane 5. All Vcc common 
3. All d4's common 6. All Vpp common 


SIGNETICS SILICON GATE MOS 2505, 2512 


CIRCUIT SCHEMATIC 


READ (8) O—~f 
Vee: PINS 
Von: PIN 10 
oy: PING 
2: PING 


NOTE: N=512 for 2505 
N = 1024 for 2512 


PACKAGE INFORMATION 


K PACKAGE 


328 
DIA 030 
020 
.045 
‘o1gINSULATOR 


44 


1, Lead Material: Kovar or Equivalent - Gold Plated 

2. Body Material: Eyelet, Kovar or Equivalent - Gold 
Plated Glass Body 

3. Lid Material: Nickel, Weld Seal 


42 


‘SqnBtiES 


SiNQtics 


DESCRIPTION 


These Signetics 2500 Series dual 100-Bit dynamic shift 
registers consist of enhancement mode P-channel MOS 
devices integrated on asingle monolithic chip. They use two 
clock phases. 


FEATURES 


e@ HIGH FREQUENCY OPERATION 

4 MHz TYPICAL CLOCK RATE 

TTL, DTL COMPATIBLE 

LOW POWER DISSIPATION — 400 pW/BIT AT 1 MHz 

LOW CLOCK CAPACITANCE 40pF MAXIMUM 

LOW OUTPUT IMPEDANCE — 300 OHMS TYPICAL 

BARE DRAIN AND MOS RESISTOR VERSIONS 

AVAILABLE 

@ STANDARD PACKAGES — 8 LEAD TO-5 AND 8 
LEAD SILICONE DIP 

@ SIGNETICS P-MOS SILICON GATE AND SILICONE 
PACKAGING TECHNOLOGIES 


APPLICATIONS 


LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST BUFFER MEMORIES 


PROCESS TECHNOLOGY 


Use of the low threshold silicon gate technology allows high 
speed (3 MHz guaranteed), while reducing power dissipation 
by a factor of 2 and reducing clock input capacitance 
dramatically as compared to conventional MOS technologies. 


SILICONE PACKAGING 


Low cost silicone DIP packaging is implemented and reli- 
ability is assured by the use of Signetics unique silicon gate 
MOS process technology. Unlike the standard metal gate 
MOS process the silicon material over the gate oxide passi- 
vates the MOS transistors, and the deposited dielectric 
material over the silicon gate-oxide-substrate structure pro- 
vides an ion barrier. In addition, Signetics proprietary sur- 
face passivation and silicone packaging techniques result in 
an MOS circuit with inherent high reliability, demonstrating 
superior moisture resistance, mechanical shock and ionic 
contamination barriers. For further information reference 
Signetics - ‘Silicone Package Qualification Report’’. 


DUAL 100-BIT DYNAMIC 
SHIFT REGISTER 


2906 
2907 
2517 


SILICON GATE MOS 2500 SERIES 


BIPOLAR COMPATIBILITY 


The dual 100 bit device can be driven directly by standard 
bipolar integrated circuits (TTL, DTL, etc.) or by MOS 
circuits. The design of the output stage provides driving 
capability for MOS or bipolar IC’s. 


It is available in bare drain configuration or with internal 
pull down resistor values of 7.5k or 20k to provide easier 
interfacing with other MOS circuitry. 


PIN CONFIGURATIONS (TOP VIEW) 


T PACKAGE V PACKAGE 


100 BIT 
REGISTER 
100 BIT 
REGISTER 


. Output Clock (¢ 1) 
. Output 2 


. Input 2 


Voo 


Input 1 
. Output 1 
- Input Clock (p>) 


Vec 


Input 1 

Output 1 

Input Clock (¢ 5) 
Vee 
Output Clock (b4) 
Output 2 

. Input 2 


Vop 


ONATAWN> 
ONO PWN = 


BLOCK DIAGRAM 


mi De Do er 


PART IDENTIFICATION TABLE 


Bare Drain 8 Pin TO-5 
Bare Drain 8 Pin DIP 
7.5k Pull Down | 8 Pin TO-5 
7.5k Pull Down | 8 Pin DIP 
8 Pin TO-5 
8 Pin DIP 


20k Pull Down 
20k Pull Down 


SIGNETICS SILICON GATE MOS 2506, 2507, 2517 


MAXIMUM GUARANTEED RATINGS (1) NOTES: 


1. Stresses above those listed under ‘‘Maximum Guaranteed Rating” 
may cause permanent damage to the device. This is a stress rating 
only and functional operation of the device at these or at any 
other condition above those indicated in the operational sections 
of this specification is not implied. 

2. For operating at elevated temperatures the device must be 
derated based on a +150°C maximum junction temperature and 
a thermal resistance of 150°C/W (T package) or 175° C/W (V 
package). 

3. All inputs are protected against static charge. 

4. Parameters are valid over operating temperature range unless 
otherwise specified. 

5. All voltage measurements are referenced to ground. 


Operating Ambient 0°C + 70°C 6. Manufacturer reserves the right to make design and process 
° 2 hanges and improvements. 
= + chang 
Storage Temperature Py Be S100: 7. Typical values are at +25°C and nominal supply voltages. 
Power Dissipation (Note 2) @ Tp=70 C 8. Vec tolerance is t5%. Any variation in actual Vec will be 
T Package 535mW tracked directly by V,,. V),, and Vo}, which are stated for 
V Package 455mW a Vec of exactly 5 volts. 
? 9% VoL (for this bare drain device) is a function only of the driven 
Clock Input Voltages with respect to Vecl3) +0.3 to -20V gate characteristics together with the external pull-down resistor. 
Supply and Data Input Voltages with (Rpp). 
a - 40.3 12V 10. See Figure 2 for definitions. 
-J3 to - 11. Logic Convention: Data Lines - Positive; Clocks - Negative. 


respect to Vcc (3) 


DC CHARACTERISTICS 
Ta = 0°C to +70°C; Vop = -5V +5%:; Vcc = +5 (8); unless otherwise noted(Notes: 4,5,6,7). 


Nut 


Mwah Sg 


Input Load Current 
(Input 7) 


IN 2, OUT 2,IN1= —5.5V, 
Vpop =—4, 5V, Ta =25C 


Input Load Current 
(Input 2) 


+5V ON OUT 2, 41, 42, Vcc. 
IN 1,OUT 1,IN2= —5.5V, 
Vpp =-4.5V, Ta = 25°C 


Output Leakage Current 
(OUT 1) (Notes 9 & 10) 


+5V ONIN 1, Vcc, OUT 2, ¢2, 
IN 2, Vpp, OUT 1 = —5.5V 
61 = —5V,Ta =25°C 


Output Leakage Current 
(OUT 2) (Notes 9 & 10) 


+5V ONIN 1, OUT 1, Vcc, 2, 
IN 2, Vpp, OUT 2 = —5.5V, 
= —5V,Tap = 25°C 


Clock Leakage Current Vé1 =-12V, Vpp = -4.5V 


All other pins +5V, 


Clock Leakage Current Vé2 = -12V, Vpp =-4.5V 


All other pins +5V 


Input ‘‘Low” Voltage 
(Note 11) 


Input “High” Voltage Vv 
(Note 11) 


Cin Input Capacitance Vin = Vcc. 1 MHz, 
(Inputs 1 & 2) 25 mV p-p 

,1 MHz, 
-P 


Vince Clock Input “‘High’’ Voltage 


Clock Input Capacitance 
(61, 62) 


SIGNETICS SILICON GATE MOS 2506, 2507, 2517 


CONDITIONS OF TEST 
Data amplitude +1.05 to +3.2 Input rise and fall times: 10 nsec. Output load is 1 TTL gate. 


TIMING DIAGRAM 


AC CHARACTERISTICS 
Ta = 25°C; Vp = -BV #5%: Veg = +5V (8) ; Vit = —11V 


Frequency Clock Rep Rate 

@ IPW Clock Pulse Width @ 4 
go 2PW Clock Pulse Width ¢ 2 
od Clock Pulse Delay 

tr, tf Clock Pulse Transition 


Data Write Time (Set-Up) 


Data In Overlap trp2 = trp1 = 10S 


Clock to Data Out V¢@=Vcc - 16V, DATA OUT =+2.5V 


Output “High” Voitage Rint = 7.9k nom., Cy = 10pF, 2507 
driving MOS (Note 11) Only, Rit = 20k nom. 2517 only 
Output “High” Voltage Ru =3.3k, Vpp = -5V 

driving TTL (Note 11) 2506 only 


Power Supply Current Outputs @ logic “0” or “1 3MHz, 
(Vpp) @ 1 = 150ns, ¢ 9 = 100ns 


SIGNETICS SILICON GATE MOS 2506, 2507, 2517 


CHARACTERISTIC CURVES 


POWER DISSIPATION PER 
BIT VERSUS FREQUENCY 


CLOCK FREQUENCY (MHz) 


POWER DISSIPATION PER BIT (uW) 


CLOCK FREQUENCY (MHz) 


POWER DISSIPATION BIT 
VERSUS TEMPERATURE 


z a 
3 3 
5 > 
fc 

- rd 
. : 
: : 
; (=) 

NOTE: TEMPERATURE (°C) 


TYPICAL CLOCK FREQUENCY 
VERSUS CLOCK AMPLITUDE 


CLOCK AMPLITUDE (V) 


MINIMUM OPERATING 
CLOCK RATE 


TEMPERATURE (°C) 


Contitions for Typical Curves: Vec=t5V, Vpp=5V. Vv; tem 1V, Pew =150ns, Opw2=1 OOns, f=3MHz, Ty=t25 °C unless otherwise noted. 


APPLICATIONS DATA 
DTL/TTL/MOS INTERFACES 


100-BIT DELAY 


Voc 
a 2506, 2507, 2517 F224] 
_; a 0 = 2p 
INPUT REGISTER 
#1 
LT = PUT 
#2 
>, > 


**3.3K for 2506 
6.8K for 2507 
3.3K for 2517 


U 
ne REGISTER ae 


200-BIT DELAY 


Vec 
eee| 2606, 2507, 2517 
100 BIT 100 
a 0 REGISTER i 
ae, 


at 
fe 


*For 2506 only. 


ot 


SIGNETICS SILICON GATE MOS 2506, 2507, 2517 


CIRCUIT SCHEMATIC 


PO AS Tee. BITS 2 TO 99) 


ooo -oa-4 


SCHEMATIC FOR SECOND 100 BITS SAME AS ABOVE. 


aan % 


100 BITS 


*For 2507 and 2517 Options Only. 


PACKAGE INFORMATION 


V PACKAGE T PACKAGE 


ON a 


NOTES: 
1. Lead Material: Atloy 42 or equivalent, tinned 
Except Surfaces Marked 
2. Body Matertat: Siticone Molded NOTES: 
1. Lead Material: Kovar or equivalent - gotd plated 
2. Body Material: Eyelet, kovar or equivatent - goid 


@) Tolerances Non-Cumuiative 
Dot Denotes Lead #1 plated glass body 

6) Lead Spacing shall be Measured within this Zone 3. Lid Material: Nickel, weid seel 
6. Body Dimensions do not Inctude Motding Fiash 


47 


SiQNGtiCs 


SiNnOtics 


FULLY DECODED, 1024X 1 DYNAMIC 
RANDOM ACCESS MEMORY 


2908 


DESCRIPTION 


The Signetics 2500 Series 1024 X 1 Random Access Memory 
employs enhancement mode P-channel devices integrated on 
a single monolithic chip. The four phase device is fully 
decoded and contains built-in automatic refresh amplifiers. 
Two chip selects allow easy expansion. Dynamic circuitry 
results in low operating power. Several features provide 
direct TTL/DTL interfacing. 


FEATURES 


@ FULLY DECODED ADDRESSING 

@ WRITE/READ CYCLE TIME 480ns TYPICAL 

@ READ ACCESS TIME 270ns TYPICAL 

@ POWER DISSIPATION 100 npW/BIT TYPICAL AT 

480ns CYCLE TIME 

2ms CELL REFRESH TIME 

@ TTL/DTL COMPATIBLE, 2.7mA BARE DRAIN 
OUTPUT 

@ TWO CHIP SELECTS PLUS BARE DRAIN OUTPUT 
FOR EASY EXPANSION é 

@ CLOCK LINE CAPACITANCE ONLY 30pF PER PHASE 

® STANDARD 22—PIN SILICONE PACKAGE 

@ SIGNETICS P—MOS SILICON GATE AND SILICONE 
PACKAGING TECHNOLOGIES 

e Vec= +5V, Vpp= -12V, Vsup= +7V 


APPLICATIONS 


CORE MEMORY REPLACEMENT 
BUFFER STORES 
MAIN MEMORY 


PROCESS TECHNOLOGY 


The use of Signetics’ unique Silicon Gate Low Threshold 
Process allows the design and production of higher perfor- 
mance MOS circuits and provides higher functional density 
ona chip then other MOS technologies. 


BIPOLAR COMPATIBILITY 


All data inputs of the 2508 can be driven directly by stand- 
ard bipolar integrated circuits (TTL, DTL etc.) or by MOS 
circuits. The data output buffer is capable of sourcing a 
minimum of 2.7 mA, sufficient to drive at least one stand- 
ard TTL load. 


49 


SILICON GATE MOS 2500 SERIES 


SILICON PACKAGING 


Low cost silicone DIP packaging is implemented and reli- 

ability is assured by the use of Signetics unique silicon gate 

MOS process technology. Unlike the standard metal gate 

MOS process the silicon material over the gate oxide passi- 

vates the MOS transistors, and the deposited dielectric mater- 
ial over the silicon gate-oxide-substrate structure provides.an 

ion barrier. In addition, Signetics proprietary surface passi- 

vation and silicone packaging techniques result in an MOS 

circuit with inherent high reliability and demonstrating sup- 
erior moisture resistance, mechanical shock and ionic con- 
tamination barriers. 


PIN CONFIGURATION (Top View) 


XC PACKAGE 


. Address 8 

. Address 7 

. Address 6 

. Clock $2 

. Clock py 

. Address 2 

. Address 1 

. Address 5 

. Chip Select 2 
. Chip Select 1 


. Address 9 
. Address 10 
Clock $4 
Clock $3 , 

. Address 4 
Address 3 

. Read/Write 
. Datatn 

. Data Out 


— 


1. 
2 
3 
4. 
5. 
6 
7. 
8 
9 
0 
1. 


_ 


VoD 


PART IDENTIFICATION TABLE 


TYPE PACKAGE OP. TEMP. RANGE 


2508XC 22-Pin 
Silicone DIP 


SIGNETICS SILICON GATE MOS 2508 


MAXIMUM GUARANTEED RATINGS (1) 


0°C to +70°C 
-~65°C to +150°C 
@T ,=70°C 730mW 


Operating Ambient Temperature!2) 
Storage Temperature 
Power Dissipation!2) 


Data and Clock Input 
‘Voltages and Supply 


Voltages with respect to Vag (3) +0.3V to -20V 


NOTES: 


1. Stresses above those listed under ‘‘Maximum Guaranteed Rating” 
may cause permanent damage to the device. This is a stress 
rating only and functional operation of the device at these or at 
any other condition above those indicated in the operational 
sections of this specification is not implied. 

2. For operating at‘elevated temperatures the device must be derated 
based on a+150°C maximum junction temperatu re and a thermal 
resistance of 110° C/W junction to ambient. 

3. All inputs protected against static charge. 

4. Parameter valid over operating temperature range unless otherwise 
specified. 

5. All voltage measurements are referenced to ground. 

6. Manufacturer reserves the right to make design and process 
changes and improvements. 

7. Typical values are at +25°C and nominal supply voltages. 

8. Vec tolerance is +5%. Any variation in actual Vec will be tracked 
directly by Vou Vine and Vou which are stated for a Vec of 
exactly 5 volts. 

9. VoL (for this bare drain device) is a function only of the driven 
gate characteristics together with the external pull-down resistor. 

10. See Figure 2 for definitions. 
11. Logic Convention: Data Lines — Positive; Clocks - Negative. 


DC CHARACTERISTICS 


POWER DISSIPATION PER BIT (uW) 


POWER DISSIPATION/BIT 
VERSUS I/teyc 


03 0.4 0.5 0.8 1.0 2.0 3.0 40 5.0 
Ttcgyc (MHz) 


Ta = 0°C to +70°C; Veg = +5V (8) ; Vpp = -12V 5%; Vgyp = +7V+5% unless otherwise specified. (See notes 4,5,6,7,8, 11) 


SYMBOL TEST 


Output Leakage Current 


Input Low Voltage 


Input High Voltage 


Address Capacitance 


Chip Select Capacitance 


(each phase) 


Data Input Capacitance 


Clock Capacitance 


| 
Cc R/W Read/Write Capacitance 


VIN =Voc f= 1MHz 
Vout =Vec f =1MHz 


SIGNETICS SILICON GATE MOS 2508 


AC CHARACTERISTICS 


TaA= 25°C; Vec = +5V(8); Vpp = -12V 45%; Vsyp = +7V +5% unless. otherwise specified (See notes 4, 5,6, 7, 8, 11) 


TEST TYP MAX UNIT 


CONDITIONS 


SYMBOL 
Clock Rise Time 


Clock Fall Time 
$1 Pulse Width 
$5 Pulse Width 
$3 Pulse Width 
64 Pulse Width 


$4 to dg Gap 


=] 
wn 


Write/Read Cycle Time 480 
tps Data Set Up Time 20 
toH Data Hold Time 
Data Out Access Time See Figure 3 


top Output Preset Time 


trs Row Address Set Up Time | 20 


= 
7) 


try Row Address Hold Time 


tes Column AddressSet UpTime} 20 


tcH Column Address Hold Time 


Chip Select Set UpTime 
Chip Select Hold Time 
Read/Write Set Up Time 
Read/Write Hold Time 
Refresh Time 


tRA Read Access Time 


2 


Oo 
” 


20 


270 


N 
NI 


, nd — 
- o 


Oo 


| Ipp | Vpp Supply Current mA See Figure 5 
VOH Output High Voltage 2 Vv Rpp = 3.3k22 
VOL Output Low Voltage ~1.0 eee oe 


51 


SIGNETICS SILICON GATE MOS 2508 


ACCESS TIME MEASUREMENT 


FIGURE 1 


TIMING DEFINITIONS 


0 —_ an oS ae ow oe oD 


0 i na re =n ray RO 
T 


DATA IN 


a a a ee oe namwmw@eweanm se @eawanm 2B aw ae aw a am oF @ 


DATA OUT 


0 ae on oe oe ow oe oe os od 


NOTE: MEASUREMENTS ARE FROM 10% AND 90% POINTS UNLESS OTHERWISE NOTED 
FIGURE 2 


52 


SIGNETICS SILICON GATE MOS 2508 


BLOCK DIAGRAM 


CS, CS 


512 STORAGE CELLS 
16 ROWS X 32 COLS. 


CHIP 
SELECT 


fee | 32 WRiTE/REFRESH 
AMPLIFIERS 


Ay 

Ag 1 OF 32 

A30 > ROW Ee O DATA 
INVERTERS STAGE 

AgO DECODER OUT 

As O 


Seba nes 
COLUMN DECODER 
li 32 WRITE/REFRESH 

AMPLIFIERS 


512 STORAGE CELLS 
16 ROWS X 32 COL. 


FIGURE 3 


TIMING DIAGRAM 


CYCLE 
TIME 


"ROW ADDRESS STABLE 


COLUMN ADDRESS STABLE 
CHIP CHIP 
SELECT SELECT STABLE 


me =< 
WRITE 


DATA IN DATA IN STABLE 


PRE Ses age gt ee ee ee Ee SP ye re oe ee ae 


DATA OUT 4 tad 
qnwaeampeeamea@@ee@= ae a=aeenp a= a= = as 


240 400 480 


TIME SCALE (ns) ty= ty<50ns FOR CLOCKS 
FIGURE 4 


53 


SIGNETICS SILICON GATE MOS 2508 


CHARACTERISTIC CURVES 


READ ACCESS TIME READ ACCESS TIME 
VERSUS CLOCK AMPLITUDE VERSUS TEMPERATURE 


Tra (ns) 


Ve- Vcc (VOLTS) TEMPERATURE (°C) 


POWER DISSIPATION 


lout VERSUS Vout VERSUS TEMPERATURE 
120 
110 
= 
3 
= e 100 
3 Z 
s 7 90 
3 
5 
80 
0 
0 10 20 30 40 i) 60 70 
Vout (VOLTS) TEMPERATURE (°C) 


NOTE: Vss= +7V 
Vec= +5V T a= 25°C except as noted 
Vop =-12V CLOCKS (see Figure 4) 


54 


DEVICE OPERATION 


To understand the operation of the 2508, refer to Figures 
2, 3, and 7. The 2508 is a 4-phase Dynamic Random Access 
Memory fully decoded on the chip and has built-in refresh 
amplifiers to allow automatic refreshing of the dynamic 
memory. 


ORGANIZATION 


The 2508 is organized as two 512X1 arrays of storage cells 
each in a 16 row by 32 column format. The two arrays are 
combined into a single 1024X1 configuration through the 
write/refresh amplifiers and the output circuit. Addresses 
A 1 through Ag select one of 32 rows and Ag through A109 


select one of 32 columns. The 1 of 32 column decoder 
drives 64 write/refresh amplifiers. Two chip selects plus 
a bare drain output device allow tying of many devices for 
the formation of large memory arrays. 


MEMORY CELL 


The memory cell consists of three devices. The storage 
mechanism consists basically of the storage of charge ona 
capacitor - the gate of one of the three devices. The high 
impedance of the gate prevents the charge from leaking. 
A second device in the cel! is used as a series switch through 
which charge passes to the gate of the storage node during 
the write or refresh cycles. The third device is connected 
to the drain of the storage transistor. During the read cycle, 
this device is turned on. Since it is in series with the storage 
device, the two in series provide a path to Vcc if the gate 
of the memory device is storing charge. If it isnot, no path 
will exist. The stored information is identified by whether 
or not a path to V¢c¢ exists. 


REFRESH AMPLIFIER 


The refresh amplifier is used to refresh the stored charge 
in the memory cell (following a read operation) or to write 
new information (during a write operation). Each refresh 
amplifier is connected to 16 memory cells. During phase 
3, the refresh amplifier is precharged. At the same time 
the output is displaying the stored information. During 
the next phase ($4), the memory cell is refreshed. 


WRITE CYCLE 


The following significant events occur during the write cycle: 


SIGNETICS SILICON GATE MOS 2508 


$4 - Row and column addresses change. 

$ 4— The common read/write node in the array is precharged. 

$2 -The output buffer is precharged, and the storage node 
is read. 


$3 - The common read/write node is again precharged. 
$4 ~ New information is written into the cell. 


READ CYCLE 


The same events as those listed above occur during the 
phases except the cell is refreshed during ¢4 and the stored 
information becomes available on the trailing edge of $5. 


ACCESS TIME 


Read access time is measured from the 10% point of the 
trailing edge of $4 to the appearance of stored information 
following $2. Typical access times are 270 ns. 


CHARACTERISTICS 
The 2508 is characterized by the following qualities: 


REFRESHING 


Since the 2508 employs a dynamic storage system, it re- 
quires periodic refreshing of data. Automatic refreshing is 
provided on the chip. Refreshing of the entire chip requires 
cycling through the 36 row address at least every 2 ms. With 
a 500 ns refresh cycle time, the memory is available 99.2% 
of the time. Read out of the memory is non-destructive and 
serves to automatically refresh the stored information. 


BIPOLAR COMPATIBILITY 


The 2508 is TTL/DTL compatible for all signals in and out 
with the exception of clock levels which are required to 
swing 17V. The 2508 bare drain output will source 2.7 mA 
to facilitate interfacing to TTL/DTL. 


POWER DISSIPATION 


The use of dynamic addressing and refreshing dramatically 
reduces system power compared to other organizations. 


SIGNETICS SILICON GATE MOS 2508 


CLOCK GENERATOR 


Vec Qa Qg Qc Qp 


CLOCK IN 
OO) 


(25 MHz) 


FIGURE 5 


FIGURE 6 


4g 


Ag 


Ag $1 ¢2 $3 
4 


$1 CS¢2 


DATA OUT 


to qs2 

= o4 64 
De a 
02 ; Ww 


FIGURE 7 


WVYSVIC OILVINAHOS 


80SZ SOW 3LV9 NOOITIS SOLLANDIS 


SIGNETICS SILICON GATE MOS 2508 


PACKAGE INFORMATION 


XC PACKAGE 


SINCtES ; 


Sintties 


DESCRIPTION 


These Signetics 2500 Series Dual 50, 100, and 200 bit recir- 
culating static shift registers consist of enhancement mode 
P-channel silicon gate MOS devices integrated on a single 
monolithic chip. Internal recirculation logic plus TTL/DTL 
level clock signals plus TRI-STATE outputs are provided for 
maximum interfacing capability. 


FEATURES 


@ TRI-STATE MOS OUTPUTS - PROVIDE POWERFUL 
BUSSING CAPABILITY 

@ TTL/DTL COMPATIBLE CLOCKS - PROVIDE 

EXTREMELY LOW CLOCK CAPACITANCE 

RECIRCULATION PATH ON CHIP 

THREE BIT LENGTHS AVAILABLE 

HIGH FREQUENCY OPERATION 

2MHz GUARANTEED CLOCK RATE 

TTL, DTL COMPATIBLE SIGNALS 

STANDARD PACKAGES - 10 LEAD TO-100, 14 PIN 

DIP 

SIGNETICS P-MOS SILICON GATE PROCESS 

TECHNOLOGY 


APPLICATIONS 


LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST STATIC BUFFER MEMORIES 
CRT REFRESH MEMORIES - LINE STORAGE 


SPECIAL FEATURES 


The three clock phases used by the register cells are gen- 
erated internally by an on-chip generator. This clock gen- 
erator is controlled by a single TTL/DTL 5V logic level 
input. 


The output has three states: 
“‘1"" low impedance to +5V 
“O" low impedance to -5V 
“OFF” high impedance ~ 10 M ohm 
The “OFF”’ state is controlledby the Output Enablecontrol 
input. 


PROCESS TECHNOLOGY 


Use of low threshold silicon gate technology allows high 
speed (2 MHz Guaranteed) while reducing power dissipation 
and clock input capacitance dramatically as compared to 
conventional technologies. 


The use of low voltage circuitry minimizes power dissipation | 


and facilitates interfacing with bipolar integrated circuits. 


TRI-STATE OUTPUT DUAL 590-100-200 
BIT STATIC SHIFT REGISTERS 


59 


SILICON GATE MOS 2000 SERIES 


2908 
2910 
2011 


BIPOLAR COMPATIBILITY 


The clock and signal inputs of these registers can be driven 
directly by standard bipolar integrated (TTL, DTL, etc.) 
or by MOS circuits. The TRI-STATE output stage provides 
driving capability for both MOS and bipolar integrated 
circuits (one standard TTL load). 


PIN CONFIGURATIONS (Top View) 


A PACKAGE 


. Recirculate Vec 


» IN, IN, 
4 OUT, : OUT, 
. NC ~ nc 
. N 
c - Veg 


. NC . Output Enable 


- OIN 


. Vop 


K PACKAGE 


IN, 

OUT, 

Vop 

@IN 

Vec 

Output Enable 
V6c 

OUT, 

. Recirculate 


POMANDRAAHN = 


PART IDENTIFICATION TABLE 


PART 
NUMBER BIT LENGTH PACKAGE 


10 Pin, TO-100 


Dual 50 

Dual 50 14 Pin, DIP 
Dual 100 10 Pin, TO-100 
Dual 100 14 Pin, DIP 
Dual 200 10 Pin, TO-100 
Dual 200 14 Pin, DIP 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


MAXIMUM GUARANTEED RATINGS (1) 


Operating Ambient Temperature (2) 0°C to +70°C 
Storage Temperature ~65°C to +150°C 


Package Power Dissipation(A & K) 
(Note 2) @T, = 70°C 535mW 


Data and Clock Input Voltages 
and Supply Voltages with 
respect to Vcc (3) +0.3V to -20V 


BLOCK DIAGRAM 


O RECIRCULATE 


NOTES: 


1: If output enable = ‘’0"’, output is ‘‘off’’. 


NOTES: 


1. 


N BIT REGISTER 


2: If output enable = ‘’1’’, see Truth Tahle 


TRUTH TABLE: 


RECIRCULATE INPUT FUNCTION 


60 


Stresses above those listed under ‘‘Maximum Guaranteed Rating” 
may cause permanent damage to the device. This is a stress rating 
only and functional! operation of the device at these or at any 
other condition above those indicated in the operational sections 
of this specification is not implied. 

For operating at elevated temperatures the device must be 
derated based on a +150°C maximum junction temperature and 
a thermal resistance of 150°C/W. 

All inputs are protected against static charge. 

Parameters are valid over operating temperature range unless 
otherwise specified. 

All voltage measurements are referenced to ground. 
Manufacturer reserves the right to make design and process 
changes and improvements. 

Typical values are at +25°C and nomimal supply voltages, 

Vec tolerance is +5%. Any variation in actual Vec will be 
tracked directly by Vv) L: Vin and Von which are stated for 

a Vec of exactly 5 volts. 


Outy 


Out2 


Recirculate 


Recirculate 


“O” is Written 


“4° is Written 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


DC CHARACTERISTICS 
Ta = 0°C to +70°C; Vcc = t5V (8); Vpp = ~5V £5%; VGG = -12V +5% unless otherwise noted. (Notes 4,5,6,7) 


SYMBOL TEST oe UNIT CONDITIONS 


Vin =-5.5V, Ta = 25°C 
Vog =1.05V,Ta = 25°C, Voyt = 
-5V 
Vic = GND, Ty = 25°C 


Input Load Current 


Output Leakage Current 


Clock Leakage Current 


Power Supply Current 
(Dual 50) 
(Dual 100) 
(Dua! 200) 


Continuous Operation 
F = 2MHz, Ta = 25°C 


Power Supply Current 
Input “Low” Voltage 
Input “High” Voltage 
Clock Input ‘‘Low’”’ Voltage 


Clock Input “High’’ Voltage 


TIMING DIAGRAM 


tt a_i |<— 


OUTPUT 
ENABLE 9 


61 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


AC CHARACTERISTICS 
Ta = 28°C, Voc =+5V (8); Vp = -5V 45%; Vitc = +0.4V to 4V; Vag = -12V 45%. 


SYMBOL TEST ee ee UNIT CONDITIONS 


Frequency Clock Rep Rate 
to Pw Clock Pulse Width 
to PW Clock Pulse Width 


ty: tf Clock Pulse Transition 


tow Data Write (Set-up) Time 


tpH Data to Clock Hold Time 
tat: tg- Clock to Data Out Delay 
t- Clock to Recirculate 
tog-s test Output Enable to Data Out 
Output Enable to Data Out 
t 
ME Disconnect 
@1MHz; Vin = Vec: 
Cin Input Capacitance ee 
VAC = 25mV p-p 


@ 1 MHz; Vout = Vcc: VAC = 
Output Capacitance 
25mV p-p 


@ 1 MHz; Va =Vec; Vac = 
Clock Capacitance ¢ ecia oe 
25mV p-p 
Output “Low’’ Voltage F 2 TTL load |; =3.2mA 
Output “High” Voltage 
2 TTL load (I; = 100uA) 
Driving 2 TTL Load 
Output “High” Voltage 
Driving MOS 


TIMING DIAGRAM 


NOTE 1: WRITE CYCLE 


The positive going edge of the 
ory eiy2 airs ere Orr s wTe eit? site | sire | arse avrss me BIT 13 recireulate control is coincident 
with the negative going edge of 


). The out 


INPUT al the input clock (@ijy 
aokwmweos LU LU UU i uiiu iiou iu ui put enable contro! may be either 


“4 or 
+8V 7 | 
DATA IN i 


control is a ‘0’ the ae enable 


DATA 
oataour “SV | GAYA loura paral Gata NOTE 2: RECIRCULATE CYCLE 
outs ouTé 
| may be either ‘1’ or ‘ 


ty l Data recirculates if the recirculate 


+6V 
RECIACULATE 9, J re ear cee 22 EE 


OUTPUT  +5V 
ENABLE NOTE 3: READ CYCLE 


The negative going edge of the 

output enable control is coincident 

with the positive edge of the clock 

{O1Nn)- Recirculate may be either 
“0”. 


62 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


APPLICATIONS INFORMATION 


TTL/DTL/MOS INTERFACES 


2610 
2511 


NOTES: 
1. Register used as a recirculating register. 
2. Register used as serial in/serial out shift register. 


MULTIPLEXING MEMORY REGISTERS AT 4MHz DATA RATE 


2509/10/11 
2509/10/11 5 


mec 


63 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


CHARACTERISTIC CURVES 


POWER DISSIPATION/BIT VERSUS 
Vpp SUPPLY VOLTAGE 


POWER DISSIPATION/BIT (mW/B!IT) 


Vop - Veg (Volts) 


POWER DISSIPATION/BIT (mW/BIT) 


OUTPUT VOLTAGE VERSUS 
OUTPUT CURRENT 


OUTPUT CURRENT (mA) 


5 4 3 2 A 


OUTPUT VOLTAGE (VOLTS) 


Igg CURRENT VERSUS 
VgG SUPPLY VOLTAGE 


+ 
o> 
on 
wn 
oO 
Zo 


PELL 
LETT N | 
TLE 


TONITE 
SESENE 
SHORE 


VoGG - Vcc (Volts) 


POWER DISSIPATION/BIT 
VERSUS TEMPERATURE 


TTT TPT 
Seen aRee 
Eee ieee a! 


TEMPERATURE (°C) 


MAXIMUM FREQUENCY VERSUS 
Vgq SUPPLY VOLTAGE 


MAXIMUM FREQUENCY (MHz) 


Ve SUPPLY VOLTAGE (VOLTS) 


64 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


CHARACTERISTIC CURVES (Cont’d.) 


Igg CURRENT PACKAGE MAXIMUM 
VERSUS TEMPERATURE POWER DISSIPATION 


8 


igg CURRENT (mA) 


GA peRree 


MAXIMUM POWER DISSIPATION (mW) 


x 
3 


vie 


tia | 
Peas 


LUT 
EE 
£ 


10 20 ww 40 50 60 


TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) 


SCHEMATIC DIAGRAM 


OUTPUT 
ENABLE 
OUTPUT STAGE 


SIGNETICS SILICON GATE MOS 2509, 2510, 2511 


PACKAGE INFORMATION 


A PACKAGE K PACKAGE 


325 
316 


DIA 
030 
ee 
045 
| Bisnsveaton 
ae} 
| 019 


16 OIA 
10 LEADS 
es 


1, Lead Material: Alloy 42 or equivaient 1. Lead Materiat Kovar or Equivalent - Gold Plated 
2. Body Material: Silicone moided 2. Body Matenal Eyelet, Kovar or Equivalent - Gold 


Plated Giass Body 
3. Mi i, Wet 
Signetics symbol d tes Leed #1 Lid Maternal Nickel, Wetd Seal 


Lead spacing shall be measured within this zone 
6. Body dimensions do not include molding flash 


8 Tolerances non cumulative 


SiNCtics 


66 


a g HIGH SPEED 64X 7X5 CHARACTER GENERATOR 
SiNGTES | 912 X 5 STATIC READ-ONLY MEMORY 


DESCRIPTION 


The Signetics 2513/2514 is a high speed 2560-bit Static 
ROM available in 64X7X5, 64X8X5, and 512X5 versions. 
The product uses +5V, -5V and -12V power supplies, 5V 
TTL level input signals and Tri-State-Outputs for direct, low 
cost interfacing with TTL, DTL and 2500 Series MOS. 


FEATURES 


@ 450 ns TYPICAL ACCESS TIME 

STATIC OPERATION 

TTL/DTL COMPATIBLE INPUTS 

+5, -5, -12V POWER SUPPLIES 

TRI-STATE OUTPUT CONTROLLED BY CHIP 
ENABLE FOR POWERFUL BUSSING CAPABILITY 
2513/CM2140 ASCII FONT STANDARD (7 X 5) 
2514 SEPARATE Vpp FOR POWER REDUCTION 


e 

e 

@ 24-PIN SILICONE DIP 

@ SIGNETICS P-MOS SILICON GATE PROCESS 
TECHNOLOGY 


APPLICATIONS 


RASTER SCAN CRT DISPLAYS (ROW OUTPUT) 
PRINTER CHARACTER GENERATOR 

PANEL DISPLAYS AND BILLBOARDS 
MiCRO-PROGRAMMING 

CODE CONVERSION 


PROCESS TECHNOLOGY 


The use of Signetics’ unique Silicon Gate Low Threshold 
Process allows the design and production of higher func- 
tional density and operating speed than other techniques. 


SILICONE PACKAGING 


Low cost silicone DIP packaging is implemented and reli- 
ability is assured by the use of Signetics unique silicon gate 
MOS process technology. Unlike the standard metal gate 
MOS process the silicon material over the gate oxide passi- 
vates the MOS transistors. In addition, Signetics proprietary 
surface passivation and silicone packaging techniques result 
in an MOS circuit with inherent high reliability, superior 
moisture resistance, and ionic contamination barriers. For 
further information reference Signetics - ‘Silicone Package 
Qualification Report” 


BIPOLAR COMPATIBILITY 


All inputs of the 2513/14 can be driven directly by stand- 
ard bipolar integrated circuits (TTL, DTL, etc). The data 
output buffers are capable of sinking a minimum of 1.6 mA, 
sufficient to drive one standard TTL load. 


67 


2913 
2914 


SILICON GATE MOS 2500 SERIES 


PIN CONFIGURATION (Top View) 


- Vec 

NC 
. Address 9 
. Address 8 
. Address 7 
. Address 6 
. Address 5 
. Address 4 
. Address 3 
. Address 2 
. Address 1 
. NC 


OM OTPWN = 


= = (6 
=O 


. Chip Enable 
- Vop 


= 
N 


- Vee 
- NC 


. Address 9 
. Address 8 
. Address 7 
. Address 6 
- Address 5 
. Address 4 
- Address 3 
. Address 2 
. Address 1 
. NC 


1. 
2. 
3. 
4. 
5. 
6. 
7. 
8. 
9. 


PART IDENTIFICATION TABLE 


PART ORGANIZATION PROGRAMMING 


CM2140 | 64X8X5 ASCII Font 
2513NX/ | 64X7X5 

CMXXXX | 64X8X5 Custom * 
2514NX/ 

CMXXXxX | 512X5 Custom * 


*Ask for ‘Signetics 2513/2514 Read Only Memory Software Package’ 


SIGNETICS SILICON GATE MOS 2513/2514 


CHARACTER FORMAT 


ROW 
ADDRESS 


Og % O03 92 0; 


EXAMPLE ‘S' 


CHARACTER 
ADDRESS 


ASCII 
CHARACTER 


DC CHARACTERISTICS 


MAXIMUM GUARANTEED RATINGS(1) 


Operating Ambient Temperature 0°C to 70°C 
Storage Temperature -65°C to +150°C 
Package Power Dissipation(2) @T , 70°C 730mW 
Input(3) and Supply Voltages 

with respect to Vcc +0.3 to-20V 


NOTES: 


. Stresses above those listed under ‘‘Maximum Guaranteed Rating” 


may cause permanent damage to the device. This is a stress rating 
only and functional operation of the device at these or at any 
other condition above those indicated in the operational! sections 
of this specification is not implied. 


. For operating at elevated temperatures the device must be 


derated based on a +150°C maximum junction temperature and 
a thermal resistance of 110°C/W junction to ambient, 


. All inputs are protected against static charge. 
. Parameters are valid over operating temperature range unless 


specified. 


. Alt voltage measurements are referenced to ground. 
. Manufacturer reserves the right to make design and process 


changes and improvements. 


. Typical values are at +25°C and nominal supply voltages. 
. Vee tolerance is +5%. Any variation in actual Vec will be 


tracked directly by vi L: Vin and Vou which are stated for 
a Vec of exactly 5 voits. 


TA = 0°C to +70°C; Veco =t5V (8); Vop =5V; VGG = -12V £5% unless otherwise noted. (Notes 4, 5, 6, 7) 


SYMBOL TEST 


Input Load Current 


Output Leakage Current 
pp Vpp Power Supply Current 


VGG Power Supply Current 


Input Logic “0” 
Input Logic “1” 


CONDITIONS 


VIN = -5.5V 
Ta = 25°C 


SIGNETICS SILICON GATE MOS 2513/2514 


AC CHARACTERISTICS 
TA= 25°C; Vcc = SV (8) ; Vpp =5V £5%; Vgg = -12V £5%; unless otherwise noted. 


[—srwson [esr Tm [nx or [ conorons 


VOL Output Logic “Zero” One TTL Load 


VOH Output Logic “One’’ . One TTL Load 


tCA retin Character Access Time See AC Test Setup 


toa (2514) Access Time (Aq - Ag) See AC Test Setup 
tRA Row Access Time (Ay - A3) See AC Test Setup 
tCE Chip Enable to Output 


Cin Address Input Capacitance ie 1 ee ; 
CC: 


BLOCK DIAGRAM 


ra O Ag 
vo] Fy | gf 
Be. cee 
Yopo MEMORY MATRIX s OA? 
(2560 BITS) <@ . 
Vv re Ag 
DD2 © oe 
(2514 only) ° O Ag 


: eae 
we ROW Aa 
ADDRESS DECODER 
ee Raa 


ee | ourrur] 
| o | pata | 
Pt [oren | 


SIGNETICS SILICON GATE MOS 2513/2514 


AC TEST SETUP 


Vec 
Any 2513/14 Oy 


* 
Vpp “pp2%GG CE 


* (2514 only) 


TIMING DIAGRAM (ADDRESS TIME) 


3.0V 
CHARACTER ADDRESS 
(Ag-Ag) ; 


' 
\ 
1 
{ 
| 
' 
' 
I 
| 
! 
' 
! 


3.0V 
OUTPUT 
(04-05) a oe @ 


t 
| 
{ 
| 
Was & ton 45-0 


ton Character Access Time 


tax Row Access Time 


70 


SIGNETICS SILICON GATE MOS 2513/2514 
CHARACTERISTIC CURVES 


Vpp POWER SUPPLY CURRENT Vpp POWER SUPPLY CURRENT 
VERSUS VOLTAGE VERSUS TEMPERATURE 


Ipp (mA) 


'poima) 


id 
me 
Lt 
a 
a 
= 
Ew 


ERRREENE 


TEMPERATURE (°C 
Vec-Voo (V) soe 


Vgcq POWER SUPPLY CURRENT Vgcq POWER SUPPLY CURRENT 
VERSUS VOLTAGE VERSUS TEMPERATURE 


Li ALT TT 
tI TT 
Litt RET 


Vcec-VYee (Vv) TEMPERATURE (°C) 


TYPICAL ACCESS TIME MAXIMUM PACKAGE 
VERSUS TEMPERATURE POWER DISSIPATION 


ACCESS TIME (ns) 
MAXIMUM PACKAGE POWER DISSIPATION (mW) 


TEMPERATURE (°C) TEMPERATURE(°C} 


71 


SIGNETICS SILICON GATE MOS 2513/2514 


APPLICATIONS INFORMATION 


CRT DISPLAY MEMORY AND CHARACTER GENERATOR 


TO CRT “2” AXIS 


* 512 BIT 
CONTROL 


CONTROL ONTRC 
ed (TTL) 


LOGIC 
(TTL) 
* 512 BIT 
O 
-5V CLOCK 


RECIRCULATE 
AND LOAD 
CONTROL 


NOTE: *512 or 1024 Bit Shift Registers (2503, 2504, 2505, 2512) 


** or Hex 64 BIT Two 2518's 
Hex 72 BIT 2518 + 2519’s 


DTL/TTL INTERFACING 


*2514 only 


72 


BABCOEE 
HIJEL AH! 
FORS TUM 


a i i r F Fi ‘ 7 
ea jee 
BiZSs567 
SqGGRRae 


SIGNETICS SILICON GATE MOS 2513/2514 


CIRCUIT SCHEMATIC 


CHARACTER (8 lines) 512 BIT OUTPUT 


DECODERS (64) MEMORY (5) BUFFER (5) 


10f8 ceO-| CHIP ENABLE 
DECODER INV. (1) 
Vec 


Voc O 
(8) ROW 
INV. (3) : DECODERS ! 


PACKAGE INFORMATION 


“NX" PACKAGE 


WHEN FORMED PARALLEL 


100 ¢ TO $45 
t t 7} 4 560 


065 
08s 


030 - | 
Ti 


NOTE 3 


NOTES: 


1. Lead material: Kovar, solder coated. 

2. Body material: Silicone molded. 

3. Tolerances non-cumulative. 

4. Lead spacing shall be measured within this zone. 
5. Body dimensions do not include molding flash. 
6. Signetics symboi denotes lead No. 1. 


SiNCtES : 


SINNOties 


HIGH SPEED 64X6X8 STATIC 
CHARACTER GENERATOR 


2916 


DESCRIPTION 


The Signetics 2516 is a high speed 3072-bit Static ROM 
available in a 64 x 6 x 8 organization. The product uses +5V, 
~5V and -12V power supplies, 5V TTL level input signals 
and Tri-State-Outputs for direct, low cost interfacing with 
TTL, DTL and 2500 Series MOS. 


FEATURES 


COLUMN OUTPUT 

450 ns TYPICAL ACCESS TIME 

STATIC OPERATION 

TTL/DTL COMPATIBLE INPUTS 

+5, -5, -12V POWER SUPPLIES 

TRI-STATE OUTPUT CONTROLLED BY CHIP 

ENABLE FOR POWERFUL BUSSING CAPABILITY 

@ 2516/CM 2150 ASCII FONT STANDARD (5 x 7) 

@ OPTIONAL SEPARATE OUTPUT Vpp FOR POWER 
REDUCTION 

@ OPTIONAL CHIP ENABLE “2” FOR 4 BIT WORD 
ORGANIZATION 

@ 24-PIN SILICONE DIP 

@ SIGNETICS P-MOS SILICON GATE PROCESS 

TECHNOLOGY 


APPLICATIONS 


VERTICAL SCAN CRT DISPLAYS (COLUMN OUTPUT) 
PRINTER CHARACTER GENERATOR 

PANEL DISPLAYS AND BILLBOARDS 
MICRO-PROGRAMMING 

CODE CONVERSION 


PROCESS TECHNOLOGY 


The use of Signetics’ unique Silicon Gate Low Threshold 
Process allows the design and production of higher func- 
tional density and operating speed than other techniques. 


BIPOLAR COMPATIBILITY 


All inputs of the 2516 can be driven directly by standard 
bipolar integrated circuits (TTL, DTL, etc.). The data out- 
put buffers are capable of sinking a minimum of 1.6mA, 
sufficient to drive one standard TTL load. | 


75 


SILICON GATE MOS 2500 SERIES 


SILICONE PACKAGING 


Low cost silicone DIP packaging is implemented and reli- 
ability is assured by the use of Signetics unique silicon gate 
MOS process technology. Unlike the standard metal gate 
MOS process the silicon material over the gate oxide passi- 
vates the MOS transistors. In addition, Signetics proprietary 
surface passivation and silicone packaging techniques result 
in an MOS circuit with inherent high reliability, superior 
moisture resistance, and ionic contamination barriers. For 
further information reference Signetics - ‘’Silicone Package 
Qualification Report.” 


PIN CONFIGURATION (Top View) 


NX PACKAGE 


Chip Enable 2 

NC - V6c6 

Output 8 . Address 9 

Output 7 . Address 8 

Output 6 . Address 7 

Output 5 . Address 6 
. Address 5 
. Address 4 
. Address 3 
. Address 2 
. Address 1 
. Chip Enable 2* 


1. 
2. 
3, 
4. 
5. 
6. 
7. 
8. 
9. 


* Optional on all custom ROMs (NC on CM 2150) 


SIGNETICS SILICON GATE MOS 2516 
PART IDENTIFICATION TABLE 


PART ORGANIZATION 


2516NX 64x6x8 
CM 2150 


PROGRAMMING 


ASCII Font 


2516NX 
CMXXXX 


Custom* 


“Ask for “Signetics 2516 Read-Only -Memory Software Package”’ 
(See Section 6) 


CHARACTER FORMAT 


eee ooooodno 
couume Pelolol [ayo o 
mg 


EXAMPLE “S” 
CHARACTER ADDRESS 


DC CHARACTERISTICS 


MAXIMUM GUARANTEED RATINGS (1) 


Operating Ambient Temperature 0°C to 70°C 
Storage Temperature -65°C to +150°C 
Package Power Dissipation (2) 
@ 70°C 730 mW 
Input!) and Supply Voltages 
with respect to Voc +0.3 to -20V 


NOTES: 


1. Stresses above those listed under ’‘Maximum Guaranteed Rating’ 
may cause permanent damage to the device. This isa stress rating 
only and functional operation of the device at these or any other 
conditions above those indicated in the Speractonal sections of 
this specification is not implied. 

2. For operating at glevated temperatures the device must be derated 
based ona +150 C maximum junction temperature and a thermal 
resistance of 110°C/W junction to ambient. 

3. All inputs are protected against static charge. 

4. Parameters are valid over operating temperature range unless 
specified. 

5. All voltage measurements are referenced to ground. 

6. Manufacturer reserves the right to make design and process 
changes and improvements. 

7. Typical values are at +25°C and nominal supply voltages, 

8. Vec tolerance is 5%. Any variation in actual Vec will be 
tracked directly by Vin Vip and Von which are stated fora 
Vee of exactly 5 volts. 


Ta =0°C to +70°C; Ver = +5V; Vin =-5V 5%; Vac = -12V +5%; unless otherwise noted. (Notes 4, 5, 6, 7) 
A CC DD GG 


Input Load Current 


Output Leakage Current 


Vpp Power Supply Current 


VGG Power Supply Current 
Input Logic “0” 


Input Logic 


nq ve 


76 


Vin = -5.5V 
Ta= 25°C 


VouT = -9.5V 
Ta = 25°C 
Vce = Yec 
Outputs Open 
Outputs Open 


SIGNETICS SILICON GATE MOS 2516 


AC CHARACTERISTICS 
Ty = 28°C;Vec= 5V'8):Vpp =-5V +5%; Vgg = -12V £5%:; unless otherwise noted. 


VOL 8 V 


Output Logic ‘’Zero”’ 0 
VOH V 
500 600 ns 
400 500 ns 
10 pF 


CONDITIONS 


One TTL Load 
One TTL Load 


See AC Test Setup” 
See AC Test Setup* 
f = 1MHz, Vin = 
Vcc, 25mV p-p 


Output Logic “One” 


Character Access Time 
Column Access Time (Ay - A3) 
Address Input Capacitance 


*T,=0°C to +70°C 


CIRCUIT SCHEMATIC 


t 
' 
! 
! 
‘ 
t 
' 
' 
ot 
O ! 
OUTPUT ! 
01-08 | 
t ! 
be 
i 
' 
! ' 
1 ! y ' 
\ ! ' | 
1 CHARACTER ==! jo) |384BIT OUTPUT 
INV. (5) 1 INV.(5) | DECODERS (64) | MEMORY (8)! BUFFER (8)! 
neg soaker ere rey neaiagac Loto cees enced sae wneee em meee e oe seecco eee 
' 


1 
t 
t 
1 
' 
: i} 
} 
1 
Ai--A ' 
1 ATA 
o—- 1 of 6 ' CeO CHIP ENABLE 
: DECODER | 1 INV. (1) 
| ke ! Vcc 
j 1 
i} i 
1 Veco ' 
| i 
| \ 
u 


* OPERATIONAL 


77. 


SIGNETICS SILICON GATE MOS 2516 


BLOCK DIAGRAM 


0492 030,05 Og O7 Og 


TH OUTPUT BUFFERS 


MEMORY MATRIX en 
(3072 BITS) 
COLUMN 
ADDRESS DECODER 


CHARACTER 


« 
Ww 
ra) 
° 
Oo 
rt) 
Q 
” 
4) 
wi 
a 
ra) 
Q 
zt 


Note: For 4-Bit organization 
Chip Enable 1 controls 
0, — 04, Chip Enable 
2 controls 05 - Og. 


AC TEST SETUP 


Vec 
An 2516 Om 


Vpp Ypp2‘cc cE 


vi CHARACTER ADDRESS 
(Ag-Ag) 


Vv 
 (Ay-Ag) 


y, OUTPUT 
9 (0,— 09) 


toa=CHARACTER ACCESS TIME 
tc_a=COLUMN ACCESS TIME 


78 


SIGNETICS SILICON GATE MOS 2516 


APPLICATIONS INFORMATION 


DTL/TTL INTERFACING 


*OPTIONAL 


CRT DISPLAY MEMORY AND CHARACTER GENERATOR 


DATA 


OUTPUT | | | 


ZAXIS POSITIVE 
O 


BRIGHT UP 


ADDRESS 
SELECTION 


O 
NEGATIVE 


CHANNEL 1 
CHARACTER DISPLAY 


ALTERNATE SCAN 


CHANNEL 2 
WAVEFORM DISPLAY 


79 


SIGNETICS SILICON GATE MOS 2516 


CHARACTERISTIC CURVES 
Vpp POWER SUPPLY CURRENT Vpp POWER SUPPLY CURRENT 
VERSUS VOLTAGE VERSUS TEMPERATURE 


Ipp (mA) 
Ipp (mA) 


Vec~ Yoo (Vv) TEMPERATURE (°C) 


VGgG POWER SUPPLY CURRENT | VGG POWER SUPPLY CURRENT 
VERSUS VOLTAGE VERSUS TEMPERATURE 


Igq (mA) 
leg (mA) 


Vec~ Veg (V) TEMPERATURE (°C) 


TYPICAL ACCESS TIME MAXIMUM PACKAGE POWER DISSIPATION 
VERSUS TEMPERATURE VERSUS TEMPERATURE 


ACCESS TIME (ns) 
MAXIMUM PACKAGE POWER DISSIPATION (mW) 


TEMPERATURE (°C) TEMPERATURE(°C) 


80 


PORSTUNM 
AB IERU 


PE RIRERIEE 
CARE GELE 
Hi Zgidsie 
ee eee 


SIGNETICS SILICON GATE MOS 2516 


APPLICATIONS DATA: PACKAGE INFORMATION 


OUTPUT INTERFACING NOTES NX PACKAGE 


The tri-state outputs on this device exhibit three states: 


“1'" — low impedance to +5V 
“0"" — low impedance to -5V 


OFF — _ high impedance = 10 megohm 


The “off” state is controlled by the chip enable control inputs. 


WHEN FORMED PARALLEL 


CUSTOM ROM ORGANIZATIONS 


The 2516 is a static ROM with a total 64 x 6 x 8 bit 

capacity. This allows a standard 5 x 7 font to be encoded in ap OISMAX. 
the ROM, eg., the 2516/CM2150 ASCII font standard 8 to L348 
product. Also custom coding of up to 6 x 8 character bias 
generators, also 256 x 8, 384 x 8, or 768 x 4 ROMs are 
available using Signetics ‘2516 Read Only Memory Software 


Package.”’ 


NOTES: 
For applications requiring a 708 x 4 organization, CHIP 1, Lead material: Kovar, solder coated. 
ENABLE HIP E e d | 2. Body material: Silicone molded. 
LE and C NABLE 2 are used to control outputs } Tolerances Hon-clanuletive: 
ue = j 4, Lead spacing shall be measured within this zone. 
1 ? and 5 8 respectively. The outputs are externally hard m cay saveruises de nat inciade wakling fade 
wired in pairs for this organization. 6. Signetics symbol denotes lead No. 1. 


Custom versions of the 2516 can be supplied with a separate 
Vpp supply terminal for the output buffer. This feature 
permits operation at reduced power dissipation. 


SMES = =——eess—<(i‘swswsSSSSS 


82 


SiHNCtiES 


DESCRIPTION 


These Signetics 2500 Series Hex 32 and 40-bit recirculating 
static shift registers consists of enhancement mode P-channel 
silicon gate MOS devices integrated on a single monolithic 
chip. Internal recirculation logic plus TTL/DTL level clock 
signals are provided for maximum interfacing capability. 


FEATURES 


@ TYPICAL CLOCK AND DATA RATE = 3MHz 

@ TTL/DTL COMPATIBLE CLOCK (SINGLE) PROVIDES 
EXTREMELY LOW CLOCK CAPACITANCE 
RECIRCULATION PATH ON CHIP 

TWO BIT LENGTHS AVAILABLE 

SINGLE-ENDED (BARE DRAIN) BUFFERS 

TTL, DTL COMPATIBLE SIGNALS 

STANDARD PACKAGE — 16 PIN SILICONE DIP 
SIGNETICS P-MOS SILICON GATE PROCESS 
TECHNOLOGY 


APPLICATIONS 


LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST STATIC BUFFER MEMORIES 

CRT REFRESH MEMORIES — LINE STORAGE 
LINE PRINTERS 

CARD EQUIPMENT BUFFERS 


PIN CONFIGURATION (Top View) 


B PACKAGE 


INg 

INS 

INg 
Recirculate 
VGG 

Clock 
OUTs 
OUTs 


1. 
2. 
3. 
4. 
5. 
6. 
7. 
8. 


83 


HEX 32-HEX 40-BiT STATIC 
SHIFT REGISTERS 


2918 
2919 


SILICON GATE MOS 2500 SERIES 
BLOCK DIAGRAM 


BIT 
REGISTER 


: NBIT ! 
pcm : 


BIT 


N 
Es REGISTER 


O RECIRCULATE 


TRUTH TABLE 


RECIRCULATE INPUT FUNCTION 


PART IDENTIFICATION TABLE 
PART 


NUMBER BIT LENGTH PACKAGE 


2518B HEX 32 16-Pin DIP 
2519B HEX 40 


Recircutate 


Recirculate 


“O" is Written 


“1” is Written 


16-Pin DIP 


SIGNETICS SILICON GATE MOS 2518, 2519 


MAXIMUM GUARANTEED RATINGS (1) 


Operating Temperature (2) 0°C to +70°C 
Storage Temperature -65°C to +150°C 
Package Power Dissipation 

at Ta = 70°C 640 mW 
Data and Clock Input Voltages 

and Supply Voltages with 

Respect to Voc +0.3V to -20V 


DC CHARACTERISTICS 


NOTES: 


1. 


Stresses above those listed under ‘‘Maximum Guaranteed Rating” 
may cause perrnanent damage to the device. This is a stress rating 
only and functional operation of the device at these or at any 
other condition above those indicated in the operational sections 
of this specification is not implied. 

For operating at elevated temperatures the device must be derated 
based ona 150°C maximum junction temperature and a thermal 
resistance of 125°C C/W junction to ambient. 

All inputs are protected against static charge. 

Parameters are valid over operating temperature range unless 
specified. 

All voltage measurements are referenced to ground. 
Manufacturer reserves the right to make design and process 
changes and improvements. 

Typical values are at +25°C and nominal supply voltages. 

Vec tolerance is +5% Any variation in actual V Cc will be 
tracked directly by ViL: ViH and Vow which are stated for a 
Vcc of exactly 5 volts. 

VoL is dependent on Ri and characteristics of driven gate. 


Ta = O°C to +70°C; Vec = +5V (8); VGG = -12V + 5% unless otherwise noted. (Notes: 3,4,5,6,7) 


SYMBOL TEST 


OUTPUT LEAKAGE CURRENT 


INPUT “LOW” VOLTAGE 
INPUT “HIGH VOLTAGE 


ViLC CLOCK INPUT “LOW” VOLTAGE 


VIHC CLOCK INPUT “HIGH” VOLTAGE . 


TIMING DIAGRAM 


4b 


Note: Input rise and fall times: 10nsec,. Output foad is 1 TTL gate. 


CONTINUOUS OPERATION 


Ta = 25°C 
F = 2MHz 


cars i es 


SIGNETICS SILICON GATE MOS 2518, 2519 


AC CHARACTERISTICS Ty = 25°C, Vcc = +5V; (8) Vgg = -12V 45%, Vitc = 0.4V to 4.0V 


SYMBOL TEST MN | TYP | MAX | UNIT CONDITIONS 
|rcauency | crocknernare foe | 2 | 2 | mis | seo ragansy cure 


ns 
[C0 PULSE TRANSTRTON [es 


tp DATA WaTE BET-UF) TIME [160 [|] “see 
it eata ro exooa nono re [ee 


a EL 
—— a at eee eee rsE 


( CAPACITANCE @ 1MHz; Vi, = Vcc: 
Vac = 25mV p-p 

CLOCK CAPACITANCE @ vee Vo =Vec: 
= 25mV oo p 


OUTPUT ee VOLTAGE Note | Note9 


APPLICATIONS INFORMATION 


TTL INTERFACE 


RECIRCULATE 
CLOCK 


I 
re) 
3 2518/2519 
MOS INTERFACE 


OUTPUT 
O 


SIGNETICS SILICON GATE MOS 2518, 2519 


APPLICATIONS DATA 


32 or 40 POSITION CRT DISPLAY MEMORY SYSTEM 


DOT RATE CLOCK 


5 POSITIVE 
VIDEO 


5 NEGATIVE 
VIDEO 


LINE MEMORY 
32 X6 


or 
40X6 


MAIN MEMORY 
1024 X 6 


8284A 


ROW ADDRESS ROW COUNT CLOCK 
COUNTER 


*These registers include internal recirculate. Two 8266B multiplexers are used for system recirculate. 


MULTIPLEXING LINE MEMORY REGISTERS AT 4MHz DATA RATE 


2518/19B 


fom 


DATA OUT 


NOTE: 
, The above schematic connects two 2518B or 2519B Hex Shift 
(SiMhz) Registers into a multiplexing scheme in order to accomplish a 
64 or 80 character/line display at 4MHz data rate. 


86 


SIGNETICS SILICON GATE MOS 2518, 2519 


CHARACTERISTIC CURVES 


IsoURCE (mA) 


igg (mA) 


IgqVERSUS TEMPERATURE MAXIMUM SHIFT FREQUENCY 
VERSUS Veg 


Vcc = +5.0V 


fmax(mHz) 


TEMPERATURE (°C) 


Vcc =+5.0V 
V6c =-12V 
Ta = 28°C 


IgglmA) 


Vout (V) 


87 


SIGNETICS SILICON GATE MOS 2518, 2519 


CIRCUIT SCHEMATIC 


2518, 2519 STATIC REGISTER 


| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 


| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
| 


N TH BIT OUTPUT 
x6) | stace | 
(1o0f 6) 


CLOCK GEN. 
{1 per chip } 


PACKAGE INFORMATION 


B PACKAGE 


LEAD #1 


052 


1044 


1. Lead Material: Alloy 42 or equivalent 

2. Body Material: Silicone molded 

@) Tolerances non cumulative 

4) Signetics symbol denotes Lead #1 

6) Lead spacing shal! be measured within this zone 
6. Body dimensions do not include molding fiash 


tc: i «. 


SiNOties 


DUAL 128-132 BIT STATIC 2521 


SHIFT REGISTERS 
2922 


SILICON GATE MOS 2500 SERIES 


DESCRIPTION PIN CONFIGURATION (Top View) 

These Signetics 2500 Series Dual 128 and 132 bit recircu- V PACKAGE 

lating static shift registers consist of enhancement mode 

P-channel silicon gate MOS devices integrated on a single 

monolithic chip. > ‘Redireulate 
. IN 

FEATURES " out, 


@ PUSH-PULL OUTPUTS - VGG 

® TTL/DTL COMPATIBLE CLOCK — _ PROVIDES 
EXTREMELY LOW CLOCK CAPACITANCE 

@ RECIRCULATION PATH ON CHIP 

@ TWO BIT LENGTHS AVAILABLE 

@ HIGH FREQUENCY OPERATION — 2MHz TYPICAL TRUTH TABLE 
CLOCK RATE 

@ TTL, DTL COMPATIBLE SIGNALS 

@ STANDARD PACKAGE — 8 LEAD SILICONE DIP 

@ SIGNETICS P-MOS_ SILICON GATE PROCESS 
TECHNOLOGY 


Recirculate 
Recirculate 
“0"' is Written 


APPLICATIONS 41" is Written 


LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST STATIC BUFFER MEMORIES 

CRT REFRESH MEMORIES — LINE STORAGE 
LINE PRINTERS 

CASSETTE RECORDERS 


BIPOLAR COMPATIBILITY 


The clock and signal inputs of these registers can be driven 
directly by standard bipolar integrated (TTL, DTL, etc.) or 
by MOS circuits. 


BLOCK DIAGRAM 


Dual 128 8 Pin DIP 


Dual 132 8 Pin DIP 


RECIRCULATE *Vec 
C) 


Dap. N BIT REGISTER 


OUT 1 


VEG 


Voc 


OUT 2 


+Voc 


89 


SIGNETICS SILICON GATE MOS 2521, 2522 


MAXIMUM GUARANTEED RATINGS (1) 


Operating Ambient Temperature (2) 0°C to +70°C 
Storage Temperature -65°C to +150°C 
Package Power Dissipation 

at Ta = 70°C 535 mW 
Data and Clock Input Voltages 

and Supply Voltages with 

respect to Vcc +0.3V to -20V 


DC CHARACTERISTICS Ta = 0°C to +70°C;Vec=+5V(8); VGg 


INPUT LOAD CURRENT 
CLOCK LEAKAGE CURRENT 
POWER SUPPLY CURRENT 
INPUT “LOW” VOLTAGE 


INPUT “HIGH” VOLTAGE 


CLOCK INPUT “LOW” VOLTAGE 


CLOCK INPUT “HIGH” VOLTAGE 


CONDITIONS OF TEST Input rise and fall times: 10 nsec. 


TIMING DIAGRAM 


NOTES: 


1. 


Stresses above those listed under ‘‘Maximum Guaranteed Rating’ 
may cause permanent damage to the device. This is a stress rating 
only and functional operation of the device at these or at any 
other condition above those indicated in the operational sections 
of this specification is not implied. 

For operating at elevated temperatures the device must be derated 
based on a +150°C maximum junction temperature and athermal 
resistance of 150°C/W junction to ambient. 

All inputs are protected against static charge. 

Parameters are valid over operating temperature range unless 
specified. 

All voitage measurements are referenced to ground. 
Manufacturer reserving the right to make design and process 
changes and improvements. 

Typical values are at +25°C and nominal supply voltages. 

Vec tolerance is 5%. Any variation in actual V will be 
tracked directly by Vin Vine and Vou which are stated fora 
Vec of exactly 5 volts. 


= -~12V +5% unless otherwise noted. 


i 5.5V, Ta = 25 C 
ne GND, T, = 25°C 
CONTINUOUS OPERATION 

° 
F = 1.5MHz, Ta=25 C 


Output load is 1 TTL gate 


90 


SIGNETICS SILICON GATE MOS 2521, 2522 


AC CHARACTERISTICS Ta = 25°C,Voc = +5V(8); Vg = -12V 45%, Vjc=0.4 to 4.0 


SYMBOL TEST Ena Bd Ed Eo UNIT CONDITIONS 


FREQUENCY CLOCK REP RATE 5 See Maximum Frequency Curve 
td pw CLOCK PULSE WIDTH 


topw CLOCK PULSE WIDTH 
t; ts CLOCK PULSE TRANSITION 
DATA WRITE (SET-UP) TIME 


DATA TO CLOCK HOLD TIME 
CLOCK TO DATA OUT DELAY 


CLOCK TO RECIRCULATE 
INPUT CAPACITANCE @ 1MHz; Vin = Voc: 


Vac= 25mV p-p 


CLOCK CAPACITANCE @ 1MHz; Vo =Vec: 

VAC = 25mV p-p 
OUTPUT “LOW” VOLTAGE 1 TTL load (i, =1.6mA) 
OUTPUT “HIGH” VOLTAGE 


DRIVING 1 TTL LOAD : 1 TTL load (1, = 100A) 
OUTPUT “HIGH” VOLTAGE 


DRIVING MOS 


TIMING DIAGRAM 


4 BIT RECIRCULATING SHIFT REGISTER * 


ett | Bit2 | sits | sits | sits | its | eit? | sits | cite | sit10 | eit11| Biv12 | eit 13 
clock 2 WOW eee 
CLOCK ¢1N +0.4 

DATA = - OATA ae tn. | | 


DATA IN 


+5V 
DATA OUT -5V 


a | | 
RECIRCULATE 6 
| | | | 


NOTE 1: WRITE CYCLE NOTE 2: RECIRCULATE CYCLE 
The positive going edge of the Data recirculates if the recirculate 
recirculative control is coincident control is a ’‘0” 

with the negative going edge of 

the input clock (¢ IN): 


*For clarity, a four bit hypothetical example is shown 


91 


SIGNETICS SILICON GATE MOS 2521, 2522 


SCHEMATIC DIAGRAM 


INPUT 


o—_t—_| 


(1 OF 2) | 


RECIRCULATE O 


CLOCK GENERATOR 
(1 PER CHIP) 


APPLICATIONS DATA 


TTL/DTL/MOS INTERFACES 


RECIRCULATE 


2521 
2522 
| 


92 


SIGNETICS SILICON GATE MOS 2521, 2522 
APPLICATIONS INFORMATION 


MULTIPLEXING LINE MEMORY REGISTERS AT 3MHz DATA RATE 


= 1 | asevane | 2522 


(= 


DATA OUT 


8880 }O 
80 


pi 


CHARACTERISTIC CURVES 


POWER SUPPLY CURRENT POWER SUPPLY CURRENT 
VERSUS POWER SUPPLY aici VERSUS TEMPERATURE 


ee ee 


ERR Eee e a 
PeREeaae se 
TTT TT TA 
ASR eer aes 


TEMPERATURE (°C) 


MAXIMUM OPERATING FREQUENCY PACKAGE MAXIMUM 
VERSUS SUPPLY VOLTAGE POWER DISSIPATION 


| gene The 


FREQUENCY (MHz) 
MAX{MUM POWER DISSIPATION (mW) 


AMBIENT TEMPERATURE (°C) 


93 


SIGNETICS SILICON GATE MOS 2521, 2522 


132 COLUMN LINE PRINTER 


LINE MEMORY 
132 X 10 


132BITS 


PARITY 
BIT 


132 
HAMMER 
ORIVERS 


132 BITS 


ote 


i 
ine 
tie 


Ascii 
DATA J aBiT 


INPUTS | copE 


it 


| 


1/0 CONTROL 


PACKAGE INFORMATION 


V PACKAGE 


1. Lead Material: Alloy 42 or equivatent tinned. 
2. Body Material: Silicone Molded 


@) Tolerances Non-Cumulative 
@ Signetics Symbot Denotes Lead =1 
& Lead Spac ing shait be Measured within this Zone 


6. Body Dimensions do not include Molding Fiash 
7. Thermal Resistance, 6 J, = .18°C/mw, 


SiNCticS : 


SiHNOtics 


DESCRIPTION 

These Signetics 2500 Series 512 and 1024 bit recirculating 
dynamic shift registers consist of enhancement mode P- 
channel MOS devices integrated on a single monolithic 
chip. Internal recirculation logic plus write and read con- 
trols are included on the chip. 


FEATURES 


@® HIGH FREQUENCY OPERATION-5 MHz Typical 

Clock Rate 

SINGLE 512, SINGLE 1024 

TTL, DTL COMPATIBLE 

WRITE AND READ CONTROLS INCLUDED 

LOW POWER DISSIPATION-150uW/bit at 1 MHz 

LOW CLOCK CAPACITANCE-80pF for 512, 160pF 

for 1024 Bits 

e@ +5, -5 POWER SUPPLIES 

@ STANDARD PACKAGE 8-LEAD DIP 

@ SIGNETICS P-MOS SILICON GATE PROCESS TECH- 
NOLOGY 


APPLICATIONS 

FAST ACCESS SWAPPING MEMORY SYSTEMS 
LOW COST SEQUENTIAL ACCESS MEMORIES 
LOW COST BUFFER MEMORIES 

CRT REFRESH MEMORIES 

DELAY LINE MEMORY REPLACEMENT 
DRUM MEMORY REPLACEMENT 


PROCESS TECHNOLOGY 


Use of low threshold s//icon gate technology allows high 
speed (5MHz typical) while reducing power dissipation and 
clock input capacitance dramatically as compared to other 
technologies. The use of low voltage circuitry minimizes 
power dissipation and facilitates interfacing with bipolar 
integrated circuits. 


BIPOLAR COMPATIBILITY 


The signal inputs of these registers can be driven directly by 
standard bipolar integrated (TTL, DTL, etc.) or by MOS 
circuits. The bare drain output stage provides driving 
capability for both MOS and bipolar integrated circuits 
(one standard TTL load). 


912 AND 1024 BIT RECIRCULATING 
DYNAMIC SHIFT REGISTERS 


95 


2924 
2929 


SILICON GATE MOS 2500 SERIES 


SILICONE PACKAGING 

Low cost silicone DIP packaging is implemented and reli- 
ability is assured by the use of Signetics unique silicon gate 
MOS process technology. Unlike the standard metal gate 
MOS process the silicon material over the gate oxide passi- 
vates the MOS transistors, and the deposited dielectric 
material over the silicon gate-oxide-substrate structure pro- 
vides an ion barrier. In addition, Signetics proprietary sur- 
face passivation and silicone packaging techniques result in 
an MOS circuit with inherent high reliability and demon- 
strating superior moisture resistance, mechanical shock and 
ionic contamination barriers. 


PIN CONFIGURATION (Top View) 
| V PACKAGE 


‘ oy) Input clock 8 Vcc 
. Output 7. by Output clock 
. Read 6. Input 


- VpoDd 5. Write 


OUTPUT 
O 


2 
- N BITS : 


WRITE (W) READ (R ) 


NOTE 
N = 512 or 1024 ‘0’ = OV, ‘1’ = +5V. 


TRUTH TABLE 


[wire [peas [runcrion 


Recirculate, Output is ‘O’ 
Recirculate, Output is Data 
Write Mode, Output is ‘O’ 
Read Mode Output is Data 


PART IDENTIFICATION TABLE 


PART NO. BIT LENGTH 


2524V 


PACKAGE 


8 pin DIP 
8 pin DIP 


SIGNETICS SILICON GATE MOS 2524, 2525 


MAXIMUM GUARANTEED RATINGS (1) 


2. 
Operating Ambient Temperature (2) 0°C to +70°C 3. 
4. 


Storage Temperature —65°C to + 150°C 


For operating at elevated temperatures the device must be 
derated based on a +150°C maximum junction temperature and 
a thermal resistance of 150°C/W junction to ambient. 

All inputs are protected against static charge. 

See “‘Minimum Operating Frequency” graph for low limits 
on data rep, rate. 


All voltage measurements are referenced to ground. 
Manufacturer reserving the right to make design and process 


Typical values are at +25°C and nominal supply voitages. 


Parameters are valid over operating temperature range unless 


- Vec tolerance is + 5%. Any variation is actual Vcc will be 


tracked directly by Vij_, VjH and VOwH which are stated 


. . - ° 
Power Dissipation (2) 535nWOT p> 70°C 5 
Data and Clock Input Voltages 6. 
and Supply Voltages with changes and improvements. 
7. 
respect to Vcc + 0.3V to —20V 8. 
otherwise specified. 
NOTES: 9 
1. Stresses above those listed under ‘‘Maximum Guaranteed Rating” ; Vv ; 
may cause permanent damage to the device. This is a stress rating ora Vcc oF exactly 6 volts. 
only and functional operation of the device at these or at any 10. 


other condition above those indicated in the operational sections 
of this specification is not implied. 


Vo_ is a function of the input characteristics of the driven 
TTL/OTL gate tg) and Vc_ amp and the value of the pull- 
down resistor (R_). 


DC CHARACTERISTICS Ty, =0°C to +70°C; Vcc = +5V(9); Vpp = 5V +5% unless otherwise noted. 


Input “Low” Voltage 


Input “High” Voltage 
Vitec Clock Input ‘‘Low”’ Voltage 
VIHC Clock Input “High” Voltage 


TIMING DIAGRAM 


BIT 1 BIT2 | BITS SIT 4 SITS | BITS | BIT? 


ouTPUT 
CLOCK ¢, 


INPUT 
CLOCK $2 


“9 


+5V eogee DATA DATA “q" 
DATA IN DATA IN2 IN3 A 


DATA OUT 


DATA 
DATA [OUT 2 


BIT 10 | BIT 11 | BIT12 | BIT 13 


Vo1 = V62 =-12V; Vpp =-5 
Vout =5-5V; Ta = 25°C 


Continuous Operation; 
gopW = 150nS; 1MHz 


Vitec =-12V; Ta = 25°C 


NOTE 1: (WRITE cycle) 


The positive and negative going 
edge of the ‘‘Write’’ control is 
coincident with the negative going 
edge of the input clock (po). The 
““Read’’ control may be either ‘'1” 
or ‘‘Q"’. 


NOTE 2: (RECIRCULATE cycle) 


Data recirculates if the ‘‘Write”’ 

control line is ‘‘0’’. ‘‘Read’’ may 
be either ‘‘1’’ or ‘‘0’’. 

DATA | 


OUT DATA 


curs NOTE 3: (READ cycle) 


sc a 


NOTE 2: NOTE 3: 


NOTE 1: 
WRITE CYCLE RECIRCULATE CYCLE READ CYCLE 


NOTE: 
This is a simplified illustration of the timing of a 4 bit recirculating shift register 
showing the 3 basic modes of operation. 


96 


| The positive going edge of the 


‘*Read’’ control is coincident with 
the negative edge of the output 
clock (4 ). The negative going edge 
of ‘*Read”’ is coincident with the 
negative going edge of either clock 
pulse succeeding the last desired 
data output bit. ‘‘Write’’ may be 
either ‘1"’ or “‘0"’. 


SIGNETICS SILICON GATE MOS 2524,2525 


CONDITIONS OF TEST 
Input rise and fall times: 10 sec Output load is 1 TTL gate 


TIMING DIAGRAM 


. 


NOTE: 
N = 512 for 2524 N = 1024 for 2525 


CONDITIONS 


SYMBOL TEST MAX 


.0005 
Frequency Clock Data Rep Rate (Note 4) 


toow Clock Pulse Width 
tod Clock Pulse Delay 
; : ; 
t 


ond 


Y UNIT 


= 
a 
N 
= 
m 
es) 
u 
< 
O 
ie) 


Clock Pulse Transition 
Data Write (Setup) Time 
H 


D 70 
Data to Clock Hold Time 20 
Clock to Data Out Delay 


tp_; Clock to “Read” or 
t w- “Write” Timing 
tr; Clock to “Read” or 


twt “Write’’ Timing 


Input Capacitance 
Output Capacitance 


“ 
V 


Cc Clock Capacitance 
2524 
2525 


xo) 
n 


MHz; V\j=Voc;Vac=25m Vp p 


xe) 


IMHz; Vo=Vec:Vac=25m Vp. 


f°.) 
i=) 

xo} 
nN 


IMHz; V=Vec; Vac=25m V 


Ry =3.0K; 1 TTL Load (ly = 
1.6mA) Note 10 


V R,_=3.0K; 1 TTL Load (1, =100uA) 
v | Ry = 5.6K; Cy = 10pF 


n 
OL Output ““Low” Voltage 
Output “‘High” Voltage 
Driving 1 TTL Load 

Output “’High’”’ Voltage 
Driving MOS 


I) 
B 


VOHI 


VOH2 


ioe) 
oO 


4.0 


: W 
o 


97 


SIGNETICS SILICON GATE MOS 2524, 2525 


CHARACTERISTIC CURVES 


MAXIMUM CLOCK RATE (Mttz) POWER DISSIPATION PER BIT (:W) 


MAXIMUM PACKAGE POWER DISSIPATION(mW) 


NOTE: 


POWER DISSIPATION/BIT 
VERSUS SUPPLY VOLTAGE 


= 
ie eal 
im 
i 
ce 
on 
cE 


SUPPLY VOLTAGE ( 


MAXIMUM CLOCK RATE 
VERSUS CLOCK AMPLITUDE 


Vop) (VOLTS) 


TTT 
LUN TEL 
LEELEN 
LEN IT 
PEELE 


CLOCK AMPLITUDE (Vy (VOLTS) 


MAXIMUM PACKAGE POWER 
DISSIPATION VERSUS TEMPERATURE 


ee 
22 se eee 
ie ee a ee 


TEMPERATURE ( C) 


IT (uw! 
POWER DISSIPATION PER BIT (uW) POWER DISSIPATION PER BIT (uW) 


MINIMUM CLOCK FREQUENCY (Hz) 


POWER DISSIPATION/BIT 
VERSUS CLOCK RATE 


CLOCK RATE (MHz) 


POWER DISSIPATION/BIT 
VERSUS TEMPERATURE. 


TEMPERATURE (°C) 


MINIMUM OPERATING CLOCK 
FREQUENCY VERSUS TEMPERATURE 


TEMPERATURE (°C) 


Conditions for typical curves: Voc = +5V, Vop = -5V, clock duty cycle = 35%, fo, « = 3MHz, vp-p = 16V, 
dpw1= Ppw2 = B0rs, Ta = +25°C unless otherwise rioted. 


SIGNETICS SILICON GATE MOS 2524, 2525 


APPLICATIONS DATA 


TTL/DTL/MOS INTERFACES 


(RECIRCULATING (USED AS AN 
SHIFT REGISTER) N BIT SHIFT 
R REGISTER) 


CIRCUIT SCHEMATIC 


WRITE 


Vee 


NOTE 
N = 512 for 2524 
N = 1024 for 2525 


SIGNETICS SILICON GATE MOS 2524, 2525 


SIMCtiES 


PACKAGE INFORMATION 


100 


V PACKAGE 


1. Lead Materiat: Alioy 42 or equivalent, tinned. 
Except Surfaces Marked 
2. Body Material: Silicone Molded 
@) Tolerances Non-Cumulative 
Signetics Symbol Denotes Lead =1 
6 Lead Spacing shalt be Measured within this Zone 
6. Body Dimensions do not include Molding Flash 


101 


SECTION 


2000/2400 METAL GATE 
MOS SPECIFICATIONS 


102 


SiNnOties bua. stan) 2000 


SHIFT REGISTERS 


METAL GATE MOS 2000 SERIES 


DESCRIPTION PIN CONFIGURATION 


The S2001K, S2002K, S2003K, $2004K, and S2005K are 
Dual Static Shift Registers manufactured with a ‘’P”’ 


BOTTOM VIEW 
channel enhancement mode process. 


The registers vary in length from dual 16 to dual 100. Two — 
power supplies and 2 external 28 volt clocks are required. 
Static operation is assured with a third clock phase that is 
generated on the chip. The pin configuration allows inter- 
changing of register lengths without rewiring the socket. 
Data is transferred into the register during ¢, and output 
data appears on the negative-going edge of ¢2. For static 
operation @, must be a ‘‘0” and @, “1”. 


N-BIT SHIFT 
REGISTER 
N-BIT SHIFT 


REGISTER 


NC-—NO INTERNAL CONNECTION 


PARTS IDENTIFICATION TABLE 


PART NO. BIT LENGTH PACKAGE 


ABSOLUTE MAXIMUM RATINGS $2001K . 10 Pin TO-100 
Vqq with respect to Gnd -16V to 0.3V $2002K eine 
Vag with respect to Gnd -30V to 0.3V S$2003K . 10 Pin TO-100 
Clock and In with respect to Gnd -30V to 0.3V ; 
Operating Temperature -55°C to +85°C . zOOB IE 4 10 Fin FOA0G 
Storage Temperature -  -B5°C to +150°C $2005K 1 10 Pin TO-100 
CIRCUIT SCHEMATIC 


DATA IN Qn 


INPUT CIRCUITRY OUTPUT BUFFER 


103 


SIGNETICS $2000 SERIES 


ELECTRICAL CHARACTERISTICS ( Notes: 1, 2, 3,4 and 5 ) 


LIMITS TEST CONDITIONS 
NOTES 
CHARACTERISTICS TYP MAX UNITS aoe Vpp Veg Vin V¢q Vd | OUTPUT 


“1” Output Voltage 
“0” Output Voltage 


Output Drive Capability 


R= 17kQ to Gnd 
R, =4 kQ to Gnd 


2001 


R, = 17kQ.to Gnd 
R, = 4kQ to Gnd 


2002/3/4/5 


Input Leakage Current 
Data Inputs 
Clock Inputs 

4 
92 

Output Impedance 
2001 
2002/3/4/5 

Input Capacitance 
Data Inputs 
Clock Inputs 


2001 
2002 
2003 
2004 
2005 


Power Supply Current 


2001/2/3 
2004/5 


Propagation Delay (tpd) 
from $9 


2001 
2002/3/4/5 


SIGNETICS $2000 SERIES 


NOTES FOR ELECTRICAL CHARACTERISTICS: FORCING FUNCTIONS 


1. Parameter valid over operating temperature range unless other- 


wise specified. CLOCK REQUIREMENTS 


2. All voltage measurements are referenced to the ground terminal. 
Terminals not specifically referenced are tied to ground. 

3. Negative logic definition: ‘“‘DOWN” Level = ‘1’, “UP” 
Level = ‘0’. 

4. Manufacturer reserves the right to make design and process 

changes and improvements. 

Output voltage levels valid from D.C. to 1 MHz. 

See output timing diagram. 

Output toad is 10 pF and 1 MQ 


f = 1 MHz, Vac = 25 MVems- All pins not specifically referenced 
are tied to guard terminal for capacitance tests. Output pins are 
left open. 


9. All typical values are at 25°C and nominal supply voltages. 


PN AH 


OUTPUT TIMING DIAGRAM 


UNITS 
$4 2 “9” 


4 $2 n4 rd 


DATA OUT 


Note: @9 may not beat “0” logic level 
for more than 10 ws. 


CLOCK DRIVER 
INPUT REQUIREMENTS 


Data in “1” 


terg 0 & tege 


Note: At high repetition rates and/or high capacitance loads, the 
transistors may require heat sinking, i.e., 1000 pF at 1 MHz. 


Note: Data In must be stable between the 10% points of 4. 


105 


SIGNETICS $2000 SERIES 


TTL INTERFACE REQUIREMENTS PACKAGE INFORMATION 


K-PACKAGE (TO-100) 
ae 
= 


cy ah S200XK V6 8490 IgEADS 
DATA OUTPUT }-_} >>o- 0 ate 
INPUT TTL /0TL 32200. 
DATA 
OUTPUT 


O 
~-wv 2401, 160 
CLOCK a 120 


5V CLOCK INPUTO GENERATOR 
DRIVER 


Vs=+5V, Vp =-9V, Vg =-23V NOTES: 
(1) All dimensions in inches 
(2) All leads weldable and solderable 


Sinntic 
iNOtiCS ie 


SiMGTCS DUAL 100-BIT STATIC 2010 


SHIFT REGISTER DC TO 3 MHZ 


METAL GATE MOS 2000 SERIES 


DESCRIPTION PIN CONFIGURATION 


The N2010K Dual 100-Bit Static Shift Register is designed 
for use at shift rates from 0 to 3 MHz.* The device employs BOTTOM VIEW 
“P’’ channel enhancement mode MOS techniques. Power 
supply requirements are -14 and -28 Vdc. Clocking is 
provided by two external -28 volt clock phases. A delayed 
second clock phase (¢2s) is generated on the chip. 

Data is transferred into the register during ¢1. Output data 
appears on the negative going edge of $9. For static 
operation, 1 must be a “0” and ¢2 a “1”. 

The N2010K is a direct pin replacement for the S2005K/ 
3003 1MHz Static Shift Register. 


*(25°) 


REGISTER 


- 
ae 
4 
re: 
8 


100—BIT SHIFT 


ABSOLUTE MAXIMUM RATINGS: 


VDD with respect to Gnd -16V to 0.3V NC—NO INTERNAL CONNECTION 
VGG with respect to Gnd -30 to 0.3V 

Clock and Input with respect to Gnd -30V to 0.3V 

Operating Temperature 0°C to +70°C 

Storage Temperature -55°C to +150°C 

CIRCUIT SCHEMATIC 


ee I. sna ES 
Poe ee 


~~ 


INPUT CIRCUITRY LAST BIT OUTPUT BUFFER 


107 


SIGNETICS 2010 METAL GATE SERIES 


ELECTRICAL CHARACTERISTICS (Notes: 1, 2, 3, 4, 9) 
RECOMMENDED POWER SUPPLY VOLTAGES: Vpp = -14 £1 Vdc, Vg& = -28 11Vde 


p LIMITS TEST CONDITIONS 


CHARACTERISTICS alee NOTES 


oe Fite ieee 
or oaetvote [ns row Pas fo oa for oa [ae [Po 


input Leakage Current a i ee 
Data Inputs | o |-15{ 0 | 0 | 
Clock Inputs fe te See es 
: oe eee ee 
Ee 


un i 
Ww WwW 


t 
N 
~s 

| 
Le) 


No 
N 
(>) 
oo 
° 
an 
< 


=a rae 


Input Capacitance 


Data Inputs 
Clock Inputs 


NO] NO} NM] nN nN 
a;o a};yoay; o ao oOo 


Power Supply Current 


I 
~ 


! 
NQ 


Ww 
bo N A) 
= ae ee | 
>| > 
NTN 
© 0 | co 


i) 
oO 
oO 
NO 
on 
oO 


NTN | ND 
oy, or] om 


Propagation Delay (tdp) from $9 -28 Bue -28 


. Parameter valid at +25°C unless ee 6. See output timing diagra 
: ave olta sets urements sig referenced to the ground terminal. Terminals not specifically 7.- Output load is 10pF a na wee 


1 
2 
enced are We grou 8. f= 1 MHz, Vac = 25mV rms. All pin gba cifically referenced are tied to guard terminal 
3. neath + ogi sae ion DOWN Level = "1", “UP’' Level = ''0” for capacitance tests. Output pins a alain 
4. Manufa the right to make design sndpro cess changes a avid improvements. 9. All typical values are at 25°C and n omnis veoh voltages. 
5. Outputy Sole age Seles atid from OC to 3 MHz, 


TYPICAL PERFORMANCE CHARACTERISTICS 


MAXIMUM OPERATION FREQUENCY POWER DISSIPATION 
VERSUS CLOCK AND SUPPLY VOLTAGE VERSUS OPERATING FREQUENCY 


1000 


Nill 


8 
SE LT 
| f 


.<) 


TYPICAL POWER DISSIPATION (mW) 
u 
SS 


° 
- 
a 
23 
4 
§ 
3° 
= 


MAXIMUM OPERATING FREQUENCY (MHz) 


SIGNETICS 2010 METAL GATE SERIES 


CLOCK REQUIREMENTS TTL INTERFACE REQUIREMENTS 


v6 8490° 


TTL/DTL N2010K v6 8490 
OATA OUTPUT i>o re) 
INPUT TTL/OTC 
DATA 
OUTPUT 


CLOCK 
5V CLOCK INPUTO GENERATOR 
DRIVER 


NOTES: 
1. Register ground (V,) is tied to the bipolar integrated 
circuit Vog power supply for proper biasing. 
= +5VDC 
Vp =-3 VDC 
Vg =-23 VDC 


TIMING 


ty & tr 
o1 PW 


. Signetics Corp. N8490A 
¢2 PW 


too 


Ciock Repetition Rate 


OUTPUT TIMING DIAGRAM 


Note: @9 may not beat ‘’0” logic tevel 
for more than 10 us. 


INPUT REQUIREMENTS 


ov 


DATA OUT 


CLOCK DRIVER 


Data in ‘°0” 


Data in “'1"" 


Tog a & tron 


NOTES: 
1. At high repetition rates and/or high capacitance loads, 
the transistors may require 
heat sinking, i.e., 1000 pF at 3MHz, 


2. %N8822B, SP322B etc. 
3. % N8880A, SP387A etc. 


Note: Data In must be stable between the 10% points of $4. 


109 


SIGNETICS 2010 METAL GATE SERIES 


PACKAGE INFORMATION 


K-PACKAGE (TO-100) 


L308 
030 
T 020 


1B : 
189 INSULATOR 
O18 


ral ne 


355 


240, 160 
220° 120 [+ 3 


NOTES: 
(1) All dimensions in inches 
(2) All leads weidable and sotderable 


SiNCtics 
ry LLU ii 


SiNNOties 


FULLY DECODED 1024 AND: 
2048 STATIC READ-ONLY MEMORIES 


2400 


DESCRIPTION 

The Signetics 2400 Series devices are high speed, fully de- 
coded, MOS static 1024 and 2048-bit read-only memories 
offering 128X8, 256X8, 256X4, and 512X4 organizations. 


Two output structure options, plus both single line and 

3-bit binary coded chip select options, provide for wide 
versatility and economy of application. The devices interface 
directly with standard TTL/DTL or MOS logic circuits. 
Process technology is P-Channel enhancement mode. 


FEATURES 
128X8, 256X8, 256X4, 512X4 ORGANIZATIONS 
STATIC OPERATION ~- NO CLOCKS 
FULLY DECODED ADDRESS 
500ns TYPICAL ACCESS TIME 
TTL/DTL COMPATIBILITY 
OUTPUT OPTIONS: 
BARE DRAIN 
20K OHM PULL-DOWN RESISTOR 
@ TWO CHIP SELECT OPTIONS: 
SINGLE LINE 
3-BIT BINARY CODED 
@ EBCDIC-ASCII CONVERSION 
TABLE IS CATALOG STANDARD, 
OTHER STANDARDS AVAILABLE 
@ +12, -12V POWER SUPPLIES 
@ STANDARD PINNING IN 16 AND 24 PIN CERAMIC 
DUAL IN-LINE PACKAGES 


APPLICATIONS: 


. CODE CONVERSION 
LOOK-UP TABLES 
MICRO-PROGRAMMING 
RANDOM LOGIC SYNTHESIS 
CHARACTER GENERATION 


SPECIAL FEATURES 


Output Options: Two output structure options allow ease 
of interfacing with TTL/DTL or other MOS circuits. 


Chip Select Options: Both the 2420 and 2430 group may be 
specified with either single line chip select or a 3 line, 3-bit 
binary coded chip select. The coded chip select allows one- 
of-eight chip selection without external logic components 
for larger memory matrices. The 2410 group is pin limited 
to single line chip select. 


Package Options: The 256X4 organization is available in 
either a 16-pin or 24-pin dual in-line package. 


For a detailed listing of part numbers and options see the 
PART IDENTIFICATION TABLE. 


111 


METAL GATE MOS 2400 SERIES 


CUSTOM ENCODING 

You may describe the particular option you desire in a book- 
let which will be provided by Signetics. Ask your local 
Signetics representative for a copy of “SIGNETICS 2400 
SERIES STATIC READ-ONLY MEMORIES — MOS-ROM 
PROGRAMMING”. The booklet contains a blank truth table 
and instructions for preparing punched data cards. 


PIN CONFIGURATIONS (Top View) 


16. Voo 

Address 4 
Address 5 
Address 6 
Address 7 


Address 3 
Address 2 15. 
Address1 14. 
Outputt = 13. 
Output 2 12. 
Output3 11. Veg 
Output 4 10. Chip Enable 
Vss 9. Address 8 


DN AASWN = 


Address:3 24. 
Address 2 23. 
Address 1 292, 
Output 1 94 
Output2 209. Address 5 
Output3 49 Address6 
Output4 18. Address 7 
Output 5 17. Voc 
Output6 46 Mode Control 
10. Output? 46° Chip Enable 
11. Output8 44° address 8 

12. Vgsg 13. No Connection 


Vop 

Chip Enable 3" 
Chip Enable 2” 
. Address 4 


CON AGAPHN = 


“No connection for single chip 
enabie options. 


Address 3 24. 
Address 2 93 
Address 1 99 
Output 1 21 
Output 2 
Output 3 
Output 4 
Output 5 
. Output6 
10. Output 7 
11. Outputs 15. Mode Control 
12. Vgg 14. Chip Enable 
13. Address 9 


Vpo 

. Chip Enable 3” 
. Chip Enable 2° 
. Address 4 

20. Address 5 

19. Address 6 

18. Address 7 

17. Address 8 

16. Veg 


ODNATRAWN a 


“No connection for single chip 
enable options. 


SIGNETICS METAL GATE MOS 2400 SERIES 


BLOCK DIAGRAMS 


2410 


OPERATING MODE 


1. Logic ‘‘1’’ level enables outputs. 


O 
CHIP ENABLE 


2420 


OPERATING MODES 


1. 128 x 8 ROM Connections 
Mode Control ~ Logic ’‘0” 
As ~ Logic ‘1’ 
2. 256 x 4 ROM Connection 
Mode Control ~ Logic ‘’1’’ 
A8 - Logic “0’’ Enables the odd 
(B1, B3, B5, B7) outputs. 
- Logic *’1’’ Enables the even 
(B2, B4, 86, BS) outputs 
CE, CE,, and CE, are AND’ed per 
customer instructions. 


2430 


OPERATING MODES 


1. 256 x 8 ROM Connection 
Mode Control — Logic ‘0°’ 
AQ - Logic ‘1 
. 512 x 4 ROM Connection 
Mode Control - Logic ‘‘1"' 
AQ - Logic ‘’0’’ Enables the odd 
(B1, BS... B7) Outputs 
—- Logic ‘‘1’’ Enables the even 
(B2, B4...B8) Outputs 
- CEp, CE,, and CE, are AND’ed per 
customer instructions, 


112 


SIGNETICS METAL GATE MOS 2400 SERIES 


ABSOLUTE MAXIMUM RATINGS 


Operating Ambient Temperature -25°C to +70°C 
Storage Temperature -65°C to + 150°C 
Power Dissipation (2) (‘“Y’’ Package) @70°C 1.14W 

(“I Package) @70°C 0.80W 


Vo6G (3) -30 to +0.3 
Vpp (3) -30 to +0.3 
Input Voltage (3, 4) ~30 to +0.3 


DC CHARACTERISTICS 
Ta =-25°C to +70°C; Vsg = +12V (17); Vpp = OV; Vgg = -12V +10% unless otherwise noted (Notes: 10, 11, 12, 13, 14, 16). 


-svwpo, | ____test_ | ww {ry { wax | uur ___[_cowprrions_ 


Input Logic ‘‘0” 
Input Logic 1” 


VssPower Supply Current Ta = 25 c 

VGGPower Supply Current Note 5, Ty, = 25°C 
Input Leakage VIN =O0V 
Pull-down Resistor Note 6 


2410, 20 25, 30, 35 


AC CHARACTERISTICS 
TaA= 25°C; Vss = +12V (17); Vpp = OV; Veg =-12V £10% unless otherwise noted .(Notes: 11, 12, 13, 14, 16). 


Output Logic ‘0’ MOS to MOS 1 Megohm to Ground, Note 8 


Output Logic “1” 1 Megohm to Ground, Note 8 


Output Logic ‘0’ ; Note 7,9 
paper ee MOS to TTL oe 
Output Logic “1” ; Note 7,9 


Address Time (bare drain) Note 15 
Address Time (bare drain) 


NOTES: 

1. Stresses above those listed under ‘‘Maximum Guaranteed Ratings’’ may cause permanent damage to the device. This is a stress rating only. 
Operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. 

2. For Operation at elevated temperatures, the device must be derated based on a maximum junction temperature of 150 °C and a thermal resistance of 
70 °C/w junction to ambient for the ‘‘Y’’ package. The ‘‘!’’ package is derated based on 100 “c/w junction to ambient. 

3. These voltages are referenced to network ground terminal (Vgo). 

4 All inputs are protected against damage by static charge. 

5. The Vegsupply may be clocked to reduce device power without affecting access time. 

6. Output to Vop: 

7. 6.8k2 to Vg gPlus 1 standard TTL gate input. 

8. This test is for devices using a 20k{2 MOS pull-down resistor (2410, 20, 25, 30, 35. ). 

9. This test is for devices supplied with a bare drain output (2411, 21, 26, 31, 36). 

10. Parameter valid over operating temperature range unless otherwise specified. 

11. All voltage measurements referenced to ground. 

12. Manufacturer reserves the right to make design changes and process improvements. 

13. Typical values are at 25 °C and nominal supply voltages. 

14. Negative logic definition is employed for this device, i.e., more negative level is logic ‘‘1’’, most positive level is logic ‘‘O’’. 

15. For bare drain devices, Ta 4 is primarily a function of the time constant of the load capacitance and external load resistor 
(tay = 4R_ Cy +50ns). 

16. CAUTION: These devices will be permanently damaged if reversed in board or socket. 


17, Vec tolerance is 10%. Any variation in actual Vec will be tracked directly by V;,, Vjy4, and Von which are stated 
for a Vec of exactly 12 voits. 


113 


SIGNETICS METAL GATE MOS 2400 SERIES 


AC TEST SETUP 


TIMING DIAGRAM 


SIGNETICS METAL GATE MOS 2400 SERIES 


PART IDENTIFICATION TABLE 


CHIP SELECT 
PART ORGANIZATION © PACKAGE OUTPUTS CONTROLS 


N24101 256 x 4 16-pin Cer. D 20k ohm Pull-down 1 
N2411 | 256 x 4 16-pin Cer. DIP Bare Drain 1 
N2420Y 128 x 8 or 256 x 4 24-pin Cer. DIP 20k ohm Pull-down 1 
N2421Y 128 x 8 or 256 x 4 24-pin Cer. DIP Bare Drain 1 
N2425Y 128 x 8 or 256 x 4 24-pin Cer. DIP 20k ohm Pull-down 3 
N2426Y 128 x 8 or 256 x 4 24-pin Cer. DIP Bare Drain 3 

N2430Y/CMO0000 256 x 8 (EBCDIC-ASCII) 24-pin Cer. DIP 20k ohm Pull-down 1 
N2430Y 256 x 8 or 512 x 4 24-pin Cer. DIP 20k ohm Pull-down 1 
N2431Y 256 x 8 or 512 x 4 24-pin Cer. DIP Bare Drain 1 
N2435Y 256 x 8or 512 x 4 24-pin Cer. DIP 20k ohm Pull-down 3 
N2436Y 256 x 8or 512 x 4 24-pin Cer. Bare Drain 3 


APPLICATIONS 


TTL-MOS-TTL INTERFACING 


x SERIES 
"1 (Bare Drain) 


8T80 7416 
8T70 7426 
8T90 


STD TTL/DTL 


Ry may range from 68022 to 33k, typically 3.3k is 
satisfactory. 

Ra 6.8k for a standard TTL (1, IN = 1.6mA) 

Rg = 2.2k 


115 


SIGNETICS METAL GATE MOS 2400 SERIES 


NOTE: Blanks are logic 1's. CMO0O000 TRUTH TABLE 


EBCDIC ASCII Code EBCDIC ASCII Code EBCDIC ; EBCDIC ASCII Code 
WORD # Bit Number WORD # Bit Number WORD # 1 WORD # Bit Number 


1234567 1234567 | 1234567 


OCOAN ODA ABWNH oO 
Qo-"200 = = 


~-_—_~ OO] -00 = 


oooor-r+2+0 
eee - oOcdod0n0e 


COCOA aa a ow 
COCO CCOC0O 
COC COCOC CSO 

O-0-0-2-20 

=-O0-2022 4 

C0000 

COOf aaa a a 

=--000--00 

20000000 

ER SNES, Sear etal Mais 


0 1 
11 
00 
10 
0 1 
11 
00 
10 
O01 


oooer++-"00 


Ooo am a a aa ow 
"we -9O 000 00 


ee ee ee ee ee 
= 2 eo ew ew ew = or 


O-0-0-02 
-0O00--00-2 
O0022-2-0 
---00000 
os eis a5 Acs) ei cay ers 
sai ed | es i ae ea as 
ci ea la oats dela ask 
O- 0-002 
-CO==002 
COOsa44-20 
--2=-00000 
tes Ste NS a Sy ae ne 
e000 CO0°0 
Riots wong aks Socce, £2) ty 


-o-0r0+/0-0 
oo2rr00++00 
oo-2/2-/0000 
-- O00 0C0CCoCoO oO 
SB a ew wow oo ow eo oo 
22 oo oe oe 
oooo0oo0o0o0o0°co;o 


116 


SIGNETICS METAL GATE MOS 2400 SERIES 


CHARACTERISTIC CURVES 
Ipp VERSUS TEMPERATURE AND ACCESS TIME VERSUS 
POWER SUPPLY VOLTAGE SUPPLY VOLTAGE 


Vop = -14V 


Ipp (mA) 


a VGG = -28V 


nal 


Talns) 


Vop = -13V 


| ce = .26V 


a 
ce 


Vpp = -12V 
VGG = .24V 


TEMPERATURE(°C) 


Ipp VERSUS SUPPLY VOLTAGE 


lpp (mA) 


NOTE: For typical 
curves, Vss = OV. 


SCHEMATIC DIAGRAM 


OUTPUT STRUCTURE 


— 


OUTPUT 


dj 
cdf *Optional 20K MOS pulldown resistor 
i] 
N2410,20,25,30 and 35 only 


Veg Yop 


117 


SIGNETICS METAL GATE MOS 2400 SERIES 


EXCERPT FROM SOFTWARE PACKAGE (CARD FORMAT) 


EXAMPLE: 
CARD 1 . CARDS 2 THROUGH 129 (4 X 256 Organization onty) CARD 1 
LUMN DATA Meta seen : 
18 STARTING AT COLUMN 1 PUNCH “CODED” : Fine od asecten Oa CODED 101 SX266 TTL N2436Y SIGNETICS HAS THE FASTEST R.0.M.'s 
OR “SINGLE” 0 008 wee 8 base 6 tea 
oAy HA cee ue Ale tt eo EACH CARD SPECIFIES THE OUTPUT OF TWO 4-BIT r) a 8 i] een 
BLANK. WORDS IN COLUMNS 1 THROUGH 8, THE DECIMAL doroonooogooogoono BO | Oe Oe) DY TY LY 
12 LEAVE BLANK EQUIVALENT OF THE BINARY CODED INPUT oo. Sede SPreTrTTreartEestrrrrrnrrririienriririi titi tt Crt TOLLE ULE 
aay PUNCH THE HOA ORGANIZATION DESIRED ADDRESS IS PUNCHED IN COLUMNS 78, 79, AND 80. Wneiiigl IQUUTeCUtredUUUitt ttt etdTiLer tide tQheveii@eeeetiiitutiirtieuei ite 
wa @X 256 4X §12. ETC. 
18 BLANK COLUMN DATA 
1921 PUNCH MOS FOR AN MOS OUTPUT 14 PUNCH OL'TPUT FOR WORDS 0 255 
PUNCH TTL FOR A TTL OUTPUT IBARE 58 PUNCH OUTPUT FOR WORDS 256 511 THE ABOVE SPECIFIES A “CODED” ROM WITH THE BINARY CODED CHIP SELECT “101” ORGANIZED 8 X 256 
2227 acne. see Rutt beena WITH TTL OUTPUTS (BARE DRAIN). THE BASIC DEVICE TYPE IS A N2436Y (“Y" INDICATES A 24-PIN CERAMIC 
Fi NCH IMAL EQUIVALENT OF BINARY a 2 
2833 PUNCH THE BASIC DEVICE TYPE DESIRED CODED INPUT ADDRESS OF THE WORD COR - DIP. N INDICATES TEMPERATURE RANGE: -25 C -— +70°C.) 
te, N2410t N2470V ETL RESPONDING TO THE OUTPUTS PUNCHED IN 
3480 COMMENTS PUNCHED HERE WILL APPEAR COLUMNS 1 4. 
AS THE TITLE ON THE TRUTH TABLE COLUMN 78 HUNDREDS DIGIT 
THIS SHOULD INCLUDE CUSTOMER PART COLUMN 79 TENS DIGIT 
IDENTIFICATION COLUMN 80 UNITS DIGIT 


EXAMPLE: 
CARDS 2-129 AND CARDS 2-257 


* CEg, CEa and CE, respectively 


CARD 2 THROUGH 129 (8 X 1280 rganization) CARDS 2 THROUGH 257(4 X 512 Organization only) 
2 THROUGH 256 (8 X 256 Organization) 
EACH CARD SPECIFIES THE OUTPUT OF ONE 8-BIT EACH CARD SPECIFIES THE OUTPUT OF TWO 4-B1T 
WORD IN COLUMNS 1 THROUGH 8. THE DECIMAL. WORDS IN COLUMNS 1 THROUGH 8. THE DECIMAL 
EQUIVALENT OF THE BINARY CODED INPUT ADDRESS 
EQUIVALENT OF THE BINARY CODED INPUT 70101010 

FOR THAT WORD IS PUNCHED IN COLUMNS 78, 79 AND 80 ADDRESS IS PUNCHES tN COLUMNS 78, 79, AND 80. 
COLUMNS DATA 
18 PUNCH OUTPUTS B1 THROUGH 88 IN COLUMN DATA : 

COLUMNS ONE THROUGH EIGHT RESPECTIVELY 14 PUNCH OUTPUT FOR WORDS 0 127 
977 LEAVE BLANK 58 PUNCH OUTPUT FOR WORDS 128-255 
78 80 PUNCH DECIMAL EQUIVALENT OF BINARY 9-77 LEAVE BLANK 

000 6 900000000000000000000 

CODED INPUT ADDRESS nncn CORRES 7000 PUNCH DECIMAL EQUIVALENT OF BIMARY evenpepgunencencencavuncensonggauenuccaagasuuauccsgeauesezuonueyeesueseene gad 

COLUMNS 18. May ay lage TO THE OU True PuNcHED In) COLUMNS (a PTT EAT LERARR SEER ER ERED ERED ORAS OUREROUOIOORUDOOEROOES OO OS TUR CROROT OSS R ELST ED 

COLUMN 78 HUNDREDS DIGIT COLUMN 78 HUNDREDS DIGIT ; 

COLUMN 79 TENS DIGIT COLUMN 79-TENS DIGIT 

COLUMN 80 UNITS DIGIT COLUMN 80-UNITS O1GIT 

«= OUTPUTS B1 THROUGH B8 ARE IN COLUMNS 1 THROUGH 8 RESPECTIVELY. 
€XAMPLE: ® DECIMAL EQUIVALENT OF BINARY CODED INPUT ADDRESS IS IN COLUMNS 78, 79, AND 80. 
ADDRESS CARDS « FOR 8 X 128 AND 8 X 256 ORGANIZATIONS — OUTPUTS ARE 81 THROUGH B8 RESPECTIVELY. 
® FOR 4X 512 ORGANIZATION: 


ATTN: THE PERSON'S NAME WHO WILL REVIEW THE TRUTH TABLE 
at un 8 ooe © O88 08 t 
CITY STATE ZIP CODE 


DATA CARDO WORD 000 OUTPUTS B1 THROUGH B4 RESPECTIVELY 

WORD 256 OUTPUTS B85 THROUGH B8 RESPECTIVELY 
DATACARD 10 WORD 010 OUTPUTS B1 THROUGH 84 RESPECTIVELY 
yale = aL WORD 266 OUTPUTS B5 THROUGH B8 RESPECTIVELY 
STREET ADDRESS 


oa see e ETC. 


FOR 4 X 256 ORGANIZATION: 


YOUR COMPANY'S NAME 
a on oa 
ou sae bt DATACARDO WORD 000 OUTPUTS 81 THROUGH B4 RESPECTIVELY 
WORD 128 OUTPUTS B5 THROUGH B8 RESPECTIVELY 
4 ouooog |oorosrorovooocneoon onde HOOCDONO ODOC OOOCOUNDNDNDNNNDNDNIENND 
t HA bee ‘ ‘ t ere tae Dene Nee bee SON Meee OT ee EY | DATACARD 10 WORD 010 OUTPUTS B1 THROUGH 64 RESPECTIVELY 
TRRERAEET OT TRAE Te PUTASTRETATORNRERUTATLOTROTOTTORIRTATROTSETORTOTIORIEAIES WORD 138 OUTPUTS BS THROUGH 88 RESPECTIVELY 


PACKAGE INFORMATION 


Y PACKAGE | PACKAGE 


LEAD NO. 1 
® 


boner | 


WHEN FORMED 
PARALLEL 


Ft ore 


1, The true-position pin spacing is 0.100 
between centerlines. Each pin centerline 
is located within +0.010 of its true 
longitudinal position relative to pins 1 


1. Lead Material: Kovar or Rodar, gold plated. 9 A a es 


2. Body Material: Kovar or Rodar top and bottom with glass seal. 
3. Lid Material: Kovar or Rodar with braze seal. 


® Tolerances non-cumulstive. 
®© Signetic symbol denotes lead No. 1 


SInGics 
il} i is 


119 


SECTION 


MOS SURE 
883 PROGRAM 


J 


120 


QUALIFICATION AND SCREENING 
PROGRAM FOR MOS DEVICES 


The Signetics SURE*/883 Program consists of a com- 
bination of 100 percent and statistical sample tests designed 
to assure specified performance, continuing uniformity, 
and long term reliability of Signetics products. These 
tests are made regularly at no extra cost to the user and are 
performed in addition to the 40 quality assurance inspect- 
ions and tests to which every circuit is subjected before 
final seal. The tests, tabulated below the specifier’s con- 
venience, are performed in accordance with the following 
conditions, sequence, and schedules on equipment cali- 
brated to meet all requirements of MIL-Q-9858A and 
MIL-C-45662A. 


Every circuit of every lot is processed to the environmental 
screens shown in Table |. These screens are performed in 
production and include 100% final production electrical 
test. Any unit failing either the environmental screens or 
the final production electrical tests is rejected and removed 
from the lot. 


After completion of Table | tests, each manufacturing lot 
is sampled and tested by Quality Assurance for confor- 
mance to the requirements of Table I!. The unsampled 
portion of the lot is held pending acceptance of the lot 
sample. Detailed test limits and conditions applicable to 
test group are shown in the Electrical Characteristics table 
of the individual part type data sheets. 


Tables I!1, and IV provide a complete process qualification 
and verification program. These tests are performed once in 
every 90 day manufacturing period, on representative de- 
vices from each standard production die process family and 
on each production package family. The representative 
circuits and packages selected are changed routinely, and 
the tests performed monitor and qualify all structurally 


MOS SURE 883 PROGRAM 


similar devices produced by the same process and pro- 
duction during that period. 


All of the applicable Electrical Parameters on the data 
sheets are performed at pretest on the Table |V samples. 
These tests are performed on representative circuit types 
from every die process family type in manufacturing during 
this period. 


Table Il consists of the Package oriented qualification 
environmental stress tests of MIL-STD-883, Groups B and C. 
Representative samples from each package product family 
type are monitored and qualified every 90 day period by 
these tests. A common device is used as the die type for 
these package and assembly qualification tests. 


Table IV consists of the die process oriented quali- 
fication electrical stress or operational tests at high tem- 
perature. Representative devices from each die process are 
monitored and qualified every 90 day period by these tests. 
The package type is randomly selected as applicable. 


TABLE | — 100% PRODUCTION SCREEN TESTS 


TEST CONDITIONS 


High Power 

Low Power 

Liquid to Liquid 

5 Cycles; 60 Seconds at 0°C, 
60 Seconds at 100°C, Transfer 


Preseal Visual 


Thermal Shock 


Time 5 Seconds. Note 1. 
Y4 Axis; 30,000 G Minimum 1 
Minute. Note 1. 


Gross Leak Test (Bubble Test) 
Note 7. 


Centrifuge 
Hermeticity 


Production 


Electrical Tests AC and DC, Tp = 25°C 


NOTE: 
1. Not applicable to solid molded packaged devices. 


TABLE I! — SIGNETICS ACCEPTANCE TESTS (See Notes 2 and 3) 


TEST GROUP CONDITIONS MIL-STD-105 INSPECTION LEVEL 


MIL-STD-883 
Method 2009 


Ta = +25°C 
Ta= 70°C 
DC Parameters Ta = o°c 
Ta = +25°C 


Visual and Mechanical 
Inspection 


DC Parameters 


DC Parameters 


AC Parameters 


NOTES: 


*Systematic Uniformity and Reliability Evaluation 


2. All test equipment calibrated to meet requirements of MIL-OQ-9858A and MIL-C-45662A. 
3. Detailed tests, conditions, and limits applicable to each test group are given in the Signetics data sheet ELECTRICAL 


CHARACTERISTICS table. 


MOS SURE 883 PROGRAM 


TABLE Il — MItL-STD-833 GROUPS B AND C ENVIRONMENTAL TESTS 


TEST DESCRIPTION MIL-STD-833 METHOD CONDITIONS LTPD 


Physical Dimensions 


Marking Permanency 
Visual and Mechanical 
Bond Strength 


Solderability 


Lead Fatigue 
Hermeticity 
a. Fine 
b. Gross 


Pre-Test Electrical 
Parameters 


Thermal Shock 


Temperature Cycle 


Moisture Resistance 
End Point Electrical 


Parameters 
FAILURE CRITERIA | 


Pre-Test Electrical 
Parameters 


Mechanical Shock 
Vibration Variable Frequency 
Constant Acceleration 


End Point Electrical 
Parameters 


FAILURE CRITERIA 
Salt Atmosphere 


Pre-Test Electical 
Parameters 


High Temperature Storage 


End Point Electrical 
Parameters 


FAILURE CRITERIA 


NOTE: 


4. The hermeticity tests are not employed for solid molded packages. 


Test Condition A 


Test Condition B, Para. 3.2.1 4 devices/no failures 
Test Condition B 1 device/no failures 
Test Condition D, Para. 3.7 15 


Solder Temperature 
260°C +10°C 


Test Condition Bo 
Note 4 

Test Condition A or B 
Test Condition C 


Table V as Applicable 
15 Cycles. Test Condition C, 
+150°C to -65°C 


10 Cycles. Test Condition C, 
+150°C to -65°C 


Omit Vibration and Initial 
Conditioning 


Table V as Applicable 
Refer to Table V 


Table V as Applicable 


Test Condition B 
Test Condition A 


Table V as Applicable 


Refer to Table V 


Test Condition A. Omit 
Initial Conditioning. 


Table V as Applicable 
Ta =+150°C, t = 1000 hours 
Table V as Applicable 


Refer to Table V 


MOS SURE 883 PROGRAM 


TABLE IV — HIGH TEMPERATURE OPERATING LIFE TESTS. 


TEST DESCRIPTION CONDITIONS LTPD 


Pre~Test Electrical Parameters Refer to Table V 


Operating Life Ta = 70°C; t= 1000 hours 
Shift Registers Logic 1‘s Clocked Through Register 
ROMs, RAMs Addresses Being Counted Through in a Binary Fashion 


TABLE V — SIGNETICS FAILURE CRITERIA 
SHIFT REGISTERS 


TEST INPUT LEAKAGE fp 1"" LEVELS "0" LEVELS 
ee 5X or 100nA whichever Data Sheet 


ROMs 


TEST 


Delta Limit 


INPUT LEAKAGE CLOCK LEAKAGE ipa | “41” LEVELS "0" LEVELS 
5X or 100nA whichever 5X or 100nA whichever 
Is greater is greater 


RAMs 
TEST INPUT LEAKAGE | taccess | ""1"" LEVELS “0” LEVELS 
is greater Limits 


*Eor dynamic memories. 


123 


PTT HA | 
ill Sal ; 124 


125 


SECTION 


MOS/ROM PROGRAMMING 
SOFTWARE INFORMATION 


126 


COMPANY 

ADDRESS 

CIP 2 SS STATE ZIP 
TEL. 

AUTHORIZED SIGNATURE 

BASIC PRODUCT TYPE 

DATE 

CUSTOMER PRINT OR 1.D. NUMBER 
PURCHASE ORDER NUMBER 


BASIC INFORMATION 


= pevice type n24 L_] L_] 
= NUMBER OF CHIP sELecTs |_]1 L_]3 
= cHiPSELECT CODE |_| ce3 L_] ceo | Icey 
=» output Device |_| mos RESISTOR 
L TTL (Bare Drain) 
= ORGANIZATION [_] 8x 256 |_|4x512 
[18x 128 [_] 4x 256 
= PACKAGE [_]16PiN [_] 24 PIN 
= LOGIC “1” MORE NEGATIVE VOLTAGE 
LOGIC “2 MORE POSITIVE VOLTAGE 
m INSTRUCTIONS FOR COMPLETING TRUTH TABLE 
(Required only if computer punch cards are not used) 


FOR 8 X 256 USE COLUMN | ADDRESS— OUTPUTS 
B1i—B8 

FOR 8 X 128 USE COLUMN | ADDRESS— OUTPUTS 
B1—B8 

FOR 4 X 256 USE COLUMN | ADDRESS WORDS 
0-127, OUTPUTS B1—B4; COLUMN I! ADDRESS 
WORDS 128-255, OUTPUTS B5—B8 

FOR 4 X 512 USE COLUMN I ADDRESS WORDS 


0—255, OUTPUTS B1—B4; COLUMN II! ADDRESS 
WORDS 256-511, OUTPUTS B5—B8 


ORGANIZATION 


The Signetics 2400 Series is a family of read-only memories. 
The 2410, 2420, and 2430 Series are offered with the fol- 
lowing organizations. — 


127 


CUSTOM CODING INFORMATION 
2400 SERIES STATIC READ-ONLY MEMORIES 


2410 Series- 1024 bit read-only 
memory organized as 256 words 
of 4 bits in a 16 pin dip. 


2420 


2420 Series- 1024 bit read-only 
memory organized a 128 words 
by 8 bits or 256 words by 4 bits 

If the 256 words by 4 organization 
is specified outputs wil! appear on 
pins 4, 6, 8, and 10. 


2430 Series- 2048 bit read-only 
memory organized as 256 words by 
8 bits or 512 words by 4 bits. If the 
512 word by 4 organization is speci- 
fied outputs will appear on pins 4, 
6, 8, and 10, 


2400 SERIES STATIC READ-ONLY MEMORIES 


ROM SELECTION CHART 


TYPE ORGANIZATION | packace | OUTPUTS CHIP SELECT CONTROLS 


256 x 4 
256 x 4 
128 x 8, 256 x 4 
128 x 8, 256 x 4 


N24101 
N24111 
N2420Y 
N2421Y 
N2425Y 
N2426Y 
N2430Y 
N2431Y 
N2435Y 
N2436Y 


16-Pin Ceramic DIP 
16-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 
24-Pin Ceramic DIP 


MOS Pull-up 1 
Bare Drain 1 
MOS Pull-up 1 
Bare Drain 1 
MOS Pull-up 3 (binary coded) * 
Bare Drain 3 (binary coded) * 
MOS Pull-up . 1 
Bare Drain 1 
MOS Pull-up 3 (binary coded) * 
Bare Drain 3 (binary coded) * 


128 x 8, 256 x 4 
128 x 8, 256 x 4 
512 x 4, 256 x 8 
512 x 4, 256 x 8 
512 x 4, 256 x 8 
512 x 4, 256 x 8 


*Mask Programmable 


CIRCUIT OPTION 


The following circuit options are available for the user’s 
particular needs: 


OUTPUT BUFFER 

For all series the user has the option of MOS or TTL 

outputs. This must be specified by the user. 

= MOS output- an output having an MOS resistor con- 
nected to Vpp. This allows interfacing with other 
MOS devices. . 

= TTL output- an output having no MOS resistor con- 
nected to Vpp. Commonly called a ‘‘bare drain’ 
output; this allows direct interfacing with TTL 
circuits and external ‘‘wired AND” capability. 


CHIP SELECT 


mw “Single’’ ROM- one which has only one chip select. A 
logical ‘‘0’’ on the chip select line places all outputs in 
the ‘1’ state (or open-circuited in the case of a’ TTL” 
output). 

™ ‘‘Coded’’ ROM- one which has a three digit binary code 
chip select. This allows paralleling up to eight devices 
without external chip select logic thereby allowing the 
user to save the cost of extra packages and PC board 
space. 

@ 2410 Series may only be ordered as a “‘single’’ ROM 
(one chip select). 

@ 2420 and 2430 Series may be ordered as “single” or 
“‘coded’’ ROM’s (one chip select or three chip selects). 


DEFINITIONS 


Logic definition: 

All logic is assumed negative 
“0” is the more positive voltage 
“1"" is the more negative voltage 


128 


Input definition: 
Al is the least significant input address 
A8 is the most significant input address 


INPUT FORMAT 


Programming information for Signetics’ 2400 Series should 
be transmitted to Signetics in the form of computer 
punched cards accompanied by information on the various 
circuit options desired. Upon receipt of each deck 
and the circuit option desired for that deck a computer gen- 
erated truth table will be made and a copy of this truth 
table returned to the customer. This minimizes the possi- 
bility of error and allows the best possible delivery (nor- 
mally 4 weeks after receipt of card deck). 


Upon receipt of the computer generated truth table check 
it carefully and if any errors are discovered notify Signetics 
immediately. 


The Signetics’ 2400 Series Read-Only Memory can be pro- 
grammed so that for any binary input A1 through A8 the 
outputs B1 through B8 are uniquely determined. Each 
deck of cards sent to Signetics must contain a card des- 
cribing the options desired (card 1), the unique outputs for 
each word in- memory (cards 2 through 129 or 257, de- 
pending on organization), and cards specifying the address 
to which the computer generated truth table should be 
sent. Cards should be punched according to the format on 
the following pages. 


If it is not feasible to use computer punched cards, the user 
should describe the circuit option desired and complete 
the truth table. Upon receipt of pages Signetics will punch 
the computer cards and return a copy of the computer 
generated truth table, (the user can realize a substantial 
savings associated with the coding charge by using com- 
puter cards). 


CARD 1 

COLUMN DATA 

1-8 Starting at column 1- punch “coded” or 
“single”’ 

9-11* If ‘coded’, punch the binary code chip 


select (i.e., 101), if ‘‘single’’ leave blank 
12 Leave blank 
13-17 Punch the ROM organization desired (i.e., 
8 X 256, 4 X 512), etc. 
18 Leave blank 


19-21 Punch MOS for an MOS output. Punch TTL 
for a TTL output (bare drain) 

22-27 Leave blank (For CM No.) 

28-33 Punch the basic device type desired (i.e., 
N24101, N2420Y), etc. 

34-80 Comments punched here will appear as the 


title on the truth table. This should include 
customer part identification 


*CE3, CE2 and CE] respectively 


CARD 2 THROUGH 129 (8 X 128 Organization) 
2 THROUGH 257 (8 X 256 Organization) 


Each card specifies the output of one 98-bit word in 
columns 1 through 8. The decimal equivalent of the binary 
coded input address for that word is punched in columns 
78, 79, and 80. 


COLUMN DATA 

1-8 Punch outputs B1 through B8 in columns 
one through eight respectively 

9-77 Leave blank 

78-80 Punch decimal equivalent of binary coded 


input address which corresponds to the 
outputs punched in Columns 1-8 


Column 78- Hundreds Digit 
Column 79- Tens Digit 
Column 80- Units Digit 


129 


2400 SERIES STATIC READ-ONLY MEMORIES 


CARDS 2 THROUGH 257 
(4 X 512 Organization only) 


Each card specifies the output of two 4-bit words in 
columns 1 through 8. The decimal equivalent of the bi- 
nary coded input address is punched in columns 78. 79, 


and 80. 


COLUMN DATA 

1-4 Punch output for words 0-255 

5-8 Punch output for words 256-511 

9-77 Leave blank 

78-8 Punch decimal equivalent of binary coded 


input address of the word corresponding to 
the outputs punched in Columns 1-4 


Column 78- Hundreds Digit . 
Column 79- Tens Digit 
Column 80- Units Digit 


CARDS 2 THROUGH 129 
(4 X 256 Organization only) 


Each card specifies the output of two 4-bit words in 
columns 1 through 8. The decimal equivalent of the binary 
coded input address is punched in columns 78, 79, and 80. 


COLUMN DATA 

1-4 Punch output for words 0-127 

5-8 Punch output for words 128-255 

9-77 Leave blank 

78-80 Punch decimal equivalent of binary coded 


input address corresponding to the outputs 
punched in Columns 1-4 


Column 78-Hundreds Digit 
Column 79- Tens Digit 
Column 80- Units Digit 


2400 SERIES STATIC READ-ONLY MEMORIES 


EXAMPLE CARDS: 
ADDRESS CARDS 


ATTN: THE PERSON'S NAME WHO WILL REVIEW THE TRUTH TABLE 
un | aoe | ee | Le. 
C CITY STATE ZIPCODE 


C STREET ADDRESS 

a | LL 

C YOUR COMPANY'S NAME 

7 | as 

oan 8 as 

0000606 0000000000000000000000000000000000000000000000000000000000000000 


VOU I2 13 1S 15 16 7 18-19 25 20-25 26-25 25 26 27 2029 30 3) 32-33 34-35 36 37 30 39 Sb 41 42 43 46 OS OG 47 48 43 30 5! 525754 S5 5657 5059 EUG! 6253 KE G5 66 67 C8O9 70:71 72:19:70 75 76:77 1879 OO 


PUM UV VED AIM UVP PETE ed 


— = & 
— ww = 
_— = 
—ee 
—o_ 
—°7o 
—~oQ 
—_ @ G&G 
—_— 2. & 


CODED 101 8X256 TTL N2436Y SIGNETICS HAS THE FASTEST R.O.M.'s 
Baan CT | | | | 


a a a i | 
COOOOHOOOMOCOM ODO MMOCCOOOOKOOOM MOM OOOO OCOMOOOMO MOC OOOMMOMRO000HOOMODDDOODDONNE 


V2 FOS TO 8 UOTE 13 NG TS Hy TT 1 19 20-25 22 23 26 25 75 27 20 29 WO I 32 32 34 3S 36 TT FO 3S 40 41 42 43-04-45 46 47 40 49 SO St S252 54 SS SE S7 SB SS ORG) 62 62 64 ES 65 67 6068 7071 12797075 71G77 1071998 


PUTTUT EAU UTEP Tee 


The above specifies a ‘‘coded’’ ROM with the binary coded dicates a 24-pin ceramic DIP. N indicates temperature 
chip select 101° organized 8 X 256 with TTL outputs range: -25°C— +70°C). 
(bare drain). The basic device type is a N2436Y (“Y” in- 


CARDS 2-129 AND CARDS 2-257 


10101010 


000 


0000000000000000000000000000000000000000000000000000000000000000000808 


V2 12 34 a 1G VF 1819 2021 22 25 24 2S 26 x7 2029 IW 3) 32 3s 3s 3S 36 37 38 39 0 AD M2 43 44 45 45 27 48 69 SO 51 S253 54:55 56 57 58 $9 0 6) 62 63 64 GS be 67 GOES 7071 72797475 1677 1079 


PEUTUVVT UEP E TEEPE 


™ Qutputs B1 through B8 are in columns 1 through 8 respectively 

respectively Word 266 outputs B5 through B8 
@ Decimal equivalent of binary coded input address is in respectively 

columns 78, 79, and 80 = For 4 X 256 Organization: 


a For 8 X 128 and 8 X 256 organizations- outputs are B1 
through B8 respectively 
™ For 4 X 512 organization: 


Data card 0 Word O00 outputs B1 through B4 
respectively 
Word 128 outputs B5 through B8 


Data card O Word 000 outputs B1 through B4 respectively 
respectively Data card 10 Word 010 outputs B1 through B4 

_ Word 256 outputs BS through B8 respectively 
respectively Word 138 outputs B5 through B8 


Data card 10 Word 010 outputs B1 through B4 . - respectively 


130 


2400 SERIES STATIC READ-ONLY MEMORIES 


ot] mM | oln|o ro) “I tlo|lolnlaolomalolrinini+tlwlol|nijalalo|rjia 
ss SISISlolalVlsSliGBlolole RIRINILIXNIXKIKINIX IRL Ololalalalalalalalialalala 
rat AIAN TAIT AlaAlaAl Aint ada ALAILNIAININI NI AINA NI AIA ANNA AAI NINA A A 
SlelsisiaiSislelSislSlVSliSisiVisis lViSiSiSiViSislQiVis/iBliSlsisisisisigisis 
elie ierltie tele le lei ele le le ie lef e dete fete pepe leper pele pe pe pepe pe le le pe pel eee 
t1 0 | 2|o S |S} 21g 
ete ier fei eie ole lirics 
o!lo o1o 


—-|/O;~r | Olr!|o O;r ll Ooj;rj Or oj;jr! o;rl or;rryoj;yr! oOo 


0 0 
0 
1 
1 
0 
0 
1 
1 
0 
0 
1 
1 
0 
0 
1 
1 
0 
0 
1 
1 
0 
0 
1 
1 
0 
0 
1 
1 
0 


1 


eS eel 
A8 A7 AG AS Ad A3 A2 At | Ba | 
0000000 Ls 
0000000 257 Ew 
0000001 | 
000000 1 ae 
000001 0 Ld 
000001 0 _—_ 
La 
Eo 
ee 
oe 
= 
= 
a 
ae 
_ 
a 
ae 
~ 
a 
ae 
~~ 
a 
Ed 
ae 
ae 
a 
Eas! 
a 
a 
= 
iw 
= 
ow 
az 
etd 
Ea 
— 


00000 1 
0 
0 


0 
0 
00 0 0 


131 


2400 SERIES STATIC READ-ONLY MEMORIES 


ACTER 


Orr !/Oo;jr!]olr 


oe 2] x 
wD | 1B 
=) 


rilrl ol;lo|lrir mir |/O!;}Oojr{t rs] oOo rir f/Ol;OoO;rf[ry oj;olrir 


ee Tika cena Hie mecoli i cee OO mee OO ee meee ee OO ce OO ee OO ee Oa ee Oe mee OO oe Deed 


I I a ON Oe Oe ee ee cee ce One Oe ee ee Oa ee ee ee ee ee Oe Oe Oe 


Dt i mee i ee ed el ee OE cee ne so) 


A8 A7 AG A5 A4 A3 A2 At 


= 
pm | Bt 
3] 
| 
| 
| 
7 | 
| 
| 
oo} | 
or a 
| 
o{ | 
4} 
| | 
of 
oF 
oe] 
of 
ae 
—_ 
—_ 
od 
Lo 
5{| | 
fo 
a 
2 
etl 
boa 
_ 
22{ 
23{ 
24{ 
| | 
| 
a7 | 
2e{ 
2] 


o ‘ 


132 


2400 SERIES STATIC READ-ONLY MEMORIES 


ADDRESS DECIMAL USER’ 
INPUT GATE ADDRESS OE TEP T RATA CHAR 


A8 A7 AG AS AG AZAZA1| 1 | It | 


Ss 


ACTER 


co 

is] 

i 

a 

QDITININI TIL MOSLOIL RI ODI DLO; ri NI VYDITILWOlLOlLMWIL ODI AIL OLTrININITFTIPOLS OI M/S DION Os rINIMit{ | woO!lo 
Al/MD1M, DI MI DI VDI NDI NI YDNiIyF sy yy TF TI SPT SL PL TF POLO MOwoOl]MOjyOl;/MOlL/MmM; wl] wolsl,o;oO;Oo};O!]O}]O}O 
Coes OS? Os oe Bn POP Ok OP OO SP OP SP PP SP PPP SP PPP 0 SP OP 0 9) 
NI/O TI MWOlSO!LM DI AIO; r INI OID OSOILMIL DIDILO!;rINI/OI/YTlLMWOS/OLBR | DI DIO; |r InI Dis; O;/O!;]m]a@ 
O;oO; ofl ol; ol; oo; ;os;olririririlri irl rjroflrin ATNTN EN ENE NIT NTE NTE NEN OTOL OTOL OOO] OS 
NIENEN IT NENT NIENTEN TEN TEN TNE NEN ENT NIN TEN ITN INT NITN IN IE NY N INN NENT NIN ITN IN INI NIN INI N 
WO OI BI DIO; Ol er INI DMiIiT WwW] O;K | Oa] ® —-I1A1 Oo Ns | @ O;r in MitlL wool oye!) d|Q|o 
Mi NmMIBNIT RI &m | O};]O]O}]0O;}0O!10;,0O)]O| 0! 0 O;1D| oD ome?) O;,ro;/o;o!1oa;o;o/;o!;o!;ojyr 
O1o;/OoO;OoO;O;/o;oO};o};}o!1o;o;o!l1o;o;o oO;o|}o O;O;Oyr yr lr pr yer pr priprper i ries 
rlol[(rs/OoOlrsl/ojrsl ol;lrs oitr|] oOo rl/olr Oller l/Ojrlol;rj olrslolrio 


- | Olr | OoOljrl|l otr | oOo 


074 


© rir} ol}; ol;rrsi rj] o;}olr 


0 1 0 
1 
0 
0 
1 
1 
0 
0 


© 
repre il epee rpr pr pere pepe le rel ryprierlielie 


De A ee el ce ee I ee OE ee ee ee DO ee ee OO ee ed 


Doel A eel i eel el ee 


De i aeeetin I OO ee Do NO oe ee ee ee Oe Oe ee Oe Oe ee ee Oe ee 2 nee el ee ee ee 


133 


2400 SERIES STATIC READ-ONLY MEMORIES 


< 
- 
< 
Q 
~ 
=) 
ou 
- 
— 
Oo 


DECIMAL 
ADDRESS - 


ADDRESS 


INPUT GATE 
A8 A7 AG AS A4 A3 A2 Al 
0 


ts] 
is] 
N 
a 


> | . 
rlOlr[| oOo oOlrliolrflolrlo}Jrjjol/r]lol lr lol;rflOoOlrs Oller fOr fOr Or PO;yr Orr l/O;ry oir: 
-lololr ler lolole ir lOlolrf[rfolojer {fe fosoljrfy rH lOlsOtr yr Ol;Oolr [rH yoOo;Oyr {rs} O;oyryr] 
ri Djiosl/os;o jo ;o;;o;yoyrwyrPryryrypryryr o1;o;o ol ;o;o;o;orr{eryariririririe) ° Oo;o;o . 

Dn a ee le Oe el 0 ee ee teirilrier f OF] OCFOPOl;o;ol rol; oflro;o;ro;o; o;o,; oro; iri~rjrijnr 
mlm le Perper pr yer pepe pe prepa detierfeilrlolholol~o; os yoa;oy;yo;os;/o;ol;os;o;o;ol;oj;yo;o;o)]o 
Se i ee I Oe a ne 0 ne Dee ee Oe Oe Tejiele lr fl oro !lolro;yoao;lo;o; oo; oa; o1 oa; ;yoy;yos;o;os;so;oj;o;o;o 
O!lLOLOLOLOlLOI!OLOIL/AOILIAOS/OlOOlOlLOlOslO er TPT Pr Pr Prem pr prey er ype ypeeespeeyeypacpe 


134 — 


2400 SERIES STATIC READ-ONLY MEMORIES 


OUTPUT DATA 


135 


TP woOLOoO;.- te 8183 oe ee 
o|S rir lr rp rir dp rp epi 
Tira : 
mpm per pr pr pr per prim pr bm pm pe pr pm ee pe Pm pe re ee pp pe pe Pr pepe pe pe le 


~rlojrlol|rjolr 


DECIMAL 
ADDRESS 


INPUT GATE 
0 0 0 0 


ADDRESS 
A8 A7 A6 AS A4 A3 A2 Al 


2400 SERIES STATIC READ-ONLY MEMORIES 


OUTPUT DATA 


136 


mTINIMI SATILOLO!LNILOD!/ DIO; yr INI YMIiSF WOLOI MIAN lO! /r I N/M SFI MWOlLOl MI BDiDloO;rs NID Tl wo} oO;rR 
Si ETErTETIFI TI TIT I TFILOLHWOIL[WOLOLWOLWOLMOS/MO[WL/WILOIO;/O!}/O;/O!}/O;/O/O;/ OORT RI eR RI ee ei’ 
DB OO OO OS OO SO OS OS OS OO 2 OS OD SD Ds 2 Ds 


DECIMAL 
ADDRESS 


0000 0 1 


ADDRESS 
INPUT GATE 
A8 A7 A6 A5 A4 A3 A2 At 


2400 SERIES STATIC READ-ONLY MEMORIES 


ou . 
rea 
nro 
Soc 


© 


137 


a 
a 
a 
feat 
ian 
- 
Ea 
al 
ad 
dl 
= 
al 
are 
iad 
— 
—_ 
wl 
fc 
onal 
~ 
i 
peed 
aoe 
= 
| 
_ 
a 
ease 
oe! 


00 0 0 
00 0 0 
000 1 
000 1 
00 1 0 
00 1 0 
0 0 1 
0 0 0 
0 0 1 
00 1 
01 0 
0 1 


8] 8]8)8|8 [8 8 8 &)8]8 8/8 [8/8 8/8 8) 8/2 |2[8 [2/8 5/2] 8) 8) [8 |e la/e 
NIENEN ENE NTN TENT N TEN ENT NEN ENN TNL NENT NTN NIN INI NIE NIN INIT NIE NT NEN LET NL IN 
oO O;rflo;rr{ Orr; OoO;rs ojrjJolr sl olrsio oO;r;olrr|]o 

_ 

— 

_ 

_ 

oO 


mr rr} olr 

rr rir (Oo; Oorri rt o;o;jrirsto oOjir 

5 es rl} ol;~ol;o;oyrltlriryrt oOo - 

r Olrfijrijyri[rirfririer (or) © 

rr CIOl/Ol/OlD/OlOloOlole {rire fri refer fete | ele te lel ele 

ee Oe (eed rene recy rer (ere ames amr eeae pen (ome ere omy rer (gen Din ere emg: Pr een Ge eg Pn- tes em! ieee mee ey penis bere eee 

ee Oem ee ee Oe Oe ee Oe OO Oe ee Oe Oe Oe Oe OO ce 0 ee ee ee 0 ee el Oe ee 
eel Oa sae OO ei Oe ce OO ne eee OO ee ee ee eB el 0 ed ee ed OO ne ed Oe 0 frprpryprpr reper ypryprie 


AB A7AGASAGAZAZA1| 1 | ne | Mm, 


ADDRESS DECIMAL 
INPUT GATE ADDRESS 


— SUNETES : 


CUSTOM CODING INFURNIALTIUIN 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


COMPANY 

ADDRESS 

CITY. 

TELEPHONE 
AUTHORIZED SIGNATURE 
DATE 

CUSTOMER PRINT OR ID NO. 

PURCHASE ORDER NUMBER 

DEVICE TYPE 2413 2415____ 
CUSTOM PATTERN NUMBER (TO BE ENTERED BY 
SIGNETICS) 


STATE ZIP__ 


INTRODUCTION 


The Signetics 2513 and 2514 are high speed silicon gate 
MOS 2560-Bit read-only memories whose organizations 
are specially suited for 64 X 8 X 5 raster scan character 
generation. 


MAJOR FEATURES OF THE 2513 AND 2514 


m ACCESS TIME 450ns TYPICALLY 
B® STATIC OPERATION 

8 TTL/DTL COMPATIBLE 
| 


TRI-STATE OUTPUTS (HIGH-LOW-DISCONNECTED) 
FOR POWERFUL BUSSING CAPABILITY 


+5, -5, ~12V POWER SUPPLIES 

24-PIN SIGNETICS SILICONE DIP 

@ SIGNETICS SILICON GATE PROCESS TECHNOLOGY 
FOR PERFORMANCE AND RELIABILITY 


ORGANIZATION AS 
CHARACTER GENERATOR 


A six-bit binary address (Aq through Ag) selects 1-of-64 
matrix characters arranged 5 dots horizontally and 8 dots 
vertically. A three bit binary address code (A through A3) 
selects 1 of 8 rows. Five outputs display a complete row of 
the character matrix. See Figure 1. The devices may also be 
used in pairs to provide 9 X 7 and 10 X 8 vertical scan 
formats. 


139 


CHARACTER FORMAT 


ROW ADDRESS 


ROW ADDRESS 


Os Oq4 03 O2 


EXAMPLE ‘S' 


FIGURE 1 


CHARACTER ADDRESS 


COLUMN ADDRESS 


4 [45 [40] 47 | 40] Ao] 
ASCII 
CHARACTER 


FIGURE 2 


ORGANIZATION AS READ-ONLY MEMORY 


For a straight 512 X 5 read-only memory, the five outputs 
will display any one of 512 5-bit stored words correspond- 
ing toa 9-bit address applied to Ay through Ag; 


DEVICE TYPE SELECTION 


The only difference between the 2513 and 2514 consists of 
a separate Vpp terminal for the output device on the 2514. 
This feature allows flexibility in power dissipation and out- 
put “0” voltage level. Otherwise the 2513 and 2514 may ke 
used as either straight ROMs or character generators. 


2513 STATIC CHARACTER GENERATOR &® 2514 STATIC READ-ONLY MEMORY 


PIN CONFIGURATION (Top View) 


. NC 

. Address 1 

. Address 2 
. Address 3 
. Address 4 
. Address 5 
. Address 6 
. Address 7 
. Address 8 
. Address 9 


. Chip Enable 23: ves 
. Vopo . cc 


OMNAARYN 3 


. NC 

. Address 1 
. Address 2 
. Address 3 
. Address 4 
. Address 5 
. Address 6 
. Address 7 
. Address 8 
. Address 9 
10. i . NC 

11. Vv 


cc 
12. Vv 


Qn OQsaon > 


© 


PACKAGE INFORMATION 


NX PACKAGE 


WHEN FORMED PARALLEL 
045 
085 


RT 


be 160" ETOE 


NOTE 3 


NOTES: 


1. Lead material: Kovar, solder coated. 

2. Body material: Silicone molded. 

3. Tolerances non-cumulative. 

4, Lead spacing shall be measured within this zone. 
5. Body dimensions do not include molding flash. 
6. Signetics symbol denotes lead No. 1. 


140 


STANDARD PATTERN 


A standard ASCII character font is available for the 2513. 
This device (2513NX/CM2140) may be used for ASCII 
character generation or for device evaluation. 


CUSTOM DEVICES 


For unique custom memory patterns, this form should be 
used to transmit coding instructions. The nomenclature for 
a custom device will consist of the basic product type 
followed by a unique CM number assigned by Signetics. For 
example, ‘’'2513NX/CM2141”. 


= PROGRAMMING WITH PUNCHED CARDS 
For maximum accuracy and minimum cost and turn- 
around time, the truth table should be transmitted to 
Signetics in the form of punched cards according to 
the format indicated on the following pages. 


= PROGRAMMING WITH WRITTEN TRUTH TABLE 
When punched data cards cannot be supplied, the truth 
table may be transmitted in written form using the 
attached blank truth table. 


VERIFICATION 


Upon receipt of either punched card or written truth table 
information, Signetics will prepare a computer tabulation of 
the instructions and return to the address indicated. If errors 
are detected, they should be transmitted to Signetics as 
quickly as possible. 


LOGIC CONVENTION 


Logic ‘1's or blackened squares in the truth table will result 
in “high’’ output from the indicated output terminal (i.e. 
3.2V minimum). Similarly, a ‘1’ address input level 
is interpreted as 3.2V minimum. 


2513 STATIC CHARACTER GENERATOR 8& 2514 STATIC READ-ONLY MEMORY 
IDENTIFICATION CARDS 


LEAVE COLS. 22, 23, 24, 25 BLANK 
INDICATES “COMMENT” CARD FOR ASSIGNMENT OF CM NO. BY SIGNETICS 


BASIC PART TYPE CUSTOMER P/N IDENTIFICATION 


SIGNETICS 2513NK~CM ACME MEMORIES P/N 135216-1 
ie | eo | | | anon a 

i ot o6 ant | | 
B000000§G0000000000000000000800§00000000000000000000000000000000000000 
102 13 14 15 16 47 16 19 20-24 22 23.26 25 26 21 20 29 30 31 32 99 94 35 38 37 38 39 40.41 42 43 44 45 46 47 48 49 58 SI 52 53 54-55 S6 ST S059 60661 62 62 64 6S 66.67 68.69 70-71 72 13.74 75 76.77 787900 


BRet DORE DROOREOE PORE OROEEEER! LG) ROR! D8) POOR PORE RO PRERReReRnenienn 
tee ee ees 1h eee ee eee eee eee eee eee ees eee eee) Eee eee eee eee eee eee eee eee eee ey: 


PERSON RESPONSIBLE FOR REVIEWING SIGNETICS 
COMPUTER GENERATED TRUTH TABLE 


ATTN. J.@. ENGINEERs MEMORY PROD. NGR. 
i bf Fee | | | 


eto 8 € © oa te 688 
OCOMPOCCOOOD DNC OO OOOO OOOO DOM OOO DOOD OOO DON DDO OOOO ODDO DDD0N DOO ONOO0000000000008 
U2 34S 678 8 UOT 12135415 16.17 18 19 20.21 22 23 26 25 26 27 28 28 30 313233 34 35 36 37 38 39:40 41 42 43-44 45 45 47 48 49:50 SI 5253 54 55 55 ST S859 106) 62 63.64 GS 6667 6869 7071 7273 7475 76-17 107988 
TT TERED) RRR ORE ORRSEORO ROR RDERRORORRERRRORROREREUOSRSRREROSRERSRURRRREESOSRR OER 
22222222222 PEPE e ee eee Ee Tere eee eee eee eee eee ee ee ee eee ee eee eee eee eee eee eee 


- 8000 ELECTRONICS LANE 
| i a6 ao 688 
f ona i 

SO 

eMITUNSHTNNAN AONERD ADH THAN RT AMAR EOUsETUAELTHLANT AMM RAMEEE MARAE DLE 


BORER RROE! DORR ORR R ERR REESE ROSE RE REE EREREEREERRERRERELELEDERERE 
eee etek kkk kkk 2k 222222222 22222222222222222227222222 


~ 


CITY STATE ZIP 


» SUNNYVALEs CALIFORNIA 94086 
| | 

i one 
000000000000000800000000000000000000000000000000000000000000000000000 
12 13 16 15 16 47 10-19 20.21 22 29 24 25 26 27 20 29 30 31 32 33 34-35 3637 38 39 40-41 42 43 44 45 46 47 48 49 S851 S253 54 SS 56 ST S858 60.61 62 6364.65.66 67 68.69.70 71 12.73 7475 7697 1079.08 


0 
" 
BEDE DOROORe! DORO ROPER ROEDER OREO ROE SEER SERRE SEDER ROEDER REE OEE EE REE ER 
geek k kkk kkk kkk kkk kkk 22k 


- ACNE MEMORIES INC. 
pone & 8b ob 


00000000000000000000000000000000000000000000000000000000 


W213 1615 1647 21 22 23 24 25 26 27 28 29 30 31 32.3334 35 36 37 38 39 40 At 42 43 44 45 46 47 48 49 SO St 52.53.5455 56 57 SO SS 606) 62 63 64 65 66 G7 6869 7071 72:73:14 75 76 77 7019 8 


PEDUDDTTTET UE EU DTD T PTT 
re Pee e eee eee eee eee eee eee ee eee rere ee eee eee eee eee ee eee eres eee e eee: 


141 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


DATA CARDS 


CHARACTER NUMBER 
OUTPUTS 05 THROUGH 0, RESPECTIVELY (DATA CARD NUMBER) 


Da 


© 9 1019 22.19 96 15 16 17 06 19 20.21 22 23 26 25 2G 27 20 29 38 31 32 33-34-35 96 37 3039 48 At 42 43:44 45 46 47 48 49.5051 52 53 54.55 56 ST S058 606) 62 63 64 6S 66 G7 GU69 70:71:12 73.7475 7677 1079 08 


1] Rs Rs RO DO? DO PPR Ree! DORR ee eee Sees eee eee eeeeeen 


22k kkk kkk kkk kkk kkk kkk 22222 
3333939333333339333333333933333333393333333333393333333333339333939393339333333333339333333 
OER UCEPPPCECECROCUCECUSTOCORRECUOCOPUOCOCUCUOCEOCOCORE ORC OSECEOCOCOECEOSEEEELER | 
EETEEETESESESLSEELELESESESESESESSSIOIIILELESEESSESESE SESE SESE EE SESS ESESESESIEEE 
CECEEGECE CECE CEE CEC EE CEE CECE CEE CC EEE SECC ECECCESCC CECE EGBG EC CE CGC GHG GE CGE CHEECH CEE 
DETTVTTTTTTTT TTT TT TTT TTT TTT TTT 


ROW ADDRESS . 


000 001 £010 011 100 101 110 111 
HOGG QUALG 2GGGL PGL1L1 LGLGL AGLLL 16060 Gi116 God 


© 8 1012 1213 14 15 16 17 18 19 20-20 22 23 24 25 26 27 20 29 390 31 32 33 34 35 HG 37 30 30 40 At 42 63 44 45 06 AT 48 49 58 SI S253 5455 56 57 5859 6061 6269 64 65 66 67 66G9 707) 72737475 76 77 7879 80 


TT RRO Ree Re TL ae an oe oe be | | ED Pee) | | Pee eRe Re Ree ORE BGRReReeeenn | 
tek kkk lk kkk kkk kk kkk kkk kkk kkk kk 22222222 
33333333333333333333333333333333333333333333333333333333333333333333333333333333 
PRUE PORE EES E CRORE CEE EEOC CCE ECEOCOC OE EC ESOC CECE EPEC E SOC EEC EEOC ECE e eee eee, 
SEEESPEFESESESELESSSSESS SE LESERESISISEISSESESIEISLESEEE EES SESE EE SESE SESESE EEE 
CCCCCBEEGECCECEGGE CECE CBE EEC CCCCECCECC CCC EEOC CCESEE SCC COCKE CCC C EC E6B6CC CC BGG CCGG SEES 
DUTT TT TTT TTT 


OO OO CO OO a) | 
s7e 
11 


BASIC DEVICE TYPE 
LEAVE COLS. 10, 11, 12, 13 BLANK FOR ASSIGNMENT OF CM NO. BY SIGNETICS 


0000000000000 0000000000000 00000000 0ND 


44:45 46 47 48-49 50 51 S2 5354 55 56 S7 5859 60.61 62 63 64 65 66 67 68.69 70 71 7273: 747S 7677 787900 


PUVTTEUT DUTT TTT TTT TET 
| Pee eee eee eee eee ee eee eee eee eee eee eee eee eee eee ee eee eee eee ee eee ee eee ee: 


3339093303333333993393333333333333333333333333933333933333333333333333333333333333 
ERR EEEE! COROSOCO CREE ECOSOC CE CEC OC CCCE CECE CCPC errr eer eeeeeeeee ee eerie rere 
‘TEED FEERERESEEEEEEELESESESELSESSSSISIOSE LSS SSEESESISESEISE SEE EES EE ESSE EEE Eee 
CECE CCCCCCEEG G66 E CECE CEC COC CCGG EGCCCEECEE CCE CCESEG EGE EEE ECCS CSE6C6E6G66EEC CCGG 6666666 
TUTTO TTT 


NOTE: 


“Character’’ number is in columns 78, 79, and 80. Note that each group of eight 5-bit words is treated as a character for convenience 
of coding. 


142 


2513 STATIC CHARACTER GENERATOR &® 2514 STATIC READ-ONLY MEMORY 


OUTPUT DATA 


foe veeeer fom] | 1! 
00019000141 0 
000 100 01 1 
0003100 100 
000100 10 1 
000100 1 1 90 
000100 1 1 1 


OUTPUT DATA 


ssayugav 
IWWID30 


ADDRESS 
AS AS A7 AG AS A4 AZ A2Z Al 


000 000 00 


°o 
°o 
°o 
° 
°o 
°o 
°o 
° 


000000 0 1 
000000 0 1 


000 000 
000000 


0.0 
Qo.0 1 


00 0 0 0 1 
000 00 1 
000 00 1 
000001 
000 00 1 
000001 
000 00 1 
000 00 1 


0 00 


0qQgo O01 


000 0 1 


ooo 0 1 


000 0 1 


ie) 


000 0 1 


ie) 


000 0.1 


1 


000 0 1 


143 


2513 STATIC CHARACTER GENERATOR ® 2514 STATIC READ-ONLY MEMORY 


ea 
us 
8% 


OUTPUT DATA 


ADDRESS 
AS AS A7 AG AS A4 AS AZ Al 
00% 310001 


‘YVHO 


OUTPUT DATA 
wy 


22 
=u 
So 
wa 
aod 


010 01 


oo 1 


feoreceoes fm] | 11]. 
0100001 
00100001 
001000 
00100010 1 
0010001410 
010001 1 


0 


ADDRESS 


AS A8 A7 AB AS A4 AS AZ Al 


144 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


ADDRESS 


AS A8 A7 AG A5 A4 A3 A2 Al 


01010001 


ere eee vee lm] 

ove coe oe: [mm 

ere eee ere | sn 

eve oeo ers {ar 

010000100 f1a2| 010 100 

eveceoverfo] |||] SEREE 
Te) 
har 
re 
re. 


rece ae veda Os 
eve ver sera 


1 
01000 1 01031319014 4114 OfF 1 
ore ort So ote 101 ssf vm 


0101031 00 


0103101 80 


0100310100 
0100310101 


01003101 10 


0100310 14 1 


0100341 01090 


010011 11 0 


145 


2513 STATIC CHARACTER GENERATOR &® 2514 STATIC READ-ONLY MEMORY 


ADDRESS 
AS AS A7 AG.AS5 A4 AZ A2ZA1 


146 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


ADDRESS 
AS AS A7 AGB AS AS AZ A2 Al 


10000010 1 


10000011 41 


1000eOoO18 14114 1 


: 


1000310 4100 


1000310311 41 


147 


aawnnnnan|fe lala [a]o]a [88 
jiee roo ooo| ze} | | | | | 
aeaee 


100 


100010 


1004100011 


1001003100 


100310010 1 


10010071 10 


1003100411 41 


100 101 000 
100101 00 1 
100 01 


101 .¢] 


1003101 01 1 


1003104 100 


Ww i”) w N 
= pad P=) x 
~ a ber} be 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


ADDRESS ADDRESS 


A9 AS A7 AG AS A4A3 A2 Al AS A8 A7 AG AS A4 A3 A2 Al 


101000000 


1010000410 


710100010 1 


101100 100 
00 


1 


°o 


N 
~ 


10100100 
10100101 
101001011 
10100110 


148 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


ADDRESS OUTPUT DATA ADDRESS 


AS AB A7 AB AS AA AZ AZ At AS AB A7 AG AS A4 A3 A2 Al 


ADDRESS 


DECIMAL 
DECIMAL 
ADDRESS 


710000001 


110 000 01 1 | 387 


110000100] a8 
1100003101 


110001 000 


71100041001 


110001 01 


711000101 1 
110001 100 
711000314 101 


7100370000 


7100370001 


149 


2513 STATIC CHARACTER GENERATOR & 2514 STATIC READ-ONLY MEMORY 


ADDRESS 


AS A8 A7 AG A5 A4 A3 A2 Al 


ADDRESS OUTPUT DATA 


A9 AS A7 AG AS A4 A3 A2 Al 


| 
<8 
=o 
oO 
wa 
A< 


: 
¢ 


150 


CUSTOM CODING INFORMATION 
2516 STATIC CHARACTER GENERATOR 


COMPANY ________ PIN CONFIGURATION 
ADDRESS 3. ee 
CITY. ————COST ATE —CZdIP_ 
TELEPHONE 
AUTHORIZED SIGNATURE 
Chip Enable 24. Vec 
DATE NC Vv 


. Output 8 . Address 9 
Output 7 . Address 8 
Output 6 . Address 7 
Output 5 . Address 6 
Output 4 . Address 5 
Output 3 . Address 4 
. Output 2 . Address 3 
. Output 1 . Address 2 
. Address 1 
- Chip Enable 2* 


CUSTOMER PRINT OR ID NO. 

PURCHASE ORDER NUMBER 

CUSTOM PATTERN NUMBER (TO BE ENTERED BY 
SIGNETICS) 


1. 
2. 
3 

4. 
5. 
6. 
7. 
8. 
9 


INTRODUCTION * Optional on all custom ROMs (NC on CM 2150) 


The Signetics 2516 is a high speed silicon gate MOS read- 
only memories whose organization is specially suited for 
64 X 6 X 8 vertical scan character generation. 


CHARACTER FORMAT 


ROW ADDRESS 


MAJOR FEATURES OF THE 2516 


64 X 6 X 8 CHARACTER MATRIX 
COLUMN OUTPUT 

ACCESS TIME 450ns TYPICALLY 

STATIC OPERATION 

TTL/DTL COMPATIBLE 

TRI-STATE OUTPUTS (HIGH-LOW- 
DISCONNECTED) FOR POWERFUL BUSSING 
CAPABILITY 

m +5, -5, -12V POWER SUPPLIES 

® 24-PIN SIGNETICS SILICONE DIP 

™ SIGNETICS SILICON GATE PROCESS TECHNOL- 
OGY FOR PERFORMANCE AND RELIABILITY 


EXAMPLE “S” 


FIGURE 1 


CHARACTER ADDRESS 


ORGANIZATION AS 
CHARACTER GENERATOR CHARACTER ADDRESS 


A six-bit binary address (Aq through Ag) selects 1-of-64 gl A5|A6|47|Ag|Ag| 
i i SCII 

matrix characters arranged 6 dots horizontally and 8 dots cuir {1{ 1} ofo[1{o 

vertically. A three bit-binary address code (Aq through A3) 

selects 1 or 6 columns. Eight outputs display a complete 


: : IGURE 2 
column of the character matrix. See Figure 1. ne 


151 


2516 STATIC CHARACTER GENERATOR 


PACKAGE INFORMATION CUSTOM DEVICES 


For unique custom memory patterns, this form should be 
used to transmit coding instructions. The nomenclature for | 
custom device will consist of the basic product type followed 
NX PACKAGE by a unique “CM” number assigned by Signetics. For ex- 
ample, ““2516NX/CM2151”. 
@ Programming with punched cards. 
For maximum accuracy and minimum cost and turn- 
around time, the truth table should be transmitted to 
Signetics in the form of punched cards according to 
the format indicated on the following pages. 
@ Programming with written truth table. 
When punched data cards cannot be supplied, the 
truth table may be transmitted in written form using 
the attached blank truth table. 


VERIFICATION 
: Lead material: yrds solder oe 
; ial: Sili : : sae ‘ 
3 Tolerencae | non-commiiating. Upon receipt of either punched card or written truth table 
S hot cearioes dernet incite rocking fat information, Signetics will prepare a computer tabulation 


6. Signetics symbol denotes lead No. 1. 


of the instructions and return to the address indicated. If 
errors are detected, they should be transmitted to Signetics 
as quickly as possible. 


LOGIC CONVENTION 
STANDARD PATTERN 


Logic “1’’s or blackened squares in the truth table will result 


A standard ASCII! Character Font is available for the 2516. in “high” output from the indicated output terminal (i.e. 
This device (2516NX/CM2150) may be used for ASCII +3.6V minimum). Similarly, a ’’1’" address input level is 
character generation or for device evaluation. interpreted as +3.2V minimum. 

IDENTIFICATION CARDS 


LEAVE COLS. 22, 23, 24, 25, 26 BLANK 
INDICATES “COMMENT” CARD _ FOR ASSIGNMENT OF CM NO. BY SIGNETICS 


BASIC PART TYPE CUSTOMER P/N IDENTIFICATION 


SIGNETICS 2516NX/CM ACME MEMORIES PYN 135216-1 
8 G88 oe & abt Ot 


i | i | i | 
COMOCKO HOOP C00000 MH 0000000000000000000§ 008 00000000000000000000000000000000000000 
123-4 STO 8 ON Z 131415 16 17 18 19 20.21 22 29.26 25 26-27 20 29 30 31 32 33 34 35 36 37 30 30 40 AN 42 49 44 45 66 47 40 49 S8 SI 52 S3 S455 56 ST S059 60.61 62.63 64 6S 66 G7 GO69 70.70 7279 76.75 7617 1679.00 
PERO ROROOOEG! DOO! DOR OEO! DPPRRERREREBEE! DOl DOE! OO) PRR R ORR E RR eee PPE Ree eeeeeeee 
2292222222§ ee eee eee eee eee rere ress eee ee ees Pee ee eee eee eee eee eee eee eee ee, 


152 


2516 STATIC CHARACTER GENERATOR 


IDENTIFICATION CARDS (Cont‘d) 


PERSON RESPONSIBLE FOR REVIEWING SIGNETICS 
COMPUTER GENERATED TRUTH TABLE 


- ATTN. 1.0. ENGINEERs MENORY PROD. 3 
be &@ @88 08 88 i am 688 
aon Bat i 
00080000000000000000000000000000000000000000000000000008 
26 27 20.29 30 313233 34 35 36 37 30 39-40 40 42 49 44 45 46 47 48 49 50 51 57 53 54 55 55 ST SO 59 60.61 62 63 G4 6S 66 S7 G8 69 70 71 1273 7475 76 77 187980 
1 


DUUUT UTEP TTT TTA A Ta 
2222222222222 kkk kkk kkk kkk klk 22 


STREET ADDRESS 


— S000 ELECTRONIC? LANE 
| a is 1 68h 

ual i 
000000000000000000000000000000000000000000000000000000000000 
21 22.23 24 25 26 27 20 29 30 31 32 39 34-35 36 37 30-90 40 41 42 43 44 45 06 47 40 49 58 SI 52 53 54 55 56 ST SO 58 60 61 62 63 64 65 65 67 68.68 7071 1273 7475 16.77 707900 


| PROPOR Oe OPO OPP Ree eee eee eee eee eee eee ees eeee seen eeeee 
aE eee eee eee ee ees PEPE E eee eee eee ee eee eee eee eee eee ee eee eee eee ee eee e eee ee ee eee: 


- 
a 
-_— 3 oo 


CITY STATE ZIP 


; SUNNYVALE: CALIFORNIA 94086 
u oO: na oan 
moe onium | | 
009 00000000000000800000000000000000000000000000000000000000000000000000 
e 13 14-15 16 17 18 19 20 21 22 23 24 25 26 27 20 29 30.31 32 33 34 35 36 37 30 39 40 41 42 43.04 45 46 47 48 49 S951 52:53 S455 SE 57 S859 60 61 62 63 64 6S 66 G7 6869 7071 12737475 1677 7079 8 
| 


iT TRE RRO Oe! POOP PRR R ROPER POS RUPE Ree e Pee eRenPenereePenePeneenean 
Pee eee eee eee ee eee eee eee reer eee eee eee eee eee eee eee eee eee eee ee eee eee ee, 


COMPANY NAME 


CODOOOOOOOODOOOKOODODDOOODOOOOODDDNNDNNDNNNNNNNHHHNNDNDNODD 


22:23 24 25 26 27 20 29 WW 31 32 33 34 95 36 37 3839 40 40 42 43 44 45 M6 47 48 49 56 St 52 53:56:55 SE ST SO S9 60.61 62 63 6465 66 67 6869 10.7) 7273:7475 1677 187908 


DEO RU ROPE OSD E RPO RRR RO EE REECE REPRE PRE RER ERE RE RRS R BEER 


8222222222 2222228222 


153 


2516 STATIC CHARACTER GENERATOR 


DATA CARDS DECIMAL CHARACTER ADDRESS 
OUTPUTS Og THROUGH 0, RESPECTIVELY (DATA CARD NUMBER 001 THRU 064) 
sry U O8LTLUQA OLGNLedy Gide1ony 8idorod1 o0100770 


(THIS EXAMPLE ILLUSTRATES OUTPUT SEQUENCE) 


COMMON OMOMMONN OOM ORMOND OOMOMMOMMOOMBOMMOOM OOO 00 TTD OOOO DODD ODD000NON ON 


VW 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33.34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 505) 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 G7 GB 69 70 71 72737475 7677 78 79 80 


De) Seen Pee Gee See Ded bee Gee GOs DO DOG Den | SOPRO POPE RPE Rn ee eenneeennne 


eee 


333333333333333333333333393333333333333333333333333333333933333333933333333333333 
Se eee CeCe CCRC ECC C CEES CECCCECCECCEOECCOCCCCECECC CECE ECCS ECCECELS 
EEPEELESESOCLESEESEPEEEOOEOEESSESEEEOSESS IEEE OSEEEIOOESESOOLE LES EOLELE LES EE EEE, 
BECCCEGEEC CEC CEEEEE CCE C CHEEKS CEC CEC CHB GEE EEC CC CCGG GCC C HCC HH GEE CC EEK E EE HE EGE ESGE 
TUTTTTTT TTT TTT aaa aaa 


COLUMN ADDRESS(A3,A2,A4) 


000 001 010 011 100 101 


(SONGGOe OMIT OSLO GLGOLRGL CLOGT IGT OLGSLOeL BeLgei io 


(THIS EXAMPLE ILLUSTRATES COLUMN ADDRESS SEQUENCE) 


eee e eee eee eee eee EERE eee eee eee eee eee eee eee eee eee r ee eee eee eee es 
3333333333333 33333333333933333333333333333393393333333999993999939339333333333333993 
BAA A AQAA Add AGA ddd dda Add ddd dag gga badd ad dada ddd dd ddd add ddd ggadagagagaaad 
SEEPESELELELISILESESELESESESEESSLESESSS SLES ELSES ELELE SES SSE SE SESE PEELE EEE EEE EEE 
GCCCCGGEEE CEC EE CE CEES CC CGGEE ECE CCRC GGGGG ECC ECC CEEG ECC EC GEGGGEC CC B6GGE CEC G6EbGE6SEE 
TUTTI TTT TTT TTT aaa 


BASIC DEVICE TYPE 
LEAVE COLS. 10, 11, 12, 13 BLANK FOR ASSIGNMENT OF CM NO. BY SIGNETICS 


(HEADER CARD) 


tk kkk kkk kkk kkk kkk 282k kkk kkk kkk kkk klk kkk kkk kkk 2222222222 222222222222222222 
3333333M333333333333333333333333333333333333333333333333333333333333333333333333 
BAAAAAAAM AAG AAA AAA AGA AMAA AAA AAA MAAN AAA A AAA AAA AAA A Adhd ddd gdgadg a 
TERT FESESESESESSEPEESSOESSESOOEESSSSESES SELES SEES ESSE LESS OLESP ELSES SLEEP EEE e yr 
CHCHCSC CECE CECE CE FE ECE E CCFC CG RE CCH CEE E CCGG CCGG CCGG SCG GC CHG CE GGEGEGG6 CCGG G6GE6GG666 


TUTTIMT TT TTT TTT TTT TTT 
NOTE 


“Character’’ number is in cotumns 78, 79, and 80. 


154 


2516 STATIC CHARACTER GENERATOR 


Character Number 


Character Number Character Number 


Character Number 


Column Decimal Column Column Decimal 
Address . Address 
Binary 


° 


Output Codes 


Character Number Character Number Character Number 


Character Number 


Column Decimal 
Address 


Output Codes 


Output Codes 


155 


2516 STATIC CHARACTER GENERATOR 


Character Number Character Number Character Number 


Character Number 


Column Decimal 
Address 


cel 
8 
rel 
8 
3 
© 
xe] 
7 ne) 
Iq 
ial 
8 
ty] 
re | 
WN 
BH 
oe 
8 
H 
3 
© 
xe] 
2 xe) 
q 
E 
° 
rg 
So 
B 
st 
So 
ie 
ies 
Oo 
rel 
| ad 
o 
a 
i 
3 
© 
xe] 
. me] 
4 
H 
A 
an 
® 
te 
ze] 
7 ne} 
<q 


8 


° 


Character Number Character Number Character Number 


Character Number 


Column Decimal 
Address 


Acsrev*fo96|097]o08{089) 100|101] [*A***|104]105|106|107|108] 109] [°° ralrrsirelsas|irelia7] |AA**p20}r21 r2z}r29)124)126| 


Output Codes 


156 


2516 STATIC CHARACTER GENERATOR 


a 
@ 
a 
E 
3 
P 
@ 
ew 
9 
s 
s 
<£ 
oO 


Character Number Character Number 


Character Number 


) 
£ 
& 8 
a2 
5) 
cs 
Eq 
2 
io) 
(6) 


Add 
sc aaa faafan] [foal rfeofofin] (face |*™ eel self 


Output Codes 


Output Codes 


Character Number 


Character Number 


i 
a 
a 
E 
3 
Zz 
@ 
~ 
9 
oO 
- 
o 
£ 
Oo 


Character Number 


Column Decimal 
Address 


157 


2516 STATIC CHARACTER GENERATOR 


Character Number Character Number Character Number 


Character Number 


Output Codes 


Column Decimal 
Address 


pao) (O" 


N 


200jzo1|z02|203|204]200) “SNS 


te 
@ 
2 
E 
3 
2 
- 
@ 
~ 
15) 
oS 
- 
i] 
£ 
O 


Character Number Character Number 


Character Number 


rc) 
E 
o % 
a? 
se) 
ane) 
Eq 
2 
io) 
oO 


158 


2516 STATIC CHARACTER GENERATOR 


Character Number 


Character Number Character Number 


Character Number 


Column Decimal Column Coiumn Decimai 
Address : Address 
Binary 


i a 


td 


27 


Output Codes 


Character Number Character Number Character Number 


Character Number 


Column Decimal Column Column Decimal 
Address Binary Address 


Dad 


Output Codes 


Output Codes 


159 


2516 STATIC CHARACTER GENERATOR 


- 
a 
Q 
E 
p>] 
2 
. 
a 
~ 
13) 
© 
te 
LJ 
<£ 
oO 


Character Number 


Character Number 


Character Number 


r] 
£ 
® 8 
ae 
e8 
5 
fe} 
O 


Address Address Address Address 
337 347 


Output Codes Output Codes 


Out put Codes 


he 
® 
2 
E 
3 
2 
i 
® 
- 
7) 
© 
toe 
G 
© 
1] 


Character Number 


Character Number 


i. 
® 
xe} 
E 
3 
2 
he 
® 
~ 
9 
C6 
= 
i] 
£ 
Oo 


6 
£ 
2 3 
am 
cs) 
ee) 
Eq 
2 
io) 
oO 


Address 
pepesessboear| [*repeoloroxspspos] eoeepoolereardorebre [Nee 


ES 
S 
v. 
A 
ws 
iv] 
oe 
~~ 
” 
© 
4 


o 


” 


Output Codes 


160 


2516 STATIC CHARACTER GENERATOR 


Character Number 


Character Number 


Character Number 


» 
@ 
Q 
E 
3 
2 
i 
® 
cud 
i$] 
a 
iw 
6 
£ 
Oo 


Column Decimal Cotumn Column Decimal 
Address : Address 
Binary 


Add 
see] [AA*re*fasa]s09|s04]s05]596|307] [***'**lac0]401]a0z}caalaoe]ace] [*A0*™ [409] 400] 410] 41s] 4r2]419 


abel ECE 


a 
a 
ao] 
oO 
1S) 
~ 
S 
Q 
a) 
3 
1°) 


Character Number Character Number Character Number 


Character Number 


Cotumn Decimal 
Address 


161 


2516 STATIC CHARACTER GENERATOR 


Output Codes 


Column Decimal 
Address 


Add Add 
“*[aao[easlasolasasa]asa] [A“M"*lasslas7[eselasolesclacr| [A lacaless 4cs|ae7|ae|ace] |“ lara|a7a|a7a[475] 47647 


Character Number 


Character Number 


Character Number 


Character Number 


Character Number 


i. 
1) 
Q 
E 
3 
2 
- 
® 
rel 
13) 
i) 
LX 
0 
x 
oO 


Character Number 


Character Number 


Column Decimal 
Address 


Output Codes 


163 


SECTION 
LINEAR AND DIGITAL 
PRODUCT INFORMATION 


164 


LINEAR 


LINEAR 


The Signetics Linear Product Line provides all of the most frequently 
required circuit functions. 

Linear products are generally available in both Military and Commer- 
cial temperature ranges and in a wide variety of package types. 


SENSE AMPLIFIERS OPERATIONAL AMPLIFIERS PHASE LOCKED LOOP 


528 (4 Channel Plated Wire) 
7520 through 7525 (Core) 


531 (High Slew Rate) 561 .01Hz to > 30MHz 

533 (Micro Power). 562 Sensitivity 300uV 

536 (FET Input) | sorter Frequency 
565 


516 (Differential IN/OUT) 1 | Operating Frequency 


537 (Precision) .001Hz to 500kHz 
51A1 (LM101A) Sensitivity 1 mv 
5101 (LM101) 566 (Function Generator) 
5107 (LM107) 567 (Tone Decoder) 
51A8 (LM108A) 

5108 (LM108) 


: 5556 (MC1556 
COMPARATORS 5558 en 


518 (Adjust Sinking) 
526 (High Speed) 

529 (Ultra High Speed) 
5710 (uA710) 

5711 (uA711) 


5709 (uA709) 
5740 (uA740) 
5741 (uA741) 
5748 (uA748) 


CORE DRIVERS 


75324 (SN75324) 
75450 (SN75450) 
75451 (SN75451) 
75452 (SN75452) 


VOLTAGE REGULATORS 


550 
5109 (LM109) 


5723 (uA723) 


MULTIPLIERS/DEMODULATORS 


5595 (MC1595) 4 Quad multiplier 
5596 (MC1596) Balanced modulator 
5111 (LM2111) Limiter-Detector 


AMPLIFIERS 


VIDEO 
501 
5733 (uA733) 
DIFFERENTIAL 
515 

511 (Dual) 

RF/IF 

510 (Dual) 
POWER DRIVER 
540 


165 


SIGNETICS MSI 


8200/01 /02/03 Buffer Registers 

8204/05 4096 Bit Bipolar ROM 2048 Bit Bipolar ROM 

8220 High Speed Content Addressable Memory Element (CAM) 

8223 256 Sit-Polar Field-Programmable Read Only Memory (From) 

8224 256 Bit ROM, ASCII to EBCDIC Code Converter, Alphabet Onty 

8225 64 Bit-Bipolar Scratch Pad Memory 

8226 1024 Bit Field/Factory Programmable Bipolar ROM (256x4) 

8228 4096 Bit Bipolar ROM (10x24x4) 

8230/31/32 8-Input Digital Multiplexer 

8233/34/35 2-Input 4-Bit Digital 

8241/42 Quad Exciusive-OR Element (8241) 4-Bit Quad Excltusive-NOR (8242) 

8243 8-Bit Position Scaler 

8250/51/52 Binary-To-Octal Decoder BCD-To-Decimal Decoder 

8260 Arithmetic Logic Element 

8261 Fast Carry Extender 

8262 9-Bit Parity Generator And Checker 

8263/64 3-Input, 4-Bit Digital Multiplexer 

8266/67 2-Input, 4-Bit Digital 

8268 Gated Full Adder 

8269 4-Bit Comparator 

8270/71 4-Bit Shift Registers 

8273 10-Bit Serial-IN, Parallel-Out Shift Register 

8274 10-Bit Parallel-tn, Seriat-Out Shift Register 

8275 Quad Bistable Latch 

8276 8-Bit Shift Register 

8277 Dual 8-Bit Shift Register 

8280/81 BCD Decade Counter/Storage Element 4-Bit Binary 
Counter/Storage Element 

8284/85 Binary Hexidecimal And BCD Decade, Synchronous Up/Down 
Counters 

8288 Divide-By-Twelve Counter/Storage Element 

8290/91 Presetable High Speed Decade/Binary Counter 

8292/93 Presetable Low Power Decade/Binary Counter 

8T01 Nixie Decoder/Driver 

8T04 Seven Segment Decoder/Lamp Driver 

8T05 Seven Segment Decoder/Transistor Driver 

8T06 Seven Segment Decode/Display Driver 

8T09 Quad Bus Driver 

8T10 Quad D-Type Bus Flip-Flop 

8T13 Dual Line Driver 

8T14 Triple Line Receiver 

8T15 Dual Communications EtA/MIL Line Driver 

8T16 Dual Communications E1A/MIL Line Receiver 

8T22 Retriggerable One-Shot 


166 


SIGNETICS: THE NUMBER 1 LINE IN MSI. 


7441 BCD-TO- CET Pe OpER DRIVER 
54 7442 BCD-TO-DECIMAL DECODER 
54 7443 EXCESS 3-TO.- DECIMAL L DECODER 
54 7444 EXCESS 3-GRAY-TO-DECIMAL DECODER 
54 7445 BCD-TO-DECIMAL DER ORER DRIVER WITH OPEN COLLECTOR 
HIGH VOLTAGE OU!TPU 
54°7475 QUADRUPLE BISTABLE LATCH 
54/7477 Spars i ela LATCH 
54 7480 GATED FUL 
54 7483 4-BIT BINARY pith ADDER SOK AE AHEAD CARRY) 
54 7486 QUAD 92-INPUT ose OR GATE 
54-7490 DECADE COUNT 
54 7491 8-BIT SHIFT R POT 
54 7499 Rw ipe. ay Weve COUNTER (DIVIDE-BY-TWO AND 
54 7493 4-BIT BINARY COUNTER 
54 7494 4-BIT Suit REGISTER CAR ALLEL «IN, SERIAL-OUT) 
54°7495 4-BIT RIGHT-SHIFT : T-SHIFT REGISTER 
54 7496 5-BIT SHIFT REGISTE 


54 74145 BCD.TO-DECIMAL DECODER DRIVER WITH OPEN COLLECTOR 
HIGH VOLTAGE OUTPUTS 
54 74150 16-LINE TO 1-LINE DATA SELECTOR, MULTIPLEXER 


54, 74151 8-LINE TO 1-LINE DATA SELECTOR ‘MULTIPLEXER 

54, 74152 at TO 1-LINE DATA SELECTOR MULTIPLEXER 

54 74154 NE TO 16-LINE DECODER DEMULTIPLEXER 

54 741768280) ‘ Bn PRESETABLE COUNTER 

54 74177(8281) 4-BIT PRESETABLE COUNTER 

54 7417 oon 4-BIT SHIFT een 

54 7417%8271) 4- Bt pall REGISTER 

54 74180 8-B D-EVEN PARITY GENERATOR CHECKER 

54 74192 SNCERONOUS DECADE UP DOWN COUNTER WITH 

PRESET INPUTS 

54 74193 Syn Oeeeer ab 4-BIT BINARY UP DOWN COUNTER 

WITH PRESET INPUTS 


54 741968290) HIGH SPEED PRESETABLE DECADE COUNTER 
54. 74197(8991) HIGH SPEED PRESETABLE BINARY COUNTER 


54.7446 BCD-TO-SEVEN SEGMENT DECODER DRIVER 
54 7447 BCD-TO-SEVEN SEGMENT DECODER DRIVER 
54/7448 BCD-TO-SEVEN SEGMENT DECODER DRIVER 
54/74144 BCD-TO-DECODER DECIMAL DRIVER WITH BLANKING 
54, 74153 DATA SELECTOR MULTIPLEXER DUAL 4-TO-1 LINE 
54/74157 QUAD 9-TO.1 LINE 
54 74166 PARALLEL-IN, SERIAL-OUT, SYNCHRONOUS LOAD 
SHIFT REGISTER 
54.74181 4-BIT ARITHMETIC UNIT W FULL LOOK-AHEAD 
54 74189 LOOK-AHEAD CARRY GENERATOR 
54 74195 4-BIT SHIFT REGISTER PARALLEL-ACCESS J-k 
INPUTS MODE CONTROL 
54 74198 8-BIT SHIFT REGISTER PARALLEL-ACCESS, 
SHIFT RIGHT-LEFT 
54 74199 8-BIT SHIFT REGISTER PARALLEL-ACCESS 
J-K INPUTS 


SIGNETICS: THE NUMBER 1 LINE IN SSI. 

54/7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE 

54/7401 QUADRUPLE 9- al POSITIVE NAND GATE (WITH OPEN 
COLLECTOR OUTP 

54/7402 QUADRUPLE 2- INBLIL POSITIVE NOR GATE 

54/7403 QUADRUPLE 9- Pan POSITIVE NAND GATE (WITH OPEN 
SEE oe UT) 

54/7404 HEX IN 

54/7405 HEX INVERTER w ITH OPEN COLLECTOR OUTPUT) 

54/7406 HEX INVERTER oe ee WITH OPEN COLLECTOR 
HIGH VOLTAGE UTS 

54/7407 ae ae DRIVER Wit OPEN COLLECTOR HIGH VOLTAGE 


S$ 

54/7408 QUADRUPLE 2-INPUT POSITIVE AND GATES 
54/7409 QUAD 2-INPUT AND GATE WITH OPEN COLLECTOR OUTPUTS 
54/7410 TRIPLE 3-INPUT POSITIVE NAND me Mi 
54/7411 TRIPLE 3-INPUT POSITIVE AND GA 
54/7416 HEX INVERTER Sat ‘DRIVER wit OPEN COLLECTOR 

HIGH VOLTAGE OUTPUTS 
54/7417 Hen ee WITH OPEN COLLECTOR HIGH VOLTAGE 


54/7490 DUAL 4-INPUT POSITIVE NAND GATE 
54/7421 DUAL 4-INPUT POSITIVE NAND GATE 
54/7426 QUAD 2-INPUT HIGH VOLTAGE NAND GATE 
54/7430 8-INPUT POSITIVE NAND GATE 
54/7440 DUAL 4-INPUT POSITIVE NAND BUFFER 
54/7450 EXPANDABLE DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE 
54/7451 EXPANDABLE DUAL 9-WIDE 2-INPUT AND-OR INVERT GATE 
54/7453 4-WIDE 2-INPUT AND-OR-INVERT GATE 
54/7454 4-WIDE 2-INPUT AND-OR-INVERT GATE 
54/7460 DUAL 4-INPUT EXPANDER 
54/7470 J-K FLIP FLOP 
54'7472  J-K MASTER-SLAVE FLIP-FLOP 
54/7473 DUAL J-K MASTER-SLAVE FLIP FLOP 
54/7474 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOP 
54/7476 DUAL _J-K MASTER-SLAVE FLIP-FLOP WITH 
PRESET AND CLEAR 

54/74107 DUAL J-K MASTER-SLAVE FLIP-FLOP 
54/74121 MONOSTABLE MULTIVIBRATOR 
54/74129 ley eae MONOSTABLE MULTIVIBRATOR 

74193 ee ope MONOSTABLE MULTIVIBRATOR 


$4/74H 
54/74H00 QUADRUPLE 2-INPUT POSITIVE NAND GA 
54/74HO1 QUADRUPLE 2-INPUT POSITIVE NAND GATE (WITH OPEN 
COLLECTOR OUTPUT) 
54/74HO4 HEX INVERTER 
54/74HOS HEX INVERTER (WITH OPEN COLLECTOR OUTPUT) 
54/74HO8 QUADRUPLE 2-INPUT POSITIVE AND GATE 
54/74H10 TRIPLE 3-INPUT POSITIVE NAND GATE 
54/74H11_— TRIPLE 3-INPUT POSITIVE AND GATE 
54/74H20 DUAL 4-INPUT POSITIVE NAND GATE 
54/74H21 DUAL 4-INPUT POSITIVE AND GATE 
54/74H22 atts bial POSITIVE NAND GATE (WITH OPEN COLLECTOR 


UTPUT) 
54/74H30 —8-INPUT POSITIVE NAND GATE 
54/74H40 DUAL 4-INPUT POSITIVE NAND BUFFERS 
54/74H50 DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES 
54/74H51 DUAL 2. WIDE 9.INPUT AND-OR-INVERT GATES 
54/74H52 4. WIDE 9.9.9.3-INPUT AND-OR-GATE 
54/74H53 EXPANDABLE 9-2-2-3-INPUT AND-OR-INVERT GATE 
54/74H54 EXPANDABLE 9.9-2-3-INPUT AND-OR-INVERT GATE 
54/74H55 EXPANDABLE 4-INPUT AND-OR-INVERT GATE 
54/74H60 DUAL 4-INPUT EXPANDER 
54/74H61 TRIPLE 3-INPUT EXPANDER 
54,'74H62 —3-2-2-3-INPUT AND-OR EXPANDER 
54/74H71_— J-K MASTER SLAVE FLIP-FLOP 
54.74H72 J-K MASTER SLAVE FLIP-FLOP 
54,74H73 DUAL J-K MASTER-SLAVE FLIP-FLOP 
54/74H74 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOP 
54/74H76 DUAL J-K MASTER-SLAVE FLIP-FLOP 


167 


Were number 1. 


SiNCtics 


tics . — 


168 


169 


SECTION 


SALES OFFICE LIST 


170 


SALES OFFICE LIST 


SIGNETICS SALES OFFICES 


FIELD SALES OFFICES 


e New England Regional Sales Office: Miller Building, Suite 11, 
594 Marrett Road, Lexington, Massachusetts 02173 
Phone: (617) 861-0840 TWX: (710) 326-6711 


e Atlantic States Regional Sales Office: 2460 Lemoine Avenue, 
Fort Lee, New Jersey 07024 
Phone: (201) 947-9870 TWX: (710) 991-9794 
Florida: 3267 San Mateo, Clearwater, 33515 
Phone: (813) 726-3469 TWX: (810) 866-0437 
Maryland: Silver Springs 
Phone: (301) 946-6030 
Pennsylvania and Southern New Jersey: 
Oakwood Drive, Medford, New Jersey 08055 
Phone: (609) 665-5071 
Virginia: 12001 Whip Road, Reston, 22070 
Phone: (301) 946-6030 


e Central Regional Sales Office: 5105 Tollview Drive, Suite 209, 
Rolling Meadows, Illinois 60008 


Phone: (312) 259-8300 TWX: (910) 687-0765 


e Northwest Regional Sales Office: 811 E. Arques, Sunnyvale, 
California 94086 
Phone: (408) 739-7700 TWX: 


Phone: (408) 736-7565 TWX: 


(910) 339-9220 
(910) 339-9283 


e Southwest Regional Sales Office: 2061 Business Center Drive, 
Suite 214, Irvine, California 92664 
Phone: (714) 833-8980, (213) 437-6718 TWX: (910) 595-1506 
California: P.O. Box 788, Del Mar, 92014 
Phone: (714) 453-7570 


REPRESENTATIVES 


ALABAMA 

Huntsville 35801: Compar Corp., 904 Bob Wallace Ave., Room 114 
Phone: (205) 539-8476 

ARIZONA 

Scottsdale 85252: Compar Corp., P.O. Box 1607 

Phone: (602) 947-4336 TWX: (910) 950-1293 
CALIFORNIA 

Palo Alto 94303: Components Unlimited, 1020 Corporation Way 
Phone: (415) 961-9064 

San Diego 92123: Celtec Company, Inc., 8799 Balboa Avenue 
Phone: (714) 279-7961 TWX: (910) 335-1512 

CANADA 

Toronto 150, Ontario: Canadian General Electric Company, Ltd., 
Electronics Components Department, 189 Dufferin Street 
Phone: (416) 537-4481 TELEX: 0221360 

COLORADO 

Denver 80222: Elcom, P.O. Box 22457 

Phone: (303) 771-6200 TWX: (910) 935-0710 
CONNECTICUT 

Hamden 06518: Compar Corp., P.O. Box 5204 

Phone: (203) 288-9276 TWX: (710) 465-1540 

FLORIDA 


Altamonte Springs 32701: WMM Associates Inc., 515 Tivoli Ct. 
Phone: (305) 831-4645 


171 


Clearwater 33516: WMM Associates Inc., 1260A S. Highland Ave. 
Phone: (813) 446-0075 

Pompano Beach 33060: WMM Associates Inc., 721 South East 6th 
Terrace 

Phone: (305) 943-3091 

INDIANA 

Indianapolis 46250: R. H. Newsom Associates, 6320 Woburn Dr. 
Phone: (317) 849-4442 


MASSACHUSETTS 
Newton Highlands 02161: Compar Corp., 88 Needham Street 
Phone: (617) 969-7140 TWX: (710) 335-1686 


MICHIGAN 
Grosse Pointe Park 48230: Greiner Associates Inc., 15324 E. Jefferson 
Phone: (313) 449-0188, (313) 449-0189 TWX: (810) 221-5157 


MINNESOTA 
Minneapolis 55416: Compar Corp., P.O. Box 16095 
Phone: (612) 922-7011 


MISSOURI 

St. Louis 63141: Compar Corporation 

11734 Lackland Industrial Drive 

Phone: (314) 567-3399 TWX: (910) 764-0839 


SOUTHERN NEW JERSEY AND PENNSYLVANIA 
Haddonfield, N.J. 08033: Compar Corp., 15 Potter Street 
Phone: (609) 429-1526 TWX: (710) 896-0679 

NEW MEXICO 

Albuquerque 87110: Compar Corp., 2129 San Mateo, N.E. 
Phone: (505) 265-1020 TWX: (910) 989-1659 


METROPOLITAN NEW YORK 

Manhasset 11030: Win-Cor Electronics Sales Corp., 
75 Plandome Road 

Phone: (516) 627-9474 
UPSTATE NEW YORK 
Rochester 14618: Fowler Beach Corp., 3700 East Avenue 
Phone: (716) 586-0468 TWX: (510) 254-2939 
NORTH CAROLINA 

Winston-Salem 27101: Compar Corp., 1106 Burke Street 
Phone: (919) 723-1002 TWX: (510) 931-3101 

OHIO 

Dayton 45405: Compar Corp., 

P.O. Box 57, Forest Park Branch 

Phone: (513) 890-9260 


Fairview Park 44126: Compar Corp., P.O. Box 4791 
Phone: (216) 333-4120 TWX: (810) 421-8396 


TEXAS 

Richardson 75080: Semiconductor Sales Associates, 
312 North Central Expressway, Suite 213 

Phone: (214) 231-6181 TWX: (910) 867-4737 


Dallas 75229: McCoy Associates Company . 
4339 Southcrest Road 
Phone: (214) 352-9517 


UTAH 
Salt Lake City 84111: Elcom, 445 East 2nd South 
Phone: (801) 355-5327 TWX: (910) 925-5607 


TWX: (510) 223-0807 


WASHINGTON 

Bellevue 98004: Western Technical Sales, 

10843 N.E. 8th. Street, Room 210, Fraser Bldg. 
Phone: (206) 454-3906 TWX: (910) 443-2309 


SALES OFFICE LIST 


DISTRIBUTORS 


CALIFORNIA 
Burbank 91504: Compar Corp., 2908 Naomi Avenue 
Phone: (213) 843-1772 TWX: (910) 498-2203 


Burlingame 94010: Compar Corp., 820 Airport Bivd. 
Phone: (415) 347-5411 TWX: (910) 374-2366 


Culver City 90230: Hamilton Electro Sales, 
10912 West Washington 
Phone: (213) 870-7171 TELEX: 677-100, 674-381, 674-354 


El Monte 91731: G.S. Marshall, 9674 Telstar Avenue 
Phone: (213) 686-1500 TWX: (910) 587-1565 


Los Angeles 90022: KT/Wesco Electronics, 

5650 Jillson Street 

Phone: (213) 685-9525 TWX: (910) 580-1980 
Mountain View 94041: Hamilton/Avnet Electronics, 
340 East Middlefield Road 

Phone: (415) 961-7000 TELEX: 348-201 


Palo Alto 94303: Wesco Electronics, 3973 East Bayshore Road 
Phone: (415) 968-3475 TWX: (910) 379-6488 

San Diego 92111: G. S. Marshall, 7990 Engineer Road, Suite 1 
Phone: (714) 278-6350 TWX: (910) 587-1565 

San Diego 92123: Kierulff Electronics, 8797 Balboa Avenue 
Phone:. (714) 278-2112 TWX: (910) 335-1182 


CANADA 

Downsview, Ontario: Cesco Electronics, Ltd., 24 Martin Ross Ave. 
Phone: (416) 638-5250 

Montreal, Quebec: Cesco Electronics, Ltd., 4050 Jean Talon West 
Phone: (514) 735-5511 TWX: (610) 421-3445 

Ottawa, Ontario: Cesco Electronics, Ltd., 1300 Carling Avenue 
Phone: (613) 729-5118 

Quebec: Cesco Electronics, Ltd., 128 St. Vallier Street 

Phone: (418) 524-3518 

COLORADO 

Denver 80216: Hamilton/Avnet Electronics, 1400 W. 46th Avenue 
Phone: (303) 433-8551 TELEX: 45872 

FLORIDA 

Hollywood 33021: Hamilton/Avnet Electronics, 

4020 North 29th Avenue 

Phone: (305) 925-5401 TELEX: 51-4328 

Orlando 32805: Hammond Electronics, 911 West Central Bivd. 
Phone: (305) 241-6601 TWX: (810) 850-4121 

ILLINOIS 

Elmhurst 60126: Semiconductor Specialists, Inc., 

195 Spangler Avenue, Elmhurst Industrial Park 

Phone: (312) 279-1000 TWX: (910) 254-0169 

Schiller Park 60176: Hamilton/Avnet Electronics, 3901 Pace Court 
Phone: (312) 678-6310 TELEX: 728-330 


MARYLAND 

Hanover 21076: Hamilton/Avnet Electronics, 7255 Standard Drive 
Phone: (301) 796-5000 TELEX: 879-68 

Rockville 20850: Pioneer Washington Electronics, Inc., 

1037 Taft Street 

Phone: (301) 427-3300 

MASSACHUSETTS 

Burlington 01803: Hamilton/Avnet Electronics, 207 Cambridge St. 
Phone: (617) 272-3060 TELEX: 9494-61 

Needham Heights 02194: Kierulff/Schley, 14 Charles Street 
Phone: (617) 449-3600 TWX: (710) 325-1179 

MICHIGAN 

Detroit 48239: Hamilton/Avnet Electronics, 8900 Telegraph Road 
Phone: (313) 538-1000 

Detroit 48240: Semiconductor Specialists, Inc. 

25127 West Six Mile Road 

Phone: (313) 255-0300 TWX: (910) 254-0169 


172 


MINNESOTA 

Minneapolis 55420: Semiconductor Specialist, Inc. 

8030 Cedar Avenue, South 

Phone: (612) 854-8841 

MISSOURI 

Hazelwood 63042: Hamilton/Avnet Electronics, 400 Brookes Lane 
Phone: (314) 731-1144 TELEX: 442348 


NORTHERN NEW JERSEY 

Cedar Grove 07009: Hamilton/Avnet Electronics, 

220 Little Falls Road 

Phone: (201) 239-0800 TELEX: 138313 

SOUTHERN NEW JERSEY AND PENNSYLVANIA 
Cherry Hill, N.J. 08034: Hamilton/Avnet Electronics, 
1608-10 West Mariton Pike 

Phone: (609) 662-9337. TELEX: 834737 

Cherry Hill, N.J. 08034: Milgray—Delaware Valley, 

1165 Marlkress Road 

Phone: N.J. (609) 424-1300 Phila. (215) 228-2000 TWX:(710) 
896-0405 

NEW YORK 

Buffalo 14202: Summit Distributors, Inc., 916 Main Street 
Phone: (716) 884-3450 TWX: (710) 522-1692 
Hauppauge, L.!. 11787: Semiconductor Concepts, Inc., 
Engineers Road 

Phone: (516) 273-1234 TWX: (510) 227-6232 
Woodbury, L.1!. 11797: Harvey Radio, 60 Crossways Park West 
Phone: (516) 921-8700 TWX: (510) 221-2184 

New York 10011: Terminal-Hudson Electronics, 

236 West 17th Street 

Phone: (212) 243-5200 TWX: (710) 581-3962 


OHIO 

Cleveland 44105: Pioneer Standard Electronics, P.O. Box 05100 
Phone: (216) 587-3600 TWX: (810) 421-8238 

Kettering 45429: Arrow Electronics, 3100 Plainfield Road 
Phone (513) 253-9176 TWX: (810) 459-1611 


TEXAS 

Dallas 75207: Hamilton/Avnet Electronics, 2403 Farrington Avenue 
Phone: (214) 638-2850 TELEX: 732359 

Dallas 75220: Solid State Electronics Company, P.O. Box 20299 
Phone: (214) 352-2601 

Houston 77019: Hamilton/Avnet Electronics, 1216 West Clay St. 
Phone: (713) 526-4661 TELEX: 762589 

Houston 77036: Universal Electronics, 5723 Savoy Street 

Phone: (713) 781-0421 


WASHINGTON 
Seattle 98121: Hamilton/Avnet Electronics, 2320 Sixth Avenue 
Phone: (206) 624-5930 TELEX: 32249 


INTERNATIONAL SALES 
EUROPEAN HEADQUARTERS: 


Signetics International Corp., Zugerstrasse, 57 

CH6340 Baar/Zug, Switzerland 

Phone: 042/315544 TELEX: 78752 

UNITED KINGDOM: 

Signetics International Corp., Trident House, Station Road, 
Hayes,Middiesex, England 
Phone: (01) 848-0202 
FRANCE: 

Signetics S.A.R.L., 90 Rue Baudin, F 92 Levallois-Perret, France 
Phone: 739-85-80/739-96-40 TELEX: 62014 

WEST GERMANY: 

Signetics GmbH, Ernsthaldenstrasse 17, D 7 Stuttgart 80, West 


Germany 
Phone: (0711) 73-50-61 


TELEX: 262349 


TELEX: 7255798 


STOCKING DISTRIBUTORS 
AUSTRALIA 


Pye Industries Ltd., Technico Electronics Division, 53 Carrington 
Road, Marrickville, Sydney, N.S.W. 

Phone: 55-0411 TELEX: 790-21490 

Pye Industries Ltd., Technico Electronics Division, 2-18 Normanby 
Road, South Melbourne, Vic. 

Phone: 69-60-61 TELEX: 31240 

WEST GERMANY - 

EBV Elektronik GmbH, Augustenstrasse 79, D~8 Munchen 2 
Phone: (0811) 52-43-40/48 

EBV Elektronik GmbH, Myliusstrasse 54, D-6 Frankfurt/Main 1 
Phone: (0611) 72-04-16/8 TELEX: 413590 

EBV Elektronik GmbH, Scheurenstrasse 1, D-4 Dusseldorf 
Phone: (0211) 8-48-46/7 TELEX: 8587267 


“Mutron” Muller & Co. KG, Postfach 164, Bornstrasse 65, D-28 
Bremen 1 

Phone: (0421) 31-04-85 TELEX: 245-325 
Dima-Elektronik, Karl Manger KG, Postfach 80 0744, 
Robert-Leichtstrasse 43, D-7 Stuttgart-Vaihingen 80 

Phone: (0711) 73-40-50/9 TELEX: 255-642 

Distron GmbH, 1000 Berlin 31, Wilhelmsaue 39-41 

Phone: 0311/870144 TELEX: 18-27-58 

Signetics GmbH, Eulenkrugstr. 81 E, D-2 Hamburg 67 

Phone: (411) 60-35-242 

AUSTRIA 

ing. Ernst Steiner, Beckgasse 30, A-1130 Wien 

Phone: (222) 82-10-605 

SWITZERLAND 

Dewald AG, Seestrasse 561, CH 8038, Zurich 

Phone: (051) 45-13-00 TELEX: 52012 

FRANCE 

S.A. Gallec Electronique, 78, Avenue des Champs-Elysées, Paris 8e 
Phone: 359-58-38/255-67-10/255-67-11 

Elic 38, le Bureau Barisien S.A.R.L., 8-10 Avenue du Grand Sabion, 
38-La Tronche 

Phone: (76) 87-67-71 TELEX: 32-739 

ITALY 

Metroelettronica S.A.S., Viale Cirene 18, 1-20135 Milano 
Phone: 546-26-41 TELEX: 33-168 Metronic 

UNITED KINGDOM 

Quarndon Electronics Ltd., Slack Lane, Derby, Derbyshire 
Phone: (0332) 3-26-51 TELEX: 37163 

$.D.S. (Portsmouth) Ltd., Hilsea Industrial Estate, Portsmouth, 
Hampshire 

Phone: 6-53-11 TELEX: 86114 

Semicomps Ltd., 5 Northfield Industrial Estate, Beresford 
Avenue, Wembley, Middlesex 

Phone: (01) 903-3161 TELEX: 935243 

SCOTLAND 

Semicomps Northern Ltd., 44, The Square, Kelso, Roxburghshire 
Phone: 2366 TELEX: 72692 


173 


SALES OFFICE LIST 


SWEDEN, NORWAY, FINLAND 
A.B. Kuno Kallman, Jarntorget 7, S-413 04 Gothenburg, Sweden 
Phone: 17-01-20 TELEX: 21072 


DENMARK 
E. Friis-Mikkelsen A/S, Krogshojvej 51, DK-2880 Bagsvaerd 
Phone: (01) 986333 TELEX: 2350 


THE NETHERLANDS 
Mulder-Hardenberg, Westerhoutpark 1A, P.O. Box 5059, Harlem 
Phone: (023) 3191 84 TELEX: 41431 


JAPAN 
Asahi Glass Co., Ltd., 1-2, Marunouchi, 2 Chome, Chiyoda-ku, 
Tokyo 

Phone: 211-0411 


SOUTH AFRICA 
Indentronics Proprietary, Ltd. Sheerline House, 24 Webber Street, 
Selby, Johannesburg 

Phone: 834-4971/2/3 


TELEX: 4616 


TELEX: 43-7660JH 


REPRESENTATIVES 


SWEDEN, NORWAY, FINLAND 
A.B.Kuno Kallman, Jarntorget 7, S-413 04 Gothenburg, Sweden 
Phone: 17-01-20 TELEX: 21072 


AUSTRALIA 

Corning Australia, Technical Products Division, Room 13, Barden 
House, Fetherston Street, Bankstown, N.S.W. 2200 

Phone: 602-9011 TELEX: 21539 


ISRAEL 
Talviton Electronics Ltd., 43 Ben-Jehuda Road, P.O. Box 3282, 
Tel-Aviv 


Phone: 444572 CABLE: Talvitko 


JAPAN 

Asahi Glass Co., Ltd., 1-2, Marunouchi, 2 Chome, Chiyoda-ku, 
Tokyo 

Phone: 211-0411 TELEX: 4616 

SWITZERLAND 


Dewald AG, Seestrasse 561, CH 8038, Zurich 
Phone: (051) 45-13-00 TELEX: 52012 


INDIA 

Semiconductors Limited, Nagar Rd. Mile 4/5, 
Ramawadi, Poona 14, Maharashtra 

Phone: 25186 CABLE: Transducer 


SOUTH AFRICA 
Indentronics Proprietary, Ltd., Sheerline House, 24 Webber Street, 
Selby, Johannesburg 


Phone: 834-4971/2/3 TELEX: 43-7660JH 


SINCtES 


174 


SiqNGtics 


811 EAST ARQUES AVENUE = SUNNYVALE, CALIFORNIA 
 $a@os6c . TEL: (408) 739-7700 . TWX: (910) 3398-s283 


D282 MOS.008-51 351V Copyright 1971 — Printed in U.S.A A Subsidiary of Corning Glass Works