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LOGIC 

DATABOOK 

VOLUME I 

NATIONAL 

SEMICONDUCTOR 

CORPORATION 



• MM54HC/74HC/54HCT/74H;CT 
High Speed microCMOS Family 

• CD4000 Family 

• MM54C/74C Family 

• CMOS LSI/VLSI 


LOGIC 

DATABOOK 

VOLUME I 


CMOS AC Switching Test 
Circuits and Timing Waveforms 

CMOS Application Notes 
MM54HC/MM74HC 
MM54HCT/MM74HCT 
CD4XXX 

MM54CXXX/MM74CXXX 

LSI/VLSI 

Appendices/ 

Physical Dimensions 



3 





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4 



Introduction 


This comprehensive databook provides information on 
National Semiconductor’s advanced CMOS logic families 
MM54HC/74HC high speed, CD4000, MM54C/74C and the 
many unique CMOS LSI products. The MM54HC/74HC 
family utilizes microCMOS technology to achieve the in- 
put and power supply characteristics of CMOS with the 
high speed and large output drive of low power Schottky. 
The MM54HC/74HC family has the same pinout as equiva- 
lent 54LS/74LS; in addition, many popular CD4000 series 
logic functions are offered where no equivalent TTL func- 
tion exists. 

The MM54HCT/74HCT is a subfamily of MM54HC/74HC 
offering TTL inputs. These MM54HCT/74HCT devices of- 
fer convenient TTL level translation to CMOS for those 
places in the system where only TTL levels are provided. 

The CD4000 series is National Semiconductor’s extensive 
line of CD40XXB and CD45XXB series devices. These 
parts meet the standard JEDEC “B-Series” specifications. 

The popular MM54C/74C series logic family metal-gate 
CMOS technology is pin-for-pin and function-for-function 
equivalent to the 54/74 family of TTL devices. Unique 
special function LSI devices in this family are compatible 
with MM54HC/74HC and CD4000 series. 

CMOS LSI offers the design engineer unique solutions to 
achieving high density low power systems. These LSI de- 
vices utilize both microCMOS silicon-gate and metal-gate 
technologies to offer the design engineer the best solu- 
tion at the lowest cost. 

Nkional provides the highest Quality and Reliability in 
CMOS Logic and LSI. This databook provides detailed 
descriptions of Military/Aerospace Radiation Hardened 
Programs, Quality Enhancement and extensive Reliability 
Reports. We are proud of our success, which sets a stand- 
ard for others to achieve. Our company-wide programs to 
achieve perfection will continue so that customers can 
continue to rely on National Semiconductor’s integrated 
circuits and products. 


Einleitung 

Dieses ausfuhrliche Datenbuch enthalt alle Informa- 
tionen uber die modernen CMOS-Logikfamilien von 
National Semiconductor, namlich uber die Typenreihen 
MM54HC/74HC, CD4000, MM54C/74C, au/Serdem uber 


viele andere CMOS-LSI-Produkte. Die Hochgeschwindig- 
keits-Loglkfamilie MM54HC/74HC baslert auf der 
microCMOS-Technologie, die die Eigenschaften der 
CMOS-Technik in bezug auf die Stromaufnahme und das 
Eingangsverhalten mit der Geschwindigkeit sowie der 
Ausgangs-Treiberkapazitat von Low-Power-Schottky- 
Bausteinen vereinigt. Die MM54HC/74HC-Typen besitzen 
die gleichen AnschlujSbelegung wie die aquivalenten 
54LS/74LS-Bausteine, au/^erdem warden viele Funktionen 
der CD4000-Familie angeboten, fiir die keine ent- 
sprechende TTL-Ausfuhrung existiert. 

Die Serie MM54HCT/74HCT ist ein Teil der MM54HC/ 
74HC-Familie und besitzt TTL-kompatible Eingange. 
Daher eignen sich diese Bausteine insbesondere fur die 
Pegelanpassung zwischen CMOS- und TTL-ICs, z. B. wenn 
Schaltungsteile nur in TTL ausgefuhrt warden konnen. Die 
CD4000-Serie von National Semiconductor besteht aus 
den Bauelementen der CD40XXB- und CD45XXD-Familien. 
Diese Typen entsprechen den Spezifikationen der B-Serie 
nach JEDEC. 

Die wait verbreitete Logikfamilie MM54C/74C in Metall- 
Gate-Technologie ist anschlu/i- und funktionskompatibel 
zu den Bausteinen der 54/74-TTL-Familie. Einige LSI- 
Bauelemente mit Spezial-funktionen in dieser Familie 
Sind kompatibel mit Bausteinen der MM54HC/74HC- bzw. 
CD4000-Familien. 

CMOS-LSI-Bausteine bieten dem Entwicklungsingenieur 
Losungsmoglichkeiten in Form von Systemen mit hoher 
Schaltungsdichte bei geringer Stromaufnahme. Diese 
LSI-Schaltungen warden mit Hilfe der microCMOS- 
Silicon-Gate- Oder Metall-Gate-Technologie hergesteljt 
und ermoglichen optimale Schaltungsauslegung bei ge- 
ringsten Kosten. 

National Semiconductor kann bei CMOS-LSI- sowie 
Logikschaltungen Bauelemente hdchster Qualitat und 
Zuverlassigkeit anbieten. Dieses Datenbuch enthalt 
detaillierte Beschreibungen der Programme fur strahlen- 
feste Bauelemente fur Militar sowie Luft und Raumfahrt, 
der Qualltatsverbesserung, au/Serdam Zuverlassig- 
keitsreports. Wir sind stolz auf unseren Erfolg, der Stan- 
dards setzt, die fur andere erstrebenswert sind. Unsere 
FIrmenprogramme, die zum Ziel haben, Zuverlassigkeit 
und Qualitat zu perfektionieren, warden kontinuierlich 
fortgefiihrt, so da/? die Kunden sich auf die Produkte und 
integrierten Schaltungen von National Semiconductor 
auch zukunftig verlassen konnen. 




Introduction 

Ce databook tres complet regroupe toutes les informa- 
tions les plus recentes concernant les families logiques 
CMOS de National Semiconductor, la MM54HC/74HC 
rapide, la CD4000, la MM54C/74C, ainsi que de nombreux 
produits originaux LSI CMOS. La famille MM54HC/74HC, 
realisee en technologie microCMOS combine les carac- 
teristiques d’entre'e et d^alimentation de la CMOS avec la 
Vitesse et la sortance de la low-power Schottky. La famille 
54HC/74HC presente le m^me brochage que la famille 
equivalente 54LS/74LS; de plus, la tres populaire famille 
CD4000 offre un choix de fonctions logiques sans equiva- 
lent en TTL. 

La famille 54HCT/74HCT, sous-ensemble de la famille 
MM54,HC/74HC, dispose d’entrees compatibles TTL. Ces 
circuits MM54HCT/74HCT effectuent un translation de 
niveau TTL-CMOS lorsque des portes TTL attaquent des 
fonctions logiques CMOS dans le systeme. 

La famille CD4000 de National Semiconductor est con- 
stituee par les series de circuits CD40XXB et CD45XXB. 
Ces circuits sont conformes aux specifications standard 
JEDEC ‘Serie B’. 

La famille logique Serie MM54C/74C realisee en technol- 
ogie CMOS porte-metallique est equivalente broche pour 
broche et fonction pour fonction a la famille de circuits 
TTL 54/74. Les circuits LSI de cette famille, reallsant des 
fonctions speciales uniques, sont compatibles avec les 
Series MM54HC/74HC et CD4000. 

Les circuits LSI CMOS offrent aux ingenieurs de concep- 
tion des solutions avantageuses leur permettant de 
realiser des systemes a haute densite et consommant 
peu. Ces circuits LSI sont realises en technologies 
microCMOS porte-silicium et en CMOS porte-metallique, 
afin que I’ingenieur de conception dispose de la mellleure 
solution au moindre cout. 

National procure la meilleure qualite et la meilleure 
fiabilite en logique CMOS et en LSI. Ce Databook fournit 
une description detaillee des Programmes d’exposition 
aux radiations dans les domaines militaire et spatial, ainsi 
que des rapports d’amelioration de la qualite et de la 
fiabilite. Nous sommes tiers de notre succes, qui introduit 
un standard que nous envient nos concurrents. Ces pro- 
grammes de qualite sont executes a I’echelle de lasoclete 
toute entiere en vue d’atteindre la perfection: ils seront 
poursuivis afin que nos clients puissent continuer a faire 
confiance aux circuits integres et aux produits National 
-^Semiconductor. 


Introduzione 

II Databook sui dispositivi logic! CMOS della National 
Semiconductor contiene informazidni, dettagliate ed ag- 
giornate, sulla famiglia ad alta velocita MM54HC/74HC, 
sulla famiglia CD4Q00, MM54C/74C e su molti prodotti LSI 
CMOS. La famiglia MM54HC/74HC, in particolare utilizza 
una tecnologia microCMOS per assommare alle caratte- 
ristiche di assorbimento e di Ingresso/Uscita tipiche del 
CMOS quelle di elevata velocita e capacita di pilotaggio 
della tecnologia bipolare “Low Power Schottky”. I 
dispositivi della famiglia MM54HC/74HC sono pin cpm- 
patlbili con gli equivalent! dispositivi TTL; nella stessa ne 
sono compresi altri che riprendono, funzionalmente, i piu 
diffusi dispositivi CD4000 ove non esista un equivalente 
TTL. 

La MM54HCT/74HCT rappresenta una sottofamiglia della 
HC,ed offre compatibilitaTTLsugli ingress!. La HCTtrova 
ideale impiego nei sistemi ove esistano solamente livelli 
TTL e si debband impiegare dispositivi CMOS, come tras- 
latori di livello. La famiglia CD4000 della National com- 
prende la maggior parte delle funzioni piu diffuse sia 
CD40XX che CD45XX. Tutti i dispositivi soddisfano le 
specifiche JEDEC per la serie “B”. 

La nota famiglia MM54C/74C, realizzata in tecnologia 
CMOS “metal gate” e equivalente “pin-to-pin” e fun- 
zionalmente alia famiglia di dispositivi TTL 54/74. Special! 
dispositivi LSI, compresi in questa famiglia sono com- 
patibili con le serie MM54HC/74HC e CD4000. 1 dispositivi 
LSI CMOS offrono ai progettisti soluzioni uniche per 
sistemi ove sia richiesta alta integrazione e basso assor- 
bimento. Quest! LSI sono realizzati sia in tecnologia 
microCMOS che “metal gate” per offrire sempre la miglior 
soluzione ai cost! piu ridotti. 

La National offre la massima qualita ed affidabiiita per i 
suoi prodotti logici CMOS e dispositivi LSI. Questo 
Databook fornisce una descrizione dettagliata dei pro- 
grammi “Radiation Hardened” per dispositivi militari ed 
aerospaziali, i miglioramenti della qualita oltre a completi 
rapporti sull’affidabilita dei component!. Siamo fieri del 
nostro successo che fissa nuovi traguardi, per altri, da 
raggiungere. 11 nostro programma, che coinvolge tutta la 
societa per il raggiungimento della perfezione elettrica e 
in pleno svolgimento; con cio i nostri client! possono con- 
tinuare a riporre la massima fiducia nei prodotti della 
National Semiconductor. 


6 




Table of Contents 

Section 1— CMOS AC Switching Test Circuits and Timing Waveforms 

MM54HC/MM74HC 1-4 

MM54HCT/MM74HCT 1-6 

CD4000 1-8 

MM54C/MM74C 1-10 

Section 2— CMOS Application Notes 

MM54HC/MM74HC Application Notes 

AN-303 HC-CMOS Power Dissipation 2-89 

AN-310 High-Speed CMOS (MM54HC/MM74HC) Processing 2-94 

AN-313 DC Electrical Characteristics of MM54HC/MM74HC High-Speed CMOS Logic 2-102 

AN-314 Interfacing to MM54HC/MM74HC High-Speed CMOS Logic 2-109 

AN-317 AC Characteristics of MM54HC/MM74HC High-Speed CMOS 2-119 

AN-319 Comparison of MM54HC/MM74HC to 54LS/74LS, 54S/74S and 

54ALS/74ALS Logic 2-124 

AN-339 National’s Process Enhancements Eliminate the CMOS SCR Latch-Up Problem 

in 54HC/74HC Logic 2-130 

AN-340 HCMOS Crystal Oscillators 2-138 

AN-347 MM74HC942 and MM74HC943 Design Guide 2-141 

AN-349 CMOS 300 Baud Modem 2-149 

AN-368 An Introduction to and Comparison of 54HCT/74HCT 

TTLCompatible CMOS Logic 2-215 

AN-375 High-Speed-CMOS Designs Address Noise and I/O Levels 2-233 

AN-376 Logic-System Design Techniques Reduce Switching-CMOS Power 2-242 

CD4000, MM54C/MM74C Application Notes 

AN-77 CMOS, The Ideal Logic Family 2-3 

AN-88 CMOS Linear Applications 2-11 

AN-90 54C/74C Family Characteristics 2-14 

AN-1 18 CMOS Oscillators 2-20 

AN-138 Using the CMOS Dual Monostable Multivibrator 2-24 

AN-140 CMOS Schmitt Trigger— A Uniquely Versatile Design Component 2-30 

AN-177 Designing with MM74C908, MM74C918 Dual High Voltage CMOS Drivers 2-40 

AN-248 Electrostatic Discharge Prevention— Input Protection Circuits and 

Handling Guide forCMOS Devices 2-52 

AN-257 Simplified Multi-Digit LED Display Design Using 

MM74C911/MM74C912/MM74C917 Display Controllers 2-68 

AN-377 DC Noise Immunity of CMOS Logic Gates 2-253 

MB-18 MM54C/.MM74C Voltage Translation/Buffering 2-257 

LSI/VLSI Application Notes 

AN-143 Using National Clock Integrated Circuits in Timer Applications 2-36 

AN-249 MM54240 Asynchronous Receiver/Transmitter RemoteController Applications 2-54 

AN-250 Applications and Uses of the MM5321 TV Camera Sync Generator 2-58 

AN-251 A Broadcast Quality TV Sync Generator Made Economical through LSI 2-62 

AN-350 Designing an LCD Dot Matrix Display Interface 2-155 

AN-353 MM58167A RealTime Clock Design Guide 2-174 


7 




Table of Contents (Continued) 

LSI/VLSI Application Notes (Continued) 

AN-359 The MM58174A Real Time Clock in a Battery Backed-Up Design Provides . 

Reliable Clock and Calendar Functions 2-192 

AN-365 The MM58274Adds Reliable Real-Time Keeping to Any Microprocessor System 2-200 

AN-371 MM58348/342/341/248 Directly Drive Vacuum Fluorescent (VF) Displays 2-221 

Section 3— MM54HC/MM74HC Data Sheets 

Analog Switches 

MM54HC4016/MM74HC4016 Quad Analog Switch 3-360 

MM54HC4051/MM74HC4051 8-Channel Analog Multiplexer 3-386 

MM54HC4052/MM74HC4052Dual4-Channel Analog Multiplexer 3-386 

MM54HC4053/MM74HC4053 Triple 2-Channel Analog Multiplexer 3-386 

MM54HC4066/MM74HC4066 Quad Analog Switch 3-397 

MM54HC4316/MM74HC4316Quad Analog Switch with Level Translator ; 3-408 

Arithmetic Functions 

MM54HC85/MM74HC85 4-Bit Magnitude Comparator 3-66 

MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators 3-158 

MM54HC182/MM74HC182 Look-Ahead Carry Generator 3-166 

MM54HC280/MM74HC280 9-Blt Odd/Even Parity Generator/Checker 3-238 

MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry 3-241 

MM54HC521/MM74HC521 8-Blt Magnitude Comparator(Equality Detector) 3-286 

MM54HC688/MM74HC688 8-Bit Magnitude Comparator (Equality Detector) 3-341 

Buffers/ Drivers 

MM54HC125/MM74HC125 TRI-STATE Quad Buffers 3-93' 

MM54HC126/MM74HC126TRI-STATEQuad Buffers 3-93 

MM54HC240/MM74HC240 Inverting Octal TRI-STATE Buffer 3-201 

MM54HC241/MM74HC241 Octal TRI-STATE Buffer 3-201 

MM54HC244/MM74HC244 Octal TRI-STATE Buffer 3-210 

MM54HC365/MM74HC365 Hex TRI-STATE Buffer : 3-263 

MM54HC366/MM74HC366 Inverting Hex TRI-STATE Buffer 3-263 

MM54HC367/MM74HC367 Hex TRI-STATE Buffer . 3-263 

MM54HC368/MM74HC368 Inverting Hex TRI-STATE Buffer 3-263 

MM54HC540/MM74HC540 Inverting Octal TRI-STATE Buffer 3-295 

MM54HC541/MM74HC541 Octal TRI-STATE Buffer 3-295 

MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/ Driver 3-413 

MM54HC4543/MM74HC4543 BCD-to-7 Segment Latch/Decoder/Driver for 
Liquid Crystal Displays 3-428 

Counters 

MM54HC160/MM74HC160 Synchronous Decade Counter 3-135 

MM54HC161/MM74HC161 Synchronous Binary Counter 3-1,35 

MM54HC162yMM74HC162 Synchronous Decade Counter 3-135 

MM54HC163/MM74HC163 Synchronous Binary Counter 3-135 

MM54HC190/MM74HC190 Synchronous Decade Up/Down Counters with Mode Control 3-170 

MM54HC191/MM74HC191 Synchronous Binary Up/Down'Counters with Mode Control 3-170 

MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters 3-177 


8 




Table of Contents (continued) 

Counters (Continued) 

MM54HC193/MM74HC193 Synchronous Binary Up/Down Counters , 3-177 

MM54HC390/MM74HC390 Dual 4-Bit Decade Counter 3-276 

MM54HC393/MM74HC393 Dual 4-Bit Binary Counter 3-276 

MM54HC590/MM74HC590 8-Bit Binary Counter with TRI-STATE Output Register 3-315 

MM54HC592yMM74HC592 8-Bit Binary Counter with Input Register 3-317 

MM54HC593/MM74HC593 8-Bit Binary Counter with Bidirectional 

Input Register/Counter Outputs 3-317 

MM54HC4017/MM74HC4017 Decade Counter/Divider with 10 Decoded Outputs 3-365 

MM54HC4020/MM74HC4020 14-Stage Binary Counter 3-369 

MM54HC4024/MM74HC4024 7-Stage Binary Counter 3-369 

MM54HC4040/MM74HC4040 12-Stage Binary Counter 3-369 

MM54HC4060/MM74HC4060 14-Stage Binary Counter 3-393 

Decoders/ Encoders 

MM54HC42/MM74HC42BCD-to-Decimal Decoder 3-46 

MM54HC137/MM74HC137 3-to-8 Line Decoder with Address Latches (Inverted Output) 3-102 

MM54HC138/MM74HC138 3-to-8 Line Decoder 3-106 

MM54HC139/MM74HC139 Dual 2-to-4 Line Decoder 3-109 

MM54HC147/MM74HC147 10-to-4 Line Priority Encoder 3-112 

MM54HC149/MM74HC149 8-to-8 Line Priority Encoder 3-115 

MM54HC154/MM74HC154 4-to-16 Line Decoder 3-124 

MM54HC155/MM74HC155 Dual 2-to-4 Line Decoders 3-128 

MM54HC237/MM74HC237 3-to-8 Decoder with Address Latches 3-197 

MM54HC4514/MM74HC4514 4-to-16 Line Decoderwith Latch 3-418 

Flip-Flops 

MM54HC73/MM74HC73 Dual J-K Flip-Flops with Clear 3-52 

MM54HC74/MM74HC74 Dual D Flip-Flop with Preset and Clear 3-56 

MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear 3-62 

MM54HC107/MM74HC107DualJ-K Flip-Flops with Clear 3-73 

MM54HC109/MM74HC109 Dual J-K Flip-Flops with Preset and Clear 3-77 

MM54HC112/MM74HC112Dual J-K Flip-Flops with Preset and Clear 3-80 

MM54HC113/MM74HC113Dual J-K Flip-Flops with Preset 3-84 

MM54HC173/MM74HC173TRl-STATEQuadD Flip-Flop . 3-147 

MM54HC174/MM74HC174HexD Flip-Flops with Clear 3-151 

MM54HC175/MM74HC175 Quad D-Type Flip-Flop with Clear 3-154 

MM54HC273/MM74HC2730ctalD Flip-Flops with Clear 3-234 

MM54HC374/MM74HC374 TRI-STATE Octal D-Type Flip-Flop 3-273 

MM54HC534/MM74HC534TRI-STATEOctal D-Type Flip-Flop with Inverted Outputs 3-292 

MM54HC564/MM74HC564 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs 3-301 

MM54HC574/MM74HC574TRI-STATE Octal D-Type Flip-Flop 3-307 

Gates/ Inverters 

MM54HC00/MM74HC00Quad2-lnputNANDGate 3-7 

MM54HC02/MM74HC02 Quad 2-Input NOR Gate 3-10 

MM54HC03/MM74HC03 Quad 2-Input Open Drain NANDGate 3-13 

MM54HC04/MM74HC04 Hex Inverter 3-16 

MM54HC08/MM74HC08 Quad 2-Input AND Gate 3-22 


9 



Table of Contents (continued) 


Gates/ Inverters (Continued) 

MM54HC10/MM74HC10Triple3-lnput NANDGate 3-25 

MM54HC11/MM74HC11Triple3-lnputANDGate 3-28 

MM54HC14/MM74HC14 Hex Inverting Schmitt Trigger 3-31 

MM54HC20/MM74HC20 Dual 4-Input NANDGate 3-34 

MM54HC27/MM74HC27Triple3-lnputNORGate 3-37 

MM54HC30/MM74HC30 8-lnput NAND Gate 3-40 

MM54HC32/MM74HC32 Quad 2-Input OR Gate 3-43 

MM54HC51/MM74HC51 Dual AND-OR-Invert Gate 3-49 

MM54HC58/MM74HC58 Dual AND-OR Gate 3-49 

MM54HC86/MM74HC86Quad 2-Input Exclusive OR Gate 3-70 

MM54HC132/MM74HC132Quad2-lnputNANDSchmitt Trigger . . 3-96 

MM54HC133/MM74HC133 13-Input NAND Gate 3-99 

MM54HC266/MM74HC266 Quad 2-Input Exclusive NOR Gate 3-231 

MM54HC4002/MM74HC4002 Dual 4-Input NOR Gate 3-374 

MM54HC4049/MM74HC4049 Hex Inverting Logic Level Down Converter 3-400 

MM54HC4050/MM74HC4050 Hex Logic Level Down Converter 3-400 

MM54HC4075/MM74HC4075Triple3-lnputORGate 3-419 

MM54HC4078/MM74HC4078 8-lnput NOR/OR Gate 3-422 

MM54HCU04/MM74HCU04 Hex Inverter 3-19 

Latches 

MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Q Output 3-59 

MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder 3-227 

MM54HC373/MM74HC373 TRI-STATE Octal D-Type Latch 3-270 

MM54HC533/MM74HC533TRI-STATEOctalD-Type Latch with Inverted Outputs 3-289 

MM54HC563/MM74HC563 TRI-STATE Octal D-Type Latch 

with Inverted Outputs 3-298 

IVIM54HC573/MM74HC573 TRI-STATE Octal D-Type Latch . 3-304 

Modems 

MM74HC942 300 Baud Modem ( + 5, - 5 Volt Supply) 3-344 

MM74HC943 300 Baud Modem (5 Volt Supply) - 3-350 

Multiplexers/Demuitiplexers 

MM54HC151/MM74HC151 8-Channel Multiplexer 3-118 

MM54HC153/MM74HC153 Dual 4-Input Multiplexer 3-121 

MM54HC157/MM74HC157 Quad 2-Input Multiplexer' 3-131 

MM54HC158/MM74HC158 Quad 2-Input Multiplexer(lnverted Output) 3-131 

MM54HC251/MM74HC251 8-Channel TRI-STATE Multiplexer 3-218 

MM54HC253/MM74HC253 Dual 4-Channel TRI-STATE Multiplexer 3-221 

MM54HC257/MM74HC257 Quad 2-Channel TRI-STATE Multiplexer 3-224 

MM54HC298/MM74HC298 Quad 2-Input Multiplexers with Storage 3-246 

MM54HC354/MM74HC354 8-Channel TRI-STATE Multiplexers with Latches 3-255 

MM54HC356/MM74HC356 8-Channel TRI-STATE Multiplexers with Latches 3-255 

Multivibrators 

MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator 3-88 

MM54HC221A/MM74HC221 A Dual Non-Retriggerable Monostable Multivibrator 3-192 


10 



Table of Contents (Continued) 

Multivibrators (Continued) 

MM54HC423A/MM74HC423A Dual Retriggerable Monostable Multivibrator 3*281 

MM54HC4046/MM74HC4046CMOS Phase Lock Loop 3-374 

MM54HC4538/MM74HC4538 Dual Retriggerable Monostable Multivibrator 3-422 

Registers 

MM54HC164/MM74HC164 8-Bit Serial-In Parallel-Out Shift Register 3-140 

MM54HC165/MM74HC165 Parallel-In Serial-Out 8-Bit Shift Register 3-143 

MM54HC194/MM74HC194 4-Bit Bidirectional Shift Register 3-184 

MM54HC195/MM74HC195 4-Bit Parallel Shift Register 3-188 

MM54HC299/MM74HC299 8-Bit TRI-STATE Universal Shift Register 3-250 

MM54HC589/MM74HC589 8-Bit Shift Register with Input Latches and 

TRI-STATE Serial Output , 3-310 

MM54HC595/MM74HC595 8-Bit Shift Registers with Output Latches 3-320 

MM54HC597/MM74HC597 8-Bit Shift Registers with Input Latches 3-325 

Transceivers/ Registered Transceivers 

MM54HC242/MM74HC242 Inverting Quad TRI-STATETransceiver 3-206 

MM54HC243/MM74HC243QuadTRI-STATETransceiver 3-206 

MM54HC245/MM74HC245 0ctal TRI-STATETransceiver 3-214 

MM54HC640/MM74HC640 Inverting Octal TRI-STATETransceiver 3-330 

MM54HC643/MM74HC643True-lnverting Octal TRI-STATETransceiver 3-330 

MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers ‘ 3-334 

MM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers 3-334 

Section 4— MM54HCT/MM74HCT Data Sheets 

Arithmetic Functions 

MM54HCT521/MM74HCT521 8-Bit Magnitude Comparator (Equality Detector) 4-80 

MM54HCT688/MM74HCT688 8-Bit Magnitude Comparator(Equality Detector) 4-111 

Buffers/ Drivers 

MM54HCT240/MM74HCT240 Inverting Octal TRI-STATE Buffer 4-57 

MM54HCT241/MM74HCT241 Octal TRI-STATE Buffer 4-57 

MM54HCT244/MM74HCT244 Octal TRI-STATE Buffer 4-57 

MM54HCT540/MM74HCT540 Inverting Octal TRI-STATE Buffer 4-88 

MM54HCT541/MM74HCT541 Inverting Octal TRI-STATE Buffer 4-88 

Counters 

MM54HCT191/MM74HCT191 Synchronous Binary Up/Down Counters with Mode Control .... 4-46 

MM54HCT193/MM74HCT193 Synchronous Binary Up/Down Counters ! 4-52 

MM54HCT590/MM74HCT590 8-Bit Binary Counter with TRI-STATE Output Register 4-103 

MM54HCT592/MM74HCT592 8-Bit Binary Counter with Input Register i 4-105 

MM54HCT593/MM74HCT593 8-Bit Binary Counter with Bidirectional Input 
Register/Counter Outputs 4-105 

Decoders/Encoders 

MM54HCT138/MM74HCT138 3-to-8 Line Decoder 4-27 

MM54HCT139/MM74HCT139 Dual 2-to-4 Line Decoder 4-30 


11 




Table of Contents (Continued) 

Decoders/ Encoders (Continued) 

MM54HCT149/MM74HCT149 8-Line to 8-Line Priority Encoder 4-33 

MM54HCT155/MM74HCT155 Dual 2-to-4 Line Decoder/Demultiplexers 4-36 

Flip/Flops 

MM54HCT74/MM74HCT74 Dual D Flip-Flops with Preset and Clear 4-18 

MM54HCT76/MM74HCT76 Dual J-K Flip-Flops with Preset and Clear 4-21 

MM54HCT109/MM74HCT109 DuaIJrK Flip-Flops with Preset and Clear 4-24 

MM54HCT112/MM74HCT112 Dual J-K Flip-Flops with Preset and Clear 4-21 

MM54HCT273/MM74HCT273 Octal D Flip-Flop with Clear 4-68 

MM54HCT374/MM74HCT374TRI-STATEOctal D-Type Flip-Flop 4-75 

MM54HCT534/MM74HCT534TRI-STATEOctal D-Type Flip-Flop 4-83 

MM54HCT564/MM74HCT564TRl-STATEOctal D-Type Flip-Flop with Inverted Outputs 4-94 

MM54HCT574/MM74HCT574TRI-STATEOctal D-Type Flip-Flop 4-100 

Gates/ Inverters 

MM54HCT00/MM74HCT00 Quad 2-Input NAND Gate 4-5 

MM54HCT04/MM74HCT04 Hex Inverter 4-7 

MM54HCT05/MM74HCT05 Hex Open Drain Inverter 4-9 

MM54HCT08/MM74HCT08 Quad AND Gate , 4-12 

MM54HCT34/MM74HCT34 Non-Inverting Gate 4-15 

Latches 

MM54HCT373/MM74HCT373 TRI-STATE Octal D-Type Latch 4-75 

MM54HCT533/MM74HCT533TRI-STATE Octal D-Type Latch. 4-83 

MM54HCT563/MM74HCT563 TRI-STATE Octal D-Type Latch with Inverted Outputs 4-91 

MM54HCT573/MM74HCT573 TRI-STATE Octal D-Type Latch 4-97 

IVlultiplexers/ Demultiplexers 

MM54HCT157/MM74HCT157 Quad 2-Input Multiplexer 4-39 

MM54HCT158/MM74HCT158 Quad 2-Input Multlplexer(lnverted Output) 4-39 

MM54HCT257/MM74HCT257 Quad 2-Channel TRI-STATE Multiplexer 4-65 

Shift Registers 

MM54HCT164/MM74HCT164 8-Bit Serial-ln/Parallel-Out Shift Register 4-43 

MM54HCT299/MM74HCT299 8-Bit TRI-STATE Universal Shift Register 4-71 

MM54HCT323/MM74HCT323 8-Bit TRI-STATE Universal Shift Register 4-73 

Transceivers/ Registered Transceivers 

MM54HCT245/MM74HCT245 Octal TRI-STATE Transceiver 4-61 

MM54HCT640/MM74HCT640 Inverting Octal TRI-STATETransceiver 4-108 

MM54HCT643/MM74HCT643True-lnvertingOctalTRI-STATETranscelver 4-108 

Section 5— CD4XXX Series CMOS Logic 

Arithmetic Functions 

CD4008BM/CD4008BC 4-Bit Full Adder 5-30 


12 




Table of Contents (Continued) 

Buffers/ Drivers 

CD4009M/CD4009C Hex Buffer (Inverting) 5-33 

CD4010M/CD4010C Hex Buffer(Non-lnverting) 5-33 

CD4049UBM/CD4049UBC Hex Inverting Buffer 5-149 

CD4050BM/CD4050BC Hex Non-Inverting Buffer 5-149 

CD4093BM/CD4093BC Quad 2-Input NAND Schmitt Trigger 5-199 

CD40106BM/CD40106BC Hex Schmitt Trigger 5-214 

CD4503BM/CD4503BC Hex Non-Inverting TRI-STATE Buffer 5-231 

CD4584BM/CD4584BC Hex Schmitt Trigger(SeeCD40106 data sheet) 5-214 

Counters 

CD4017BM/CD4017BCDecadeCounter/Dividerwith10DecodedOutputs . . . : 5-55 

CD4018BM/CD4018BC Presettable Divide-by-N Counter 5-60 

CD4020BM/CD4020BC 14-Stage Ripple-Carry Binary Counter/Divider 5-67 

CD4022BM/CD4022BC Divide-by-8 Counter/Divider with 8 Decoded Outputs 5-55 

CD4024BM/CD4024BC 7-Stage Ripple-Carry Binary Counter/Divider 5-84 

CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter 5-94 

CD4040BM/CD4040BC 12-Stage Ripple Carry Binary Counter/Divider 5-67 

CD4060BM/CD4060BC 14-Stage Ripple Carry Binary Counter/Divider 5-67 

CD4089BM/CD4089BC Binary Rate Multiplier 5-192 

CD40160BM/CD40160BC Decade Counter with Asynchronous Clear 5-218 

CD40161BM/CD40161BC Binary Counter with Asynchronous Clear 5-218 

CD40162BM/CD40162BC Decade Counter with Asynchronous Clear 5-218 

CD40163BM/CD40163BC Binary Counter with Asynchronous Clear 5-218 

CD40192BM/CD40192BCSynchronous4-Bit Up/Down Decade Counter ; 5-226 

CD40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter 5-226 

CD4510BM/CD4510BC BCD Up/Down Counter 5-235 

CD4516BM/CD4516BC Binary Up/Down Counter 5-235 

CD4518BM/CD4518BC Dual Synchronous Up Counter 5-258 

CD4520BM/CD4520BC Dual Synchronous Up Counter 5-258 

CD4522BM/CD4522BC Programmable Divide-by-n 4-Bit BCD Counter 5-267 

CD4526BM/CD4526BC Programmable Divide-by-n 4-Bit Binary Counter 5-267 

CD4527BM/CD4527BC BCD Rate Multiplier 5-192 

Decoders/ Encoders 

CD4028BM/CD4028BC BCD-to-Decimal Decoder 5-91 

CD451 1 BM/CD451 1 BC BCD-to-7-Segment Latch Decoder/Driver 5-242 

CD4514BM/CD4514BC 4-Bit Latched 4-to-1 6 Line Decoders 5-253 

CD4515BM/CD4515BC 4-Bit Latched 4-to-16 Line Decoders 5-253 

CD4529BM/CD4529BC Dual 4-Channel or Single 8-Channel Analog Data Selector 5-281 

CD4543BM/CD4543BC BCD-to-7-Segment Latch/Decoder/Driver for 
Liquid Crystal Displays 5-300 

Flip-Flops 

CD4013BM/CD4013BC Dual D Flip-Flop 5-35 

CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset 5-87 

CD4042BM/CD4042BC Quad Clocked D Latch 5-123 

CD4043BM/CD4043BC TRI-STATE NOR R/S Latches 5-127 

CD4044BM/CD4044BC TRI-STATE NAND R/S Latches 5-127 


13 




Table of Contents (Continued) 

Flip-Flops (Continued) 

CD4076BM/CD4076BC TRI-STATE Quad Flip-Flop 5-188 

CD4099BM/CD4099BC 8-Bit Addressable Latches 5-209 

CD40174BM/CD40174BC Hex D Flip-Flop 5-223 

CD40175BM/CD40175BCQuad D Flip-Flop 5-223 

CD4723BM/CD4723BC Dual 4-Blt Addressable Latch 5-306 

CD4724BM/CD4724BC 8-Bit Addressable Latch 5-306 

Gates/Inverters 

CD4000M/CD4000C Dual Input NOR Gate Plus Inverter 5-5 

CD4001M/CD4001C Quad 2-Input NOR Gate 5-8 

CD4001 BM/CD4001 BC Quad 2-Input NOR Buffered B Series Gate 5-12 

CD4002M/CD4002C Dual 4-Input NOR Gate 5-17 

CD4002BM/CD4002BC Dual 4-Input Buffered NOR Gate 5-21 

CD4007M/CD4007C Dual Complementary Pair Plus Inverter 5-27 

CD4011M/CD4011CQuad2-lnputNANDGate : 5-8 

CD401 1 BM/CD401 1 BC Quad 2-Input NAN D Buffered B Series Gate 5-12 

CD4012M/CD4012C Dual 4-Input NAND Gate 5-17 

CD4012BM/CD4012BC Dual 4-Input Buffered NAND Gate 5-21 

CD4019BM/CD4019BC Quad AND-OR Select Gate 5-64 

CD4023M/CD4023C Triple 3-Input NOR Gate 5-76 

CD4023BM/CD4023BC Triple 3-Input Buffered NANDGate 5-80 

CD4025M/CD4025CTriple3-lnputNANDGate 5-76 

CD4025BM/CD4025BC Triple 3-Input Buffered NOR Gate 5-80 

CD4030M/CD4030CQuad Exclusive-ORGate 5-100 

CD4041M/CD4041C Quad True/Complement Buffer 5-119 

CD4048BM/CD4048BC TRI-STATE Expandable 8-Functlon 8-Input Gate 5-143 

CD4069UBM/CD4069UBC Inverter Circuits 5-168 

CD4070BM/CD4070BC Quad 2-Input Exclusive-ORGate 5-172 

CD4071 BM/CD4071 BC Quad 2-Input OR Buffered B Series Gate 5-176 

CD4072BM/CD4072BC Dual 4-Input OR Buffered B Series Gate 5-181 

CD4073BM/CD4073BC Double Buffered Triple 3-Input AND Gate 5-184 

CD4075BM/CD4075BC Double Buffered Triple 3-Input OR Gate 5-184 

CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate 5-176 

CD4082BM/CD4082BC Dual 4-Input AND Buffered B Series Gate 5-181 

CD4519BM/CD4519BC 4-Bit AND/OR Selector 5-263 

Multiplexers/ Demultiplexers 

CD4016BM/CD4016BC Quad Bilateral Switch 5-48 

CD4051BM/CD4051BC Analog Multiplexers/Demultiplexers 5-154 

CD4052BM/CD4052BC Analog Multiplexers/Demultiplexers 5-154 

CD4053BM/CD4053BC Analog Multiplexers/Demultiplexers 5-154 

CD4066BM/CD4066BCQuad Bilateral Switch 5-162 

CD4512BM/CD4512BC 8-Channel Data Selector 5-248 

CD4529BM/CD4529BC Dual 4-Channel or Single 8-Channel Analog Data Selector 5-281 

Multivibrators 

CD4046BM/CD4046BC Micropower Phase-Locked Loop 5-131 

CD4047BM/CD4047BC Low Power Monostable/ Astable Multivibrator 5-138 


14 




Table of Contents (Continued) 

Multivibrators (Continued) 

CD4528BM/CD4528BC Dual Monostable Multivibrator 5-275 

CD4538BM/CD4538BC Dual Monostable Multivibrator 5-287 

CD4541BM/CD4541BC Progrannnnable Tinner with Oscillator 5-295 

Registers 

CD4006BM/CD4006BC1 8-Stage Static Shift Register 5-24 

CD4014BM/CD4014BC 8-Stage Static Shift Register 5-40 

CD4015BM/CD4015BC Dual 4-Bit Static Register : 5-44 

CD4021BM/CD4021BC 8-Stage Static Shift Register 5-72 

CD4031BM/CD4031BC 64-Stage Static Shift Register 5-103 

CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional Parallel/Serial 

Input/Output Bus Register 5-107 

CD4035BM/CD4035BC 4-Bit Parallel-ln/Parallel-Out Shift Register 5-115 

Section 6— MM54CXXX/MM74CXXX Series 

Arithmetic Functions 

MM54C83/MM74C83 4-Bit Binary Full Adder 6-34 

Buffers/ Drivers 

MM54C04/MM74C04 Hex Inverter 6-5 

MM54C14/MM74C14 Hex Schmitt Trigger 6-12 

MM54C240/MM74C240 Octal Buffers and Line Drivers with TRI-STATE 

Outputs(lnverting) 6-105 

MM54C244/MM74C244 Octal Buffers and Line Drivers with TRI-STATE 

Outputs (Non-Inverting) 6-105 

MM54C901/MM74C901 Hex Inverting TTL Buffer 6-117 

MM54C902/MM74C902Hex Non-Inverting Buffers 6-117 

MM54C903/MM74C903 Hex Inverting PMOS Buffer 6-117 

MM54C904/MM74C904 Hex Non-Inverting PMOS Buffers 6-117 

MM54C906/MM74C906 Hex Open Drain N-Channel Buffer 6-126 

MM54C907/MM74C907 Hex Open Drain P-Channel Buffer 6-126 

MM54C914/MM74C914 Hex Schmitt Triggerwith Extended Input Voltage 6-138 

MM54C941/MM74C941 Octal Buffers/Line Receivers/ Line Drivers with 

TRI-STATE Outputs 6-155 

MM70C95/MM80C95TRI-STATE Hex Buffers 6-164 

MM70C96/MM80C96TRI-STATE Hex Inverters 6-164 

MM70C97/MM80C97TRI-STATE Hex Buffers 6-164 

MM70C98/MM80C98TRI-STATE Hex Inverters 6-164 

MM74C908Dual CMOS 30 Volt Relay Driver 6-169 

MM74C911 4-Digit LED Display Controller 6-173 

MM74C912 6-Digit BCD LED Display Controller Driver 6-180 

MM74C917 6-Digit Hex LED Display Controller Driver 6-180 

MM74C918 Dual CMOS 30 Volt Relay Driver 6-169 

MM74C956 4Character LED Alphanumeric Display Controller Drlver(17-Segment) 6-204 

MM78C29/MM88C29 Quad Single-Ended Line Driver 6-208 

MM78C30/MM88C30 Dual Differential Line Driver 6-208 


15 





Table of Contents (continued) 

CMOS Memories 

MM54C89/MM74C89 64-Bit (16x4) TRI-STATE Random Access Memory 6-44 

MM54C200/MM74C200 256-Bit (256 X 1)TRI-STATE Random Access Memory 6-97 

. MM54C910/MM74C910 256-Bit (64x4) TRI-STATE Random Access Memory 6-134 

MM54C989/MM74C989 64-Bit (16 x 4) TRI-STATE Random Access Memory 6-160 

Comparators 

MM54C85/MM74C85 4-Bit Magnitude Comparator *. 6-38 

Counters 

MM54C90/MM74C90 4-Bit Decade Counter 6-48 

MM54C93/MM74C93 4-Bit Binary Counter 6-48 

MM54C160/MM74C160 Decade Counterwith Asynchronous Clear 6-68 

MM54C161/MM74C161 Binary Counterwith Asynchronous Clear 6-68 

MM54C162/MM74C162 Decade Counterwith Synchronous Clear 6-68 

MM54C163/MM74C163BinaryCounterwith Synchronous Clear :. 6-68 

MM54C192/MM74C192 Synchronous 4-Bit Up/Down Decade Counter 6-90 

MM54C193/MM74C193 Synchronous 4-Bit Up/Down Binary Counter 6-90 

MM74C925 4-Diglt Counterwith Multiplexed 7-Segment Output Driver ; . . 6-186 

MM74C926 4-Digit Counterwith Multiplexed 7-Segment Output Driver 6-186 

MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver 6-186 

MM74C928 4-Digit Counter with Multiplexed 7-Segment Output Driver 6-186 

MM74C945 4 1/2-Dlgit LCD Up Counter/Latch Driver 6-190 

MM74C946 4-Dlgit LCD Up-Down Counten/Latch/Driver 6-197 

MM74C947 4-Digit LCD Up-Down Counter/Latch/Driver ; 6-190 

Decoders/ Encoders 

MM54C42/MM74C42 BCD-to-Decimal Decoder 6-20 

MM54C48/MM74C48 BCD-to-7-Segment Decoder 6-22 

MM54C154/MM74C154 4-Line to 16-Line Decoder/Demultipiexer 6-63 

MM54C915/MM74C915 7-Segment-to-BCD Converter 6-141 

MM54C922/MM74C922 16-Key Keyboard Encoder 6-145 

MM54C923/MM74C923 20-Key Keyboard Encoder 6-145 

Flip-Flops 

MM54C74/MM74C74 Dual D Flip-Flop 6-30 

MM54C76/MM74C76DualJ-K Flip-Flops with Clear and Preset 6-27 

MM54C107/MM74C107 Dual J-K Flip-Flops with Clear ! 6-27 

MM54C173/MM74C173TRI-STATEQuadD Flip-Flop 6-81 

MM54C174/MM74C174 Hex D Flip-Flop 6-84 

MM54C175/MM74C175QuadD Flip-Flop 6-87 

MM54C374/MM74C374 0ctalD-Type Flip-Flop with TRI-STATE Outputs 6-110 

Gates/fnverters 

MM54C00/MM74C00 Quad 2-Input NAND Gate 6-5 

MM54C02/MM74C02 Quad 2-Input NOR Gate 6-5 

MM54C08/MM74C08 Quad 2-Input AND Gate 6-9 

MM54C10/MM74C10Triple3-lnputNANDGate 6-5 

MM54C20/MM74C20 Dual 4-Input NAND Gate 6-5 


16 




Table of Contents (continued) 

Gates/Inverters (Continued) 

MM54C30/MM74C30 8-Input NAND Gate 6-15 

MM54C32/MM74C32 Quad 2-Input OR Gate 6-18 

MM54C86/MM74C86 Quad 2-Input EXCLUSIVE-OR Gate 6-41 

MM54C909/MM74C909 Quad Comparator 6-129 

Latches 

MM54C73/MM74C73 Dual J-K Flip-Flops with Clear 6-27 

MM54C373/MM74C373 Octal Latch with TRI-STATE Outputs 6-110 

Multiplexers/Demultiplexers 

MM54C150/MM74C150 16-Line to 1-Line Multiplexer 6-54 

MM54C151/MM74C151 8-Channel Digital Multiplexer 6-59 

MM54C157/MM74C157 Quad 2-Input Multiplexer 6-66 

MM72C19/MM82C19TRI-STATE16-Lineto 1-Line Multiplexer 6-54 

Multivibrators 

MM54C221/MM74C221 Dual Monostable Multivibrator 6-101 

MM54C932/MM74C932 Phase Comparator 6-151 

Registers 

MM54C95/MM74C95 4-Bit Right-Shift/Left-Shift Register 6-52 

MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register 6-73 

MM54C165/MM74C165 ParalleLLoad 8-Bit Shift Register 6-77 

MM54C195/MM74C195 4-Bit Register 6-94 

Special Functions 

MM54C905/MM74C905 12-Bit Successive Approximation Register 6-121 

Section 7— LSI/ VLSI CMOS 

Display Drivers 

MM5450 LED Display Drivers i 7-32 

MM5451 LED Display Drivers ....'. 7-32 

MM5452 Liquid Crystal Display Drivers 7-37 

MM5453 Liquid Crystal Display Drivers 7-37 

MM5480 LED Display Driver 7-43 

MM5481 LED Display Driver 7-47 

MM5483 Liquid Crystal Display Driver 7-51 

MM5484 16-Segment LED Display Driver, 1 1 Segment LED Display Driver 7-54 

MM5485 16-Segment LED Display Driver, 1 1 Segment LED Display Driver 7-54 

MM5486 LED Display Driver 7-57 

MM58201 Multiplexed LCD Driver 7-85 

MM58241 High Voltage Display Driver 7-90 

MM58242 High Voltage 20 Output Vacuum Fluorescent Display Driver. 7-95 

MM58248 High Voltage 35 Output Vacuum Fluorescent Display Driver 7-100 

MM58341 High Voltage 32 Output Vacuum Fluorescent Display Driver 7-126 

MM58342 High Voltage 20 Output Fluorescent Display Driver 7-131 


17 




Table of Contents (Continued) 

Display Drivers (Continued) 

MM58348 High Voltage 35 Output Vacuum Fluorescent Display Driver 7-136 

MM58438 32-Bit LCD Display Driver 7-141 

MM58538 Multiplexed LCD8-Row/26-Column Driver 7-145 

MM58539 Multiplexed LCD 34-Column Driver 7-150 

MM58540 Multiplexed LCD 32-Row/32-Column Driver 7-155 

MM58548 Multiplexed LCD 16-Row/16-Column Driver 7-160 

Oscillators/ Dividers 

MM5368 CMOS Oscillator Divider Circuit 7-11 

MM5369 Series 17 Stage Oscillator/Divider 7-14 

MM53107 Series 17-Stage Oscillator/Divider 7-17 

Other (LSI, VLSI CMOS) 

MM5034, MM5035 Octal 80-Bit Static Shift Register 7-3 

MM5307 Baud Rate Generator/ Programmable Divider 7-6 

MM531 26 Infra Red Transmitter 7-19 

MM53226 Infra Red Transmitter 7-24 

M M5437 Noise Generator 7-29 

MM54240 Asynchronous Receiver/Transmitter Remote Controller 7-62 

MM58250 Infra Red Transmitter 7-105 

Real Time Clocks 

MM58167A Microprocessor Real Time Clock 7-70 

MM58174A Microprocessor Real Time Clock 7-78 

MM58274 Microprocessor Real Time Clock 7-113 

Section 8— Appendices/ Physical Dimensions 

Introduction to the Reliability Military/ Aerospace Programs 8-3 

Radiation Hardened Technologies from National Semiconductor 8-17 

Commercial Quality Enhancement Programs 8-33 

Silicon Gate Reliability Report 8-37 

Metal Gate Reliability Report 8-49 

Physical Dimensions 8-71 


18 




Alphanumeric Index 


AN-77 CMOS, The Ideal Logic Family 2-3 

AN-88 CMOS Linear Applications 2-11 

AN-90 54C/74C Family Characteristics 2-14 

AN-1 18 CMOS Oscillators ; 2-20 

AN-138 Using the CMOS Dual Monostable Multivibrator 2-24 

AN-140 CMOS Schmitt Trigger — A Uniquely Versatile Design Component 2-30 

AN-143 Using National Clock Integrated Circuits In Timer Applications 2-36 

AN-177 Designing with MM74C908, MM74C918 Dual High Voltage CMOS Drivers 2-40 

AN-248 Electrostatic Discharge Prevention — Input Protection Circuits and 

Handling Guide for CMOS Devices 2-52 

AN-249 MM54240 Asynchronous Receiver/Transmitter Remote Controller Applications 2-54 

AN-250 Applications and Usesof the MM5321 TV Camera Sync Generator 2-58 

AN-251 A Broadcast Quality TV Sync Generator Made Economical through LSI 2-62 

AN-257 Sinnplified Multi-Digit LED Display Design Using 

MM74C911/MM74C912/MM74C917 Display Controllers 2-68 

AN-303 HC-CMOS Power Dissipation 2-89 

AN-310 High-Speed CMOS (MM54HC/MM74HC) Processing 2-94 

AN'313 DC Electrical Characteristics of MM54HC/MM74HC High-Speed CMOS Logic 2-102 

AN-314 Interfacing to MM54HC/MM74HC High-Speed CMOS Logic 2-109 

AN-317ACCharacteristicsof MM54HC/MM74HCHigh-SpeedCMOS 2-119 

AN-319 Comparison of MM54HC/MM74HC to 54LS/74LS, 54S/74S and 

54ALS/74ALS Logic 2-124 

AN-339 National’s Process Enhancements Eliminate the CMOS SCR Latch-Up Problem 

in 54HC/74HC Logic 2-130 

AN-340 HCMOS Crystal Oscillators 2-138 

AN-347 MM74HC942 and MM74HC943 Design Guide 2-141 

AN-349 CMOS 300 Baud Modem 2-149 

AN-350 Designing an LCD Dot Matrix Display Interface 2-155 

AN-353 MM58167A Real Time Clock Design Guide 2-174 

AN-359 The MM58174A Real Time Clock In a Battery Backed-Up Design Provides 

Reliable Clock and Calendar Functions 2-192 

AN-365 The MM58274 Adds Reliable Real-Time Keeping to Any Microprocessor System 2-200 

AN-368 An Introduction to and Comparison of 54HCT/74HCT 

TTL Compatible CMOS Logic 2-215 

AN-371 MM58348/342/341/248 Directly Drive Vacuum Fluorescent (VF) Displays 2-221 

AN-375 HIgh-Speed-CMOS Designs Address Noise and I/O Levels 2-233 

AN-376 Logic-System Design Techniques Reduce Switching-CMOS Power 2-242 

AN-377 DC Noise Immunity of CMOS Logic Gates 2-253 


19 




Alphanumeric Index(continued) 

CD4000M/CD4000C Dual Input NOR Gate Plus Inverter 5-5 

CD4001 M/CD4001 C Quad 2-Input NOR Gate 5-8 

CD4001 BM/CD4001BC Quad 2-Input NOR Buffered B Series Gate 5-12 

CD4002M/CD4002C Dual 4-Input NOR Gate 5-17 

CD4002BM/CD4002BC Dual 4-Input Buffered NOR Gate 5-21 

CD4006BM/CD4006BC 18-Stage Static Shift Register 5-24 

CD4007M/CD4007C Dual Complementary Pair Plus Inverter 5-27 

CD4008BM/CD4008BC 4-Bit Full Adder 5-30 

CD4009M/CD4009C Hex Buffer (Inverting) 5-33 

CD4010M/CD4010C Hex Buffer(Non-lnverting) 5-33 

CD401 1 M/CD401 1C Quad 2-Input NAND Gate 5-8 

CD401 1 BM/CD401 1 BC Quad 2-Input NAND Buffered B Series Gate 5-12 

CD4012M/CD4012C Dual 4-Input NAND Gate 5-17 

CD4012BM/CD4012BC Dual 4-Input Buffered NAND Gate 5-21 

CD4013BM/CD4013BC Dual D Flip-Flop 5-35 

CD4014BM/CD4014BC 8-Stage Static Shift Register 5-40 

CD4015BM/CD4015BC Dual 4-Bit Static Register 5-44 

CD4016BM/CD4016BCQuad Bilateral Switch 5-48 

CD4017BM/CD4017BC Decade Counter/Dividerwith 10 Decoded Outputs 5-55 

CD4018BM/CD4018BC Presettable Divide-by-N Counter 5-60 

CD4019BM/CD4019BC Quad AND-OR Select Gate 5-64 

CD4020BM/CD4020BC 14-Stage Ripple-Carry Binary Counter/Divider * 5-67 

CD4021BM/CD4021BC 8-Stage Static Shift Register 5-72 

CD4022BM/CD4022BC Divide-by-8 Counter/Dividerwith 8 Decoded Outputs 5-55 

CD4023M/CD4023C Triple 3-Input NOR Gate 5-76 

CD4023BM/CD4023BC Triple 3-Input Buffered NAND Gate 5-80 

CD4024BM/CD4024BC 7-Stage Ripple-Carry Binary Counter/Divider 5-84 

CD4025M/CD4025CTriple3-lnputNANDGate 5-76 

CD4025BM/CD4025BC Triple 3-Input Buffered NOR Gate 5-80 

CD4027BM/CD4027BCDualJ-K Master/Slave Flip-Flop with Set and Reset 5-87 

CD4028BM/CD4028BC BCD-to-Decimal Decoder 5-91 

CD4029BM/CD4029BC Presettable Binary/ Decade Up/Down Counter 5-94 

CD4030M/CD4030C Quad ExclusIve-OR Gate 5-100 

CD4031BM/CD4031BC 64-$tage Static Shift Register 5-103 

CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional Parallel/Serial 

Input/Output Bus Register 5-107 

CD4035BM/CD4035BC 4-Bit Parallel-ln/Parallel-Out Shift Register 5-115 

CD4040BM/CD4040BC 12-Stage Ripple Carry Binary Counter/Divider 5-67 

* CD4041 M/CD4041C Quad True/Complemeht Buffer 5-119 

CD4042BM/CD4042BC Quad Clocked D Latch 5-123 

CD4043BM/CD4043BC TRI-STATE NOR R/S Latches 5-127 

CD4044BM/CD4044BC TRI-STATE NAND R/S Latches 5-127 

CD4046BM/CD4046BC Micropower Phase-Locked Loop 5-131 

CD4047BM/CD4047BC Low Power Monostable/ Astable Multivibrator 5-138 

CD4048BM/CD4048BC TRI-STATE Expandable 8-Function 8-Input Gate 5-143 

CD4049UBM/CD4049UBC Hex Inverting Buffer 5-149 

CD4050BM/CD4050BC Hex Non-Inverting Buffer ^ 5-149 

CD4051BM/CD4051BC Analog Multiplexers/Demultiplexers 5-154 

GD4052BM/CD4052BC Analog Multiplexers/Demultiplexers 5-154 

CD4053BM/CD4053BC Analog Multiplexers/Demultiplexers 5-154 

CD4060BM/CD4060BC 14-Stage Ripple Carry Binary Counter/Divider 5-67 


20 




Alphanumeric Indexicontmued) 

CD4066BM/CD4066BC Quad Bilateral Switch 5-162 

CD4069UBM/CD4069UBC Inverter Circuits 5-168 

CD4070BM/CD4070BC Quad 2-Input Exclusive-OR Gate 5-172 

CD4071 BM/CD4071 BC Quad 2-Input OR Buffered B Series Gate 5-176 

CD4072BM/CD4072BC Dual 4-Input OR Buffered B Series Gate 5-181 

CD4073BM/CD4073BC Double Buffered Triple 3-Input AND Gate 5-184 

CD4075BM/CD4075BC Double Buffered Triple 3-Input OR Gate 5-184 

CD4076BM/CD4076BC TRI-STATE Quad Flip-Flop 5-188 

CD4081 BM/CD4081 BC Quad 2-Input AND Buffered B Series Gate 5-176 

CD4082BM/CD4082BC Dual 4-Input AND Buffered B Series Gate 5-181 

CD4089BM/CD4089BC Binary Rate Multiplier 5-192 

CD4093BM/CD4093BCQuad2-lnputNANDSchmitt Trigger 5-199 

CD4094BM/CD4094BC 8-Stage Shift/Store Register 5-204 

CD4099BM/CD4099BC 8-Bit Addressable Latches 5-209 

CD40106BM/CD40106BC Hex Schmitt Trigger 5-214 

CD40160BM/CD40160BC Decade Counter with Asynchronous Clear'. 5-218 

CD40161BM/CD40161 BC Binary Counter with Asynchronous Clear 5-218 

CD40162BM/CD40162BC Decade Counter with Asynchronous Clear 5-218 

CD40163BM/CD40163BC Binary Counter with Asynchronous Clear 5-218 

CD40174BM/CD40174BC Hex D Flip-Flop 5-223 

CD40175BM/CD40175BCQuad D Flip-Flop 5-223 

CD40192BM/CD40192BC Synchronous 4-Bit Up/Down Decade Counter 5-226 

Cp40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter 5-226 

CD4503BM/CD4503BC Hex Non-Inverting TRI-STATE Buffer 5-231 

CD4510BM/CD4510BC BCD Up/Down Counter 5-235 

CD451 1 BM/CD451 1 BC BCD-to-7-Segment Latch Decoder/Driver 5-242 

CD4512BM/CD4512BC 8-Channel Data Selector 5-248 

CD4514BM/CD4514BC 4-Bit Latched 4-to-16 Line Decoders 5-253 

CD4515BM/CD4515BC 4-Bit Latched 4-to-16 Line Decoders 5-253 

CD4516BM/CD4516BC Binary Up/Down Counter 5-235 . 

CD4518BM/CD4518BC Dual Synchronous Up Counter 5-258 

CD4519BM/CD4519BC 4-Bit AND/OR Selector 5-263 

CD4520BM/CD4520BC Dual Synchronous Up Counter 5-258 

CD4522BM/CD4522BC Programmable Divide-by-n 4-Bit BCD Counter 5-267 

CD4526BM/CD4526BC Programmable Divide-by-n 4-Bit Binary Counter 5-267 

CD4527BM/CD4527BC BCD Rate Multiplier 5-192 

CD4528BM/CD4528BC Dual Monostable Multivibrator 5-275 

CD4529BM/CD4529BC Dual 4-Channel or Single 8-Channel Analog Data Selector 5-281 

CD4538BM/CD4538BC Dual Monostable Multivibrator 5-287 

CD4541BM/CD4541BC Programmable Timer with Oscillator 5-295 

CD4543BM/CD4543BC BCD-to-7-Segment Latch/Decoder/Driver for 

Liquid Crystal Displays 5-300 

CD4584BM/CD4584BC Hex Schmitt Trigger (See CD40106 data sheet) 5-214 

CD4723BM/CD4723BC Dual 4-Bit Addressable Latch 5-306 

CD4724BM/CD4724BC 8-Bit Addressable Latch 5-306 

MB-18 MM54C/74C VoltageTranslation/Buffering 2-257 

MM5034, MM5035 Octal 80-Bit Static Shift Register 7-3 

MM5307 Baud Rate Generator/Programmable Divider 7-6 

MM5368 CMOS Oscillator Divider Circuit ; .". . . 7-11 

MM5369Series17Stage Oscillator/Divider ' 7-14 

MM53107 Series 17-Stage Oscillator/Divider 7-17 


21 




Alphanumeric Index (continued) 

MM53126 Infra Red Transmitter 7-19 

MM53226 Infra Red Transmitter 7-24 

MM5437 Noise Generator 7-29 

MM5450, MM5451 LED Display Drivers 7-32 

MM5452, MM5453 Liquid Crystal Display Drivers 7-37 

MM5480 LED Display Driver . 7-43 

MM5481 LED Display Driver 7-47 

MM5483 Liquid Crystal Display Driver 7-51 

MM5484, MM5485 16-Segment LED Display Driver, 1 1 Segment LED Display Driver 7-54 

MM5486 LED Display Driver 7-57 

MM54240 Asynchronous Receiver/Transmitter Remote Controller 7-62 

MM58167A Microprocessor Real Time Clock 7-70 

MM58174A Microprocessor Real Time Clock 7-78 

MM58201 Multiplexed LCD Driver 7-85 

MM58241 High Voltage Display Driver ' 7-90 

MM58242 High Voltage 20 Output Vacuum Fluorescent Display Driver 7-95 

MM58248 High Voltage 35 Output Vacuum Fluorescent Display Driver 7-100 

MM58250 Infra Red Transmitter 7-105 

MM58274 Microprocessor Real Time Clock 7-113 

MM58341 High Voltage 32 Output Vacuum Fluorescent Display Driver 7-126 

MM58342 High Voltage 20 Output Fluorescent Display Driver 7-131 

MM58348 High Voltage 35 Output Vacuum Fluorescent Display Driver 7-136 

MM58438 32-Bit LCD Display Driver '. 7-141 

MM58538 Multiplexed LCD 8-Row/26-Column Driver 7-145 

MM58539 Multiplexed LCD 34-Column Driver 7-150 

MM58540 Multiplexed LCD 32-Row/32-Column Driver 7-155 

MM58548 Multiplexed LCD 16-Row/16-Column Driver 7-160 

MM54C00/MM74C00 Quad 2-Input NANDGate 6-5 

MM54C02/MM74C02 Quad 2-Input NOR Gate 6-5 

MM54C04/MM74C04 Hex Inverter 6-5 

MM54C08/MM74C08Quad2-lnputANDGate 6-9 

MM54C10/MM74C10Triple3-lnput NANDGate 6-5 

MM54C14/MM74C14 Hex Schmitt Trigger 6-12 . 

MM54C20/MM74C20 Dual 4-Input NANDGate 6-5 

MM54C30/MM74C30 8-Input NAND Gate 6-15 

MM54C32/MM74C32‘Quad 2-Input OR Gate 6-18 

MM54C42/MM74C42 BCD-to-Decimal Decoder 6-20 

MM54C48/MM74C48 BCD-to-7-Segment Decoder 6-22 

MM54C73/MM74C73 Dual J-K Flip-Flops with Clear 6-27 

MM54C74/MM74C74 Dual D Flip-Flop 6-30 

MM54C76/MM74C76Dual J-K Flip-Flops with Clear and Preset 6-27 

MM54C83/MM74C83 4-Bit Binary Full Adder 6-34 

MM54C85/MM74C85 4-Bit Magnitude Comparator 6-38 

MM54C86/MM74C86 Quad 2-Input EXCLUSIVE-OR Gate .' 6-41 

MM54C89/MM74C89 64-Bit (16 X 4) TRI-STATE Random Access Memory 6-44 

MM54C90/MM74C90 4-Bit Decade Counter : 6-48 

MM54C93/MM74C93 4-Bit Binary Counter 6-48* 

MM54C95/MM74C95 4-Bit Right-Shift/Left-Shift Register 6-52 

MM54C107/MM74C107 Dual J-K Flip-Flops with Clear 6-27 

MM54C150/MM74C150 16-Line to 1-Line Multiplexer 6-54 

MM54C151/MM74C151 8-Channel Digital Multiplexer 6-59 

MM54C154/MM74C154 4-Line to 16-Line Decoder/Demultiplexer 6-63 


22 




Alphanumeric Index (continued) 

MM54C157/MM74C157 Quad 2-input Multiplexer 6-66 

MM54C160/MM74C160 Decade Counterwith Asynchronous Clear 6-68 

MM54C161/MM74C161 Binary Counterwith Asynchronous Clear 6-68 

MM54C162/MM74C162 Decade Counterwith Synchronous Clear 6-68 

MM54C163/MM74C163 Binary Counterwith SynchronousClear 6-68 

MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register 6-73 

MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register 6-77 

MM54C173/MM74C173TRI-STATEQuadD Flip-Flop 6-81 

MM54C174/MM74C174 Hex D Flip-Flop 6-84 

MM54C175/MM74C175QuadD Flip-Flop 6-87 

MM54C192/MM74C192 Synchronous 4-Bit Up/Down Decade Counter 6-90 

MM54C193/MM74C193 Synchronous 4-Bit Up/Down Binary Counter 6-90 

MM54C195/MM74C195 4-Bit Register 6-94 

MM54C200/MM74C200 256-Bit (256 x 1) TRI-STATE Random Access Memory 6-97 

MM54C221/MM74C221 Dual Monostable Multivibrator 6-101 

MM54C240/MM74C240 Octal Buffers and Line Drivers with TRI-STATE 

Outputs(lnverting) 6-105 

MM54C244/MM74C244 Octal Buffers and Line Drivers with TRI-STATE 

Outputs (Non-Inverting) 6-105 

MM54C373/MM74C373 Octal Latch with TRI-STATE Outputs 6-110 

MM54C374/MM74C374 Octal D-Type Flip-Flop with TRI-STATE Outputs 6-110 

MM54C901/MM74C901 Hex Inverting TTL Buffer 6-117 

MM54C902/MM74C902 Hex Non-Inverting Buffers , 6-117 

MM54C903/MM74C903 Hex Inverting PMOS Buffer 6-117 

MM54C904/MM74C904 Hex Non-Inverting PMOS Buffers 6-117 

MM54C905/MM74C905 12-Bit Successive Approximation Register 6-121 

MM54C906/MM74C906 Hex Open Drain N-Channel Buffer 6-126 

MM54C907/MM74C907 Hex Open Drain P-Channel Buffer 6-126 

M M54C909/ M M74C909 Quad Com parator 6-129 

MM54C910/MM74C910 256-Bit (64 X 4) TRI-STATE Random Access Memory 6-134 

MM54C914/MM74C914 Hex Schmitt Triggerwith Extended Input Voltage 6-138 

MM54C915/MM74C915 7-Segment-to-BCD Converter 6-141 

MM54C922/MM74C922 16-Key Keyboard Encoder : 6-145 

MM54C923/MM74C923 20-Key Keyboard Encoder 6-145 

MM54C932/MM74C932 Phase Comparator 6-151 

MM54C941/MM74C941 Octal Buffers/Line Receivers/Line Drivers with 

TRI-STATE Outputs 6-155 

MM54C989/MM74C989 64-Bit (16 X 4) TRI-STATE Random Access Memory 6-160 

MM70C95/MM80C95TRI-STATE Hex Buffers ' 6-164 

MM70C96/MM80C96TRI-STATE Hex Inverters 6-164 

MM70C97/MM80C97TRI-STATE Hex Buffers 6-164 

MM70C98/MM80C98TRI-STATE Hex Inverters 6-164 

MM72C19/MM82C19TRI-STATE 16-Line to 1-Line Multiplexer 6-54 

MM74C908Dual CMOS 30 Volt Relay Driver ■ 6-169 

MM74C911 4-Digit LED Display Controller 6-173 

MM74C912 6-Digit BCD LED Display Controller Driver 6-180 

MM74C917 6-Digit Hex LED Display Controller Driver 6-180 

MM74C918 Dual CMOS30Volt Relay Driver 6-169 

MM74C925 4-Digit Counter with Multiplexed 7-Segment Output Driver 6-186 

MM74C926 4-Digit Counter with Multiplexed 7-Segment Output Driver 6-186 

MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver 6-186 

MM74C928 4-Digit Counter with Multiplexed 7-Segment Output Driver 6-186 


23 





Alphanumeric Index (continued) 

MM74C945 4 1 /2-Digit LCD Up Counter/Latch Driver 6-190 

MM74C946 4-Digit LCD Up-Down Counter/Latch/Driver 6-197 

MM74C947 4-Digit LCD Up-Down Counter/Latch/Driver 6-190 

MM74C956 4Character LED Alphanumeric Display Controller Driver(17-Segment) 6-204 

MM78C29/MM88C29 Quad Single-Ended Line Driver 6-208 

MM78C30/MM88C30 Dual Differential Line Driver 6-208 

MM54HC00/MM74HC00Quad2-lnputNANDGate 3-7 

MM54HC02/MM74HC02 Quad 2-Input NOR Gate 3-10 

MM54HC03/MM74HC03,Quad 2-Input Open Drain NAND Gate 3-13 

MM54HC04/MM74HC04 Hex Inverter 3-16 

MM54HCU04/MM74HCU04 Hex Inverter : . . 3-19 

MM54HC08/MM74HC08Quad2-lnputANDGate 3-22 

MM54HC10/MM74HC10Triple3-lnputNANDGate 3-25 

MM54HC11/MM74HC11Triple3-lnputANDGate 3-28 

MM54HC14/MM74HC14 Hex Inverting Schmitt Trigger 3-31 

MM54HC20/MM74HC20 Dual 4-Input NAND Gate 3-34 

MM54HC27/MM74HC27Triple3-lnputNORGate 3-37 

MM54HC30/MM74HC30 8-Input NAND Gate 3-40 

MM54HC32/MM74HC32 Quad 2-Input OR Gate 3-43 

MM54HC42/MM74HC42BCD-to-Declmal Decoder 3-46 

MM54HC51/MM74HC51 Dual AND-OR-Invert Gate 3-49 

MM54HC58/MM74HC58 Dual AND-OR Gate 3-49 

MM54HC73/MM74HC73 Dual J-K Flip-Flops with Clear 3-52 

MM54HC74/MM74HC74 Dual D Flip-Flop with Preset and Clear '. 3-56 

MM54HC75/MM74HC75 4-Blt Bistable Latch with Q and Q Output 3-59 

MM54HC76/MM74HC76DualJ-KFlip-Flopswith Preset and Clear 3-62 

MM54HC85/MM74HC85 4-Bit Magnitude Comparator 3-66 

MM54HC86/MM74HC86 Quad 2-Input Exclusive OR Gate 3-70 

MM54HC107/MM74HC107DualJ-K Flip-Flops with Clear 3-73 

MM54HC109/MM74HC109 Dual J-K Flip-Flops with Preset and Clear 3-77 

MM54HC112/MM74HC1 12 DualJ-K Flip-Flops with Preset and Clear.’ 3-80 

MM54HC1 13/MM74HC1 13 Dual J-K Flip-Flops with Preset 3-84 

MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator 3-88 

MM54HC125/MM74HC125TRI-STATEQuad Buffers 3-93 

MM54HC126/MM74HC126TRI-STATEQuad Buffers 3-93 

MM54HC132/MM74HC132 Quad 2-Input NAND Schmitt Trigger 3-96 

MM54HC133/MM74HC133 13-Input NANDGate ^ 3-99 

MM54HC137/MM74HC137 3-to-8 Line Decoder with Address Latches (Inverted Output) 3-102 

MM54HC138/MM74HC138 3-to-8 Line Decoder 3-106 

MM54HC139/MM74HC139 Dual 2-to-4 Line Decoder 3-109 

MM54HC147/MM74HC147 10-to-4 Line Priority Encoder 3-112 

MM54HC149/MM74HC149 8-to-8 Line Priority Encoder 3-115 

MM54HC151/MM74HC151 8-Channel Multiplexer 3-118 

MM54HC153/MM74HC153 Dual 4-Input Multiplexer 3-121 

MM54HC154/MM74HC154 4-to-16 Line Decoder 3-124 

MM54HC155/MM74HC155 Dual 2-to-4 Line Decoders 3-128 

MM54HC157/MM74HC157 Quad 2-input Multiplexer 3-131 

MM54HC158/MM74HC158 Quad 2-Input Multiplexer(lnverted Output) 3-131 

MM54HC160/MM74HC16d Synchronous Decade Counter 3-135 

MM54|HC161/MM74HC161 Synchronous Binary Counter 3-135 

MM54HC162/MM74HC162 Synchronous Decade Counter ' 3-135 


24 





Alphanumeric Index (continued) 

MM54HC163/MM74HC163Synchronous Binary Counter 3-135 

MM54HC164/MM74HC164 8-Bit Serial-In Parallel-Out Shift Register 3-140 

MM54HC165/MM74HC165 Parallel-In Serial-Out 8-BitShift Register 3-143 

MM54HC173/MM74HC173TRI-STATE Quad D Flip-Flop 3-147 

MM54HC174/MM74HC174 Hex D Flip-Flops with Clear 3-151 

MM54HC175/MM74HC175 Quad D-Type Flip-Flop with Clear 3-154 

MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators 3-158 

MM54HC182/MM74HC182 Look-Ahead Carry Generator 3-166 

MM54HC190/MM74HC190Synchronous Decade Up/Down Counters with Mode Control 3-170 

MM54HC191/MM74HC191 Synchronous Binary Up/Down Counters with Mode Control 3-170 

MM54HC192/MM74HC192Synchronous Decade Up/Down Counters 3-177 

MM54HC193/MM74HC193SynchronousBinaryUp/DownCounters . . . . ; 3-177 

MM54HC194/MM74HC194 4-Bit Bidirectional Shift Register 3-184 

MM54HC195/MM74HC195 4-Bit Parallel Shift Register 3-188 

MM54HC221 A/MM74HC221 A Dual Non-Retriggerable Monostable Multivibrator 3-192 

MM54HC237/MM74HC237 3-to-8 Decoder with Address Latches 3-197 

MM54HC240/MM74HC240 Inverting Octal TRI-STATE Buffer 3-201 

MM54HC241/MM74HC2410ctalTRI-STATEBuffer 3-201 

MM54HC242/MM74HC242 Inverting Quad TRI-STATETransceiver 3-206 

MM54HC243/MM74HC243QuadTRI-STATETransceiver 3-206 

MM54HC244/MM74HC2440ctal TRI-STATE Buffer 3-210 

MM54HC245/MM74HC245 Octal TRI-STATETransceiver 3-214 

MM54HC251/MM74HC251 8-Channel TRI-STATE Multiplexer 3-218 

MM54HC253/MM74HC253 Dual 4-Channel TRI-STATE Multiplexer 3-221 

MM54HC257/MM74HC257 Quad 2-Channel TRI-STATE Multiplexer 3-224 

MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder 3-227 

MM54HC266/MM74HC266 Quad 2-Input Exclusive NOR Gate 3-231 

MM54HC273/MM74HC273 Octal D Flip-Flops with Clear 3-234 

MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker 3-238 

MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry 3-241 

MM54HC298/MM74HC298Quad2-lnputMultiplexerswithStorage 3-246 

MM54HC299/MM74HC299 8-Bit TRI-STATE Universal Shift Register 3-250 

MM54HC354/MM74HC354 8-Channel TRI-STATE Multiplexers with Latches 3-255 

MM54HC356/MM74HC356 8-Channel TRI-STATE Multiplexers with Latches 3-255 

MM54HC365/MM74HC365 Hex TRI-STATE Buffer i 3-263 

MM54HC366/MM74HC366 Inverting Hex TRI-STATE Buffer 3-263 

MM54HC367/MM74HC367HexTRI-STATE Buffer '. 3-263 

MM54HC368/MM74HC368lnverting Hex TRI-STATE Buffer 3-263 

MM54HC373/MM74HC373TRI-STATE Octal D-Type Latch 3-270 

MM54HC374/MM74HC374TRI-STATEOctal D-Type Flip-Flop 3-273 

MM54HC390/MM74HC390 Dual 4-Bit Decade Counter 3-276 

MM54HC393/MM74HC393Dual4-BitBinaryCounter 3-276 

MM54HC423A/MM74HC423A Dual Retriggerable Monostable Multivibrator 3-281 

MM54HC521/MM74HC521 8-Bit Magnitude Comparator(Equality Detector) 3-286 

MM54HC533/MM74HC533TRI-STATEOctal D-Type Latch with InvertedOutputs 3-289 

MM54HC534/MM74HC534 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs 3-292 

MM54HC540/MM74HC540 Inverting Octal TRI-STATE Buffer 3-295 

MM54HC541/MM74HC541 Octal TRI-STATE Buffer 3-295 

MM54HC563/MM74HC563 TRI-STATE Octal D-Type Latch with Inverted Outputs 3-298 

MM54HC564/MM74HC564TRI-STATEOctal D-Type Flip-Flip with InvertedOutputs 3-301 

MM54HC573/MM74HC573 TRI-STATE Octal D-Type Latch 3-304 


25 





Alphanumeric Index(continued) 

MM54HC574/MM74HC574TR1-STATE Octal D-Type Flip-Flop 3-307 

MM54HC589/MM74HC589 8-Bit Shift Register with Input Latches and 

TRI-STATE Serial Output 3-310 

"M M 54 H 0590/ MM 74 H 0590 8-Bit Binary Oounter with TRI-STATE Output Register 3-315 

M M 54 H 0592/ MM 74 H 0592 8-Bit Binary Oounter with Input Register 3-317 

M M 54 H 0593/ MM 74 H 0593 8-Bit Binary Oounter with Bidirectional 

Input Register/Oounter Outputs : 3-317 

MM54H0595/MM74H0595 8-Bit Shift Registers with Output Latches 3-320 

MM54H0597/MM74H0597 8-Bit Shift Registers vyith Input Latches 3-325 

MM54H0640/MM74H0640 Inverting Octal TRI-STATETransceiver 3-330 

MM54H0643/MM74H0643 True-Inverting Octal TRI-STATETransceiver 3-330 

MM54H0646/MM74H0646 Non-Inverting Octal Bus Transceiver/Registers 3-334 

MM54H0648/MM74H0648 Inverting Octal Bus Transceiver/Registers 3-334 

M M 54 H 0688/ MM 74 H 0688 8-Bit Magnitude Oomparator(Equality Detector) 3-341 

MM54H04002/MM74H04002 Dual 4-Input NOR Gate 3-357 

MM54H04016/MM74H04016 Quad Analog Switch 3-360 

MM54H04017/MM74H04017 Decade Oounter/DIvider with 10 Decoded Outputs T 3-365 

MM54H04020/MM74H04020 14-Stage Binary Oounter 3-369 

MM54H04024/MM74H04024 7-Stage Binary Oounter. 3-369 

MM54H04040/MM74H04040 12-Stage Binary Oounter 3-369 

MM54H04046/MM74H04046 OMOS Phase Lock Loop 3-374 

MM54H04049/MM74H04049 Hex Inverting Logic Level Down Oonverter 3-383 

MM54H04050/MM74H04050 Hex Logic Level Down Oonverter 3-383 

MM54H04051/MM74H04051 8-Ohannel Analog Multiplexer 3-386 

MM54H04052/MM74H04052 Dual 4-Ohannel Analog Multiplexer 3-386 

MM54H04053/MM74H04053 Triple 2-Ohannel Analog Multiplexer 3-386 

MM54H04060/MM74H04060 14-Stage Binary Oounter 3-393 

MM54H04066/MM74H04066 Quad Analog Switch 3-397 

MM54HO4075/MM74HO4075Triple3-lnputORGate 3-402 

MM54HG4078/MM74HG4078 8-Input NOR/OR Gate 3-405 

MM54HG4316/MM74HG4316Quad Analog Switch with Level Translator 3-408 

MM54HG4511/MM74HG4511 BGD-to-7 Segment Latch/Decoder/Driver 3-413 

MM54I-IG4514/MM74HG4514 4-to-1 6 Line Decoder with Latch 3-418 

MM54HG4538/MM74HG4538 Dual Retriggerable Monostable Multivibrator 3-422 

MM54HG4543/MM74HG4543 BGD-to-7 Segment Latch/Decoder/Driver for 

Liquid Grystal Displays 3-428 

MM74HG942 300 Baud Modem ( -f- 5, -5 Volt Supply) 3-344 

MM74HG943 300 Baud Modem (5 Volt Supply) 3-350 

MM54HGT00/MM74HGT00 Quad 2-Input NAND Gate 4-5 

MM54HGT04/MM74HGT04 Hex Inverter 4-7 

MM54HGT05/MM74HGT05 Hex Open Drain Inverter : 4-9 

MM54HGT08/MM74HGT08QuadANDGate 4-12 

MM54HGT34/MM74HGT34 Non-Inverting Gate 4-15 

MM54HGT74/MM74HGT74 Dual D Flip-Flops.with Preset and Olear 4-18 

MM54HGT76/MM74HGT76 Dual J-K Rip-Flops with Preset and Olear 4-21 

MM54HGT109/MM74HGT109 Dual J-K Flip-Flops with Preset and Olear 4-24 

MM54HGT1 12/MM74HGT1 12 Dual J-K Flip-Flops with Preset and Olear 4-21 

MM54HGT138/MM74HGT138 3-to-8 Line Decoder 4-27 

, MM54HGT139/MM74HGT139 Dual 2-to-4 Line Decoder 4-30 

MM54HGT149/MM74HGT149 8-Line to 8-Line Priority Encod.er 4-33 

MM54HGT155/MM74HGT155 Dual 2-to-4 Line Decoder/Demultiplexers 4-36 


26 




Alphanumeric Index(continued) 

MM54HCT157/MM74HCT157 Quad 2-Input Multiplexer 4-39 

MM54HCT158/MM74HCT158 Quad 2-Input Multiplexer(lnverted Output) 4-39 

MM54HCT164/MM74HCT164 8-Bit Serial-ln/Parallel-Out Shift Register 4-43 

MM54i:lCT191/MM74HCT191 Synchronous Binary Up/Down Counters with Mode Control .... 4-46 

MM54HCT193/MM74HCT193Synchronous Binary Up/Down Counters 4-52 

MM54HCT240/MM74HCT240 Inverting Octal TRI-STATE Buffer 4-57 

MM54HCT241/MM74HCT241 Octal TRI-STATE Buffer 4-57 

MM54HCT244/MM74HCT244 Octal TRI-STATE Buffer 4-57 

MM54HCT245/MM74HCT245 Octal TRI-STATE Transceiver 4-61 

MM54HCT257/MM74HCT257 Quad 2-Channel TRI-STATE Multiplexer 4-65 

MM54HCT273/MM74HCT273 Octal D Flip-Flop with Clear 4-68 

MM54HCT299/MM74HCT299 8-Bit TRI-STATE Universal Shift Register ,. 4-71 

MM54HCT323/MM74HCT323 8-Bit TRI-STATE Universal Shift Register 4-73 

MM54HCT373/MM74HCT373TRI-STATEOctal D-TypeLatch 4-75 

MM54HCT374/MM74HCT374 TRI-STATE Octal D-Type Flip-Flop 4-75 

MM54HCT521/MM74HCT521 8-Bit Magnitude Comparator (Equality Detector) 4-80 

MM54HCT533/MM74.HCT533 TRI-STATE Octal D-Type Latch 4-83 

MM54HCT534/MM74HCT534TRI-STATEOctal D-Type Flip-Flop 4-83 

MM54HCT540/MM74HCT540 Inverting Octal TRI-STATE Buffer 4-88 

MM54HCT541/MM74HCT541 Inverting Octal TRI-STATE Buffer 4-88 

MM54HCT563/MM74HCT563 TRI-STATE Octal D-Type Latch with Inverted Outputs 4-91 

MM54HCT564/MM74HCT564TRI-STATEOctal D-Type Flip-Flop with Inverted Outputs 4-94 

MM54HCT573/MM74HCT573TRI-STATE Octal D-Type Latch 4-97 

MM54HCT574/MM74HCT574TRI-STATE Octal D-Type Flip-Flop . . . . ; 4-100 

MM54HCT590/MM74HCT590 8-Bit Binary Counter with TRI-STATE Output Register 4-103 

MM54HCT592/MM74HCT592 8-Blt Binary Counter with Input Register 4-105 

MM54HCT593/MM74HCT593 8-Blt Binary Counter with Bidirectional Input 

Register/Counter Outputs 4-105 

MM54HCT640/MM74HCT640 Inverting Octal TRI-STATE Transceiver 4-108 

MM54HCT643/MM74HCT643 True-Inverting Octal TRl-STATETransceiver 4-108 

MM54HCT688/MM74HCT688 8-Bit Magnitude Comparator{Equality Detector) 4-111 


27 








Section Contents 

MM54HC/IV1M74HC 1-4 

MIVI54HCT/MM74HCT 1-6 

CD4000 1-8 

MM54C/MM74C 1-10 


1-2 



AC Parameter Definitions 

^MAX Operating frequency. This is the fastest speed that a 
circuit can be toggled. 

tpHL Propagation delay from input to output; output going 
high to low. 

tpLH Propagation delay from input to output; output going 
low to high. 

fpzH Enable propagation delay time. This is measured 
from the input to the output going to an active high 
level from TRI-STATE®. 

tpzL Enable propagation delay time. This is measured 
from the input to the output going to an active low 
level from TRI-STATE. 

tpHz Disable propagation delay time to the output going 
from an active high level to TRI-STATE, 
tptz Disable propagation delay time to the output going 
from an active low level to TRI-STATE, 
tw Input signal pulse width. 

ts input setup time. This is the time that data must be 

present prior to clocking input transitioning, 
tn Input hold time. This is the time that data must re- 
main after clocking input has transitioned. 
tREM Clock removal time. This is the time that an active 
clear or enable signal must be removed before the 
clock input transitions. (Sometimes called recovery 
time) 

tp Input signal rise time. 

tf Input signal fall time. 

tTLH Output rise time (transition time low to high) 

fTHL Output fall time (transition time high to low) 



1-3 


CMOS AC Diagrams 



CMOS AC Diagrams 







MM54HC/MM74HC AC Switching Test 
Circuits and Timing Waveforms (Continued) 





CMOS AC Diagrams 


MM54HCT/MM74HCT AC Switching Test 
Circuits and Timing Waveforms 




Test Circuit for Push Puil Outputs 


Test Circuit for TRi-STATE and Open Drain Output 
Tests (Notes 2 and 3) 



Test Circuit for Open Drain Outputs 


Note 1: Cl includes load and test jig capacitance. 

Note 2: S1 = Vcc for tpzL. and tpLz measurements. 

S1 = Gnd for tpzH. and tpnz measurements. 

Note 3: For open drain circuits S1 = Vcc and measurements are the same 
as tpzL and tpLz- 


-+•90% 

INPUT -+-1.3V 


*— tf = 6 ns — s 
-90% 90% ‘ 


tf = 6 ns 
...I. 3.0V 


— — gmd 



TL/F/5376-9 


Propagation Delay Waveforms 


1.3V 1.3V ■ 

^ 10 % 10 % -J/ 


tp — tf — 6 ns 


input Pulse Width Waveforms 


1-6 



MM54HCT/MM74HCT AC Switching Test 
Circuits and Timing Waveforms (Continued) 



Setup and Hold Time Waveforms 




Note 4: Waveform for negative edge sensitive circuits will be inverted. 

Note 5: This waveform is applicable to both TRI-STATE and open drain switching time measurements. 



1-7 


CMOS AC Diagrams 





CMOS AC Diagrams 







CD4000 AC Switching Test 
Circuits and Timing Waveforms (Continued) 





TRI-STATE Output Enable and Disable Waveforms 


Note 4: Waveform for negative edge sensitive circuits will be inverted. 



1-9 


CMOS AC Diagrams 





CMOS AC Diagrams 


MM54C/MM74C AC Switching Test 
Circuits and Timing Waveforms 



Toe 

-rr (NOTES 1 AND 3) 


Test Circuit for Push Puii Outputs 

Vcc 



T'e 

(NOTES 1 AND 3) 


Test Circuit for Open Drain Outputs 


T 

[(NOTES 1 AND 3) 


TL/F/5376-18 

Test Circuit for TRI-STATE Output Tests 


Note 1: Cl includes load and test jig capacitance. 

Note 2: SI = Vcc tpzu 3nd tpLz measurements. 

SI = Gnd for tpzn. and tpHz measurements. 
Note 3: See individual data sheet 
for component values. 


INPUT -f-50% 


t,==20ns fc-j 

tf=20ns 

^90% 

90% JU 



- 50% 

50% 'r 

^^10% 


.. L- 



GND 

r: ■ 



/ 



— VOM, 

-jL 50% 


A- 50% 


1.... L-. 



— VoL 


IPLH Hi 




TL/F/5376-24 


*— tr=20ns — ^ 

- 90% 90% ^ ^ 

0% 50% - 


Propagation Delay Waveforms 


-V 50% 50% -Jh 

Input Pulse Width Waveforms 


- tf = 20 ns 

TL/F/5376-25 


1-10 




CMOS AC Diagrams 






Section 2 

CMOS Application 
Notes 




Section Contents 

AN-77 CMOS, The Ideal Logic Family 2-3 

AN-88 CMOS Linear Applications 2-11 

AN-90 54C/74C Family Characteristics 2-14 

AN-1 18 CMOS Oscillators 2-20 

AN-138 Using the CMOS Dual Monostable Multivibrator 2-24 

AN-1 40 CMOS Schmitt Trigger — A Uniquely Versatile Design Component 2-30 

AN-143 Using National Clock Integrated Circuits in Timer Applications 2-36 

AN-177 Designing with MM74C908, MM74C918 Dual High Voltage CMOS Drivers 2-40 

AN-248 Electrostatic Discharge Prevention — Input Protection Circuits and 

Handling Guide for CMOS Devices 2-52 

AN-249 MM54240 Asynchronous Receiver/Transmitter Remote Controller Applications 2-54 

AN-250 Applicationsand Usesofthe MM5321 TV Camera Sync Generator 2-58 

AN-251 A Broadcast Quality TV Sync Generator Made Economical through LSI 2-62 

AN-257 Simplified Multi-Digit LED Display Design Using 

MM74C911/MM74C912/MM74C917 Display Controllers 2-68 

AN-303 HC-CMOS Power Dissipation 2-89 

AN-310 High-Speed CMOS (MM54HC/MM74HC) Processing 2-94 

AN-313 DC Electrical Characteristics of MM54HC/MM74HC High-Speed CMOS Logic 2-102 

AN-314 Interfacing to MM54HC/MM74HC High-Speed CMOS Logic 2-109 

AN-317ACCharacteristicsofMM54HC/MM74HCHigh-SpeedCMOS ■ 2-119 

AN-319 Comparison of MM54HC/MM74HC to 54LS/74LS, 54S/74S and 

54ALS/74ALS Logic. 2-124 

AN-339 National’s Process Enhancements Eliminate the CMOS SCR Latch-Up Problem 

in 54HC/74HC Logic 2-130 

AN-340 HCMOS Crystal Oscillators - 2-138 

AN-347 MM74HC942 and MM74HC943 Design Guide 2-141 

AN-349 CMOS 300 Baud Modem 2-149 

AN-350 Designing an LCD Dot Matrix Display Interface 2-155 

AN-353 MM58167A Real Time Clock Design Guide 2-174 

AN-359 The MM58174A Real Time Clock in a Battery Backed-Up Design Provides 

Reliable Clock and Calendar Functions 2-192 

AN-365 The MM58274 Adds Reliable Real-Time Keeping to Any Microprocessor System 2-200 

AN-368 An Introduction to and Comparison of 54HCT/74HCT 

TTL Compatible CMOS Logic 2-215 

AN-371 MM58348/342/341/248 Directly DriveVacuum Fluorescent (VF) Displays 2-221 

AN-375 High-Speed-CMOS Designs Address Noise and I/O Levels 2-233 

AN-376 Logic-System Design Techniques Reduce Switching-CMOS Power 2-242 

AN-377 DC Noise Immunity of CMOS Logic Gates 2-253 

MB-18 MM54C/74C Voltage Translation/Buffering ; 2-257 


2-2 




CMOS, the Ideal 
Logic Family 


INTRODUCTION 

Let's talk about the characteristics of an ideal logic 
family. It should dissipate no power, have zero 
propagation delay, controlled rise and fall times, 
and have noise immunity equal to 50% of the 
logic swing. 

The properties of CMOS (bomplementary MOS) 
begin to approach these ideal characteristics. 

First, CMOS dissipates low power. Typically, the 
static power dissipation is 10 nW per gate which is 
due to the flow of leakage currents. The active 
power depends on power supply voltage, frequency, 
output load and input rise time, but typically, gate 
dissipation at IMHz with a 50 pF load is less than 
lOmW. 

Second, the propagation delays through CMOS are 
short, though not quite zero. Depending on power 
supply voltage, the delay through a typical gate is 
on the order of 25 to 50 ns. 

Third, rise and fall times are controlled, tending 
to be ramps rather than step functions. Typically, 
rise and fall times tend to be 20 to 40% longer 
than the propagation delays. 

Last, but not least, the noise immunity approaches 
50%, being typically 45% of the full logic swing. 

Besides the fact that it approaches the characteris- 
tics of an ideal logic family and besides the obvious 
low power battery applications, why should de- 
signers choose CMOS for new systems? The answer 
is cost. 

On a component basis, CMOS is still more expen- 
sive than TTL. However, system level cost may be 


National Semiconductor 
Application Note 77 
Stephen Calebotta 
January 1983 


lower. The power supplies in a CMOS system will 
be cheaper since they can be made smaller and with 
less regulation. Because of lower currents, the 
power supply distribution system can be simpler 
and therefore, cheaper. Fans and other cooling 
equipment are not needed due to the lower dissi- 
pation. Because of longer rise and fall times, the 
transmission of digital signals becomes simpler 
making transmission techniques less expensive. 
Finally, there is no technical reason why CMOS 
prices cannot approach present day TTL prices as 
sales volume and manufacturing experience in- 
crease. So, an engineer about to start a new design 
should compare the system level cost of using 
CMOS or some other logic family. He may find 
that, even at today's prices, CMOS is the most 
economical choice. 

National is building two lines of CMOS. The first 
is a number of parts of the CD4000A series. The 
second is the 54C/74C series which National 
introduced and which will become the industry 
standard in the near future. 

The 54C/74C line consists of CMOS parts which 
are pin and functional equivalents of many of the 
most popular parts in the 7400 TTL series. This 
line is typically 50% faster than the 4000A series 
and sinks 50% more current. For ease of design, it 
is spec'd at TTL levels as well as CMOS levels, and 
there are two temperature ranges available: 54C, 
-55°Cto +125°C or 74C, -40°C to +85°C. Table I 
compares the port parameters of the 54C/74C 
CMOS line to those of the 54L/74L low power 
TTL line. 



TABLE I. Comparison of 54L/74L Low Power TTL and 54C/74C CMOS Port Parameters 


FAMILY 

Vcc 

VlL 

MAX 

l|L 

MAX 

V|H 

MIN 

•tH 

2.4V 

VoL 

MAX 

•OL 

VoH 

MIN 

•oh 

'pdO 

TYP 

tpdi 

TYP 

Pdiss/gate 

STATIC 

Pdiss/gate 

1 MHz, 50 pF LOAD 

54L/74L 

5 

0 7 

0 18 mA 

20 

10 mA 

0-3 

2 0 mA 

24 

lOO/iA 

31 

35 

1 mW 

2 25 mW 

54C/74C 

5 

08 

- 

3.5 

- 

0.4 

•360mA 

24 

'\00nA 

60 

45 

0 00001 mW 

1.25 mW 

54C/74C 

10 

2.0 

- 

80 


1 0 

"^0^A 

9.0 

"IOmA 

25 

30 

0 00003 mW 

5 mW 


*Assumes interfacing to low power TTL. 
** Assumes interfacing to CMOS. 


2-3 


AN-77 



AN-77 


CHARACTERISTICS OF CMOS 

The aim of this section is to give the system 
designer not familiar with CMOS, a good feel for 
how it works and how it behaves in a system. 
Much has been written about MOS devices in 
general. Therefore, we will not discuss the design 
and fabrication of CMOS transistors and circuits. 


The basic CMOS circuit is the inverter shown, in 
Figure 2-1. It consists of two MOS enhancement 
mode transistors, the upper a P-channe( type, the 
lower an N-channel type. 


Vrt 



FIGURE 2-1. Basic CMOS Inverter. 

The power supplies for CMOS are called Vqq and 
Vss, or Vqq and Ground depending on the manu- 
facturer. Vdq and Vss 3^® carryovers from con- 
ventional MOS circuits and stand for the drain and 
source supplies. These do not apply directly to 
CMOS since both supplies are really source supplies. 
Vqc and Ground are carryovers from TTL logic 
and that nomeclature has been retained with the 
introduction of the 54C/74C line of CMOS. V^c 
and Ground is the nomenclature we shall use 
throughout this paper. 


The logic levels in a CMOS system are Vqc (logic 
”1") and Ground (logic "0"). Since “on" MOS 
transistor has virtually no voltage drop across it if 
there is no current flowing through it, and since 
the input impedance to CMOS device is so high 
(the input characteristic of an MOS transistor is 
essentially capacitive, looking like a lO^^n resistor 
shunted by a 5 pF capacitor), the logic levels seen 
in a CMOS system will be essentially equal to the 
power supplies. 


Now let's look at the characteristic curves of 
MOS transistors to get an idea of how rise and 
fall times, propagation delays and power dissipation 
will vary with power supply voltage and capacitive 
loading. Figure 2-2 shows the characteristic curves 
of N-channel and P-channel enhancement mode 
transistors. 


There are a number of important observations to 
be made from these curves. Refer to the curve of 
Vqs 15V (Gate to Source Voltage) for the 

N-channel transistor. Note that for a constant 
drive voltage V^s, the transistor behaves like a 
current source for Vps's (Drain to Source Voltage) 
greater than Vqs “ Vj (Vj is the threshold 


voltage of an MOS transistor). For Vps's below 
Vqs “ Vy, the transistor behaves essentially like a 
resistor. Note also that for lower Vps's, there are 
similar curves except that the magnitude of the 
Ips's are significantly smaller and that in fact, Ips 
increases approximately as the square of increasing 
Vgs- The P-channel transistor exhibits essentially 
identical, but complemented, characteristics. 



OUTPUT VOLTAGE Vqs IV) 


TL/F/6019-2 


OUTPUT VOLTAGE Vqs (V) 



FIGURE 2-2. Logical “1" Output Voltage vs 
Source Current. 


If we try to drive a capacitive load with these 
devices, we can see that the initial voltage change 
across the load will be ramp-like due to the current 
source characteristic followed by a rounding off 
due to the resistive characteristic dominating as 
Vps approaches zero. Referring this to our basic 
CMOS inverter in Figure 2-1, as Vps approaches 
zero, Vqut will approach Vqq or Ground depend- 
ing on whether the P-channel or N-channel transistor 
is conducting. 


Now if we increase Vqq and, therefore, Vqs ^he 
inverter must drive the capacitor through a larger 
voltage swing. However, for this same voltage 
increase, the drive capability (Ips) increased 
roughly as the square of Vqs therefore, the 
rise times and the propagation delays through the 
inverter as measured in Figure 2-3 have decreased. 


So, we can see that for a given design, and therefore 
fixed capacitive load, increasing the power supply 
voltage will increase the speed of the system. 


2-4 



Increasing V^c increases speed but it also increases 
power dissipation. This is true for two reasons. 
First, CV^f power increases. This is the power 
dissipated in a CMOS circuit, or any other circuit 
for that matter, when driving a capacitive load. 


transfer curves begin to round off (Figure 2-4d). As 
ViN passes through the region where both transis- 
tors are conducting, the currents flowing through 
the transistors cause voltage' drops across them 
giving the rounded characteristic. 



FIGURE 2-3. Rise and Fall Times and Propagation 

Delays as Measured in a CMOS System. 


For a given capacitive load and switching frequency, 
power dissipation increases as the square of the 
voltage change across the load. 

The second reason is that the VI power dissipated 
in the CMOS circuit increases with S/qq (for V^c's 
> 2V-r). Each time the circuit switches, a current 
momentarily flows from Vcc to Ground through 
both output transistors. Since the threshold voltages 
of the transistors do not change with increasing 
Vcc/ the input voltage range through which the 
upper and lower transistors are conducting simul- 
taneously increases as Vqc increases. At the same 
time, the higher Vqc provides higher Vqs voltages 
which also increase the magnitude of the Jqs 
currents. Incidently, if the rise time of the input 
signal was zero, there would be no current flow 
from Vcc to Ground through the circuit. This 
current flows because the input signal has a finite 
rise time and, therefore, the input voltage spends a 
finite amount of time passing through the region 
where both transistors conduct simultaneously. 
Obviously, input rise and fall times should be kept 
to a minimum to minimize VI power dissipation. 

Let's look at the transfer characteristics, Figure 2-4, 
as they vary with Vcc- purposes of this 

discussion we will assume that both transistors in 
our basic inverter have identical but complementary 
characteristics and threshold voltages. Assume the 
threshold voltages, V-p, to be 2V. If Vcc 's less 
than the threshold voltage of 2 V, neither transistor 
can ever be turned on and the circuit cannot 
operate. If Vcc equal to the threshold voltage 
exactly then we are on the curve Figure 2-4a. 
We appear to have 100% hysteresis. However, it is 
not truly hysteresis since both output transistors 
are off and the output voltage is being held on the 
gate capacitances of succeeding circuits. If Vqc is 
somewhere between one and two threshold volt- 
ages (Figure 2-4b), then we have diminishing 
amounts of "hysteresis" as we approach Vqq equal 
to 2Vj (Figure 2-4c). At Vcc equal to two thres- 
holds we have no "hysteresis" and no current flow 
through both the upper and lower transistors dur- 
ing switching. As Vcc exceeds two thresholds the 



TL/F/6019-5 

(a) 


TL/F/6019 6 

(b) 



FIGURE 2-4. Transfer Characteristics vs Vqq. 


Considering the subject of noise in a CMOS system, 
we must discuss at least two specs: noise immunity 
and noise margin. 

National's CMOS circuits have a typical noise 
immunity of 0.45 Vcc - This means that a spurious 
input which is 0.45 Vcc o'" away from Vcc o*" 
Ground typically will not propagate through the 
system as an erroneous logic level. This does not 
mean that no signal at all will appear at the output 
of the first circuit. In fact, there will be an output 
signal as a result of the spurious input, but it will 
be reduced in amplitude. As this signal propagates 
through the system, it will be attenuated even 
more by each circuit it passes through until it 
finally disappears. Typically, it will not change any 
signal to the opposite logic level. In a typical 
flip flop, a 0.45 Vcc spurious pulse on the clock 
line would not cause the flop to change state. 


National also guarantees that its CMOS circuits 
have a IV DC noise margin over the full power 
supply range and temperature range and with any 
combination of inputs. This is simply a variation of 
the noise immunity spec only now a specific set of 
input and output voltages have been selected and 
guaranteed. Stated verbally, the spec says that for 
the output of a circuit to be within 0.1 Vcc volts 
of a proper logic level (Vcc or Ground), the input 



2-5 


AN-77 




AN-77 


can be as much as 0.1 Vcc Pi'JS IV away from 
power supply rail. Shown graphically we have; 



Vcc 

TL;F/6019-9 

FIGURE 2-5. Guaranteed CMOS DC Margin Over 
Temperature as a Function of Vqq. 
CMOS Guarantees IV. 

This is similar in nature to the standard TTL noise 
margin spec which is 0.4V. 



4.5 5.0 5.5 

Vcc 

TL/F/6019-10 

FIGURE 2-6. Guaranteed TTL DC Margin Over 

Temperature as a Function of Vqq. 
TTL Guarantees 0.4V. 


For a complete picture of Vqut vs V,n refer to 
the transfer characteristic curves in Figure 2-4. 


If we were going to tie the unused inputs to a 
logic level, inputs A & B would have to be tied to 
Vcc to enable the other inputs to function. That 
would turn on the lower A and B transistors and 
turn off the upper A and B transistors. At most, 
only two of the upper transistors could ever be 
turned on.. However, if inputs A and B were tied 
to input C, the input capacitance would triple, but 
each time C went low, the upper A, B and C 
transistors would turn on, -tripling the available 
source current. If input D was low also, all four of 
the upper transistors would be on. 



So, tying unused NAND gate inputs to Vcc 
(Ground for NOR gates) will enable them, but 
tying unused inputs to other used inputs guarantees 
an increase in source current in the case of NAND 
gates (sink current in the case of NOR gates). 
There is no increase in drive possible through the 
series transistors. By using this approach, a multiple 
input gate could be used to drive a heavy current 
load such as a lamp or a relay. 


SYSTEM CONSIDERATIONS 

This section describes how to handle many of the 
situations that arise in normal system design such 
as unused inputs, paralleling circuits for extra 
drive, data bussing, power considerations and inter- 
faces to other logic families. 


Parallel gates: depending on the type of gate, tying 
inputs together guarantees an increase in either 
source or sink current but not both. To guarantee 
an increase in both currents, a number of gates 
must be paralleled as in Figure 3-2. This insures 
that there are a number of parallel combinations 
of the series string of transistors (Figure 3-1), 
thereby increasing drive in that direction also. 


Unused inputs: simply stated, unused inputs should 
not be left open. Because of the very high imped- 
ance (~10^^r2), a floating input may drift back 
and forth between a "0" and “I” creating some 
very intriguing system problems. All unused inputs 
should be tied to Vcc, Ground or another used 
input. The choice is not completely arbitrary, 
however, since there will be an effect on the 
output drive capability of the circuit in question. 
Take, for example, a four input NAND gate being 
used as a two input gate. The internal structure is 
shown in Figure 3-1, Let inputs A & B be the 
unused inputs. 


L-d^ Li><J 


FIGURE 3-2. Paralleling Gates or Inverters Increases 
Output Drive in Both Directions. 


Data bussing: there are essentially two ways to do 
this. First, connect ordinary CMOS parts to a bus 
using transfer gates (part no. CD4016C). Second, 



2-6 




and the preferred way, is to use parts specifically 
designed with a CMOS equivalent of a TRI-STATE® 
output. 

Power supply filtering: since CMOS can operate 
over a large range of power supply voltages (3V 
to 15V), the filtering necessary is minimal. The 
minimum power supply voltage required will be 
determined by the maximum frequency of opera- 
tion of the fastest element in the system (usually 
only a very small portion of any system operates 
at maximum frequency). The filtering should be 
designed to keep the power supply voltage some- 
where between this minimum voltage and the 
maximum rated voltage the parts can tolerate. 
However, if power dissipation is to be kept to a 
minimum, the power supply voltage should be 
kept as low as possible while still meeting all speed 
requirements. 


rise time is long, power dissipation increases since 
the current path is established for the entire period 
that the input signal is passing through the region 
between the threshold voltages of the upper and 
lower transistors. Theoretically, if the rise time 
were zero, no current path would be established 
and the VI power would be zero. However, with a 
finite rise time there is always some current flow 
and this current flow increases rapidly with power 
supply voltage. 

Just a thought about rise time and power dissipa- 
tion. If a circuit is used to drive many loads, its 
output rise time will suffer. This will result in an 
increase in VI power dissipation in every device 
being driven by that circuit (but not in the drive 
circuit itself). If power consumption is critical, it 
may be necessary to improve the rise time of that 
circuit by buffering or by dividing the loads in 
order to reduce overall power consumption. 


Minimizing system power dissipation: to minimize 
power consumption in a given system, it should be 
run at the minimum speed to do the job with the 
lowest possible power supply voltage. AC and DC 
transient power consumption both increase with 
frequency and power supply voltage. The AC 
power is described as CV^f power. This is the 
power dissipated in a driver driving a capacitive 
load. Obviously, AC power consumption increases 
directly with frequency and as the square of the 
power supply. It also increases with capacitive load, 
but this is usually defined by the system and is not 
alterable. The DC power is the VI power dissipated 
during switching. In any CMOS device during 
switching, there is a momentary current path from 
the power supply to ground, (when Vqc > 2Vy) 
Figure 3-3. 




RISE TIME TO 
PERIOD RATIO 


X RISE TIME TO PERIOD RATIO 

VCC - 2Vt ^ tRISE «FAL1. 

Vcc 'total 


WHERE — = FREQUENCY 

'total 


Pvi = 1/2 (Vcc - 2Vt) Icc max ('rise + 'fall) FREQ. 

TL/F/6019-13 

FIGURE 3-3. DC Transient Power. 


The maximum amplitude of the current is a rapidly 
increasing function of the input voltage which in 
turn is a direct function of the power supply 
voltage. See Figure 2-4d. 

The actual amount of VI power di.ssipated by the 
system is determined by three things: power supply 
voltage, frequency and input signal rise time. A 
very important factor is the input rise time. If the 


So, to summarize the effects of power supply 
voltage, input voltage, input rise time and output 
load capacitance on system power dissipation, we 
can say the following: 

1. Power supply voltage: CV^f power dissipation 
increases as the square of power supply voltage. 
VI power dissipation increases approximately 
as the square of the power supply voltage. 

2. Input voltage level: VI power dissipation in- 
creases if the input voltage lies somewhere 
between Ground plus a threshold voltage and 
Vcc iTiinus a threshold voltage. The highest 
power dissipation occurs when V|n is at 1/2 
Vcc - CV^f dissipation is unaffected. • 

3. Input rise time: VI power dissipation increases 
with longer rise times since the DC current path 
through the device is established for a longer 
period. The CV^f power is unaffected by slow 
input rise times. 

4. Output load capacitance: the CV^f power dissi- 
pated in a circuit increases directly with load 
capacitance. VI power in a circuit is unaffected 
by its output load capacitance. However, in- 
creasing output load capacitance will slow 
down the output rise time of a circuit which in 
turn will affect the VI power dissipation in the 
devices it is driving. 

INTERFACES TO OTHER LOGIC TYPES 

There are two main ideas behind all of the follow- 
ing interfaces to CMOS. First, CMOS outputs 
should satisfy the current and voltage requirements 
of the other family's inputs. Second, and probably 
most important, the other family's outputs should 
swing as near as possible to the full voltage range 
of the CMOS power supplies. 

P-Channel MOS: there are a number of things to 
watch for when interfacing CMOS and P-MOS. The 
first is the power supply set. Most of the more 
popular P-MOS parts are specified with 17 to 24V 
power supplies while the maximum power supply 
voltage for CMOS is 15V. Another problem 



2-7 


AN-77 



AN-77 


is that unlike CMOS, the output swing of a push- 
pull P-MOS output is significantly less than the 
power supply voltage across it. P-MOS swings from 
very close to its more positive supply (V^^) to 
quite a few volts above its more negative supply 
(Vdd). So, even if P-MOS uses a 15V or lower 
power supply set, its output swing will not go low 
enough for a reliable interface to CMOS. There are 
a number of ways to solve this problem depending 
on the configuration of the system. We will discuss 
two solutions for systems that are built totally 
with MOS and one solution for systems that 
include bipolar logic. 


•_ 15V 


i 

Vcc 


V. 


Vcc 

1 - 

CMOS 

GND 


PMOS 

Voo 

Ip 

CMOS 

CNO 


TL/F/6019-14 


FIGURE 3-4. A One Power Supply System Built 
Entirely of CMOS and P-MOS. 


First, MOS, only. P-MOS and CMOS using the 
same power supply of less than 15V, Figure 3-4. 


outputs. The CMOS can still drive P-MOS directly 
and now the P-MOS can drive CMOS with no 
pull-down resistors. The other restrictions are that 
the total voltage across the CMOS is less than 15V 
and that the bias supply can handle the current 
requirements of all the CMOS. This approach is 
useful if the P-MOS supply must be greater than 
15V and the CMOS current requirement is low 
enough to be done easily with a small discrete 
component regulator. 

If the system has bipolar logic, it will usually 
have at least two power supplies. In this case, the 
CMOS IS run off the bipolar supply , and it inter- 
faces directly to P-MOS, Figure 3-6. 



Bun the CMOS from the bipolar supply and interface directly to P-MOS 


FIGURE 3-6. A System With CMOS, P-MOS and Bipolar 
Logic. 


In this configuration CMOS drives P-MOS directly. 
Flowever, P-MOS cannot drive CMOS directly be- 
cause of its output will not pull down close enough 
to the lower power supply rail. Rpp (R pull down) 
is added to each P-MOS output to pull it all the 
way down to the lower rail. Its value is selected 
such that it is small enough to give the desired 
RC time constant when pulling down but not so 
small that the P-MOS output cannot pull it 
virtually all the way up to the upper power supply 
rail when it needs to. This approach will work with 
push-pull as well as open drain P-MOS outputs. 

Another approach in a purely MOS system is to 
build a cheap zener supply to bias up the lower 
power supply rail of CMOS, Figure 3-5. 



Use a bias supply to reduce the voltage across the CMOS 
to match the logic swing of the P-MOS. Make sure the 
resulting voltage across the CMOS is less than 15V. 


FIGURE 3-5. A P-MOS and CMOS System Where The 
P-MOS Supply is Greater Than 15V. 


N-Channel MOS; interfacing to N-MOS is some- 
what simpler than interfacing to P-MOS although 
similar problems exist. First, N-MOS requires 
lower power supplies than P-MOS, being in the 
range of 5V to 12V. This is directly compatible 
with CMOS. Second, N-MOS logic levels range 
from slightly above the lower power supply rail to 
about 1 to 2V below the upper rail. 

At the higher power supply voltages, N-MOS and 
CMOS can be interfaced directly since the N-MOS 
high logic level will be only about 10 to 20 percent 
below the upper rail. However, at lower supply 
voltages the N-MOS output level will be down 20 
to 40 percent below the upper rail and something 
may have to be done to raise it. The simplest solu- 
tion is to add pull up resistors on the N-MOS 
outputs as shown in Figure 3-7. 



Both operate off same supply with pull up resistors optional from 
N-MOS to CMOS 

FIGURE 3-7. A System With CMOS and N-MOS Only. 


In this configuration the P-MOS supply is selected 
to satisfy the P-MOS voltage requirement. The bias 
supply voltage is selected to reduce the total 
voltage across the CMOS (and therefore its logic 
swing) to match the minimum swing of the P-MOS 


TTL, LPTTL, DTL: two questions arise when 
interfacing bipolar logic farnilies to CMOS. First, 
is the bipolar family's logic "1" output voltage high 
enough to drive CMOS directly? 


2-8 




TTL, LPTTL, and DTL can drive 74C series CMOS 
directly over the commercial temperature range 
without external pull up resistors. However, TTL 
and LPTTL cannot drive 4000 series CMOS directly 
(DTL can) since 4000 series specs do not guarantee 
that a direct interface with no pull up resistors will 
operate properly. 

DTL and LPTTL manufactured by National (NS 
LPTTL pulls up one diode drop higher than the 
LPTTL of other vendors) will also drive 74C 
directly over the entire military temperature range. 
LPTTL manufactured by other vendors and stan- 
dard TTL will drive 74C directly over most of the 
mil temperature range. However, the TTL logic 
"1" drops to a somewhat marginal level toward the 
lower end of the mil temperature range and a pull 
up resistor is recommended. 

According to the curve of DC margin vs V^c for 
CMOS in Figure 2-5, if the CMOS sees an input 
voltage greater than Vqc “ ^ -^V (V'cc 5V), the 
output is guaranteed to be less than 0.5V from 
Ground. The next CMOS element will amplify 
this 0.5V level to the proper logic levels of Vcc or 
Ground. The standard TTL logic “1" spec is a Vqut 
min. of 2.4V sourcing a current of 400 /jA. This 
is an extremely conservative spec since a TTL 
output will only approach a one level of 2.4V 
under the extreme worst case conditions of lowest 
temperature, high input voltage (0.8V), highest 
possible leakage currents (into succeeding TTL 
devices), and V^q at the lowest allowable (Vqq = 
4.5V). 


The LPTTL input current is small enough to allow 
CMOS to drive two loads directly. Normal power 
TTL input currents are ten times higher than 
those in LPTTL and consequently the CMOS out- 
put voltage will be well above the input logic "0" 
maximum of 0.8V‘. However, by carefully examin- 
ing the CMOS output specs we will find that a two 
input NOR gate can drive one TTL load, albeit 
somewhat marginally. For example, the logical 
"0" output voltage for both an MM74C00 and 
MM74C02 over temperature is specified at 0.4V 
sinking 360 /jA (about 420)uA at 25°C) with an 
input voltage of 4.0V and a Vcc of 4.75V. Both 
schematics are shown in Figure 3-9. 


Vqc 



FIGURE 3-9a. MM74C00. 


Under nominal conditions (25°C, Vj^ = 0.4V, 
nominal leakage currents into CMOS and Vcc “ 
5V) a TTL logic "1" will be more like Vcc ” 2 Vd, 
Of Vcc ~ ’1-2V. Varying only temperature, the 
output will change by two times -2mV per °C, or 
-4 mV per ‘^C. Vcc ~ 1 ■2V is more than enough 
to drive CMOS reliably without the use of a pull 
up resistor. 

If the system is such that the TTL logic "1 " output 
can drop below Vcc ~ 1-5V, use a pull up resistor 
to improve the logic "1" voltage into the CMOS. 


Vcc 

^ Rpu 

Vcc 


\ 


TTL 

► 

CMOS 

GND 


GND 


Pull up resistor, Rpu, is needed only at the lower end of the Mil 
temperature range. 

FIGURE 3-8. TTL to CMOS Interface. 

The second question is, can CMOS sink the bipolar 
input current and not exceed the maximum value 
of the bipolar logic zero input voltage? The logic 
“1" input is no problem. 


Vcc 



= A + B 


TL/F/6019 20 


FIGURE 3-9b. MM74C02. 


Both parts have the same current sinking spec but 
their structures are different. What this means is 
that either of the lower transistors in the MM74C02 
can sink the same current as the twp lower series 
transistors in the MM74C00. Both MM74C02 
transistors together can sink twice the specified 
current for a given output voltage. If we allow the 
output voltage to go to 0.8V, then a MM74C02 
can sink four times 360)LtA, or 1.44 mA which is 
nearly 1.6 mA. Actually, 1.6 mA is the maximum 


2-9 


AN-77 




ZZNV 


spec for the TTL input current and most TTL 
parts run at about 1 mA. Also, 360/zA is the 
minimum CMOS sink current spec, the parts will 
really sink somewhere between 360 and 540juA 
(between 2 and 3 LPTTL input loads). The 360iuA 
sink current is specified with an input voltage of 
4.0V. With an input voltage of 5.0V, the sink 
current will be about 560/zA over temperature, 
making it even easier to drive TTL. At room 
temperature with an input voltage of 5V, a CMOS 
output can sink about SOO/uA. A 2 input NOR 
gate, therefore, will sink about 1 .6 mA with a Vqut 
of about 0.4V if both NOR gate inputs are at 5V. 

The main point of this discussion is that a common 
2 input CMOS NOR gate such as an MM74C02- 


can be used to drive a normal TTL load in lieu of a 
special buffer. However, the designer must be 
willing 'to sacrifice some noise immunity over 
temperature to do so. 


TIMING CONSIDERATIONS IN CMOS MSIs 

There is one more thing to be said in closing. All 
the flip-flops used in CMOS designs are genuinely 
edge sensitive. This means that the J-K flip-flops 
do not "ones catch" and that some of the timing 
restrictions that applied to the control lines on 
MSI functions in TTL have been relaxed in the 
74C series. 


2-10 



CMOS Linear 
Applications 


National Semiconductor 
Application Note 88 
Gene Taajes 
July 1973 



PNP and NPN bipolar transistors have been used 
for many years in "complementary" type of 
amplifier circuits. Now, with the arrival of CMOS 
technology, complementary P-channel/N-channel 
MOS transistors are available in monolithic form. 
The MM74C04 incorporates a P-channel MOS 
transistor and an N-channel MOS transistor 
connected in complementary fashion to function 
as an inverter. — ' 


R1 



FIGURE 2. A 74CMOS Invertor Biased for Linear Mode 
Operation. 


Due to the symmetry of the P- and N-channel 
transistors, negative feedback around the comple- 
mentary pair will cause the pair to self bias itself 
to approximately 1/2 of the supply voltage. 
Figure 1 shows an idealized voltage transfer 
characteristic curve of the CMOS inverter con- 
nected with negative feedback. Under these 
conditions the inverter is biased for operation 
about the midpoint in the linear segment on* the 
steep transition of the voltage transfer character- 
istic as shown in Figure 1. 


The power supply current is constant during 
dynamic operation since the inverter is biased for 
Class A operation. When the input signal swings 
near the supply, the output signal will become 
distorted because the P-N channel devices are 
driven into the non-linear regions of their transfer 
characteristics. If the input signal approaches the 
supply voltages, the P- or N-channel transistors 
become saturated and supply current is reduced to 
essentially zero and the device behaves like the 
classical digital inverter. 



0 7.5 15 

INPUT VOITAGE - V,n TUF/6020-1 


■ 

1 

p 

■ 

m 

y 

■ 

■ 


■ 

m 


a 


n 

n 

m 



■ 

■ 

m 


H 

M 

II 

IBI 

■ 



m 

B 

■ 

B 



2 5 5 0 7 5 10 12 5 15 

INPUT VOLTAGE -V.;u TL/F/6020-3 


FIGURE 3. Voltage Transfer Characteristics for an 
Inverter Connected as a Linear Amplifier. 


FIGURE 1. Idealized Voltage Transfer Characteristics of 
an MM74C04 Inverter. 


Under AC conditions, a positive going input will 
cause the output to swing negative and a negative 
going input will have an inverse effect. Figure 2 
shows 1/6 of a MM74C04 inverter package 
connected as an AC amplifier. 


Figure 3 shows- typical voltage characteristics of 
each inverter at several values of the Vcc- The 
shape of these transfer curves are relatively 
constant with temperature. Temperature affects 
for the self biased inverter with supply voltage is 
shown in Figure 4. When the amplifier is operating 
at 3 volts, the supply current changes drastically as 
a function of supply voltage because the MOS 
transistors are operating in the proximity of their 
gate-source threshold voltages. 



2-11 


88NV 



89NV 



TEMPERATURE TUF/6020-4 

FIGURE 4. Mormalized Amplifier Supply Current Versus 
Ambient Temperature Characteristics. 

Figure 5 shows typical curves of voltage gain as a 
function of operating frequency for various supply 
voltages. 

Output voltages can swing within millivolts of the 
supplies with either a single or dual supply. 



FIGURE 5. Typical Voltage Gain Versus Frequency 
Characteristics for Amplifier Shown in Figure 2. 

APPLICATIONS 

Cascading Amplifiers for Higher Gain. 

By cascading the basic amplifier block shown in 
Figure 2 a high gain amplifier can be achieved. The 
gain will be multiplied by the number of stages 
used. If more than one inverter is used inside the 
feedback loop (as in Figure 6) a higher open loop 
gain is achieved which results in more accurate 
closed loop gains. 


10M.f2 

■V/V- 



TL/F/6020 6 


FIGURE 6. Three CMOS Inverters Used as an XIO AC 
Amplifier. 


Post Amplifier for Op Amps. 

A standard operational amplifier used with a 
CMOS inverter for a Post Amplifier has several 
advantages. The operational amplifier essentially 
sees no load condition since the input impedance 
to the inverter is very high. Secondly, the CMOS 
inverters will swing to within millivolts of either 
supply. This gives the designer the advantage of 
operating the operational amplifier under no load 
conditions yet having the full supply swing 
capability on the output. Shown in Figure 7 is the 
LM4250 micropower Op Amp used with a 74C04 
inverter for increased output capability while 
maintaining the low power advantage of both 
devices. 


+ t.5V +1.5 V 



TLyF/6020-7 

FIGURE 7. MM74C04 Inverter Used as a Post Amplifier 
for a Battery Operated Op Amp. 

The MM74C04 can also be used with single supply 
amplifier such as the LM324. With the circuit 
shown in Figure 8, the open loop gain is approxi- 
mately 160 dB. The LM324 has 4 amplifiers in a 
package and the MM74C04 has 6 amplifiers per 
package. 


+ 12 V 



FIGURE 8. Single Supply Amplifier Using a CMOS 
Cascade Post Amplifier with the LM324. 

CMOS inverters can be paralleled for increased 
power to drive higher current loads. Loads of 
5.0 mA per inverter can be expected under AC 
conditions. 

Other 74C devices can be used to provide greater 
complementary current outputs. The MM74C00 
NAND Gate will provide approximately 10 mA 


2-12 




from the V^c supply while the IVIIVI74C02 will 
supply approximately 10 mA from the negative 
supply. Shown in Figure 9 is an operational 
amplifier using a CMOS power post amplifier to 
provide greater than 40 mA complementary 
currents. 




TL/F/6020-10 

Phase Shift 

Oscillator Using MM74C04 



W6.0Vpp 

TL/F/6020-9 

FIGURE 9. MM74C00 and MM74C02 Used as a Post 
Amplifier to Provide Increased Current Drive. 


Other Applications. 

Shown in Figure 10 is a variety of applications 
utilizing CMOS devices. Shown is a linear phase 
shift oscillator and an integrator which use the 
CMOS devices in the linear mode as well as a few 
circuit ideas for clocks and one" shots. 


c 



Integrator Using 
Any Inverting CMOS Gate 



Square Wave Oscillator 


c 


+v 


cc 


INPUT 


One Shot 



1.4 RC 

TL/Fy6020-13 


Conclusion 

} 

Careful study of CMOS characteristics show that 
CMOS devices used in a system design can be used 
for linear building blocks as well as digital blocks. 

Utilization of these new devices will decrease 
package count and reduce supply requirements. 
The circuit designer now can do both digital and 
linear designs with the same type of device. 



TL/F/6020-14 

Staircase Generator 


FIGURE 10. Variety of Circuit Ideas Using CMOS 
Devices. 


2-13 


AN-88 




AN-90 


54C/74C Family 
Characteristics 


National Semiconductor 
Application Note 90 
Thomas P. Redfern 
August 1973 



INTRODUCTION 

The purpose of this 54C/74C Family Character- 
istics application note is to set down, in one place, 
all those characteristics which are common to the 
devices in the MM54C/MM74C logic family. The 
characteristics which can be considered to apply 
are: 

1. Output voltage-current characteristics 

2. Noise characteristics 

3. Power consumption * 

4. Propagation delay (speed) 

5. Temperature characteristics 

With a good understanding of the above charac- 
teristics the designer will have the necessary tools 
to optimize his system. An attempt will be made 
to present the information in as simple a manner 
as possible to facilitate its use. This coupled with 


the fact that 54C/74C has the same function and 
pin-out as standard series 54L/74L will make the 
application of CMOS to digital systems very 
straightforward. 


OUTPUT CHARACTERISTICS 

Figure 1 and Figure 2 show typical output drain 
characteristics for the basic inverter used in the 
54C/74C family. For more detailed information on 
the operation of the basic inverter the reader is 
directed to application note AN-77, "CMOS, The 
Ideal Logic Family." Although more complex 
gates, and MSI devices, may be composed of 
combinations of parallel and series transistors the 
considerations that govern the output character- 
istics of the basic inverter apply to these more 
complex structures as well. 


Vos (V) 



(A) Typical Output Sink Characteristic 


(B| Typical Output Source Characteristic 


(N-Channel) 


(P-Channel) 


FIGURE 1 



(A) Typical Output Sink Characteristic 
(N-Channel) 


(B) Typical Output Source Characteristic 
(P-Channel) 


FIGURE 2 


2-14 



The 54C/74C family is designed so that the output 
characteristics of all devices are matched as closely 
as possible. To ensure uniformity all devices are 
tested at four output conditions (see Figures 1 
and 2). These points are: 


Vcc = 5.0V 

V|N = 5.0V 

Iqs > 1.75 mA 
Vds > 5.0V 

V|N = OV 

1 IqsI 1 -75 mA 
IVdsI >5.0V 

Vcc =•• 10V 

V|N = 10V 

Ids ^ 8,0 mA 

Vds > 10V 

V,N =0V 

HdsI >8.0 mA 
IVosI .>10V 


Note that each device data sheet guarantees these 
points in the table of electrical characteristics. 


The output characteristics can be used to determine 
the output voltage for any load condition. Figures 
1 and 2 show load lines for resistive loads to Vcc 
for sink currents and to GND for source currents. 
The intersections of this load line with the drain 
characteristic in question gives the output voltage. 
For example at Vcc = 5.0V, Vqut = 1-5V (typ) 
with a load of 500^2 to ground. 


Ail 54C/74C devices are guaranteed to have a 
noise margin of 1.0V or greater over all operating 
conditions (see Figure 4). 



Vcc TL;F/6021-6 

FIGURE 4. Guaranteed Noise Margin Over Temperature 
vs Vcc 


Noise immunity is an important device character- 
istic. However, noise margin is of more use to the 
designer because it very simply defines the amount 
of noise a system can tolerate under any circum- 
stances and still maintain the integrity of logic 
levels. 


These figures also show the guaranteed points for 
driving two 54L/74L standard loads. As can be 
seen there is typically ample margin at Vcc 5.0V. 

In the case where the 54C/74C device is driving 
another CMOS device the load line is coincident 
with the Ids = 0 axis and the output will then 
typically switch to either Vcc or ground. 

NOISE CHARACTERISTICS 
Definition of Terms 

Noise Immunity: The noise immunity of a logic 
element is that voltage which applied to the input 
will cause the output to change its output state. 


Any noise specification to be complete must 
define how measurements are to be made. Figure 5 
indicates two extreme cases; driving all inputs 
simultaneously and driving one input at a time. 
Both conditions must be included because each 
represents one worst case extreme. 

( 


Vcc 



Noise Margin: The noise margin of a logic element 
is the difference between the guaranteed logical 
"1" ("0") level output voltage and the guaranteed 
logical "1" ("0") level input voltage. 

The transfer characteristic of Figure 3 shows 
typical noise immunity and guaranteed noise 
margin for a 54C/74C device operating at Vcc = 
10V. The typical noise immunity does not change 
with voltage and is 45% of Vcc- 



FIGURE 3. Typical Transfer Characteristic 


Vcc 



Vn = ALLOWABLE NOISE VOLTAGE = 1.0V 

(B) TL/F/6021-8 

FIGURE 5. Noise Margin Test Circuits 

To guarantee a noise margin of 1.0V, all 54C/74C 
devices are tested under both conditions. It is 
important to note that this guarantees that every 
node within a system can have 1.0V of noise, in 
logic “1" or logic "0" state, without malfunction- 
ing. This could not be guaranteed without testing 
for both conditions in Figure 5. 


2-15 


AN-90 




AN-90 


POWER CONSUMPTION 

There are four sources of power consumption in 
CMOS devices: (1) leakage current (2) transient 
power due to load capacitance (3) transient power 
due to Internal capacitance and (4) transient power 
due to current spiking during switching. 

The first, leakage current, is the easiest to calculate 
and is simply the leakage current times Vcc- The 
data sheet for each specific device specifies this 
leakage current. 

The second, transient power due to load capaci- 
tance, can be derived from the fact that the energy 
stored on a capacitor is 1/2 CV^. Therefore every 
time the load capacitance is charged or discharged 
this amount of energy must be provided by the 
CMOS device. The energy per cycle is then 
2 [(1/2) CVcc^] = CVcc^. Energy per unit time, 
or power, is then f, where C is the load 

capacitance and f is the frequency. 

The third, transient power due to internal capaci- 
tance takes exactly the same form as the load 
capacitance. Every device has some internal nodal 
capacitance which must be charged and discharged. 
This then represents another- power term which 
must be considered. 

The fourth, transient power due to switching 
current, is caused by the fact that whenever a 
CMOS device goes through a transition, with 
Vcc ^ 2 Vy, there is a time when both N-channel 
and P-channel devices are both conducting. An 
expression for this current is derived in application 
note AN-77. The expression is: 

1 

Pvi (Vcc ” 2 Vj) Ice MAX (l^RISE + ^FALl) ^ 

where; 

V-j- == threshold voltage 

lcc(MAX) = non-capacitive current 

during switching 

f = frequency 

Note that this expression, like the capacitive power 
term is directly proportional to frequency. If the 
Pvi term is combined with the term arising from 
the internal capacitance; a capacitance Cpp may 
be defined which closely approximates the no load 
power consumption for a CMOS device when used 
in the following expression: 

Power (no load) = Cp^ ^ 

The total power consumption is then simplified 
to: 

T otal Power = (Cpo + Cl) Vqc^ f ( leak Vcc ) 


The procedure for obtaining Cpo is to measure 
the no load power at Vcc = 10V vs frequency and 
calculate the value of Cpo which corresponds to 
the measured power consumption. This value of 
CpD is given on each 54C/74C data sheet and 
with equation (1) the computation of power 
consumption is straightforward. 

To simplify the task even further Figure 6 gives a 
graph of normalized power vs frequency for dif- 
ferent power supply voltages. To obtain actual 
power, consumption find the normalized. power for 
a particular Vcc frequency^ then multiply 
hy CpQ + Cl- 



FIGURE 6. Normalized Typical Power Consumption 
vs Frequency 


As an example let's find the total power consump- 
tion for an MM74C00 operating at f = 100 kHz, 
Vcc = 10V and Cl = 50 pF. From the curve, 
normalized power per gate equals lO^uW/pF. From 
the data sheet Cpo = 12 pF; therefore, actual 
power per gate is: 

power lOpW 0.62 mW 

= X (12 pF -r 50 pF) = 

gate pF gate 

no. of gates power 

total power = X + Ileakage ^ ^cc 

package gate 

= 4 X 0.62 mW -r O.OlpA X 10V ^ 2.48 mW 


Up to this point the discussion of power con- 
sumption has been limited to simple gate functions. 
.Power consumption for an MSI function is more 
complex but the same technique just derived 
applies. To demonstrate the technique let's com- 
pute the total power consumption of a MM74C161 , 
four bit binary counter, at Vqc " 10V, f = 1 MHz 
and Cl = 50 pF on each output. 

The no load power is still given by P (no load) = 
CpD Vec^ T This demonstrates the usefulness 
of the concept of the internal capacitance, Cpp. 
Even through the circuit is very complex and has 
many nodes charging and discharging at various 
rates, all of the effects can be easily lumped into 
one easy to use term, Cpp. 


2-16 




Calculation of transient power due to load capaci- 
tance is a little more complex since each output 
is switched at one half the rate of the previous 
output: Taking this into account the complete 
expression for power consumption is: 


f f 

PjoTAL = CpD Vcc^ f + Cl Vcc^“ Cl ~ 


no load 

output 2nd stage 

power 

power of 


1st stage 

f 

f 

+ Cl Vcc^- 

-f- 2 Cl Vcc^ — + 1 L Vcc 

8 

16. 

3rd stage 

4th stage leakage ' 


& carry term 


output 

This reduces to: 




Vcc -- POWER SUPPLY VOLTAGE (V) tl;F/602M0 

FIGURE 7. Typical Propagation Delay per pF of Load 
Capacitance vs Power Supply 

the propagation delay for zero load capacitance is 
not zero and depends on the internal structure of 
each device, an offset term must be added that is 
unique to a particular device type. Since each 
data sheet gives propagation delay for 50 pF the 
actual delay for different loads can be computed 
with the aid of the following equation: 


PjOTAL “ (CpD + Cl) Vcc^ ^ + II Vcc 


From the data sheet Cpp = 90 pF and II = O.OBjuA. 
Using Figure 6 total power is then: 


IOOmW 

Ptotal = (90 pF + 50 pF) X + 0.05 X lO"® 

pF 

X 10V = 14 mW 


This demonstrates that with more complex devices 
the concept of Cpp greatly simplifies the calcula- 
tion of total power consumption. It becomes an 
easy task to compute power for different voltages 
and frequencies by use of Figure 6 and the 
equations above. 

PROPAGATION DELAY 

Propagation delay for all 54C/74C devices is 
guaranteed with a load of 50 pF and input rise 
and fall times of 20 ns. A 50 pF load was chosen, 
instead of 15 pF as in the 4000 series, because it 
is representative of loads commonly seen in CMOS 
systems. A good rule of thumb, in designing with 
CMOS, is to assume 10 pF of interwiring capaci- 
tance. Operating at the specified propagation 
delay would allow 5 pF fanout for the 4000 
series while 54C/74C has' a fanout of 40 pF. A 
fanout of 5 pF (one gate input) is all but useless, 
and specified propagation delay would most prob- 
ably not be realized in an actual system. 

Operating at loads other than 50 pF poses a 
problem since propagation is a function of load 
capacitance. To simplify the problem Figure 7 
has been generated and gives the slope of the 
propagation delay vs load capacitance line (Atp^/ 
pF) as a function of power supply voltage. Because 


tpd 


= (C- 50) pF X 


pF 


Cl - 50 pF 


where: 


C = Actual load capacitance 


l^pd 


Cl = 50 pF 


propagation delay with 50 pF 
load, (specified on each de- 
vice data sheet) 


= Value obtained from Figure 7. 

pF 


As an example let's compute the propagation 
delay for an MM74C00 driving 15 pF load and 
operating with a Vcc 5.0V. The equation 
gives: 



15pF 


ns 

= (15-50) pF X0.57 — -^50ns 
pF 


= -20 ns + 50 ns = 30 ns 


The same formula and curves may be applied to 
more complex devices. For example the propaga- 
tion delay from data to output for an MM74C157 
operating at Vqc - 10V and Cl = 100 pF is: 

tod =(100- 50) 0.29 ns -1- 70 ns 

iCL = 100pF 


= 14.5 -F 70 85 ns 


2-17 


AN-90 




AN-90 


It is significant to note that this equation and 
Figure 7 apply to all 54C/74C devices. This is true 
because of the close match in drive characteristics 
of every device including MSI functions, i.e., the 
slope of the propagation delay vs load capacitance 
line at a given voltage is typically equal for all 
devices. The only exception is high fan-out buffers 
which have a smaller Atp^/pF. 

Another point to consider in the design of a 
CMOS system is the affect of power supply 
voltage on propagation delay. Figure 8 shows 
propagation delay as a function of Vcc and 
propagation delay times power consumption vs 
Vcc "for an MM74C00 operating with 50 pF load 
at f = 100 kHz. 

f 



Vrc (V) f TUF/6021-11 

FIGURE 8. Speed Power Product and Propagation Delay 
vs Vcc 

Above Vqc = 5.0V note the speed power product 
curve approaches a straight line. However the 
tpd curve starts to "flatten out." Going from 


Vcc ~ 5.0V to Vqc - 10V gives a 40% decrease 
in propagation delay and going from Vqc -10V 
to Vqc - 15V only decreases propagation delay 
by 25%. Clearly for Vqc > 10V a , small increase 
in speed is gained by a disproportionate increase 
in power. Conversely, for small decreases in power 
below Vcc = 5.0V large increases in propagation 
delay result. 

Obviously it is optimum to use the lowest voltage 
consistent with system speed requirements. How- 
ever in general it can be seen from Figure 8 that 
the best speed power performance will be obtained 
in the Vcc = 5.0V to Vcc = TOV range. 

TEMPERATURE CHARACTERISTICS . 

FiguresO and lOgive temperature variations in drain 
characteristics for the N-channel and P-channel 
devices operating at Vcc = 5.0V and Vcc ~ 
respectively. As can be seen from these curves the 
output sink and source current decreases as tem- 
perature increases. The affect is almost linear and 
can be closely approximated by a temperature 
coefficient of -0.3% per degree centigrade. 

Since the tp^ can be entirely attributed to rise 
and fall time, the temperature dependence of 
tpd is a function of the rate at which the output 
load capacitance can be charged and discharged. 
This in turn is a function of the sink/source 
current which was shown above to vary as -0.3% 
per degree centigrade. Consequently we can say 
that tpd varies as -0.3% per degree centigrade. 
Actual measurements of tp^ with temperature 
verifies this number. 




VouTdl (V) tl;f/602M3 


(A) Typical Output Drain Characteristic 
(N-Channel) 


FIGURE 9 


(B) Typical Output Drain Characteristic 
{P-Channel) 



VouT(O) (V) TUF/6021-14 

(A) Typical Output Drain Characteristic 
(N-Channel) 


FIGURE 10 



(B) Typical Output Drain Characteristic 
(P-Channel) 


2-18 





0 5 0 10 15 

ViN (V) TUF/602M6 

FIGURE 11. Typical Gate Transfer Characteristics 

The drain characteristics of Figure 9 and 10 show 
considerable variation with temperature. Examina- 
tion of the transfer characteristics of Figure 11 


indicates that they are almost independent of 
temperature. The transfer characteristic is not 
dependent on temperature because although both 
the N-channel and P-channel device characteristics 
change with temperature these changes track each 
other closely. The proof of this tracking is the 
temperature independence of the transfer charac- 
teristics. Noise margin and maximum/minimum 
logic levels will then not be dependent on 
temperature. 

As discussed previously power consumption is a 
function of CpQ, C|_, Vqq, f and I leakage* All 
of these terms are essentially constant with tem- 
perature except I leakage* However, the leakage 
current specified on each 54C/74C device applies 
across the entire temperature range and therefore 
represents a worst case limit. 



2-19 


AN-90 




AN-118 


CMOS Oscillators 


National Semiconductor 
Application Note 118 
Mike Watts 
October 1974 



INTRODUCTION 

This note describes several square wave oscillators that 
can be built using CMOS logic elements. These circuits 
offer the following advantages: 

■ Guaranteed startability 

■ Relatively good stability with respect to power supply 
variations 

■ ' Operation over a wide supply voltage range (3V to 1 5V) 

■ Operation over a wide frequency range from less than 
1 Hz to about 1 5 MHz 

■ Low power consumption (see AN-90) 

■ Easy interface to other logic 'families and elements 
including TTL 

Several RC oscillators and two crystal controlled oscil- 
lators are described. The stability of the RC oscillator 
will be sufficient for the bulk of applications; however, 
some applications will probably require the stability of 
a crystal. Some applications that require a lot of stability 
are; 

1. Timekeeping over a long interval. A good deal of 
stability is required to duplicate the performance of 
an ordinary wrist watch (about 12 ppm). This is, of 
course, obtainable with a crystal. However, if the 
time interval is short and/or the resolution of the 
timekeeping device is relatively large, an RC oscillator 
may be adequate. For example; if a stopwatch is built 
with a resolution of tenths of seconds and the longest 
interval of interest is two minutes, then an accuracy 
of 1 part in 1200 (2 minutes x 60 seconds/minute x 
10 tenth/second) may be acceptable since any error 
is less than the resolution of the device. 

2. When logic elements are operated near their specified 
limits. It may be necessary to maintain clock frequency 
accuracy within very tight limits in order to avoid 
exceeding the limits of the logic family being used, 
or in which the timing relationships of clock signals 

• in dynamic MOS memory or shift register systems 
must be preserved. 

3. Baud rate generators for communications equipment. 


4. Any system that must interface with other tightly 
specified systems. Particularly those that use a "hand- 
shake” technique in which Request dr Acknowledge 
pulses must be of specific widths. 

LOGICAL OSCILLATORS 


Before describing any specific circuits, a few words about 
logical oscillators may clear up some recurring confusion. 


Any odd number of inverting logic gates will oscillate if 
they are tied together in a ring as shown in Figure 1. 
Many beginning logic designers have discovered this (to 
their chagrin) by inadvertently providing such a path in 
their designs. However, some people are confused by the 
circuit in Figure 1 because they are accustomed to 
seeing sinewave oscillators implemented with positive 
feedback, or amplifiers with non-inverting gain. Since 
the concept of phase shift becomes a little strained when 
the inverters remain In their linear region for such a short 
period, it is far more straightforward to analyze the 
circuit from the standpoint of ideal switches with finite 
propagation delays rather than as amplifiers with 180° 
phase shift. It then becomes obvious that a "1" chases 
itself around the ring and the network oscillates. 




ANY EVEN NUMBER OF 
ADDITIONAL GATES 


FIGURE 1. Odd Number of Inverters will Always Oscillate 


The frequency of oscillation will be determined by the 
total propagation delay through the ring and is given by 
the following equation. 


1 

f = 

2nTp 

Where; 


f = frequency of oscillation 
Tp = Propagation delay per gate 
n = number of gates 


2-20 




This is not a practical oscillator, of course, but it does 
illustrate the maximum frequency at which such an 
oscillator will run. All that must be done to make this a 
useful oscillator is to slow It down to the desired 
frequency. Methods of doing this are described later. 

To determine the frequency of oscillation, it is necessary 
to examine the propagation delay of the inverters. 
CMOS propagation delay depends on supply voltage and 
load capacitance. Several curves for propagation delay 
for National's 74C line of CMOS gates are reproduced 
in Figure 2. From these, the natural frequency of 
oscillation of an odd number of gates can be determined. 

An example may be instructive. 

Assume the supply voltage is 10V. Since only one input 
is driven by each inverter, the load capacitance on each 
inverter is at most about 8 pF. Examine the curve in 
Figure 2c that is drawn for Vqc == 10V and extrapolate 
it down to 8 pF. We see that the curve predicts a 
propagation delay of about 17 ns. We can then calculate 
the frequency of oscillation for three inverters using the 
expression mentioned above. Thus: 


f 


1 

2x3x 17x 10"^ 


9.8 MHz 


Lab work indicates this is low and that something closer 
to 16 MHz can be expected. This reflects the conserva- 
tive nature of the curves in Figure 2. 

Since this frequency is directly controlled by propaga- 
tion delays, it will vary a great deal with temperature, 
supply voltage, and any external loading, as indicated 


by the graphs in Figure 2. In order to build a usefully 
stable oscillator it is necessary to add passive elements 
that determine oscillation frequency and minimize the 
effect of CMOS characteristics. 

STABLE RC OSCILLATOR 


Figure 3 Illustrates a useful oscillator made with three 
Inverters. Actually, any inverting CMOS gate or combina- 
tion of gates could be used. This means left over portions 


MIV174C04 MM74C04 IVIIVI74C04 

R2 I R1 

... 'VVv ' 9 *vw — 


'/out 


TL/F/6022-5 


FIGURE 3. Three Gate Oscilaltor 


of gate packages can be often used. The duty cycle will 
be close to 50% and will oscillate at a frequency that 
is given by the following expression. 

1 

/ 0.405 R2 \ 

2 R1 C -f- 0.693 I 

\r1 + R2 / 

Another form of this expression is: 


1 

f ^ 

2C (0.405 Req + 0.693 R1) 


Where: 


R1 R2 
R1 + R2 


Propagation Delay vs 
Ambient Temperature 
MM54C00/MM74C00, 
MM54C02/MM74C02, 
MM54C04/MM74C04 


Propagation Delay vs 
Ambient Temperature 
MM54C00/MM74C00, 
MM54C02, MM74C02, 
MM54C04/MM74C04 


Propagation Delay Time vs 
Load Capacitance 
MM54COO/MM74COO, 
MM54C02, MM74C02, 
MM54C04/MM74C04 



AMBIENT TEMPERATURE ( C) 


AMBIENT TEMPERATURE ( C) 


CL - LOAD CAPACITANCE (pF) 


TL/F/6022-2 


TL/F/6022-3 


TL/F/6022-4 


(a) 


(b) 


(c) 


FIGURE 2. Propagation Delay for 74C Gates 


2-21 


AN-118 



AN-118 


The following 

three special cases may be useful. 


0.559 

If R1 = R2= R 

f ~ 


RC 


0.455 

If R2»> R1 

f ~ 


RC 


0.722 

If R2«< R1 

fs 


RC 


Figure 5b, which obviously will not oscillate. This 
illustrates that there is some value of Cl that will not 
force the network to oscillate. The real difference 
between this two gate oscillator and the three gate 
oscillator is that the former must be forced to oscillate 
by the capacitor while the three gate network will 
always oscillate willingly and is simply slowed down by 
the capacitor. The three gate network will always 
oscillate, regardless of the value of Cl but the two gate 
oscillator will not oscillate when C1 is small. 


Figure 4 illustrates the approximate output waveforrh 
and the voltage V., at the charging node. 



FIGURE 4. Waveforms for Oscillator in Figure 3 


Note that the voltage V 2 will be clamped by input 
diodes when V-i is greater than Vcc of more negative 
than ground. During this portion of the cycle current 
will flow through R2. At all other times the only current 
through R2 is a very minimal leakage term. Note also 
that as soon as passes through threshold (about 50% 
of supply) and the input to the last inverter begins to 
change, will also change in a direction that reinforces 
the switching action; i.e., providing positive feedback. 
This further enhances the stability and predictability of 
the network. 

This oscillator is fairly insensitive to power supply 
variations due largely to the threshold tracking close to 
50% of the supply voltage. Just how stable it is will be 
determined by the frequency of oscillation; the ’lower 
the frequency the more stability and vice versa. This is 
because propagation delay and the effect of threshold 
shifts comprise a smaller portion of the overall period. 
Stability will also be enhanced if R1 is made large 
enough to swamp any variations in the CMOS output 
resistance. 

TWO GATE OSCILLATOR WILL NOT 
NECESSARILY OSCILLATE 

A popular oscillator is shown in Figure 5a. The only 
undesirable feature of this oscillator is that it may not 
oscillate. This is readily demonstrated by letting the value 
of C go tp zero. The network then degenerates into 


MIVI74C04 IVIM74C04 



(a) TL/F/6022-7 


MIVI74C04 MM74C04 



-i>^ 


R1 < R2 


(b) TL/F/6022-8 


FIGURE 5. Less Than Perfect Oscillator 


The only advantage the two gate oscillator has over the 
three gate oscillator is that It uses one less inverter. 
This may or may not be a real concern, depending on the 
gate count in each user's specific application. However, 
the . next section offers a real minimum parts count 
oscillator. 

A SINGLE SCHMITT TRIGGER MAKES 
AN OSCILLATOR 

Figure 6 illustrates an oscillator made from a single 
Schmitt trigger. Since the MM74C14 is a hex Schmitt 
trigger, this oscillator consumes only one sixth of a 
package. The remaining 5 gates can be used either as 
ordiriary inverters .like the MM74C04 or their Schmitt 
trigger characteristics can be used to advantage in the 
normal manner. Assuming these five inverters can be used 
elsewhere in the system. Figure 6 must represent the 
ultimate in low gate count 'oscillators. 


R 



T 

“ TL/F/6022-9 


FIGURE 6. Schmitt Trigger Oscillator 


Voltage V.-j is depicted in Figure 7 and changes between 
the two thresholds of the. Schmitt trigger. If these 
thresholds were constant percentages of Vcc 
supply voltage range, the oscillator would be insensitive 
to variations in Vcc- However, this is not the case. The 
thresholds of the Schmitt trigger vary enough to make 
the oscillator exhibit a good deal of sensitivity to Vcc- 

Applications that do not require extreme stability or 
that have access to well regulated supplies should not 
be bothered by this sensitivity to Vcc- Variations in 
threshold can be expected to run as high as four or five 
percent when Vcc varies from 5V to 15V. 


2-22 




^mn 



TL/F/6022-10 

FIGURE 7. Waveforms for Schmitt Trigger Oscillator 
in Figure 6 


A CMOS Crystal Oscillator 

Figure 8 illustrates a crystal oscillator that uses only 
one CMOS inverter as the active element. Any odd 
number of inverters may be used, but the total propaga- 
tion delay through the ring limits the highest frequency 


that can be obtained. Obviously, the fewer inverters 
that are used, the higher the maximum possible frequency. 


CONCLUSIONS 

A large number of oscillator applications can be imple- 
mented with the extremely simple, reliable, inexpensive 
and versatile CMOS oscillators described in this note. 
These oscillators consume very little power compared 
to most other approaches. Each of the oscillators 
requires less than one full package of CMOS inverters of 
the MM74C04 variety. Frequently such an oscillator can 
be built using leftover gates of the MM74C00, MM74C02, 
MM74C10 variety. Stability superior to that easily 
attainable with TTL oscillators is readily attained, 
particularly at lower frequencies. These oscillators are 
so versatile, easy to build, and inexpensive that they 
should find their way into many diverse designs. 



FIGURES. Crystal Oscillator 



2-23 


AN-118 




AN-138 


Using the CMOS Dual 
Monostable Multivibrator 


National Semiconductor 
Application Note 138 
Thomas P. Redfern 
May 1975 



INTRODUCTION 

The MM54C221/MM74C221 is a dual CMOS monostable 
multivibrator. Each one-shot has three inputs (A, B and 
CLR) and two outputs (Q and Q). The output pulse 
width is set by an external RC network. 

The A and B inputs trigger an output pulse on a negative 
or positive input transition respectively. The CLR input 
when low resets the one-shot. Once triggered the A and B 
inputs have no, further control on the output. 

THEORY OF OPERATION 

Figure 1 shows that in its stable state, the. one-shot 
clamps Cext ground by turning N1 ON and holds 
the positive comparator input at \/qq by turning N2 
OFF. The prefix N is used to denote N-channel transistors. 

The signal, G, gating N2 OFF also gates the comparator 
OFF thereby keeping the internal power dissipation to 
an absolute minimum. The only power dissipation when 
in the stable state is that generated by the current 
through Rext- The bulk of this dissipation is in Rext 
since the voltage drop across N1 is very small for normal 
ranges of Rext- 

To trigger the one-shot the CLR input must be high. 


The gating, G, on the comparator is designed such that 
the comparator output is high when the one-shot is in 
its stable state. With the CLR input high the clear input 
to FF is disabled allowing the flip-flop to respond to the 
A or B input. A negative transition on A or a P 9 sitive 
transition on B sets Q to a high state. This in turn gates 
N1 OFF, and N2 and the comparator ON. 

Gating N2 ON establishes a reference of 0.63 V^c 
the comparator's positive input. Since the voltage on 
Cext can not change instantaneously VI = OV at this 
time. The comparator then will maintain its one level on 
the output. Gating N1 OFF allows Cext "tc start charging 
through Rext toward M qq exponentially. 

Assuming a perfect comparator (zero offset and infinite 
gain) when the voltage on Cext. equals 0.63 Vqq 
the comparator output will go from a high state to a 
low state resetting Q to a low state. Figure 2 is a timing 
diagram summarizing this sequence of events. 

This diagram is idealized by assuming zero rise and fall 
times and zero propagation delay but it shows the basic 
operation of the one-shot. Also shown is the effect of 
taking the CLR input low. Whenever CLR goes low FF 




Vec 



2-24 




H 


CLR 



B 


H 

L 




Q 


COMPARATOR 

OUTPUT 



FIGURE 2. One-Shot Timing Diagram 


is reset independent of all othqr inputs. Figure 2 also 
shows that once triggered, the output is independent of 
any transitions on B (or A) until the cycle is complete. 


TL/F/6023-2 

because the leakage and ON impedance of transistor N1 
have a minimal effect on accuracy with this value of 
resistance. 


The output pulse width is determined by the following 
equation: 

VI = Vcc (1 ext Cext) =0.63 Vcc (D 

Solving for t gives: 

' Rext Cext (1/0.37) = Rext Cext (2) 


Two values of C^xt were chosen, 1000 pF and O.I^jF. 
These values give pulse widths of lO/us and 1000/js with 
RgXT ~ 

Figures 3 and 4 show the resulting distributions of pulse 
widths at 25°C for various power supply voltages. 
Because propagation delays, at the same power supply 
voltage, are the same independent of pulse width, the 
shorter the pulse width the more the accuracy is 


A word of caution should be given in regards to the 
ground connection of the external capacitor (Cext)- 
It should always be connected as shown in Figure 1 to 
pin 14 or 6 and never to pin 8. This is important 
because of the parasitic resistor R*. Because of the large 
discharge current through R"^, if the capacitor is con- 
nected to pin 8, a four layer diode action can result 
causing the circuit to latch and possibly damage itself. 

ACCURACY 

There are many factors which influence the accuiacy of 
the one-shot. The most important are: 



'5 2 0 2 5 


0% Point pulse width: 

AtVcc = 5V, Tw = 10 6.,s 
AtVcc = 10V, TwMO.s 
AtVcc = 15V, Tw=9.8s 

Perceiitaye of units withm 4“i. 
AtVcc = 5V, 90% of units 

AtVcc = 10V, 95% of units 

AtVcc = 15V, 98% of units 


OUTPUT PULSE WIDTH (Tw, %) 


TL/F/6023-3 


FIGURE 3. Typical Pulse Width Distribution for lOjus Pulse. 


a. Comparator input offset 

b. Comparator gain 

c. Comparator time delay 

d. Voltage divider R1, R2 

e. Delays in logic elements 

f. ON impedance of N1 and N2 

g. Leakage of N1 

h. Leakage of C^xt 

i. Magnitude of Rext ^ext ■ 

The characteristics of C^xt Rext ^re, of course, 
not determined by the characteristics of the one-shot. 
In order to establish the accuracy of the one-shot, devices 
were tested using an external resistance of lOkLZand 
various capacitors. A resistance of 10 kI2 was chosen 



5 2 0 2 5 


OUTPUT PULSE WIDTH (T^. %) 


0% pulse width. 

AtVcc = 5V, Tw -- 1020 /5 
AtVcc = 10V, Tw = ld00;.s 
AtVcc--15V, Tw= 982,is 

Perceiitaye of uinib within 4%. 
AtVcc = 5V, 95% of units 

AtVcc = 10V, 97% of units 

AtVcc = 15V, 98% of units 


TL/F/6023-4 


FIGURE 4. Typical Pulse Width Distribution for 1000/is Pulse. 



2-25 


AN-138 




AN-138 


affected by propagation delay. Figures 3 and 4 clearly 
show this effect. As pointed out in application note 
AN-90, 54C/74C Family Characteristics, propagation 
delay is a function of Vcc- Figure 3, (Pulse Width = 
lOjUs) shows much greater variation with Vcc 
Figure 4 (Pulse Width = lOOOps). This same information 
1 is shown in Figures 5 and 5 in a different format. In 



Vcc (V) 


TL/F/6023-5 


FIGURE 5. Typical Percentage Deviation from 
Vcc = 10V Value vs Vcc (PVV = IOms). 



5 10 15 


FIGURE 6. Typical Percentage Deviation from 
Vcc = 10V Value vs V^c (PW = IOOOms). 


these figures the percent deviation from the average 
pulse width at 10V Vcc is shown vs Vcc- In addition 
to the average value the 10% and 90% points are shown. 
These percentage points refer to the statistical distribu- 
tion of pulse width error. As an example, at Vcc ~ ^0^ 
for ^0|Jis pulse width, 90% of the devices have errors of 
less than +1.7% and 10% have errors less than -2.1%. 
In other words, 80% have errors between +1.7% and 
- 2 . 1 %. 


The minimum error can be obtained by operating at 
the maximum Vqo ^ price must be paid for this and 
this price is, of course, increased power dissipation. 


Figure 7 shows typical power dissipation vs Vcc 
operating both sides of the one-shot at 50% duty cycle. 
Also shown in the same figure Is typical minimum pulse 
width vs Vcc- The minimum pulse width is a strong 
function of internal propagation delays. It is obvious 
from these two curves that increasing Vqc beyond 10V 
will not appreciably improve inaccuracy due to propa- 
gation delay but will greatly increase power dissipation. 

Accuracy is also a function of temperature. To determine 
the magnitude of its effects the one-shot was tested at 
temperature with the external resistance and capacitance 
maintained at 25°C. The resulting variation is shown in 
Figures 8 and 9. 

8 
6 
4 
2 
0 

-2 
-4 
-6 

-55 25 125 

Ta - AMBIENT TEMPERATURE { C) 

FIGURE 8. Typical Pulse Width Error vs 
Temperature (PW = 10 ms). 





Ta - AMBIENT TEMPERATURE ( C) TL/F/6023-9 

FIGURE 9. Typical Pulse Width Error vs 
Temperature (PW = IOOOms). 

Up to this point the external timing resistor, Rext« has 
been held fixed at 10 k^2. In actual applications other 
values may be necessary to achieve the desired pulse 
width. The question then arises as to what effect this 
will have on accuracy. 



250 

225 

200 

175 

150 

125 

100 

75 

50 

25 


5 


10 • 15 


DO > 


J> 3> 
-H O 
tn 

^ s 


Vcc (V) 


FIGURE 7. Typical Minimum Pulse Width and 
Power Dissipation vs Vcc- TL/p,g 


Vcc 



As Rext becomes larger and larger the leakage current 
on transistor NV becomes an ever increasing problem. 
The equivalent circuit for this leakage is shown in 
Figure 10. 


2-26 



v(t) is given by: 

v(t) = (Vcc - II Rext) (1 "■ Cext) 

As before, when v(t) = 0.63 Vq^/ the output will reset. 
Solving for ti_ gives: 


We have just defined the limitation on the maximum size 
of Rext* There is a corresponding limit on the mini- 
mum size that Rext can assume. This is brought about 
because of the finite ON impedance of NT. As Rext 's 
made smaller and smaller the amount of voltage across 
N1 becomes significant. The voltage across N1 is: 


tu ” Rext Cext 


^ / Vcc k Rext \ 

Cn ) (3) 

\0.37 Vcc-k Rext/ 


Using T as defined in Equation 2 the pulse width error is: 
tL-T 


PW Error = 


x 100% 


Substituting Equations 2 and 3 gives: 

Vcc “ k Rext 


RextCext<-'i 


PW Error =- 


t’n / ^cc k Rext \ _ 
\0.37 Vcc-Il Rext/ 


R e XT Ce XT 1/0.37) . 


Rext ^ext ^'n (1/0.37) 


VnI “ Vcc ("oN/iREXT '"on) (4) 

The output pulse width is defined by: 

V (to) = (Vcc - Vfji) (1 -e-'o''’EXT Cext) 

+ V|\]i = 0.63 Vqc 
Solving for to gives: 



Pulse Width Error is then: 

to -T 

PW Error = x 100% 

T 


PW Error is plotted in Figure 11 for Vcc = 5, 10 and 
15V. As expected, decreasing Vcc causes PW Error to 
increase with fixed II- Note that the leakage current, 
although here assumed to flow through N1, is general 
and could also be interpreted as leakage through C^xt* 
See MM54C221 /MM74C221 data sheet for leakage limits. 



FIGURE 11. Percentage Pulse Width Error Due to Leakage. 


To demonstrate the usefulness of Figure 11 an example 
will be most helpful. Let us assume that N1 has a 
leakage of 250 x 10~® amps, C^xt has leakage of 
150 X 10"^ amps, output pulse width = 0.1 seconds and 
Vcc “ 5V. What Rext Cext should be used to 
guarantee an error due to leakage of less than 5%. 

From Figure 11 we see that to meet these conditions 

Rext k < 0-14V. 

Then: 

Rext < 0.14/(250 + 150) x 10~^ 

< 350 kO 

Choosing standard component values of 250 kH and 
0.004iuF would satisfy the above conditions. 


. Substituting Equations 2 and 4 gives: 

/Vcc - VnA 

Rext ^ext ^ , ) Rext Cext (1/0.37) 

\ 0.37 V QQ / 

Rext Cext (1/0.37) 

This function is plotted in Figure 12 for roN 50r2, 
25n and 16.712. These are the typical values of roN for 
a Vcc of 5V, 10V and 15V respectively. 

As an example, assume that the pulse width error due to 
roN must be less than 0.5% operating at Vcc ^ 5V. The 
typical value of Ton for V^c 5V is 5012. Referring to 



Rext (U) TL/F/6023-12 

FIGURE 12. Percentage Pulse Width Error 
Due to Finite rQN Transistor Ml vs ReXT* 

the 5012 curve in Figure 12, Rext R^ost be greater than 
10 kl2 to maintain this accuracy. At Vcc ^ ^^V, Rext 
must be greater than 5 kl2 as can be seen from the 2512 
curve in Figure 12. 

Although clearly showr) on the MM54C221 /MM74C221 
data sheet, it is worthwhile, for the sake of clarity, to 
point out that the parasitic capacitance between pins 
7 (15) and 6 (14) is typically 15 pF. This capacitor is in 
parallel with Cfrxr mt/sf be taken intb account when 
accuracy is critical. 



2-27 


AN-138 












2-29 





AN-140 


CMOS Schmitt Trigger 
— a Uniquely Versatile 
Design Component 


INTRODUCTION 

The Schmitt trigger has found many applications in 
numerous circuits, both analog and digital. The versa- 
tility of a TTL Schmitt is hampered by its narrow 
supply range, limited interface capability, low input 
impedance and unbalanced output characteristics. The 
Schmitt trigger could be built from discrete devices to 
satisfy a particular parameter, but this is a careful and 
sometimes time-consuming design. 

The CMOS Schmitt trigger, which comes six to a 
package, uses CMOS characteristics to optimize design 
and advance into areas where TTL could not go. These 
areas include: interfacing with op amps and transmission 
lines, which operate from large split supplies, logic level 
conversion, linear operation, and special designs relying 
on a CMOS characteristic. The CMOS Schmitt trigger 
has the following advantages: 

■ High impedance input typical) 

■ Balanced input and output characteristics'^ 

• Thresholds are typically symmetrical to 1/2 Vcc- 

• Outputs source and sink equal currents 

• Outputs drive to supply rails 

■ Positive and negative-going thresholds show low 
variation with respect to temperature 

■ Wide supply range (3— 15V), split supplies possible 

■ Low power consumption, even during transitions 

■ High noise immunity, 0.70 Vcc typical 

Applications demonstrating how each of these charac- 
teristics can become a design advantage will be given 
later in the application note. 


National Semiconductor 
Application Note 140 
Gerald Buurma 
June 1975 


ANALYZING THE CMOS SCHMITT 

The input of the Schmitt trigger goes through a standard 
input protection and- is tied to the gates of four stacked 
devices. The upper two are P-channel and the lower two 
are N-channel. Transistors P3 and N3 are operating in the 
source follower mode and introduce hysteresis by 
feeding back the output voltage, out', to two different 
points in the stack. 


When the input is at OV, transistors PI and P2 are ON, 
and N1, N2 and P3 are OFF. Since out' is high, N3 is 
ON and acting as a source follower, the drain of N1, 
which is the source of N2, is at Vcc— V jh- 1^1^® input 
voltage is ramped up to one threshold above ground 
transistor N1 begins to turn ON, N1 and N3 both being 
ON form a voltage divider network biasing the source of 
N2 at roughly half the supply. When the input is a 
threshold above 1/2 Vcc, N2 begins to turn ON and 
regenerative switching is about to take over. Any more 
voltage on the input causes out' to drop. When out' drops, 
the source of N3 follows its gate, which is out', the 
influence of N3 in the voltage divider with N1 rapidly 
diminishes, bringing out' down further yet. Meanwhile 
P3 has started to turn ON, its gate being brought low by 
the rapidly dropping out'. P3 turning ON brings the 
source of P2 low and turns P2 OFF. With P2 OFF, out' 
crashes down. The snapping action is due to greater than 
unity loop gain through the stack caused by positive 
feedback through the source follower transistors. When 
the input is brought low again an identical process occurs 
in the upper portion of the stack and the snapping 
action takes, place when the lower threshold is reached. 



Vcc 

J 


TL 



2-30 





Out' is fed into the inverter formed by P4 and N4; 
another inverter built with very small devices, P5 and 
N5, forms a latch which stabilizes out'. The output is 
an inverting buffer capable of sinking 360/iA or two 
LPTTL loads. 

The typical transfer characteristics are shown in Figure 
2; the guaranteed trip point range is shown in Figure 3. 


WHAT HYSTERESIS CAN DO FOR YOU 

Hysteresis is the difference in response due to the direc- 
tion of input change. A noisy signal that traverses the 
threshold of a comparator can cause multiple transitions 
at the output, if the response time of the comparator is 
less than the time between spurious effects. A Schmitt 
trigger has two thresholds: any spurious effects must be 
greater than the threshold difference to cause multiple 
transitions. With a CMOS Schmitt at Vcc = 10V there is 


typically 3.6V of threshold difference, enough hysteresis 
to overcome almost any spurious signal on the input. 

A comparator is often used to recover information sent 
down an unbalanced transmission line. The threshold of 
the comparator is placed at one half the signal amplitude 
(See Figure 4b). This is doen to prevent slicing level 
distortion. If a 4jUs wide signal is sent down a transmission 
line a 4ps wide signal should be received or signal distor- 
tion occurs. If the comparator has a threshold above half 
the signal amplitude, then positive pulses sent are shorter 
and negative pulses are lengthened (See Figure 4c). This 
is called slicing level distortion. The Schmitt trigger does 
have a positive offset, Vt+, but it also has a negative 
offset Vj_. In CMOS these offsets are approximately 
symmetrical to half the signal level so a 4ius wide pulse 
sent is also recovered (see Figure 4d). The recovered 
pulse is delayed in time but the length is not changed, 
so noise immunity Is achieved and signal distortion is not 
introduced because of threshold offsets. 




Vcc (V) TL/F/6024-3 


FIGURE 2. Typical CMOS Transfer Characteristics FIGURE 3. Guaranteed Trip Point Range, 

for Three Different Supply Voltages. 



TIME (/us) TL/F/6024.4 


FIGURE 4., CMOS Schmitt Trigger Ignores Noise 



2-31 


AN-140 



AN-140 



a) Capacitor impedance at lowest operating frequency should be much less than R | |R = 1/2R. 



Vcc 



Vss 


TL/F/6024-6 


b) By using split supply (±1.5 to ±7.5) direct interface is achieved. 


FIGURE 5. Sine to Square Wave Converter with Symmetrical Level Detection. 


C2 



APPLICATIONS OF THE CMOS SCHMITT 

•Most of the following applications use a CMOS Schmitt 
characteristic to either simplify design or increase per- 
formance. Some of the applications could not be done 
at all with another logic family. 

The circuit in Figure 5a is the familiar sine to square 
wave converter. Because of input symmetry the Schmitt 
trigger is easily biased to achieve a 50% duty cycle. The 
high input impedance simplifies the selection of the bias- 
ing resistors and coupling capacitor. Since CMOS has a 
wide supply range the Schmitt trigger could be powered 
from split supplies (see Figure 5b). This biases the mean 
threshold value around zero and makes direct coupling 
from an op amp output possible. 


In Figure 4, we see a frequency to voltage conv,erter that 
accepts many waveforms with no change in output 
voltage. Although the energy in the waveforms are quite 
different, it is only the frequency that determines the 
output voltage. Since the output of the CMOS -Schmitt 
pulls completely to the supply rails, a constant voltage 
swing across capacitor Cl causes a current to flow 
through the capacitor, dependent only on frequency. 
On positive output swings, the current is dumped to 
ground through D1. On negative output swings, current 
is pulled from the inverting op amp node through D2 and 
transformed into an average voltage by R2 and C2. 

Since the CMOS Schmitt pulls completely to the supply 
rails the voltage change across the capacitor is just the 
supply voltage. 


2-32 




Schmitt triggers are often used to generate fast transi- 
tions when a slowly varying function exceeds a pre- 
determined level. In Figure 7, we see a typical circuit, a 
light activated switch. The high impedance input of the 
CMOS Schmitt trigger makes biasing very easy. Most 
photo cells are several brightly illuminated and a 
couple MH dark. Since CMOS has a typical input 

impedance, no effects are felt on the input when the 
output changes. The selection of the biasing resistor is 
just the solution of a voltage divider equation. 

A CMOS application note wouldn't be complete without 
a low power application. Figure 8 shows a simple RC 
oscillator. With only six R's and G's and one Hex CMOS 


trigger, six low power oscillators can be built. The square 
wave output is approximately 50% duty cycle because of 
the balanced input and output characteristics of CMOS. 
The output frequency equation assumes that t^ = t 2 » 
tpdO tpdl • 

We earlier saw how the CMOS Schmitt increased noise 
immunity on an unbalanced transmission line. Figure 9 
shows an application for a balanced or differential 
transmission line. The circuit in Figure 7a is CMOS 
EXCLUSIVE OR, the MM74C86, which could also be 
built from inverters, and NAND gates. If. unbalanced 
information is generated on the line by signal crosstalk 
or external noise sources, it is recognized as an error. 




FIGURE 7. Light Activated Switch couldn't be Simpler. The Input Voltage Rises as Light Intensity Increases, when is 
Reached, the Output will go Low and Remain Low until the Intensity is Reduced Significantly. 






OUTPUT 

WAVEFORMS 


TL/F/6024-9 


FIGURE 8. Simplest RC Oscillator? Six R's and C's make the CMOS Schmitt into Six Low Power Oscillators. Balanced 
Input and Output Characteristics give the Output Frequency a Typically 50% Duty Cycle. 


1/3 MM74C14 



Error is detected iMhen transmission line is unbalanced in either direction. 


TL/F/6024-10 


a) Differential Error Detector. 


1/3 MM74C14 Schmitt Trigger 
1/6 .MIV174C04 lovelier 



Transmitted data appears at F as long as. transmission line is balanced, 
unbalanced data is ignored and error is detected by above circuit. 


A B 

F 

0 0 

NC 

0 1 

0 

1 0 

1 

1 1 

NC 


NC = No Change 


b) Differential Line Receiver. 


TL/F;6024-11 


FIGURE 9. Increase Noise Immunity by using the CMOS Schmitt Trigger to Demodulate a Balanced Transmission Line. 



2-33 


AN-140 



AN-140 


The circuit in Figure 9b is a differential line receiver 
that reco^yers balanced transmitted data but ignores 
unbalanced signals by latching- up. If both circuits of 
Figure 9 were used together, the error detector could 
signal the transmitter to stop transmission and the line 
receiver would remember the last valid information bit 
when unbalanced signals persisted on the line. When 
balanced signals are restored, the receiver can pick up 
where it left off. 

The standard voltage range for CMOS inputs is Vqc 
+ 0.3V and ground -0.3V. This is because the input pro- 
tection network is diode clamped to the supply rails. Any 
input exceeding the supply rails either sources or sinks 
a large amount of current through these diodes. Many 
times an input voltage range exceeding this is desirable; 
for example, transmission lines often operate from ±12V 
and op amps from ±15V. A solution to this problem is 
found in the MM74C914. This new device has an uncom- 
mon input protection that allows the input signal to go 
to 25V above ground, and 25V below Mqq- This means 
that the Schmitt trigger in the sine to square wave 
converter, in Figure 5b, could be powered by ±1.5V 
supplies and still be directly compatible with an op amp 
powered by ±15V supplies. 

A standard input protection circuit and the new input 
protection are shown in Figure 10. The diodes shown 
have a 35V breakdown. The input voltage can go positive 
until reverse biased D2 breaks down through forward 
bias D3, which is 35V above ground. The input voltage 
can go negative until reverse biased D1 breaks down 
through forward bias D2, which is 35V below Vcc- 
Adequate input protection against static charge is still 
maintained. 


Vcc 



a) 


CMOS can be linear over a wide voltage range if proper 
consideration is paid to the biasing of the inputs. Figure 
11 shows a simple VCO made with a CMOS inverter, 
acting as an integrator, and a CMOS Schmitt, acting as a 
comparator with hysteresis. The inverter ‘ integrates the 
positive difference between its threshold and the input 
voltage V|m. The inverter output ramps up until the 
positive threshold of the Schmitt trigger is reached. At 
that time, the Schmitt trigger output goes low, turning 
on the transistor through Rg and speeding up capacitor 
Cg. Hysteresis keeps the output low until the integrating 
capacitor C is discharged through R^. Resistor Rq 
should be kept much smaller than RC to keep reset time 
negligible. The output frequency is given by 

^ ^ Vth - V|N 

(Vj+ ~ V-p_) Rcc- 

The frequency dependence with control voltage is given 
by the derivative with respect to V|ry) So, 

d fp ^ -1 

d V,N (Vt+ - Vt-) RC, 


where the minus sign indicates that the output frequency 
increases as the input is brought further below the inverter 
threshold. The maximum output frequency occurs when 
V|N is at ground and the frequency will decrease as V|n 
is raised up and will finally stop oscillating at the 
inverter threshold, approximately 0.55 Vcc- 


Vcc 



b) 


FIGURE 10. Input Protection Diodes, in a) Normally Limit the Input Voltage Swing to .0.3V above Vqq and 0.3V 
below Ground. In b) D2 or D1 is Reverse Biased Allowing Input Swings of 25V above Ground or 25V below Vqq. 



2-34 




The pulses from the VCO output are quite narrow 
because the reset time is much smaller than the integra- 
tion time. Pulse stretching comes quite naturally to a 
Schmitt trigger. A one-shot or pulse stretcher made with 
an inverter and Schmitt trigger is shown in Figure 12. 
A positive pulse coming into the inverter causes its 
output to go low. discharging the capacitor through the 
diode D1. The capacitor is rapidly discharged, so the 
Schmitt input is brought low and the output goes 
positive. Check the size of the capacitor to make sure 
that inverter can fully discharge the capacitor in the 
input pulse time, or 

, C AV AV . 

'sink inverter > + 

AT R 


where AV = Mqq for CMOS, and AT is the input pulse 
width. 

For very narrow pulses, under 100 ns, the capacitor can 
be omitted and a large resistor will charge up the CMOS 
gate capacitance just like a capacitor. 

When the inverter input returns to zero, the blocking 
diode prevents the inverter from charging the capacitor 
and the resistor must cKarge it from its supply. When 
the input voltage of the Schmitt reaches V-j-+, the 
Schmitt output will go low sometime after the Input 
pulse has gone low. 


THE SCHMITT SOLUTION 

The Schmitt trigger, built from discrete parts, is a careful 
and sometimes time-consuming design. When introduced 
in integrated TTL, a few years ago, many circuit designers 
had. renewed interest because it was a building block 
part. The input characteristics of TTL often make biasing 
of the trigger input difficult. The outputs don't source 
as much as they sink, so multivibrators don't have 50% 
duty cycle, and a limited supply range hampers inter- 
facing with non 5V parts. 

The CMOS Schmitt has a very high input impedance with 
thresholds approximately symmetrical to one half the 
supply. A high voltage input is available. The outputs 
sink and source equal currents and pull directly to the 
supply rails. 

A wide threshold range, wide supply range, high noise 
immunity, low power consumption, and low board 
space make the CMOS Schmitt a uniquely versatile 
part. 

Use the Schmitt trigger for signal conditioning, restora- 
tion of levels, discriminating noisy signals, level detecting 
with hysteresis, level conversion between logic families, 
and many other useful functions. 

The CMOS Schmitt is one step closer to making design' 
limited only by, the imagination of the designer. 



1/6MM74C04 



‘ Q To - t|(y + T 

T 


/ Vcc - Vbe \ C Vcc Vrc 

T=RCtn BE SURE THAT Isinkimverter > — TL;f/6024-15 

\ Vcc - Vj. / t R 

FIGURE 12. Pulse Stretcher. A CMOS Inverter Discharges a Capacitor, 
a Blocking Diode allows Charging through R only. Schmitt Trigger 
Output goes Low after the RC Delay. 



2-35 


on-NV 




AN-143 


Using National Clock 
Integrated Circuits in Timer 
Applications 


National Semiconductor 
Application Note 143 
November 1975 



INTRODUCTION 

The following is a description of a technique which 
allows the use of the National IVIM5309; IVIIVI5311, 
MM5312 and IVII\/15315 clock integrated circuits as 
timers in industrial and consumer applications. What 
will be presented is the basic technique along with some 
simple circuitry and applications. 

BASIC TECHNIQUE 

When first approaching the problem of using clock chips 
for timers, the most obvious technique is to attempt to 
compare the display data with preset BCD numbers. 
Because of the multiplexing and number of data bits 
this technique, while possible, is unwieldy and requires a 
large number of components. 


An easier method is to use one or more demultiplexed 
BCD lines as control waveforms whose edges determine 
timer data. In Figure 1 we examine the 1-bit of the BCD 
data of the units second time. 


From this waveform we observe a one second wide pulse 
every two seconds. If we look at the 4-bit of the 10 
minutes digit we find a pulse which is 20 minutes wide 
and occurs once each hour. 


Figure 5. is a chart showing the various pulses and their 
widths for all digits and the useful BCD lines. 


UNIT SECOND 
DIGIT TIME 
BC0 1 


Q 1 


ISEC 


^2SEC- 




FIGURE 1, 1 Second Pulse Every 2 Seconds 


TL/D/7397-1 


10MINITE DIGIT 
TIME 
BCD 1 



TL/ D/7397-2 


FIGURE 2. 20 Minute Pulse Every Hour 


2-36 





BCD 

PULSE RATE 

PULSE WIDTH 

BCD 

PULSE RATE 

PULSE WIDTH 


1 Sec Digit 



10 Sec Digit 


1 

1 every 2 sec 

1 sec* 

1 

1 every 20 sec 

10 sec* 

2 



2 

1 every min 

20 sec 

4 

1 every 10 sec 

4 sec 

4 

1 every min 

20 sec 

8 

1 every 10 sec 

2 sec 

8 



• 

1 Min Digit 



10 Min Digit 


1 

1 every 2 min 

1 min* 

1 

1 every 20 min 

10 min* 

2 



2 

1 every hr 

20 min 

4 

1 every 1 0 min 

4 min 

4 

1 every hr 

20 min 

8 

1 every 10 min 

2 min 

8 




Units Hrs Digit (12 Hr Mode) 


Units Hrs Digit (24 Hr Mode) 

1 

1 every 2 hrs 

1 hr* 

1 

1 every 2 hrs 

1 hr*, 

2 



2 



4 

1 every 1 2 hrs 

4 hrs 

4 



8 

1 every 1 2 hrs 

4 hrs 

8 




10 Hrs Digit (12 Hr 

Mode) 


10 Hrs Digit (24 Hr Mode) 

1 



1 

1 every 24 hrs 

10 hrs 

2 

1 every 1 2 hrs 

9 hrs 

2 

1 every 24 hrs 

4 hrs 

4 

1 every 1 2 hrs 

9 hrs 




8 

1 every 1 2 hrs 

9 hrs 





^Square waves 


TL/D/7397-3 


FIGURE 3 


SIMPLE DEMULTIPLEXING 

In the simple case where, for example, a four hour wide 
pulse each day is desired, perhaps to turn on lights in the 
evening, a simple demultiplexing scheme using one diode 
is shown in Figure 4. When power is applied, the internal 
multiplex circuitry vyill strobe each digit until the digit 
with the diode connected is accessed. This digit will 
sink the multiplex charging current and stop the multi- 
plex scanning. Thus, the BCD outputs now present the 
data from the selected digit. The waveforms as previously 
discussed are presented at the BCD lines. Note that these 
pulses are negative true for all BCD outputs. 

An advantage of this type of timer over mechanical 
types is the elimination of line power drop outs. The 
circuit shown in Figure 5 will maintain timing to within 
a few percent during periods of power line failure, but 
automatically return to the 60 Hz line for timing as soon 
as power is restored. 


MORE COMPLEX APPLICATIONS 

Where it is desired to maintain the display, or in more 
complex timing of the "10 seconds every two hours" 
variety, external demultiplexing shown in Figure 6 can 
be used. In this figure the BCD lines are demultiplexed 
with MM74C74 flip-flops. Examining the waveforms of 
these circuits we see two edges which allow the 10 
second each two hours timing. These are differentiated 
by the NAND and INVERTERS and the first edge sets 
and the second resets the S-R flip-flop. The output of the 
flip-flop is ten seconds wide every two hours. By exam- 
ining the edges of the Figure 3 entries any combination 
of timings can be obtained with the circuit of Figure 6. 

LOW FREQUENCY WAVEFORM GENERATION 

The asterisked BCD lines in Figure 3 are those wave- 
forms which are symmetric. By the use of the simple 
diode demultiplexing scheme previously discussed we 


2-37 


AN-143 




AN-143 


Vss 



BCD LINES 
FOR SELECTED 
DIGIT 


TU D/7397-4 



easily obtain square waves with periods of two seconds, 
two minutes, twenty minutes and two hours. In other 
cases, where the waveforms are asymmetric, a simple 
flip-flop can square, while dividing by two, these wave- 
forms producing other low frequency square waves as 
long as one per two days. 

SUMMARY 

We have shown some simple low cost timer and waveform 
generating examples using National clock integrated 


circuits. Because of the vast number of timing applica- 
tions possible, this can in no way be looked at as the 
limit of clock-timer circuits. Use of the Reset on the 
MM5309 and MM531 5 or the use of clocks in conjunction 
with programmable counters such as the MM74C161 
allows other possibilities to meet specific applications. 
Also the clock chips themselves can run on frequencies 
other than 50 or 60 Hz (actually from dc to 10 kHz) 
which can allow scaling of the waveforms presented in 
Figure 3 to different timing rates. 


2-38 






2-39 


AN-143 





AN-177 


Designing with MM74C908, 
MM74C918 Duai High 
Voltage CMOS Drivers 


National Semiconductor 
Application Note 177 
Jen-yen Ruang 
March 1977 



INTRODUCTION 

By combining the merits of both CMOS and bipolar 
technologies on a single silicon chip, the MM74C908, 
MM74C918 provides the following distinguished fea- 
tures as general purpose high voltage drivers. 

■ Wide supply voltage range (3V to 18V) 

■ High noise immunity (typ 0.45 Vcc) 

■ High input impedance (typ 1012^2) 

■ Extremely low standby power consumption (typ 
750 nW at 15V) 

■ Low output "ON" resistance (typ 8^1) 

■ High output drive capability (loUT ^ 250 rnA at 
VOUT = Vcc - 3V, and Tj = 65°C) 

■ High output "OFF" voltage 

Among these, the first 4 are typical and unique char- 
acteristics of CMOS technology which are fully util- 
ized in this circuit to achieve all the design advan- 
tages in a typical CMOS system. 

The high output currents and low "ON" resistance 
are achieved through the use of an NPN Darlington 
pair at the output stage. 

The MM74C908 is housed in an 8-lead epoxy dual- 
in-line package, which can dissipate at least 1.14W. 
The higher power^ version, MM74C918, comes in a 
14-lead epoxy dual-in-line package, with power cap- 
ability up to a minimum of 2.27W. 


The circuitry for each of the 2 identical sections is 
shown in Figure 1 . 

With both inputs sitting at logical "1" level, the 
output of the inverter is also at logical "1", which 
prevents the • P-channel transistor from being turned 
"ON"; therefore, the output is in its "OFF" state. 
Only a small amount of leakage current can flow. 

On the other hand, when one or' both of the inputs 
is at logical "0" level, the output of the inverter is 
also at logical "0", which turns on the P-channel tran- 
sistor and, hence, the Darlington pair. 

POWER CONSIDERATION 

To assure junction temperature of 150°C or less, the 
on-chip power consumption must be limited to within 
the- power handling capability of the packages. In 
Figure 2, the maximum power dissipation on-chip 
is shown as a function of ambient temperature for 
both MM74C908 and MM74C918. These curves are 
generated from (1) at Tj = = 150°C. 

T| = TA + PD0jA (1) 

where Tj = junction temperature 
Ta = ambient temperature 
Pq = power dissipation 

^jA " thermal resistance between junction and 
ambient 


Vcc 



FIGURE 1 TL/F/6025 1 



0 10 30 50 70 90 110 130 150 

Ta - AMBIENT TEMPERATURE (°C) 


FIGURE 2. Maximum Power Dissipation vs 
Ambient Temperature * 

TL/F/6025-2 



2-40 





A general application circuit for the MI\/174C908, 
MM74C918 is as shown in Figure 3. 


Vcc 



For both sections A and B; 

vcc-vl 


'out 


Ron + Rl 


( 2 ) 


The device "ON" resistance, RqN' ^ function of 
junction temperature, Tj. The worst-case Rqn ^ 
function of Tj is given in (3). 


Ron = 9 [1 +0.008 (Tj-25)] 


(3) 


The total power dissipation in the device also consists of 
normal CMOS power terms (due to leakage current, 
internal capacitance, switching etc.) which are insignifi- 
cant compared to the power dissipated at the output 
stages. Thus, the output power term defines the allowable 
limits of operation and is given by: 


Pd = pda + Pdb 

= '^OUTA * Ron + i^outb * Ron 


(4) 


Given R|_a and RlB^ 0)/ (2), (3), (4) can be used to 
calculate Pq, Tj, etc. through iteration. 


For example, let Vl = OV, Vqc ~ Ri_/\ = 10012, 

Rlb = 5012, Ta = 25°C, Oja = 1 10°C/W. 


Assume: 

Ron = 12.2812 

By (2): 


IOUTA = 


IOUTB = 


10 

= 0.089A 

12.28 + 100 

10 

= O.ieiA 

12.28 + 50 


By (4): 

PD = (0.089)2 • 12.28 + (0.161)2 • 12.28 = 0.41W 

By(1): 

Tj = 70.5°C 

And by (3); 

Ron = 12.2812 


DESIGN TECHNIQUE . 

In a typical design, Rl must be chosen to satisfy the 
load requirement (e.g., a minimum current to turn 
on a relay) and at the same time, the power consumed 
in the driver package must be kept below its maximum 
power handling capability. 


To minimize the design effort, a graphical technique is 
developed, which combines all the parameters in one 
plot, which can be used efficiently to obtain an optimal 
design. 


Assume Ta = 25°C and that both sections of the 
MM74C908 in Figure 3 are operating under identical 
conditions. The maximum allowable package dissipation 
is: 


Pd = 2 (Vcc - Vqut) X IqUT 


= (150 - Ta) = 1.14W 

110 


where Tj = 150°C, 0jA = 1ld°C/W are used in (1) per 
the data sheet. 


Thus, the maximum power allowed in each section is: 

Pd = (Vcc - Vqut) x IqUT = 0.57W 


A constant power curve Pq = 0.57W can then be plotted 
as shown in Figure 4. The circuit must operate below 
this curve. Any voltage-current combination beyond it 
(in the shaded region) will not guarantee Tj to be lower 
than 150°C. 

For any given Rl, a load line (7) can be superimposed 
on Figure 4. 

1 , 1 

iouT= — (Vcc - Vl* (V cc- V qut) 

Rl Rl 


The slope of this load line is — 1 /Rl and it intersects 
with the vertical and horizontal axes at 1 /Rl (Vqc ~ 
Vl) and Vcc — Vl respectively. 


Given Vqc Vl, a minimum Rl can be obtained by 
drawing the load line tangent to the constant power 
curve. In Figure 4, at Vcc - Vl = 5V the line inter- 
sects (out axis at IquT = 450 mA. Thus, Rl(MIN) = 
5V/450 mA = 11.112. Any Rl value below this will 
move the intersecting point up and cause a section of the 
load line to extend into the shaded region. Therefore, 
the junction temperature can exceed Tj(|viAX) 150°C 
in the worst case if the circuit operates on such a section 
of the load line. 


Whether this situation will occur or not is determined 
by both the value of Vcc - Vl and the Rqn range of 
the drivers. 



2-41 


AN-177 




AN-177 


I 



Vqc - VqUT TL/F/6025-4 

FIGURE 4 


By (3), at Tj = 150°C RON(MAX) this is a 

straight line* passing through the origin with a. slope of 
•OUT/(VcC “ ^OUT) = T/18 mho and intersects the 
load line at point A. Similarly, point B and C can be 
found for typical {~10^2) and minimum {~512) RqN 
at Tj = 150°C. 

For Vqq — Vl = 5V, the tangent point falls between A 
and C. Hence, R|_ > 11.10 calculated above must be 
satisfied; otherwise, part of the load line within the 
specified RqN range will extend into the shaded region 
and therefore, Tj > 150°C may occur. 

For Vqc — V|_ = lOV, however, a section of the load 
line can go beyond, the Pq - 0.57W curve without 
affecting the safe operation of the circuit. By inspection 
of Figure 4, the reason is clear— the load line extends, 
into the shaded region only outside of the specified 
Ron range (to the right of point A'). Within the Rqn 
range, the load line lies below the Pq = 0.57W curve, 
thus, a safe operation. 

To a first approximation**, the section of the load line 
between A and C is the operating range for the circuit at 
Vqc — Vl = 5V and Rl = 1 1 .IH. Hence, the available 
current and voltage ranges for this circuit are 310 mA > 
•out ^ 172 mA and 3.4V > VquT ^ 1-9V, respec- 
tively. 

Thus, by simply drawing no more than 3 straight lines, 
one obtains ail of the following immediately: 

1. All the necessary design information (e.g., minimum 
Rl, minimum available IqliT ^rid VquT' 

2. Operating characteristics of the circuit as a whole, 
including the effect of different Rqn values due to 
process variations, thus, a better insight into the’ 
circuit operation. 


3. Most importantly, a guarantee that the circuit will be 
operating in the safe region, (Tj < 150°C). 

For different ambient temperatures or for different 
power considerations. Figure 4 can be applied by prop- 
erly scaling the IqLIT axis. (Note that loUT Tj — Ta 
and IquT “ Pq)- 



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 


VCC - VqUT IV) TL/F/6025-5 

FIGURE 5. Typical IqUT vs Typical VquT 

*Strictly speaking, Rqn 's a non-linear function 'of IquT- A 
typical Rqn characteristic at Tj = 150°C is shown in Figure 5. 
The non-linear characteristic near the origin is due to the fact 
that the output NPN transistor is not saturated. As soon as 
saturation is reached (IqUI — 1^0 the curve becomes a 
straight line which extrapolates back to the origin. For practi- 
cal design purposes, it is sufficient to consider Rqn 3® ^ linear 
function of IqUT- 

**Note that as the pperating point on the load line moves away 
from the Pq = 0.57W curve, (away from the tangent point in 
this case), the actual junction temperature drops. Therefore, at 
point A, for example, the device is actually running cooler than 
Tj = 150°C, even in the worst case. Hence, Rqn value drops 
below 18n and the actual operating point is slightly different 
from A. 


2-42 




To further simplify the design, a family of such curves 
has been generated as shown in Figure 6. Each of these 
curves corresponds to a particular T/\ and Pq (per driver) 
as indicated, and similar to the Pq = 0.57V\/ curve in 
Figure 4, is generated from (6) by using appropriate Ta 
values. The application of these curves is illustrated as 
follows: 

Example 1 


b) Vcc-Vl= 10V 


The RLdVlIlM) given in (8) may not be a true 
minimum if the tangent point does not fall inside 
the specified Rqn region. The actual Rl(MIN) 
can be obtained as shown in Figure 7. The calcula- 
tions and results are given in Table II. 


1. In Figure 3, assume that the two drivers in the 
MM74C908 package are to operate under identical 
conditions. Find minimum Rl at 1 /\ = 25°C, 45°C, 
65°C and 85°C for both Vqc - V|_ = 5V and V^C — 
Vl=10V. 

Then plot Rl(MIN) vs Ta- 
a)Vcc-VL = 5V 

By constructing the load lines tangent to the 
curves for Ta = 25°C, 45°C, 65°C and 85°C, 
RL(MIN) "for each case can be obtained through 
the vertical coordinate for the intersection points 
as shown in Figure 6. These are calculated in 
Table I. 


Note that the same results (within graphical error) 
can be obtained analytically by letting dRi_/ 
dRoN 0- R can be shown that 


Rl(MIN) = 


(Vcc - Vl)^ 

4X (Max Power Per Driver) 


( 8 ) 


Note that the Rl(MIN) values in Table II are 
lower than those given by (8). This corresponds to 
the section on each of the 4 load lines in Figure 7' 
which extends beyond the power limit curve at 
each associated, temperature. However, this section 
on each load line is outside the specified Rqn 
range. Within the Rqn range, load lines are below 
the power limits; therefore, safe operation is 
guaranteed. 


The Rl(MIN) vs Ta plot is as shown in Figures. 


Ail the curves generated so far are restricted to 
pd < 0.57W due to our simplifying assumption 
that both drivers are operating identically. In 
Figure 9 a few more curves are added to account 
for the general situation in which only the restric- 
tion Pda PDB ^ 1.14W is required, (i.e., Pda 
can be different from Pdb)- Application of 
Figure 9 is illustrated as follows: 


TABLE I 


Ta 

25“ C 

45“ C 

65“ C 

85“ C 

IOUT@ D1, 2, 3, 4 (mA) 

450 

375 

310 

240 

IoUT®>P1.2,3,4 

11.1 

13.3 

16.1 

20.8 


TABLE il 


Ta 

25° C 

45“ C 

65° C 

85° C 

IquT @ D1 , 2, 3, 4 (mA) 

261 

230 

197 

166 

10 

Rl(MIN) d1,2, 3, 4 ^ 

38.3 

43.5 

50.8 

60.2 



2-43 


AN-177 




AN-177 



0 1 2 3 4 , 5 6 7 8 9 10 11 12 13 14 15 

VCC - VouT<''> TL/F/6025-6 

FIGURE 6 



0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 


VCC “ Vqut fv) TL;F/6025-7 

FIGURE? 


2-44 





AN-177 



AN-177 


Example 2 

In Figure 3, assume that driver A has to deliver 200 mA 
to its load while driver B needs only 100 mA. Design 
RLA R|_b for Vcc — Vl = 5V. 

By inspection of Figure 4, units with high Rqn values 
will not be able to deliver 200 mA. However, since 
section B does not need the same amount of drive, we 
can reduce the power consumed in this section to com- 
pensate for the higher power {> 0.57W) required in 
section A. 

The design procedure follows: 

Section A 

1. Draw a load line intersecting Rqn 18^2 line at 
IOUT = 200 mA. 

2. This load line intersects the IqliT at loUT " 
710 mA and is tangent to PpA — 0.9W curve, thus 
Rla — 5V/710 mA = 1 AQ. will guarantee both 
Pda ^ 0.9W and loUTA ^ 200 mA. 

Section B 

1. Draw a load line intersecting RqN ' line at 

•out “ 100 

2. Similar to (2) above, it is seen .immediately that 
RLB ^ 5V/150 mA - 33.312 will guarantee lODTB ^ 
100 mAand PdB<0.18W. 


Since Pqa + ^DB < 0.9 + 0.18 < 1 .14W 

RLA = 7.112 
RLB = 33.312 

satisfy all the requirements in this problem. 

The design in Example 2 illustrated the simple and 
straight-forward use of the curves and the result 
meets all the problem requirements. However, it 
should be noted that there is not much design margin 
left for tolerance in resistances and other circuit 
parameters. The reason is obvious— we are pushing at 
the power limit of the MM74C908 package— and the 
solutions are sinnple: 

a) Increase Vqq supply 

b) Use the higher power package MM74C918. 

The design for higher Vqc 's identical to that in 
Example 2 and will not be repeated here. 

For the 14-lead higher power (2.27W) MI\/174C918, 
= 55°C/W, this is exactly half that of the 8-lead 
MM74C908. Therefore, by scaling the IqUT by 
a factor of 2, the same family of curves in Figure 9 
can be applied directly. This is shown in Figure 10. 
(Note that the slope of the Rqn = 1812 line has been 
adjusted to the new scale). 


2000 
1900 
1800 
1700 
1600 
1500 
1400 
1300 
1200 

5 1100 
3 

1000 
900. 

800 
700 
600 
500 
400 
300 
200 
100 
0 

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 

Vcc-VqutI'') TL/F/6025-10 

FIGURE 10 



Ta= 107 C 
Ta=,117'C- 
Ta= 125"C 
Ta= 130"C' 
Ta = 135"C- 
Ta= 140 C 


2-46 




By drawing the same load lines, it is found that: 

RLA- 5V/710mA= 1 
guarantees PpA ^ 0.9W 


and 


RlB = 5V/150 mA = 33.3^2 
guarantees Pdb ^ 0.1 8W 

Pda + Pdb < i -OBW 

which is way below the maximum power 2.27W 
available. Therefore, both R|_a and Rlb can be 
lowered to account for tolerance in the resistors. Con- 
sider specifically the following example: 

Example 3 

Assume driver A, B of the MM74C918 have to deliver 
250 mA and 150 mA, respectively, to its load. Design 
RLA and Rlb at Vcc - Vl = lOV. 

Driver A 

1. In Figure 11 , draw the load line intersecting RqN “ 
1812 at loUT = ’250 mA. 

2. This load line intersects the IquT axis at 450 mA. 
Thus, by inspection RlA — 10V/450 mA = 22.20 
guarantees PpA < 1.14W. 

Driver B 

1. Draw the load line intersecting Rqn 180 at 
lOUT ~ 180 mA. 

2. This load line intersects the IqLIT axis at 210 mA. 
Thus, by inspection RlB — 10V/210 mA = 47.60 
guarantees Pps < 0.4W. 


Since Pqa + PdB < 1-14 + 0.4 = 1.8W, while the 
package is capable of delivering 2.27W, both Rla 
and Rlb can be lower than the above values and 
the circuit still operates safely. By picking the closest 
standard resistance values: 

Rla = 200 
Rlb “ 430 

For 5% tolerance in these values, 

190 < Rla <210 
40:850 < Rlb <45.150 


Thus: 

«OUTA(IVIIN)> 

l0UTB(MIN)> 
PdA(MAX)< (- 


10V 


180 + 210 


-= 256.4 mA > 250 mA 


10V 


180 + 45.1.50 
10V \ 2 


-= 158.3 mA> 150 mA 


r)' 


180 + 190/ 

10V \ 2 


180 = 1.31W 


52W 


/ luv \ ^ 

PDB(IVIAX) < * 18^ = 9-' 

\1 80 + 40.850 / 


PdA(MAX) + PdB(MAX) < 1 .31 + 0.52 < 2.27W 
Therefore: 

Rla = 20O-(1.5W, 5%) 

Rlb = 430 (IW, 5%) 

will guarantee satisfactory performance of the circuit. 



6 7 8 

Vcc “ Vqut (V) 
FIGURE 11 


14 15 

TL;F/6025-11 


2-47 


AN-177 



AN-177 


APPLICATIONS 


Like most other drivers, the MM74C908, MM74C918 
can be used to drive relays, lamps, speakers, etc. These 
are shown in Figure 12. (To suppress transient spikes at 
turn-off, a diode as shown as Figure 12a is recommended 
at the relay coil or any other inductive load.) 


15V, power dissipation per package is typically 750 nW 
when the outputs are not drawing current. Thus, the 
drivers can be sitting out on line (a telephone line, for 
example) drawing essentially zero current until acti- 
vated— an ideal feature for many applications. 


However, the MIV174C908, MM74C918 offers a unique 
CMOS feature that is not available in drivers from other 
logic families— extremely low standby power. At Vcc “ 


yhe dual feature and the NAND function of the driver 
clesign can also be used to advantage as shown in the 
following applications: 




FIGURE 12b. Lamp Driver 



2-48 




In Figure 13, the 2 drivers in the package are connected 
as a Schmitt trigger oscillator, where R1 and R2 are used 
to generate hysteresis. R3 and C are the inverting feed- 
back timing elements and R4 is the pull-down load for 
the first driver. Because of its current capability, the 


circuit can be used to drive an array of LEDs or lamps. 
If resistor R4 is replaced by an LED (plus a current 
limiting resistor), the circuit becomes a double flasher 
with the 2 LEDs flashing out of phase. This is shown in 
Figure 14. 






AN-177 


Another oscillator circuit using only 1/2 of the package 
and 4 passive components is shown in Figure 15. Assume 
V| is slightly below the input trip point/ the driver is 
"ON” and charging both Vq and V| until V| reaches the 
trip point, Vj, when the driver starts to turn "OFF". 
Vq can be made much higher than V| at this instance by 
adjusting the component values such that RfCf » 
(RONIIRl^Cl- Since Vq is higher than V|, V| is still 
going up, although the driver is "OFF" and Vq is 
ramping down. The rising V| will eventually equal to 


the falling Vq, and then start discharging. Then, both 
V| and Vq discharge until V| hits the trip point, Vj, 
again, when the driver is turned "ON", charging up Vq 
and subsequently V| to complete a cycle. 


This oscillator is ideal for low cost applications like the 
1 -package siren shown in Figure 16, where 1 oscillator 
is used as a VCO while the other is generating the voltage 
ramp to vary the frequency at the VCO output. 


Vcc = 10V 



(a) 



FIGURE 15. Single Driver Oscillator 


Vcc = 10V 



2-50 









AN-248 


Electrostatic Discharge 
Prevention — Input Protection 
Circuits and Handling Guide 
for CMOS Devices 

Introduction 

During the past few years, there have been significant 
increase in the usage of low-power CMOS devices in 
system designs. This has resulted in more stringent at- 
tention to handling techniques of these devices, due to 
their static sensitivity, than ever before. 

All CMOS devices, which are composed of complementary 
pairs of n- and p-channel MOSFETs, are susceptible to 
damage by the discharge of electrostatic energy between 
any two pins. This sensitivity to static charge is due to the 
fact that gate input capacitance (5 picofarads typical) in 
parallel with an extremely high input resistance (10''2ohms 
typical) lends itself to a high input impedance and hence 
readily builds up the electrostatic charges, unless proper 
precautionary measures are taken. This voltage build-up on 
the gate can easily break down the thin (1000 A) gate oxide 
insulator beneath the gate metal. Local defects such as 
pinholes or lattice defects of gate oxide can substantially 
reduce the dielectric strength from a breakdown field of 
8-10 X 10®V/cm to 3-4 x 10®V/cm. This then becomes the 
limiting factor on how much voltage can be applied safely 
to the gates of CMOS devices. 

When a higher voltage, resulting from a static discharge, 
is applied to the device, permanent damage like a short to 
substrate, Vqd pin, Vss pin, or output can occur. Now 
static electricity is always present in any manufacturing 
environment. It is generated whenever two different mate- 
rials are rubbed together. A person walking across a pro- 
duction floor can generate a charge of thousands of volts. 
A person working at a bench, sliding around on a stool or 
rubbing his arms on the work bench can develop a high 
static potential. Table I shows the results of work done by 
Speakman'' on various static potentials developed in a 
common environment. The ambient relative humidity, of 
course, has a great effect on the amount of static charge 
developed, as moisture tends to provide a leakage path to 
ground and helps reduce the static charge accumulation. 


TABLE I. Various Voltages Generated in 15%-30% 
Relative Humidity (after Speakman^) 

Most Common Highest 


Condition 

Reading 

(Volts) 

Reading 

(Volts) 

Person walking across 
carpet 

12,000 

39,000 

Person walking across 
vinyl floor 

4,000 

13,000 

Person working at bench 

500 

3,000 

16-lead DIPs in plastic 
box 

3,500 

12,000 

16-lead DIPs in plastic 
shipping tube 

500 

3,000 


National Semiconductor 
Application Note 248 
Vivek Kulkarni 
June 1980 


Standard Input Protection Networks 

In order to protect the gate oxide against moderate levels 
of electrostatic discharge, protective networks are pro- 
vided on all National CMOS devices, as described below. 

Figure 1 shows the standard protection circuit used on 
all A, B, and 74C series CMOS devices. The series resis- 
tance of 200 ohms using a P'*' diffusion helps limit the 
current when the input is subjected to a high-voltage 
zap. Associated with this resistance is a distributed 
diode network to Vqd which protects against positive 
transients. An additional diode to Vss helps to shunt 
negative surges by forward conduction. Development 
work is currently being done at National on various 
other input protection schemes. 



Figure 1. Standard Input Protection Network 


Other Protective Networks 

Figure 2 shows the modified protective network for 
CD4049/4050 buffer. The input diode to Vdd is deleted 
here so that level shifting can be achieved where inputs 
are higher than Vqd- 



Figure 2. Protective Network for CD4049/50 
and MM74C901/2 

Figure 3 shows a transmission gate with the intrinsic 
diode protection. No additional series resistors are used 
so the on resistance of the transmission gate is not af- 
fected. 

All CMOS circuits from National’s CD4000 Series and 
74C Series meet MILtSTD- 38510 zap test requirements 
of 400 volts from a lOOpF charging capacitor and 1.5kQ 
series resistance. This human body simulated model of 



2-52 




? GATE (P-CHANNEU 



DIODE BREAKDOWN 
02 = 60 VOLTS 
D, = 25 VOLTS 

•THESE ARE INTRINSIC DIODES 

^ GATE (N-CHANNEL) 

Figure 3. Transmission Gate with Intrinsic Diodes to 
Protect Against Static Discharge 


100 pF capacitance in series with 1 .5 kQ series resistance 
was proposed by Lenzlinger^ and has been widely ac- 
cepted by the industry. The set-up used to perform the 
zap test i's shown in Figure 4. 


V 2 AP is applied to DUT in the foiiowing modes by charg- 
ing the 100 pF capacitor to V 2 ap with the switch Si in 
position 1 and then switching to position 2, thus 
discharging the charge through 1.5 kf2 series resistance 
into the device under test. Tabie li shows the various 
modes used fortesting. 


TABLE II. Modes of High-Voltage Test 


Mode 

■f Terminal 

-Terminal 

1 

Input 

Vss 

2 

Vdd 

Input 

3 

Input 

Associated Output 

4 

Associated Output 

Input 


Pre- and post-zap performance is monitored on the input 
leakage parameter at Vdq = 18 Volts. It has been found 
that all National’s CMOS devices of CD4000 and 74C 
families can withstand 400 volts zap testing with above 
mentioned conditions and stiil be under the pre- and 
post-zap input leakage conditions of ±10nA. 

Handling Guide for CMOS Devices 

From Tabie I, it is apparent that extremely high static 
voltages generated in a manufacturing environment can 
destroy even the optimally protected devices by reaching 
tfieir threshold failure energy levels. For preventing such 
catastrophies, simple precautions taken could save 
thousands of dollars for both the manufacturer and the 
user. 

In handling unmounted chips, care should be taken to 
avoid differences in voltage potential between pins. Con- 
ductive carriers such as conductive foams or conduc- 
tive rails should be used in transporting devices. The- 
following simple precautions should also be observed. 

1. Soldering-iron tips, metal parts of fixtures and tools, 
and handling facilities should be grounded. 

2. Devices should not be inserted into or removed from 
circuits with the power on because transient voltages 
may cause permanent damage. 

3. Table tops should be covered with grounded conduc- 
tive tops. Also test areas should have conductive floor 
mats. 


Si 

10M 12 Rs = 1.5k 



S, =H9 - WETTED ■‘B0UNCELESS''RELAY 


Figure 4. Equivalent RC Network to Simulate Human 
Body Static Discharge (After Lenzlinger^) 

Above all, there should be static awareness amongst all 
personnel involved who handle CMOS devices or the 
sub-assembly boards. Automated feed mechanisms for 
testing of devices, for example, must be insulated from 
the device under test at the point where devices are 
connected to the test set. This is necessary as the trans- 
port path of devices can generate very high levels of 
static electricity due to continuous sliding of devices. 
Proper grounding of equipment or presence of ionized- 
air blowers can eliminate all these problems. 

At National all CMOS devices are handled using all the 
precautions described above. The devices are also trans- 
ported in anti-static rails or conductive foams. Anti- 
static, by definition^ means a container which resists 
generation of triboelectric charge (frictionally generated) 
as the device is inserted into, removed from, or allowed 
to slide around in it. It must be emphasized here that 
packaging problems will not be solved merely by using 
anti-static rails or containers as they do not necessarily 
shield devices from external static fields, such as those 
generated by a charged person. Commercially available 
static shielding bags, such as 3M company’s low resis- 
tivity (< 10“^ ohms/sq.) metallic coated polyester bags, 
will help prevent damages due to external stray fields. 
These bags work on the well-known Faraday cage 
principle. Other commercially available materials are 
Legge company’s conductive wrist straps, conductive 
floor coating, and various other grounding straps which 
help prevent against the electrostatic damage by pro- 
viding conductive paths for the generated charge and 
equipotential surfaces. 

It can be concluded that electrostatic discharge preven- 
tion is achievable with simple awareness and careful 
handlirig of CMOS devices. This will mean wide and 
useful applications of CMOS in system designs. 


Footnotes 

1. T.S. Speakman, “A Model for the Failure of Bipolar 
Silicon Integrated Circuits Subjected to ESD,” 12th 
Annual Proc. of Reliability Physics, 1974. 

2. M. Lenziinger, “Gate Protection of MIS Devices,’’ IEEE 
Transac. on Electron Devices, ED-18, No. 4, April 1971. 

3. J.R. Huntsman, D.M. Yenni, G. Mueller, “Fundamental 
Requirements for Static Protective Containers.’’ Pre- 
sented at 1980 Nepcon/West Conference, Application 
Note — 3M Static Control Systems. 




2-53 


AN-248 




AN-249 


MM54240 Asynchronous 
Receiver/Transmitter Remote 
Controller Applications 


National Semiconductor 
Application Note 249 
J. Hong 
May 1980 



Introduction 

The MM5420 Asynchronous Receiver/Transmitter Remote 
Controller is a low cost, easy-to-use circuit for serial data 
transmission applications. The'circuit is fabricated' in 
the N-channel metal gate process which gives it a wide 
supply voltage range (Vdd = 4.75V- 1 1 .50V) and TTL com- 
patibility. 

A typical application would consist of an information 
handling center and up to 128 information gathering and 
information suppiying stations. The information handling 
center would be composed of one MM54240 circuit inter- 
faced to a microprocessor I/O system. The MM54240 in 
this instance is called the “master” circuit. An infor- 
mation gathering and supplying station would be one 
MM54240 interfaced to a A-to-D converter/D-to-A conver- 
ter system or a digital peripheral system or any informa- 
tion source/destination. The MM54240 in this instance 
is the “slave” circuit. 

The simpiest way to interface such a system is by means 
of a twisted pair or a coaxial cable. A pull-up resistor is 
necessary on this communication line since the circuit 
drivers are open drain outputs. Care should be taken to 
reduce capacitance and resistance on this line. With the 
use of pulse width modulation techniques, frequency 


tolerance between the circuits is broadened. This 
feature is extremely desirable since the need for an ex- 
pensive crystal controlled oscillator or ceramic resonator 
is eliminated. Furthermore, critical timing schemes with 
start and stop bits are not used. In addition, a debounce 
circuit is incorporated which contributes greatly to the 
noise immunity feature of the circuit. 

Circuit Description 

A functional block diagram of the MM54240 is shown in 
Figure 2. The Control Logic section consists of the 
switching functions of the circuit. The PWM encoder/de- 
coder encodes and decodes the pulse width modulation 
data format. The Shift Registers store and shift the data. 

Temperature Control and Security 
Application 

The MM54240 can be used in many different types of low 
to medium speed processor controlled applications. For 
a system with 128 “slave” circuits, the time that it takes 
to interrogate all “slave” circuits can range from 1 to 2.5 
seconds depending on the oscillator frequency of each 
individual circuit. 



• • 


Figure 1. Typical System Block Diagram 


2-54 




The following example illustrates a possible in-the 
home use of such a system. A set of MM54240 circuits 
are used for controlling the temperature of the various 
rooms inside the house, the security of the windows and 
entrances, and also for turning the lights on and off when 
certain events take place. The processor controlling the 
system is a COP421L and it is directly interfaced to the 
MM54240 “master” circuit. Three address inputs of the 
“master” circuit are not used and they are tied directly 
to the power supply. A maximum of 16 “slave” circuits 
are then possible. They will start with address 112 and 
go up to 127. The “master” circuit has the Data I/O ports 
interfaced to the L I/O ports, the Address inputs inter- 
faced to the D I/O ports, and the Control inputs interfaced 
to the G output ports of the COP421 L. The Mode input is 
tied to Vdd to select “master” operation and the only ex- 
ternal components are the R-C’s connected to each cir- 
cuit. The power supply terminals are shared between 
the two circuits. 

The heating system of the house consists of a furnace 
with a multi-speed air blower. A thermocouple thermo- 
meter installed' in each room supplies the temperature 
information to the processor. The amount of air flowing 
into a room is controlled by a variable ventilation 
grating. When the temperature of the room falls, the 
ventilator opens further to let in increasing amounts of 
warm air. When all the rooms are sufficiently heated, 
the furnace is turned off. The temperature in different 
rooms may not be the same since the processor can 
control and adjust them to a programmed setting. 

The first “slave” circuit has hard-wired address 112 and 
it is used for furnace control. The control (C-|, C2) inputs 


are set up for (0,1) the low impedance output port selec- 
tion. D-i of the D outputs is used for furnace ignition. The 
other D outputs are used for controlling the air blower’s 
variable speed. The second “slave” circuit has hard- 
wired address 113 and it is used for temperature sensing 
and ventilation opening control. The control (C-|, C2) in- 
puts are set up for (0,0) 4 in/4 out selection. D1-D4 are 
low impedance output ports for controlling the ventilator 
opening; D5-D8 are high impedance input ports for re- 
ceiving temperature information from the thermocouple. 

The third “slave” circuit has hard-wired address 1 14 and 
it is used for security purposes. The control (Ci, C 2 ) in- 
puts are set up for (1,0) the weak pull-up option. The pro- 
cessor will have to initialize the output latches by loading 
logic ones into them. The De I/O port is for Arming and 
Disarming the alarms. This is accomplished by a locking 
switch shorting the I/O port to Vss when armed. The D1-D5 
I/O ports are connected to doors and windows. When 
they are shut, the I/O ports are shorted to Vss- When a 
window or door is opened, the voltage level of that I/O 
port will increase. When the COP421L processor detects 
this change, it will enable the alarm at the Ds I/O port 
and turn the light on at the D7 I/O port. The processor 
can also be programmed to turn the light — D7 I/O port 
— on when one or certain doors are open. 

The second and third “slave” circuit cohfigurations can 
be duplicated for other rooms. Each “slave” circuit has 
an optional clear switch in case the processor circuit 
fails and the “slave” circuit outputs have to be over- 
ridden. 


ADDRESS INPUT 


DATA I/D 


LATCHES 


CDIVIPARATOR 





ADDRESS 


DATA 

r 

SHIFT REGISTER 


SHIFT REGISTER 

1 



CLDCK 

GENERATOR 


PWM 

ENCODER/ 

DECODER 



Figure 2. Circuit Functional Block Diagram 


2 


2-55 


AN-249 




AN-249 



TL/B/7396-3 


Figure 3. Temperature Control and Security Application 





Power Line Transmission 

A MM54240 system can be interfaced using other tech- 
niques. The pulse width modulated information can be 
transmitted by carriers like Radio Frequency, infra-red 
waves, pov;er line transmission or any other suitable 


POWER LINE 110V 

TRANSMISSION 60 Hz 

INTERFACE AC 



M 

TL/B/7396-4 

Figure 4. Power Line Transmission Application 


medium. For power line transmission applications, an 
interfacing circuit is used to modulate the information 
on the 60 Hz AC lines. For the “master” circuit, the pro- 
cessor must generate a signal to control the direction of 
transmission of the interface circuit. For the “slave” 
circuit, the chip select (CS) output is designed for this 
purpose and can be used directly to control the direction 
of transmission of the interface circuit. 

Radio Frequency Transmission 

A Radio Frequency transmission system can be built in 
a similar structure. An I/O multiplexing circuit has to be 
designed to direct the flow of the transmitted data. 

Conclusion 

The MM54240 is a flexible, easy-to-use, and adaptable cir- 
cuit. It can be used in any application where a serial data 
transmission is desired. The transmitted data is pulse 
width modulated. This gives it desirable features such as 
a low cost oscillator, wide frequency tolerance, and ex- 
cellent noise immunity. Up to 129 MM54240 circuits can be 
used for any one system. The circuit is fabricated in the 
N-channel metal gate process. Designed with National’s 
Microbus™ structure in mind, the circuit is easily and 
directly interfaced to most microprocessor systems. 



TL;B/7396-5 


Figure 5. Radio Frequency Transmission Application 



2-57 


AN-249 




AN-250 


Applications and Uses of 
the MM5321 TV Camera 
Sync Generator 


National Semiconductor 
Application Note 250 
Edwin Schoell 
May 1980 



1. Introduction 

The MM5321 has been introduced to replace the older 
MM5320 and correct some difficulties associated with that 
part. It is a plug-in replacement in almost all applications. 

Major Differences and Improvements are: 

■ Horizontal reset control allows resetting to beginning or 
center of horizontal line. 

■ Vertical (field) index pulse with both 1 .26 and 2.045 MHz 
clock. 

■ Improved clocking characteristics. 

■ Vertical interval always generated after vertical reset 
pulse at pin 5. 

■ Vertical sync separator included. 

Power Supplies 

The MM5321 is designed to operate from a total supply 
voltage of 17 volts, or various combinations to supply a 
total of 17 volts. Interfacing to TTL or CMOS is best ac- 


complished using -f5V and -12V as shown in Figure 1. 
Note that no ground is needed for the MM5321, but it is 
used as the power return for peripheral chips. 

Input Interfacing 

Since the MM5321 is a P-channel device, input switching 
thresholds are with respect to the most positive (Vss) 
power supply voltage. For this reason, it is important to 
use the same regulators, or insure the 5V supply to the 
driver chip is the same as the 5V supply to the MM5321. 
Problems with poor clocking can often be traced to drive 
levels not coming to within 1.5 volts of the 5V supply to 
the MM5321 . In some cases, the addition of a 470Q pull-up 
resistor from clock input to Vss will solve the problem. 

Input clocking problems have also been found with low 
duty cycle waveforms of the 2.048 MHz clock. A look at 
the data sheet will reveal that a 50 percent duty cycle is 
best, but 3 to 4 on/off (43%-57%) ratio is satisfactory. 
This can be obtained from a properly configured divide 
by seven counter from a 14.31818 MHz clock. 


5V Vss 



CMOS INTERFACE 
- NOT USED FOR TTL 


Vss = 5V 



LIMIT 


INPUT LOGIC LEVELS 


Figure 1. Input/Output Interfacing 


2-58 




Two schemes for driving the MM5321 are shown in 
Figure 2. The first shows a CMOS gate oscillator/buffer, 
while the second uses a transistor crystal oscillator and 
a TTL up-counter programmed to divide by seven and 
produce a 3 to 4 on/off ratio for the MM5321 clock input. 
In color applications the 14.32 MHz is also divided by four 
in a shift register type of counter to produce quadrature 
3.58'MHz for the systems chroma modulators. 

All other inputs should be tied high or low depending on 
the application of the part, with the exception of the hori- 
zontal reset, which is internally pulled down to Vqg- 

Output Interfacing 

The MM5321 will drive 1 TTL load when operated with 
+ 5V and -12V supplies as shown in Figure 1. The output 
structure is an active device to Vss and a current source 
load to Vqd, Figure 3. When interfacing to CMOS, a 
27 kQ current limit resistor must be used to prevent 
damage to the CMOS inputs when the protection diode is 
turned “on”. 


2. Some Applications 

The most basic application of the MM5321 is a TV 
camera sync generator, where it will generate all the 
usual drive signals as well as high quality composite 
sync. In this application, little interfacing is needed. 


Genlocking 

In some systems, it is necessary to lock the sync genera- 
tor to another source of sync. This is commonly done by a 
process called “genlocking” in which the two generators 
are either fed from the same master (2.045 MHz) clock, or 
the crystal oscillator of one generator is phase-locked to 
vertical or horizontal sync of the master generator. 

The vertical divider may be reset either by feeding com- 
posite sync to the vertical reset control, or by feeding 
differentiated (short pulses) of vertical sync to the verti- 
cal reset pin of the MM5321. 



5V 

+ 5V I 1 I 



TL/F/6162-2 


Figure 2. Input Clock Generating Schemes 


4 ^ 


Vss 

-i- 


INTERNAL 

CIRCUITS 






vdd 


Figure 3. MM5321 Input/Output Circuits 


Z 


2-59 


1-250 




AN-250 


Figure 4 shows a genlock application. External hori- 
zontal sync is used as a reference to a phase detector 
which compares to the horizontal sync generated by the 
MM5321. The error signal controls the clock to the 
MM5321. In order to insure exact horizontal and vertical 
timing, external composite sync is fed to the Vertical 
Reset Control of the MM5321. Circuitry inside the 
MM5321 decodes the vertical interval of the external 
sync generating a vertical sync pulse to reset the verti- 
cal counter of the MM5321. In effect then, this input 
acts as a vertical sync separator. 

A disadvantage of this approach is that there is a one field 
delay between the source and the MM5321, so that serra- 
tion pulses of the slave will begin one half line earlier than 
that of the source. 

A more precise genlock application is shown in Figure 5. 
Phase locking is done at 3.58 MHz, vertical Is reset with 
the leading edge of a vertical sync pulse derived from 
incoming video with the vertical control of the MM5321 


resetting to the eleventh half line of generated sync. 
Composite sync resets the horizontal divider chain for 
clock periods before horizontal sync resulting in a fus 
delay between master and slave. Horizontal drive may 
be used to reset the horizontal counter to within one 
clock period or 0.5f^s of master sync. In order not to 
produce double frequency horizontal drive during the 
vertical interval, horizontal sync from the master is 
gated with vertical drive from the slave. 

It should be noted in the above application that if the 
phase lock were omitted, and the 2.048 MHz OSC were 
allowed to free run, the MM5321 would still maintain 
vertical and horizontal lock with the source. However, 
timing errors will build up with time and since the 
counters in the MM5321 can only be reset in 1 divided by 
2.045MHz or 500ns intervals, the effect will be to shift 
the position of horizontal sync 500 ns (1% of 1 horizon- 
tal line) every few lines depending on how far apart the 
two clock sources are. 


COMPOSITE 

SYNC 



Figure 4. Genlocking 



COMPOSITE 

SYNC 

HORIZ 

DRIVE 


ETC. 


TL/F/6152 5 


Figure 5. Geniocking with Color-Burst Phaselock 


2-60 




As an example, assuming a 0.1 % error in clock frequen- 
cy, after 1000 clock cycles, the error between clocks will 
be 1 clock cycle or 489 ns and the horizontal counter will 
reset one line earlier. 1000 clock cycles occur in AS9ns, 
or once every 7.7 horizontal lines. 

The effect will be a sawtooth appearance on a vertical 
line displayed on a display. 

3. PAL and Other Non-Standard 
Applications 

The MM5321 may be used with some external circuitry 
ito generate approximately correct PAL sync. By using 
the vertical control on the even line after 50 Horizontal 
lines are counted, the divide by 525 is reset to bVz lines 
from zero. The field reference is slightly reduced to give 
horizontal rate of 50 Hz. It can be seen that for 819 lines, 
147 and 152 extra pulses are needed. 

Figure 6 shows a realizable circuit, the MM5321 provides 
all the necessary wave forms as in the 525 lines case. A 
divide by two provides odd and even field identification. 
A programmable counter is toggled at half field rate be- 
tween the counts of 50 and 55; The MM5321 is reset at 
these times, the combinational logic around the 74C93 
is toggled to detect alternately the 10th and 11th counts. 


1.25 MHz 


The ensure reliable reset of the 74C93 counter an extra 
delay was provided by a 74C14 inverter. The vertical drive 
sets an R-S flip flop at 0 time. The divide by 10/divide by 
11 counter is enabled to count five, ten, or eleven 
pulses, the R-S flip flop is reset by the output of the divide 
by 5 counter. 

The circuit now awaits the next vertical blanking pulse. 

Specifications 


Line Period 
Line Blanketing 
Front Porch 
Horizontal Pulse 
Back Porch 
Burst 
Field 

Duration of Field Sequence 
Field Blank. Int. 

No. of Serrations 


64jjs 
11.2ms 
1 .6ms 
4.8ms 
4.8ms 
2.4ms 
50Hz/312 = 313 
91 H 
21 H lines 
6 


In conclusion it can be seen that this sync generator 
does not exactly conform with CCIR specs. However, 
there should be a few applications where these wave- 
forms would be ample. 


50 pF:^ 



— I>o-|>o— ' 


V274C04 





8 

11 

1 

MM5321 - 
2 6 

16 

t 

15 

j 



CMOS SUPPLIES ARE -f12V AND OV 


Figure 6. PAL Application 


2-61 


AN-250 




AN-251 


A Broadcast Quality TV Sync 
Generator Made Economical 
through LSI 


National Semiconductor 
Application Note 251 
Robert B. Johnson and 
Eugene H. Campbell 
May 1980 



The growing number of applications of video tape recor- 
ders and TV cameras in the consumer market have re- 
sulted in the need for a single-chip LSI integrated circuit 
TV camera sync generator. The National Semiconductor 
MM5321 TV Camera Sync Generator has been developed 
to economically provide the basic sync functions for 
color and monochrome, 525 line, 60 Hz, interlaced appli- 
cations — and provide it with the reliability and accuracy 
of a digital 1C system. A Metal-Oxide-Semiconductor 
(MOS) technology was chosen as the most economical 
method of obtaining the necessary circuit density and 
speed. 

Figure 1 shows the simplified block diagram and Figures 
2 through 5 are the timing diagrams of the generator. 

All inputs and outputs of the 14-pin device are TTL com- 
patible without the use of external components. Two 
supplies are required, with the nominal difference be- 
tween them 17 volts. Ambient temperature may be varied 
between -25°Cand -f-70°C. 

The output functions provided are Horizontal Drive, Ver- 
ticai Drive, Composite Blanking, Composite Sync, and 
Color Burst Gate. In addition, a Fieid Index output func- 
tion identifies a particular field, and a Color Burst Sync 
output presents a pulse at half the horizontal rate, but 
otherwise identical to the Color Burst Gate, and may be 
used to synchronize the color burst with the generator. 


All output functions are derived from the clock applied 
to the Master Clock input. The user may select either of 
two input frequencies by selecting the proper horizontal 
divider, which is accomplished by hard-wiring the Divider 
Control pin to either the Vss (most positive) or Vqg (most 
negative) power supply. 

In color applications, a frequency four times the color 
burst is usually available to generate the 0°C and 90°C 
color sub-carrier signais. Dividing that frequency by 
seven results in 2.04545MHz, which is the input ciock 
signai to be used when the Divider Control pin is con- 
nected to Vss- With the control pin wired to Vqg. the hori- 
zontal divider is programmed to accept an input signai 
eighty times.the horizontal rate, or 1.260 MHz. 

The horizontal divider is essentialiy a 65-bit shift register 
which can be shortened to 40-bits with the Divider Con- 
trol logic. Control logic also selects the proper set of 
register taps used for decoding the horizontal timing 
edges. 

One of the outputs of the horizontal divider is a signal 
used to drive the ten-stage vertical counter and a 42-bit 
shift register, which together provide the vericai division 
and timing edges. 

Shift registers are usually very efficient logic blocks in 
MOS designs, which is why they were selected for many 
of the counters in this product. Parasitic capacitances 
may be used to store charge for periods of time that are 


HORIZONTAL 

RESET 


CLOCK 

INPUT 


DIVIDER 

CONTROL 


RESET 

CONTROL 


VERTICAL 

RESET 



Figure 1. Block Diagram of a TV Camera Sync Generator TL/F/6153-1 


Fabricated with MOS/LSi Techniques 


2-62 




essentially dependent only on semiconductor junction 
characteristics. Thus, in MOS it is possible to design 
both dynamic and static shift registers. Dynamic regis- 
ters were used for both the vertical and horizontal 
counters because in each case the clock frequency is 
well above any minimum limitation due to leakage cur- 
rent 'considerations, and they offer a layout/size advan- 
tage over static type cells. The configuration selected 


uses ten transistors and is capable of being reset to 
either a “’1” or “0” logic state. 

The vertical divider is comprised of DC flip-flops config- 
ured as a ten-stage short-cycled, modulus 525, ripple 
counter. Each stage is resettable, and to accommodate 
additional vertical reset versatility, stages 1, 2, and 8 
can be set or reset. 




Figure 2. Sync Generator Output Waveforms 


2,94545MHz “ i3'8 

"fss; winnnjuuuijmruijmnjmnnnnnji^^ 




_ SERRATION GATE _ 
9 Ta > 0.870H 


FRONT PORCH _ 
3 Ta = 0.023H 


EQUALIZATION 

. GATE • 

5Ta = 0 0386H 


_ HORIZONTAL SYNC_ 
10 Ta = 0.0774H 


_ HORIZONTAL DRIVE _ 
13 Ta = 0.101H 


HORIZONTAL BLANKING _ 
22 Ta = 0 170H 



- — COLOR — 

BURST GATE • 


5 Ta = 0 0386 



TUF/6153-3 

Figure 3. Horizontal Timing Diagram with the Input 
Clock Frequency Equal to 2.04545 MHz 


Z 


2-63 


1-251 




AN-251 



k- HORIZONTAL— 

I SYNC ' 



HORIZONTAL DRIVE BACK PORCH 

8Tb = 0.1H I 6TbS>- 0.075H | 




TL/F/G153-4 


Figure 4. Horizontal Timing Diagram with the Input 
Clock Equal to 1.260 MHz 










Figure 6. Simplified Vertical Timing Logic 


Figure 6 indicates the method of generating the vertical 
output functions. Decoding logic detects the 525th state 
and short cycles the counter by resetting it to zero. Sim- 
ultaneously, the input of the 42-bit shift register is set to 
zero and the vertical blanking and equalization gates are 
initiated. Six register clock periods later, the equalization 
gate is terminated and the serration pulse is initiated by 
the arrival of a zero state at the sixth bit of the shift reg- 
ister. Similarly, the serration gate is terminated and the 
equalization gate reinitiated when a zero is detected at 
the 12th tap and, finally, the equalization gate is termin- 
ated when the 18th tap changes to a zero. The vertical 
drive pulse is also initiated when the register input goes 
to a zero, and is terminated when the zero reaches the 
18th bit. The vertical blanking pulse lasts until the zero 
propagates to the 42nd bit, at which time the register 
input is reset to a logical “1” level. 

In some applications, particularly video recorder tape 
editing, it is necessary to identify which field of the ver- 
tical frame the system is in. For that purpose, the gener- 
ator derives a Field Index pulse which identified field 
one by occurring for two input clock periods at the lead- 
ing edge of thewertical blanking pulse of field one. Field 
one is defined as the field with a whole scanning line in- 
terval between the equalizing pulse and the last line sync 
pulse of the preceding field. * 

When designing MOS circuits, one must be aware of the 
effects of power supply variations, ambient temperature 
excursions, and process variables on circuit performance. 
This is the case in design of most circuits of course, but 
MOS tends to be more sensitive than bipolar circuits 
due to increased parasitic capacitance and limited cur- 
rent drive capabilities. The speed of any MOS product is 
essentially dependent upon how fast critical capacitive 
nodes can be charged and discharged. The charging or 
discharging current is in turn a function of the size, the 
voltages applied to, and the threshold and gain factor of 
the transistor(s) supplying the current. Threshold and 
gain factor are functions of process variables such as 
gate oxide thickness, the type of substrate material and 


its impurity concentration. They are also affected by 
temperature, which reduce the fermi potential (decreas- 
ing threshold), and modifies the carrier mobility in the 
transistor channel (which lowers the gain factor), the re- 
^duction in gain factor generally has more effect than the 
change in threshold, resulting in an overall reduction in 
speed with increasing temperature. 

As far as the sync generator is concerned, this variation 
in performance as a function of environmental and power 
supply conditions could cause skewing of individual 
output timing edges, reducing the accuracy of the sync 
functions. Careful design essentially eliminates this 
problem in the MM5321. First, all output functions were 
matched for total logic delay by simulating circuit per- 
formance for all environmental and process variations, 
and then optimizing the delays to the output buffers. 
Second, all output functions are resynchronized at the 
outputs by an internal clock signal running at the input 
clock rate, with its own optimized delay characteristics 
with respect to the horizontal divider clock. For all 
worst-case conditions the output functions reach the 
synchronizing point before the synchronizing clock. 
Third, all the output buffers themselves are identical 
and therefore have matched delays. Thus, the design 
results in output functions whose timing delays are 
matched with respect to each other, but will have differ- 
ences in delay with respect to the input clock on a part 
to part basis (due to variations in process variables). 
Even on a part to part basis, maximum differences in 
delay between two parts with the maximum allowed pro- 
cess variation should be less than 200ns, or 0.003H, at 
similar temperature and power supply values. 

The output buffers are push-pull using the circuit confi- 
guration shown in Figure 7. The output transistors Q1 
and Q2 provide the sink and source characteristics 
shown in Figure 8. When' interfacing directly with TTL, 
the 800Q resistor serves to limit the excess sink current 
supplied to the TTL clamp diode, by reducing the gate 
drive to Q2. This minimizes excessive power dissipation 
on the chip and protects the TTL diode. Q8 is the logic 
transfer device driven by the synchronizing clock. 



2-65 


AN-251 




AN-251 



VOUT (VOLTS) TL/F/6153-8 


VouT (VOLTS) TL/F/6153-9 


Figure 8a. Typical Output Sink Current as a Function 
of Output Voltage 


Figure 8b. Typical Output Source Current as a Function 
of Output Voltage 


CLOCK 

INPUT 


INTERNAL INTERNAL 
Vgg clock CLOCK 



Vss TL/F/6153-10 


Figure 9. Schematic of Input Clock Buffer 


The most critical circuitry in the generator, from the 
■standpoint of speed, is the input clock buffer (Figure 9). 
The buffer is designed to generate a two-phase, full 
power supply amplitude clock signal from the single- 
phase low amplitude input signal. Q1 through Q4 con- 
stitute a Schmitt trigger type input stage that guarantees 
a trip-point range of Vss - 4.2V maximum for “0” levels, 
and Vss -2.0V minimum for TTL “1” levels. When 
interfacing directly with TTL, the normal supplies will be 


-(-5 volts connected to. Vss. and -12V connected to the 
Vqg pin. For a tolerance of 5% on the Vss supply, the 
guaranteed trip-points decipher to a required input level 
more negative than 4.75V-4.2V, or 0.55V, for the “0” level, 
and a required level more positive than 4.75V-2.0V, or 2.75, 
for the “1” level. These levels are obtainable from stan- 
dard TTL without any external interface components. 
Q10 and Q11 are feedback latches which eliminate in- 
ternal clock overlap problems. 


2-66 



VERTICAL 

RESET 

CONTROL 



TO VERTICAL 
DIVIDER 
RESET 
CIRCUITRY 


TL;F/6153-11 


Figure 10. Basic Logic for Detecting Proper State of the Composite Sync Input 
Signal for Resetting the Vertical Divider in “Gen-Lock” Operation 


To provide as much versatility as possible, a variety of 
divider reset (“gen-clock”) features have been included. 
The horizontal and vertical dividers have individual Ver- 
tical and Horizontal Reset inputs which allow independ- 
ent resetting of the appropriate divider. With the inputs 
tied together, both dividers may be reset simultaneously. 

The vertical divider may be reset to either of two states, 
depending upon the DC level of the Reset Control pin. If 
the Reset Control is tied to Vss, the most positive supply, 
a TTL “1” to the ”0” level transition on the Vertical Reset 
pin will reset the vertical divider to all zeros, which is 
time zero as defined by the vertical timing diagram. With 
the Reset Control returned to Vqg, a Vertical Reset 
pulse will reset the vertical divider to the fifth serration 
pulse (eleven 0.5H time intervals from time zero). This 
allows the reset pulse to be generated by analog detec- 
tion of a composite sync or video signal, and used to 
gen-lock the slave sync generator within the same field 
interval. The horizontal divider is always reset to zero, as 
defined by the horizontal timing diagram. 

The Field Index output pulse occurs once during each 
field one at time zero and last for two master clock peri- 
ods. it can be used to gen-lock similar sync generator 
chips by connecting it to their Vertical Reset inputs and 
wiring the Reset Control to the Vss supply. 

Another method of resetting the vertical divider is pro- 
vided by using the Reset Control pin as an input for a 
composite sync signal from which gen-locking is desired. 
The slaved generator detects the fifth serration pulse 
and resets the vertical divider to the proper state (Figure 
10 ). 

The reset control logic generates a two-phase clock with 
a frequency equal to the input clock rate anytime the 
composite sync input signal is more negative than the 
Reset Control trip-point. A 16-bit dynamic shift register 
with its input connected to Vss is driven by the modu- 
lated clock signal. When the composite sync input be- 
comes more positive than the Reset Control trip-point, 
or if the 16th bit becomes a “1”, all sixteen bits of the 


register are reset to zeros. If the composite sync signal 
remains low for fifteen master clock periods, another 
two-phase signal is generated which acts as the clock 
for a 5-bit shift register used to store the sampled state 
of the inverted (and filtered) composite sync signal. The 
sample is the average value of the filtered signal during 
an approximately 200ns sampling window occurring just 
before the fifteenth master clock time after the compo- 
site sync input signal initially went low. The input trip- 
point of the 5-bit register determines whether the sam- 
pled signal is stored as a “1” or “0” logic state. 

.Fifteen input clock periods equal a time of 7.3^3 at an 
input clock frequency of 2.04545MHz, and 11.9^3 when 
the input rate is 1.260MHz. The only interval of the com- 
posite sync waveform which is legitimately low during 
this time is the vertical sync pulse. In the present design, 
the first five serrated intervals must be successfully de- 
tected before the vertical divider is reset to the proper 
state. The limitation in this design may be the difficulty 
in acutally acquiring legitimate detection due to exces- 
sive noise and missing pulses in the composite sync 
input signal. If this proves to be the case, it is possible 
to eliminate the second and/or fourth bits of the 5-bit 
register as detection requirements. This should improve 
the statistical probability of getting an initial gen-lock 
condition within a reasonable time. 

As illustrated above, the Reset Control input has a dual 
function. It selects the reset state of the vertical divider 
when hardwired to either Vss or Vqg- and acts as a dyna- 
mic input when gen-locking is to be established using a 
composite sync input signal. When using the Reset 
Control as the input for a composite sync signal, the 
Vertical Reset pin should be hardwired to Vss- 

The MM5321 TV Sync Generator has been designed with 
both versatility and economy as the primary objectives. 
We feel it exemplifies the role of MOS/LSI standard 
products can play in providing useful consumer products 
in a manner that both large and small volume users will 
find attractive. 


2-67 


AN-251 




AN-257 


Simplified Multi-Digit LED SSio:N“°^ 

Display Design Using Larry wakeman 

MM74C911/MM74C912/ 

MM74C917 Display 
Controllers 



I. Introduction 

The MM74C911, MM74C912 and MM74C9127 are CMOS 
display controllers that control multiplexing of 
8-segment LED displays. These devices each have an 
on-chip multiplex oscillator and associated logic to 
easily implement multi-digit displays with minimal addi- 
tional hardware. These controllers were designed to be 
easily interfaced to a microprocessor as a small 4-or 
6-byte area of write-only memory (WOM), but they are 
not limited to this environment. 

The MM74C911 is the simplest of these devices. It has 
one data input for each of its eight segment outputs, 
allowing direct control of any LED segment. Both the 
MM74C912 and MM74C917 have five data inputs which 
accept either BCD (MM74C912) or hexadecimal 
(MM74C917) data, plus decimal point. The MM74C911 
can interface up to four 8-segment displays and the 
MM74C912/MM74C917 can control up to six 8-segment 
displays. 


il. Functional Description — MM74C911 

The functional block diagram for the MM74C911 is 
shown in Figure 1. The eight data inputs are buffered 
and bussed to the four dual-port latches. To write data 
Into a particular latch, K1 and K2 address Tnputs are 
decoded and the proper latch is enabled when CE and 
WE are taken low. 

The latch outputs are controlled by the multiplexer 
(MUX) logic. All four latch data outputs are commonly 
bussed, and are sequentially read by the MUX logic. The 
bussed 8-segment outputs.are then buffered by bipolar 
segm ent driver transistors, which are enabled when 
SOE Is low, an d are in TRI-STATE® mode when Segment 
Output Enable (SOE) is held high. This allows easy display 
blanking without loss of data. 

The multiplexer logic controls all of the timing for the 
MM74C911 and also generates the digit output strobes. 
The timing diagram is shown in Figure 2. 


K1 

K2 



7L/F/6030-1 


Figure 1. MM74C911 Block Diagram 


2-68 








TmUX - MiSl 


04 

Figure 2. MUX Timing for MM74C91 "I TL/F;6030-2 

By raising the Digit In-Out (DIO) input high, the internal 
oscillator is disabled and the digit outputs become 
inputs which control reading of the 4-digit latches. This 
allows the MM74C911 to b e slaved to other multiplex 
timing signals. If both SOE and DIO are held high, both 
the display and oscillator are disabled causing the 
MM74C911 to be in a low-power mode where it typically 
draws less than 1/iA. Figure 3 shows the truth table for 
these control inputs. 


DIO/OSE 

sot 

MODE 

0 

0 

NORMAL DISPLAY MODE 

0 

1 

DISPLAY BLANKED 

1 

0 

WILL DISPLAY ONE DIGIT* 

1 

1 

LOW POWER MODE 


Figure 3. Operating Modes for the MM74C911/ 

MM74C912/MM74C917 (*The 74C911 Digit 
Outputs become inputs.) 

III. Functional Description — 
MM74C912/MM74C917 

The functional block diagram for the MM74C912 and 
MM74C917 is shown in Figure 4. These devices are very 


similar to the MM74C911. There are only five data inputs 
on the MM74C912 and MM74C917 which are buffered, 
then bussed to six 5-bit dual-port latches. The address 
present on K1, K2, and K3 will dictate which of the six 
latches will be loaded when both CE and WE are low. The 
outputs of all of the latches are commonly bussed and fed 
into a decoder ROM which converts BCD (MM74C912) or 
hexadecimal {MM74C917) code to seven segment. The 
fifth bit is the decimal point, which bypasses the ROM. 
The 8-segment bits are then buffered by eight NPN- 
segment drivers. Like the MM74C911, these outp uts are 
TRI-STATE and will blank the display when SOE is held 
high. 

All of the multiplexing is controlled by an internal oscil- 
lator and control logic. The logic sequentially reads each 
latch and activates the digit outputs. The oscil lator can be 
disabled by raising the Oscillator Enable (OSE) input high, 
but the digit outputs do not become inputs and thus the 
MM74C912, and M M7 4C91 7 can not be slaved. However, by 
raising both SOE and OSE high, these parts can be put into 
a low-power mode similar to the MM74C911. Figure 3 
shows the controller operating modes. 

The MM74C912 and the MM74C917 are identical except 
for the last seven ROM locations. The ROM outputs are 
shown in Figure 5 for both parts. 


IV. Display Interface Design 

A. Common Cathode LED’s 

Since the MM74C911/MM74C912/MM74C917 contain all 
the multiplex circuitry necessary to operate a 4- or 
6-digit display, all the designer must do is choose appro- 
priate segment resistors and digit drivers to properly 
illuminate the LEDs. A typical LED connection is shown 
in Figure 6. Based on the selected display, a certain 
segment current will be required. This current will 
determine the value of the segment resistor and the type 
of digit driver necessary. The design for the MM74C911 is 



2-69 


AN-257 



AN-257 














nearly the same as for the MM74C912/MM74C917 except 
that due to multiplexing the 6-digit controllers must be 
designed to a higher peak current value. 

As an example, suppose the the NSN781 (2-digit, 0.7" 
common catholde LED display) has been selected. 
These displays require an average current of 8 mA per 
segment for good illumination. The MM74C911 multi- 
plexes four digits; thus, any one digit is on V4 of the 
time. Each digit must have a peak current four times its 
average current to achieve the same brightness. The 
MM74C911 must supply about 32mA per segment, and 
the MM74C912/MM74C917 would have to supply a cur- 
rent six times the average current or about 48mA. 

The maximum digit driver current is the maximum num- 
ber of “on” segments multiplied by the segment cur- 
rent. For the MM74C911 design, the digit current is 
~260mA, and is ~380mAfor the MM74C912/MM74C917. 
Using this digit current value, the digit driver can be 
selected. Figure 7 shows possible digit driver ICs, but 
discrete transistors or Darlingtons may also be used, 
and may be desirable in some higher current applications. 
It is also important to keep in mind that the output voltage 
of the driver at the designed current, as this voltage can 
affect the display controllers current drive. For most de- 
signs, an output voltage of <2V Is reasonable. 


Once the digit driver has been chosen and the output 
voltage at the desired current is known, the segment 
resistor, Rseg can be calculated using: 

r. Vseg - Vled- Vdo 
nsEG- j — 


where V|_ed is the voltage across the LED, 1.8V; Vdo is 
the digit driver output voltage at the chosen current; 
•sEG is the peak segment current; and Vseg is the 
MM74C911 or MM74C912 segment driver output voltage 
at the peak segment current, which can be determined 
from the curves in Figure 8. 

In most cases, Rseg can be more quickly determined 
from Figure 9 which plots Rseg vs. average segment 
current. These curves are plotted for various digit driver 
output voltages using current values from Figure 8. 
Thus, for the above example, if a DS75492 driver I.C. is 
used with the MM74C911 to interface to the NSB781 
LEDs Rseg = 38 Q assuming the drivers output voltage is 
1.0 V. Note that Figure 7 tabulates minimum output drive 
where the above Vqq is an approximation of the 
DS75492S typical Vqq at 260 mA. 


Part 

Number 

Driver Type 

Number of 
Drivers 

Minimum 

Output Drive 

DS75492 

Darlington Driver 

6 

250mA@1.5V 

DS75494 

Multiple Transistor Driver 

6 

150 mA@0.35V 

DS8646 

Transistor Driver 

6 

84 mA@0.55V 

DS8658 

Transistor Driver 

4 

84mA@0.55V 

DS8870 

Darlington Driver 

6 

350mA@1.4V 

DS8871/2 

Transistor Driver 

8/9 

40 mA@0.5V 

DS8877 

Transistor Driver 

6 

35 mA@0.5V 

DS8920 

Transistor Driver 

9 

40mA@0.5V 

DS8963 

Darlington Driver 

8 

500 mA@1.5V 

DS8978 

Transistor Driver 

9 

100 mA@0.7V 

DS8692 

Transistor Driver 

8 

350mA@1.0V 


Figure 7. Typical LED Digit Drivers and Their Characteristics 



SEGMENT DRIVER OUTPUT VOLTAGE (V) 

TL/F/6030-8 


SEGMENT DRIVER OUTPUT VOLTAGE (V) 

TL/F;6030-9 


Figure 8. Typical Segment Driver Current vs. Output Voltage for (a) MM74C911 (b) MM74C912/MM74C917 



2-71 


AN-257 




AN-257 



0 5/20 10/40 15/60 20/80 25/100 

AVERAGE/PEAK SEGMENT CURRENT (mA) 



0 5/30 10/60 1^/90 20/120 

AVERAGE/PEAK SEGMENT CURRENT (mA) 


TL/F/6030-10 


TL/F/6030-t1 


Figure 9. Average LED Segment Current vs. Segment Resistor for (a) IVIM74C911 (b) MM74C912/MM74C917 


Figures 10 and 11 tabulate some typical segment resis- 
tor values for various National LED displays. (See Opto- 
electronics Databook for detailed specifications.) This 
table was compiled for a well lit room, but variation in 
ambient lighting may require some slight modification 
in the typical segment resistor values. 

If a transistor digit driver is being used, it is sometimes 
desirable to use a base current limiting resistor between 
the controller’s output and the transistor’s base. This will 
help limit the powerdissipation of thedisplaycontrollef In 
critical situations. The digit resistor, Rqiq, can be calcu- 
lated using: 

D ’ Vdig-Vdi 
Hdig j 

•di 


where Vqi is the digit driver input voltage, 0.7V for a 
transistor, Ipi is the desired digit driver current and Vqig 
Is the controller’s digit output voltage for the chosen 
current which can be found from Figure 12. 

When the MM74G911 is to be used as a “master” to 
drive another MM74C911 or other logic, the digit outputs 
must have a high output voltage of 3.0V to driver ano- 
ther MM74C911 or 3.5V to drive standard CMOS logic. 
The digit resistor should be > 300Q for Vqh ^ 3.0V and 
Rdig ^ 350 for Vqh ^ 3.5V. 

A final design consideration is pow^r dissipation. When 
designing a low-power system where the total current is 
to be minimized, the total system power consumption is 
simply: 

Pt -Vcclbo + Idi] 


DISPLAY 

DRIVER 

TYPICAL RANGE DF 

SEGMENT RESISTORS 

PART NO. 

HEIGHT (IN.) 

NO. OF DIGITS 

NSA1298 

0.110 

9 

DS75492 

300-1000 

300-2000 Q* 

NSA1558 

i 

0.140 

8 

DS75492 

200-800 Q 

200-1 800Q* 

NSN381 

0.3 

2 

DS75492 

2N3904 

15-80Q 

NSB3881 

0.5 

4 

DS75492 

2N3904 

15-80Q 

NSN581 

0.5 

2 

DS75492 

2N3904 

10-60Q 

NSB5881 

0.5 

4 

DS75492 

2N3904 

10-60Q 

NSN781 

0.7 

2 

DS75492 

2N3904 

10-50 Q 

NSB7881 

0.7 

4 

DS75492 

2N3904 

10-50 Q 


Figure 10. MM74C911 Segment Resistor Values for Various Displays (Vcc = 5V) (*Using Red LED Filter over 
Display) 


2-72 




DISPLAY 

DRIVER 

TYPICAL RANGE OF 

PART NO. 

HEIGHT (IN.) 

NO. OF DIGITS 

(Rd = 0) 

SEGMENT RESISTORS 

NSA1298 

0.110 

9 

DS75494 

. 

200-800 Q 

300-1 500 Q* 

NSA1558 

0.140 

8 

DS75494 

150-700 Q 

150-1000Q* 

NSN381 

0.3 

2 

DS75492 

5-50 Q 

NSB581 

0.5 

2 

DS75492 

5-50 Q 

NS5931 

0.5 

6 

DS75492 

2N3904 

5-40 Q 

NSN781 

0.7 

2 

DS75492 

2N3904 

5-30 Q 


Figure 11. MM74C912/MM74C917 Segment Resistor for Average Intensity for Various Displays (*Using Red LED 
Filter over Display) 



0 1.0 2.0 3.0 4.0 5.0 

DIGIT OUTPUT VOLTAGE (V) 

* TL/F/6030-12 



Figure 12. Typical Digit Driver Current vs. Output Voltage for (a) MM74C911 (b) MM74C912/MI\/I74C917 


where Iqo 's the maximum digit driver output current, 
Vcc is the power supply voltage, and Iqi is the digit dri- 
ver input current. 

When a circuit design employs large segment currents, 
the maximum dissipation should be calculated to 
ensure that the power consumption of the controller or 
digit driver is within the maximum limits. The display 
controller power dissipation is: 

Pc = S{Iseg)(Vcc “ Vseg) 

where Iseg ^nd Vseg ^re the peak segment current and 
segment voltage, as previously determined; and S is the 
maximum number of segments lit per digit. The maxi- 
mum package dissipation for the controllers vs, 
temperature is shown in Figure 13. 

To gain an understanding of how segment current 
affects the controllers power dissipation, Figure 14 
plots average and peak LED segment current vs. pack- 
age dissipation for both the MM74C911 and the 
MM74C912/MM74C917. These typical curves are plotted 
using the typical segment driver output currents and 
voltages from Figure 8. 


As the digit driver output voltage Vdq becomes larger, 
the driver dissipates more power, thus the designer 
should also ensure that the driver’s dissipation is not 
exceeded. Generally, the standard digit driver IC will 
dissipate around V 2 watt. (See specific data sheets.) Dri- 
ver power dissipation can be calculated by: 

Pd = (Vdo)(Idig) 

where Vqq and Iqig are the digit driver output voltage 
and current. In a standard digit driver, one output will be 
active all the time, but if discrete transistors are used, 
each transistor is turned on 25% of the time. The ave- 
rage power dissipation for each discrete transistor digit 
driver is Va of the above equation. 

B. Common Anode LED Display 

AlthoughconnectingtheMM74C911/MM74C912/MM74C917 
to common anode displays is somewhat more difficult 
than to common cathode displays, it can be done. 
These controllers still provide all the necessary timing 
signals, but some extra buffering must be added to 
ensure the correct logic levels and drive capability. 



2-73 


AN-257 




AN-257 


(a) 





-50 -25 0 25 50 75 100 125 -55 -25 0 25 50 . 75 100 125 

AMBIENT TEMPERATURE (°C) tl/f/6030.i4 AMBIENT TEMPERATURE (X) tuf/6030.i5 

Figure 13. MM74C911/MM74C912MM74C917 Maximum Power Dissipation for (a) Plastic “N” Package (b) 
Ceramic “J” Package (Note = 125°C Maximum Junction Temperature) 




5/20 10/40 15/60 20/80 25/100 5/30 10/60 15/90 20/120 

AVERAGE/PEAK SEGMENT CURRENT (mA) tl/f/ 603 o.i 6 AVERAGE/PEAK SEGMENT CURRENT (mA) ruF/eoso i? 


Figure 14. Typical Power Dissipation vs. Segment Current for (a) MM74C911 (b) MM74C912/MM74C917 


To drive common anode displays, the display 
controller’s segment outputs must be inverted and the 
digit outputs must be current buffered. Figure 15 shows 
a simple circuit to interface to most common anode dis- 
plays. An 8-digit calculator digit driver IC, DS8871, is 
used to drive the display segments. Segment resistors on 
the controller’s segment outputs are not necessary but 
may be necessary on the outputs of the DS8871 driver. 

For higher current displays, the choice of digit driver 
transistor is important as the digit current will depend 
on how high the digit driver output of the display con- 
troller can pull up due to the emitter follower configura- 
tion. For good display brightness, a high gain medium 
power transistor should be used. 


C. Vacuum Fluorescent (VF) Displays 
The MM74C911/MM74C912/MM74C917 are not directly 
capable of driving VF displays, but serve as a major 
functional block to ease driving 4- or 6-dlgit displays. 
The controllers provide the multiplex timing for this dis- 
play, but the segment and digit outputs must be level 
shifted, and a filament voltage must be applied. 

In Figure 16, a DS8654 or similar device is used to trans- 
late the segment and digit voltages to 30V to drive the 
segment plates and digit grids. The AC filament voltage 
is derived from a separate low-voltage transformer 
which is biased by a zener. Since there is no pull-down 
in the DS8654, pull-down resistors must be added. The 
exact anode and cathode voltages and the bias zener 
will depend on the display used, but the basic circuit is 
the same. 


2-74 



Ee 


WE 

D1 

K1 

02 

K2 

03 


04 

oio 

MM74C911 

DD 

Sa 

g 

Sb 

f 

Sc 

e 

Sd 

d 

Se 

c 

Sf 

b 

Sg 

a 

sdp 




Figure 15. MM74C911 to Common Anode LED Interface Using 9 Digit Driver 


IN1 

0UT1 

IN2 

0UT2 

IN3 

° 0UT3 

IN4 

8 0UT4 

INS 

5 OUTS 

IN6 

^ 0UT6 

IN7 

0UT7 

INS 

OUTS 


VACUUM FLORESCENT DISPLAY 


I f f I f I f f I I f f 


mil 

Hill 



[ALL RESISTORS = 100KQ) 


Figure 16. MM74C912/MM74C917 to Vacuum Fluorescent Display Interface 








AN-257 


V. l\/gM74C911 Display Applications 

Of tho three CMOS display controllers, the MM74C911 is 
the si mplest, but also the most versatile. Since the char- 
acter font is not predetermined, many non-numerical 
char acters can be displayed using standard 8-segment 
displays. In many cases, it may be desirable to enable 
a snnall microprocessor to display prompt messages 
wheue the use of more complicated alpha-numeric dis- 
pla’ys is not justified. For these cases, the MM74C911 is 
ideal, because any combination of segments can be 
controlled. Figure 17 shows many of the possible letters 
anfd numbers that can be displayed along with their 
binary and hexadecimal values on 8-segment displays. 

There is no reason to restrict the MM74C911 to 
ai'lpha-numeric displays, as the controller allows direct 
control of individual LEDs. The MM74C911 can be con- 
nected to a mixture of numerical and discrete LEDs as 
'typified by Figure 18. Thus status and numerical data 
can be simultaneously controlled. 

Taking this one step further, all the LEDs could be 
discrete as shown in Figure 19. This type of arrangement 
is multipurpose. The LEDs could be configured as a 4 x 8 
matrix or possible two-bar graphs of 16 LEDs, Figure 20, 
or maybe some sort of binary data display. There are 
I many variations possible. 

VI. Slaving The MM74C911 

As mentioned, the MM74C911 has the unique feature of 
being able to be slaved to external multiplex logic or a 
“master” MM74C911. This feature is useful when the 
controller is to be synchronized with a rhaster. Figure 21 
shows a typical application where two MM74C911S are 
used to drive a 16-segment alpha-numeric display. In 
order to drive this display, synchronization is required to 
ensure that both controllers are outputting the same 
digit information at the same time. 


A more subtle advantage to slaving MM74C911s occurs 
when trying to use multi-controllers to drive more digits. 
This case, illustrated in Figure 22, allows fewer, more 
powerful digit drivers to be used. This can be advanta- 
geous when using smaller displays that require little 
power to begin with. 

VII. MM74C912/MM74C917 
Display Applications 

Both the MM74C911/MM74C912 have predetermined 
character fonts and this limits their versatility, but 
greatly simplifies their application in hex and decimal 
display application. Still, there are a few small “tricks” 
that can be used to stretch the controller’s capabilities. 

In many applications, the decimal point segment is not 
needed, particularly when the MM74C917 is used. Gene- 
rally, this part is used to display hexadecimal address 
and data information where decimal points are rarely 
needed. These segments could be used for status infor- 
mation. Figure 23 shows a typical implementation. The 
status LEDs could indicate power, run and halt status 
information of a host /.(P or could indicate the type of 
instruction being executed. Although the MM74C912 
applications would tend to use the decimal point more 
often, it is equally capable of implementing Figure 23. 

Another possibility, if all six digits are not required. Is to 
use the unused digits for status indicators. A possible 
example using the MM74C917 is shown in Figure 24, 
and another possible implementation for the MM74C912 
is shown in Figure 25. In both of these applications, four 
bits of data is loaded into digits 1 and/or 2. Depending 
on the data loaded, various combinations of discrete 
LEDs would be lit. The tables included in these figures 
illustrate numerical combinations and their results. 


CHARACTER 

HEX CODE 
FOR 74C911 

DISPLAY 

CHARACTER 

HEX CODE 
FOR 74C911 

DISPLAY 

0 

FC 

n 

u 

J 

78 

LI 

1 

60 

1 

1 

L 

1C 

1 

L 

2 

OA 

_i 

/_ 

N 

2A 

n 

3 

F2 

_/ 

_/ 

0 

FC 

n 

1 1 

4 

66 

'-1 

0 

3A 

o 

5 

B6 

s 

P 

CE 

0 

1 

6 

BE 

B 

R 

OA 

r 

7 

EO 

1 

S 

B6 

c 

1 

8 

FF 

o 

o 

T 

8C 

h 

9 

F6 

o 

_/ 

U 

7C 

LI 




U 

38 

u 

A 

EE 

n 

1 1 

Y 

76 

B 

B 

3E 

L 

U 

Y 

4E 


C 

9C 

r 

/_ 



D 

7A 

_/ 

/_/ 

(Blank) 

00 


E 

9E 

c 

/L 


01 


F 

8E 

c 

/ 

— 

02 

- 

G 

BC 

r 

u 

— 

12 

- 

H 

1 6E 

n 

7 

CA 

0 

1 

H 

2E 

L 

1 1 


01 

Zl 

1 

1 OC 

1 

1 

< 

9B 

c 

1 

I 20 

1 





Figure 17. Segment Codes for Various Characters Using 8-Segment Displays (MSB of Hex Code is segment a, 
LSB is Decimal Point ie for 0 (a=1, b = 1, c = 1, d = 1, e = 1, f =1, g = 0, dp = 0) = FC) 


2-76 









NSL57124 
(32 PLACES) 


TL/F/6030-22 


Figure 20. Dual 16 Element Bar Graph Display 


'8 



5V 5V 



Figure 21. Interfacing to Alphanumeric Displays 



2-79 


AN-257 








Figure 23. 7-Segment Displays with 6-Discrete LED Indicators for MM74C912/MM74C917 Using “DP” Segment 



vcc 

Sa 

WE 


Sb 

CE 


Sc 



Sd 

K1 


Se 

K2 


Sf 

K3 


Sg 



Sop 

OSE 

IV1M74C917 


DP 


D1 

0 


02 

C 


D3 




A 


D5 


GND 

D6 



NSB3881 


f 1 

1 1 

f f 

f f 

LJ. 

LJ. 

U. 

I 1 


0S75492 DIGIT DRIVER 


LED’S (1=0N) 

INPUTS 



DP 1 d c 

A B C 0 OP 

1/0 0 0 0 
1/0 0 0 1 
1/0010 
1/0 011 
1/0 100 
1/0 101 
1/0110 
1/0111 

1/0 

00011/0 

0 0 10 1/0 
001 11/0 
11111/0 

0 10 0 1/0 

1 1 0 0 1/0 

1 0 0 0 1/0 


Figure 24. MM74C917 (a) Display with 8 Discrete LED’s (b) Inputs for LED Output Table 



AN-257 


5V 


TO mP 
INTERFACE 




Sa 

WE 

WE 

Sb 

CE 

CE 

Sc 

A2 

K3 

Sd 

A1 

K2 

Se 

AO 

K1 

Sf 



Sg 

f 

OSE 

SOE 

sdp 


MM74C912 


D4 

D 

D1 

D3 

C 

D2 

D2 

B 

03 

D1 — - 

A 

04 

DO 

OP 

. D5 


GND 

06 


30Q 

(8 PLACES) 




r 


“ON’ 

SEGMENTS 

BCD INPUTS 


DP 

G 

0 

B 

A 

0 

c 

B 

A 

DP 

1/0 

0 

0 

0 

0 

1 

1 

1 

1 

1/0 

1/0 

0 

0 

0 

1 

1 

1 

0 

0 

1/0 

1/0 

0 

0 

1 

0 

0 

0 

0 

1 

1/0 

1/0 

0 

0 

1 

1 

0 

1 

1 

1 

1/0 

1/0 

0 

1 

0 

0 

1 

1 

1 

0 

1/0 

1/0 

n 

1 

0 

1 

— 

— 

— 

— 

1/0 

1/0 

0 

1 

1 

0 

— 

— 

— 

— 

1/0 

1/0 

0 

1 

1 

1 

0 

0 

0 

0 

1/0 

1/0 

1 

0 

0 

0 

1 

1 

0 

1 

1/0 

1/0 

1 

0 

0 

1 

— 

— 

— 

_ 

1/0 

1/0 

1 

0 

1 

0 

0 

1 

0 

0 

1/0 

1/0 

1 

0 

1 

1 

1 

0 

1 

1 

1/0 

1/0 

1 

1 

0 

0 

1 

0 

1 

0 

1/0 

1/0 

1 

1 

0 

1 

0 

1 

0 

1 

1/0 

1/0 

1 

1 

1 

0 

_ 

_ 

_ 


1/0 

1/0 

1 

1 

1 

Jj 

1 

0 

0 

Xj 

1/0 



NSB3881 


1 1 

1 f 

1 f 

I I 



i_i^ 



NSL5808 
. (10 PLACES) 


3Y 4Y 

DS7549Z DIGIT DRIVER 


TL/F/6030-27 


Figure 25. MM74C912 (a) 4 Digit Display with Discrete LEDs (b) I/O Data Table 


VIII. Interfacing To Microprocessors 

The CMOS LED display controllers can be easily inter- 
faced to most of the popular microprocessors with the 
addition of only a few ICs. Most microprocessor data 
and address bus logic is specified to be TTL compatible. 
A standard TTL logic high, Vqh is supposed to be > 2.4 at 
full load which is not compatible with a CMOS V|h > 3.5 V. 
Although microprocessor inputs will typically pull-up 
above 3.5V, this is not guaranteed over the entire tem- 
perature range. It is recommehded that pull-up resistors 
be added to raise this level above 3.5 V. Under most con- 
ditions, a 5-10 K resistor should suffice. 

The write timing of the display controllers is illustrated 
in Figure 26. The minimum write access time is 430ns 
for the MM74C912/MM74C917 and 450ns for the 
MM74C911. A write to the controller is accomplished by 
placing the d^ired data on the data inputs, lowering 
the CE and WE inputs, and then raising them to com- 
plete the wri^ Even though CE and WE are inter- 
changeabje, CE is usually derived from the address 
decoding logic and WE is connected to the CPU write 
strobe. Other than the slight timing differences between 


the MM74C911 and the MM74C912/MM74C917, the only 
other major microprocessor interfacing differences are 
that the MM74C912/MM74C917 have an additional digit 
address bit which must be connected to the micro- 
processors address bus, and the MM74C911 has eight 
data inputs whereas the MM74C912/MM74C917 have 
only five. 

A. Interfacing To The INS8080 

These controllers can be connected to the 
INS8080/1NS8224/INS8238 CPU group with no external 
logic if no more than a minimal amount of address 
decoding is required. Since the INS8080 has a separate 
memory and I/O port address spaces, one of the I/O p ort 
address bits could be directly connected to the CE 
input. Figure 27 illustrates this using an MM74C911. 
When ever an OUT instruction is executed causing the 
l/OW (INS8080 write enable signal) to go low and the 
address is such that A7 is low, AO A1 will select the digit 
to be written. If more decoding is required, some exter- 
nal gating logic may be added to the CE input. 


2-82 




D. Interfacing To The 6800 

When using the INS8080, Z80, or NSC800, these proces- 
sors have separate I/O and memory address spaces. 
This usually allows simpler interfaces to be designed. 
The 6800 has no separate I/O addressing so I/O ports 
are usually mapped into a small block of memory. This 
requires more address decoding to ensure that memory 
and I/O don’t overlap. 

Figure 30 shows a DM8131 6-bit address bus compara- 
tor whose Bp inputs .are a combination of A15-A12 
address bits, the ^2 (6800 system clock) and the VMA 
(Valid Memory Access) control signal. When these 
inputs equal the corr^ponding Tp inputs, the ou tput 
goes low. The 6800 R/W signal is connected to the WE. 

E. Interfacing To The INS8060/INS8070 

Like the 6800, the INS8060/8070 series of microproces- 
sors don’t have any separate I/O addressing, so the 
MM74C911/MM74C912/MM74C917 must be memory 
addressed, but unlike the 6800 both the INS8070 series 
and the INS8060 have separate read/write strobes, 
which can simplify interfacing the display controllers. 
Figure 31 illustrates a typical INS8060 interface. The 
NWDS (write enable) is directly connected to the 
MM74C912S WE input and the DM8131 provides the 
address decoding for the controller. The INS8060 has 
only 12 address bits (unless using paged addressing) so 
bits Aq-Ah are decoded by the comparator. 

The IN S8070 series microprocessor has the identical 
NWDS signal but has 16 address bits. Thus Figure 31 
would connect the A10-A15 address bits to the DM8131. 




TL/F/6030-28 


Figure 26. MM74C911/MM74C912/MM74C917 Timing Diagram (See data sheets for numbers) 


The MM74C912/MM74C917 would be interfaced by con- 
necting the A, B, C, D and DP to bit D0-D4 of the data 
bus and connecting K1-K3 to A 0 -A 2 . Writing data to these 
controllers would be the same as writing to the MM74C91 1 . 

B. Interfacing to the Z80^'^* 

To connect these display controllers to the Z80 micro- 
processor, only a minor modification to the INS 8080 
need be made. The Z80 control signals are slightly dif- 
ferent from the INS8080. Instead of the INS 8080 I/O 
write strobe, the Z80 has an I/O request line (lOREQ), 
which goes low to indicate an I/O port is to be accessed, 
and a write (WR) strobe which indicates that a memory 
or I/O write is to be done. By OR-ing, these together an 
equivalent l/OW signal is generated as shown in Figure 28. 

C. Interfacing to the NSC800 

The NSC800 has very different timing because the lower 
eight address bits and the data bus are multiplexed. But 
when connecting the display controllers as I/O ports, 
the interface is only slightly different from the INS8080 
design. When an I/O instruction is executed, the port 
address that appears on A0-A7 is duplicated on 
A8-A15, and this address can be used directly. The con- 
troller WE inpuj_must be decoded from a WR (write 
enable) and lO/M (I/O or memory enable) as shown in 
Figure 29. Note that since the NSC800 is a CMOS micro- 
processor, no pull-up resistors are needed. 

Figure 29 uses address bit A15 which is equivalent to bit 
A7 on the previous examples. As with the previous 
examples, if more address decoding is required, either 
gates or decoders could be connected to the CE input. 



2-83 


AN-257 




INS8080 04 

DATA 

BUS D3 



WE 



SEGMENT 

OUTPUTS 

K2 


K1 

DiO 


MM74C911 ^ 

DP 


Q 

f 

DIGIT 

OUTPUTS 

d 


b 

a 



PORT ADDRESS = OXXX XXAB (BINARY) 
(WHERE X = DON’T CARE AND AB 
ARE THE DIGIT SELECT (00-11) 


ALL INPUT RESISTORS 5-10K2 


Figure 27. INS8080/INS8224/INS8238 Interface to MM74C911 



LJ LJ t-J f !-J' 

If If If If If If 


PORT ADDRESS = 0XXX XABC (BINARY) 
(WHERE X = DON’T CARE AND ABC IS 
DIGIT ADDRESS 


Figure 28. Z80 Interface to MM74C912/MM74C917 









F. Multiple Display Controllers 

In systems where multiple display controllers are to be 
used, the simple addressing schemes of the previous 
examples may prove to be too costly in I/O capabilities, 
so some extra decoding is necessary to derive the CE 
signals. A typical method uses a 2-4 line decoder or a 
3-8 line decoder. Where the total time from a stable 
address to the write pulse goes inactive is ^ 1 /uS, a 
CMOS decoder such as the MM74C42 or MM74C154 can 
be used, but if faster accessing is required, their LS' 
equivalents should be employed. 

Figure 32 shows a typical implementation of a 16-digit 
display using half of a DM74LS139 decoder to provide 
the CE signals for each controller. 

G. Making The MM74C911/MM74C912/ 

MM74C917 Look Like RAM 

So far, the discussion of addressing the controllers has 
been to separate the devices from memory, but there 
are certain advantages to not doing this. In many 
instances, microprocessor software requirements are 
such that data outputted to the controller also must be 
remembered by the microprocessor for later use. Since 
data cannot be read from the display controllers, the 
processor must also write the data in a spare register or 


a memory location. This extra writing and “book- 
keeping” software can be eliminated by addressing the 
MM74C911/MM74C912/MM74C917 over existing RAM. 
When data is written to the controller, it could also be 
stored in RAM simultaneously and can be read later by 
the CPU. 

Figure 31 shows a simple example of this using an 
MM74C912 controller and two MM2114 1Kx4 memory 
chips. A DM74LS30 is used to detect when the last eight 
bytes of this memory is being accessed and enables the 
controller display. Thus, the last eight bytes of the RAM 
contains a duplicate copy of what the display controller is 
displaying. 

IX. Conclusion 

All three controllers provide simple and inexpensive inter- 
faces to multiplexed multidigit displays. These devices 
are particularly well suited to microprocessor en- 
vironments, but any type of CMOS compatible control 
hardware can be used. The MM74C911/MM74C912/ 
MM74C917 can most easily drive common anode dis- 
plays. By'providing most of the multiplex circuitry into one 
low-cost integrated circuit, the burden of designing 
discrete multiplexing has been eliminated. 


CPU DATA 
BUS D0-D7 


CPU J 
ADDRESS < 
BUS ' 


CPU WRITE 
ENABLE 
(ACTIVE LOW) 



Figure 32. Multi-Digit Array 



2-87 


AN-257 






HC-MOS Power 
Dissipation 


National Semiconductor 
Application Note 303 
Kenneth Karakotsios 
February 1 984 



) 


If there is one single characteristic that justifies the exis- 
tence of CMOS, it is low power dissipation. In the quiescent 
state, high-speed CMOS draws five to seven orders of mag- 
nitude less power than the equivalent LSTTL function. 
When switching, the amount of power dissipated by both 
metal gate and high-speed silicon gate CMOS is directly 
proportional to the operating frequency of the device. This is 
because the higher the operating frequency, the more often 
the device is being switched. Since each transition requires 
power, power consumption increases with frequency. 

First, one will find a description of the causes of power con- 
sumption in HC-CMOS and LSTTL applications. Next will 
follow a comparison of MM54HC/MM74HC to LSTTL power 
dissipation. Finally, the maximum ratings for power dissipa- 
tion imposed by the device package will be discussed. 

Quiescent Power Consumption 

Ideally, when a CMOS integrated circuit is not switching, 
there should be no DC current paths from Vcc to ground, 
and the device should not draw any supply current at all. 
However, due to the inherent nature of semiconductors, a 
small amount of leakage current flows across all reverse-bi- 
ased diode junctions on the integrated circuit. These leak- 
ages are caused by thermally-generated charge carriers in 
the diode area. As the temperature of the diode increases, 
so do the number of these unwanted charge carriers, hence 
leakage current increases. 

Leakage current is specified for all CMOS devices as Ice- 
This is the DC current that flows from Vcc to ground when 
all inputs are held at either Vcc or ground, and all outputs 
are open. This is known as the quiescent state. 

For the MM54HC/MM74HC family, Ice is specified at ambi- 
ent temperatures (Ta) of 25°C, 85“C, and 125“C. There are 
three different specifications at each temperature, depend- 
ing on the complexity of the device. The number of diode 
junctions grows with circuit complexity, thereby increasing 
the leakage current. The worst case Ice specifications for 
the MM54HC/MM74HC family are summarized in Table I. In 
addition, it should be noted that the maximum Icc current 
will decrease as the temperature goes below 25°C. 


TABLE I. Supply Current (Icc) for MM54HC/MM74HC 
Specified at Vcc = 6V 


Ta 

Gate 

Buffer 

MSI 

Unit 

25°C 

2.0 

4.0 

8.0 

}xfK 

85°C 

20 

40 

80 

fxA 

125°C 

40 

80 

160 

jllA 


To obtain the quiescent power consumption for any CMOS 
device, simply multiply Icc by the supply voltage: 

Pdc=IccVcc 

Sample calculations show that at room temperature the 
maximum power dissipation of gate, buffer, and MSI circuits 
at Vcc=6V are 10 /nW, 20 p.W, and 40 fxW, respectively. 

Dynamic Power Consumption 

Dynamic power consumption is basically the result of charg- 
ing and discharging capacitances. It can be broken down 
into three fundamental components, which are: 

1 . Load capacitance transient dissipation 

2. Internal capacitance transient dissipation 

3. Current spiking during switching. 

Load Capacitance Transient Dissipation 

The first contributor to power consumption is the charging 
and discharging of external load capacitances. Figure / is a 
schematic diagram of a simple CMOS inverter driving a ca- 
pacitive load. A simple expression for power dissipation as a 
function of load capacitance can be derived starting with: 

Ql=ClVcc 

where Ci_ is the load capacitance, and Ql is the charge on 
the capacitor. If both sides of the equation are divided by 
the time required to charge and discharge the capacitor 
(one period, T, of the input signal), we obtain: 



TL/L/5021-1 

FIGURE 1. Simple CMOS Inverter Driving a 
Capacitive External Load 

Since charge per unit time is current (Ql/T = I) and the in- 
verse of the period of a waveform is frequency (1/T = f): 
lL = CLVccf 

To find the power dissipation, both sides of the equation 
must be multiplied by the supply voltage (P = VI), yielding: 
Pl = Cl Vcc^f 


2 


2-89 


AN-303 




AN-303 


One note of caution is in order. If all the outputs of a device 
are not switching at the same frequency, then the power 
consumption must be calculated at the proper frequency for 
each output: 

PL = Vcc2(CLifi +CL2f2+ • • • +CLnfn)' 

Examples of devices for which this may apply are: counters, 
dual flip-flops with independent clocks, and other integrated 
'Circuits containing dual, triple, etc., independent circuits. 

internal Capacitance Transient Dissipation 

Internal capacitance transient dissipation is similar to load 
capacitance dissipation, except that the internal parasitic 
“on-chip” capacitance is being charged and discharged. 
Figure 2 \s a. diagram of the parasitic nodal capacitances 
associated with two CMOS inverters. 


vcc 



FIGURE 2. Parasitic internai Capacitances 
Associated with Two inverters 


Ci and C 2 are capacitances associated with the overlap of 
the gate area and the source and channel regions of the P- 
and N-channel transistors, respectively. C 3 is due to the 
overlap of the gate and source (output), and is known as the 
Miller capacitance. C 4 and C 5 are capacitances of the para- 
sitic diodes from the output to Vcc and ground, respectively. 
Thus the total internal capacitance seen by inverter 1 driv- 
ing inverter 2 is: 

C| = Cl -f C 2 + 2 C 3 + C 4 + C 5 

Since an internal capacitance may be treated identically to 
an external load capacitor for power consumption calcula- 
tions, the same equation may be used: 

P| = C|Vcc2f 


Vcc 


INPUT O- 


6ND<V|N<Vcc 


IE 


-O OUTPUT 


Ji 


VCC>VoUT>GND 


1 


At this point, it may be assumed that different parts of the 
internal circuitry are operating at different frequencies. Al- 
though this is true, each part of the circuit has a fixed fre- 
quency relationship between it and the rest of the device. 
Thus, one value of an effective C| can be used to compute 
the Internal power dissipation at any frequency. More will be 
said about this shortly. 

Current Spiking During Switching 

The final contributor to power consumption is current spik- 
ing during switching. While the input to a gate is making a 
transition between logic levels, both the P- and N-channel 
transistors are turned partially on. This creates a low imped- 
ance path for supply current to flow from Vcc fo ground, as 
illustrated in Figure 3. > 

For fast input rise and fall times (shorter than 50 ns for the 
MM54HC/MM74HC family), the resulting power consump- 
tion is frequency dependent. This is due to the fact that the 
more often a device is switched, the more often the input is 
situated between logic levels, causing both transistors to be 
partially turned on. Since this power consumption is propor- 
tional to input frequency and specific to a given device in 
any application, as is C|, it can be combined with C|. The 
resulting term is called “Cpo,” the no-load power dissipation 
capacitance. It is specified for every MM54HC/MM74HC 
device in the AC Electrical Characteristic section of each 
data sheet. 

It should be noted that as input rise and fall times become 
longer, the switching current power dissipation becomes 
more dependent on the amount of time that both the P- and 
N-channel transistors are turned on, and less related to Crd 
as specified in the data sheets. Figure 4 is a representation 
of the effective value of Cpp as input rise and fall times 
increase for the MM54HC/MM74HC08, MM54HC/ 
MM74HC139, and MM54HC/MM74HC390. To get a fair 
comparison between the three curves, each is divided by 
the value of Crd for the particular device with fast input rise 
and fall times. This is represented by “Cpoo,” the value of 
CpD specified in the data sheets for each part. This compar- 
ison appears in Figure 5. Cpp remains constant for input rise 
and fall times up to about 20 ns, after which it rises, ap- 
proaching a linear slope of 1 . The graphs do not all reach a 
slope of 1 at the same time because of necessary differ- 
ences in circuit design for each part. The MM54HC/ 
MM74HC08 exhibits the greatest change in Cpp, while the 
MM54HC/MM74HC139 shows less of an increase in Crd at 


O 


TL/L/5021-3 


Vcc 

1 Hp-CHANNEL 
O OUTPUT 

^ Rn-channel 

rr* TL/L/5021-4 


FIGURE 3. Equivalent schematic of a CMOS inverter whose input is between logic levels 


2-90 




any given frequency. Thus, the power dissipation for most of 
the parts in the MM54HC/MM74HC family will fall within 
these two curves. One notable exception is the MM54HC/ 
MM74HCU04. 


This equation can be used to compute the total power con- 
sumption of any MM54HC/MM74HC device, as well as any 
other CMOS device, at any operating frequency. It includes 
both DC and AC contributions to power usage. Cpp and Ice 
are supplied in each data sheet for the particular device, 
and Vcc and f are determined by the particular application. 



INPUT RISE AND FALL TIME 


TL/L/5021-5 

FIGURE 4. Comparison of Typical Cpo for 
MM54HC/MM74HC08, MM54HC/MM74HC139 


MM54HC/MM74HC390 as a Function of 
Input Rise and Fall Time, 
trise = tfaii, Vcc = 5V, Ta = 25X 



Comparing HC-CMOS to LSTTL 

Although power consumption is somewhat dependent on 
frequency in LSTTL devices, the majority of power dissipat- 
ed below 1 MHz is due to quiescent supply current. LSTTL 
contains many resistive paths from Vqc to ground, and even 
when it is not switching, it draws several orders of magni- 
tude greater supply current than HC-CMOS. Figure ^ is a 
bar graph comparison of quiescent power requirements 
(Vcc)x{lcc) between LSTTL and HC-CMOS devices. 

The reduction in CMOS power consumption as compared to 
LSTTL devices is illustrated in Figures 7 and 8. These 
graphs are comparisons of the typical supply current (Iqc) 
required for equivalent functions In MM54HC/(MM74HC, 
MM54HC/MM74C, CD4000, and 54LS/74LS logic families. 
The currents were measured at room temperature (25°C) 
with a supply voltage of 5V. 

Figure 7 represents the supply current required for a quad 
NAND gate with one gate in the package switching. The 
MM54HC/MM74HC family draws slightly more supply cur- 
rent than the 54C/74C and CD4000 series. This is mainly 
due to the large size of the output buffers necessary to 
source and sink currents characteristic of the LSTTL family. 
Other reasons include processing differences and the larger 
internal circuitry required to drive the output buffers at high 
frequencies. The frequency at which the CMOS device 
draws as much power as the LSTTL device, known as the 
power cross-over-frequency, is about 20 MHz. 

In Figure 8, which is a comparfson of equivalent flip-flops 
(174) and shift registers (164) from the different logic fami- 
lies, the power cross-over frequency again occurs at about 
20 MHz. 


INPUT RISE AND FALL TIME 


TL/L/5021-6 

FIGURE 5. Normalized Effective Cpp (Typical) 
for Slow Input Rise and Fall Times. 


trise = tfaii, Vcc = 5V,Ta = 25X 


Inputs that do not pull all the way to Vcc O'' ground can also 
cause an increase in power consumption, for the same rea- 
son given for slow rise and fall times. If the input voltage is 
between the minimum input high voltage and Vcc. then the 
input N-channel transistor will have a low impedance (i.e., 
be “turned on”) as expected, but the P-channel transistor 
will not be completely turned off. Similarly, if the input is 
between ground and the maximum input low voltage, the P- 
channel transistor will be fully on and the N-channel transis- 
tor will be partially on. In either case, a resistive path from 
Vcc to ground will occur, resulting in an increase in power 
consumption. 

Combining all the derived equations, we arrive at the 
following: 

Ptotal = (Cl + C po) Vec^f + IccVcc 



POWER CONSUMPTION (MILLIWATTS) 

TL/L/5021-7 

FIGURE 6. High Speed CMOS (HC-CMOS) vs. LSTTL 
Quiescent Power Consumption 



2-91 


AN-303 




AN-303 


The power cross-over frequency increases as circuit com- 
plexity increases. There are two major reasons for this. 
First, having more devices on an LSTTL integrated circuit 
means that more resistive paths between Vcc and ground 
will occur, and more quiescent current will be required. In a 
CMOS integrated circuit, although the supply leakage cur- 
rent will increase, it is of such a small magnitude (nanoAmps 
per device) that there will be very little increase in total pow- 
er consumption. 



10kHz 100kHz 1MHz 10MHz 100MHz 
INPUT FREQUENCY 

TL/L/5021-8 

FIGURE 7. Supply Current vs. Input Frequency 
for Equivalent NAND Gates 



10kHz 100kHz 1MHz IQMHz 100MHz 
FREQUENCY 

TL/L/5021-9 

FIGURE 8. Supply Current vs. Frequency 

Secondly, as system complexity increases, the precentage 
of the total system operating at the maximum frequency 
tends to decrease. Figure 9 shows block diagrams of a 
CMOS and an equivalent LSTTL system. In this abstract 
system, there is a block of parts operating at the maximum 
frequency (Fmax). a block operating at half F^ax. a block 
operating at one quarter F^ax. and so on. Let us call the 
power consumed in the first section PI. In a CMOS system, 
since power consumption is directly proportional to the op- 
erating frequency, the amount of power consumed by the 
second block will be (P1)/2, and the amount used in the 
third section will be (P1)/4. If the power consumed over a 
large number of blocks Is summed up, we obtain: 

PtOTAL=P1+(P1)/2 + (P1)/4+ . . . + (P1)/(2n-1) 
and Ptotal^2{P1) 


Now consider the LSTTL system. Again, the power con- 
sumed in the first block is PI . The amount of power dissipat- 
ed in the second block is something less than PI , but great- 
er than (P1 )/2. For simplicity, we can assume the best case, 
that P2 = (P1)/2. The power consumption for all system 
blocks operating at frequencies Fmax/2 and below will be 
dominated by quiescent current, which will not change with 
frequency. The power used by blocks 3 through n will be 
approximately equal to the power dissipated by block 2, 
(PI )/2. The total power consumed in the LSTTL system is: 

PtOTAL=(P1+(P1)/2 + (P1)/2+ . . . +(P1)/2 

Pt0TAL=P1+(N-1)(P1)/2 , 

and for n>2, Ptotal>2{P1) 

Thus, an LSTTL system will draw more power than an 
equivalent HC-CMOS system. 


CMOS: 



P0WERi=Pi POWER2 = Pi/2 P0WER3 = Pi/4 P0WERn = Pi/2(n-1) 


LSTTL: 



P0WERi=Pi P0WER2 ~Pi/2 P0WER3~Pi/ 2 P0WERn'^Pl/2 

TL/L/5021-10 

FIGURE 9. Comparison of Equivalent CMOS 
and LSTTL Systems 


This effect is further illustrated in Figure 10. An arbitrary 
system is composed of 200 gates, 150 counters, and 150 
full adders, with 50 pF loads on all of the outputs. The sup- 
ply voltage Is 5V, and the system is at room temperature. 
For this system, the worst case power consumption for 
CMOS Is about an order of magnitude lower than the typical 
LSTTL power requirements. Thus, as system complexity in- 
creases, CMOS will save more power. 

Maximum Power Dissipation Limits 

It is important to take into consideration the maximum pow- 
er dissipation limits imposed on a device by the package 
when designing with high-speed CMOS. Both the plastic 
and ceramic packages can dissipate up to 500 mW. Al- 
though this limit will rarely be reached in typical high-speed 
applications, the MM54HC/MM74HC family has such large 
output current source and sink capabilities that driving a re- 
sistive load could possibly take a device to the 500 mW 
limit. This maximum power dissipation rating should be de- 
rated by -12 mW/®C, starting at 65“C for the plastic pack- 
age and 1 00°C for the ceramic package. This is illustrated in 
Figures 1 1 and 12. Thus, if a device In a plastic package Is 
operating at 70°C, then the maximum power dissipation rat- 
ing would be 500 mW — (70°O~65°C) (12 mW/°C) = 44 
mW. Note that the .maximum ambient temperature is 85°C 
for plastic packages and 1 25°C for ceramic packages. 


2-92 




i 100 m 


10m 


LSTT 

WOR 

L SYSl 
ST CAS 

EM: 

E TYPICAL 



L_ 





HIGH- 

WORS 

SPEED 

TCASE 

CMOS 

SYSTEM: > 

TYPICAL^ 





y/THESYi 
/ CONSI 

TEMS 
ST OF 



z 

200 GATES 
150 COUNTERS 

isnpiiii AnnPRi; 


Z 

r 

CL = 50pF, ALL OUTPUTS 


100 Ik 10k 100k 1M 10M 
FREQUENCY OF SYSTEM (Hz) 


100 M 



TL/L/5021-11 


AMBIENT TEMPERATURE (°C) — - 


FIGURE 10. System Power vs. Frequency 
MMHC74HC vs. LSTTL 


TL/L/5021-13 


FIGURE 12. Ceramic Package (MM54HC) 
High Temperature Power Derating 
for MM54HC/MM74HC Family 



AMBIENT TEMPERATURE (°C) — 

TL/L/5021-12 


FIGURE 11. Plastic Package (MM74HC) 
High Temperature Power Derating 
for MM54HC/MM74HC Family 


Summary 

The MM54HC/MM74HC high-speed silicon gate CMOS 
family has quiescent (standby) power consumption five to 
seven orders of magnitude lower than the equivalent LSTTL 
function. At high frequencies (30 MHz and above), both 
families consume a similar amount of power for very simple 
systems. However, as system complexity increases, HC- 
CMOS uses much less power than LSTTL. To keep power 
consumption low. Input rise and fall times should be fast 
(less than 50 to 1 00 ns) and inputs should swing all the way 
to Vcc and ground. 

There is an easy-to-use equation to compute the power 
consumption of any HC-CMOS device in any application: 

PtOTAL= (Cl+ CpD)Vcc2f + IccVcC 
The maximum power dissipation rating is 500 mW per pack- 
age at room temperature, and must be derated as tempera- 
ture increases. 



2-93 


AN-303 




AN-310 


High-Speed CMOS 

(MM54HC/MM74HC) 

Processing 


National Semiconductor 
Application Note 310 
Kenneth Karakotsios 
June 1 983 



The MM54HC/MM74HC logic family achieves its high 
speed by utilizing microCMOS Technology. This is a 3.5 sili- 
con gate P-well CMOS process single layer poly, single lay- 
er metal, P-well process with oxide-isolated transistors. Why 
do silicon-gate transistors (polycrystalline) switch faster 
than metal-gate transistors? The reason is related both to 
the parasitic capacitances Inherent in integrated circuits and 
the gain of the, transistors. The speed at which an MOS 
transistor can switch depends on how fast its internal para- 
sitic capacitance, as well as its external load capacitance, 
can be charged and discharged. Capacitance takes time to 
be charged and discharged, and hence degrades a transis- 
tor’s performance. The gain of a transistor is a measure of 
how well a transistor can charge and discharge a capacitor. 
Therefore, to increase speed, it is desirable to both de- 
crease parasitic capacitance and increase transistor gain. 
These advantages are achieved with National’s silicon-gate, 
CMOS process. To understand exactly how these Improve- 
ments occur in silicon-gate CMOS, it is helpful to compare 
the process to the metal-gate CMOS process. 

Metal-Gate CMOS Processing 

Figure 1 through 12 are cross Sections of a metal-gate 
CMOS pair of P- and N-channel transistors with associated 
guard rings. Guard rings are necessary in metal-gate proc- 
essing to prevent leakage currents between the sources 
and drains of separate transistors. The starting material is 
an N- type silicon substrate covered by a thin layer of ther- 
mally grown silicon dioxide (SiOa) {Figure 1). Silicon dioxide, 
also called oxide acts as both a mask for certain processing 
steps and a dielectric insulator. Figure 2 shows 


the addition of a lightly doped P- well in which the N-chan- 
nel transistors and P + guard rings will later be located. The 
P- well is Ion Implanted into the substrate. A thin layer of 
oxide allows ions to be implanted through it, while a thicker 
oxide will block ion implantation. 

Next, the oxide over the P- well is stripped, and a new 
layer of oxide is grown. Following this, holes are etched into 
the oxide where the P+ source, drain, and guard ring diffu- 
sions shall occur. The P+ regions are diffused, and then 
additional oxide is grown to fill the holes created for diffu- 
sion {Figures 3, 4, and 5). The following step is to cut holes 
in the oxide to diffuse the N-channel sources, drains and 
guard bands. Then oxide is again thermally grown {Figures 6 
and 7). 

In the following step, the composite mask is created by 
again cutting holes in the oxide. This defines the areas 
where contacts and transistor gates will occur {Figure 5). A 
thin layer of gate oxide is grown over these regions {Figure 
9), and alignment of this to the source and drain regions is a 
critical step. If the gate oxide overlaps the source or drain, 
this will cause additional parasitic capacitance. 

Contacts to transistor sources and drains are cut into the 
thin oxide where appropriate {Figure 10), and then the Inter- 
connect metal is deposited {Figure 1 1). Depositing the met- 
al over the gate areas is also a critical step, for a misalign- 
ment will cause extra unwanted overlap capacitance. Figure 
12 illustrates the final step in processing, which is to deposit 
an insulating layer of silicon dioxide over the entire surface 
of the integrated circuit. 


Si02 



FIGURE 1. Initial Oxidation, Thermally Grown Silicon 
Dioxide Layer on Silicon Substrate Surface 


Si02 



TL/L/5044-1 


FIGURE 2. P- Mask and Formation of P- Well Tub in 
Which N-Channei Devices Will Be Located 


2-94 




SiO? 



FIGURE 3. P- Well Oxidation, Thermaliy Grown Siiicon 
Dioxide Layer Over P- Well Area 



FIGURE 4. P + Mask and Formation of Low Resistance P + Type Pockets In 
P- Well and N-Substrate 



FIGURE 5. P + Oxidation, Thermally Grown Siiicon 
Dioxide Layer Over P-f Type Pockets . 



FIGURE 7. N + Oxidation, Thermally Grown Silicon 
Dioxide Layer Over N + Type Pockets 


2 


TL/L/5044-2 


TL/L/5044-3 


2-95 


AN-310 






Silicon-Gate CMOS Processing 

The silicon-gate CMOS process starts with the same two 
steps as the metal-gate process, yielding an N - substrate 
with an ion-implanted P- well {Figures 13 and 14). That, 
however, is where the similarity ends. Next, the initial oxide 
is stripped, and another layer of oxide, called pad oxide, is 
thermally grown. Also, a layer of silicon nitride is deposited 
across the surface of the wafer {Figure 15). The nitride pre- 
vents oxide growth on the areas it covers. Thus, in Figure 
16, the nitride is etched away wherever field oxide is to be 
grown. The field oxide is a very thick layer of oxide, and It is 
grown everywhere except in the transistor regions {Figure 
17). As an oxide grows in silicon, it consumes the silicon 
substrate beneath it and combines it with ambient oxygen to 
produce silicon dioxide. Growth of this very thick oxide 
causes the oxide to be recessed below the surface of the 
silicon substrate by a significant amount. A recessed field 
oxide eliminates the need for guard ring diffusions, because 
current cannot flow through the field oxide, which complete- 
ly isolates each transistor from every other transistor. 

The next step is to deposit a layer of polycrystalline silicon, 
also called poly, which will form both the gate areas and a 
second layer of interconnect {Figure 18). The poly is then 
etched, and any poly remaining becomes a gate if it is over 
gate oxide, and interconnect if it is over field oxide. A new 
layer of oxide is grown over the poly, which will act as an 
Insulator between the poly and the metal interconnect {Fig- 
ure 19). The poly over the transistor areas is not as wide as 
the gate oxide. This allows the source and drain diffusions 
to be ion implanted through the gate oxide. The poly gate 
itself, along with the field oxide. Is used as a mask for im- 
plantation. Therefore, the source and drain implants will au- 
tomatically be aligned to the gate poly, which is what makes 
this process a self-aligned gate process {Figure 20). 

Figure 21 illustrates the steps of cutting contacts into the 
insulating layer of oxide, so the metal may be connected to 
gate and field poly, as well as to source and drain implants. 
A layer of metal is deposited across the entire wafer, and is 
etched to produce the desired interconnection. Finally, as in 
metal-gate processing, an insulating layer of oxide is depos- 
ited onto the wafer {Figure 22). 

Advantages of Silicon-Gate Processing 

There are three major ways in which silicon-gate processing 
reduces parasitic capacitance: recessed field oxide, lower 
gate overlap capacitance, and shallower junction depths. 
Figures 23 and 24 are cross sections of metal gate and 
silicon gate CMOS circuits, respectively. These figures show 
the parasitic on-chip capacitances (Ci through C 4 ) for each 
type of process. 

The N + and P+ source and drain regions, as well as guard 
ring regions, in the metal-gate process, have two capaci- 
tances associated with them: periphery and area capaci- 
tances (C 2 and Ci). These capacitances are associated 
with the diode junctions between the P + regions and the 
N- substrate, as well as the N+ regions and P- well. The 
finer line widths of silicon-gate CMOS, coupled with the 
shallower junction depths, act to decrease the size of these 
parasitic diodes. Capacitance is proportional to diode area, 


hence the diode area reduction results in a significantly re- 
duced parasitic capacitance in silicon-gate CMOS. 

Another origin of unwanted capacitance is the area where 
the gate overlaps the source and drain regions (C 4 ). The 
overlap Is much larger in metal-gate processing than in sili- 
con-gate CMOS. This is due to the fact that the metal-gate 
must be made wider than the channel width to allow for 
alignment tolerances. In silicon-gate processing, since the 
gate acts as the mask for the iop implantation of the source 
and drain regions, there is no alignment error, which results 
in greatly reduced overlap. 

How does the use of polysilicon gates increase the gain of a 
MOSFET? Polysilicon may be etched to finer line widths 
than metal, permitting the fabrication of transistors with 
shorter gate lengths. The equation that describes the gain 
of a MOSFET is shown below: 

I = [(Gate Voltage) -(Threshold Voltage )] 2 

Thus, a decrease in gate length will cause an increase in 
current drive capability. This, in turn, will allow the transistor 
to charge a capacitance more rapidly, therefore increasing 
the gain of the transistor. Also, the gate oxide is thinner for 
the silicon-gate CMOS process. A thinner gate oxide in- 
creases the Beta term in the equation, which further in- 
creases gain. Finally, although it is not apparent from the 
processing cross sections, the transistor threshold (turn on) 
voltage is lower. This is accomplished by the use of ion 
implants to adjust the threshold. 

There is one more advantage of silicon-gate processing that 
should be noted: the polysilicon provides for an additional 
layer of interconnect. This allows three levels of Intercon- 
nect, which are metal, polysilicon, and the N+ and P+ ion- 
implanted regions. Having these three levels helps to keep 
the die area down, since much die area is usually taken up 
by Interconnection. 

When all these advantages are summed up, the result Is a 
CMOS technology that produces devices as fast as the 
equivalent LSTTL device. Figure 25 illustrates a comparison 
between the MM74HC00 buffered NAND gate and the 
MM74C00, CD4011B, and DM74LS00 NAND gates. The 
MM74HC00 is about an order of magnitude faster than the 
CD4011B buffered NAND gate, and about 5 times faster 
than the unbuffered MM74C00, at 15 pF. As load capaci- 
tance increases, the speed differential between metal-gate 
and silicon-gate CMOS increases, with the MM74HC00 op- 
erating as fast as the DM74S00 at any load capacitance. 

Summary 

Polycrystalline silicon-gate CMOS has many advantages 
over metal-gate CMOS. It Is faster because on-chip parasitic 
capacitances are reduced and transistor gains are in- 
creased. This is due mainly to a recessed field oxide and a 
self-aligned gate process. Transistor gains are increased by 
decreasing transistor lengths and threshold voltages, and 
increasing beta. Polysilicon also allows for an extra layer of 
interconnect, which helps to keep die area down. 


2-97 


AN-310 




AN-310 




FIGURE 14. Ion-Implanted P- Tub In Which N-Channel 
Devices Will Be Located 


PAD OXIDE nitride 



FIGURE 15. Initial Oxide Is Stripped, Pad Oxide Is Thermally Grown, and a Layer of Sil- 
icon Nitride Is Deposited Across the Surface of the Wafer 



TL/L/5044-16 


2-98 







PAD OXIDE NITRIDE 



FIGURE 17. Field Oxide Is Thermally Grown. The Nitride 
Acts as a Barrier to Oxidetarowth 


GATE OXIDE POLY 



FIGURE 18. Nitride is Stripped, Pad Oxide Is Stripped Over Transistor Areas and a 
Thin Gate Oxide Is Grown Poiycrystaiiine Silicon Is Deposited 


INTERCONNECT 



FIGURE 19. Polysilicon Layer is Etched to Provide Gate and Interconnect Poly Areas. 
New Layer of Oxidation is Grown 


TL/L/5044-8 


2 


TL/L/5044-9 


2-99 


AN-310 





AN-31 


N+ SOURCE 
AND DRAIN 
REGIONS 


P+ SOURCE 
AND DRAIN 
REGIONS 


GATE OXIDE 
INTERCONNECT \ 
POLY \ 


V INSULATING 
\ OXIDE 


field ) f 

OXIDE / N+ 


FIELD OXIDE 


IN “SUBSTRATE I 


FIGURE 20. N + and P + Source and Drain Regions Are Ion Implanted, and the 
Reoxidation Is Grown Thicker to Form an insuiating Layer 


INTERCONNECT 
POLY 


INSULATING 
OXIDE 




FIELD OXIDE 




FIGURE 21. Contact Openings Are Cut in the Insuiating Oxide, and a Layer of 
Metaiization Is Deposited Across the Entire Wafer 


METAL GATE VAPOX 


FIELD i 

OXIDE / N+ 


FIELD OXIDE 


FIELD 
P+ \ OXIDE 


IN “SUBSTRATE! 


FIGURE 22. Metal Mask Is Etched to Provide interconnect. Vapox (Si02) Is Deposited 
Over Entire Surface of Wafer 


2-100 





FIGURE 23. Cross Section of Metal Gate CMOS Process 
Showing Parasitic On-Chip Capacitances 


METAL GATE wADnY 



TL/L/5044-12 


FIGURE 24. Cross Section of Silicon Gate CMOS Process Showing Parasitic 
On-Chip Capacitances 



20 40 60 80 100 120 140 160 


LOAD CAPACITANCE— pF 

TL/L/5044-13 

FIGURE 25. Propagation Delay vs. Load Capacitance 
for 2-Input NANDGate 



2-101 


AN-310 



AN-313 


DC Electrical 
Characteristics 
of MM54HC/MM74HC High- 
Speed CMOS Logic 

The input and output characteristics of the MM54HC/ 
MM74HC high-speed CMOS logic family were conceived to 
meet several basic goals. These goals are to provide input 
current and voltage requirements, noise immunity and qui- 
escent power dissipation similar to CD4000 and MM54C/ 
MM74C metai-gate CMOS logic and output current drives 
similar to low power Schottky TTL. In addition, to enable 
merging of TTL and HC-CMOS designs, the MM54HCT/ 
MM74HCT sub family differs only in their input voltage re- 
quirements, which are the same as TTL, to ease interfacing 
between logic families. 

In order to familiarize the user with the MM54HC/MM74HC 
logic family, its input and output characteristics are dis- 
cussed in this application note, as well as how these char- 
acteristics are affected by various parameters such as pow- 
er supply voltage and temperature. Also, for those users 
who have been designing with metal-gate CMOS and TTL 
logic, notable differences and features of high-speed CMOS 
are compared to those logic families. 

A Buffered CMOS Logic Family 

The MM54HC/MM74HC is a “buffered” logic family like the 
CD4000B series CMOS. Buffering CMOS logic merely de- 
notes designing the IC so that the output is taken from an 
inverting buffer stage. For example, the internal circuit im- 
plementation of a NAND gate would be a simple NAND fol- 
lowed by two inverting stages. An unbuffered gate would be 
implemented as a single stage. Both are shown in Figure 1. 
Most MSI logic devices are inherently buffered because 
they are inherently multi-stage circuits. Gates and similar 


vcc vcc vcc vcc 




. FIGURE 1. Schematic Diagrams of (a) Unbuffered and 
(b) Buffered NAND Gate 


National Semiconductor 
Application Note 313 
Larry Wakeman 
June 1983, 


small circuits yield the greatest improvement in perform-- 
ance by buffering. 

There are several advantages to buffering this high-speed 
CMOS family. By using a standardized buffer, the output 
characteristics for all devices are more easily made identi- 
cal. Multi-stage gates will have better noise Immunity due to 
the higher gain caused by having several stages from input 
to output. Also, the output Impedance of an unbuffered gate 
may change with input logic level voltage and input logic 
combination, whereas buffered outputs are unaffected by 
input conditions. 

Finally, single stage gates implemented in MM54HC/ 
MM74HC CMOS would require large transistors due to the 
large output drive requirements. These large devices would 
have a large input capacitance associated with them. This 
would affect the speed of circuits driving into an unbuffered 
gate, especially when driving large fanouts. Buffered gates 
have small input transistors and correspondingly small input 
capacitance. 

One may think that a major disadvantage of buffered circuits 
would be speed loss. It would seem that a two or three 
stage gate would be two to three times slower than a buff- 
ered one. However, internal stages are much faster than the 
output stage and the speed lost by buffering is relatively 
small. 

The one exception to buffering is the MM54HCU04/ 
MM74HCLI04 hex inverter which is unbuffered to enable its 
use in various linear and crystal oscillator applications. 



2-102 



CMOS Input Voltage Characteristics 

As mentioned before, MM54HC/MM74HC standard input 
levels are similar to metal-gate CMOS. This enables the 
high-speed logic family to enjoy the same wide noise margin 
of CD4000 and MM54C/MM74C logic. With Vcc = 5V these 
input levels are 3.5V for minimum logic “1” (V|h) and 1.0V 
for a logic “0” (V|l). The output levels when operated at 
Vcc = 5V±10% and worst case input levels, are specified 
to be Vcc“0.1 or 0.1V. The output levels will actually be 
within a few millivolts of either Vcc or ground. 

When operated over the entire supply voltage range, the 
input logic levels are: V|h = 0.7Vcc and V|i_=0.2Vcc- Figure 
2 illustrates the input voltage levels and the noise margin of 
these circuits over the power supply range. The shaded 
area indicates the noise margin which is the difference be- 
tween the input and output logic levels. The logic “1” noise 
margin is 29% of Vcc and the logic “0” noise margin is 
19% of Vcc- Also shown for comparison are the 54LS/ 
74LS input levels and noise margins over their supply range. 
These input levels are specified on individual data sheets at 
Vcc = 2.0V, 4.5V, 6.0V. At 2.0V the input levels are not quite 
0-7(Vcc) and 0.2(Vcc) as at low voltages transistor turn on 
thresholds become significant. This is shown in Figure 2. 


V 0 H= Vcc -0.1V 


V|H = 0.7Vcc 



2 3 4 5 

POWER SUPPLY VOLTAGE (V) 

TL/F/5052-3 

FIGURE 2. Worst Case Input and Output Voltages Over 
Operating Supply Range for “HC” and “LS” Logic 


The input and output logic voltages and their behavior with 
temperature variation is determined by the input to output 
transfer function of the logic circuit. Figure 3a shows the 
transfer function of the MM54HC00/MM74HC00 NAND 
gate. As can be seen, the NAND gate has Vcc and ground 
output levels and a very sharp transition at about 2.25V. 
Thus, good noise immunity is achieved, since input noise of 
a volt or two will not appear on the output. The transition 
point is also very stable with temperature, drifting typically 
50 or so millivolts over the entire temperature range. As a 
comparison, the transfer function for a 54LS00/74LS00 is 
plotted in Figure 3b. LSTTL output transitions at about 1.1V 
and the transition region varies several hundred millivolts 
over the temperature range. Also, since the transition region 
is closer to the low logic level, less ground noise can be 
tolerated on the input. 

In typical systems, noise can be capacitively coupled to the 
signal lines. The amount of voltage coupled by capacitively 
induced currents is dependent on the impedance of the out- 
put driving the signal line. Thus, the lower the output imped- 
ance the lower the induced voltage. High-speed CMOS of- 
fers improved noise immunity over CD4000 in this respect 
because Its output impedance Is one tenth that of CD4000 
and so it is about 7 times less susceptible to capacitively 
induced current noise. 



1.0 2.0 3.0 4.0 5.0 

INPUT VOLTAGE TL/F/5052-4 

(a) 



1.0 2.0, 3.0 4.0 5.0 

INPUT VOLTAGE TL/F/5052-5 

(b) 

FIGURE 3. Input/Output Transfer Characteristics for (a) 
’HCOO and (b) ’LSOO Nand Gate 


The MM54HCT/MM74HCT sub-family of MM54HC/ 
MM74HC logic provides TTL compatible input logic voltage 
levels. This will enable TTL outputs to be guaranteed to 
correctly drive CMOS inputs. An incompatibility results be- 
cause TTL outputs are only guaranteed to pull to a 2.7V 
logic high level, which is not high enough to guarantee a 
valid CMOS logic high input. To design the entire family to 
be TTL compatible would compromise speed, input noise 
immunity and circuit size. This sub-family can be used to 
interface sub-systems implemented using TTL logic to 
CMOS sub-systems. The input level specifications of 
MM54HCT/MM74HCT circuits are the same as LSTTL. Min- 
imum input high level is 2.0V and the maximum low level is 
0.8V using a 5V± 10% supply. 

A fairly simple alternative to interfacing from LSTTL is to tie 
a pull-up resistor from the TTL output to Vcc. usually 
4-10 ka. This resistor will ensure that TTL will pull up to 
Vcc- (See Interfacing MM54HC/MM74HC High-Speed 
CMOS Logic application note.) 

High-Speed CMOS Input Current and Capacitance 

Both standard “HC” and TTL compatible “HCT” circuits 
maintain the ultra low Input currents Inherent in CMOS cir- 
cuits when CMOS levels are applied. This current is typically 
less than a nanoamp and is due to reverse leakages of the 
input protection diodes. Input currents are so small that they 
can usually be neglected. Since CMOS inputs present es- 
sentially no load, their fanout is nearly infinite. 




2-103 


AN-313 




AN-313 


Each CMOS input has some capacitance associated with it, 
as do TTL inputs. This capacitance is typically 3-5 pF for 
MM54HC/MM74HC, and Is due to package, input protection 
diode, and transistor gate capacitances. Capacitance infor- 
mation is given In the data sheets and is measured with all 
pins grounded except the test pin. This method Is used be- 
cause It yields a fairly conservative result and avoids capaci- 
tance meter and power supply ground loops and decoupling 
problems. Figure 4 plots typical input capacitance versus 
input voltage for HC-CMOS logic with the device powered 
on. The small peaking at 2.2V is due to Internal Miller feed- 
back capacitance effects. 

When comparing MM54HC/MM74HC input currents to TTL 
logic, 54LS/74LS does need significantly more input cur- 
rent. LSTTL requires 400 ju-A of current when a logic low is 
applied and 40 \ifK in the high state which is significantly 
more than the worst case 1 jaA leakage that MM54HC/ 
MM74HC has. 


10.0 

9.0 

u. 8.0 

i 7.0 

I 6.0 

i 5.0 
§ 4.0 

I 3.0 

z 

“ 2.0 

1.0 

1.0 2.0 3.0 4.0 5.0 

INPUT VOLTAGE 

TL/F/5052-6 

FIGURE 4. Input Capacitance vs. Input Voltage 
for a Typical Device 



MM54HC/MM74HC Power Supply Voltage and 
Quiescent Current 

Figure 5 compares the operating power supply range of 
high-speed CMOS to TTL and metal-gate CMOS. As can be 
seen, MM54HC/MM74HC can operate at power supply volt- 
ages from 2-6V. This range is narrower than the 3-1 5V 
range of CD4000 and MM54C/MM74C CMOS. The narrow- 
er range is due to the silicon-gate CMOS process employed 
which has been optimized to attain high operating frequen- 
cies at Vcc=5V. The 2-6V range is however much wider 
than the 4.5V to 5.5V range specified for TTL circuits, and 
guaranteeing operation down to 2V is useful when operating 
CMOS off batteries in portable or battery backup applica- 
tions. 

The quiescent power supply current of the high-speed’ 
CMOS family is very similar to CD4000 and MM54C/ 
MM74C CMOS. When CMOS circuits are not switching 
there is no current path between Vcc and ground, except 
for leakage currents which are typically much less than 
1 ;xA. These are due to diode and transistor leakages. 



CMOS 


TL/F/5052-7 

FIGURE 5. Comparison of Supply Range for 
“HC”, “LS” and Metal-Gate 



0 25 50 75 100 125 

TEMPERATURE-°C 

TL/F/5052-8 

FIGURE 6. Typical Quiescent Supply Current 
Variation with Temperature 


Figure 6 illustrates how this leakage increases with temper- 
ature by plotting typical leakage current versus temperature 
for an MSI and SSI device. As a result of this temperature 
dependence, there is a set of standardized Ice specifica- 
tions which specify higher current at elevated temperatures. 
A summary of these specifications are shown in Table I. 


TABLE I. Standardized Iqc Specifications for 
MM54HC/MM74HC Logic at 25°C, 85°C and 125°C at 
Vcc = 60 V 


Temperature 

Gates 

Flip-Flops 

MSI 

25°C 

2jaA 

4 jliA 

8 jaA 

85°C 

20 /xA 

40 jixA 

80 jllA 

125'’C 

40 jllA 

80 fxA 

160 fxA 


2-104 




Output Characteristics 

One of the prime advantages of MM54HC/MM74HC over 
metal-gate CMOS (besides speed) is the output drive cur- 
rent, which is about ten times CD4000 or MM54C/MM74C 
logic. The larger output current enables high-speed CMOS 
to directly drive large fanouts of 54LS/74LS devices, and 
also enables HC-CMOS to more easily drive large capaci- 
tive loads. This improvement in output drive is due to a vari- 
ety of enhancements provided by the silicon-gate process 
used. The basic current equation for a MOSFET is: 

I = (Beta)(Width/Length)((Vg-Vt)Vd-0.5(V§)) 

Where Vg is the transistor gate voltage, Vt is the transistor 
threshold voltage, and Vd is the transistor drain voltage 
which is equivalent to the circuit output voltage. This CMOS 
process, when compared to metal-gate CMOS, has in- 
creased transistor gains, Beta, and lower threshold volt- 
ages, Vt. Also, improved photolithography has reduced the 
transistor lengths, and wider transistors are also possible 
because of tighter geometries. 

Figure 7 compares the output high and low current specifi- 
cations of MM74HC, 74LS and metal-gate CMOS for stan- 
dard device outputs. High-speed CMOS has worst case out- 
put low current of 4 mA which is similar to low power 
Schottky TTL circuits, and offers symmetrical logic high and 
low currents as well. In addition, CMOS circuits whose func- 
tions make them ideal for use driving large capacitive loads 
have a larger output current of 6 mA. For example, these 
bus driver outputs are used on the octal flip-flops, latches, 
buffers, and bidirectional circuits. 


Table II summarizes the various output current specifica- 
tions for MM54HC/MM74HC CMOS along with their equiva-^ 
lent LSTTL fanouts. As Table II shows, the output currents 
of the MM54HC/MM74HC devices are derated from the 
MM74HC devices. The derating is caused by the decrease 
in current drive of the output transistors as temperature is 
increased. To show this, Figure 8 plots typical output source 
and sink currents against temperature for both standard and 
bus driver circuits. This variation is similar to that found in 
metal-gate CMOS, and so the same -0.3% per °C derating 
that is used to approximate temperature derating of CD4000 
and MM54C/MM74C can be applied to 54HC/74HC. As an 
example, the approximate worst case 25°C current drive 
one would expect by using the 4 mA 85°C data sheet num- 
ber would be about 4 mA at Vqut = 0-26V, and this is what 
is specified in the device data sheets. 



-60 -20 20 60 100 140 

TEMPERATURE-°C TL/F/5052-10 

P) (a) 



74HC-CM0S 74LSTTL CD4000 OR 
74C-CM0S 


TL/F/5052-9 

FIGURE 7. Comparison of 74HC, 74LS and CD4000/ 74C 
Output Drive Currents, Iqh and Iql 



-60 -20 20 60 100 140 


TEMPERATURE-^C TL/F/5052-11 


(b) 


FIGURE 8. Typical Output (a) Source and (b) Sink 
Current Temperature for Standard and Bus Outputs 


TABLE 11. Data Sheet Output Current Specifications 
for MM54HC/MM74HC Logic 


Device 

Vcc = 4.5V 

Output High 
Current 

Output Low 
Current 

LSTTL 

Fanout 

Standard 54HC 

4.0 mA (Vout = 3.7V) 

4.0 mA(VouT=0.4V) 

10 

Bus Driver 54HC 

6.0 mA (Vout=3.7V) 

6.0 mA {Vout=0-4V) 

15 

Standard 74HC 

4.0 mA (Vqut = 3.94) 

4.0 mA (Vqut = 0.33V) 

10 

Bus 74HC 

6.0 mA (Vqut =3.94) 

6.0 mA (Vqut = 0.33V) 

15 



2-105 


AN-313 




AN-313 


The data sheet specifications for output current are mea- 
sured at only one output voltage for either source or sink 
current for each of three temperature ranges, room, com- 
mercial, and military. The outputs can supply much larger 
currents if larger output voltages are allowed. This is shown 
in Figures 9 and 10, which plot output current versus output 
voltage for both N-channel sink current and P-channel 
source current. Both standard and bus driver outputs are 
shown. For example, a standard output would typically sink 
20 mA with Vql = 1 V, and typically capable of a short circuit 
current oj 50 mA. 



0 1.0 2.0 3.0 4.0 5.0 


OUTPUT VOLTAGE 

(a) TL/F/5052-12 



OUTPUT VOLTAGE 

(b) TL/F/5052-13 


The output current and voltage characteristics of a logic cir- 
cuit determine how well that circuit will switch its output 
when driving capacitive loads and transmission lines. The 
more current available, the faster the load can be switched. 
In order for HC-CMOS to achieve LSTTL performance, the 
outputs should have characteristics similar to LSTTL. This 
similarity is illustrated in Figure 11 by plotted typical LSTTL 
and HC-CMOS output characteristics together. 

As the supply voltage is decreased, the output currents will 
decrease. Figure 12a plots the output sink current versus 
power supply voltage with a 0.4V output voltage, and Figure 
12b plots output source current against power supply with 
an output voltage of Vqc-0.8V. It is Interesting to note that 
MM54HC/MM74HC powered at Vcc = 3V, typically, will still 
drive 1 0 LSTTL inputs (T = 25®C). 

Absolute Maximum Ratings 

Absolute maximum ratings are a set of guidelines that de- 
fine the limits of operation for the MM54HC/MM74HC logic 
devices. To exceed these ratings could cause a device to 
malfunction and permanently damage Itself. These limits 
are tabulated in Table III, and their reasons for existing are 
discussed below. 

The largest power supply voltage that should be applied to a 
device is 7V. If larger voltages are applied, the transistors 
will breakdown, or "punch through”. The smallest voltage 
that should be applied to a MM54HC/MM74HC circuit is 
— 0.5V. If more negative voltages are applied, a substrate 
diode would become forward biased. In both cases large 
currents could flow, damaging the device. 


FIGURE 9. Typical P-Channel Output Source Current vs. 
Output Voltage for (a) Standard and 
(b) Bus Outputs 



0 1.0 2.0 3.0 4.0 5.0 

OUTPUT VOLTAGE 

(a) TL/F/5052-14 



0 1.0 2.0 3.0 4.0 5.0 

OUTPUT VOLTAGE 

(b) TL/F/5052-15 


FIGURE 10. Typical N-Channel Output Sink Current vs. Output Voltage 
for (a) Standard and (b) Bus Outputs 


2-106 






TL/F/5052-17 


FIGURE 1 1. Comparison of Standard LSTTL and HC-CMOS Output 
(a) Source and (b) Sink Currents 



SUPPLY VOLTAGE 


SUPPLY VOLTAGE 


(a) 


TL/F/5052-18 


(b) 


TL/F/5052-19 


FIGURE 12. Output (a) Sink and (b) Source Current 
Variation with Power Supply 


High-speed CMOS inputs should not have DC voltages ap- 
plied to them that exceed Vcc or go below ground by more 
than 1.5V. To do so would forward bias input protection 
diodes excessive currents which may damage them. In ac- 
tuality the diodes are specified to withstand 20 mA current. 
Thus the input voltage can exceed 1 .5V if the designer limits 
his input current to less than 20 mA. The output voltages 
should be restricted to no less than -0.5V and no greater 
than Vcc + 0.5V, or the current must be limited to 20 mA. 
The same limitations on the input diodes apply to the out- 
puts as well. This includes both standard and TRI-STATE® 
outputs. These are DC current restrictions. In normal high 
speed systems, line ringing and power supply spiking una- 
voidably cause the inputs or outputs to glitch above these 
limits. This will not damage these diodes or internal circuitry. 
The diodes have been specifically designed to withstand 
momentary transient currents that would normally occur in 
high speed systems. 


Additionally, there is a maximum rating on the DC output or 
supply currents as shown in Table 3. This is a restriction 
dictated by the current capability of the integrated circuit 
metal traces. Again this is a DC specification and it is ex- 
pected that during switching transients the output and sup- 
ply currents could exceed these specifications by several 
times these numbers. 

For most CD4000 and MM54C/MM74C CMOS operating at 
Vcc = 5V, the designer does not need to worry about exces- 
sive output currents, since the output transistors usually 
cannot source or sink enough current to stress the metal or 
dissipate excessive amounts of power. The high-speed 
CMOS devices do have much improved output characteris- 
tics, so care should be exercised to ensure that they do not 
draw excessive currents for long durations, i.e., greater than 
0.1 seconds. It is also important to ensure that internal dissi- 
pation of a circuit does not exceed the package power dissi- 
pation. This will usually only occur when driving large cur- 
rents into small resistive loads. 


TABLE III. Absolute Maximum Ratings for 
MM54HC/MM74HC CMOS Logic 


Symbol 

Parameter 

Value 

Unit 

Vcc 

DC Supply Voltage 

-0.5 to 7.0 

V 

V|N 

DC input Voltage 

— 1 .5 to Vcc^F 1 -5 

V 

Vqut 

DC Output Voltage 

— 0.5 to VccT 0-5 

V 

•out 

DC Current. Per Output Pin 

Standard 

±25 

mA 

Bus Driver 

±35 

mA 

•cc 

DC Vcc O'” Ground Current 

Standard 

±50 

mA 

Bus Driver 

±70 

mA 

•iK. lOK 

I Input or Output Diode Current 

±20 

mA 



2-107 


AN-313 




AN-313 


MM54HC/MM74HC Input Protection 

As with any circuits designed with MOS transistors “HC” 
logic must be protected against damage due to excessive 
electrostatic discharges, which can sometimes occur during 
handling and assembly procedures. If no protection were 
provided, large static voltages appearing across any two 
pins of a MOS IC could cause damage. However, t^e new 
input protection which takes full advantage of the “H'C” sili- 
con-gate process has been carefully designed to reduce the 
susceptibility of these high-speed CMOS circuits to oxide 
rupture due to large static voltages. In conjunction with the 
input protection, the output parasitic diodes also protect the 
circuit from large static voltages occuring between any in- 
put, output, or supply pin. 

Figure 13 shows a schematic of the input protection net- 
work employed. The network consists of three elements: a 
poly-silicon resistor, a diode connected to Vcc. and a dis- 
tributed diode-resistor connected to ground. This high- 
speed process utilizes the poly resistor to more effectively 
isolate the Input diodes than the diode-resistor used in met- 
al-gate CMOS. This resistor will slow down incoming tran- 
sients and dissipate some of their energy. Connected to the 
resistor are the two diodes which clamp the input spike and 


prevent large voltages from appearing across the transistor. 
These diodes are larger than those used In metal-gate 
CMOS to enable greater current shunting and make them 
less susceptible to damage. The input network is ringed 
by Vcc and ground diffusions, which prevent substrate 
currents caused by these transients from affecting other 
circuitry. 

The parasitic output diodes {Figure 13) that Isolate the out- 
put transistor drains from the substrate are also important in 
preventing damage. They clamp large voltages that appear 
across the output pins. These diodes are also ringed by Vcc 
and ground diffusions to again shunt substrate currents, 
preventing damage to other parts of the circuit. 

Summary 

The MM54HC/MM74HC, because of many process en- 
hancements, does provide a combination of features from 
54LS/74LS and metal-gate CMOS logic families. High- 
speed CMOS gives the designer increased flexibility in pow- 
er supply range over LSTTL, much larger output drive than 
CMOS has previously had, wider noise immunity than 54LS/ 
74LS, and low CMOS power consumption. 



FIGURE 13. Schematic Diagram of Input and Output Protection Structures 


2-108 





Interfacing to MM54HC/ 
MM74HC High-Speed CMOS 
Logic 

On many occasions it might be necessary to interface 
MM54HC/MM74HC logic to other types of logic or to some 
other control circuitry. HC-CMOS can easily be interfaced to 
any other logic family including 54LS/74LS TTL, MM54C/ 
MM74C, CD4000 CMOS and 10,000 ECL logic. Logic inter- 
facing can be sub-divided into two basic categories: inter- 
facing circuitry operating at the same supply voltage and 
interfacing to circuitry operating on a different voltage. In the 
latter case, some logic level translation is usually required, 
but many easily available circuits simplify this task. Usually, 
both instances require little or no external circuitry. 

interfacing Between TTL and MM54HC/MM74HC Logic 

This high-speed CMOS family can operate from 2-6V, how- 
ever, in most applications which interface to TTL, both logic 
families will probably operate off the same 5V TTL supply. 
The interconnection can be broken down into two cate- 
gories: TTL outputs driving CMOS inputs, and CMOS out- 
puts driving TTL inputs. In both cases the interface is very 
simple. 

In the first case, TTL driving HC, there are some minor dif- 
ferences in TTL specifications for totem-pole outputs and 
high-speed CMOS Input specifications. The TTL output low 
level is completely compatible with the MM54HC/MM74HC 
input low, but TTL outputs are specified to have an output 
high level of 2.4V (2.7V for LSTTL). High-speed CMOS’s 


National Semiconductor 
Application Note 314 
Larry Wakeman 
June 1983 


logic “1 ” input level is 3.5V (Vcc = 5.0V), so TTL is not guar- 
anteed to pull a valid CMOS logic “1 ” level. If the TTL circuit 
is only driving CMOS, its output voltage is usually about 
3.5V. HC-CMOS typically recognizes levels greater than 3V 
as a logic high, so in most instances TTL can drive 
MM74HC/MM54HC. 

To see why TTL does not pull up further, Figure 1a shows a 
typical standard TTL gate’s output schematic. As the output 
pulls up, it can go no higher than two diode voltage drops 
below Vcc due to Q2 and D2. So when operating with a 5V 
supply, the TTL output cannot, go much higher than about 
3.5V. Figure 1b shows an LSTTL gate, which has an output 
structure formed by Q2 and Q4. As the LSTTL output goes 
high, these two transistors cannot pull higher than two base- 
emitter voltage drops below Vcc. ^nd, as above, the output 
cannot go much higher than 3.5V. If the output of either the 
LSTTL or TTL gate is loaded or the off sink transistor has 
some collector leakages, the output voltage will be lower. 
Many LSTTL and ALSTTL circuits take R2 of Figure 2b and 
instead of connecting it to ground, it is connected to the 
output. This enables the TTL output to go to 4.3V 
(Vcc = 5.0V) which is more than adequate to drive CMOS. A 
simple measurement of open circuit Voh can verify this cir- 
cuit configuration. 





" TL/F/5053-1 

(a) (b) 

FIGURE 1. Schematic Diagrams for Typical (a) Standard and 
(b) Low Power Schottky TTL Outputs 


2-109 


AN-314 




AN-314 


Since LSTTL specifications guarantee a 2.7V output high 
level instead of a 3.5V output high, when designing to the 
worst case characteristics greater compatibility is some- 
times desired. One solution to increase compatibility is to 
raise the output high level on the TTL output by placing a 
pull-up resistor from the TTL output to Vcc. as shown in 
Figure 2. When the output pulls up, the resistor pulls the 
voltage very close to Vcc- The value of the resistor should 
be chosen based on the LSTTL and CMOS fanout of the LS 
gate. Figure 3 shows the range of pull-up resistors values 
versus LS fanout that can be used. For example, if an 
LSTTL device is driving only CMOS circuits, the resistor val- 
ue is chosen from the left axis which corresponds to a zero 
LSTTL fanout. 

A second solution Is to use one of the many MM54HCT/ 
MM74HCT TTL input compatible devices. These circuits 
have a specially designed input circuit that is compatible 
with TTL logic levels. Their Input high level is specified at 
2.0V and their input low is 0.8V with Vcc = 5.0V ±10%. 
Thus LS can be directly connected to HC logic and the extra 
pull-up resistors can be eliminated- The direct Interconnec- 
tion of the TTL to CMOS translators is shown in Figure 4. 

If TTL open collector outputs with a pull-up resistor are driv- 
ing MM54HC/MM74HC logic, there is no interface circuitry 
needed as the external pull-up will pull the output to a high 
level very close to Vcc- The value of this pull-up for LS 
gates has the same constraints as the totem-pole outputs 
and its value can be chosen from Figure 2 as well. The 
special TTL to CMOS buffers may also be used In this case, 
but they are not necessary. 



0 4 8 12 16 20 


LSTTL FANOUT 

TL/F/5053-2 

FIGURE 3. Range of Pull-Up Resistors for Low 
Power Schottkey TTL to CMOS Interface 


When MM54HC/MM74HC outputs are driving TTL inputs, 
as shown in Figure 5, there is no incompatibility. Both the 
high and low output voltages are compatible with TTL. The 
only restriction in high-speed CMOS driving TTL is the same 
fanout restrictions that apply when TTL is driving TTL. 



CMOS Inputs Using a Puii-Up Resistor 


2-110 





Vcc = 5V 



FIGURE 4. LSTTL Outputs Directly Drives MM54HCT/MM74HCT Logic 
Directly Which Can Interface to MM54HC/MM74HC 



FIGURE 5. High-Speed CMOS Can Directly Connect Up 
to LSTTL Within its Fanout Restrictions 


TL/F/5053-4 


2-111 


AN-314 




AN-314 


High-speed CMOS has much improved output drive com- 
pared to CD4000 and MM54C/MM74C metal-gate CMOS 
logic. Figure 6 tabulates the fanout capabilities for this fami- 
ly. MM54HC/MM74HC standard 'Outputs have a fanout ca- 
pability of driving 10 LSTTL equivalent load and MM74HC 
bus driver outputs can drive up to 15 LSTTL inputs. It is 
unlikely that greater fanouts will be necessary, but several 
gates can be paralleled to increase output drive. 

MM54HC/MM74HC and NMOS/HMOS Interconnection 

With the introduction of CMOS circuits that are speed-equiv- 
alent to LSTTL, these fast CMOS devices will replace much 
of the bipolar support logic for many NMOS and HMOS mi- 
croprocessor and LSI circuits. As a group, there Is no real 
standard set of input and output specifications, but most 
NMOS circuits conform to TTL logic input and output logic 
level specifications. 

NMOS outputs will typically pull close to Vcc- As with 
LSTtL, standard MM54HC/MM74HC CMOS inputs will 
typically accept NMOS outputs directly. However, to 
improve compatibility the MM54HCT/MM74HCT series of 
TTL compatible circuits may be used. These devices are 
particularly useful in microprocessor systems, since many 
of the octal devices are bus oriented and have pin-outs 
with inputs and outputs on opposite sides of the package. 
As with LSTTL, a second solution is to add a pull-up 
resistor between the NMOS output and Vcc- Both methods 
are shown in Figure 7. 

MM54HC/MM74HC outputs can directly drive NMOS in- 
puts. In fact, this situation is the same as if high-speed 
CMOS was driving itself. NMOS circuits have near zero in- 
put current and usually have input voltage levels that are 
TTL compatible. Thus MM54HC/MM74HC needs no addi- 
tional circuitry to drive NMOS and there is also virtually no 
DC fanout restriction. 

Interfacing High-Speed CMOS to MM54C/MM74C, 
CD4000 and CMOS-LSI 

MM54HC/MM74HC CMOS and metal-gate CMOS logic in- 
terconnection is trivial. When both families are operated for 


the same power supply, no interface circuitry is needed. 
MM54HC/MM74HC, CD4000 and MM54C/MM74C logic 
families are completely input and output logic level compati- 
ble. Since both families have very low Input currents, there 
is essentially no fanout limitations for either family. 

The same input and output compatibility of the HC-CMOS 
makes it also Ideal for use interfacing to CMOS-LSI circuits. 
For example, MM54HC/MM74HC can be directly connect- 
ed to the NSC800, and 80C48 microprocessors and other 
microCMOS products, as well as CMOS telecommunica- 
tions products. 

MM54HC/MM74HC to ECL Interconnection 

There may be some instances where an ECL logic system 
must be connected to high-speed CMOS logic. There are 
several possible methods to interconnect these families. 
Figure 8 shows one method which uses the 10125/10525 
ECL to TTL interface circuit to go from ECL to HC-CMOS 
logic and the 10124/10524 to connect CMOS outputs to 
ECL inputs. These devices allow the CMOS to operate with 
Vcc = 5V while the ECL circuitry uses a -5.2V supply. 

An alternate approach would be to operate the CMOS from 
the - 5.2V ECL supply as shown In Figure 9. Thus CMOS 
outputs could be directly connected to ECL inputs. 

Logic Interfaces Requiring Level Translation 

There are many instances when interfacing from one logic 
family to another that the other logic family will be operating 
from a different power supply voltage. If this is the case, a 
level translation must be accomplished. There are many dif- 
ferent permutations of up and down level conversions that 
may be required. A few of the. more likely ones are dis- 
cussed here. 


HC-CMOS Equivalent 
Fanouts 

LSTTL 

TTL 

S-TTL 

ALS-TTL 

Min 

Typ 

Min 

Typ 

Min 

Typ 

Min 

Typ 

Standard Output 
MM54HC/MM74HC 

10 

20 

2, 

4 

2 

4 

20 

40 

Bus Driver Output 
MM54HC/MM74HC 

15 

30 

4 

8 

3 

6 

30 

60 


FIGURE 6. Equivalent Fanout Capabilities of 
High-Speed CMOS Logic 


2-112 






NMOS-LSI 
CIRCUITS OR 
MICROPROCESSORS 


TTL INPUT 
COMPATIBLE CMOS 



HIGH-SPEED 
CMOS LOGIC 






. TL/F/5053 -6 


(a) 


5V 



TL/F/6053-7 


(b) 


FIGURE 7. Improved Compatibility NMOS to CMOS Connection Using 
(a) TTL Input Compatible Devices or (b) External Pull-Up Resistors 


2 - 






If MM54HC/MM74HC is operated in a battery back up appli- 
cation for a TTL system, high-speed CMOS may be operat- 
ed at Vqc = 2-3V and can be connected to 5V TTL CMOS 
operating at 3V can be directly connected to TTL since its 
input and output levels are compatible with TTL, and the 


TTL output levels are compatible with CMOS inputs, as 
shown in Figure 10. When high-speed CMOS is operated at 
2V, the TTL outputs will exceed the CMOS power supply 
and the CMOS outputs will just barely pull high enough to 
drive TTL, so some level translation will be necessary. 


VCC = 5V VCC=3V 



LSTTL LOGIC 


HC-CMOS LOGIC 


TL/F/5053-10 

(a) 


VCC = 3V VCC = 5V 



FIGURE 10. When HC-CMOS Is Operating At Vcc = 3V 
No Logic Level Conversion Circuitry Is Needed 



2-115 


AN-314 




AN-314 


CD4000 and MM54C/MM74C metal-gate CMOS logic can 
be operated over a wider supply range that MM54HC/ 
MM74HC, and because of this there will be instances when 
metal-gate CMOS and HC-CMOS will be operated off differ- 
ent supply voltages. Usually 9V to 1 5V CD4000 logic levels 


will have to be down converted to 5V high-speed CMOS 
levels. Figure 1 1 shows several possible down conversion 
techniques using either a CD4049, CD4050, MM54HC4049, 
MM54HC4050, or MM54C906. 


VCC = 5V 



FIGURE 11. CD4000 or 74C Series CMOS to HC-CMOS'Connection with Logic 
Level Conversion Using (a) Special Down Converters or (b) Open Drain CMOS 


2-116 



Since CMOS has a high input impedance, another possibili- 
ty is to use a resistor voltage divider for down level conver- 
sion as shown in Figure 12. Voltage dividers will, however, 
dissipate some power. 


Up conversion from MM54HC/MM74HC to metal-gate 
CMOS can be accomplished as shown in Figure 13. Here an 
MM54C906 open drain buffer with a pull-up resistor tied to 
the larger power supply is used. 



STANDARD CMOS LOGIC 


FIGURE 12. CMOS to “HC” CMOS Logic Level Translation 
Using Resistor Divider 



STANDARD CMOS LOGIC 


FIGURE 13. HC-CMOS to 004000 or 74C Series CMOS Connection with 
Logic Level Conversion Using an Open Drain CMOS Circuit 


2-117 



AN-314 


12V-24V 12V-24V 



FIGURE 14. Interfacing Between HC-CMOS and High Voltage Control Logic 


High Voltage and Industrial Control Interfaces 

On occasion, interfacing to industrial and automotive control 
systems may be necessary. If these systems operate within 
the metal-gate CMOS supply range, interfacing MM54HC/ 
MM74HC to them is similar to interfacing to CD4000 operat- 
ing at a higher supply. In rugged industrial environments, 
care may be required to ensure that large transients do not 
harm the CMOS logic. Figure 14 shows a typical connection 
to a high voltage system using diode clamps for input and 
output protection. 

The higher drive of HC-CMOS can enable direct connection 
to relay circuits, but additional isolation is recommended. 
Clamp diodes should again be used to prevent spikes gen- 
erated by the relay from harming the CMOS device. For 
higher current drive an external transistor may be used to 
Interface to high-speed CMOS. Both of these are shown in 
Figure 15. Also, the higher drive enables easy connection to 
SCR’s and other power control semiconductors as shown in 
Figure 16. 

Conclusion 

Interfacing between different logic families Is not at ail diffi- 
cult. In most instances, when no logic level translation be- 
tween is done, no external circuitry is needed to Intercon- 
nect logic families. Even though the wide supply range of 
MM54C/MM74C and CD4000 creates many possible logic 
level conversion interface situations, most are easily han- 
dled by employing a minimum of extra circuitry. Additionally, 
several special interface devices also simplify logic level 
conversion. 


VCC = 5V 



TL/F/5053-17 

FIGURE 15. Interfacing MM54HC/MM74HC to Relays 


110V 



TL/F/5053-18 

FIGURE 16. MM54HC/MM74HC Driving an SCR 


2-118 





AC Characteristics of 
MM54HC/MM74HC 
High-Speed CMOS 


National Semiconductor 
Application Note 317 
Larry Wakeman 
June 1983 



When deciding what circuits to use for a design, speed is 
most often a very important criteria. MM54HC/MM74HC is 
intended to offer the same basic speed performance as low 
power Schottky TTL while giving the designer the low power 
and high noise immunity characteristics of CMOS. In other 
words, HC-CMOS is about ten times faster than CD4000 
and MM54C/MM74C metal-gate CMOS logic. Even though 
HC-CMOS logic does have speeds similar to LSTTL, there 
are some differences in how this family’s speeds are speci- 
fied, and how various parameters affect circuit performance. 
To give the designer an idea of the expected performance, 
this discussion will include how the AC characteristics of 
high-speed CMOS are specified. This logic family has been 
specified so that in the majority of applications, the specifi- 
cations can be directly applied to the design. Since it is 
impossible to specify a device under all possible situations, 
performance variations with power supply, loading and tem- 
perature are discussed, and several easy methods for de- 
termining propagation delays in nearly any situation are also 
described. Finally, it Is useful to compare the performance 
of HC-CMOS to 54LS/74LS and to CD4000. 

Data Sheet Specifications 

Even though the speeds achieved by this high-speed CMOS 
family are similar to LSTTL, the input, output and power 
supply characteristics are very similar to metal-gate CMOS. 
Because of this, the actual measurements for various timing 
parameters are not done the same way as TTL. The 
MM54HCT/MM74HCT TTL input compatible circuits are an 
exception. 

Standard HC-CMOS AC specifications are measured at 
Vcc = 2.0V, 4.5V, 6.0V for room, military and commercial 
temperature ranges. Also HC is specified with LS equivalent 
supply (5.0V) and load conditions to enable proper compari- 
son to low power Schottkey TTL. Input signal levels are 
ground to Vcc with rise and fall times of 6 ns (10% to 90%). 
Since standard CMOS logic has a logic trip point at about 
mid-supply, and the outputs will transition from ground to 
Vcc. timing measurements are made from the 50% points 
on input and output waveforms. This is shown in Figure 1. 
Using the mid-supply point gives a more accurate represen- 
tation of how high-speed CMOS will perform in a CMOS 
system. This is different from the 1 .3V measurement point 
and ground to 3V input waveforms that are used to measure 
TTL timing. 

This output loading used for data sheet specifications fall 
into two categories, depending on the output drive capability 
of the specific device. The output drive categories are stan- 
dard outputs (Iol = 4 mA) and bus driver outputs 
(Iol= 6 mA). Timing measurements for standard outputs 
are made using a 50 pF load. Bus driver circuits are mea- 
sured using both a 50 pF and 1 50 pF load. In all AC tests, 
the test load capacitance includes all stray and test jig ca- 
pacitances. 

TRI-STATE® measurements where the outputs go from an 
active output level to a high impedance state, are made 
using the same input waveforms described above, but the 
timing is measured to the 10% or 90% points on the output 
waveforms. The test circuit load is composed of a 50 pF 


capacitor and a 1 kn resistor. To test tpHz. the resistor is 
swiched to ground, and for tpLz it is switched to Vcc- The 
TRI-STATE test circuit and typical timing waveforms are 
shown in Figure 2. 

Measurements, where the output goes from the high imped- 
ance state to active output, are the same except that mea- 
surements are made to the 50% points and for bus driver 
devices both 50 pF and 1 50 pF capacitors are used. 




(b) 


5V 



CL = 50pF (STANDARD DEVICE) 

Cl = 50 or 150 pF (BUFFER DEVICE) 


TL/F/5067-3 

(C) 

FIGURE 1. Typical Timing Waveform for (a) Propagation 
Delays, and (b) Clocked Delays. Also Test 
Circuit (c) for These Waveforms (tr = tf = 6 ns) 



2-119 


AN-317 




AN-317 



VCC 



TL/F/5067-5 

(b) 

FIGURE 2. Typical TRI-STATE (a) Timing Waveforms 
and (b) Test Circuit 

Note: Some early data sheets used a different test circuit. This has been 
changed or will be changed. i 

The MM54HCT/MM74HCT TTL input compatible devices 
are intended to operate with TTL devices, and so it makes 
sense to specify them the same way as TTL. Thus, as 
shown in Figure 3, typical timing input waveforms use 0-3V 
levels and timing measurements are made' from the 1.3V 
levels on these signals. The test circuits used are the same 
as standard HC input circuits. This is shown in Figure 3. 
These measurements are compatible with TTL type speci- 
fied devices. 

Specifying standard MM54HC/MM74HC speeds using 2,5V 
input measurement levels does represent a specification in- 
compatibility between TTL and most RAM /ROM and micro- 
processor speed specifications. It should not, however, 
present a design problem. The timing difference that results 
from using different measurement points is the time it takes 
for an output to make the extra excursion from 1 .3V to 2.5V. 
Thus, for a standard high-speed CMOS output, the extra 
transition time should result, worst case, in less than a 2 ns 
increase in the circuit delay measurement for a 50 pF load. 
Thus in speed critical designs adding 1 -2 ns safely enables 
proper design of HC into the TTL level systems. 

Power Supply Affect on AC Performance 

The overall power supply range of MM54HC/MM74HC logic 
is not as wide as CD4000 series CMOS due to performance 
optimization for 5V operation; however, this family can oper- 
ate over a 2-6V range which does enable some versatility, 




(b) 


FIGURE 3. Typical Timing Waveforms for (a) 
Propagation Delays, and (b) Clocked Delays for 54HCT/ 
74HCT Devices (tr = tf = 6 ns) 


especially when battery operated. Like metal-gate CMOS, 
lowering the power supply voltage will result in increased 
circuit delays. Some typical delays are shown in Figure 4. As 
the supply voltage is decreased from 5V to 2V, propagation 
delays increase by about two to three times, and when the 
voltage is Increased to 6V, the delays decrease by 10-15%. 



2 3 4 5 6 

POWER SUPPLY VOLTAGE 

' ■ TL/F/5067-8 

FIGURE 4. Typical Propagation Delay Variations of 
74HC00,74HC139, 74HC174 with Power Supply 


2-120 




In some designs it may be important to calculate the expect- 
ed propagation delays for a specific situation not covered in 
the data sheet. This can easily be accomplished by using 
the normalized curve of Figure 5 which plots propagation 
delay variation constant, t(V), versus power supply voltage 
normalized to 4.5V and 5V operation. This constant, when 
used with the following equation and the data sheet 5.0V 
specifications, yields the required delay at any power 
supply. 

tpD(V) ='[t(V)] [tpD(5V)] 1.0 

Where tpD(5V) is the data sheet delay and tpD(V) is the 
resultant delay at the desired supply voltage. 
This curve can also be used for the Vcc = 4.5V specifica- 
tions. 

For example, to calculate the typical delay of the 74HC00 at 
Vcc = 6V, the data sheet typical of 9 ns (1 5 pF load) is used. 
From Figure 5 t(V) is 0.9, so the 6V delay would be 8 ns. 



POWER SUPPLY VOLTAGE 


TL/F/5067-9 

FIGURE 5. MM54HCMM74HC Propagation Delay 
Variation Vs. Power Supply Normalized to 
Vcc = 4.5V, and Vcc = 5.0V 


Speed Variation with Capacitive Loading 

When high-speed CMOS is designed into a CMOS system, 
the load on a given output is essentially capacitive, and is 
the sum of the individual input capacitances, TRI-STATE 
output capacitances, and parasitic wiring capacitances. As 
the load is increased, the propagation delay increases. The 
rate of increase in delay for a particular device is due to the 
increased charge/discharge time of the output and the load. 
The rate at which the delay changes is dependent on the 
output impedance of the MM54HC/MM74HC circuit. As 
mentioned, for high-speed CMOS, there are two output 
structures: bus driver and standard. 

Figure 6 plots some typical propagation delay variations 
against load capacitance. To calculate under a particular 
load condition what the propagation delay of a circuit is, one 
need only know what the rate of change of the propagation 
delay with the load capacitance and use this number to ex- 
trapolate the delay from the data sheet vaue to the desired 
value. Figure 7 plots this constant, t(C), against power sup- 
ply voltage variation. Thus, by expanding on equation 1.0, 
the propagation delay at any load and power supply can be 
calculated using: 

tpD(C.V) = [t(C) (Cl - 15 pF)] + [tpD(5V) t(V)] 1.1 


Where t(V) is the propagation delay variation with power 
supply constant, tpD(5V) is the data sheet 4.5V (use 
(Cl - =50 pF) in equation) or 5V delay. Cl is the load ca- 
pacitance and tpD(C,V) is the resultant propagation delay at 
the desired load and supply. This equation’s first term is the 
difference in propagation delay from the desired load and 
the data sheet specification load. The second term is es- 
sentially equation 1.0. If the delay is to be calculated at 
Vcc==5V, then t(V) = 1 and t(C)= 0.042 ns/pF (standard 
output), 0.028 ns/pF (bus output). 

Using the previous 74HC00 example, the delay at Vcc = 6V 
and a 100 pF load is: 

tpD(1 00 pF,6V) = (0.042)(1 00—1 5) + (0.9 X 9) = 1 1 ns 



0 50 100 150 200 250 

LOAD CAPACITANCE-pF 

TL/F/5067-10 

FIGURE 6. Typical Propagation Delay Variation 
With Load Capacitance for 74HC04, 74HC164, 
74HC240, 74HC374 



TL/F/.5067-11 

FIGURE 7. Propagation Delay Capacitance Variation 
Constant Vs. Power Supply 


Speed Variations with Change 
in Temperature 

Changes In temperature will cause some change in speed. 
As with CD4000 and other metal-gate CMOS logic parts, 
MM54HC/MM74HC operates slightly slower at elevated 
temperatures, and somewhat faster at lower temperatures. 
The mechanism which causes this variation is the same as 
that which causes variations in metal-gate CMOS. This 



2-121 


AN-317 




AN-317 


factor is carrier mobility, which decreases with increase in 
temperature, and this causes a decrease in overall transis- 
tor gain which has a corresponding affect on speed. 

Figure 8 shows some typical temperature-delay variations 
for some high-speed CMOS circuits. As can be seen, 
speeds derate fairly linearly from 25“C at about -0.3%/C. 
Thus, 125‘’C propagation delays will be increased about 
30% from 25"C. 54HC/74HC speeds are specified at room 
temperature, -40 to 85°C (commercial temperature range), 
and -55 to 125‘’C (military range). In virtually all cases the 
numbers given are for the highest temperature. 

To calculate the expected device speeds at any tempera- 
ture, not specified in the device data sheet, the following 
equation can be used: 

tpD(T) = [1 + ((T-25)(0.003))] [tpD(25)] 1 .2 

Where tpD(T) is the delay at the desired temperature, and 
tpD(25) is the room temperature delay. Using the 74HC00 
example from the previous section, the expected Increase in 
propagation delay when operated at Vcc = 5V and 85‘’C is 
[1 +(85-25)(0.003)](10 ns)] = 12 ns. The expected delay at 
some other supply can also be calculated by calculating the 
room temperature delay then calculating the delay at the 
desired temperature. 



-55 -35 -15 5 25 45 65 85 105 125 


TEMPERATURE-°C 

TL/F/5067-12 

FIGURE 8. Typical Propagation Delay Variation 
With Temperature for 54HC02, 54HC390, 
54HC139,54HC151 


Output Rise and Fall, Setup and Hold Times 
and Pulse Width Performance Variations 

So far, the previous discussion has been restricted to propa- 
gation delay variations, and in most instances, this is the 
most important, parameter to know. Output rise and fall 
times may also be important. Unlike TTL type logic families 
HC specifies these in the data sheet. High-speed CMOS 
outputs were designed to have typically symmetrical rise 
and fall times. Output rise and fall time variations track very 
closely the propagation delay variations over temperature 
and supply. Figure 9 plots rise and fall time against output 
load at Vcc= 5V and at room temperature. Load variation of 
the transition time is twice the delay variation because de- 
lays are measured at halfway points on the waveform tran- 
sition. 

Setup times and pulse width performance under different 
conditions may be necessary when using clocked logic cir- 
cuits. These parameters are indirect measurements of in- 


ternal propagation delays. Thus they exhibit the similar tem- 
perature and supply dependence as propagation delays. 
They are, however. Independent of output load conditions. 



0 50 100 150 200 250 


OUTPUT LOAD CAPACITANCE-dF 

TL/F/5067-13 

FIGURE 9. Typical Output Rise or Fall Time Vs. Load For 
Standard and Bus Driver Outputs 


Input Rise and Fall Times 

Another speed consideration, though not directly related to 
propagation delays, is input rise and fall time. As with other 
high-speed logic families and also CD4000B and 54C/74C 
CMOS, slow input rise and fall times on input signals can 
cause logic problems. 

Typically, small signal gains for a MM54HC/MM74HC gate 
is greater than 1 000 and, if input signals spend appreciable 
time between logic states, noise on the input or power sup- 
ply will cause the output to oscillate during this transition. 
This oscillation could cause logic errors in the user’s circuit 
as well as dissipate extra power unnecessarily. For this rea- 
son MM54HC/MM74HC data sheets recommend that input 
rise and fall times be shorter than 500 ns at Vcc = 4.5V. 
Flip-flops and other clocked circuits also should have their 
input rise and fall times faster than 500 ns at Vcc = 4.5V. 
clock Input rise and fall times become too long, system 
noise can generate internal oscillations, causing the internal 
flip-flops to toggle on the wrong external clock edge. Even if 
no noise were present, internal clock skew caused by slow 
rise times could cause the logic to malfunction. 

If long rise and fall times are unavoidable, Schmitt triggers 
(’HC14/’HC132) or other special devices that employ 
Schmitt trigger circuits should be used to speed up these 
input signals. 

Logic Family Performance Cohiparison 

To obtain a better feeling of how high-speed CMOS com- 
pares to bipolar and other CMOS logic families, Figure 10 
plots MM54HC/MM74HC, 54LS/74LS and CD4000B logic 
device speeds versus output loading. HC-CMOS propaga- 
tion delay and delay variation with load is nearly the same 
as LSTTL and about ten times faster than metal-gate 
CMOS. Utilizing a silicon-gate process enables achievement 
of LSTTL speeds, and the large output drive of this family 
enables the variation with loading to be nearly the same as 
LSTTL as well. 

When comparing to CD4000 operating at 5V, HC-CMOS is 
typically ten times faster, and about three times faster than 
CD4000 logic operating at 1 5V. This is shown in Figure 1 1. 


2-122 







OUTPUT CAPACITANCE LOAD— pF TEMPERATURE— °C 

TL/F/5067-14 TL/F/5067-16 

FIGURE 10. Comparison of LSTTL FIGURE 12. Comparison of HC-CMOS, Metal-Gate 

and High-Speed CMOS Delays CMOS, and LSTTL Propagation Delay Vs. Temperature 


At 5V CD4000 has about a tenth the output drive of 
MM54HC/MM74HC and as seen in Figure 10, the capaci- 
tive delay variation is much larger. 

As shown in Figure 12, the temperature variation of HC- 
CMOS is similar to CD4000. This is due to the same physi- 
cal phenomenon In both families. The 54LS/74LS logic fam- 
ily has a very different temperature variation, which is due to 
different circuit parameter variations. One advantage to 
CMOS is that its temperature variation is predictable, but 
with LSTTL, sometimes the speed increases and other 
times speed decreases with temperature. 

The inherent symmetry of MM54HC/MM74HC’s logic levels 
and rise and fall times tends to make high to low and low to 
high propagation delay very similar, thus making these parts 
easy to use. 


Conclusion 

High-speed CMOS circuits are speed compatible with 
54LS/74LS circuits, not only on the data sheets, but even 
driving different loads. In general, HC-CMOS provides a 
large improvement in performance over older metal-gate 
CMOS. 

By using some of the equations and curves detailed here, 
along with data sheet specifications, the designer can very 
closely estimate the performance of any MM54HC/ 
MM74HC device. Even though the above examples illus- 
trate typical performance calculations, a more conservative 
design can be implemented by more conservatively estimat- 
ing various constants and using worst case data sheet lim- 
its. It is also possible to estimate the fastest propagation 
delays by using speeds about 0.4-0.7 times the data sheet 
typicals and aggressively estimating the various constants. 


CD40 

(VCC 

11B 
= 5V) 

y 

PT 

74C374 / 
(VCC = 5V) 


k 

:374 (V 

CD4011B 
(Vca^lSV) 
:C=15V) j 

\ 



74HC373 





/ 74HC00 

/| 








I 


50 100 150 200 250 


OUTPUT CAPACITANCE LOAD-pF 

TL/F/5067-15 

FIGURE 11. Comparison of Metal-Gate CMOS and 
High-Speed CMOS Delays 



2-123 


AN-317 




AN-319 


Comparison of 
MM54HC/MM74HC to 
54LS/74LS, 54S/74S and 
54ALS/74ALS Logic 


National Semiconductor 
Application Note 319 
Larry Wakeman 
June 1983 



The MM54HC/MM74HC family of high speed logic compo- 
nents provides a combination of speed and power charac- 
teristics that is not duplicated by bipolar logic families or any 
other CMOS family. This CMOS family has operating 
speeds similar to low power Schottky (54LS/74LS) technol- 
ogy. MM54HC/MM74HC is approximately half as fast (de- 
lays are twice as long) as the 54ALS/74ALS and 54S/74S 
logic. Compared to CD4000 and 54C/74C, this is an order 
of magnitude improvement in speed, which is achieved by 
utilizing an advanced 3.5 micron silicon gate-recessed oxide 
CMOS process. The MM54HC/MM74HC components are 
designed to retain all the advantages of older metal gate 
CMOS, plus provide the speeds required by today’s high 
speed systems. 

Another key advantage of the MM54HC/MM74HC family is 
that it provides the functions and pin outs of the popular 
54LS/74LS series logic components. Many functions which 
are unique to the CD4000 metal gate CMOS family have 
also been implemented in this high speed technology. In 
addition, the MM54HC/MM74HC. family contains several 
special functions not previously implemented in CD400P or 
54LS/74LS. 

Although the functions and the speeds are the same as 
54LS/74LS, some of the electrical characteristics are differ- 
ent from either LS-TTL, S-TTL or ALS-TTL. The following 
discusses these differences and highlights the advantages 
and disadvantages of high speed CMOS. 

AC PERFORMANCE 

As mentioned previously, the MM54HC/MM74HC logic fam- 
ily has been designed to have speeds equivalent to LS-TTL, 


and to be 8-10 times faster than CD4000B and MM54C/ 
MM74C logic. Table I compares high speed CMOS to the 
bipolar logic families. HC-CMOS gate delays are typically 
the same as LS-TTL, and ALS-TTL is two to three times 
faster. S-TTL Is also about twice as fast as HC-CMOS. Fllp- 
flpp and counter speeds also follow the same pattern. 

Also, HC logic’s propagation delay variation due to changes 
in capacitive loading is very similar to LS-TTL. Figure 1 illus- 
trates this by plotting delay versus loading for the various 
bipolar logic families and MM54HC/MM74HC. HC-CMOS 
has virtually the same speed and load-delay variation as 



0 50 100 ISO 200 

LOAD CAPACITANCE (pF) 

TL/F/5101-1 

FIGURE 1. HC, LS, ALS, S Comparison of Propagation 
Delay vs Load for a NAND Gate 


TABLE I. Comparison of Typical AC Performance of LS-TTL, S-TTL, ALS-TTL and HC-CMOS 


Gates 

LS-TTL 

ALS-TTL 


S-TTL 

Units 

74XX00 Propagation Delay 

8 

5 

8 

4 


74XX04 Propagation Delay 

8 

4 

8 

3 

ns 

Combinational MSI 

74XX1 39 Propagation Delay 






Select 

25 

8 

25 

8 

ns 

Enable 

21 

. 8 

20 

7 

ns 

74XX151 Propagation Delay 





m 

Address 

27 

8 

26 

12 


Strobe 

26 

7 


12 


74XX240 Propagation Delay 


3 

10 

5 

ns 

Enable/Disable Time 


7 

17 

10 

ns 


74XX1 74 Propagation Delay 

20 

7 

18 



Operating Frequency 

40 

50 

50 



74XX374 Propagation Delay 

19 

7 

16 



Enable/Disable Time 

21 

9 

17 



Operating Frequency 

50 

50 

50 




2-124 












LS-TTL and, as is expected, is slower than ALS and S-JTL 
logic. The slopes of these lines indicate the amount of varia- 
tion in speed with loading, and are dependent on the output 
impedance of the particular logic gate. The delay variation 
of LS-TTL and HC-CMOS is similar whereas ALS-TTL and 
S-TTL have slightly less variation. 

POWER DISSIPATION 

CD4000B and MM54C/MM74C CMOS devices are well 
known for extremely low quiescent power dissipation, and 
high speed CMOS retains this feature. Table II compares 
typical HC static power consumption with LS, ALS and S- 
TTL Even CMOS MSI dissipation is well below 1 /xW while 
LS-TTL dissipation is many milliwatts. This makes 
MM54HC/MM74HC ideal for battery operated or ultra-low 
power systems where the system may be put to “sleep” by 
shutting off the system clock. 


TABLE II. Comparison of Typical Quiescent 
Supply Current for Various Logic Families 



HC-CMOS 

LS-TTL 

ALS-TTL 

S-TTL 

SSI 

0.0025 jiiW 

5.0 mW 

2.0 mW 

75 mW 

Flip-Flop 

0.005 jLiW 

20.0 mW 

10 mW 

150 mW 

MSI 

0.25 /xW 

90 mW 

40 mW 

470 mW 


CMOS dissipation increases proportionately with operating 
frequency. Doubling the operating frequency doubles the 
current consumption. This is due to currents generated by 
charging internal and load capacitances. Figure 2 shows 
power dissipation versus frequency for a completely unload- 
ed NAND gate, flip-flop and counter implemented in all 4 
technologies. 

The LS, S and ALS curves are essentially flat because the 
quiescent currents mask out capacitive effects, except at 
very high frequencies. Capacitive effects are slightly lower 
for the TTL families, so that, at high frequencies, CMOS 
dissipation may actually be more than ALS and LS. Howev- 
er, the power crossover frequency is usually well above the 
maximum operating frequency of MM54HC/MM74HC. 


The previously mentioned curves plot unloaded circuits. 
When considering typical system power consumption, ca- 
pacitive loading should also be considered. Table III lists 
components to implement all the support logic for a small 
microprocessor based system. By assuming a typical load 
capacitance of 50 pF, the power dissipation for these devic- 
es can be calculated at various average system clock fre- 
quencies. Figure 3 plots power consumption for 74HC, 
74LS, 74ALS and 74S logic implementations. Above 1 MHz, 
capacitive currents now also tend to dominate bipolar power 
dissipation as well. 


TABLE III. Hypothetical “Glue” Logic for a 
Typical Microprocessor System 


System Components 

# of ICs 

Address Decoders (’138) 

10 

Address Comparators (’688) 

5 

Address/ Data Buffers (’240/4) 

10 

Address/ Data Latches (’373/4) 

20 

MSI Control/Gating (’00, ’10) 

30 

Misc. Counter/Shift Reg (’161, ’164) 

20 

Flip-Flops (’73/4) 

10 


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TL/F/5101-2 


FIGURE 3. Power Consumption for Hypothetical 
Microprocessor System Support Logic 


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FIGURE 2. Supply Current Consumption Comparison 
for (a) 74XX00 (b) 74XX714 (c) 74XX161 Circuits 



2-125 


AN-319 



AN-319 


Since, in a typical system, some sections will operate at a 
high frequency and other parts at lower frequencies, the 
average system clock frequency is a simplification. For ex- 
ample, a 10 MHz microprocessor will have a bus cycle fre- 
quency of 2 to 5 MHz. Most system and memory compo- 
nents will be accessed a small amount of the time, resulting 
in effective clock frequencies on the order of 1 00 kHz for 
these sections. Thus, the average system clock frequency 
would be around 1 to 2 MHz, and an 8 to 1 power savings 
would be realized by using CMOS. 

Another simplification was made to calculate system power. 
CMOS circuits will dissipate much less power when TRI- 
STATE®, which would save much power since, in a given 
bus cycle, only a few buffers will be enabled. LS, ALS and S, 
however, actually dissipate more power when their outputs 
are disabled. 

Several interesting conclusions can be drawn from Figure 3. 
First, notice that, at higher frequencies, the bipolar logic 
families start to dissipate more power. This is a result of 
current consumption due to switching the load. As the oper- 
ating frequency approaches infinity, this will be the dominant 
effect. So, for extremely fast low power systems, minimizing 
load capacitance and overall operating frequency becomes 
more Important. As lower power TTL logic is introduced, 
system power will be increasingly dependent on capacitive 
load effects similar to CMOS. 


Second, TTL logic has a slightly smaller logic voltage swing 
than CMOS. Thus, for a given load, TTL will actually have a 
lower average load current. So, similar to the unloaded ex- 
ample, at very high frequencies, CMOS could consume 
more power than TTL. As Figure 5 indicates, these frequen- 
cies are usually far above the 30 MHz limit of HC-CMOS or 
LS-TTL. 

INPUT VOLTAGE CHARACTERISTICS 
AND NOISE IMMUNITY 

To maintain the advantage CMOS has In noise immunity, 
the input logic levels are defined to be similar to metal gate 
CMOS. At Vcc=5V, MM54HC/MM74HC is designed to 
have Input voltages of V|h = 3.5V and V|l= 1.0V. Additional- 
ly, input voltage over the operating supply voltage range is: 
V|H = 0.7Vcc and Vil = 0.2Vcc- This compares to V|h = 2.0V 
and Vn_=0.8V specified for LS-TTL over its supply range. 
Figure 4 illustrates the input voltage differences, and the 
greater noise immunity HC logic has over its supply range. 
Maintaining wide noise immunity gives HC-CMOS an advan- 
tage in many industrial, automotive, and computer applica- 
tions where high noise levels exist. 


VOH = VCC-0.1V 


V|H=0.7Vcc 



2 3 4 5 

POWER SUPPLY VOLTAGE (V) 


TL/F/5101-5 


FIGURE 4. Worst-Case Input and Output Voltages Over 
Operating Supply Range for HC and LS Logic 


— 

— 


Vcc 

= 4.5V 



— 

25° C 


-55 

1 “ 







J5°C 








0 12 3 4 

INPUT VOLTAGE (V) 

(a) 



INPUT VOLTAGE (V) 

(b) 



TL/F/5101-6 


0 1 2 3 4 5 

INPUT VOLTAGE (V) 

TL/F/5101-7 

(C) 


FIGURE 5. Input-Output Transfer Characteristics for 74XX00 
NAND Gate Implemented in (a) HC-CMOS (b) LS-TTL (c) ALS-TTL 


2-126 



Another indication of DC noise immunity is the typical trans- 
fer characteristics for the logic families. Figure 5 shows the 
transfer function of the 74XX00 NAND gate for HC-CMOS, 
LS-TTL and ALS-TTL. High speed CMOS has a very sharp 
transition typically at 2.25V, and this transition point is very 
stable over temperature. The bipolar logic transfer functions 
are not as sharp and vary several hundred millivolts over 
temperature. This sharp transition is due to the large circuit 
gains provided by triple buffering the HC-CMOS gate com- 
pared to the single bipolar gain stage. Figure 6 compares 
the transfer function of the ’HC08 and the ’ALS08, both of 
which are double buffered. The ’ALS08 has a sharper tran- 
sition, but the CMOS gate still has less temperature varia- 
tion and a more centered trip point. However, the TTL trip 
point is not dependent on Vcc variation as CMOS is. 

The high speed CMOS input levels are not totally compati- 
ble with TTL output voltage specifications. To make them 
compatible would compromise noise immunity, die size, and 
significant speed. The designer may improve compatibility 
by adding a pull-up resistor to the TTL output. He may also 
utilize a series of TTL-to-CMOS level converters which are 


5 


4 

3 

2 

1 
0 

0 1 2 3 4 5 

INPUT VOLTAGE (V) 

TL/F/5101-9 

(a) 


Vcc = 4.5V 

Tj 











■ 

n 

125'’C 


-5J 










25°C 







i 



being provided to ease design of mixed HC/LS/ALS/S sys- 
tems. These buffers have 0.8V and 2.0V TTL input voltage 
specifications, and provide CMOS compatible outputs. 
When mixing logic, the noise immunity at the TTL to CMOS 
interface is no better than LS-TTL, but a substantial savings 
in power will occur when using MM54HC/MM74HC logic. 

INPUT CURRENT 

The HC family maintains the ultra-low input currents typical 
of CMOS circuits. This current is less than 1 juA and is 
caused by input protection diode leakages. This compares 
to the much larger LS-TTL input currents of 0.4 mA for a low 
input and 40 jaA for a high input. ALS-TTL input currents are 
0.2 mA and 20 p,A and S-TTL input currents are 3.2 mA and 
100 )LtA. Figure 7 tabulates these values. The near zero in- 
put current of CMOS eases designing, since a typical input 
can be viewed as an open circuit. This eliminates the need 
for fanout restrictions which are necessary in TTL logic 
designs. 




0 1 2 3 4 5 

INPUT VOLTAGE (V) 

(b) 


TL/F/5101-8 


FIGURE 6. Input-Output Transfer Characteristics for 
74XX08 AND Gate Implemented in (a) HC-CMOS (b) ALS-TTL 



TL/F/5101-10 

FIGURE 7. Comparison of Input Current Specifications 
for Various Logic Families 



2-127 


AN-319 




AN-319 


POWER SUPPLY RANGE 

Figure 4 also compares the supply range of MM54HC/ 
MM74HC logic and LS-TTL. The high speed CMOS family Is 
specified to operate at voltages from 2V to 6V. 54LS, 54S 
and 54ALS logic is specified to operate from 4.5V •to 5.5V, 
and 74LS and 74S will operate from 4.75V to 5.25V. 74ALS 
is specified over a 4.5V to 5.5V supply range. This wider 
operating range for the HC family eases power supply de- 
sign by eliminating costly regulators and enhances battery 
operation capabilities. 

OUTPUT DRIVE 

Since there was no speed, noise immunity, or power trade- 
off, standard HC-CMOS was designed to have similar high 
current output drive that is characteristic of LS-TTL and 
ALS-TTL. Schottky TTL has about 5 times the output drive 
of MM54HC/MM74HC. Thus HC-CMOS has an output low 
current specification of 4 mA at an output voltage of 0.4V. In 
keeping with CD4000B series and 54C/74C series logic, the 
source and sink currents are symmetrical. Thus HC logic 
can source 4 mA as well. This large increase in output cur- 
rent for high speed CMOS over CD4000B also has the add- 
ed advantage of reducing signal line crosstalk which can be 
of greater concern in high speed systems. Figure 8 com- 
pares HC, LS, and ALS specified output currents. 

Since TTL logic families do have significant input currents 
they have a limited fanout capability. Table IV illustrates the 
limitations of these families, based on their input and output 


currents. High speed CMOS is also included. MM54HC/ 
MM74HC has the same CMOS-to-CMOS .fanout character- 
istics as CD4000B, virtually infinite. 


TABLE IV. Fanout of HC-CMOS, LS-TTL, 
ALS-TTL, S-TTL 


From, To 

74HC 

74LS 

74ALS 

74S 

74HC 

4000 

10 

20 

2 

74LS 

* 

20 

40 

4 

74ALS 

* 

20 

40 

4 

74S 

* 

50 

100 

10 


As another Indication of the similarity of HC-CMOS to LS- 
TTL, Figure 9 plots typical output currents versus output 
voltage for LS and HC. The output sink current curves are 
very similar, but LS source current Is somewhat different, 
due to its emitter-follower output circuitry. 
MM54HC/MM74HC bus driving circuits, namely the TRI- 
STATE buffers and latches, have half again as much output 
current drive as standard outputs. These components have 
a 6 mA output drive. The 6 mA was chosen based on a 
trade-off of die size and speed-load variations. This current 
is less than the 1 2 mA or more specified for LS and ALS bus 
driver circuits, because the bus fanout limitations of these 
families do not apply in CMOS systems. S-TTL bus output 
sink current is 48 mA. 



ALS-m LS-m HC-CMOS 


TL/F/5101-11 

FIGURE 8. Output Current Specifications for ALS-TTL, S-TTL and HC-CMOS 



0 1.0 2,0 3.0 4.0 5.0 

OUTPUT VOLTAGE (V) 



0 1.0 2.0 3.t) 4.0 5.0 

OUTPUT VOLTAGE (V) 


TL/F/5101 -12 

(a) (b) 

FIGURE 9. Comparison of Standard LS-TTL and HC-CMOS Output (a) Source (b) Sink Currents 


TL/F/5101 -13 


2-128 



OPERATING TEMPERATURE RANGE 

The operating temperature range and temperature effects 
on various HC-CMOS operating parameters differ from bipo- 
lar logic. The recommended temperature range for 74LS, 
74S, and 74ALS is 0°C to 70°C, compared to -40°C to 85°C 
for the 74HC family. 54 series logic is specified from -55°C 
to 125®C for ail four families. 

Temperature variation of operating parameters for the 
MM54HC/MM74HC family behaves very predictably and is 
due to the gain decreasing of MOSFET transistors as tem- 
perature is increased. Thus the output currents decrease 
and propagation delays increase at about 0.3% per degree 
centigrade. 

Figure 10 shows typical propagation delays for the 74XX00 
over the -55°C to +125“C temperature range. The 
’HCOO’s speed increases almost linearly with temperature, 
whereas the LS and ALS behave differently. 

A WORD ABOUT PLUG-IN REPLACEMENT OF TTL 

MM54HC/MM74HC logic implements TTL equivalent func- 
tions with the same pin outs as TTL. HC is not designed to 
be directly plug-in replaceable, but, with some care, some 
TTL systems can be converted to MM54HC/MM74HC with 
little or no modification. The replaceability of HC is deter- 
mined by several factors. 

One factor is the difference in Input levels. In systems where 
all TTL Is not being replaced and TTL outputs feed CMOS 
inputs, the input high voltages, as specified, are not totally 
compatible. Although TTL outputs will typically drive HC in- 
puts correctly, an external pull-up resistor should be added 
to fhe TTL outputs, or an MM54HCT/MM74HCT TTL com- 
patible circuit should be used. This incompatibility tends to 
limit the designer’s ability to intermingle TTL and 


HC-CMOS. Note, though, that HC outputs are completely 
compatible with the various TTL family’s input specifica- 
tions; therefore, there is no problem when HC is driving TTL. 
Another source of possible problems can occur when the 
LS design floats device inputs. This practice is not recom- 
mended when using LS-TTL, but it is sometimes done. Usu- 
ally, TTL inputs float high; however, CMOS inputs may float 
either high or low depending on the static charge on the 
input. It Is therefore important to always tie unused CMOS 
inputs to either Vcc or ground to avoid incorrect logic func- 
tioning. 

A third factor to consider when replacing any TTL logic is 
AC performance. The logic functions provided by 54HC/ 
74HC are equivalent to LS-TTL, and the propagation delay, 
set-up and hold times are similar to LS. However, there are 
some differences in the way CMOS circuits are Implement- 
ed which will cause differences in speed. For the most part, 
these differences are minor, but it is important to verify that 
they do not affect the design. 

CONCLUSION 

The MM54HC/MM74HC family represents a major step for- 
ward in CMOS performance. It is a full line family capable of 
being designed into virtually any application which now uses 
LS-TTL with substantial improvement in power consump- 
tion. ALS and S-TTL primarily offer faster speeds than HC- 
CMOS, but still do not have the input and output advantages 
or the lower power consumption of CMOS. Because of its 
high input impedance and large output drive, HC logic is 
actually easier to use. This, coupled with continued expan- 
sion of the 54HC/74HC, will make it an increasingly popular 
logic family. 



-60 -20 20 60 100 140 

TEMPERATURE (°C) 


(a) 



TEMPERATURE (“C) 

<b) 



TL/F/5101-14 ' 


-20 20 60 100 140 


TEMPERATURE (“C) 

TL/F/5101-15 


(C) 


FIGURE 10. Propagatiorv Delay Variation Across Temperature for (a) 74LS00 (b) 74ALS00 and (c) 74HC00 



2-129 


AN-319 





AN-339 


National’s Process 
Enhancements Eliminate 
the CMOS SCR Latch-Up 
Problem In 54HC/74HC Logic 

INTRODUCTION 

SCR latch-up is a parasitic phenomena that has existed in 
circuits fabricated using bulk silicon CMOS technologies. 
The latch-up mechanism, once triggered, turns on a parasit- 
ic SCR internal to CMOS circuits which essentially shorts 
Vcc to ground. This generally destroys the CMOS 1C or at 
the very least causes the system to malfunction. In order to 
make MM54HC/MM74HC high speed CMOS logic easy to 
use and reliable it is very important to eliminate latch-up. 
This has been accomplished through several layout and 
process enhancements. It is primarily several proprietary in- 
novations In CMOS processing that eliminates the SCR. 

First, what is “SCR latch-up?” It is a phenomena common 
to most monolithic CMOS processes, which involves “turn- 
ing on” a four layer thyristor structure (P-N-P-N) that ap- 
pears from Vcc ^0 ground. This structure Is formed by the 
parasitic substrate interconnections of various circuit diffu- 
sions. It most commonly can be turned on by applying a 
voltage greater than Vcc or Jess than ground any input or 
output, which fonvard biases the input or output protection 
diodes. Figure 1 schematically Illustrates these diodes found 
in the MM54HC/MM74HC family. Standard CD4000 and 
MM54C/MM74C logic also has a very similar structure. 
These diodes can act as the gate to the parasitic SCR, and 
if enough current flows the SCR will trigger. A second meth- , 
od of turning on the SCR is to apply a very large supply 
voltage across the device. This will breakdown internal di- 
odes causing enough current to flow to trigger latch-up. In 
HC logic the typical Vcc breakdown voltage is above 10V so 
this method is more uncommon. In either case, once the 
SCR is turned on a large current will flow from Vcc to 
ground, causing the CMOS circuit to malfunction and possi- 
bly damage itself. 

CMOS SCR problems can be minimized by proper system 
design techniques or added external protection circuits, but 
obviously the reduction or elimination of latch-up in the IC 
itself would ease CMOS system design, increase system 
reliability and eliminate additional circuitry. For this reason it 
was Important to eliminate this phenomena in National’s 
high speed CMOS logic family. 

Characterization of this proprietary high speed CMOS proc- 
ess for latch up has verified the elimination of this parasitic 
mechanism. In tests conducted under worst case conditions 
(Vcc=7V and Ta= 125X) it has been impossible to latch- 
up these devices on the inputs or on the outputs. 



FIGURE 1. Schematic Diagram of Input and Output 
Protection Structures 


National Semiconductor 
Application Note 339 
Larry Wakeman 
May 1983 



in testing for latch-up, caution must be exercised when try- 
ing to force large currents into an IC. As with any Integrated 
circuit there are maximum limitations to the current handling 
capabilities of the internal metalization, and diodes, and 
thus they can be damaged by excessive currents. This is 
discussed later in the test section. 

To enable the user to understand what latch-up is and how 
it has been eliminated, it is useful to review the operating of 
a simple discrete SCR, and then apply this to the CMOS 
SCR. Since most latch-up problems historically have been 
caused by extraneous noise and system transients, the AC 
characteristics of CMOS latch are presented. Also various 
methods of external and internal protection against latch-up 
is discussed as well as example test methods for determin- 
ing the latch up susceptibility of CMOS IC’s. 

SIMPLE DISCRETE SCR OPERATION 

To understand the behavior of the SCR structure parasitic 
to CMOS IC’s, it is first useful to review the basic static 
operation of the discrete SCR, and then apply it to the 
CMOS SCR. There are two basic trigger methods for this 
SCR. One is turning on the SCR by forcing current into its 
gate, and the second is by placing a large voltage across its 
anode and cathode. Figure 2 shows the basic four layer 
structure biased Into its forward blocking state. The SCR 
action can be more easily understood if this device is mod- 
eled as a cross coupled PNP and NPN transistor as shown 
in Figure 3. 

In the case of latch-up caused by forward biasing a diode, if 
current Is injected into the base of Q2, this transistor turns 
on, and a collector current beta times its base current flows 
into the base of Q1. Q1 in turn amplifies this current by beta 
and feeds It back Into the base of Q2, where the current is 
again amplified. If the product of the two transistors’ Beta 
becomes greater than one, B(NPN)xB(PNP)>1, this current 
multiplication continues until the transistors saturate, and 
the SCR is triggered. Once the regenerative action occurs a 
large anode current flows, and the SCR will remain on even 
after the gate current is removed, if enough anode current 
flows to sustain latch-up. However, if the transistor current 
gains are small no self sustaining positive feedback will oc- 
cur, and when the base current Is removed the collector 
current will stop. In a similar manner the SCR can be trig- 
gered by drawing current by fonvard biasing the base of Q1. 



TL/F/5346-2 

FIGURE 2. Simplified SCR Structure 


2-130 






The second case, the SCR may also be triggered without 
injecting any gate current. In the forward blocking state the 
small leakage current that is present does not trigger the 
SCR, but if the voltage is increased to a point where signifi- 
cant leakage currents start conducting, these currents could 
also trigger the SCR, again forming a low impedance path 
through the device. The same requirement that the Beta 


product of the PNP and NPN be greater than one in order 
for the SCR to trigger applies here as well. This leakage cur- 
rent trigger is characteristic of Schottkey diode operation. 

THE CMOS SCR: STATIC DC OPERATION 

For discussion purposes CMOS SCR latch up characteris- 
tics can be divided into two areas. One is the basic opera- 
tion of the SCR when static DC voltages are applied, and 
the second is the behavior when transients or pulses are 
applied. 

First looking at the device statically, the parasitic SCR in 
CMOS Integrated circuits Is much more complex and Its trig- 
gering Is somewhat different than the simple SCR already 
discussed. However, the regenerative feedback effect is ba- 
sically the same. Figure 4a shows a simplified P- well 
CMOS structure illustrating only the diffusions and the re- 
sultant parasitic transistors. The NPN transistor is a vertical 
device whose emitter is formed by n+ diffusions. The P- 
well forms the base and the N - substrate forms the collec- 
tor of the NPN. The PNP transistor Is a lateral device. Its 
emitter is formed by p + diffusions, its base is the N — sub- 
strate, and its collector is the P- well. 

Figure 4b illustrates a cross section of a simplified N- well 
process and its corresponding parasitic bipolar transistors. 
In this process the NPN is a lateral device and the PNP is 
vertical. Essentially the description of the P- well SCR is 
the same as the N- well version except the NPN is a low 
gain lateral device and the PNP is a high gain vertical tran- 
sistor. Thus the following discussion for the P- well also 
applies to the N - well with this exception. 


Vcc gnd 



vcc 



FIGURE 4. Simplified Cross Section of CMOS Processes a) P- well and b) N- well 



2-131 


688NV 






AN-339 


The transistors for the P— well CMOS process are drawn 
schematically in Figure 5, so that their cross coupled inter- 
connection is more easily seen. The SCR structure In Figure 
5 differs from that of Figure 3 in two ways. First, the transis- 
tors of Figure 5 have multiple emitters, due to the many 
diffusions on a typical die. One emitter of each trdhsistor 
could function as the trigger input to the SCR. Secondly, R1 
and R2 have been added and are due to P- and N- sub- 
strate resistances between the base of each transistor and 
the substrate power supply contacts. 



TL/F/5346-7 

FIGURE 5. Schematic of Simple SCR Model 

Like the discrete SCR there are two basic methods of turn- 
ing the CMOS SCR on. The first method Is however slightly 
different. In the CMOS parasitic SCR current cannot be di- 
rectly injected into the base of one of its transistors. Instead 
either node G1 must be raised above Vcc enough to turn on 

01, or node G2 must be lowered below ground enough to 
turn on 02. If G1 is brought above Vcc. current is injected 
from the emitter of 01 and is swept to the collector of Q1. 
The collector of 01 feeds the base of 02 and also R2. R2 
has the effect of stealing current from the base of 02, but as 
current flows through R2 a voltage will appear at the base of 

02. Once this voltage reaches 0.6 volts 02 will turn on and 
feed current from its collector back Into R1 and into 01. If 
0.6 volts is generated across R1, 01 then turns on even 
more. 

Again, If the two transistors have enough gain and enough 
anode current flows to sustain the SCR, It will turn on, and 
remain on even after G1 is returned to Vcc- The actual re- 
quirements for latch up are altered by the two resistors, R1 
and R2. Since the resistors shunt some current away from 
the base of both transistors, the resistors essentially reduce 
the effective gains of the transistors. Thus the transistors 
must actually have much higher gains in order to achieve an 
overall SCR loop gain greater than one, and hence enable 
the SCR to trigger. The actual equations to show quantita- 
tively how the resistors effect the SCR’s behavior could be 
derived, but It is sufficient to notice that as R1 and R2 be- 
come smaller the SCR becomes harder to turn on. 1C de- 
signers utilize this to reduce latch up. 

The second method of turning on the SCR mentioned earli- 
er also applies here. If the supply voltage is raised to a large 
value, and internal substrate diodes start breaking down ex- 
cessive leakage currents will flow possibly triggering the 
SCR. The resistors also affect this trigger method as well, 
since they steal some of the leakage currents from Q1 and 
Q2, and hence It takes more current to trigger the SCR. In 
high speed CMOS the process enhancements reduce the 
transistor betas and hence eliminate latch up by this mecha- 
nism as well. 

While useful, the SCR model of Figures 4 and 5 Is very 
simplified, since in actuality the CMOS SCR is a structure 


with many transistors interconnected by many resistances. 
Although still somewhat simiplified, Figure 6 attempts to il- 
lustrate how the parasitics on a chip connect. It is important 
. to remember that any transistor or diode diffusion can para- 
sitically form part of the SCR. In the figure transistor 01 and 
02 are single emitter transistors formed by the input protec- 
tion diodes. Internal P and N channel transistors have no 
external connection and are represented by 03 and 04. 05 
and 06 represent output transistor diffusions, and the sec- 
ond emitter corresponds to the output. All of these transis- 
tors are connected together by the N- substrate and P- 
well resistances, which are illustrated by the resistor mesh. 


Vcc 



FIGURE 6. Distributed Modei of CMOS SCR 


If any of the emitters associated with the trigger inputs G1 - 
G4 become forward biased the SCR may be triggeredMIso 
due to the Intertwined nature of this structure, part of the 
SCR may be initially latched ilip. In this case only a limited 
amount of current may flow, but this limited latch up may 
spread and cause other parts to be triggered until eventually 
the whole chip Is involved. 

In general the trigger to the SCR has been conceptualized 
as a current, since Ideally the CMOS input looks into the 
base of the SCR transistors. However this may not be quite 
true. There may be some resistance in series with each 
base, due to substrate or input protection resistances. In 
newer silicon gate CMOS processes, MM54HC/MM74HC 
for example, a poly-silicon resistor is used for electrostatic 
protection, and this enables larger voltages to be applied to 
the circuit pins without causing latchup. This is because the 
poly resistor actually forms a current limit resistor In series 
with the diodes. In most applications the designer is more 
concerned with accidental application of a large voltage, 
and the use of the poly resistor internally enables good volt- 
age resistance to latch up. CMOS outputs are directly con- 
nected to parasitic output diodes since no poly resistor can 
be placed on an output without degrading output current 
drive. Thus the output latch up mechanism Is usually 
thought of as a current. 


2-132 




Temperature variations will affect the amount of current re- 
quired to trigger the SCR. This is readily understandable 
since temperature effects the bipolar transistor’s gain and 
the resistance of the base-emitter resistors. Generally, as 
the temperature is increased less current is needed to 
cause latch-up. This is because as temperature increases 
the bipolar transistor’s base-emitter voltage decreases and 
the base-emitter resistor value increases. Figure 7 plots trig- 
ger current versus temperature for a sensitive CMOS input. 
This data was taken on a CMOS device without any layout 
or process enhancements to eliminate latch up. Increasing 
temperature from room to 125“C will reduce the trigger cur- 
rent by about a factor of three. Once the circuit is latched 
up, heating of the device die caused by SCR currents will 
actually increase the susceptibility to repeated latch up. 



- 55 - 35-15 5 25 45 65 85 105 125 
TEMPERATURE-^C 

TL/F/5346-9 

FIGURE 7. Temperature versus SCR Trigger Current for 
Special CMOS T est Structure 

OTHER LATCH UP TRIGGER METHODS 

There are some other methods of latching up CMOS cir- 
cuits, they are not as circuit design related and shall only be 
briefly mentioned. The first is latch up due to radiation bom- 
bardment. In hostile environments energetic atomic parti- 
cals can bombard a CMOS die freeing carriers in the sub- 
strate. These carriers then can cause the SCR/ to trigger. 
This can be of concern in high radiation environments which 
call for some sort of radiation hardened CMOS logic. 
Another latch up mechanism is the application of a fast rise 
or fall spike to the supply Inputs of a CMOS device. Even if 
insufficient current Is injected into the circuit the fast voltage 
change could trigger latch up. This occurs because the volt- 
age change across the part changes the junction depletion 
capacitances, and this change in capacitance theoretically 
could cause a current that would trigger the SCR latch. In 
actual practice this Is very difficult to do because the re- 
sponse time of the SCR (discussed shortly) is very poor. 
This is hardly a problem since power supplies must be ade- 
quately decoupled anyway. 

A third latch up cause which is completely internal to the 1C 
itself and is out of the control of the system designer is 
internally triggered latch up. Any internal switching node 
connects to a diode diffusion, and as these diffusions switch 
the junction depletion capacitance associated with these 
nodes changes causing a current to be generated. This cur- 
rent could trigger the SCR. The poor frequency response of 
the SCR tends to make this difficult, but as chip geometries 
are shrunk packing densities will increase and the gain of 
the lateral PNP transistor increase. This may increase the 
latch up susceptibility. It is up to the 1C designer to ensure 


that this doesn’t happen, and care in the layout and circuit 
design of 54HC/74HC logic has ensured that this will be 
avoided. 

THE CMOS SCR: TRANSIENT BEHAVIOR 

With the introduction of fast CMOS logic the transient na- 
ture of the CMOS SCR phenomena becomes more impor- 
tant because signal line ringing and power supply transients 
are more prevalent in these systems. Older metal gate 
CMOS (CD4000 & 74HC) circuits have slow rise and fall 
times which do not cause a large amount of line ringing. 
Power supply spiking is also somewhat less, again due to 
slow switching times associated with these circuits. 

The previous discussion assumed that the trigger to the 
CMOS SCR was essentially static and was a fixed current. 
Under these conditions a certain value current will cause 
the SCR to trigger, but if the trigger Is a short pulse the peak 
value of the pulse current that will trigger the SCR can be 
much larger than the static DC trigger current. This is due to 
the poor frequency characteristics of the SCR. 

For short noise pulses, <5 jus, the peak current required to 
latch up a device is dependent on the duty cycle of the 
pulses. At these speeds it is the average current that caus- 
es latch-up. For example, if a 1 MHz 50% duty cycle over 
voltage pulse train is applied to a device that latched with 
20 mA DC current, then typically the peak current required 
will be about 40 mA. For a 25% duty cycle the peak current 
would be 80 mA. An example of this is shown in Figure 8 
which plots latch up current against over-voltage pulse 
width at 1 MHz. 



0 20 40 60 80 100 

PULSE DUTY CYCLE- % 


TL/F/5346-10 

FIGURE 8. Trigger Current of SCR of Input Overvoltage 
Pulses at High Repetition Rate on Speciai Test Unit 


If the pulse widths become long, many microseconds, the 
latch up current will approach the DC value even for low 
duty cycles. This is shown In Figure 9 which plots peak trig- 
ger current vs pulse width for the same test device used in 
Figure 8. The repetition rate in this case is a slow 2.5 kHz 
(period =400 jits). These long pulse widths approach the 
trigger time of the SCR, and thus pulses lasting several mi- 
croseconds are long enough to appear as DC voltages to 
the SCR. This indirectly indicates the trigger speed of the 
SCR to be on the order of ten to fifteen microseconds. This 
is however dependent on the way the IC was designed and 
the processing used. 

In normal high speed systems noise spikes will typically be 
only a few nanoseconds in duration, and the average duty 
cycle will be small. So even a device that is not designed to 



2-133 


AN-339 




AN-339 



0 1S 30 45 60 

PULSE WIDTH-fiS 

TL/F/5346-11 

FIGURE 9. Trigger Current of Pulse on Special Test Unit 
SCR for Single Transient Overvoltage 

be latch up resistant, will probably not latch up even with 
significant line ringing on its inputs or outputs (Then again 
. . .)• However, in some systems where inductive or other 
loads are used transients of several microseconds can be 
easily generated. For example, some possible applications 
are automotive and relay drivers. In other CMOS logic fami- 
lies spikes of this nature are much more likely to cause the 
SCR to trigger, but here again MM54HC/MM74HC high 
speed CMOS is immune. 

PREVENTING SCR LATCH UP: 

USER SYSTEM DESIGN SOLUTIONS 

SCR latch-up can be prevented either on the system level 
or on the 1C level. Since National’s MM54HC/MM74HC se- 
ries will not latch up, this eliminates the need for the system 
designer to worry about preventing latch up at the system 
level. This not only eases the design, but negates the need 
to add external diodes and resistors to protect the CMOS 
circuit, and hence additional cost. (Note however that even 
though the devices don’t latch up, diode currents should be 
limited to their Absolute Maximum Ratings listed in the Data 
Sheets). , 

If one is using a CMOS device that may latch up, older 
CD4000 CMOS or another vendors HC for example, and Its 


input or output voltages may forward bias the input or output 
diodes then some external circuitry may need to be added 
to eliminate possible SCR triggering. As with the previous 
discussions of latch-up preventing SCR latch-up falls into 
two categories: the static case, and the transient condition. 
Each is related but has some unique solutions. 

In the static condition to ensure SCR latch up does not oc- 
cur, the simplest solution is to design CMOS systems so 
that their Input/output diodes don’t become forward biased. 
To ease this requirement some special circuits that have 
some of their input protection diodes removed are provided, 
and this enables input voltages to exceed the supply range. 
These devices are MM54HC4049/50, CD4049/50, and 
MM54C901/2/3/4. 

If standard logic is used and input voltages will exceed the 
supply range, an external network should be added that pro- 
tects the device by either clamping the input voltage or by 
limiting the currents which flow through the Internal diodes. 
Figure 10 illustrates various input and output diode clamping 
circuits that shunt the diode currents when excessive input 
voltages are applied. Usually either an additional input or 
output diode is required, rarely both, and if the voltages only 
exceed one supply then only one diode is necessary. If an 
external silicon diode is used the current shunt is only par- 
tially effective since this diode Is in parallel with the internal 
silicon protection diode, and both diodes clamp to about 
0.7V. 

A second method, limiting input current, is very effective in 
preventing latch-up, and several designs are shown in 
Figure 11. The simplest approach is a series Input resistor. It 
is recommended that this resistor should be as large as 
possible without causing excessive speed degradation yet 
ensure the input current is limited to a safe value. If speed is 
critical, it Is better to use a combination diode-resistor net- 
work as shown In Figures 11b and 11c. These Input networks 
effectively limit Input currents while using lower input resis- 
tors. The series resistor may not be an ideal solution for 
protecting outputs because it will reduce the effective drive 
of the output. In most cases this is only a problem when the 
output must drive a lot of current or must switch large ca- 
pacitances quickly. 


Vcc OR Vdo Vcc or Vdd VcC or Vod 



GNO OR VSS ' GKD OR Vs^ GNO OR Vss 

TL/F/5346-12 

Schottky Diodes Germanium Diodes Zener Diodes 

(a) (b) (c) 

FiGURE 10. External Input and Output Protection Diodes Circuits for Eliminating SCR Latch-up 


Vcc OR VDD 



GNO OR Vss 


Vcc OR VDD Vcc OR Vdd 



GND OR Vss GND OR Vss 


TL/F/5346-13 


(a) (b) (c) 

FiGURE 11. Input Resistor and Resistor-Diode Protection Circuits for Eliminating Latch-up 


2-134 



A third approach is instead of placing resistors in series with 
the inputs to place them in series with the power supply 
lines as shown in Figure 12. The resistors must be bypassed 
by capacitors so that momentary switching currents don’t 
produce large voltage transients across R1 and R2. These 
resistors can limit input currents but primarily they should be 
chosen to ensure that the supply current that can flow is 
less than the holding current of the SCR. Thus even though 
the input current can cause latch up it cannot be sustained 
and the IC will not be damaged. 



TL/F/5346-14 

FIGURE 12. Supply Resistor-Capacitor Circuits for 
Eliminating Latch-up 


This last solution has the advantage of fewer added compo- 
nents, but also has some disadvantages. This method may 
not prevent latch up unless the resistors are fairly large, but 
this will greatly degrade the output current drive and switch- 
ing characteristics of the device. Secondly, this circuit pro- 
tects the IC from damage but if diodes currents are applied 
causing large supply currents, the circuits will logically mal- 
function where as with other schemes logic malfunction can 
be prevented as well. 

PREVENTING LATCH UP: IC DESIGN SOLUTIONS 

The previous latch up solutions involve adding extra compo- 
nents and hence extra cost and board space. One can 
imagine that in a microprocessor bus system if for some 
reason the designer had to protect each output of several 
CMOS devices that are driving a 16-bit address bus that up 
to 32 diodes and possibly 16 resistors may need to be add- 
ed. Thus for the system designer the preferable solution is 
, to use logic that won’t latch up. 


Most methods previously employed to eliminate latch up are 
either not effective, increase the die size significantly, and/ 
or degrade MOS transistor performance. The process en- 
hancements employed on 54HC/74HC logic circumvent 
these problems. Primarily it is effective without degrading 
MOS performance. 

When designing CMOS integrated circuits, there are many 
ways that the SCR action of these circuits can be reduced. 
One of the several methods of eliminating the SCR is to 
reduce the effective gain of at least one of the transistors, 
thus eliminating the regenerative feedback. This can be ac- 
complished either by modifying the process and/or by in- 
serting other parasitic structures to shunt the transistor ac- 
tion. Also the substrate resistances modeled as R1 and R2 
in figures 4 and 5 can be reduced. As these resistances 
approach zero more and more current is required to develop 
enough voltage across them to turn on the transistors. 

As mentioned, the current gains of the NPN and PNP para- 
sitic transistors directly affect the current required to trigger 
the latch. Thus some layout and process enhancements 
can be implemented to reduce the NPN and PNP Betas. In 
a P-well process the gain of the vertical NPN is determined 
by the specific CMOS process, and is dependent on junc- 
tion depths and doping concentrations. These parameters 
also control the performance of the N-MOS transistors as 
well and so process modification must be done without de- 
grading CMOS performance. To reduce the gain of the verti- 
cal PNP the doping levels of the P- well can be increased. 
This will decrease minority carrier lifetimes. It will also re- 
duce the substrate resistance lowering the NPN base-emit- 
ter resistance. However this will increase parasitic junction 
capacitances, and may affect NMOS threshold voltages and 
carrier mobility. The depth of the well may be Increased as 
well. This will reduce layout density due to increased lateral 
diffusion, and increase processing time as it will take longer 
to drive the well deeper into the substrate. 

The lateral PNP’s gain Is determined by the spacing of input 
and output diode diffusions to active circuitry and minority 
carrier life times in the N - substrate. The carrier life times 
are a function of process doping levels as well, and care 
must be exercised to ensure no MOS transistor perform- 
ance degradation. Again the doping levels of the substrate 
can be Increased, but this will increase parasitic junction 
capacitances, and may alter the PMOS threshold character- 
istics. The spacing between input/output diodes and other 


INPUT N-CHANNEL DRAIN/ 


6N0 DIODE Vcc OUTPUT DIODE 




2-135 


AN-339 



AN-339 


diffusions can be increased. This will increase the PNP’s 
base width, lowering its beta. This may be done only a limit- 
ed amount without significantly impacting die size and cost. 
Another method for enhancing the latch-up immunity of 
MM54HC/MM74HC is to short out the SCR by creating ad- 
ditional parasitic transistors and reducing the effective sub- 
strate resistances. These techniques employ the use of 
ringing structures (termed guard rings) to surround inputs 
and outputs with diffusions that are shorted to Vcc or 
ground. These diffusions act to lower the substrate resist- 
ances, making it harder to turn on the bipolar transistors. 
They also act “dummy” collectors that shunt transistor ac- 
tion by collecting charges directly to either Vcc or ground, 
rather than through active circuitry. Figure 13 shows a cross 
section of how this might look and Figure 14 schematically 
illustrates how these techniques ideally modify the SCR 
structure. 

Ideally, in Figure 14 If the inputs are forward biased any 
transistor action is immediately shunted to Vcc or ground 
through the “dummy” collectors. Any current not collected 
will flow through the resistors, which are now much lower in 
value and will not allow the opposite transistor to turn on. 


Vcc 



TL/F/5346-16 

FIGURE 14. Schematic Representation of SCR with 
Improvements to Reduce Turn On. 

Unfortunately in order to reduce latch up these techniques 
add quite significantly to the die size, and still may not be 
completely effective. 

The ineffectiveness of the ringing structures at completely 
eliminating latch up is for one because the collectors are 
only surface devices and carriers can be injected very deep 
into the N - substrate. Thus they can very easily go under 
the fairly small “dummy” collectors and be collected by the 
relatively large active P- well. A possible solution might be 
to make the collector diffusions much deeper. This suffers 
from the same drawbacks as making the well deeper, as 
well as requiring additional mask steps increasing process 
complexity. Secondly, the base emitter resistances can be 
reduced only so much, but again only the surface resistanc- 
es are reduced. Some transistor action can occur under the 
P- well and deep in the N- bulk where these surface 
shorts are only partially effective. 

The above discussion described modifications to a P- well 
process. For an N - well process the descriptions are the 
same except that instead of a P - well an N - well is used 
resulting in a vertical PNP instead of an NPN and a lateral 
NPN instead of a PNP. 


These methods are employed in 54HC/74HG CMOS logic, 
but in addition processing enhancements were made that 
effectively eliminate the PNP transistor. The primary en- 
hancement is a modification to the doping profile of the N - 
substrate (P- well process). This lowers the conductivity of 
the substrate material while maintaining a lightly dope sur- 
face concentration. This allows optimum performance 
NMOS and PMOS transistors while dramatically reducing 
the gain of the PNP and its base-emitter resistance. The 
gain of the PNP is reduced because the minority carrier life- 
times are reduced. This modification also increases the ef- 
fectiveness of the “dummy” collectors by maintaining carri- 
ers closer to the surface. This then eliminates the SCR latch 
up mechanism. 

5.0 TESTING SCR LATCH-UP 

There are several methods and test circuits that can be 
employed to test for latch-up. The one primarily used to 
characterize the 54HC/74HC logic family is shown in Figure 
15. This circuit utilizes several supplies and various meters 
to either force current into the Vcc diodes or force current 
out of the ground diodes. By controlling the input supply a 
current is forced into or out of an input or output of the test 
device. As the input supply voltage is increased the current 
into the diode increases. Internal transistor action may 
cause some supply current to flow, but this should not be 
considered latch up. When latch-up occurs the power sup- 
ply current will jump, and if the input supply is reduced to 
zero the power supply current should remain. The input trig- 
ger current is the input current seen just prior to the supply 
current jumping. 

Testing latch-up i4 a destructive test, but in order to test 
54HC/74HC devices without causing Immediate damage, 
test limits for the amount of input or output currents and 
supply voltages should be observed. Even though immedi- 
ate damage is avoided, SCR latch-up test is a destructive 
test and the 1C performance may be degraded when testing 
to these limits. Therefore parts tested to these limits should 
not be used for design or production purposes. In the case 
of Nationals high speed CMOS logic the definition of “latch- 
up proof” requires the following test limits when using the 
standard DC power supply test as is shown in Figure 15. 

1. Inputs: When testing latch-up on CMOS inputs the cur- 
rent into these inputs should be limited to less than 
70 mA. Application of currents greater than this may 
damage the input protection poly resistor or input metali- 
zation, and prevent further testing of the IC. 

2. Outputs: When testing outputs there Is a limit to the met- 
alization’s current capacity. Output test currents should 
be limited to 200 mA. This limitation is due again to met- 
alization short term current capabilities, similar to Inputs. 
Application of currents greater than this may blow out the 
output. 

3. Supply: The power supply voltage is recommended to be 
7.0V which Is at the absolute maximum limit specified in 
54HC/74HC and is the worst case voltage for testing 
latch-up. If a device latches up it will short out the power 
supply and self destruct. (Another Vendors HC may 
latch-up for example.) It is recommended that to prevent 
immediate destruction of other vendors parts that the 
power supply be current limited to less than 300 mA; 


2-136 




In almost all instances at high temperature, if it is going to 
occur, latch-up will occur at current values between 
0-50 mA. 

There are a few special considerations when trying to mea- 
sure worst case latch-up current. Measuring input latch-up 
current is straight fonvard, just force the inputs above or 
below the power supply, but to measure an output it must 
first be set to a high level when forcing it above Vcc. or to a 
low level when forcing it below ground. When measuring Tri- 
State outputs, the outputs should be disabled, and when 
measuring analog switches they should be either left open 
or turned off. 

To measure the transient behavior of the test device or to 
reduce 1C heating effects a pulse generator can be used In 
place of the input supply and an oscilloscope with a current 
probe should then replace the current meter. Care should 
be exercised to avoid ground loops in the test hardware as 
this may short out the supplies. 


Although there are several methods of testing latch-up, this 
method is very simple and easy to understand. It also yields 
conservative data since manually controlling the supplies is 
a slow process which causes localized heating on the chip 
prior to latch-up, and lowers the latch-up current. 

6.0 CONCLUSION 

SCR latch-up in CMOS circuits is a phenomena which when 
understood can be effectively controlled both from the inte- 
grated circuit and system level. National’s proprietary 
CMOS process and layout considerations have eliminated 
CMOS latch-up in the MM54HC/MM74HC family. This will 
increase the ease of use and design of this family by negat- 
ing the need for extra SCR protection circuitry as well as 
very favorable Impact system integrity and reliability. 


Testing SCR Latch-Up of HCMOS 


Vcc DIODE TEST CIRCUIT GROUND DIODE TEST CIRCUIT 

AMMETER AMMETER 




Ta = 125X 

FIGURE 15. Bench Test Setup for Measuring LatcH-up 



2-137 


AN-339 




AN-340 


HCMOS Crystal Oscillators 


With the advent of high speed HCMOS circuits, it is possible 
to build systems with clock rates of greater than 30 MHz. 
The familiar gate oscillator circuits used at low frequencies 
work well at higher frequencies and either L-C or crystal 
resonators maybe used depending on the stability required. 
Above 20 MHz, it becomes expensive to fabricate funda- 
mental mode crystals, so overtone modes are used. 




TL/F/5347-2 

Reactance of Crystal Resonator 
FIGURE 1 

Basic Oscillator Theory 

The equivalent circuit of a quartz crystal, and its reactance 
characteristics with frequency are shown in Figure 1. Fr is 
called the resonant frequency and Is where Li and Ci are in 
series resonance and the crystal looks like a small resistor 
R1. The frequency Fa is the antIresonant frequency and is 
the point where Li-Ci look Inductive and resonate with Cq 
to form the parallel resonant frequency Fa, Fr and Fa are 
usually less than 0.1 % apart. In specifying crystals, the fre- 
quency Fr is the oscillation frequency to the crystal In a 
series mode circuit, and Fr is the parallel resonant frequen- 
cy. In a parallel mode circuit, the oscillation frequency will 
be slightly below Fa where the Inductive component of the 
Li -Ci arm resonates with Cq and the external circuit ca- 
pacitance. the exact frequency is often corrected by the 
crystal manufacture to a specified load capacitance, usually 
20 or 32 picofarads. 


TABLE I. Typical Crystal Parameters 


Parameter 

32 kHz 
fundamental 

200 kHz 
fundamental 

2 MHz 

fundamental 

30 MHz 
overtone 

Ri 

200 kn 

2kft 

100 ft 

20 ft 

Li 

7000H 

27H 

529 mH 

11 mH 

Ci 

.003 pF 

0.024 pF 

0.012 pF 

0.0026 pF 

Co 

1.7 pF 

• 9pF 

4pF 

6 pF 

Q 

100k 

18k 

54k 

100k 


National Semiconducter 
Application Note 340 
Thomas B. Mills 
May 1983 

The Pierce oscillator is one of the more popular circuits, and 
is the foundation for almost all single gate oscillators in use 
today. In this circuit. Figure 2, the signal from the Input to the 
output of the amplifier is phase shifted 180 degrees. The 
crystal appears as a large inductor since it is operating in 
the parallel mode, and in conjunction with Ca and Cr. forms 
a pi network that provides an additional 180 degrees of 
phase shift from output to the input. Ca in series with Cr 



plus any additional stray capacitance form the load capaci- 
tance for the crystal. In this circuit, Ca is usually made about 
the same value as Cr, and the total value of both capacitors 
in series is the load capacitance of the crystal which is gen- 
erally chosen to be 32 pF„ making the value of each capaci- 
tor 64 pF. The approximation equations of the load imped- 
ance, Zi, presented to the output of the crystal oscillator’s 
amplifier by the crystal network is: 



Where Xo= -j/coCR and Rl Is the series resistance of the 
crystal as shown in Table I. Also <i) = 27rf where f is the 
frequency of oscillation. 

The ratio of the crystal network’s Input voltage to it’s output 
voltage is given by: 

oa _ coCr _ Cr 
eR wCa Ca 

Ca and Cr are chosen such that their series combination 
capacitance equals the load capacitance specified by the 
manufacturer, ie 20 pF or 32 pF as mentioned. In order to 
oscillate the phase shift at the desired frequency around the 
oscillator loop must be 360” and the gain of the oscillator 
loop must be greater of equal to one, or: 

(Aa)(Af)^1 

Where Aa is amplifier gain and Ap is crystal network voltage 
gain of the crystal tt network: oa/or. Thus not only should 
the series combination of Cr and Ca be chosen. The ratio of 
the two can be set to adjust the loop gain of the oscillator. 
For example if a 2 MHz oscillator is required. Then 
Rl= 10011 (Table I). If eA/eR = 1 and the crystal requires a 
32 pF load so Cr = 64 pF and then Ca becomes 64 pF also. 
The load presented by the crystal network is Zl= C'A'n’ (2 
MHz)(64pF)2)/100 = 16ka 



2-138 




The CMOS Gate Oscillator 

A CMOS gate sufficiently approaches the ideal amplifier 
shown above that it can be used in almost the same circuit. 
A review of manufacturers data sheets will reveal there are 
two types of inverting CMOS gates: 

a) Unbuffered: gates composed of a single inverting stage. 
Voltage gain in the hundreds. 

b) Buffered: gates composed of three inverting stages in 
series. Voltage gains are greater than ten thousand. 

CMOS gates must be designed to drive relatively large 
loads and must supply a fairly large amount of current. In a 
single gate structure that is biased in its linear region so 
both devices are on, supply current will be high. Buffered 
gates are designed with the first and second gates to be 
much smaller than the output gate and will dissipate little 
power. Since the gain is so high, even a small signal will 
drive the output high or low and little power is dissipated. In 
this manner, unbuffered gates will dissipate more power 
than buffered gates. 

Both buffered and unbuffered gates maybe used as crystal 
oscillators, with only slight design changes in the circuits. 


When designing with buffered gates, the value of R 2 or Cb 
may be Increased by a factor of 10 or more. This will in- 
crease the voltage loss around the feedback loop which is 
desirable since the gain of the gate is considerably higher 
than that of an unbuffered gate. 

Ca and Cb form the load capacitance for the crystal. Many 
crystals are cut for either 20 to 32 picofarad load capaci- 
tance. This is the capacitance that will cause the crystal to 
oscillate at Its nominal frequency. Varying this capacitance 
will vary the frequency of oscillation. Generally designers 
work with crystal manufacturers to select the best value of 
load capacitance for their application, unless an off the shelf 
crystal is selected. 

High Frequency Effects 

The phase shift thru the gate may be estimated by consider- 
ing it’s delay time: 

Phase Shift = Frequency X Time delay X 360“ 

The “typical gate oscillator” works well at lower frequencies 
where phase shift thru the gate is not excessive. However, 
above 4 MHz, where 10 nsec of time delay represents 14.4° 
of excess phase shift, R 2 should be changed to a small 
capacitor to avoid the additional phase shift of R 2 . The val- 
ue of this capacitor is approximately 1/a)C where aj = 27rf, 
but not less than about 20 pF. 


Rf 10 MQ 



Rf = 10 MS2 



‘ Cb ~ 62 pF 


TL/F/5347-4 

FIGURE 3. Typical Gate Oscillator 


TL/F/5347-5 

FIGURE 4. Gate Oscillator for Higher Frequencies 


In this circuit, Rp serves to bias the gate in its linear region, 
insuring oscillation, while R 2 provides an impedance to add 
some additional phase shift in conjunction with Cb- It also 
serves to prevent spurious high frequency oscillations and 
isolates the output of the gate from the crystal network so a 
clean square wave can be obtained from the output of the 
gate. Its value is chosen to be roughly equal to the capaci- 
tive reactance of Cb at the frequency of oscillation, or the 
value of load impedance Zl calculated above. In this case, 
there will be a two to one loss in voltage from the output of 
the gate to the input of the crystal network due to the volt- 
age divider effect of R 2 and Zl- If Ca and Cb are chosen 
equal, the voltage at the input to the gate will be the same 
as that at the input to the crystal network or one half of the 
voltage at the output of the gate. In this case, the gate must 
have a voltage gain of 2 or greater to oscillate. Except at 
very high frequencies, all CMOS gates have voltage gains 
well in excess of 1 0 and satisfactory operation should result. 
Theory and experiment show that unbuffered gates are 
more stable as oscillators by as much as 5 to 1 . However, 
unbuffered gates draw more operating power if used in the 
same circuit as a buffered gate. Power consumption can be 
minimized by increasing feedback which forces the gate to 
operate for less time in its linear region. 


Improving Oscllator Stability 

The CMOS gate makes a* mediocre oscillator when com- 
pared to a transistor or FET: It draws more power and is 
generally less stable. However, extra gates are often avail- 
able and are often pressed into service as oscillators. If 
improved stability Is required, especially from buffered gate 
oscillators, an approach shown In Figure 5 can be used. 


Rf = 10 mq 



TL/F/5347-6 

FIGURE 5. Gate oscillator with improved stability 



2-139 


AN-340 




AN-340 


In this circuit, Ca and Cg are made large to swamp out the 
effects of temperature and supply voltage change on the 
gate input and output impedances. A small capacitor in se- 
ries with the crystal acts as the crystal load and further iso- 
lates the crystal from the rest of the circuit. 

Overtone Crystal Oscillators 

At frequencies above 20 MHz, it becomes increasingly diffi- 
cult to cut or work with crystal blanks and so generally a 
crystal is used in it’s overtone mode. Also, fundamental 
mode crystals above this frequency have less stability and 
. greater aging rates. All crystals will exhibit the same reac- 
tance vs. frequency characteristics at odd overtone fre- 
quencies that they do at the fundamental frequency. How- 
ever, the overtone resonances are not exact multiples of 
the fundamental, so an overtone crystal must be specified 
as such. 

In the design of an overtone crystal oscillator, it is very im- 
portant to suppress the fundamental mode, or the circuit will 
try to oscillate there, or worse, at both the fundamental and 
the overtone with little predictability as to which. Basically, 
this requires that the crystal feedback network have more 
gain at the overtone frequency than the fundamental. This is 
usually done with a frequency selective network such as a 
tuned circuit. 

The circuit in Figure 6 operates in the parallel mode just as 
the Pierce oscillator above. The resonant circuit La — Cb is 
an effective short at the fundamental frequency, and is 
tuned somewhat below the deferred crystal overtone fre- 
quency. Also, Cl is chosen to suppress operation in the 
fundamental mode. 

The coll La may be tuned to produce maximum output and 
will affect the oscillation frequency slightly. The crystal 
should be specified so that proper frequency is obtained at 
maximum output level from the gate. 

Some Practical Design Tips 

In the above circuits, some generalizations can be made 
regarding the selection of component values. 

r' 


Rp: Sets the bias point, should be as large as practical. 

R1: Isolates the crystal network from the gate output and 
provides excess phaseshift decreasing the probability of 
spurious oscillation at high frequencies. Value should be ap- 
proximately equal to input impedance of the crystal network 
or reactance of Cb at the oscillator frequency. Increasing, 
value will decrease the amount of feedback and improve 
stability. 

Cb: Part of load for crystal network. Often chosen to be 
twice the value of the crystal load capacitance. Increasing 
value will increase feedback. 

Ca’. Part of crystal load network. Often chosen to be twice 
the value of the crystal load capacitance. Increasing value 
will increase feedback. 

Cl: Used in place of R1 in high frequency applications. 
Reactance should be approximately equal to crystal net- 
work input impedance. 

Oscillator design is an imperfect art at best. Combinations 
of theoretical and experimental design techniques should 
be used. 

A. Do not design for an excessive amount of gain around 
the feedback loop. Excessive gain will lead to instability 
and may result in the oscillator not being crystal con- 
trolled. 

B. Be sure to worst case the design. A resistor may be 
added in series with the crystal to simulate worst case 
crystals. The circuit should not oscillate on any frequen- 
cy with the crystal out of the circuit. 

C. A quick check of oscillator peformance is to measure the 
frequency stability with supply voltage variations. For 
HCMOS gates, a change of supply voltage from 2.5 to 6 
volts should result in less than 10 PPM change in fre- 
quency. Circuit value changes should be evaluated for 
improvements in stability. 


fo:=ai MHz 
Rf=10 MQ 



La 0:9 mH 
11.5 TURNS 


FIGURE 6. Parallel Mode Overtone Circuit 


TL/F/5347-7 


2-140 




MM74HC942and 
MM74HC943 Design Guide 


National Senniconductor 
Application Note 347 
Peter Single 
Steve Munich 
April 1984 



SECTIONS 


1) Timing and Control 2-141 

a) Input and Output Thresholds 2-141 

b) Logic States and Control Pin Function 2-141 

c) The Oscillator 2-142 

2) The Modulator 2-143 

a) Operation 2-143 

b) Transmit Level Adjustment 2-143 

3) The Line Driver 2-144 

a) Operation 2-144 

b) Second Harmonic Distortion 2-144 

c) Dynamic Range 2-144 

d) Transmission of Externally Generated Tones. 2-144 

i) Using the Line Driver 2-144 

il) Using TRI-STATE® Capability 2-144 


4) The Hybrid 2-145 

5) The Receive Filter 2-145 

6) TheFTLCPin , 2-145 

7) The Carrier Detect Circuit.^ 2-146 

a) Operation 2-146 

b) Threshold Control 2-146 

c) Timing Control 2-146 

8) The Discriminator 2-147 

a) The Hard Limiter 2-147 

b) Discriminator Operation 2-147 

9) Power Supplies 2-147 

a) DC Levels and Analog Interface 2-147 

b) Power Supply Noise 2-147 


1) TIMING AND CONTROL 
a) Input and Output Thresholds 


Originate and Answer Mode 


The MM74HC942/943 may be used in a CMOS or TTL en- 
vironment. In a CMOS environment, no interfacing is re- 
quired. If the MM74HC942/943 is interfaced to NMOS or 
bipolar logic circuits, standard interface techniques may 
be used. These are discussed in detail in National 
Semiconductor Application Note AN-314. This note is in- 
cluded in the National Semiconductor MM54HC/74HC 
High Speed microCMOS Logic Family Databook. 


b) Logic States and Control Pin Function 
Transmitted Data 

TXD (pin 1 1) in conjunction with O/A selects the frequency 
of the transmitted tone and thus controls the transmitted 
data. 

TXD = Vcc selects a “mark” and thus the high tone of the 
tone pair.This is discussed further in the following section. 


This is controlled by O/A (pin 13). 0/A = Vqc selects 
originate mode. 0/A = GND selects answer mode. These 
modes refer to the tone allocation used by the modem. 
When two modems are communicating with each other 
one will be in originate mode and one will be in answer 
mode. This assures that each modem is receiving the tone 
pair that the other modem is transmitting. The modem on 
the phone that originated the phone call is called the 
originate modem. The other modem is the answer modem. 

The other pin controlling the transmitted tone is TXD 
(pin 11). 


Bell 103 Tone Allocation 


Data 

Originate Modem 

Answer Modem 

Transmit 

Receive 

Transmit 

Receive 

Space 

1070 Hz 

2025 Hz 

2025 Hz 

1070 Hz 

Mark 

1270 Hz 

2225 Hz 

2225 Hz 

1270 Hz 


2-141 


AN-347 




AN-347 


Squelch Transmitter 

Transmitter squelch is achieved by putting SQT = Vcc 
(SQT is pin 14). The line driver remains active in this state 
(assuming ALB = GND), 

This state is commonly used during the protocol of estab- 
lishing a call. The originate user initiates a phone call with 
its transmitter squelched, and waits for a tone to be re- 
ceived before beginning transmission. During the wait 
time, the modem is active to allow tone detection, but no 
tone may be transmitted. 

The state SQT = Vcc rriay also be used if the line driver is 
required but a signal other than modem tones (e.g., DTMF 
tones or voice) is to be transmitted. This is discussed fur- 
ther in Transmission of Externally Generated Tones (sec- 
tion 3d). 

Analog Loop Back 

ALB = Vcc, SQT = GND selects the state “analog loop 
back”. (The state ALB = SQT = Vcc is discussed in the 
following section.) 

In analog loop back mode, the modulator output (at the 
line driver) is connected to the demodulator input (at the 
hybrid), and the demodulator is tuned to the transmitted 
frequency tone set. Thus the data on the TXD pin will, after 
some delay, appear at the RXD pin. This provides a simple 
“self test” of the modem. 

The signal applied to the demodulator during analog loop 
back is sufficient to cause the carrier detect output CD to 
go low indicating receipt of carrier. 

In analog loop back mode, the modulator and transmitter 
are active, so the transmitted tone is not squelched. 

Power-Down Mode 

The state SQT = ALB = Vcc puts the MM74HC942/943 in 
power-down mode. In this state, the entire circuit except 
the oscillator is disabled. (The oscillator is left running in 
case it is required for a system clock) . In power-down 
mode the supply current falls from 8 mA (typ) to 180 fiA 
(typ), and all outputs, both analog' and digital, TRI-STATE 
(become Hi-Z). 


Using TRI-STATE Capability 


ALB' 


SQT' 



CHIP 

SELECT 


The ability of the outputs to TRI-STATE allows the modem 
to be connected to other circuitry in a bus-like configura- 
tion with the state SQT or ALB = GND being the modem 
chip select. 

c) The Oscillator 

The oscillator is a Pierce crystal oscillator. The crystal 
used in such an oscillator is a parallel resonant crystal. 


The Oscillator 



The capacitors used on each end of the crystal are a com- 
bination of on-chip and stray capacitances. This generally 
means the crystal is operating with less than the specified 
parallel capacitance. This causes the oscillator to run 
faster than the frequency of the crystal. This is not a prob- 
Jem as the frequency shift is small (approximately 0.1%). 

The oscillator is designed to run with equal capacitive 
loading on each side of the crystal. This should be taken 
into consideration when designing PC layouts. This need 
not be exact. 

If a 3.58 MHz oscillator is available, the XTALD pin may be 
driven. The internal inverter driving this pin is very weak 
and can be overpowered by any CMOS gate output. 


TL/F/5531-1 


2-142 




The Oscillator and Power-Down Mode 

When the chip powers down, all circuits except the oscil- 
lator are switched off. The oscillator is left running so it 
may be used as a clock to drive other circuits within the 
system. 

It is possible to shut the oscillator down by clamping the 
XTALS pin to Vcc or GND. This will cause the total chip 
current to fall to less than 5 /^A. This may be useful in bat- 
tery powered systems where minimizing supply current is 
important. 

Powering Down the Oscillator 

r MM74HC942/943 



TL/F/5531-3 

2) MODULATOR SECTION 
a) Operation 

The modulator receives data from the transmit data (TXD) 
pin and synthesizes a frequency shift keyed, phase 
coherent sine wave to be transmitted by the line driver 
through the transmit analog (TXA) pin. Four different sine 


wave frequencies are generated, depending on whether 
the modem is set to the orginate or answer mode and 
whether the data input to TXD is a logical high or low. See 
Timing and Control (section 1) for more information. 

The TXD and 0/A pins set the divisor of a dual modulus 
programmable divider. This produces a clock frequency 
which is sixteen times the frequency of the carrier to be 
transmitted. The clock signal is then fed to a four bit 
counter whose outputs go to the sine ROM. The ROM acts 
like a four-to-sixteen decoder that selects the appropriate 
tap on the D/A converter to synthesize a staircase- 
approximated sine wave. A switched capacitor filter and a 
low pass filter smooth the sine wave, removing high fre- 
quency components and insuring that noise levels are 
below FCC regulations. 

b) Transmit Level Adjustment 

Themaximumtransmit leveloftheMM74HC943is -9 dBm. 
Since most phone lines attenuate the signal by 3 dB, the 
maximum level that will be received at the exchange is 
- 12 dBm. This level is also the maximum allowed by most 
phone companies. The MM74HC942 has a maximum 
transmit level of 0 dBm, making possible adjustments for 
line losses up to - 12 dB. The resistor values required to 
adjust the transmit level for both the MM74HC942 and the 
MM74HC943 follow the Universal Service Order Code and 
can be found in the data sheets. This resistor added be- 
tween the TLA pin and Vcc serves to control the voltage 
reference at the top of the D/A ladder, adjusting output 
levels accordingly. 

Note that for transmission above -9 dBm the required 
resistor must be chosen with the co-operation of the rele- 
vant phone company. This resistor is usually wired into the 
phone jack at the installation as the resistor value is 
specific to the particular phone line. This is called the 
Universal Registered Jack Arrangement. This arrange- 
ment is possible only with the MM74HC942 because of the 
dynamic range constraints of the MM74HC943. 


The Modulator 



TRANSMIT 

CARRIER 

(fc) 


TUF;5531-4 



2-143 


AN-347 





AN-347 


3) THE LINE DRIVER 
a) Operation 

The line driver is a class A power amplifier for transmitting 
the carrier signals from the modulator. It can also be used 
to transmit externally generated tones such as DTMF sig- 
nals, as discussed in section 3d. When used for trans- 
mitting modem-produced tones, the external input (EXI) 
pin shouid be grounded to pin 19 for both the MM74HC942 
and the MM74HC943.The line driver output isthetransmit 
analog (TXA) pin. 

The Line Driver Equivalent Schematic 


+ Vcc 



TL/F/5531 5 


b) Second Harmonic Distortion 

If the modem is operating in the originate mode, the line 
driver output has frequencies of 1070 Hz for a space and 
1270 Hz for mark. The second harmonic for a space fre- 
quency is at 2140 Hz, and this falls in the originate modem’s 
receive frequency band from 2025 Hz to 2225 Hz. While the 
modulator produces very little second harmonic energy, the 
amplifier has been designed not to degrade the analog out- 
put any further. The result is that the second harmonic is 
below - 56 dBm. Thus it is well below the minimum carrier 
amplitude recognized by the demodulator. 


DTMF, voice or other externally generated tones. Both the 
inverting and non-inverting inputs to the line driver are 
available for this purpose. A DTMF tone generator with a 
TRI-STATE output may instead be directly connected to 
the same node as the TXA pin rather than the line driver. 
The choice of which method to use depends on whether 
the MM74HC942 or MM74HC943 is being used and the sig- 
nal level of the transmission. Most phone companies 
allow DTMF tone generation at 0 dBm. This level is the 
maximum that the MM74HC942 can produce and is be- 
yond the range of the MM74HC943. 

If the line driver is to be used for external tone generation, 
the modem must be powered up and the transmission 
must be squelched by the SQT pin being held high. This 
will disable the output of the modulator section. The 
choice between the EXI pin and DSI pin is up to the user. 
The EXI pin gives a fixed gain of about 2. The DSI input 
ailows for adjustable gain as a series resistor is 
necessary. 

Using the DSI input 



A better soiution may be to use the power-down mode of 
the MM74HC942/943 with a DTMF tone generator that has 
a TRI-STATE output. Such a device is a TP53130 and is 
shown in the diagram following. When the tone generator 
is not in use and the modem is not squelched, the DTMF 
generator’s output is in TRI-STATE. Rather than using the 
line driver, the tone generator’s output is instead con- 
nected to the same node as the TXA pin. The tone gener- 
ator is active when the modem is in power-down. Power- 
down TRI-STATEs the TXA output. 


c) Dynamic Range 


Interfacing to DTMF tjlenerator Using TRI-STATE Feature 


The decision to usetheMM74HC942ortheMM74HC943is 
a tradeoff between output dynamic range and power sup- 
piy constraints. The power supply is discussed in another 
section. The MM74HC942 will transmit a( 0 dBm while the 
maximum transmit level of the MM74HC943 is -9 dBm. 
This level applies to externaiiy generated tones as well as 
the standard modem tone set. 

It is important to realize that the signal levels referred to 
above, and in the data sheet’s specifications, are the 
leveis referred to a 600n load resistor (representing the 
phone line) when driven from the external 600D source 
resistor. Also, the transmit levels discussed previously are 
maximum values. Typical values are 1 dB to 2 dB below 
these. 

d) Transmission of Externally Generated Tones 

Since a phone line connection is usually made on theTXA 
pin, it may be useful to use the line driver to transmit 



C TO PHONE 

LINE 


TL/F/5531-7 


‘2-144 




4) THE HYBRID 

The MM74HC942/943 has an on-chip hybrid. (A hybrid in 
this context refers to a circuit which performs two-to-four 
wire conversion.) 

Under ideal conditions the phone line and isolation net- 
work have an equivalent input impedance of 600P. Under 
these conditions the gain from the transmitter to the op 
amp output is zero, while the gain from the phone line to 
the op amp output is unity. Thus the hybrid, by subtracting 
the transmitted signal from the total signal on the phone 
line, has removed the transmitted component. 

Unfortunately, these ideal conditions rarely exist and 
filtering is used to remove the remaining transmitted 
signal component. This is discussed further in the next 
section. 


Note that the signals into the hybrid must be referred to 
GND in the MM74HC942 and GNDA in the case of the 
MM74HC943. Thus blocking capacitors are required in the 
latter case. This is discussed further in DC Levels and 
Analog Interface (section 9a). 


5) THE RECEIVE FILTER 

The signal from the hybrid is a mixture of transmitted 
and received signals. The receive filter removes the 
transmitted signals so only received signal goes to the 
discriminator. 

The receive filter may be characterized by driving RXA1 or 
RXA2 with a signal generator. The filter response may then 
beobserved at the FTLCpin with the capacitor removed. In 
this state the output impedance of the FTLC pin is 16 kfi 
nominal. 

6) THE FTLC PIN 

The FTLC pin is at the point of the circuit where the receive 
filter output goes to the hard limiter input and the carrier 
detect circuit input. 

The signal at the output of the receive filter may be as low 
as 7 mVrms. It is thus important that the wiring to the FTLC 
pin and the associated circuit be clean. Ideally the track 
from the capacitor to pin 19 (GND on the MM74HC942, 
GNDA on the MM74HC943) should be shared by no other 
devices. 

If these precautions are not observed, circuit performance 
may be unnecessarily degraded. 


The Hybrid 



TL/,‘^/5531-fj 


Characterizing the Receive Filter 


The FTLC Pin and Associated Circuitry 


MM74HC942/943 *^1 



RECEIVE 

FILTER 

OUTPUT 


r HARD LIMITER ""1 



GROUND/ 

NOISE' 


TL;F/5531-9 


tl;f/553mo 



2-145 


AN-347 





AN-347 


7) the carrier detect circuit 

a) Operation 

The carrier detect circuit senses if there is carrier present 
on the line. If carrier is not present, the data output is 
clamped high. 

The RC circuit filters the DC from the output of the receive 
filter. The comparator inputs are thus the filter output, and 
the DC level of the receive filter minus the controlled off- 
set. The controlled offset sets the amount that the AC sig- 
nal must exceed the DC, level (and thus the AC amplitude) 
before the comparator Switches. When this happens, the 
comparator output sets a resettable one-shot \A/hlch con- 
verts the periodic comparator output to a continuous 
signal. This signal then controls the time delay set by the 
CDT pin. After the preset time delay the CD bar output 
goes low. This shifts the comparator offset providing 
hysteresis to the overall circuit. 

b) Threshold Control 

The carrier detect threshold may be adjusted by adjusting 
the voltage on the CDA pin. 

The carrier detect trip points are nominally set at 
-43 dBm and -46 dBm. The CDA pin sits at a nominal 
1.2V. The carrier detect trip polnts are directly proportional 
to the voltage on this pin, so doubling the voltage causes a 
6 dB increase in the carrier detect trip points. Similarly, 
halving the voltage causes a 6 dB decrease in carrier 
detect trip points. 

Note that as the carrier detect trip point is reduced, the 
system noise will approach the carrier level, and the ac- 
curacy and predictability of the carrier detect trip points 
will decrease. 

The output impedance of the CDA pin his high. It Is con- 
stant (±10%) from die to die but has a very high 
temperature coefficient. It is thus advisable, if the CDA pin 
Is driven, to drive from a low source impedance. 

Because the output impedance of the CDA pin is high, 
capacitive coupling from the adjacent XTALD pin can pre- 
sent a problem. For this reason a 0.1 /xF capacitor is usu- 
ally connected from the CDA pin to ground. If the CDA pin 
is driven from a low impedance source, this capacitor may 
be omitted. 


If a resistor is connected from the CD bar pin to the CDA 
pin, the CDA voltage will vary depending on whether car- 
rier is detected. This will effectively increase the carrier 
detect hysteresis. 


Increased Carrier Detect Hysteresis 



Similarly an inverter and a resistor from the CD bar pin to 
the CDA pin will reduce the hysteresis. This is not recom- 
mended as the 3 dB nominal figure chosen is close to the 
minimum value useable for stable operation. 

c) Timing Conrol 

The capacitor on the CDT pin adjusts the amount of time 
that carrier must be present before the carrier is recog- 
nized as valid. 

This circuit is designed for a long off-to-on time compared 
to the on-to-off time. This means carrier must be present 
and stable to be acknowledged, and that if carrier is 
marginal It will be rejected quickly. 

The equations for the capacitor value are 
Ton-to-off = C * 0.54 seconds 
and 

Toff-^o-on “ ^ * 0-4 seconds. 

The ratio of on-to-off and off-to-on times may be adjusted 
over a narrow range by the addition of pull-up or pull-down 
resistors on the CDT pin. 


Carrier Detect Block Diagram 


RECEIVE FILTER 
OUTPUT 


Vcc 



TL/F/553M1 


2-146 




The repeatability of the times is high from die to die at 
fixed temperature, but is strongly temperature dependent. 
The times will shift by approximately ± 30% over process 
and temperature. 

8) THE DISCRIMINATOR 

a) The Hard Limiter 



The signal to the inverting input of the comparator has the 
same DC component as the signal to the non-inverting in- 
put. The differential input to the comparator is thus the AC 
component of the filter output. The comparator has very 
low input offset and so the limiter will operate with very 
low input signal levels. > 

The demodulator employed requires an input signal hav- 
ing equal amplitude for a mark and a space. It also re- 
quires a high level signal. The hard limiter converts all 
signals to a square wave. All amplitude information is lost 
but frequency information is retained. 

By removing the capacitor from the FTLC pin, the hard 
limiter ceases to operate, but the filter output may be 
observed. This is useful for circuit evaluation and testing. 

b) Discriminator Operation 

The discriminator separates the incoming energy into 
mark and space energy. This occurs in the band pass 
filters which are tuned to the mark and space frequencies. 
The outputs of the mark and space band pass filters are 
rectified to extract the output amplitudes. The rectifier 
outputs are filtered to remove ripple. The low pass filter 
outputs are compared to determine if the mark or space 
path is receiving greater energy, and thus if the incoming 
data is a mark or a space. 

The output of the discriminator is only valid if carrier is 
being received. If carrier is not being received (as deter- 
mined in the carrier detect circuit) the RXD output is 
clamped high. This stops the discriminator from attempt- 
ing to demodulate a signal which is too low for reliable 
operation. 


9) POWER SUPPLIES 

a) DC Levels and Analog Interface 

The MM74HC942 refers all analog inputs and outputs to 
GND (pin 19). The analog interface thus requires no DC 
blocking capacitors. 

The MM74HC943 refers all analog inputs and outputs to 
GNDA (pin 19) which requires a nominal 2.5V supply. The 
current requirements of GNDA are low, so the GNDA sup- 
ply may be derived with a simple resistive divider. The 
GNDA supply can then be referenced to GND using ca- 
pacitors. This GNDA supply will have poor load regulation 
so the high current interface must be connected to GND 
and a DC blocking capacitor used. 

As the FTLC capacitor is connected to the input of the hard 
limiter, any noise on the FTLC ground return will couple 
directly into this circuit. The signal on FTLC may be only 
millivolts, so It is important that the FTLC capacitor 
ground be at the same potential as the chip’s ground 
reference. Thus when using the MM74HC943 the FTLC 
capacitor ground return should go directly to GNDA (pin 
19). For both the MM74HC942 and MM74HC943 this 
ground return should be shared by no other circuits. 
Failure to observe this precaution could result in un- 
necessary reduction of dynamic range and carrier detect 
accuracy, and an increase in error rate. 

b) Power Supply Noise 

It is important that the power supplies to the 
MM74HC942/943 be stable supplies, having low noise, 
particularly in the frequency band from 50 kHz to 10 MHz. 

The MM74HC942/943 use switched capacitor techniques 
extensively. A feature of switched capacitor circuits is 
their ability to translate noise from high frequency bands 
to low frequency bands. At the same tirne it is difficult to 
design op amps with high power supply rejection at high 
frequencies. (The MM74HC942/943 has 19 op amps inter- 
nally.) As a result the high frequency PSSR of the 
MM74HC942/943 is not high, so high frequency noise on 
the power supply can degrade circuit operation. 

This should not cause a problem if the circuits are 
powered from a three terminal regulator, and no other cir- 
cuitry shares the regulator. Power supply noise could be a 
problem If; 

a) One or both of the power supplies are switching regu- 
lator circuits. Switching regulators can produce a lot of 
supply noise. 

b) The modem shares its supply with a large digital cir- 
cuit. Digital circuits, particularly high speed CMOS (the 
HC family) can produce large spikes on the supplies. 
These spikes have wide spectral content. 


FROM 

RECEIVE 

FILTER 



DEMODULATED 

DATA 



2-147 


AN-347 




AN-347 


Ideally the modem could have its own supply. This may not 
be cost effective, so in some applications power supply 
filters may be necessary. These may just be RC filters but 
LC filters may be necessary depending on the extent of the 
supply noise. Miniature inductors in half watt resistor 
packages are cheap, lend themselves to automatic inser- 
tion, and are Ideal for these filters. 


It Is difficult to set specifications for a “clean” supply 
because spectral density considerations are important. 
The following guidelines should be taken as “rule of 
thumb”: 

a) From 50 kHz to 20 MHz the ripple should not exceed 
-60dBV. 

b) From DC to 50 kHz the ripple should not exceed 
-50dBV. 


MM74HC942 Analog Interface 



MM74HC943 Analog Interface 



TO 

PHONE 

LINE 


T 


2-148 




CMOS 300 Baud Modem 


National Semiconductor 
Application Note 349 
Anthony Chan 
Peter Single 
Daniel Deschene 
April 1984 



INTRODUCTION 

The advent of low cost microprocessor based systems 
has created a strong demand for low cost, reliable means 
of data communication via the dial-up telephone network. 
The most widespread means for this task Is the Bell 103 
type modem, which has become the de facto standard of 
low speed modems. This type of modem uses frequency 
shift keying (FSK) to modulate binary data asynchron- 
ously at speeds up to 300 baud. 

The success of this type of modem, despite its modest 
transmission speed, is largely due to its ability to provide 
full duplex data transmission at low error rates even with 
unconditioned telephone lines. It also has a significant 
cost advantage over the other types of modems available 
today. Advances in CMOS and circuit design technology 
have made possible the MM74HC942— a high perform- 
ance, low power. Bell 103 compatible single chip modem. 
This chip combines both digital and linear circuitry to 
bring the benefits of system level integration to modem 
and system designers. 

THE PROCESS— microCMOS 

The chip was designed with National’s double poly CMOS 
(microCMOS) process used extensively for its line of PCM 
CODECs and filters. This is a self-aligned, silicon gate 
CMOS process with two layers of polysilicon, one of which 
is primarily used for gates of the MOS transistors. Thus 
there are three layers of interconnect available (two 
polysilicon and one metal layer) making possible a very 
dense layout. 

The two polysilicon layers also offer a near perfect 
capacitor structure which is used to advantage in the 
linear portions of the chip. The self-aligned silicon gate P 
and N-chanei MOSFETs combine high gain with minimal 
parasitic gate-to-drain overlap capacitance, facilitating 
the design of operational amplifiers with high gain-band- 
width product and excellent dynamic range. 

CHIP ARCHITECTURE 

The chip architecture was arrived at after critically 
evaluating several trial system partitionings of the Bell 
103 type data set. The overriding goal was to integrate as 
much of the function as possible without sacrificing ver- 
satility and cost effectiveness in new applications. The 
resulting chip architecture reflects this philosophy. Since 
the majority of users of this device would probably be 
digital designers unfamiliar with filter design and analog 
signal processing, inclusion of these functions was thus 

Reprinted from Midcon/82 


mandatory. The precision filters needed for a high per- 
formance modem also make discrete implementations ex- 
pensive. On the other hand, the majority of new systems 
will typically include a microprocessor which is quite 
capable of handling the channel establishment protocol. 
Besides, different systems may require different proto- 
cols. Circuitry for this task was therefore omitted. 

A block diagram illustrating the chip architecture is 
shown in Figure 1. The on-chip line driver and line hybrid 
greatly simplify interfacing to the phone line by saving two 
external op amps. The output of the line hybrid, which is 
used to reduce the effect of the local transmit signal on 
the received signal, goes to a programmable receive band- 
pass filter. This filter improves the signal-to-noise ratio at 
the input of the frequency discriminator, which performs 
the actual FSK demodulation. The output of the receive 
filter is also monitored by a carrier detector which com- 
pares the amplitude of the received signal to an externally 
adjustable threshold level. 

The modulator consists of a frequency synthesizer which 
generates a clock at ^frequency determined by the TXD 
(transmit data) and 0/A (originate/answer) inputs. This is 
subsequently shaped by the sine converter into the final 
modulated transmit carrier signal. 

All internal clocks and control signals are derived from an 
on-chip oscillator operating from a common 3.58 MHz TV 
crystal. On-chip control logic allows the modem to be set 
to answer or originate mode operation, or to an analog 
loop-back mode via the 0/A and ALB inputs respectively. 
The line driver can be squelched via the SOT input, which 
typically occurs during the channel establishment 
sequence. 

Another feature of this design not obvious from the block 
diagram of Figure 1 is that the chip can be powered down 
by asserting the ALB and SOT inputs simultaneously, a 
condition that does not occur during normal operation. 
This cuts power consumption to typically under 50 
making it very suitable for battery operation. 

DEMODULATOR 

Receive Filler 

This is a nine pole, switched capacitor^’ ^ bandpass filter. 
It is programmable by Internal logic to one of two pass- 
bands, corresponding to originate or answer mode opera- 
tion. The measured frequency response of the filter is 
shown in Figure 2. It shows that better than 60 dB of adja- 
cent channel rejection has been achieved. Note also the 
deep notches at the frequencies of the locally transmitted 
tone pair. 



2-149 


AN-349 





FIGURE 1. Chip Architecture of the MM74HC942 



FIGURE 2. Measured Frequency Response of the Receive Filter 



A key design goal was to minimize the delay distortion of 
the filter. This has also been met as evidenced by the delay 
response curves shown in Figures 3a and 3b. These curves 
have been normalized to the delays at 1170 Hz and 2125 Hz 
respectively. They show that the delay distortion in the 
1020 Hz to 1320 Hz band Is approximately 70 ns, while that 
in the 1975 Hz to 2275 Hz band is approximately 110 fis. 
These bands contain all the significant sidebands of a 
300 baud FSK signal. The low delay distortion of the re- 
ceive filter translates directly into low jitter in the demodu- 
lated data. 

An on-chip, second order, real time anti-aliasing filter 
precedes the receive filter. This masks the sampled data 
nature of the switched capacitor design from the user, 
contributing to the ease of use of the chip. 

Frequency Discriminator 

Referring to Figure 4, the filtered receive carrier Is first 
hard limited to remove any residual amplitude modula- 
tion. It is then split into two parallel, functionally identical 
paths, each consisting of a second order bandpass filter 



FIGURE 3a. Normalized Deiay Response of the Receive 
Filter in Answer Mode 


(BPF), a fuli wave detector and a post detection lowpass 
filter (LPF). 

The bandpass filter In the upper path is tuned to the ‘mark’ 
frequency, and that in the lower path to the ‘space’ fre- 
quency. The detectors are full wave rectifier circuits 
which, together with the post detection filters, measure 
the energy in the mark and space frequencies. These are 
compared by the trailing comparator to decide whether a 
mark or space has been received. 

Carrier Detector 

The carrier detector compares the output of the receive 
filter against an externally adjustable threshold voltage. 
Referring back to Figure 1, if the CDA (carrier detect ad- 
just) pin is left floating, the threshold is nominally set to 
ON at -44 dBm, and OFF at -47 dBm. This can be 
modified by forcing an external voltage at the CDA input. If 
the received carder exceeds the set threshold, the CD (car- 
rier detect) output will go low after a preset time delay. This 
delay is set externally by a timing capacitor connected to 
the CDT (carrier detect timing) pin. 



FIGURE 3b. Normalized Deiay Response of the Receive 
Filter in Originate Mode 


FROM 

RECEIVE 

FILTER 



FIGURE 4. Block Diagram of the Frequency Discriminator 



2-151 


AN-349 




AN-349 


MODULATOR 

As shown in Figure 5, the modulator consists of a fre- 
quency synthesizer and a sine wave converter. The trans- 
mit data (TXD) and mode (0/A) inputs set the divisor of a 
dual modulus programmable divider. This produces a 
clock at sixteen times the frequency of the transmitted 
tone. This then clocks a four bit counter, whose states 
represent the voltage levels corresponding to the sixteen 
time slots in one cycle of a staircase approximated sine 
wave. The sine ROM decodes the state of the counter and 
drives a digital-to-analog converter to synthesize the fre- 
quency shift keyed sine wave. This modulator design also 
preserves phase coherence in the transmit carrier across 
frequency excursions. 



TRANSMIT 

CARRIER 

(fc) 


TL/F/5532-6 


FIGURE 5. Modulator Block Diagram 


The reference voltage for the digital-to-analog converter is 
derived from a reference generator controlled by an exter- 
nal resistor (RTLA). This allows the transmit signal level to 
be programmable in accordance with the Universal Serv- 
ice Order Code. This code specifies the programming re- 
sistances corresponding to various transmit levels.’ If no 
external resistor ls connected, the transmit level defaults 
to - 12 dBm. 

The synthesized sine wave is filtered by a second order, 
real time lowpass filter to remove spurious harmonics 
before being fed to the line driver amplifier. 

LINE INTERFACE 

Line Driver 

This is a class A power amplifier designed to drive a 600f} 
line through an external 600n terminating resistor. With 
the proper transmit level programming resistor installed, 
it will drive the line at 0 dBm when operated from ± 5V sup- 
plies. The quiescent current of the output stage of the 
driver varies with the programmed transmit level to max- 
imize the efficiency of the amplifier. A class A design was 
chosen mainly because It can tolerate a wider range of 
reactive loads. 

As shown in Figure 6, both inverting and non-inverting in- 
puts of the driver amplifier are accessible externally, mak- 
ing it easy to accommodate an' external signal source, 
such as a tone dialer. An external capacitor can also be 
connected between the inverting input and the amplifier 
output to give it a lowpass response. 

Line Hybrid 

The line hybrid is essentially a difference amplifier which, 
when connected as shown in Figure 6, causes the trans- 
mit carrier to appear as common-mode signal and be can- 
celled from the output, if the termination resistor (Rj) and 
phone line impedance are perfectly matched, the output 
of the line hybrid would be just the received carrier. In prac-.' 
tice, perfect matching is impossible and 10 dB to 20 dB of 
transmit carrier rejection is more realistic. The residual is 
more than adequately rejected by the receive filter of the 
demodulator. 


MM74HC942 


Rt 

LINE 

TERMINATION 

RESISTOR 



PHONE 

LINE 



TL;F/5532-7 

FIGURE 6. Typical Interface Between the MM74HC942 and the Phone Line 


2-152 




TIMING AND CONTROL 

This includes an oscillator amplifier, divider chain and in- 
ternal control logic. The oscillator, in conjunction with an 
external 3.58 MHz TV crystal and the divider chain, pro- 
vides all the internal clocks for the switched capacitor cir- 
cuits and the frequency synthesizer. The control logic or- 
chestrates the various operating modes of the chip (e.g., 
originate, answer or analog loop-back modes). 


APPLICATIONS 

Figure 7 shows the MM74HC942 in an acoustically coupled 
modem application. It demonstrates the simplicity of the 
resulting design and a dramatic reduction in parts count. 
F/gt/re 5 shows two typical direct connect modem applica- 
tions. The simplicity of these circuits is again evident. 

The simple power supply requirement (±5V), low power 
(60 mW when transmitting at -9 dBm, 0.5 mW standby) 
and low external component count makes the MM74HC942 
an efficient implementation of the 300 baud modem 
function. 



FIGURE 7. Typical Implementation of an Acoustically Coupled Modem Using the MM74HC942 




2-153 


AN-349 




AN-349 


2 WIRE CONNECTION 


4 WIRE CONNECTION 




^COMMUNICATION^ 
CHANNEL 
OR 

PHONE LINE 


600 

-WSr- 


I I 



FIGURE 8. Typical Implementations of Direct Connect Modems Using the MM74HC942 


SUMMARY 

In conclusion, the MM74HC942 integrates the entire data 
path of a Bell 103 type data set into a 20-pin package with 
the following features: 

• On-chip 9 pole receive filter 

• Carrier detector with adjustable threshold 

• Analog demodulator with low bit jitter and bias 

• Phase coherent modulator with low spurious harmonics 

• 600n line driver wifh adjustable transmit level 

• On-chip line hybrid 

• Full duplex originate or answer mode operation 


• Low power operation, power-down mode 

• Simple supply requirements ( ± 5V) 

REFERENCES 

1 . J . Caves et al., “Sampled Analog Filtering using Switched 
Capacitors as Resistor Equivaients”, IEEE Journal of Solid 
State Circuits, Vol. SC-12, No. 6, Dec. 1977 

2. W. Black et al., “A High Performance Low Power CMOS 
Channel Filter”, IEEE Journal of Solid State Circuits, Vol. 
SC-15, No. 6, Dec. 1980 


2-154 




Designing an LCD Dot Matrix 
Display Interface 


National Semiconductor 
Application Note 350 
Bob Lutz 
February 1984 



The MM58201 is a CMOS LCD driver capable of driving a 
multiplexed display of up to 192 segments (24 segment 
columns by 8 backplanes). The number of backplanes 
being driven is programmable from oneto eight. Data to be 
displayed is sent to the chip serially and stored in an inter- 
nal RAM. An external resistor and capacitor control the 


frequency of the driving signals to the LCD. The MM58201 
can also be programmed to accept the oscillator output 
and backplane signals of another MM58201 for cascading 
purposes. The displayed data may also be read serially 
from the on-chip RAM. A simplified functional block 
diagram of the MM58201 is shown in Figure 1. 


BACKPLANES 



FIGURE 1. MM58201 Functional Diagram 



2-155 


AN-350 




AN-350 




BACKGROUND 

LCD displays have become very popular because of their 
ultra-low power consumption and high contrast ratio 
under high ambient light levels. Typically an LCD has a 
backplane that overlaps the entire display area and mul- 
tiple segment lines that each overlap just one segment or 
descriptor. This means that a separate external connec- 
tion is needed for every segment or descriptor as shown in 
Figure 2. For a display with many segments such as a dot 
matrix display, the number of external connections could 
easily grow to be very large. 

Unlike other display technologies that respond to peak or 
average voltage and current, LCDs are sensitive to the rms 
voltage between the backplane and given segment loca- 
tion. Also, any DC bias across this junction would cause 
an irreversible electrochemical action that would shorten 
the life of the display. A typical LCD driving signal Is 
shown in Figure 3. The backplane signal is simply a sym- 
metrical square wave. The individual segment outputs are 
also square waves, either in phase with the backplane for 
an “off” segment or out of phase for an “on” segment. 
This causes a Vrms of zero for an “off” segment and a 
Vrms of -k V for an “on” segment. 


One way to reduce the number of external connections is 
to multiplex the display.'An example of this could be an 
LCD with its segments arranged as intersections of an X-Y 
grid. A driver to control a matrix like this would be fairly 
straightforward for an LED display. However, it is more 
complex for an LCD because of the DC bias restriction. 

A multiplexed LCD driver must generate a complex set of 
output signals to insure that an “on” segment sees an rms 
voltage greater than the display’s turn-on voltage and that 
an “off” segment, sees an rms voltage less than the dis- 
play’s turn-off voltage. The driver must also insure that 
there is no DC bias. 

One pattern that can accomplish this is shown as an ex- 
ample in Figure 4. This is the pattern that the MM58201 
uses. The actual Vrms of an “on” segment and an “off” seg- 
ment is shown in Figure 5. If there are eight backplanes, the 
Vrms{ON) = 0.2935 x Vjc and the Vrms(OFF) = 0.2029 x Vtc- 
It can be seen in Figure 6 that as the number of backplanes 
increases, the difference between Vrms (ON) and Vrms (OFF) 
becomes less. Refer to the specifications of the LCD to de- 
termine exactly what Vrms is required. 



TUBf5606-2 


“OFF” SEGMENT “1 [~\ 1"“ 

DRIVE (IN PHASE) ^ j | | | | j 

BACKPLANE ^ rLTUir 


“ON” SEGMENT 
DRIVE (180° OUT OF PHASE) 


□n_n_rL 


TL/B/5606-3 


FIGURE 2. Typical LCD Pin Connections 


FIGURE 3. Drive Signals from a Direct 
Connect LCD Driver 


POLARITY 



SI S2 
BP1 
BP2 

BP3 

■ =on (dark) 



TL/B/5606-4 


FIGURE 4. Example of Backplane and Segment Patterns 


/ 


2-156 







AN-350 



1 2 3 4 5 6 7 8 

NUMBER OF BACKPLANES 

TL/B/5606-7 

FIGURES. AVrms/VTc 


FUNCTIONAL DESCRIPTION 

Connecting an MM58201 to an LCD 

The backplane and segment outputs of the MM58201 con- 
nect directly to the backplane and segment lines of the 
LCD. These outputs are designed to drive a display with a 
total “on” capacitance of up to 2000 pF. This is especially 
important for the backplane outputs, as it is usually the 
backplanes that have the most capacitance. As the capac- 
itance of the output lines increases, the DC offset be- 
tween a backplane and segment signal may increase. 
Most LCD displays specify that a maximum offset of 
50 mV is acceptable. For backplane capacitance under 
2000 pF the MM58201 guarantees an offset of less than 
10 mV. „ 

If the LCD display to be used has 24 segments per back- 
plane or less, then each MM58201 should be configured as 
a “master” so that each one will generate its own set of 
backplane signals. However, if the LCD display has more 
than 24 segments per backplane, more than one MM58201 
will be needed for each backplane. To synchronize the driv- 
ing signals there must be one “master” chip and then an 
additional “slave” chip for every 24 segments after the 
first 24. When a chip is configured as a “slave” it does not 
generate its own backplane signals. It simply synchro- 
nizes itself to the backplane signals generated by a 
“master” chip by sensing the BP1 signal. An example of 
both an all “master” configuration and a “master-slave” 
configuration will be shown later. 


Since the input impedance of Vjc may vary between 10 kf2 
and 30 kO, the output impedance of the voltage reference 
at Vjc should be relatively low. One example of a Vjc driver 
is shown in Figure 8. To put the MM58201 in a standby 
mode, bring Vjc to Vss (ground). This will blank out the 
display and reduce the supply current to less than 300 nk. 


15V 



Vtc 


TL/B/5606-10 

FIGURES. Example of Vjc Driver 
RC Oscillator 

This oscillator works with an external resistor tied to Vqq 
and an external capacitor tied to Vss- The frequency of 
oscillation is related to the external R and C by; 

fosc = V1-25RC±30% 

The value of the external resistor should be in the range 
from 10 kt) to 1 Mfi. The value of the external capacitor 
should be less than 0.005 ixF. 

The oscillator generates the timing required for multiplex- 
ing the LCD.Thefrequencyof the oscillator is 4N times the 
refresh rate of the display, where N is the number of 
backplanes programmed. Since the refresh rate should be 
in the range from 32 Hz to 100 Hz, the oscillator frequency 
should be: 

128N<fosc<400N 

If the frequency is too slow, there will be a noticeable 
flicker in the display. If the frequency is too fast, there will 
be a loss of contrast between segments and an increase in 
power consumption. 

Serial Input and Output 


Voltage Control Pin and Circuitry 

The voltage presented at the Vjc pin determines the ac- 
tual voltage that is output on the backplane and segment 
lines. These voltages are shown in Figure 7. Vjc should be 
set with respect to Vrms (ON) and Vrms (OFF) and can be 
calculated as shown in Figure 5. 



TL/B/5606-8 


a. Backplane Output 


0.68 Vtc 
0.32 Vtc 

TLm/5606-9 

b. Segment Output 


FIGURE 7. Output Voltages 


Data is sent to the MM58201 serially through the DATA IN 
pin. Each transmission must consist of 30 bits of informa- 
tion, as shown in Figure 9. The first five bits are the ad- 
dress, MSB first, of the first column of LCD segments that 
are to be changed. The next bit is a read or write flag. The 
following 24 bits are the actual data to be displayed. 

The address specifies the first LCD column that is going to 
be affected. The columns are numbered as shown in 
Figure 10. Data is always written in three column chunks. 
Twenty-four bits of data must always be sent, even if some 
of the backplanes are not in use. The starting column can 
be any number between one (00000) and twenty-four 
(10111). If column 23 or 24 is specified the displayed data 
will wrap around to column 1. 

If the R/W bit is a “0” then the specified columns of the 
LCD will be overwritten with the new data. If the bit is a “1 ” 
then the data displayed in the specified columns will be 
available serially at the DATA OUT pin and the display will 
not be changed. 


2-158 




cs 1 I I I I I T r 

jTJTjnjTjnjnjiJTJTJ^ 

DATA IN DON’T CARE | A4 1 A3 | A2 | A1 | AO | R/W | D1 | D2 | D3 | • • • | D22 j D23 | D24 | DON’T CARE 

DATA OUT — ■ ■ — ■ I — ■■■ I D1 I D2 ^ D3 I • • • | D22 | D23 | D24 j 

TL/B/5606-11 

FIGURE 9. Transmission of Data 



SI 

S2 

S3 

S4 

S5 

S6 

S7 

SB 

S9 

S10 

S11 

SI 2 

S13 

S14 

S15 

SI 6 

S17 

S1B 

S19 

S20 

S21 

S22 

S23 

S24 


BP1 













D1 

09 

017 










B2 

_ J 

BP2 














D2 

DIO 

DIB 










B1 

4 

BP3 







1 






D3 

Oil 

019 










BO 

_ q 

BP4 













D4 

012 

D20 










M/s 

. J 

BP5 

1 












05 

013 

021 











BP6 













D6 

014 

022 










'' 

BP7 






r 








D7 

015 

023 











BPS 












j 

DB 

016 

024 






□ 































A4 

"T” 

~ir 

“o” 

IT 

0 

‘ 0 

0 

"1“ 

“T" 


0 

~T~ 

0 

0 

0 

0 

1 


1 

1 


1 

"T” 

1 

1 

A3 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

1 

1 

1 

1 

1 

1 

0 

0 

0 

0 


0 

0 

0 

1 

A2 

0 

0 

0 

0 

1 

M 

1 

1 

0 

0 

0 

0 

1 

1 

1 

1 

0 

0 

0 

0 

"T^ 

1 

1 

1 

0 

A1 

0 

0 

1 

1 

0 

PF 

1 

1 

0 

0 

1 

1 

0 

0 

1 

1 

0 

0 

1 

1 

0 

0 

1 

1 

0 

AO 

0 

1 

D 

1 

0 

1 

0 

1 

0 

1 

0 

1 

0 

1 

0 

in 

0 

1 

0 

1 

zn 

1 

0 

1 

0 


TL/B/5606 12 


Diagram above shows where data will appear on display if starting address 01 100 is specified in data format. 

FIGURE 10. Address of Particular Segment Columns 


The data is formatted as shown in Figure 10. The first bit in 
the data stream corresponds to backplane 1 in the first 
specified column. The second bit corresponds to back- 
plane 2 in the first specified column and so on. 

During initialization each MM58201 must be programmed 
to select how many backplanes are to be used, and 
whether the chip is to be a “master” or a “slave”. The for- 
mat of this transmission is just like a regular data trans- 
mission except for the following: the address must be 
11000; the R/W must be a write (0); the first three data bits 
must be selected from the list in Table I. The next bit 
should be a “1” for the chip to be a master or a “0” for the 
chip to be a slave. The following 20 bits are necessary to 
complete the transmission but they will be ignored. The 
mode cannot be read back from the chip. 


TABLE I. Backplane Select 


Number of 
Backplanes 

B2 

B1 

BO 

2 

0 

0 

1 

3 

0 

1 

0 

4 

0 

1 

1 

5 

1 

0 

0 

6 

1 

0 

1 

7 

1 

1 

0 

8 

1 

1 

1 


The timing of the CLK, CS, DATA IN, and DATA OUT are il- 
lustrated in Figure 11. The frequency of the clock can be 
between DC and 100 kHz with the shortest half-period 
being 5.0 iis. A transmission is initiated by CS going low. 


CS can then be raised anytime after the rising edge of the 
first clock pulse and before the rising edge of the last 
clock pulse (the clock edge that reads in D24). 30 bits of in- 
formation must always be sent. 

The data at DATA IN is latched on each rising edge of the 
clock pulse. The data at DATA OUT is valid after each fall- 
ing edge of the last 24 clock pulses. 

It is important to note that during a read or write trans- 
mission the LCD will display random bits. Thus the trans- 
missions should be kept as short as possible to avoid dis- 
rupting the pattern viewed on the display. A recommended 
frequency is: 

^osc = 30/(tLCD-7 ts) 

ticD = turn on/off time of LCD 

ts = time between each successive transmission 

This should produce a flicker-free display. 

The DATA OUT pin is an open drain N-channel device to 
Vss- This output must be tied to Vqd through a resistor if it 
is to be used. It could also be tied to a lower voltage if this 
output is to be interfaced to logic running at a lower 
voltage. The value of the resistor is calculated by: 

R = ( + V - 0.4)/0.0006 

+ V = voltage of lower voltage logic 

Power Supply 

Vqd can range between 7V and 18V. A voltage should be 
used that is greater than or equal to the voltage that you 
calculate for V-|-q as shown in Figure 5. 



2-159 


AN-350 



AN-350 



TYPICAL APPLICATIONS 

One application of the MM58201 is a general purpose 
display to show graphic symbols and text. This type of 
display could be gsed in an electronic toy or a small port- 
able computer or calculator. One such display is shown in 
Figure 12. This display consists of four separate LCD 
displays that 'are built into one housing. Each separate 
LCD display has 8 backplanes and 24 segment lines. The 
entire display will require four MM58201S to control it. 

The circuit diagram of this application is shown in Figure 14. 
Each separate LCD display is driven by one MM58201.The 
backplanes are driven by the separate MM58201s and are 
not paralleled together. There are three common lines; 
CLK, DATA IN, and DATA OUT. The CLK and DATA IN are 
generated from an output port such as an INS8255. Four 
other bits of the output port generate a linear select with a 
different bit going to each MM58201 chip select as shown 
in Figure 13. DATA OUT is sent to one bit of an input port. 


The Vjc driver is as described beforehand. The MM74C9l)6 
is an open drain CMOS buffer that has near regular TTL 
compatible inputs. This is to provide level translation from’ 
the 5V supply of the computer system to the 1 2V supply of 
.theMM58201. 

If I/O ports are not available, the circuit in Figure tS'Could 
be used as an interface between the MM58201s and a 
microprocessor bus. 

To reduce the number of connections between the circuit 
and the LCD, all of the backplanes could have been driven 
by one MM58201 as shown in Figure 16. The other 
MM58201S would be configured as “slaves” synchronized 
to the one “master” MM58201 . This would save 24 connec- 
tions to the LCD but would increase the capacitance of the 
backplanes. In this application the capacitance is not a 
problem with either setup. 



FIGURE 11, Timing of One Transmission 


SI S24 


I I • • ° I I I I • • • I I 


LCDO 


LC01 




LCD 2 


LCD 3 


rL/B/b606-14 


7 

6 

5 

4 

'3 

2 

1 

0 

DATA 

IN 

CLK, 

□ 

□ 

CS4 

C^ 

C^ 

C^ 


TL/B;5606 


CS4 CSS CS2 CS1 

1110 
110 1 
10 11 
0 1 1 1 , 
1111 


Chip 1 selected 
Chip 2 selected , 
Chip 3 selected 
Chip 4 selected 
No chip selected 


FIGURE 12. Four Separate LCD Displays FIGURE 13. Chip Select Scheme 

Positioned to Look Like One Display 


2-160 





INPUT <7. 5k 

PORT nATA niiT I 


128 CONNECTIONS FROM LCD 


FIGURE 14. Diagram of Application 


D3 O 3 

IV1M74HC374 
D4 O 4 * 


Do 06 

CL OC 


1 2 / INPUT 
I X '1 PORT 


^ 4 1 DIVI74LS126 

ADDRESS 6 | V> • 

DECODE X— ^ 

MIV174HC02 


WR ^ 1 
ADDRESS _T] 
DECODE * 


a. Output Port 


b. Input Port 


FIGURE 15- Input and Output Ports for Interface 


2-161 










AN-350 


12V 



FIGURE 16. Diagram of Master-Slave Set-Up Not Used for this Application 


SOFTWARE 

The real heart of this system is the software which con- 
sists of four parts. Part one is the initialization portion. 
This sets up the MM58201s as “masters” and programs 
them for 8 backplanes. It then sets up the needed pointers 
for the other subroutines which consist of: 


1) GRAPH: displays pattern on LCD. 

2) TEXT: prints ASCII characters on display. 

3) SCROLL: scrolls whatever pattern is displayed to 

the right until LCD is cleared. 


This application used an NSC800^^ with 8080 mnemon- 
ics. It could easily be adapted for other microprocessors. 


MAIN 

This progam initializes the MM58201s. It controls the se- 
quence of display output by calling other programs. 

It first sends out a “dumrhy” transmission to make sure 
that the chips are ready to respond to a valid transmission. 
It then programs the chips to be “masters” and to use 
eight backplanes. 

After initialization, this program sets up the correct, 
pointers to display a graphic symbol. First it displays the 
upper eight bits of it, then it displays the lower eight bits. 

The words “TESTING MM58201” are then displayed. A call 
to scroll then causes this to scroll to the right until the 
screen is blank. Finally the words “END OF TEST” appear 
and the program ends. 

The method to create a custom graphic symbol will be 
demonstrated in the next section. 


2-162 






EX T r^N r;F.'At--| I‘>EIPT.1[I\-Mni;>lj.y fl;.XT i- CURSOR i- SCROLL 

yXK':i.TiAi..i:{r:: riih: stack porNTFR 

LXI SPyLFFr-H 

ylNiriALIZE ITTE SKI 
?GET MODE (.1 r-OP PORT A 

init; m^;! AvOom 

oor 27M 

• SET l•••GF^T A AG OUTI TJT AND PORT' C A£> INPUT 

MUI AKIPFH 

(.HJT' 2^N ?|-'C)fa‘ A DDR 

MUJ AyilOlt 

OUT 2611 ;i='C)RT ti: DDR 

y in:i;tiali2E the rauR gbzoi's 

MUI A»0 ?SET Fafl! WRITF MODE 

S'TA MODE 

L.X;r I DMAGIEf? ySEND A COMPLETE TRANSMIBGION TO CLflAR OUT' 

MVI Ey 'l LOOOE t ANY OLD CHIP SELECT ♦ 

MOI DrOOOOT. l.:l.0B 
CALL WRITE 

LXI Hy MAST ER ? CONFIGURE CHIPS 0* ;l y 2v AND 3 AS MASTERS 

MMI Dy 0 0(H) 111 OB 

CALI. WRITE 

I..XI 1 1 y MASTER 

MOT Dy 0 0 0 01.1 0;l.B 

CA1,..I. WI«:ITE 

LXI HyMASTEF^ 

MUI DyOOOOlOllB 
CALL WRI t ie; 

LXI I- 1 y MASTER 
MOT Dy 00 00 011 IB 
CAL.L WRITE 

• SET UP F'G.I:NTTE;R and counters to display NATIONAL SEMI SYMBOL 

MUI By 21 FE;: HOLDS # OF COLUMNS TO CHANGE 

RESTRT J MO;r DyO FD FIOLDS THE STARTING CXTLUMN NUMBER FOR IJF’PEER HALE' 

MUI Ey^B FEE HOLDS STARTING COLUMN NUMBER FOR L.OWIER IIALF- 

DSLODF'J MOD CyD 

LXI HyNATSMl FDISPI..AY UPPER HALF OF GRAPFIIC 

CALL GRAPH 

. LXI HyNATSM2 FDISPI..AY LOWER FIALF OF GRAPHIC 
MOD GyE 
CAL.I. GRAPI-I 

LXI HyOl^'l-FFH F PAUSE 

PAU(;>!;;F DCX I-I 

MOD AyH 
GRA I 

JNZ F’AUSE 

INR r.) 

INR D 
INR D 
INR F 
.INI’J E-; 

INFi!' E , 

MDI Ay 30 
CMP n 
JN'Z DSl .001 

l.X'I HyTEEXri SPRINT FIRST TEXT 

MVI AyO FZERO THE CURSOR 

S'l'A CURSOR 
CALL TEXT 

CALL SC:F?0L.L FSCFStOLl. THE TEXT 

LXI HyTEXT2 
MDI AyO 
STA CURSOFC 
CAI...I. TEXT 

LXI HyOFFFFH F PAUSE 

PAUSE! : DCX H 

MDI Ay 2 
PAUSI;E2J DCR A 

',JNZ PAUSE2 
MOD AyH 
ORA L 

JNZ PAUSE 1 


F PRINT SECOND TEXT 
FZEf^O THE CURSOF^ 


f;increment' starting column Nur^BEriS 


F DISPLAY IT UNTIL COLUMN COUNT IS 30 


AN-350 



AN-350 


LXI H?TEXr3 ; PRINT THIRD TEXT 

HVI AyO 
‘o I A CURS(3R 
CALL TEXT 


RST 6 


?END 


TEXT3.J Dt:-! 


MM5820;l 


TEXT2J DP “THIS IS THE END 
texts: DEJ • OF" TF^E TEST 


0 

() 

0 


mastelr: dp 111 IE? 
slave: dp 01 he? 


: ADDRESS FOR MASTER 
: ADDRESS F'OR SLAVE 


NATSMi: DP OFFHy OFF'Hy OFFHy 7FHy SFH, 9FH» OCFHy 67Hr S3Hy OlHy 7FH 
DEJ 3FHy 9FH» OCFHv 67Hy 33H 
DP 99Hf OFFHy OFFHy OOHy OOH 

NATSM2: DE3 OFFHy OFFHy OFFHy 0E6Hy OFSHy 0F9Hy OFCHy OFEHy OFFH 
DP OEOHy 0E6Hy OFSHy 0F9Hy OFCH 
DEJ OFEHy 0F"FHy OFFHy 0F"FHy OFFHy OOHy OOH 
END 


GRAPH 

This subroutine is the center of the software. It is the inter-- 
face between the calling programs and the hardware. All 
I/O is generated by this subroutine. 

There are two entrances to this subroutine: graph and 
read. Graph is the entrance used to display new data. 
Read is the entrance used to read data from the display. 

The HL register should point to the beginning of the data ^ 
to be displayed. The B register should hold the number of 
columns to change. This must be a multiple of three. The C 
register should hold the column number to start with. This 
must also be a multiple of three. These restrictions are to 
simplify the software. 

The first operation is the calculation of the correct chip to 
enable and the column number to start within that chip. 
The first bit of the column address is output with the cor- 
rect chip select going low. The rest of the column address 


is then output with all the chip selects high. If the opera- 
tion is a write, the data is sent to the display bit by bit. If the 
operation is a read, the data is read in bit by bit. 

To create a custom graphic symbol, draw it on a grid as 
shown in Figure 17. Group the upper eight squares as a 
byte with the least significant bit at the top, counting a 
dark square as a one. Group the lower eight squares as a 
byte with the most significant bit at the bottom. Use this 
generated data as input lists to the graph subroutine. A 
good example of this is shown in the listing of main when 
it calls graph. 

Pad the data at the end with zeros as shown to keep the 
number of data values a multiple of three. Remember, 
this is only a software restriction. A different routine 
could be used that would allow any number of columns 
to be displayed. 


7F 3F 9F CF 67 33 01 7F 3F 9F CF 67 33 99 FF FF 00 00 


• ••/ 













-7 






















■; 












-V. 





T: 



























1 













































vT 







■■ 





' / . ; 




[S 





//! 


i 





% 

















Y 










71 

Tv 





TT 






77 







Y 

1 

VV 



i 

1 

t 

Vr' 










i 



% 









■>< 


i 

i 

77 


i 





i 

i 





Y'/ 

7: 




E6 F3 F9 FC FE FF EO E6 F3 F9 FC FE FF FF FF FF 00 00 


Data Upper: 7F, 3F, 9F, CF, 67, 33, 
01,7F,3F, 9F, CF,67, 
33, 99, FF, FF, 00, 00 
Data Lower; E6, F3, F9, FC, FE, FF, 

EO, E6, F3, F9, FC, FE, 

FF, FF, FF, FF, 00, 00 


TL/B/5606-20 


FIGURE 17. Example Graphic Symbol 


2-164 




NOUyn 

puBi.ic GRAPH- i>:e:ad- WRrTi:-;. modi/ 


tGRAI'HIC DISPLAY DRIUEI.; 

? INI-'UE't l-IL. - POINTS) TO <3TAi;;T OP 'DATf'^ 

P D - It OP (3 l::IT COLIJMN‘5 TO CHANCi;; ('MUST UE-I MLil.. f , 01 0 

? C - COLUMN # TO STAU- T WITH CMUST VUl MUI..T . (ll- 0> 

t OUTT'UTJ NO REGIS r EIRE-; DiyTUl-^&lil) 

? DATA |-•OXNT•E[) TO IG E)IGPLAYEr.) UN L..C1.) DT;SE:i.. AY , 

f cai.jjMNB NOT spi:.:ciriED are not i..:t peict ee) . 


l^'l-'AD I 

PoAUE AU... SJTATEG 
PUSH F'SH 
Pi.JS)Ei B 
PUSH [) 

I'USJEI 1-1 

?f'LAG pof;; a i\'e:ai.t operakjn 
MOT A» TO (10 00 0 0 1?. 
S)TA MODE 
JMP graf:mi;i. 


GF^APIH 

?SAUE ALL S)TA1ES 
PUSI-I PSW 
PU£)H i:i 
l•■■U‘3H D 
F'UOH H 


.FT.ACv TOR A WRITE OPERATION 
MO I AjO 

SJTA mode; 


JCAl.CULAFE WHICH 56)20.1. 
GF<AET I:l, : MUI d-()ie;eh 
ACC t MOV A-C 
SOI 2 -^F 
JC GO 
MOV CjA 
MOV AvD 
RLC 

MOV D-A 
,JMP ACC 


TO ACCESJS 
; ‘ST ART WITH COL 

JSUEn'RACT 2/\ FH‘‘OM COI..MMN i.'ni.lNT 

fiT cai-;;ry ;rs si;.t the copi;:l(:t citte- .is.- 
?e-e;t; c gets ne:w ct.iLUhN NLiMi.:b:i.; 


* INE3REME:NT- the cs to next cetip 


‘..)T.:.Li..(.:Tr D 


(30 : 

m.loop; 


MOV E»C 

c:all wr;i;te: 

DCR i;.: 

DCE«: E: 

DCR E:: 

jz e:nd*g 


tE3ET COLUMN NI.JME;!|.LR 

?[)RAW 3 COLUMNS 

iSUEisTRACT 3 PROM COLUMN COUNT 


JIF DONEIi- JUMPv 


MOV 

AxE 

?ADO 3 TO ADDF^ESS 

AITI 

3 ' 


CE‘I 

;P.L0() OE! 

address not max ti-ii.; 

JNZ 

SRJTl 


MOV 

A»D 


RL.C 


; SELECT NEXT 5020:1 CS 

MOV 

D)-A 


Mv:i; 

A»0 


MOV 

E»A 

tSAVE ne:xt addrejss 

JMP 

MJ,.OOP 

;loop until done 

POP 

11 

; restore: all states 


D 


pQp. 

Ei! 


POP 

PSW 


re:t 




write: 

d:i;oplay 

3 COLUMNS OP DATA 

f 

input: 

HE.-- POINTS TO START Of- DATA 

t 


E: -- ADDF^ESS) 

t 


D ■ OUTPUT C6> 

f 

output: 

l-IL.-<-- l-IL - 4 - 3 


fSAVE ALL EdTATESS 
BU3H P6)W 

i“tjsh e;: 

PU£)E) D 

‘START: MVI A» 00()01l;l1 .B ?:i: 6 >OLATE: C£> in REG [) 

ANA D 
M(DV DfA 

MOV AjE ;( 3ET ADDRE65S EiITES AT HIGH END OF- BYTE.- 

RLC 

RI..C: 

MOV ErA 


2 - 



AN-350 


?Ol)TF*U! 
L0G1- : 


five: ai;)E)f-:e:ss ie:it‘5 with chip ‘3i::i.j:cr 

MVI CvS 
MOV A»E 

Ri..c: ; r-otatie; addf«es£> 


MOV E»A 

MVI AflOOOOOOOB 
ANA E 
(3RA D 

CALL DISPLY 
OCR C 
JNZ Wa,OC)P 


?GET MGIE: 

;mef<qe with chip seuecf 

?DEC ADDRESS FJIT COUNlEFi 
?LG0P UNTIL ADOR'ESS IS OUT 


; SIGNAL. FOR A READ OR WFLLTE 
LDA MODE 
GRI 0 000:1 111 Ei: 

CALL. DISPLY 

JP DISO ?JUMP IF THIS IS A WRIFEE 

fF^FEAD ri-IIE; DATA 

MVI &f3 rS EiiYTES OF DATA 

RE ADI? MMl CyS FS BITS PER BYTE 

MVI DfO F CLEAR DAIA BYTEE 

READ2: IN 22F^ FGET A ’BIT OF i:)ATA 

ANI OOOOOOOIB FMASF< OFF UNWANTED BITS 

ORA D F MERGE WITFI DATA E?Y!E 

RRC Fr^OTATE DATA 

MOV DvA , 

MVI A»0 00 011;l:l.B FSET UP 58201 TO READ NEXT Bll 
C:aLI.. DISPLY 

FL.OOP unt:i:l. done witfi byte 


F INCREMENT BYTE POINTIEiR 
FLOOR UNTIL DONIE! WiTFI AL.L BYTEE 


OCR C 
JNZ READ2 
MOV MU'.) 
INX H 
DCR B 
JNZ READl 


F FvEST ORIE 


: STATES 
POF=’ E) 
POP B 


F'OF' PSW 
REt 


FDISP1..AY THE DATA 



DISO ? 

MVI Bf3 

F3 BYTES OF DATA 


DISl? 

MVI Ci-S 

MOV D»M 

Fa BITS PER BYTE 


DIS)2 : 

MOV A)D 

RF<C 

MOV D»A 

ANI lOOOOOOOB 
GFE'I 0000111 IB 

F ROTATE DATA 

FGET NEXT BIT 
FSET CS 



CALL DISPI..Y 

DCFi; c: 

F OUTPUT A BIT OF 

DATA 


JNZ DIS2 

;i;nx h 

DCR B 

FLOOR UNTIL DONE 

WITFI 


JNZ DISl 

FLOOR unt:i:l done: 

WITFI 


Ff^ESTGRE STATES 
F^'OP E) 


POF^ B 
F-GP PSW 
RET 


DISPLY t 

FDISPL.AY ROUTINE 

F input: a •••• DATA ANE) CHIP SELECT 

F BIT 7 -- DATA 

? BITS) 0-3 - CHIP SEL.ECT 

F OUTPUT? NO REGISTERS DISTUR-BET) 

F OUTPUT ONE BIT TO 58201 


FHSH FM3W 


FSAVE STATES 


ANI lOOOllllB 
OUT 2 OH 
□RI OlOOOOOOB 
GUT 20H 
ANI lOllllllB 
OUT 20H 


FMASFC OFF UNWANTED E5ITS> 

FSET UP DATA AND CHIP (SELECI' 
FCL.OCK HIGH 

FCL.OCK LOW 


F'(DP F’SW F.FOEESTOREE STATIEiS) 


66 



TEXT 

This subroutine will take the ASCII text pointed to by HL and 
display it on the LCD starting at the column pointed to by 
the memory location CURSOR. The data should end with a 
zero. CURSOR should be in the range of 0-15 as this is the 
extent of this LCD display. The first operation is the calcula- 
tion of the offset into the ASCII table of the first character. 
Thirty-two is subtracted from the ASCII number because 
the table starts with a space character. This result is then 


multiplied by six because the data to be displayed is six 
bytes long. We now have the offset into the table. The 
character is displayed on the LCD. This operation is 
repeated until all the characters have been displayed. 

A custom font can be generated using the same technique 
as that used to create a custom graphic symbol. 


Naoao 

EiiXIf^N GF<Al=H 

PUBLIC TEXT 9 LETTRf CURSOR 

TEIXTt 

n:>ISPI..AY A CHARACTEF^ STFtlNG ON LCD DISPLAY 
? INf-'Ur: HL -• POINTtS TO BEGINNING OF STRING 

t CURSOR - CURRENT CURSOR POSITION 

f output: cursor cursor + length of STRINt; 

f NO f^egisters disturejed 

JSAUE states 

J CHECK FOR END OF STRING 


; PRINT LETTER 


JLOOP UNTIL DONE 
: RESTORE STATES 


PUSH F^-SW 
PUS>H H 

T.LOOP: hOU A»M 
CPI 0 
JZ TH-IN 
CALL LETTR 
INX H 

JMP T.LOOP 
T.FINJ POP H 

POP PSW 
RET 


LETTR : 

?DISPI..AY AN ASCII CHARACTER ON LCD DISPLAY 
f input: a ~ CFFARACTER TO DISPLAY 

t CURSOR - CURRENT CURSOR LOCATION (0 -• 9S) 

f output: cursor o cursor + i 

? NO REGISTERS DISTUREJED 


FSAUE STATES 

PUSjH PSW 
F'USI-I EJ 
PUSH D 
PUSH H 


fSET UP HL. TO POINT TO CORRECT DATA 


LXI H.. ASCII 
MUI E!»0 
SUI 20H 
MOV C»A 
CALL. MULT 
DAD B 

LDA CURSOI^ 
MOD B/A 
ADD B 
At)D B 
ADD B 
ADD B 
ADD B 
MOM CvA 


;hl points to base address 

;bc: gets ascii offset minus a constant 


; MULTIPLY offset BY 6 (DOUBLE PF^ECISION) 
?HL POINTS TO CORRECT CHARACFER DATA 
? MULTIPLY CURSOR BY 6 TO GET COl.UMN NUMBER 


MMI B»6 
CALL GEi’APH 
LDA CURSOR 
INR A 
CPI :16 
JNZ T.E^ND 
MMI A»0 

T.tlND: STA CUfiSOR 


?E:ACH (CHARACTER IS SIX COLUMNS WIDE 
? DISPLAY THE CHARACTER 
^INCREMENT CURSOR 

F CHECK FOR END OF LCD DISPLAY 

FIF SOr RIEiSET TO ZEEiO 


? RESTORE STATES 
POP hi 
POP D 
POP B 
POP PSW 
RET 


2-167 


AN-350 



AN-350 


MULrt 

jmult;i;ply bc ie:y g:i;x 
? :i.NF-'ui; ii!L' -- Mui..nrL.icAND 

? OUTPUrt BC :■>•= BC * 6 

t NO reoiste:f?s oisrur^BEE) 

PU£)F^ 1='SW 
l"•U!5l-l H 
MOM \U& 

MOM LyC 
DAD B 
DAD B 
DAD B 
DAD B 
DAD B 
MOM ByH 
MOM C y L. 
in-oi::- |..| 

POF' PSW 
IVEET 


c:oFi:soF«j 

ascii: 


DS 1 

DB OyOrOyOrOyO 
DEJ 0 V f 9S » 0 y 0 y 0 
DB 0y7f ()./7r0y0 
DE.=! 2 0 y .1 27 y 2 0 y 1 27 y 2 0 y 0 
DB 36 y ''F2 y ;L 27 y ^2 y :l 8 y 0 
DB 35y:l9yE}y:L00y9£)y0 . 
DIE! S ^ y 73 y 1. 0 2 * 32 y B 0 y U 
DB 0y0y7yby0y0 
DB ()y28y3^y6Jjy0y0 
DB 0y65y3'Fy28y0y0 
i;)B 3^y20y;l.27.20»3^y() 
DB 3y8y62yBy£N0 
DB 0y6'f!y^8y(Jy0yl) 

DE:: 0 y 0 y 8 y 0 y 8 y 0 
i;>B 0y96y96y()y0yn 
DB 32y;l6yey^y2y0 


? SPACE 

fii 

J<|V 

y7. 

; < 

y > 


?/ 


DIE: 62 . 8 1 y 73 y 69 y 62 y 0 #0 

DB 0y66yl27.6'Fy0y0 f J 

DB 1. 22 y 73 y 73 y 73 y 7 0 y 0 5 2 

DB 3'ly6Sy73y73yS^Fy0 y3 

E)B 15yBy8yl26y8y0 
DB 39y69y69y69yS7y0 
DIE: 62 y 73 y 73 y 73 y ^19 y 0 t 6 

DB ;l y97jl7y9y7y0 P7 

DB 5^ y 73 y 73 y 73 y y 0 y 8 

DB 6y9y9y9v:L26y0 y9 


DB Oy'o^yS^yOyOyO yt 

DB 96y5^y5*1.0yny0 yy 

DB 8y20y3^y65y0y0 :< 

DB 20 y 20 y 20 y 20 y 20 y 0 y 

DB 0y6Sy3^y20y8y0 y> 

DE:: 2y.ly88y5y2y 0 y? 

DB 62 y 6S y 93 y B9 y 78 y 0 SO? 


DB ;l2'Fy:iey:l7y1.8yl2'Fy0 SA 
die: 127 y 73 y 73 y 73 y y 0 J IE: 
DB 62y6‘::y65y6Sy3^yO yC 

i:)lE! ■ 1 27 y 6S y 6S y 65 y 62 y 0 y D 

DB 1 27 y 73 y 73 r 65 y 65 *0 y EE 

I:>IE: 127y9y9rd viyO ?E 

DB 62 y 65 y 65 y £) 1 y :l. J/E y 0 y C: 

E>B 127y8y8y0yl27yO yH 

DB 0y65yiri7y65-0y0 yl 

DB 32 y 60 y 60 v 60 y 63 y 0 y J 

DB 1 27 y 8 y 2 0 y 30 y 65 y 0 y E< 

DIE: 1 27 y 60 y 60 « 60 y 60 y 0 y L. 

DB 127y2yl2y2y:l27yO yM 

E)IE: 1 27 r 0 y 8 y 1 6 y 1. 27 y 0 y N 

DB 62 y 65 y 65 y 65 y 62 y 0 y 0 

DB :l.27y9y9y9y6yO yp 

DB 62 y 65 y 8 1 y 33 y 90 m 0 ? t? 

E>r:: 1 27 y 9 y 25 y 0 1 y 7 0 y 0 y 1^ 

DE;: 30 y 69 y 73 y B :l. y 30 y 0 y S 

E)IE: Iylyl27ylyly0 yT 

DB 63y60y60y60y63y0 yU 

die: 3 .L y 32 y 60 y 32 y 3 1 y 0 y M 

DB ;L 27 y 32 y 20 y 32 y 1. 27 y 0 y W 

DIE: 99y20y8r20y99y0 yX 

E)B 3y0yl20y0y3y0 yY 

E>B 97y81y73y69y67yO y Z 



SCROLL 


This subroutine will scroll whatever is displayed on the 
LCD to the right until the screen is clear. It first reads in 
three columns of data. It then writes three columns of data 
with the HL pointer shifted by one byte. This will shift the 
displayed data by one column. This is repeated until the- 

I 


entire LCD has been shifted by one column. Then the en- 
tire operation is repeated until all the displayed data is 
shifted off the screen. 

This subroutine could easily be adapted to scroll the 
display to the left if desired. 


N 808 () 

!-'UBLIC SCROl.L 
EXTRN REAP y GRAPH 


SICROLLJ 

d:i;spi..ay id ti-ie right i)Nr;i;L. cl.ear 
; input: none 

t (DUTf-ur: NO f;:egisti::rs ai-;e: ciiano^ep 

? SJCREEN ;i:D ‘5CRaiJ..ED UNTIL CLEAF^ 


?SAUE ALL SITAIES 
PLIiSH P!5W 
PUS)H IE: 
PUf;H 0 
PUS)H 1-1 


fSET UF^- AL.I.. THE PDINTEERG 
MU I D » 96 

reepeat: mui AvO 

SI A 0UFF8:ER 
hUI B y 3 
MUI CvO 


i..GC)P unt;i;i.. gcreeeen is c:lear <96 t:Yc:L.Es> 
:clie:ar i"if^st e^yte in ejuffeer 


lElEAP 3 CfJLUMNS A1..WAYS 
: START WITH COLUMN ZEF<G 


yREAE) THE DATA 

L- . REE AID : LXI H » E:UFFEF6v 1 

c:al.i.. read 

. LXI HyEitUFFER 
CALL. GRAi-'H 


ySET HL T(D PO;i:NT to EiUFFERU 


ySET HL. TO SHIFT IIIEE DATA 
yREEDRAW THE SHIFTED DATA 


?MGUE LAST CIDL.UMN OF L.AST READ INTO FIRST CIILUMN OF NEXT WRITIE: 
L.[)A &UFI"ER+3 
STA E::UFFTER 


P UPDATE COUNTERS 
MOD AyC 
ADI 3 
MOU (E:yA 
(:i=‘I 96 
JNZ 1... , I'^lEiAP 

i;)l:r' i:;- 

JNZ R-EPEAT 


? INCREMENT COLUMN NUMBEF-: 

? CHECK IF DONE WIIH ONE CYCIJiE 

? DECREMENT l.OOP COUNT 

FLOOR UNTIL. DONE WITH ALL CYCLES 


P I’^ESTOREE STATES 
i-'or" FI 
POl-' D 
F•‘GF•• & 
F•'( 3 |■■ F>SW 
RET 


I5:UF|:-EF<: DS 


AN-350 



AN-350 


OTHER APPLICATIONS 

There are many different types of LCDs that can be con- 
trolled by the MM58201. Some of these are shown in 
Figure 18. 

Up to 24 seven-segment digits can be controlled by one 
MM58201. The software to control a multiplexed seven- 
segment display is not too much different from that of the 
previous application. The software is simpler because 
only one MM58201 is needed instead of four. A logic 
diagram for a six-digit multiplexed seven-segment LCD 
display is shown in Figure 19 and the software to control it 
is in Listing 5. 


Given a string of numbers to display, this subroutine sim- 
ply looks up the data It needs from a look-up table and 
stores this data in a buffer. After every three digits, the 
subroutine sends this data to the MM58201 to be dis- 
played. The digit backplanes are wired backward In 
groups of three to simplify the software. The subroutines 
that this subroutine uses are very similar to the equivalent 
subroutines in the LCD dot matrix application. Since there 
is only one MM58201, the software is simpler. There is no 
need to calculate which MM58201 chip select to enable. 



O O DO O O 
OiU u u u Q u 




± I III 

1 1 u 

1=1 1=1 - 
LI U 

1 1 1 

-1- 

1 1 1 

n~ 

— \ — 

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 

•SI S24 

lllllllllllll 

iiiiiiiiiii 

llllllliillll 

nTTTTTTTTTTTT 

IIIMIIIIII 

IIIIIIIIIII 


SI S24 

^ TL/B/5606 21 


FIGURE 18. Typical LCD Connections to the MM58201 


2-170 







N80U0 

? INITIALIZE THE 810 
M'/I A?0 
GUT 27H 
MUI AjOFFH 
GUT 2/lH 


LXI EiiCfTEST 
MUX Ey6 
CALL. NUMBEI-i 

f;:st 6 


■(EGTJ CMS I»2f3s.^y5.6 


fSUIEiRGUriNE TO DISF’L.AY iMUMERAl.‘5 ON L.C:[) DXSFl.AY 


I 

INF'UT ESC •••• 

E •••• 

POINTS TO BCD DATA STRIN(5 

LENGTH OF DATA STRING <MUL7 II'LE OF 3> 

t 

IDUT PUT 

NO REGISTERS DISTURESED 

: 

... 

DATA STRING IS DISPI..AYi:-"D 

nume.'!Ef: : 

PUSH PSW 
F'USH E? 

JSAVE STATES 


PUSH D 

PU<5H H 


digs: 

MUI D»3 

H..OOP FOR 3 d;i:gits 

LOOF’J 

LDAX E) 

LXI H LI ABLE 
ADD I.. 

MOD L » A 

MDI Ai-OOH 
ADC: H 

MOD FLA 

? CALCULATE ADDREiSS 'IN IT) TABl.E 


MOV A»M 

F'USH PSW 

' JGET OUTPUT DATA FROM TAB1..E 


LXI 

Hi 

-DATA 

MOV 

A! 

.L 

ADD 

D 


MOV 

Li 

^A 

OCR 

1. 


l"•OP 

PSW 

MOV 

Ml 

-A 

INX 

B 


DCR 

E 


DCR 

D 


JNZ 

I..OOP 

I..XI 

Fh 

■ DATA 


CALL. WRITE 


; STORE INTO DATA lEiUFFER 


JXNCREMEENT FMDXNTER TO DATA STRING 
FDECREEMENT =1= OF DIGITS 
JDECREMEENT 3 D'EGIT COUNT 
tIF NOT THIR'D DitGIT THEN l.(3QP EiiACK 


'JDISF1..AY IHESE THREE DliGITE? 


MOD As^E 
ANA A 
JNE-E - DIGS 

|::.Qp i-i 

F'OE-' D 
Ei! 

FDf-' PSW 
RiE;r 

WRITE? 

t DISF'LAY 3 DIGITS 
t INPUT HI. ™ POINTS TO START OF DA I A 

? E • COLUMN ADDRESS 

t (DUTFnjr - NO F!:egisters disturejed 

PUS5H PSW ?SAUE STATES 

F-USI-I Ei! 

F’USH D 
PUSH H 


F CHECK FOR LAST DIGin’ OI" DATA STRING 

; RESTORE STATES 


MOD AfE ?QET ADDRESS PITS AT HIGH END OF- lEsYTE 

RI.C 

RI..C: 

MOD EvA 


'2 



JOLJTfHJT F-ilUE: ADDFiESS IE:IT<3 
MVI C:y5 
WJ..a(3P: MO'.I A,E 

PL.C J ROTATE ADDf^EGO 

MOy EyA 

M'v'.i: Ay 100 0 000 OE: ;GET MSE:: & EENADLE CFTIP SELECT BIT 
ANA E 



CAL.I 

OUT 

y OUTPUT EITT WITH, CHIP S)E:L1“I:T 


DCR 

c: 



,JNZ 

W . LOD|:‘ 

yLOOP UNTIL ADDRESS) IS OUT 

; SIGNAL 

I'OFC 

A WIn’ITE 



hUI 

AyOOFI 



CALL OUT 

; OUTPUT A ZERO t.!lT 

y OUTPUT 

THE 

DATA 



MUI 

B y 3 

y3 BYTES OF" DATA 

DIG.! : 

MUI 

Cyl3 

yS BiTG pe:r bytie; 


MOV 

Dfh 


t>;i:£>2 : 

MOO 

AyD 

y ROTATE DATA 


rf;:c 




MOD 

DyA 



ANI 

10 000 00 OB 

yGET NEXT BIT 


ora 

000 0 0 1)0 IB 

y DISABLE ch;i:p gie:lect 


CALI 

GUT 



DCFi 

C 



,JNZ 

t>i:s 2 

yLOOP UNTIL DONEE WITIl BYTIE! 


INX 

H 



DCR 

E? 



^JNZ 

DI£>J. 

•yLOOP UNTIL. DONEE NTTM 3 BYTEEG 


POF-‘ 

H 

y RESTORE STATEEG 


F^'GP 

D 



F-QP 

B 



F-GF- 

F-'SW 



RET 




GUT ; 

JSUEJPGUTINE TO OUTPUT ONE BIT TO THE MMGE3201 
y :i;NPur a data ejit in msb pogifton 

? (DUI FnJT NO F«EG;r:STERS DXSTURE3ED 

f - OUTPUT ONE BIT TO 5{320;l 

PU£)Fi PSW 
GUT 20H 

ORI OlLOOOOOOB y CLOCK HIGH 
OUT 20H 

ANi ;ioi;i.;iiJ.iB ; CLOCK lon 
OUT 20H 
-POF- PSW 
I^ET 

data: ds 3 

table: db ooiiiiLiiiiy onoooiiOBy oioiioiiiBy aiooi:Li:i.B 

DE3 0J.l()0].10By..0:L10:l:l01By 0;lll3.;l01.Br OOOOOllilB 

DB ():L;l.ll:lllE;!y oiiloilllB 

END 


SUMMARY 

The MM58201 makes it easy to interface a multiplexed 
LCD display to a microprocessor. It is simply a matter of 
connecting the display and the microprocessor to the 
chip, choosing a value for Vjc, then interfacing your pro- 
gram to use the subroutines listed here or similar ones. 


Multiplexed LCDs are the perfect way to cut down on dis- 
play interconnections while still taking advantage of the 
LCD’s low power consumption and high contrast ratio— 
and the MM58201 makes them easy to use. 


AN-350 




AN-353 


MM58167A Real Time Clock 
Design Guide 


The MM58167A is a real-time 24-hour format clock with in- 
out/output structure and control lines that facilitate interfac- 
ing to microprocessors. It provides a reliable source of cal- 
endar data from milliseconds through months, as well as 6 
bytes plus 2 nibbles of RAM, which are available to the user 
if the alarm (compare) interrupt is not used. The MM58167A 
features low power consumption (typically 4.5 microam- 
peres at 3-volt supply) during battery backed mode, flexible 
interrupt structure (alarm and repetitive), and a fast Internal 
update rate (1 kHz). Systems utilizing this device include, 
personal computers, process control, security, and data ac- 
quisition. 

This application note covers hardware interface to micro- 
processors, clock interrupts, oscillator operation, accuracy, 
calibration techniques, software, and battery back-up con- 
siderations. 



National Semiconductor 
Application Note 353 
Milt Schwartz 
May 1984 


Hardware Description Overview 

1.0 Figure / is a functional block diagram of the MM58167A. 
It can be subdivided into the following sections; 

1.1 Oscillator 

The oscillator consists of an internal inverter to which 
the user connects a 32.768 kHz crystal, bias resistor 
and capacitors, to form a Pierce parallel resonant circuit. 

1.2 Prescaler 

The prescaler divides the 32.768 kHz oscillator down to 
1 kHz using pulse swallowing techniques. The 1 kHz 
pulse rate is the Incrementing signal for the timekeeping 
counters. 


Block Diagram 



opgi , .SE . 4 

DRAIN _ 


IHTEBBU PT 
il4. ffDTPtJT 
(OPEN DRAIN 
OPER ATION DURING 
PWR inPR CONDITION) 





«-!-*■ 

ADDRESS 


DECODER 

\ 


A4 — ■ » 


TL/B/5727-1 

FIGURE 1 


2-174 










Hardware Description Overview (Continued) 

1.3 Timekeeping Counters 

The timekeeping section consists of a 14-stage BCD 
counter, each stage having read/write capability. The 
counters keep time in a 24-hour format. Figure 8 shows 
the counter detail of calendar-date-time format. 

1.4 Rollover Status 

A rollover status bit (read only) informs the user that 
invalid data may have been read, due to the counters 
being incremented during a counter read or between 
successive counter reads. This situation occurs be- 
cause the counters are clocked asynchronously with re- 
spect to the microprocessor. 

1.5 RAM 

14 nibbles of RAM are provided for alarm (compare) 
interrupt or general storage. The nibbles are packed 2 
per address except for 2 locations, address 08 and OD 
(HEX). The nibble at address 08 appears in the high 
order 4 bits, while the nibble at address OD appears in 
the low order 4 bits. See memory map Figure 2 for de- 
tails. 


Address 

In HEX 

D7 D6 D5 D4 

D3 D2 D1 DO 

8 

Milliseconds 

No RAM 

Exists 

9 

Tenths of Seconds 

Hundredths 

of Seconds 

A 

Tens of Seconds 

Units of Seconds 

B 

Tens of Minutes 

Units of Minutes 

C 

Tens of Hours 

Units of Hours 

D 

No RAM 

Exists 

Day of Week 

E 

Tens 

Day of Month 

Units 

Day of Month 

F 

Tens of 

Months 

Units of 

Months 


FIGURE 2. RAM Memory Map 


1.6 Comparator 

A 46-bit comparator compares values in RAM against 
the counters to provide an alarm (compare) interrupt. 
When a compare occurs, the main interrupt will be acti- 
vated if the DO bit of the interrupt control register was 
set. The standby interrupt will be activated if a “1”was 
written to address 1 6 hex. 

1.7 Interrupt Hardware 

Interrupt hardware consists of two interrupt outputs. The 
main interrupt and the standby interrupt. The main inter- 
rupt is an active high push-pull output. The standby in- 
terrupt is an active low open drain output. For the main 
interrupt, an 8-bit control register allows the user to se- 
lect from 1 to 7 interrupt rates, as well as an alarm. An 
8-bit status register informs the user which of the 8 inter- 
rupts occurred. A one-bit control register enables/dis- 
ables the standby interrupt. The standby interrupt is acti- 
vated only for the alarm condition. A 46-bit comparator 
matches the timekeeping counters against RAM for the 
alarm interrupt. 


1.8 Input/Output and Control Lines 

The input/output structure consists of a 5-bit address 
bus and 8-bit bidirectional data bus. The control lines 
are chip select, power down, read and write. In addition, 
a ready output is provided for those microprocessors 
that have wait-state capability and meet the timing re- 
quirements of the ready signal. The power down input 
acts as a chip select of opposite polarity. It differs from 
the chip select in that it TRI-STATES the main interrupt 
output while the chip select does not TRI-STATE the 
interrupt. The power down input is intended to facilitate 
deselecting the chip for battery backed operation. Chip 
select, read and write are active low controls. The ready 
output is active low open drain and is caused by chip 
select and the negative-going-edge of read or write (it is 
an internal one-shot). If the ready output is not used as a 
control line when interfacing to a microprocessor, it may 
be left open circuit. 

Detail Descriptions 

OSCILLATOR 

Figure 3 represents the internal and external circuitry that 
comprise the oscillator. The inverter, which is the heart of 
the oscillator, is designed to consume minimum power. The 
inverter has a typical gain of 30 at 1 kHz and 4 at 30 kHz. 
The oscillator input may be driven from an external source. 
If this is desired, the input should swing rail-to-rail and be 
approximately a 50% duty cycle. The oscillator output pin is 
open circuit for this case. The external oscillator circuit may 
be constructed using a CMOS inverter, N-FET, or a transis- 
tor (see Figure 4). Referring to Figure 3, the external 20 MH 
resistor biases the inverter in its active region. The internal 
feedback resistor may be too large in value to guarantee 
reliable biasing. 

The external series resistor is to protect the crystal from 
being overdriven and possibly damaged. Manufacturers of 
these crystals specify maximum power that the crystal can 
dissipate. It is this rating which determines what value of 
series resistor should be used. The two external capacitors 
are effectively in series with each other (from an A.C. view- 
point). This total value comprises the load capacitance (typi- 
cally 9 to 13 picofarad) specified by the crystal manufacturer 
at the crystal’s oscillating frequency. The rule of thumb in 
choosing these capacitors is: 

1 /load capacitance = 1 /Cl + 1 /C2 
C2 is greater than Cl (typically two to four times) 
Cl is usually trimmed to obtain the 32768 Hertz fre- 
quency. 

The start-up time of this oscillator may vary from two to 
seven seconds (empirical observation) and is due to the 
high “Q” of the crystal. Typical waveform values monitored 
at the oscillator output are observed to be 3 volts peak to 
peak riding on a 2.5 volt D.C. level (for V + = 5 volts). 

CHOOSING THE CRYSTAL 

The below parameters describe the crystal to be used 
Parallel Resonant, tuning fork (N cut) or XY Bar 
Q>= 35,000 

Load Capacitance (CL) 9 to 1 3 Picofarad 

Power Rating 20 Microwatt Max. 

Accuracy User Choice 

Temperature Coefficient User Choice 



2-175 


AN-353 



Q1 -32,768 H7 
Mnfg. Tel.# 

RCD 800-228-8108 

Saronix 415-856-6900 

Reeves-Hoffman 717-243-5929 



Cl = 5 -► 30 pf 

Circuit Specialists 
Part# 275-0430-005 
Tel.# 1-800-528-1417 
Johanson #9613 or #9410-3 pc. 
Tel.# 201-334-2676 
C2 = 1 5 — > 20 pf mica 


TL/B/5727-2 

FIGURE 3. Oscillator Circuit and Recommended Connections 


/ 



TL/B/5727-3 


20M 200k 



TL/B/5727-5 


FIGURE 4. Examples of External OSC Circuits 


^6 



Detail Descriptions (Continued) 

When used with a crystal, the accuracy of the oscillator cir- 
cuit over voltage and temperature is about +/- 10 PPM. 
Voltage variations cause about 50% of the inaccuracy and 
temperature variations account for the other half. This inac- 
curacy results in an error of about 5 minutes per year. Errors 
due to external components must be taken into account by 
the user. If an external oscillator is used, then it determines 
the accuracy of the clock. The oscillator input pin (pin 10), is 
a high impedance node that is susceptible to ‘noise’. The 
usual result is the clock gains time at a high rate (on the 
order of seconds per hour or greater). This noise is usually 
the result of coupling from pin 9 which is a low order ad- 
dress bit if tied directly to a microprocessor bus. Sugges- 
tions to alleviate this condition are: 

1 . Gate pin 9 with chip select. 

2. Use a slow rise and fall time non inverting buffer 
such as a CMOS to drive pin 9. If this choice is 
made, similar CMOS should drive the write and 
read strobes to avoid timing conflicts. 

3. Use an external oscillator and drive pin 10 with a 
low impedance device (CMOS or transistor), leave 
pin 1 1 open circuit. 

4. Connect all oscillator components as close as 
possible to pins 1 0 and 1 1 . 

CALIBRATION 

To calibrate the oscillator three methods are suggested. 
The one second repetitive interrupt is activated. This is 
done by first connecting the interrupt (pin 13) of the clock to 
the interrupt of the microprocessor. Next a short program is 
written that sets bit D2 of the interrupt control register, and 
then enters a loop that wastes time while awaiting an inter- 
rupt. The interrupt service routine only needs to read the 
interrupt status register, which clears the interrupt, and then 
returns. The result is a 1 second periodic signal at pin 13. 
The flow chart of Figure 5 is an example of the detail steps. 
A time event meter is used to measure the time interval 
between successive positive going edges of the interrupt 
output while adjusting the variable capacitor Cl. This period 
will be 1 second when the oscillator is at 32,768 Hertz. The 


second method is to monitor the most significant bit (07) of 
counter 1 , while statically reading. A static read is performed 
by connecting chip select and read low, and applying the 
address of the selected counter. Refer to Figure 6 for detail. 
The period of this output is one second if the oscillator is 
exact at 32,768 Hertz. The adjustment procedure is the 
same as for the first method. 

A third method is to monitor DO of the seconds counter 
(addr 2) while statically reading. The DO output presents a 



FIGURE 5. Flow Chart for Calibration 
Using the 1 Hz Repetitive Interrupt 



FIGURE 6. Hardware to Achieve a Static Read of Address 1 



2-177 


AN-353 




AN-353 


Detail Descriptions (Continued) 

square wave that is one second high, one second low when 
the oscillator is at 32,768 Hertz. Refer to Figure 7 for static 
read hardware. If the 32,768 Hertz is to be measured direct- 
ly, then a HI impedance LO capacitance amplifier or com- 
parator or CMOS gate should be connected to the oscillator 
output pin to prevent the measuring instrument from offset- 
ting the frequency of the oscillator. This addition is perma- 
nently a part of the oscillator circuit and must be battery 
backed if the clock is battery backed. The reason for battery 
backing this buffer is to ensure that its input impedance 
does not change during the power down operation which^ 
could result in the oscillator stopping or being offset in 
frequency. 

PRESCALER OPERATION 

The 32,768 Hertz signal is divided to an even 32,000 Hertz 
using pulse swallowing techniques. This is accomplished by 
dropping three pulses every 1 28 counts of the 32,768 Hertz 
signal. The resulting 32 kHz is then divided to produce 1 
kHz which is the internal incrementer for the rest of the 
timekeeper. This 1 kHz waveform is nonmonotonic with re- 
spect to individual periods. As a result, there are 750 short 
and 250 long periods within a one second interval. 

The short period is 1/1024 seconds, and the long period Is 
[1/1024 + 3/32768] seconds. As a result, the milliseconds, 
hundredths and tenths of seconds “jitter”. The Inaccuracy 
on an individual period basis is about 91 microseconds. The 
period and number of clock edges are correct over one sec- 
ond within the accuracy of the crystal oscillator. The ten 
thousandths of seconds counter referred to In the data 


sheet counts milliseconds. The 1 second and slower signals 
are jitter free. Refer to Figure 8 for counter block diagram. 

TIMEKEEPING COUNTERS 

The timekeeping counters are Intended to work with valid 
BCD values. In general, if illegal codes are entered then no 
guarantee Is given for recovery. As shown in Figure 6, the 
timekeeping stages are arranged as a ripple counter. The 
month, day of month, and day of week counters count 1 
through N. The milliseconds through hours counters count 0 
through N. The rollover of a counter stage increments the 
next higher order counter. This rollover takes place when 
the highest allowed value plus one is decoded. For exam- 
ple, in a 30-day month, the day of month counter would 
decode the value 31 , reset to one and increment the month 
counter. If the highest allowed value plus one is written to a 
counter, the counter will reset when the write is removed 
and “may” Increment the next higher order counter. 

For example, if February 29 is written to the clock, the read 
back will be a “1” in the day of month counter and the 
month may read “3”. However, for leap year use, February 
31 may be written. If this is done on Mar 1 at 0 (hours 
through milliseconds), then the clock will read March 1 after 
24 hours. In this way, the value Feb 31 could be used as an 
indication that the date is really Feb 29. Refer to Figures 9A 
9B, and 9C for flowcharts of a program and alarm interrupt 
bit map that take leap year into account. Note that the soft- 
ware implemented leap year counter is accurate at least 
through the year 2048. For a perpetual calendar, a more 
sophisticated algorithm would be needed. 



TL/B/5727-8 

FIGURE 7. Static Read Hardware Where Up Has External Wait State Capability 


2-178 







AN-353 



Note: Initialize a 4 state counter at first power on. 
Use the two least significant bits of day of 
week RAM as the four state software 
counter. Use the two least significant bits 
of millisecond RAM for FLAG 1 and 
FLAG 2. 

Leap year is now relative to March 1 st. This pro- 
gram requires that the system be powered and 
clock read once during February and once during 
March. Clock is battery backed. 




INTERPRET AS 
FEB 29 

I ^ 





FINISH CLOCK 
READ 


( RETURN TO ^ 
MAIN PROGRAM J 


TL/B/5727-10 


FIGURE 9A. Leap Year Flow Chart 


2-180 












TL/B/5727-11 

FIGURE 9B. Leap Year Flow Chart and Hardware 





Address 



DATA 

Function 





Hi Nibble 

Lo Nibble 


4 

3 

2 

1 

0 

7 

6 

5 

4 

3 

2 

1 

0 

Milliseconds 

0 

1 

1 0 

0 

0 

0 

0 

0 

0 

No RAM Exists 

Hundredths and 
Tenths of Seconds 

0 

1 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

Seconds 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

Minutes 

0 

1 

0 

1 

1 

0 

0 

0 

0 

0 

0 

0 

0 

Hours 

0 

1 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

Day of Week 

, 0 

1 

1 

0 

1 

No RAM Exists | 

1 

1 

X 

X 

Day of Month 

0 

1 

1 

1 

0 

0 

' 0 

0 

0 

0 

0 

0 

1 

Months 

0 

1 

1 

1 

1 

0 

0 

0 

0 

0 

0 

1 

1 


FIGURE 9C. Clock RAM Bit Map For Alarm Interrupt on March 1 @ 0 Hrs 


2-181 


AN-353 








AN-353 


INTERRUPTS 

The 58167 has two interrupt output pins. The main interrupt 
(pin 13) is active “high”, and is active when the power down 
pin is “high”. When power down (pin 23) is low, the main 
interrupt output Is TRI-ST ATED. The second interrupt is the 
“standby interrupt” and is an active low open drain requiring 
a pull up resistor to VDD. This interrupt is always powered. 
Refer to Figure 10 for typical sink current versus voltage out 
characteristics. Separate control bits exist for the two inter- 
rupts. The main interrupt offers two modes ^f operation 
which may be combined. Mode 1 Is the Interactive repetitive 
interrupt. For this case, a logic 1 is written to one or more 
bits In the control register (address 1 1 hex) from D1 through 
D7, a logic 0 is written into the DO position. Refer to Figure 
1 1 for bit configuration of the interrupt control and status 
registers. 



VOUT (V) 


TL/B/5727-12 

FIGURE 10. Typical Curve of I vs V of Standby Interrupt 


As a result, the clock chip provides an interactive repetitive 
interrupt, that occurs when the selected counter rolls over. 
That is, the user must clear the interrupt so the next one can 
be recognized. This is done by reading the interrupt status 
register (address 1 0 hex). This read results in the user ob- 
taining the interrupt status (which interrupt occurred) and 


the clearing of the interrupt output as well as the status 
register. It is the positive-goIng-edge of the read strobe 
which causes the preceding. This clearing action precludes 
polling the status register. For precision timing, the positive- 
going-edge of the repetitive interrupt should be used as a 
trigger. The one-per-second through one-per-month repeti- 
tive Interrupts will be as accurate as the setting of the crys- 
tal oscillator. The ten-per-second interrupt will be accurate 
to about 91 microseconds. Refer to prescaler description for 
more detail. 

The second mode of main interrupt is the “compare” or 
“alarm”. In this case, a specific value is entered in the RAM 
of the clock. When the time keeping counter(s) match that 
value, the interrupt becomes active. Refer to Figure 13 for a 
typical example. Figures 1 1 and 12 show Internal interrupt 
logic and waveforms. In addition to a specific one time inter- 
rupt (alarm), a repetitive interrupt can be achieved by repro- 
gramming the selected RAM location with a future event 
value. The rule of thumb for an “alarm” interrupt Is: All nib- 
bles of higher order than specified are set to C hex (always 
compare). All nibbles lower than specified are set to “zero”. 
A programming example of the fastest interrupt rate obtain- 
able (500 per second) is given in Figure 14. This program 
written in NSC800 code (Z80) sets “always compare” con- 
ditions (CC hex) In RAM locations 9 through C, E and F. 
RAM location D which corresponds to the day of the week 
counter (a single digit), is set to C. RAM location 8 is set to 
0. When the first interrupt occurs, the service routine reads 
the status register and sets the value 2 into RAM location 8. 
At succeeding interrupts, the values 4, 6, 8 are set into loca- 
tion 8 and the sequence repeats. 

If an interrupt is activated and the Interrupt occurs during 
battery backed operation (power down), the main Interrupt 
output will be active high when system power returns. 



TL/B/5727-13 

FIGURE 1 1. Interrupt Registers and Logic 


2-182 




COMPARE 


COMPARE 

INTERRUPT (PIN 13) 
OUTPUT ■ — i.i 
(PIN 14) 

STANOBY 

INTERRUPT 

OUTPUT 


REPETITIVE 

INTERRUPT 

OUTPUT 


CAUSED BY 
READING INTERRUPT 
STATUS REGISTER 


CAUSED BY 
-READING INTERRUPT 
STATUS REGISTER 


CAUSED BY 
-WRITING AO 
TO ADDRESS 16 HEX 



FIGURE 12. Internal Interrupt Timing 





Milliseconds 


Hundredths and 
Tenths of Seconds 


Seconds 


Minutes 


Hours 


Day of Week 


Day of Month 


Hi Nibble 


5 


Lo Nibble 


1 


No RAM Exists 


Months 

0 1 

I 1 

1 

1 

1 

1 




2-183 


























AN-353 


4092 

4091 

4090 

408F 

408E 

408D 

408C 

408B 

408A 

4089 

4088 

lOlC 

lOlD 


0800' 
0802' 
0805' 
0807' 
080A' 
080C' 
080E' 
0811' 
0813' 
0816' 
0818' 
08 IB’ 
' 081E' 
0820' 
0823' 
0826' 
0829 ' 
082C' 
082F' 
0832' 
0835' 
0837* 
083A' 
083C' 
083E' 
0840' 
0841' 


0900' 
0903' 
0905' 
0907' 
09 OA' 
090C' 
090F' 
0912' 
0914’ 
0917' 
09 lA' 
091B’ 


NAME ('1500Hz') 

TITLE 58167 500HZ REPETITIVE INTERRUPT (10/13/83) 

;THIS PROGRAM IS FOR USE WITH THE 58167 POWER DOWN BOARD 
; INTERFACED TO THE NSC888 BOARD. CODE IS NSC800. 

;A 500HZ SIGNAL IS GENERATED AT THE INTERRUPT PIN (13). 
;THIS SIGNAL IS GENERATED USING THE COMPARE INTERRUPT 
;AND UPDATING THE "RAM” FOR THE NEXT INTERRUPT 


ORG 0800H 

RESET EQU 04092H 
CONT EQU 0409 IH 
STAT EQU 04090H 
MON EQU 0408FH 
DOM EQU 0408EH 
DOW EQU 0408DH 
HRS EQU 0408CH 
MIN EQU 0408BH 
SEC EQU 0408AH 
HT EQU 04089H 
MIL EQU 04088H 
VECl EQU OlOlCH 
VEC2 EQU OIOIDH 


3E 

00 

INIT; LD 

A.O 

;SET UP INTRPT FOR NSC888 

32 

lOlC 

LD 

(VECl) ,A 

. * 

3E 

09 

LD 

A,009H 

; * 

32 

lOlD 

LD 

(VEC2) ,A 

' ; * 

3E 

08 

LD 

A, 8 

. ♦ 

D3 

BB 

OUT 

(OBBH) .A 


31 

IFFF 

LD 

SP.OIFFFH 

;INIT STACK POINTER 

3E 

FF 

LD 

A.OFFH 


32 

4092 

LD 

(Reset) ,A 

;RESET ALL CLOCK COUNTERS 

3E 

00 

LD 

A.O 


32 

4091 

LD 

(CONT) ,A 

;CLEAR INTRPT CONTROL 

3A 

4090 

LD 

A, (STAT) 

;CLEAR ANY PENDING INTRPT 

3E 

CC ' 

LD 

A.OCCH 

;SET RAM FOR INTRPT 

32 

408F 

LD 

(MON) ,A 


32 

408E 

LD 

(DOM) ,A 


32 

408D 

LD 

(DOW) ,A 


32 

408C 

LD 

(HRS) .A 


32 

408B 

LD 

(MIN) ,A 


32 

408A 

LD 

(SEC) ,A 


32 

4089 

LD 

' (HT) ,A 


3E 

00 

LD 

A.O 


32 

4088 

LD 

(MIL) .A 


3E 

01 

LD 

A,1 


32 

4091 

LD 

(CONT) . A 

;SET COMPARE INTRPT 

FB 

> 

El 



00 


NOP ; NOP 



C3 

0840 

JP 

NOP 

;WASTE TIME AWAITING 





;INTERRUPI 



.•INTERRUPT SERVICE ROUTINE 

GETS THE VALUE IN THE 



•.MILLISECOND 

RAM. TEST FOR 

8. IF YES THEN SET RAM 



;EQUAL TO 0, 

CLEAR INTERRUPT AND RETURN. 



;IF NO, ADD 

2 TO RAM MILLISECOND, 


;CLEAR INTERRUPT AND RETURN. 

; "REMEMBER" RAM MILLISECONDS IS "HIGH", ORDER NIBBLE 
;ONLY 





ORG 0900H 


3A 4088 


LD 

A. (MIL) 

;GET RAM MILLSEC 

E6 FO 


AND 

OFOH 

;MASK 

FE 80 


CP ' 

080H 

;? RAM = 8 

CA 0912' 


JP 

Z.ZERO 


C6 20 


ADD- 

A.020H 


32 4088 


LD 

(MIL) ,A 


C3 0917’ 


JP 

RETRN 


3E 00 

ZERO ; 

LD 

A.O 


32 4088 


LD 

(MIL) ,A 


3A 4090 

RETRN ; 

LD 

A, (STAT) 

•.CLEAR INTRPT 

FB 


El 



C9 


RET 




END 

FIGURE 14. NSC800 Assembly Code for 500 Hz Interrupt 


2^184 




STANDBY INTERRUPT 

A “1” written to address 16 hex enables the standby inter- 
rupt and a “0” disables it. This interrupt also becomes ac- 
tive when a match exists between time keeping counter(s) 
and a value written into RAM. The standby interrupt can be 
cleared as soon as it is recognized. The user should ensure 
that a delay of one millisecond or greater exists prior to 
reenabling the standby interrupt. This delay is necessary 
because of the internal signal level which causes the inter- 
rupt. If this delay does not occur, then the standby interrupt 
becomes reactivated until the internal latched compare 
goes away, which occurs at the next 1 kHz clock. Figure 12 
illustrates interrupt timing. 

RAM 

RAM is organized as shown in Figure 2. There are 4 bits of 
RAM for each BCD counter. The RAM may be used as gen- 
eral purpose or for an alarm interrupt. It is possible under 
certain conditions to perform the compare interrupt and use 
selected bits of the RAM for general purpose storage. Any 
RAM position that is set for the ‘always compare’ condition 
allows the user to manipulate the 2 LO order bits in each 
nibble. However, the 2 high order bits in each nibble position 
must be maintained as logic 1 ’S. For example, the user may 
have an alarm interrupt that does not use the day of the 
week as a condition for interrupt. Therefore the 2 low order 
bits might be used as a 4 state software counter to keep 
track of leap year. Reading and writing the RAM is the same 
as any standard RAM. 

HARDWARE INTERFACE CONSIDERATIONS 

There are four basic methods of interfacing the 58167A to a 
microprocessor. They are memory mapped, microproces- 


sor ports (for single chip microprocessors like the 8048), 
peripheral adapter, and separate latches. The advantage of 
memory mapped interface is use of all memory reference 
instructions. The disadvantages are the processor may 
need to be “wait-stated” and the environment is noisier with 
respect to the crystal oscillator. Refer to Figure 15 for typi- 
cal bus interface. 

Microprocessors that have separate ports (16 are sufficient) 
offer the capability to interface directly without “wait-stat- 
ing”, or additional device count. Eight of the port bits (data) 
need to be bidirectional for this interface. Figure 16 indi- 
cates port interface. Programmable peripheral interface de- 
vices such as the 8255A or NSC810 afford the user the 
advantage of timing control by data bit manipulation, as well 
as a less noisy environment with respect to the oscillator 
circuit. Figure 17 depicts the 8255 A and NSC810 interface. 
External latches may be used in place of the programmable 
peripheral interface device. This results in higher package 
count but easier troubleshooting. Also, the latches do not 
have to be manipulated through a control register. Figure 18 
illustrates the external latch approach. For the peripheral 
approaches, address, data, chip select, read and write 
strobes are manipulated by controlling the data bus bits via 
program execution. The peripheral interface approach facili- 
tates calibration of the oscillator because the chip select, 
read strobe, and address lines can be set to steady state 
logic levels. Refer to calibration techniques for more detail. 




^ READY 






(Z80 


WAIT 


0 




NSC8Q0) 




° SHOT ^ 




(i? SYSTEM 
BUS (NQN-MUXED) 









ADDRESS 


ADDRESS 



CS 

MM58167A 

FOR NSC800, 
Z80 , 8085, 


“T 


DECODE 



OR ANY 
PROCESSOR 


L 




JL 

AODR 

WITH WAIT 
STATE CAPABILITY 


r 

^ DATA ^ 

4-0 

DATA 



Va 1 

7-0 










TL/B/5727-15 


FIGURE 15. Typical juP Bus Interface 


Q 



2-185 


AN-353 





cs 




WR 


A4 


A3 

MM58167A 

A2 


A1 


AO 


D7-00 1 


TL/B/5727-16 

FIGURE 16. MM58167A Interfaced to Single Chip Microcomputer 



FIGURE 17. MM58167A Interfaced to juP Through Peripheral Adapter 



FIGURE 18. MM58167A Interfaced to ap Using TRI-STATE Latches 


86 




POWER DOWN/BATTERY BACKED CONSIDERATIONS 

Battery back up of the clock may be considered by the user 
to maintain time during power failure, provide a “wake-up” 
alarm, save the time that power failure occurred, calculate 
how long power failure lasted. The first step in providing a 
battery backed system is to isolate the system supply from 
the battery. This is to ensure that the battery is not dis- 
charged by the system supply when power failure occurs. 
Figure 19 shows two techniques to achieve isolation. Figure 
19A is implemented using diodes to isolate. In one case a 
Schottky diode is used to guarantee minimum voltage drop 
loss, while in the other case an adjustable voltage regulator 
(LM317) is used from a higher voltage and regulated to 
about 5.7 volts. A 1N914 diode in series with the regulator 
achieves the 5 volts for the clock. The Schottky diode has a 
drop of about 0.3 volts. Thus the V + of the clock is typically 
at 4.7 volts. The user must be cautious about input signals 
not exceeding the 4.7 volt V+, since the clock is a CMOS 
device. This situation could arise if the devices driving the 
inputs of the clock were CMOS and received power from 
the 5 volt system supply. Figure 19B makes use of the low 


saturation of a PNP transistor (0.1 volt) to take care of the 
above situation. The NPN transistor is used to achieve isola- 
tion. The zener diode ensures that the circuit stops conduct-- 
ing and appears open circuit before the battery switches in. 
Some basic considerations must be adhered to in a power 
down situation where the real time clock is battey backed. 
One is to ensure no spurious write strobes accompanied by 
a chip select occur during power down or power up. Another 
is to guarantee the system is stable when selecting/dese- 
lecting the clock. Also, any legitimate write-in-progress 
should be completed. To accomplish this, hardware is im- 
plemented such that early power failure is detected (usually 
a comparator detects DC failure, a retriggerable one-shot 
detects AC failure) See Figures 20 and 21. At this point the 
clock chip is deselected. The worst case is the power fails 
faster than the detection circuit can cause deselection. 
When power returns, the hardware detects power on, but 
the system must be stable before communication is allowed 
with the real-time-clock. 


SCHOnKY 

1N6263 




TL/B/5727-19 



FIGURE 19. Isolating System Supply from Battery 



5V 

SYSTEM 


f— © 


TL/B/5727-21 


FIGURE 20. Sensing D.C. Failure Using a Comparator 



2-187 


AN-353 



AN-353 



FIGURE 21. Sensing AC Line Failure Using Retriggerable One Shot 


The 5-volt system supply rise and fall time characteristics 
during power turn on and power failure must be known. 
Care should be taken to allow a legitimate write in progress 
to be completed. This is necessary because a “short write” 
could cause erroneous data to be entered to the clock. If 
the clock is used as a “read only” device (except for initiali- 
zation of calendar and time), the Circuitry to allow a write in 
progress to be completed does not have to be considered. 
For this situation, a switch in series with the write strobe 
could be Implemented such that the write line to the clock is 
“tied high” after initialization. 

To sense system DC power failure a comparator and volt- 
age reference may be used. Figure 22, detail 1 , shows the 
comparator and voltage reference configured such that the 
comparator output is “low” when 5-volt system power is 
greater than 4.6 volts. If possible, the power fail trip point 
should be referenced to a lightly loaded (fast collapse) DC 
supply, preferably higher than the 5-volt system. This would 
allow early sense of power failure. When using comparators, 
the output may oscillate as the trip point is approached. The 
oscillation is caused by noise on the DC line appearing at 
the input to the comparator when at or near the trip voltage. 
The cleaner the supply, the less chance of oscillation. In all 
cases, hysteresis should be used to minimize oscillations. 
Note that the 20 kohm pull-up resistor is connected to the 
battery backed node, while the LM139 V+ pin is connected 
to the 5-volt system supply. Used this way, the comparator 
does not draw any current except leakage from the battery 
and the output remains high during power down. 

To sense AC failure, a retriggerable one-shot may be used. 
The RC time out may be adjusted to allow for one or more 
cycles of 60 Hertz to be missed. Using this approach, the Q’ 
output of the one-shot is always high while 60 Hertz is pres- 
ent. When a cycle is missed the pne-shot times out and Q 


goes low. Figure 21 shows AC sensing. This technique 
could cause a spurious deselect of the clock if a “glitch” 
occurs on the AC line resulting in a missed cycle. 

For this application, the circuit shown in Figure 22 was im- 
plemented. The MM58167A was interfaced to the NSC800 
in memory mapped locations. A demo program was written 
to exercise the clock, and display time, date and calendar. 
Power was switched on and off at irregular intervals, to test 
the battery backed circuitry. The results were that the clock 
kept correct time. Battery backed current for all circuitry was 
10 microamp. For general consideration, this circuitry allows 
a chip select in progress to be completed. 

FUNCTIONAL OPERATION OF FIGURE 22 

Power up sequencing consists of the LM139 (comparator) 
making a high to low transition when the 5-volt system sup- 
ply exceeds 4.6 volts. This transition triggers the 0.5 second 
one-shot causing its output to be low and removes the low 
reset on the D flip-flop through nand gate J. The output of 
the 2 microsecond one-shot is “don’t care” once the com- 
parator switches from high to low. After 0.5 seconds, the 
system is assumed to be stable, and the D flip-flop output 
which was reset is clocked high by the low to high transition 
of the 0.5 second one-shot. Thus, the clock chip is enabled 
allowing normal communication with the microprocessor. 
The power down sequence consists of the comparator mak- 
ing a low to high transition when the 5-volt supply is less 
than 4.6 volts. If no chip select is present, the D flip-flop is 
reset through nand gate J, causing pin 23 of the clock to be 
low (deselected). If a legitimate chip select was in progress, 
the reset action through nand gate J would be delayed by 
the low level of the 2-microsecond one-shot. 


2-188 




TL/B/5727-23 


FIGURE 22. Detailed Schematic of Power Down Circuitry, and Interface to NSC888 Board 


ege-NV 




AN-353 


A wait State generator was implemented using the chip se- 
lect as the sensing signal. This was necessary to comply 
with NSC800 wait state timing. The wait generator provides 
2 microseconds of access time, which is more than ade- 
quate to meet clock chip timing requirements. Pull-down re- 
sistors were added to all clock input pins to guarantee <no 
floating inputs during power down. This ensures that the 
CMOS clock does not draw excessive current from the bat- 
tery during power down. A diode isolates 5-volt system from 
the battery (A 3.4-volt Tadiran nonrechargeable lithium cell 
was used in this application). The battery is isolated from 
the 5-volt supply using a circuit comprised of PNP and NPN 
transistors along with a zener diode. The zener diode value 
was selected such that the combined voltage drop of the 
zener and the base emitter of the NPN transistor was great- 
er than the battery voltage. This ensures no current will be 
drawn from the battery by the 5-volt supply when power 
failure occurs. 

The battery is non rechargeable, but allows up to 10 mi- 
croamps of charge current without damaging the cell. An 
LM139 voltage comparator and LM385-2.5 voltage refer- 
ence were used to sense the 5-volt system supply. The trip 
point was adjusted such that when the 5-voit supply 
dropped to 4.6 volts, the comparator switched from low to 
high. Observation of the comparator output showed oscilla- 
tion, but caused no malfunction. The duration of the oscilla- 
tion was about 1 00 microseconds. Burst noise on.the 5-volt 
supply was about 0.5 volts peak to peak. For the circuitry 
implemented, the 5-volt supply should fall no faster than 1 
volt per millisecond. This rate allows 100 microseconds for 
deselect to take place while the supply is falling from 4.6 
volts to 4.5 volts. Thus, deselect occurs while the system is 
stable. 

Miscellaneous 

TEST MODE 

The test mode applies the oscillator output to the input of 
the millisecond counter. This affords faster testing of the 
chip. This mode is intended for factory testing, where a pro- 
grammable pulse generator is used. A pulse rate of 50 kHz 
may be used in this mode. The pulse should swing rail to rail 
and be a square wave. Apply the pulses to the oscillator 
input pin, leaving the oscillator output pin open circuit. The 
basic sequence would be to write values to the counters, 
enter test mode and apply a known number of pulses. Next, 
read the counters using normal read sequence. 

GO COMMAND 

A write to address 15 hex (data is a “don’t care”) will clear 
the seconds through milliseconds counters. If the value In 


the seconds counter Is equal to or greater than 40 when the 
GO command is executed, then the minute counter will be 
incremented. 

REST COMMAND 

Writing the value FF hex to address 12 hex causes the 
hours through milliseconds counters to be reset to zero. The 
day of week, day of month, and month counters are set to 1 . 
Writing the value FF hex to address 1 3 hex causes the RAM 
to be cleared. 

GENERAL TIMING CONSIDERATIONS: 

To guarantee a valid read/ write without using the ready out- 
put, the following criteria must be met. 

Read Operation 

1. Address setup before RD = 100 ns min 
- 2. CS to RD = 0 min 

3. Read strobe width = 950 ns min 

4. Address hold after read = 50 ns min 

Write Operation 

1. Address setup before WR = 100 ns min 

2. CS to WR = 0 ns min 

3. WR and data must be coincident for 950 ns min 

4. Data hold after WR = 1 10 ns min 

5. Address hold after WR = 50 ns min 

If the ready output Is used to guarantee read write opera- 
tion, then the following recommendations are made. Refer- 
encing the April 1 982 data sheet, during a read, the ready 
line makes its positive transition 1 00 nanoseconds before 
data is valid. (Not shown In the data sheet). The user should 
not use this signal to latch data into an external latch. If this 
signal is used to wait state a microprocessor, then a critical 
examination of the microprocessor timing with respect to 
when it terminates its wait stated cycle must be made. This 
examination must also include aqy set-up time the proces- 
sor needs prior to reading data. Also, note that the ready 
output (per the data sheet) negative-going-edge occurs 150 
nanoseconds after the read or write strobe has gone low. 
Check microprocessor timing to ensure that the ready signal 
would be recognized as a “wait-signal”. 

It is not advised to perform sequential reading by connect- 
ing chip select and read low and cycling through the coun- 
ters by changing address lines. The reason is that it is possi- 
ble to cause an internal latch to “flip,” the result being an 
error in timekeeping. 





2-190 



SOFTWARE CONSIDERATIONS 
Reading the Counters 

A read of one counter plus the rollover status bit or all the 
counters plus the rollover bit must be done within 800 mi- 
croseconds. If the rollover status bit is a “1” then a com- 
plete read of counter(s) must be performed again. The 800 
microsecond value is conservative. If the time between the 
read of any counter(s) and the rollover status bit exceeds 
800 microseconds, then the status bit will always be set. 
The order of reading must be counter(s) first, then rollover 
status bit. This is because the positive going edge of the 
read strobe clears the status bit. Refer to Figure 23. The 
status bit is enabled for a period of 1 50 microsecond maxi- 
mum at a rate of 1 kHz. If during this 150 microsecond peri- 
od a counter(s) read occurs, the status bit will be set. This is 
true no matter how often the rollover status is read during 
that time period. Each rollover status read resets the status 
bit, but any counter read within the 1 50 microsecond period 
will set the rollover status bit. If the counters are read after a 
repetitive interrupt, then allow 1 50 microseconds (conserva- 
tive) from the sense of the interrupt to the read of the coun- 
ters (ripple delay time) and the data will be valid. If the coun- 
ters are read after a compare Interrupt, the read can occur 
immediately and will be valid. 


Writing the Counters 

The counters may be written to in any order, because the 
write overrides the internal increment. If it is desired to write 
all the counters without increments occurring in between 
writes, then the complete write operation must be per- 
formed within 800 microseconds. As long as valid BCD val- 
ues (with respect to the specific counter) are written, no 
other counter is affected by the write. In general, writing the 
high order to low order counters is the conservative ap- 
proach. This method is less susceptible to increments be- 
tween writes for cases where the writing takes greater than 
800 microseconds. For initialization of time. If the “GO” 
command is issued prior to any write, then 1 0 milliseconds 
are available to write from months through tenths and hun- 
dredths of seconds without any effect due to internal incre- 
menting. 

BIBLIOGRAPHY 

MM58167A Microprocessor Real Time Clock Data Sheet 
April 1982. 

"Crystal Oscillator Design And Temperature Compensa- 
tion” By Marvin E. Frerking. 

National Semiconductor Application Note AN-313 D.C. 
Electrical Characterization Of High Speed CMOS Logic. 
LM-139 Quad Voltage Comparator Data Sheet. 



FIGURE 23. Rollover Status Bit Logic 


TL/B/5727-25 


> 



2-191 


AN-353 



AN-359 


The MM58174A Real Time 
Clock in a Battery Backed-Up 
Design Provides Reliable 
Clock and Calendar Functions 

INTRODUCTION 

National Semiconductor’s MM58174A microprocessor 
real time clock is a reliable and economical solution to 
adding clock and calendar timekeeping to any system. 
This metal-gate CMOS circuit {Figure 7) will operate with a 
supply voltage as low as 2.2V, allowing easy implementa- 
tion of battery back-up circuitry to maintain timekeeping 
year after year, even when the system’s main supply fails. 
The MM58174A has counters for months, day of month, 
day of week, hours, minutes, seconds and tenths of sec- 
onds, as well as a register for automatic leap year calcula- 
tions. Also included are periodic and single interrupt 
capabilities at 0.5, 5 and 60 second intervals. 

This application note will describe how to interface the 
MM58174A to microprocessors with battery backed-up 
circuitry. Included will be a functional circuit description, 
trouble-shooting hints, crystal oscillator adjustment and 
supplier information, Please refer to the data sheet for AC 
and DC electrical specifications and timing diagrams. 

DESCRIPTION OF FEATURES 

Reading and Writing the Time 

The MM58174A has BCD counters for tenths of seconds 
through months, which are accessed by a 4-bit address as 


National Semiconductor 
Application Note 359 
Steve Munich 
February 1984 



shown In Table I. Months through minutes registers can be 
read'and written to. Tens of seconds, units of seconds and 
tenths of seconds registers can only be read and are reset 
to zero when counting is enabled by the start/stop flip- 
flop. When properly addressed, a nibble of data appears 
on the data pins DB0-DB3 when a read occurs, and data is 
accepted on these pins during a write. Any unused data 
pins will be ignored during a write operation (e.g., days of 
week uses only DB2 through DBO). To insure proper 
counter incrementation and accessing, all timing specifi- 
cations must be observed. It is particularly important that 
the RD strobe width be less than 15 for the highest 
timekeeping accuracy, but never greater than 15 ms. 


Address 13 is a write only leap year status register. 
Writing a “1” to DB3 at this address will cause the time 
02/28 23:59 59.9 to roll over to 02/29 00:00 00.0 in one-tenth 
of a second. If a “1 ” is instead written to any other data bit, 
the roll-over will go to 03/01 00:00 00.0 and the leap year 
will occur as shown in Table II. 


CONTROL BUS ADDRESS BUS INTERRUPT DATA BUS 



TL/F/6169-1 

FIGURE 1. Block Diagram 


2-192 











TABLE I. Address Decoding for Internal 
Registers 


Selected Counter 

Address Bits 
AD3 AD2 ADI ADO 

Mode 

0 Test Only 

0 

0 

0 

0 

Write Only 

1 Tenths of Seconds 

0 

0 

0 

1 

Read Only 

2 Units of Seconds 

0 

0 

1 

0 

Read Only 

3 Tens of Seconds 

0 

0 

1 

1 

Read Only 

4 Units of Minutes 

0 

1 

0 

0 

Read or Write 

5 Tens of Minutes 

0 

1 

0 

1 

Read or Write 

6 Units of Hours 

0 

1 

1 

0 

Read or Write 

7 Tens of Hours 

0 

1 

1 

1 

Read or Write 

8 Units of Days 

1 

0 

0 

0 

Read or Write 

9 Tens of Days 

1 

0 

0 

1 

Read or Write 

10 Day of Week 

1 

0 

1 

0 

Read or Write 

11 Units of Months 

1 

0 

1 

1 

Read or Write 

12 Tens of Months 

1 

1 

0 

0 

Read or Write 

1 3 Years 

1 

1 

0 

1 

Write Only 

14Stop/Start 

1 

1 

1 

0 

Write Only 

15 Interrupt 

1 

1 

1 

1 

Read or Write 


TABLE 11. Years Status Register 


Mode: Address 13, Write Mode | 


DBS 

DB2 

DB1 

DBO 

Leap Year 

1 

0 

0 

0 

Leap Year - 1 

0 

1 

0 

0 

Leap Year -2 

0 

0 

1 

0 

Leap Year -3 

0 

0 

0 

1 


Detecting Changed Data 

It is possible that during a sequential read of months 
through tenthsof seconds a roll-over may occur. If the time 
at the start of the read is 23:59 59.5 and it rolls over to the 
time 00:00 00.0, the microprocessor could read back 23:50 
00.0 or 23:00 00.0, etc. Wrong data could also be stored in 
the clock if the clock is running and is updated during a 
write (the start/stop flip-flop discussed in the next* 
paragraph will help avoid invalid writes). The MM58174A 
has a data-changed flip-flop which indicates that a tenths 
of seconds roll-over has occurred. This flip-flop sets all the 
data lines high each time the tenths of seconds counter is 
updated. The “F” on the data lines is then cleared by the 
next low-to-high transition of any read strobe. In a sequen- 
tial read of the counters, the tenths of seconds counter 
may change while the read strobe is low, but an “F” may 
never be seen before the read strobe comes high. Thus, 
the “F” may not be detected, although the experimental 
probability of this occurrence is approximately one In ten 
thousand reads, in the worst-case. It is essential to restart 
the whole sequence of reads, beginning from the tens of 
months register whenever an “F” is encountered on the 
data lines. A better procedure, outlined in the flowchart of 
Figure 2, would be to always begin each sequence of 
reads with the tenths of seconds register and end with this 
register. If comparing the two values read from this 
register shows them to be equal, the data read is valid and 
should be used. If the compare yields two different values, 
repeat the same sequence of reads until the same value is 



TL/F/6169 2 


FIGURE 2. Flowchart to Detect Changed Data 

read from the tenths of seconds register at the beginning 
and end of the sequence. It is advisable to use a machine 
code clock reading routine, or else the time to execute 
machine-interpreted code may be longer than one-tenth of 
a second, invalidating all sequential reads. 

Clock Accuracy 

Two important factors affect the accuracy of the 
MM58174A. Any internal counter can jitter by -30.5 ns, 
meaning that the true count can be late by this amount. 
Also, whenever the clock is restarted (see next section), in- 
stead of holding a “0” in the tenths of seconds position for 
one-tenth of a second, the clock immediately jumps to a 
“1 ”. So each time the clock is restarted, one-tenth of a sec- 
ond is lost. Accuracy would be maintained if the clock Js 
restarted 0.1 second after the time reference’s minutes 
change. 


2-193 


AN-359 



AN-359 


Starting and Stopping the Clock 

Table I shows that address 14 accesses the start/stop flip- 
flop. A “1 ” on DBO will start the clock. Writing a “0” to DBO 
will stop it. This flip-flop is used for precise starting and 
stopping of the clock. It also prevents writing invalid data 
during a clock roll-over, as mentioned in the last para- 
graph. Before any sequence of writes, stop the clock. 
Restart it after the last write is completed: 

Interrupts 

The interrupt counter is controlled internally by three se- 
quential flip-flops. By sending a sequence of read strobes 
to these flip-flops, the interrupt counter can be cleared or 
enabled. Initialization is necessary at power-up because 
these flip-flops can come up in any state. It is also 
necessary to re-initialize if an interrupt is not serviced 
■within 16.6 ms. To initialize interrupts on the MM58174A, 
first write a “0” on the data lines at address 15, then read 
that address three times. The first read will clear any inter- 
rupts set. The second read insures that the counter is 
reset and the third read enables interrupts. Be sure to 
disable the microprocessor from accepting interrupts 
before initialization, because the act of writing “0” to ad- 
dress 15 may cause an interrupt. 

Table III indicates which values turn on the 0.5, 5 and 60 
second periodic or single interrupts. These values are writ- 
ten at address 15, as shown in Table I. To set a particular 
interrupt, a write need only occur once. Whenever an inter- 
rupt occurs, the signal at pin 13 falls from high to low. 


TABLE III. Interrupt Selection and Status 


Mode: Address 15, Read or Write Mode | 

Function 

DBS 

DB2 

DB1 

DBO 

No Interrupt 

X 

0 

0 

0 

Int. at 60 Sec. Interval^ 

* 

1 

0 

0 

Int. at 5.0 Sec. Interval^ 

* 

0 

1 

0 

Int. at 0.5 Sec. Intervall" 

* 

0 

0 

1 


*0 for single interrupt (write), 1 for periodic interrupt (write), 
X don’t care (read) 
f^Add 16.6 ms to each time interval 


To service the interrupt, read address 15 three times. This 
causes tbs' interrupt output on pin 13 to return high and 
restarts the interrupt timer if periodic interrupts have been 
selected. The interrupt register may be read to see which 
interrupts have been set, but the MM58174A has no status 
bit indicating that the clock has sent out an interrupt. A 
version prior to the MM58174A had interrupt acknowl- 
edgement capability (the MM58174), so be sure to match 
data sheets with the correct parts. One final note about in- 
terrupts: they are not intended to be generated when the 
chip is in the sleep mode (see next paragraph). The 
MM58174A must be running with at least a 4V supply for 
interrupts to function. 

Powering Down and Up 

When the supply to pin 16 falls below 5V, timing becomes 
much more critical because propagation delays increase 
with a lowering of the power supply voltage. Note that the 
data sheet has timing specifications for 5V, and although 
the part Is fully operational down to^V, your design may 


not tolerate it. When the supply falls below 4V but stays 
above 2.2V, the MM58174A is in the sleep mode and only 
microamps are drawn from the battery. In this mode, the 
chip is not accessible by reading or writing, but time is be- 
ing maintained. 

On power-up from zero volts Vqq, one must make sure the 
chip is not in the test mode. This is done by writing a “0” to 
DB3 at address 0. It is advisable to do this even when com- 
ing out of the sleep mode. The test mode is mainly for pro- 
duction testing of the circuit. 

There are several things to consider when designing the 
power-down circuitry. The basic functional requirements 
are to disable the chips before full power loss or malfunc- 
tion, and to wait for Vqq to stabilize before enabling the 
chip on power-up. A desirable feature would be to allow 
the read or write in progress to complete. Figures 3 and 4 
include a typical power-down circuit which achieves these 
goals. In general, avoid using TTL since it is not rated 
below 4.5V. The power-down circuitry’s signals to the 
MM58174A must not be allowed to deviate more than a 
diode drop above the clock’s supply or below ground in 
order to avoid triggering SCR latch-up. Finally, be sure to 
use a PNP switch instead of a diode to disconnect the 
power supply from the battery. This will allow the 
MM58174A to see a Vqq closer to 5.0V coming from the 
main supply rather than 4.3V, enhancing timing re- 
quirements. See Figures 3 and 4 and the next section for 
more information on design of power-down circuitry. 

DESIGN IDEAS 

Figures 3 and 4 show two possible ways of interfacing the 
MM58174A to a microprocessor; the former with wait 
stating and the latter eliminating wait states using the 
NSC810A RAM/10 timer as a peripheral interface adapter. 

Real Time Clock Interface with Wait States 

the design of Figure 3 uses wait states to guarantee that 
the set-up and hold times of the MM581 74A are satisfied. If 
one can afford to constrict his microprocessorthroughput 
while accessing the MM58174A, this design has the ad- 
vantages of simplified software and somewhat less ex- 
pensive hardware. Decreased microprocessorthroughput 
is usually not a consideration in most applications unless 
‘the clock is continuously being accessed for a real time 
display, while at the same time the processor is multi- 
plexing the execution of other tasks. 

The HC688S of Figure 3 are used to fully decode the 4 bits 
of address space for the real time clock and to generate 
chip select and wait states. Each time an address be- 
tween 4080H and 408FH appears on the address lines of 
the bus, the second of the cascaded HC688s generates a 
low strobe that allows the power-down circuitry to create a 
chip select, and also fires an HC123 one-shot configured 
to drive a 2 ^s wait state onto the wait line of the micro- 
processor bus. For wait lines of the opposite polarity, the 
HC123’s Q output could be used. A shift register may also 
be configured to give the proper access time delay. 

Power is supplied to the parts from a 5.0V supply which is 
disconnectable by a PNP switch to a battery. When the 
main supply is on, the PNP in saturation brings the voltage 
at node B to about 4.8V. The diode near node B is back- 
biased to keep the battery from discharging and to protect 
it from damage by isolating it from 5V. If the main supply 
were to drift far enough downward, the diode would 
forward-bias, bringing node B to 0.7V below the battery 
voltage. Since the clock is now in the sleep mode, the only 


2-194 




parts needed to be powered by the battery are the clock 
and the power-dow n ci rcuitry. An NPN between the bus 
connection and the WR pin, as shown in Figure 3, will re- 
duce power consumption without inverting the signal into 
this pin. This is made necessary because both CS and WR 
inputs on the MM58174A have pull-ups to Vqc which could 
cause an unnecessary current drain if either input were to 
become grounded_Trhe NPN switch isolates the WR from 
ground, while the CS input is held high by the power-down 
circuitry. 

Power-Down Circuitry Operation 

The power-down circuitry of Figures 3 and 4 consists of 
seven HCOO NAND gates and an LM139 low voltage com- 
parator with an assortment of resistors, diodes and ca- 
pacitors at the differential input. 

With the 5.0V supply on, the assortment of diodes, 
resistors and capacitors at the comparator’s differential 
input creates a low output. But when the supply is off, the 
battery pulls this output high through the 20 k^2 resistor. 
On power-up, after a short delay by the diodes and capaci- 
tors at the inverting input, the LM139’s low level output 
enables a latch made from HCOO NAND gates to allow a 
chip select from the ‘HC688 {Figure 3) or the NSC810A 
{Figure 4) to flow through to pin 1 (CS) of the MM58174A. 

As power from the 5.0V supply falls below 4.5V, the com- 
parator’s output immediately goes high. This threshold 
voltage is adjustable by the 200 kfi potentiometer at the 
LM139’s inverting input. A high output from the com- 
parator to the NAND latch will disable chip selects to the 
MM58174A. 

So as power begins to fail, this circuit will allow reads or 
writes to the MM58174A to go to completion if tf)e chip is 
selected before the LM139’s _^utput goes high. This 
assumes that the MM58174A’s CS pin returns high before 
the supply falls to 4.0V (the minimum Vqc to access the 
chip). The length of the chip select strobe determines the 
limit of how fast the main power supply can drop from 4.5V 
to 4.0V. In situations where power failure detection is more 
critical, it is suggested that the comparator’s output be 
connected to the microprocessor’s highest priority inter- 
rupt so that the necessary software can be accessed. 

This power-down circuitry has the advantage of proper 
operation in the presence of noise. With a slowly falling 
power supply in a noisy environment, the comparator’s 
output may oscillate momentarily. This oscillation will 
have no bearing on the chip select signal to the MM58174A 
in this circuit because the HCOO latch only allows chip 
selects when the LM139 output is high, and it also does 
not alter their length once they begin. When the supply 
falls low enough to stop the comparator from oscillating, 
chip selects are locked out. One may consider the time 
that the comparator bounces as a delay before chip ac- 
cess is completely locked out as the standby mode is 
entered. If the cessation of comparator oscillation is 
desired, hysteresis can be added. A diagram of this can be 
found in the LM139 data sheet. 

Real Time Clock Interface without Wait States Using a PIA 

Figure 4 shows the details of a design using the NSC800™ 
CMOS microprocessor and the NSC810A as a peripheral 
interface adapter. This has the advantages of lower chip 
count and the absence of wait states. Similar PIAs, such 
as the INS8255 or the 8155, could be used with some soft- 
ware adaptation. The power-down circuitry is operation- 
ally equivalent to that of Figure 3, except that in this 


design the chip select is created by the PIA. Only the 
essential connections between the NSC800 and the 
NSC810A are shown in the Figure 4. 

The NSC800 is an 8-bit CMOS microprocessor combining 
the features of the Intel 8085 and the Zilog Z80''V In this ap- 
plication 8085 code is used to manipulate the control 
strobes and handle interrupts as detailed in Figures 5 
through 9. The interconnection between the NSC800 and 
the NSC810A is straightforward, except for the CE con- 
nection on the NSC810A. By tying CE to A13 of the 
NSC800, chip enabling occurs whenever an IN 2X or an 
OUT 2X instruction is executed, because the same port ad- 
dress appears on NSC800 lines AD0-AD7 as on A8-A16. 
Using 2X will raise A13 on the NSC800 high, where X 
represents a specific port address. This method of ena- 
bling is entirely optional. For more information on the 
NSC800 and NSC810A, refer to the NSC800 Microproc- 
essor Family Handbook. ^ 

Software Description 

The ports on the NSC810A are specially configured to con- 
trol the data, address and control lines. The software allows 
the port sign als to fulfill timmg requirements. Port C is used 
to control the WR, RD and CS lines, port B is used to control 
the address lines, and port A is used to read and write the 
data. 

The NSC810A is configured into the strobed input mode in 
the read subroutine in order to get the shortest possible 
RD strobe. As stated previously, the read strobe must be 
under 1 5 /xs to guarantee prop er co unter operation. The RD 
strobe is fed back to the PC2/STB input of the NSC810A in 
order to latch in the data from the MM58174A. The read 
subroutine of Figure 5 begins by setting th e po rt C direc- 
tion. All bits are set for output, except PC2/STB, which is 
set for input. Port B is set out and port A is set in. Next, all 
the control strobes from port C are set high using bit set. 
Before calling the read routine, the MM58174A address to 
be accessed was loaded into the NSC800’s register B, and 
it is now sent out on port B. Bit clear is used to lower the 
CS strobe from PC5. The mode definition register is then 
written to for selecting the strobed mode of the NSC810A. 
Bit clear is used to lower the RD strobe from port C, and 
before it is raised again, a MOV instruction puts control 
values from port C Into the accumulator in the shortest 
time possible. Using these three instructions, the read 
strobe is held low for a bout 5 ^s. The rising edge of the RD 
strobe Is fed into PC2/STB to latch the data into port A, 
and the IN instruction reads the data. Before exiting the 
read subroutine, the mode definition register of the 
NSC810A is again accessed to return the PIA’s operation 
to the basic I/O mode. A wait loop may be added to the 
read subroutine or elsewhere in the code to limit the 
number of read strobes to less than 10,000 per second. 
This specification has been added because more than 
10,000 reads per second can slightly degrade timekeeping 
accuracy. The write subroutine of Figure 6 uses the 
NSC810A ports in the same manner as the read routine; 
i.e., port A for data, port B for address and port C for con- 
trol strobes. However, there is no need to latch the data in 
port A, so the basic I/O mode is used. The write subroutine 
uses the control strobes from port C by beginning with all 
three strobes high, manipulating CS and WR low, and fi- 
nally bringing these port outputs high again. Before call- 
ing the write subroutine, the desired address to be ac- 
cessed is to be stored in the NSC800’s register B, and data 
stored in register A. 



2-195 


AN-359 




TYPICAL MICROPROCESSOR 
BUS 


i P3 05 1 

„„ MM74HC688 I 
P2 04 1 


I PS 05 1 

MM74HC688 „ | 
P2 041 


AN-359 


5V SUPPLY - 
2N2g07 


_y 1 LM336 

JL L A 2.5V REF 


[Bl 2N222 





cs 

RD 

WR 

DBS 

Vdd 

XTAL IN 

XTAL OUT 

INT 

MM58174A. . 1 

DB2 

ADD 

DB1 

AD1 

DBO 

AD2 

Vss 

ADS 


r-oQ— 


Q = 32.768 kHz crystal (RCD, Saronix) 

Cy = variable capacitor (Erie, Circuit.Specialists) 


FIGURE 3. Real Time Clock Interface with Walt States 



2-197 



FIGURE 4. Real Time Clock Interface to NSC800 and NSC810A without Wait States 


l>0 


69e-NV 




AN-359 


READ; MVI A, OFBH 
OUT 026H 
MVI A, OFFH 
OUT 025H 
MVI A, OOH 
OUT 024H 
MVI A, 038H 
OUT 02EH 
MOV A, B 
OUT 021 H • 
MVI A, 020H 
OUT02AH 
MVI A, 01 H 
OUT 027H 
MVI C, 030H 
MVI A.010H 
OUT 02AH 
MOV A, C 
OUT 02EH 
IN 020H 
ANIOFH 
MOV C, A 
MVI A, OOH 
OUT 027H 
MOV A. C 
RET 


DATA IS RETURNED INTO REG A 
SET PORT C 

;DIRECTION 
SET PORT B 

iDIRECTION OUT 
SET PORT A 

;DIRECTION IN 
SET PC3, PC4 & PCS HIGH 
;USING BIT SET 
PUT ADDRESS IN A 
ADDRESS OUT ON PORT B 
BIT CLEAR - PCS 

;CHIP SELECT 
SELECT STROBED 
;MODE 
GET READY 
BIT CLEAR - PC4 
;RD STROBE 
LATCH DATA IN PORT A 

:& BRING STROBES HIGH 
GET DATA FROM PORT A 
MASK-OUT LOWER BITS 
SAVE DATA 
RETURN TO 

;BASIC I/O MODE 
RECOVER DATA 


TL/F/6169-5 


FIGURE 5. Read Subroutine 


MOV C, A 

;BEFORE CALLING WRITE SUBROUTINE 
iSTORE 174A ADDRESS IN REG B 
;ANDDATAIN REG A 
iSAVE DATA IN REG C 

MVI A, OFBH 


OUT 026H 

;SET PORT C DIRECTION ■ 

MVI A, OFFH 
OUT 022H 

;SET PORT C HIGH 

OUT 024H 

;SET PORT A DIRECTION OUT 

OUT 025H 

;SET PORT B DIRECTION OUT 

MOV A, B 

;MOVE 174A ADDRESS TO REG A 

OUT 021 H 

iADDRESS OUT FROM PORT B 

MVI A, 020H 

;CHIP SELECT - BIT CLEAR 

OUT 02AH 

;ON PCS 

MVI A, 08H 

iWRITE STROBE - BIT CLEAR 

OUT02AH 

;ON PC3 

MOV A, C 

;RECOVER DATA FROM REG C 

OUT 020H 

:DATA GOES OUT 

MVI A, OFFH 

:SET PORT C 

OUT 022H 

;HIGH 

RET 



TL/F/6169-6 

FIGURES. Write Subroutine 


ORG 1200H 
LXI SP.OIFH 
MVI A, OOH 
MVI B, OOH 
CALL WRITE 
LXI H, VECTOR 
SHLD1016H . 
MVI A, 04H 
OUTOBBH 
Dl 

MVI A, OOH 
MVI B.OFH 
CALL WRITE 
CALL READ 
CALL READ 
CALL READ 
El 


.•ORIGINATE @1200H 
:LOAD STACK POINTER 
iENTER NON-TEST MODE 


rVECTOR" IS INTERRUPT SERVICE 
:ROUTINE @1016H 
;SET NSCSOO’S INTERRUPT CON- 
:TROL REGISTER FOR RSTA 
iDISABLE NSC800 INTERRUPTS 
iENABLE INTERRUPTS ON 174A 


:ENABLE NSC800 INTERRUPTS 

I 

TL/F/6169-7 

FIGURE 7. Initialization 


Figure 7 shows the necessary initialization code for the 
NSC800, NSC810A, and the MM58174A, which usetheread 
and write subroutines. Of greatest importance is the code 
to insure that the clock is not in the test mode. Notice that 
a Dl instruction is used to disable interrupts before a “0” is 


written to address 15. Also included is the code to initial- 
ize interrupts on the MM58174A. F/gt/reSshows the inter- 
rupt service routine, while Figure 9 shows a method of 
time setting by first stopping the clock, then restarting it 
once the setting is complete. 


VECTOR; MVI B, OFH 
CALL READ 
CALL READ 
CALL READ 
El 

RET 


TL/F/6169 


FIGURE 8. Interrupt Service Routine 


MVI A, OOH ;STOP CLOCK USING 

MVI B, OEH :START/STOP FLIP-FLOP 

CALL WRITE 

(time setting code) 

MVIA, 01H 
MVI B.OEH 
CALL WRITE 


TL/F/6169-9- 

FIGURE 9. Recommended Procedure for Setting Time 


Oscillator Design 

The MM58174A is driven by a standard Pierce oscillator. 
Figure 70 shows both the internal and external component 
sizes to be used. For crystals with a power rating of less 
than 1 fjSN, a 200 kfi resistor, in series with the oscillator 
output, should be used to insure that the crystal is not 
overdriven. The typical gain for the internal inverter and in- 
ternal 200 kfi series resistor is 20 at 1 kHz input frequency 
and about 5 at 30 kHz. The oscillator may take from two to 
seven seconds to begin oscillating due to the high Q of the 
crystal. 


20M 



FIGURE 10. Crystal Oscillator 
Crystal Information 

Choose one of the following crystal types: parallel reso- 
nant or tuning fork (NT CUT or XY BAR) with a Q> 35,000 
and a frequency of 32.768 kHz. The load capacitance re- 
quired ranges from 9 pF to 13 pF. The maximum power 
rating is 20 (AN. The choice of crystal accuracy and 
temperature coefficient are left to the user. Two crystals 
used in our lab are RCD’s #RV-38 and Saronix’s 
#NTF3238C. 


I 


2-198 




Oscillator Adjustment and External Drive 

A well-tuned oscillator for the MM58174A will have a fre- 
quency error of no more than ± 10 ppm. This would result 
in the clock being off by ±5 minutes per year. This is a 
worst-case number, taking into account such factors as 
temperature variation (-40“C to 85°C) and supply varia- 
tion (2.2V to 5.5V). The external oscillator components can 
also contribute to error and this should be taken into ac- 
count by the user. 

Adjusting the trimmer capacitor at pin 15 will minimize the 
oscillator error. But simply putting a scope probe on the 
crystal will load the oscillator with at least 10 pF, 
significantly altering the frequency. There are two good 
ways of isolating the probe from the oscillator. One 
method is to put the part in the test mode by writing a “0” 
to DBS at ADO, then tune the signal at DBO to 16,384.00 Hz 
using an accurate frequency counter. Another method 


would be to isolate the oscillator from the probe by adding 
an inverter to the small capacitance at pin 14. This would 
load the oscillator, but the Input capacitance of the gate 
would not be affected by a probe at the output. The total 
capacitance on pin 14 should be kept near 15 pF. 

To drive the oscillator from an external clock, connect the 
clock to pin 14 (crystal out) and tie pin 15 (crystal in) high. 


CONCLUSION 

The MM58174A can easily be interfaced to a microproc- 
essor to bring the functions of a real time clock and calen- 
dar to any system. With a power-fail/back-up circuit, the 
system will be able to keep accurate time for years, in- 
dependent of the system power supply. 



2-199 


AN-359 




AN-365 


The MM58274 Adds Reliable 
Real-Time Keeping to Any 
Microprocessor System 


INTRODUCTION 

When a Real-Time Clock (RTC) is to be added into a digital 
system, the designer will face a number of design con- 
straints and problems that do not usually occur in normal 
systems. Attention to detail in both hardware and software 
design is necessary to ensure that a reliable and trouble 
free product is implemented. 

The extra circuitry required for an RTC falls Into three main 
groups: a precise oscillator to control real-time counting; a 
backup power source to maintain time-keeping when the 
main system power is removed; power failure detection and 
write protection circuitry. The MM58274 in common with 
most RTC devices uses an on-chip oscillator circuit and an 
external watch crystal (frequency 32.768 kHz) as the time 
reference. A battery is the usual source of backup power, 
along with circuitry to isolate the battery-backed clock from 
the rest of the system. Like any CMOS component, the RTC 
must be protected against data corruption when the main 
system power fails; a problem that is very often not fully 
appreciated. 

Rather than dealing strictly with any one particular applica- 
tion, this applications note discusses all of the aspects 
involved in adding a reliable RTC function to a microproc- 
essor system, with descriptions of suitable circuitry to 
achieve this. Hardware problems, component selection, and 
physical board layout are examined. The software examples 
given in the data sheet are explained and clarified, and 
some other software suggestions are presented. Finally a 
number of otherwise unrelated topics are lumped together 
under ‘Miscellany’; including a discussion on how the 
MM58274 may be used directly to upgrade an existing 
MM58174A installation. 

I • 

CONTENTS 

1.0 HARDWARE 

1.1 COMPONENT SELECTION 

1.1.1 Crystal 

1.1.2 Loading Capacitors 

1.1.3 Backup Battery: 

Capacitors 

Nickel-Cadmium Cells 

Alkaline 

Lithium 

Other Cells and Notes 
Temperature Range 

1.2 BOARD LAYOUT 

1.2.1 Oscillator Connection 

1.2.2 - Battery Placement 

1.2.3 Other Components 


National Semiconductor 
Application Note 365 
Peter K. Thomson 
April 1984 


1.3 POWER SUPPLY ISOLATION SCHEMES 

1.3.1 The Need for Isolation 

1.3.2 Isolation Techniques I — 5V Supply Only 

1.3.3 Isolation Techniques II — Negative 
Supply Switched 

1.3.4 Other Methods 

1.4 POWER FAIL PROTECTION 
i;4.1 Write Protect Switch 

1.4.2 5V Sensing 

1.4.3 Supply Pre-Sense 

1.4.4 Switching Power Supplies 

1.4.5 Summary 

2.0 SOFTWARE 

2.1 DATA VALIDATION 

2.1.1 Post-Read Synchronization 

2.1.2 Pre-Read Synchronization 

2.2 INTERRUPT AS A ‘DATA-CHANGED’ FLAG 

2.3 WRITING WITHOUT HALTING TIME-KEEPING 

2.4 THE CLOCK AS A ^P WATCHDOG 

2.5 THE JAPANESE CALENDAR 

3.0 MISCELLANY 

3.1 CONTIECTION to NON-MICROBUS SYSTEMS 

3.2 TEST MODE 

3.3 TEST MODE AND OSCILLATOR SETTING 

3.4 UPGRADING AN MM58174 SYSTEM WITH 
THE MM58274 

3.5 WAIT STATE GENERATION FOR FAST /iPs 

APPENDIX A-1 Reading Valid Real-Time Data (Reprinted 
from the MM58274 Data Sheet) 

APPENDIX A-2 MM58274 Functional Truth Tables 

1.0 HARDWARE 

Selecting the correct components for the job and imple- 
menting a good board layout is crucial to developing an 
accurate and reliable Real-Time Clock function. The range 
of component choices available is large and the suitability of 
different types depends on the demands of the system. 

1.1 COMPONENT SELECTION 

With reference to Figure 1, the oscillator components and 
the battery are examined and the suitability of different 
types is discussed. 



2-200 





100 nF DISK tuf/6737 i 


FIGURE 1. MM58274 System Installation 


1.1.1 Crystal 

The oscillator is designed to work with a standard low power 
NT cut or XY Bar clock crystal of 32.768 kHz frequency. The 
circuit is a Pierce oscillator and is shown complete in Figure 
2. The 20 Mfi resistor biases the oscillator into its linear 
region and ensures oscillator start-up. The 200 kfi resistor 
prevents the oscillator amplifier from overdriving the crystal. 
If very low power crystals are used (i.e., less than 1 fiVsi) an 
external resistor of around 200 kfi may have to be added to 
reduce the drive to the crystal. 

The oscillator will drive most normal watch crystals, with up 
to 20 /tW drive available from the on-chip oscillator. 



FIGURE 2. Complete Oscillator Diagram 


1.1.2 Loading Capacitors 

Two capacitors are used to provide the correct output load- 
ing for the crystal. One is a fixed value capacitor in the 
range 18 pF-20 pF and the other is a variable 6 pF-36 pF 
trimmer capacitor. Adjusting the trimmer allows the crystal 
loading (and hence the oscillator frequency) to be fine tuned 
for optimal results. 

The capacitors are the components most likely to affect the 
overall accuracy of the oscillator and care must be exer- 
cised in selection. Ceramic capacitors offer good operating 


temperature range with close tolerance and low tempera- 
ture coefficients (typically ± 3 ppm/K, for good quality exarh- 
ples). If trimming is undesirable a pair of close tolerance 
(±5% or better) capacitors in the range 18 pF-20 pF may 
be used. The average time-keeping accuracy for this config- 
uration is within ±20 seconds per month. 


1.1.3 Backup Battery 

There are a number of different cell types available that can 
be used for time-keeping retention. Some cells are more 
suitable than others, and the way in which the system is 
used also influences the choice of cell. Ideally the standby 
voltage of the RTC should be kept as low as possible, as the 
supply current increases with increasing voltage (Figure 3). 
Four different power sources are discussed; capacitors, 
nickel-cadmium rechargeable cells, alkaline and lithium pri- 
mary cells. 



1 2 3 4 5 6 

Vdd (V) TL/F/6737-3 


FIGURE 3. Typical Iqd (mA) vs. Vqd (V) for MM58274 in 
Standby Mode (T^ = 25°C) 



2-201 


AN-365 






AN-365 


Capacitors 

When the system is permanently powered, and any long 
term removal of system power (i.e., more than a few hours) 
requires complete restarting, then a 1-2 Farad capacitor 
may be sufficient to run the clock’ during the power down. 
This can keep the clock running for 48-72 hours. 

Nickel’Cadmiurh Cells 

Nickel-cadmium (Ni-Cad) cells can be trickle-charged from 
the system power supply using a resistor as shown in Figure 
1. The exact value of resistor used depends on the capacity 
and number of cells in the battery. Consult the manufactur- 
ers data for information on charging rates and times. 

A 3- or 4-cell battery should be used to power the clock (the 
nominal battery voltages are 3.6V for 3 cells in series and 
4.8V for 4 cells), with 3 cells preferable. PCB mounting bat- 
teries of 100 mAh capacity are available and these will give 
around 6 months data retention (at normal room tempera- 
ture). For this cell type to be used the system must spend a 
large proportion of its time turned on to keep the battery 
charged (i.e., used daily). 

Alkaline 

Alkaline cells are among the least expensive primary cells 
which are suitable for use in real-time clock applications. 
They are available in a large range of capacities and shapes 
and have a very good storage (shelf) life. 

Two cells in series will provide a nominal 3V, which is ade- 
quate to power the clock (via the isolating diode). The main 
problem with the alkaline system is that the cell terminal 
voltage drops slowly over the life of the cell. When the volt- 
age at the clock supply pin drops to 2.2V, the cells must be 
replaced (battery voltage around 2.6V-2.7V). With present 
alkaline cells, this point is usually reached when the cells 
are only Vs to Va discharged. 

Provisions must be made either to check the battery voltage 
at regular intervals or to replace the cells regularly enough 
to avoid the danger of using discharged cells. Once again 
the manufacturers data regarding capacity and cell voltage 
against time must be examined to determine a suitable cell 
selection. A good alkaline system will supply 1-2 years con- 
tinuous time-keeping. 

Lithium 

Lithium cells are the most suitable cell for real-time clock 
applications. A single cell with 3V potential Is sufficient to 
power the system. The cell potential is very stable over use 
and the storage life is excellent. The energy density of lith- 
ium cells is very high, giving enough capacity in a physically 
small cell to power the clock continuously for at least 5 years 
(at room temperature using a 1,000 mAh cell). 

Several cells which are recommended for RTC use are 
D2/3A*, D2A*, and 1/6DEL/P"*. Each have 1,000 mAh 
capacity. These cells are available with solder pin connec- 
tions for PCB mounting, giving a reliable backup supply. 

Other Cells and Notes 

There are many other types of cells, both primary and sec- 
ondary, which may be adapted for RTC use. When selecting 
a cell type, attention must be paid to: 

a. Cell capacity and physical size. 

b. Storage (shelf) life. 

c. Voltage variation over use. 


‘Duracell Trade Number. 
“Tadiran Trade Number. 


d. Operating temperature range. 

e. The method of battery connection and mounting. 

In general soldered cells are preferable to connector 
mounted cells. With replaceable batteries, the battery and 
connector contacts must be kept thoroughly clean. Dirty or 
corroded contacts can cause the clock to be starved of 
power, giving erratic and unreliable performance. The ease 
of operator access for cell replacement should also be con- 
sidered. 

Temperature Range 

The performance of any cell will be satisfactory for most 
office or domestic environments. When ‘ruggedized’ equip- 
ment is to be used (i.e., field portable equipment, automo- 
tive, etc.) the temperature specification of different cell 
types should be taken into account when selecting a cell. 
Lithium cells offer good performance over 0®C-70®C with 
little loss in capacity. Once again, the manufacturer’s data 
should be examined to determine suitability, especially 
since different cells of the same type can have markedly dif- 
ferent characteristics. 

Few types of cells will offer any useful capacity at tempera- 
tures in or below the range 0°C-10°C, and fewer still will 
operate over the full military temperature range (-55°C to 
-}-125°C). Solid lithium cells and mercury-cadmium cells 
are two systems which can cover this range. 

1.2 BOARD LAYOUT 

1.2.1 Oscillator Connection 

The oscillator components must be built as close to the pins 
of the clock chip as is physically possible. The ideal config- 
uration is shown in Figure 4. From Figure 2, the oscillator 
circuit, it can be seen that both Osc In and Osc Out are high 
impedance nodes, susceptible to noise coupling from adja- 
cent lines. Hence the oscillator should, as far as is practica- 
ble, be surrounded by a guard ground. The absolute 
maximum length of PCB tracking on either pin is 2.5 cm (1 
inch). Longer tracks increase the parasitic track to track 
capacitances, increasing the risk of noise coupling and 
hence reducing the overall oscillator stability. 

Where the system operates in humid or very cold environ- 
ments (below 5°C), condensation or ice may form on the 
PCB. This has the effect of adding parasitic resistances and 
capacitances between pins 14 and 15, and also to ground. 
This variation in loading adversely affects the stability of the 
oscillator and in extreme cases may cause the oscillator to 
stop. 

Keeping the PCB tracks as short as possible will help to 
minimize the problem, and on its own this may be sufficient. 
Where the operating conditions are particularly severe, the 
PCB and oscillator components should be coated with a 
suitable water repellent material, such as lacquer or silicon 
grease (suitability being determined by the electrical prop- 
erties of the materials — high impedance and low dielectric 
constant). 

Figures 2 and 4 show the trimmer placed on Osc Out. The 
placement of the trimmer capacitor on either Osc In or Osc 
Out is not critical. Placing the trimmer on Osc Out yields a 
smaller trim range, but less susceptibility to changes in trim- 
mer capacitance. Placement of the trimmer capacitor on 
Osc In gives a wider trim span, but slightly greater suscepti- 
bility to capacitance changes. 


2-202 




MM58274 



FIGURE 4. Oscillator Board Layout 


1.2.2 Battery Placement 

For the battery, placement is less critical than with the oscil- 
lator components. Practical considerations are of greater 
importance now; i.e. accessibility. The battery should be 
placed where it is unlikely to be accidentally shorted or dis- 
connected during routine operation and servicing of the 
equipment. 

When replaceable cells are used, connecting a 100 (if 
capacitor across the RTC supply lines will keep the clock 
operating for 30-40 seconds with the battery disconnected 
(Figure 5). This allows the battery to be replaced regardless 
of whether or not the main supply is active. 


BATTERY 



FIGURE 5. Simplified Power Supply Diagram with 
100 (if Capacitor Added 


1.2.3 Other Components 

The placement of the other RTC dedicated components 
(e.g., supply disconnection and power failure protection 
components) is not particularly critical. However, the same 
guidelines as applied to the battery should be followed when 
the PCB layout is designed. 

1.3 POWER SUPPLY ISOLATION SCHEMES 
1.3.1 The Need for Isolation 

There two reasons for disconnecting the clock circuit from 
the rest of the system: 

1. To prevent the backup battery from trying to power the 
whole system when the main power fails. 

2. To minimize the battery current (and extend battery life) 
by preventing current leakage out of the RTC input pins. 

The MIVI58274 inputs have internal pull-up devices which 
pull the Inputs to V^d in power down mode. This turns off the 
Internal TTL input buffers and causes the interface func- 
tions of the clock to go to full CMOS logic levels, drawing no 
supply current (except for the unavoidable leakage current 
of the internal MOS transistors). For the MM58274 this is 
achieved by isolating the ground (Vss) supply line from the 
rest of the system. 

Figures 6a and 6b show the two cases where first N/qd fSaj 
and then Vss s'"® open-circuited. The line out from the 
MM58274 represents any of the Control, Address, or Data 
lines on the RTC, with the internal pull-up resistor shown. 
The two diodes and resistor Rs represent the logic device 
connected to the RTC input and the resistance of the rest of 
the system with no power applied. 



2-203 


AN-365 



AN-365 


i 


Vdo disconnection 



(EQUIVALENT SYSTEM 
Rs RESISTANCE WITH NO 
POWER APPLIED) 



a) Vqd Disconnection b) Vss Disconnection 

FIGURE 6. Current Leakage Prevention by Proper Supply Disconnection 


When VpD is open-circuit as in Figure 6a, there is a com- 
plete current path, shown by the arrows, out of the RTC 
input and through the external circuitry. This battery current 
is a complete waste and serves only to reduce the cell life. 
Depending on the value of Rs, the voltage level at the pin 
may fall low enough to turn on the internal TTL level buffer, 
wasting further current as the buffer is no longer fully 
CMOS. 

With Vss disconnected (Figure 6b), there is no return path to 
^ the battery and the pin is pulled completely up to Vpo- The 
TTL buffer is switched off and no power is lost. 

1.3.2 isolation Techniques I — 5V Supply Only 

Figure 7 shows the isolation circuit suggested in the 
MM58274 data sheet. This circuit provides complete discon- 
nection where only the system -f- 5V is available for switch- 
ing control. 



FIGURE 7. 5V Isolation Circuit 


TR2 is the disconnecting device, which is controlled by TR3 
and its associated circuitry. TR3 is turned on by its bias 
chain R2, ZD1, R4 as the system supply rises up to 4.2V. 
TR3 and R3 then turn on TR2 to connect the clock to the 
system supply. D1 isolates the backup battery when the sys- 
tem supply is active. The 100 nF disk capacitors decouple 
the supply during R/W operations and should be included in 
any disconnection scheme. 

TR3 is necessary to prevent R3 and TR2 from leaking bat- 
tery current in the power down condition. The circuit without 
TR3 is shown in Figure 8 where TR2 has been replaced by 
equivalent diodes to clearly show the problem. The circuitry 



Rs = SYSTEM RESISTANCE 
WITH NO POWER 

APPLIED j IL/F 6737 9 

FIGURE 8. Current Leakage In Simplified 
Disconnection Schemes 

could be simplified by replacing TR3 with a Zener diode 
(Figure 9). There will be a small loss of current down through 
TR2 however, as the Zener will pass a small leakage current 
at below its ‘knee’ voltage. Thus the Zener should be 
selected for its low current capability. 



FIGURE 9. Alternative Supply Disconnection Scheme 
Sensing 5V (Decoupling Capacitors < 
Omitted for Clarity) 


Finally TR1 and R1 (Figure 7) are optional components 
which are only required when the interrupt output is used. If 
interrupts are left programmed when the power fails, the 
interrupt timer will still time-out setting the interrupt output. 
Since this is an active low pull-down transistor it effectively 
shorts directly across TR2, destroying the RTC isolation and 
discharging the battery into the rest of the system (Figure 
10). In order to prevent this from occurring, TR1 and R1 are 
added. 


2-204 





EQUIVALENT 
CIRCUIT FOR A 
CMOS DEVICE 0/P 


(PO\WER SUPPLY 
EQUIVALENT 
POWERED DOWN 
SOURCE 
RESISTANCE) 


ri./F/6737 n 


FIGURE 10. Battery Discharge Path via Unisolated 
Interrupt Output 


None of the disconnection components are at all critical, 
with general purpose transistors being completely adequate 
for the task. D1 should be a small-signal silicon or germa- 
nium diode. 

1.3.3 Isolation Techniques II — 

Negative Supply Switched 

Where a negative voltage supply is available (either regu- 
lated or unregulated) the circuit of Figure 11 may be used. 
This is similar in operation to its diode equivalent shown in 
Figure 12, where the voltage drops across the diodes pro- 
vide the correct potential to the clock. Figure 11 has the 
advantage, however that the clock power' is supplied from 
the ground line by transistor action, rather than via the resis- 
tor as in Figure 12. Less power is dissipated In the resistor 
as only transistor bias current need by drawn. 



FIGURE 11. Negative Voltage Driven Supply 

Disconnection Scheme (Decoupling 
Capacitors Omitted for Clarity) 



1.3.4 Other Methods 

There are many other possibilities for supply disconnection 
schemes, i.e., relay disconnection. When designing a dis- 
connection scheme, the performance must be analyzed 
both with the system power applied and with 
absent. Check for leakage paths and undue voltage drops 
and try to set up so that, disconnection and reconnection will 
take place as near to the backup voltage as possible. 

1.4 POWER FAIL PROTECTION 

One of the major causes of unreliability in RTC designs is 
due to inadequate power failure protection. As the system is 
powered up and down, the izP and surrounding logic can 
produce- numerous spurious signals, including spurious 
writes and illegal control signals (i.e., RD and WR both 
active together). 

Bipolar logic devices can produce spikes and glitches as the 
internal biasing switches off around 3V-3.5V, and the tran- 
sistors operate in their linear region for a short time. Any 
such spurious signals, if applied to the RTC, could cause 
the time (data to be corrupted. Systems using 74HC logic 
and CMOS processors are less stringent in their power fail- 
ure requirements as the devices tend to work right down to 
around 2V. Some form of write protection is still required, 
however. 

In order to protect the time data, the system must be physi- 
cally prevented from- writing to the clock when the power 
supply is not stable. The ideal situation is to ban Write 
access to the clock before the system -i- 5V starts to fail, and 
then keep the chip ‘locked-out’ until the power is restored 
and stabilized. This ideal access control signal is illustrated 
in Figure 13. 

Three methods of power fail protection are discussed, 
although there are also many other possibilities. 

1.4.1 Write Protect Switch 

By far the simplest and potentially the most hazard-free 
method is to use a switch on the WR control line to the clock 
(Figure 14). This is completely adequate, but requires the 
intervention of an operator to alter time data or program 
interrupts. 

Some thought must be given to ensuring that the operator 
cannot accidentally leave the VVR line switched in. This piay 
be achieved by the physical access method used (i.e., the 
machine is impossible to operate or switch off when in the 
time setting mode, because of the placement of access 
hatches, etc.) or with software. The switch state could be 
sensed by trying to alter the data in the Tens of Years 
counter or Interrupt register just prior to leaving the clock 
setting routine, and refusing to leave the routine until the 
WR switch has been opened. The switch condition should 
similarly be checked whenever the system is initialized or 
reset. 

The physical location of the switch should also be consid- 
ered for ease of accessibility. How easy the switch is to 
reach will depend on the system; i.e., in some cases a ‘tam- 
per proof clock may be required. 


FIGURE 12. Diode Equivalent Circuit of Figure 11. 



2-205 


AN-365 




AN-365 


SYSTEM SUPPLY 
UNDEFINED 


PRE-FAILURE. 
LOCKOUT PERIOD 


SYSTEM 5V 


MM58274 
WRITE ACCESS ENABLE 


SYSTEM SUPPLY 
UNDEFINED 



, . NORMAL STANDBY , 

\ 


I POST-FAILURE 
LOCKOUT PERIOD 

Ik 

MODE OPERATION 






FIGURE 13. RTC Access Lockout Definition 


Vbat 



FIGURE 14. Write Protection by Manually 
Switching WR 


1.4.2 5V Sensing 

The circuit of Figure 15 senses the system 5V supply and 
prevents access to the clock if the supply falls below 
4.2V-4.3V. This circuit should be used where only the sys- 
tem 5V is available for reference. The LM139 comparator 
and associated components sense the 5V supply and gen- 
erate the power fail signal (R Fail). The 74HC75 and compo- 
nents disconnect the WR line. 

R3 and ZDI provide a reference voltage of 2V-3V for the 
comparator. R4 and VR1 form a potential divider chain 
sensing the 5V line, and VR1 is adjusted to switch the com- 
parator output at 4.2V-4.3V. An alternative to VR1 would be 
to use a pair of close tolerance resistors ( ± 2%) with values 


selected to suit the Zener diode reference used. The combi- 
nation of R4, D3 and C2 provide an RC time cohstant to 
delay the comparator when sensing the return of 5V (to pro- 
vide the post-failure delay in Figure 13). The LM139 has an 
open-collector output which is held low when 5V is present 
and is switched off when 5V fails. This line is pulled high by 
R5 to flag power failure (R Fail). Since the comparatpr is a 
linear device drawing a bias current, it is powered by the 
system 5V supply to avoid consuming battery power. 

One 74HC75 package contains four latches, of which two 
are used. These are transparent latches controlled by the 
‘G’ input. With G high, the latch is transparent and the Q 
and Q outputs follow the Data input. When G is low, the 
state of Q and Q on the falling edge is latched. In this way, 
F2 prevents P. Fail from locking out the clock if there is a 
Write cycle in progress. F1 isolates the WR input on the 
clock when F2 passes the P. Fail signal. Cl, R2 and D1 do 
not slow the advent of P. Fail, but they cause a delay in the 
release of the function to mask any comparator noise or 
oscillation as the comparator switches off or on (i.e., during 
the undefined supply periods). 

D2, C3 and R6 smooth the comparator supply and help it to 
function effectively. The time constants of the RC networks 
should be selected to suit the power supply of the system 
that is used. Comparing the functioning of this circuit with 
the ideal case of Figure 13 shows that most of the conditions 
can be satisfied, except that there is no real pre-failure lock- 
out period. This cannot be achieved without some form of 
look ahead power failure. 


WR FROM 
CONTROL BUS 



FIGURE 15. Power Supply Failure Detection and Write Protection Circuitry 


2-206 



As an alternative to F1 a permanently powered 74HC4066 
analog switch could be used as the isolating component 
(Figure 16). The 74HC4066 does not require pull-up resistors 
on its inputs as there are no internal CMOS buffers inside 
this device which must be controlled. The resistor on the 
WR line is for the benefit of the 74HC75. 

Note that both of the devices mentioned must be perma- 
nently powered from the battery to be useful in this way. 
Unused gates in any such device must NOT be used in com- 
binational logic that is not permanently powered. All unused 
inputs should be tied to Vqq or Vss to. render them inactive. 


1.4.4 Switching Power Supplies 

Switching power supplies are available which generate 
power failure signals. This signal may be adequate for direct 
use as a R Fail line, but the manufacturer’s information 
should be consulted to determine the suitability of a given 
power unit. P. Fail must still be gated with the Write signal for 
the clock, regardless of the actual detection method 
employed. 



TUF/6737-17 


FIGURE 16. F1 Replaced by a 74HC4066 Analog Switch (Pull-Up Resistors Not Required on CS or RD Inputs) 


1.4.3 Supply Pre-Sense 

The same circuit of Figure 15 can be used with unregulated 
supplies or other voltage lines which will fail before the 5V 
line. To achieve this, point X is connected to the sensed volt- 
age instead of 5V, and the R4/VR1 ratio is adjusted to suit. 
The majbr benefit here is that advance warning of an 
impending 5V failure can be detected, allowing a pre-failure 
lockout signal to be generated. 

Less precision is required to sense the unregulated supply 
than the system 5V supply. Consequently less complex cir- 
cuitry can be used to do the detection and this is reflected in 
the circuit of Figure 17. Most 5V regulators will operate with 
an input voltage from 7V to 25V. Typically the input voltage is 
around 9V to 12V, giving some headroom. In Figure 17 this 
voltage is high enough to drive a current through the Zener 
diode and turn on transistor TR1, holding P. FAIL low. Rlim 
limits the Zener current. The Zener voltage is selected to 
switch off before the regulator fails, around 7.5V-8.5V 
depending on the time constant of the supply. With no cur- 
rent, TR1 switches off and Rp pulls P. Fail high. 

When power is re-applied the 5V supply will stabilize before 
the Zener switches on, removing P. Fail. To provide a longer 
post-failure lockout period Rum could be replaced with two 
resistors and a diode/capacitor delay as in Figure 15. 

Figure 18 is another extension of the same basic idea to pro- 
vide an advance interrupt signal to allow housekeeping 
before the RTC (and CMOS RAM) is loc ked o ut. The extra 
rectifying components D1 , Ct and Rt keep NMI off as long as 
input power is present. Time constant t 2 is selected to be at 
2-3 times faster than ri, the supply time constant. The inter- 
rupt signal is thus asserted before P. Fail. 



FIGURE 17. Power Fail Signal Generation from 
Unregulated Supplies 


1.4.5 Summary 

The general guidelines for power fail protection are: 

1. Physically Isolate the WR input to the clock. The /iP 
cannot be relied upon to logically operate the isolation 
mechanism. 

2. The clock should be isolated before the 5V power line 
starts to fail, and stay isolated until after it has re- 
established. 

3. Consider the action of the sensing and protection cir- 
cuitry if the supplies oscillate or if a momentary glitch 
occurs. 



2-207 


AN-365 



AN-365 



FIGURE 18. Power Fall Circuit with (iP Housekeeping Interrupt 


4. The Power Fail signal rnust be gated with Write strobes to 
the RTC. A foreshortened Write may also cause data cor- 
ruption. 

5. Logic components (and ICs in general) should be 
avoided when designing power failure schemes. Discrete 
components are far more predictable in their perform- 
ance when the power supplies are not well defined. The 
exception to this general rule is when using permanently 
powered HCMOS logic devices. They will function in a 
reliable manner down to 2V. 

System-powered logic devices cannot be relied on for power 
failure or Write isolation (not even CMOS). 

2.0 SOFTWARE 

2.1 DATA VALIDATION 

The MM58274 data sheet describes in some detail three dif- 
ferent methods of reading the clock and validating the real- 
time data. These techniques are reproduced in Appendix 
A-1. Rather than repeating the data sheet examples, this 
applications note examines the principles that lie behind the 
techniques suggested. 

The basic problem is that the /zP must somehow be synchro- 
nized with the changes in real-time in order to read valid 
data. This synchronization can either be done prior to read- 
ing the time data (pre-read), or after reading the data (post- 
read synchronization). 

2.1.1 Post-Read Synchronization 

Using the Data-Changed Flag (DCF) or the lowest order 
time register as outlined in the appendix: Time Reading 
using DCF and Time Reading with very slow Read cycles; 
are both examples of post-read synchronization. 

What this means is that the data is read out first, and then 
verified. This is achieved by defining a random time-slot, 
started by the first DCF or low order register read, and 
ended by the second such read. If DCF has not been set 
during the time-slot or the lowest order register has not 
changed, then no real-time change occurred during that 
time-slot. All real-time reads during the time-slot are thus 
guaranteed. 


2.1.2 Pre-Read Synchronization 

The Interrupt Timer technique uses pre-read synchroniza- 
tion. Once it has been initialized as described, the interrupt 
timer times out just after the real-time data has changed. 
Thus the fxP is guaranteed a full 100 ms period in which to 
read the time counters before the next change occurs. 

The interrupt timer has to be synchronized with the real- 
time counters because it is an independent unit which may 
be started and stopped at any time by the /^P. This software 
synchronization is achieved by using another pre-read tech- 
nique. The timer is set up and ready to go, but then the ^lP 
waits for DCF to occur before issuing the start command. 
The same technique could be used to actually read the 
time-data, but post-read synchronization is faster. 

2.2 INTERRUPT AS A DATA-CHANGED’ FLAG 

DCF is set every 100 ms when the 1/10ths of seconds 
counter is changed. When the time is only being read to the 
nearest second or minute, it would be useful to have a flag 
which is only set by a change in the lowest order counter 
being used. 

If the interrupt output from the clock is not being used, the 
timer can be used as a programmable data-changed flag. To 
achieve this, the timer is set up and started in exactly the 
same way as described for interrupt time reading (Appendix 
A-1). The interrupt output however, should be left uncon- 
nected. When reading the real-time data, the technique 
used is the same as for the normal Data-Changed Flag 
except that the Interrupt Flag is tested instead of DCF. 

Note that the lowest order real-time register which is to be 
read out should be used to initially synchronize the counter. 
The interrupt timer is started when the real-time counter 
value is seen to change. 

2.3 WRITING WITHOUT HALTING TIME-KEEPING 

For most purposes the RTC should be halted when the time 
is being set, especially if large numbers of counters are 


2-208 



being updated. The clock can also then be re-started in syn- 
chronism with an external time reference. If only a few 
counters are to be altered and the clock is already synchro- 
nized, then this can be done without stopping the clock. An 
example of a minor change which may be undertaken in this 
way is daylight savings (winter/summer change of hour). 

The problem to be overcome when writing in this way Is that 
the write strobe may coincide with a time change pulse. As 
the time counters are synchronous, the 100 ms clock pulse 
is fed to each one. Writing to one counter may cause a spu- 
rious carry to be generated from that counter, causing the 
next one up the chain to be incremented. 

Since a spurious carry will only affect the next counter if it 
coincides with a time update pulse, the solution is once 
again to synchronize clock access with the real-time 
change. The most suitable method for this is pre-read syn- 
chronization. In other words, the ixP must wait for DCF to be 
set before starting to write data to the clock, giving a guar- 
anteed 100 ms period for writing. 

2.4 THE CLOCK AS A WATCHDOG 

The interrupt timer can be used as a watchdog circuit, 
operating on a non-maskable interrupt input to the juP. The 
timer is sei up in either single or repeat interrupt mode for 
the watchdog period required: 0.1s, 0.5s or 1 second are 
probably the most useful times for this. Synchronization 
with real-time is not required. 

In the main program loop the writes to the clock, 
stopping and then re-starting the interrupt timer. The timer 
period selected will depend on how long the main loop takes 
to execute. As long as the fiP continues to execute the loop, 
no time-outs occur and no interrupts are generated. If the 
/iP fails for some reason to reset the timer, it eventually 
times out, generating the initializing interrupt to restore 
operations. 

2.5 THE JAPANESE CALENDAR 

Because the MM58274 has a programmable leap year 
counter, this allows the possibility of programming for the 
Japanese Showa calendar. The Japanese calendar counts 
years from the time that the present Japanese Emperor 
comes to power. Emperor Hirohito took office in 1926 
(Showa year 1), hence 1984 is Showa year 59. Since the 
days and months of Showa follow the Gregorian pattern, 
Showa year 59 is also a leap year. 

The normal law for the MM58274 is to program ‘the number 
of years since last leap year.’ This remains the same 
whether the clock is loaded with the Gregorian or Showa 
year. When software is used to calculate the leap year 
count value from the year, then the formula used must 
be modified. 

The formula for the Gregorian year is: 

Leap Year Value = [Gregorian Year/4] REMAINDER 
Whereas for the Showa year the formula is: 

Leap Year Value = [(Showa Year + 1)/4] REMAINDER 

Leap Year Value is the number from 0 to 3 which is written 
into the leap year counter, and is the REMAINDER of the 
integer calculations shown above. 


3-0 MISCELLANY 

3.1 CONNECTION TO NON Microbus^" SYSTEMS 

Adding the MM58274 to non Microbus processors is made 
fairly straightforward because of the flexibility of the control 
signal timing. Figure 19 shows two examples of logic to con- 
nect the clock to a 6502/6800 microprocessor bus. 

Figure 19a the RD and WR inputs are strobed, generating 
reasonably typical Microbus type control signals. In Fig- 
ure 19b, CS is used as the strobe signal. There is no particu- 
lar advantage to either circuit, they are just variations on the 
same theme. This circuit flexibility may be used to advan- 
tage to save SSI packages in the board design. 




b) 

FIGURE 19. 6800/6502 Bus Interface 
3.2 TEST MODE 

Test Mode is used by National Semiqonductor when the 
MM58274 is tested during manufacture. It enables the real- 
time counters to be clocked rapidly through their full count 
sequence. 

The MM58274 counters are clocked synchronously to sim- 
plify iiP access, with ripple carry signals from each counter 
to the next. In Test Mode some of these carries are inter- 
cepted and permanently asserted causing the counters to 
count each clock pulse. The prescaler is also bypassed so 
that the counters count every clock applied to the Osc 
In pin. The Test Mode counter connection is shown in 
Figure 20. 

If Test Mode is to be used for incoming inspection or device 
verification, then the clock waveform of Figure 21 should be 
applied to the oscillator input (Osc In, pin 15). The MM58274 
uses semi-dynamic flip-flops in the counters which are only 
fully static when the oscillator input is high. Thus Figure 21 
shows that the oscillator waveform is normally high, pulsing 
low to clock the real-time counters. The time data in the 
counters changes on the rising edge of Osc In. 


2-209 


AN-365 




AN-365 



XTAL 

IN 

XTAL 

OUT 


INT 



FIGURE 20. Test Mode Interconnection Diagram of Internal Counter Stages 


10 ,iS < tw < 35 (Vdd = 2V-5.5V) 


ViH > TSVo Vdd 



1 1 


OSC IN 1 

(PIN 15) 1 

1 

r:" 

TL'F/6737-23 


V|L < 250/0 Vdd 



FIGURE 21. Oscillator Waveform for Counter Clocking in Test Mode 


The pulse width limits for reliable clocking are shown on the 
diagram. When running with a 32 kHz crystal, the normal 
pulse width is 15.26 fis. With no forcing input, the oscillator 
will self bias to around 2.5V (V^d = 5V). While a few hun- 
dred mV swing above and below this level is sufficient to 
drive the oscillator, for guaranteed test clocking the input 
should swing between Vih > 75% Vqq and V|l< 25% Vdq. 

3.3 TEST MODE AND OSCILLATOR SETTING 

When Test Mode is used to set the oscillator frequency, the 
interrupt timer must be disabled (interrupt register pro- 
grammed with all Os) for the oscillator frequency to appear 
on the interrupt output. No test equipment should be con- 
nected directly to either oscillator pin, as the added loading 
will alter the characteristics of the oscillator making precise 
tuning impossible. 

Note that oscillator frequency will vary slightly as the supply 
varies between operating and standby voltages. Typically 
this variation will be around ±6 seconds per month 
(VsTANDBY = 2.4V), slowing at standby voltage. When the 
clock will spend the greater part of its working life in standby 
mode, it may prove worthwhile to correct for this in the tun- 
ing. This can be done by tuning at standby voltage (by writ- 


ing the RTC into test mode, then disconnecting it from the 
system to tune on battery backup). Alternatively, the clock 
can be slightly overtuned at operational voltage, tuning to 
32.7681 kHz. 

In a similar way, where the RTC spends equal amounts of 
time in both operational and standby modes (i.e., powered 
by day, standby at night), the oscillator may be tuned some- 
where between the two conditions. Following these tuning 
suggestions will not eliminate time-keeping errors, but they 
will help in minimizing them. 

Time-keeping accuracy cannot be exactly specified. It 
depends on the quality of the components used in the oscil- 
lator circuit and their physical layout, also the stability of the 
supply voltage, the variations in ambient temperature, etc. 
With good components and a reasonably stable environ- 
ment however, time-keeping accuracy to within 4 seconds/ 
month can be achieved, although 8 seconds/mbnth is some- 
what more typical in practical systems. 

3.4 UPGRADING AN MM58174A SYSTEM WITH 
THE MM58274 

The MM58274 has the same pin-out as the MM58174A and 
can be used as a direct replacement, with certain reserva- 


2-210 








tions. The two devices are not quite the same in their exter- 
nal circuit appearances, and this is reflected in their 
applications circuits. In addition, the MM58274 is not soft- 
ware compatible with the MM58174A, requiring a change in 
the operating system to use the MM58274. 

Figure 22 shows the circuit diagram for the MM58174A sys- 
tem connection. There are two major differences between 
this and the MM58274 diagram (Figure 1); a) the oscillator 
circuit and b) the supply disconnection scheme. 


The change of pin of the tuning capacitor (from Osc Out to 
Osc In) is not critical. 

b) The Supply Disconnection Scheme 

The MM58174A uses mostly pull-down devices on its /iP 
inputs to pull the inputs to CMOS levels, and so the 5V 
power line is disconnected on th is deyice. The two excep- 
tions to this are the CS and WR inputs which have pull-up 
resistors to inactivate the internal write strobe. As Figure 5a 



FIGURE 22. MM58174A System Installation 


a) The Oscillator Circuit 

The MM58274 normally operates with an 18 pF-20 pF fixed 
loading capacitor as opposed to the 15 pF of the MM58174A. 
This is a reflection of the greater internal capacitance of the 
MM58174A, rather than any change in the characteristics 
of the oscillator itself. The MM58274 will operate using a 
15 pF capacitor, but the oscillator will probably need to be 
retrimmed. 

Operating with a 15 pF capacitor will make the oscillator 
more sensitive to changes in the environment, i.e,, tempera- 
ture, voltage, moisture, etc. This will result in lower accuracy 
in time-keeping. The oscillator is more prone to stopping at 
low voltage. Oscillation would normally be maintained down 
to 1.8V-1.9V (although not guaranteed): with a 15 pF load it 
may only oscillate down to 2.0\/-2.1 V. It is thus important to 
check the battery regularly and replace it before the RTC 
voltage falls below 2.2V. 

Where possible the 15 pF capacitor should be replaced by 
an 18 pF-20 pF capacitor (anywhere in the range 18 pF- 
20 pF is adequate), or a second 3 pF-5 pF capacitor may be 
added in parallel with the 15 pR* 

*When components have been soldered into the oscillator circuit, allow the 
circuit to cool to room temperature before attempting to retune the oscillator. 


shows, there is a leakage path through these pins, which in 
most MM58174A installations are individually isolated. 

The largest penalty in inserting an MM58274 into an 
MM58174A circuit is the battery current that is lost through 
the pull-up devices. This will increase the typical supply cur- 
rent from 4 fiA to 50-100 ^A and it is up to the individual user 
to decide whether or not this drain is tolerable in a particular 
application. 

The most important requirement is that the WR input should 
be electrically isolated or current leakage through pin inputs 
may force the inputs low enough to cause spurious writes to 
occur. Since it is already customary to isolate these inputs 
for the MM58174A, this may not be a problem. Where this 
has n ot be en done, either the circuit will have to be modified 
or the WR PCB track can be cut and a switch or some extra 
circutry added to allow isolation. 

Note that power fail disconnection and input isolation may 
be achieved using the same components. In Figure 22 the 
MM74HC4066 analog switch will do both jobs. 

The current drained by the input pull-ups may be minimized 
with some attention to the data/address driving devices. It is 



2-211 


AN-365 






AN-365 


( 


often possible to replace LSTTL devices with standard 7400 
series devices and reduce the leakage (at the cost of some 
increase in operating current). Many 7400 series device out- 
puts lack diodes in the right places to pass leakage cur- 
rents. LSTTL devices will, for the main part, have these 
diodes. CMOS devices will always have diodes to both 
power rails on inputs and outputs. , 

There is no hard and fast rule for this. Wherp devices from 
one manufacturer work, the same part from a different one 
may not. Some trial and error experimentation may prove 
worthwhile in selecting devices. 

3.5 WAIT STATE GENERATION FOR FAST /iPs 

Although the MM58274 has faster access times than the 
MM58174A, in many cases, the /tP will be too fast to directly 
access the RTC. Figure 23 shows a circuit which will pro- 


duce wait states of any length required to enable the RTC to 
be accessed, using the 74HC74 dual D-type flip-flop. 

The RTC ^ signal clocks up a logic 1 on the Q output of the 
first F/F, removing the Preset from all the other F/Fs and 
pulling the /^P WAIT line low, via the transistor. The other 
F/Fs 1 to n, form a shift register clocked by the 02 system 
clock. 

After n 02 clocks (where n is the number of flip-flops in the 
shift register) a logic 0 shifts out from the nth F/F, resetting 
the main flip-flop. The main F/F then presets the shift regis- 
ter and clears the WAIT signal, ready for the next CS edge to 
repeat the cycle. On power-up the delay generator will ini- 
tialize itself after a maximum of n system clocks have 
occur red so no reset signal is required. Some /iPs demand 
that a WAIT/READY input is synchronized with 02 of the sys- 
tem clock. This can readily be achieved by selecting the cor- 
rect 02 edge as the clock signal for the shift register chain. 


FLIP-FLOP - IVIM74HC74 D-TYPE LATCH 



TL/F/6737-P5 


FIGURE 23. Access Delay Generator (Clocked Wait State Generator) 



2-212 



APPENDIX A-1. READING VALID REAL-TIME DATA 
TIME READING USING DCF 

Using the Data-Changed Flag (DCF) technique supports 
microprocessors with block move facilities, as all the neces- 
sary time data may be read sequentially and then tested for 
validity as shown below. 

1) Read the control register, address 0: This is a dummy 
read to reset the data-changed flag (DCF) prior to reading 
the time registers. 

2) Read time registers: All desired time registers are read 
out in a block. 

3) Read the control register and test DCF: If DCF is still 
clear (logic 0), then no clock setting pulses have occurred 
since step 1. All time data is guaranteed good and time 
reading is complete. 

If DCF is set (logic 1), then a time change has occurred 
since step 1 and time data may not be consistent. Repeat 
steps 2 and 3 until DCF is clear. The control read of step 3 
will have reset DCF, automatically repeating the step 1 
action. 

TIME READING USING AN INTERRUPT 

In systems such as point-of-sale terminals and data loggers, 
time reading is usually only required on a random demand 
basis. Using the data-changed flag as outlined above is 
ideal for this type of system. Where the nP must respond to 
any change in real-time (e.g., industrial timers/process con- 
trollers, TV/VCR clocks or any system where real-time is 
displayed) then the interrupt timer may be for time reading. 
Software is used to synchronize the interrupt timer with the 
time changing as outlined below: 

1) Select the interrupt register (write 2 or 3 to ADDRO). 

2) Program for repeated interrupts of the desired time inter- 
val (see Table IIB in Appendix A-2): Do not start the timer 
yet 

3) Read control register ADO: This is a dummy read to reset 
the data-changed flag. 


4) Read control register ADO repeatedly until data-changed 
flag is set. 

5) Write 0 or 2 to control register. Interrupt timing 
commences. 

When Interrupt occurs, read out all required time data. 
There is no need to test DCF as the interrupt ‘pre- 
synchronizes’ the time reading already. The interrupt flag is 
automatically reset by reading from ADDRO to test it. In 
repeat interrupt mode, the timer continues to run with no 
further intervention necessary. 

TIME READING WITH VERY SLOW READ CYCLES 

If a system takes longer than 100 ms to complete reading of 
all the necessary time registers (e.g., when CMOS proces- 
sors are used or where high level interpreted language rou- 
tines are used) then the data-changed flag will always be set 
when tested and is of no value. In this case, the time regis- 
ters themselves must be tested to ensure data accuracy. 

The technique below will detect both time changing 
between read strobes (i.e., between reading tens of minutes 
and units of hours) and also time changing during read, 
which can produce invalid data. 

1 ) Read and store the value of the lowest order time register 
required. 

2) Read out all the time registers required. The registers 
may be read out in any order, simplifying software 
requirements. 

3) Re-read the lowest order register and compare it with the 
value stored previously in step 1. If it is still the same, 
then all time data is good. If it has changed, then store 
the new value and go back to step 2. 

In general, the rule is that the first and last reads must both 
be of the lowest order time register. These two values can 
then be compared to ensure that no change has occurred. 
This technique works because for any higher order time reg- 
ister to change, all the lower order registers must also 
change. If the lowest order register does not change, then 
no other register has changed either. 



2-213 


AN-365 




AN-365 


APPENDIX A-2. FUNCTIONAL TRUTH TABLES FOR MM58274 

TABLE I. Address Decoding for Internal Registers ^ 


Register Selected 

Address Bits 

Access 

AD3 

AD2 

ADI 

ADO 

0 Control Register 

0 

0 

0 

0 

Split Read and Write 

1 Tenths of Secs 

0 

0 

0 

1 

Read Only 

2 Units Seconds 

0 

0 

1 

0 

R/W 

3 Tens Seconds 

0 

0 

1 

1 

R/W 

4 Units Minutes 

0 

1 

0 

0 

R/W 

5 Tens Minutes 

0 

1 

0 

1 

R/W 

6 Units Hours 

0 

1 

1 

0 

R/W 

7 Tens Hours 

0 

1' 

1 

1 

R/W 

8 Units Days 

1 

0 

0 

0 

R/W 

9 Tens Days 

1 

0 I 

0 

1 

R/W 

10 Units Months 

1 

0 

1 

0 

R/W 

11 Tens Months 

1 

0 i 

1 

1 

R/W 

12 Units Years 

1 

1 

0 

0 

R/W 

13 Tens Years 

1 

1 

0 

1 . 

R/W 

14 Day of Week 

1 

1 

1 

0 

R/W 

15 Clock Setting/Interrupt Registers 

1 

1 

1 

1 

R/W 


TABLE IIA. Clock Setting Register Layout 


Function 

1 Data Bits Used | 

Comments 

Access ^ 

DBS 

DB2 

DB1 

DBO 

Leap Year Counter 

X 

X 



0 indicates a Leap Year 

R/W 

AM/PM Indicator (12 Hour Mode) 



X 


0 = AM 1 = PM 

0 in 24 Hour Mode 

R/W 

12-24 Hour Select Bit 




X 

0 = 12 Hour Mode 

1 = 24 Hour Mode 

R/W 


TABLE ilB. Interrupt Control Register 


Function 

Comments 

Control Word 

DBS 

DB2 

DB1 

DBO 

No Interrupt 

Interrupt output cleared, Start/Stop bit set to 1. 

X 

0 

0 

0 

0.1 Second 


0/1 

0 

0 

1 

0.5 Second 


0/1 

0 

1 

0 

1 Second 

1 

0/1 

0 

1 

1 

5 Seconds 


0/1 

1 

0 

0 

10 Seconds 


0/1 

1 

0 

1 

30 Seconds 


0/1 

1 

1 

0 

60 Seconds 


-.0(1 J 

1 

1 

1 


Timing Accuracy: — 

Single Interrupt Mode (all time delays): , ± 1 ms 

Repeated Mode: ±1 ms on initial timeout, thereafter synchronous with first interrupt (i.e., timing errors do not 
accumulate). 

DB3 = 0 for Single Interrupt DBS = 1 for Repeated Interrupt 


TABLE III. The Control Register Layout 


Access (ADDRO) ' 

DBS 

DB2 

DB1 

DBO 

Read From: 

Data Changed Flag 

0 

0 

Interrupt Flag 

Write To: 

Test 

Clock 

Interrupt 

Interrupt 



Start/Stop 

Select 

Start/Stop 


0 = Normal 

0 = Clock Run 

0 = Clk. Set Reg. 

0 = Int. Run 


1 = Test Mode 

1 = Clock Stop 

1 = Int. Reg. 

1 = Int. Stop 


2-214 




An Introduction to 
and Comparison of 
54HCT/74HCT TTL 
Compatible CMOS Logic 


National Semiconductor 
Application Note 368 
Larry Wakeman 
March 1984 



The 54HC/74HC series of high speed CMOS logic is 
unique in that it has a sub-family of components, 
designated 54HCT/74HCT. Generally, when one en- 
counters a 54/74 series number, the following letters 
designate some speed and power performance, usually 
determined by the technology used. Of course, the letters 
HC designate high speed CMOS with the same pinouts 
and functions as 54LS/74LS series. The sub-family of HC, 
called HCT, is nearly identical to HC with the exception 
that its input levels are compatible with TTL logic levels. 

This simple difference can, however, lead to some confu- 
sion as to why HCT is needed; how HCT should be used; 
how it is implemented; when it should be used; and how its 
performance compares to HC or LS. This paper will at- 
tempt to answer these questions. 

It should also be noted that not all HCTs are the same. 
That is, HCTs from other vendors may have some charac- 
teristics that are different. Thus, when discussing general 
characteristics this paper will directly address National 
Semiconductor’s 54HCT/74HCT which is compatible with 
JEDEC standard 7. Other vendors’ ICs which also meet 
this standard will probably have similar characteristics. 

WHY DOES HCT EXIST? 

Ideally, when a designer sits down to design a low power 
high speed system, he would like to use 54HC/74HC, and 
CMOS LSI components. Unfortunately, due to system re- 
quirements he may have to use NMOS microprocessors 
and their NMOS or bipolar peripherals or bipolar logic 
(54S/74S, 54F/74F, 54ALS/74ALS, or 54AS/74AS) because 


either the specific function does not exist in CMOS or the 
CMOS device may not have adequate performance. Since 
the system designer still desires to use HC where possible, 
he will mix HC with these products. If these devices are 
specified to be TTL compatible, incompatibilities may 
result at the interface between the TTL, NMOS, etc. and HC. 


More specifically, in the case of where a TTL or NMOS out- 
put may drive an HC input, a specification incompatibility 
results. Table I lists the output drive specifications of TTL 
compatible outputs with the input specifications of 
54HC/74HC. Notice that the output high level of a' TTL 
specified device will not be guaranteed to have a logic 
high output voltage level that will be guaranteed to be 
recognized as a valid logic high input level by HC. A TTL 
output will be equal to or greater than 2.4V, but an HCMOS 
input needs at least 3.15V. It should be noted that in an ac- 
tual application the TTL output will pull-up probably to 
about Vcc minus 2 diode voltages, and HC will accept 
voltages as low as 3V as a valid one level so that in almost 
all cases there is no problem driving HC with TTL. 

Even with the specified incompatibility, it is possible to 
improve the TTL-CMOS interface without using HCT. 
Figure 1 illustrates this solution. By merely tying a pull-up 
resistor from the TTL output to Vcc, this will force the out- 
put high voltage to go to Vcc- Thus, HC can be directly in- 
terfaced very easily to TTL. This works very well for 
systems with a few lines requiring pull-ups, but for many 
interfacing lines, HCT will be a better solution. 



FIGURE 1. Interfacing LS-TTL Outputs to Standard 
CMOS Inputs Using a Pull-Up Resistor 



2-215 


AN-368 





AN-368 


WHEN TO USE 54HCT/74HCT LOGIC 

The 54HCT/74HCT devices are primarily intended to be 
used to provide an easy method of interfacing between 
TTL compatible microprocessor and associated periph- 
erals and bipolar TTL logic to 54HC/74HC. There are 
essentially two application areas where a designer will 
want to perform this interface. 

1. The first case is illustrated in Figure 2. In this case the 
system is a TTL compatible microprocessor. This figure 
shows an NS16XXX (any NMOS /xP may be substituted) 
that is in a typical system and therefore must be inter- 
faced to 54HC/74HC. In this instance, the popular gate,- 
buffer, decoder, and flip-flop functions provided in the 
54HCT/74HCT sub-family can be used to interface the 
many lines that come from TTL compatible outputs. It is 
also easy to upgrade this configuration to an all CMOS 
system once the CMOS version of the microprocessor is 
available by replacing the HCT with HC. 

2. A second application Is, when in speed-critical situa- 
tions a faster logic element than HC, probably ALS or AS, 
must be used in a predominantly 54HC/74HC system, or a 
specific logic function unique to TTL is placed into an HC 
design. This situation is illustrated in Figure 3. In this 
case, pull-up resistors on an HC input may be sufficient, 
but if not, then an HCT can be used to provide the guaran- 
teed interface. 


TABLE I. Output Specifications for LS-TTL and NMOS LSI Compared to the Input 
Specifications for HCT and HC 

Note the specified incompatibility between the output levels HC input levels. 



LS Output 

NMOS Output 

HC Inputs 

HCT Input 


VoUT 

•out 

VoUT 

•out 

V,N 

•in 

VlN 

•in 

Output 

High 

2.7V 

400 fik 

2.4V 

400 /xA 

3.15V 

1 fiA 

2.0V 

1 ixA 

Input 

High 

Output 

Low 

0.5V 

8.0 mA 

0.4V 

2.0 mA 

0.9V ' 

1 fiA 

0.8V 

1 /xA 

Input 


Vcc = 4.5V 


TABLE li. 54HC/74HC and 54HCT/74HCT Output Specifications Compared to 
54LS/74LS TTL input Specifications and Showing Fanout 

Both HC and HCT output specifications are the same for the two sets of output types. 



HC Output 

HCT Output 

LS Inputs 


VoUT 

•out 

VoUT 

•out 

Vir^ 

•in 

Fanout 

Standard 

Output 

Output 

High 

3.7V 

4.0 mA 

3.7V 

4.0 mA 

2.0V 

40 ^A 

10 

Output 

Low 

0.4V 

4.0 mA 

,0.4V 

4.0 mA 

0.8V 

400 ^A 

Bus 

Output 

I 

Output 

High 

3.7V 

6.0 mA 

3.7V 

6.0 mA 

2.0V 

40 ^xA 

15 

Output 

Low 

0.4V 

6.0 mA 

0.4V 

6.0 mA 

0.8V 

400 fiA 


Vcc = 4.5V 


The input high logic level of HC is the only source of in- 
compatibility. 54HC/74HC can drive TTL easily and its in- 
put low level is TTL compatible. Again referring to Table I, 
the logic output of the TTL type device will be recognized 
to be a valid logic low (0) level, so there is no incompatibil- 
ity here. Table II shows that the specified output drive of 
HC Is capable of driving many LS-TTL inputs, so there is no 
incompatibility here either (although one should be aware 
of possible fanout restrictions similar to that encountered 
when designing with TTL). 

The question then arises: since only the input high level 
must be altered, why not design CMOS logic to be TTL 
compatible? 54HC/74HC was designed to optimize per- 
formance in all areas, and making a completely TTL 
compatible logic family would sacrifice significant per- 
formance. Most importantly, there is a large loss of AC 
noise immunity, and there are speed and/or die size 
penalties when trying to design for TTL Input levels. 

Thus, since it is obvious that there is a need to Interface 
with TTL and TTL compatible logic, yet optimum perform- 
ance would be sacrificed, a limited sub-family of HCT 
devices was created. It is completely TTL input compat- 
ible, which enables guaranteed direct connection of TTL 
outputs to its inputs. In addition, HCT still provides many 
of the other advantages of 54HC/74HC. 


2-216 





FIGURE 2. Applications Where a TTL Compatible 
NMOS Microprocessor is Interfaced to a CMOS 
System ' 



TL/F/6751-3 


FIGURE 3. A Conceptual Diagram Showing How HCT 
May Be Used to Interface a Faster ALS Part or Some 
Unique TTL Function in a CMOS System 


The functions chosen for implementation in 54HCT/74HCT 
were chosen to avoid the undesirable situation where the 
designer is forced to add in an extra gate solely forthe inter- 
face. A variety of HCT functions are provided to not only in- 
terface to HC, but to perform the desired logic function at 
the same time. 

Although not the primary intention, a third use for 54HCT/ 
74HCT is as a direct plug-in replacement for 54LS/74LS 
logic in already designed systems. If HCT is used to replace 
LS, power consumption can be greatly reduced, usually by 
a factor of 5 or so. This lower power consumption, and 
hence less heat dissipation, has the added advantage of in- 
creasing system reliability (in addition to the greater 
reliability of 54HC/74HC and 54HCT/74HCT). This is ex- 
tremely useful in power-critical designs and may even offer 
the advantage of reduced power supply costs. 

One note of caution: when plug-in replacing HCT for TTL, 
54HCT/74HCT(as well as 54HC/74HC) does not have iden- 
tical propagation delays to LS. Minor differences will oc- 
cur, as would between any two vendors’ LS products. To be 
safe, it is recommended that the designer verify that the 
performance of HCT is acceptable. 


PERFORMANCE COMPARISON: HCT vs HC LS-TTL 

To enable intelligent use of HCT in a design, both for the in- 
terface to NMOS or TTL and for TTL replacement applica- 
tions, it is useful to compare the various performance 
parameters of HCT to those of HC and LS-TTL. 

Input/Output Voltages and Currents 

Table III tabulates the input voltages for LS-TTL and 
LS-TTL compatible ICs, HCT, and HC. Since HCT was de- 
signed to have TTL compatible inputs, its input voltage 
levels are the same. However, the input currents for HCT 
are the same as HC. This is an advantage over LS-TTL, 
since there are no fanout restrictions when driving into 
HCT as there are when driving into LS. 

Referring to Table 11, the output voltage and current 
specifications for HC and HCT gates are shown. As can be 
seen, the output specifications of HCT are identical to HC. 
This was chosen since the primary purpose of HCT is to 
drive into HC as the interface from other logic. 



2-217 


AN-368 






898NV 


There are some differences as to how LS-TTL, ALS-TTL 
and AS-TTL outputs are specified when compared to HCT 
(or HC), as shown in Table IV. The military parts are ^asy to 
compare. HC/HCT has the same Iql as LS and much 
greater Iqh- At the commercial temperature range a direct 
comparison is difficult. LS has a higher output current, but 
also a higher output voltage and narrow operating temper- 
ature range. Taking these into account, the output driveof 
74HC/HCT is roughly the same as LS. 

In the HC family, there is a higher output drive specified for 
bus compatible devices. Again, HCT is identical. As can 
be seen back in Table II, the bus drive capability of both HC 
and HCT are identical, and both source and sink currents 
are symmetrical. This increased drive over standard de- 
vices provides better delay times when they are used in 
high load capacitance bus organized CMOS systems. 

Both HC and HCT also have another voltage/current 
specification which is applicable to CMOS systems. This 
is the no load output voltage. In CMOS systems, usually 
the DC output drive for a device need not be greater than 
several fiA since all CMOS inputs are very high impedance. 
For this reason, there is a 20 /xA output voltage specifica- 
tion which says that 54HC/74HC and 54HCT/74HCT will 
pull to within 100 mV of the supplies. 

NOISE MARGIN TRADEOFFS WITH HCT 

The nominal trip point voltage for an HCT device has been 
designed to be around 1 .4V, as compared to the 2.5V for a 
standard HC device. This will degrade the ground level 
noise margin for HCT by almost a volt. HC, on the other 
hand, has its trip point set to offer optimal noise margin 
for both Vcc and ground. 


TABLE III. A Comparison of Input Specifications for 54LS/74LS, NMOS-LSI, 54HC/74HC, 
and 54HCT/74HCT 


The HCT specifications maintain the TTL compatible Input voltage requirements and the HC input 
currents. 



LS Inputs 

NMOS LSl Input 

HC Inputs 

HCT Input 

Vw 

l|N 

VoUT 

•out 

V,N 

■in 

V|N 

■in 

Input 

High 

2.0V 

40 /xA 

2.0V 

10 /xA 

3.15V 

1/xA 

2.0V 

1 /xA 

Input 

Low 

0.8V 

400 /xA 

0.8V 

10 /xA 

0.9V 

1 /xA 

0.8V 

1 /xA 


Vcc = 4.5V 


TABLE IV. This Compares the Output Drive of HC and HCT to LS for both the Military 
Temperature Range and the Commercial Temperature Range Devices at Rated Output Currents 



Military Temperature 

Commercial Temperature* 

HC/HCT Output 

LS Output 

HC/HCT Output 

LS Output 

VoUT 

■out 

VoUT 

■out 

VoUT 

■out 

VoUT 

■out 

Input 

High 

3.7V 

4.0 mA 

2.5V 

400 /xA 

' 3.84V 

4.0 mA 

2.7V 

400 /xA 

Input 

Low 

0.4V 

4.0 mA 

0.4V 

4.0 mA 

0.33V 

4.0 mA 

0.5V 

8.0 mA 


Vcc = 4.5V 

*The commercial temperature range for HC/HCT is - 40‘’C to + BS^C, but for LS it is 0°C to 70“C. 


This may be a minor point since normally HCT is mixed 
with TTL and in this case the worst-case system noise 
margin is defined by the TTL circuits. If the HCT is being 
driven only by HC and not LS, then the worst-case Vcc 
margin is determined by the HC devices. This is not a nor- 
mal- usage, but may occur if, for example, some spare HCT 
logic can be utilized by HC to save chip count. Figure 4 
graphs input noise margin for HC, HCT in an LS applica- 
tion and HCT being driven by HC. As one can see, the HC 
has a large Vcc and ground noise margin, the HCT inter- 
facing from LS has a rhargin equal to LS, and the HCT in- 
terfacing from HC has a skewed margin. 


5.0 



(a) (b) (c) 


IHIIIf = specified data sheet performance 
I I = actual device performance 

TL/F/6751-4 

FIGURE 4. Guaranteed and Typical Noise Margins for 
a) HC b) HCT in TTL System c) HCT in HC System 


2-218 




POWER CONSUMPTION OF HCT 

In normal HC applications, power consumption is essen- 
tially zero in the quiescent state but is proportional to 
operating frequency when operating. In LS, large quies- 
cent currents flow which overshadow (except at very high 
frequencies) other dynamic components. 54HCT/74HCT 
is a combination of these, depending on the application. 
Both quiescent and frequency-dependent power can be 
significant. 

Referring back to Figure 1, this figure shows an LS-TTL 
output driving an HCT input. To see how quiescent current 
is drawn, notice that it is possible to have valid TTL 
voltages of 2.7V and 0.4V (ignoring the pull-up resistor). 
With 0.4V on the HCT input, we find the input N-channel 
transistor OFF and the P-channel ON. Thus, the output of 
this stage is high. Also, since one of the P or N-channel 
transistors is OFF, no quiescent current flows. However, 
when, the HCT input is high, 2.7V, the N-channel is ON and 
the P channel is slightly ON. This will cause some current 
to flow through both the transistors, even in the static 
state. 

Thus in a TTL appication, HCT has the unusual character- 
istic that it will draw static current only when its inputs are 
driven by TTL (and TTL-like) outputs, and only when those 
outputs are high. Thus, to calculate total power, this 
quiescent power must be summed with the frequency-de- 
pendent component. 

When HCT is driven by HC, as it possibly might be, the HC 
outputs will have high and low levels of Vqc and ground; 
never statically turning on both transistors simultane- 
ously. Thus in this applicatioh, HCT will only dissipate 


frequency-dependent power, and Cpo calculations can be 
made to determine power (see National Semiconductor 
application note, AN-303). In the latter application, HCT 
will dissipate the same amount of power as HC; in the first 
TTL application, the power dissipated will be more since 
there is also a DC component. 

To show this, Figure 5 plots power versus frequency for an 
HCTOO being driven by HC, typical LS and worst-case LS. 
Notice that at the lower frequencies, the DC component 
for the TTL input is much greater; at higher frequencies, 
the two converge as the dynamic component becomes 
dominant. 

SPEED/PROPAGATION DELAY PERFORMANCE 

Of primary importance is the speed at which the com- 
ponents operate in a system. HCT was designed to have 
the same basic speeds as HC. This was accompished in 
spite of the fact that HCT requires the addition of a TTL in- 
put translator, which will add to internal propagation 
delays. A second concern in the design was to maintain 
the required speeds while minimizing the possible power 
consumption of the input stage when driven TTL high 
levels. 

These requirements dictated designing HCT on a slightly 
more advanced 3/x N-well process, as well as increasing 
the die to help compensate for speed loss. This process is 
slightly faster than the standard HC process, and this 
enables the HCT parts to have the same delays as their HC 
counterparts, while minimizing possible quiescent cur- 
rents. Figure 6 shows a comparison of 74HCT240 and 
74HC240 propagation delays, and they are identical. 




0 40 80 120 160 

LOAD CAPACITANCE (pF) 


TUF/6751 6 


FIGURES. Power Consumption of 74HCT00 Being 
Driven by a) Worst-Case TTL Levels b) Typical TTL Levels 
c) CMOS Levels 


FIGURE 6. Typical Propagation Delay vs Load for 
74HC240 and 74HCT240 Are Virtually the Same. Slight 
Differences Result from Different Design and Processing. 



2-219 


AN-368 




AN-368 


One interesting point is that HOT and HC speed specifica- 
tions are measured differently. One can compare the AC 
test waveforms in the HC databook and see that HC is 
measured with 0V-5V input waveforms and using 2.5V 
points on these waveforms. HCT, on the other hand, is 
tested like LS-TTL. HCT’s input waveforms are 0V-3V and 
timing is measured using the 1.3V on both the input and 
the output waveforms. 

The different test conditions for HCT result because HCT 
will be primarily usd in LS-TTL applications. If HCT Is used 
in HC systems, the actual speeds will be slightly different, 
but the differences will be small (<1 ns-2 ns). 

HC and HCT speeds are not identical to LS-TTL. Some 
delays will be faster and some slightly slower. This is due 
to inherent differences in designing with CMOS versus 
bipolar logic. For an average system implemented in HC or 
LS-TTL, the same overall performance will result. On an In- 
dividual part basis, some speeds will differ, so the 
designer should not blindly assume that HC or HCT will 
duplicate whatever a TTL IC does. 

CMOS LATCH-UP AND ELECTROSTATIC DISCHARGE 
OF 54HCT/74HCT 

These two phenomena are not strictly performance 
related in the same sense that speed or noise immunity 
are. Instead, latch-up and electrostatic discharge (ESD) 
immunity impact the ease of design, insusceptibility to 
spurious or transient signals causing a failure, and 
general reliability of 54HCT/74HCT. 

Latch-up is a phenomenon that is a traditional problem 
with older CMOS families; however, as with 54HC/74HC, 
latch-up has been eliminated in 54HCT/74HCT circuits. In 
older CMOS, it is caused by forward biasing any protec- 
tion diode on either an IC’s input or output. If enough cur- 
rent flovys through the diode (as low as 10 mA), then It is 
possible to trigger a parasitic SCR (four layer diode) within 
the IC that will cause the Vcc and ground pins to short out. 
Once shorted, the supply pins will remain so even after the 


trigger source Is removed, and can only be stopped by 
removing power. Latch-up is described in much more 
detail in National Semiconductor application note 
AN-339, and, in particular, a set of performance criteria is 
discussed. 

By a combination of process enhancements and some 
careful IC layout techniques, the latch-up condition can- 
not occur in 54HC/74HC or 54HCT/74HCT. If one attempts 
to cause latch-up by forcing current into the protection 
diodes, the IC will be overstressed in the same manner as 
overstressing a TTL circuit. 

ESD has also been a concern with CMOS ICs. Primarily for 
historical reasons, MOS devices have always been con- 
sidered to be sensitive to damage due to static dis- 
charges. However, process enhancements and careful in- 
put protection network design have actually improved 
54HC/74HC and 54HCT/74HCT immunity to where it is ac- 
tually betterthan bipolar logic. This includes 74ALS, 74LS, 
74S, 74AS and 74F. ESD is measured using a standard 
military 38510 ESD test circuit, which zaps the test device 
by discharging a 100 pF capacitor through a 1 .5 kfl resistor 
into the test circuit. ESD test data is shown in National 
Semiconductor reliability report, PR-11. 

CONCLUSION 

HCT is a unique sub-family designation of HC. It is in- 
tended primarily for TTL level to HC interfacing, although 
it Is far from restricted only to this application. HCT can be 
used as a pin-for-pin socket replacement of TTL, or can be 
mixed with HC logic. 

54HCT/74HCT has the same speeds as HC and LS, the 
same noise immunity as TTL and a significantly lower 
power consumption than LS-TTL, although It is slightly 
greater than HC. Additionally, by providing latch-up im- 
munity and low ESD sensitivity like the 54HC/74HC family, 
the overall system reliability and integrity is increased. All 
of these performance parameters enable HCT’s use in a 
wide range of applications. 


2-220 




The MM58348/342/341/248/ 
242/241 Directly Drive 
Vacuum Fluorescent (VF) 
Displays 


National Semiconductor 
Application Note 371 
David Stewart 
August 1984 



1. INTRODUCTION 

National has produced a family of high voltage display 
drivers which is specially designed for use with vacuum 
fluorescent (VF) displays. These circuits are fabricated 
using a standard metal gate CMOS process which has 
been extended to allow a maximum operating voltage of 
60V, thus enabling the design of bright multiplexed 
displays. In this way, the advantages of CMOS are re- 
tained (low power), while the range of applications for this 
technology is increased. Many of today’s high voltage 
MOS display drivers require the use of one external 
resistor per display output, and this leads to a con- 
siderable increase in component count and board area. 
National’s display drivers, however, incorporate an on- 
board pull-down resistor structure which removes these 
disadvantages. 

This application note is intended to demonstrate several 
ways in which these display drivers can be configured to 
drive and control a wide range of VF displays. Although 
particular attention will be given to one specific display, a 
32-character alphanumeric display, the design is pre- 
sented in such a way as to enable easy extrapolation to 
the system designer’s specific application. 

2. FUNCTIONAL DESCRIPTION 

There are six circuits in this new family of high voltage VF 
drivers and they can be sub-divided according to maxi- 
mum operating voltage, number of display outputs, data 
interfacing requirements and ability to be cascaded. Each 
of the three circuit configurations is available with maxi- 
mum operating voltages of 35V (MM583XX) or 60V 
(MM582XX). Due to the nature of the output stage required 
to attain high voltage operation of CMOS devices, the 
drive capabilities of the display output decrease as maxi- 
mum operating voltage increases. Therefore, to maintain 
the option of trading off display voltage against drive cur- 
rent, each circuit has a high voltage (reduced drive) version 
and a low voltage (high drive) version. The three circuit 
configurations can be identified by the number of display 
outputs they contain (e.g., 20, 32 or 35 outputs). In all 
cases, data is entered serially into a 5V internal CMOS 
shift register. This data is latched to the output either by 
an external enable control signal (MM58241/341/242/342) 
or automatically by a leading start bit in the data stream 
(MM58248/348). Figure 1 shows how the 6 device numbers 
correspond to the different circuit configurations and 
operating voltages. 


The MM58348/248 devices use a two control line data in- 
put format (data in and clock) which enables the 40-pin 
part to have 35 display outputs. To load data into the con- 
troller, a start bit precedes the 35 data bits. The start bit is 
a logical “1” clocked into the 1C by the first clock pulse. 
Next, 35 data bits are clocked into these parts. The start 
and data bits are shifted in on the rising edge of the clock. 
As the data is clocked into the 1C, the start bit is shifted 
down the 35-bit register. On the rising edge of the 36th 
clock pulse, data is transferred to the display register and 
the start bit is shifted into the control latch. On the 
negative edge of the clock, the shift register is cleared. 
The display register feeds the level shifters that translate 
5V CMOS levels to the 35V-60V required by the display. 
The MM58348/248 devices are not cascadable. Typically, 
these devices would perform the segment refresh drive in 
a multiplexed multi-digit system. A functional block dia- 
gram is shown in Figure 2. 

The MM58341 /241 /342/242 devices use a three control line 
data input format (data in, clock and enable) and have 
either 32 or 20 display outputs, as given by Figure 1. This 
configuration sacrifices some outputs to enable cascad- 
ing, enhance control signal flexibility, and provide bright- 
ness control. Here again, data is shifted into the shift reg- 
ister on the rising edge of clock, but no start bit is needed. 
Instead, the enable signal is taken high to input data to the 
chip. When the enable is taken low, the contents of the 
shift register are loaded into the display register. Again, 
the display register feeds the level translator and display 
driver outputs. 

Each of the MM58241/341 and MM58242/342 devices has 
a serial data output pin which is connected directly to the 
last stage’s output of the shift register. By connecting 
data out from one device to the data in pin of another 
device, and by holding each circuit’s enable constantly 
high, the display drivers can be cascaded. The result is a 
shift register with a variable number of bits, depending on 
the mix of circuits used. 

The MM58341/241/342/242 devices also have a blanking 
control Input. A logic high on this pin turns all outputs off, 
while still retaining the display data. If a logic “0” is then 
applied, the display data will return unchanged. Conse- 
quently, the brightness of the display is proportional to the 
duty cycle of this blank signal. A functional block diagram 
of these devices is shown in Figure 3. 



Operating Voltage 

35V 

60 V 

Number 

of 

Outputs 

20 

MM58342 

MM58242 

32 

MM58341 

MM58241 

35 

MM58348 

MM58248 


20 and 32 output drivers use envelope enable data format 
and may be cascaded. 

35 output (5x7 dot matrix) drivers use start bit data format. 


FIGURE 1. The Complete VF Display Driver Family 



2-221 


AN-371 




Block Diagrams 



FIGURE 2. MM58348/248 


OUTPUT OUTPUT 

32* /20t 1 



FIGURES. MM58341/241* and MM58342/242t 




2. FUNCTIONAL DESCRIPTION (Continued) 


Referring to the functional block diagrams shown in 
Figures 2 and 3, it is clear that all the internal logic is im- 
plemented in standard 5V CMOS. Such signals do not pos- 
sess sufficient drive for the high voltage output stage, so 
the data passes through a bank of 15V level shifters to the 
output section. A schematic of the output stage is shown 
in Figure 4. It can be seen that all these display drivers use 
a two-stage high voltage structure with active pull-up tran- 
sistors and passive pull-down resistors to the display volt- 
age. Because resistor pull-downs are used, it is the output 
switching “off” time which is critical for the system 
design, and this is typically 20 ^s for a rail-to-rail voltage 
swing. 


LEVEL 

SHIFTER 

OUTPUT 



Vdd=5V±0.5V 


DISPLAY 

OUTPUT 


VoiS = -30V 
OR Vois = -55V 


TL/F/7394 4 


FIGURE 4. High Voltage Output Structure 


3. DESIGN CONSIDERATIONS 

3.1. The VF Display Configuration 

The operation of a VF display is merely an extension of the 
valve principle, i.e., it is a voltage controlled device. An AC 
waveform is applied across the filament of the display, 
and this excitation causes electrons to be emitted. If both 
the grid and the anode are at a high positive voltage with 
respect to the cathode, the electrons reach the anode 
area, which is coated with a fluorescent material. When 
bombarded by electrons, this material emits light, hence 
one segment of the display is turned on. 

This particular family of display drivers can drive a wide 
range of VF displays. The simplest case is where each dis- 
play segment can be directly driven by wiring each output 
to the display anode. This normally occurs on displays 
with a small number of digits and segments (e.g., 4 charac- 
ters of 7 segments) and this can be driven by cascading 
the drivers until sufficient data bits are available. This 
display configuration has the advantage of not requiring 
any refresh (which would be required if a multiplexed con- 
figuration were used) but has the disadvantage of needing 
one wire per segment. 

As the size of the display increases, the number of avail- 
able segments also rises, thus a multiplexing scheme 
which will reduce the number of display connections is 
desirable. This is normally achieved by hard wiring all the 
segments (anodes) of each digit together, then using the 
grids to select each digit in turn. The correct segment data 


can then be displayed. Using these techniques necessi- 
tates that the display be continually refreshed with each 
digit of data, even when that data has not changed. 

To see the advantage of multiplexing, if a 32 character 
5x7 dot matrix display is used, a total of 1 120 segments is 
available. For this reason, the display is multiplexed and 
has 32 grid inputs and 35 segment inputs. The required 
refreshing task must be accomplished without the detec- 
tion of flickering by the human eye, i.e., at a rate greater 
then 50 Hz. (Refresh timing is discussed later.) 

Given the aforementioned display pinout and control 
logic, it is desirable in multiplexed displays to use the 
MM58341 to control the display grids (digits) and one 
MM58348 to control the display anodes (segments). 

3.2. The Display-Driver interface 

When using the MM58XXX series, no buffering is required 
between the driver output pins and the VF display. It is 
necessary only that the driver charge and discharge the 
display in such a time that the refresh rate outlined in the 
previous section can be achieved. All the VF drivers have 
LSTTL compatible inputs, and, as the data source is 
generally a microprocessor, no special interface require- 
ments exist. 

3.3. The Microprocessor-Driver Interface 

Typically, the system utilizing these display drivers will 
have some sort of microprocessor or single chip computer 
controlling the display. Thus, this processor will control 
one or more of the display drivers. The drivers have rela- 
tively little intelligence, therefore the host processor will 
be in charge of updating the display drivers and generat- 
ing refresh timing if needed. The advantage of having mini- 
mal intelligence on the drivers themselves is flexibility. 
Virtually any display size or type'can be used with equal 
ease, from small 7-segment, to British flag types, to larger 
5 X 7, 7 X 9 or 5 X 12 displays. 

The drivers can be directly interfaced to the microcon- 
troller, COPS™4XX, or 80C48/9. This would normally be 
accomplished by connecting the driver’s data and clock 
lines to control ports on the microprocessor. The 
MM58248/348 series is capable of accepting clock rates 
up to 1 MHz, and the MM58241/341 800 kHz. This is far 
faster than the control port bit manipulation rates for 
these controllers and will ensure compatibility with most 
low end microprocessors. 1 MHz input clock rates will also 
ensure that the desired display refreshing rate is attained. 

In higher end systems using NSC800^^ or 6800 8-bit micro- 
processors, the 1 MHz clock rate, coupled with a 300 ns 
minimum pulse width, simplifies direct interfacing of 
these drivers to a/^P bus. In the simple case, some logic for 
address decoding would set aside an I/O port for com- 
munication to each driver, then several bits of the data bus 
could be gated to create the clock, data and enable 
signals. 



2-223 


AN-371 




AN-371 


4. TYPICAL DESIGN IMPLEMENTATION 

4.1. Simple Direct Drive Application 

Figure 5 illustrates a simple cascaded direct drive applica- 
tion where MM58241s are cascaded to drive a 7-segment 
(plus decimal point) display. The MM58241s were chosen 
because of the ease with which they can be cascaded. The 
MM58248S can also be used and provide a few more out- 
puts per package, but cannot be cascaded. 

In this application, the controlling n? need only update the 
display whenever the data changes. When updating the 
display, the data is assembled, enable is raised, and the 
data is clocked serially to the driver. Once all the data is 
loaded into the shift registers, the enable is taken low. This 
action updates the display. 


4.2. A 32-Digit 5x7 Dot Matrix Application 

In this application, the obvious choice is to implement 
some sort of multiplexing scheme to drive the display with 
fewer lines. This application usually requires that a dedi- 
cated controller be used to generate all the timing signals. 

General multiplex timing of a VF display is usually similar 
to LED multiplexing. First, the segment data for one char- 
acter is output to the display. Next, the digit strobe for that 
digit is raised, enabling the character. Then the digit 
strobe is brought low while the segment data is changed 
to the next character on, the display. The next character is 
enabled by raising the digit strobe. This action continues 
until each character is turned on sequentially. Figure 6 
shows the basic timing for a simple display. 


DIRECT DRIVE VF DISPLAY 



CLOCK 

SERIAL DATA CONTROLLER 

ENABLE and LOGIC 


TL/F/7394-5 


FIGURE 5. Typical Direct Drive System with 



DIGIT 4 I [ ^ 

DIGIT 5 I 


DIGIT N 


TL/F/7394 6 

FIGURE 6. Simplified Timing for Multiplexed VF Display 


2-224 










4.2. A 32-Digit 5x7 Dot Matrix Application (Continued) 

In this design, it is logical to use one MM58341 to control 
the display’s digits. As will be seen, this driver can be 
easily used to shift a single high level bit which will be 
used to sequentially enable each character. One MM58348 
can be used to drive the segments. A 5 x 7 matrix has 35 
segments, which is ideal for the MM58348. Therefore, this 
configuration has a total of 6 connecting lines to interface 
the microprocessor to the display drivers. The connection 
diagram is shown in Figure 7. Because both of the drivers 
accept data only when the clock is active, it would be pos- 
sible to couple both data lines together. However, 
although this saves one interface line, there is a dispropor- 
tionate increase in the software burden. 

The choice of which driver to use for segments and which 
for digits is dependent only on which configuration is the 
simplest to implement in hardware or software. The 
MM58241/242/248 devices are all equally capable of driv- 
ing the digits or segments of a display. 


4.3. Multiplexed Display Refresh Timing: The Controllers 

Considering first the digit driver (MM58341), it is clear that 
the digits must be enabled sequentially and that this proc- 
ess must be continuous, even when the display data has 
not changed. To this end, the data for the MM58341 is 
simply a one followed by 31 zeroes, where the one is 
shifted along the internal register. As each digit is en- 
abled, the corresponding segment data is displayed. To 
ensure that no ghosting effects are seen during the transi- 
tion between digits, the blank signal is activated for a 
short time before and after the segment data is changed. 
Figure 8 shows the microprocessor waveforms and the 
resultant display waveforms for the 32-character design. 
Thus, one can see how the blank is used to mask the dis- 
play while the digit enable signal goes low and the seg- 
ment data Is latched. 


32 CHARACTER 5x7 DOT MATRIX DISPLAY 



FIGURE 7a. Typical Architecture for Higher 
End System Utilizing Dedicated Display 


■ □ □ □ ■ 
□ □ □ □ ■ 

□ □BHD 

□ □HDD 

□ □ □ □ □ 
□ □HDD 


35 

SEGMENT 

LINES 


COMMON 
DIGIT LINE 


FIGURE 7b. Detail of Typical Dot Matrix Digit 


2-225 


AN-371 




AN-371 


4.3. Multiplexed Display Refresh Timing: Controllers (Continued) 


MM58241 

INPUTS 


IVIIVI58248 

INPUT 


MM58248 
SEGMENT OUTPUT 


MM58241 

OUTPUTS 

DIGIT 

DRIVERS 



Notel: Digit 32 “on”. 

Note 2: Inter-digit blanking. 

Note 3: Digit 1 "on”. 

Note 4: Digit 2 “on”. 

FIGURE 8. Microprocessor and Display Timing Waveforms 


In between digit strobes, the segments are updated. The 
first 34 bits of segment data are set up and then the blank 
signal is activated to disable all 32 digits. The 35th bit is 
clocked in, updating the segments. Then the digit driver is 
clocked, shifting the digit strobe bit one position in the 
register. The enable is then brought low, enabling the next 
digit. Finally, blank is deactivated and the data displayed. 
Also, once the digit enable bit has been entered by the first 
MM58341 clock pulse, only one additional clock is re- 
quired to enable each subsequent digit. 

During the blank time, the order in which the segments or 
the digits are updated is not critical since this occurs 
■ while the display is blank. The digit driver may be clocked 
first, or the segments could be changed first. 

The segment data must be latched to the MM58348 outputs 
immediately before the relevant digit is accessed, but also 
while the display is blanked. Because the MM58348 resets 
its internal shift register each time the data is latched, it can 
accept all but the final data bit while still displaying the 
previous digit, so the final clock and data bit can be loaded 
when the blank signal is high. 

In general then, the philosophy for driving this VF display 
is: 

a) Set up the start bit and the first 34 bits of the segment 
data within the internal shift register of the anode 
driver {MM58348). 


b) Blank the display (disable all digits). 

c) Clock the grid driver (MM58341) to enable the correct 
digit. 

d) Load the final segment data bit into the anode driver, 
thus latching all 35 data bits onto the outputs, [c) and d) 
may be reversed.] 

e) Remove blank signal (enables correct digit). 

f) Load first 34 segment bits of next digit while displaying 
this data. 

g) Repeat steps a) to f) for every digit in the display. 

Note that items a through g must be executed continu- 
ously, even when the data has not changed. 

4.4. Multiplexed Display Refresh Timing: 

Display Brightness 

The obvious goal of a multiplexed design is to reduce the 
driver/display interface while maintaining proper display 
brightness and legibility. Thus, the limits of multiplexed 
operation are partly defined by the display’s ability to ap- 
pear bright, even as the number of multiplexed digits in- 
creases. As the number of characters is increased, the 
“on” time of each character is reduced, hence its per- 
ceived brightness is diminished. Also, the refresh rate 
needed by the display to prevent eye fatigue and flicker 
and th’e speed at which the controllers can update the 
display determine the limits of multiplexing. 


2-226 




4.4. Multiplexed Display Refresh Timing: 

Display Brightness (Continued) 

The refresh rate of the display is defined as the frequency 
at which each digit is enabled (i.e., the reciprocal of the 
time taken to display all digits). It is generally accepted 
that in order to avoid visible flickering, a refresh rate in ex- 
cess of 50 Hz is required. Typically, VF manufacturers 
recommend 100 Hz-200 Hz. Some sample calculations 
follow and assume a refresh rate of 100 Hz. Therefore, the 
time given to display all digits is 1/(100 Hz) = 10 ms, and is 
10 ms/(number of digits) for any one digit. For this ex- 
ample, 10 ms/32 = 312.5 [is. This is defined as the total 
digit multiplex time and will be made up of a digit “on” 
time and an inter-digit blanking time. The inter-digit blank- 
ing is required to prevent display ghosting when digit in- 
formation changes. 

In general, then, the total digit time (to) is the inverse of the 
refresh rate (fr) divided by the number of digits in the 
display (nd), i.e., 

t0 = i/(fr X nd) seconds. 

Since each digit time is composed of the “on” time, tooN. 
and the blanking time, tooFF- the total digit time is: 

to = tooN + tooFF (sBconds). 

A useful measure of the brightness of a multiplexed display 
can be obtained by comparing it to the direct drive (100% 
brightness) case. In the direct drive application each digit is 
“on” permanently, while in the multiplexed mode each digit 
is “on” only for a portion of the time taken to refresh the 
display. Therefore, the measure of multiplexed brightness 
is given by the ratio of an individual digit “on” time to the 
total refresh time. Noting that the refresh time is a function 
of the total digit time (to) and the number of display digits 
(nd), a percentage figure for the brightness compared to the 
direct drive case can easily be calculated. 

percent muxed brightness = , . x 100 

tpxnd 

percent muxed brightness = — — — — x 100 

(tDON + tDOFF)nd 

Thus, regardless-of the display logic’s refresh speed, the 
display brightness will obviously depend on the amount of 
multiplexing and the amount of inter-digit blanking time. 
This is one constraint limiting the multiplexing scheme, 
and display manufacturers’ data sheets should be con- 
sulted to determine a display’s limits. This will, to a large 
degree, determine whether a design should use 32-digit 
multiplexing or perhaps two separate 16-digit multiplexed 
displays. 

There are also limitations on the refresh rate based on the 
speeds of the hardware. In this design, the “on” time has a 
minimum value given by the time required to load the start 
bit and the first 34 data bits of the MM58348/248, i.e., the 
time required for 35 clock pulses of the MM58348. The 
MM58348 has a maximum clock frequency of 1 MHz, so 
the minimum time for 35 clock pulses is 35/(1 MHz) = 35 /xs. 
The digit “off” time is constrained by the time required to 
clock the digit driver and to loa(;l the final segment data bit, 
or the time for the display outputs to switch off then on, 
whichever is greater. The MM58341 has a maximum clock 
frequency of 800 kHz, so the minimum digit “off” time due 
to driver limitations is related to 1/(800 kHz ) -f 1/(1 MHz) = 
2.25 /xs. The blanking signal must be active during this 
time. Also, though the display outputs take typically 20 (is 
to switch, the display itself limits the minimum digit “off” 
time and is actually 20 /xs. 


Thus, the minimum total digit time per digit is: 
to = 35 /xS -F 20 /xs = 55 /xs. 

At a refresh rate of 10 ms, 10 ms/55 /xs equals the 
theoretical maximum number of digits that can be multi- 
plexed, or about 180 35-segment characters. This is un- 
realizable since current display “on” times must be 
greater than 35 /xs, and total digit duty cycles (or percent 
brightness) must be much higher. 

percent brightness = - _ x 100 = 0.25%. 

^ ^ 55/xSXl80 

For the 32-digit case, the percent brightness is more 
realistic: 

percent brightness = x 100 = 2.9% 

u.j I ms X o2 

These times are the limits of the drivers. If the time re- 
quired to load them is limited by the speed of the control- 
ling processor, the update times are calculated from the 
clock rates of the controlling /xP. However, as one can see, 
the limitations are more likely due to the display. 

4.5. VF Display Brightness Control 

Generally, to control or vary the brightness of a display, 
one can either vary the display drive voltage or vary the 
“on” time duty cycle by applying a signal to the blanking 
control. The duty cycle of the blanking signal will deter- 
mine the brightness. This latter technique is preferred 
since more predictable behavior results. 

In the simple direct drive case the MM58241/341/242/342 
must be used. A periodic waveform is applied to the blank- 
ing pin. Its frequency should be greater than 100 Hz-200 Hz. 
As the duty cycle is varied, the percentage of time that the 
digits are “on” is changed and the perceived brightness 
changes. 

In a multiplexed application, the brightness can be altered 
by merely modifying the relative length of the inter-digit 
blanking signal. This is easily accomplished in the soft- 
ware of the controlling by adding a delay while the 
blanking signal is active and subtracting the same delay 
from the time the blanking signal is inactive. 

The relative brightness is the percentage of time that any 
one character is “on” divided by the sum of the character’s 
“on” and “off” times. The latter term was previously de- 
fined as the total digit time. Thus: 

relative brightness = tooN/to- 

Due to hardware refresh update speed limitations, 100% 
and 0% brightness cannot be achieved and also maintain 
proper refreshing, although 0% can be achieved just by 
stopping refresh and blanking continuously. (Note that 
this percentage Is relative to the theoretical minimum and 
maximum brightness for a given multiplexed display, not 
the brightness relative to a direct drive display as was 
done previously.) 

In the above 32-digit example, the maximum brightness is 
(assuming 10 ms refresh rate and 20 /xS minimum inter- 
digit blanking): 

max percent brightness = (0.29 ms/0.31 ms) x 100 
= 93.6%. 

The minimum brightness, assuming 35 /xS minimum “on” 
time is: 

min percent brightness = (0.035 ms/0.31 ms) x 100 
= 11.2%. 



2-227 


AN-371 




AN-371 


Clearly there is a large range of available display 
brightness levels which are easily software controllable 
by altering the duty cycle of the blanking signal. 

Again, the above analysis assumes that the microproc- 
essor unit is interfacing with^he display drivers at their 
maximum data rates. If this is not the case, some part of 
the brightness range will be lost. 

Refer to Appendix for general system considerations. 

5. THE SOFTWARE 

Having outlined the general method by which the data can 
be displayed, it now remains to demonstrate how this can 
be achieved at the microprocessor level. It was thought 
best to use a familiar microprocessor for this task, so the 
implementation will use a 6502 and 6522 VIA circuit. The 
procedure which will be described is merely one example 
of how these display drivers can be applied, and it is hoped 
that by concentrating on the arranging and loading of the 
data, a more general benefit will be gained. 

The application to be described here is that of an alpha- 
numeric display where characters are entered from a 



TL/F/7394-10 


FIGURE 9. General 1C Flowchart 


keyboard onto a VF display, feeding in from the left. The 
program will also accept control codes such as line feed, 
delete, etc. The general flowchart for this routine is shown 
in Figure 9. When the character is collected from the 
keyboard buffer it must first be established that it is a valid 
ASCII code; if not, it is ignored and the present data will 
continue to be displayed. The next thing to check is 
whether it is a control code. If it is a control code, the func- 
tion represented must be executed on the existing data 
and the resulting data displayed. Assuming the ASCII 
code is not identified as a control code, it must corre- 
spond to a display character, and hence will be entered at 
the start of the display data buffer. Following this, the 32 
characters denoted by the contents of the display data 
buffer are displayed, and after the last digit is enabled the 
keyboard buffer is checked for new data. As the display 
refresh rate far exceeds the speed of the human typist, 
each set of data is displayed several times before it 
changes. 

Looking at the routine for displaying the 32 digits in more 
detail, a flowchart can be drawn up, as shown in Figure 10. 



^ MAIN PROGRAM 

TL/F/7394 1 1 

FIGURE 10. Display Data Subroutine Flowchart 


2-228 




5. THE SOFTWARE (Continued) 


After first setting up and clearing the port lines and both 
the display drivers, a routine is performed for each of the 
32 display characters. The ASCII code is collected and 
decoded to reveal memory locations where the corre- 
sponding 35 segment bits are stored. The start bit and first 
34 data bits are loaded into the MM58348. Then the 
MM58341 blank signal is activated while the relevant digit 
is enabled and the final segment bit is loaded. After blank 
is removed, the next ASCII code is collected and decoded, 
etc. When the last digit has been loaded, control returns to 
the main program for the updating of the display data. 

The machine code routine for the setting up of each digit 
of display data is shown in Figure 11. The relevant ad- 
dresses'of ports and digit codes are included in Figure 12 
to make the program comprehensible. The address of the 
segment data is stored in locations 00E2 and 00E3, and it 
is assumed that this is updated outside the display 
subroutine. The ports can be addressed as 8-bit memory 
locations or as individual lines. When considered as in- 
dividual bits, the fifth address bit either sets or clears that 
bit, i.e., STA 0915 sets PA5 and 090B clears PB3. 

The segment data for each character is stored as 7 con- 
secutive memory locations, each containing 5 data bits. 


The contents of each location are loaded into port A via 
the accumulator, starting with the highest memory ad- 
dress. This is achieved by indexing the lowest memory 
address by the contents of the Y register (starting as 06) 
and decrementing this register as every 5 bits are loaded. 
The least significant bit of port A is used for the segment 
data (PAO) and the 5 data bits are loaded by storing the 
code to port A, logically shifting it to the right, and storing 
it to port A again. This procedure is repeated 5 times for 
each memory location. The code given in Figure 77 is for 
the brightest case, i.e., where the blank signal is disabled, 
as soon as the data has been latched to the display out- 
puts. Clearly, the brightness can be altered by delaying 
this action. 

The data is held in memory in the form of 7 locations of 5 
bits each. This format was chosen because each location 
can be equated to one row of the 5 x 7 dot matrix, where 
the lowest memory location corresponds to the bottom 
row. For example, if it is desired that a “5” be displayed in 
the form shown in Figure 12, then the 36-bit data stream is 
as demonstrated. Assuming that the data is stored at the 7 
locations starting at address 2120, then the location con- 
tents are as denoted in Figure 13. 


DISPLAY 

STA 0910 



STA 090B 

\ Enable low. 


STA 0918 



STA 0920 



STA 0908 



STA 0918 

\ Load 35th segment 


STA 0900 

\ 

Load start bit. 

STA 0908 

\ bit. 


LDY #06 

\ 

Load 30 segment 

STA 090C 

\ Blank low. 


JSR LOAD5 

\ 

bits, 5 at a time. 

RTS 

\ Ret. to main prog. 


LDA (1) E2 

\ 

Load lowest addr. LOAD5 

LDA (l),Y E2 

\ Load mem. contents. 


LDX #04 



LDX #05 

\ Count for 5 bits. 

LOOP1 

STA 0920 


LOOP2 

STA 0920 

\ Push data to port A. 


STA 0918 



STA 0918 

\ Segment clock high. 


STA 0908 



STA 0908 

\ Segment clock low. 


LSRA 



LSRA 

\ Shift seg. data 


DEX 



DEX 

\ and dec. bit count. 


BNE LOOP1 

\ 

Load 4 seg. bits. 

BNE LOOP2 



STA 091 B 

\ 

Enable high. 

DEY 

\ Set up address of 


STA 0919 



BNE LOAD5 

\ next 5 seg. bits. 


STA 0909 

\ 

Digit select clock. 

RTS 

\ Return to display 


STA 091 C 

\ 

Blank high. 


\ subroutine. 




FIGURE 11. Display Data Load Subroutine 

TL/F/7394 12 


Port A— Address 0920 Port B— Address 0921 


Port Bit 

Function 

Address 

PBO 

Clock 8 

09-8 

PB1 

Clock 1 

09-9 

PB2 

Data 1 

09-A 

PB3 

Enable 

09-B 

PB4 

Blank 

09-C 

PB5 

Not Used 

09-D 

PB6 

Not Used 

09-E 

PB7 

Not Used 

09-F 


Port Bit 

Function 

Address 

PAO 

Data 8 

09-0 

PA1 

Not Used 

09-1 

PA2 

Not Used 

09-2 

PA3 

Not Used 

09-3 

PA4 

Not Used 

09-4 

PA5 

Not Used 

09-5 

PA6 

Not Used 

09-6 

PA7 

Not Used 

09-7 


tl;f;7394.i3 

Lowest memory address giving location of segment 
display data: stored in locations 00E2 and 00E3. 


FIGURE 12. Port and Relevant Memory Addresses 



2-229 


AN-371 




AN-371 


5. THE SOFTWARE (Continued) 


Desired Data Stream 

01110000010000111110100001000011111 I 1 I 

start 

bit 

direction of data entry : ► 


Memory Contents (Assuming Lowest Address = 2120) 


row 7 
row 6 
row 5 
row 4 
row 3 
row 2 
row 1 


Address 

Contents 

2120 

OE 

2121 

11 

2122 

01 

2123 

IE 

2124 

10 

2125 

10 

2126 

IF 


Desired Dispiay Character (Numeric 5) 

row 1 
row 2 
row 3 
row 4 
row 5 
row 6 
row 7 


xxxxx 

X 

X 

xxxx; 

X 

X X 
XXX 


FIGURE 13. Example of Segment Data Arrangement 


6. CONCLUSIONS 


This design example is merely one of the many possible 
applications for the MM58348/341/248/241 family of high 
voltage display drivers. For other applications it should be 
noted that the other 2 circuits in this series, namely the 
MM58342 and the MM58242, can provide a much wider 
range of possible connections. For example, larger 
displays such as the 2-line by 40-digit 5x7 dot matrix for- 
mats can be driven with two MM58348s and two 
MM58342S cascaded to form a 40-bit shift register. 

The method by which the segment data Is shown to be 
stored and accessed in memory is convenient in the above 
example, although again it is only one of the many 
methods. An alternative using 5 locations of 7-segment 
data bits is possible, where the software would be faster 


but the data formatting more difficult. There are many 
trade-offs to be found with so versatile a series of circuits. 

The code used to demonstrate this example is that of the 
6502 microprocessor, and it would be a simple task to con- 
vert the instructions for another device (e.g.. National’s 
CMOS NSC800). The versatility of display formats avail- 
able is a major feature, and the fact that these display 
drivers are CMOS devices guarantees their low power con- 
sumption. In addition, the outputs incorporate Internal 
pull-down resistors which greatly reduce the external 
component count. This cuts the required board area; con- 
sequently a considerable saving in system cost can be 
made. 


2-230 




APPENDIX: SYSTEM CONSIDERATIONS FOR 
VF DISPLAY DRIVING 

The purpose of the following text is to show how a 
designer can make decisions on displays he can drive or 
ranges of brightness he can achieve with a given system. 
Alternatively, it can be used as a method of designing a 
system to meet a desired display specification. 

THE THEORY 

1. System Decisions 
System Constraints: 

a) Refresh rate (f^) 

b) Number of display digits (nd) 

c) Rate at which drivers are clocked by system (fcLK) 
Associated Parameters: 

a) Total time available to display all digits (t^) 

b) Total time allocated to each digit (tp) 

c) Total time each digit is on (tpoN) 

d) Total time each digit is off (tpoFF) 

e) Number of display segments (ns) 

f) Number of system clocks required to display one digit 
(ncoN) 

g) N umber of system clocks required to load segment bits 
(nc) 

h) Number of system clocks required to latch both seg- 
ment and digit data (ncopF) 

From the above definitions, the following equations can 
be stated: 

tr = 1/fr (seconds) 
tp =tr/nd = 1/(frX nd) (seconds) 
fooN =time to load segment bits for next digit 
= ns system clocks 
= ncoN system clocks 
= ncoN^fcLK (seconds) 

tDOFF = time to latch segment bits and to enable rele- 
vant digit 

= ncpFF system clocks 
= ncoFF/fcLK (seconds) 

Hence: 

fD = tDON + fDOFF 

= (nCoN^fcLK) + (nCoFF/fCLK) 

= (nCoN + nCoFFV^CLK 
= ric/fcLK (seconds) 

And: 

fcLK = nc/tp 

= nc X frX nd (Hertz) 

2. Brightness Variation Considerations 

The brightness of the display is proportional to the duty 
cycle of the blank signal, and the range of intensities 
available depends on the size of tpoN end ultimately the 
refresh rate, fr. 

Bd = brightness of the display 
= duty cycle of blank signal 
= fDON/tD 

In the above example, the least bright case is where the 
blank signal is low for only one system clock per digit. 
Bd(min) = 1/nc 


And the brightest case is where blank is low only for the 
time required to latch the segment data and enable’the 
digit. 

Bd (max) = (nc - ncoFF)/nc 
= 1 -(ncoFFVnc) 

The range of available brightness level, Br, is: 

Br = Bd (max)/Bd (min) 

= [(nc - ncoFF)/nc]/(1 /nc) 

= nc - ncoFF 

It should be noted that this is the minimum range of 
available brightness levels because tp was minimized to 
maximize fr. If the system clock were fast enough to allow 
the maximum refresh rate to be in excess of the desired fr, 
then tp could be increased from its minimum value. This 
would, in turn, produce a wider range of brightness levels. 

It should also be noted that most manufacturers quote a 
minimum duty cycle for each digit. The system designer 
should ensure that neither end of the brightness specifica- 
tion exceeds this value. 


THE APPLICATION 

For the purposes of doing some sample calculations us- 
ing the above theory, we will assume use of the system 
previously described, i.e., the driving of a 32-digit 5x7 dot 
matrix display by one MM58341 /241 and one MM58348/248. 

1. System Decisions 

The number of display digits is fixed, i.e., nd = 32 
(ncoN = 35 and ncoFF = 2, so nc = 37 system clocks). 
Assume system has a 125 kHz clock rate. 

Therefore, the resulting refresh rate is; 

‘ fr = fcLK/(ncxnd) 

= 125000/(37x32) 

= 105 Hz 

Also, the system clock rate needed for a given refresh rate 
can be calculated, e.g., f ^ = 200 Hz. 

fcLK = ncx frX nd ^ 

= 37x32x200 
= 237 kHz 

= approximately 250 kHz 

There are many other examples of how this theory can be 
used to evaluate the possibilities for VF systems. 

2'. Brightness Variation Considerations 

We can now calculate the range of brightness intensities 
available with the above system, i.e., where fpiK = 125 kHz, 
fr=105 Hz. 

Bd(min)=1/nc ^ 

= 1/37 

Bd (max) = 1 - (ncoFF/nc) 

= 1-(2/37) 

= 35/37 

Br = Bd (max)/Bd (min) 

= 35 

So the brightness can vary from its lowest value to its max- 
imum value, which is 35 times the minimum level. 

Also note that the minimum duty cycle for this display is 
given as 1 /40 (manufacturer’s specification), so there is no 
problem in this application. 



2-231 


AN-371 




AN-371 


Let us now take the example of driving the same display 
with a system where fcLK = 500 kHz, at a desired refresh 
rate of 200 Hz. 

no = fcLK'(fr X nd) 

= 500000/(200 X 32) 

= 78 system clocks 

ncoFF is 2 as before, and although we require only 35 
clocks to load the segment data, 
ncoN = ric - ncoFF 
= 78-2 

= 76 system clocks 

In general, the higher the system clock rate, the wider the 
brightness contjol range. 

Therefore, 

Bd (min) = 1/nc 
= 1/78 


But, remembering that Bd (min) must be less than the 
stated duty cycle (1/40): 

Bd(min) =2/78 
= 1/39 

Bd(max) =1-(ncoFF/nc) 

= 1-(2/78) 

= 76/78 
= 38/39 

Br = Bd (max)/Bd (min) 

= (38/39)/(1/39) 

= 38 


So, we can see that by manipulation of the system con- 
straints, a wider range of brightness levels can be at- 
tained, although this is ultimately limited by the stated 
duty cycle of the display. 


I 



2-232 




High-Speed-CMOS designs 
address noise and 
i/0 ievels 


- National Semidbnductor 
Application Note 375 
Larry Wakeman 
September 1 984 


To maximize the benefits of high-speed CMOS, you must cope 
with environmental interactions and component limitations. 
Especially important are system noise decoupling and 
both transient and steady-state level control. 


Designs using high-speed-CMOS logic, such as the 
MM54HC/74HC Series, can attain characteristics that mark 
improvements over LS-TTL designs. To optimize these 
characteristics, however, you must adopt proper design pro- 
cedures. This article deals with the ICs’ input-output and 
noise-immunity considerations. 

High-speed CMOS logic is essentially a digitai-IC family that 
combines TTL (bipolar) and CD4000 (CMOS) characteris- 
tics. Because of the family's high speed, you must be more 
aware of the requirements of fast systems than in the case 
of CD4000B logic. Although the 54HC/74HC IC’s CMOS 
construction results in noise immunity comparable to the 
CD4000 family, its high speed necessitates system-ground- 
ing and supply-decoding techniques normally used in LS- 
TTL system design. 

The following sections discuss general usage guidelines, 
system noise susceptibility and immunity, and the 54HC/ 
74HC logic’s power-supply-noise characteristics. Note that, 
unless specific exceptions are stated, the considerations 
discussed apply also to 54HCT/74HCT, HC’s TTL-compati- 
ble subset. 

FOLLOW BASIC GUIDELINES 

The basic rules for designing with 54HC/74HC circuits are 
similar to those that apply to 74LS, CD4000B and 54C/74C 
devices. First, under normal static operating conditions, the 
Input should not exceed Vcc or go below ground. In normal 
high-speed systems, transients and line ringing can cause 
inputs to violate this rule momentarily, forcing the ICs to. 
enter an SCR-latch-up mode. 

INPUT DIODE OR 

Vcc OUTPUT DIFFUSION Vcc 


Latch-up results if either the input- or output-protection di- 
odes are fonA/ard biased because of voltages above Vcc or 
below ground. As a result, the IC’s internal parasitic SCR 
shorts Vcc to ground Figure 1 shows the diodes in a CMOS 
IC, schematically (a) and in a simplified die cross section 
(b). 

Thanks to some processing refinements, SCR latch-up isn’t 
a problem with the MM54HC/74HC Series. There are, how- 
ever, limitations on the currents that the internal metalliza- 
tion and protection diodes can handle, so for high-level tran- 
sients (pulse widths less than 20 ms and Inputs above Vcc 
or below ground), you must limit the current of the IC’s Inter- 
nal diode to 20 mA rms, 100 mA peak. Usually, a simple 
resistor configured in series with the input suffices. 
Powering the device Is another Important design concern. 
Don’t power up Inputs before both Vcc 3od ground are con- 
(a) 



POLYSILICON 

RESISTOR 


INPUT DIODE OR 
OUTPUT DIFFUSION 



FIGURE 1. Essential but sometimes evil, the diodes in CMOS-logic ICs can be easily damage^ by excessive 
currents. Reversed supplies or large input or output currents can cause diode burnout. 


Published in EON Magazine 
©Copyright 1984 Cahners Publishing 


2-233 



AN-375 


nected, and don’t plug or unplug pc boards into or from 
powered connectors unless input currents are short lived or 
limited in the manner already described. Both conditions 
can forward bias input diodes, resulting in excessive diode 
currents. Again, Figure 1 shows these diodes and the possi- 
ble current paths. If these conditions are unavoidable, add 
external current limiting to prevent damage to 54HC/74HC 
circuits, or use special connectors that apply power before 
signals. Some family members (notably the HC4049/60) 
have modified input structures and can survive the applica- 
tion of power to the input before the supply. 

Floating inputs are a frequently overlooked problem. CMOS 
inputs have extremely high impedance and, if left open, can 
float to any voltage. This situation can result in logic-func- 
tion mishaps and unnecessary power consumption. More- 
over, open inputs are susceptible to electrostatic damage. 
You should thus tie unused inputs to Vcc or ground, either 
through a resistor or directly. 

Finally, for correct logic results you should use inputs with 
rise and fall times faster then 500 ns. Slower transition times 
can result in logic errors and oscillation. 

OBSERVE OUTPUT RULES 

You must observe certain usage rules for 54HC/74HC out- 
puts as well as for inputs. Output voltages shouldn’t exceed 
the supply voltage, and currents in the output diodes 
shouldn’t exceed 20 mA. Moreover, output rms drive cur- 
rents shouldn’t exceed 25 mA for 4 mA standard-output de- 
vices'or 35 mA for 6-mA devices. The die’s metal lines dic- 
tate this limitation. Violations can result in long-term deterio- 
ration. Much larger currents (greater than 100 mA peak) 
arising from capacitive-load charging and line driving are 
normal and pose no real problem. As a rule of thumb, don’t 
allow the output current’s rms value to exceed the device’s 
current rating. Unlike the inputs, unused outputs should be 
left floating to allow the output to switch without drawing any 
dc current. 

When testing a pc board. Its often necessary to short the 
output of one CMOS device to overdrive and force a given 
level on the input of the IC driven by this output. In other 
instances, you might need to short the' outputs on a one- 
time basis. You can do so without degrading the IC’s life if 
you follow a few rules. When bench testing 54HC/74HC 
devices, for example, you can short one output for several 
minutes without harm. In automatic testing, you can short as 
many as eight outputs for a 1-sec duration. Here again, the 
limitation Is Imposed by the metallization. 

POWER-SUPPLY CAVEATS 

Now that you’ve looked at Input and output signals, give 
some extra attention to power-supply considerations. For 
instance, supply levels affect the device’s logical operation. 
You should, for example, keep the supplies within the 2 to 
6V range for HC devices and the 4.5 to 5.5V range for HCT 
devices. Voltages as high as 7V or as low as OV won’t harm 
the ICs, but their performance isn’t guaranteed at these lev- 
els. However, HCs and HCTs (with the exception of one- 
shots and Schmitt triggers) can typically function with sup- 
plies as low as about 1 .4V. 

As with any IC, it’s crucial that you not reverse the supply 
voltages. Doing so will forward bias a substrate diode be- 
tween Vcc and ground {Figure 1), resulting in excessive cur- 
rents and damage to the IC. As with Inputs and outputs, 
don’t let Vcc or ground rms currents exceed 50 mA for 


(a) 

Vcc 

VOUT 
PF 

TL/F/8127-3 

(b) 




2V 


TL/F/8127-4 



TL/F/8127-5 

FIGURE 2. The reaction of 74HC00 gates (a) to noise 
spikes is clearly seen in these scope photos. The gate 
exhibits noise immunity of 2V or more (b). Furthermore, 
the immunity is equally good for positive- and negative- 
going noise spikes. 


2-234 



4 mA devices or 70 mA for 6 mA units. Again, transients 
pose no real problem as long as their rms values stay within 
the devices’ ratings. 

UNDERSTANDING NOISE 

What happens if the signals just discussed aren’t clean? In 
digital-logic systems, "noise” is defined as extraneous volt- 
age in the signal or supply paths. For CMOS, ECL or TTL 
devices, system noise that’s great enough can affect the 
logic’s integrity. CMOS-logic families such as the CD4000 
and 74C are highly immune to certain types of system noise. 
This immunity is due mainly to the nature of CMOS, but also 
to the fact that the devices’ slowness reduces self-induced 
supply noise and crosstalk and prevents the logic from re- 
sponding to short externally induced or radiated transients. 
However, in high-speed CMOS (which is about 10 times 
faster than CD4000 logic), crosstalk, induced supply noise 
and noise transients become factors. Higher speeds allow 
the device to respond more quickly to externally induced 
noise transients and accentuate the parasitic interconnec- 
tion inductances and capacitances that increase self-in- 
duced noise and crosstalk. 

Because HC-CMOS specifies input levels similar to those of 
CD4000 logic, its dc noise rejection is also superior to LS- 
TTL. And because high-speed CMOS has an output imped- 
ance one-tenth that of CD4000 devices, it’s less susceptible 
to noise currents coupled to its outputs. As a result, lower 
stray voltages are induced for a given amount of current 
coupling. 

To quantify these noise parameters, first define “noise im- 
munity”: a device’s ability to prevent noise on its input from 
being transferred to its output. More specifically, it’s the 
amount of voltage that can be applied to an input without 
causing the output to change state. For HC-CMOS, this im- 
munity is approximately 2V; in the worst case, it’s the maxi- 
mum input Low or High logic levels specified in the data 
sheet. 



TL/F/ai27-6 

FIGURE 4. Noise margins for HC-CMOS and an HCT- 

CMOS-TTL combination are illustrated by this graph. 

You can see that the all-CMOS system exhibits the 
higher noise immunity. 

Noise immunity is an important attribute, but noise margin 
proves more useful because it defines the amount of noise 
that a system can tolerate and still maintain correct logic 
operation. It’s defined as the difference between the output 
logic Low (or High) of one gate and the input logic Low (or 
High) of the gate the given device is driving. 

For example, in HC-CMOS using a 4.5V Vcc. typical output 
levels are ground and Vcc. and input thresholds are 
V|H = 3.15V and V|i_=0.9V. These figures yield noise mar- 
gins of approximately 1 300 mV (logic One) and 8^0 mV (log- 
ic Zero). LS’s noise immunity is 700 and 400 mV, respec- 
tively. Note that 54HC/74HC input levels are skewed slight- 
ly toward ground, so the ICs tolerate slightly more Vcc noise 
than ground noise. 


(a) (b) 




0 Q 



74HC74 

ViK — 

— 

CLK Q 


n 


(PRESET = CLEAR = Vcc) 



TL/F/8127-7 



TL/F/8127-8 


FIGURE 3. Exhibiting high clock-noise immunity, this 74HC74 flip flop 
(a) shows no change in output for noise spikes greater than 2V (b) 



2-235 


AN-375 




AN-375 


To illustrate noise margin and immunity, Figure 2 shows the 
output that results when you apply several types of simulat- 
ed noise to a 74HC00’s input. Typically, even 2V or more 
input noise produces little change in the output. Figure 3 
shows how noise affects a 74HC74’s clock input. Again, no 
logic errors occur with 2V or more clock noise. 
54HCT/74HCT ICs have an input buffer specially designed 
to yield TTL input levels of 0.8 and 2V, Their noise-immunity 
characteristics are therefore substantially different from 
those of 54HC/74HC devices. In evaluating these differ- 
ences, note two general applications for HCT logic; in a TTL 
or NMOS (eg, XMOS, HOMS) system; or in an all-CMOS, 
HC or HCT system. 

In the first case, the HCT inputs get driven by outputs that 
are essentially TTL and specify output levels of 0.4 and 2.4V 
(or 0.5 and 2.7V). In this situation, the specified noise mar- 
gin is similar to the TTL margin; 400 mV for a logic Zero and 
either 400 or 700 mV for a logic One. These values, shown 
in Figure 4, are significantly less than those of an all-HC 
system. 

Now examine the second case. When using HCT with HC, 
output logic levels are almost equal to power-supply levels. 
Therefore, HCT’s specified noise margin is approximately 
700 mV for a logic Zero and 2.4V for a logic One. At first 
glance, the high noise margin for Ones might seem strange, 
but this situation presents a tradeoff against the Zero-level 
margin. Compare the two gate-transfer functions in Figure 5; 
the HCT device has a logic trip point at 1 .4V, while the HC 
gate trips at 2.4V. Thus, HC’s typical performance is twice 
that of HCT for ground noise; for Vcc noise, HCT is about 
50% better. 

The conclusion? In a normal system (including all-CMOS 
systems), HC provides better noise immunity than HCT. The 
one case where HCT could prove more helpful is in systems 
that are designed with noiseless ground and dirty Vcc- Nat- 
urally, this design approach isn’t good. A second fact high- 
lighted by these transfer functions, HC is conservatively 
specified for its input and output logic levels, whereas HCT 
is specified more tightly. So even though data-sheet limits 
for HCT seem better, actual system performance indicates 
that HC provides better overall noise margins. 



HC HCT 

(DRIVEN BY 

HC OR HCT) TL/F/8127-9 

FIGURE 5. Comparing HC and HCT logic, this graph 
shows noise immunity of the respective families. HC 
wins for ground noise, HCT for Vcc noise. 

CONSIDER SYSTEM NOISE 

Now take a closer look at system noise, which you can 
group into several categories, depending on the source. The 
type of noise dictates the appropriate nolse-supression 
technique. 

• Power-supply Ice noise, generated in the power-supply 
line, comes from logic switching in CMOS circuits. , 

• Transmission-line reflections, unwanted ringing and over- 
shoot phenomena arise from signals propagating down 
improperly terminated transmission and signal lines. 

• Signal crosstalk Is caused by capacitive or Inductive cou- 
pling of extraneous voltages from one signal line to an- 
other or to the power-supply line. 

• Radiated noise, an RF phenomenon that originates with- 
in a high-speed-logic system, emits to other systems. It 
arises from the high-frequency energy emitted when log- 
ic toggles. This noise, not a major problem with regard to 
logic integrity, can interfere with other systems. 


Vcc 



FIGURE 6. This schematic shows the currents in a 74HC00 gate that result when applying a positive 
input step. Also shown are the internal parasitic and external load capacitances. 


2-236 







Power-supply spiking is perhaps the most important contrib- 
utor to system noise. When any element switches logic 
states, it generates a current spike that produces a voltage 
transient. If these transients become too large, they can 
cause logic errors because the supply-voltage drop upsets 
internal logic, or because a supply spike on one circuit’s 
output feeds an extraneous noise voltage into the next de- 
vice’s input. 

With CMOS logic in its quiescent state, essentially no cur- 
rent flows between Vqc and ground. But when an Internal 



(b) 



20 mV 


gate or an output buffer switches state, a momentary cur- 
rent flows from Vcc to ground. This current has two compo- 
nents: the current required to charge and discharge any 
stray or load capacitance, and the current that flows directly 
from Vcc to ground when the p- and n-channel transistors 
turn on momentarily during an input transition. 

Figure 6 shows the paths for these current components 
within a 74HC00 upon application of a positive step to the 
device’s input. Cpi, Cp 2 , and Cp 3 represent the internal par- 
asitic capacitances; Cl is the external load capacitance. Iji , 
\j 2 and It 3 correspond to the currents that flow through 
both the n- and p-channel transistors during switching. Icpi, 
Icp 2 and lcp 3 are the charging currents for the capacitances. 
The switching transient caused by an unloaded output 
changing state typically equals 20 mA peak. Figure 7b 
shows the current and voltage spikes resulting from switch- 
ing a single unloaded NAND gate. Figures 7c through (e) 
show the current spike’s increase due to the addition of 1 5-, 
50- and 100-pF loads. The large amount of ringing results 
from the test circuit’s transmission-line effects. 

This ringing occurs partly because the CMOS gate switches 
from a very high impedance to a very low one and back 


(c) 


5V 500 mV 100 ns 












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TL/F/8127-14 TL/F/8127-15 

FIGURE 7. The effects of capacitive ioads are seen in these photos; (b) through (e) show 
the spikes resulting with no ioad and with 15-, 50- and 100-pF loads, respectively. 

The ringing arises from the test circuit’s transmission-iine effects. 


2-237 


AN-375 




AN-375 


(a) 


(b) 


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5V 500 mV 100 ns 












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TL/F/8127-18 


TL/F/8127-16 

FIGURE 8. On>chip circuitry before a 74HC00’s output stage (a) generates little current spiking, 
as shown in the photo (b). In the test circuit, one input is switching (but not the output). 
Note the very small power-supply glitches provoked by the input-circuit transitions 


again. Note that, even for medium-size loads, load-capaci- 
tance current becomes a major current contributor, verified 
by the dramatic increase in current from the unloaded to the 
100-pF-load case. 

Although internal logic generates current spikes when 
switching, the bulk of a spike’s current comes from output- 
circuit transitions. Why? Because the outputs have the larg- 
est p- and n-channel currents and the greatest parasitic and 
load capacitances. Figure 8 shows the Ice current for a 
74HC00 gate with one input switching, the other at ground 
(thus, with no output transitions). 

The best way to reduce noise-voltage transients is to imple- 
ment good power-supply busing. You should maintain a low 
ac Impedance from each circuit’s Vcc to ground. In one 
model for a supply bus {Figure both Vcc and ground 
traces exhibit inductances, resistances and capacitances. 


To reduce voltage transients, keep the supply line’s parasit- 
ic inductances as low as possible by reducing trace lengths, 
using wide, traces, ground planes, strip-line or microstrip 
transmission-line techniques and by decoupling the supply 
with bypass capacitors. 

For effective supply decoupling, bypass capacitors must 
supply the charge required by the current spike for its dura- 
tion with minimal voltage change. You can determine a by- 
pass capacitor’s approximate value from the expression: 

Idt (SPIKE CURRENT) (SPIKE DURATION) 
BYPASS - jjv - (ALLOWABLE DROOP VOLTAGE) 

Consider this example: A typical MM54HC/74HC has an Ice 
transient of about 20 mA, lasting approximately 20 ns (ex- 
cluding ringing). If you allow 400-mV peak noise, the re- 
quired bypass capacitance Is about (20 mA)(20 ns)/0.4V = 1 
nF per output. 



TL/F/81 27-17 


FIGURE 9. This equivalent circuit for a power-supply bus emphasizes both the Vec’s and the ground’s series 
inductances.Try to minimize these inductances through careful circuit layout 


2-238 




CURRENT PROBE 
TO SCOPE (Icc) 



TL/F/8127-19 


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TL/F/81 27-23 

FIGURE 10. Demonstrating the importance of bypassing, photos (b) through (e) show power-supply transients 
that occur when a 74HC00 is decoupled with 1-, 4.7-, 10- and 100-nF capacitors, respectively 




AN-375 


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TL/F/81 27-25 

FIGURE 11. Showing results similar to those depicted in Figure 10, these photos show the effects of bypassing a 
74HC74 flip flop with capacitors of 1 (b) to 10 nF (d). You can see that the 10 nF bypass yields supply spiking 
approximately 40% lower than that of the 1-nF capacitor. 


In order to prevent additional voltage spiking, this local by- 
pass capacitor must exhibit low inductive reactance. You 
should therefore use high-frequency ceramic capacitors and 
place them very near the 1C to minimize wiring inductance. 
The approximate amount of tolerable inductance Is given 
by: 



(SPIKE VOLTAGE) (SPIKE RISE OR FALL TIME) 

(SPIKE CURRENT) 

For example, restricting the Inductive noise spike to 1 00 mV 
peak with 20 mA current and 4 ns rise time yields (0.4V)(4 
ns)/20 mA = 80 nH max. Note that, in addition to localized 
decoupling of very fast transients, you also need bulk de- 
coupling of spikes generated by the board’s ICs. To decou- 
ple, provide a high-value capacitor for smoothing long time 
periods. 


To show how decoupling affects supply noise in real-world 
situations. Figure 10 depicts the power-supply transients 
that result when you choose different values of decoupling 
capacitors. In this example, one gate of a 74HC00 toggles, 
and 1-, 4.7-, 10- and 100-nF capacitors have approximately 
10 cm of wiring between them and the supply. Figure 11 
presents similar results, obtained with the 74HC74 circuit. 
Note in both cases (although the unbypassed situation isn’t 
depicted) that a 1 nF capacitor greatly reduces the voltage 
transient. 

Based on empirical and theoretical considerations, you can 
determine a set of guidelines. These practical maxims serve 
only as a foundation for a system that should yield good 
results. Consequently, there’s some leeway in following 
them for particular designs. As a rule of thumb, it’s generally 
good design practice to restrict both Vcc and ground noise 
to less than 250 mV. 


2-240 





(a) 


(b) 




I -J 


TL/F/81 27-28 

FIGURE 12. Tailor bypassing to the system’s supply scheme. Circuit diagram (a) shows the method to 
use with local regulators; (b) shows the scheme to adopt with a centralized regulated supply. 

Use tantalum- or aluminum-electrolytic capacitors. 


Before presenting the guidelines, examine some compara- 
tive attributes of earlier CMOS, HC, HCT and LS-TTL devic- 
es. First, because of higher speeds and larger output cur- 
rents, the supply-bypassing requirements of HC devices are 
more rigorous than those of earlier metal-gate-CMOS ICs. 
Compared with those of LS-TTL, the requirements for 
HC/HCT are similar or a little more stringent, depending on 
the application. 

Furthermore, for random logic, 54HC/74HC and 
54LS/74LS are similar, but in bus-driving applications HC 
devices can produce larger spikes. Finally, HCT logic needs 
better grounding than HC logic. In fact, its design considera- 
tions closely follow those of LS-TTL. However, as with HC, 
HCT exhibits greater Vcc spiking in bus-driving applications. 
Now you’re ready for the guidelines: 

• Keep Vcc-bus routing short. When using double-sided or 
multilayer circuit boards, use strip-line, transmission-line 
or ground-plane techniques. 

• Keep ground lines short, and on pc boards make them as 
wide as possible, even if trace width varies. Use separate 
ground traces to supply high-current devices such as re- 
lay and transmission-line drivers. 

• In systems mixing linear and logic functions and where 
supply noise is critical to the analog components’ per- 
formance, provide separate supply buses or even sepa- 
rate supplies. 


• If you use local regulators, bypass their inputs with a tan- 
talum capacitor of at least 1 /xF {Figure 12a), and bypass 
their outputs with a 10- to 50-|aF tantalum- or alumium- 
electrolytic capacitor (b). 

• If the system uses a centralized regulated power supply, 
use a 10- to 20-/i,F tantalum-electrolytic capacitor or a 
50- to 1 00-/xF aluminum-electrolytic capacitor to decou- 
ple the Vcc bus connected to the circuit board {Figure 
12b). 

• Provide localized decoupling.. For random logic, a rule of 
thumb dictates approximately 10 nF (spaced within 12 
cm) per every two to five packages, and 1 00 nF for every 
10 packages. You can group these capacitances, but it’s 
more effective to distribute them among the ICs. If the 
design has a fair amount of synchronous logic with out- 
puts that tend to switch simultaneously, additional decou- 
pling might be advisable. Octal flip flops and buffers in 
bus-oriented circuits might also require more decoupling. 
Note that wire-wrapped circuits can require more decou- 
pling than ground-plane or multilayer pc boards. 

• For circuits that drive transmission lines or large capaci- 
tive loads (jxP buses, for example), use a 10 nF ceramic 
capacitor close to the devices’ supply pins.' 

• Finally, terminate transmission-line grounds near the 
drivers. 


2-241 


AN-375 





AN-376 


Logic-System Design 
Techniques Reduce 
Switching-CMOS Power 


National Semiconductor 
Application Note 376 
Larry Wakeman 
October 1 984 



By adopting certain techniques in the design of your CMOS-based logic system, 
you can effect dramatic reductions in the transitional power these 
zero-qUiescent-current devices consume when switching. 


This article describes ways to reduce the power consump- 
tion in logic designs using high-speed CMOS ICs, The 
MM54HC/74HC logic family has near-zero power dissipa- 
tion when in the quiescent mode. Its only substantial power 
drain arises from dynamic switching currents. Traditional 
TTL and NMOS systems do not share this low-power fea- 
ture, requiring instead that you reduce power by selecting 
low-power ICs and external components. 

The CMOS device is inherently efficient, but you can greatly 
enhance system efficiency by designing around the follow- 
ing guidelines: 

• minimizing effective system operating frequency; 

• minimizing static dc-current paths (eg, in pull-up or -down 
resistors); 

• putting the logic to sleep (by removing the clock); 

• capitalizing on power-down situations. 

Total system power dissipation is the sum of two compo- 
nents; static (or quiescent) and dynamic power. LS TTL sys- 
tems consume such a great amount of quiescent power that 
the dynamic component pales into insignificance. When us- 
ing 54HC/74HC logic in power-critical applications, howev- 
er, you must consider both components. The following sec- 
tions describe how to determine system power by using HC 
devices’ power-dissipation-capacitance (Cpp) specs. The 
text also discusses a few power-reduction philosophies and 
some of the differences in consumption for 54HCT/74HCT 
TTL-compatible CMOS logic. Because system power is sim- 
ply total Ice times the supply voltage, the calculations treat 
power and current interchangeably. 

Calculating the quiescent power is just as easy — ^the sum of 
the dc currents times the supply voltage. Thus, total system 
quiescent power is 

PsYSTEM = (lcci + >002 + • • • tcCn) Vec- ( 1 ) 


The currents in this expression are caused by pull-up and 
load resistors and TTL, NMOS and linear circuits in the sys- 
tem. If it’s appreciable — although unlikely — you can include 
the very small quiescent Ice MM54HC/74HC devices. 
Generally, the worst-case Ice values in the CMOS ICs’ data 
sheets are very conservative. Typical values range from ten 
to 1 00 times less than the limits; moreover, it’s almost sta- 
tistically impossible for a system to contain all worst-case 
devices. 

As pointed out earlier, the major contributors to CMOS ICs’ 
power dissipation are dynamic switching currents. Figure 1 
is a schematic diagram of one 74HC00 NAND gate, and It 
shows the dynamic currents that result from switching one 
input Low to High. When the 1C is not switching, there’s no 
dc-current path from Vec to ground except for leakage. This 
is because whenever an n-channel device is On, its, comple- 
mentary p-channel partner is Off. 

CMOS power consumption is caused by the transient cur- 
rents that charge and discharge internal and external ca- 
pacitances during logic transitions. As frequency increases, 
these currents naturally increase. You can’t measure these 
currents or their associated capacitances individually, but 
you can measure the total current. You can equate this total 
current to a power-dissipation capacitance (Cpo) as follows: 

Icc = (CPD + CL)(Vcc)(fic). (2) 

where Icc is the supply current, Vec is the supply voltage, 
flC is the input toggle rate and Cl is the toggled load capaci- 
tance. Referring again to Figure /, the load current II results 
from switching the load capacitance. To obtain the internal 
equivalent capacitance, you must subtract the load current 
from Icc- 


Vcc 



TL/F/8128-1 

FIGURE 1. Principal contributors to CMOS power consumption, these transient currents are the result 
of transitional charging and discharging of Internal and load capacitances. The average currents are 
naturally a function of the operating frequency. 

Published in EDN Magazine © Copyright 1984 Cahners Publishing Co. 


2-242 







Using the Cpp figure spec’d in data sheets, you can esti- 
mate the current consumption of each device in your sys- 
tem if you know the toggling frequency. By multiplying both 
sides of Equation 2 by Vcc. you can determine the dynamic 
power consumption. 

PdYNAMIC = (CpD + CL)(Vcc2)(f). (3) 

As mentioned, Cpp is an indirect measure of the amount of 
switching current a circuit consumes. It depends on how 
much of the circuit’s internal logic is switching and how 
many outputs are toggling. For example, a 74HC374 octal 3- 
state flip flop clocked at 1 MHz dissipates much more power 
if its data inputs change every clock period than it would if 
its outputs are disabled and its inputs are tied High or Low 
during clocking. 

Figure 3 shows that when the flip flop’s outputs are enabled 
and the data inputs are changing, virtually all internal nodes 
are toggling and all internal parasitic capacitances are 
charging. On the other hand, if the data is held High and the 
outputs are disabled, only the clock logic dissipates power 
(and very little at that). All other sections are static. 

As you’ll see, the method of testing Cpp (see “Test Cpp in 
realistic situations’’) can yield various values that might or 
might not be applicable to the particular way the part is be- 
ing used. Fortunately, several generalizations allow reason- 
able approximations to Cpo’s value, as discussed In the fol- 
lowing section. 

TEST CpD IN REALISTIC SITUATIONS 

In 54HC/74HC data sheets, one or two Cpo values are 
specified. At best, the parameter is a simplification of the 
worst-case operating mode of a device under typical operat- 
ing conditions. However, because most devices have sever- 
al possible toggling modes (each having a different power 


consumption), you might do well to characterize Cpp for 
your particular application. 

The nearby Figure 2 shows a circuit for measuring CpQ. 
Normally, the 1C is set up in a given toggling mode, with its 
output pins pulled out of the test socket to reduce stray-in- 
duced errors. For automated testing, you could use a stan- 
dard load (eg, 50 pF) and subtract its Ice contribution from 
the total. The ammeter in series with the Vcc line is by- 
passed with 0.1- and 1-ju,F capacitors. 

For simple measurements, you can set the input’s toggle 
frequency at 200 kHz, with Vcc = 5V. This yields an amme- 
ter reading in microamps, that’s equal to CpQ in picofarads. 
You could use other voltages and frequencies, but little vari- 
ation should result. For example, JEDEC’s high-speed- 
CMOS committee recommends 1 MHz. 

To better understand what datasheet Cpo means, the fol- 
lowing listing describes by part type how each 1C is toggled. 
In measuring Cpp, the worst path is always chosen. More- 
over, within the constraints listed, as much of the internal 
•circuitry and as many of the outputs as possible are toggled 
simultaneously. 

• Gates: All inputs except one are held at either Vcc or 
ground, depending on which state causes the output to 
toggle. The one remaining input is toggled at a, given 
frequency. CpQ is given on a per-gate basis. ' 

• Decoders: One Input is toggled, thereby causing the out- 
puts to toggle at the same rate. Normally, one of the 
address-select pins Is switched while the decoder is en- 
abled. All other inputs are tied to Vcc or ground, which- 
ever enables operation. Cpo is expressed on a per - in- 
dependent - decoder basis. 


X 


-tr POWER 
SUPPLY 


PULSE 

GENERATOR 

(NOTEl) 


-TL 


Vcc 


I INPUT(S) 


TEST 1C OUTPUT(S) 


(NOTE 3) - 


I INPUT(S) 


GND 

T 


n 



10 /iF 


(NOTE 2) 


TL/F/8128-2 


Notes: 1. OUTPUT = square wave with ^ 6-nsec rise and fall times; levels = GND and Vcc- 

2. Bend all output pins from test socket, or use known load and deduct its current from measured Ice- 

3. Terminate all unused inputs to GND or Vcc- 


FIGURE 2. Measure equivalent CMOS-system capacitance with this simple test circuit. The text describes how to toggle 


the various CMOS logic functions (excepting one>shots, of course, which draw dc power). 


I 



2-243 


AN-376 




AN-376 


• Multiplexers: One data input is tied high, and a second 
is tied low. The address-select lines and enable inputs 
are configured such that by toggling one address line the 
two data inputs are alternately selected, causing the out- 
puts to toggle. If it’s a 3-state MUX, Cpp is given for 
outputs both enabled and disabled. Cpo is measured per 
multiplexer function. 

• 3-state buffers and transceivers: When the outputs 
are enabled, Cpp is measured as for simple gates; ie, on 
a per-buffer basis. The same holds true for the 3-state 
condition. Transceivers are measured per buffer as well, 
both enabled and disabled. 

• Latches: The device is clocked and data is toggled every 
other clock pulse. Other preset or clear inputs are held to 
enable output toggling. If the device has commonly 
clocked latches, the clock is toggled and one latch is 
exercised. 3-state latches are measured with their out- 
puts both enabled and disabled. Cpc is given on a per- 
iatch basis. 

• Flip flops: The same as for latches. The device’s inputs 
are configured to toggle, and any preset or clear inputs 
are held inactive. 

• Shift registers: The register is clocked and the serial 
data input is toggled every other clock pulse, as for latch- 
es and flip flops. Other clear or load pins are held inac- 
tive, and parallel data inputs are held at Vcc or ground. 
3-state devices are measured with outputs both enabled 
and disabled. If the device takes parallel loads only, it’s 
loaded with 10101010... and clocked to shift the data out, 
then reloaded. 

• Counters: A signal is applied to its clock input; other 
clear or load inputs are held inactive. Cpo is given, for 
each counter within a package. 

• Arithmetic circuits: adders, magnitude comparators, 
encoders, parity generators, ALUs and other miscellane- 
ous circuits. The general rule is to exercise these parts to 
obtain the maximum number of outputs toggling simulta- 
neously while toggling only one or two inputs. 

« Display drivers: Cpp is generally not required for LED 
drivers, because the LEDs use so much more power they 
overshadow the drivers’ Cpp: moreover, when blanked 
the drivers are rarely driven at any significant speed. If 
needed, however, Cpp is measured with outputs enabled 
and disabled, while toggling between a lamp test and 
blank (if provided), or between a display of numbers 6 
and 7. LCD drivers are tested by toggling their phase 
inputs, which control the segment and backplane wave- 
forms.' If either of these driver types has latched inputs, 
the latches are set to a flow-through mode. 

• One-shots: In some cases, when a device's Ice is signif- 
icant, CpD might not be specified. When it is, Cpo is test- 
ed by toggling one trigger input such that the output is a 
square wave. The timing resistor is tied to a separate 
Vcc line, to eliminate its power contribution. 

FIGURING DYNAMIC SYSTEM POWER 

How do you calculate a system’s dynamic power? You can 
do it on several levels, depending on the accuracy needed. 
The simplest approach is to use a Cpp model that’s the sum 
of the CMOS ICs’ Cpps and the load capacitances. Then, 
assuming an average frequency, plug these numbers into 
Equation 2 or Equation 3. 



10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 

TL/F/8128-3 

FIGURE 3. Output status determines dynamic 
dissipation in this 3-state-output flip flop. The 1C 
dissipates an order-of-magnitude higher power 
with its outputs enabled. 

The most accurate approach, however, is to determine each 
component’s operating frequency and its capacitive load. 
This method is used in critical battery powered applications. 
The following section describes this approach and proposes 
simplifications. In this approach, system dynamic power is 
the sum of the individual circuits’ power dissipation: 

Pj = Pl + P 2 + P 3 + P 4 "i" ©fc, (4) 

where Py is the total power and Pp is the power for each 
component. By substituting Equation 3 into Equation 4, the 
total system power is 

Pt = (Cpi + CLl)(Vcc2)(f) + 

(Cp 2 + CL2)(Vcc2)(f) + ...etc. (5) 
In Equation 5, load capacitances Cli, Cl 2 , etc are not sim- 
ply the sum of all individual output loads. Cl is actually de- 
pendent on device type. Why? Different devices switch a 
different number of outputs simultaneously. What’s more, 
these outputs can toggle at a different rate from that of the 
IC’s clock or input. Thus, for an individual IC and its load, the 
actual power is 

P|C = Vec^ [(CpoO + (CLifii) + (Cl2^L2) + (6) 

where Cl is the load on each of the simultaneously toggling 
outputs, and fL is the toggle rate seen by the load. A good 
example is the power dissipation of a 4-bit CMOS counter. 
Here there are four output terms — each output switches at a 
different frequency. Accordingly, there are four (each) dis- 
tinct Cl and fL terms. To simplify Equation 6, define an 
effective load capacitance Cle which is the actual load mul- 
tiplied by the ratio of the load toggle rate to the IC’s toggle 
frequency: 

Cle = (CL)(fL/f)- (7) 

Substituting Equation 7 into Equation 6 and grouping 
terms, 

P|C = Vec^ f(CpD + Clei + Cle2 + "•■)• (8) 

This procedure simplifies the process because output tog- 
gle rates are almost exclusively a binary division of the input 
clock. Thus, for an accurate calculation of system power, 
you must calculate It for each IC using Equation 8 and take 
the total. The counter is a prime candidate for using Equa- 
tion 8. Here, the first stage’s effective output capacitance is 
half the actual; the second, one-quarter, and so on. 


2-244 



TAILOR f, C TO DEVICE TYPE 

To make practical use of the foregoing methods, the follow- 
ing list describes most of theXMOS-logic categories in 

terms of effective load and operating frequency; 

• Gates and buffers: Power calculations for these are 
straightforward. Cpp, given for each gate, sums directly 
with its output load. Operating frequency is the rate at 
which the output toggles. For disabled 3-state buffers, 
the power calculation uses the 3-state-output Cpp multi- 
plied by the input frequency (no load capacitance includ- 
ed.) 

• Decoders: Each independent decoder can toggle no 
more than two outputs at a time. To calculate power con- 
sumption, sum CpD with the load on two outputs. The 
frequency Is the rate at which the outputs switch. 

• Multiplexers: For non-3-state devices, sum the loads on 
all used outputs and add the sum to Cpo- The frequency 
is that at which the outputs switch. For 3-state devices, 
use only Cpp; the frequency is the inputs’ toggle rate. 

• Counters: The operating frequency for each of a coun- 
ter’s outputs is that of the previous stage divided by two. 
The loads on lower order stages contribute less current. 
So to calculate power, sum CpD with one-half the first 
stage’s load plus one-quarter the second stage’s, and so 
on. For decade and other modulo counters, this proce- 
dure is slightly different. In general, you can neglect out- 
puts more than four stages removed from the clock. A 
simple approximation is to sum Cpp with the average 
output load and use the input clock frequency. 

• Latches, flip flops and shift registers: For these devic- 
es, the frequency is the ICs’ clock rate. The outputs typi- 
cally change state at half the clock rate, so when calcu- 
lating power dissipation, add Cpo to half the output load. 
If the data inputs change more sloyviy, you can modify 
the effective load downward by the ratio of the data rate 
to the clock rate. Again, if the outputs are disabled, no 
load dissipation exits and you should use the 3-state 
CpD- 


74HC04 



These rules notwithstanding, it’s rarely necessary to go 
through a detailed analysis of each 1C. In most instances, a 
simpler analysis can yield good results. In noncritical appli- 
, cations where power consumption Is used to determine the 
system’s power-supply needs, the simpler analysis suffices. 
U^ng this method, you estimate the average operating fre- 
quency for major sections of the system. Next, sum all the 
CpDS and effective loads in each section: 

Pblock = vcc^UvG t(Cpi + Clei) + 

(Cp2 + Cle 2) + • . ■ + (Cpn + Cler)]- (9) 
Thus, to approximate the total system’s power consump- 
tion, you must approximate the effective loads for each 
group of devices (or the entire system) and add them to- 
gether. ' 

Consider a microprocessor-based system using an 8 MHz 
clock frequency. In this example, you might determine that 
the bus operates at approximately 2 MHz, random control 
logic at 4 MHz, and the RAM and I/O devices at 100 kHz. 
You could estimate an overall system clock to be 1 to 
2 MHz, depending on the actual size of each block. Next, 
you’d sum the Cpp and the effective load capacitances — 
say 2000 and 1000 pF, respectively. The ballpark estimate 
for system power is 

P = (5)2 (1 MHz)(2000 pF + 1000 pF) = 75 mW. (10) 
Exceptions to the above rules are one-shot ICs and gates 
configured as oscillators, which use CMOS In an essentially 
linear manner. Their power consumption is not strictly attrib- 
utable to negligible quiescent currents or dynamic switching 
currents. 

Consider one-shots, some of which draw dc current continu- 
ously, some only when the output pulse is triggered (check 
data sheets for the device type you’re using). The culprits 
are the ICs’ Internal linear CMOS comparators that use dc 
bias circuits. HC one-shots use several design approaches. 
One (the ’HC123A/221A/423A) uses a comparator that 
shuts off after a pulse times out; the second (the ’HC4538) 
leaves the comparators on at all times. 


74HC04 



(b) 



R1 

AAAr 


:c2 :^ci 


(d) 


TL/F/8 128-4 


FIGURE 4. Drawing higher-than-calcuiated power, these CMOS oscillator configurations suffer 
from “soft” logic levels at their gates’ inputs. Circuits (a) through (d) are 3-inverter, 
2-inverter, Schmitt-trigger and crystal oscillators, respectively. 


2-245 


AN-376 




(O 

N. 


CO 


Z 

< 


A one-shot’s overall power consumption is its quiescent 
power plus the power consumed by Its timing elements and 
CpD- If the comparators turn off, you multiply the quiescent 
current by the duty cycle of the output pulse. Thus, the over- 
all expression for one-shot power consumption is 


Pos=(lcc)(Vcc)(D) + (Cext + Cl + CpD){Vcc2)(f), <11) 


where Pqs 's the total power, D the one-shot’s duty cycle, 
Cext the timing capacitor, Cl the load on both outputs, and 
f the operating frequency. In general, the Cpp term Is small 
at lower frequencies; you can safely set it to zero to simplify 
the equation. 


What about oscillators? The circuits shown in Figure 4 draw 
more current at a given operating frequency than you’d cal- 
culate using only Cpp. This Is because in these applications, 
the inputs to some of the gates are at “soft” logic levels for 
significant amounts of time. This causes both p- and n- 
channel transistors to conduct simultaneously and hence 
draw dc current. 


Figure 5a plots current vs input voltage for the 74HC00 gate 
and gives an idea of the amount of current typically drawn 
when soft logic levels are applied. The large spike at 2.3V is 
the result of the output’s switching. At low frequencies, the 
oscillator’s supply current can be several milliamps higher 
than you might expect because of the amount of dc current 
drawn. 


The same is true of a 74HC14 used as an oscillator. Figure 
5b shows the supply current vs Input voltage for the 
74HC14 and the 74C14 (or CD40106). Because the actual 
power consumed vaires with frequency and component val- 
ues, it’s best to determine it empirically. As with the one- 
shots, the oscillator timing capacitor’s contribution to power 
dissipation can be expressed by P = Vcc(Ct)f. 
MM54HC/74HC logic uses bigger devices and lower tran- 
sistor thresholds than metal-gate CMOS,' so it might be 
more desirable to use either CD4000 or MM54C/74C logic 
for lower power oscillators (if operating frequency and out- 
put-drive requirements permit.) 


MORE SPECIAL CASES: HCT 

Because of their unique applications In TTL and NMOS sys- 
tems, 54HCT/74HCT devices have some additional traits 
that you should consider in designing systems. In TTL sys- 
tems, the HCT ICs’ inputs are driven under worst-case con- 
ditions by TTL levels of 0.5 and 2.4V. With these Input levels 
applied, HCT consumes significant quiescent current: about 
200 to 500 jLtA per Input. You must consider this dc current 
when calculating power. 

To see the origins of this quiescent current, refer to Figure 
6, which shows a typical HCT’s input. With a 2.4V input 
level, the n-channel transistor turns fully on; the p-channel 
device turns slightly on. This scenario results in a quiescent 
current dependent on the number of logic-One inputs ap- 
plied. The 0.5V level is close enough to ground to cause the 
n-channel transistor to turn off, so HCT ICs draw quiescent 
current only when its inputs are at a high state. 

The Icc values with these logic levels are specified In the 
HCT data sheets. It’s specified on a per-input basis — this 
allows you some flexibility in determining quiescent power 
when an 1C is driven by both CMOS and TTL. The specified 
quiescent-current value results In calculated Icc values of 
several milliamps per 1C, significantly less than that of LS 
TTL circuits. 

Note, however, that using this data-sheet approach yields 
current values roughly five times higher than that actually 
seen in system designs. The reason for this is that the Icc 
test is spec’d at Vcc=5.5V and V|n = 2.4V, but even worst- 
case TTL Output-High levels are at least 3.4V under these 
conditions. Output levels can only attain a low 2.4V with 
Vcc= 4.5V. Moreover, both TTL and NMOS outputs typical- 
ly assume levels closer to 3V (at Vcc=4.5V), lowering qui- 
escent current more. The point is, don’t let Icc specs scare 
you into thinking CMOS is a power hog. 



0 1.0 2.0 3.0 4.0 5.0 


INPUT VOLTAGE (V) 

(a) 



FIGURE 5. “Soft” logic levels cause high currents in a 74HC00 inverter (a) and a 74HC14 connected as an osciliator 
(b,c). Because the power varies with frequency and component values, it’s best to determine its vaiue empiricaliy. 


2-246 




In mixed TTL-CMOS applications, the calculation of power 
consumed by the HCT logic must take into account both the 
dynamic and the quiescent currents.The dynamic portion is 
the same as that for HC logic— -in fact, Cpp is measured with 
0 and 5V input levels to exclude any quiescent current. The 
static portion is the sum of the number of TTL logic-One 
inputs times their High-period duty cycle times the current 
per input. For a single 1C, the power consumption is 

Pic = (Vcc)(lcc)(N)(D) + Vcc2 f(CpD + Cle). (12) 
where Cle >s defined as before, N is the number of TTL-driv- 
en inputs and D is the logic-High duty cycle. 

Ice is the data sheet’s per-input spec. This expression can 
then be one term in Equation 4. If you’re using the pack- 
age-level quiescent current, the terms N and D drop out. 
What about a situation in which HC drives HCT? In this sce- 
nario, ground and Vec levels are applied, thereby ensuring 
that the p- and n-channel transistors don’t turn on simulta- 
neously. You can thus determine HCT power dissipation just 
as for HC by using CpQ. 


Vcc 



TL/F/812a-6 

FIGURE 6. TTL-compatible CMOS is a special case. This 
schematic shows the 54HCT/74HCT family’s input 
buffer. With a 2.4V input applied, the n-channel 
transistor is fully On; the p-channel, slightly On. 




FIGURE 7. Reducing clock rate — but not throughput — this scheme allows you to reduce power by clocking a system’s 
n subsections only as fast as needed, instead of clocking ail system blocks at the full clock frequency 


2-247 


AN-376 



AN-376 


NOW LET’S REDUCE POWER 

When designing low-power CMOS systems, there are sev- 
eral ways to minimize power. These methods Involve reduc- 
ing operating frequencies, cutting system load capacitanc- 
es, using fast Input transition times and minimizing any dc- 
current paths. 

First, for low-power system implementations, it’s Important 
not to overdesign the operating frequency. Very simply put, 
it makes no sense to clock a counter at 20 MHz when 5 
MHz will suffice. 

Note that a reduction In overall system clock frequency 
doesn’t necessarily entail a reduction in throughput. For ex- 
ample, consider a system consisting of four subsections, 
clocked at 8 MHz (Figure 7a). Rather than clocking all sec- 
tions in parallel, you can reduce power by clocking each 
section only as fast as need be (Figure 7b). A second exam- 
ple of reducing the overall system clock rate is shown in 
Figure 8. 

In {a), a CMOS memory array is driven directly from the 
CPU’s address bus. Here, every memory Is driven at the bus 
frequency. If, however, the address is latched by each mem- 
ory block only when that block is being accessed {b), then 
only the block currently being accessed is clocked. This is 
why some CMOS RAMs Incorporate on-chip address latch- 
es. 

Another Way to operate a system at the minimum possible 
frequency is to switch the system clock. The system is thus 
made to operate at the highest frequency only when need- 


ed. Figure 9 shows the logic used to Implement this scheme 
for a CMOS jaP system. In this method, there are two oscil- 
lators, either of which can feed a divIde-by-two circuit that 
provides a square-wave output. The flip flop’s output is the 
system clock. The system’s jmP can set or reset the flip flop 
so that it can operate at either frequency. 

Besides frequency reduction, there are several other meth- 
ods to save power, including reducing load capacitances. 
You can accomplish this by reducing wiring capacitance (es- 
pecially in high-frequency sections) through good layout 
practices, and by maintaining close proximity between Inter- 
related high-frequency sections. In some Instances where 
you might instinctively parallel several unused inputs, you 
can achieve lower load capacitance by tying the unused 
inputs to a supply. In another example, when using RC oscil- 
lators, it’s best to use the smallest capacitor and the largest 
resistor possible. 

Slow input transitions can cause extra dissipation. If an input 
signal rises slowly, it causes both input transistors to con- 
duct for a longer time, thereby causing more current to flow. 
One rule of thumb is if rise and fall times are shorter than 25 
nsec, minimal current will flow. But don’t go overboard. Be 
aware that slow transitions are more tolerable in slower op- 
erating sections because the transitions occur less often. 
Therefore, weigh the importance of the extra dissipation 
against the cost of speeding signals up. 

It’s important to point out that floating inputs can result in 
unnecessary power dissipation. If inputs are open, the input 


4-PAGE 

MEMORY 

ARRAY 


4-PAGE 

MEMORY 

ARRAY 



TL/F/8128-8 


(a) 


(b) 


FIGURE 8. Latching memories’ addresses (b) can reduce system power. In (a), every memory is driven at the bus 
frequency. By contrast, in (b)’s configuration, only the memory block being addresed is clocked. 


2-248 







OSCILLATOR 


FROM fiP 
' OATA BUS DO 


FROM mP 
ADDRESS BUS 


HARD-WIRED 
TO Vcc OR GND 
FOR ADDRESS 
SELECTION 


uP m 


TL/F/8128-9 


FIGURE 9. Switch your system’s clock frequency for reduced power consumption. The circuit 
shown is a software-selectable oscillator for a microprocessor system. 


voltage can float to an indeterminate and intermediate level; 
thus, don’t float CMOS Inputs. This action can turn on both 
p- and n-channel transistors, resulting in supply-current 
drain. In bus-oriented systems, don’t allow the bus to be- 
come completely 3-stated or float for extended periods be- 
cause this will have the same effect as leaving inputs open. 
Bus structures subject to prolonged 3-state conditions 
should be terminated to ensure that the bus lines pull to 
either Vcc O'" ground. For short durations, the bus capaci- 
tance can maintain valid logic levels, so for short-time float- 
ing, pull-up or -down resistors might not be necessary. 
Finally, make sure your design ensures solid Vcc ^nd 
ground logic levels at 54HC/74HC inputs. If the logic Low is 
greater than 0.5V or the logic High is lower than Vcc “0.5V, 
then the normally Off p- or n-channel transistor can actually 
conduct slightly, causing additional Ice to flow (similarly to 
the previously discussed HOT “soft” levels). 

BE WARY OF STATIC LOADS 

Previous sections discussed the effects of capacitive loads 
on system power dissipation. What about resistive loads? In 
ultra-low-power systems, their contribution can be signifi- 
cant, so it’s important to find ways to eliminate or minimize 
their detrimental effects. The loads could be pull-up resis- 
tors, bus terminators, displays, relays or peripheral drivers. 
Of course, the most obvious way to reduce power is to se- 
lect low-power relays or displays, for example, and to make 
resistor values as high as possible. In addition, you can 
switch these loads out of the circuit when not needed. 
Figure 10 shows a circuit that dissipates no static power; 
you can use it to terminate a 3-state bus to the last active 
logic level seen on the bus. This technique is useful to en- 
sure the bus doesn’t float when 3-stated. The circuit uses a 
74HC244 whose input is tied to its output. If the terminating 
resistors must be completely turned off, use the 3-state En- 
able. 



MM74HC244 


TL/F/8128-10 


icon < R < 200k 


FIGURE 10. Dissipating zero static power, this scheme 
can serve to terminate a 3-state bus to the last active 
logic level seen on the bus. To disconnect the 
terminating resistors, use the 3-state Enable command. 



2-249 


AN-376 



AN-376 


Figure 1 1 illustrates a method of controlling a series of pull- 
up resistors using the output of an HC gate or 3-state buffer. 
Because HC outputs can pull up to Vcc. you can use them 
as an enable for many pull-ups, as long as the parallel com- 
bination of the pull-up resistors exceeds 2 kfl. You can also 
use the method for pull-down resistors. 



TL/F/8128-11 

FIGURE 11. Enable or disable pull-up resistors with this 
configuration. You can use an HC device’s outputs to 
enable several pull-ups. The scheme is also applicable 
to pull-down resistors. 


When considering whether you should add circuitry to dis- 
able pull-up resistors, remember that in CMOS systems, the 
pull-ups only dissipate power when the driving output is low. 
No power is consumed when the driving output is high or at 
the 3-state level (disabled). 

THE FINAL SOLUTION: POWER DOWN 

When all else fails, the best way to reduce system power is 
to shut off the system or unnecessary parts. Before you do 
this, keep in mind that turning off the clock to a section of 
the system is almost tantamount to turning the section off 
(thanks to the ICs’ low leakage currents). The advantage of 
the clock-killing approach? It avoids the complications of 
the power-down methods that follow. 

Still, there are occasions in which parts of a system are 
powered down. When all or part of a system is shut off, or 
when one of several interconnected systems Is powered 
down, you should respect several criteria to avoid spurious 
signals during the power-down period, and to eliminate pos- 
sibly fatal conditions. 

One condition that requires very careful consideration is the 
application of high-level signals to unpowered HC devices. 
Figure 12a shows in block form the basic concepts of pow- 
ering down part of a system. In this scenario, it’s possible to 
apply a logic One to the unpowered CMOS logic. If this 
happens to either an input (b) or a 3-state output (c). the 
device will still be powered. 




TO UNPOWEREO 

Vcc line and 

OTHER COMPONENTS 


TO SYSTEM 
GROUND 


(b) 


TL/F/8128-12 

(C) 


FIGURE 12. This basic power-up and -down system (a) presents dangers to CMOS-logic ICs. As the 
input (b) and output (c) schematics show, a logic One can actually power up the “unpowered” system, 
thereby causing damage to input and output diodes. 


2-250 




2-251 



BACK-UP 

SUPPLY 



(a) 


(c) 


BACK-UP -±“ 
SUPPLY -IT 


MAIN 

SUPPLY 


Vcc 


I POWERED 
SYSTEMS 


POWER-CONTROL 

LOGIC 








Vcc 


POWERED- 

DOWN 

SYSTEM 



(b) 


(d) 


TL/F/8128-13 


FIGURE 13. Solutions to the problems in Figure 12, these configurations protect CMOS circuits’ inputs and outputs in power-down situations. 
The brute-force solution in (a) limits input currents; (b)’s scheme forces inputs to ground; in (c), 3-state gates disable the inputs. 

In (d), 74HC4049 or -4050 level translators isolate inputs from the power supply. 


9ze-Nv 


ro 






AN-376 


Referring again to Figures 12b and 12c, the input protection 
diodes and the output parasitic diodes form a patfY to the 
Vcc pin. The voltage at this pin will ,be V||vj-0.7V. The “un- 
powered” system is really powered up by the logic signal 
through these diodes. If the “unpowered” Vcc i'ne accepts 
appreciable current, diode damage can (and usually does) 
result. 

Figure 13 shows several solutions to the signal-powered 
“unpowered” problem. A resistor in series with each input 
(a) limits the current to 20 mA max. This low-cost, brute- 
force solution has the undesirable tendency, however, to 
dissipate power from the supply. 

To avoid extra power consumption, you can use the meth- 
ods in Figures 13b to 13d. Upon removal of power, addition- 
al logic can force all inputs to ground (b). Alternatively, 3- 
state logic can disable the signals by presenting an open 
circuit (c). The third possible solution (d) is to use a 
74HC4049 or 74HC4050 — circuits that lack a Vcc diode. In 
this case, even when power is removed the inputs are iso- 
lated from the power supply. 

A situation analogous to the previous section’s might occur 
on bidirectional buses or In “party-line” media, where 3- 
state output devices are powered down on the bus. In this 
case, power down all but the 3-state buffer, as shown in 
Figure 14. Because the buffers inputs are shut off, the 1C 
draws negligible extra power. 

In addition to ensuring that power-down proceeds smoothly, 
it’s important to guarantee that spurious signals from the 
subsystem that’s shutting down do not cause logic errors in 
the powered section. For example, battery-backed memory 
must be controlled to prevent spurious writes by the host 
processor that’s shutting off. 

Figure 15 Illustrates a method for eliminating spurious oper- 
ation upon loss of power. First, the system detects the loss 
of system power prior to the system’s malfunction by com- 
paring the system voltage to an arbitrary minimum voltage 
(V 2 ), or by directly monitoring the ac line for loss of 50 or 60 
Hz. Having detected this loss, the system should perform all 


bookkeeping operations to prepare for power-down before 
the minimum correct operating voltage (V 3 ) is attained. 

At V 3 , the system cannot be guaranteed to function correct- 
ly — therefore, powered logic should disable all signals that 
might affect the powered or battery-backed subsystem. 
Once stable power is restored to the minimum operating 
voltage (V 4 ), the signals should be re-enabled. 

Clearly, there is more to shutting off a system (while leaving 
part of It powered by a backup battery) than just switching 
the power supplies. The primordial design consideration 
when powering down a system is to ensure that spurious 
signals do not destroy valuable data or logic conditions in 
the battery-operated subsystem. 



© NORMAL SYSTEM OPERATION 
® LOW-VOLTAGE POWER-FAIL DETECT 
©MINIMUM OPERATING VOLTAGE 
©MINIMUM RESTORED OPERATING VOLTAGE 
©NORMAL SYSTEM OPERATION 

FIGURE 15. Prevent spurious host-processor write 
operations in battery-backup systems by using this 
graph’s concepts. To sum up, the system should 
prepare itself for power-down before minimum- 
operating voitage V 3 is reached, and re-enabie signais 
when V 4 is attained upon power-up. 



TL/F/8128-14 


FIGURE 14. Powering down ail but the 3-state buffer, this method protects CMOS ICs’ 
output-protection diodes. The buffers draw negiigibie system power. 


2-252 




DC Noise Immunity 
of CMOS Logic Gates 


National Semiconductor 
Application Note 377 
Vivek Kulkarni 
July 1984 



Introduction 


Transfer Characteristics 


The immunity of a CMOS logic gate to noise signals is a 
function of many variables, such as individual chip differ- 
ences, fan-in and fan-out, stray inductance and capaci- 
tance, supply voltage, location of the noise, shape of the 
noise signal, and temperature. Moreover, the immunity of a 
system of gates usually differs from that of any individual 
gate; thus a generalized analysis of the noise immunity of a 
logic circuit becomes a very complex process when one 
takes all the above parameters into consideration. 

The complementary structure of the inverter results in a 
near-ideal input-output characteristic with switching point 
midway (46%-55%) between the “0” and “1” output logic 
levels. The result is a high noise immunity (defined as the 
maximum noise voltage which can appear on the input with- 
out switching an inverter from one state to another). Nation- 
al’s CMOS circuits have a typical noise immunity of 0.45 
Vcc- This means that a spurious input which is 45% of the 
power supply voltage typically will not propagate through 
the circuit. However, the standard guaranteed value through 
the industry is 30%. 

This note describes the variation of the transfer region (or 
DC noise immunity) of a multiple-input gate in conjunction 
with the gate configuration — a consideration important in 
the system design. 



V|N- INPUT VOLTAGE (V) 

TL/F/8129-1 

(a) 



ViN- INPUT VOLTAGE (V) 


TL/F/8129-2 

(b) 


FIGURE 1. Minimum and Maximum Transfer 
Characteristics for (a) Inverting Logic Function and (b) 
Noninverting Logic Function 


FIGURE 1 illustrates minimum and maximum transfer char- 
acteristics useful for defining noise immunity for an inverter 
and a non-inverter. Some definitions are as follows: 

V|H min=^he minimum input voltage high-level input 
for which the output logic level does not change 
state. 

Then: 

VNL=Vii_max=“low level” noise immunity 
VNH = VpD-V|H = ‘‘high level” noise immunity 
VoHmin = rninimum high level output voltage for rated 
Vnl [for inverting function as' in Figure 1{a)] 

Table 1 shows the UB and B series noise immunity and 
noise margin ratings determined by the Joint Electron De- 
vices Engineering Council (JEDEC).. B series ratings are 
slightly higher than the UB series because of the buffered 
nature of these gates. 


TABLE I. UB and B Series DC Noise Immunity 
and Noise Margin (Ta=25°C) 


Characteristics 

Test 

Conditions 

Input 

Voltage 

(V) 

Vo 

(V) 

Vdd 

(V) 

Input Low Voltage 

V|L max 




B types 

0.5/4.5 

5 

1.5 


. 1/9 

10 

3 


1.5/13.5 

15 

4 

UB types 

0.5/4.5 

5 

1 


1/9 

10 

2 


1.5/13.5 

15 

2.5 

Input High Voltage 

V|H min 




B types 

0.5/4.5 

5 

3.5 


1/9 

10 

7 


1.5/13.5 

15 

11 

UB types 

0.5/4.5 

5 

4 


1/9 

10 

8 


1.5/13.5 

15 

12.5 


2-253 


AN-377 




AN-377 


Since the MOS transistors are voltage-controlled resistors, 
the transfer characteristics and consequently the DC noise 
immunity are determined by the parallel series combination 
of the transistor impedances in conjunction with the input 
voltages, the number of inputs, and the gate circuit configu- 
ration. This consideration becomes more important for a 
system designer who has harsh-noise-prone applications. 
The value of the standard transistor ON resistance may vary 
from 1 0 Mfl down to almost 30fl (depending on the dimen- 
sions of the MOS-FET and applied voltages). For different 
input conditions, different combinations of the Impedances 
of the N-channel transistors connected in parallel and the 
P-channel transistors connected in series will come Into 
play for a NOR gate. This is illustrated in Figure 2. For a 
NAND gate, similar considerations hold good and give rise to 
varying transfer characteristics as shown in Figure 3. 

Example of CD4001 




A = 0. B = 1 




B 



FIGURE 2. Typical Transfer ON/OFF Resistances for 
Various Input Combinations for CD4001 


Analysis 

The DC transfer characteristics of the CMOS inverter can 
be calculated from the simplified DC current-voltage charac- 
teristics of the N- and P-channel MOS devices. 

In the transfer region, where both transistors are in satura- 
tion, the following relationships can be used for an inverter. 
N-channel drain current will be; 

•dsn = Y (V|N - Vtn)2 (1) 

P-channel drain current will be: 

-•dsp = ^ (ViN - Vdd - Vtp)2 (2) 

where: 

^ox Wp „ _ ;Ap Cqx Wp 
Kn T . Kp - . 

•-n Lp 

Taking the ratio of (2) and (1): 

IldspI ^ (V|N - VDD ~ Vtp)^ 

Idsn Kn' (V,n-Vtn)2 

Kg ^ M , (V|N - Vtn)^ , . 

Kn Idsn ■ (V|N “ Vqd - Vtp)2 ^ ^ 

Studies made at National show good correlations between 
the process monitor pattern and actual device on a wafer - 
for drive currents. Thus the ratio Kp/Kp can be calculated 
for the actual device if one knows drive currents for the test 
pattern, widths of N- and P-channel devices and threshold 
voltages from a given process. 

The transition voltage is calculated from basic current equa- 
tions and from the fact that some current has to flow 
through P- and N-channel devices. Equating saturation cur- 
rents and rearranging terms, one can obtaini; 

Transition Voltage = V|n* 

Vtn + -i/P (Vdd “ IVtpI) 

= ^ ^ (4) 

^ITTK^ ' ^ 


2-254 




V|N - INPUT VOLTAGE (Vdc) 


TL/F/8129-8 




I 

5 



0 5 10 

V|N - INPUT VOLTAGE (Voc) 



FIGURE 3. Allowed Voltage Transfer Curve Shifts 
which Result Due to Various Input Combinations 
of Multiple Input Gates 


TL/F/8129-9 


TL/F/8129-10 






AN-377 


By selecting |Vjp| = Vtn and Kp = Kn, transition voltage can 
be designed to fall midway between OV and Vdd — an ideal 
situation for obtaining excellent noise immunity. However, it 
is not always possible to obtain equal threshold voltages 
because of process variations. Also, W/L ratio for a P-chan- 
nel device must be made 2 or 3 times larger than W/L ratio 
for an N-channel device to take into account mobility varia- 
tions. The designer should consider these factors when de- 
signing for the best noise immunity characteristics. 

In equation (4), the value of Kp/Kn substituted Is obtained 
from equation (3). With different gate configurations, effec- 
tive Wp and Wn values change; also, Kp/Kp ratio changes 
and a shift in transfer characteristics results. 

For the 4-input NOR gate like CD4002, an empirical relation 
for the low noise margin Vnl has been obtained, which is as 
follows: 

Vnl==Vdd[ (5) 

Nm J 

where: 

Ni = number of used inputs/gate 

Nm = total number of inputs/gate 

NORMALIZED 



The input voltage high noise margin Vnh can be calcu- 
lated by: 

Vnh = Vdd[o.9 (6) 


Similar equations can be derived for a NAND gate. 

From equations (5) and (6), one can see that the low noise 
margin Vnl will decrease as a function of the number of 
controlled inputs, while it will increase for a NAND gate. The 
input HIGH noise margin will increase as a function of the 
number of controlled inputs for the NOR gate; for the NAND 
gate it will decrease. 

Figure 4 depicts VouT=^ (V|n) different configurations 
for NOR and NAND gates. The system designer can thus 
use these facts effectively In his design and obtain the best 
possible configuration for the desired noise immunity with 
National’s logic family. 


-p- 


0 0.3 0.7 NORMALIZED >— 4 0 0.3 0.7 N0RMALIZEDf-| 

V|N ' V|N J. 

4-INPUT NOR 4-INPUT NAND *=* 

C04002 * TL/F/8129-11 CD4012 H-/F/8129-12 

FIGURE 4. Example of Transfer Voltage Variation for NOR and NAND Gates for Various Input Combinations 

1. Carr, W.N., and Mize, J.P., MOS/LSI Design and Application, Texas Instruments Electronic Series, 1972 


2-256 




MM54C/MM74C Voltage 
T ranslation/Buffering 


National Semiconductor 
Memory Brief 18 
John Jorgensen 
Thomas P. Redfern 


INTRODUCTION 


A new series of MI\/l54C/MM74C buffers has been designed 
to interface systems operating at different voltage levels. 
In addition to performing voltage translation, the 
MM54C901/IV1M74C901 through MM54C904/I\/IM74C904 
hex buffers can drive two standard TTL loads at 
Vcc = 5V. This is an increase of ten times over the two 
LpTTL loads that the standard MM54C/MM74C gate can 
drive. These new devices greatly increase the flexibility 
of the IV1M54C/MM74C family when interfacing to other 
logic systems. 


PMOS TO CMOS INTERFACE 

Since most PMOS outputs normally can pull more nega- 
tive than ground, the conventional CMOS input diode 
clamp from input to ground poses problems. The least 
of these is increased power consumption. Even though 
the output would be clamped at one diode drop {-0.6V), 
all the current that flows comes from the PMOS negative 
supply. For TTL compatible PMOS this is -1 2 V. A PMOS 
output designed to drive one TTL load will typically sink 


5 mA. The total power per TTL output is then 
5 mA X 12V = 60 mW. The second problem is more 
serious. Currents of 5 mA or greater from a CMOS 
input clamp diode can cause four-layer diode action on 
the CMOS device. This, at best, will totally disrupt 
normal circuit operation and, at worst, will cause 
catastrophic failure. 

To overcome this problem the MM74C903 and 
MM74C904 have been designed with a clamp diode from 
inputs to Vcc only. This single diode provides adequate 
static discharge protection and, at the same time, allows 
voltages of up to -17V on any input. Since there is 
essentially no current without the diode, both the high 
power dissipation and latch up problems are eliminated. 

To demonstrate the above characteristics. Figures 1, 2, 
and 3 show typical TTL compatible PMOS circuits 
driving standard CMOS with two clamp diodes, TTL 
compatible PMOS dfiving MM74C903/MM74C904, and 
the TTL compatible PMOS to CMOS system interface, 
respectively. 


IsiMK 

I / I 5mA(TYP) I 

1 PMOS TTL r— I | | 

ILL OUTPUT ^ 


OUTPUT i I I 


Vcc 

fcl 


Vcc < 15V (MM54C903/MM74C903 or JA 

MM54C904/MM74C904 


FIGURE 3. PMOS to CMOS or TTL Interface 


2-257 



MB-18 


CMOS TO CMOS OR TTL INTERFACE 

When a CMOS system which is operating at \/cc = lOV 
must provide signals to a CMOS system whose Vcc = 5V, 
a problem similar to that found in PMOS-to-CMOS inter- 
face occurs. That is, current would flow through the 
upper input diode of the device operating at the lower 
Vcc- This current could be in excess of 10 mA on a 
typical 74C device, as shown in Figure 4. Again, this will 
cause increased power as well as possible four layer diode 
action. 



TUF/6034-5 

FIGURE 5 


Using the MM74C901 or MM74C902 will eliminate this 
problem. This occurs simply because these parts are 
designed with the upper diode removed, as shown In 


Figure 5. With this diode removed the current being 
sourced goes from about 10 mA to the leakage current 
of the reverse biased input diode. 

Since the MM74C901 and MM74C902 are capable of 
driving two standard TTL loads with only normal input 
levels, the output can be used to directly drive TTL. With 
the example shown, the inputs of the MM74C901 are In 
excess of 5V. Therefore, they can drive more than two 
TTL loads. In this case the device would drive four loads 
with V||vj = 10V. If the MM74C902 were used, the output 
drive would not increase with increased input voltage. 
This is because the gate of the output n-channel device is 
always being driven by an internal inverter whose output 
equals that of Vqc of the device. 

The example used was for systems of Vcc “ 10V on one 
system and Vqc = 5V on the second, but the MM74C901 
and MM74C902 are capable of using any combination of 
supplies up to 15V and greater than 3V, as long as Vcci 
is greater than or equal to Vcc 2 sod grounds are 
common. Figure 6 diagrams this configuration. 



The inputs on these devices are adequately protected 
with the single diode, but, as with all MOS devices, 
normal care in handling should be observed. 











Section 3 

MM54HC/MM74HC 






Section Contents 

IV1M54HC00/MM74HC00 Quad 2-Input NAND Gate 3-7 

MM54HC02/MM74HC02 Quad 2-Input NOR Gate 3-10 

MM54HC03/MM74HC03Quad2-lnputOpen Drain NAND Gate 3-13 

MM54HC04/MM74HC04 Hex Inverter 3-16 

MM54HCU04/MM74HCU04 Hex Inverter 3-19 

MM54HC08/MM74HC08Quad2-lnputANDGate 3-22 

MM54HC10/MM74HC10Triple3-lnputNANDGate 3-25 

MM54HC11/MM74HC11 Triple3-lnput ANDGate 3-28 

MM54HC14/MM74HC14 Hex Inverting Schmitt Trigger 3-31 

MM54HC20/MM74HC20 Dual 4-Input NAND Gate 3-34 

MM54HC27/MM74HC27Triple3-lnputNORGate 3-37 

MM54HC30/MM74HC30 8-Input NAND Gate 3-40 

MM54HC32/MM74HC32 Quad 2-Input OR Gate 3-43 

MM54HC42/MM74HC42 BCD-to-Decimal Decoder 3-46 

MM54HC51/MM74HC51 DualAND-OR-InvertGate 3-49 

MM54HC58/MM74HC58 Dual AND-OR Gate 3-49 

MM54HC73/MM74HC73 Dual J-K Flip-Flops with Clear 3-52 

MM54HC74/MM74HC74 Dual D Flip-Flop with Preset and Clear 3-56 

MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Q Output 3-59 

MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear 3-62 

MM54HC85/MM74HC85 4-Bit Magnitude Comparator 3-66 

MM54HC86/MM74HC86 Quad 2-Input Exclusive OR Gate 3-70 

MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear 3-73 

MM54HC109/MM74HC109 Dual J-K Flip-Flops with Preset and Clear 3-77 

, MM54HC1 12/MM74HC1 12 Dual J-K Flip-Flops with Preset and Clear 3-80 

MM54HC1 13/MM74HC1 13 Dual J-K Flip-Flops with Preset 3-84 

MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator 3-88 

MM54HC125/MM74HC125TRI-STATE Quad Buffers 3-93 

MM54HC126/MM74HC126TRI-STATEQuad Buffers 3-93 

MM54HC132/MM74HC132Quad2-lnputNANDSchmitt Trigger 3-96 

MM54HC133/MM74HC133 13-Input NAND Gate 3-99 

MM54HC137/MM74HC137 3-to-8 Line DecoderwIth Address Latches (Inverted Output) 3-102 

MM54HC138/MM74HC138 3-to-8 Line Decoder 3-106 

MM54HC139/MM74HC139 Dual 2-to-4 Line Decoder 3-109 

MM54HC147/MM74HC147 10-to-4 Line Priority Encoder 3-112 

\ 


3-3 




Section Contents (Continued) 

MM54HC149/MM74HC149 8-to-8 Line Priority Encoder 3-115 

MM54HC151/MM74HC151 8-Channel Multiplexer 3-118 

MM54HC153/MM74HC153 Dual 4-Input Multiplexer 3-121 

MM54HC154/MM74HC154 4-to-1 6 Line Decoder 3-124 

MM54HC155/MM74HC155 Dual 2-to-4 Line Decoders 3-128 

MM54HC157/MM74HC157 Quad 2-Input Multiplexer 3-131 

MM54HC158/MM74HC158 Quad 2-Input Multiplexer(lnverted Output) 3-131 

MM54HC160/MM74HC160 Synchronous Decade Counter 3-135 

MM54HC161/MM74HC161 Synchronous Binary Counter 3-135 

MM54HC162/MM74HC162 Synchronous Decade Counter 3-135 

MM54HC163/MM74HC163 Synchronous Binary Counter 3-135 

MM54HC164/MM74HC164 8-Bit Serial-In Parallel-Out Shift Register 3-140 

MM54HC165/MM74HC165 Parallel-In Serlal-Out8-Bit Shift Register 3-143 

MM54HC173/MM74HC173TRI-STATEQuadDFIip-Flop 3-147 

MM54HC174/MM74HC174 Hex D Flip-Flops with Clear 3-151 

MM54HC175/MM74HC175QuadD-Type Flip-Flop with Clear 3-154 

MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators 3-158 

M M54HC1 82/ M M74HC1 82 Look-Ahead Carry Generator 3-166 

MM54HC190/MM74HC190 Synchronous Decade Up/Down Counters with Mode Control 3-170 

MM54HC191/MM74HC191 Synchronous Binary Up/Down Counters with Mode Control 3-170 

MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters 3-177 

MM54HC193/MM74HC193Synchronous Binary Up/Down Counters 3-177 

MM54HC194/MM74HC194 4-Bit Bidirectional Shift Register 3-184 

MM54HC195/MM74HC195 4-Bit Parallel Shift Register r. 3-188 

MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable Multivibrator 3-192 

MM54HC237/MM74HC237 3-to-8 Decoder with Address Latches 3-197 

MM54HC240/MM74HC240 Inverting Octal TRI-STATE Buffer " 3-201 

MM54HC241/MM74HC241 Octal TRI-STATE Buffer 3-201 

MM54HC242/MM74HC242 Inverting Quad TRI-STATETransceiver 3-206 

MM54HC243/MM74HC243QuadTRI-STATETransceiver 3-206 

MM54HC244/MM74HC244 Octal TRI-STATE Buffer 3-210 

MM54HC245/MM74HC2450ctal TRI-STATETransceiver 3-214 

MM54HC251/MM74HC251 8-Channel TRI-STATE Multiplexer 3-218 

MM54HC253/MM74HC253 Dual 4-Channel TRI-STATE Multiplexer 3-221 

MM54HC257/MM74HC257 Quad 2-Channel TRI-STATE Multiplexer 3-224 


3-4 




Section Contents (Continued) 

MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder 3-227 

MM64HC266/MM74HC266 Quad 2-Input Exclusive NOR Gate 3-231 

MM54HC273/MM74HC273 Octal D Flip-Flops with Clear 3-234 

MM54HC280/MM74HC280 9-Blt Odd/ Even Parity Generator/Checker 3-238 

MM54HC283/MM74HC283 4-Bit Binary Adder with FastCarry 3-241 

MM64HC298/MM74HC298 Quad 2-Input Multiplexers with Storage 3-246 

MM54HC299/MM74HC299 8-Bit TRI-STATE Universal Shift Register 3-250 

MM54HC354/MM74HC354 8-Channel TRI-STATE Multiplexers with Latches 3-255 

MM54HC356/MM74HC356 8-Channel TRI-STATE Multiplexers with Latches 3-255 

MM54HC365/MM74HC365 Hex TRI-STATE Buffer 3-263 

MM54HC366/MM74HC366 Inverting Hex TRI-STATE Buffer 3-263 

MM54HC367/MM74HC367 Hex TRI-STATE Buffer 3-263 

MM54HC368/MM74HC368 Inverting Hex TRI-STATE Buffer 3-263 

MM54HC373/MM74HC373 TRI-STATE Octal D-Type Latch 3-270 

MM54HC374/MM74HC374 TRI-STATE Octal D-Type Flip-Flop 3-273 

MM54HC390/MM74HC390 Dual 4-Bit Decade Counter 3-276 

MM54HC393/MM74HC393 Dual 4-Bit Binary Counter 3-276 

MM64HC423A/MM74HC423A Dual Retriggerable Monostable Multivibrator 3-281 

. MM54HC521/MM74HC521 8-Bit Magnitude Comparator (Equality Detector) 3-286 

MM54HC533/MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs 3-289 

MM54HC534/MM74HC534 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs 3-292 

MM54HC540/MM74HC540 Inverting Octal TRI-STATE Buffer 3-295 

MM54HC541/MM74HC541 Octal TRI-STATE Buffer 3-295 

MM54HC563/MM74HC563 TRI-STATE Octal D-Type Latch with Inverted Outputs 3-298 

MM54HC564/MM74HC564 TRI-STATE Octal D-Type Flip-Flip with Inverted Outputs 3-301 

MM54HC573/MM74HC573 TRI-STATE Octal D-Type Latch 3-304 

MM54HC574/MM74HC574TRI-STATE Octal D-Type Flip-Flop 3-307 

MM54HC589/MM74HC589 8-Bit Shift Register with Input Latches and 

TRI-STATE Serial Output 3-310 

MM54HC590/MM74HC590 8-Blt Binary Counter with TRI-STATE Output Register 3-315 

MM54HC592/MM74HC592 8-Bit Binary Counter with Input Register 3-317 

MM54HC593/MM74HC593 8-Blt Binary Counter with Bidirectional 
Input Register/Counter Outputs ^ 3-317 


3-5 





Section Contents (Continued) 

MM54HC595/MM74HC595 8-Bit Shift Registers with Output Latches 3-320 

MM54HC597/MM74HC597 8-Bit Shift Registers with Input Latches 3-325 

MM54HC640/MM74HC640 Inverting Octal TRI-STATETransceiver 3-330 

MM54HC643/MM74HC643True-lnvertingOctalTRI-STATETransceiver 3-330 

MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers 3-334 

IVIM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers 3-334 

f(/1M54HC688/MM74HC688 8-Blt Magnitude Comparator(Equality Detector) 3-341 

MM54HC4002/MM74HC4002 Dual 4-Input NOR Gate 3-357 

MM54HC4016/MM74HC4016 Quad Analog Switch ! 3-360 

MM54HC4017/MM74HC4017 Decade Counter/Divider with 10 Decoded Outputs 3-365 

MM54HC4020/MM74HC4020 14-Stage Binary Counter 3-369 

MM54HC4024/MM74HC4024 7-Stage Binary Counter 3-369 

MM54HC4040/MM74HC4040 12-Stage Binary Counter 3-369 

MM54HC4046/MM74HC4046 CMOS Phase Lock Loop 3-374 

MM54HC4049/MM74HC4049 Hex Inverting Logic Level Down Converter 3-383 

MM54HC4050/MM74HC4050 Hex Logic Level Down Converter 3-383 

MM54HC4051/MM74HC4051 8-Channel Analog Multiplexer 3-386 

MM54HC4052/MM74HC4P52 Dual 4-Channel Analog Multiplexer / 3-386 

MM54HC4053/MM74HC4053Triple2-Channel Analog Multiplexer 3-386 

MM54HC4060/MM74HC4060 14-Stage Binary Counter 3-393 

MM54HC4066/MM74HC4066 Quad Analog Switch 3-397 

MM54HC4075/MM74HC4075Triple3-lnputORGate 3-402 

MM54HC4078/MM74HC4078 8-Input NOR/OR Gate ; 3-405 

MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator 3-408 

MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver 3-413 

MM54HC4514/MM74HC4514 4-to-16 Line Decoder with Latch 3-418 

MM54HC4538/MM74HC4538Dual Retriggerable Monostable Multivibrator 3-422 

MM54HC4543/MM74HC4543 BCD-to-7 Segment Latch/Decoder/Driver for 

Liquid Crystal Displays '. 3-428 

MM74HC942 300 Baud Modem ( + 5, -5 Volt Supply) 3-344 

MM74HC943 300 Baud Modem (5 Volt Supply) 3-350 


3-6 




National 
Semiconductor 

MM54HC00/MM74HC00 
Quad 2-Input NAND Gate 

General Description 

These NAND gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. All gates have buffered 
outputs. All devices have high noise immunity and the ability 
to drive 10 LS-TTL loads. The 54HC/74HC logic family is 
functionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 

Connection and Logic Diagrams 



microCMOS 


Features 

■ Typical propagation delay: 8 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 fxA maximum (74HC Series) 

■ Low input current: 1 julA maximum 

■ Fanout of 10 LS-TTL loads 



Dual-ln-Line Package 



Top View 

Order Number MM54HC00J or MM74HC00J, N 
See NS Package J14A or N14A 



TL/F/5292-2 



3-7 


MM54HC00/MM74HC00 



MM54HC00/MM74HC00 




Maximum Low Level 
Output Voltage 

Vin = V,h 
| loUTk20 ju,A 


V|N = V|H 
|louTk4.0 mA 
liouTl^s.a mA 


l|N 

Maximum Input 
Current 

V|N = Vcc or GND 

6.0V 


±0.1 

•cc 

Maximum Quiescent 
Supply Current 

V|N = VccorGND 
•oUT=0 M-A 

6.0V 


2.0 


Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: -12 mW/*C from SS'C to 85®C; ceramic “J” package: -12 mW/*C from 100*C to 125“C. 
Note 4; For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when 
designing with this supply. Worst case V|h and V|l occur at Vcc=5.5V.and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, 
Icci and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-8 

























































AC Electrical Characteristics vcc= 5 v,TA= 25 ”c,CL=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tpHL. tPLH 

Maximum Propagation 
Delay 


8 

15 

ns 


AC Eiectrical Characteristics Vcc=2.0V to 6.0V, Cl =50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Paranjeter 

Conditions 

Vcc 

Ta=25X 

74HC 

Ta=- 40 to 85°C 

54HC 

Ta=- 55 to 125“C 

Units 

Typ 

Guaranteed Limits 

tpHL. tpLH 

Maximum Propagation 


2.0V 

45 

90 

113 

134 

ns 


Delay 


4.5V 

9 

18 

23 

27 

ns 




6.0V 

8 

15 

19 

' 23 

ns 


Maximum Output Rise 


2.0V 

30 

75 

95 

110 

ns 


and Fall Time 


4.5V 

8 

15 

19 

22 

ns 




6.0V 

7 

13 

16 

19 

ns 

CpD 

Power Dissipation 

(per gate) 



■ 



pF 


Capacitance (Note 5) 




■ 




C|N 

Maximum Input 


■■I 

5 


. 10 

10 

pF 


Capacitance 


Hi 







Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f+ Iqc Vcc. and the no load dynamic current consumption, ls=CpD Vcc t+ Icc- 




MM54HCOO/MM74HCOO 












MM54HC02/MM74HC02 


National 

Semiconductor 


MM54HC02/MM74HC02 Quad 2-Input 
NOR Gate 


microCMOS 


General Description 

These NOR gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. All gates have buffered 
outputs, providing high noise immunity and the ability to 
drive 1 0 LS-TTL loads. The 54HC/74HC logic family Is func- 
tionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 

Connection and Logic Diagrams 


Features 

■ Typical propagation delay: 8 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent supply current: 20 fiA ^naximum 
(74HC Series) 

■ Low input current: 1 juA maximum 

■ High output current: 4 mA minimum 


VCC Y4 


Dual-In-Line Package 
B4 A4 Y3 



Top View 

Order Number MM54HC02J or MM74HC02J, N 
See NS Package J14A or N14A 


3-10 



Absolute Maximum Ratings (Notes i & 2) 

Operating Conditions 



Supply Voltage (Vec) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1-5V 

Supply Voltage (Vec) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vec + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(ViN. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (T^) 




DC Vec or GND Current, per pin (Ice) 

±50 mA 

MM74HC 

-40 

±85 

“C 

Storage Temperature Range (Tstg) 

-65°Cto +150°C 

MM54HC 

-55 

±125 

“C 

Power Dissipation (Pq) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temp. (Tl) (Soldering 10 seconds) 

260“C 

(tr.tf) Vcc=2.0V 


1000 

ns 



Vcc=4.5V 


500 

ns 



Vec = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta = 

= 25X 

74HC 

Ta= -40 to 85X 

54HC 

TA=-55to125X 

Units 






Guaranteed Limits 


Vih 

Minimum High Level ‘ 



nil 

■9 


1.5 

V 


Input Voltage 




BE9 


3.15 

V 





n 

ig 


4.2 

V 

V|L 

Maximum Low Level 




0.3 

0.3 

0.3 

V 


Input Voltage 




0.9 

0.9 

0.9 

V 




6.0V 

HI 

1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

Vin=V|l 








Output Voltage 

|IoutN20 ixA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V,L 
|IoutI^ 4.0 mA 

^g9 


3.98 

3.84 

3.7 

V 



^^OUTi^5.2 mA 



5.48 

5.34 

5.2 

V 

VoL 

Maximum Low Level 

V|N = V|H orViL 








Output Voltage 

lloUll^SOfiA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



ViN = V|HOrV|L 
|IoutI^ 4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



jlouTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum Input 
Current 

V|N = Vcc Of GND 

6.0V 


±0.1 

±1.0 

±1.0 

jiiA 

•cc 

Maximum Quiescent 

V|N ” Vcc Of GND 

6.0V 


2.0 

20 

40 



Supply Current 

•oUT~6 mA 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: ' Power Dissipation temperature derating — plastic "N” package; - 1 2 mW/°C from 65°C to 85®C; ceramic “J” package: - 1 2 mW/*C from 1 00°C to 1 25*C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when 
designing with this supply. Worst case V(h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The Vih value at 5.5V is 3.85V.) The worst case leakage current (I|n. 
Ice. and Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-11 


MM54HC02/MM74HC02 




















MM54HC02/MM74HC02 


AC Electrical Characteristics vcc= 5 v,TA= 25 “c,CL=i 5 pF,tr=t,= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tpLH 

Maximum Propagation 
Delay 


8 

15 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 25“C 

74HC 

TA=-40to85“C 

Ta = 

54HC 

-55 to125“C 






Typ 

Guaranteed Limits 


tpHL. tpLH 

Maximum Propagation 


2.0V 

45 

90 

113 


134 

s 


Delay 


4.5V 

9 

18 

23 


27 





6.0V 

8 

15 

19 


23 

WM 

triH. tjHL 

Maximum Output Rise 


2.0V 

30 

75 

95 


110 

mS 


and Fall Time 


4.5V 

8 

15 

19 


22 

RH 




6.0V 

7 

13 

16 


19 

■1 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 



■ 



pF 

C|N 

Maximum Input 
Capacitance 



5 

10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f+ Ice Vcc. and the no load dynamic current consumption, ls=CpD Vec t+ Icc- 


3-12 











National 


Semiconductor 

V J 


microCMOS 


MM54HC03/MM74HC03 Quad 2-Input 
Open Drain NAND Gate 


General Description 

These NAND gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. All gates have buffered 
outputs. All devices have high noise immunity and the ability 
to drive 10 LS-TTL loads. The 54HC/74HC logic family Is 
functionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 

As with standard 54HC/74HC push-pull outputs there are 
diodes to both Vcc and ground. Therefore the output should 
not be pulled above Vcc as it would be clamped to one 
diode voltage above Vcc- This diode is added to enhance 
electrostatic protection. 


Features 

■ Typical propagation delay: 12 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 ixA maximum (74HC Series) 

■ Low input current: 1 juA maximum 

■ Fanout of 10 LS-TTL loads 


Connection and Lopic Diagrams 


Dual-ln-Line Package 



Top View 

Order Number MM54HC03J or MM74HC03J,N 
See NS Package J14A or N14A 


A 

B 



TL/F/5295-2 



3-13 


MM54HC03/MM74HC03 



MM54HC03/MM74HC03 


Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqijt) 

Clamp Diode Current (1 |k, Iqk) 

-0.5to VCC+0.5V 
±20 mA 

DC Input or Output Voltage 
(Vin.Vout) 

0 

Vcc 

V 

DC Output Current, per pin (Iqut) 

±25 mA 




DC Vcc or GND Current, per pin (Ice) 

±50 mA 

Operating Temp. Range (Ta) 




Storage Temperature Range (Tstg) 

-65“Cto ±150“C 

MM74HC 

-40 , 

+ 85 

°C 

Power Dissipation (Pq) (Note 3) 

500 mW 

MM54HC 

-55 

+ 125 

”C 

Lead Temp. (TO (Soldering 10 seconds) 

260“C 

Input Rise or Fall Times 






> 

0 

c\i 

II 

0 


1000 

ns 



Vcc = 4.5 V 


500 

ns 



Vcc=6.0V 


400 

ns 


DC Electrical Characteristics (Note 4 ) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25°C 

74HC 

Ta=- 40 to 85“C 

54HC 

Ta=- 55 to125X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 



Input Voltage 


4.5V 


3.15 

3.15 

3.15 





6.0V 


4.2 

4.2 

4.2 


V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|HOrV|L 








Output Voltage 

|IoutI^ 20 p.A 

2.0V 

2.0 

1.9 

1.9 

1.9 




Rl=i kn 

4.5V 

4.5 

4.4 

4.4 

4.4 





6.0V 

6.0 

5.9 

5.9 

5.9 


Vql 

Minimum Low Le\^l 

V|N = V|H 








Output Voltage 

|IoutI^ 20 fi,A 

2.0V 

0 

0.1 

0.1 

0.1 

V 



Rl= oo 

4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V,h 
l•oUTl^4.0 mA 

4.5V 

0.2 

0.26 

0.33 i 

0.4 

V 



i•0UTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

Ilkg 

Maximum High Level 

ViN = V|HorV|L 

6.0V 


0.5 

5 

10 

, JLtA 


Output Leakage Current 

VouT = Vcc 







•in 

Maximum Input 

Current 

V|N~ Vcc Oi' OND 

6.0V 

, 

±0.1 

±1.0 

±1.0 

jjlA 

•cc 

Maximum Quiescent 

V|N~ Vcc 0*' GND 

6.0V 


2.0 

20 

40 

jllA 


Supply Current 

IOUT = 0 P-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3; Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/“C from 65®C to BS'C; ceramic “J” package: - 1 2 mW/*C from 1 0O’C to 1 25*0. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh, and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-14 








AC Electrical Characteristics vcc= 5 v.TA= 25 “c,CL=i 5 pF.tr=t,= 6 ns 




Conditions 

Typ 

Guaranteed 

Limit 

Units 

tpHL. tPLH 

Maximum Propagation 
Delay 

Rl=i Kn 

10 

20 

ns 


AC Electrical Characteristics 

Vcc=2.0V to 6.0V, Cl = 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

1 

Conditions 

Vcc 

Ta = 

25X 

74HC 

Ta=-40 to 85X 

Ta = 

54HC 

-55 to125X 

Units 





Typ 

Guaranteed Limits 


fpHL. tpLH 

Maximum Propagation 

Rl=i Kn 

2.0V 

63 

125 

158 


186 

ns 


Delay 


4.5V 

13 

25 

32 


37 

ns 




6.0V 

11 

21 

27 


32 

ns 

tTHL 

Maximum Output 


2.0V' 

30 

75 

95 


110 

ns 


Fall Time 


4.5V 

8 

15 

19 


22 

ns 




6.0V 

7 

13 

16 


19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 


20 




pF 

ClN 

Maximum Input 
Capacitance 



5 

10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd = Cpd Vcc^ f + Icc Vcc. and the no load dynamic current consumption, ls = Cpo Vcc f + IcC- 
The power dissipated by Rl is not included. 



3-15 


MM54HC03/MM74HC03 





MM54HC04/MM74HC04 


National 
Semiconductor 

MM54HC04/MM74HC04 Hex Inverter 

General Description 

These inverters utilize microCMOS Technology, 3.5 micron 
silicon gate P-weli CMOS, to achieve operating speeds simi- 
lar to LS-TTL gates with the low power consumption of stan- 
dard CMOS integrated circuits. 

The MM54HC04/MM74HC04 is a triple buffered Inverter. It 
has high noise immunity and the ability to drive 10 LS-TTL 
loads. The 54HC/74HC logic family is functionally as well as 
pin-out compatible with the standard 54LS/74LS logic fami- 
ly. All inputs are protected from damage due to static dis- 
charge by Internal diode clamps to Vcc and ground. 


Connection and Logic Diagrams 

Duai-ln-Line Package 


Vcc A6 Y6 A5 Y5 A4 Y4 



Features 

■ Typical propagation delay: 8 ns 

■ Fan out of 10 LS-TTL loads 

■ Quiescent power consumption: 10 jaW maximum at 
room temperature 

■ Typical Input current: 10-5 juiA 



microCMOS 



Order Number MM54HC04J or MM74HC04J, N 
See NS Package J14A or N14A 


1 of 6 inverters 



3-16 



Absolute Maximum Ratings (Notes i & 2) Operating Conditions 


Supply Voltage (Vec) 

-0.5 to -f-7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1.5V 

Supply Voltage (Vec) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vec 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 




DC Vec or GND Current, per pin (Ice) 

±50 mA 

MM74HC 

-40 

±85 

°c 

Storage Temperature Range (Tstg) 

-65'’Cto +150“C 

MM54HC 

-55 

±125 

°c 

Power Dissipation (Pd) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temperature (TO 


> 

0 

evi 

II 

0 

0 

> 


1000 

ns 

' (Soldering 1 0 seconds) 

260“C 

Vec = 4.5V 


500 

ns 


, 

Vec = 6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 






Ta = 

25X 

74HC 

54HC 


Symbol 

Parameter 

Conditions 

Vcc 

Ta=- 40 to 85°C 

Ta=~ 55 to125°C 

Units 





Typ 

Guaranteed Limits 


■V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 , 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 




0.3 



Input Voltage 


4.5V 




0.9 





6.0V 


■a 


1.2 


Vqh 

Minimum High Level 

V|N = V,L 



■i 

||■|■|||■||| 




Output Voltage 

IIoutI^SO fiA 

2.0V 

2.0 

iii 


1.9 

V 




4.5V 

4.5 



4.4 





6.0V 

6.0 



5.9 




ViN = V|L 
|IoutI^ 4.0 mA 

M 

4.2 

3.98 

3.84 

3.7 

■ 



i•0UTi^6.2 mA 

Hi 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|n = V,h 








Output Voltage 

|louTl^20fxA 

2.0V 

0 

0.1 


0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



Vin = V,h 
|IoutN 4.0 mA 

4.5V 


0.26 

0.33 

0.4 

V 



ilouTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

•in 

Maximum Input 
■Current 

V|N = Vcc or GND 

6.0V 



±1.0 



•cc 

Maximum Quiescent 

V|N “ Vcc or GND 

6.0V 



20 

40 



Supply Current 









Note 1; Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating -- plastic “N” package: -12 mW/*C from 65"C to 85'C: ceramic “J” package: - 12 mW/“C from 100*C to 125®C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-17 


MM54HC04/MM74HC04 





















MM54HC04/MM74HC04 


AC Electrical Characteristics vcc= 5 v,TA= 25 »c,cu=i 5 pF,t,=t,= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tpLH 

Maximum Propagation 
Delay 


8 


ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl= 50 pF, tr=tf =6 ns (unless otherwise specified) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta=25X 

74HC 

Ta=- 40 to 85X 

Ta=- 

54HC 

-55 to 125X 

Units 





Typ 

Guaranteed Limits 


tPHL. tpLH 

Maximum Propagation 


2.0V 



120 


145 

ns 


Delay 


4.5V 


19 

24 


*29 

ns 




6.0V 

HI 

H 

20 


24 

ns 

tlLH- tlHL 

Maximum Output Rise 


2.0V 



95 


110 

ns 


and Fall Time 


4.5V 



19 


22 

ns 




6.0V 



16 


, 19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 



1 



pF 

C|N 

Maximum Input 
Capacitance 





10 

10 

pF 


Note 5: CpQ determines the no load dynamic power consumption, Pd=Cpd Vcc^ f + Ice Vcc. and the no load dynamic current consumption, ls= Cpo Vec f + Icc- 


3-18 






National 

Semiconductor 


MM54HCU04/MM74HCU04 Hex Inverter 



microCMOS 


General Description 

These inverters utilize microCMOS Technology, 3.5 micro 
silicon gate P-well CMOS, to achieve operating speeds simi- 
lar to LS-TTL gates with the low power consumption of stan- 
dard CMOS integrated circuits. 

The MM54HCU04/MM74HCU04 is an unbuffered inverter. 
It has high noise immunity and the ability to drive 15 LS-TTL 
loads. The 54HCU/74HCU logic family is functionally as 
well as pin-out compatible with the standard 54LS/74LS 


logic family. All inputs are protected from damage due to 
static discharge by internal diode clamps to Vcc and 
ground. 

Features 

■ Typical propagation delay: 7 ns 

■ Fanout of 1 5 LS-TTL loads 

■ Quiescent power consumption: 10 juA maximum at 
room temperature 

■ Typical input current: 10-5 ju, A 


Connection and Schematic Diagrams 


Dual-lh-Line Package 

Vcc A6 Y6 AS Y5 A4 Y4 



TL/F/5296-1 


Order Number MM54HCU04J or MM74HCU04J, N 
See NS Package J14A or N14A 



TL/F/5296-2 



3-19 


MM54HCU04/MM74HCU04 





Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) “ 0-5 to + 7.0V 

DC Input Voltage (V|n) - 1 -5 to Vcc + 1 -SV 

DC Output Voltage (Vqut) - 0.5 to Vcc + 0.5V 

Clamp Diode Current (I|k, Iqk) ±20 mA 

DC Output Current, per pin (Iqut) ± 25 mA 

DC Vcc or GND Current, per pin (Ice) ±50 mA 

Storage T emperature Range (T stg) ~ 55"C to + 1 50“C 

Power Dissipation (Pp) (Note 3) 500 mW 

Lead Temp. (T i) (Soldering 1 0 seconds) 260°C 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(V|N. Vqut) 

Operating Temp. Range (Ta) 
MM74HCU -40 

MM54HCU -55 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

V|H 

Minimum High Level 


Input Voltage 

V|L 

Maximum Low Level 
Input Voltage 


T* = 25“C 

Conditions Vcc TA=-40to85°C Ta= - 55 to 125°C Units 

Typ I Guaranteed Limits 



VoL 

Maximum Low Level 
Output Voltage 

Vin=V,h 
|IoutN20 fiA 

2.0V 

4.5V 

6.0V 



V|N = Vcc 
|IoutI^5-0 itiA 
ibuTl^^.B mA 

4.5V 

6.0V 

•in 

Maximum Input 
Current 

V|N = Vqc or GND 

6.0V 


Maximum Quiescent 
Supply Current 

V|N = Vcc oi” GND 
Iqut^O /^A 

6.0V 



3.7 

V 

5.2 

V 

0.2 

V 

0.5 

V 

0.5 

V 

0.4 

V 

0.4 

V 

±1.0 

JLtA 

40 

fxA 


Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/*C from SS'C to 85*0; ceramic "J” package: - 1 2 mW/*C from 1 00“C to 1 25*C. 
Note 4: For a power supply of 5V ± 1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|l occur at Vcc=5.5V and 4.5Y respectively. (The Vm value at 5.5V is 3.85V;) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-20 




















AC Electrical Characteristics vcc= 5 v,TA= 25 “c,CL=i 5 pF,tr=t,= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tpLH 

Maximum Propagation 
Delay 


■ 


ns 


AC Electrical Characteristics Vcc = 2.0V to 6.0V, Cl= 50 pF, tr=tf=6 ns (unless othenvise specified) 



Parameter 

Conditions 

! 

Vcc 

Ta = 25X 

74HCU 

TA=-4pto85X 

Ta = 

54HCU 
-55 t0l25X 

Units 






Guaranteed Limits 


tPHb tPLH 

Maximum Propagation 


[RR9 

49 

82 

103 


120 

ns 


Delay 



9.9 

16 

21 


24 

ns 





8.4 

14 

18 


20 

ns 

tTLH. tTHL 

Maximum Output Rise 


jRRflj 

30 




110 

ns 


and Fall Time 



8 




22 

ns 





7 




19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 

■ 

90 




pF 

CiN 

Maximum Input 
Capacitance 


■ 

8 

15 

15 

15 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd = C po Vcc^ f + Icc Vcc. and the no load dynamic current consumption. Is = Cpo Vcc Icc- 


Typical Applications 


R2-10Mn 



TL/F/5296-3 



= C 

R2 

Ri 

I 



■VOUT 


TL/F/5296-4 


FIGURE 2. Stable RC Oscillator 


Ri 

V(N-- - vW* 


R2 

VW 


R2 > 6R^ 


VquT 


FIGURE 3. Schmitt Trigger 


TL/F/5296-5 



3-21 


MM54HCU04/MM74HCU04 





















MM54HC08/MM74HC08 


National 

Semiconductor 

^ ^ ^ 


microCMOS 


MM54HC08/MM74HC08 
Quad 2-Input AND Gate 

General Description 

These AND gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. The HC08 has buffered 
outputs, providing high noise immunity and the ability to 
drive 10 LS-TTL loads. The 54HC/74HC logic family is func- 
tionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 

Connection Diagram 

Dual-ln-Line Package 

Vcc B4 A4 Y4 B3 A3 Y3 



A1 B1 Y1 A2 B2 Y2 GNO 

TL/F/5297-1 

Top View 

Order Number MM54HC08J or MM74HC08J, N 
See NS Package J14A or N14A 


Features 

■ Typical propagation delay: 7 ns (tpHt). 12 ns (tpLH) 

■ Fanout of 10 LS-TTL loads 

■ Quiescent power consumption: 2 jiiA maximum at room 
temperature 

■ Typical input current: 10 “5 


3-22 



Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vec) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5toVcG+1.5V 

Supply Voltage (Vec) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vec + 0.5V 

DC Input or Output Voltage 

0 

Vec 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA- 

Operating Temp. Range (Ta) 




DC Vec or GND Current, per pin (Ice) 

±50 mA 

MM74HC 

-40 

+ 85 

‘’C 

Storage Temperature Range (Tstg) 

-65“Cto +150“C 

MM54HC 

-55 

+ 125 

“C 

Power Dissipation (Pq) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temp. (Tl) (Soldering 10 seconds) 

260“C . 

(tr.tf) Vec = 2.0V 


1000 

ns 



Vec = 4.5 V 


500 

ns 



, Vec = 6.0V 


400 

ns 


DC Eiectricai Characteristics (Note 4) 


Symboi 

Parameter 



B 









PB 

Guaranteed Limits 


V(H 

Minimum High Level 



n 

■a 

■■H 




Input Voltage 


WSm 


EQ 













VlL 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|H 








Output Voltage 

|louTk20 fxA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V,h 
|IoutN 4.0 mA 

4.5V 

4.2 

3.98 


3.7 

V 



i^OUT^^6.2 mA 

6.0V 

5.7 

5.48 


5.2 

V 

VoL 

Maximum Low Level 

ViN=V|HorV|L 








Output Voltage 

lloUll^SOfiA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



ViN=ViH orViL 
|Iout 1^4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



IJoutI^ 5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum Input 
Current 

Vifvi = Vec oi" GND 



H 




■cc 

Maximum Quiescent 

ViN=Vcc or GND 

6.0V 



20 

40 



Supply Current 

IOUT=0 M-A 



nn 





Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: -12 mW/'C from eS'C to 85*C; ceramic “J” package: - 12 mW/“C from 100®C to 125®C. 
Note 4: For a power supply of 5V ± 1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc=5-5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (Iin, Ice. and 
•oz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-23 


MM54HC08/MM74HC08 





















MM54HC08/MM74HC08 


AC Electrical Characteristics vcc=5v.ta=25»c. cl= 15 pF.tr=tt =6 ns 


Symbol 

Parameter 

Conditions 

Typ 



tpHL 

Maximum Propagation 
Delay, Output High to Low 


12 

20 

ns 

fpLH 

Maximum Propagation 
Delay, Output Low to High 


7 

15 

ns 


AC Electrical Characteristics Vcc= 2.0V to 6.0V, Cl= 50 pF, tr= tf = 6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25X 

74HC 

Ta=~ 40 to 85"C 

54HC 

Ta=- 55 tOl25‘’C 

Units 





Typ 

Guaranteed Limits 


fPHL 

Maximum Propagation 


2.0V 

Wi 


151 

175 

■■ 


Delay, Output High to Low 


4.5V 

19 


30 

35 

wm 




6.0V 

0 


25 

30 . 

mm 

fpLH 

Maximum Propagation 


2.0V 




134 

ns 


Delay, Output 


4.5V 




27 

ns 


Low to High 


6.0V 

8 



23 

ns 

tlLH. flHL 

Maximum Output Rise 


2.0V 

30 


95 

110 

■1 


and Fall Time 


4.5V 


^^9 

19 

22 

BS 




6.0V 



16 

19 

MM 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 


38 




pF 

C|N 

Maximum Input 

Capacitance 



B 


10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f+ Ice Vcc. arid the no load dynamic current consumption, ls= Cpc Vec f + Icc- 


3-24 


















National 

Semiconductor 


MM54HC10/MM74HC10 
Triple 3-Input NAND Gate 

General Description 

These NAND gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. All gates have buffered 
outputs. All devices have high noise immunity and the ability 
to drive 10 LS-TTL loads. The 54HC/74HC logic family Is 
functionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by Internal diode clamps to Vcc 
and ground. 

Connection and Logic Diagrams 



microCMOS 


Features 

■ Typical propagation delay: 8 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 jitA maximum (74HC Series) 

■ Low input current: 1 fxA maximum 

■ Fanout of 10 LS-TTL loads 



Dual-ln-Line Package 



Top View 

Order Number MM54HC10J or MM74HC10J,N 
See NS Package J14A or N14A 


TL/F/5153-1 




3-25 


MM54HC10/MM74HC10 



MM54HC10/MM74HC10 


Absolute Maximum Ratings (Notes 1 & 2) 


Supply Voltage (Vcc) 

DC Input Voltage (V|n) 

DC Output Voltage (Vqut) 

Clamp Diode Current (I|k, Iqk) 

DC Output Current, per pin (Iqlit) 

DC Vcc oi' GND Current, per pin (Ice) 
Storage Temperature Range (Tstg) 
Power Dissipation (Pq) (Note 3) 

Lead Temperature (T|J . 

(Soldering 1 0 seconds) 


-0.5 to +7.0V 
-1.5toVcc+1.5V 
-0.5 to Vcc + 0.5V 
±20 mA 
±25 mA 
±50 mA 
-65"Cto +150“C 
500 mW 


DC Electrical Characteristics (Note 4) 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(V|N. Vqut) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 

Input Rise or Fall Times 
(tr.tf) Vcc=2.0V 
Vcc = 4.5 V 
Vcc = 6.0 V 


74HC 54HC 

TA=-40to85X TA=-55to125°C Units 

Guaranteed Limits 




0.3 

0.3 

V 

0.9 

0.9 

V 

1.2 

1.2 

V 


Minimum High Level 
Output Voltage 


V|N = V|H orViL 
|louTk20 }lA 


V|N=ViH orViL 
|louTk4.0 mA 
'■ k 5.2 mA 


Maximum Low Level 
Output Voltage 

VlN = V|H 
|ioUTk20 ixA 


V|N=ViH 
IIoutI^^.O mA 


Maximum input 
Current 



V|N = VccorGND 6.0V 


Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified ail voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: - 12 mW/^C from 65®C to 85®C; ceramic “J” package: - 1 2 mW/*C from 1 00®C to 1 25®C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc = 5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage curreht (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-26 





















AC Electrical Characteristics vcc= 5 v,TA= 25 »c,CL=i 5 pF.tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Q 


Units 

tpHL. fPLH 

Maximum Propagation 
Delay 


B 

15 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 25‘*C 

74HC 

Ta=-40 to 85“C 

54HC 

TA=-55to125°C 

Units 





Typ 

Guaranteed Limits 


fpHL. tpLH 

Maximum Propagation 


2.0V 

■ 1 


113 ’ 

134 

ns 


Delay 


4.5V 

■9 


23 

27 

ns 




6.0V 

8 


19 

23 

ns 

tlLH. fjHL 

Maximum Output Rise 


2.0V 

30 

75 

95 

110 



and Fall Time 


4.5V 

8 

15 

19 

22 





6.0V 

7 

13 

16 

19 


CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 

B 


9 



pF 

Qn 

Maximum Input 
Capacitance 


B 

5 

10 

10 

10 

pF 


Note 5: CpQ determines the no load dynamic power consumption, Pd=Cpd Vcc^f+IccVcc. and the no load dynamic current consumption, ls=CpD Vccf+Icc- 


( 


3 


3-27 


MM54HC10/MM74HC10 












MM54HC11/MM74HC11 


National 
Semiconductor 

MM54HC11/MM74HC11 
Triple 3-Input AND Gate 

General Description 

These AND gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS Integrated circuits. All gates have buffered 
outputs, providing high noise immunity and the ability to 
drive 1 0 LS-TTL loads. The 54HC/74HC logic family is func- 
tionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 



microCMOS 


Features 

■ Typical propagation delay: 12 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 fxA maximum (74HC Series) 

■ Low input current: 1 juA maximum 

■ Fanout of 1 0 LS-TTL loads 



Connection and Logic Diagrams 

Dual-In-Line Package 


Vcc Cl Y1 C3 B3 A3 Y3 



Top View 


TL/F/5298-1 


Order Number MM54HC11J or MM74HC11J, N 
See NS Package J14A or N14A 



TL/F/5298-2 


3-28 



Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to +7,0V 


Min 

Max 

Units 

DC Input Voltage (Vin) 

-1.5toVcc+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (Iik, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (T^) 




DC Vcc or GND Current, per pin (Icc) 

±50 mA 

MM74HC 

-40 

±85 

°c 

Storage Temperature Range (Tstg) 

,-65“Cto ±150°C 

MM54HC 

-55 

±125 

°c 

Power Dissipation (Pd) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temperature (TJ 


(tr.tf) Vcc=2.0V 


1000 

ns 

(Soldering 1 0 seconds) 

260‘’C 

Vcc = 4.5 V 


500 

ns 



Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25'’C 

74HC 

Ta=- 40 to 85X 

54HC 

Ta=- 55 to125'’C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

VlL 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

VlN = V|H 








Output Voltage 

|louTk20 }xA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

.5.9 

5.9 

5.9 

V 



V|N = V|H 









|louTk4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



i•0UTl^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|n = V|h or V|L 








Output Voltage 

|louTk20 ixA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|HOrV|L 
|louTk4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



i•0UTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

•in 

Maximum Input 
Current 

V|N = Vcc or GND 

6.0V 


±0.1 

±1.0 

±1.0 

jiiA 

•cc 

Maximum Quiescent 

V|N = Vcc or GND 

6.0V 


2.0 

20 

40 

jliA 


Supply Current 

Iqut^O M-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic "N” package: -12 mW/'C from 65*C to SS^C; ceramic “J” package: - 12 mW/®C from 100“C to 125*C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Icc. and 
loz) occur for CMO? at the higher voltage and so the 6.0V values should be used. 


3-29 


MM54HC11/MM74HC11 



MM54HC11/MM74HC11 


AC Electrical Characteristics vcc= 5 v,TA= 25 "c,CL=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tpHL. tpLH 

Maximum Propagation 
Delay 


12 

20 

ns 


AC Electrical Characteristics 

Vcc=2.0V to 6.0V, Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vec 

Ta= 

25X 

74HC 

TA=-40tO 85X 

Ta= 

54HC 

-55tOl25X 

Units 





Typ 

Guaranteed Limits 


tpHL. tpLH 

Maximum Propagation 


2.0V 

■Qj 


156 


190 

WM 


Delay 


4.5V 



31 


38 





6.0V 



27 


31 

WM 

tjLH. tlHL 

Maximum Output Rise 


2.0V 

30 

WM 

95 


110 

mS 


and Fall Time 


4.5V 

8 

mm 

19 


22 





6.0V 

7 

13 

16 


19 

■■ 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 


35 




pF 

C|N 

Maximum Input 
Capacitance 



5 

10 

10 

10 

pF 


Note 5: Cpp determines the no load dynamic power consumption, Pq = Cpp Vcc^ f + Ice Vcc« and the no load dynamic current consumption, is = Cpp Vec t + Icc- 


3-30 


















^1 National 
mSi Semiconductor 


microCMOS 


MM54HC14/MM74HC14 
Hex Inverting Schmitt Trigger 

General Description I 

The MM54HC14/MM74HC14 utilizes microCMOS Technol- 
ogy, 3.5 micron silicon gate P-well CMOS, to achieve the 
low power dissipation and high noise immunity of standard 
CMOS, as well as the capability to drive 1 0 LS-TTL loads. 

The 54HC/74HC logic family is functionally and pinout com- 
patible with the standard 54LS/74LS logic family. All inputs 
are protected from damage due to static discharge by inter- 
nal diode clamps to Vcc and ground. 

Connection and Schematic Diagrams 


Features 

■ Typical propagation delay: 13 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 ju,A maximum (74HC Series) 

■ Low input current: 1 jaA maximum 

■ Fanout of 10 LS-TTL loads 

■ Typical hysteresis voltage: 0.9V at Vcc = 4.5V 


Duai-ln-Line Package 



A1 Y1 A2 Y2 A3 Y3 GND 
Top View 

Order Number MM54HC14J or MM74HC14J,N 
See NS Package J14A or N14A 



Vcc Vcc 


3-31 


MM54HC14/MM74HC14 



MM54HC14/MM74HC14 


Absolute Maximum Ratings 

‘ Supply Voltage (Vcc) 

DC Input Voltage (V|n) 

DC Output Voltage (Vqut) 

Clamp Diode Current (I|k, Iqk) 

DC Output Current, per pin (Iqui) 

DC Vcc or GND Current, per pin (Ice) 

Storage Temperature Range (Tstg) 

Power Dissipation (Pp) (Note 3) 

Lead Temp, (TO (Soldering 10 seconds) 


-65‘ 


(Notes 1 & 2) 
-0.5 to +7.0V 
to Vcc + 1.5V 
to Vcc "L 0.5V 
±20 mA 
±25 mA 
±50 mA 
Cto ±150“C 
500 mW 
260“C 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(ViN. Vqut) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 


Max 


Vcc 


±85 

±125 


Units 

V 

V 


“C 

“C 


DC Eiectrical Characteristics (Note 4) 






Ta= 

25“C 

74HC 

54HC 


Symbol 

Parameter 

Conditions 

Vcc 

TA=-40to 85“C 

Ta=- 55 toi25X 

Units 





Typ 

Guaranteed Limits 


Vt± 

Positive Going 

Minimum 

2.0V 

1.2 

1.0 

1.0 

1.0 

V 


Threshold Voltage 


4.5V 

2.7 

2.3 

2.3 

2.3 

' V 




6.0V 

3.2 

2.7 

2.7 

2.7 

V 



Maximum 

2.0V 

1.2 

1.5 

1.5 

1.5 

V 




4.5V 

2.7 

3.15 

3.15 

3.15 

V 




6.0V 

3.2 

4.2 

4.2 

4.2 

V 

Vt- 

Negative Going 

Minimum 

2.0V 

0.7 



0.3 

V 


Threshold Voltage 


4.5V 

1.8 



0.9 

V 




6.0V 

2.2 



1.2 

V 



Maximum 

2.0V 

0.7 


1.0 


V 




4.5V 

1.8 


2.2 


V 




6.0V 

2.2 

WM 

2.7 


V 

Vh . 

Hysteresis Voltage 

Minimum 

2.0V 

0.5 

0.2 

0.2 

0.2 

V 




4.5V 

0.9 

0.4 

0.4 

0.4 

V 




6.0V 

1.0 

0.6 

0.6 

0.6 

V 



Maximum 

2.0V 

0.5 

1.2 

1.2 

1.2 

V 




4.5V 

0.9 

2.25 

2.25 

2.25 

V 




6.0V 

1.0 

3.0 

3.0 

3.0 ( 

V 

Vqh 

Minimum High Level 

V|N = V|L 








Output Voltage 

1Iout 1 = 20 fiA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = ViL 

IIqutH 4.0 mA . 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



|louTi = 5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = ViH 

■1 







Output Voltage 

|IoutI = 20 jaA 


0 

0.1 

0.1 

0.1 

V 





0 

0.1 

0.1 

0.1 

V 





0 

0.1 

0.1 

0.1 

V 



V|N = V|H 
|IoutI = 4.0 mA 

M 

0.2 

0.26 

0.33 

0.4 

V 



|l 0 UTi = 5.2 mA 


0.2 

0.26 

0.33 

0.4 

V 

l|N 





±0.1 

±1.0 

±1.0 

juiA 

•cc 

Maximum Quiescent 

V|N“ Vcc 0*" GND 

6.0V 


2.0 

20 

40 

juA 


Supply Current 

Iout = 0M'A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/*C from 65°C to BS'C; ceramic “J" package: - 1 2 rnWrC from 1 0O^C to 1 25'C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when 
designing with this supply. Worst case V|h and V|l occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (Iin, 
Ice. and Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-32 















AC Electrical Characteristics vcc= 5 v.TA= 25 »c.cL=i 5 pF.v=tf= 6 ns 


Symbol 


Parameter 


Maximum Propagation Delay 


Conditions 


Guaranteed Limit 


22 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl =50 pF, tr = tf = 6 ns (unless otherwise specified) 


Symbol Parameter 

tpHL. tpLH Maximum Propagation 
Delay 


Conditions Vcc 


Ta = 

25"C 

74HC 

Ta=- 40 to 85“C 

54HC 

TA=-55to125“C 

Units 

Typ 

Guaranteed 

Limits 


60 

125 

156 

188 

ns 

13 

25 

31 

38 

ns 

11 

21 

26 

. 32 

ns 



Note 5: Cpo determines the no load dynamic power consumption, Pq = Cpo Vcc^ t+lcc Vcci and the no load dynamic current consumption, Is = 
CpoVccf+lcc- 


Typical Performance Characteristics 


Input Threshold, Vt+ , Vj-, 
vs Power Supply Voltage 



2.0 3.0 4.0 5.0 6.0 

POWER SUPPLY VOLTAGE (V) 


Propagation Delay vs 
Power Supply 



2.0 3.0 4.0 5.0 6.0 

POWER SUPPLY VOLTAGE (V) 


Typicai Appiications 

Low Power Oscillator 


:aaa 


Vt- 

. VcC-Vt- 


Vt4-(Vcc-Vt-) 

Vt- (Vcc-Vt + ) 

Note: The equations assume ti + tpdo + tpdt 


3-33 


MM54HC14/MM74HC14 











MM54HC20/MM74HC20 


National 
Semiconductor 

MM54HC20/MM74HC20 
Dual 4-input NAND Gate 

General Description 

These NAND gates utilize microCMOS Technology, 3.5 mi- 
cron silicon gate P-Well CMOS, to achieve operating 
speeds similar to LS-TTL gates with the low power con- 
sumption of standard CMOS integrated circuits. All gates 
have buffered outputs. All devices have high noise immunity 
and the ability to drive 10 LS-TTL loads. The 54HC/74HC 
logic family is functionally as well as pin-out compatible with 
the standard 54LS/74LS logic family. All inputs are protect- 
ed from damage due to static discharge by internal diode 
clamps to Vcc and ground. 



microCMOS 


Features 

■ Typical propagation delay: 12 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 jaA maximum (74HC Series) 

■ Low input current: 1 ju,A maximum 

■ Fanout of 10 LS-TTL loads 



Connection and Logic Diagrams 


Dual-In-Line Package 


Vcc DZ C2 NC BZ AZ YZ 



TL/F/5299-1 


Order Number MM54HC20J or MM74HC20J, N 
See NS Package J14A or N14A 




Y=:ABCD 


TL/F/5299-2 


3-34 



Absolute Maximum Ratings (Notes i & 2) 

Operating Conditions 



Supply Voltage (Vec) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to Vec + 1.5V 

Supply Voltage (Vec) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 toVGC + 0.5V 

DC Input or Output Voltage 

0 

Vec 

V 

Clamp Diode Current (I|k. Iqk) 

±20 mA 

(V(N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (T a) 




DC Vec or GND Current, per pin (Ice) 

±50 mA 

MM74HC 

-40 

+ 85 

“C 

Storage Temperature Range (Tsjq) 

-65‘’Cto +150'’C 

MM54HC 

-55 

+ 125 

°c 

Power Dissipation (Pq) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temp. (TJ (Soldering 10 seconds) 

260°C 

> 

o 

evi 

II 

o 

o 

> 


1000 

ns 



Vcc=4.5V 


500 

ns 



Vcc=6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symboi 

Parameter 

Conditions 


Ta = 

25X 

74HC 

Ta=- 40 to 85X 

54HC 

Ta=- 55 to125‘’C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 



m 

1.5 



V 


Input Voltage 




3.15 



V 




1^1 

IH 

4.2 



V 

V|L 

Maximum Low Level 


2.0V 


0.3 



V 


Input Voltage 


4.5V 


0.9 



V 




6.0V 


1.2 



V 

Vqh- 

Minimum High Level 

V|N = V|H orViL 








Output Voltage 

|IoutI^20 /xA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|HOrViL 
|IoutI^4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



jlouTi^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

VlN = V|H 



■I 





Output Voltage 

|louTk20 fxA 

2.0V 

0 

Bl 

0.1 

0.1 

V 




4.5V 

0 


0.1 

0.1 

V 




6.0V 

0 


0.1 

0.1 

V 



V|N = V|h 

1 10071^4.0 mA 

^^1 

0.2 

0.26 

0.33 

0.4 

V 



il0UTU5.2 mA 


0.2 

0.26 

0.33 

0.4 

V 

l|N 






±1.0 


jaA 

•cc 

Maximum Quiescent 

V|N “ Vec or GND 



2.0 

20 

40 

liA 


Supply Current 

IOUT=0 P-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 12 mW/'C from 65'C to 85"C: ceramic "J” package: - 12 mW/®C from lOO'C to 125*0. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when 
designing with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, 
Ice. and Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-35 


MM54HC20/MM74HC20 





















MMS4HC20/MM74HC20 


AC Electrical Characteristics vcx:= 5 v,TA= 25 '>c,CL=i 5 pF,v=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tpHL. tpLH 

Maximum Propagation 
Delay 


8 

15 ' 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl =50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 



Ta=25X 

74HC 

TA=-40to85‘’C 

Ta = 

54HC 

-55 to125X 

Units 





Typ 

Guaranteed Limits 


tpHL. fPLH 

Maximum Propagation 



45 

90 

113 


134 

mm 


Delay 



9 

18 

23 

■ 1 

27 

■a 




EBSi 

’ 8 

15 

19 


23 


tTLH. tTHL 

Maximum Output Rise 



30 


95 

n 




and Fall Time 



8 

mm 

19 








7 

H 

16 

IfBI 




Power Dissipation 
Capacitance (Note 5) 

(per gate) 

■ 

20 




H 

C|N 

Maximum Input 
Capacitance 


■ 

5 


10 

10 

pF 


Note 5: CpD determines the no load dynamic power consumption, Pd= C po Vcc^ f + Iqq Vcc. and the no load dynamic current consumption, Is = CpD Vcc Icc- 


3-36 



































National 
Semiconductor 

MM54HC27/MM74HC27 
Triple 3-Input NOR Gate 

General Description 

These NOR gates utilize mIcroCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. All gates have buffered 
outputs, providing high noise immunity and the ability to 
drive 10 LS-TTL loads. The 54HC/74HC logic family is func- 
tionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 



microCMOS 


Features 

■ Typical propagation delay: 8 ns 

■ Wide operating supply voltage range: 2-6V • 

■ Low Input current: < 1 juA 

■ Low quiescent supply current: 20 juA maximum 
(74HC Series) 

■ Fanout of 10 LS-TTL Loads 



Connection and Logic Diagrams 

Dual-ln-Line Package 

Vcc Cl Y1 C3 B3 A3 Y3 


1 






9 

8 


1 

■ 

1 

1 



■ 

■ 


1 






1 

r; 1 

CM 

3 

4 

5 

6 

B 


A1 B1 A2 B2 C2 Y2 GNO 
Top View 

Order Number MM54HC27J or MM74HC27J,N 
See NS Package J14A or N14A 


TL/F/5300-1 




3-37 


MM54HC27/MM74HC27 





MM54HC27/MM74HC27 


Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (Vin) 

-1.5toVcc+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (Iik, Iqk) 

±20 mA 

(Vin.Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 




DC Vcc or GND Current, per pin (Icc) 

±50 mA 

MM74HC 

-40 

+ 85 

“C 

Storage Temperature Range (Tstg) 

-65"Cto +150“C 

MM54HC 

-55 

+ 125 

“C 

Power Dissipation (Pd) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temperature (T l) 


> 

0 

c\j 

II 

8 

> 


1000 

ns 

(Soldering 10 seconds) 

260‘*C 

Vcc=4.5V 


500 

ns 



Vcc=6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

:25X 

74HC 

TA==-40to 85X 

54HC 

Ta=- 55 to125"C 






Typ 

Guaranteed Limits 


V|H 

Minimum High Level 





||||n|9| 




Input Voltage 












m 





V|L 

Maximum Low Level 





0.3 


ml 


Input Voltage 





0.9 

0.9 

V 





HI 

1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|L 

M 







Output Voltage 

|louTk20 )xA 


2.0 

1.9 

1.9 

1.9 

V 





4.5 

4.4 

4.4 

4.4 

V 





6.0 

5.9 

5.9 

5.9 

V 



V,N = V,L 
|louTk4.0 mA 

^^9 

4.2 

3.98 


3.7 

V 



i^OUTi^5.2 mA 


5.7 

5.48 


5.2 

V 

Vql 

Maximum Low Level 

V|N = V|HOrV|L 

M 


■1 





Output Voltage 

I'oUtI^20(xA 


0 

Bl 

0.1 

0.1 






0 

mm 

0.1 

0.1 





6.0V 

0 

m 

0.1 

0.1 




Vin = V|h or V|L 
l•oUTl^4.0 mA 

4.5V 

0.2 



0.4 




I^OUtI^ 5.2 mA 

6.0V 

0.2 

mllBm 

mm 

0.4 


l|N 

Maximum Input 
Current 



i 


±1.0 

±1.0 

fiA 

•cc 

Maximum Quiescent 




2.0 

20 

40 

/jlA 


Supply Current 




i 





Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 12 mW/*C from 65*C to 85'C; ceramic “J” package: - 12 mW/*C from 100'C to 125'’C. 
Note 4: For a power supply of 5V ± 1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-38 






































AC Electrical Characteristics vcc= 5 v.TA= 25 “c,CL=i 5 pF,tr=tf= 6 ns 



Parameter 




Units 

fpHL. tpLH 

Maximum Propagation 
Delay 



15 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl =50 pF, tr=tf=6 ns (unless otherwise specified) 


Syrnbol 

Parameter 

Conditions 

Vcc 

Ta=25X 

74HC 

Ta=- 40 to 85X 

Ta=- 

54HC 

-55 to125X 

Units 



Typ 

Guaranteed Limits 



Maximum Propagation 



45 




134 

WM 


Delay 



9 




27 





ESI 

8 




23 

■■ 

tjLH. tlHL 

Maximum Output Rise 



30 

75 

95 


110 

ns 


and Fall Time 



8 

15 

19 


22 

ns 





7 

13 

16 


19 

ns 


Power Dissipation 
Capacitance (Note 5) 

(per gate) 

■ 

36 




pF 


Maximum Input 
Capacitance 


■ 

5 

10 

10 

10 

pF 


Note 5: CpQ determines the no load dynamic power consumption, Pq = Cpo Vcc^ f + ice Vcc. and the no load dynamic current consumption, ls= Gpo Vcc t+ Icc- 



3-39 


MM54HC27/MM74HC27 




























MM54HC30/MM74HC30 


National 

Semiconductor 


MM54HC30/MM74HC30 8-Input NAND Gate 


microCMOS 


General Description 

This NAND gate utilizes microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. This device has high 
noise immunity and the ability to drive 10 LS-TTL loads. The 
54HC/74HC logjc family is functionally as well as pin-out 
compatible with the standard 54LS/74LS logic family. All 
inputs are protected from damage due to static discharge by 
internal diode clamps to Vcc and ground. 

Connection and Logic Diagrams 


Features 

■ Typical propagation delay: 20 ns 

■ Wide power supply range: 2-6\/ 

■ Low quiescent current: 20 fxA maximum (74HC Series) 

■ Low input current: 1 fiA maximum 

■ Fanout of 10 LS-TTL loads 


Dual-ln-Line Package 



Top View 

Order Number MM54HC30J or MM74HC30J, N 
See NS Package J14A or N14A 



Y=ABCDEFGH 


3-40 




Absolute Maximum Ratings (Notes t & 2 ) Operating Conditions 


Supply Voltage (Vec) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1.5V 

DC Supply Voltage (Vec) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vec + 0.5V 

DC Input or Output Voltage 




Clamp Diode Current (Iqd) 

±20 mA 

(V|N. Vqut) 

0 

Vec 

V 

DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 




DC Vec or GND Current, per pin (Ice) * 

±50 mA 

MM74HC 

-40 

±85 

“C 

Storage Temperature Range (Tstg) 

-65‘’Cto ±150°C 

MM54HC 

-55 

±125 

“C 

Power Dissipation (Pd) (Note 3) 

500 mW 

Input Rise/Fall Times 




Lead Temp. (TO (Soldering, 10 seconds) 

260“C 

< 

0 

0 

11 

to 

b 

< 


1000 

ns 



Vec = 4.5 V 


500 

ns 



Vcc=6.0V 


400 

ns 


DC Eiectricai Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

1 

Vcc 

Ta= 

= 25“C 

74HC 

Ta=- 40 to 85°C 

54HC 

TA=-55to125X 

Units 

Typ 

Guaranteed Limits 


Minimum High Level Input 


2.0V 


1.5 





Voltage 


4.5V 


3.15 







6.0V 


4.2 







M 


0.3 

0.3 

0.3 

V 






0.9 

0.9 

0.9 

V 






1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level Output 

V|N = V|HOrV|L 








Voltage 

|louTk20 /xA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|HOrViL 









110071^4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



ilouTi^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level Output 

Vin = Vih 








Voltage 

|loUTk20 fxA 

2.0V 


0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|h 

III 

M 

M 






|IoutI^ 4 mA 





0.4 

V 



ilouTl^5.2 mA 





0.4 

V 

l|N 

Maximum Input Current 

V|N = Vec or GND 

6.0V 


± 0.1 

±1.0 

±1.0 

IllA 


Maximum Quiescent Supply 

V|fsj = Vec or GND 

6.0V 

■ 


20 

40 

jxA 


Current 

Iout^O^A 


■ 






Note 1; Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless othenvise specified all voltages are referenced to, ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package; - 1 2 mW/^C from GS'C to 85®C; ceramic “J” package: - 1 2 mW/'C from 1 0O'C to 1 25*0. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc=5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-41 


l\/IM54HC30/MM74HC30 










MM54HC30/MM74HC30 


AC Electrical Characteristics vcc=5v,TA=25'c,CL=i5pF,tr=t,=6ns 


Symbol 

Parameter 

Conditions 


Guaranteed 

Limit 

Units 

^PHL. tPLH 

Maximum Propagation Delay 


20 

30 



AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl= 50 pF, tr=tf=6tns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25X 

74HC 

TA=-40to 85“C 

Ta = 

54HC 

-55 to125“C 

Units 





Typ 

Guaranteed Limits 


tpHL. tPLH 

Maximum Propagation 


2.0V 

66 

160 

190 


220 

ns 


Delay 


4.5V 

23 

35 

42 


49 

ns 




6.0V 

18 

30 

36 


42 

ns 

tjLH. tlHL 

Maximum Output 


2.0V 

30 


95 


110 

ns 


Rise and Fall 


4.5V 

8 

■9 

19 


22 

ns 


Time 


6.0V 

7 

13 

16 


19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 



34 




pF 

Qn 

Maximum Input 
Capacitance 


, 

5 

10 

10 

10 

pF 


Note 5; Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f+icc Vcc. and the no load dynamic current consumption, ls=CpD Vcc f+Icc- 


3-42 













National 
Semiconductor 

MM54HC32/MM74HC32 
Quad 2-Input OR Gate 

General Description 

These OR gates utilize microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS, to achieve operating speeds simi- 
lar to LS-TTL gates with the low power consumption of stan- 
dard CMOS integrated circuits. All gates have buffered out- 
puts, providing high noise, immunity and the ability to drive 
10 LS-TTL loads. The 54HC/74HC logic family is functional- 
ly as well as pin-out compatible with the standard 54LS/ 
74LS logic family. All inputs are protected from damage due 
to static discharge by internal diode clamps to Vcc and 
ground. 



microCMOS 


Features 

■ Typical propagation delay: 10 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 fxA maximum (74HC Series) 

■ Low input current: 1 juA maximum 

■ Fanout of 1 0 LS-TTL loads 



Connection and Logic Diagrams 


Dual-in-Line Package 



Top View 


TL/F/5132-1 


Order Number MM54h|C32J or MM74HC32J,N 
See NS Package J14A or N14A 


A 

B 


Y 


Y = A+B 


TL/F/5132-2 





3-43 


MM54HC32/MM74HC32 



MM54HC32/MM74HC32 


Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) “ 0.5 to + 7.0V 

DC Input Voltage (V|n) - 1 .5 to Vcc + 1 -SV 

DC Output Voltage (Vqut) - 0.5 to Vcc + 0-5V 

Clamp Diode Current (I|k, Iqk) ± 20 mA 

DC Output Current, per pin (Iqut) i 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) ~ 55^ to + 1 50°C 

Power Dissipation (Pq) (Note 3) 500 mW 

Lead Temperature (TJ 

(Soldering 10 seconds) 260°C 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(V|N> Vout) 

Operating T emp. Range (T a) 
MM74HC -40 

MM54HC -55 

Input Rise or Fall Times 
(tr.tf) Vcc = 2.0V 

Vcc = 4.5 V 
Vcc = 6.0 V 


DC Electrical Characteristics (Note 4) 


Conditions 


Symbol Parameter 

V|H Minimum High Level 

Input Voltage 

V|L Maximum Low Level 

Input Voltage 


Vqh Minimum High Level V|n = V|h or V|l 

Output Voltage | IqutI ^ 20 jllA 2.0V 

4.5V 

6.0V 

ViN = V|HorViL 
|loUTl^4.0mA 4.5V 

IIoutI^ 5.2 mA 6.0V 

Vql Maximum Low Level V|{m = V|l 

Output Voltage | IquiI ^ 20 juiA 2.0V 


Maximum Input 
Current 


VlN = ViL 
|louTk4.0 mA 
il0UTi^5.2 mA 
V|fs| = Vcc or GND 


Ta = 25'’C 


74HC 

TA=-40to85°C Ta = 
Guaranteed Limits 


54HC 

-55to125‘’C Units 



Ice Maximum Quiescent V|N = VccorGND 6.0V 
Supply Current l0UT= 0 M-A 

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: -12 mW/*C from 65®C to 85“C; ceramic “J” package: - 12 mW/'C from 100®C to 125*0. 
Note 4; For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when 
designing with this supply. Worst case Vm and V|l occur at V(x= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, 
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-44 














AC Electrical Characteristics vcc= 5 v,TA= 25 '>c,CL=i 5 pF,tr=t,= 6 ns 



Parameter 



Guaranteed 

Limit 

Units 

tPHL. tpLH 

Maximum Propagation 
Delay 


10 

18 

ns 


AC Electrical Characteristics 

Vcc=2.0V to 6.0V, Cl=50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25°C 

74HC 

Ta=-40 to 85“C 

Ta = 

54HC 

-55 to125“C 

Units 





Typ 

Guaranteed Limits 


tpHL. tPLH 

Maximum Propagation 




100 

125 


150 

ns 


Delay 




20 

25 


30 

ns 






17 

21 


25 

ns 


Maximum Output Rise 




75 

95 


110 

ns 


and Fall Time 




15 

19 


22 

ns 






13 

16 


19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 


50 




pF 

C|N 

Maximum Input 
Capacitance 


■ 

5 

10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f + Iqq Vcc. and the no load dynamic current consumption, ls=Cpo Vcc Icc- 



3-45 


MM54HC32/MM74HC32 









MM54HC42/MM74HC42 


National 
Semiconductor 

MM54HC42/MM74HC42 
BCD-to-Decimal Decoder 

General Description 

This decoder utilizes microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS. Data on the four input pins select 
one of the 10 outputs corresponding to the value of the BCD 
number on the inputs. An output will go low when selected, 
otherwise it remains high. If the input data is not a valid BCD 
number all outputs will remain high. The circuit has high 
noise immunity and low power consumption usually associ- 
ated with CMOS circuitry, yet also has speeds comparable 
to low power Schottky TTL (LS-TTL) circuits, and is capable 
of driving 10 LS-TTL equivalent loads. 



All inputs are protected frpm damage due to static dis- 
charge by diodes to Vcc and ground. 

Features 

■ Typical propagation delay: 15 ns 

■ Wide supply range: 2V-6V 

■ Low quiescent current: 80 jmA (74HC) 

■ Fanout of 1 0 LS-TTL loads 



Connection Diagram 

Dual-in-line Package 

INPUTS OUTPUTS 

, ^ , 

Vcc A B c. D 9 8 7 



OUTPUTS TL/F/5301-1 

Top View 


Truth Table 


No 

Inputs 

Outputs 


D 

C 

B 

A 

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

0 

L 

L 

L 

L 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

1 

L 

L 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

2 

L 

L 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

3 

L 

L 

H 

H 

H 

H 

H 

L 

H 

H 

H 

H 

H 

H 

4 

L 

H 

L 

L 

H 

H 

H 

H 

L 

H 

H 

H 

H 

H 


L 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

H 

H 

H 


L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

H 

H 


L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 

H 

H 


H 

L 

L 

L 

H 

H 

H 

H 

H 

H 

H 

H 

L 

H 


H 

L 

L 

H 

±L 



H 

Jj_ 

H 

H 

H 

H 

L 


n 

n 

El 


H 

H 

H 

H 

H 

H 

m 

El 

El 

El 


n 

H 

n 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 


H 

H 

L 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

IInVALIU 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 


H 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 


H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 


Order Number MM54HC42J or MM74HC42J, N 
See NS Package J16A or N16E 

Logic Diagram 


H = High Level, L=Low Level 



TL/F/5301-2 


3-46 




Absolute Maximum Ratings (Notes i & 2 ) 

Operating Conditions 



Supply Voltage (Vcc) 

- 0.5 to + 7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5toVcc+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(Vin.Vout) 




DC Output Current, per pin (Iqut) 

±25 mA 

operating Temp. Range (Ta) 




DC Vcc O'* GND Current, per pin (Icc) 

±50 mA 

MIVI74HC 

-40 

+ 85 

°c 

Storage Temperature Range (Tstg) 

-65"Cto ±150“C 

IVIM54HC 

-55 

+ 125 

°c 

Power Dissipation (Pq) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temp. (Tl) (Soldering 10 seconds) 

260°C 

< 

o 

o 

II 

b 

< 


1000 

ns 



Vcc = 4.5 V 


500 

ns 



Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note4) 






T. — 

= 25°C 

74HC 

54HC 


Symbol 

Parameter 

Conditions 

Vcc 

• a 

Ta=- 40 to 85“C 

Ta=- 55 to125°C 

Units 





Typ 

Guaranteed Limits 


ViH 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 



0.3 

0.3 

V 


Input Voltage 


4.5V 



0.9 

0.9 

V 




6.0V 


■a 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

VlN=V|H orViL 



■i 





Output Voltage 

|louTk20 fxA 

2.0V 

2.0 

19 

1.9 

1.9 

V 




4.5V 

4.5 

19 

4.4 

4.4 

V 




6.0V 

6.0 


5.9 

5.9 

V 



V|N = V|h 0rV|L 
|louTk4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



jlouTi^6.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

VoL 

Minimum Low Level 

V|n = V|h orViL 








. Output Voltage 

liourl^sOftA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N==V|HOrV|L 
|IoutN 4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



i^OUTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum Input 
Current 

V|N = Vcc or GND 

6.0V 


±0.1 

±1.0 

±1.0 

juA 


Maximum Quiescent 

V|N = Vcc 01' gnd 

6.0V 


8.0 

80 

160 

jaA 


Supply Current 

IOUT = 0 M 








Note 1; Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 12 mW/*C from to SS^C; ceramic “J” package: - 12 mW/'C from 100*C to 125“C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when 
designing with this supply. Worst case Vm and V|l occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, 
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-47 


MM54HC42/MM74HC42 




MM54HC42/MM74HC42 


AC Electrical Characteristics vcc=5v,TA=25»c,CL=i5pF,tr=t,=6ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tPLH 

Maximum Propagation 
Delay 


15 

25 



AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl =50 pF, tr=tf =6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25“C 

74HC 

Ta=-40 to 85“C 

Ta = 

54HC 

-55 tOl25“C 

Units 





Typ 

Guaranteed Limits 


tpHL. tpLH 

Maximum Propagation 


2.0V 



189 


224 

WM 


Delay 


4.5V 



38 


45 

■a 




6.0V 



32 


38 

wm 

tjLH. tjHL 

Maximum Output Rise 


2.0V 


75 

95 


110 

n 


and Fall Time 


4.5V 


15 

19 


22 





6.0V 


13 

16 


19 

mm 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per package) 






pF 

Qn 

Maximum Input 
Capacitance 



5 

10 

. 10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pq = CpQ Vcc^ f + Ice Vcc. and the no load dynamic current consumption, Is = Cpo Vcc t + icc- 


3-48 














National 

Semiconductor 


PRELIMINARY 


MM54HC51/MM74HC51 
Dual AND-OR-Invert Gate 
MM54HC58/MM74HC58 Dual AND-OR Gate 


microCMOS 


General Description 

These gates utilize microCMOS Technology, 3.5 micron sili- 
con gate P-well CMOS, to achieve operating speeds similar 
to LS-TTL gates with the low power consumption of stan- 
dard CMOS Integrated circuits. All gates have buffered out- 
puts, providing high noise immunity and the ability to drive 
10 LS-TTL loads. The 54HC/74HC logic family Is functional- 
ly as well as pin-out compatible with the standard 54LS/ 
74LS logic family. All inputs are protected from damage due 
to static discharge by internal diode clamps to Vcc and 
ground. 


Features 

■ Typical propagation delay: 10 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent supply current: 20 jaA maximum 
(74 Series) 

■ Low input current: 1 juA maximum 

■ High output current: 4 mA minimum 


Connection Diagrams 


’ Dual-In-Line Package 

Vcc C1 B1 FI E1 D1 Y1 
|l4 |l3 ll2 In |io lo Is 


Top View 

Order Number MM54HC51J or MM74HC51J, N 
See NS Packages J14A or N14A 

Dual-ln-Line Package 



Top View 

Order Number MM54HC58J or MM74HC58J, N 
See NS Packages J14A or N14A 


MM54HC51/MM74HC51/MM54HC58/MM74HC58 



MM54HC51/MM74HC51/nM54HC58/MM74HC58 


Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vec) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5toVcc+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc T- 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 




DC Vcc or GND Current, per pin (Ice) 

±50 mA 

MM74HC 

-40 

+ 85 

“C 

Storage Temperature Range (Tstg) 

-65‘’Cto +150‘’C 

MM54HC 

-55 

+ 125 

“C 

Power Dissipation (Pq) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temp. (Tl) (Soldering 10 seconds) 

260“C 

> 

0 
c\j 

II 

1 


1000 

ns 



Vcc = 4.5V 


500 

ns 



Vcc = 6.0V 


400 

ns 


DC Eiectricai Characteristics (Note 4) 


, Symboi 

Parameter 

Conditions 

Vcc 

Ta = 

25°C 

74HC 

Ta=- 40 to 85“C 

54HC 

Ta=- 55 to125“C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|HOrV|L 








Output Voltage 

IIoutI^so p,A 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V , 




6.0V 

6.0 

5.9 

5.9 

5.9 . 

V 



V|N = V|HOr V|L 
|louTk4.0 mA 


4.2 

3.98 

3.84 

3.7 

V 



|l0UTi^5.2 mA 


5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|HorV|L 








Output Voltage 

1IoUtI^20(j,A 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|H orViL 
|IoutU 4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



|IoutI^ 5.2 mA 

6.0V 

0:2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum Input 
Current 

V|N = Vcc or GND 


■ 

±0.1 

±1.0 

±1.0 

jaA 

•cc 

Maximum Quiescent 

V|N = VccorGND 

6.0V 


2.0 

20 

40 

fiA 


Supply Current 

IOUT = 0 M 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: —12 mW/'C from 65°C to SS'C; ceramic “J” package: -12 mW/^C from 100“C to 125®C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc=5-5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|m, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-50 














AC Electrical Characteristics vcc=5v,TA=25»c.cL=i5pF.tr=tf=6ns 



Symbol 

— 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 


tPHL.tPLH 

Maximum Propagation 
Delay 


10 

20 

ns 


AC Electrical Characteristics Vcc= 2.0V to 6.0V, Cl= 50 pF, tr= tf = 6 ns (unless otherwise specified) 




3-51 


MM54HC51/MM74HC51/MM54HC58/MM74HC58 












MM54HC73/MM74HC73 


National 
Semiconductor 

MM54HC73/MM74HC73 
Dual J-K Flip-Flops with Clear 

General Description 

These J-K Flip-Flops utilize microCMOS Technology, 3.5 
micron silicon gate P-well CMOS. They possess the high 
noise immunity and low power dissipation of standard 
CMOS integrated circuits. These devices can drive 10 LS- 
TTL loads. 

These flip-flops are edge sensitive to the clock input and 
change state on the negative going transition of the clock 
pulse. Each one has independent, J, K, CLOCK, and 
CLEAR inputs and Q and Q outputs. CLEAR is independent 
of the clock and accomplished by a low level on the Input. 

The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 



microCMOS 


All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 16 ns 

■ Wide operating voltage range: 2-6V 

■ Low input current: 1 fxA maximum 

■ Low quiescent current: 40 jaA (74HC Series) 

■ High output drive: 10 LS-TTL loads 



Connection and Logic Diagrams Truth Tabie 


Dual-ln-Line Package , 

J1 Q1 01 GND K2 02 02 



Order Number MM54HC73J or MM74HC73J, N 
See NS Package J14A or N14A 


Inputs 

Outputs 

CLR 

CLK 

J 

K 

Q 

Q 

L 

X 

X 

X 

L 

H 

H 

i 

L 

L 

QO 

QO 

H 

4. 

H 

,L 

H 

L 

H 

i 

L 

H 

L 

H 

H 

4- 

H 

H 

TOGGLE 

H 

H 

X 

X 

QO 

QO 



TL/F/5072-2 



CL 

-ifl- 

CL 

T 

TL/F/5072-3 


3-52 



Absolute Maximum Ratings (Notes i a 2) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (Vin) 

-1.5 to Vcc+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqijt) 

-0.5to Vcc+0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 




DC Vcc or GND Current, per pin (Icc) 

±50 mA 

MM74HC 

-40 

±85 

“C 

Storage Temperature Range (Tstg) 

-65°Cto +150°C 

MM54HC 

-55 

±125 

°C 

Power Dissipation (Pc) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temperature (T l) 


0 

II 

to 

b 

< 


1000 

ns 

(Soldering 10 seconds) 

260“C 

Vcc = 4.5V 


500 

ns 



Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25X 

74HC 

Ta=- 40 to 85“C 

54HC 

Ta=- 55 to125°C 

Units 





Typ 

Guaranteed Limits 


ViH 

Minimum High Level 




1.5 

1.5 

1.5 

V 


Input Voltage 




3.15 

3.15 

3.15 

V 





n 

4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 

im 


0.3 

o.b 

V 


Input Voltage 


4.5V 



0.9 

0.9 

V 




6.0V 



1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N=V|HorV|L 








Output Voltage 

|louTk20 }xA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orV|L 
|louT|S4.0mA 

^^1 


3.98 

3.84 

3.7 

V 






5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|HOrViL 








Output Voltage 

|IoutI^20 p,A 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

o‘ 

0.1 

0.1 

0.1 

V 



V|N = V|H orV|L 
|Iout1^4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



|IoutI^ 5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

l|N 






±1.0 

±1.0 

juA 

Icc 

Maximum Quiescent 

V|N = Vcc or GND 

6.0V 


4.0 

40 

80 

juA 


Supply Current 

Iout=0mA 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating -> plastic “N” package: - 12 mW/'C from to 85*0; ceramic “J” package: - 1 2 mW/*C from 1 0O'C to 1 25“C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc=5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, Icc. and 
I 02 ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-53 


l\/IM54HC73/MM74HC73 












MM54HC73/MM74HC73 


AC Electrical Characteristics vcc=5v.TA=25**c,CL=i5pF.tr=tf=6ns 

Symbol ' I Parameter T Conditions I Typ I Guaranteed Limit 


^MAX 


tpHL. tpLH 


tpHL. tpLH 


tREM 


S 


tH 


tw 


Maximum Operating 
Frequency 


Maximum Propagation 
Delay Clock to Q or Q 


Maximum Propagation 
Delay Clear to Q or Q 


Minimum Removal Time, 
Clear to Clock 


Minimum Hold Time 
J or K to Clock 


Minimum Pulse Width, 
Clock or Clear 



50 

30 

16 

21 

21 

26 

10 

20 

14 

20 

-3 

0 

10 

16 



AC Electrical Characteristics Cl= 50 pF, tr=tf = 6 ns (unless otherwise specified) 


Maximum Operating 
Frequency 



tpHL. tPLH 

Maximum Propagation 
Delay Clear to Q or Q 

tREM 

Minimum Removal Time 
Clear to Clock 

ts 

Minimum Setup Time 

J or K to Clock 

tH 

Minimum Hold Time 

J or K from Clock 

tw 

Minimum Pulse Width 
Clock or Clear 

tTLH. tjHL 

Maximum Output Rise 
and Fall Time 

tr.tf 

Maximum Input Rise and 
Fall Time 

CpD 

Power Dissipation 
Capacitance (Note 5) 

C|N 

Maximum Input 
Capacitance 


10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f + Ice Vcc> and the no load dynamic current consumption, ls=CpD Vec f + Icc- 


3-54 





















































































3-55 


MM54HC73/MM74HC73 










MM54HC74/MM74HC74 


ffgi National 
MSA Semicx}nductor 

MM54HC74/MM74HC74 

Dual D Flip-Flop with Preset and Ciear 



General Description 

The MM54HC74/MM74HC74 utilizes microCMOS Technol- 
ogy, 3.5 micron silicon gate P-well CMOS, to achieve oper- 
ating speeds similar to the equivalent LS-TTL part. It pos- 
sesses the high noise immunity and low power consumption 
of standard CMOS integrated circuits, along with the ability 
to drive 10 LS-TTL loads. 

This flip-flop has independent data, preset, clear, and clock 
inputs and Q and Q outputs. The logic level present at the. 
data input is transferred to the output during the positive-go- 
ing transition of the clock pulse. Preset and clear are Inde- 
pendent of the clock and accomplished by a low level at the 
appropriate Input. 


The 54HC/74HC logic family is functionally and pinout com- 
patible with the standard 54LS/74LS logic family. All inputs 
are protected from damage due to static discharge by inter- 
nal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 20 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 40 j^A maximum (74HC Series) 

■ Low input current: 1 jmA maximum 

■ Fanout of 10 LS-TTL loads 


Connection and Logic Diagrams 

Dual-ln-Line Package 

Vcc CLR2 D2 CLK2 PR2 02 02 



Truth Tabie 


Inputs 

Outputs 

PR 

CLR CLK 

D 

Q 

Q 

L 

H 


n 

H 

L 

H 

L 


H 

L 

H 




WM 

H* 

H* 



wM 


H 

L 




U 

L 

H 



m 

B 

QO 

QO 


Note: Q0=the ievel of Q before the indicated input condi- 
tions were established. 


* This configuration is nonstable; that is, it will not persist 
when preset and clear inputs return to their inactive (high) 
level. 


TOP VIEW TL/F/5106-1 

Order Number MM54HC74J or MM74HC74J, N 
See NS Package J14A or N14A 



TL/F/5106-2 


3-56 



Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5toVcc+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. out) 




DC Output Current, per pin (Iout) 

±25 mA 

Operating Temp. Range (Ta) 
MM74HC 

-40 

+ 85 

“C 

DC Vcc or GND Current, per pin (Ice) 

±50 mA 

MM54HC 

-55 

+ 125 

“C 

Storage Temperature Range (Tstg) 

-65‘’Cto +150‘'C 

Input Rise or Fall Times 




Power Dissipation (Pq) (Note 3) 

500 mW 

(tr.tf) Vcc=2.0V 


1000 

ns 

Lead Temp. (TJ (Soldering 10 seconds) 

260"C 

Vcc = 4.5V 


500 

ns 



Vcc = 6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta = 

= 25“C 

74HC 

Ta=- 40 to 85°C 

54HC 

Ta=- 55 to125X 

Units 




1 


Guaranteed Limits 


V|H 

Minimum High Level 




■3 





Input Voltage 










i 

QSQI 

m 

MM 



V 

V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

VOH 

Minimum High Level 

Vin = V|h or V|L 








Output Voltage 

|louTk20fiA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|n = V|h orViL 
|louTk4.0 mA 

4.5V 

4.3 

3.98 

3.84 

3.7 

V 




6.0V 

5.2 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

Vin=V|h orV|i_ 



■i 





Output Voltage 

|loUTk20 p,A 

2.0V 

0 

Bl 

0.1 

0.1 

V 




4.5V 

0 

mm 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|H orViL 
I^OUTl^4.0 mA 


0.2 

0.26 

0.33 

0.4 

V 



I^OUTl^5.2 mA 


0.2 

0.26 

0.33 

0.4 

V 

•in 





±0.1 

±1.0 

±1.0 

IxA 

■cc 

Maximum Quiescent 

V|N ~ Vcc or GND 

6.0V 


4.0 

40 

80 

ju,A 


Supply Current 

IOUT=0 P-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic "N” package: - 1 2 mW/*C from es^C to 85*0; ceramic "J” package: - 1 2 mW/*C from 1 00*0 to 1 25*0. 
Note 4: For a power supply of 5V ± 1 0%Mhe worst case output voltages (Vqhi and Vql) occur for HO at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|i_ occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (Iin, Iqc. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-57 


MM54HC74/MM74HC74 





































MM54HC74/MM74HC74 


AC Electrical Characteristics vcc= 5 v,TA= 25 ”c,CL=i 5 pF,tr=tf= 6 ns 


Symbol 


^MAX 


tpHL. tpLH 


tpHL. tpLH 


tREM 


Conditions 


Maximum Operating 
Frequency 


Maximum Propagation 
Delay Clock to Q or Q 


Maximum Propagation _ 
Delay Preset or Clear to Q or Q 


Minimum Removal Time, 
Preset or Clear to Clock 


Minimum Setup Time 
Data to Clock 


Minimum Hold Time 
Clock to Data 


Minimum Pulse Width 
Clock, Preset or Clear 



AC Electrical Characteristics Cl = 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

^MAX 

Maximum Operating 
Frequency 

tPHL. tpLH 

Maximum Propagation 
Delay Clock to Q or Q 

tPHL. tpLH 

Maximum Propagation 
Delay Preset or Clear 
ToQorQ 

tREM 

Minimum Removal Time 
Preset or Clear 

To Clock 

ts 

Minimum Setup Time 

Data to Clock 

tH 

Minimum Hold Time 

Clock to Data 

tw 

Minimum, Pulse Width 
Clock, Preset or Clear 

tTLH. tTHL 

Maximum Output 

Rise and Fall Time 

tptf 

Maximum Input Rise and 
Fall Time 

CpD 

Power Dissipation 
Capacitance (Note 5) 

CiN 

Maximum input 
Capacitance 



Ta= 

25X 

74HC 

TA=-40to85X 

54HC 

Ta=- 55 to125°C 

Units 

Typ 1 

Guaranteed Limits I 




Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f+ Icc Vcc. and the no load dynamic current consumption, ls=CpD Vcc f + Icc- 


3-58 














































































National 

Semiconductor 


MM54HC75/MM74HC75 
4-Bit Bistable Latch with 


Q and Q Output 



microCMOS 


General Description 

This 4-bit latch utilizes microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS. To achieve the high noise immu- 
nity and low power consumption normally associated with 
standard CMOS integrated circuits. These devices can drive 
10 LS-TTL loads. 

This latch is ideally suited for use as temporary storage for 
binary information processing, input/output, and indicator 
units. Information present at the data (D) input is transferred 
to the Q output when the enable (G) is high. The Q output 
will follow the data input as long as the enable remains high. 
When the enable goes low, the information that was present 
at the data input at the time the transition occurred is re- 
tained at the Q output until the enable is permitted to go 
high again. 


The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 
All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Typical operating frequency: 50 MHz 

■ Typical propagation delay: 12 ns 

■ Wide operating supply voltage range: 2-6V 

■ Low input current: < 1 fiA 

■ Low quiescent supply current: 80 fiA maximum 
(74HC Series) 

■ Fanout of 1 0 LS-TTL loads 


Connection and Logic Diagrams 

Dual-ln-Line Package 

ENABLE 

IQ 2Q 20 1-2 GND 3Q 3Q 40 



3-4 

TOP VIEW 


TL/F/5303-1 


Truth Table 


Inputs 

Outputs 

D G 

Q Q 

L H 

H H 

X L 

L H 

H L 

Qo Qo 


H = High Level: L==Low Level 
X = Don’t Care 

Qo = The level of Q before the transition of G 


Order Number MM54HC75J or MM74HC75J, N 
See NS Package J16A or N16E 


(1 of 4 latches) 




3-59 


MM54HC75/MM74HC75 







MM54HC75/MM74HC75 


Absolute Maximum Ratings (Notes i & 2 ) 

Supply Voltage (Vcc) - 0.5 to + 7.0V 

DC Input Voltage (Vin) -1.5 to Vcc + 1 .5V 

DC Output Voltage (Vqut) ~ 0.5 to Vcc+ 0.5V 

Clamp Diode Current (I|k, Iqk) ±20 mA 

DC Output Current, per pin (Iqlit) ^ 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage T emperature Range (T stg) “ 65“C to + 1 50“C 

Power Dissipation (Pq) (Note 3) 500 mW 

Lead Temp. (TJ (Soldering 10 seconds) 260®C 

DC Electricai Characteristics (Note 4) 


Symboi 

Parameter 

VlH 

Minimum High Level 
Input Voltage 

V|L 

Maximum Low Level 
Input Voltage 

Vqh 

Minimum High Level 
Output Voltage 

Vol 

Maximum Low Level 
Output Voltage 


Maximum Input 
Current 

Icc 

Maximum Quiescent 
Supply Current 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(V|N. Vqut) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 

Input Rise or Fall Times 
(tr.tf) Vcc=2.0V 
Vcc = 4.5V 
Vcc = 6.0V 


74HC 54HC 

TA=-40to85X TA=-55to125X Units 

Guaranteed Limits 



Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3; Power Dissipation temperature derating — plastic “N" package: - 1 2 mW/*C from 65*0 to 85*C; ceramic "J” package: - 1 2 mW/*C from 1 00*C to 1 25*C. 
Note 4: For a power supply of 5V ± 10% the worst case output voltages (Vqh. and Vol) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-60 








































tH 

Minimum Hold Time 

Enable to Data 


tw 

Minimum Enable Pulse Width 



CpD 

Power Dissipation 

(per commonly 


Capacitance (Note 5) 

clocked latched 
pair) 

C|N 

Maximum Input 

Capacitance 



Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpq Vcc^ f+lcc Vcc. and the no load dynamic current consumption, ls=CpD Vcc f + Icc- 


3-61 


MM54HC7S/MM74HC75 

































MM54HC76/MM74HC76 


National 


Semiconductor 

V ~J 

microCMOS 


MM54HC76/MM74HC76 Dual J-K Flip-Flops 
with Preset and Clear 


General Description 

These high speed (30 MHz minimum) J-K Flip-Flops utilize 
mIcroCMOS Technology, 3.5 micron silicon P-well CMOS, 
to achieve, the low power consumption and high noise Im- 
munity of standard CMOS integrated circuits, along with the 
ability to drive 10 LS-TTL loads. 

Each flip-flop has Independ^t J, K, PRESET, CLEAR, and 
CLOCK inputs and Q and Q outputs. These devices are 
edge sensitive to the clock input and change state on the 
negative going transition of the clock pulse. Clear and pre- 
set are Independent of the clock and accomplished by a low 
logic level on the corresponding Input. 


Connection and Logic Diagrams 


The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 
All inputs are protected from damage due to static dis- 
charge by Internal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 16 ns 

■ Wide operating voltage range 

■ Low input current: 1 iiA maximum 

■ Low quiescent current: 40 jaA maximum (74HC Series) 

■ High output drive: 10 LS-TTL loads 

Truth Tabie 


Dual-ln-Llne Package 



CLK 1 PR 1 CLR 1 J1 Vcc CLK 2 PR 2 CLR 2 


TL/F/5074-1 

Top View 


Inputs 

Outputs 

PR 

CLR 

CLK 

J 

L 

Q 

Q 

L 

H 

X 

X 

B 

H 

L 

H 

L 

X 

X 

B 

L 

H 

L 

L 

X 

X 

B 

L* 

L* 

H 

H 

4 - 

L 

B 

QO 

QO 

H 

H 

4 - 

H 

n 

H 

L 

H 

H 

4 - 

L 


L 

H 

H 

H 

i 

H 


TOGGLE 

H 

H 

H 

X 


QO 

QO 


*This is an unstable condition, and is not guaranteed 


Order Number MM54HC76J or MM74HC76J, N 
See NS Package J16A or N16E 



CL CL 



CL CL 

T T 


TL/F/5074-3 


3-62 



Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vec) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC 1 nput Voltage (V|n) 

-1.5toVcc+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vec + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 




DC Vec or GND Current, per pin (Ice) 

±50 mA 

MM74HC ' 

-40 

±85 

“C 

Storage Temperature Range (Tstg) 

-65'’Cto +150“C 

MM54HC 

-55 

±125 

“C 

Power Dissipation (Pq) (Note 3) 

500 mW 

Input Rise or Fall Times 




Lead Temp. (Tl) (Soldering 10 seconds) 

260“C 

> 

0 

evi 

il 

0 


1000 

ns 



Vcc = 4.5V 


500 

ns 



Vcc=6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 






T- - 

= 25X 

74HC 

54HC 


Symboi 

Parameter 

Conditions 


•A 

Ta=- 40 to 85X 

Ta=- 55 to125“C 

Units 






Guaranteed Limits 


V|H 

Minimum High Level 




■9 


1.5 

V 


Input Voltage 






3.15 

V 





llllll 

ig 


4.2 

V 

V|L 

Maximum Low Level 




0.3 

0.3 

0.3 

V 


Input Voltage 




0.9 

0.9 

0.9 

V 






1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N=V|HOrV|L 








Output Voltage 

HoUtI^SO p,A 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 
|IoutI^ 4.0 mA 

mSm 


3.98 

3.84 

3.7 

V 



i•0UTi^5.2 mA 



5.48 

5.34 

5.2 

^ V 

Vql 

Maximum Low Level 

V|N=V|h orViL 








Output Voltage 

|loUTl^20jiA 

2.0V 

0 

0.1 

■ 0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|H orViL 
110071^4.0 mA 

4.5V 

0.2 

0.26 

0.33 


V 



ilouTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 


V 

•in 






±1.0 

±1.0 

jiiA 

•cc 

Maximum Quiescent 

V|N~ Vcc or GND 

6.0V 


D 

40 

80 



Supply Current 

•OUT=0 mA 



WM 





Note 1: Absolute Maximum Ratings are those values beyontJ which damage to the device may occur. 
Note 2: Unless otherwise specified ail voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic "N” package: -12 mW/*C from QS’C to SS'C; ceramic "J” package: - 12 mW/'C from lOO'C to 125*0, 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vjh and V|l occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-63 


MM54HC76/MM74HC76 
























MM54HC76/MM74HC76 


AC Electrical Characteristics vcc= 5 v,TA= 25 ”c,cl=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

^MAX 

Maximum Operating Frequency 


tpHL. tpLH 

Maximum Propagation Delay Clock to Q or Q 


tPHL. tpLH 

Maximum Propagation Delay Clear to Q or Q 


tpHL. tpLH 

Maximum Propagation Delay Preset to Q or Q 



tREM 

Minimum Removal Time 


Minimum Setup Time J or K to Clock 

tH 

Minimum Hold Time J or K to Clock 

tw 

Minimum Pulse Width Preset, Clear or Clock 



10 

20 

14 

20 

-3 

0 


AC Electrical Characteristics Cl= 50 pF, tr=tf =6 ns (unless otherwise specified) 


Symbol Parameter Conditions | Vcc 


X Maximum Operating 

Frequency 



tpHL. tpLH 

Maximum Propagation 
Delay Clear to Q or Q 

tpHL. tpLH 

Maximum Propagation 
Delay, Preset to Q or Q 

tREM 

Minimum Removal Time 
Preset or Clear 
to Clock 



Minimum Setup Time 
J or Kto Clock 


Minimum Hold Time 
J or K from Clock 



tiLH. tjHL 

Maximum Output Rise 
and Fall Time 

tntf 

Maximum Input Rise and 
Fall Time 

CpD 

Power Dissipation 
Capacitance (Note 5) 

Qn 

Maximum Input 
Capacitance 



(per flip-flop) 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd V(x;2 f + Ice Vcc. and the no load dynamic current consumption, ls=CpD Vcc Icc- 


5 

10 

i 10 

10 

pF 


3-64 












































































Typical Applications 


N Bit Presettable Ripple Counter with Enable and Reset 
DATA C DATA B DATA A 


COUNTER ENABLE 


Q 

PRESET , 

J 


CLEAR 

Q 

CLOCK ^ 



Q 

PRESET 

J 


CLEAR 

5 

CLOCK ^ 



PRESET 

Q 

J 


CLEAR 

Q 

CLOCK ^ 




N Bit Parallel Load/Serial Load Shift Register with Clear 
DATA A DATA B DATA C 


J preset q 


“ CLOCK “ 



J preset q 


CLOCK ° 



J 

PRESET Q 


CLEAR 

K 

CLOCK ® 



3-65 










MM54HC85/MM74HC85 



National 

mii Semiconductor 

MM54HC85/MM74HC85 

4-Bit Magnitude Comparator 

General Description 

The MM54HC85/MM74HC85 Is a 4-bit magnitude compara- 
tor that utilizes microCMOS Technology, 3.5 micron silicon 
gate P-well CMOS. It is designed for high speed comparison 
of two four bit words. This circuit has eight comparison in- 
puts, 4 for each word; three cascade inputs (A<B, A>B, 
A=B); and three decision outputs (A<B, A>B, A=B). The 
result of a comparison is indicated by a high level on one of 
the decision outputs. Thus it may be determined whether 
one word is "greater than," "less than," or "equal to” the 
other word. By connecting the outputs of the least signifi- 
cant stage to the cascade inputs of the next stage, words of 
greater than four bits can be compared. In addition the least 
significant stage must have a high level applied to the A=B 
input, and a low level to the A<B, and A>B Inputs. 


microCMOS 


The comparator’s outputs can drive 10 low power Schottky 
TTL (LS-TTL) equivalent loads, and is functionally, and pin 
equivalent to the 64LS85/74LS85. All Inputs are protected 
from damage due to static discharge by diodes to Vcc and 
ground. 

Features 

■ Typical propagation delay: 27 ns 

■ Wide operating voltage range: 2--6V 

■ Low input current: 1 ju,A maximum 

■ Low quiescent current: 80 ju,A maximum (74HC Series) 

■ Output drive capability: 10 LS-TTL loads 


Connection Diagram 


Dual-In-Line Package 

DATA INPUTS 


Vcc A3 B2 A2 A 1 



^A<B A=B A>B^ ^A>B A=B A<B^ GND 
CASCADE INPUTS OUTPUTS 


Order Number MM54HC85J or MM74HC85J, N 
See NS Package J16A or N16E 


Truth Table 


A3, B3 

A2, B2 

A3 > B3 

X 

A3<B3 

X 

A3 = B3 

A2> B2 

A3 = B3 

A2 < B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 

A3 = B3 

A2 = B2 


Comparing 

Inputs 


A1,B1 


Cascading 

Inputs 



3-66 
















Absolute Maximum Ratings (Notes i & 2 ) 

Supply Voltage (Vcc) - 0.5 to + 7.0V 

DC Input Voltage (V|fsj) - 1 .5 to Vcc + -SV 

DC Output Voltage (Vqut) “ 0.5 to Vcc ■*" 0.5V 

Clamp Diode Current (I|k. Iqk) ±20 mA 

DC Output Current, per pin (Iqlit) ± 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) -65“C to + 1 50‘’C 

Power Dissipation (Pq) (Note 3) 500 mW 

Lead Temp. (TjJ (Soldering 10 seconds) 260“C 


Operating Conditions 



Min 

Max 

Units 

Supply Voltage (Vcc) 

2 

6 

V 

DC Input or Output Voltage 
(V|N. Vqut) 

0 

Vcc 

V 

Operating Temp. Range (Ta) 

MM74HC 

-40 

+ 85 

“C 

MM54HC ^ 

-55 

+ 125 

“C 

Input Rise or Fall Times 

(tr.tf) Vcc=2.0V 


1000 

ns 

Vcc=4.5V 


500 

ns 

Vcc=6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

= 25X 

74HC 

TA=-40to85”C 

54HC 

TA=-55tOl25X 

Units 





Typ 

Guaranteed Limits 



Minimum High Level 



■ 

1.5 

1.5 

1.5 

V 


Input Voltage 


KIM 


3.15 

3.15 

3.15 

V 




1 6.0V 1 

■ 

4.2 

4.2 

4.2 

V 


Maximum Low Level 


QQI 

■j 


0.3 

0.3 



Input Voltage 





0.9 

0.9 







1.2 

1.2 

1.2 


Vqh 

Minimum High Level 

V|N=V|HOrV|L 

M 







Output Voltage 

|loUTk20 p.A 


2.0 

1.9 

1.9 

1.9 






4.5 

■SI 

4.4 

4.4 






6.0 


5.9 

5.9 

V 



V|N = V|H orViL 
|louTk4.0 mA 


4.2 

m 

3.84 

3.7 

V 



ilouTi^5.2 mA 


5.7 


5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H orV|L 



H 



■H 


Output Voltage 

|loUTl^20fiA 

2.0V 

0 

Bl 

0.1 

0.1 

HI 




4.5V 

0 

HI 

0.1 

0.1 

HI 




6.0V 

0 

mm 

0.1 

0.1 

^1 



V|N = V|H orViL 
|JoutI^ 4.0 mA 

4.5V 

0.2 

0.26 


- 0.4 

H 



1 *01171 ^5.2 mA 

6.0V 

0.2 

0.26 


0.4 

n 

l|N , 

Maximum Input 
Current 

V|N ~ Vcc 01' GND 



±0.1 

±1.0 

±1.0 

jaA 

Icc 

Maximum Quiescent 

V|N ~ Vcc 01' gnd 



8.0 

80 

160 

jllA 


Supply Current 









Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic "N” package: - 1 2 mW/*C from 65“C to BS'C; ceramic “J” package: - 1 2 mW/'C from 1 00®C to 1 25*C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|l occur at Vcc=5-5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 




3-67 


MM54HC85/MM74HC85 









































MM54HC85/MM74HC85 


AC Electrical Characteristics vcc= 5 v,TA= 25 "c,CL=i 5 pF.tr=tf= 6 ns 


Conditions 


Symbol 

Parameter 

tPHL. tpLH 

Maximum Propagation Delay Data Input to A<B or A> B 

tpHb tPLH 

Maximum Propagation Delay A= B Input to A= B Output 

tPHb tpLH 

Maximum Propagation Delay Cascade Input to Output 

tPHL. tPLH 

Maximum Propagation Delay Data Input to A= B 



AC Electrical Characteristics Cl=50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol Parameter 


tpHb tpLH Maximum Propagation 
Delay Data Input to 
Output 


Conditions Vcc 




Maximum Propagation Delay 
A = B Input to A = B Output 



tpHL. tPLH 

Maximum Propagation 

Delay Cascade Input 
to Output (except A = B) 


tlLH. tTHL 

Maximum Output Rise 
and Fall Time 


Qn 



CpD 

Power Dissipation Capacitance | 

(Note 5) 



Note 5: Cpo determines the no load dynamic power consumption, Pq = Cpo Vcc^ f+lcc Vcc. and the no load dynamic current consumption, 
Is = CpD Vcc t + icc- 


Typical Application 


GND— IA>Bin 
V cc— I A= Bin 
6ND— IA<Bin 


Cascading Comparators 


LEAST SIGNIFICANT I 
4-BIT WORDS 1 


A9 

A10 

MOST SIGNIFICANT All 
4-BIT words' B8 



3-68 























































3-69 


MM54HC85/MM74HC85 



MM54HC86/MM74HC86 


National 


Semiconductor 

V y 


microCMOS 


MM54HC86/MM74HC86 
Quad 2-Input Exclusive OR Gate 


General Description 

This EXCLUSIVE OR gate utilizes microCMOS Technology, 
3.5 micron silicon gate P-well CMOS, to achieve operating 
speeds similar to equivalent LS-TTL gates while maintaining 
the low power consumption and high noise immunity char- 
acteristic of standard CMOS integrated circuits. These 
gates are fully buffered and have a fanout of 10 LS-TTL 
loads. The MM54HC/74HC logic family is functionally as 
well as pin out compatible with the standard 54LS/74LS 
logic family. All inputs are protected from damage due to 
static discharge by internal diode clamps to Vcc and 
ground. 


Connection Diagram 


Features 

■ Typical propagation delay: 9 ns 

■ Wide operating voltage range: 2-6V 

■ Low input current: 1 juA maximum 

■ Low quiescent current: 20 fxA maximum (74 Series) 

■ Output drive capability: 1 0 LS-TTL loads 


Dual-ln-Line Package 


Vcc B4 A4 Y4 B3 A3 Y3 



A1 B1 Y1 A2 B2 Y2 GNO 

Top View 

Order Number MM54HC86J or MM74HC86J, N 
See NS Package J14A or N14A 


TL/F/5365-1 


Truth Tabie 


Inputs 

Outputs 

A 

B 

Y 

L 

L 

L 

L 

H 

H 

H 

L 

H 

H 

H 

L 


Y=A ® B=AB + AB 


3-70 



Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) “ 0.5 to + 7.0V 

DC Input Voltage (V|n) - 1 .5 to Vcc + 1 -SV 

DC Output Voltage (Vqut) -0.5 to Vcc + 0.5V 

Clamp Diode Current (I|k, Iqk) ±20 mA 

DC Output Current, per pin (Iout) ± 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) -65“C to + 1 50'’C 
Power Dissipation (Pq) (Note 3) 500 mW 

Lead Temperature (TJ 

(Soldering 10 seconds) 260°C 


Operating Conditions 



Min 

Max 

Units 

Supply Voltage (Vcc) 

2 

6 

V 

DC Input or Output Voltage 

0 

Vcc 

V 

(V|N. Vqut) 

Operating Temp. Range (Ta) 

MM74HC 

-40 

+ 85 

“C 

MM54HC 

-55 

+ 125 

°c 

Input Rise or Fall Times 

< 

o 

o 

11 

ro 

b 

< 


1000 

ns 

Vcc = 4.5 V 


500 

ns 

Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

. Parameter 

Conditions 

Vcc 

Ta = 

= 25°C 

74HC 

Ta=- 40 to 85°C 

54HC 

TA=-55to125“C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|H orV|L 








Output Voltage 

|IoutI^20 }xA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|HOrV|L 
llouTk4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



il0UTi^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H orViL 








Output Voltage 

|IoutI^ 20 fiA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|H orViL 
|loUTk4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



|IoutI^ 5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

•in 

Maximum Input 
Current 

V|N~ Vcc or gnd 

6.0V 


±0.1 

±1.0 

±1.0 

jliA 

•cc 

Maximum Quiescent 

V|N = Vcc or GND 

6.0V 


2.0 

20 

40 

JLtA 


Supply Current 

■out = 6 J^A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: -12 mW/*C from SS'Cto BS^C; ceramic “J” package: -12 mW/°C from 100*0 to 125*0. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HO at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc = 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for OMOS at the higher voltage and so the 6.0V values should be used. 



3-71 


MM54HC86/MM74HC86 




MM54HC86/MM74HC86 


AC Electrical Characteristics vcc= 5 v,TA= 25 °c,CL=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 



tPHL. tpLH 

Maximum Propagation 
Delay 


12 

20 

ns 


AC Electrical Characteristics Vcc= 2.0V to 6.0V, Cl= 50 pF, tr= tf = 6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vec 

Ta= 

25“C 

74HC 

Ta=-40 to 85“C 

54HC 

TA=-55tOl25*C 

Units 

Typ 

Guaranteed Limits 

tpHb tPLH 

Maximum Propagation 


2.0V 

60 

120 

151 

179 



Delay 


4.5V 

12 

24 

30 

36 

mm 




6.0V 

10 

20 

26 

30 

1 ns 

tjLH. tlHL 

Maximum Output Rise 


2.0V 

30 


95 


B 


and Fall Time 


4.5V 

8 

■a 

19 






6.0V 

7 

13 

16 



CpD 

Power Dissipation 

(per gate) 


25 




pF 


Capacitance (Note 5) 








C|N 

Maximum Input 





10 

io 

pF 


Capacitance 









Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f+ Ice Vcci and the no load dynamic current consumption, ls=CpQ Vec Icc- 


3-72 















National 

Semiconductor 


MM54HC107/MM74HC107 
Dual J-K Flip-Flops with Ciear 

General Description I 

These J-K Flip-Flops utilize microCMOS Technology, 3.5 
micron silicon gate P-well CMOS, to achieve the high noise 
immunity and low power dissipation of standard CMOS inte- 
grated circuits. These devices can drive 10 LS-TTL loads. 
These flip-flops are edge sensitive to the clock input and 
change state on the negative going transition of the clock 
pulse. Each one h^ independent J, K, CLOCK, and CLEAR 
inputs and Q and Q outputs. CLEAR is independent of the 
clock and accomplished by a low level on the input. 

The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 

All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 


Connection Diagram 

Duai-ln-Line Package 

Vcc CLR 1 CLK 1 K2 CLR 2 CLK 2 J2 


microCMOS 



Features 

■ Typical propagation delay: 16 ns 

■ Wide operating voltage range: 2~6V 

■ Low input current: 1 jaA maximum 

■ Low quiescent current: 40 jaA (74HC series) 

■ High output drive: 1 0 LS-TTL loads 


Truth Tabie 


Inputs 

Outputs 

CLR 

CLK 

J 

K 

Q 

Q 

L 

X 

X 

X 

L 

H 

H 

4- 

L 

L 

QO 

QO 

H 

4- 

H 

L 

H 

L 

H 

4. 

L 

H 

L 

H 

H 

i 

H 

H 

TOGGLE 

H 

H 

X 

X 

QO 

QO 


Order Number MM54HC107J or MM74HC107J, N 
See NS Package J14A or N 14 A 

Logic Diagram 



;K ^>o4-[>0-t 


107/MM74HC107 





MM54HC107/MM74HC107 


Absolute Maximum Ratings (Notes i & 2 ) 

Supply Voltage (Vcc) - 0-5 to + 7.0V 

DC Input Voltage (V|n) -1.5 to Vcc + 1 -SV 

DC Output Voltage (Vqut) “ 0-5 to Vcc + 0-5V 

Clamp Diode Current (I|k, Iqk) ± 20 mA 

DC Output Current, per pin (Iqlit) ± 25 mA 

DC Vcc or GND Current, per pin (Icc) ± 50 mA 

Storage T emperature Range (T stg) - 65‘*C to + 1 50®C 

Power Dissipation (Pq) (Note 3) 500 mW 

Lead Temperature (Tl) 

(Soldering 10 seconds) 260®C 

DC Electrical Characteristics (Note 4) 


Operating Conditions 



Min 

Max 

Units 

Supply Voltage (Vcc) 

2 

6 

V 

DC Input or Output Voltage 

0 

Vcc 

V 

(ViN. Vqut) 

Operating Temp. Range (Ta) 
MM74HC 

-40 

+ 85 

“C 

MM54HC 

-55 

+ 125 

"C 

Input Rise or Fall Times 
(tr.tf) Vcc=2.0V 


1000 

ns 

Vcc = 4.5 V 


500 

ns 

Vcc = 6.0 V 


400 

ns 


Symboi 

Parameter 

Conditions 

Vcc 

m 



54HC 

Ta=- 55 to125X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


1^9 


1.5 

1.5 

1.5 



Input Voltage 




3.15 

3.15 

3.15 







4.2 

4.2 

4.2 


V|L 

Maximum Low Level 



m 


0.3 

0.3 



Input Voltage 


WSm 



0.9 

0.9 






m 

1.2 

1.2 

1.2 


Vqh 

Minimum High Level 

V|N = V|HOrV|L 








Output Voltage 

|loUTk20 fiA 

2.0V 

2.0 

1.9 

1.9 

1,9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 
l•oUTl^4.0 mA 

4.5V 


3.98 

3.84 

3.7 

■■ 



jlouTl^6.2 mA 

6.0V 


5.48 

5.34 

5.2 


Vql 

Maximum Low Level 

ViN = V|HOrV|L 

■1 





BB 


Output Voltage 

liourl^sOfiA 


0 

0.1 

0.1 

0.1 






0 

0.1 

0.1 

0.1 





1^9 

0 

0.1 

0.1 

0.1 

bih 



V|N = V|HOrV|L 
|IoutI^ 4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 




6.0V 

0.2 

0.26 

0.33 

0.4 

V 

ilN 

Maximum Input 
Current 

V|N~VccorGND 

6.0V 


±0.1 

±1.0 

±1.0 

jliA 

•cc 

Maximum Quiescent 

V|N ~ Vcc 01' GND 

6.0V 



40 

80 



Supply Current 

•oUT=0 P-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 


Note 2: Unless othenvise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating plastic “N” packager -12 mW/®C from 65*C to SS'C; ceramic “J” package: -12 mW/®C from 100*C to 125“C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and VojJ occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively, (the Vjh value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-74 




























AC Electrical Characteristics vcc= 5 v.TA= 25 «c,CL=i 5 pF.tr=t,= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

^MAX 

Maximum Operating 
Frequency 


50 

30 

MHz 

tpHL. tpLH 

Maximum Propagation 
Delay Clock to Q or Q 


16 

21 

ns 

tpHL. tPLH 

Maximum Propagation 
Delay Clear to Q or Q 


21 

26 

ns 

tREM 

Minimum Removal Time, 
Clear to Clock 


10 

20 

ns 

ts 

Minimum Setup Time, 

J or K to Clock 


14 

20 

ns 

tH 

Minimum Hold Time 

J or K from Clock 


-3 

0 

ns 

tw 

Minimum Pulse Width, 
Clock or Clear 


10 

16 

ns 


AC Electrical Characteristics Cl =50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25°C 

74HC 

Ta=- 40 to 85°C 

54HC 

Ta=- 55 to125°C 

Units 

Typ 

Guaranteed Limits 

fMAX 

Maximum Operating 


2.0V 

9 , 

5 

4 

3 

MHz 


Frequency 


4.5V 

45 

27 

21 

18 

MHz 




6.0V 

53 

31 ' 

24 

20 

MHz 

tpHb tPLH 

Maximum Propagation 


2.0V 

70 

126 

160 

185 

ns 


Delay Clock toQorQ 


4.5V 

18 

25 

32 

37 

ns 




6.0V 

16 

21 

27 

32 

ns 

tpHL. tpLH 

Maximum Propagation 


2.0V 

126 

155 

194 

250 . 

ns 


Delay Clear to Q or Q 


4.5V 

25 

31 

39 

47 

, ns 




6.0V 

21 

26 

32 

40 

ns 

tREM 

Minimum Removal Time 


2.0V 

55 

100 

125 

150 

ns 


Clear to Clock 


4.5V 

11 

20 

25 

30 

ns 




6.0V 

9 

17 

21 

25 

ns 

ts 

Minimum Setup Time 


2.0V 

77 

100 

125 

150 

ns 


J or K to Clock 


4.5V 

15 

20 

25 

30 

ns 




6.0V 

13 

17 

21 

25 

ns 

tH 

Minimum Hold Time 


2.0V 

-3 

0 

0 

0 

ns 


J or K to Clock 


4.5V 

-3 

0 

0 

0 

ns 




6.0V 

-3 

0 

0 

0 

ns 

tw 

Minimum Pulse Width 


2.0V 

55 

80 

100 

120 

ns 


Clear or Clock 


4.5V 

11 

16 

20 

24 

ns 




6.0V 

10 

14 

18 

21 

ns 


Maximum Output Rise 


2.0V 

30 

75 

95 

110 

■i 

hhhh 

and Fall Time 


4.5V 

8 

15 

19 

22 


■^1 



6.0V 

7 

13 

16 

19 

wm 


Maximum Input Rise and 


2.0V 


1000 

1000 

1000 

n 


Fail Time 


4.5V 


500 

500 

500 


WKM 



6.0V 


400 

400 

400 

■9 

CpD 

Power Dissipation 

(per flip-flop) 


80 




pF 


Capacitance (Note 5) 








C|N 

Maximum Input 



5 

10 

10 

10 

pF 


Capacitance 








Note 5: Cpo determines the no load dynamic power consumption, Pd==Cpd Vcc^ f +I cc Vcc. and the no load dynamic current consumption, ls = CpD Vcc f+ Icc- 


3-75 


MM54HC107/MM74HC107 








MM54HC107/MM74HC1 07 


Typical Applications 


N Bit Binary Rippie Counter with Enable and Reset 

COUNTER ENABLE 



BIT 3 BIT 2 LSB 


TL/F/5304-4 


N Bit Shift Register with Clear 


CLEAR 



TL/F/5304-5 


3-76 





National 

Semiconductor 


MM54HC109/MM74HC109 

Dual J-K Flip-Flops with Preset and Clear 


microCMOS 


General Description 

These J-K FLIP-FLOPS utilize microCMOS Technology, 3.5 
micron silicon gate P-well CMOS, to achieve the low power 
consumption and high noise immunity of standard CMOS 
integrated circuits, along with the ability to drive 10 LS-TTL 
loads. 

Each flip flop has independent J, K PRESET, CLEAR and 
CLOCK inputs and Q and Q outputs. These devices are 
edge sensitive to the clock input and change state on the 
positive going transition of the clock pulse. Clear and preset 
are independent of the clock and accomplished by a low 
logic level on the corresponding input. 


The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 
All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 20 ns 

■ Wide operating voltage range: 2-6V 

■ Low input current: 1 /xA maximum 

■ Low quiescent current: 40 /xA maximum (74HC Series) 

■ Output drive capability: 10 LS-TTL loads 


Connection Diagram 

Dual-In-Line Package 

Vcc CLR2 J2 K2 CLK 2 PR 2 Q2 Q2 


L CLR_ 

Ik q 





CLR 1 J1 K1 CLK 1 PR 1 01 01 GND 

Top View 

Order Number MM54HC109J or MM74HC109J, N 
See NS Package J16A or N16E 


Function Tabie 


Inputs 

Outputs 

PR 

CLR 

CLK 

J 

K 

Q 

Q 

L 

H 

X 

X 

X 

H 

L 

H 

L 

X 

X 

X 

L 

H 

L 

L 

X 

X 

X 

H* 

H* 

H 

H 

T 

L 

L 

L 

H 

H 

H 

T 

H 

L 

TOGGLE 

H 

H 

T 

L 

H 

QO 

QO 

H 

H 

T 

H 

H 

H 

L 

H 

H 

L 

X 

X 

QO 

QO 


3-77 


MM54HC109/MM74HC109 



MM54HC109/MM74HC109 


Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

- 0.5 to + 7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5toVcc+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vout) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqlit) 

±25 mA 

Operating Temp. Range (T^) 
MM74HC 

-40 

±85 


DC Vcc or (jND Current, per pin (Ice) 

±50mA 

MM54HC 

-55 

±125 

“C 

Storage Temperature Range (Tstg) 

-65“Cto +150“C 

Input Rise or Fall Times 




Power Dissipation (Pd) (Note 3) 

500 mW 

(tr.tf) Vcc = 2.0V 


1000 

ns 

Lead Temp. (Tl) (Soldering 10 seconds) 

260“C 

Vcc = 4.5V 


500 

ns 


Vcc = 6.0V 


400 

ns 


DC Eiectrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

= 25"C 

74HC 

Ta=- 40 to 85X 

54HC 

TA=-55to125‘’C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 





V 


Input Voltage 


4.5V 





V 




6.0V 


1^91 



V 

VlL 

Maximum Low Level 


2.0V 



0.3 

0.3 

V 


Input Voltage 


4.5V 



0.9 

0.9 

V 




6.0V 



1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|n = V|h orViL 








Output Voltage 

|loufl^20 ^A 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orV|L 
|1outI^4.0 mA 

4.5V 


3.98 

3.84 

3.7 

V 



1101171^6.2 mA 

6.0V 


5.48 

5.34 

5.2 

V 

Vol 

Maximum Low Level 

V|N=V|HorV|L 








Output Voltage 

|IoutI^20ju.A 

2.0V 

0 

0.1 

0.1 


y 




4.5V 

0 

0.1 

0.1 


V 




6.0V 

0 

0.1 

0.1 


V 



V|N = V|H orViL 
I^OUTN4.0 mA 

4.5V 

■ 



0.4 

V 



ij0UTl^6.2 mA 

6.0V 

■1 



0.4 

V 

l|N 

Maximum Input 
Current 

V|N~ Vcc or GND 

6.0V 


±0.1 

±1.0 

±1.0 


Icc 

Maximum Quiescent 

V|N~ Vcc 0*' gnd 

6.0V 


4.0 

40 

80 

jxA 


Supply Current 

Iout=6 M-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N" package: - 1 2 mW/®C from 65*C to BS'C; ceramic “J” package: - 1 2 mW/*C from 1 00°C to 1 25'’C. 
Note 4: For a power supply of 5V ± 1 0% the worst case output voltages (Vqh. and Vol) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-78 












AC Electrical Characteristics vcc= 5 v,TA= 25 oc.cL=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 



^MAX 

Maximum Operating Frequency 


50 

30 

MHz 

tpHL. fPLH 

Maximum Propagation 

Delay, Clock to Q or Q 


m 

30 

Bi 

tpHL. tPLH 

Maximum Propagation _ 

Delay, Preset or Clear to Q or Q 


m 

42 

■ 

tREM 

Minimum Removal Time, Preset or Clear to Clock 



5 


ts 

Minimum Setup Time, J or K to Clock 



20 

ns 

tH 

Minimum Hold Time, J or K to Clock 



0 

ns 

tw 

Minimum Pulse Width: Preset, Clear or Clock 


9 

16 

ns 


AC Electrical Characteristics Cl = 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25"C 

74HC 

Ta=- 40 to 85“C 

54HC 

Ta=- 55 to125‘’C 

Units 





Typ 

Guaranteed Limits 


^MAX 

Maximum Operating 


2.0V 


5 

4 

4 

MHz 


Frequency 


4.5V 


27 

21 

18 

MHz 




6.0V 


31 

24 

20 

MHz 

tpHL. tPLH 

Maximum Propagation 



88 



261 

ns 


Delay, Clock to Q or Q 



18 



52 

ns 





15 



44 

ns 

tpHb tPLH 

Maximum Propagation 



115 

230 

290 

343 

MM 


Delay, Preset or Clear 



23 

46 

58 

69 



to Q or Q 



20 

39 

49 

58 

MM 

tREM 

Minimum Removal Time 


EQSI 


25 

32 

37 

ns 

Preset or Clear 




5 

6 

7 

ns 


to Clock 


mmm 


4 

5 

6 

ns 

ts 

Minimum Setup Time 


KQn 


100 

126 

119 

ns 


J or K to Clock 




20 

25 

30 

ns 




EE3I 


17 

21 

20 

ns 

tH 

Minimum Hold Time 


QSQI 

■■1 

0 

0 

0 

ns 


Clock to J or K 




0 

0 

0 

ns 




EEEl 


0 

0 

0 

ns 

tw 

Minimum Pulse Width 




80 

100 

120 

ns 


Clock, Preset or Clear 




16 

20 

24 

ns 





8 

14 

18 

20 

ns 

tjLH. tjHL 

Output Rise and 




75 

95 

110 

ns 


Fall Time 




15 

19 

22 

ns 




Eral 


13 

16 

19 

ns 


Maximum Input Rise and 




1000 

1000 

1000 

ns 


Fall Time 




500 

500 

500 

ns 





HI 

400 

400 

400 

ns 




m 

80 




pF 




■ 



10 

10 

pF 


Note 5: CpD determines the no load dynamic power consumption, Po=CpD Vcc^ t+lcc Vcc. and the no load dynamic current consumption, ls=CpD Vcc t+ Icc- 


3-79 


MM54HC109/MM74HC109 




























MM54HC112/MM74HC112 


National 

JtSi Semiconductor 

MM54HC1 12/MM74HC112 

Dual J-K Flip-Flops with Preset and Clear 



microCMOS 


General Description 

These high speed (30 MHz minimum) J-K Flip-Flops utilize 
microCMOS Technology, 3.5 micron silicon gate P-well 
CMOS, to achieve the low power consumption and high 
noise immunity of standard CMOS integrated circuits, along 
with the ability to drive 1 0 LS-TTL loads. 

Each flip-flop has independ^t J, K, PRESET, CLEAR, and 
CLOCK inputs and Q and Q outputs. These devices are 
edge sensitive to the clock input and change state on the 
negative going transition of the clock pulse. Clear and pre- 
set are independent of the clock and accomplished by a low 
logic level on the corresponding input. 


The 54HC/74HC logic family Is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 
All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 16 ns 

■ Wide operating voltage range 

■ Low input current: 1 maximum 

■ Low quiescent current: 40 jaA (74HC Series) 

■ High output drivel: 1 0 LS-TTL loads 


Connection and Logic Diagrams Truth Tabie 


Dual-In-Line Package 

Vcc CLR 1 CLR 2 CLK 2 K2 J2 PR 2 Q2 



Order Number MM54HC112J or MM74HC112J, N 
See NS Package J16A or N16E 


Inputs 

Outputs 

PR 

CLR 

CLK 

J 

L 

Q 

Q 

L 

H 

X 

X 

X 

H 

L 

H 

L 

X 

X 

X 

L 

H 

L 

L 

X 

X 

X 

L* 

L* 

H 

H 

1 

L 

L 

QO 

QO 

H 

H 

1 

H 

L 

H 

L 

H 

H 

1 

L 

H 

L 

H 

H 

H 

1 

H 

H 

TOGGLE 

H 

H 

H 

X 

X 

QO 

QO 


*This is an unstable condition, and is not guaranteed 



3-80 




Absolute Maximum Ratings (Notes i & 2 ) 

Supply Voltage (Vcc) — 0.5 to + 7.0V 

DC Input Voltage (V|n) - 1 :5 to Vcc + 1 -SV 

DC Output Voltage (Vqut) “ 0.5 to Vcc + 0.5V 

Clamp Diode Current (I|k, Iqk) ± 20 mA 

DC Output Current, per pin (Iqlit) ^ 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) -65°C to + 1 50°C 
Power Dissipation (Pq) (Note 3) 500 mW 

Lead Temp. (T l) (Soldering 1 0 seconds) 260°C 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(Vin.Vout) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 

Input Rise or Fall Times 
(tr.tf) Vcc=2.0V 
Vcc = 4.5V 
Vcc = 6.0V 


DC Electrical Characteristics (Note 4) 


Symboi 

Parameter 

V|H 

Minimum High Level 
Input Voltage 

V|L 

Maximum Low Level 
Input Voltage 


Conditions 



Minimum High Level 
Output Voltage 

V|N = V|HorV|L 
|louTk20 IX A- 


V|N = V|HorV|L 
I^OUTk4.0 mA 
ilouTi^5.2 mA 


Maximum Low Level V|n = V m or V|l 
O utput Voltage | IqlitI ^ 20 /xA 


V|N = V|HorV|L 
|louTk4.0 mA 
ilouTi^5.2 mA 


Ta = 25“C 
Typ 


74HC 

= -40to85°C Ta= 
Guaranteed Limits 


54HC 

-55 to125'’C 




l|N 

Maximum Input 
Current 

V|N = VccOrGND 

6.0V 


±0.1 

±1.0 

±1.0 

jxA 

icc 

Maximum Quiescent 
Supply Current 

V|N = VccorGND 
Iout=0fA 

6.0V 


4.0 

40 

80 



Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: -12 mW/^Cfrom 65*Cto 85*0; ceramic “J” package: -12 mW/“Cfrom lOO'Cto 125®C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-81 


MM54HC112/MM74HC112 










MM54HC112/MM74HC112 


AC Electrical Characteristics vcc=5v,TA=25“c,CL=i5pF,tf=t,=6ns 


Parameter 

Conditions 

Typ 

Guaranteed Limit 

Units 


Maximum Operating 
Frequency 

. 

50 

30 

MHz 

tpHL. tpLH 

Maximum Propagation 

Delay, Clock to Q or Q 


16 

21 

ns 

tpHL.tPLH 

Maximum Propagation 

Delay, Clear to Q or Q 


21 

26 

ns 

tpHL. tPLH, 

Maximum Propagation 

Delay, Preset to Q or Q 


23 

28 

ns 

tREM 

Minimum Removal Time, 
Preset or Clear to Clock 


10 

20 

ns 

ts 

Minimurh Setup Time 

J or K to Clock 


14 

20 

ns 

tH 

Minimum Hold Time 

J or K from Clock 

- 


0 

ns 

tw 

Minimum Pulse Width 

Clock Preset or Clear 


10 

16 

ns 

AC El6CtriCdl Chdrsctoristics CL=50pF,tr=tf=6 ns (unless otherwise specified) 

Symbol 

Parameter 

Conditions 

Vcc 

Ta=25X 

74HC 

Ta=- 40 to 85“C 

54HC 

Ta=- 55 to125°C 

Units 

Typ 

Guaranteed Limits 

^MAX 

Maximum Operating 
Frequency 


2.0V 

4.5V 

,6.0V 

9 

45 

53 

5 

27 

31 

4 

21 

24 

3 

18 

20 

MHz 

MHz 

MHz 

tPHL. tPLH 

Maximum Propagation 

Delay, Clock to Q or Q 


2.0V 

4.5V 

6.0V 

100 

20 

17 

126 

25 

21 

160 

32 

27 

183 

37 

32 

ns 

ns 

ns 

tPHL. tpLH 

Maximum Propagation 

Delay, Clear to Q or Q 


2.0V 

4.5V 

6.0V 

126 

25 

21 

155 

31 

26 

191 

39 

33 

250 

47 

40 

ns 

ns 

ns 

tPHL. tpLH 

Maximum Propagation 

Delay, Preset to Q or Q 


2.0V 

4.5V 

6.0V 

137 

27 

23 

165 

33 

28 

210 

41 

35 

240 

50 

40 

ns 

ns 

ns 

tREM 

Minimum Removal Time 
Preset or Clear 
to Clock 


2.0V 

4.5V 

6.0V 

55 

11 

9.4 

100 

20 

17 

125 

25 

21 

150 

30 

25 

ns 

ns 

ns 

■ 

Minimum Setup Time 

J or K to Clock 


m 

i 


125. 

25 

21 

150 

30 

25 

n 

tH 

Minimum Hold Time 

J or K from Clock 


2.0V 

4.5V 

6.0V 

-3 

-3 

-3 


0 

0 

0 

0 

0 

0 

ns . 

ns 

ns 

tw 

Minimum Pulse Width 

Preset, Clear or Clock 


2.0V 

4.5V 

6.0V 

55 

11 

9 

80 

16 

14 

100 

' 20 

18 


ns 

ns 

ns 

m 

Maximum Output Rise 
and Fall Time 


i 


75 

15 

13 

95 

19 

16 

110 

22 

19 

H 

tr.tf 

Maximum Input Rise and 

Fall Time 


2.0V 

4.5V 

6.0V 


1000 

500 

400 

1000 

500 

400 

1000 

500 

400 

ns 

ns 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per flip-flop) 


80 




PF 

C|N 

Maximum Input Capacitance 



5 

10 

10 

10 

PF . 

Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ t+lcc Vcc. and the no load dynamic current consumption, ls=CpD Vcc t+ Icc- 


3-82 




































Typical Applications 


N Bit Presettable Ripple Counter with Enable and Reset 
DATA C DATA B 


COUNTER ENABLE 


CLOCK 

RESET 


1 

PRESET 


■ 

U J 

• • • 

1 

CLEAR 

TO 

■ 

^ CLOCK ^ 

NEXT BIT 

■ 



DATA A 

__l 

llllllllllllllllllll^^ 

Q 

PRESET 

J 


CLEAR 

Q 

CLOCK ^ 


BIT 3 


BIT 2 


LSB 


TL/F/5307-4 


N Bit Parallel Load/Seriai Load Shift Register with Clear 
DATA A DATA B DATA C 



TL/F/5307-5 


3-83 


MM54HC112/MM74HC112 





MM54HC113/MM74HC113 


National 

— c — F — 

Semiconductor 

\ 7 


microCMOS 


Dual J-K Flip-Flops with Preset 


General Description 

These high speed J-K Flip-Flops utilize microCMOS Tech- 
nology, 3.5 micron silicon gate P-well CMOS, to achieve the 
high noise imrnunity and low power dissipation of standard 
CMOS integrated circuits. These devices can drive 10 LS- 
TTL loads. 

These flip-flops are edge sensitive to the clock Input and 
change state on the negative going transition of the clock 
pulse. Each one has iridependent J, K, CLOCK, and PRE- 
SET inputs and Q and Q inputs. PRESET is Independent of 
the clock and accomplished by a low level on the input. 
The 54HC/74HC logic family is functionally as well as pin- 


out compatible with the standard 54LS/74LS logic family. 
All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 16 ns 

■ Wide operating voltage range: 2-6V 

■ Low input current: 1 ijlA maximum 

■ Low quiescent current: 40 julA (74HC Series) 

■ High output drive: 1 0 LS-TTL loads 


Cdnnection Diagram and Truth Table 

DuaMn-Line Package 

Vcc CLK 2 K2 J2 PR2 Q2 Q2 



GND 

TL/F/5073-1 


Top View 

Order Number MM54HC113J or MM74HC113J, N 
See NS Package J14A or N14A 


Logic Diagram 



CL 

T 


TL/F/5073-2 


3-84 









Absolute Maximum Ratings 

Supply Voltage (Vcc) 

DC Input Voltage (V|n) 

DC Output Voltage (Vout) 

Clamp Diode Current (I|k, Iqk) 

DC Output Current, per pin (Iqlit) 

DC Vcc or GND Current, per pin (Ice) 

Storage Temperature Range (Tstg) 

Power Dissipation (Pq) (Note 3) 

Lead Temp. (J[) (Soldering 10 seconds) 


- 1.6 

-0.5 


65 ^ 


(Notes 1 & 2) 
■0.5 to +7.0V 
to Vcc + 1.5V 
to Vcc + 0.5V 
±20 mA 
±25 mA 
±50 mA 
Cto +150“C 
500 mW 
' 260“C 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(V|N. Vout) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 

Input Rise or Fall Times 
(tr.tf) Vcc=2.0V 
Vcc = 4.5 V 
Vcc = 6.0 V 


Max 

Units 

6 

V 

Vcc 

V 

+ 85 

“C 

+ 125 

“C 

1000 

ns 

500 

ns 

400 

ns 


DC Eiectrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

= 25"C 

74HC 

Ta= -40 to 85"C 

54HC 

Ta=- 55 to125“C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 



■ 

1.5 

1.5 

1.5 

V 


Input Voltage 




3.15 

3.15 

3.15 

V 





■ 

4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 



m 

0.3 

0.3 

0.3 

V 


Input Voltage 




0.9 

0.9 

' 0.9 

V 






1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|HOrViu 

Mi 







Output Voltage 

|louTk20 fxA 


2.0 

1.9 

1.9 

1.9 

V 





4.5 

4.4 

4.4 

4.4 

V 





6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 
|IoutI^4.0 mA 


4.2 

3.98 

3.84 

3.7 

V 



|louTi^5.2 mA 


5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H orViL 

M 







Output Voltage 

[loUjI^SOjiA 


0 

0.1 

0.1 

0.1 

V 




^g9 

0 

0.1 

0.1 

0.1 

V 




QSJ9 

0 

0.1 

0.1 

0.1 

V 



V|n = V|h orViL 
|louTk4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



^^OUTU5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

hN 

Maximum input 
Current 

V|N = Vcc 01' GND 



±0.1 

±1.0 

±1.0 


•cc 

Maximum Quiescent 

V|N = Vcc or gnd 

6.0V 


4.0 

40 

80 

juA 


Supply Current 

Iqut^O mA 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3; Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/*C from 65®C to ceramic “J” package: - 1 2 mW/®C from 1 00*C to 1 25*C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc = 5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, Icc. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-85 


MM54HC113/MM74HC113 




























MI\/I54HC113/MM74HC113 


AC Electrical Characteristics vcc= 5 v,TA= 25 "c.cL=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

^MAX 

Maximum Operating 

Frequency 


50 

30 

MHz 

fpHL. tPLH 

Maximum Propagation Delay, 
Clock to Q or Q 


16 

21 

ns 

tpHL. tPLH 

Maximum Propagation Delay, 
Preset to Q or Q 


23 

28 

ns 


Minimum Removal Time, 

Preset to Clock 


10 

20 

ns 

ts 

Minimum Setup Time, 

J or K to Clock 


14 

20 

ns 

tH 

Minimum Hold Time, 

J or K from Clock 


-3 

0 

ns 

tw 



10 

16 

ns 


AC Eiectricai Characteristics Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25°C 

74HC 

Ta=- 40 to S5°C 

54HC 

Ta=- 55 to125°C 

Units 



KM 



^MAX 

Maximum Operating 


2.0V 

9 

5 

4 

3 

MHz 


Frequency 


4.5V 

45 

27 

21 

18 

MHz 




6.0V 

53 

31 

24 

20 

MHz 

tPHL. tPLH 

Maximum Propagation 


2.0V 

100 

125 

160 

183 

ns 


Delay, Clock to Q or Q 


4.5V 

20 

25 

32 

37 

ns 




6.0V 

17 

33 

27 

32 

ns 

tpHL. tPLH 

Maximum Propagation 


2.0V 

137 

165 

206 

239 

ns 


Delay, Preset to Q or Q 


4.5V 

27 

33 

41 

47 

ns 




6.0V 

23 

28 

35 

40 

ns 

tREM 

Minimum Removal Time 


2.0V 

55 

100 

125 

150 

ns 


Preset to Clock 


4.5V 

11 

20 

25 

30 

ns 




6.0V 

9 

17 

21 

25 

ns 


Minimum Setup Time 


2.0V 

77 

100 

125 

150 

ns 


J or K to Clock 


4.5V 

15 

20 

25 

30 

ns 




6.0V 

13 

17 

21 

25 

ns 

tH 

Minimum Hold Time 


2.0V 

-3 

0 

0 

0 

ns 


J or K from Clock 


4.5V 

-3 

0 

0 

0 

ns 




6.0V 

-3 

0 

0 

0 

ns 

tw 

Minimum Pulse Width, 


2.0V 

55 

80 

100 

120 

ns 


Preset, Clear or Clock 


4.5V 

11 

16 

20 

24 

ns 




6.0V 

9 

14 

18 

20 

ns 

tTLH. tjHL 

Maximum Output Rise 


^^1 


WM 

95 

110 

ns 


and Fall Time 


e!^ 


■a 

19 

22 

ns 




6.0V 

7 

13 

16 

19 

ns 

tr. tf 

Maximum Input Rise and 


2.0V 


1000 

1000 

1000 

ns 


Fall Time 


4.5V 


500 

500 

500 

ns 




6.0V 


400 

400 

400 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per flip-flop) 


80 




pF 

C|N 

Maximum Input Capacitance 



5 

10 

10 

10 

pF 


r Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ Icc Vcc. and the no load dynamic current consumption, ls = CpQ Vcc Icc- 


3-86 














3-87 


MM54HC113/MM74HC113 






MM54HC123A/MM74HC123A 


National 


Semiconductor 

microCMOS 


MM54HC 1 23A/MM74HC1 23A 

Dual Retriggerable Monostable Multivibrator 


General Description 

The MM54/74HC123A high speed monostable multivibra- 
tors (one shots) utilize microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS. They feature speeds comparable 
to low power Schottky TTL circuitry while retaining the low 
power and high noise immunity characteristic of CMOS cir- 
cuits. 

Each multivibrator features both a negative, A, and a posi- 
tive, B, transition triggered input, either of which can be 
used as an inhibit input. Also included is a clear input that 
when taken low resets the one shot. The ’HC123 can be 
triggered on the positive transition of the clear while A is 
held low and B is held high. 

The ’HC123A is retriggerable. That is it may be triggered 
repeatedly while their outputs are generating a pulse and 
the pulse will be extended. 

Pulse width stability over a wide range of temperature and 
supply is achieved using linear CMOS techniques. The out- 


Connection Diagram 


put pulse equation is simply: PW= (Rext) (Cext); where PW 
is in seconds, R is in ohms, and C is in farads. All inputs are 
protected from damage due to static discharge by diodes to 
Vcc and ground. 

Features 

■ Typical propagation delay: 40 ns 

■ Wide power supply range: 2V-6V 

■ Low quiescent current: 80 jaA maximum (74HC Series) 

■ Low input current: 1 fiA maximum 

■ Fanout of 10 LS-TTL loads 

■ Simple pulse width formula T = RC 

■ Wide pulse range: 400 ns to «> (typ) 

■ Part to part variation: ± 5% (typ) 

■ Schmitt Trigger A & B inputs enable infinite signal input 
rise and fall times. 


Dual-ln-Line Package Timing Component 


Rexti 

Vcc Cext Cexti Q1 Q2 CLR2 62 A2 



Order Number MM54HC123AJ or 
MM74HC123AJ, N 
See NS Package J16A or N16E 

Truth Table 


inputs 

Outputs 

Ciear 

A 

B 

Q 

Q 

L 

X 

X 

L 

H 

X 

H 

X 

L , 

H 

X 

X 

L 

L 

H 

H 

L 

T 

-TL 

ur 

H 

i 

H 

-TL 

u- 

t 

L 

H 

jn_ 

U" 


Vcc 



TO Cext TO r/Cext 
TERMINAL TERMINAL 


H = High Level 
L = Low Level 

t = Transition from Low to High 
T = Transition from High to Low 
_n= One High Level Pulse 
~Lr= One Low Level Pulse 
X = Irrelevant 


TL/F/5206-2 


3-88 




Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) ~ 0.5V to -f 7.0V 

DC Input Voltage (V|n) - 1 .5V to Vcc + 1 -SV 

DC Output Voltage (Vqut) ~ 0.5V to Vcc + 0.5V 

Clamp Diode Current (I|k, Iqk) ^ ±20 mA 

DC Output Current, per pin (Iout) i 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) -65‘’C to ± 1 50‘’C 
Power Dissipation (Pp) (Note 3) 500 mW 

Lead Temperature (Tl) 

(Soldering 10 seconds) 260“C 


Operating Conditions 



Min 

Max 

Units 

Supply Voltage (Vcc) 

2 

6 

V 

DC Input or Output Voltage 

0 

Vcc 

V 

(V|N. Vqut) 

Operating Temp. Range (Ta) 
MM74HC 

-40 

±85 

“C 

MM54HC 

-55 

±125 

°c 

Input Rise or Fall Times 
(Clear Input) 

(tr.tf) Vcc=2.0V 


1000 

ns 

Vcc = 4.5V 


500 

ns 

Vcc = 6.0V 


400 

ns 


DC Eiectricai Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25'’C 

74HC 

TA=-40to85X 

54HC 

Ta=- 55 tOl25X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level Input 


2.0V 


1.5 

1.5 

1.5 

V 


Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level Input 


2.0V 

■ 


0.3 

0.3 

V 


Voltage 


4.5V 



0.9 

0.9 

V 




6.0V 

Wm 

1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|H orViL 








Output Voltage 

hoUTk 20 fiA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 






V 



llouTk 4.0 mA 

4.5V 


3.98 

3.84 

3.7 

V 



hoUTl^ 5.2 mA 

6.0V 


5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|HOrV|L 








Output Voltage 

|loUTt^20fiA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



ViN = V|H orViL 






V 



|IoutI^ 4 mA 

4.5V 

0.2 

0.26 

0.33 


V 



ilouTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 


V 

•in 

Maximum Input Current 
(Pins 7, 15) 

V|N ~ Vcc Q*' GND 

6.0V 


±0.5 

±5.0 

±5.0 

juA 

l|N 

Maximum Input Current 
(all other pins) 




±0.1 

±1.0 


juA 

Icc 

Maximum Quiescent Supply 

V|N~Vcc or GND 

6.0V 



80 

160 

IxA 


Current (standby) 

*OUT=0 M • 







Icc 

Maximum Active Supply 

V|N~ Vcc or GND 

2.0V 

36 

80 


130 

fxA 


Current (per 

R/Cext~0-5Vcc 

4.5V 

0.33 

1.0 


1.6 

mA 


monostable) 


6.0V 

0.7 

2.0 


3.2 

mA 


Note 1: Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation Temperature Derating: 


Plastic “N” Package: -12mW/*C from SS'C to BS'C 
Ceramic “J” Package: -12mW/®C from 100®C to 125*0, 

Note 4: For a power supply of 5V ±10% the worst-case output voltages (Vqh. Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst-case Vm and V|l occur at Vcc = 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst-case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6,0V values should be used. 



3-89 


MM54HC123A/MI\/I74HC123A 



























MM54HC123A/MM74HC123A 


AC Electrical Characteristics vcc= 5 v,ta= 25 ”c, cl= 15 pF,tr=tf=6 ns 


Symbol 

Parameter 




Units 

tPLH 

Maximum Trigger Propagation Delay 

A, B or Clear to Q 




ns , 

tPHL 

Maximum Trigger Propagation Delay 

A, B or Clear to Q 


25 

42 

ns 

tpHL 

Maximum Propagation Delay, Clear to Q 


20 

27 


tpLH 

Maximum Propagation Delay, Clear to Q 


22 

33 

ns 

tw 

Minimum Pulse Width, A, B or Clear 


14 

26 

ns 

fpEM 

Minimum Clear Removal Time 



0 

ns 

tWQ(MIN) 

Minimum Output Pulse Width 

Q. C 
00 

CVl CM 

II II 

UJ 111 

0 a: 

400 


ns 

two 

Output Pulse Width 

CexT“'^000 

RexT”^0 kft 

10 




AC Electrical Characteristics Cl = 50 pF tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25‘’C 

74HC 

Ta=- 40 to SSX 

54HC 

Ta=- 55 to125“C 

Units 

09 

Guaranteed Limits 

tpLH 

Maximum Trigger Propagation 


2.0V 

77 

169 

194 

210 

ns 


Delay, A, B or Clear to Q 


4.5V 

26 

42 

51 

57 

ns 




6.0V 

21 

32 

39 

44 

ns 

tPHL 

Maximum Trigger Propagation 


2.0V 

88 


229 

250 

ns 


Delay, A, B or Clear to Q 


4.5V 

29 


60 

67 

ns 




6.0V 

24 


46 

51 

ns 

tpHL 

Maximum Propagation Delay 


2.0V 

54 

114 

132 

143 

m 


Clear to Q 


4.5V 

23 

34 

41 

45 





6.0V 

19 

28 

33 

36 


tPLH 

Maximum Propagation Delay 


2.0V 

56 

IQ 


147 

M 


Clear to Q 


4.5V 

25 



46 





6.0V 

20 

HI 


37 


tw 

Minimum Pulse Width 


2.0V 





m 


A, B, Clear 


4.5V 















tpEM 

Minimum Clear 


2.0V 

■ 


0 

0* 

B 


Removal Time 


4.5V 

■ 


0 

0 





6.0V 

■ 


0 

0 


tTLH. tlHL 

Maximum Output 


2.0V 





B 


Rise and Fall Time 


4.5V 


11 



H 




6.0V 


H 



B 

tWQ(MIN) 

Minimum Output 

CexT= 28 pF 

2.0V 

1.5 

■ 



B 


Pulse Width 

REXT = 2kft 

4.5V 

450 




wm 



REXT=6kJI (Vcc = 2V) 

6.0V 

0 

00 

CO 

■ 



H 

tWQ 

Output Pulse Width 

Cext=0-1 

Min 


D 




ms 






■ 








Max 

iiW 

1 

B 



ms 

C|N 

Maximum Input 


■ 


20 

20 

20 

pF 


Capacitance (Pins 7 & 1 5) 


■ 






C|N 

Maximum input 


■ 

B 


10 

10 

pF 


Capacitance (other inputs) 


■ 

■ 






3-90 


































MM54HC123A/MM74HC123A 












MM54HC123A/MM74HC123A 


TRIGGER OPERATION 

As shown in Figure 1 and the logic diagram before an input 
trigger occurs, the one shot is in the quiescent state with the 
Q output low, and the timing capacitor Cext completely 
charged to Vcc- When the trigger input A goes from Vcc to 
GND (while inputs B and clear are held to Vcc) a valid trig- 
ger is recognized, which turns on comparator C1 and N- 
channel transistor N1 ©. At the same time the output latch 
is set. With transistor N1 on, the capacitor Cext rapidly dis- 
charges toward GND until Vrefi is reached. At this point 
the output of comparator C1 changes state and transistor 
N1 turns off. Comparator C1 then turns off while at the 
same time comparator C2 turns on. With transistor N1 off, 
the capacitor Cext begins to charge through the timing re- 
sistor, Rext. toward Vcc- When the voltage across Cext 
equals Vref 2. comparator C2 changes state causing the 
output latch to reset (Q goes low) while at the same time 
disabling comparator C2. This ends the timing cycle with the 
monostable in the quiescent state, waiting for the next trig- 
ger. 

A valid trigger is also recognized when trigger input B goes 
from GND to Vcc (while input A Is at GND and Input clear is 
at Vcc®)- The ’HC123A can also be triggered when clear 
goes from GND to Vcc (while A is at GND and B is at 
Vcc®)- 

It should be noted that in the quiescent state Cext is fully 
charged to Vcc causing the current through resistor Rext ^ 
be zero. Both comparators are “off” with the total device 
current due only to reverse junction leakages. An added 
feature of the ’HC1 23A is that the output latch Is set via the in- 
put trigger without regard to the capacitor voltage. Thus, prop- 
agation delay from trigger to Q is Independent of the value 
of Cext. Rext. or the duty cycle of the input waveform. 


RETRIGGER OPERATION 

The ’HC123A is retrIggered if a valid trigger occurs ® fol- 
lowed by another trigger ® before the Q output has re- 
turned to the quiescent (zero) state. Any retrigger, after the 
timing node voltage at pin or has begun to rise from Vrefi, 
but has not yet reached Vref 2, will cause an Increase in 
output pulse width T. When a valid retrigger is Initiated ® , 
the voltage at the R/Cext pio will again drop to Vrefi be- 
fore progressing along the RC charging curve toward Vcc- 
The Q output will remain high until time T, after the last valid 
retrIgger. 

Because the trigger-control circuit flip-flop resets shortly af- 
ter Cx has discharged to the reference voltage of the lower 
reference circuit, the minimum retrIgger time, t^r is a function 
of internal propagation delays and the discharge time of Cx: 
t ^ 187 565 + (0.256 Vcc)Cx 

^ Vcc ~ 0-7 [Vcc ~ 0-7] 2 
RESET OPERATION 

These one shots may be reset during the generation of the 
output pulse. In the reset mode of operation, an input pulse 
on clear sets the reset latch and causes the capacitor to be 
fast charged to Vcc by turning on transistor Q1 (D . When 
the voltage on the capacitor reaches Vref 2. the reset latch 
will clear and then be ready to accept another pulse. If the 
clear input is held low, any trigger inputs that occur will be 
inhibited and the Q and Q outputs of the output latch will 
not change. Since the Q output is reset when an input low 
level is detected on the Clear Input, the output pulse T can 
be made significantly shorter than the minimum pulse width 
specification. 


Typical Output Pulse Width vs. 
Timing Components 



TIMING CAPACITOR (F) 

TL/F/5206-7 


Typical Distribution of Output 
Pulse Width, Part to Part 



0.92 0.96 1.00 1.04 1.06 

OUTPUT PULSE WIDTH (ms) 

TL/F/5206-8 


Typical 1ms Pulse Width 



POWER SUPPLY (V) 

TL4F/5206-9 



Minimum Rext vs. 
Supply Voltage 



2 3 4 5 6 

POWER SUPPLY (V) TL/F/5206-10 


Typical 1ms Pulse Width 
Variation vs. Temperature 



-55 -15 25 65 105 125 

TEMPERATURE (“0 TL/F/5266-11 


Note: R and C are not subjected to temperature. The C is polypropylene. 


3-92 



National 
Semiconductor 

MM54HC125/MM74HC125 
MM54HC126/MM74HC126 
TRI-STATE® Quad Buffers 

General Description 

These are general purpose TRI-STATE high speed non-in- 
verting buffers utilizing microCMOS technology, 3.5 micron 
silicon gate P-well CMOS. They have high drive current out- 
puts which enable high speed operation even when driving 
large bus capacitances. These circuits possess the low 
power dissipation of CMOS circuitry, yet have speeds com- 
parable to low power Schottky TTL circuits. Both circuits are 
capable of driving up to 1 5 low power Schottky Inputs. 

The MM54HC125/MM74HC125 require the TRI-STATE 
control input C to be taken high to put the output Into the 
high impedance condition, whereas the MM54HC126/ 
MM74HC126 require the control input to be low to put the 
output into high impedance. 

All inputs are protected from damage due to static dis- 
charge by diodes to Vcc and ground. 


Connection Diagrams 

Dual-ln-Line Package 

Vcc C4 A4 Y4 C3 A3 Y3 



TL/F/5308-1 

Top View 


Order Number MM54HC125J or MM74HC125J, N 
See NS Package J14A or N14A 



microCMOS 


Features 

■ Typical propagation delay: 13 ns 

■ Wide operating voltage range: 2-6V 

■ Low input current: 1 jaA maximum 

■ Low quiescent current: 80 jaA maximum (74HC) 

■ Fanout of 1 5 LS-TTL loads 


Dual-ln-Line Package 


Vcc C4 A4 Y4 C3 A3 Y3 



TL/F/5308-2 

Top View 

Order Number MM54HC126J or MM74HC126J, N 
See NS Package J14A or N14A 



Truth Tabies 


inputs 

Output 

Y 

A 

c 

H 

L 

H 

L 

L 

L 

X 

H 

Z 


Inputs 

Output 

Y 

A 

c 

H 

H 

H 

L 

H 

L 

X 

L 

Z 



3-93 


MM54HC125/MM74HC125/MM54HC126/MM74HC126 





MM54HC125/MM74HC125/MMS4HC126/MM74HC126 


Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) 

DC Input Voltage (Vin) 

DC Output Voltage (Vqut) 

Clamp Diode Current (I|k, Iqk) 

DC Output Current, per pin (Iqut) 

DC Vcc or GND Current, per pin (Ice) 

Storage Temperature Range (Tstg) 

Power Dissipation (Pq) (Note 3) 

Lead Temp. (TO (Soldering 10 seconds) 


DC Electrical Characteristics (Note 4) 


Operating Conditions 


-0.5 to +7.0V 


Min 

Max 

Units 

-1.5 toVcc-l-1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

-0.5 to VcC + O.SV 

DC Input or Output Voltage 

0 

Vcc 

V 

±20 mA 

(V|N. Vqut) 




T" 25 mA 

Operating Temp. Range (Ta) 





MM74HC 

-40 

+ 85 

“C 

±50 mA 

MM54HC 

-55 

+ 125 

“C 

-65“Cto +150°C 

Input Rise or Fall Times 




500 mW 

(tr.tf) Vcc=2.0V 


1000 

ns 

260“C 

Vcc = 4.5 V 


500 

ns 


Vcc = 6.0V 


400 

ns 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25“C 

74HC 

TA=-40to 85X 

54HC 

TA=-55to125X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 

m 

19 

mmssiHi 

1.5 

V 


Input Voltage 


4.5V 


99 


3.15 

V 




6.0V 

mil 

B1 


4.2 

V 

V|L 

Maximum Low Level 


2.0V 

■ 


0.3 


V 


Input Voltage 


4.5V 



0.9 


V 




6.0V 

mm 

1.2 

1.2 


V 

Vqh 

Minimum High Level 

V|N-V|HorV|L 








Output Voltage 

l>OUTk20 ^A 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = ViHOrV|L 

1 Iqut 1^6.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



IIoutI^^.S mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|HOr^V|u 








Output Voltage 

|IoutI^ 20 fiA 

2.0V 

0 

0.1 

0.1 

0.1 





4.5V 

0 

0.1 

0.1 

0.1 





6.0V 

0 

0.1 

0.1 

0.1 

V 



ViN = V|HorV|L 
|IoutI^ 6.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

■ 



IIoutI^^.B mA 

6.0V 

ms 

0.26 

0.33 

0.4 

V 

Iqz 

Maximum TRI-STATE 

ViN = V|H or ViL 

6.0V 

■ 

±0.5 

±5 

±10 

jaA 


Output Leakage 

VoUT=Vcc orGND 


■ 






Current 

Cn = Disabled 



■* 




l|N 

Maximum Input 

Current 

V|N~ Vcc or gnd 

6.0V 


±0.1 

±1.0 

±1.0 

B 

Icc 

Maximum Quiescent 

V|N“Vcc orGND 

6.0V 


8.0 

80 

160 



Supply Current 

Iqut =6 f-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3; Power Dissipation temperature derating — plastic “N” package: - 12 mW/'C from to SS'C; ceramic “J” package: - 12 mW/°C from 100“C to 125‘’C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V^ and V|l occur at Vcc= 5-5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Icc. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-94 

















AC Electrical Characteristics vcc=5v.TA=25°c.cL=45pF,tr=t(=6ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tPLH 

Maximum 

Propagation Delay Time 


13 

18 

ns 

tpZH 

Maximum 

Output Enable Time to High Level 

Rl= 1 kft 

13 

25 

ns 


Maximum 

Output Disable Time from High Level 

Rl=i ka 
Cl=5pF 

17 

25 

ns 

tpZL 

Maximum 

Output Enable Time to Low Level 

Rl=i ka 

18 

25 

ns 

tPLZ 

Maximum 

Output Disable Time from Low Level 

Rl=i ka 

Cl=5pF 

13 

25 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl =60 pF, tr=tf = 6 ns (unless otherwise specified) 



Parameter 

Conditions 

Vcc 

Temperature °C 

Units 

54HC/74HC 

Ta=25X 

74HC 

-40 to 85“C 

54HC 

-55 to125°C 

Typ 

Guaranteed Limits 

tPHL. tpLH 

Maximum Propagation 


2.0V 

40 

100 

125 

150 

ns 


Delay Time 


4.5V 

14 

20 

25 

30 

ns 




6.0V 

12 

17 

21 

25 

ns 

tpLH. tpHL 

Maximum Propagation 


^^1 

m^mi 



195 

WM 


Delay Time 



WBm 



39 








HESIIIil 

33 


tpZH. tpZL 

Maximum Output 

Rl=i kn 





188 

ns 


Enable Time 


4.5V 

14 

25 

31 

38 

ns 




6.0V 

12 

21 

26 

31 

ns 

tpHZ. tPLZ 

Maximum Output 

Rl=i ka 

2.0V 

WM 




Bi 


Disable Time 


4.5V 

mm 




mm 




6.0V 

Bai 

■■ 



wm 

tpZL. tpZH 

Maximum Output 

Cl= 150 pF 

2.0V . 





n 


Enable Time* 

Rl=i ka 

4.5V 

HB 




mm 




6.0V 

mM 




wm 

tjLH. tjHL 

Maximum Output 

Cl = 50 pF 






n 


Rise and Fall Time 







mm 









■9 

C|N 

Input Capacitance 




10 


10 

pF 

Gout 

Output Capacitance Outputs 



15 

20 

20 

20 

pF 

CpD 

Power Dissipation 

(per gate) 






■■ 


Capacitance (Note 5) 

Enabled 


45 




mm 



Disabled 


6 




■9 


, Note 5: Cpo determines the no load dynamic power consumption, Pd = C po Vcc^ f + Iqq Vcc. and the no load dynamic current consumption, Is = Cpo Vcc t + Icc- 



3-95 


MM54HC125/MM74HC125/MM54HC126/MM74HC126 






















MM54HC132/MM74HC132 


PRELIMINARY 


National 
dSt Semiconductor 

MM54HC132/MM74HC132 Quad 2-Input 
NAND Schmitt Trigger 




microCMOS 


General Description 


The MM54HC132/MM74HC132 utilizes microCMOS Tech- 
nology, 3.5 micron silicon gate P-well CMOS, to achieve the 
low power dissipation and high noise immunity of standard 
CMOS, as well as the capability to drive 10 LS-TTL loads. 
The 54HC/74HC logic family is functionally and pinout com- 
patible with the standard 54LS/74LS logic family. All inputs 
are protected from damage due to static discharge by inter- 
nal diode clamps to Vcc and ground. 


Features 

■ Typical propagation delay: 12 ns 

■ Wide power supply range: 2V-6V 

■ Low quiescent current: 20 jaA maximum (74HC Series) 

■ Low Input current: 1 jxA maximum 

■ Fanout of 10 LS-TTL loads 

■ Typical hysteresis voltage: 0.9V at Vcc = 4.5V 



3-96 




Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) - 0-5 to + 7.0V 

DC Input Voltage (V|n) ' - 1 .5 to Vcc + 1 -SV 

DC Output Voltage (Vout) - 0.5 to Vcc + 0-5V 

Clamp Diode Current (Iik, Iqk) ± 20 mA 

DC Output Current, per pin (Iout) ± 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) -65°C to + 1 50“C 
Power Dissipation (Pp) (Note 3) 500 mW 

Lead Temperature (TJ 

(Soldering 1 0 seconds) 260‘’C 


Operating Conditions 


Min 

Supply Voltage (Vcc) 2 

DC Input or Output Voltage 0 

(V|N. Vqut) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 


Max Units 

6 V 

Vcc V 


+ 85 “C 

+ 125 “C 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25X 

74HC 

TA=-40to85°C 

54HC 

Ta=- 55 to125“C 

Units 





Typ 

Guaranteed Limits 


Vt+ 

Positive 


Min 

2.0V 


1.0 

0.95 

0.95 

V 

Going Threshold Voltage 


Max 



1.5 

1.5 

1.5 

V 



























3.0 


2.95 






mu 


4.2 


4.2 


Vt- 

Negative 







0.3 



Going Threshold Voltage 



mu 




0.85 






BEIfl 



0.9 

0.9 






mu 



2.05 

2.05 






BBWI 










mu 






Vh 

Hysteresis Voltage 


Min 

2.0V 



0.2 

0.2 





Max 

2.0V 



1.2 

1.2 





Min 

4.5V 



0.4 

0.4 

V 




Max 

4.5V 



2.25 

2.25 

V 




Min 

6.0V 



0.6 

0.6 





Max 

6.0V 



3.0 

3.0 


VoH 

Minimum High Level 

yiN=yiH orViL 








Output Voltage 

|IoutI^20 /xA 

2.0V 

2.0 


1.9 

1.9 






4.5V 

4.5 


4.4 

4.4 






6.0V 

6.0 


5.9 

5.9 




yiN=yiHOrViL 

louT^4.0mA 

4.5V 

4.2 

3.98 


3.7 




HoutI^ 5.2 mA 

6.0V 

5.7 

5.48 


5.2 


VoL 

Maximum Low Level 

yiN=yiHorViu 








Output Voltage 

|IoutI^ 20 fxA 

2.0V 

0 

0.1 


0.1 






4.5V 

0 

0.1 


0.1 






6.0V 

0 

0.1 


0.1 




yiN=yiH orViL 
louT^4.0mA 

4.5V 


0.26 


0.4 




||out1 ^5.2 mA 

6.0V 


0.26 


0.4 


•in 

Maximum Input 

Vim = Vnr: or GND 

6.0V 


±0.1 

±1.0 

±1.0 

/xA 


Current 














2.0 

20 

40 

juA 










Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 


Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/^C from 65°C to 85°C: ceramic “J” package: - 1 2 mW/'C from 1 00°C to 1 25'’C. 
Note 4: For a power supply of 5V ± 1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|i_ occur at Vcc= 5-5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 



3-97 


MM54HC132/MM74HC132 
















MM54HC132/MM74HC132 


AC Electrical Characteristics vcc= 5 v.TA= 25 »c,CL=i 5 pF,t,=t,= 6 ns 



Parameter 

Conditions 




tpHb tpLH 

Maximum Propagation 
Delay 


12 


ns 




AC Electrical Characteristics Vcc= 2.0V to 6.0V, Cl= 50 pF, tr= tf = 6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25X 

74HC 

TA=-40to85X 

Ta= 

54HC 

-55to125“C 

Units 





Typ 

Guaranteed Limits 


tpHL. tpLH 

Maximum Propagation 



63 

125 

158 


186 

ns 


Delay 



13 

25 

32 


37 

ns 




6.0V 

11 

21 

27 


32 

ns 

tTLH. tjHL 

Maximum Output Rise 



30 

75 

95 


110 

Di 


and Fall Time 



8 

15 

19 


22 






7 

13 

16 


19 


CpD 

Power Dissipation 
Capacitance (Note 5) 

(per gate) 

■ 

■ 








■ 

■ 

5 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pq = C po Vcx;2 f + Iqq Vcc. and the no load dynamic current consumption, Is = Cpo Vcc f + Ice- 


3-98 































National 
Semiconductor 

MM54HC1 33/MM74HC 1 33 
13-Input NAND Gate 

General Description 

This NAND gate utilizes microCMOS Technology, 3.5 mi- 
cron silicon gate P-well CMOS, to achieve operating speeds 
similar to LS-TTL gates with the low power consumption of 
standard CMOS integrated circuits. All gates have buffered 
outputs. All devices have high noise immunity and the ability 
to drive 10 LS-TTL loads. The 54HC/74HC logic family Is 
functionally as well as pin-out compatible with the standard 
54LS/74LS logic family. All inputs are protected from dam- 
age due to static discharge by internal diode clamps to Vcc 
and ground. 



microCMOS 


Features 

■ Typical propagation delay: 20 ns 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 20 juA maximum (74HC Series) 

■ Low input current: 1 fiA maximum 

■ Fanout of 10 LS-TTL loads 



Connection and Logic Diagrams 

Dual-ln-Line Package 



Top View 

Order Number MM54HC133J or MM74HC133J, N 
See NS Package J16A or N16E 


TL/F/5134-1 




3-99 


MM54HC133/MM74HC133 



MM54HC133/MM74HC133 


Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

DC Input Voltage (V|n) 

DC Output Voltage (Vqijt) 

Clamp Diode Current (I|k, Iqk) 

DC Output Current, per pin (Iqut) 

DC Vcc or GND Current, per pin (Ice) 
Storage Temperature Range (Tstg) 
Power Dissipation (Pp) (Note 3) 

Lead Temperature (Tl) 

(Soldering 1 0 seconds) 


- 0.5 to + 7.0V 


Min 

Max 

Units 

-1.5toVcc+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

±20 mA 

(V|N. Vqut) 




±25 mA 

Operating Temp. Range (Ta) 





MM74HC 

-40 

+ 85 

“C 

±50 mA 

MM54HC 

-55 

+ 125 

“C 

-65‘*Cto +150‘’C 

Input Rise or Fall Times 




500 mW 

(tr.tf) Vcc = 2.0V 


1000 

ns 


Vcc = 4.5V 


500 

ns 

260‘’C 

Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4 ) 


Symboi 

Parameter 

Conditions 

Vcc 



74HC 

TA=-40to85X 

54HC 

Ta=- 55 tOl25"C 

Units 






Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 

jm 

■9 



V 


Input Voltage 


4.5V 


■iHM 



V 




6.0V 


BS 


HHK&ilHI 

V 

V|L 

Maximum Low Level 


2.0V 

jm 




V 


Input Voltage 


4.5V 





V 




6.0V 

[[jlllll 




V 

Vqh 

Minimum High Level 

V|N = V|HOrViL 








Output Voltage 

|IoutI^ 20 fiA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

.4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N='V|H orViL 
HoutI^ 4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



^•oUTi^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H 








Output Voltage 

|IoutN20 }xA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|h 
1101171^4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 




hoUTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 


Iin 

Maximum Input 
Current 

ViN~ Vcc or GND 

6.0V 

■ 


±1.0 

±1.0 

|LtA 

•cc 

Maximum Quiescent 

V|N ~ Vcc or GND 

6.0V 

m 


20 

40 



Supply Current 

Iout=0F'A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/^C from SS'C to 85’C: ceramic “J” package: - 1 2 mW/'C from 1 00®C to 1 25®C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc = 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (Iin, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-100 












AC Electrical Characteristics vcc= 5 v,TA= 25 “c,CL=i 5 pF,tr=tf= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tPLH 

Maximum Propagation Delay 


20 

30 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25“C 

74HC 

Ta=-40 to 85“C 

Ta=- 

54HC 

-55 to125“C 

Units 





Typ 

Guaranteed Limits 



Maximum Propagation 


2.0V 

66 

160 

190 


220 

ns 


Delay 


4.5V 

23 

35 

42 


49 

ns 




6.0V 

18 

30 

36 


42 

ns 

tjLH. 

Maximum 




75 

95 


110 

ns 

tlHL 

Output Rise and 


ISi 


15 

19 


22 

ns 


Fall Time 




13 

16 


19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 


m 





pF 

C|N 

Maximum Input Capacitance 



5 

10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f + Ice Vcc. and the no load dynamic current consumption, ls= Cpo Vec f + Icc- 


3-101 


MM54HC133/MM74HC133 












MM54HC137/MM74HC137 


National 

Sim Semiconductor 


PRELIMINARY 


microCMOS 


MM54HC137/MM74HC137 3-to>8 Line 
Decoder With Address Latches 
(inverted Output) 


General Description 

This device utilizes microCMOS Technology, 3.5 micron sili- 
con gate P-well CMOS, to implement a three-to-eight line 
decoder with latches on the three address inputs. When GL 
goes from low to high, the address present at the select 
inputs (A, B and C) is stored in the latches. As long as GL 
remains high no address changes will be recognized. Out- 
put enable controls, G1 and G2, control the state of the 
outputs independently of the select or latch-enable inputs. 
All of the outputs are high unless G1 is high and G2 is low. 
The HC1 37 is ideally suited for the implementation of glitch- 
free decoders in stored-address applications in bus oriented 
systems. 


The 54HC/74HC logic family is speed, function and pin-out 
compatible with the standard 54LS/74LS logic family. All 
inputs are protected from damage due to static discharge by 
diodes to Vcc and ground. 

Features 

■ Typical propagation delay: 20 ns 

■ Wide supply range: 2-6V 

■ Latched inputs for easy interfacing. 

■ Fanout of 10 LS-TTL loads. 


Connection and Functional Block Diagrams 


Duai-ln-Line Package 





SELECT ENABLE OUTPUT 

TL/F/5310-1 INPUTS 

Order Number MM54HC137J 
or MM74HC137J,N 
See NS Package J16A or N16E 


ENABLE J fij, !5L 

lyoiiTC I 



3-102 




Absolute Maximum Ratings (Notes i & 2 ) 

Operating Conditions 



Supply Voltage (Vec) 

-0.5 to +7.0V 

Supply Voltage (Vcc) 

DC Input or Output Voltage 

Min 

Max 

Units 

DC Input Voltage (Vin) 

-1.5 to VCC+1-5V 

2 

0 

6 

Vcc 

V 

V 

DC Output Voltage (Vqut) 

-0.5 to Vec + 0.5V 

(V|N. Vqut) 



Clamp Diode Current (I|k, Iqk) 

±20mA 

Operating Temp. Range (Ta) ‘ 




DC Output Current, per pin (Iout) 

±25 mA 

MM74HC 

-40 

±85 

°c 

DC Vec or GND Current, per pin (Ice) 

±50 mA 

MM54HC 

-55 

±125 

°c 

Storage Temperature Range (Tstg) 

-65°Cto +150°C 

Input Rise or Fall Times 
(tr.tf) Vcc = 2.0 V 


1000 

ns 

Power Dissipation (Pq) (Note 3) 

500 mW 

Vcc=4.5V 


500 

ns 

Lead Temperature (TJ 


Vcc = 6.0 V 


400 

ns 


(Soldering 10 seconds) 260*C 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25X 

74HC 

Ta=- 40 to 85X 

54HC 

Ta=- 55 to125X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 

i 

4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 



[■ 

0.3 

0.3 

0.3 

V 


Input Voltage 




0.9 

0.9 

0.9 

V 




QQI 


1.2 

1.2 

1.2 

V 

VoH 

Minimum High Level 

V|N = V|HorV|L 


1 






Output Voltage 

|IoutI^20 iiA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 
|IoutI^ 4.0 mA 



3.98 

3.84 

3.7 

V 



ilouTi^5.2 mA 

IQQn 


5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H orV|L 








Output Voltage 

1IoUtI^20jiA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|n = V|h or V|L 
|IoutI^ 4.0 mA 



0.26 

0.33 

0.4 

V 



i•oUTl^5.2 mA 



0.26. 

0.33 

0.4 

V 

•in 

Maximum Input 
Current 

V|N = Vcc or GND 

6.0V 


±0.1 

±1.0 

±1.0 

|LtA 

•cc 

Maximum Quiescent 

V|fg = Vcc or GND 

6.0V 


8.0 

80 

160 

fiA 


Supply Current 

Iout=0/J'A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 12 mW/*C from 65*C to 86‘’C: ceramic “J” package: - 12 mW/®C from 100°C to 125®C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|l occur at Vcc=5.5V and 4.5V respectively. (The V(h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-103 


MM54HC137/MM74HC137 






MM54HC1 37/MM74HC137 


AC Electrical Characteristics vcc= 5 v,TA= 25 °c,CL=i 5 pF,tr=t,= 6 ns 


Symbol 

Parameter 

Conditions 



Units 

tpLH 

Maximum Propagation Delay, A, B or C to any Y Output 


14 

29 

ns 

tpHL 

Maximum Propagation Delay, A, B or C to any Y Output 


20 

42 

ns 

tpLH 

Maximum Propagation Delay G2 to any Y Output 


12 

22 

ns 

tPHL 

Maximum Propagation Delay G2 to any Y Output 


15 

34 

ns 

tPLH 

Maximum Propagation Delay G1 to any Output 


13 

25 

ns 

tpHL 

Maximum Propagation Delay GL to any Output 


17 

34 

ns 

tpLH 

Maximum Propagation GL to Output 


15 

30 


tPHL 

Maximum Propagation Delay GL to Output 

% 

22 

34 


ts 

Minimum Setup Time at A, B and C Inputs 



20 

ns 

tH 

Minimum Hold Time at A, B and C Inputs 



0 

ns 

tw 

Minimum Pulse Width of Enabling Pulse at ^ 



16 

ns 


AC Electrical Characteristics Cl= 50 pF, tr=tf =6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25“C 

74HC 

Ta=- 40 to SS'-C 

54HC 

Ta=- 55 tOl25“C 

Units 





Typ 

Guaranteed Limits 


tpLH 

Maximum Propagation Delay 


2.0V 

85 

170 





A, B or C to any Y Output 


4.5V 

17 

34 







6.0V 

14 

29 




tpHL 

Maximum Propagation Delay 


2.0V 

120 



358 



A, B or C to any Y Output 


4.5V 

24 



72 





6.0V 

20 , 



61 


tpLH 

Maximum Propagation Delay 


2.0V 

65 

130 

164 




G2 to any Y Output 


4.5V 

13 

26 

33 






6.0V 

11 

22 

28 



tpLH 

Maximum Propagation 


2.0V 



189 




Delay G1 to Output 


4.5V 



38 






6.0V 



32 



tPHL 

Maximum Propagation 


2.0V 

98 


246 

291 

■a 


Delay G1 to Output 


4.5V 

20 


49 

58 

■iH 




6.0V 

17 


42 

’ 49 


tPLH 

Maximum Propagation 


2.0V 

88 

175 

221 




Delay GL to Output 


4.5V 

18 

35 

44 






6.0V 

15 

30 

37 



tpHL 

Maximum Propagation 


2.0V 

125 

250 

315 

373 

■a 


Delay GL to Output 


4.5V 

25 

50 

63 

75 





6.0V 

21 

43 

54 

63 


fpHL 

Maximum Propagation Delay 


2.0V 

98 


246 

291 

■a 


G2, to any Y Output 


4.5V 

20 


49 

58 





6.0V 

17 


42 

49 



Minimum Setup Time 


2.0V 




150 



at A, B and C inputs 


4.5V 




30 





6.0V 

n 



25 


tH 

Minimum Hold Time 


2.0V 

■jjll 

50 


75 

mm 


at A, B and C inputs 


4.5V 


10 


15 

■JH 




6.0V 


8 


13 


tTLH» tjHL 

Output Rise and 


2.0V 

30 

75 





Fall Time 


4.5V 

8 

15 



■|H 




6.0V 

7 

13 




tw 

Minimum Pulse Width 


2.0V 


80 

100 

120 


of Enabling Pulse at GL 


4.5V 


16 

20 

24 





6.0V 


14 

18 

21 


CpD 

Power Dissipation 
Capacitance (Note 5) 



75 





C|N 

Maximum Input Capacitance 



5 

lEI 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f + Ice Vcc. and the no load dynamic current consumption, ls= Cpo Vec f + Icc- 


3-104 














































Typical Application 


STROBE ■ 
DECODER ENABLE < 

fxo - 

XI - 
xz - 


INPUT 

ADDRESS 


GL 

C 

B 

A GZ 

Gl 

YO Yl 

Y2 

Y3 

Y4 Y5 Y6 

Y7 


GL C B A GZ G1 

YO'YI Y2 Y3 Y4 Y5 Y6 Y7 


GL C B A GZ G1 

YO Y1 Y2 Y3 Y4 Y5 Y6 YT 


TTTTTTTf TTTTTTTT 

1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 


GL C B A G2 Gl 

YD Yl Y2 Y3 Y4 Y5 Y6 Y7 


TTTTTTTr 

0 I Z 3 4 5 6 7 


OUTPUTS 

6-Line to 64-Line Decoder with input Address Storage 


TO FIVE 
)> OTHER 
DECODERS 


TL/F/5310-3 


Truth Table 


inputs 

Outputs 

Enabie 

Seiect 

GL 

Gl 

G2 

C 

B 

A 

YO 

Y1 

Y2 

Y3 

Y4 

Y5 

Y6 

Y7 

X 

X 

H 

X 

X 

X 

H 

H 

H 

H 

H 

H 

H 

H 

X 

L 

X 

X 

X 

X 

H 

H 

H 

H 

H 

H 

H 

H 

L 

H 

L 

L 

L 

L 

L 

H 

H 

H 

H 

H 

H 

H 

L 

H 

L 

L 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

L 

L 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

L 

H 

L 

L 

H 

H 

H 

H 

H 

L 

H 

H 

H 

H 

L 

H 

L 

H 

L 

L 

H 

H 

H 

H 

L 

H 

H 

H 

L 

H 

L 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

H 

L 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

L 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 

H 

H 

L 

X 

X 

X 

Output corresponding to stored 
address L; all others, H 


H = high level, L = low level, X = irrelevant 


3-105 


MM54HC137/MM74HC137 



MM54HC138/MM74HC138 


National 
Semiconductor 

MM54HC138/MM74HC138 
3-to-8 Line Decoder 

General Description 

This decoder utilizes microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS, and is well suited to memory ad- 
dress decoding or data routing applications. The circuit fea- 
tures high noise immunity and low power consumption usu- 
ally associated with CMOS circuitry, yet has speeds compa- 
rable to low power Schottky TTL logic. 

The MM54HC138/MM74HC138 has 3 binary select inputs 
(A, B, and C). If the device is enabled these inputs deter- 
mine which one of the eight normally high outputs w ill go 
low. Two active low and one active high enables (G1, G2A 
and G2B) are provided to ease the cascading of decoders. 



microCMOS 


The decoder’s outputs can drive 1 0 low power Schottky TTL 
equivalent loads, and are furtctionally and pin equivalent to 
the 54LS138/74LS138. All inputs are protected from dam- 
age due to static discharge by diodes to Vcc and ground. 

Features 

■ Typical propagation delay: 20 ns 

■ Wide power supply range: 2V-6V 

■ Low quiescent current: 80 jaA maximum (74HC Series) 

■ Low input current: 1 juA maximum 

■ Fanout of 10 LS-TTL loads 



Connection and Logic Diagrams 


Dual-ln-Line Package 

DATA OUTPUTS 



TL/F/5120-1 

Order Number MM54HC138J 
orMM74HC138J,N 
See NS Package J16A or N16E 



Truth Tabie 


Inputs 

Outputs 

Enable 

Select 

G1 

02* 

C 

B 

A 

YO 

V 

Y2 

Y3 

Y4 

Y5 

Y6 

Y7 

X 

H 

X 

X 

X 

H 

H 

H 

H 

H 

H 

H 

H 

L 

X 

.X 

X 

X 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 

L 

L 

L 

L 

H 

H 

H 

H 

H 

H 

H 

H 

L 

L 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

L 

L 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

L 

L 

H 

H 

H 

H 

H 

L 

H 

H 

H 

H 

H 

L 

H 

L 

L 

H 

H 

H 

H 

L 

H 

H 

H 

H 

L 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

H 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 


*G2 = G2A + G2B 

H = high level, L=low level, X= don’t care 


3-106 



Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc)* 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 
MM74HC 

-40 

±85 

°c 

DC Vcc or GND Current, per pin (Ice) 

±50 mA 

MM54HC 

-55 

±125 

°c 

Storage Temperature Range (Tstg) 

-65“Cto +150°C 

Input Rise or Fall Times 




Power Dissipation (Pq) (Note 3) 

500 mW 

(tr.tf) Vcc=2.0V 


1000 

ns 

Lead Temp. (Tl) (Soldering 10 seconds) 

260“C 

Vcc=4.5V 


500 

ns 


Vcc = 6.0 V 


400 

ns 


DC Eiectrical Characteristics (Note 4) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta = 

25°C 

74HC 

Ta=-40 to 85°C 

54HC 

Ta=- 55 to125X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Levei 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|HOrV|L ■ 








Output Voltage 

|IoutI^ 20 fiA 

2.0V 

2.0 

1.9 

1.9 

1.9 





4.5V 

4.5 

4.4 

4.4 

4.4 





6.0V 

6.0 

5.9 

5.9 

5.9 




V|N = V|HOrViL 
|louTk4.0 mA 


4.2 

3.98 

3.84 

3.7 




jlouTi^5.2 mA 


5.7 

5.48 

5.34 

5.2 


VoL 

Maximum Low Level 

V|N = V|H orViL 








Output Voltage 

|IoutI^20 (i,A 


0 

0.1 

0.1 

0.1 

V 





0 

0.1 

0.1 

0.1 

V 





0 

0.1 

0.1 

0.1 

V 



V|N = V|HOrV|L 
|louTk4.0 mA 


0.2 

0.26 

0.33 

0.4 

V 



jlouTi^5.2 mA 


0.2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum Input 
Current 

V|N~ Vcc or GND 

6.0V 


±0.1 

±1.0 

±1.0 

/jlA 

icc 

Maximum Quiescent 

V|N = Vcc or GND 

6.0V 


8.0 

80 

160 

jaA 


Supply Current 

IOUT = 0 mA 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N" package: -12 mW/*C from 65°C to 85'C: ceramic “J” package: - 12 mW/'C from lOO'C to 125*0. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and Vil occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-107 


MM54HC138/MM74HC138 











MM54HC138/MM74HC138 


AC Electrical Characteristics vcc=5v,TA=25“c.cL=i5pF,tr=t,=6ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPLH 

Maximum Propagation 

Delay, Binary Select to any Output 



25 

ns 

tPHL 

Maximum Propagation 

Delay, Binary Select to any Output 


28 

35 

ns 

tpHL. tPLH 

Maximum Propagation 

Delay, G1 to any Output 


18 

25 

ns 

tPHL 

Maximum Propagation 

Delay G2A or G2B to 

Output 


23 

30 

ns 

tpLH 

Maximum Propagation 

Delay G2A or G2B to 

Output 


18 

25 

ns 


AC Electrical Characteristics Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25”C 

74HC 

Ta=- 40 to 85X 

54HC 

Ta=- 55 to125“C 

Units 





Typ 

Guaranteed Limits 


tPLH 

Maximum Propagation 


2.0V 



189 

224 



Delay Binary Select to 


4.5V 



38 

45 

mm 


any Output Low to High 


6.0V 



32 

38 

mm 

tPHL 

Maximum Propagation 


2.0V 

100 

200 

252 

298 

ns 


Delay Binary Select to any 


4.5V 

20 

40 

40 

60 

ns 


Output High to Low 


6.0V 

17 

34 

43 

51 

ns 

tPHL. tpLH 

Maximum Propagation 


2.0V 

75 

150 

189 

224 

ns 


Delay G1 to any 


4.5V 

15 

30 

38 

45 

ns 


Output 


6.0V 

13 

26 

32 

38 

ns 

tpHL 

Maximum Propagation 


2.0V 



221 

261 

mm 


Delay G2A or G2B to 


4.5V 



44 

52 

mm 


Output 


6.0V 

22 


37 

44 

mm 

tPLH 

Maximum Propagation 


2.0V 







Delay G2A or G2B to 


4.5V 







Output 


6.0V 






tjLH. tjHL 

Output Rise and 


2.0V 



95 

110 

S 


Fall Time 


4.5V 



.19 

22 

MM 




6.0V 



16 

19 

mm 

C|N 

Maximum Input 

Capacitance 





10 

10 


CpD 

Power Dissipation 
Capacitance 

(Note 5) 


75 




fiF 


Note 5: Cpo determines the no load dynamic power consumption, Pd= C pp Vcc^ f + Ice Vcc. and the no load dynamic current consumption, ls= CpQ Vec Icc- 


3-108 
















National 
Semiconductor 

MM54HC139/MM74HC139 
Dual 2-T0-4 Line Decoder 

General Description 

This decoder utilizes microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS, and is well suited to memory ad- 
dress decoding or data routing applications. It pbssesses 
the high noise immunity and low pow6r consumption usually 
associated with CMOS circuitry, yet has speeds comparable 
to low power Schottky TTL logic. 

The MM54HC139/MM74HC139 contain two independent 
one-of-four decoders each with a single active low enable 
input (G1, or G2). Data on the select inputs (A1, and B1 or 
A2, and B2) cause one of the four normally high outputs to 
go low. 

The decoder’s outputs can drive 10 low power Schottky TTL 
equivalent loads, and are functionally as well as pin equiva- 



microCMOS 


lent to the 54LS139/74LS139. All inputs are protected from 
damage due to static discharge by diodes to Vcc and 
ground. 

Features 

■ Typical propagation delays — 

Select to outputs (4 delays): 18 ns 
Select to output (5 delays): 28 ns 
Enable to output: 20 ns 

■ Low power: 40 jaW quiescent supply power 

■ Fanout of 10 LS-TTL devices 

■ Input current maximum 1 jaA, typical 10 pA ■ 



Connection Diagram 

Dual-ln-Line Package 


SELECT DATA OUTPUTS 

ENABLE , , , * ^ 

Vcc G1 A2 B2 2Y0 2Y1 ' 2Y2 2Y3 



TL/F/5311-1 

Order Number MM54HC139J or MM74HC139J, N 
See NS Package J16A or N16E 


Truth Tabie 


’HC139 


Inputs 

Outputs 

Enable 

Select 

G 

B 

A 

YO 

Y1 

Y2 

Y3 


H 

X 

H 

H 

H 

H 


H 

L 

L 

H 

H 

H 


H 

H 

H 

L 

H 

H 



L 

H 

H 

L 

H 

■■ 


H 

H 

H 

H 

L 


H = high level, L=low level, X= don’t care 


Logic Diagram 

V: MM54HC139/MM74HC139 


SELECT 





OUTPUTS 


TL/F/5311-2 



3-109 


MM54HC139/MM74HC139 






MM54HC139/MM74HC139 


Absolute Maximum Ratings (Notes i & a) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to 4- 7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA ' 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 
MM74HC 

-40 

+ 85 

"C 

DC Vcc or GND Current, per pin (Icc) 

±50 mA 

MM54HC 

-55 

+ 125 

“C 

Storage Temperature Range (Tstg) 

-65“Cto ±150"C 

Input Rise or Fall Times 




Power Dissipation (Pc) (Note 3) 

500 mW 

(tr.tf) Vcc=2.0V 


1000 

ns 

Lead Temp. (TJ (Soldering 10 seconds) 

260“C 

Vcc = 4.5 V 


500 

ns 


Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

= 25'’C 

74HC 

Ta=- 40 to 85"C 

54HC 

Ta=- 55 to125"C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 




Input Voltage 


4.5V 


3.15 

3.15 






6.0V 


4.2 

4.2 



V|L 

Maximum Low Level 


2.0V 



0.3 

0.3 



Input Voltage 


4.5V 



0.9 

0.9 





6.0V 

III 


1.2 

1.2 


Vqh 

Minimum High Level 

ViN = ViHorV|L 








Output Voltage 

|loUTk20 fiA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 
|IoutI^ 4.0 mA 

4.5V 

4.2 

3,98 

3.84 

3.7 




hoUTi^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 


VoL 

Maximum Low Level 

V|N = V|Hor V|L 








Output Voltage 

|loUTk20 jxA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|N = V|H orViL 
|louTk4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 




|louTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 


l|N 

Maximum Input 
Current 

V|N = Vcc or GND 

6.oy 

■ 


±1.0 

±1.0 

jiA 

•cc 

Maximum Quiescent 

V|N~ Vcc or GND 

6.0V 

■ 


80 

160 

}xA 


Supply Current 

Iqut-O P'A 


■i 






Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: -12 mW/“Cfrom SS'C to85®C: ceramic “J” package: -12 mW/“Cfrom 100*0 to 125*0. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HO at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vih and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
loz) occur for OMOS at the higher voltage and so the 6.0V values should be used. 


3-110 












AC Electrical Characteristics 

Vcc=5V, Ta=25°C, Cl=15 pF, tr=tf=6 ns 



Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 


Maximum Propagation 

Delay, Binary Select to any Output 

4 levels of delay 


18 

30 

ns 

tpHL. tPLH 

Maximum Propagation 

Delay, Binary Select to any Output 

5 levels of delay 


28 

38 

ns 

tPHL. tpLH 

Maximum Propagation 

Delay, Enable to any Output 


19 

30 

ns 


AC Eiectricai Characteristics Cl = 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

25°C 

74HC 

Ta=- 40 to 85°C 

54HC 

Ta=- 55 to125“C 

Units 





Typ 

Guaranteed Limits 


tPHL. tpLH 

Maximum Propagation 


2.0V 

110 

175 

219 

254 

ns 


Delay Binary Select to 


4.5V 

22 

35 

44 

51 

ns 


any Output 4 levels of delay 


6.0V 

18 

30 

38 

44 

ns 

fpHL. tPLH 

Maximum Propagation 


2.0V 

165 

220 

275 

320 

ns 


Delay Binary Select to any 


4.5V 

33 

44 

55 

64 

ns 


Output 5 levels of delay 


6.0V 

28 

38 

47 

54 

ns 

tpHL. tPLH 

Maximum Propagation 


2.0V 

115 

175 

219 

254 ' 

ns 


Delay Enable to any 


4.5V 

23 

35 

44 

51 

ns 


Output 


6.0V 

19 

30 

38 

44 

ns 

tTLH. tTLH 

Maximum Output Rise 


2.0V 

30 


95 

110 

ns 


and Fall Time 


4.5V 

8 


19 

22 

ns 




6.0V 

7 


16 

19 

ns 

C|N 

Maximum Input 

Capacitance 





10 

10 

fxF 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(Note 5) 


75 




P.F 


Note 5: Cpo determines the no load dynamic power consumption, Pd = Cpd Vcc^ Icc Vcc. and the no load dynamic current consumption, ls = CpD Vcc t+ Icc- 


3-111 


MM54HC139/MM74HC139 






















MM54HC147/MM74HC147 


National 
Semiconductor 

MM54HC1 47/iyiM74HC1 47 
10-to-4 Line Priority Encoder 
General Description 

This high speed 1 0-to-4 Line Priority Encoder utilizes micro- 
CMOS Technology, 3.5 micron silicon gate P-well CMOS. It 
possesses .the high noise immunity and low power con- 
sumption of standard CMOS integrated circuits. This device 
is fully buffered, giving it a fanout of 10 LS-TTL loads. 

The MM54HC147/MM74HC147 features priority encoding 
of the inputs to ensure that only the highest order data line 
is encoded. Nine input lines are encoded to a four line BCD 
output. The implied decimal zero condition requires no input 
condition as zero is encoded when all nine data lines are at 
a high logic level. All data inputs and outputs are active at 
the low logic level. 



microCMOS 


The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 
All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Low quiescent power consumption: 40 jaW maximum at 
25^C 

■ High speed: 31 ns propagation delay (typical) 

■ Very low input current: 10 “5 ^llA typical 

■ Wide supply range: 2V to 6V 



Connection and Logic Diagrams 

Duai-ln-Line Package 


INPUTS 

OUTPUT > . OUTPUT 

Vcc NC D 3 2 1 9 A 




15 

14 

13 

12 

11 

10 

9 

r . 





□ 


1 

1 





1 

1 

1 






1 



1 

2 

3 

4 

5 

6 

n 

8 


4 5 6 7 8 C B GND 


INPUTS OUTPUTS 

TL/F/5007-1 

Top View 

Order Number MM54HC147J or MM74HC147J, N 
See NS Package J16A or N16E 


Truth Table 


Inputs 

Outputs 

1 

2 

3 

4 

5 

6 

7 

8 

9 

D 

C 

B 

A 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

□ 

X 

X 

X 

X 

X 

X 

X 

L 

L 

H 

H 

L 

X 

X 

X 

X 

X 

X 

X 

L 

H 

L 

H 

H 

H 

X 

X 

X 

X 

X 

X 

L 

H 

H 

H 

L 

L 

L 

X 

X 

X 

X 

X 

L 

H 

H 

H 

H 

L 

L 

H 

X 

X 

X 

X 

L 

H 

H 

H 

H 

H 

L 

H 

L 

X 

X 

X 

L 

H 

H 

H 

H 

H 

H 

L 

H 

H 

X 

X 

L 

H 

H 

H 

H 

H 

H 

H 

H 

L 

L 

X 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 


H = High Logic Level, L = Low Logic Level, X = Irrelevant 



3-112 









Absolute Maximum Ratings (Notes i & 2 ) Operating Conditions 


Supply Voltage (Vcc) 

-0.5 to +7.0V 


Min 

Max 

' Units 

DC Input Voltage (V|n) 

-1.5 to VCC+1-5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

(V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 
MM74HC 

-40 

±85 

°c 

DC Vcc or GND Current, per pin (Icc) 

±50 mA 

MM54HC 

-55 

±125 

”0 

Storage Temperature Range (Tstg) 

-65°Cto ±150°C 

Input Rise or Fall Times 




Power Dissipation (Pq) (Note 3) 

500 mW 

(tr.tf) Vcc=2.0V 


1000 

ns 

Lead Temp. (Tl) (Soldering 10 seconds) 

260“C 

Vcc = 4.5 V 


500 

ns 


Vcc = 6.0 V 


400 

ns 


DC Electricai Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25°C 

74HC 

Ta=- 40 to 85“C 

54HC 

Ta=- 55 to125“C 

Units 





Typ 

Guaranteed Limits 


ViH 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|HorV|L 








Output Voltage 

|IoutI^ 20 fxA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|HOrV|L 
|louTk4.0 mA 

4.5V 

4.7 

3.98 

3.84 

3.7 

V 



ilouTi^5.2 mA 

6.0V 

5.2 

5.48 

5.34 

5.2 

V 


Maximum Low Level 

V|N = V|HorV|L 








Output Voltage 

|IoutI^20 /xA 



0.1 

0.1 

0.1 

V 






0.1 

0.1 

0.1 

V 






0.1 

0.1 

0.1 

V 



V|N = V|HOrViL 
|IoutI^4.0 mA 



0.26 

0.33 

0.4 

V 



il0UTi^5.2 mA 



0.26 

0.33 

0.4 

V 

^9 

Maximum Input 
Current 

V|N ~ Vcc or GND 


■ 

±0.1 

±1.0 

±1.0 

laA 

Icc 

Maximum Quiescent 

V|N~ Vcc or GND 

6.0V 


8.0 

80 

160 

/xA 


Supply Current 

Iqut^o F-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package; -12 mW/^C from 65*0 to 85*0; ceramic “J” package: - 12 mW/*0 from 100*0 to 125*0. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HO at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|l occur at Vcc= 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Icc. and 
loz) occur for OMOS at the higher voltage and so the 6.0V values should be used. 


3-113 


MM54HC147/MM74HC147 





MMS4HC147/MM74HC147 


AC Electrical Characteristics vcc= 5 v,TA= 25 'c,CL=i 5 pF.tr=t,= 6 ns 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPHL. tpLH 

Maximum Propagation 
Delay 


31 

38 

ns 


AC Electrical Characteristics Vcc= 2.0V to 6.0V, Ci_= 50 pF, tr= tf = 6 ns (unless otherwise specified) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta = 

25“C 

74HC 

Ta=- 40 to 85X 

Ta = 

54HC 

-55 to125“C 

Units 





Typ 

Guaranteed Limits 


tpHL. tPLH 

Maximum Propagation 


2.0V 

181 

220 

275 


319 

ns 


Delay 


4.5V 

36 

44 

55 


64 

ns 




6.0V 

31 

37 

47 


54 

ns 

tjLH. tlHL 

Maximum Output Rise 


2.0V 

30 

75 

95 


110 

ns 


and Fall Time 


4.5V 

8 ■ 

15 

19 


22 

ns 




6.0V 

7 

13 

16 


19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 

(per package) 


180 




pF 

C|N 

Maximum Input 
Capacitance 



5 

10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpd Vcc^ f + i^q Vcc. and the no load dynamic current consumption, ls=CpD Vcc f + Icc- 




3-114 





National 
Semiconductor 

MM54HC149/MM74HC149 
8 Line to 8 Line Priority Encoder 



microCMOS 


General Description 

This priority encoder utilizes microCMOS Technology, 3.0 
micron silicon gate N-well CMOS. It has the high noise im- 
munity and low power consumption typical of CMOS cir- 
cuits, as well as the speeds and output drive similar to 
LS-TTL. 

This priority encoder accep t s 8 in put request lines, Ri7-Rl0, 
and outputs 8 lines, RO7-RO0. Only one request output 
can be low at a time. The output that is low is dependent on 
the highest priority request that is low. The order of priority 
is RI7 highest and RIO lowest. Also provided is and enable 
input, ROE, which when high f orces all outputs high. A re- 
quest output Is also provided, RQP, which goes low when 
any RIn is active. 

All inputs to this device are protected from damage due to 
electrostatic discharge by diodes to Vcc and ground. 


Features 

■ Propagation delay: 1 5 ns typical 

■ Wide power supply range: 2-6V 

■ Low quiescent current: 80 fxA max (74HC Series) 

■ Wide input noise immunity 


Connection Diagram 

Dual-In-Line Package 


Vcc ROO R01 R02 R03 R04 R05 R06 R07 RQP 



Top View 

Order Number MM54HC149J or MM74HC149J,N 
See NS Package J20A or N20A 


Truth Tabie 


Inputs 

Outputs 

0 

1 

2 

3 

4 

5 

6 

7 

RQE 

0 

1 

2 

3 

4 

5 

6 

7 

RQP 

X 

X 

X 

X 

X 

X 

X 

X 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

H 

L 

H 

H 

H 

H 

H 

H 

H 

H 

H 

X 

X 

X 

X 

X 

X 

X 

L 

L 

H 

H 

H 

H 

H 

H 

H 

L 

L 

X 

X 

X 

X 

X 

X 

L 

H 

L 

H 

h' 

H 

H 

H 

H 

L 

H 

L 

X 

X 

X 

X 

X 

L 

H 

H 

L 

H 

H 

H 

H 

H 

L 

H 

H 

L 

X 

X 

X 

X 

L 

H 

H 

H 

L 

H 

H 

H 

H 

L 

H 

H 

H 

L 

X 

X 

X 

L 

H 

H 

H 

H 

L 

H 

H 

H 

L 

H 

H 

H 

H 

L 

X 

X 

L 

H 

H 

H 

H 

H 

L 

H 

H 

L 

H 

H 

H 

H 

H 

L 

X 

L 

H 

H 

H 

H 

H 

H 

L 

H 

L 

H 

H 

H 

H 

H 

H 

L 

L 

H 

H 

H 

H 

H 

H 

H 

L 

L 

H 

H 

H 

H 

H 

H 

H 

L 



3-115 


MM54HC149/MM74HC149 



MM54HC149/MM74HC149 


Absolute Maximum Ratings (Notes 1 & 2) 


Supply Voltage (Vcc) 

DC Input Voltage (V|fs|) 

DC Output Voltage (Vqut) 

Clamp Diode Current (I|k, Iqk) 

DC Output Current, per pin (Iqut) 

DC Vcc or GND Current, per pin (Ice) 
Storage Temperature Range (Tstg) 
Power Dissipation (Pq) (Note 3) 

Lead Temperature (TJ 
(Soldering 1 0 seconds) 


-0.5 to +7.0V 
-1.5 to VCC+1.5V 
-0.5 to Vcc + 0.5V 
±20 mA 
±25 mA 
±50 mA 
-65°C to ±150"C 
500 mW 

260“C 


Operating Conditions 

Min 

Supply Voltage (Vcc) 2 

DC I nput or Output Voltage 0 

(V|N. Vqut) 

Operating Temp. Range (Ta) 
MM74HC -40 

MM54HC -55 

Input Rise or Fall Times 
(tr.tf) Vcc=2.0V 
Vcc = 4.5 V 
Vcc = 6.0 V 


Max 

6 

Vcc 


±85 

±125 

1000 

500 

400 


Units 

V 

V 


“C 

°c 

ns 

ns 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta= 

= 25°C 

74HC 

Ta=- 40 to 85°C 

54HC 

Ta=- 55 to125°C 

Units 



Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 


2.0V 


0.3 

0.3 

. 0.3 

V 


Input Voltage 


4.5V 


0.9 

0.9 

0.9 

V 




6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|H orViL 








Output Voltage 

|IoutI^20 /xA 

2.0V 

2.0 


1.9 

1.9 

V 




4.5V 

4.5 


4.4 

4.4 

V 




6.0V 

6.0 


5.9 

5.9 

V 



V|N = V|HdrV|L 
|IoutI^ 4.0 mA 

4.5V 

4.2 

.3.98 

3.84 

3.7 

V 



||outI^ 5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H orViL 






‘ 


Output Voltage 

|Iout1s: 20 jiA 

2.0V 

0 

0.1 


0.1 

V 



' 

4.5V, 

0 

0.1 


0.1 

V 




6.0V 

0 

0.1 


0.1 

V 



ViN=V|H orVm 
1 IoutU 4.0 mA 

4.5V 

0.2 

0.26 


0.4 

V 



||outI^ 6.2 mA 

6.0V 

0.2 

0.26 


0.4 

V 

l|N 

Maximum Input 
Current 

V|N = Vqq or GND 

6.0V 


±0.1 

±1.0 

±1.0 

julA 

Icc 

Maximum Quiescent 

V|N~ Vcc 0^" GND 

6.0V 


8.0 

80 

160 

/xA 


Supply Current 

IoUT"=6 P-A 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 

Note 2: Unless otherwise specified all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/°C from 65°C to 85°C: ceramic “J" package: - 1 2 mW/*C from 1 00°C to 1 25‘’C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vih and Vil occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 

AC Electrical Characteristics vcc=5v,TA=25*c,CL=i5pF,tr=tf=6ns(Note6) 


Symbol 


Parameter 


Conditions 


Typ 


Guaranteed Limit 


Units 


tpHL. tpLH 


Maximum Propagation Delay, Any Input 
To Any Output 


20 


33 


3-116 






AC Electrical Characteristics Vcc = 2.0V to 6.0V, Cl =50 pF, tr=tf = 6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25“C 

74HC 

Ta=-40 to 85°C 

Ta = 

54HC 

-55 to125°C 

Units 





Typ 

1 Guaranteed Limits 


tpHL. tpLH 

Maximum Propagation 




205 

255 


310 

ns 


Delay Any Input To Any 


WBEm 


41 

51 


62 

ns 


Output 




35 

43 


53 

ns 

tjLH. tjHL 

Maximum Output Rise 


2.0V 

30 

75 

95 


110 

ns 


and Fall Time 


4.5V 

8 

15 

19 


22 

ns 




6.0V 

7 

13 

16 


19 

ns 

CpD 

Power Dissipation 
Capacitance (Note 5) 



70 




pF 

C|N 

Maximum Input 
Capacitance 



5 

10 

10 

10 

pF 








MM54HC151/MM74HC151 


National 
Semiconductor 

MM54HC151/MM74HC151 8-Channel 




microCMOS 


Digital Multiplexer 

General Description 

This high speed Digital multiplexer utilizes micro- 
CMOS Technology, 3.5 micron silicon gate P-well CMOS. 
Along with the high noise immunity and low power dissipa- 
tion of standard CMOS integrated circuits, it possesses the 
ability to drive 10 LS-TTL loads. The MM54HC151/ 
MM74HC151 selects one of the 8 data sources, depending 
on the address presented on the A, B, and C inputs. It fea- 
tures both true (Y) and complement (W) outputs. The 
STROBE input must be at a low logic level to enable this 
multiplexer. A high logic level at the STROBE forces the W 
output high and the Y output low. 

The 54HC/74HC logic family is functionally as well as pin- 
out compatible with the standard 54LS/74LS logic family. 


All inputs are protected from damage due to static dis- 
charge by internal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay 
data select to output Y: 26 ns 

■ Wide operating supply voltage range: 2-6V 

■ Low input current: < 1 juA maximum 

■ Low quiescent supply current: 80 juA maximum (74HC) 

■ High output drive current: 4 mA minimum 


Connection and Logic Diagrams 

Dual-In-Line Package 

DATA INPUTS DATA SELECT 

Vcc 4 5 6 7 A B C 



DATAiNPUTS OUTPUTS TL/F/5313-1 

Top View 


Truth Tabie 


Inputs 

Outputs 

Select 

Strobe 



C 

B 

A 

S 

Y 

W 

X 

X 

X 

H 

L 

H 

L 

L 

L 

L 

DO 

DO 

L 

L 

H 

L 

D1 

DT 

L 

H 

L 

L 

D2 

D2 

L 

H 

H 

L 

D3 

D3 

H 

L 

L 

L 

D4 

D4 

H 

L 

H 

L 

D5 

D5 

H 

H 

L 

L 

D6 

D6 

H 

H 

H 

L 

D7 

D7 


H = High Level, L = Low Level, X = Don’t Care 
DO, D1 ...D7 = the level of the respective D input 


Order Number MM54HC151J or MM74HC151J, N 
See NS Package J16A or N16E 



3-118 




Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) - 0.5 to + 7.0V 

DC Input Voltage (V|n) - 1 .5 to Vcc + 1 -SV 

DC Output Voltage (Vout) “ 0.5 to Vcc + 0.5V 

Clartip Diode Current (I|k, Iqk) ± 20 mA 

DC Output Current, per pin (Iqut) ± 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage Temperature Range (Tstg) -65°C to + 1 50°C 
Power Dissipation (Pq) (Note 3) 500 mW 

Lead T emp. (T J (Soldering 1 0 seconds) 260°C 


Operating Conditions 



Min 

Max 

Units 

Supply Voltage (Vcc) 

2 

6 

V 

DC Input or Output Voltage 

0 

Vcc 

V 

(V|N. Vqut) 

Operating Temp. Range (Ta) 

MM74HC 

-40 

+ 85 


MM54HC 

-55 

+ 125 

“C 

Input Rise or Fall Times 

(tr.tf) Vcc=2.0V 


1000 

ns 

Vcc = 4.5 V 


500 

ns 

Vcc = 6.0 V 


400 

ns 


DC Eiectricai Characteristics (Note 4) 






Ta = 

25^0 

74HC 

54HC 


Symbol 

Parameter 

Conditions 

Vcc 

Ta=- 40 to BSX 

TA=-55to125°C 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum' High Level 


2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 


4.5V 


3.15 

3.15 

3.15 

V 




6.0V 


4.2 

4.2 

4.2 

V 

VlL 

Maximum Low Level 




0.3 

0.3 

0.3 

V 


Input Voltage 




0.9 

0.9 

0.9 

V 






1.2 

1.2 

1.2 

V 

Vqh 

Minimum High Level 

V|N = V|HOrV|L 








Output Voltage 

|louTk20 fxA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|HOrV|L 
|IoutN 4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



i^OUTl^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low Level 

V|N = V|H orV|L 








Output Voltage 

1 bull ^20 fiA 

2.0V 

0 

0.1 


0.1 

V 




4.5V 

0 

0.1 


0.1 

V 




6.0V 

0 

0.1 


0.1 

V 



V|N = V|HOrV|L 
|IoutN 4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



IioutN 5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum Input 
Current 

V|N“ Vcc Oi* GND 

6.0V 


±0.1 

±1.0 

±1.0 

fxA 

•cc 

Maximum Quiescent 

V|N~ Vcc or GND 

6.0V 


8.0 

80 

160 

juA 


Supply Current 

•OUT = 0 F-A 








Note 1; Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless othenvise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 1 2 mW/*C from 65°C to SS'C; ceramic “J” package: - 1 2 mW/*C from 1 00“C to 1 25'’C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc = 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 



3-119 


MM54HC151/MM74HC151 







MM54HC151/MM74HC151 


AC Electrical Characteristics vcc=5v.TA=25*c.cL=i5pF.tr=tf=6n8 


Symbol 

Parameter 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tpHL. tPLH 

Maximum Propagation Delay 
A, B or C to Y 




ns 

tpHL. tPLH 

Maximum Propagation Delay 
A, B or C to W 


27 

35 

ns 

tPHL. tPLH 

Maximum Propagation Delay 
Any D to Y 


22 

29 

ns 

tPHL. tPLH 

Maximum Propagation Delay 
anyDtoW ‘ 



32 

ns 

tpHL. tPLH 

Maximum Propagation Delay 
Strobe to Y 


17 

23 

ns 

tPHL. tPLH 

Maximum Propagation Delay 
Strobe to W 


16 

21 

ns 


AC Electrical Characteristics Cl= 50 pF, tr=tf=6 ns (unless otherwise specified) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta= 


74HC 

TA=-40to85X 

54HC 

TA=-55to125X 

Units 





Typ 

Guaranteed Limits 


fpHL. tPLH 

Maximum Propagation Delay 



90 

205 

256 

300 

■OH 


A, B or C to Y 



31 

41 

51 

60 





mEm 

26 

35 

44 

51 

OJI 




B3I 

95 

205 

256 

300 

^01 





32 

41 

51 

60 





EEQ 

27 

35 

44 

51 

oo 

fPHL. tPLH 

Maximum Propagation Delay 


021 

70 

195 

244 

283 

^oi 


any D to Y 



27 

39 

49 

57 






23 

33 

41 

48 

^^O 

tpHL. tPLH 

Maximum Propagation Delay 


2.0V 

75 

185 

231 

268 

^oi 


any D to W 


4.5V 

29 

37 

46 

54 





6.0V 

25 

32 

40 

46 

^^O 

tpHb tPLH 

Maximum Propagation Delay 


021 

50 

140 

175 

203 



Strobe to Y 



21 

28 

35 

41 





mEm 

18 

24 

30 

35 

091 

tpHL. tpLH 

Maximum Propagation Delay 



45 

127 

159 

185 

ns 


Strobe to W 


1^21 

20 

25 

32 

37 

ns 




SO 

17 

22 

28 

32 

ns 

tlLH. tTHL 

Maximum Output Rise 


2.0V 

30 


95 

110 

ns 


and Fall Time 


4.6V 

8 

11 

19 

22 

ns 




6.0V 

7 

Q 

16 

19 

ns 


Power Dissipation 
Capacitance (Note 5) 

(per package) 


110 




pF 

Qn 

Maximum Input 

Capacitance 



5 

10 

10 

10 

pF 

Note 5: Cpo determines the no load dynamic power consumption, Pd=Cpq Vcc 2 f+ |qq Vcc. and the no load dynamic current consumption, ls=CpD Vcc t+ Icc- 


3-120 
















































































National 

Semiconductor 


MM54HC153/MM74HC153 
Dual 4-Input Multiplexer 
General Description 

This 4-to-1 line multiplexer utilizes microCMOS Technology, 
3.5 micron silicon gate P-well CMOS. It has the low power 
consumption and high noise immunity of standard CMOS 
integrated circuits. This device is fully buffered, allowing it to 
drive 10 LS-TTL loads. Information on the data inputs of 
each multiplexer is selected by the address on the A and B 
inputs, and is presented on the Y outputs. Each multiplexer 
possesses a strobe input which enables it when taken to a 
low logic level. When a high logic level is applied to a strobe 
input, the output of its associated multiplexer is taken low. 
The 54HC/74HC logic family is functionally and pinout com- 
patible with the standard 54LS/74LS logic family. All inputs 


Connection Diagram 


microCMOS 


are protected from damage due to static discharge by inter- 
nal diode clamps to Vcc and ground. 

Features 

■ Typical propagation delay: 24 ns 

■ Wide power supply range: 2V-6V 

■ Low quiescent current: 80 jaA maximum (74HC Series) 

■ Low input current: 1 jaA maximum 

■ Fanout of 1 0 LS-TTL loads 


Dual-ln-Line Package 


STROBE A , 

OR ecl CRT ORO ORO 



STROBE 
1G SELECT 


ICO OUTPUT GND 
— * 1Y 


Truth Tabie 


Top View 

Order Number MM54HC153J or MM74HC153J,N 
See NS Package J16A or N16E 


Data Inputs 


Strobe Output 



Select inputs A and B are common to both sections. 
H = high level, L = low level, X = don’t care. 


3-121 


MM54HC153/MM74HC153 






MM54HC153/MM74HC153 


Absolute Maximum Ratings (Notes i & 2) 

Operating Conditions 



Supply Voltage (Vcc) 

-0.5 to +7.0V 


Min 

Max 

Units 

DC Input Voltage (V|n) 

-1.5toVcc+1.5V 

Supply Voltage (Vcc) 

2 

6 

V 

DC Output Voltage (Vqut) 

-0.5 to Vcc + 0.5V 

DC Input or Output Voltage 

0 

Vcc 

V 

Clamp Diode Current (I|k, Iqk) 

±20 mA 

{V|N. Vqut) 




DC Output Current, per pin (Iqut) 

±25 mA 

Operating Temp. Range (Ta) 
MM74HC 

-40 

±85 

°c 

DC Vcc or GND Current, per pin (Ice) 

±50 mA 

MM54HC 

-55 

±125 

“C 

Storage Temperature Range (Tstg) 

-65°Cto +150*C 

Input Rise or Fall Times 




Power Dissipation (Pd) (Note 3) 

500 mW 

(tr.tf) Vcc=2.0V 


1000 

ns 

Lead Temperature (Ji) 


Vcc = 4.5V 


500 

ns 

(Soldering 1 0 seconds) 

260“C 

Vcc = 6.0V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symboi 

Parameter 

Conditions 

Vcc 

Ta= 

:25"C 

74HC 

Ta=- 40 to SSX 

54HC 

Ta=- 55 to125X 

Units 





Typ 

Guaranteed Limits 


V|H 

Minimum High Level 


2.0V 


■3 



V 


Input Voltage 


4.5V 





V 




6.0V 





V 

V|L 

Maximum Low Level 


2.0V 




0.3 

V 


Input Voltage 


4.5V 


mlM 


0.9 

V 




6.0V 




1.2 

V 

Vqh 

Minimum High Level 

V|N = V|H orV|L 








Output Voltage 

|IoutI^20 ixA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 




4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



V|N = V|H orViL 
|IoutI^ 4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



I^OUT^^6.2 mA 

6.0V 

5.3 

5.48 

5.34 

5.2 

V 

VoL 

Maximum Low Level 

V|N = V|H or V|L 








Output Voltage 

|IoutI^20 }xA 

2.0V 

0 

0.1 

0.1 

0.1 

V 




4.6V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



ViN = V|H orV|L 
|louTk4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



^^OUTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

■in 

Maximum input 
Current 

ViN~ Vcc or GND 

6.0V 


±0.1' 

±1.0. 

±1.0 

fxA 

Icc 

Maximum Quiescent 

V|N“ Vcc or GND 

6.0V 


8.0 

80 

160 

ju,A 


Supply Current 

•OUT = 0 M 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic “N” package: - 12 mW/*C from 65*C to 85’C: ceramic “J” package: - 1 2 mW/'C from 1 0O'C to 1 25'‘C. 
Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case Vm and V|l occur at Vcc=5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Iqc. and 
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 


3-122 










tpHL. ^PLH Maximum Propagation Delay, Select A or B to Y 


Maximum Propagation Delay, any Data to Y 


tpHbtpLH I Maximum Propagation Delay. Strobe to Y | | 8 | 

AC Electrical Characteristics Cl =50 pF, tr=tf=6 ns (unless otherwise specified) 


T =9*;‘>r 74HC 

I A ^ T. = -dn 


Conditions 


74HC 54HC 

Ta= -40 to 85°C Ta= -55 to ■ 


Guaranteed Limits 






^TLH. tjHL 

Maximum Output 

Rise and Fall Time 


C|N 

Maximum Input Capacitance 





Power Dissipation 
Capacitance 


(Note 5) (per package) 
Outputs Enabled 
Outputs Disabled 























MM54HC154/MM74HC154 


National 
Semiconductor 

MM54HC154/MM74HC154 
4-to-16 Line Decoder 

General Description 

This decoder utilizes microCMOS Technology, 3.5 micron 
silicon gate P-well CMOS, and is well suited to memory ad- 
dress decoding or data routing applications. It possesses 
high noise immunity, and low power consumption of CMOS 
with speeds similar to low power Schottky TTL circuits. 

The MM54HC154/MM74HC154 have 4 binary select inputs 
(A, B, C, and D). If the device is enabled these inputs deter- 
mine which one of the 16 normally high outputs will go low. 
Two active low enables (G1 and G2) are provided to ease 
cascading of decoders with little or no external logic. 



microCMOS 


Each output can drive 1 0 low power Schottky TTL equiva- 
lent loads, and is functionally and pin equivalent to the 
54LS154/74LS154. All inputs are protected from damage 
due to static discharge by diodes to Vcc and ground. 

Features 

■ Typical propagation delay; 21 ns 

■ Power supply quiescent current: 80 juA (7^4HC) 

■ Wide power supply voltage range: 2-6V 

■ Low input current: 1 juA maximum 



Connection Diagram Dual-ln-Line Package 

INPUTS OUTPUTS 



Top View 

Order Number MM54HC154J or MM74HC154J, N 
See NS Package J24A or N24C 


Truth Table 


Inputs 1 

Low 

Output* 

G1 

G2 

D 

c 

B 

A 

L 

L 

L 

L 

L 

L 

0 

L 

L 

L 

L 

L 

H 

1 

L 

L 

L 

L 

H 

L 

2 

L 

L 

L 

L 

H 

H 

3 

, L 

L 

L 

H 

L 

L 

4 

L 

L 

L 

H 

L 

H 

5 

L 

L 

L 

H 

H 

L 

6 

L 

L 

L 

H 

H 

H 

7 

L 

L 

H 

L 

L 

L 

8 

L 

■ L 

H 

L 

L 

H 

9 

L 

L 

H 

L 

H 

L 

10 

L 

L 

H 

L 

H 

H 

11 

L 

L 

H 

H 

L 

L 

12 

L 

L 

H 

H 

L 

H 

13 

L 

L 

H 

H 

H 

L 

14 

L 

L 

H 

H 

H 

H 

15 

L 

H 

X 

X 

X 

X 

— 

H 

L 

X 

X 

X 

X 

— 

H 

H 

X 

X 

X 

X 

— 


*AII others high 


3-124 



Absolute Maximum Ratings (Notes 1 & 2) 

Supply Voltage (Vcc) “ 0.5 to + 7.0V 

DC Input Voltage (V|n) - 1 .5 to Vcc+ 1 -SV 

DC Output Voltage (Vqijt) “ 0.5 to Vcc + 0.5V 

Clamp Diode Current (I|k, Iqk) ± 20 mA 

DC Output Current, per pin (Iqut) ± 25 mA 

DC Vcc or GND Current, per pin (Ice) ± 50 mA 

Storage T emperature Range (T stg) - 65“C to + 1 50°C 

Power Dissipation (Pp) (Note 3) 500 mW 

Lead Temp. (Tl) (Soldering 10 seconds) 260°C 


Operating Conditions 



Min 

Max 

Units 

Supply Voltage (Vcc) 

2 

6 

V 

DC Input or Output Voltage 

0 

Vcc 

V 

(V|N. Vqut) 

Operating Temp. Range (Ta) 

MM74HC 

-40 

+ 85 

“C 

MM54HC 

-55 

+ 125 

“C 

Input Rise or Fall Times 

(tr.tf) Vcc=2.0V 


1000 

ns 

Vcc = 4.5V 


500 

ns 

Vcc = 6.0 V 


400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

= 25X 

74HC 

Ta=- 40 to 85X 

54HC 

Ta=- 55 to125°C 

Units 





Typ 

Guaranteed Limits 



Minimum High 


2.0V 


1.5 

1.5 

1.5 

- V 


Level Input 


4.5V 


3.15 

3.15 

3.15 

V 


Voltage 


6.0V 


4.2 

4.2 

4.2 

V 


Maximum Low 


2.0V 


0.3 

0.3 

0.3 

V 


Level Input 


4.5V 


0.9 

0.9 

0.9 

V 


Voltage 


6.0V 


1.2 

1.2 

1.2 

V 

Vqh 

Minimum High 

V|n = V|h orViL 








Level Output 

|IoutI^20 ixA 

2.0V 

2.0 

1.9 

1.9 

1.9 

V 


Voltage 


4.5V 

4.5 

4.4 

4.4 

4.4 

V 




6.0V 

6.0 

5.9 

5.9 

5.9 

V 



Vin = Vih or V|L 
1 IoutI^ 4.0 mA 

4.5V 

4.2 

3.98 

3.84 

3.7 

V 



^^OUT^^5.2 mA 

6.0V 

5.7 

5.48 

5.34 

5.2 

V 

Vql 

Maximum Low 

ViN = V|Hor V|L 








Level Output 

|IoutI^20 iiA 

2.0V 

0 

0.1 

0.1 

0.1 

V 


Voltage 


4.5V 

0 

0.1 

0.1 

0.1 

V 




6.0V 

0 

0.1 

0.1 

0.1 

V 



V|n = V|h or V|L 
|louTk4.0 mA 

4.5V 

0.2 

0.26 

0.33 

0.4 

V 



|l0UTi^5.2 mA 

6.0V 

0.2 

0.26 

0.33 

0.4 

V 

l|N 

Maximum 

Input Current 

V|N~ Vcc or GND 

6.0V 


±0.1 

±1.0 

±1.0 

/xA 

•cc 

Maximum 

V|N~ Vcc or GND 

6.0V 


8.0 

80 

160 

^lA 


Quiescent 
Supply Current 

Iqut =6 








Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified all voltages are referenced to ground. 


Note 3: Power Dissipation temperature derating — plastic "N" package; - 1 2 mWrC from 65“C to SS'C; ceramic “J" package: - 1 2 mW/'C from 1 0CC to 1 25“C. 
Note 4: For a power supply of 5V ±1 0% the worst case output voltages (Vqh. and Vql) occur for HC at 4.5V. Thus the 4.5V values should be used when designing 
with this supply. Worst case V|h and V|l occur at Vcc = 5.5V and 4.5V respectively. (The V|h value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice. and 
Iqz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 



3-125 


MM54HC154/MM74HC154 



MM54HC154/MM74HC154 


AC Electrical Characteristics vcc= 5 v,TA= 25 '’c,CL=i 5 pF,tr=tf= 6 r 


Symbol 

Parameter 

Conditions* 

Typ 

Guaranteed Limit 

Units 

tPHL. tpLH 

Maximum Propagation Delay, ^ or A, B, C, D 


21 

32 

ns 


AC Electrical Characteristics Vcc=2.0V to 6.0V, Cl =50 pF, tr=tf=6 ns (unless otherwise specified) 


Symbol 

Parameter 

Conditions 

Vcc 

Ta = 

25X 

74HC 

Ta=- 40 to 85X 

Ta= 

54HC 

-55 to125X 

Units 





Typ 

Guaranteed Limits 


fpHL. fpLH 

Maximum Propagation 


2.0V 

63 

160 

190 


220 

mm 


Delay, G1 or G2 


4.5V 

24 

36 

42 


46 



or A, B, C, D 


6.0V 

20 

30 

35 


39 

WM 

tTLH. tlHL 

Maximum Output 


2.0V 

25 

II 

95 


110 

HOI 


Rise and Fall Time 


4.5V 

7 

11 

19 


22 





6.0V 

6 

13 

16 


19 


CpD 

Power Dissipation 
Capacitance (Note 5) 



90 





C|N 

Maximum Input 
Capacitance 



5 

10 

10 

10 

pF 


Note 5: Cpo determines the no load dynamic power consumption, Pd= Cpo Vcc^ f + Ice Vcc. and the no load dynamic current consumption, ls= Cpo Vec ^ + icc- 


3-126 






















MM54HC154/MM74HC154 





MM54HC155/MM74HC155 


National prelm 

Semiconductor 

MM54HC155/MM74HC155 Dual 2-To-4 
Line Decoder/Demultiplexers 


PRELIMINARY 


mIcroCMOS 


General Description 

The MM54HC155/MM74HC155 is a high speed silicon-gate 
CMOS decoder/demultiplexer. It utilizes mi 9 roCMOS Tech- 
nology, 3 jll silicon gate N well CMOS and features dual 1- 
line-to-4-line demultiplexers with independent strobes and 
common binary-address inputs. When both sections are en- 
abled by the strobes, the common address inputs sequen-. 
tially select and route associated input data to the appropri- 
ate output of each section. The individual strobes permit 
activating or inhibiting each of the 4-bit sections as desired. 
Data applied to input C1 is inverted at its outputs and data 
applied to C2 is true through its outputs. The inverter follow- 
ing the Cl data input permits use as a 3-to-8-rine decoder, 
or 1-to-8-line demultiplexer, without gating. 

All inputs to the decoder are protected from damage due to 
electrostatic discharge by diodes to Vcc and Ground. 


Connect and Logic Diagrams 


The device is capable of driving 1 0 low power Schottky TTL 
equivalent loads. 

The MM54HC155/MM74HC155 is functionally and pin 
equivalent to the 54LS155/74LS155 with the advantage of 
reduced power consumption. 

Features 

■ Applications 

Dual 2-to-4-line decoder 
Dual 1-to-4-line demultiplexer 
3-to-8-line decoder 
1-to-8-line demultiplexer 

■ Typical propagation delay: 22 nS 

■ Low quiescent current: 40 /xA maximum 
(74HC series) 

■ Wide operating range: 2~6V 

Truth Tables 

2-to-4-Line Decoder 

or 1-Line to 4-line Demultiplexer 

I Inputs I Outputs I 











Absolute Maximum Ratings (Notes 1 and 2) 

Supply Voltage (Vcc) - 0.5V to + 7.0V 

DC Input Voltage (V|n) - 1 .5V to Vcc + 1 .5V 

DC Output Voltage (Vqut) “ 0.5 to Vcc + 0.5V 

Clamp Diode Current (Ijk, Iqk) 20 mA 

DC Output Current, per pin (Iout) 25 mA 

DC Vcc or GND Current, per Pin (Ice) 50 mA 

Storage T emperature Range (T stg) ~ OS^C to + 1 50°C 

Power Dissipation (P^j) (Note 3) 500 mW 

Lead Temp. (Tj) (Soldering 1 0 sec) 260“C 


Operating Conditions 



Min Max 

Unit 

Supply Voltage (Vcc) 

2 6 

V 

DC Input or Output Voltage 



(V|N. Vqut) 

0 Vcc 

V 

Operating Temperature Range (Ta) 



MM74HC 

-40 +85 

c 

MM54HC 

-55 + 125 

c 

Input Rise/Fall Time Vcc = 2.0V 

1000 

ns 

(tr.tf) Vcc = 4.5V 

500 

ns 

Vcc = 6.0V 

400 

ns 


DC Electrical Characteristics (Note 4) 


Symbol 

Parameter 

Conditions 

< 

o 

o 

Ta = 

25X 

74HC 

Ta= -40‘’to85'’C 

54HC 

Ta 55" to 125"C 

Units 

Typ 

Guaranteed Limits 

ViH 

Minimum High Level 




2.0V 


1.5 

1.5 

1.5 

V 


Input Voltage 




4.5V 


3.15 

3.15 

3.15 

V 






6.0V 


4.2 

4.2 

4.2 

V 

V|L 

Maximum Low Level 




2.0V 




0.3 



Input Voltage 




4.5V 



0.9 

0.9 







6.0V 



1.2 

1.2 




V|N = ViH orV|L 

mil 






Vqh 

Minimum High Level 


msmsM 



1.9 

1.9 

1.9 

V 


Output Voltage 



om 


4.4 

4.4 

4.4 

V 





ms 


5.9 

5.9 

5.9 

V 




■out 

= 4.0 mA 

4.5V 


3.98 


3.7 

V 




■out 

= 5.2 mA 

6.0V 


5.48 


5.2 

V 



V|N = V|H orViL 







VoL 

Maximum Low Level 


IoutI = 20 jliA 

2.0V 

0 

0.1 

0.1 

0.1 

V 


Output Voltage 


IoutI = 20 iiA 

4.5V 

0 

0.1 

0.1 

0.1 

V 




IoutI = 20 jiA 

6.0V 


0.1 

0.1 

0.1 

V 







■ 



0.4 

V 



■H 

IBBi 


ms 

■ 



0.4 

V 

>IN 

Maximum Input 

V|N ~ VecorGND 

6.0V 


±0.1 

±1.0 

±1.0 

juiA 


Current 










icc 

Maximum Quiescent 

V|N ~ Vcc or GND 

6.0V 


8 

80 

160 

fxA 


Supply Current 

Iqut = 0 julA 









Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 
Note 2: Unless otherwise specified, all voltages are referenced to ground. 

Note 3: Power Dissipation temperature derating — plastic “N" package: -12 mW/°C from 65°C to BS'C. 


ceramic "J” package: -12 mW/*C from lOO^C to 125“. 

Note 4: For a power supply of 5V ±10% the worst case output voltages (Vqh and Vql) occur at 4.5V. Thus the 4.5V values should be used when designing with 
this supply. Worst case Vm and Vil occur at Vcc = 5.5V and 4.5V respectively. (The Vm value at 5.5V is 3.85V.) The worst case leakage current (I|n, Ice and Iqz) 
occur at the higher voltage and so the 6.0V values should be used. 



3-129 


MM54HC155/MM74HC155 










MM54HC155/MM74HC155 


AC Electrical Characteristics (Note 6) vcc = sv , ta = Z5°c, cl = is pf, tr = tf = e ns 

Symbol 

Parameters 

Conditions 

Typ 

Guaranteed 

Limit 

Units 

tPLH. tPHL 

Maximum Propagation Delay 
from Inputs A, B, or C2 to 
any Output 




ns 

tPLH. tpHL 

Maximum Propagation Delay 
from Inputs G1 or G2 to 
any Output 




ns 

tPLH. tPHL 

Maximum Propagation Delay 
from Input Cl to any 

Output 




ns 

AC ElGCtriCdl ChGrdCtGriStiCS (Note 6) Cl = so pF, tr = tf = e ns (unless otherwise specified) 

Symbol 

Parameter 

Vcc 

Typ 

Guaranteed Limits 

Units 

T = 25X 

T = 25°C 

74HC 

T = -40“to85X 

54HC 

T = -55“ to 125“C 

tpLH. tPHL 

Maximum Propagation Delay 
from Inputs A, B, or C2 to 
any Output 

2.0V 






4.5V 






litiM 







Maximum Propagation Delay 
from Inputs G1 or G2 to 
any Output 

EEDI 












039 






tPLH. tpHL 

Maximum Propagation Delay 
from Input Cl to any 

Output 

2.0V 

■ 

■■■1 


OOHHHH 

OH 

4.5V 






6.0V 






fTLH. tTHL 

Rise and Fall Time 

2.0V 






4.5V 






6.0V 






CpD 

Power Dissipation 
Capacitance 

EOi 






091 












C|N 

Minimum Input Capacitance 


5 

10 

10 

10 

pF 

Note 5: CPC determines the no load dynamic power consumption, Pd = (CPD*Vcc**2)*f +