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MICROPROCESSOR, 




Motorola's Microcontroller and 
Microprocessor Families 

Volume I 



Reliability 

Volume I 



Data Sheets 

Volume I and II 



Mechanical Data 

Volume II 



Evaluation Modules 

Volume II 



Ordering Information Forms 

Volume II 



I 
I 
I 
I 
I 



MOTOROLA MICROPROCESSOR DATA 



I 
I 



Motorola's Microcontroller and 
Microprocessor Families 

Volume I 



Reliability 

Volume I 



Data Sheets 

Volume I and II 



I 



Mechanical Data 

Volume II 



Evaluation Modules 

Volume II 



Ordering Information Forms 

Volume II 



MOTOROLA MICROPROCESSOR DATA 



MOTOROLA 



MICROPROCESSOR DATA 

VOLUME I 



Prepared by 
Microprocessor Products Group 

This book is intended to provide the design engineer with the technical data needed 
to completely and successfully design a microcomputer-based system. The Technical 
Summary and Advance Information data sheets for Motorola's microcontroller, micro- 
processor, and peripheral components are included. 

The information in this book has been carefully checked; no responsibility, however, 
is assumed for any inaccuracies. Furthermore, this information does not convey to the 
purchase of microelectronic devices any license under the patent rights of the 
manufacturer. 

Additional information on Motorola's new products and system development products 
are also included. For further marketing and application information, please contact: 

Motorola Inc. 

Microprocessor Products Group 
Microcontroller Division 
6501 William Cannon Drive West 
Austin, Texas 78735-8598 

512-891-2034 
512-891-2034 
602-994-6561 
Local Sales Office 
512-891-2990 

Motorola reserves the right to make changes without further notice to any products 
herein to improve reliability, function or design. Motorola does not assume any liability 
arising out of the application or use of any product or circuit described herein; neither 
does it convey any license under its patent rights nor the rights of others. Motorola 
products are not authorized for use as components in life support devices or systems 
intended for surgical implant into the body or intended to support or sustain life. Buyer 
agrees to notify Motorola of any such intended end use whereupon Motorola shall 
determine availability and suitability of its product or products for the use intended. 
Motorola and ® are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal 
Employment Opportunity/Affirmative Action Employer. 

Series A 
Second Printing 
©MOTOROLA INC., 1988 

Printed in U.S.A. "All Rights Reserved" 



iii 




Applications 

EVB/EVM/Development Systems 
Literature — Literature Distribution Center 
Marketing Information — Pricing 
Marketing Information — Availability 



DATA CLASSIFICATION 



Product Preview 

Data sheets herein contain information on a product under development. Motorola re- 
serves the right to change or discontinue these products without notice. 



Technical Summary 

Data sheets herein contain information on new products. Specifications and information 
are subject to change without notice. 

Advanced Information 

Data sheets herein contain information on new products. Specifications and information 
are subject to change without notice. , 



EXORciser is a register trademark of Motorola, Inc. 

HDS-300, MDOS, and BUFFALO are trademarks of Motorola, Inc. 

MS-DOS is a trademark of Microsoft, Inc. 

IBM is a register trademark of International Business Machines, Inc. 



TABLE OF CONTENTS 



The Microprocessor/Microcontroller and Peripheral Data book consist of a two volume set. Refer 
to the table of contents and the master index for division of the chapters and locations of devices. 

Page 

Chapter 1 — Motorola's Microprocessor and Microcontroller Families 

M68HC11/M6801/M6805/M6804 Families 1-1 

Development Support 1-4 

Single-Chip MCU Selector Guides 1-4 

Chapter 2 — Reliability and Quality Summary 

Introduction 2-1 

Quality and Reliability System 2-1 

Packaging System 2-2 

Results and Conclusion 2-23 

Failure Rate Calculations 2-24 

Chapter 3 — Data Sheets 

(See master Index for sequence) 

Chapter 4 — Mechanical Data 

Introduction Vol. II 

Package Dimensions Vol. II 

Chapter 5 — Evaluation Modules 

Development Station Vol. II 

Low Cost MCU Evaluation Modules Vol. II 

Chapter 6 — Product Ordering Forms 

Introduction Vol. II 



MOTOROLA MICROPROCESSOR DATA 



MASTER INDEX 



Device Page 
Number Description Number 

MC2672 Programmable Video Tinner Controller 3-1 

MC2674 Advanced Video Display Controller , 3-28 

MC6800 8-Bit Microprocessor Unit 3-61 

MC6801/ 

MC6803 8-Bit Microcontroller Unit 3-92 

MC6801U4/ 

MC6803U4 8-Bit Microcontroller Unit 3-131 

MC68701 8-Bit Microcontroller Unit 3-174 

MC68701U4 8-Bit Microcontroller Unit ,. 3-214 

MC6802 8-Bit Microprocessor with Clock and RAM. 3-256 

MC6804J1 8-Bit Microcontroller Unit 3-278 

MC6804J2 8-Bit Microcontroller Unit 3-297 

MC6804P2 8-Bit Microcontroller Unit ..... 3-316 

MC68704P2 8-Bit Microcontroller Unit with EPROM 3-335 

MC68HC04J2 8-Bit HCMOS Microcontroller Unit.. ; 3-355 

MC68HC04J3 8-Bit HCMOS Microcontroller Unit ., 3-374 

MC68HC04P4 8-Bit HCMOS Microcontroller Unit 3-393 

MC68HC704P4 8-Bit HCMOS Microcontroller Unit with OTPROM or EPROM 3-395 

MC6805P2 8-Bit Microcontroller Unit with 1K ROM 3-397 

MC6805P6 8-Bit Microcontroller Unit 3-415 

MC6805R2 8-Bit Microcontroller Unit with A/D Converter 3-433 

MC6805R3 8-Bit Microcontroller Unit with A/D Converter 3-453 

MC6805S2 8-Bit Microcontroller Unit with A/D Converter, SPI, 

and Three Timers — 3-473 

MC6805S3 8-Bit Microcontroller Unit with A/D Converter, SPI, 

and Three Timers 3-502 

MC6805U2 8-Bit Microcontroller Unit ,.. 3-532 

MC6805U3 8-Bit Microcontroller Unit 3-550 

MC68705P3 8-Bit Microcontroller Unit with EPROM 3-568 

MC68705P5 8-Bit Microcontroller Unit with EPROM 3-586 

MC68705R3 8-Bit Microcontroller Unit with A/D Converter 

and EPROM 3-604 

MC68705R5 8-Bit Microcontroller Unit with A/D Converter 

Secured EPROM 3-624 

MC68705S3 8-Bit Microcontroller Unit with A/D Converter, SPI, 

EPROM, and Three Timers , 3-643 

MC68705U3 8-Bit Microcontroller Unit with EPROM...;. 3-674 

MC68705U5 8-Bit Microcontroller Unit with Secured EPROM 3-692 

MC68HC05A6 8-Bit Microcontroller Unit 3-710 

MC68HC05B4 8-Bit Microcontroller Unit 3-712 

MC68HC05B6 8-Bit Microcontroller Unit . 3-751 

MC68HC05C2 8-Bit Microcontroller Unit 3-792 



MOTOROLA MICROPROCESSOR DATA 

vii 



MASTER INDEX (Continued) 



Device Page 
Number Description Number 

MC68HC05C3 8-Bit Microcontroller Unit 3-819 

MC68HC05C4 8-Bit Microcontroller Unit 3-859 

MC68HC05C8 8-Bit Microcontroller Unit 3-899 

MC68HC05C9 8-Bit Microcontroller Unit ..... Vol. II 

MC68HC05L6 8-Bit Microcontroller Unit Vol. II 

MC68HC05M4 8-Bit Microcontroller Unit .............. Vol. II 

MC68HC05P1 8-Bit Microcontroller Unit Vol. II 

MC68HCL05C4 8-Bit Microcontroller Unit Vol. II 

MC68HCL05C8 8-Bit Microcontroller Unit Vol. II 

MC68HSC05C4 8-Bit Microcontroller Unit Vol. II 

MC68HSC05C8 8-Bit Microcontroller Unit Vol. II 

MC68HC705B5 8-Bit Microcontroller Unit with OTPROM... Vol. II 

MC68HC705C4 8-Bit Microcontroller Unit with OTPROM or EPROM Vol. II 

MG68HC705C8 8-Bit Microcontroller Unit with Standard EPROM . Vol. II 

MC68HC805B6 8-Bit Microcontroller Unit with EEPROM Vol. II 

MC68HC805C4 8-Bit Microcontroller Unit with OTPROM or EEPROM Vol. II 

MC146805E2 8-Bit Microcontroller Unit.... Vol. II 

MC146805F2 8-Bit Microcontroller Unit .. Vol. II 

MC146805G2 8-Bit Microcontroller Unit .......... .L;.......... Vol. II 

MC6809 8-Bit Microcontroller Unit .....v.... ........:..... ; Vol. II 

MC6809E 8-Bit Microcontroller Unit Vol. II 

MC6810 128x8 Bit Static RAM Vol. II 

MC68HC11A0 8-Bit HCMOS Microcontroller Unit with SPI, SCI, ■ 

and A/D Converter..... Vol. II 

MC68HC11A1 8-Bit HCMOS Microcontroller Unit with SPI, SCI, A/D Converter, 

and EEPROM. Vol. II 

MC68HC1 1 A8 8-Bit HCMOS Microcontroller Unit with SPI, SCI, A/D Converter, 

and EEPROM Vol. II 

MC68HC11D3 8-Bit HCMOS Microcontroller Unit SPI, SCI, and EEPROM.. Vol. II 

MC68HC11E1 8-Bit HCMOS Microcontroller Unit with SPI, SCI, A/D Converter, 

and EEPROM... Vol. II 

MC68HC1 1E9 8-Bit HCMOS Microcontroller Unit with SPI, SCI, A/D Converter, 

and EEPROM.... Vol. II 



MC68HC11F1 8-Bit HCMOS Microcontroller Unit with SPI, SCI, A/D Converter, 

and EEPROM Vol, I! 

MC68HC711D3 8-Bit HCMOS Microcontroller Unit with OTPROM or EEPROM Vol. I 

MC68HC811E2 8-Bit HCMOS Microcontroller Unit with SPI, SCI, A/D Converter, 



and EEPROM ...... Vol. II 

MC146818 Real Time Clock with RAM Vol. I 

MC146818A Real Time Clock with RAM...:...::...... Vol. I 

MC6821 Peripheral Interface Adapter Vol. I; 

MC-1 46823 CMOS Parallel Interface....;..:.........:............ Vol. I 

MC68HC24 Port Replacement Mbdule.:iv;.:;:.v,.;...,... v....,,..../..:...: Vol. I 

MC68HC34 Dual Port RAM Vol. II 

MC6840 Programmable Timer Module Vol i 

MC6844 Direct Memory Access Controller Vol. I 

MC6845 CRT Controller... Vol. II 



MOTOROLA MICROPROCESSOR DATA 
viii 



MASTER INDEX (Concluded) 



Device Page 
Number Description Number 

MC6850 Asynchronous Communications Interface Adapter Vol. II 

MC6852 Synchronous Serial Data Adapter Vol. II 

MC6854 Advanced Data Link Controller Vol. II 

MC68488 General-Purpose Interface Adapter Vol.11 

MC6898 Cable Driver and Receiver Vol. II 

MC68HC99 Hard Disk Controller Vol.11 



MOTOROLA MICROPROCESSOR DATA 
ix 



Motorola's Microcontroller and 
Microprocessor Families 

Volume I 



MOTOROLA MICROPROCESSOR DATA 



MOTOROLA'S 
MICROCONTROLLER AND MICROPROCESSOR 
FAMILIES 

Motorola manufactures the industry's most complete selection of solid-state microcontroller units 
(MCU) and microprocessor (MPU), providing the performance and design flexibility needed by 
the design engineer. ; 

Motorola's family concept has been extremely popular in the MCU industry. This family concept 
was pioneered with the introduction of the M6800 Family 1974. Four families have evolved from 
the M6800 Family to fulfill expanding customer requirements. These families are the M68HC11, 
M6801, M6805, and the M6804. Figure 1-1 illustrates the family evolution. 

Numerous peripheral devices have been developed and are available to support the MCUs and 
MPUs. 



M68HC11/M6801/M6805/M6804 FAMILIES 

The M68HC11 Family offers high performance in a single-chip MCU with Electronic Eraseable 
Programmable Read Only Memory (EEPROM), a 16-bit timer, a Serial Communication Interface 
(SCI), a Serial Peripheral Interface (SPI), and an 8-bit Analog-to-Digital (A/D) converter. The M6801 
Family includes high performance in a single chip with Eraseable Programmable Read Only 
Memory (EPROM) and SCI. The rapidly expanding M6805 Family is available in a variety of memory 
and package sizes with various special Input/Output (I/O) functions. The M6805 is available in 
High-Density N-Channel Metal Oxide Silicon (HMOS), Complementary Metal Oxide Silicon (CMOS), 
and High-Density Complementary Metal Oxide Silicon (HCMOS). The M6804 Family now provides 
the 8-bit processing capabilities that compete in the 4-bit price arena. A One Time Programmable 
Read Only Memory (OTPROM) is also available in the M68HC11, M6804, and M6805 Families. 



Technology 

Motorola's first MCUs and MPUs were produced in HMOS which offered a low cost single-chip 
solution in high production volumes. CMOS was then introduced which offered very low power 
consumption and a wide power supply tolerance at performance levels similar to HMOS. The 
introduction of HCMOS offered the best of both worlds, with high-density and low power con- 
sumption. Tables 1-1 and 1-2 list Motorola's MCUs, MPUs, and peripheral product line by tech- 
nology. 



ROM Size 

The mask ROM capacities of the present single-chip MCUs range from a low of 512 bytes in the 
M6804 Family to a high of 8K in the M68HC1 1 Family. Refer to Table 1-3 through 1-7 to determine 
what ROM is offered in the MCU product line. In selecting ROM size, the ROM usage efficiency 
of the instruction set should be considered, along with the application to be programmed. 



MOTOROLA MICROPROCESSOR DATA 
1-1 



6.0 



5.0 



4.0 




[j8HC32^] 



3.0 



2.0 - 





CUSTOM 








CPU 











- I 6800 



1.0 - 



146805E2 — I 'G2, 'F2 



1468705 




-f 6805/68705 FAMILY 


1 : : { 









68HC805B6 

68HC;b5B6 

68HC05M4 

68HC05C9 

68HC05A6 

68HC705C8 

68HC05P1 




i68HC05C4~! 



J68HC705B5 
68HC705C4 



1975 1976-1978 "■ 1979 



1980 



1981 



1982 



1983 



1984 



1985 



1987 



1988 



1990 



INTRODUCTION YEAR 



Figure 1-1. Motorla MCU/MPU Evolution 



Table 1-1. MCU/MPU Technology Listing 



1 



HMOS/NMOS 


HCMOS 


CMOS 


MC6800 


MC68705P3 


MC68HC04J2 


MC68HSC05C4 


MC146805E2 


MC6801 


MC68705P5 


MC68HC04J3 


MC68HSC05C8 


MC146805F2 


MC6801U4 


MC6805R2 


MC68HC04P4 


MC68HC705B5 


MC146805G2 


MC68701 


MC6805R3 


MC68HC704P4 


MC68HC705C8 




MC68701U4 


MC68705R3 


MC68HC05A6 


MC68HC805C4 




MC6802 


MC68705R5 


MC68HC05B4 


MC68HC11A0 




MC6803 


MC6805S2 


MC68HC05B6 


MC68HC11A1 




MC6803U4 


MC6805S3 


MC68HC805B6 


MC68HC11A8 




MC6804J1 


MC68705S3 


MC68HC05C2 


MC68HC11D3 




MC6804J2 


MC6805U2 


MC68HC05C3 


MC68HC11E1 




MC6804P2 


MC6805U3 


MC68HC05C4 


MC68HC11E9 




MC68704P2 


MC68705U3 


MC68HC05C8 


MC68HC11F1 




MC6805P2 


MC68705U5 


MC68HC05C9 


MC68HC711A8 




MC6805P6 


MC6809/9E 


MC68HC05L6 


MC68HC711D3 








MC68HC05M4 


MC68HC711E9 








MC68HC05P1 


MC68HC811E2 








MC68HCL05C4 










MC68HCL05C8 







Table 1-2. Peripheral Technology Listing 



HMOS/NMOS 


HCMOS 


CMOS 


MC6810 




MC6821 


MC68HC24 


MC68HC34 


MC146818 


MC6840 




MC6844 


MC68HC99 




MC146818A 


MC6845 




MC6850 






MC146823 


MC6852 




MC6854 








MC6898 




MC68488 








MC2672 




MC2674 









Non-Mask ROM Versions 

EEPROM, EPROM, OTPROM, and/or non-ROM versions are offered in practically all single-chip 
MCUs. These versions serve for limited to high volume applications/prototype debugging, and 
field trials. EEPROM and OTPROM versions are available in the M6805 and M68HC11 Families. 
EPROM versions are available in the M6805 and M6801 Families. Refer to Table 1-3 through 1-7 
to determine what is offered in the MCU product line. 



RAM Size 

On-chip Random Access Memory (RAM) sizes range from 30 bytes in the M6804 Family to 512 
bytes in M68HC11 Family. The M6805 has versions of 64, 104, 112, and 176 bytes. Architectures 
such as the M68HC11, M6801, and M6805 Families, which permit multi-level subroutines plus 
ROM and RAM data tables, allow trade-off ROM and RAM utilization. ROM usage can be minimized 
with subroutines and look-up tables, while RAM usage can be optimizes with ROM tables and 
fewer subroutines. 



Digital Input/Output 

Single-chip MCUs are available in 52-pin quad packages as well as the smaller (and lower cost) 
20-pin packages. Five to fourteen pins serve power and control functions permitting up to 12 I/O 



MOTOROLA MICROPROCESSOR DATA 
1-3 



essentially any mix of inputs and outputs. Higher output drive current is available in the M6805 
Family. 



Expansion Bus 

The non-ROM versions include a bus to access off-chip program memory and additional I/O. The 
M6801 Family also includes a three bus structure for off-chip expansion. The three bus structure 
permits the number of bus pins to be optimized for the amount of address space needed off-chip. 
The M68HC11 Family can operate in an expanded mode and address up to 64K bytes of external 
memory. 



Interrupts 

When an application program must synchronize with two or more external events, interrupt 
hardware in some form is usually necessary. The M68HC11, M6801, and M6805 Families include 
fully automatic interrupts (registers are saved) with programmable vectors for both an external 
and internal timer. 



Timers 

Timers are the most frequently used on-chip functions. Timers may generate interrupts to a 
program at a periodic rate, measure external events, and generate measured output waveforms. 
The M68HC11, M6801, and M68HC05 devices include a 16-bit timer that may be used to perform 
three of the preceeding functions simultaneously. The M6805 and M6804 timers consist of a 
programmable 8-bit counter and selectable 7-bit prescaler. 

Special Functions 

Various members of the MCU Families include additional I/O functions. For example, the M68HC1 1 , 
M6801, and some of the M6805 Family include a SCI. The SCI is used for long-range communi- 
cations, as in data transfer from an MCU to a.terminal or modem. The M68HC1 1 Family and some 
of the M6805 Family also contain a SPI. TheSPI is used primarily for serial communication between 
chips on the same printed circuit board. Selected members of the M68HC11 and M6805 Family 
include multi-channel A/D converters. The MC6805R/S versions contain four analog input channels, 
and the M68HC1 1 MCUs features up to eight analog input channels. 

DEVELOPMENT SUPPORT 

The M68HC11, M6801, and M6804, and M6805 Families are fully supported by a series of eco- 
nomical evaluation modules (EVM). A more powerful development system is also available in the 
HDS-300. The support products are covered in more detail in Chapter 5 Evaluation Modules. 

SINGLE-CHIP SELECTOR GUIDES 

Tables 1-3 through 1-7 list the different features available for devices within a family. The tables 
provide information as to RAM, ROM, EPROM, timer, etc. Table 1-8 lists the OTPROM devices 
available. 



MOTOROLA MICROPROCESSOR DATA 
1-4 



Table 1-3. M6801 Family Selector Guide 





Definitions: 



6801 


HMOS 


40 


128 


2048 




29 


16 


64K 


Yes 


P,S 


68701 


HMOS 


40 


128 




2048 


29 


16 


64K 


Yes 


S 


6803 


HMOS 


40 


128 






13 


16 


64K 


Yes 


P,S 


6801 U4 


HMOS 


40 


192 


4096 




29 


16 


64K 


Yes 


P,S 


68701 U4 


HMOS 


40 


192 




4096 


29 


16 


64K 


Yes 


S 


6803U4 


HMOS 


40 


192. 






13 


16 


64K 


Yes 


P 



P = Plastic 
S = Cerdip 
I/O = Input/Output 

SCI = Serial Communication Interface 
RAM = Random Access Memory 
ROM = Read Only Memory 
EPROM = Eraseable Programmable ROM 



Table 1-4. M6804 Family Selector Guide 




6804P2 


HMOS 


28 


30 


1016 




20 


8 


P,FN 


68704P2 


HMOS 


28 


30 




1020 


20 


8 


S 


6804J1 


HMOS 


20 


30 


512 




12 


8 


P 


6804J2 


HMOS 


20 


30 


1000 




12 


8 


P 


68HC04P4 


HCMOS 


28 


172 


3700 




20 


8 


P 


68HC04J2 


HCMOS 


20 


30 


1000 




12 


8 


P 


68HC04J3 


HCMOS 


20 


122 


1672 




12 


8 


P 


68HC704P4 


HCMOS 


28 


172 




3700 


20 


8 


S 



Definitions: 



p = 


Plastic 


s = 


Cerdip 


FN = 


Plastic Leaded Chip Carrier 


I/O = 


Input/Output 


RAM = 


Random Access Memory 


ROM = 


Read Only Memory 


EPROM = 


Eraseable Programmable ROM 



MOTOROLA MICROPROCESSOR DATA 
1-5 



Table 1-5. M6805 Family Selector Guide 




6805P2 


HMOS 


28 


64 


1110 




20 


8 






P,S,FN 


6805P6 


HMOS 


28 


64 


1804 




20 


8 






P,S,FN 


68705P3 


HMOS 


28 


112 




1804 


20 


8 






S 


68705P5 


HMOS 


28 


112 




1804 


20 


8 






S 


6805R2 


HMOS 


40/44 


64 


2048 




32 


8 


Yes 




P,S,FN 


6805R3 


HMOS 


40/44 


112 


3776 




32 


8 


Yes 




P,S,FN 


68705R3 


HMOS 


40 


112 




3776 


32 


8 


Yes 




S 


68705R5 


HMOS 


40 


112 




3776 


32 


8 


Yes 




S 


6805S2 


HMOS 


28 


64 


1480 




21 


8 


Yes 


Yes 


P,S,FN 


6805S3 


HMOS 


28 


104 


2720 




21 


8 


Yes 


Yes 


P,S,FN 


68705S3 


HMOS 


28 


104 




3752 


21 


8 


Yes 


Yes 


S 


6805U2 


HMOS 


40/44 


64 


2048 




32 


8 






P,S,FN 


6805U3 


HMOS 


40/44 


112 


3776 




32 


8 






P,S,FN 


68705U3 


HMOS 


40 


112 




3776 


32 


8 






S 


68705U5 


HMOS 


40 


112 




3776 


32 


8 






S 



Definitions: 



p 


= Plastic 


s 


= Cerdip, 


FN 


= Plastic Leaded Chip Carrier 


I/O 


= Input/Output 


RAM 


= Random Access Memory. 


ROM 


= Read Only Memory 


EEPROM 


= Eraseable Programmable ROM 


SPI 


= Serial Peripheral Interface 


A/D 


= Analog/Digital Converter 



MOTOROLA MICROPROCESSOR DATA 
1-6 



Table 1-6. M6805 HCMOS/CMOS Family Selector Guide 




68HC05A6 


HCMOS 


40/44 


176 


4160 




2056 


32 


16 


Yes 


Yes 




P,FN 


68HC05B4 


HCMOS 


48/52 


176 


4160 






32 


16 




Yes 


Yes 


P,FN 


68HC05B6 


HCMOS 


40/52 


176 


5952 




256 


32 


16 




Yes 


Yes 


P,FN 


68HC05C2 


HCMOS 


40 


176 


2096 






32 


16 








P 


68HC05C3 


HCMOS 


40 


176 


2096 






32 


16 


Yes 


Yes 




P 


68HC05C4 


HCMOS 


40/44 


176 


4160 






32 


16 


Yes 


Yes 




P,FN 


68HC05C8 


HCMOS 


40/44 


176 


7700 






32 


16 


Yes 


Yes 




P,FN 


68HC05L6 


HCMOS 


68 


176 


6208 






32 


16 


Yes 






FN 


68HC05M4 


HCMOS 


52 


128 


4K 






32 


8/16 






Yes 


FN 


68HCL05C4 


HCMOS 


40/44 


176 


4160 






32 


16 


Yes 


Yes 




P/FN 


68HCL05C8 


HCMOS 


40/44 


176 


8K 






32 


16 


Yes 


Yes 




P,FN 


68HSC05C4 


HCMOS 


40/44 


176 


4160 






32 


16 


Yes 


Yes 




P,FN 


68HSC05C8 


HCMOS 


40/44 


176 


8K 






32 


16 


Yes 


Yes 




P,FN 


68HC705C8 


HCMOS 


40/44 


304 








32 


16 


Yes 


Yes 




P,FN 


68HC805B6 


HCMOS 


48/52 


176 




8K 


6208 


32 


16 




Yes 




P,FN 


68HC805C4 


HCMOS 


40/44 


176 






4160 


32 


16 


Yes 


Yes 




P,FN 


146805E2 


CMOS 


40 


112 


0 






16 


8 








P,S,FN 


146805F2 


CMOS 


28 


64 


1089 






20 


8 








P,S,FN 


146805G2 


CMOS 


40 


112 


2106 






32 


8 








P,S,FN 



Definitions: 



P = Plastic 
S = Cerdip 
FN = Plastic Leaded Chip Carrier 
I/O = Input/Output 
A/D = Analog/Digital Converter 
SCI = Serial Communications Interface 
SPI = Serial Peripheral Interface 
RAM = Random Access Memory 
ROM = Read Only Memory 
EPROM = Eraseable Programmable ROM 
EEPROM = Electrical Eraseable ROM 



MOTOROLA MICROPROCESSOR DATA 
1-7 




Table 1-7. M68HC11 Family Selector Guide 




68HC11A0 


HCMOS 


48/52 


256 






38 


16 


64K 


Yes 


Yes 


Yes 


P,FN 


68HC11A1 


HCMOS 


48/52 


256 




512 


38 


16 


64K 


Yes 


Yes 


Yes 


P,FN 


68HC11A8 


HCMOS 


48/52 


256 


8192 


512 


38 


16 


64K 


Yes 


Yes 


Yes 


P,FN 


68HC11D3 


HCMOS 


40/44 


192 


4096 




30 


16 


64K 


No 


Yes 


Yes 


P,FN 


68HC11E1 


HCMOS 


52 


512 


0 


512 


38 


16 


64K 


Yes 


Yes 


Yes 


FN 


68HC11E9 


HCMOS 


52 


512 


12K 


512 


38 


16 


64K 


Yes 


Yes 


Yes 


FN 


68HC11F1 


HCMOS 
























68HC81 1 E2 


HCMOS 


48/52 


256 




2K- 


38 


16 


64K 


Yes 


Yes 


Yes 


P.FN 



Definitions: 



P Plastic 
FN '= Plastic Leaded Chip Carrier 
I/O = Input/Output ] 
A/D = Analog/Digital Converter 
SCI = Serial Communication Interface 
SPi = Serial Peripheral Inte'rface 
RAM = Random Access Memory 
ROM = Read Only Memory 
EPROM = Eraseable Programmable ROM 
EEPROM = Electrical Eraseable ROM 



Table 1-8, One-Time Programmable ROM (OTPROM) Devices 



Device 


OTPROM 

(Bytes) 


RAM 

(Bytes) 


I/O 


Timer 
Bit 


A/D, SCI 
SPI 


COP 
Watchdog 


Pin 
Package 


68HC704P4 


3740 


124 


20 


8 






28-DIP,DW* 


68HC705B5* 


6208 


176 


24 


16 


A/D, SCI 


Yes 


52-FN,48-DIP 


68HC705C4* 1 


4160 


176 


24 


16 


SCI, SPI 


., - . Yes 


44-FN,40-DIP 


68HC705C8 


7616 


304 


24 


16 


SCI, SPI 


Yes 


44-FN,40-DIP 


68705R3 


3776 


112 


24 


8 


A/D 




40-P 


68HC711D3* 


4096 


192 


24 


16 


SCI, SPI 


■ Yes 


44-FN,40-DIP 


68HC711A8* 


8192 


256 


38 


16 


A/D, SCI, SPI 


Yes , 


52-FN 


68HC711E9* 


12K 


512 


38 


16 


A/D, SCI, SPI 


Yes 


48-DIP,52-FN 



NOTES: 

1. Use MC68HC705C8 for window emulation. 



2. Definitions: 




FN = 


Plastic Quad (PLCC) 


DW = 


Small Outline (Wide-Body SOIC) 


DIP = 


Dual-ln-Line Package 


RAM = 


Random Access Memory 


I/O = 


Input/Output 


A/D = 


Analog/Digital 


SCI = 


Serial Communications Interface 


SPI = 


Serial Peripheral Interface 


COP = 


Computer Operating Properly 


3. *Available in 


1989. 



MOTOROLA MICROPROCESSOR DATA 
1-8 



Reliability 

Volume I 




MOTOROLA MICROPROCESSOR DATA 



MICROPROCESSOR PRODUCTS GROUP 
RELIABILITY AND QUALITY ASSURANCE 
1987 ANNUAL RELIABILITY REPORT 
SUMMARY 




INTRODUCTION 

The Motorola MOS Microprocessor Reliability and Quality Monitor (R&QA) Program is designed 
to generate an ongoing data base of reliability and quality performance for various categories of 
Microprocessor products. The primary purpose of the program is to identify negative trends in 
the data so that immediate corrective action can be taken. The program also allows Motorola to 
develop a large data base of reliability and quality results that can be reported quarterly to 
customers. The following report summarizes the reliability and quality data for 1987. 

The reliability monitor tests are conducted on sample groups pulled on a quarterly basis from 
major categories of products representing a matrix of processing and packaging technologies. 
Product mix, sample availability and equipment capacity may cause the specific sample groups 
pulled for a given quarter to vary from quarter to quarter. Each sample group has a specific set 
of reliability tests associated with it that are appropriate for that product type based on our history 
for that classification. At the end of each quarter, results are reported for all sample groups that 
have completed testing. In addition at the end of each year a complete summary of the 4 quarters 
is reported. 

The quality results that are reported are the electrical and visual/mechanical (Average Outgoing 
Quality (AOQ), given in parts per million defective) for the Microprocessor Group. This data 
represents the summary of results from the QC gate operation performed on every lot during 
1987. Electrical AOQ represents any AC, DC, or functional failure at any temperature (each lot 
may be typically gated at hot, room or cold temperatures). Visual/mechanical AOQ represents 
failures such as bent leads, incorrect marking, marking permanency problems, and cracked pack- 
ages. The AOQ reported is the product the process average (ratio of defective devices to largest 
sample size) and the lot acceptance rate. 

QUALITY AND RELIABILITY SYSTEM 

A complete Reliability and Quality Assurance (R&QA) system is in place to monitor and control 
the performance of Motorola's MOS Microprocessor Components. Incoming Quality Control in- 
spects starting wafers, masks, chemicals, package piece parts, and molding compounds. Process 
Engineering and In-Process Quality Control perform step-by-step monitoring of the wafer process 
to check oxidation, diffusion, photolithography, ion implantation, polysilicon deposition, metal- 
lization, passivation, and other process operations. Final visual, class probe, and capacitance- 
voltage plots complete the wafer area inspection. Environmental monitors are also performed for 
air cleanliness, water quality, temperature, and humidity. 

In the assembly area, In-Process Quality Control performs monitors on equipment performance 
and gate inspections at the major process steps on all lots. The Outgoing Quality Control group 
continues this philosophy in the final test area by performing electrical and visual-mechanical 



MOTOROLA MICROPROCESSOR DATA 



2-1 



gates. The electrical inspection, which consists of AC, DC, and functional tests, is performed to a 
0.1% (maximum) Acceptable Quality Level (AQL) sampling plan. The visual/mechanical inspection 
is also performed to a 0.1% AQL sampling plan. Any lot which fails either of these gates is returned 
to production for 100% rescreen. An R&QA Engineering organization exists to approve final test 
programs and support the Outgoing Quality Control organization. Test programs are tailored to 
assure all required specifications are met or the devices are rejected. 

The R&QA Engineering organization is also responsible for performing qualifications of new 
designs and process changes prior to introduction. In addition, R&QA Engineering establishes 
and maintains monitor programs to assure processes stay in control once they are qualified. 
Results from these programs provide rapid feedback to correct problems as they occur. 

Supporting these efforts is the Metrology Laboratory which includes both a Standards and a 
Calibration Laboratory to provide National Bureau of Standards traceability to all production 
measurements. 

Also offering required support are a Chemical Laboratory with such equipment as a gas chro- 
matograph/mass spectrograph and X-ray fluorescent systems for detailed incoming chemical 
analyses; a Surface Analysis Laboratory whose equipment includes a Scanning Electron Micro- 
scope (SEM) and a Scanning Auger Microprobe (SAM); and a Product Analysis Laboratory for 
detailed analyses of failure modes and mechanisms for Microprocessor devices. 



PACKAGING SYSTEM 

Motorola Microprocessor devices are produced in plastic, CERDIP, PGA, and sidebraze packages. 
The ceramic package types are hermetically sealed to protect the integrated circuit from environ- 
mental factors and permit operation over extreme temperature ranges. Although plastic devices 
are not hermetic, modern epoxies exhibit extremely high moisture resistance, and long lifetimes 
may therefore be expected from these devices in typical environments. 

In recent years, plastic encapsulated devices have gained widespread acceptance throughout the 
electronics industry. Improvements in materials and process controls have resulted in significant 
improvements in reliability performance. In addition, plastic packages have the advantage of low 
cost and physical strength. 

Encapsulated integrated circuits incorporate the simpliest processing and package construction 
of the various systems available. The die is attached to a leadframe, wire bonded and encapsulated 
using an epoxy novolac molding compound. The die may be attached to the leadframe by epoxy 
or by any of a variety of eutectic forming metal preforms. Wire bonding in plastic may be ther- 
mocompression or. thermosonic, but the wire is always gold. The encapsulant is the most critical 
component of the system since it controls contamination, moisture resistance, and stress effects. 
Epoxy novolacs have become the industry standard molding compound since they combine 
excellent characteristics in all these areas. 

The plastic package is, by far, the most resistant to physical damage since the die is completely 
encapsulated and cavity hermeticity is not a concern. Since the package is light in weight and the 
plastic is less brittle than ceramic, chipping and cosmetic damage are not problems. The leadframe 
and plating are equivalent to CERDIP. 

In comparing plastic to ceramic packages, there are two characteristics to be considered: moisture 
resistance and thermal characteristics. Microprocessor plastic products perform very well on 



MOTOROLA MICROPROCESSOR DATA 



moisture resistance related tests. This is due to advances in molding compounds, the characteristic 
low voltages and the moderate power dissipation of Microprocessor products. In most instances 
plastic devices will provide excellent performance, essentially equivalent to hermetic performance. 
Thermal resistance has been improved dramatically through the introduction of copper lead- 
frames, and this results in lower junction temperatures, and subsequent improvements in electrical 
characteristics and reliability performance^ 

Many users of integrated circuits continue to have requirements or preferences for hermetically 
sealed ceramic packages. These requirements are usually based on applications in a highly humid 
environment, increased temperature range or high power dissipation. Motorola produces two 
different types of ceramic packaged devices: CERDIP and sidebraze. 

The sidebraze, or solder seal, package is composed of three layers of alumina which are screened 
with refractory metal such as tungsten or moly manganese and fired together to form the package 
body with a cavity for the die. The refractory metal is then plated and Alloy 42 leadframes are 
brazed to the bottom, sides or top of the package, depending on the vendor. The advantage of 
the sidebraze version is accurate lead alignment without the need for forming. The final piece 
part operation is plating, which may be gold or tin with a selective gold plate in the cavity. Although 
epoxy die bonding is feasible in this package — due to the higher sealing temperature, most 
manufacturers, including Motorola, employ a eutectic bond. Both aluminum ultrasonic wire bond- 
ing and gold thermocompression bonding are used in this package. 

The cerdip package is composed of two ceramic piece parts: the base and the cap. Sandwiched 
between these two layers is a leadframe composed of Alloy 42 imbeded in a sealing glass, the 
leadframe requires a forming operation similar to a plastic dip. The die is mounted in this package 
using a eutectic bond while the wire bonds are aluminum (ultrasonic). A tin plate is applied to 
the exterior leads of the package. 

Some tradeoffs exist in the performance characteristics of the two hermetic packages as they are 
offered by Motorola. Both typically are ceramic, hermetic, employ a eutectic die bond, use ultra- 
sonic aluminum wire bonding, and have tin plating on the exterior leads. The thermal resistance 
of the packages is very similar, with the sidebraze having a slight advantage. Both packages 
perform well oh the standard thermal and mechanical environmental tests, but each is susceptible 
to handling damage. Loose shipping rail packaging or high velocity impacts during testing can 
chip the sidebraze package and sever the interlayer metallization. This type of handling will not 
effect the 10 mil thick leadframe of the CERDIP package, but hermeticity failures can occur. The 
CERDIP package is slightly thicker and heavier, but no conductive surfaces are exposed so the 
shorting potential in dense packaging is reduced. Extensive testing of 24, 28, and 40 lead CERDIP 
and sidebraze devices has indicated no significant differences in reliability. 



RELIABILITY TEST 

The following paragraphs describe the various reliability test included in Motorola's Reliability 
and Quality Assurance Program. 



High Temperature Operating Life Test 

High temperature operating life (HTOL) testing is performed to accelerate failure mechanisms 
which are thermally activated through the application of extreme temperatures and the use of 
dynamic operating conditions. The temperature and voltage conditions used in the stress are 
typically 125°C with the bias level at the maximum data sheet specification limit of 5.5 volts. All 



MOTOROLA MICROPROCESSOR DATA 
2-3 



devices used in the HTOL test are sampled directly after final electrical test with no prior burn-in 
or other special screening. Testing is performed with dynamic signals applied to the device for 
a minimum test duration of 1008 hours. 

Device equivalent hours assume the Arrhenius relationship using an activation energy of 0.7 eV 
to extrapolate from the device junction temperature at 1 25°C (ambient) to the junction temperature 
at 70°C (ambient). Failure rates given in Failure in Time (FIT) are derived using the Chi-Square 
distribution to a 90% confidence limit. A FIT is one failure per billion device hours of 0.0001%/ 
1000 hours. , 

Tables 2-1 through 2-3 show the results for the high temperature operating life test for packaging; 
plastic, plastic leaded chip carrier (PLCC), and ceramic. Each of these tables also lists the different 
technology used in the test. Table 2-4 lists the grand totals of Table 2-1 through 2-3 by technology 
and packaging. Figure 2-1 shows a trend chart of the high temperature operating life by technology, 
and Figure 2-2 is a trend chart of the total of the high temperature operating life test. 



Table 2-1. High Temperature Operating Life Test 
PLASTIC 

STRESS VOLTAGE: 5.5 Volts 
TEMPERATURE: 125°C 
LONGEST STRESS: 1008 Hours 



Device 
Type 


Test 
Devices 


125X 
Device Hrs. 


70°C Equiv. 
Device Hrs. 1 


Failures 


FITS 2 
0.7 eV 


NMOS DIP 












MC3870 


45 


45,400 


6.49 x10 5 


1 


5970 


MC6800 


135 


136,000 


1.42 x10 s 


0 


1606 


MC6802 


378 


380,000 


5.41 x10 6 


0 


421 


MCM6810 


45 


45,400 


4.13 x TO 5 


0 


5521 


MC6840 


135 


136,000 


1.37 x10 s 


0 


1664 


MC6844 


45 


45,400 


5.00 x10 5 


0 


4561 


MC6845 


45 


45,400 


4.09 x TO 5 


0 


5575 


MC6846 


45 


45,400 


4.57 x10 5 


.0 


4990 


MC6850 


135 


136,000 


1.63 x10 s 


0 


1399 


MC6852 


45 


45,400 


7.22 x10 s 


0 


3158 


MC6854 


45 


45,400 


. 3.87 x10 s 


0 


5892 


MC68661 


135 


136,000 


1.32 x 10 s 


0 


1727 


MC68652 


45 


45,400 


3.90 x10 s 


0 


5847 


MC68901 


45 


45,400 


8.10x10 s 


0 


2815 


CUSTOM A 


945 


951,000 


2.11 x10 7 


2 


252 


CUSTOM B 


525 


530,000 


7.54 x10 s 


0 


302 


CUSTOM C 


1834 


1,820,000 


3.76 x10 7 


1 


103 


TOTAL 


4627 


4,633,600 


8.21 x10 7 


4 


97 


CMOS DIP 












MC146805E2 


45 


43,000 


1.08x10 s 


0 


2111 


MC146805F2 


225 


224,000 


5.71 x10 6 


,1 


679 


MC146805G2 


89 


74,200 


1.88x10 s 


0 


1213 


MC146818 


45 


45,400 


1.17x10 s 


0 


1949 


MC146818A 


90 


90,800 


2.34 x10 s 


0 


974 


MC146823 


340 


342,000 


8.82 x10 s 


0 


259 


TOTAL 


834 


819,400 


2.10X10 7 


1 


185 



1) Activation energy used in equivalent device hour calculation is 0.7 ev) 

2) 90% confidence. . 



MOTOROLA MICROPROCESSOR DATA 



Table 2-1. High Temperature Operating Life Test 
PLASTIC (Continued) 



STRESS VOLTAGE: 5.5 Volts 
TEMPERATURE: 125°C 
LONGEST STRESS: 1008 Hours 



Device 
Type 


Test 
Devices 


125T 
Device Hrs. 


70°C Equiv. 
Device Hrs. 1 


Failures 


FITS 2 
0.7 eV 


HMOS DIP 












MC2674 


45 


45,000 , 


6.30 x 10 b 


0 


3619 


MC2681 


90 


90,800 


1.25x 10 6 


0 


1824 


MC6801 


135 


136,000 


1.42 x 10 6 


0 


1606 


MC6801 U4 


412 


364,000 


5.09 x 10 6 


o 


448 


MC6803U4 


45 


43,400 


5.95 X10 5 


0 


3832 


MC6804J2 


167 


163,000 


3.16X10 6 


0 


722 




90 


fifl finfl 

OO/OVU 


1 .82 x 10 s 


o 


1253 




180 




2.67 x 10 s 


o 


854 




43 


41 700 


K 1 ? y 1 

D. 1 o A 1U 


1 


6321 


MC6805R2 


45 


41*200 


4.36 x10 5 


0 


5320 


MC6805R3 


180 


182,000 


1.92 x10 6 


0 


1188 




/IK 


AC Af\(\ 


7 Oft v 1 ft5 
/.ZU X I u 


u 


3167 


MC6805S3 


45 


43,900 


6.99 x10 5 


1 


5543 


MC6805T2 


135 


122,000 


1.79 x10 s 


1 


2165 


MC6809 


90 


90,800 


1.37x10 s 


1 


2828 


MC6809E 


135 


136,000 


2.06 x10 s 


0 


1107 


MC68000 


504 


468,000 


7.28 x10 s 


0 


313 


MC68008 


45 


45,400 


5.38 x10 5 


0 


4238 


MC68010 


45 


45,400 


6.50 x10 s 


0 


3508 


MC68230 


45 


45,400 


8.90 x10 s 


0 


2562 


MC68681 


43 


41,000 


6.50 x10 s 


0 


3508 


TOTAL 


2669 


2,567,200 


3.78 X10 7 


4 


211 


HCMOS DIP 












MC68HC05C4 


410 


389,000 


9.94x10 6 


1 


390 


MC68HC05C8 


89 


89,800 


2.29 x10 s 


0 


996 


XC68HC000 


134 


134,000 


3.20 x10 s 


1 


1211 


TOTAL 


633 


612,800 


1.55 x10 7 


2 


343 


PLASTIC DIP 


8763 


8,633,200 


1,56x10 s 


11 


106 



1) Activation energy used in equivalent device hour calculation is 0.7 ev> 

2) 90% confidence. 



MOTOROLA MICROPROCESSOR DATA 



Table 2-2. High Temperature Operating Life Test 
PLCC 



STRESS VOLTAGE: 5.5 Volts 
TEMPERATURE: 125°C 
LONGEST STRESS: 1008 Hours 



uevice 


_ 


125°C 


_ ft0 - _ 

70 C ECfUlV. 


Failures 


EITC2 


lype 


_ 

D6VICGS 


Dovi'cg Hrs. 


Device Hrs. 




0.7 eV 


HMOS PLCC 












MC6805R2 


89 


81,900 


8.34 x10 5 


0 


2734 


MC6805R3 


450 


430,000 


4.38 x10 6 


0 


512 




ZOU 




t 1 a v 1 n6 

Ot I H A I U 


0 
U 


AAA 


CUSTOM E 


1189 


1,200,000 


2.20 x10 7 


0 


104 


TOTAL 


2008 


1,990,900 


3.24 x10 7 


0 


70 


HCMOS PLCC 












MC68HC11 


2155 


2,160,000 


5.66 x10 7 


14 


356 


CUSTOM E 


. 416 


417,000 


7.56 x10 6 


1 


513 


CUSTOM G 


1358 


1,360,000 


2.46 x10 7 


2 


216 


TOTAL 


3929 


3,937,000 


8.87 x10 7 


17 


266 


CMOS PLCC 












MC146805F2 


45 


45,400 


1.17X10 6 


0 


1949 


MC146805G2 


90 


89,000 


2.26X10 6 


0 


1009 


MC146818 


45 


45,400 


1.17X10 6 


0 


1949 


MC146818A 


89 


88,900 


2.26 x10 6 


0 


1009 


TOTAL 


269 


268,700 


6.83 x10 6 


0 


334 


PLCC 


6206 


6,196,600 


1.28 x10 s 


17 


184 



1) Activation energy used in equivalent device hour calculation is 0.7 eV. 

2) 90% confidence. 



Table 2-3. High Temperature Operating Life Test 
CERAMIC 



STRESS VOLTAGE: 5.5 Volts 
TEMPERATURE: 125°C 
LONGEST STRESS: 1008 Hours 



Device 
Type 


Test 
Devices 


125°C 
Device Hrs. 


70°C Equiv. 
Device Hrs. 1 


Failures 


FITS 2 
0.7 eV 


NMOS 












MC6821L 


44 


44,300 


6.02 x10 s 


0 


3788 


MC6821S 


45 


45,400 


6.18x10 5 


0 


3690 


MC6844S 


135 


136,000 


1.96x10 6 


0 


1163 


MC6850 


90 


90,800 


1.39x10 6 


0 


1640 


MC6850S 


45 


45,400 


6.95 x10 5 


0 


3281 


MC6852S 


45 


44,000 


7.96 x10 s 


0 


2865 


TOTAL 


404 


405,900 


6.06 x10 6 


0 


376 


HCMOS 












MC68020R 


542 


541,000 


9.59 x10 s 


2 


554 


MC68605R 


77 


77,000 


1.80 x10 s 


0 


1267 


MC68824R 


135 


136,000 


3.00 x10 s 


0 


760 


MC68851R 


144 


145,000 


3.19x10 s 


1 


1215 


MC68882R 


604 


597,000 


1.40X10 7 


2 


379 


TOTAL 


230 


230,000 


5.30 x10 s 


0 


430 


1732 


1,726,000 


3.69 X10 7 


5 


251 



1) Activation energy used in equivalent device hour calculation is 0.7 eV. 

2) 90% confidence. 



MOTOROLA MICROPROCESSOR DATA 



Table 2-3. High Temperature Operating Life Test 
CERAMIC (Continued) 



STRESS VOLTAGE: 5.5 Volts 
TEMPERATURE: 125°C 
LONGEST STRESS: 1008 Hours 



Device 
Type 


Test 
Devices 


125°C 
Device Hrs. 


70°C Equiv. 
Device Hrs.'' 


Failures 


FITS 2 

0.7 eV 


CMOS 












MC1468705F2 


45 


34,400 


8.57 x10 6 


0 


2661 


MC1468705F2S 


90 


908,000 


2.28 x10 6 


0 


1000 


TOTAL 


135 


942,000 


3.14 x10 s 


0 


726 


HMOS 












MLooOoL 


45 


45,400 


6.40 x 1 0 5 


0 


3563 


MC6809EL 


45 


45,400 


7.07 x10 5 


0 


3225 


MC6809ES 


45 


45,400 


6.25 x10 5 


,0 


3648 


MC6809S 


90 


90,800 


1.25X10 6 


1 


3100 


MC68701S 


45 


45,400 


4.74 x10 5 


0 


4811 


MC68701U4L 


45 


45,400 


6.22 x10 5 


0 


3666 


XC68704P2S 


300 


301,000 


6.62 x10 6 


1 


585 


MC68705P3 


45 


45,400 


7.00 x10 5 


0 


3258 


MC68705S3 


45 


45,400 


4.78 x10 5 


0 


4770 


MC68000L 


170 


171,000 


2.53 x10 6 


0 


901 


MC68000R 


248 


245,000 


3.93 x10 6 


0 


580 


MC68010L 


94 


94,000 


1.52 x10 6 


0 


1500 


MC68010R 


45 


45,400 


7.30 x10 5 


0 


3124 


MC68230L 


90 


90,800 


1.74x10 6 


1 


2227 


TOTAL 


1352 


1,355,800 


2.28 x10 7 


3 


293 


CERAMIC 


3623 


4,433,700 


6.89 x10 7 


8 


189 



B 



1) Activation energy used in equivalent device hour calculation is 0.7 eV. 

2) 90% confidence. 



Table 2-4. High Temperature Operating Life Test 
TECHNOLOGY and PACKAGING 



STRESS VOLTAGE: 5.5 Volts 
TEMPERATURE: 125°C 
LONGEST STRESS: 1008 Hours 



Device 
Type 


Test 
Devices 


125°C 
: Device Hrs. 


70°C Equiv. . 
Device Hrs. 1 


Failures 


FITS 2 
0.7 eV 


NMOS 


5,031 


5,039,500 


8.82 x10 7 


4 


91 


HMOS 


6,029 


5,913,900 


9.30 x10 7 


7 


127 


CMOS 


1,238 


2,030,100 


3.10X10 7 


1 


125 


HCMOS 


: 6,294 


6,275,000 


1.41 X10 8 


24 


224 


DIP 


( 8,763) 


( 8,633,000) 


1.56x10 s 


11 


106 


PLCC 


( 6,206) 


( 6,196,600 ) " " 


1.28x10 s 


17 


184 


PLASTIC 


([14,969]) 


([14,829,800]) 


2.84 x10 s 


28 


127 


CERAMIC 


[ 3,623] 


[ 4,433,700] 


6.89 x10 s 


8 


189 


GRAND TOTAL 


18,592 


19,259,300 


3.53 x10 s 


36 


117 



1) Activation energy used in equivalent device hour calculation is 0.7 eV. 

2) 90% confidence. 



MOTOROLA MICROPROCESSOR DATA 
2-7 



1000 




YR 1985 YR 1986 YR 1987 

YEAR 



FAILURE 

RATE 
IN FITS 




CMOS 
■O HCMOS 



YR 1985 



YR 1986 
YEAR 



YR 1987 



Figure 2-1. High Temperature Operating Life Trend Chart 
(By Technology) 



MOTOROLA MICROPROCESSOR DATA 
2-8 



TOTALS 1985-1987 



FAILURE 

RATE 
IN FITS 



1000 
900 
800 
700 
600 
500 
400 
300 
200 
100 
0 




YR 1985 



YR 1986 
YEAR 



YR 1987 



Figure 2-2. High Temperature Operating Life Trend Chart 
(Total) 



Temperature Humidity Bias Test 

Temperature humidity bias (THB) is an environmental test performed at a temperature of 85°C 
and a relative humidity of 85%. The test is designed to measure the moisture reistance of plastic 
encapsulated circuits. A nominal voltage of 5 volts static bias is applied to the device to create 
the electrolytic cells necessary to accelerate corrosion of the metallization. Testing is performed 
to JEDEC Standard 22, Method A101. Most groups are tested to 1008 hours with some groups 
extended beyond to look for longer term effects. 

Table 2-5 shows the results of the temperature humidity bias test. Table 2-6 lists the grand total 
of the devices tested in Table 2-5. Figure 2-3 shows the trend chart for the temperature humidity 
bias test. 



MOTOROLA MICROPROCESSOR DATA 



Table 2-5. Temperature Humidity Bias Test 



TEMPERATURE: 85°C 
HUMIDITY: 85% 
LONGEST STRESS 



1008 Hours 



a 



Device 






— Failures Per Sample — 












Type 






1008 Hrs 




168 Hrs 


504 Hrs 


% Failures 


MMOQ DIP 






■ 










0/68 


0/68 


0/68 


0.00 


MC6802 




0/34 


1/34 


0/33 


2.94 


MC6840 




0/68 


0/68 


0/68 


0.00 


MC6845 




0/34 


0/34 


0/34 


0.00 






0/34 


0/34 


0/34 


0.00 






0/34 


0/34 


0/34 


0.00 




TOTAL 


0/272 


1/272 


0/271 


0.37 


HMOS DIP 












MC6801 




0/68 


0/67 


0/66 


0.00 


MC6802 




0/34 


0/34 


0/34 


0.00 


MC6803U4 




0/34 


0/34 


0/34 


0.00 


MC6804J2 




0/222 


0/222 


0/222 


0.00 






0/34 


0/34 


0/34 


n fin 
u.uu 


MC6805P4 




0/34 


2/34 


0/32 


5.88 


MC6805P3 




0/68 


0/67 


0/67 


0.00 


MC6805T2 




0/68 


0/65 


0/65 


0.00 


MC6809 




0/34 


0/34 


0/34 


0.00 


MC6809E 




0/102 


0/102 


0/102 


0.00 


MC68000 




0/136 


0/134 


0/134 


0.00 


MC68008 




0/94 


0/94 


1/93 


1.08 


MC68010 




0/34 


0/34 


0/29 


0.00 




TOTAL 


0/962 






0.32 


HMOS PLCC 












MC68000 




0/45 


0.45 


0/45 


0.00 


MC68705R3 




0/254 


0.254 


0/254 


0.00 




TOTAL 


0/299 


0/299 


0/299 


0.00 


CMOS DIP 












MC146804E2 




0/68 


0/68 


0/68 


0.00 


MC146805F2 




0/34 


0/34 ' 


0/34 


0.00 


MC146805G2 




0/68 


0/68. 


0/68 


0.00 


MC146818A 




0/34 


0/34 


0/34 


0.00 


MC1 46823 




0/34 


0/34 


0/34 


0.00 




TOTAL 


0/238 


0/238 


0/238 


0.00 


HCMOS DIP 












MC68HC05C4 




0/102 


0/102 


0/102 


0.00 




TOTAL 


0/102 


0/102 


0/102 


0.00 


HCMOS PLCC 












XC68HC11A8 




0/231 


. 0/231 


0/231 


0.00 


MC68HC1 1 




0/615 


0/615 


0/615 


0.00 


MC68HC000 




0/135 


0/135 


0/135 


0.00 


MC68605 




0/231 


1/231 


0/230 


0.43 




TOTAL 


0/1212 


1/1212 


0/1211 


0.083 



MOTOROLA MICROPROCESSOR DATA 
2-10 



Table 2-6. Temperature Humidity Bias Test 
GRAND TOTAL 



TEMPERATURE: 85°C 

HUMIDITY: 85% 

LONGEST STRESS: 1008 Hours 



Device Type 


— Failures Per Sample — 










168 Hrs 


504 Hrs 


1008 Hrs 


% Failures ■., 


NMOS 


0/272 


1/272 


0/272 


0.37 


HMOS 


0/1261 


2/1254 


1/1245 


0.24 


HCMOS 


0/1314 


1/1314 


0/1313 


0.08 


CMOS 


0/238 


0/238 


0/238 


0.00 


DIP 


0/1574 


3/1567 


1/1558 


0.26 


PLCC 


0/1511 


1/1511 


0/1510 


0.07 


GRAND TOTAL 


0/3085 


4/3078 


1/3068 


0.163 



0.9 
0.8 
0.7 

CUM % 0 6 
FAILURE 0.5 




0.1 ~ — : : — 

0 -I i — I 7- : — ' 

YR 1985 YR 1986 YR 1987 

YEAR 

Figure 2-3. Temperature Humidity Bias Trend Chart 



Autoclave Test 

Autoclave, like THB, is an environmental test which measures device resistance to moisture 
penetration along the leadframe-plastic interface. Conditions employed during the test include 
121°C, 100% relative humidity, and 15 psig. Corrosion of the die is the expected failure mechanism. 
Autoclave is a highly accelerated and destructive test performed per JEDEC Standard 22, Method 
A1 02. Testing is routinely performed for 144 hours. 

Table 2-7 lists the results of the autoclave test. Table 2-8 lists the grand total of the devices tested 
in Table 2-7. Figure 2-4 shows the trend chart for the autoclave test. 



MOTOROLA MICROPROCESSOR DATA 
2-11 



Table 2-7. Autoclave Test 



TEMPERATURE: 121°C 
PRESSURE: 15 psig 
LONGEST STRESS: 144 Hours 



Device Type 


— Failures Per Sample — 


48Hrs 


96 Hrs 


144 Hrs 


% Failures 


NMOS DIP 












MC6800 




0/44 


0/44 


0/44 


0.00 


MC6802 




0/22 


0/22 


0/22 


0.00 


MC6840 




0/44 


0/44 


0/44 


0.00 


MC6845 




0/22 


0/22 


0/22 


0.00 


MC6846 




0/22 


0/22 


0/22 


0.00 


MC6850 




0/65 


0/65 


0/65 


0.00 


MC6852 




0/22 


0/22 


0/22 


0.00 


MC6854 




0/44 


0/44 


0/44 


0.00 


MC68661 




0/22 


0/22 


0/22 


0.00 


MC68901 




0/22 


0/22 


0/22 


0.00 


CUSTOM A 




0/330 


0/327 


0/326 


0.00 


CUSTOM B 




0/462 


0/462 


0/462 


0.00 


CUSTOM C 




0/847 


2/846 


0/843 


0.24 




TOTAL 


0/1968 


2/1964 


0/1960 


0.10 


HCMOS DIP 












MC68HC21 




0/22 


0/22 


0/22 


0.00 


MC68HC05C4 




0/114 


0/114 


0/114 


0.00 




TOTAL 


0/136 


0/136 


0/136 


0.00 


UVlUa Ulr 












IVIL l4bo(Jbrz 




0/65 


0/65 


0/65 


0.00 






0/44 ,-. 


0/44 


0/44 


0.00 


IVH,14doio 




0/192 


0/192 


0/192 


0.00 


IVIt.l4boloA 




0/394 


0/394 


0/394 


0.00 


MC146805E2 




0/22 


0/22 


0/22 


0.00 


MC146805F2 




0/43 


0/43 


0/43 


0.00 


ML/14boUDU^ 




0/66 


0/66 


0/66 


0.00 


lvlt/14bo 1 io 




0/534 


0/534 


0/534 


0.00 


IVIL14bo/Ubrz 




0/34 


0/34 


0/34 


0.00 




TOTAL 


0/1394 


0/1394 


0/1394 


0.00 


HMOS DIP 












MC2674 




0/22 


0/22 


0/22 


0.00 


MC6801 




0/297 


0/297 


0/297 


0.00 


MPRSfll I Id 
IVIl^OOU 1 U4 




1/777 


0/776 


1/776 


0.13 


MC6802 




0/22 


0/22 


0/22 


o!oo 


MC6803U4 




0/44 


0/44 


0/44 


0.00 


MC6804J2 




0/354 


0/354 


0/354 


0.00 


MC6804P2 




0/66 


0/66 


0/66 


0.00 


MC6805P2 




0/44 


1/44 


0/43 


2.32 


MC6805R2 




0/34 


0/34 


0/34 


0.00 


MC6805R3 




0/98 


0/98 ' 


0/98 


0.00 


MC6805S2 




0/44 


0/44 


0/44 


0.00 


MC6805S3 




0/22 


. .. 0/22 


0/22 


0.00 


MC6805T2 




0/66 


0/66 


0/66 


0.00 


MC6809 




0/44 


0/43 


0/43 


0.00 


MC6809E 




0/44 


.0/44 


0/44 


0.00 


MC68000 




0/110 


0/110 


0/110 


0.00 


MC68008 




0/22 


0/22 


0/22 


0.00 


MC68010 




0/22 


0/22 


0/22 


0.00 


MC68230 




0/22 


0/22 


0/22 


0.00 


MC68661 




0/44 


0/44 


0/44 


0.00 


MC68681 




0/65 


0/64 


0/64 


0.00 




TOTAL 


1/2263 


1/2260 


1/2259 


0.13 



MOTOROLA MICROPROCESSOR DATA 
2-12 



Table 2-7. Autoclave Test (Continued) 



TEMPERATURE: 121°C 
PRESSURE: 15 psig 
LONGEST STRESS: 144 Hours 



Device Type 


— Failures Per Sample — 


48 Hrs 


96 Hrs 


144 Hrs 


/o Failures 


HMOS PLCC 










MC6805R2 


0/1 70 


U/ 1 /u 


VI I iv 


u.uu 


MC68705R3 






... u/^op 


u.uu 


CUSTOM D 






vlHO£ 


u.uu 


CUSTOM E 


1/693 


0/692 


0/691 


0.14 


TOTAL 


1/1552 


0/1550 


0/1548 


0.06 


HCMOSPLCC 










MC68HC1 1 


1/1150 


0/1148 


2/1146 


0.26 


MC68HC11A8 


0/320 


0/320 


0/320 


0.00 


MC68HC000 


0/135 


0/135 


0/135 


0.00 


MC68605 


0/45 


0/45 


0/44 


0.00 


CUSTOM E 


1/363 


1/361 : 


0/359 


0.55 


CUSTOM G 


0/770 


0/770 


0/770 


0.00 


TOTAL 


2/2783 


1/2779 


2/2775 


0.18 


CMOS PLCC 










MC146805F2 


0/102 


0/102 


0/102 


0.00 


MC146805G2 


0/68 


0/68 


0/68 


0.00 


MC146818 


0/102 


0/101 


0/101 '• 


0.00 


MC146818A 


0/33 


0/33 


0/33 


0.00 


TOTAL 


0/305 


0/304 


0/304 


0.00 



Table 2-8. Autoclave Test 
GRAND TOTAL 



TEMPERATURE: 121°C 
PRESSURE: 15 psig 
LONGEST STRESS: 144 Hours 



Device Type 


— Failures Per Sample — 




96 Hrs 






48 Hrs 


144 Hrs 


% Failures 


NMOS 


0/1968 


2/1963 


0/1959 


0.10 


HMOS 


2/3815 


1/3810 


1/3807 


0.10 


HCMOS 


2/2919 


1/2915 


2/2909 


0.17 


CMOS 


0/1699 


0/1698 


0/1698 


0.00 


DIP 


1/5761 


3/5753 


1/5748 


0.09 


PLCC 


3/4640 


1/4633 


2/4625 


0.13 


GRAND TOTAL 


4/10401 


4/10386 


3/10373 


0.106 



MOTOROLA MICROPROCESSOR DATA 
2-13 




Temperature Cycle Test 

Temperature cycle testing accelerates the effects of thermal expansion mismatch among the 
different components within a specific packaging system. During temperature cycle testing, de- 
vices are inserted into a cycling system and held at the cold (-65°C) dwell temperature for at 
least ten minutes. Following this cold dwell, the devices are heated to the hot ( + 105X) dwell 
where they remain for another ten minute minimum time period. The system employs a circulating 
air environment to assure rapid stabilization at the specified temperature. The dwell at each 
extreme, plus the two transition times of five minutes each (one up to the hot dwell temperature, 
another down to the cold dwell temperature), constitutes one cycle. Test duration is for 1000 
cycles with some tests extended to look for longer term effects. 

Table 2-9 lists the test results of the temperature cycle test testing at a temperature range of a 
-65°C to 150°C. Table 2-10 lists the grand total of the devices tested in Table 2-9. Table 2-11 lists 
the test results of the temperature cycle test testing at a temperature range of a -50°C to 150°C. 
Table 2-12 lists the grand total of the devices and results of Table 2-11. Figure 2-5 shows the trend 
chart for the temperature cycle test. 



MOTOROLA MICROPROCESSOR DATA 
2-14 



Table 2-9. Temperature Cycle Test 



TEMPERATURE: - 65°C to + 1 50°C 
STRESS METHOD: Air to Air 
LONGEST STRESS: 1000 Cycles 



Device Type 


— Failures Per Sample — 


IvU OyO 


500 eye 


IK eye 


% Fdilurcs 


NMOS DIP 












MC3870 




0/38 


0/38 


0/38 


0.00 


MC6800 




0/114 


0/114 


0/114 


0.00 


MCM6810 




0/38 


0/37 


0/37 


0.00 


MC6840 




0/1 14 


0/114 


0/114 


0.00 


MC6844 




0/38 


0/38 


0/38 


o!oo 


MC6845 




0/38 


0/38 


1/38 


2.63 


MC6846 




0/38 


0/38 


0/38 


0 00 


MC6850 




0/1 14 


0/1 14 


1/1 14 


0 88 






0/76 


0/76 


0/76 


nnn 
u.uu 


MC6854 




0/38 


0/38 


0/38 


0.00 


MC68661 




0/38 


0/38 


0/38 


0.00 


CUSTOM A 




0/307 


0/307 


0/307 


0.00 


CUSTOM B 




0/115 


0/115 


0/115 


0.00 


CUSTOM C 




0/1306 


0/1 306 


3/1306 


0.23 




TOTAL 


0/2412 


0/2411 


5/2411 


0.21 


NMOS CERAMIC 












MC6821S 




0/38 


0/38 


0/38 


0.00 ■ ■ 


MC6821L 




0/38 


0/38 


0/38 


0.00 


MC6844S 




0/1 1 4 


0/1 14 


0/114 


0.00 


MC6850 




0/1 14 


0/1 14 


0/1 14 


0.00 : . 




TOTAL 


0/304 


0/304 


0/304 


0.00 


HMOS PLCC 












MC6805R2 




0/152 


3/152 


4/149 


4.61 


MC6805R3 




0/38 


0/38 


0/38 


0.00 


CUSTOM E 




0/153 


1/153 


0/152 


0.65 




TOTAL 






4/ooy 




HMOS DIP 












MC2674 




0/37 


0/37 


0/37 


0.00 


MC6801 




0/546 


1/546 


2/542 


0.55 


MC6801U4 




0/668 


0/653 


0/638 


0.00 


MC6802 




0/38 


0/38 


0/38 


0.00 


MC6803U4 




0/114 


0/114 


0/114 


0.00 


MC6804J2 




0/76 


0/76 


0/76 


0.00 


MC6804P2 




0/114 


0/114 


0/1 14 


0.00 


MC6805P2 




0/76 


0/76 


0/75 


0.00 


MC6805P4 




0/38 


0/38 


0/38 


0.00 


MC6805P6 




1/432 


2/429 


0/427 


0.69 


MC6805S2 




1/38 


0/37 


0/37 


2.63 


MC6805R2 




0/38 


0/38 


0/38 


0.00 


MC6805R3 




0/152 


0/152 


3/152 


1.97 


MC6805S2 




0/38 


0/38 


0/38 


0.00 


MC6805S3 




0/37 


0/37 


0/37 


0.00 


MC6805T2 




0/114 


0/114 


0/114 


0.00 


MC6809E 




1/114 


0/113 


0/113 


0.88 


MC6809 




0/76 


0/76 


0/76 


0.00 




TOTAL 


3/2746 


3/2726 


5/2704 


0.40 



B 



MOTOROLA MICROPROCESSOR DATA 
2-15 



Table 2-9. temperature Cycle Test (Continued) 



TE M PE R ATU RE : - 65°C to + 1 50°C 
STRESS METHOD: Air to Air 
LONGEST STRESS: 1000 Cycles 



a 



Device Type 


— Failures Per Sample — 


100 eye 


" ■ 500 eye 


IK eye 


% Failures 


HMOS CERAMIC 












MC6801L 




0/38 


0/38 


0/38 


0.00 


MC6809EL 




0/38 


0/38 


0/38 


0.00 


MC6809ES 




0/38 


0/38 


3/38 


7.89 


MC6809S 




0/76 


0/76 


2/76 


2.63 


MC68120L 




0/76 


0/76 


0/76 


0.00 


MC68701 




0/38 


0/38 


0/38 


0.00 


MC68701U4L 




0/38 


0/37 


0/37 


0.00 


MC68705P3 




0/38 


0/38 


1/38 


2.63 


MC68705S3S 




0/38 


0/38 


0/38 


0 00 


MC68000L 




0/1 13 


0/1 1 2 


fi/1 1 o 


n fin 


MC68000R 




0/38 


0/38 


0/37 


0 00 


MC68010R 




0/38 


0/38 


0/38 


0.00 


MC68230L 




0/38 


0/38 


0/38 


0.00 


MC68451L 




0/36 


0/36 


0/36 


0.00 


MC68901 L 




0/38 


0/38 


0/38 


0.00 




TOTAL 


0/719 


0/717 


6/716 


0.84 


HCMOS PLCC 












MC68HC11 




1/538 


0/537 


2/535 


0.56 


MC68881 




0/78 


0/78 


0/78 


0.00 


XC68882 




1/135 


0/134 


0/134 


0.74 


CUSTOM E 




0/253 


4/252 


5/246 


3.56 


CUSTOM G 




0/1 153 


1/1 1 53 


2/1 1 50 


0.26 




TOTAL 


2/2157 


5/2154 


9/2143 


0.74 


HCMOS DIP 












MC68HC05C4 






U/ZZo 


0/223 


0 00 


MC68HC05C8 




0/338 


0/338 


3/338 


0^89 


MC68HC21 




0/109 


0/109 


0/109 


0.00 




TOTAL 


0/670 


0/670 


3/670 


0.45 


HCMOS CERAMIC 












MC68020R 




0/77 


0/77 


0/77 


0.00 


MC68605R 




0/231 


0/231 


0/231 


0.00 


MC68824R 




0/231 


0/231 


1/230 


0.43 


MC68851R 




0/77 


0/77 


0/77 


0.00 


MC68881R 




0/74 


0/74 


0/74 


0.00 


MC68704P2 




0/135 


0/135 


0/135 


o.bo 




TOTAL 


0/825 


0/825 


1/824 


0.12 


CMOS PLCC 












MC146805F2 




0/76 


0/76 


0/76 


0.00 


MC146805G2 




0/114 


0/114 


0/113 


0.00 


MC146818 




0/38 


0/38 


0/38 


0.00 


MC146818A 




0/76 


0/76 


0/76 


0.00 




TOTAL 


0/304 


0/304 


0/303 


0.00 


CMOS DIP 

MC146805E2 

MC146805F2 

MC146805G2 

MC146818 

MC146818A 

MC1 46823 

MC1468705F2 


TOTAL 


0/38 

0/190 

0/152 

0/38 

0/76 

0/76 

0/38 


0/38 

0/189 

0/152 

0/38 

0/76 

0/76 

0/38 


0/38 

0/189 

0/1 52 

0/38 

0/76 

0/76 

0/38 


0.00 
0.00 
0.00 
0.00 
0.00 
0.00 
0.00 


0/608 


0/607 


0/607 


0.00 



MOTOROLA MICROPROCESSOR DATA 
2-16 



Table 2-10. Temperature Cycle Test 
GRAND TOTAL 



TEMPERATURE: - 65°C to + 1 50°C 
STRESS METHOD: Air to Air 
LONGEST STRESS: 1000 Cycles 



Device Type 



100 eye 



— Failures Per Sample — 



500 eye 



1Kcyc 



% Failures 



NMOS 

HMOS 

CMOS 

HCMOS 

PLCC 

DIP 

PLASTIC 
CERMAIC 



0/2716 

3/3808 

0/912 

2/3652 

2/2804 

3/6436 

5/9240 

0/1848 



0/2715 
7/3786 
0/911 
5/3649 
9/2801 
3/6414 
12/9215 
0/1846 



5/2715 
15/3759 

0/910 
10/3637 
13/2785 
10/6392 
23/9177 

7/1844 



0.18 
0.67 
0.00 
0.47 
0.86 
0.25 
0.44 
0.38 



GRAND TOTAL 



5/11088 



12/11061 



30/11021 



0.43 



Table 2-11. Temperature Cycle Test 



TEMPERATURE: - 50°C to + 1 50°C 
STRESS METHOD: Air to Air 
LONGEST STRESS: 1000 Cycles 









— Failures Per Sample — 




Device TvDe 






















100 eye 


500 eye 


1Kcyc 


% Failures 


NMOS DIP 












MC68661 




0/114 


0/114 


0/114 


0.00 


MC68901 




0/38 


0/38 


0/38 


0.00 




TOTAL 


0/152 


0/152 


0/152 


0.00 


HMOS DIP 












MC6801 




0/231 


0/231 


0/231 


0.00 


MC6801U4 




0/77 


0/77 


0/77 


0.00 


MC68000 




0/114 


0/114 


0/107 


0.00 


MC68008 




0/38 


0/38 


1/38 


2.63 


MC68230 




0/38 


0/38 


1/38 


2.63 


MC68681 




0/112 


0/111 


0/111 


0.00 




TOTAL 


0/610 


0/609 


2/602 


0.33 


HMOS PLCC 












MC68HC11 




0/384 


0/384 


0/384 


0.00 


MC68705R3 




0/107 


0/107 


0/107 


0.00 


CUSTOM G 




0/737 


1/737 


0/736 


0.14 


CUSTOM E 




0/154 


0/154 


0/154 


0.00 




TOTAL 


0/1382 


1/1382 


0/1381 


0.07 


HMOS PLCC 










— — — ■ 


MC68HC11A8 




0/80 


0/80 


0/80 


0.00 


MC68881 




1/76 


0/75 


0/75 


1.32 


CUSTOM E 




2/198 


2/195 


1/191 


2.53 


CUSTOM G 




0/308 


0/308 


0/308 


0.00 




TOTAL 


3/662 


2/658 


1/654 


0.92 



MOTOROLA MICROPROCESSOR DATA 
2-17 



Table 2-12. Temperature Cycle Test 
GRAND TOTAL 



TEMPERATURE: - 50°C to + 1 50°C 
STRESS METHOD: Air to Air 
LONGEST STRESS: 1000 Cycles 



Device Type 


— Failures Per Sample — 






1Kcyc 


% Failures 


100 eye 


500 eye 


NMOS 


0/152 


0/152 


0/152 


0.00 


HMOS 


0/1992 


1/1991 


2/1983 


0.15 


HCMOS 


3/662 


2/658 


1/654 


0.92 


PLCC 


3/2044 


3/2040 


1/2035 


0.34 


DIP 


0/762 


0/761 


2/754 


0.27 


GRAND TOTAL 


3/2806 


3/2801 


3/2789 


0.32 



1 ♦ 

0.9 •- 
0.8 ■- 
0.7 •■ 

CUM % 0 6 '" 
FAILURE 0.5 - 
RATE 04 .. 

0.3 ■■ 
0.2 ■- 
0.1 ■- 

o +■ 

YR 1985 YR 1986 YR 1987 

YEAR 



Figure 2-5. Temperature Cycle Trend Chart 



Thermal Shock Test 

The objective of thermal shock testing is the same as that for temperature cycle testing — to 
emphasize differences in expansion coefficients for components of the packaging system. How- 
ever, thermalshock provides additional stress in that the device is exposed to a sudden change 
in temperature due to the transfer time of ten seconds maximum as well as the increased thermal 
conductivity of a liquid ambient. Devices are placed in a flourocarbon bath and cooled to -65°C. 
After being held in the cold chamber for five minutes minimum, the devices are transferred to 
an adjacent chamber filled with flourocarbon at +150°C for an equivalent time. Two five minute 
dwells plus two ten second transitions constitute one cycle. Test duration is normally for 1000 
cycles with some tests being extended to look for longer term effects. 

Table 2-13 lists the results of the thermal shock test and Table 2-14 lists the grand total of Table 
2-13. Figure 2-6 shows the trend chart for the thermal chart for the thermal shock test. 




MOTOROLA MICROPROCESSOR DATA 
2-18 



Table 2-13. Thermal Shock Test 



TEMPERATURE: - 65°C to + 1 50°C 
STRESS METHOD: Liquid to Liquid 
LONGEST STRESS: 1000 Cycles 







— Failures Per Sample — 












Device Type 










100 eye 




IK eye 


% Fdilurcs 


NMOS DIP 










MC2674 


0/34 


0/34 


0/34 


0.00 


MC3870 


0/135 


2/135 


0/133 


1.48 


MC6800 


0/34 


0/34 


0/34 


0.00 


MC6802 


0/34 


0/34 


0/34 


0.00 


MCM6810 


0/34 


0/34 


0/34 


0.00 


MC6846 


0/34 


0/34 


0/29 


0.00 


MC6850 


0/68 


0/68 


0/67 


0.00 


MC68488 


0/34 


0/34 


0/34 


0.00 


MC68661 


0/68 


0/68 


1/68 


1.47 


TOTAL 


0/475 


2/474 


1/467 


0.64 


HMOS DIP 










MC6801 


0/432 


0/431 


0/431 


0.00 


MC6803U4 


0/68 


0/68 


0/68 


0.00 


MC6804J2 


0/343 


0/343 


0/343 


0.00 


MC6804P2 


0/34 


0/34 


0/34 


0.00 


MC6805P2 


0/68 


0/68 


0/68 


0.00 


MC6805P4 


0/34 


0/34 


0/34 


0.00 




0/432 


4/432 


0/428 


ft Q*3 

u.yo 


MC6805R3 


0/34 


0/34 


0/34 


0.00 


MC6805S2 


0/68 


0/68 


0/68 


0.00 


MC6805S3 


0/34 


0/34 


2/32 


5.88 


IVlCo8051 2 


0/34 


0/34 


0/34 


0.00 


MC68661 


0/34 


0/34 


0/33 ■:, 


0.00 


MC68681 


0/102 


0/102 


0/95 


0.00 


MC68901 


0/33 


0/34 


0/33 


0.00 


TOTAL 


0/1750 


4/1750 


2/1735 


0.34 


HMOS CERAMIC 










MC6801L 


0/38 


0/38 


0/37 


0.00 


MC6850 


0/38 


0/38 


0/37 


0.00 


MC68000L 


0/38 


0/36 


0/36 


0.00 


MC68010R 


0/38 


0/38 


0/38 


0.00 


MC68451L 


0/38 


0/38 


0/36 


0.00 


TOTfll 
1 KJ 1 ML 




0/188 




0/184 


A Aft 

0.00 


HCMOS DIP 










XC68HC01 


0/34 


0/34 


0/34 


0.00 


MC68HC05C8 


0/68 


0/68 


0/68 


0.00 


TOTAL 


0/102 


0/102 


0/102 


0.00 


HMOS PLCC 










MC68HC11 


0/615 


2/614 


0/612 


0.33 


HCMOS CERAMIC 










MC68020R 


0/462 


0/461 


1/459 


0.22 


MC68881R 


0/205 


0/205 


0/199 


0.00 


TOTAL 


0/667 


0/666 


1/658 


0.15 


CMOS DIP 










MC146805G2 


0/34 


0/34 


0/31 


0.00 


MC146805F2 


0/68 


0/68 


0/68 


0.00 


MC146818 


0/34 


0/34 


0/33 


0.00 


MC146823 


0/34 


0/34 


0/34 


0.00 


TOTAL 


0/170 


0/170 


0/166 


0.00 



MOTOROLA MICROPROCESSOR DATA 
2-19 



Table 2-14. Thermal Shock Test 
GRAND TOTAL 



TEMPERATURE: - 65°C to + 1 50°C 
STRESS METHOD: Liquid to Liquid 
LONGEST STRESS: 1000 Cycles 




0.2 — 

0.1 

0 \ 1 1 

YR 1985 YR 1986 YR 1987 

YEAR 



Figure 2-6. Thermal Shock Trend Chart 



Data Retention Test 

Data retention testing or high temperature storage is performed to measure the stability of the 
programmed EPROM and EEPROM devices during storage at elevated temperatures with no 
electrical stress applied. The devices are stored at an ambient of 150°C. An acceleration of charge 
loss from the storage cell is the expected result. All groups are typically tested to 1008 hours. 

Table 2-15 lists the results and the grand total of the data retention test. Figure 2-7 shows the 
trend chart for the data retention bake test. 



MOTOROLA MICROPROCESSOR DATA 
2-20 



Table 2-15. Data Retention Test 



TEMPERATURE: 150°C 
LONGEST STRESS: 1008 Hours 



Device Type 


— Failures Per Sample — 


168 Hrs. 


504 Hrs. 


1008 Hrs. 


% Failures 


HMOS CERAMIC 

MC1468705F2 

MC68701U4 

MC68705R3 

MC68704P2 

MC68701 


0/78 

0/44 

0/45 

0/442 

0/45 


0/78 

0/44 

0/45 

0/442 

0/45 


0/78 

0/44 

0/45 

0/442 

0/45 


0.00 
0.00 
0.00 
0.00 
0.00 


IUIAL 


0/654 


0/654 


0/654 


0.00 


HMOS DIP 

MC68000 


0/100 


0/100 


0/100 


0.00 


HMOS PLCC 

MC68705R3 


1/2044 


0/2043 


1/2043 


0.10 


HCMOS PLCC 

XC68HC11A8* 
MC68HC11A8* 


1/385 
2/1668 


0/381 
2/1667 


0/377 
2/1665 


0.26 
0.36 


TOTAL 


3/2053 


2/2048 


2/2042 


0.34 


HMOS 
HCMOS 


1/2798 
3/2053 


0/2797 
2/2048 


1/2797 
2/2042 


0.07 

0.3 

45 


GRAND TOTAL 


4/4851 


2/4845 


3/4839 


0.19 



*These EEPROM units were prestressed through 10K write/erase cycles. 



CUM % 0 3 
FAILURE 0.25 
RATE o 2 




0.05 

0 \ 1 ; 1 

YR 1985 YR 1986 YR 1987 

YEAR 

Figure 2-7. Data Retention Bake Trend Chart 



EEPROM Write/Erase Cycling Test 



The write/erase endurance test measures EEPROM cell operation over an expected life time. All 
cells are alternately cycled for 10,000 cycles between an erased state "1" and a write state "0" 
at the device high temperature specification of 85°C. The most common failure mode is failure 
to write a "0" within the 10 msec specification limit. 



MOTOROLA MICROPROCESSOR DATA 
2-21 



Table 2-16 lists the results and grand total of the EEPROM write/erase cycling test. Table 2-17 lists 
the average outgoing quality from year 1979 through 1987. 



a 



Table 2-16. EEPROM Write/Erase Cycling Test 



VOLTAGE: 5.5 Volts 
TEMPERATURE: 85°C 
LONGEST STRESS: 10K Cycles 



Device Type 


— Failures Per Sample — 


1Kcyc 


2K eye 


5K eye 


8K eye 


10K eye 


Failure 


HCMOS PLCC 

XC68HC11A8 
(Mask: 1B96D) 
XC68HC11A8 
(Mask: 2B96D) 
MC68HC11A8 
(Mask: 2B96D) 
MC68HC11A8 
(Mask: 7B96D) 


1/288 
3/642 
1/314 
3/1289 


1/287 
2/633 
1/313 
0/1286 


3/286 
2/629 
0/312 
0/1286 


0/283 
2/627 
0/312 
1/1286 


1/283 
0/625 
0/312 
1/1285 


2.10 
1.42 
0.64 
0.39 


TOTAL 


8/2533 


4/2519 


5/2513 


3/2508 


2/2505 


0.87 


Write/Erase Cycling Failure Rate Calculation 


Device Type 


Test 
Device 


85°C 
Device Hrs. 


70°C Equiv. 
Device eye 1 


Failures 


% IK eye 
0.53 eV 2 


HCMOS PLCC 

MC68HC11A8 
(Mask: 1 & 2B96D) 
MC68HC11A8 

(Mask: 7B96D (Current Mask)) 


1244 
1289 


12,440,000 
12,900,000 


2.58 x10 7 
2.67 x10 7 


17 
5 


0.090 
0.035 


GRAND TOTAL 


2533 


25,340,000 


5.24 X10 7 


22 


0.056 



1) Activation energy used in equivalent device cycle calculation is 0.53 eV.. 

2) 90% confidence. 



Table 2-17. Average Outgoing Quality 





Goal 
(PPM) 


Electrical 


Visual/Mech. 


Time Frame 


AOQ(PPM) 


AOQ (PPM) 




Actual 


Actual 


Year 1979 


3000 


(~)4000 


(~)4500 


Year 1980 


2500 


(~)2000 


(~)2500 


Year 1981 


1500 


1725 


1920 


Year 1982 


900 


717 


1103 


Year 1983 


425 


383 


380 


Year 1984 


200 


419 


403 


Year 1985 


80 


272 


137 


Year 1986 


50 


291 


509 


Year 1987 


50 


232 


190 



MOTOROLA MICROPROCESSOR DATA 
2-22 



RESULTS AND CONCLUSION 



The 1987 Microprocessor Reliability results indicate that the major product lines have excellent 
overall reliability performance. The reliability performance of our products is evaluated through 
extensive stress/testing which includes life test, temperature cycle, thermal shock, THB, autoclave, 
and data retention bake. This year's results indicate there are many areas where significant gains 
were made in reliability performance as compared to the 1986 results. , 

The overall High Temperature Operating Life test result for the year was excellent with a failure 
rate of 117 FITs compared to the 1986 yearly total of 264 FITs (based on 0.7 eV). Failure rate 
improvements were seen in all of the key process technologies during the year. The life test failure 
rate for NMOS was 91 FITs which is a 55% improvement compared to the previous yearly results. 
The HMOS failure rate improved to a 127 FIT level as compared to the 467 FIT level this technology 
achieved in 1986. The HCMOS failure rate was 224 FITs which is a 16% improvement in the 1986 
figure. The 5 micron CMOS technology achieved a failure rate of 125 FITs which is excellent and 
a significant improvement over 1986. 

The environmental results for 1987 indicate that our products lines are capable pf meeting rigid 
environmental extremes with very low failure rates. The actual stress results for the various 
thermal cycling and moisture tests are detailed below. 

The temperature cycle results for 1987 improved to an overall 0.43% cumulative failure rate 
through 1000 cycles. This is a 51% gain over the 1986 figures. Thermal shock results for this 
period also improved substantially to a 0.30% level. These figures are excellent. 

Both temperature humidity bias and autoclave produced improved failure rate performance during 
1987. Temperature humidity bias achieved a 0.16% cumulative failure rate through 1008 hours. 
The autoclave test for this time frame resulted in a 0.11% figure which is a 56% improvement 
over 1986. 

Data retention bake, which is used to evaluate the ability of the MCU EPROM and EEPROM devices 
to store charge over an extended period of time, has a cumulative percent fallout of 0.19%. This 
figure has improved 42% during 1987 as compared to the previous years results. 

Write/erase cycling, which was begun this year to measure the MCU EEPROM arrays operational 
endurance over an expected life time, resulted in an overall failure rate of 0.056%/1K cycles at 
70°C. The most recent material evaluated in the 4th quarter of 1987 achieved a 0.035%/1 K cycles 
failure rate. 

Average Outgoing Quality levels for both electrical and visual/mechanical performance improved 
for 1987. The yearly figures are 232 ppm for electrical and 190 ppm for visual/mechanical. 

In summary, the Motorola Microprocessor Product Group's products are achieving very high 
levels of reliability and quality performance. Improvements in many key areas have been made 
during the course of the year, and as a group our goal will be to continually upgrade the Reliability 
and Quality of our products. 

For more information, contact Microprocessor Reliability Engineering at 512/440-2530 or write to: 

Microprocessor Reliability Engineering 
Motorola Inc. 

6501 William Cannon Drive West 
Austin, Texas 78735-8598 



MOTOROLA MICROPROCESSOR DATA 
2-23 



FAILURE RATE CALCULATIONS 



Environmental tests are designed to measure device resistance to unusual and severe stress not 
expected under normal operating conditions. Device performance under these conditions is ex- 
pressed as a percent of devices defective and compared to previous results. Life tests, on the 
other hand, accelerate the use conditions of the device with temperature and voltage in a manner 
which is more quantitatively correctable to system operation. Life test failure rates are expressed 
as failures per unit time and are calculated using established principles or probability and statistics. 

The principles of reliability engineering have indicated that failure rates for semiconductor devices 
will take the form of the"bathtub" curve (Figure 2-8). 



t 



FAILURE 
RATE 



CLASSICAL FAILURE RATE CURVE 



REGION 1 



REGION 2 



REGION 3 



TIME 



Figure 2-8. Device Failure Rate as a Function of Time 



The following three regions are represented in the curve: 

1 . Infant Mortality — a region of high bur rapidly declining failure rates, usually associated with 
manufacturing defects. 

2. Random Failures — a region of low, random failures caused by more subtle defects. This 
area of the curve represents the useful part of device life. 

3. Wearout — a region of rapidly rising failure rates related to device wearout. Most semicon- 
ductors will not reach this stage before they are replaced because of changes in technology. 

Techniques for calculating life test failure rates assume that the devices being tested have passed 
infant mortality and entered the stable random failure portion of the life curve. Failures which 
occur in this area are few and are known to approximate specific probability distributions. These 
probability distributions are used to calculate sample failure rates which can be projected to the 
population in general through the application of confidence limits. Techniques used to calculate 
life test failure rates for micorprocessors are discussed below. 

A failure rate for any sample of life tested devices can be determined by dividing the number of 
failures by the number of device hours. However, this rate will apply to that sample only. Ff you 
are interested in projecting from the sample to the population in general, you must establish 
confidence limits. The application of confidence limits is a statement of how "confident" you are 
that the sample failure rate approximates that for the population in general. To obtain rates with 
different confidence levels, it is necessary to make use of specific probability distributions which 
take the same form as the actual failure distribution. 



MOTOROLA MICROPROCESSOR DATA 
2-24 



It has been determined that failures in semiconductors that have entered the middle portion of 
the bathtub curve will approximate a Poisson distribution; this distribution applies when one has 
a large sample with an extremely small number of events of interest, such as device failures. 
Given a Poisson failure process, a Chi-Square distribution can be used to establish confidence 
limits for failure rates. R&QA Engineering has determined that the following general formula, 
which utilizes values from a Chi-Square table, can be used to calculate failure rates for semicon- 
ductors: 

^ X 2<^> 
2t 



where: 




A. = Failure Rate 

x 2 = Chi-Square Function 

100 - Confidence Level 



a 



100 

d.f. = Degrees of Freedom = 2r + 2 
r = Number of Rejects 
t = Device Hours 



To calculate the failure rate, first determine the level of confidence you require and calculate 
degrees of freedom. Select the Chi-Square value for a Chi-Square distribution table with the 
appropriate degrees of freedom and confidence level. Divide that value by twice the actual device 
hours, at the temperature of interest. 

The above formula applies for calculating a device failure rate, provided that the test is conducted 
at system temperature. However, since we are unable to observe long-term effects which develop 
over time, the test is accelerated through the application of a high temperature. In oder to calculate 
a failure rate at the ambient temperature of a system, a factor must be supplied to compensate 
for the acceleration. The factor (Fa) which equates test temperature with rated temperature is 
derived from the Arrhenius relationship: 

Fa = exp((<|>/k). (1 -1) ) 
Tr Tt 

where: 

Fa = Acceleration Factor 

cj> = Activation Energy, eV 

k = Boltzman's Constant, 8.62 x 10 _5 eV/K 

Tr = Junction Temperature, K at the Rated 

Ambient of 70°C 
Tt = Junction Temperature, K at the Life Test 

Ambient of 125°C 



Motorola uses 70°C for the system temperature (To) to more closely approximate the actual 
temperature of the device during system operation and to supply a degree of conservatism to 
the failure rate calculation. 

Motorola uses an activation energy value of 0.7 electron volt. A 0.7 eV was selected as an average 
value because a variety of different failure mechanisms exist for microprocessor and other VLSI 



MOTOROLA MICROPROCESSOR DATA 
2-25 



devices, with activation energies ranging from 0.40 eV for oxide related failures to 1.0 eV or greater 
for contamination and metal related failures. Tr and Tt of the equation are the average junction 
temperatures present at the rated and test ambients. Motorola uses junction, rather than ambient 
temperature, because they produce acceleration factors that are more conservative and repre- 
sentative of actual conditions. These temperatures are calculated as follows: 



Once this step has been completed, the acceleration factor can be calculated and applied as a 
multiplier to the number of device test hours under accelerated test conditions to determine the 
equivalent number of hours at rated operating conditions. To determine the failure rate at the 
operating temperature use equation (1) substituting the equivalent device hours at rated tem- 
perature for t in the equation. 

Equation (1) provides a failure rate expressed in percent per thousand hours. This number, stated 
as a percentage per each thousand hours of operation, is one way Motorola R&QA Engineering 
expresses failure rates for Microprocessors. One other way of expressing failure rates is Failures 
In Time (FITs) which refers to failed units per 10 9 device hours (1 FIT=X.x 10 4 ). 

Mean Time To Failure (MTTF) is another parameter frequently used to express failure rates. MTTF 
is the average time to a failure of a nonrepayable item such as a semiconductor and is expressed 
as the reciprocal of the failure rate: 




Tj = Ta + Pd-6JA 



(3) 



where: 



Tj 
TA 

pd 

ejA 



Junction Temperature, °C 
Ambient Temperature, °C 
Average Power Dissipation, Watts 
Thermal Resistance — Junction to Ambient, 
°C Per Watt 




(4) 



MOTOROLA MICROPROCESSOR DATA 
2-26 



Data Sheets 

Volume I and II 




This chapter (found in both Volume I and Volume II) contains the data sheets 
for the Microprocessors, Microcontrollers, and Peripheral devices. For information 
on packaging, refer to Chapter 4. Ordering forms are located in Chapter 6. 



MOTOROLA MICROPROCESSOR DATA 



3 



MOTOROLA MICROPROCESSOR DATA 



MOTOROLA 

SEMICONDUCTOR mmmmmmam ^ Hmmmmmmamammtm 

TECHNICAL DATA 

MC2672 



Advance Information 

Programmable Video Timing Controller 
(PVTC) 

The MC2672 programmable video timing controller (PVTC) is a programmable device designed 
for use in CRT terminals and displays systems that employ raster scan techniques. The PVTC gener- 
ates the vertical and horizontal timing signals necessary for the display of interlaced or non-inter- 
laced data on a CRT monitor. It provides consecutive addressing to a user specified display buffer 
memory domain and controls the CPU-display buffer interface for various buffer configuration 
modes. A variety of operating modes, display formats, and timing profiles can be implemented by 
programming the control registers in the PVTC. Applications include CRT terminals, word-process- 
ing systems, small business computers, and home computers. 

• 4 MHz Character Rate 

• Up to 256 Characters Per Row 

• 1 to 16 Raster Lines Per Character Row 

• Up to 128 Character Rows Per Frame 

• Programmable Horizontal and Vertical Sync Generators 

• Interlaced or Non-interlaced Operation 

• Up to 16K RAM Addressing for Multiple Page Operation 

• Automatic Wraparound of RAM 

• Addressable, Incrementable, and Readable Cursor 

• Programmable Cursor Size, Position, and Blink 

• Split Screen and Horizontal Scroll Capability 

• Light Pen Register 

• Selectable Buffer Interfce Modes 

• Dynamic RAM Refresh 

• Completely TTL Compatible 

• Single +5-Volt Power Supply 

• Power-On Reset Circuit 



This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-1 



MC2672 



BLOCK DIAGRAM 



CE 



A0-A2 



INTR 



Interface 



Read/Write 
Control Logic 




GND 



CCLK 



Address 
Decoder 















Data Bus 
Drivers 



Clock 
Buffer 



Control 



Initialization 
and Display 
.Registers 



Command, 
Decode 
Logic 



Interrupt 
Logic and 
Status 




Timing 



Timing Chain 

and 
Decode Logic 



Display 
Memory 
Handshake 
Logic 



Display 



Address 
Timing 
Multiplexers 



Cursor, 
Pointer, and 
Light Pen 
Registers 



Cursor and 
Compare 
Logic 



CTRL1, 



CTRL2. 



CTRL3. 



DADDO- 
DADD13, 



Light Pen Strobe 



CURSOR, 



HSYNC. 



VSYNC/CSYNC, 



BLANK. 



ABSOLUTE MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


v C c 


-0.3 to +7.0 


V 


Input Voltage 


Vin 


-0.3 to +7.0 


V 


Operating Temperature Range 


T A 


0 to 70 


°c 


Storage Temperature Range 


T stg 


-55 to + 150 


°c 



THERMAL CHARACTERISTICS 



Characteristic 


Symbol 


Value 


Rating 


Thermal Resistance 
Plastic Package 


6ja 


50 


°C/W 



This device contains circuitry to pro- 
tect the inputs against damage due to 
high static voltages or electric fields; 
however, it is advised that normal pre- 
cautions be taken to avoid application 
of any voltage higher than maximum- 
rated voltages to this high-impedance 
circuit. For proper operation it is rec- 
ommended that Vj n and V ou t be con- 
strained to the range GND=s(Vj n or 
V 0Ut )ssVrjc. Reliability of operation is 
enhanced if unused inputs are tied to 
an appropriate logic voltage level (e.g., 
either GND or Vqc)- 



MOTOROLA MICROPROCESSOR DATA 
3-2 



MC2672 



POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj=T A +(PD*ejA) (1) 



where: 




T A 


= Ambient Temperature, °C 


ej A 


= Package Thermal Resistance, 




Junction-to-Ambient, °C/W 


PD 


= P|NT+PP0RT 


pint 


= ICC x V CG Watts — Chip Internal Power 


pport 


= Port Power Dissipation, Watts — User Determined 



For most applications PpORT<P|NT and can be neglected. PpORT ma Y become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpORT is neglected) is: 

PD = K-(Tj + 273°C> (2) 

Solving equations (1) and (2) for K gives: 

K = PD-(TA+273°C>+ejA-PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at 
equilibrium) for a known Ta- Using this value of K, the values of Pd and Tj can be obtained by solving equations 
(1) and (2) iteratively for any value of Ta 



DC ELECTRICAL CHARACTERISTICS (T A = 0°C to 70°C, Vgc = 5j V ±5%) 



Parameter 


Symbol 


Min 


Max 


Unit 


Input Low Voltage 


V|L 


-0.3 


0.8 


V 


Input High Voltage 


V| H 


2.0 


v C c 


V 


Output Low Voltage dLoad = 2.4 mA) 


vol 




0.4 


V 


Output High Voltage (Except INTR Output) l|_oad= 200 ^ A 


voh 


2.4 




v 


Input Leakage Current Vj n = 0 to VfJC 


■in 


-10 


10 


M A 


Hi-Z (Offstate) Input Current Vj n = 0.4 to 2.4 V 


'TSI 


-10 


10 


^A 


INTR Open-Drain Output Leakage Current Voh = 2 - 4 V CC 


lLOH 




10 


/.A 


Internal Power Dissipation 


Pint 




800 


mW 



NOTE: All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 



MC2672 



AC ELECTRICAL CHARACTERISTICS - BUS TIMING (Ta=0° to 70°C, V C c = 5.0 V ±5%, See Note 1) 







MC2672B3 


MC2672B4 




Parameter 


Symbol 


Min 


Max 


Min 


Max 


Unit 


A0-A2 Setup Time to W, R Low 


tAS 


30 




30 


~ ... 


ns 


A0-A2 Hold Time from W, R High 


tAH 


0 




0 




ns 


CI Setup Time to W, R Low 


tcs 


0 


-. 


■ 0 


- 


ns 


CE Hold Time from W, R High 


tCH 


0 




0 




ns 


W, R Pulse Width 


tRW 


250 




, 250 




ns 


Data Valid after R Low 


tDD 




200 . 




200 


ns 


Data Bus Floating after R High 


tDF 




100 




• 100 


ns 


Data Setup Time to W High 


tDS 


150 




150 




ns 


Data Hold Time from W High 


l DH 


10 




5 




ns 


High Time from CE to C~E (see Note 2) Consecutive Commands 

Other Commands 


tec 


600 
300 




600 
300 




ns 
ns 




NOTES: _ _ 

1. Timing is illustrated and specified referenced to W and R inputs. Device may also be operated with CE as the "strobing" 
input. In this ase, all timing specifications apply referenced to falling and rising edges of CE. 

2. This specification requires that the CE input be negated (high) between read and/or write cycles. 

3. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



BUS TIMING DIAGRAM 



A0-A2 



D0-D7 (Write) 




D0-D7(Read) Float 



MOTOROLA MICROPROCESSOR DATA 
3-4 



MC2672 



AC ELECTRICAL CHARACTERISTICS - CHARACTER CLOCK TIMING (T A = 0°C to 70"C, V C c = 5.0 V ±5%, See Note 1) 



Parameter 


Symbol 


MC2672B3 


M2672B4 


Unit 


Min 


Max 


Min 


Max 


CCLK Period 


»CCP 


370 




250 




ns 


CCLK High Time 


*CCH 


125 




TOO 




ns 


CCLK Low Time 


»CCL 


125 




100 




ns 


Output Delay Time from CCLK Edge 

DADD0-DADD13, BCE, WDB, RDB", MBC 

BLANK, HSYNC, VSYNC/CSYNC, CURSOR, BEXT, BREQ, BACK ' 


tCCD 


40 
40 


175 
225 


40 
40 


150 
200 


ns 



NOTES: 

1. BCE, WDB, and RDB delays track each other within 10 nanoseconds. Also, these output delays will tend to follow the direction 
(minimum/maximum) of DADD0-DADD13 delays. 

2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



CCLK 



Outputs 
(See Note 1) 



Outputs 
WDB, RDB, BCE 



CHARACTER CLOCK TIMING DIAGRAM 



-tccp- 



*—tCCL-*\ 

l CCD 



1 



-tCCH" 



tCCD- < *• 



1 




NOTES: 

1. DADD0-DADD13, BLANK, HSYN C, CSYNC/VSYNC, CURSOR, BEXT, BREQ, BCE, MBC, BACK. 

2. BCE changes state on both CCLK edges. 



MOTOROLA MICROPROCESSOR DATA 
3-5 



MC2672 



AC ELECTRICAL CHARACTERISTICS— OTHER TIMINGS (T A =0°C to 70°C, V C c=5.0 V ±5%) 



Parameter ■ 


Symbol 


MC2672B3 


MC2( 


S72B4 


Unit 


Min 


Max 


Min 


Max 


READY/ RDFLG Low from W HIGH 


tRDL 




tccP + 30 




tcCP + 30 


ns ' 


BACK High from PBREO. Low 


l BAK 




225 




200 


ns 


BEXt High from PBREQ High 


tBXT 




225 




200 


ns 


Light Pen Strobe Setup Time to CCLK Low 


tLPS 


120 




120 




ns 


Light Pen Strobe Hold Time from CCLK Low 


l LPH 


-10 




-10 




hs 


WrT Low from CCLK" Low 


l IRL 




225 




200 


ns 


INTfT High from W, R~ High 


t|RH 




600 




600 


ns 



NOTES: 

1. Timing is illustrated and specified referenced to W and R inputs. Device may also be operated with CE as the "strobing" 
input. In this case, all timing specifications apply referened to falling and rising edges of CE. 

2. All voltage measurements are referenced to ground. All time measurements are at the 0 8 V to 2.0 V level for inputs and 



outputs. Input levels are 0.4 V to 2.4 V. 



OTHER TIMING DIAGRAMS 





MOTOROLA MICROPROCESSOR DATA 
3-6 



MC2672 




Wfora 
Delayed 
Command 



Ready or 
RDFLG Status 
Bits 



PBREQ 



BACK 
BEXT 



W or R Which 
Resets 
Interrupt 



INTR' 



tRDL N— 



V 




tBAK |<— 

—T ' it 



t|RH 



r 



MOTOROLA MICROPROCESSOR DATA 



MC2672 



COMPOSITE SYNC TIMING DIAGRAM 



Even Field 
Last Displayed Scan 
of Previous Field 



-Vertical Front Porch- 



Vertical SYNC 
Pulse 



-Vertical Back Porch 



—I "J 



First Displayed Scan 
of Even Field 

Horizontal Sync 
'Pulses 



BLANK 



-Vertical Blanking Interval- 



^L_n_ 



Odd Field 

Last Displayed Scan 
of Even Field 



Ir 



Vertical Front Porch — V4 H- 



. Vertical SYNC_J^_ Vertjca | Back Rorch 
Pulse -HHHK 



'/ 2 H- 



First Displayed Scan 
of Odd Field 



? V4 Horizontal SYNC->lh*- k jK — H — H Period 

BLANK [j | < _ Vertical Blanking Interval — -> | 1 ^ 1 | ~l 

Horizontal Blanking Interval 

NOTES: 

1. In non-interlaced operation the even field is repeated continuously, and the odd field is not. 

2. Interlaced operation the even field alternates with the odd field. 

3. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



SIGNAL DESCRIPTION 

The input and output signals for the PVTC are described in 
the following .paragraphs. 

Vcc AND GND 

Power is supplied to the PVTC using these two pins. Vcc 
is the +5 volts +5% power input and GND is the ground 
connection. 

ADDRESS LINES (A0-A2) 

These lines are used to select PVTC internal registers for 
read/write operations and for commands, 

DATA BUS (D0-D7) 

These lines comprise the 8-bit bidirectional three-state 
data bus. Bit 0 is the least significant bit and bit 7 is the most 
significant bit. All data, command, and status transfers bet- 
ween the CPU and the PVTC take place over this bus. The 
direction of the transfer is controlled by the read and write in- 
puts when the chip enable input is low. When the chip 
enable input is high the data bus is in the high-impedance 
state. 

READ STROBE (R) 

This pin is an active low input. A low on this pin while chip 
enable is low causes the contents of the register selected by 
A0-A2 to be placed on_the data bus. The read cycle begins 
on the falling edge of R. 



WRITE STROBE (W) 

This pin is an active low input. A low on this pin while chip 
enable is also low causes the contents of the data bus to be 
transferred to the register sejected by A0-A2. The transfer 
occurs on the rising edge of W. 

CHIP ENABLE (CE) 

This pin is an active low input. When low, data transfers 
between the CPU_and the PVTC are enabled on_D0-D7 as 
controlled by the W, R, and A0-A2 inputs. When CE is high, 
the PVTC is effectively isolated from the data bus and DO 
through D7 are placed in the high-impedance state. 

CHARACTER CLOCK (CCLK) 

This pin is the timing signal derived from the video dot 
clock which is used to synchronize the PVTC's timing func- 
tions. 

HORIZONTAL SYNC (HSYNC) 

This pin is an active high output which provides video 
horizontal sync pulses. The timing parameters are program- 
mable. 

VERTICAL SYNC/COMPOSITE SYNC (VSYNC/CSYNC) 

A control bit selects either vertical or composite sync 
pulses on this active high output. When CSYNC is selected, 
equalization pulses are included. The timing parameters are 
programmable. 



MOTOROLA MICROPROCESSOR DATA 
3-8 



MC2672 



BLANK (BLANK) DISPLAY ADDRESS (DADD0-DADD13) 



This active high output defines the horizontal and vertical The display address is used by the PVTC to address up to 

borders of the display. Display control signals which are out- 16K of display memory. These outputs are floated at various 




MC2672 



TABLE 1 - PVTC ADDRESSING 



A2 


A1 


AO 


Read ( R = 0) 


Write (W = 0) 


0 


0 


0 


Interrupt Register 


Initialization Registers* 


0 


0 


1 


Status Register 


Command Register 


0 


1 


0 


Screen Start Address Lower Register 


Screen Start Address Lower Register 


0 


1 


1 


Screen Start Address Upper Register 


Screen Start Address Upper Register 


1 


0 


0 


Cursor Address Lower Register 


Cursor Address Lower Register 


1 


0 


1 


Cursor Address Upper Register 


Cursor Address Upper Register 


1 


1 


0 


Light Pen Address Lower Register 


Display Pointer Address Lower Register 


1 


1 


1 


Light Pen Address Upper Register 


Display Pointer Address Upper Register 



•There are 11 initialization registers which are accessed sequentially via a simple address. The PVTC 
maintains an internal pointer to these registers which is incremented after each write at this address 
until the last register (IR10, the split-screen register) is accessed. The pointer then continues to point 
to the split-screen register. Upon power-up or a master reset command, the internal pointer is reset to 
point to the first register; (IRO) (of the initialization register group. The internal pointer can also be preset 
to any register of the group via the "load IR address pointer" command. 




OPERATION CONTROL 

The operation control section decodes configuration and 
operation commands from the CPU and generates appro- 
priate signals to other internal sections to control the overall 
device operation. It contains the timing and display registers 
which configure the display format and operating modes, 
the interrupt logic, and the status register which provides 
operational feedback to the CPU. 

TIMING 

The timing section contains the cursors and decoding 
logic necessary to generate and monitor timing outputs and 
to control the display format. These timing parameters are 
selected by programming of the initialization registers. 

DISPLAY CONTROL 

The display control section generates linear addressing of 
up to 16K bytes of display memorv. Internal comparators 
limit the portion of the memory which is displayed to pro- 
grammed values. Additional functions performed in this sec- 
tion include cursor positioning, storage of light pen "hit" 
locations, and address comparisons required for generation 
of timing signals and the split-screen interrupt. 

BUFFER CONTROL . 

The buffer control section generates three signals which 
control the transfer of data between the CPU and the display 
buffer memory. Four system configurations requiring four 
different handshaking schemes are supported. These are 
described in SYSTEM CONFIGURATIONS- 



SYSTEM CONFIGURATIONS 

Figure 1 illustrates the block diagram of a typical display 
terminal that uses an MC2672, character ROM, a keyboard in- 
terface, and an attribute controller. In this system, the CPU 
examines inputs from the data communications line and the 
keyboard and places the data to be displayed in the display 
buffer memory. The buffer is typically a RAM wich holds the 
data for a single or multiple screenload (page) or for a single 
character row. 

The PVTC supports four common system configurations 
of display buffer memory, designated the independent, 
transparent, shared, and row-buffer modes. The first three 



modes utilize a single or multiple page RAM and differ 
primarily in the means used to transfer display data between 
the RAM and the CPU. The row-buffer mode makes use of a 
single row buffer (which can be shift register or a small 
RAM) that is updated in real time to contain the appropriate 
display data. 

The user program bits 0 and 1 of IRO to select the mode best 
suited for the system environment. The CNTRL1-CNTRL3 out- 
puts perform different functions for each mode and are named 
accordingly in the description of each mode given in the fol- 
lowing paragraphs. 

INDEPENDENT MODE 

The CPU-to-RAM interface configuration for this models 
illustrated in Figure 2. Transfer of data between the CPU and 
display memory is accomplished via a bidirectional l atche d 
port and is contr olled by the signals read data bu ffer ( RDB), 
write data buffer (WDB), and buffer chip enable (BCE). This 
mode provides a non-contention type of operation that does 
not address the memory directly. The read or write operation 
is performed at the address contained in the cursor address 
register or the pointer address register as specified by the 
CPU. The PVTC enacts the data transfers during blanking 
intervals in order to prevent visual disturbances of the 
displayed data. 

The CPU manages the data transfers by supply commands 
to the PVTC. The commands used are: 

1. Read/write at pointer address. 

2. Read/write at cursor address (with optional incre- 
ment of address). 

3. Write from cursor address to pointer address. 
The operational sequence for a write operation is: 

1. CPU checks RDFLG status bit to assure that any 
previous operation has been completed. 

2. CPU loads data to be written to display memory into 
the interface latch. 

3. CPU writes address into cursor or pointer registers. 

4. CPU issues "write at cursor with/without increment" 
or "write at pointer" command. 

. 5. PVTC generates control signals and outputs specified 
address to perform requested operation. Data is 
copied from the interface latch into the memory. 



MOTOROLA MICROPROCESSOR DATA 
3-10 



MC2672 



6. PVTC sets RDFLG status to indicate that the write is 
completed. 

Similarly, a read operation proceeds as follows: 

1 . Steps 1 . and 3. as above 

2. CPU issues "read at cursor with/without increment" 



5. PVTC generates control signals and outputs block 
addresses to copy data from the interface latch into 
the specified block of memory. 

6. PVTC sets RDFLG status to indicate that the block 
write is completed. 



MC2672 



FIGURE 2 - INDEPENDENT BUFFER-MODE CONFIGURATION 



MC2672 
PVTC 



DADD 

CTRL3 
CTRL1 
CRTL2 



Display Address 



BCE 



WDB 



i 



Refresh 
RAM 



ADR 



-> CE 

W 



Data I/O 

7^ 



1Z 



CP_ SN74LS364 
OE 

R T | ! w. 

From CPU J L From CPU 



Display Data Bus 



>To 
Video 
Logic 



OE 

CP SN74LS364 



System Data Bus 



FIGURE 3 - READ/WRITE AT CURSOR/POINTER COMMAND TIMING DIAGRAM 
(Command Received During Active Display Window) 



CCLK 



W 



V 



V 



Horizontal Blanking 
Interval 



V 



RDB 



WDB 



BCE 



~Y V ~"V NV Last V Cursor or V N"\/ V V pvtc control Signals W1 st CharW ' V 

AAA K AAddressA Pointer Address A k A A A toVACandDCG A AddressA A 

\ 



-Refresh Addresses- 



t : — r 

»_ I 



i — \ 

I V 

J k. 



NOTE: Write waveforms shown in dotted lines. 



MOTOROLA MICROPROCESSOR DATA 
3-12 



MC2672 



FIGURE 4 - READ/WRITE AT CURSOR/ POINTER COMMAND TIMING DIAGRAM 
(Command Received While Display is Blanked) 



CCLK> 



CE' 



W 



BLANK- 



DADD 



RDB 



WDB 



BCE 



Mr 



V 



XV V VPVTC Read Command V V"V V V y VpvTC Write Command* V" 
A _A A Address A K^-A A A A A £2*22 A A 

- -' " — Refresh Addresses- — 



-Refresh Addresses 



r\—TY 



FIGURE 5 - WRITE FROM CURSOR-TO-POINTER COMMAND TIMING 



CCLK 



CE 



BLANK 



DADD 



WDB 













u 










\J 










/ 












v Y Y AnyCh8r1 

AAA Address , 


Cursor Address )( fes+1* 


1 





BLANK is Set Until First VBLANK After Last Write 

I 



Pointer 
Address - 1 



Pointer 
Address 




RDB 



MOTOROLA MICROPROCESSOR DATA 
3-13 



MC2672 



SHARED AND TRANSPARENT BUFFER MODES 

In these modes the display buffer RAM is a part of the 
CPU memory domain and is addressed directly by the CPU. 
Both modes use the same hardware configuration with the 
CPU accessing the display buffer via three-sta te drivers (see 
Figure 6). The processor bus request (PBREQ) control signal 
informs the PVTC that the CPU is requesting access to the 
display buffer. In r espons e to this request, the PVTC raises 
bus acknowledge (BACK.) until its bus external (B EXT) out- 
put has freed the display address and data buses for CPU ac- 



cesses. BACK, which can be used as a "hold" input to the 
CPU, is then lowered to indicate that the CPU can access the 
buffer. 

In transparent mode, the PVTC delays the granting of the 
buffer to the CPU until a vertical or horizontal blanking inter- 
val, thereby causing minimum disturbance of the display. In 
shared mode, the PVTC will blank the display and grant im- 
mediate access to the CPU. Timing for these modes is il- 
lustrated in Figures 7, 8, and 9. 



FIGURE 6 - PVTC SHARED OR TRANSPARENT BUFFER MODES 



a 



(PBREQ — 
BACK 



BEXT 



MC2672 
PVTC 



CTRL1 
CTRL3 
CTRL2 



CPU 



P 



Select 
Decode 



Display Address 



-N 

V 



Refresh 
RAM 

ADR 



> CE 



W 



Data I/O 



Display Data Bus 



SN74LS244 



Upper 



System Address Bus 



Lower 




SN74LS245 



System Data Bus 



MOTOROLA MICROPROCESSOR DATA 
3-14 



MC2672 



FIGURE 7 - TRANSPARENT-BUFFER MODE TIMING 



CCD?' 



PBREQ 



(See 
Note 1) 



BACK J~ 



BLANK 



DADD 



I See Note 1) 



V 



Horizontal Blanking Interval 



/(See Note 2) 



(See Note 2) 



.•V 



■V— 
-N — -\ 



V~>ryLast Char. l / System X \ / V PVTC CTRL Sianalsy 1st Char. Y~"a|"Y PVTC CTRL Signals y 1st Char.tf 

A K , A Address ] \ Addresses! k f ~ \ A toVACandDCG A Address A K A toVACandDCG A Address A 



NOT ES: 

1 . P BREQ m ust be asserted prior to the risin g edge of 'BLANK in order for sequence to begin during that blanking period. 

2. If PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked. 



FIGURE 8 - SHARED-BUFFER MODE TIMING 



CCLK 
PBREQ 
B"SC"K 
BEXT 
BLANK 



DADD K K 5Y "> 



n_n_n 
\ 




_n 


JXf\f\J 

— Nf— 


/ 






^ 






\l 



/ (See Note 1) 



— -V 



/System^ 




\ (Addresses 


H 



(See Note 1) k 

■czz"^— I 

XPVTC CTRL Signals W 1st Char. \/""^ ¥ PVTC CTRL Signals V 1st Char. )/ 
to VAC and DCG A Address 1 |^ A lo VAC and DCG A Address A 



NOTE: 

1. If PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked. 



MOTOROLA MICROPROCESSOR DATA 
3-15 



MC2672 



FIGURE 9 - SHARED AND TRANSPARENT MODE TIMING 



a 



(a) During Vertical Blank or after 'display off command 

^ i\ru\nJ\f\f\ 



PBREQ 



BACK 



BEXT 



I 



VBLANK 
orDBLANK 



DADD 



r Refresh Addresses-' 



Sys. Add. 



4 Refresh >. 
Addresses 



ROW-BUFFER MODE 

Figures 10 and 11 show the timing and a typical hardware 
implementation for the row-buffer mode. During the first 
scan line (line 0) of each character row, the PVTC halts the 
CPU and DMA's the next row of character data from the 
system memory to row-buffer memory. The PVTC then 
releases the CPU and displays the row-buffer data for the 



CCLK 



(b) After 'display off and three-state' command 

rvrvrJ\rd'\f\ 



PBREQ 



BACK 



BEXT 



BLANK 



.-V- 



I — — -\ : 

DADD " \ System Processor has ^ Continuous 



Bus Control 



program med number of scan lines. The bus-request control 
(BREQ) signal informs the CPU that character addresses and 
the memory bus control (MBC) signal will start at the next 
falling edge of BLANK. The CPU must release the address 
and data buses before this time to prevent bus contention. 
After the row of character data is transferred to the CPU, 
BREQ returns high to grant memory control back to the 
CPU. 



FIGURE 10 - ROW-BUFFER MODE CONFIGURATION 



2x2111 



BREQ 
To CPU 



MC2672 
PVTC 



CTRL2 

CTRL3 



LSB's 



Display Address 



System Address Bus 




System Data Bus 



MOTOROLA MICROPROCESSOR DATA 
3-16 



MC2672 



FIGURE 11 - ROW-BUFFER MODE TIMING 



CCLK 



BREQ 



MBC 



^ ( Line 0 Only) 



-N- 



OPERATION 

After power is applied, the PVTC will be in an inactive 
state. Two consecutive "master reset" commands are 
necessary to release this circuitry and ready the PVTC for 
operation. Two register groups exist within the PVTC: the 
initialization registers and the display control registers. The 
initialization registers select the system configuration, 
monitor timing, cursor shape, display memory domain, and 
screen format. These are loaded first and normally require no 
modification except for certain special visual effects. The 
display control registers specify the memory address of the 
base character (upper left corner of screen), the cursor posi- 
tion, and the pointer address for independent memory 
access mode. These usually require modification during 
operation. 

After initial loading of the two register groups, the PVTC is 
ready to control the monitor screen. Prior to executing the 
PVTC commands which turn on the display and cursor, the 
user should load the display memory with the first data to be 
displayed. During operation, the PVTC will sequentially ad- 
dress the display memory within the limits programmed into 
its registers. The memory outputs character codes to the 
system character and graphics generation logic, where they 
are converted to the serial video stream necessary to display 



the data on the CRT. The user effects changes to the display 
by modifying the contents of the display memory, the PVTC 
display control and command registers, and the initialization 
registers, if required. Interrupts and status conditions 
generated by the PVTC supply the "handshaking" informa- 
tion necessary for the CPU to effect the display changes in 
the proper time frame. 



INITIALIZATION REGISTERS 

There are11 initialization registers (I RO-IR 10) which are ac- 
cessed sequentially via a single address. The PVTC maintains 
an internal pointer to these registers which is incremented 
after each write at this address until the last register (IR10, 
the split-screen register) is accessed. The pointer then con- 
tinues to point to the split-screen register. Upon power-up or 
a master reset command, the internal pointer is reset to point 
to the first register (IRO) of the initialization register group. 
The internal pointer can also be preset to any register of the 
group via the "load IR address pointer" command. These 
registers are write only and are used to specify parameters 
such as the system configuration, display format, cursor 
shape, and monitor timing. Register formats are shown in 
Figure 12 and described in the following paragraphs. 




FIGURE 12 - INITIALIZATION REGISTER FORMATS (Page 1 of 3) 



7 


6 5 


4 3 


2 


1 0 




Scan Lines Per Character Row 






Not Used 


Non-interlaced 


Interlaced 


Sync Select 


Buffer-Mode Select 




0000=1 Line 
0001 =2 Lines 
0010 = 3 Lines 
• 

• 


0000= Undefined 
0001=5 Lines 
0010 = 7 Lines 
• 
• 


0=VSYNC 
1=CSYNC 


00= Independent 
01 = Transparent 

10 = Shared 

11 = Row 




1110=15 Lines 
1111 = 16 Lines 


1110 = 31 Lines 

1111 = Undefined 







IRO 



MOTOROLA MICROPROCESSOR DATA 
3-17 



MC2672 



FIGURE 12 - INITIALIZATION REGISTER FORMATS (Page 2 of 3) 



7 6 5 4 3 2 1 0 



Interlace 
Enable 


Equalizing Constant 


0=Non- 

Interlace 
1 = Interlace 


0000000=1 CCLK 

0000001=2 CCLK Calculated from: 

• EC = 0.5(H AC t+Hfp + HSYNC+Hbp>-2(HSYNC) 

• ■ ■ ■ 
• 

1111110=127 CCLK 
1111111 = 128 CCLK 



IR2 



IR3 



Not Used 


Horizontal Sync Width 


Horizontal Back Porch 




0000 = 2 CCLK 


000= 1 CCLK 




0001 =4 CCLK 

• 


001 = 5 CCLK 

• ■ 




1110 = 30 CCLK 


110 = 25 CCLK 




1111 = 32 CCLK 


111 = 29 CCLK 



7 6 5 


4 


3 2 1 


0 


Vertical Front Porch 


Vertical Back Porch 


000 = 4 Scan Lines 
001=8 Scan Lines 
• 




00000 = 4 Scan Lines 
00001=6 Scan Lines 
• 




• 

110=28 Scan Lines 
111=32 Scan Lines 




■ • 

11110=64 Scan Lines 
11111=66 Scan Lines 





IR4 



Character 
Blink Rate 


Active Character Rows Per Screen* 


0=1/16 


0000000=1 Row 


VSYNC 


0000001 = 2 Rows 


1 = 1/32 


• 


VSYNC 


• • 
• 




1111110=127 Rows 




1111111 = 128 Rows 



Mo. interlace mode. with odd total character rows per screen the last character row will be the programmed scan lines per 
character row minus one. 



IR5 



Active Characters Per Row 



00000010 = 2 Characters 

00000011 = 4 Characters 



11111110= 255 Characters 
11111111 = 256 Characters 



MOTOROLA MICROPROCESSOR DATA 
3-18 



MC2672 



FIGURE 12 - INITIALIZATION REGISTER FORMATS (Page 3 of 3) 



IR6 



IR8 



7 6 


5 


4 


3 ; 


2 1 


0 


First Line of Cursor 


Last Line of Cursor 


0000= Scan Line 0 
0001 = Scan Line 1 

• 

• 

1110= Scan Line 14 
11 11 = Scan Line 15 


0000= Scan Line 0 
0001 = Scan Line 1 

• 

• 

11 10= Scan Line 14 
1111 = Scan Line 15 


7 6 


5 


4 


3 ' 


2 1 


0 


Light Pen Line 


Cursor 
Blink 


Double 
Height 
Char. 


Underline Position 


00= Scan Line 3 
01 = Scan Line 5 
10t Scan Line 7 
11 1 Scan Line 9 


0=No 
1 = Yes 


0=No 
1 = Yes 


0000= Scan Line 0 
0001 = Scan Line 1 

• 

• 

11 10= Scan Line 14 
1111 = Scan Line 15 


7 6 


5 


4 


3 


2 1 


0 


Display Buffer First Address LSBs 






H"0O0" = 0 
H"001"= 1 

• 

• 


NOTE: MSBs are in IR9I3.0J 








H"FFE" = 4,094 
H"FFF" = 4,095 







1 



7 6 5 4 3 2 1- C 



Display Buffer Last Address 


Display Buffer First Address MSBs 


0000=1,023 




0001 =2,047 




* 
• 


See IR8 


1110=15,359 




1111 = 16,383 





7 6 5 4 3 2 1 0 



Cursor 




Blink 




Rate 


Split-Screen Interrupt Row 


0=1/16 


0000000= Row 0 


VSYNC 


0000001 = Row 1 


1 = 1/32 


• 


VSYNC 






1111110=Row 126 




■1111111 = Row 127 



MOTOROLA MICROPROCESSOR DATA 
3-19 



MC2672 



a 



SCAN LINES PER CHARACTER ROW (IR0[6:31) - Both 
interlaced and non-interlaced scanning are supported by the 
PVTC. For interlaced mode, two different formats can be im- 
plemented, depending on the interconnection between the 
PVTC and the character generator (see IR1[7]). This field 
defines the number of scan lines used to compose a char- 
acter row for each technique. As scanning occurs, the scan 
line count is output on the LA0-LA3 and LI pins. 

VS/CS ENABLE (IR0[2]| - This bit selects either vertical 
sync pulses or composite syne pulses on the VSYNC/ 
CSYNC output (pin 18). The composite sync waveform con- 
forms to EIA RS170 standards, with the vertical interval com- 
posed of six equalizing pulses, six vertical sync pulses, and 
six more equalizing pulses. 

BUFFER MODE SELECT (IR0[1:0]» - Four buffer memory 
modes may be selectively enabled to accommodate the 
desired system configuration. See SYSTEM CONFIGURA- 
TION. 

INTERLACE ENABLE 0R1[7]) - Specifies interlaced or 



non-interlaced timing operation. Two modes of interlaced 
operation are available, depending on whether L0-L3 or LI, 
L0-L2 are used as the line address for the character 
generator. The resulting displays are shown in Figure 13. 

For "interlaced sync" operation, the same information is 
displayed in both odd and even fields, resulting in enhanced 
readability. The PVTC outputs successive line numbers in 
ascending order on the LA0-LA3 lines, one per scan line for 
each field. 

The "interlaced sync and video" format doubles the 
character density on the screen. The PVTC outputs suc- 
cessive line numbers in ascending order on the LI, LA0-LA2 
lines, one per scan line for each field, but alternates begin- 
ning the count with even and odd line numbers. This 
displays the odd field with even scan lines in even character 
rows and odd scan lines in odd character rows, and the even 
field with odd scan lines in even character rows and even 
scan lines on odd character rows. This provides balanced 
beam currents in the odd and even fields, thus minimizing 
character variations due to different loading of the CRT 
anode supply between fields. 



FIGURE 13 - INTERLACED DISPLAY MODES 



t 

Line Address 
To Char. Gen. 



T 

Line Address 
To Char. Gen. 



LI 

LO ■ 
L1 • 
L2 • 
L3 



Line Address 
To Char. Gen. 



9 Scan 
Lines/ 
Row 



0 

1 • 

2 — ■• 

3 — • 

4 — 

5 — • 



17 Scan 
Lines/ 
Row 



7 — « 



0 - 

1 - 

2 — • — ; 

3 — • 

4 — 

5 — • 



Non-interlaced 
IRO=1000; Total Lines/ Row =9 



o 
7 

r o 



0- 



1 T 

2 • 

2- o 

3 — • 

3- o 

4 — 

4 -b-o-o- 

5 — • 

5-o 



o-o-o-o- 



9 Scan 
Lines/ 
Row 



7 

I 8 



— •-•-•-•-« 

7 -o-o-o-o— < 



1 -o-o-o-o— o- 

1 , — 

1 2 - o 

2 — • — 

3- o 

3 — • 

4- 0-0-0 

4 — 

5- o 

5 — « 

6 -o 

6 — • 

7 -o— o— o— o— o- 

7 — 

o 18 



Interlaced Sync 
IR0=01111; Total Lines/Row=17 



O tu 

°i 

'l-ooooo- 
2 — • 

,3-o 

4 — ••• 

1 5-o— — — 



7 -oo o oo- 



2-o 
3'— •• 



J 6-< 
7 — < 



1 - ooooo- 



,3-o- 



>5-o- 



7-00000- 



'2-o 

U-ooo- 
5 — • 



Interlaced Sync and Video 
IR0=0011; Total Lines/Row=9 



MOTOROLA MICROPROCESSOR DATA 
3-20 



MC2672 



EQUALIZING CONSTANT (IR1 [6:0]) - This field indirect- 
ly defines the horizontal front porch and is used internally to 
generate the equalizing pulses for the RS170 compatible 
CSYNC. The value for this field is the total number of char- 
acter clocks (CCLK) during a horizontal line period divided by 
two, minus two times the number of character clocks in the 
horizontal sync pulse: 

ec= hact+Hfp + hsync+h B p _ 2(HSYNC) 

i 2 

The definition of the individual parameters is illustrated in 
Figure 14. The minimum value of Hpp is two character 
clocks. 

Note that whe n using the attributes controller the blank pulse 
is delayed three CCLKs relative to the HSYNC pulse. 



HORIZONTAL SYNC PULSE WIDTH <IR2[6:3]) - This 
field specifies the width of the HSYNC pulse in CCLK 
periods. 

HORIZONTAL BAC K POR CH (IR2[2:0]) - This field 
defines the number of CCLKs between the trailing edge of 
HSYNC and the trailing edge of BLANK. 

VERTICAL FRONT PORCH (IR3[7:51) - Programs the 
number of scan line periods between the rising edges of 
BLANK and VSYNC during a vertical retrace interval. The 
width of the VSYNC pulse is fixed at three scan lines. 



"VERTICAL BACK PORCH {IR3[4:0]| - This field deter- 
mines the number of scan line periods between the falling 
edges of the VSYNC and BLANK outputs. 

CHARACTER BLINK RATE (IR4[7]» - Specifies the fre- 
quency for the character blink attribute timing. The blink rate 
can be specified as 1/16 or 1/32 of the vertical field rate. The 
timing signal has a duty cycle of 75% and is multiplexed onto 
the DADD11/BLINK output at the falling edge of each 
BLANK. 

CHARACTER ROWS PER SCREEN (IR4[6:0D - This field 
defines the number of character rows to be displayed. This 
value multiplied by the scan lines per character row, plus the 
vertical front and back porch values, and the vertical sync 
pulse width (three scan lines) is the vertical scan period in 
scan lines. 

ACTIVE CHARACTERS PER ROW (IR5[7:0]> - This field 
determines the number of characters to be displayed on each 
row of the CRT screen. The sum of this value, the horizontal 
front porch, the horizontal sync width, a nd the horizontal 
back porch is the horizontal scan period is CCLKs. 

FIRST AND LAST SCAN LINE OF CURSOR (IR6[7:4] 
AND IR6[3:0]) - These two fields specify the height and 
position of the cursor on the character block. The "first" line 
is the topmost line when scanning from the top to the bot-. 
torn of the screen. 




FIGURE 14 - HORIZONTAL AND VERTICAL TIMING 



Char/Row 
(IR5) 



HBLANK 



HSYNC 



VBLANK 



-»| |-<- Front Porch (IR1) 



Back Porch (IR2) — >j \+- 



_»J u*_HSYNC (IR2) 

' 1 »-* Char Rows/Screen (IR4)- 



|<-Scan Lines Per Row ( I R0) 



1 



■*\ \<- Front Porch (IR3) 
VSYNC I | 



Back Porch(IR3) -»-) 

TL 



-*f ( - VSYNC (Fixed at 3) 
Lines/ Row 



Equalizing 
Constant 



HSYNC HBACK 
Width Porch 

|R2 1 i i i M m' 

Char. Rows/ Screen 

»* i [ i i i i m 



IR1 



VFRONT . VBACK 
Porch Porch 



IR3 



Characters Per Row 



ir5 i i i i i i i n 



MOTOROLA MICROPROCESSOR DATA 
3-21 



MC2672 



a 



LIGHT PEN LINE POSITION (IR7[7:6]| - This field 
defines which of four scan lines of the character row will be 
used for the light pen strike — through attribute by the 
MC2673 VAC. The timing signal is multiplexed onto the 
DADD9/LPL output during the falling edge of BLANK. 

CURSOR BLINK ENABLE 0R7[5]) - This bit controls 
whether or not the cursor output pin will be blinked at the 
selected rate 0R10[7]). The blinkduty cycle for the cursor is 
50%. 

DOUBLE HEIGHT CHARACTER ROW ENABLE (IR714]) 

- If enabled, the number of each scan line will be repeated 
twice in succession, causing the height of the character row 
to double. This bit can be changed at any time but will only 
become effective at the beginning of the character row fol- 
lowing the time it is changed. This allows selected character 
rows to be of double height. The split-screen interrupt can 
be used to notify the CPU when the effectuate changes to 
this bit. For each double height row which replaces a normal 
row, one row count should be subtracted from the "char- 
acter rows per screen" field (IR4) to maintain the same total 
number of scan lines per field. 

UNDERLINE POSITION (IR7[3:0]j — This field defines which 
scan line of the character row will be used for the underline 
attributes by the attributes controller. The timing signal is mul- 
tiplexed onto the DADD10/UL output during the falling edge 
of BLANK. 

DISPLAY BUFFER FIRST ADDRESS (IR9[3:0] AND 
IR8[7:0]) AND DISPLAY BUFFER LAST ADDRESS 
(IR9t7:4]> - These two fields define the area within the buf- 
fer memory where the display data will reside. When the data 
at the "display buffer last address" is displayed, the PVTC 
will wrap-around and obtain the data to be displayed at the 
next screen position from the "display buffer first address" 



If "last address" is the end of a character row and a new 
screen start address has been loaded into the screen start 
register, or if "last address" is the last character position of 
the screen, the next data is obtained from the address con- 
tained in the screen start register. 

,.' Note that there is no restriction in displaying data from 
other areas of the addressable memory. Normally, the area 
between these two bounds is used for data which can be 
overwritten (e.g., as a result of scrolling), while data that is 
not to be overwritten would be contained outside these 
bounds and accessed by means of the split-screen interrupt 
feature of the PVTC. 

CURSOR BLINK RATE (IR10[7]) - The cursor blink rate 
can be specified at 1/16 or 1/32 of the vertical scan fre- 
quency. Blink is effective only if blink is enabled by I R7[5] . 

SPLIT-SCREEN INTERRUPT (IR10[6:0]) - The split- 
screen interrupt can be used to provide special screen effects 
such as a row of double height characters or to change the 
normal addressing sequence of the display memory. The 
contents of this field is compared, in real time, to the current 
character row number. Upon a match, the PVTC sets the 
split-screen status bit, and issues an interrupt request if so 
programmed. The status change/ interrupt request is made 
at the beginning of scan line zero of the split-screen char- 
acter row. 



TIMING CONSIDERATIONS 

Normally, the contents of the initialization registers are not 
changed during operation. However, this may be necessary 
to implement special display features such as multiple cur- 
sors, smooth scrolling, horizontal scrolling, and double 
height character rows. Table 2 describes the timing details 
for these registers which should be considered when imple- 
menting these features. 



TABLE 2 - TIMING CONSIDERATIONS 



Parameter 


Timing Considerations 


Field Line of Cursor 
Last Line of Cursor 
Light Pen Line 
Underline 


These parameters must be established at a minimum of two characters times 
prior to their occurrence. 


Double Height Characters 


Set/ reset during the character row prior to the row which is to be/ not to be 
double height. 


Cursor Blink 
Cursor Blink Rate 
Character Blink Rate 


New values become effective within one field after values are changed. 


Split-Screen Interrupt Row 


Change anytime prior to line zero of desired row. 


Character Rows Per Screen 


Change only during vertical blanking period. 


Vertical Front Porch 


Change prior to first line of VFP. 


Vertical Back Porch 


Change prior to fourth line after VSYNC. 


Screen-Start Register 


Change prior to the horizontal blanking interval of the last line of character 
row before row where new value is to be used. 



MOTOROLA MICROPROCESSOR DATA 
3-22 



MC2672 



ing registers in the group store address values which specify 
the cursor and buffer pointer locations, the location of the 
first character to be displayed on the screen, and the location 
of a light pen "hit". With the exception of the light pen 
register, the user initializes these registers after powering on 
the system and changes their values to control the data 
which is displayed. 



FIGURE 15 - DISPLAY CONTROL REGISTER FORMATS 

(a) Command Register (Write Only) 

7 6 5 4 3 2 1 0 

Command Code 



Refer to COMMANDS for Command Codes 



(b) Screen Start Registers (Read and Write), 
Cursor Address Registers (Read and Write), 
Pointer Address Register (Write Only), and 
Light Pen Address Register (Read Only) 



7 6 5 4 3 2 1 0 





Upper Register 


Not Used 


MSBs 



DISPLAY CONTROL REGISTERS 



There are nine registers in this group, each with an in- 
dividual address. Their formats are illustrated in Figure 15. 
The command register is used to invoke one of 16 possible 
PVTC commands as described in COMMANDS. The remain- 



Lower Register (LSBs) 
H"0000" = 0 

H"0001" = 1 

NOTE: MSBs are in Upper Register [5:0] 

H"3FFE" = 16,382 
H"3FFF"= 16,383 . 



SCREEN-START REGISTERS 

The screen-start registers contain the address of the first 
character of the first row (upper left corner of the active 
display). At the beginning of the first scan line of the first 
row, this address is transferred to the row-start register 
(RSR) and into the memory-address counter (MAC).- The 
counter is then advanced sequentially at the character rate 
the number of times programmed into the active characters- 
per-row register (iR5) thus reaching the address of the last 
character of the row plus one. At the beginning of each sub- 
sequent scan line of the first row, the MAC is reloaded from 
the RSR and the above sequence is repeated. At the end of 
the last scan line of the first row, the contents of the MAC is 
loaded into the RSR to serve as the starting memory address: 
for the second character row. This process is repeated for 



the programmed number of rows per screen. Thus, the data 
in the display memory is displayed sequentially starting from 
the address contained in the screen start register. After the 
ensuing vertical retrace interval, the entire process repeats 
again. ■ ■ ■■ 

The sequential operation described above will be modified 
upon the occurrence of either of two events. First, if during 
the incrementing of the memory address counter the 
"display buffer last address" (IR9[7:4]l is reached, the MAC 
will be loaded from the "display buffer first address" register 
0R9[3:0]), (IR8[7:0]) at the next character clock. Sequential 
operation will then resume starting form this address. This 
wraparound operation allows portions of the display buffer 
to be used for purposes other than storage of displayable 
data and is completely automatic without any CPU interven- 
tion (see Figure 16a). 



MOTOROLA MICROPROCESSOR DATA 

3-23 



MC2672 



FIGURE 16 - DISPLAY ADDRESSING OPERATION 



Bottom of Screen- 



Screen Start- 



16K 




-Display Buffer Start 



♦-Display Buffer End 




Memory 

(a) Display Memory Wraparound 



Screen Start !-♦> 



Split Screen-! 



Screen Start 2- 




16K 




-Display Buffer Start 



■<-Bbttom of Screen 




Monitor 

-Display Buffer End Display 



Memory 

(b) Display Memory Split Screen With Wraparound 



The sequential row-to-row addressing can also be 
modified under CPU control. If the contents of the screen- 
start register (upper, lower, or both) are changed during any 
character row (say row "n"), the starting address of the next 
character row (row "n+1") will be the next value of the 
screen-start register and addressing will continue sequential- 
ly from there. This allows features such as split-screen 
operation, partial scroll, or status line display to be im- 
plemented. The split-screen interrupt feature of the PVTC is 
useful in controlling this type of operation. Note that in order 
to obtain the correct screen display, the screen-start register 
must be reloaded with the original value prior to the end of 
the vertical retrace. See Figure 16b. 

During vertical blanking the address counter operation is 
modified by stopping the automatic load of the contents of 
the FlSR into the counter, thereby allowing the address out- 
puts to free-run: This allows dynamic memory refresh to oc- 
cur during the vertical retrace interval. The refresh address- 
ing starts at the last address displayed on the screen and in- 
crements by one for each character clock during the retrace 
interval. If the display buffer last address is encountered 
refreshing continues from the display buffer first address. 



CURSOR ADDRESS REGISTERS 

The contents of these registers define the buffer memory 
address of the cursor. If enabled, the cursor output will be 
asserted when the memory address counter matches the 
value of the cursor address registers. The cursor address 
registers may be read or written by the CPU or incremented 
via the "increment cursor address" command. In indepen- 
dent buffer mode, these registers define a buffer memory ad- 
dress for PVTC controlled access in response to "read/write 
at cursor with/without increment" commands, or the first 
address to be used in executing the "write for cursor to 
pointer" command. 

DISPLAY POINTER ADDRESS REGISTERS 

These registers define a buffer memory address for PVTC 
controlled accesses in response to "read/write at pointer" 
commands. They also define the last buffer memory address 
to be written for the "write from cursor to pointer" com- 
mand. 

LIGHT PEN ADDRESS REGISTERS 

If the light pen input is enabled, these registers are used to 



MOTOROLA MICROPROCESSOR DATA 
3-24 



MC2672 



store the current character address upon receipt of a light 
pen strobe input. Several sources of delay between the 
display of a character upon the screen and the receipt of a 
light pen hit can be expected to exist in a system environ- 
ment. These delays include address pipelining in the char- 
acter generation circuits, delays in the video generation cir- 
cuits, and delays in the light detection circuitry itself. These 
delays cause the value stored in the light pen register to dif- 
fer from the actual address of the character at which the light 
pen hit actually was detected. Software must be used to cor- 
rect this condition. 

INTERRUPT/STATUS REGISTERS 

The interrupt and status registers provide information to 
the CPU to allow it to interface with the PVTC to effect 
desired changes to implement various display operations. 
The interrupt register provides information on five possible 
interrupting conditions, as shown in Figure 17. These condi- 
tions may be selectively enabled or disabled (masked) from 
causing interrupts by certain PVTC commands. An interrupt 
condition which is enabled (mask bit equal to one) will cause 
the INTR output to be asserted and will cause the corres- 
ponding bit in the interrupt register to be set upon occur- 
rence of interrupt condition. An interrupt condition which is 
disabled (mask bit equal to zero) has no effect on either the 
INTR output or the interrupt register. 

The status register provides six bits of status information; 
the five possible interrupting conditions plus the NOT BUSY 
bit. For this register, however, the contents are not effected 
by the state of the mask bits. 

Descriptions of each interrupt/ status register bit follows. 
Unless otherwise indicated, a bit, once set, will remain set 
until reset by the CPU by issuing a "reset interrupt/ status 
bits" command. The bits are also reset by a "master reset" 
command and upon power-up. 

RDFLG (SR[5]) - This bit is present in the status register 
only. A zero indicates that the PVTC is currently executing 
the previously issued command. A one indicates that the 
PVTC is ready to accept a new command. 



VBLANK (l/SR[4]) - Indicates the beginning of a vertical 
blanking interval, is set to a one at the beginning of the first 
scan line of the vertical front porch. 

LINE ZERO (l/SR[3]( - Is set to a one at the beginning of 
the first scan line (line zero) of each active character row. 

SPLIT SCREEN (l/SR[21) - This bit is set when a match 
occurs between the current character row number and the 
value contained in the split-screen interrupt register, 
IR10[6:0]. The equality condition is only checked at the 
beginning of line zero of each character row. This bit is reset 
when either of the screen-start registers is loaded by the 
CPU. 

READY (I/SRI11) - Certain PVTC commands affect the 
display and may require the PVTC to wait for a blanking 
interval before enacting the command. This bit is set to one 
when execution of the command has been completed. No 
command should be invoked until the prior command is 
completed. 

LIGHT PEN (l/SR[0]» - A one indicates that a light pen 
hit has occurred and that the contents of the light pen 
register have been updated. This bit will be reset when either 
of the light pen registers is read. 



COMMANDS 

The PVTC commands are divided into two classes: the in- 
stantaneous commands, which are executed immediately 
after they are invoked, and the delayed commands which 
may need to wait for a blanking interval prior to their execu- 
tion. Command formats are shown in Table 3. The com- 
mands are asserted by performing a write operation to the 
command register with the appropriate bit pattern as the 
data byte. 




FIGURE 17 - INTERRUPT AND STATUS REGISTER FORMAT 



7 6 


5 


4 


3 


2 


1 


0 








Line 


Split 




Light 


Not Used 


RDFLG 


VBLANK 


Zero 


Screen 


Ready 


Pen 


Always Read 


0= Busy 


0=No 


0=No 


0=No 


0= Busy 


0=No 


as Zero 


1 = Ready 


1=Yes 


1 = Yes 


1 = Yes 


1 = Ready 


1 = Yes 



MOTOROLA MICROPROCESSOR DATA 
3-25 



MC2672 



TABLE 3 — PVTC COMMAND FORMATS 



a 



D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 


Hex 


Command 


Instantaneous Commands 


0 


0 


0 


0 


0 


0 


0 


0 




Master Reset 


0 


0 


0 


1 


V 


V 


V 


V 




Load IR Pointer with Value V (V = 0 to 10) 


0 


0 




d 


d 


d 


1 


0* 




Disable Light Pen 


0 


0 




d 


d 


d 


1 


1* 




Enable Light Pen 


0 


0 




d 


1 


N 


d 


0* 




Display Off - Float DADD Bus If N = 1 


0 


0 




d 


1 


N 


d 


1* 




Display On - Next Field (N= 1) or Scan Line (N = 0) 


0 


0 




1 


d 


d 


d 


0* 




Cursor Off 


0 


0 




1 


d 


d 


d 


1* 




Cursor On 


0 


1 


0 


N 


N 


N 


N 


N 




Reset Interrupt/ Status - Bit Reset where N = 1 


1 


0 


0 


N 


N 


N 


N 


N 




Disable Interrupt - Disable where N= 1 


0 


1 


1 


N 


N 


N 


N 


N 




Enable Interrupt — Enables Interrupts and Resets the Corresponding 




















Interrupt/Status Bits where N= 1 








V 


L 


S 


R 


L 












B 


Z 


s 


D 


P 






Delayed Commands 


1 


0 




0 


0 


1 


0 


0 


A4 


Reset at Pointer Address 


1 


0 




0 


0 


0 


1 


0 


A2 


Write at Pointer Address 


1 


0 




0 




0 


0 


1 


A9 


Increment Cursor Address 


1 


0 




0 




1 


0 


0 


AC 


Read at Cursor Address 


1 


0 




0 




0 


1 


0 


AA 


Write at Cursor Address , 


1 


0 




0 




1 


0 


1 


AD 


Read at Cursor Address and Increment Address 


1 


0 




0 




0 


1 


1 


AB 


Write at Cursor Address and Increment Address 


1 


0 




1 




0 


1 


1 


BB 


Write from Cursor Address to Pointer Address 



*Any combination of these three commands is valid. 
d= Don't Care 



INSTANTANEOUS COMMANDS 

The instantaneous commands are executed immediately 
after the trailing edge of the write pulse during which the 
command is issued. These commands do not affect the state 
of the RDFLG or READY interrupt/ status bits. However, a 
command should not be invoked if the RDFLG bit is low. 

MASTER RESET 

This command initializes the PVTC and may be invoked at 
any time to return the PVTC to its initial state. Upon power- 
up, two successive master reset commands must be applied 
to release the PVTC's internal power on circuits. In trans- 
parent and shared buffer modes, the CNTRL1 input must be 
high when the command is issued. The command causes the 
following: 

1. VSYNC and HSYNC are driven low for the duration of 
reset and BLANK goes high. BLANK remains high until 
a "display on" command is received. 

2. The interrupt and status bits and masks are set to zero, 
except for the RDFLG flag which is set to a one. 

3. The transparent mode, cursor off, display off, and light 
pen disable states are set. 

4. The initialization register pointer is set to address IRO. 

LOAD IR ADDRESS 

This command is used to preset the initialization register 
pointer with the value "V" defined by D3-D0. Allowable 
values are 0 to 10. 



ENABLE LIGHT PEN 

After invoking this command, receipt of a light pen strobe 
input will cause the light pen register to be loaded with the 
current buffer memory address and the corresponding inter- 
rupt and status flag to be set. Once loaded, further loads are 
inhibited until either one of the light pen registers are read or 
a reset function is performed. 

DISABLE LIGHT PEN 

Light pen hits will not be recognized. 

DISPLAY OFF 

Asserts the BLANK output. The DADD0 through DADD13 
display address bus outputs may be optionally placed in the 
high-impedance state by setting bit 2 to a one when invoking 
the command. 

DISPLAY ON 

Restores normal blanking operation either at the beginning 
of the next field (bit 2=1) or at the beginning of the next 
scan line (bit 2 = 0). Also returns the DADD0-DADD13 
drivers to their active state. 

CURSOR OFF 

Disables cursor operation. Cursor output is placed in the 
low state. 

CURSOR ON 

Enables normal cursor operation. 



MOTOROLA MICROPROCESSOR DATA 
3-26 



MC2672 



RESET INTERRUPT/ STATUS BITS 

This command resets the designated bits in the interrupt 
and status registers. The bit positions correspond to the bit 
positions in the registers: 



Bit 0 - Light Pen 
Bit 1 - Ready 
Bit 2 - Split Screen 
Bit 3 - Line Zero 
Bit 4 - Vertical Blank 



DISABLE INTERRUPTS 

Sets the interrupt mask to zeros for the designated condi- 
tions, thus disabling these conditions from asserting the 
INTR output. Bit position correspondence is as above. 



ENABLE INTERRUPTS 

Resets the selected interrupt and status register bits and 
writes the associated interrupt mask bits to a one. This 
enables the corresponding conditions to assert the INTR out- 
put. Bit position correspondence is as above. 

DELAYED COMMANDS 

This group of commands is utilized for the independent 
buffer mode of operation, although the "increment cursor" 
command can also be used in other modes. With the excep- 
tion of the "write from cursor to pointer" and "increment 
cursor" commands, all the commands of this type will be 
executed immediately or will be delayed depending 6n when 
the command is invoked. If invoked during the active screen 
time, the command is executed at the next horizontal blank- 
ing blanking interval. If invoked during a vertical retrace in- 
terval or a "display off" state, the command, is executed im- 
mediately. 



MECHANICAL DATA 



ORDERING INFORMATION (T A = 0°C to 70°C) 



PIN ASSIGNMENTS 



Package Type 


Frequency 


Order Number 


Plastic 
P Suffix 


2.7 MHz 
4.0 MHz 


MC2672B3P 
MC2672B4P 



RI 

CE[ 
W.I 
CTRL1 [ 
CTRL2 I 
CTRL3 [ 
CURSOR [ 
DO I 
D1[ 
D2t 
D3[ 
D4[ 
D5[ 
D6[ 
D7t 
CCLK[ 

blank! 

VSYNC/f 
CSYNC 1 
HSYNC[ 

GND[ 



]v C c 

]A2 
]A1 
]A0 
]LPS 
]TNTR 
]DADD0 
33 ]DADD1 



]DADD2 

]DADD3/LI 

1DADD4/LA0 

1DADD5/LA1 

]DADD6/LA2 

JDADD7/LA3 

]DADD8/LNZ 

IDADD9/LPL 

1DADD10/UL 
iDADDII 
/BLINK 
1DADD12/ 
J ODD 

]DADD13/LL 



MOTOROLA MICROPROCESSOR DATA 
3-27 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 



MC2674 



Advance Information 

Advanced Video Display Controller (AVDC) 

The MC2674 advanced video display controller (AVDC) is a programmable device designed for 
use in CRT terminals and display systems that employ raster-scan techniques. The AVDC generates 
the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced 
data on a CRT monitor. It provides consecutive addressing to a user specified display buffer mem- 
ory domain and controls the CPU-display buffer interface for various buffer configuration modes. A 
variety of operating modes, display formats, and timing profiles can be implemented by program- 
ming the control registers in the AVDC. 

A minimum CRT terminal system configuration consists of an AVDC, a keyboard controller, an 
asynchronous communications interface adapter, character ROM, and an attributes controller. Other 
necessary parts of the system are a single-chip microcomputer such as the MC6809, display buffer 
RAM, and a small amount of TTL for miscellaneous address decoding, interface, and control. Sys- 
tem complexity can be enhanced by upgrading the microprocessor and expanding via the system 
address and data buses. 

• 4 MHz Character Rate 

• 1 to 256 Characters Per Row 

• 1 to 16 Raster Lines Per Character Row 

• Bit Mapped Graphics Mode 

• Programmable Horizontal and Vertical Sync Generators 

• Interlaced or Non-interlaced Operation 

• Up to 64K RAM Address for Multiple-Page Operation 

• Readable, Writeable, and Incrementable Cursor 

• Programmable Cursor Size and Blink 

• AC Line Lock 

• Automatic Wraparound of RAM 

• Automatic Split Screen 

• Automatic Bidirectional Soft Scrolling 

• Programmable Scan Line Increment 

• Row Table Addressing Mode 

• Double Height Tops and Bottoms 

• Double Width Control Output 

• Selectable Buffer Interface Modes 

• Dynamic RAM Refresh 

• Completely TTL Compatible 

• Single +5-Volt Power Supply 

• Power-On Reset Circuit 

• Applications Include: CRT Terminals, Word Processing Systems, Small Business Computers, 
and Home Computers 



This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-28 



MC2674 



BLOCK DIAGRAM 



CE 



Interface 



Read/ 
Write 
Control 
Logic 



Address 
Decoder 



INTR 



D0-D7 



CO 



Data 
Bus 
Drivers 



VCC 
GND 



CCLK 



Clock 
Buffer 



7X 



Timing 



Control 




Initialization, 






Pointer . 






and 






Display 






Registers 








Command 






Decode 






Logic 








Interrupt 






Logic 






Status 






Register 







CTRL1 




0 



Timing Chain 

and 
Decode Logic 



Display 




Scroll and 






Double Height 






Logic 








Address 






Timing 






Multiplexers 








Cursor and 






Screen Start 






Registers 








Cursor 






and 






Compare 






Logic 







DADD0-DADD13 



Cursor 




ACLL 



VSYNC/CSYNC 



BLANK 



MOTOROLA MICROPROCESSOR DATA 
3-29 



MC2674 



ABSOLUTE MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


vcc 


-0.3 to +7.0 


V 


Input Voltage 


V in 


-0.3 to +7.0 


V 


Operating Temperature Range 


T A 


0 to 70 


°c 


Storage Temperature Range 


T stg 


-55 to +150 


°c 


THERMAL CHARACTERISTICS 


Characteristic 


Symbol 


Value 


Rating 


Thermal Resistance 
Plastic Package 


»ja 


50 


°C/W 



This device contains circuitry to pro- 
tect the inputs against damage due to 
high static voltages or electric fields; 
however, it is advised that normal pre- 
cautions be taken to avoid application 
of any voltage higher than maximum- 
rated voltages to this high-impedance 
circuit. For proper operation it is rec- 
ommended that Vj n and V ou t be con- 
strained to the range GNDs(Vj n or 
V ou t)*sVcc- Reliability of operation is 
enhanced if unused inputs are tied to 
an appropriate logic voltage level (e.g., 
either GND or Vcc)- 



POWER CONSIDERATIONS 



The average chip-junction temperature, Tj, in °C can be obtained from: 

T j = T A +{P D .6 JA ) 



(1) 



where: 

T A 

0JA 

PD 

p int 

PPORT 



= Ambient Temperature, °C 

= Package Thermal Resistance, Junction-to-Ambient, °C/W 
= P|NT +p PORT 

= \qq x Vcc, Watts — Chip Internal Power 

= Port Power Dissipation, Watts — User Determined 



For most applications PpORT <p INT and can be ne 9 lected - p PORT mav become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pp and Tj (if PpoRT IS neglected) is: 

P D = K+(Tj + 273°C) (2) 

Solving equations (1) and (2) for K gives: 

K = P D • (T A + 273°C) + 0j A'PD 2 < 3 > 
where K is a constant pertaining to the particular part, K can be determined from equation (3) by measuring Pp (at 
equilibrium) for a known T A . Using this value of K, the values of Pp and Tj can be obtained by solving equations 
(1) and (2) iteratively for any value of T A 

DC ELECTRICAL CHARACTERISTICS (T A = 0°C to 70°C, V C c = 5.0 V±5%) 



Parameter 


Symbol 


Min 


Max 


Unit 


Input Low Voltage 


VlL 


-0.3 


0.8 


V 


Input High Voltage 


V|H 


2.0 


vcc 


V 


Output Low Voltage (Iol = 2 4 mAI 


vol 




0.4 


V 


Output High Voltage (Except INTR Output) (Ioh= -200 ^A) 


VOH 


2.4 




V 


Input Leakage Current (Vj n = 0 to Vcc' 


■in 


-10 


10 


fA 


Hi-Z (Off-State) Leakage Current (V C c = 5.25 V, V in = 0.4 to 2.4 V) 


'TSI 


-10 


10 


M A 


INTR Open-Drain Output Leakage Current (Vo = 0 to Vcc) 


!OD 




10 


/*A 


Internal Power Dissipation (Measured at Ta=0°C) 


pint 




800 


mW 



MOTOROLA MICROPROCESSOR DATA 
3-30 



MC2674 



AC ELECTRICAL CHARACTERISTICS - BUS TIMING (T A = 0°C to 70°C. V C c = 5 V±5%> 



Parameter 


Symbol 


2.7 MHz 


4.0 MHz 


Unit 


Mm 


Max 


Min 


Max 


A0-A2 Setup Time to W, R Low 


l AS 


30 




30 




ns 


A0-A2 Hold Time from W. E High 


t.AH 


0 




0 




ns 


C~E Setup Time to W, R Low 


tcs 


0 


- 


0 


- 


ns 


CE Hold Time from W, R High 


'CH 


0 




0 




ns 


w, n ruise wioin 


l RW 


250 




200 




ns 


Data Valid after R Low 


'DD 




200 




200 


ns 


Data Bus Floating after R High 


l DF 




100 




100 


ns 


Data Setup Time to W High 


«DS 


150 




150 




ns 


Data Hold Time from W High 


l DH 


10 




5 




ns 


High Time from C'E to CT 
Consecutive Commands 
Other Accesses 


tec 


tCCP 
300 




l CCP 
300 




ns 
ns 



A0-A2 



D0-D7 
(Read) 



W 



D0-D7 
(Write) 



CE, R, W.1 



BUS TIMING DIAGRAM 



=3 



tAS 



l CS 



Float 



\ 



X 



-IRW- 



-tDD- 



XEEEX- 



7 



- l DS- 



/ 



X 



Valid 



J' 



tAH 



tCH 



-tDF- 



X 



-'DH 



X 




Float 



- l CC- 



NOTES: 

1. Any two must be high for trje- 

2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 
3-31 



MC2674 



AC ELECTRICAL CHARACTERISTICS - CHARACTER CLOCK (CCLK) TIMING (T A =0°C to70.°C, V C c = 5 V±5%) 







2.7 MHz 


4.0 MHz 




Parameter 


Symbol 


Min 


Max 


Min 


Max 


Unit 


CCLK Period 


tCCP 


370 


10000 


250 


10000 


ns 


CCLK High Time 


tCCH 


125 




100 




ns 


CCLK Low Time 


l CCL 


125 




100 




ns 


Output Delay Time from CCLK Edge 
DADDO-13, MBC 

BLANK, HSYNC, VSYNC/CSYNC, CURSOR, BEXT, BREQ, 
BACK, BCE, WDB, RDB* 


tCCD1 
ICCD2 ! 


40 
40 


175 
225 


40 
40 


■ . 150 
200 


ns 
ns 



* BCE, WDB, and RDB delays track each other within 10 nanoseconds. Also, these output delays will tend to follow direction (minimum/ max- 
imum) of DADD0-DADD13 delays. 



CCLK TIMING DIAGRAM 



- l CCP- 



CCLK 



Outputs 
(Note!) 



Outputs WDB, 
RDB, BC~E 



/ \ / \ 

<CCD1 (<_t C CL— H 
tCCD2- 



5t 



-tCCH- 



tCCD2 



X 



NOTES: _ 

1. DADD0-DADD13, BLANK, H SYNC , CSYNC/VSYNC, CURSOR, BEXT, BREQ, BCE, MBC, BACK. 

2. BCE changes state on both CCLK edges. 

3. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



AC ELECTRICAL CHARACTERISTICS - OTHER TIMING (T A = 0°C to 70°C, V C c = 5 V ± 5%) 







2.7 MHz 


4.0 MHz 




Parameter 


Symbol 


Min 


Max 


Min 


Max 


Unit 


READY/RDFLG low from W High* 


l RDL 




tCCP + 30 




tCCP + 30 


ns 


BACK High from PBREQ Low 


tBAK 




225 




200 


ns 


BEXT High from PBREQ High 


tBXT 




225 




200 


ns 


INTR Low from CCLK Low 


t|RL 




225 




200 


ns 


INTR High from W, R High* 


t|RH 




600 




600 


ns 


ACLL from HSYNC 


tAC 


3xtCCP 




3xt C CP 




ns 



*Timing is illustrated and specified referenced to W and R inputs. Device may also be operated withCE as the "strobing" input. In 
this case, all timing specifications apply referenced to falling and rising edges of CE. 



MOTOROLA MICROPROCESSOR DATA 
3-32 



MC2674 



OTHER TIMING DIAGRAMS (Sheet 2 of 2) 




BLANK 



HSYNC 



VBLANK Status Bit 



st HSYNC 
VBLANK 



/ 



-t|R'L-*" 



\ 



CCLK 



BLANK 



■tCCD1- 



tCCD2" 



Honzonta 
Blanking 
Interval 



DADD0-DADD13 



Line Zero and Split 
Screen Status Bits 



X 



\ 



tCCDT 



Multiplexed 
Signals Valid 



Address of 
1st Character 
of Row 



>CDC 



/ 



-«IRL- 



INTR 



NOTE: All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 

3-33 



MC2674 



OTHER TIMING DIAGRAMS (Sheet 2 of 2) 



HSYNC 



BLANK 



_JUlvfLJT_JLJLJL_rL_ 



Normal VSYNC (ACLL= 1 ) 



ACLL 



Delayed VSYNC 



W for a Delayed Command 



READY or RDFLG Status Bits 



PBREQ 



BACK 



BEXT 



W or R Which Resets Interrupt 



TNTR 



^ - Vpp = n Scan Lines 



■tAC 



-Vpp= n + 3 Scan Lines > 



< <RDL 



V- W 





< > 

/ 


-tBAK ■ 
!— * 





tBXT 



■* — *> 



'IRH 



J 



NOTE: All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 
3-34 



MC2674 



AC ELECTRICAL CHARACTERISTICS - ROW TABLE INPUT TIMING <T A = 0°C to 70°C, V C c = 5 V±5%) 



Parameter 


Symbol 


2.7 MHz 


4.0 MHz 


Unit 


Min 


Max 


Min 


Max 


Data Setup Time to CCLK Low 


l DSRT 


100 




60 




ns 


Data Hold Time from CCLK Low 


tDHRT 


60 




60 




ns 



ROW TABLE FETCH I/O TIMING DIAGRAM 

Latch D0-D7 Into Latch D0-D7 Into 
SSR1 Lower SSR1 Upper 



CCLK 



BLANK 



MBC 



CURSOR 



DADD 



D0-D7 



"1 



l CCD1 



tCCD2 • 



tCCD1 



r 



\ 



1 !SS y ^ SSR2 Address 




tDSRT" 



X 









< 'DSRT 




^DHRT-J 




<-<DHRT-W 


f Row Start "\> 


f" Row Start 



Address Lower /\ Address Upper 



NOTE: All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



Even Field 

Last Displayed 
Scan of 
Previous Field 



COMPOSITE SYNC TIMING DIAGRAM 



CSYNC 



BLANK 



-Vertical Front Porch - 



^Vertical SYNC PulseJ 



-Vertical Back Porch- 



First Displayed Scan 
of Even Field 

Horizontal 
SYNC 
Pulses 



llJVLJLJLJUUUUl^ 

-j — N — N— i 



'J 



-Vertical Blanking Interval- 



Odd Field 

Last Displayed 
Scan of 
Even Field 



CSYNC 



JU 



-Vertical Front Porch - Vfc H • 



(Vertical SYNC Pulse* 



• Vertical Back Porch - V4 H- 
— V4 H 



First Displayed 
Scan of 
Odd Field 



JlliUULMMJ^^ 

Vi Horizontal SYNC > <- 

r-\ — V 



■ H Period 



-Vertical Blanking Interval- 



NOTES: 

1. In non-interlaced operation the even field is repeated continuously. 

2. In interlaced operation the even field alternates with the odd field. 



Horizontal Blanking Interval 



MOTOROLA MICROPROCESSOR DATA 
3-35 



MC2674 



SIGNAL DESCRIPTION 

The input and output signals for the AVDC are described 
in the following paragraphs; 

ADDRESS LINES (A0-A2) 

These input lines are used to select AVDC internal register 
for read/ write operations and for commands. 

DATA BUS (D0-D7) 

The 8-bit bidirectional three-state data bus controls all 
data, command, and status transfers between the CPU and 
the AVDC. Bit 0 is the least significant bit and bit 7 is the 
most significant bit. The direction of the transfer is- con- 
trolled by the read (R) and write (W) inputs when chip enable 
(CE) input is low. When the C~E input is high, the data bus is 
in the three-state condition. 

READ STROBE (R) 

This pin is an active low input. A low on this pin while CE 
is low causes the contents of the register selected by the ad- 
dress lines to be placed on the data bus. The read cycle 
begins on the leading (falling) edge of R. 

WRITE STROBE (W) 

This is an active low input. A low on this pin while CE is 
also low causes the contents of the data bus to be transfer- 
red to the register selected by the address lines. The transfer 
occurs on the trailing (rising) edge of W. 

CHIP ENABLE (CE) 

This is an active low input. When low, data transfers bet- 
ween the CPU and the AVDC are enabled on the data bus as 
controlled by the write strobe, read strobe, and address 
lines. When CE is high, effectively, the AVDC is isolated 
from the data bus and D0-D7 are placed in the three-state 
condition. 

CHARACTER CLOCK (CCLK) 

This input is the timing signal derived from the video dot 
clock which is used to synchronize the AVDC's timing func- 
tions. 

HORIZONTAL SYNC (HSYNC) 

This active high output provides video horizontal sync 
pulses. The timing parameters are programmable. 

VERTICAL SYNC/COMPOSITE SYNC (VSYNC/CSYNC) 

A control bit selects either vertical or composite sync 
pulses on this active high output. When CSYNC is selected, 
equalization pulses are included. The timing parameters are 
programmable. 

BLANK (BLANK) 

This active high output defines the horizontal and vertical 
borders of the display. Display control signals which are out- 
put on display addresses DADDO and DADD3 through 
DADD13 are valid on the trailing edge of BLANK. 



CURSOR GATE (CURSOR) 

This output becomes active for a specified number of scan 
lines when the address continued in the cursor register 
matches the address output on DADDO through DADD13 for 
displayable character addresses. The first and last lines of the 
cursor and a blink option are programmable. When the row 
table addressing mode is enabled, this output is active for a 
portion of the blanking interval prior to the first scan line of a 
character row, while the AVDC is fetching the starting ad- 
dress for that row. 

INTERRUPT REQUEST (WfR) 

This is an open-drain output which supplies an active low 
interrupt request from any of five maskable sources. This pin 
is inactive after a power-on reset or a master reset command . 

AC LINE LOCK (ACLL) 

If this input is low after the programmed vertical front 
porch interval, the vertical front porch will be lengthened by 
increments of horizontal scan line times until this input goes 
high. 

HANDSHAKE CONTROL 1 (CTRL1) 

In independent mode, provides an active low write data 
buffer (WDB) output which strobes data from the interface 
latch into the display memory. In transparent an d shared 
modes, this is an active low processor bus request (PBREQ) 
input which indicates that the CPU desires to access the 
display memory. 

HANDSHAKE CONTROL 2 (CTRL2) 

In independent mode, provides an active low read data 
buffer (RDB) output which strobes data from the display 
memory into the interface latch. In transparent and shared 
modes, this is an active low bus external enable (BEXT) out- 
put which indicates that the AVDC has relinquished control 
of the display memory (DADD0-DADD13 are in the three- 
state condition) in response to a CPU bus request. BEXT 
also goes low in response to a 'display off and float DADD' 
comma nd. In row buffer mode, it is an active low bus re- 
quest (BREQ) output which halts the CPU during a line 
DMA. 

HANDSHAKE CONTROL 3 (CTRL3) 

In ind epen dent mode, provides the active low buffer chip 
enable (BCE) signal to the display memory. In transparent 
and sha red modes, provides an active low bus acknowledge 
(BACK) output which serves as a ready signal to the CPU in 
response to a processor bus request. In row buffer mode, 
this is an active high memory bus control (MBC) output 
which configures the system for the DMA transfer of one 
row of character codes from system memory to the row 
display buffer. 

DISPLAY ADDRESS (DADD0-DADD13) 

.These outputs are used by the AVDC to address up to 16K 
of display memory directly; or to 64K of memory by demulti- 
plexing DADD14 and DADD15. These outputs are floated at 
various times depending on the buffer mode. Various control 



MOTOROLA MICROPROCESSOR DATA 
3-36 



MC2674 



signals are multiplexed on DADDO through DADD13 and are 
valid at the trailing edge of BLANK. The following para- 
graphs describes the control signals. 

LINE GRAPHICS (DADDO/LG) - This is the output 
which denotes bit-mapped graphics mode. 

DISPLAY ADDRESS 14 (DADD1/DADD14) - This is the 
multiplexed address bit used to extend addressing to 64K. 

DISPLAY ADDRESS 15 (DADD2/DADD15) - This is the 
multiplexed address bit used to extend addressing to 64K. 

LAST ROW (DADD3/ LR) - This is the output which indi- 
cates the last active character row of each field. 

LINE ADDRESS (DADD4-DADD7/LA0-LA3) - These 
outputs provide the number of the current scan line count 
for each character row. 

FIRST LINE (DADD8/FL) - This output is asserted dur- 
ing the blanking interval just prior to the first scan line of 
each character row. 

DOUBLE WIDTH (DADD9/DW) - This output denotes a 
double width character row. 

UNDERLINE (DADD10/UL) - This output is asserted 
during the blanking interval just prior to the scan line which 
matches the programmed underline position (line 0 through 
15). 

BLINK FREQUENCY (DADD11/BLINK) - Blink fre- 
quency provides an output divided down from the vertical 
sync rate. 

ODD FIELD (DADD12/ODD) - This active high signal is 
asserted before each scan line of the odd field when interlace 
is specified. Replaces DADD4/LA0 as the least significant 
line address for interlaced sync and video applications. 

LAST LINE (DADD13/LL) - This output is asserted dur- 
ing the blanking interval just prior to the last scan line of each 
character row. 

Vcc AND GND 

Power is supplied to the AVDC using these two pins. Vqc 
is the +5 volts +5% power input and GND is the ground 
connection. 

FUNCTIONAL DESCRIPTION 

As shown in the block diagram, the AVDC contains the 
following major blocks: data bus buffer, interface logic, 
operation control, timing, display control, and buffer con- 



TABLE 1 - AVDC ADDRESSING 



A2 


A1 


AO 


Read (R = 0) 


Write (W = 0) 


0 


0 


0 


Interrupt Register 


Initialization Registers* 


0 


0 


1 


Status Register 


Command Register 


0 


1 


0 


Screen Start 1 Lower Register 


Screen Start 1 Lower Register 


0 


1 


1 


Screen Start 1 Upper Register 


Screen Start 1 Upper Register 


1 


0 


0 


Cursor Address Lower Register 


Cursor Address Lower Register 


1 


0 


1 


Cursor Address Upper Register 


Cursor Address Upper Register 


1 


1 


0 


Screen Start 2 Lower Register 


Screen Start 2 Lower Register 


1 


1 


1 


Screen Start 2 Upper Register 


Screen Start 2 Upper Register 



•There are 15 initialization registers which are accessed sequentially via a single address. 
The AVDC maintains an internal pointer to these registers which is incremented after 
each write at this address until the last register (IR14) is accessed. The pointer then con- 
tinues to point to IR14 for additional accesses. Upon a power-on or a master reset com- 
mand, the internal pointer is reset to point to the first register (IRO) of the initialization 
register group. The internal pointer can also be preset to any register of the group via the 
'load IR address pointer' command. 



trol. The major blocks are described in the following 
paragraphs. 

DATA BUS BUFFER 

The data bus buffer provides the interface between the ex- 
ternal and internal data buses. It is controlled by the opera- 
tion control block to allow read and write operations to take 
place between the controlling CPU and the AVDC. 

INTERFACE LOGIC 

The interface logic contains address decoding and read 
and write circuits to permit communications with the 
microprocessor via the data buffer. The functions performed 
by the CPU read and write operations are shown in Table 1 . 

OPERATION CONTROL 

The operation control section decodes configuration and 
operation commands from the CPU and generates ap- 
propriate signals to other internal sections to control the 
overall device operation. It contains the timing and display 
registers which configure the display format and operating 
mode, the interrupt logic, and the status register which pro- 
vides operational feedback to the CPU. 

TIMING 

The timing section contains the counters and decoding 
logic necessary to generate the monitor timing outputs and 
to control the display format. These timing parameters are 
selected by programming of the initialization registers. 

DISPLAY CONTROL 

The display control section generates linear addressing of 
up to 16K bytes of display memory. Internal comparators 
limit the portion of the memory which is displayed to pro- 
grammed values. Additional functions performed in this sec- 
tion include cursor positioning and address comparisons re- 
quired for generation of timing signals, double-height tops 
and bottoms, smooth scrolling, and the split-screen inter- 
rupts. 

BUFFER CONTROL 

The buffer control section generates three signals which 
control the transfer of data between the CPU and the display 
buffer memory. Four system configurations requiring four 
different 'handshaking' schemes are supported. These are 
described in SYSTEM CONFIGURATIONS. 



MOTOROLA MICROPROCESSOR DATA 

3-37 



MC2674 



SYSTEM CONFIGURATIONS 

Figure 1 illustrates the block diagram of a typical display 
terminal that uses an MC2674, character ROM, a keyboard in- 
terface, and an attribute controller. In this system, the CPU 
examines inputs from the data communications line and the 
keyboard and places the data to be displayed in the display 
buffer memory. This bufferis typically a RAM which holds the 
data for a single or multiple screenload (page) or for a single 
character row. 

The AVDC supports four common system configurations 
of display-buffer memory, designated the independent, 
transparent, shared, and row-buffer modes. The frst three 
modes utilize a single or multiple page RAM and differ 
primarily in the means used to transfer display data between 
the RAM and the CPU. The row-buffer mode makes use of a 
single row buffer (which can be a shift register or a small 
RAM) that is updated in real time to contain the appropriate 
display data. 

The user programs IRO bits 0 and 1 select the mode best 
suited for the system environment. The CTRL1, CTRL2, and 
CTRL3 outputs perform different functions for each mode and 
are named accordingly in the description of each mode. 



INDEPENDENT MODE 

The CPU-to-RAM interface configuration for this mode is 
illustrated in Figure 2. Transfer of data between the CPU and 
display memory is accomplished via a bid irecti onal latched 
port an d is c ontrolled by read data bu ffer ( RDB), write data 
buffer (WDB), and buffer chip enable (BCE). This mode pro- 
vides a non-contention type of operation that does not re- 
quire address multiplexers. The CPU does not address the 
memory directly — the read or write operation is performed 
at the address contained in the cursor address register or the 
pointer address register as specified by the CPU. The AVDC 
enacts the data transfers during blanking intervals in order to 
prevent visual disturbances of the displayed data. 

The CPU manages the data transfers by supplying com- 
mands to the AVDC. The commands used are: 

1. Read/write at pointer address, 

2. Read/write at cursor address (with optional increment 
of address), and 

3. Write from cursor address to pointer address. 
The operational sequence for a write operation is: 

1. CPU checks RDFLG status bit to assure that any de- 
layed commands have been completed. 

2. CPU loads data to be written to display memory into the 
interface latch. 

3. CPU writes address into cursor or pointer registers. 

4. CPU issues "write at cursor with/without increment" 
or "write at pointer" command. 

5. AVDC generates control signals and outputs specified 
address to perform requested operation. Data is copied 
from the interface latch into the memory. 



6. AVDC sets RDFLG status to indicate that the write is 
completed. 

Similarly, a read operation proceeds as follows: 

1 . Steps 1 . and 3. as above. 

2. CPU issues "read at cursqr with/ without increment", or 
"read at pointer" command. 

3. AVDC generates control signals and outputs specified 
address to perform requested operation. Data is copied 
from memory to the interface latch and AVDC sets 
RDFLG status to indicate that the read is completed. 

4. CPU checks RDFLG status to see if operation is com- 
pleted. 

5. CPU reads data from interface latch. 

Loading the same data into a block of display memory is 
accomplished via the "write from cursor to pointer" com- 
mand: 

1. CPU checks RDFLG status bit to assure that any de- 
layed commands have been completed. 

2. CPU loads data to be written to display memory into the 
interface latch! 

3. CPU writes beginning address of memory block into 
cursor address register and ending address of block into 
pointer address register. 

4. CPU issues "write from cursor to pointer" command. 

5. AVDC generates control signals and outputs block ad- 
dresses to copy data from the interface latch into the 
specified block of memory. 

6. AVDC sets RDFLG status to indicate that the block 
write is completed. 

Similar sequences can be implemented on an interrupt 
driven basis using the READY interrupt output to advise the 
CPU that a previously asserted delayed command has been 
completed. 

Two timing sequences are possible for the "read/write at 
cursor/ pointer" commands. If the command is given during 
the active display window (defined as first scan line of the 
first character row to the last scan line of the last character 
row), the operation takes place during the next horizontal 
blanking interval, as illustrated in Figure 3. If the command is 
given during the vertical blanking interval, or while the 
display has been commanded blanked, the operation takes 
place immediately. In the latter case, the execution time for 
the command is approximately five character clocks (see 
Figure 4). 

Timing for the "write from cursor to pointer" operation is 
shown in Figure 5. The memory is filled at a rate of one loca- 
tion per two character times. The command will execute only 
during blanking intervals and may require many horizontal or 
vertical blanking intervals to complete. Additional delayed 
commands can be asserted immediately after this command 
has completed. 

Immediately commands can be asserted at any time 
regardless of the state of the ready state/interrupt. 



MOTOROLA MICROPROCESSOR DATA 
3-38 



FIGURE 1 - CRT TERMINAL BLOCK DIAGRAM 



MC2674 



Double 
Height 
Logic 



Timing 
Chain 



Cursor 
Logic . 



Soft 
Scroll 
Logic 



SYNC 
Generator 



Memory 
Control 



CPU 



c 



31 



Timing SYNC 



Character 
ROM 



7S 



7^ 



Program 
Memory 



Keyboard 
Interface 



Data Comm 
Interface 



Keyboard 



Line Drivers 
and Receivers 



Modem 



Clock 
Generator 



0 



Video 
Shift 
Register 



V 



Attributes 
and 
Color 
Logic 




Double 
Width 
and 
Dot 
Modulation 
Logic 



Video, 
Control 



Attribute Controller 



Data Communications Line 



Monitor 



2 

O 

■P. 




MC2674 



FIGURE 2 - INDEPENDENT BUFFER MODE CONFIGURATION 




Display Address 



BCE 



WDB 



RDB 



CP SN74LS364 
OE 



1Z 



R - 

From CPU 



Refresh 
RAM 

ADR 




Display Data Bus 



OE 

CP SN74LS364 



System Data Bus 



Video 
Logic 



CCLK 



FIGURE 3 - READ/WRITE AT CURSOR/ POINTER COMMAND TIMING 
(Command Received During Active Display Window) 



CE 



W 

BLANK 
DADD 
RDB 
WDB 
BCE 



V 



"y — y — y-Arv-^Y 

_A A A IV I Address A 

Nr— 



Horizontal Blanking 

Interval AVDC Control Signals 



Cursor or 
Pointer Address 



..A 



| k' 1 ' "^•^^ HviA,uimniion)i M » Addres s 
I - * Refresh ^ 



Refresh 
Addresses 



NOTES: 

1. Write waveforms shown in dotted lines. 

2. If command execution occurs just prior to the first scan line of a character row and row table addressing mode is enabled, 
execution of the command is delayed by two character clocks from the timing illustrated. 

3. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 
3-40 



MC2674 



FIGURE 4 - READ/WRITE AT CURSOR/ POINTER COMMAND TIMING 
(Command Received While Display Is Blanked) 









ce\J 




h 






h 



BLANK 



DADD 



AVDC Read Command 



RDB 



BCE 



Address \ 

^ Refresh ^. i N Refresh. ; ^ 

Addresses K A ddresses 

\ I Nl 



AVDC Write Command 
Address 



'l_J~~ 
PL-TV 



NOTE: All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



SHARED AND TRANSPARENT BUFFER MODES 

In these modes, the display buffer RAM is a part of the 
CPU memory domain and is addressed directly by the CPU. 
Both modes use the same hardware configuration with the 
CPU accessing the display buffer via three-sta te drivers (see 
Figure 6). The processor bus request (PBREQ) control signal 
informs the AVDC that the CPU is requesting access to the 
display buffer. In r espons e to this request, the AVDC raises 
bus acknowledge (BACK) until its bus external (BEXT) out- 
put h as freed the display address and data buses for CPU ac- 
cess. BACK, which can be used as a "hold" input to the 
CPU, is then lowered to indicate that the CPU can access the 
buffer. 

In transparent mode, the AVDC delays the granting of the 
buffer to the CPU until a vertical or horizontal blanking inter- 
val, thereby causing minimum disturbance of the display. In 
shared mode, the AVDC will blank the display and grant im- 
mediate access to the CPU. Timing for these modes is il- 
lustrated in Figures 7, 8, and 9. 

ROW BUFFER MODE 

Figures 10 and 11 show the timing and a typical hardware 
implementation for the row buffer mode. During the first 
scan line (line 0) of each character row, the AVDC halts the 
CPU and DMA's the next row of character data from the 
system memory to the row buffer memory. The AVDC then 
releases the CPU and displays the row buffer data for the 
programmed number of scan lines. The control signal BREQ 
informs the CPU that character addresses and the MBC 
signal will start at the next falling edge of BLANK. The CPU 
must release the address and data buses before this time to 
prevent bus contention . After the row of character data is 
transferred to the CPU, BREQ returns high to grant memory 
control back to the CPU. 



ROW TABLE ADDRESS MODE 

In this mode, each character row in the screen image 
memory has a unique starting address. This provides greater 
flexibility with respect to screen operations, such as editing, 
than the sequential addressing mode. The row table. Figure 
12, is a list of starting addresses for each character row and 
may reside anywhere in the AVDC's addressable memory 
space. Each entry in the table consists of two bytes: the first 
byte contains the eight least significant bits of the row start- 
ing address and the second byte contains, in its six least 
significant bits, the six most significant bits of the row start- 
ing address. The function of the two most significant bits of 
the second byte is selected by programming IR0[7] . They 
may be used either as row attribute bits to control double 
width and double height for that character row, or as an ad- 
ditional two address bits to extend the usable display 
memory to 64K. 

The first address of the row table operation is designated 
in screen start register 2 (SSR2). If row table addressing is 
enabled via IR2[7], the AVDC fetches the next row's starting 
address from the table during the blanking interval prior to 
the first scan line of each character row, while simul- 
taneously incrementing the contents of SSR2 by two so as 
to point to the next table entry. The fetching of the row start- 
ing address from the row table is indicated by the assertion 
of the CURSOR output during BLANK. The address read 
from the table by the AVDC is loaded into screen start 
register 1 (SSR1) for use internally. Since the contents of 
SSR2 changes as the table entries are fetched, it must be re- 
initialized to point to the first table entry during each vertical 
retrace interval. 

Row table addressing is intended primarily for use in con- 
junction with the row buffer mode of operation and requires 
no additional circuitry in that case. It may also be used with 




MOTOROLA MICROPROCESSOR DATA 
3-41 



FIGURE 5 - WRITE FROM CURSOR TO POINTER COMMAND TIMING 



-jiAaaaaaaaaaaaaaaaaa 

"V~ N — ~ 



CE 

w 

BLANK 
HSYNC 

DADD 
WDB 



HFP = Odd 



Y~~^0f V ¥ Last V Cursor ¥ Cursor V Cursor Y Cursor V RF Y RF Y AVDC Con " 01 Y 1s,Row Y )T 
A, fcJ l A AAddrA Address A Address+1 A Address+2 A Address + 3 A Addr AAddr A s ' 9 " als A Addr A J \ 




BLANK 



HSYNC 



DADD 



BLANK 



HSYNC 



DADD 



HFP= Even 



Command 
Completion 



NY VLastW Cursor V Pointer V Pointer 

kgA A Addr A Address+N A Address— 1 A 



-1 A Address 



NOTE: 

If command execution occurs just prior to the first scan line of a character row and row table addressing mode is enabled, execution of the 
command is delayed by two character clocks from the timing illustrated. 



MC2674 



FIGURE 6 — AVDC SHARED OR TRANSPARENT BUFFER MODES 



BEXT 



CPU 



f PBREQ > 

I BACK •< —m — : 



MC2674 
AVDC 



CTRL1 
CTRL3 
CTRL2 



{- 

V W > 



Select 
Decode 



Tt 



Upper 



System Address Bus 



Display Address 



SN74LS244 




Lower 



Display Data Bus 



SN74LS245 




System Data Bus 



FIGURE 7 - TRANSPARENT BUFFER MODE TIMING 



PBTlEQ ^ 



BACK 



BEXT 



BLANK 



DADD 



NOTES: 



-V 



^(4) 



(3,4) 



in 



Horizontal Blanking Interval 



fLast Char' 
L Address 



System Addresses 



3-OE 



\— — v— \ 



,VDC CTRL Signals 



YAVDC CTRL Signals 



Vlst Chary 
A Address A 



1. P BREQ m ust be asserted prior to the risi ng edg e of BLANK in order for sequence to begin during that blanking period. 

2. If PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked. 

3. Accesses during vertical blank or "display off" are granted only at the beginning of the horizontal front porch. 

4. If row table addressing is enabled, CPU access is delayed by two character clocks prior to the first scan line of each character 
row. 

5. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 
3-43 



MC2674 



FIGURE 8 - SHARED BUFFER MODE TIMING 



PBREQ 



NOTES: 



^ , 



«»Z3i3gSKZD — C^OEiELl^ 



1. If PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked. 

2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



FIGURE 9 - SHARED AND TRANSPARENT MODE TIMING 



j\j\j\nJ\j~vr\. 



PBREQ 



BACK ^ 



VBLANK or 
DBLANK 

DADD 



Sys. ADD 



Refresh Addresses 



ED— dip— DC 



Refresh 
Addresses 



a) During Vertical Blank or after 'display off command in shared 
mode only. See Figure 7 for transparent timing. 



CCLK 
PBREQ 
BACK 
BEXT 
BLANK 



-v 



DADD 



System Processor Has Continuous Bus Control 

ft 



b) After 'display off and 3-state' command. 



the other modes, but circuitry must be added to route the 
data from the display memory to the data bus inputs of the 
AVDC. Additionally, when not operating in row buffer 
mode, care must be taken to assure that the CPU does not 
attempt to access the AVDC while it is reading the row table. 
One way of preventing this is to latch prior to reading or 
writing the AVDC. The AVDC should only be accessed if the 
latch is low, indicating that the last line of the row is not 
active. 

Figure 13 illustrates a typical hardware implementation for 
use in conjunction with independent and transparent modes, 
and Figure 14 shows the timing for row table operation. 



OPERATION 

After power is applied, the AVDC will be in an inactive 
state. Two consecutive "master reset" commands are 
necessary to release this circuitry and ready the AVDC for 
operation. Two register groups exist within the ADC; the 
initialization registers and the display control registers. The 
initialization registers select the system configuration, 
monitor timing, cursor shape, display memory domain, 
pointer address, scrolling region, double height and width 
condition, and screen format. These are loaded first and nor- 
mally require no modification except for certain special visual 



MOTOROLA MICROPROCESSOR DATA 
3-44 



MC2674 



FIGURE 10 - ROW BUFFER MODE CONFIGURATION 

2x2111 




FIGURE 11 - ROW BUFFER MODE TIMING 




NOTES: 

1 . If row table addressing is enabled, BREQ will be asserted at the middle of the last scan line of the prior row, and MBC will 
be asserted at the beginning of BLANK. 

2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and 
outputs. Input levels are 0.4 V to 2.4 V. 



MOTOROLA MICROPROCESSOR DATA 
3-45 



MC2674 



FIGURE 12 - ROW TABLE ADDRESS FORMAT 




Row Table 
in Memory 



Third 
Data Row 



First 
Data Row 



Second 
Data Row 



SSR2 



Last Char 



1st Char 



2nd Char 



Last Char 



1st Char 



2nd Char 



Last Char 



FIGURE 13 - ROW TABLE MODE CONFIGURATION (NON-ROW BUFFER MODES) 



Select 
Decode 



MC2674 
AVDC 



DADD 



R 

w 

CE 



CCLK 
BLANK 



CURSOR 
D0-D7 



7K 

*~\ CD r* 

CO 

K 

to 

CN 



CE 
S/R 



SN74LS245 



Display Address 



DBLNK 



CURSOR 
* *- 



or 

SN74LS244 



7^ 



RAM 
ADD 
Data I/O 



Display Data Bus 



System Data Bus 



MOTOROLA MICROPROCESSOR DATA 
3-46 



MC2674 



FIGURE 14 - ROW TABLE MODE TIMING 



Row Buffer 
Mode 



BLANK 



HSYNC 



J1 



BREQ 



MBC 



DADD 



CURSOR 



CCLK 



1 



Last Line of Row 



Hi 1 



n 



•EC + 2 HSW CCLKs 



Last Line Addresses 



I Possible Cursors 
J 



Transparent 
Buffer Mode 



SSR2 
'SSR2+1 
(Refresh 



First Line of Row 



First Line Addresses 



\ 



I 



n 



Refresh 



I Possible Cursors | 



Fetch 
Control 
Interval 



BREQ 



BEXT 



Independent , 
Buffer Mode 



3- State 



First Line Addresses 



Bus Request 

During 
Fetch Cycle 



(Cursor or Pointer Addresses 
/ for Delayed Commands) \ 



First Line Addresses 



3- State 



r 



No Fetch Bus 
Request 



i_r 



¥ 
Jill 



RDB 



a = Multiplexed Control Signals 
EC = Equalizing Constant 
HSW= Horizontal SYNC Width 



MOTOROLA MICROPROCESSOR DATA 
3-47 



MC2674 



effects. The display control registers specify the mem- 
ory address of the base character (upper left corner of 
screen), the cursor position, and the split screen ad- 
dresses associated with the scrolling area or an alter- 
nate memory. These may require modification during 
operation. 

After initial loading of the two register groups, the 
AVDC is ready to control the monitor screen. Prior to 
executing the AVDC commands which turn on the dis- 
play cursor, the user should load the display memory 
with the first data to be displayed. During operation, 
the AVDC will sequentially address the display memory 
within the limits programmed into its registers. The 
memory outputs character codes to the system char- 
acter and graphics generation logic, where they are con- 
verted to the serial video stream necessary to display 
the data on the CRT. The user effects changes to the 
CRT. The user effects changes to the display by modi- 
fying the contents of the display memory, the AVDC 
display control and command registers, and the initial- 
ization registers, if required. Interrupts and status con- 



ditions generated by the AVDC supply the "handshaking" 
information necessary for the CPU to effect real time 
display changes in the proper time frame if required. 



INITIALIZATION REGISTERS 

There are 15 initialization registers (IR0-IR14) which 
are accessed sequentially via a single address. The AVDC 
maintains an internal pointer to these registers which 
is incremented after each write at this address until the 
last register (IR14) is accessed. The pointer then contin- 
ues to point to IR14 for further accesses. Upon a power- 
on or a master reset command, the internal pointer reset 
to point to the first register (IRO) of the initialization 
register group. The internal pointer can also be preset 
to any register of the group via the "load IR address 
pointer" command. These registers are write only and 
are used to specify parameters such as the system con- 
figuration, display format, cursor shape, and monitor 
timing. Register formats are shown in Figure 15. 



FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 1 of 4) 



7 


6 5 


4 3 


2 


1 0 


Double 


Scan Lines Per Character Row 


Sync 


Buffer-Mode 


Height/ 


Non-Interlaced 


Interlaced 


Select 


Select 


Width 


0000= 1 Line 


0000 = 2 Lines 


0=VSYNC 


00 ^ Independent 




0001=2 Lines 


0001=4 Lines 


1=CSYNC 


01 = Transparent 




0010 = 3 Lines 


0010=6 Lines 




10 = Shared 




• 


• 




1 1 = Row 




• 

1110=15 Lines 


• 

1110 = 30 Lines 




Buffer 




1111 = 16 Lines 


1111 = Undefined 







IRO 



7 6 5 4 _3 2 1 0 



Interlace 
Enable 


Equalizing Constant 


0000000=1 CCLK 




0 = Non- 


0000001=2 CCLK 




•' 


Calculated from: 


Interlace 


■ ■ ■■• 


EC = 0.5 (H AC T+ H F P+ H S YNC+ H B p) -2(H S YNC> 


1 = Inter- 


1111110=127 CCLK 




lace' 


1111111 = 128 CCLK 





7 6 5 4 3 2 1 0 



Row 
Table 


Horizontal Sync Width 


Horizontal Back Porch 


0=Off 


0000 = 2 CCLK 


000= Not Allowed 


1 = On 


0001=4 CCLK 
• 


001 = 3 CCLK 

• 




• 

1110 = 30 CCLK 


• 

110 = 23 CCLK 




1111=32 CCLK 


111 = 27 CCLK 



MOTOROLA MICROPROCESSOR DATA 
3-48 



MC2674 



FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 2 of 4) 



7 6 5 4 3 2 1 0 



Vertical Front Porch 


Vertical Back Porch 


000= 


= 4 Scan Lines 




00000 = 4 Scan Lines 




001 = 


= 8 Scan Lines 




00001 =6 Scan Lines 






• 




• 






• 




• 




110= 


28 Scan Lines 




11110=64 Scan Lines 




111 = 


32 Scan Lines 




1 1 1 1 1 = 66 Scan Lines 




7 


6 


5 


4 3 2.1 


0 


Character 










Blink Rate 






Active Character Rows Per Screen 




0=1/64 






0000000= 1 Row 




VSYNC 






0000001 = 2 Rows 




1 = 1/128 






• 




VSYNC 






• 
• 










1111110=127 Rows 










1111111 = 128 Rows 




7 


6 


5 


4 3 2 1 


0 


Active Characters Per Row 








00000010 = 3 Characters 










00000011 =4 Characters 
• 










• 

11111110 = 256 Characters 










11111111 = 256 Characters 





7 6 5 4 3 2 . 1 ; 0 



IR6 



First Line of Cursor 


Last Line of Cursor 


0000= Scan Line 0 


0000= Scan Line 0 


0001 = Scan Line 1 
• 


0001 = Scan Line 1 
• 


• 

1110= Scan Line 14 


• 

1110= Scan Line 14 


1111 = Scan Line 15 


1111 = Scan Line 15 



7 6 


5 


4 


3 2 1 


0 


Light Pen Line 


Cursor 
Blink 


Cursor 
Rate 


Underline Position' 


00= Scan Line 3 
01 = Scan Line 1 
10= Scan Line 5 
11 = Scan Line 7 


0=Off 
1 = On 


0=1/32 
1 = 1/64 


0000= Scan Line 0 
0001 = Scan Line 1 

• 

• 

11 10= Scan Line 14 
1111 = Scan Line 15 



MOTOROLA MICROPROCESSOR DATA 
3-49 



MC2674 



FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 3 of 4) 

6 5 4 3 2 



IR8 



Display Buffer First Address LSBs 



H'000' = 0 
H'001'=1 



H'FFE' = 4,094 
H'FFP = 4,095 



NOTE: MSBs are in IR9[3:0] 



a 



Display Buffer Last Address 


Display Buffer First Address MSBs 


0000- 1,023 ': . 




0001 = 2,047 






See IR8 


1110=15,359 




1111 = 16,383 





IR10 



IR11 



7 


6 


5 4 3 2 1 


0 


Display Pointer Address Lower 


SeeiR11 


7 


6 


5 4 3 2 1 


0 


LZ Down 


LZ Up 


Display Pointer Address Upper 


O=0ff . 
1 = On 


0=Off 
1 = On 


H'0000'=0 
H'0001' = 1 

■ ■ • ■ 
• 

H'3FFF' = 16,383 



7 6 5 4 3 2 1 0 



IR12 


Scroll Start 


Split Register 1 




0=Off 


0000000= Row 1 




1 = On 


0000001 = Row 2 

• 






• 

1111111 = Row 128 



MOTOROLA MICROPROCESSOR DATA 
3-50 



MC2674 



FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 4 of 4) 





7 


6 5 


4 3 2 


0 


IR13 


Scroll End 


Split Register 2 




0=Off 
1 = On 




0000000= Row 1 
0000001 = Row 2 

• 

• 

1111111 = Row 128 





7 6 


5 4 


3 2 1 0 


Double 1 


Double 2 


Lines to Scroll 


00= Normal 


00= Normal 


0000=1 


01 = Double Width 


01 = Double Width 


0001 = 2 


10= Double Width 


10= Double Width 


• 


and Tops 


and Tops 


• 


' 11 = Double Width 


1 1 = Double Width 


1110=15 


and Bottoms 


and Bottoms 


1111 = 16 



DOUBLE HEIGHT/WIDTH ENABLE (IR0[7]) - When this 
bit is set, the. value in IR14[7:6] is used to control the double 
height and width conditions of each character row. Asser- 
tion of this bit also allows IR14[7:6] to be programmed in two 
ways: 

1. By the CP writing to IR14 directly. 

2. When the contents of screen start register 1 (SSR1) 
upper are changed, either by the CPU writing to this 
register or by the automatic loading of SSR1 when 
operating in row table mode, the two most significant 
bits of SSR1 upper are copied into IR14[7:6]. Thus, the 
most significant bits of each row table entry can be us- 
ed to control double height and double width attributes 
on a row-by-row basis. 

IR14[5:4] are not active when this bit is set. When this bit 
is reset, the double height and width attributes operate as 
described in IR[14], 

SCAN LINES PER CHARACTER ROW (IR0[6:3]) - Both 
interlaced and non-interlaced scanning are supported by the 
AVDC. For interlaced mode, two different formats can be 
implemented, depending on the interconnection between 
the AVDC and the character generator (see IR1[7]). This field 
defines the number of scan lines used to compose a char- 
acter row for each technique. As scanning occurs, the scan 
line count is output on the LAO- L A3 and ODD pins. 

VSYNC/CSYNC (IR0[2]) - This bit selects either vertical 
sync pulses or composite sync pulses on the VSYNC/ 
CSYNC output (pin 18). The composite sync waveform con- 
forms to EIA RS170 standards, with the vertical interval com- 
posed of six equalizing pulses, six vertical sync pulses, and 
six more equalizing pulses. 

BUFFER MODE SELECT (IR0[1:01) - Four buffer memory 
modes may be selectively enabled to accommodate the 
desired system configuration. See SYSTEM CONFIGURA- 
TIONS. 

INTERLACE ENABLE (IR1 [7]) - Specifies interlaced or 
non-interlaced timing operation. Two modes of interlaced 
operation are available, depending on whether L0-L3 or 



ODD, L0-L2 are used as the line address for the character 
generator. The resulting displays are shown in Figure 16. 

For "interlaced sync" operation, the same information is 
displayed in both odd and even fields, resulting in enhanced 
readability. The AVDC outputs successive line numbers in 
ascending order on the LA0-LA3 lines, one per scan line for 
each field. 

The "interlaced sync and video" format doubles the char- 
acter density on the screen. The AVDC outputs successive 
line numbers in ascending order on the odd and LA0-LA2 
lines, one per scan line for each field. 

EQUALIZING CONSTANT (IR1[6:01) - This field indirect- 
ly defines the horizontal front porch and is used internally to 
generate the equalizing pulses for the RS170 compatible 
CSYNC. The val ue for this field is the total number of 
character clocks (CCLKs) during a horizontal line period 
divided by two, minus two times the number of character 
clocks in the horizontal sync pulse: 

EC= ™ n bYNL — -2(HSYNC> 



The definition of the individual parameters is illustrated in Fig- 
ure 17. 

Note that when usi ng the attributes controller it will delay 
the blank pulse three CCLKs relative to the HSYNC pulse. 

ROW TABLE MODE ENABLE (IR2[7]) - Assertion/ nega- 
tion of this bit causes the AVDC to begin/terminate 
operating in row table mode starting at the next character 
row. See ROW TABLE ADDRESS MODE. By using the split 
interrupt capability of the AVDC, this mode can be enabled 
and disabled on a particular character row. This allows a 
combination of row table and sequential addressing to be 
utilized to provide maximum flexibility in generating the 
display. 

HORIZONTAL SYNC PULSE WIDTH (IR2[6:3]) - This 
field specifies the width of the HSYNC pulse in CCLK 
periods. 



MOTOROLA MICROPROCESSOR DATA 
3-51 



MC2674 



FIGURE 16 - INTERLACED DISPLAY MODES 



Line Address 
To Character Generator 



Odd 

- LO 

- L1 

- L2 

- L3 



Line Address 
To Character Generator 



Line Address 
To Character Generator 



o uj 
7 — 



0 • 



1 -o-o-o-o— o- 

2 « 

2- 0 

3 • 

3- 0 

4 

4 - O-O-O 

5 • 

5- 0 

6 • 

I -O- 



7 

7 -o-o-o-o— o- 

8 : 

8 

0 



0 



1 -o-o-o-o— o- 

2 — • 

2 -o 

3 • 

3-0 

4 

4 -O-O-O 

5 • 

5-0 — 

6 



6-0 

7 

/ -o— o-o-o— o- 



uj O 

r o 

2 
4 
6 



1-00000- 



3-0 

— ••• 

5-0 

— • 

7-00000- 



I'OOOOO- 

— » 

3-0 

— •• • 

5-0 • 



7-ooooo^ 



1-00000- 



3-0- 



• ••- 

5-0 

6 •■ 



7-0 0 0 00" 



1-O0OOO- 

— • 

3-0 

— — 

5-0 ! 



Non-interlaced 

IR0=1000; Total Lines/Row = < 



Interlaced SYNC 

IRO=1000; Total Lines/Row= 16 



Interlaced SYNC and Video 
IR0 = 0100; Total Lines/Row=10 



HORIZONTAL BACK POR CH (IR2[2:0]) — This field 
defines the number of CCLKs between the trailing edge 
of HSYNC and the trailing edge of BLANK. 

VERTICAL FRONT PORCH (IR3[7:3J) — This field spec- 
ifies the number of scan line periods between the rising 
edges of BLANK and VSYNC during the vertical retrace 
interval. The vertical front porch is extended in incre- 
ments of scan lines if the ACLL input is low at the end 
of the programmed value. 

VERTICAL BACK PORCH (IR3[4:0]) — This field de- 
termines the number of scan line periods between the 
falling edges of the VSYNC and BLANK outputs. 

CHARACTER BLINK RATE (IR4[7]) — Specifies the fre- 
quency for the character blink attribute timing. The blink 
rate can be specified as 1/64 or 1/128 of the vertical field 
rate. The timing signal has a duty cycle of 50% and is 
multiplexed onto the DADD1/BLINK output at the falling 
edge of each BLANK. 



CHARACTER ROWS PER SCREEN (IR4[6:0]) — This 
field defines the number of character rows to be dis- 
played. The value multiplied by the scan lines per char- 
acte row, plus the vertical front porch, the vertical back 
porch values, and the vertical sync pulse width is the 
vertical scan period in scan lines. 



ACTIVE CHARACTERS PER ROW (IR5[7:0]) — This 
field determines the number of characters to be dis- 
played on each row of the CRT screen. The sum of this 
value, the horizontal front porch, the horizontal sync 
width, and the horizontl back porch is the horizontal 
scan period in CCLKs. 

FIRST AND LAST SCAN LINE OF CURSOR (IR6[7:4], 
IR6[3:0]) — These two field specify the height and po- 
sition of the cursor on the character block. The "first" 
line is the topmost line when scanning from the top to 
the bottom of the screen. 



MOTOROLA MICROPROCESSOR DATA 
3-52 



MC2674 



FIGURE 17 - HORIZONTAL AND VERTICAL TIMING 



Character Row 
(IR5) 



r — l 



Front Porch (I R1) 



Back Porch(IR2) 



HSYNC 



— J L — HSYNC (IR2) 

1 1 1^- Character Rows/Screen (IR4)- 



|^— Scan Lines Per Row (IRO) 



1 



VBLANK 

—*\ \*— Front Porch (I R3) 
VSYNC J~\ 



J 



— *| (<— VSYNC (IR7) 



Back Porch (IR3) — \<— 

n 



Lines/ Row 



Equalizing 
Constant 



IRO [J 



IR1 



IR2 



HSYNC HBACK 
Width Porch 



Character Rows/ Screen 



n 



'B4| I I I I l | I ] 



VFRONT VBACK 
Porch Porch 

h i i i i i"i ri 

Characters per Row 

■R5 j 1 1 1 1 1 1 "i — i 



VSYNC 
Width 



VERTICAL SYNC PULSE WIDTH (IR7[7:6]» - This field 
specifies the width of the VSYNC pulse in scan line periods. 

CURSOR BLINK ENABLE (IR7[5]| - This bit controls 
whether or not the cursor output pin will be blinked at the 
selected rate (IR7[4]). The blink duty cycle for the cursor is 
50%. 

CURSOR BLINK RATE (IR7[4]) - The cursor blink rate 
can be specified at 1/32 or 1/64 of the vertical scan frequen- 
cy. Blink is effective only if blink is enabled by IR7[5J. 

UNDERLINE POSITION (IR7[3:0]) — This field defines which 
scan line of the character row will be used for the underline 
attribute by the attributes controller. The timing signal is mul- 
tiplexed onto the DADD10/UL output during the falling edge 
of BLANK. 

DISPLAY BUFFER FIRST ADDRESS (IR9[3:0]) ( IR8[7:0] 
AND DISPLAY BUFFER LAST ADDRESS (IR9[7:4]) - 

These two fields define the area within the buffer memory 
where the display data will reside. When the data at the 
"display buffer last address" is displayed, the AVDC will 
wraparound and obtain the data to be displayed at the next 
screen position from the "display buffer first address". If 
"last address" is the end of a character row and a new 
screen start address has been loaded into the screen start 
register, or if "last address" is the last character position of 
the screen, the next data is obtained from the address con- 
tained in the screen start register. 

Note that there is no restriction in displaying data from 
other areas of the addressable memory. Normally, the area 



between these two bounds is used for data which can be 
overwritten (e.g., as a result of scrolling), while data that is 
not to be overwritten would be contained outside these 
bounds and accessed by means of the automatic split screen 
or split screen interrupt features of the AVDC. 

DISPLAY POINTER ADDRESS LOWER (IR10[7:0] AND 
DISPLAY POINTER ADDRESS UPPER (IR11[5:01) - These 
two fields define a buffer memory address for AVDC con- 
trolled accesses in response to "read/ write at pointer" com- 
mands. They also define the last buffer memory address to 
be written for the "write from cursor to pointer" command. 

SCAN LINE ZERO DURING SCROLL DOWN (IRZ11[7]) - 

This field specifies normal scan iine count or all scan line zero 
counts for the new character row that occurs at the top of 
the scrolling area during soft scroll down operation. If the 
character generator provides blanks during scan line zero, 
this will cause the new row to be automatically blanked on 
the display. This feature can be used, if necessary, to blank 
the new row until the CPU places "blank data" into the 
display buffer. 

SCAN LINE ZERO DURING SCROLL UP (IR11[6J) - This 
field specifies normal scan line count or all scan line counts 
for the new character row that occurs at the bottom of the 
scrolling area during soft scroll up operation. 

SCROLL START (IR12[71) — This bit is asserted when 
soft scroll is to take place. The scrolling area begins at the 
row specified in split register 1 (IR12[6:0]). If set, the first 



MOTOROLA MICROPROCESSOR DATA 
3-53 



MC2674 



, 4. The specified double width and height conditions ( I R 14) 
are also asserted in two possible ways: 

a) Automatic split will assert the programmed condition 
for the current row. 

b) During soft scroll operation the programmed condi- 
tions are asserted for the partial row scrolling onto or 
off the screen: 

DOUBLE 1 (IR14[7:61) - This field specifies the condi- 
tions (double width/ height or normal) of the row designated 
in split register 1 (IR12[6:0]). When double height tops or 
bottoms has been specified, the AVDC will automatically 
toggle between tops and bottoms until another split 1 or 2 
occurs which changes the double height/ width condition. If 
a double height top row is specified, the scan line count will 
start at zero and increment the scan line every other scan 
line. If a double height bottom row is specified, the AVDC 
will start a one half the normal scan line total. If double width 
is specified, the AVDC will assert the DADD9/DW output at 
the falling edge of blank. This condition will also remain ac- 
tive until the next split 1 or 2. When IR0(7] = 1, the values 
written into bits 7 and 6 of screen start 1 upper will also be 
written into IR14[7:6] and the automatic toggling between 
tops and bottoms is disabled. 

DOUBLE 2 (IR14[5:4]) - This field specifies the condi- 
tions (double width/ height or normal) of the row designated 
in split register 2 (IR13[6:0]). Not used with IR0[7] = 1. 

LINES TO SCROLL (IR14[3:01) - This field defines the 
scan line increment to be used during a soft scroll operation. 
This value will only be used when scroll start (IR12[7]) and 
scroll end 0R13[7]) are enabled. 

TIMING CONSIDERATIONS 

Normally, the contents of the initialization registers are not 
changed during normal operation. However, this may be 
necessary to implement special display features such as 
multiple cursors and horizontal scrolling. Table 2 describes 
timing details for these registers which should be considered 
when implementing these features. 



TABLE 2 - TIMING CONSIDERATIONS 



Parameter 


Timing Considerations 


First Line of Cursor 
Last Line of Cursor 
Underline Line 


These parameters must be established at a minimum of two character times prior to their 
occurrence. 


Double Height Character Rows 
Double Width Character Rows 
Rows to Scroll 


Set/ reset prior to the row specified in split 1 or 2 registers. 


Cursor Blink - 
Cursor Blink Rate 
Character Blink Rate 


New values become effective within one field after values are Changed. 


Split Register 1 
Split Register 2 


Change anytime prior to line zero of desired row. 


Character Rows Per Screen 


Change only during vertical blanking period. 


Vertical Front Porch 


Change prior to first line of VFP. 


Vertical Back Porch . 


Change prior to four line after VSYNC. 


Screen Start Register 1 
Row Table Mode Enable 


Change prior to the horizontal blanking interval of the last line of character row before row where 
new value is to be used. 



MOTOROLA MICROPROCESSOR DATA 
3-54 



row to scroll scan line count will be reduced by the value in. 
the lines to scroll register OR14[3:0]). The scan line count of 
this row will start at the programmed offset value. When this 
bit is asserted, scroll end IR13[7] must be set before split 
register 2. 

SPLIT REGISTER 1 (IR12[6:01) - Split register 1 can be 
used to provide special screen effects such as soft (scan line 
by scan line) scrolling, double height/ width rows, or to 
change the normal addressing sequence of the display 
memory. The contents of this field is compared, in real time, 
to the current row number. Upon a match, the AVDC sets 
the split screen 1 status bit, and issues an interrupt request if 
so programmed. The status change/ interrupt request is 
made at the beginning of the scan line zero of the split screen 
character row. If enabled by the SPL1 bit of screen start 
register 2, an automatic split screen to the address specified 
in screen start register 2 will be made for the designated 
character row. During a scroll operation, this field defines 
the first character row of the scrolling area. 

SCROLL END (IR13[7]) - This field specifies that the row 
programmed in split register 2 (IR13[6:0J) is to be the last 
scrolling row of the scrolling area. Note that this bit must be 
asserted for a valid row only when the scroll start bit IR12[7] 
is also asserted. 

SPLIT REGISTER 2 (IR13[6:0]| - This field is similar to 
the split register 1 field except for the following: 

1 . Split screen 2 status bit is set. 

2. During a scroll operation, this field defines the last 
character row of the scrolling area. This row will be 
followed by a partial row. The LTSR < I R 14) value 
replaces the normal scan lines/ row value for the partial 
row, thus keeping the total scan lines/screen the same. 

3. If enabled by the SPL2 bit of screen start register 2, an 
automatic split to the address contained in screen start 
register 2 will occur in one of two ways: 

a) If not scrolling an automatic split will occur for the 
next character row. 

b) If scrolling, the automatic split will occur after the 
partial row being scrolled onto or off the screen. 



MC2674 



DISPLAY CONTROL REGISTERS 

There are seven registers in this group, each with an in- 
dividual address. Their formats are illustrated in Figure 18. 
The command register is used to invoke one of 19 possible 
AVDC commands as described in COMMANDS. The re- 
maining registers in the group store address values which 
specify the cursor location, the location of the first character 
to be be displayed on the screen, and any split screen ad- 
dress locations. The user initializes these registers after 
powering on the system and changes their values to control 
the data which is displayed. 

SCREEN START REGISTERS 1 AND 2 

The screen start 1 registers contain the address of the first 
character of the first row (upper left corner of the active 
display). At the beginning of the first scan line of the first 
row, this address is transferred to the row start register 
(RSR) and into the memory address counter (MAC). The 
counter is then advanced sequentially at the character clock 
rate for the number of times programmed into the active 
characters per row register (IR5), thus reaching the address 
of the last character of the row plus one. At the beginning of 
each subsequent scan line of the first row, the MAC is 
reloaded from the RSR and the above sequence is repeated. 
At the end of the last scan line of the first row, the contents 
of the MAC is loaded into the RSR to serve as the starting 
memory address for the second character row. This process 
is repeated for the programmed number of rows per screen. 
Thus, the data in the display memory is displayed sequen- 
tially starting from the address contained in the screen start 
register. After the ensuing vertical retrace interval, the entire 
process repeats again. 

During vertical blanking, the address counter operation is 
modified by stopping the automatic load of the contents of 
the RSR into the counter, thereby allowing the address out- 
puts to free-run. This allows dynamic memory refresh to oc- 
cur during the vertical retrace interval. The refresh address- 



ing starts at the last address displayed on the screen and in- 
crements by one for each character clock during the retrace 
interval. If the display buffer last address is encountered, 
refreshing continues from the display buffer first address. 

The sequential operation described above will be modified 
upon the occurrence of any of three events. First, if during 
the incrementing of the memory address counter the 
"display buffer last address" (IR9[7:4]) is reached, the MAC 
will be loaded from the "display buffer first address" register 
0R9[3:0] and IR8[7:0]) at the next character clock. Sequen- 
tial operation will then resume starting from this address. 
This wraparound operation allows portions of the display 
buffer to be used for purposes other than storage of display- 
able data and is completely automatic without any CPU 
intervention (see Figure 19a). 

The sequential row to row addressing can also be modified 
via split register 1 (IR12) and split register 2 (IR13), under 
CPU control, or by enabling the row table addressing mode. 
If bit 6 of screen start register 2 upper (SPL1) is set, the 
screen start register 2 contents will be loaded automatically 
into the RSR at the beginning of the first scan line of the row 
designated by split register 1 (IR12[6:0]). If bit 7 of screen 
start 2 upper (SPL2) is set, the screen start register 2 con- 
tents is automatically loaded into the RSR at the end of the 
last scan line of the row designated by split register 2 
OR13[6:0]). SPL1 and SPL2 are write only bits and will read 
as zero when reading screen start register 2. 

If the contents of screen start register 1 (upper, lower, or 
both) are changed during any character row (e.g., row 'n'), 
the starting address of the next character row (row 'n+ 1') 
will be the new value of the screen start register and address- 
ing will continue sequentially from there. This allows fea- 
tures such as split screen operation, partial scroll, or status 
line display to be implemented. The split screen interrupt fea- 
ture of the AVDC is useful in controlling the CPU initiated 
operations. Note that in order to obtain the correct screen 
display, screen start register 1 must be reloaded with the 
original (origin of display) value prior to the end of the ver- 
tical retrace. See Figure 19b. 




FIGURE 18 - DISPLAY CONTROL REGISTER FORMATS (Sheet 1 of 2) 

6 5 4 3 2 1 



Command Code 



See COMMANDS for Command Codes 



Command Registers (Write Only) 







Upper Register 


DADD15 


DADD14 


Most Significant Bits 



MOTOROLA MICROPROCESSOR DATA 
3-55 



MC2674 



FIGURE 18 - DISPLAY CONTROL REGISTER FORMATS (Sheet 2 of 2) 



7 6 


5 4 3 2 1 


0 


Lower Register (Least Significant Bit) 


H'0000' = 0 
H'0001'=1 
Through 
H'3FFE'= 16,382 
H'3FFF' = 16,383 


NOTE: Most significant bits are in upper register [5:0] 





NOTES: 

1 . Bits 7 and 6 of upper register are not used in the cursor address register. 

2. Bits 7 and 6 of upper register are always zero when read by the CPU. 

3. When IR0[7] = 1, the values written into bits 7 and 6 of screen start 1 upper will also be written into 
IR14[7:6] to control the double width and double height attributes of the display as follows: 



1 


6 


Attribute 


0 


0 


None 


0 


1 


Double Width Only 


1 


0 


Double Width and Double Height Tops 


1 


1 


Double Width and Double Height Bottoms 



a 



Screen Start 1 Register (Read and Write) and 
Cursor Address Registers (Read and Write) 



7 , 


6 


5 


4 3 2 1 


0; 






Upper Register 


SPL2 
0=Off 
1=0n 


SPL1 
0 = Off 
1='On 


Most Significant Bits 



Lower Register (Least Significant Bit) 
H'0000'=0 ~~ ~ . -. ,'„■■.. ■■ 

H'000T = 1 

Through NOTE: Most significant bits are in upper register [5:0] 

H'3FFE' = 16,382 

H'3FFF' = 16.383 



NOTE: 

Bit 7 and bit 6 are always zero when read by the CPU. 

Screen Start 2 Registers (Read and Write) 



When row table addressing mode is enabled, the first ad- 
dress of the row table is designated in SSR2. The AVDC 
fetches the next row's starting address from the table during 
the blanking interval prior to the first scan line of each char- 
acter row and loads it into SSR1 for use as the starting ad- 
dress of the next row. Since the contents of SSR2 changes 
as the table entries are fetched, it must be re-initialized to 
point to the first table entry during each vertical retrace inter- 
val. 

The values of the two most significant bits of SSR1 upper 
are multiplexed onto the DADD1/DADD14 and DADD2/ 
DADD15 outputs during the falling edge of BLANK. If 
IR0[7] = 0, these two bits act as memory page select bits 
which may be used to extend the display memory addressing 



range of the AVDC up to 64K. In that case, these two bits 
act as a two-bit counter which is incremented each time that 
"wraparound" occurs (see above). Note that the counter is 
incremented at the falling edge of BLANK and that for pro- 
per display operation the wraparound address should be pro- 
grammed to occur at the last character position of a row. 
Also, the first address accessed in the new page will be the 
address contained in the display buffer first address register 
<IR9[3:0] and IR8[7:0]). 

CURSOR ADDRESS REGISTERS 

The contents of these registers define the buffer memory 
address of the cursor. The cursor output will be asserted 
when the memory address counter matches the value of the 



MOTOROLA MICROPROCESSOR DATA 
3-56 



MG2674 



FIGURE 19 - DISPLAY ADDRESSING OPERATION 



Bottom of Screen — ► 



Screen Start—* 



16K 




*- Display Buffer Start 



■—Display Buffer End 




Memory 

(a) Display Memory Wraparound 



Screen Start 1 — » 




Screen Start 2 — » 




— Display Buffer Start 

— Bottom of Screen 



Split Screen—* 





Monitor 

— Display Buffer End Display 



Memory 

(b) Display Memory Split Screen With Wraparound 



cursor address registers for the scan lines specified in IR6. 
The cursor address registers can be read or written by the 
CPU or incremented via the "increment cursor address" 
command. In independent buffer mode, these registers 
define a buffer memory address for AVDC controlled access 
in response to "read/write at cursor with/without incre- 
ment" commands, or the first address to be used in 
executing the "write from cursor to pointer" command. 

INTERRUPT/STATUS REGISTERS 

The interrupt and status registers provide information to 
the CPU to allow it to interact with the AVDC to effect 
desired changes that implement various display operations. 
The interrupt register provides information on five display 
operations. The interrupt register provides information on 
five possible interrupt conditions, as shown in Figure 20. 
These conditions can be selectively enabled or disabled 



(masked) from causing interrupts by certain AVDC com- 
mands. An interrupt conditi on wh ich is enabled (masked bit 
equal to one) will cause the INTR output to be asserted and 
will cause the corresponding bit in the interrupt register to be 
set upon the occurrence of the interrupting condition. An 
interrupt condition which is di sable d (mask bit equal to zero) 
has no effect on either the INTR output or the interrupt 
register. 

The status register provides six bits of status information: 
the five possible interrupt conditions plus the RDFLG bit. For 
this register, however, the contents are not affected by the 
state of the mask bits. 

Descriptions of each interrupt/ status register bit follow. 
Unless otherwise indicated, a bit, once set, will remain set 
until reset by the CPU by issuing a "reset interrupt/ status 
bits" command. The bits are also reset by a "master reset" 
command and upon power-up. 



MOTOROLA MICROPROCESSOR DATA 
3-57 



MC2674 



FIGURE 20 - INTERRUPT AND STATUS REGISTER FORMAT 



7 6 


5 


4 


3 


2 


1 


0 








Line 










RDFLG 


VBLANK 


Zero 


Split 1 


Ready 


Split 2 


Not Used 


0= Busy 


0=No 


0=No 


0=No 


0=Busy 


0=No 


Always Read as 0 


1 = Ready 


1 = Yes 


1 =Yes 


1 = Yes 


1 = Ready 


1=Yes 



RDFLG (l/SR[51) - this bit is present in the status 
register only. A zero indicates that the AVDC is currently 
executing the previously issued delayed command. A one 
indicates that the AVDC is ready to accept a new delayed 
command. 

VBLANK (l/SR[4J) - Indicates the beginning of a vertical 
blanking interval. Set to one at the beginning of the first scan 
line of the vertical front porch. 

LINE ZERO (l/SR[3]| - Set to one at the beginning of the . 
first scan line (line 0) of each active character row. 

SPLIT SCREEN 1 (l/SR[21) - This bit is set when a match 
occurs between the current character row number and the 
value contained in split register 1, IR12[6:0], The equality 
condition is only checked at the beginning of line zero of 
each character row. 

READY (l/SR[1l) - The delayed commands affect the 
display and may require the AVDC to wait for a blanking 
interval before enacting the command. This bit is set to one 



when execution of a delayed command has been completed. 
No other delayed command should be invoked until the prior 
delayed command is completed. 

SPLIT SCREEN 2 (l/SRK)]) - This bit is set when a match 
occurs between the current character row number and the 
value contained in split register 2 (IR13[6:0]>. 



COMMANDS 

The AVDC commands are divided into two classes: the in- 
stantaneous commands which are executed immediately 
after they are invoked, and the delayed commands which 
may need to wait for a blanking interval prior to their execu- 
tion. Command formats are shown in Table 3. The com- 
mands are asserted by performing a write operation to the 
command register with the appropriate bit pattern as the 
data byte. 



TABLE 3 — AVDC COMMAND FORMATS 



D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 


Hex 


Command 


Instantaneous Commands 


0 


0 


0 


0 


0 


0 


0 


0 




Master Reset 


0 


0 


0 


1 


V 


V 


V 


V 




Load IR Pointer with Value V (V = 0 to 14) 


0 


0 


1 


d 


d 


d 


1 


0* 




Disable Graphics 


0 


0 


1 


d 


d 


d : 


. 1 


1* 




Enable Graphics 


0 


0 


1 


d 


1 


N 


d 


0* 




Display Off — Float DADD Bus if N = 1 


0 


0 


1 


d 


1 


N 


d 


1* 




Display On — Next Field (N = 1) or Scan Line (N = 0) 


0 


0 


1 


1 


d 


d 


d 


0* 




Cursor Off 


0 


0 


1 


1 


d 


d 


d 


1* 




Cursor On 


0 


1 ' 


0 


N 


N 


N 


N 


N 




Reset Interrupt/Status: bit Reset where N=1 


1 


0 


0 


, N 


N :, 


N 


N 


N 




Disable Interrupt: Disable where N = 1 


0 


1 . 


1 


N 


N 


N 


N 


N 




Enable Interrupt: Enables Interrupts where N = 1 








V 


L 


S 


R 


S 




Interrupt Bit 








B 


2. 


P 


D 


P 




Assignments 












1 


Y 


2 






Delayed Commands 




0 


1 


0 


0 


1 


0 


0 


A4 


Read at Pointer Address 




0 


1 


0 


0 


0 


1 


0 


A2 


Write at Pointer Address 




.0,. 


,, 1 . 


0 


.1 


0 


0 


1 


A9 


Increment Cursor Address 




0 


... i . 


0 


1 


1 


0 


0 


AC 


Read at Cursor Address 




0 


1 


0 


1 


0 


1 


0 


AA 


Write at Cursor Address 




0 


1 


0 


. T • , 


1 


0 


1 


AD 


Read at Cursor Address and Increment Address 




0 


1 


0 


.1 


0 


1 


t 


AB 


Write at Cursor Address and Increment Address 




0 


1 


1 


1 


0 


1 


1 


BB 


Write from Cursor Address to Pointer Address 




0 


1 


1 


1 


1 


0 


1 


BD 


Read from Cursor Address to Pointer Address 



NOTES: 

*Any combination of these three commands is valid. 
d = Don't care. 



MOTOROLA MICROPROCESSOR DATA 
3-58 



MC2674 



INSTANTANEOUS COMMANDS 

The instantaneous commands are executed immediately 
after the trailing edge of the write pulse during which the 
command is issued. These commands do not affect the state 
of the RDFLG or READY interrupt/ status bits and can be in- 
voked at any time. 

MASTER RESET 

This command initializes the AVDC and can be invoked at 
any time to return the AVDC to its initial state. Upon power- 
up, two successive master reset commands must be applied 
to release the AVDC's internal power-on circuits. In 
transparent and shared buffer modes, the CTRL1 input must 
be high when the command is issued. The command causes 
the following: 

1. VSYNC and HSYNC are driven low for the duration of 
the command and BLANK goes high. After command 
completion, HSYNC and VSYNC will begin operation 
and BLANK will remain high until a "display on" com- 
mand is received. 

2. The interrupt and status bits and masks are set to zero, 
except for the RDFLG flag which is set to a one. 

3. The row buffer mode, cursor-off, display-off, and line 
graphics disable states are set. 

4. The initialization register pointer is set to address IRO. 

5. IR2[7] is reset. 

LOAD IR ADDRESS 

This command is used to preset the initialization register 
pointer with the value "V" defined by D3-D0. Allowable 
values are 0 to 14. 

ENABLE GRAPHICS 

After invoking this command, the AVDC will increment 
the MAC to the next consecutive memory address for each 
scan line even if more than one scan line per row is program- 
med. This mode can be used for bit-mapped graphics where 
each location in the display buffer within the defined area 
contains the bit pattern to be displayed. This command is 
row buffered and should be asserted during the character 
row prior to the row where this feature is required. This 
allows the user to enter and exit graphics mode on character 
row boundaries. 

To perform split screen operations while in graphics mode 
use SSR2 only. 

DADDO/LG is asserted during the trailing edge of BLANK 
for each scan line while this mode is active. 

DISABLE GRAPHICS 

Normal addressing resumes at the next row boundary. 

DISPLAY OFF 

Asserts the BLANK output. The DADDO through DADD13 
display address bus outputs can be optionally placed in the 
three-state condition by setting bit 2 to a one when invoking 
the command. 



DISPLAY ON 

Restores normal blanking operation either at the beginning 
of the next field (bit 2=1) or at the beginning of the next 
scan line (bit 2 = 0). Also returns the DADD0-DADD13 
drivers to their active state. 

CURSOR OFF 

Disables cursor operation. Cursor output is placed in the 
low state. 

CURSOR ON 

Enables normal cursor operation. 

RESET INTERRUPT/STATUS BITS 

This command resets the designated bits in the interrupt 
and status registers. The bit positions correspond to the bit 
positions in the registers: 

BitO - Split 2 

Bit 1 - Ready 

Bit 2 — Split 1 

Bit 3 — Line Zero 

Bit 4 - Vertical Blank 

DISABLE INTERRUPTS 

Sets the interrupt mask to zeros for the designated condi- 
tions, thus disabling these conditions from being set in the 
interrupt register and asserting the INTR output. Bit position 
correspondence is as above. 

ENABLE INTERRUPTS 

This command writes the associated interrupt mask bit to 
a one. This enables the corresponding conditions to be set in 
the interrupt register and asserts the INTR output. Bit posi- 
tion correspondence is as above. 

DELAYED COMMANDS 

This group of commands is utilized for the independent 
buffer mode of operation, although the "increment cursor" 
command can also be used in other modes. With the excep- 
tion of the "write from cursor to pointer" and "increment 
cursor" commands, all the commands of this type will be 
executed immediately or will be delayed depending on when 
the command is invoked. If invoked during the active screen 
time, the command is executed at the next horizontal blank- 
ing interval. If invoked during a vertical retrace interval or a 
"display off" state, the command is executed immediately. 

The "increment cursor" command is executed immedi- 
ately after it is issued and requires approximately three CCLK 
periods for completion. The "write from cursor to pointer" 
command executes during blanking intervals. The AVDC will 
execute as many writes as possible during each blanking 
interval. If the command is not completed during the current 
blanking interval, the command will be held in suspension 
during the next active portion of the screen and continues 
during the next blanking interval until the command is 
completed. 



ORDERING INFORMATION (Vcc = 5 V±5%, T A = 0°C to 70°C) 



Package Type 


Frequency 


Order Number 


Plastic 
P Suffix 


2.7 MHz 
4.0 MHz 


MC2674B3P 
MC2674B4P 



MOTOROLA MICROPROCESSOR DATA 
3-59 



MC2674 



PIN ASSIGNMENT 




R 
CE 
W [ 

CTRL1 I 
CTRL2 
CTRL3 
CURSOR 
DO 
D1 
D2 
D3 
D4 
D5 
D6 
D7 
CCLK 



BLANK 
VSYNC/ 
CSYNC 
HSYNC 



GND 1 20 



1 • 

2 
3 
4 



[5 
[6 
[ 7 
t 8 
[9 

Q10 
11 

12 
13 
14 
15 



qi6 

17 
18 
19 



40 
39 
38 
37 
36 
35h 



3 v cc 

] A2 
3 A1 

AO 

ACLL 
INTR 



DADDO/LG 
DADD1/ 
DADD14 
DADD2/ 
DADD15 
] DADD3/LR 

] DADD4/LA0 

DADD5/LA1 

DADD6/LA2 

DADD7/LA3 

] DADD8/FL 

] DADD9/DW 

] DADD10/UL 

T DADD11/ 
J BLINK 
1 DADD12/ 
J ODD 

] DADD13/LL 



MOTOROLA MICROPROCESSOR DATA 
3-60 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 



MC6800 



8-Bit Microprocessing Unit (MPU) 

The MC6800 is a monolithic 8-bit microprocessor forming the central control function for Motorola's 
M6800 Family. Compatible with TTL, the MC6800, as with all M6800 system parts, requires only one 
+ 5.0-volt power supply and no external TTL devices for bus interface. 

The MC6800 is capable of addressing 64K bytes of memory with its 16-bit address lines. The 8-bit data 
bus is bidirectional as well as three-state, making direct memory addressing and multiprocessing applica- 
tions realizable. 

• 8-Bit Parallel Processing 

• Bidirectional Data Bus 

• 16-Bit Address Bus — 64K Bytes of Addressing 

• 72 Instructions — Variable Length 

• Seven Addressing Modes — Direct, Relative, Immediate, Indexed, Extended, Implied, and 
Accumulator 

• Variable Length Stack 

• Vectored Restart 

• Maskable Interrupt Vector 

• Separate Nonmaskable Interrupt — Internal Registers Saved in Stack 

• Six Internal Registers — Two Accumulators, Index Register, Program Counter, Stack Pointer and 
Condition Code Register 

• Direct Memory Addressing (DMA) and Multiple Processor Capability 

• Simplified Clocking Characteristics 

• Clock Rates as High as 2.0 MHz 

• Simple Bus Interface without TTL 

• Halt and Single Instruction Execution Capability 




This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-61 



MC6800 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


vcc 


-0.3 to +7.0 


V 


Input Voltage 


Vin 


-0.3 to +7.0 


v : 


Operating Temperature Range 
MC6800, MC68A00, MC68B00, 
MC6800C, MC68A00C 


T A 


T L toT H 
-0to70 
-40 to + 85 


°c 


Storage Temperature Range 


T stg 


-55 to +150 


°c 


THERMAL RESISTANCE 


Rating 


Symbol 


Value 


Unit 


Plastic Package 
Cerdip Package 


ejA 


100 
60 


°c/w 



POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj = T A +(PD-ejA) (D 




= Ambient Temperature, °C 
= Package Thermal Resistance, 
Junction-to-Ambient, °C/W 
= P|NT+PP0RT 

= 'CC xV CC' Watts — Chip Internal Power 
= Port Power Dissipation, Watts — User Determined 



For most applications PpORT<P|NT ar >d can De neglected. PpORT may become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpORT ,s neglected) is: 

PD= K : (Tj+273°C) (2) 

Solving equations (1) and (2) for K gives: 

K = PD*(T A + 273°C) + ejA'PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pq (at 
equilibrium) for a known T A . Using this value of K, the values of Pq and Tj can be obtained by solving equations 
(1) and (2) iteratively for any value of Ta 



DC ELECTRICAL CHARACTERISTICS (V cc = 5.0 Vdc, ±5%, Vss = 0, Ta = T|_ to Th unless otherwise noted) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Input High Voltage 


Logic 
01,02 


V|H 
V IHC 


Vss + 2.0 
V C c -0.6 




Vcc 

V C C + 0.3 


V 


Input Low Voltage 


Logic 

01,02 


V|L 
V|LC 


Vss-0.3 
Vss-0.3 




Vss + 0.8 
Vss + 0.4 


V 


Input Leakage Current 
(Vj n = 0 to 5.25 V, Vqc = Max) 
<V ln =0 to 5.25 V, Vcc = 0 V to 5.25 V) 


Logic 

01,02 


lin 




1.0 


2.5 
100 


/«A 


Hi-Z Input Leakage Current 
(V in = 0.4 to 2.4 V, V C c = Max) 


D0-D7 
A0-A15, R/W 


hz 




2.0 


10 
100 


fA 


Output High Voltage 
(lLoad=-205MA, V C C=Min) 
<lLoad=-145MA, v C C=Min) 
<lLoad=-100^A, Vrx=Min> 


D0-D7 

A0-A15, R/W, VMA 
BA 


VOH 


Vss + 2.4 
Vss + 2.4 
Vss + 2.4 






V 


Output Low Voltage dLoad = 1-6 mA, Vcc=Min) 


vol 






Vss + 0.4 


V 


Internal Power Dissipation (Measured at Ta = T|_) 


pint 




0.5 


1.0 


w 


Capacitance 
(V in = 0, T A = 25°C, f = 1 .0 M Hz) 


01 

02 
D0-D7 
Logic Inputs 
A0-A15, R/W, VMA 


c in 
c out 




25 
45 
10 
6.5 


35 
70 
12.5 
10 
12 


PF 
PF 



MOTOROLA MICROPROCESSOR DATA 
3-62 



MC6800 



CLOCK TIMING (Vcc=5.0 V- *5%, Vss=0. Ta=T|_ to Th unless otherwise noted) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Frequency of Operation 


M LooUU 




0.1 




1.0 






[VI ^DOMvAJ 


f 


0.1 




1.5 


MHz 




kipcoonn 

MOOoDUU 




0.1 


_ 


2.0 




Cycle Time (Figure 1) 


MC6800 




1.000 




10 






MC68A00 


*cyc 


0.666 




10 


fiS 




MC68B00 


0.500 


- 


10 




C\nrk Pukp Width 


01, 02 — MC6800 




400 


_ 


9500 




(Measured at Vcc - 0.6 V) 


01,02 - MC68A00 


PW^h 


230 


_ 


9500 


ns 




01,02 - MC68B00 


180 


- 


9500 




Total 01 and 02 Up Time 


MC6800 




900 










MC68A00 


t ut 


600 






ns 




MC68B00 




440 








Rise and Fall Time (Measured between Vjjs + 0.4 and Vcc - 


0.6) 


tr.tf 






100 


ns 


Delay Time or Clock Separation (Figure 1) 














(Measured at Vov = Vss + 0 -6 V@t r = tfs100 ns) 




t d 


0 




9100 


ns 


(Measured at Vov = Vss + 1-0 V@t r =tf£35 ns) 






0 




9100 





FIGURE 1 - CLOCK TIMING WAVEFORM 



01 



02 



0r — 1 h— PW^h 
V IHC 



td 



1cV| H 

V V° 
V ILC ^ 




\ 



t0f 



NOTES: 

1. Voltage levels shown are V|_<0.4, Vh^2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted. 



READ/WRITE TIMING (Reference Figures 2 through 6, 8, 9. 11. 12 and 13) 



Characteristic 


Symbol 


MC6800 


MC68AO0 


MC68B00 


Unit 


Min 


Typ 


Max 


Min 


Typ 


Max 


Min 


Typ 


Max 


Address Delay 
























C = 90pF 


tAD 






270 






180 






150 


ns 


C = 30 pF 








250 






165 






135 




Peripheral Read Access Time 
tacc = tut-<tAD + tDSR! 


l acc 


530 






360 






250 






ns 


Data Setup Time (Read) 


tDSR 


100 






60 






40 






ns 


Input Data Hold Time 


tH 


10 






10 






10 






ns 


Output Data Hold Time 


tH 


10 


25 




10 


25 




10 


25 




ns 


Address Hold Time (Address, R/W, VMA) 


tAH 


30 


50 




30 


50 




30 


50 




ns 


Enable High Time for DBE Input 


tEH 


450 






280 






220 






ns 


Data Delay Time (Write) 


tDDW 






225 






200 






160 


ns 


Processor Controls 
























Processor Control Setup Time 


tpcs 


200 






140 






110 








Processor Control Rise and Fall Time 


tpCr. tpcf 






100 






100 






100 




Bus Available Delay 


tBA 






250 






165 






135 


ns 


Hi-Z Enable 


tTSE 


0 




40 


0 




40 


0 




40 


Hi-Z Delay 


tTSD 






270 






270 






220 




Data Bus Enable Down Time During 01 Up Time 


t DB E 


150 






,120 






75 








Data Bus Enable Rise and Fall Times 


tDBEr. tDBEf 






25 






25 






25 





MOTOROLA MICROPROCESSOR DATA 
3-63 



MC6800 



FIGURE 2 - READ DATA FROM MEMORY OR PERIPHERALS 

. Start of Cycle 



02 



Add rets 

From MPU 



Oats 
From Memory 
or Peripherals 



Data Not Valid 



01 ; r 



V|HC 
VlLC, 



\ 



/ 



- 'AD- 



-t AD - 



FIGURE 3 - WRITE IN MEMORY OR PERIPHERALS 
— Start of Cycle 



01 



l cyc- 



02 



Address 

From MPU 



V IHC 
VlLC 



\ 



-'AD- 



•'AD- 



VlLC 



V|HC 



—'AH 



— 'H 



-'DSR — 



VlLC 



\ 



■•■'AH 



-'DBE- 



■ 'DBEf . 



Data 

From MPU 



Data Not Valid 



— 'DBE 




1 



-*DDW 



NOTES: 

1. Voltage levels shown are V|_s0.4, V(-|£2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted. 



MOTOROLA MICROPROCESSOR DATA 
3-64 



MC6800 



FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY 
versus CAPACITIVE LOADING (T DDW ) 



l0H--205jiAmax@2 
" Iol ■ 1.6 mA max @0. 

Vrr = 5.0V 


4V 
















IV 
















TA 


= 25°C 




































































































































































































































Cl ir 


eludes stray c 


apacitance 



200 300 400 

C L , LOAD CAPACITANCE (pF) 



FIGURE 5 - TYPICAL READ/WRITE, VMA, AND ADDRESS 
OUTPUT DELAY versus CAPACITIVE LOADING (T AD ) 



bUU 
500 
400 


lOH =-145 /iA max @ 2 
" 10 L = '-6 mA max @ 0.4 

Vrr = 5.0 V 


4V 
















V 
















TA = 


25°C 






















































































VMA 








300 


















I 

ArlHracc B/\ 


V — 




























200 

100 
n 
























































































Cl ir 


eludes 


stray capacitance 



100 



200 300 400 

Cl, LOAD CAPACITANCE (pF) 



600 



FIGURE 6 - BUS TIMING TEST LOADS 



1 v cc 



Test Point O— 



R L " 2.2 kfi 

MMD6150 
, or Equiv. 



MMD 7000 
or Equiv. 



C = 130 pF for DO-D7, E 

= 90 pF for AO-A15, R/W, and VMA 

(Except t AD 2) 
= 30 pF for AO-A15, R/W, and VMA 

(t AD 2 only) 
= 30 pF for BA 
R = 11.7 kft for D0-D7 

= 16.5 kft for A0-A15, R/W, and VMA 
= 24 kfi for BA 



TEST CONDITIONS 

The dynamic test load for the Data Bus is 
130 pF and one standard TTL load as shown. 
The Address, R/v7, and VMA outputs are tested 
under two conditions to allow optimum opera- 
tion in both buffered and unbuffered systems. 
The resistor (R) is chosen to insure specified 
load currents during V OH measurement. 

Notice that the Data Bus lines, the Address 
lines, the Interrupt Request line, and the DBE 
line are all specified and tested to guarantee 
0.4 V of dynamic noise immunity at both 
"1" and "0" logic levels. 



I 



MOTOROLA MICROPROCESSOR DATA 
3-65 



MC6800 



Clock, *1 
Clock, $2 
RESIT 

Non-Maskable Interrupt 
HALT 
Interrupt Request 
Three-State Control 
Data Bus Enable 
Bus Available 
Valid Memory Address 

Read/Write, R/W 



Vcc= pin8 
Vss = P«ns1,21 



FIGURE 7 - EXPANDED BLOCK DIAGRAM 

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 

Li t t t t t t Ml.U LLi 



Output 
Buffers 



Instruction 
Decode 

and 
Control 



Program 
Counter 



Stack 
Pointer 



Index 
Register H 



Instruction 
Register 



Data 
Buffer 



TTTTTTTT 

D7 D6 D5 D4 D3 D2 D1 DO 



Output 
Buffers 



Program 
Counter 



Stack 
Pointer 



Index 
Register ^ 



Accumulator 
A 



Accumulator 
B 



Condition 
Code 
Register 



ALU 



MOTOROLA MICROPROCESSOR DATA 
3-66 



MC6800 



MPU SIGNAL DESCRIPTION 



Proper operation of the MPU requires that certain control 
and timing signals be provided to accomplish specific func- 
tions and that other signal lines be monitored to determine 
the state of the processor. 

Clocks Phase One and Phase Two (01, 02) - Two pins 
are used for a two-phase non-overlapping clock that runs at 
the Vcc voltage level. 

Figure 1 shows the microprocessor clocks. The high level 
is specified at V|hg and the low level is specified at V|i_C- 
The allowable clock frequency is specified by f (frequency) . 
The minimum 01 and 02 high level pulse widths are specified 
by PW^h (pulse width high time) . To guarantee the required 
access time for the peripherals, the clock up time, t u t, is 
specified. Clock separation, td, is measured at a maximum 
voltage of Vov (overlap voltage). This allows for a multitude 
of clock variations at the system frequency rate. 



Address Bus (A0-A15) - Sixteen pins are used for the ad- 
dress bus. The outputs are three-state bus drivers capable of 
driving one standard TTL load and 90 pF. When the output is 
turned off, it is essentially an open circuit. This permits the 
MPU to be used in DMA applications. Putting TSC in its high 
state forces the Address bus to go into the three-state mode. 

Data Bus (D0-D7) - Eight pins are used for the data bus. 
It is bidirectional, transferring data to and from the memory 
and peripheral devices. It also has three-state output buffers 
capable of driving one standard TTL load and 130 pF. Data 
Bus is placed in the three-state mode when DBE is low. 

Data Bus Enable (DBE) - This level sensitive input is the 
three-state control signal for the MPU data bus and will 
enable the bus drivers when in the high state. This input is 
TTL compatible; however in normal operation, it would be 
driven by the phase two clock. During an MPU read cycle, 
the data bus drivers will be disabled internally. When it is 
desired that another device control the data bus, such as in 
Direct Memory Access (DMA) applications, DBE should be 
held low. 

If additional data setup or hold time is required on an MPU 
write, the DBE down time can be decreased, as shown in 
Figure 3 (DBE*02). T.he minimum down time for DBE is 
tDBE as shown. By skewing DBE with respect to E, data 
setup or hold time can be increased. 

Bus Available (BA) — The Bus Available signal will nor- 
mally be in the low state; when activated, it will go to the 
high state indicating that the microprocessor has stopped 
and th at the address bus is available. This will occur if the 
HALT line is in the low state or the processor is in the WAIT 
state as a result of the execution of a WAIT instruction. At 
such time, all three-state output drivers will go to their off 
state and other outputs to their normally inactive level. The 
processor is removed from the WAIT state by the occurrence 
of a maskable (mask bit l = 0) or nonmaskable interrupt. This 
output is capable of driving one standard TTL load and 
30 pF. If TSC is in the high state, Bus Available will be low. 

Read/ Write (R/W) - This TTL compatible output signals 
the peripherals and memory devices wether the MPU is in a 



Read (high) or Write (low) state. The normal standby state of 
this signal is Read (high). Three-State Control going high will 
turn Read/Write to the off (high impedance) state. Also, 
when the processor is halted, it will be in the off state. This 
output is capable of driving one standard TTL load and 
90 pF. 



RESET - The RESET input is used to reset and start the 
MPU from a power down condition resulting from a power 
failure or initial start-up of the processor. This level sensitive 
input can also be used to reinitialize the machine at any time 
after start-up. 

If a high level is detected in this input, this will signal the 
MPU to begin the reset sequence. During the reset se- 
quence, the contents of the last two locations (FFFE, FFFF) 
in memory will be loaded into the Program Counter to point 
to the beginning of the reset routine. During the reset 
routine, the interrupt mask bit is set and must be cleared 
unde r progr am cont rol before the MPU can be interrupted by 
IRQ. While RESET is low (assuming a minimum of 8 clock 
cycles have occurred) the MPU output signals will be in the 
following states: VMA = low, BA=low, Data Bus = high im- 
pedance, R/W = high (read state), and the Address Bus will 
contain the reset addre ss FFFE . Figure 8 illustrates a power 
up sequence using the RESET control line. After the power 
supply reaches 4.75 V, a minimum of eight clock cycles are 
required for the processor to stabilize in preparation for 
restarting. During these eight cycles, VMA will be in an in- 
determinate state so any devices that are enabled by VMA 
which could accept a false write during this time (such as 
battery-backed RAM) must be disabled until VMA is forced 
low after eight cycles. RESET can go high asynchronously 
with the system clock any time after the eighth cycle. 



RESET timing is shown in Figure 8. The maximum r ise and 
fall transition times are specified by tprjr and tpcf • If RESET 
is high at tpcs (processor control setup time), as shown in 
Figure 8, in any given cycle then the r estart se quence will 
begin on the next cycle as shown. The RESET control line 
may also be used to reinitialize the MPU system at any time 
during its operation. This is accomplished by pulsing RESET 
low for the duratio n of a minimum of three complete 02 
cycles. The RESET pulse can be completely asynchronous 
with the MPU system clock and will be recognized during 02 
if setup time tpcs is met. 

Interrupt Request (IRQ) - This level sensitive input re- 
quests that an interrupt sequence be generated within the 
machine. The processor will wait until it completes the cur- 
rent instruction that is being executed before it recognizes 
the request. At that time, if the interrupt mask bit in the Con- 
dition Code Register is not set, the machine will begin an in- 
terrupt sequence. The Index Register, Program Counter, Ac- 
cumulators, and Condition Code Register are stored away on 
the stack. Next, the MPU will respond to the interrupt re- 
quest by setting the interrupt mask bit high so that no further 
interrupts may occur. At the end of the cycle, a 16-bit ad- 
dress will be loaded that points to a vectoring address which 
is located in memory locations FFF8 and FFF9. An address 
loaded at these locations causes the MPU to branch to an in- 
terrupt routine in memory. Interrupt timing is shown in 
Figure 9. 




MOTOROLA MICROPROCESSOR DATA 
3-67 



CO 



1 1 Cycle | 




1 1 • *» .1 


#2 | | 



FIGURE 8 - RESET TIMING 

#7 #8 #9 n n+1n + 2 n + 3 n + 4 n + 5 



+ 1 m + 2 m + 3 



02 



_rLTLn,jTJxji 



Power On f~ 
Switch J 

Power 



.5.25 V 



Supply —fit 4 75 v 



n_n_n_r 



RESET 



-Vr 



Address 
Bus 



wwwwwwwwwwwwwwww 



jMMMMMMMMMM ~Xj? 

, '. FF FE 7/FFFE FFFE FFFE FFFF New PC 




-tpcs 



tpCr 




VMA ( 
Data Bus 

BA 



-ff- 



FFFE FFFE 



liittiiii^ 



PC 8-15 PC 0-7 First 

Instruction 



»\\\\\\M = Indeterminate 



FIGURE 9 - INTERRUPT TIMING 



Cycle i j j I j i I | 

#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 



o 

CT> 
00 



_TL 



Address -v/- 
Bus _X_ 



IRQ or 
NMI 

Interrupt 
Mask 



v — — v v y — — v v v v v 

A A A A A_ -A A A A 



Next I nst 
Fetch 



SP(n) SP(n-1) SP(n-2) SP(n-3) SP(n-4) SP(n-5) SP(n-6) SP(n-7) FFF8 FFF9 New PC 

Address Address Address 



• tPCS 



— y v y — — y y~ 

A A A A A 



Inst (x) 



PC 0-7 PC 8-1 5 X 0-7 X8-15 ACCA ACCB 



y 



CCR New PC 8-15 New PC 0-7 First Inst of 

Address Address Interrupt Routine 



MC6800 



The HALT line must be in the high state for interr upts to 
be serviced. Interrupts will be latched internally while HALT 
is low. 

The IRQ has a high-impedance pullup device internal to 
the chip; however, a 3 kQ external resistor to Vcc should be 
used for wire-OR and optimum control of interrupts. 

Non-Maskable Interrupt (NMI) and Wait for Interrupt 
(WAD - The MC6800 is capable of handling two types of in- 
terrupts: maska ble (IRQ) as described earlier, an d no n- 
maskable (NMI) which is an edge sensitive input. IRQ is 
mask able b y the interrupt mask in the condition code register 
while NMI is not maskable. The handling of these interrupts 
by the MPU is the same except that each has its own vector 
address. The behavior of the MPU when interrupted is 
shown in Figure 9 which details the MPU response to an in- 
terrupt while the MPU is executing the cont rol program. The 
interrupt shown could be either IRQ" or NMI and can be asyn- 
chronous with respect to <t>2. The interrupt is shown going 
low at time tpcs in cycle #1 which precedes the first cycle of 
an instruction (OP code fetch). This instruction is not ex- 
ecuted but instead the Program Counter (PC), Index 
Register (IX), Accumulators (ACCX), and the Condition 
Code Register (CCR) are pushed onto the stack. 

The Interrupt Mask bit is set to prevent further interrupts. 
The address of the inter rupt service routine is then fetched 
from FFFC, FFFD for an NMI interrupt and from FFF8, FFF9 
for an IRQ interrupt. Upon completion of the interrupt ser- 
vice routine, the execution of RTI will pull the PC, IX, ACCX, 
and CCR off the stack; the Interrupt Mask bit is restored to 
its condition prior to Interrupts (see Figure 10). 

Figure 11 is a similar interrupt sequence, except in this 
case, a WAIT instruction has been executed in preparation 
for the interrupt. This technique speeds up the MPU's 
response to the interrupt because the stacking of the PC, IX, 
ACCX, and the CCR is already done. While the MPU is 
waiting for the interrupt, Bus Available will go high in- 
dicating the following states of the control lines: VM A is low, 
and the Address Bus, R/W and Data Bus are all in the high 
impedance state. After the interrupt occurs, it is serviced as 
previously described. 

A 3-10 k8 external resistor to Vrjc should be used for wire- 
OR and optimum control of interrupts. 

MEMORY MAP FOR INTERRUPT VECTORS 



Vector 


Description 


MS 


LS 


FFFE 


FFFF 


Reset 


FFFC 


FFFD 


Non-Maskable Interrupt 


FFFA 


FFFB 


Software Interrupt 


FFF8 


FFF9 


Interrupt Request 



Refer to Figure 10 for program flow for Interrupts. 

Three-State Control (TSC) - When the level sensitive 
Three-State Control (TSC) line is a logic "1", the Address 
Bus and the R/W line are placed in a high-impedance state. 
VMA and BA are forced low when TSC="1" to prevent 
false reads or writes on any device enabled by VMA. It is 
necessary to delay program execution while TSC is held 
high. This is done by insuring that no transitions of 01 (or 02) 
occur during this period. (Logic levels of the clocks are irrele- 
vant so long as they do not change). Since the MPU is a 
dynamic device, the 01 clock can be stopped for a maximum 



time PW^h without destroying data within the MPU. TSC 
then can be used in a short Direct Memory Access (DMA) 
application. 

Figure 12 shows the effect of TSC on the MPU. TSC must 
have its transitions at tTSE (three-state enable) while holding 
01 high and 02 low as shown. The Address Bus and R/W 
line will reach the high-impedance state at tTSD (three-state 
delay), with VMA being forced low. In this example, the 
Data Bus is also in the high-impedance state while 02 is be- 
ing held low since DBE=02. At this point in time, a DMA 
transfer could occur on cycles #3 and #4. When TSC is 
returned low, the MPU Address and R/Wlines return to the 
bus. Because it is too late in cycle #5 to access memory, this 
cycle is dead and used for synchronization. Program execu- 
tion resumes in cycle #6. 

Valid Memory Address (VMA) — This output indicates to 
peripheral devices that there is a valid address on the address 
bus. In normal operation, this signal should be utilized for 
enabling peripheral interfaces such as the PIA and ACIA. 
This signal is not three-state. One standard TTL load and 
90 pF may be directly driven by this active high signal. 

HALT - When this level sensitive input is in the low state, 
all activity in the machine will be halted. This input is level 
sensiti ve. 

The HALT line provides an input to the MPU to al low co n- 
trol of program execution by an outside source. If HALT is 
high, the MPU will execute the instructions; if it is low, the 
MPU will go to a halted or idle mode. A response signal, Bus 
Available (BA) provides an indication of the current MPU 
status. When BA is low, the MPU is in the process of ex- 
ecuting the control program; if BA is high, the MPU has 
halted and all internal activity has stopped. _ 

When BA is high, the Address Bus, Data Bus, and R/W 
line will be in a high-impedance state, effectively removing 
the MPU from the system bus. VMA is forced low so that the 
floating system bus will not activate any device on the bus 
that is enabled by VMA. 

While the M PU is h alted , all program activity is stopped, 
and if either an NMI or IRQ interrupt occurs, it will be latched 
into the MPU and acted on as so on as the MPU is taken out 
of the halted mode. If a RESET command occurs while the 
MPU is halted, the following states occur: VMA=low, 
BA=low, Data Bus=high impedance, R/W= high (read 
state), and the Address Bus will co ntain ad dress FFFE as 
long as RESET is low. As soon as the RESET line goes high, 
the MPU will go to locations FFFE and FFFF for the address 
of the reset routine. 

Figure 13 shows the timing relationships involved when 
halting the MPU. The instruction illustr ated is a one byte, 2 
cycle instruction such as CLRA. When HALT goes low, the 
MPU will halt after complet ing exe cution of the current in- 
struction. The transition of HALT must occur tpcs before 
the trailing edge of 0 1 of th e last cycle of an instruction 
(point A of Figure 13). HALT must not go low any time later 
than the minmum tpcs specified. 

The fetch of the OP co de by the MPU is the first cycle of 
the instruction. If HALT had not been low at Point A but 
went low during 02 of that cycle, the MPU would have 
halted after completion of the following instruction. BA will 
go high by time tBA (bus available delay time) after the last 
instruction cycle. At this point in time, VMA is low and R/W, 
Address Bus, and the Data Bus are in the high-impedance 
state. 



MOTOROLA MICROPROCESSOR DATA 
3-69 



MC6800 



To debug programs it is advantageous to step through 
programs instruction by instruction. To do this, HALT must 
be brought high for one MPU cycle and then returned low as 
shown at point B of Figure 13. Again, the transitions of 
HALT must occur tpcs before the trailing edge of 01. BA 
will go low at tjjA after the leading edge of the next *1, irw 
dicating that the Address Bus, Data Bus, VMA and R/W 



lines are back on the bus. A single byte, 2 cycle instruction 
such as LSR is used for this example also. During the first cy- 
cle, the instruction Y is fetched from address M + 1. BA 
returns high at tfjA on the last cycle of the instruction in- 
dicating the MPU is off the bus. If instruction Y had been 
three cycles, the width of the BA low time would have been 
increased by one cycle. 



FIGURE 10 - MPU FLOWCHART 



a 





Halt 


^flACT? 


r- 


Y 


1 — BA 




[is 


^HALT?^ 




In 


0 -►BA 










— Jn 



Q RESET ^ 



(See Note 3) 
TAP? 



Modify I 




Stack 
PC, X, A, B, CC 




0 — BA 



1-*-ITMP 
1 — 1 



Vector PC 


NMI 


FFCA 


SWI 


FFFA 


IRQ 


FFF8 



Condition Code Register 
|1|1|H|||N|Z|V|C 



'ITEMP' 1-Bit 
Buffer Register 



Notes: 

1 . Reset is recognized at any position in the flowchart. 

2. Instructions which affect the l-Bit act upon a one-bit buffer register, 
"ITMP." This has the effect of delaying any CLEARING of the l-Bit one 
clock time. Setting the l-Bit, however, is not delayed. 

3. See Tables 6-11 for details of Instruction Execution. 



MOTOROLA MICROPROCESSOR DATA 
3-70 



FIGURE 11 - WAIT INSTRUCTION TIMING 

#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 n n+1n + 2 n + 3 n + 4 n + 5 




Interrupt 
Mask 



Wait 
inst 



PC 0-7 PC 8-1 5 I 0-7 18-15 ACCA ACCB CCR 



Note: Midrange waveform indicates 
high impedance state. 



■<=x=xzzx 

SP(n-7) FFF8 FFF9 



♦-tpcs 



s 



First Inst 
of Interrupt 
Routine 




New PC 8-15 New PC 0-7 
Address Address 



FIGURE 12 - THREE-STATE CONTROL TIMING 

*5 | =6 




02 » DBE 



MC6800 



FIGURE 13 - HALT AND SINGLE INSTRUCTION EXECUTION FOR SYSTEM DEBUG 




Data 
Bus 



DOCZX> 



Inst 
X 



-ooooo- 

Inst 



Note: Midrange waveform indicates 
high impedance state. 



MPU REGISTERS 



The MPU has three 16-bit registers and three 8-bit 
registers available for use by the programmer (Figure 14). 

Program Counter - The program counter is a two byte 
(16 bits) register that points to the current program address. 

Stack Pointer - The stack ponter is a two byte register 
that contains the address of the next available location in an 
external push-down /pop-up stack. This stack is normally a 
random access Read/Write memory that may have any loca- 
tion (address) that is convenient. In those applications that 
require storage of information in the stack when power is 
lost, the stack must be nonvolatile. 

Index Register — The index register is a two byte register 
that is used to store data or a sixteen bit memory address for 
the Indexed mode of memory addressing. 

Accumulators — The MPU contains two 8-bit ac- 
cumulators that are used to hold operands and results from 
an arithmetic logic unit (ALU). 



Condition Code Register - The condition code register in- 
dicates the results of an Arithmetic Logic Unit operation: 
Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C), 
and half carry from bit 3 (H). These bits of the Condition 
Code Register are used as testable conditions for the condi- 
tional branch instructions. Bit 4 is the interrupt mask bit (I). 
The unused bits of the Condition Code Register (b6 and b7) 
are ones. 



FIGURE 14 - PROGRAMMING MODEL OF 
THE MICROPROCESSING UNIT 



Accumulator A 
Accumulator B 
Index Register 
Program Counter 
Stack Pointer 



Condition Code 
Register 



L Carry (From Bit 7) 

— Overflow 

— Zero 

— Negative 

— Interrupt 

— Half Carry (From Bit 3) 



MOTOROLA MICROPROCESSOR DATA 
3-72 



MC6800 



MPU INSTRUCTION SET 



The MC6800 instructions are described in detail in the 
M6800 Programming Manual This Section will provide a 
brief introduction and discuss their use in developing 
MC6800 control programs. The MC6800 has a set of 72 dif- 
ferent executable source instructions. Included are binary 
and decimal arithmetic, logical, shift, rotate, load, store, 
conditional or unconditional branch, interrupt and stack 
manipulation instructions. 

Each of the 72 executable instructions of the source 
language assembles into 1 to 3 bytes of machine code. The 
number of bytes depends on the particular instruction and 
on the addressing mode. (The addressing modes which are 
available for use with the various executive instructions are 
discussed later.) 

The coding of the first (or only) byte corresponding to an 
executable instruction is sufficient to identify the instruction 
and the addressing mode. The hexadecimal equivalents of 
the binary codes, which result from the translation of the 72 
instructions in all valid modes of addressing, are shown in 
Table 1 . There are 197 valid machine codes, 59 of the 256 
possible codes being unassigned. 



When an instruction translates into two or three bytes of 
code, the second byte, or the second and third bytes con- 
taints) an operand, an address, or information from which an 
address is obtained during execution. 

Microprocessor instructions are often divided into three 
general classifications: (1) memory reference, so called 
because they operate on specific memory locations; (2) 
operating instructions that function without needing a 
memory reference; (3) I/O instructions for transferring data 
between the microprocessor and peripheral devices. 

In many instances, the MC6800 performs the same opera- 
tion on both its internal accumulators and the external 
memory locations. In addition, the MC6800 interface 
adapters (PIA and ACIA) allow the MPU to treat peripheral 
devices exactly like other memory locations, hence, no I/O 
instructions as such are required. Because of these features, 
other classifications are more suitable for introducing the 
MC6800's instruction set: (1) Accumulator and memory 
operations; (2) Program control operations; (3) Condition 
Code Register operations. 



TABLE 1 - HEXADECIMAL VALUES OF MACHINE CODES 



00 








40 


NEG 


A 




80 


SUB 


A 


IMM 


CO 


SUB 


Q 


IMM 


01 


NOP 






41 








81 


CMP 


A 


IMM 


C1 


CMP 


B 


IMM 


02 








42 








82 


SBC 


A 


IMM 


C2 


SBC 


B 


IMM 


03 








43 


COM 


A 




83 








C3 








04 








44 


LSR 


A 




84 


AND 


A 


IMM 


C4 


AND 


Q 


IMM 


05 








45 








85 


BIT 


A 


IMM 


C5 


BIT 


B 


IMM 


06 


TAP 






46 


ROR 


A 




86 


LDA 


A 


IMM 


06 


LDA 


B 


IMM 


07 


TPA 






47 


ASR 


A 




87 








C7 








08 


INX . 






48 


ASL 


A 




88 


EOR 


A 


IMM 


C8 


EOR 


B 


IMM 


09 


DEX 






49 


ROL 


A 




89 


ADC 


A 


IMM 


C9 


ADC 


B 


IMM 


OA 


civ . 






4A 


DEC 


A 




8A 


ORA 


A 


IMM 


CA 


ORA 


B 


IMM 


0B 


SEV 






4B 








8B 


ADD 


A 


IMM 


CB 


ADD 


B 


IMM 


OC 


CLC 






4C 


INC 


A 




8C 


CPX 


A 


IMM 


CC 








0D 


SEC 






4D 


TST 


A 




8D 


BSR 




REL 


CD 








0E 


CLI 






4E 








8E 


LDS 




IMM 


CE 


LDX 




IMM 


OF 


SEI 






4F 


CLR 


A 




8F 








CF 








10 


SBA 






50 


NEG 


B 




90 


SUB 


A 


DIR 


DO 


SUB 


B 


DIR 


11 


CBA 






51 








91 


CMP 


A 


DIR 


D1 


CMP 


B 


DIR 


12 








52 








92 


SBC 


A 


DIR 


D2 


SBC 


B 


DIR 


13 








53 


COM 


B 




93 








D3 








14 








54 


LSR 


B 




94 


AND 


A 


DIR 


D4 


AND 


B 


DIR 


15 








55 








95 


BIT 


A 


DIR 


DS 


BIT 


B 


DIR 


16 


TAB 






56 


ROR 


B 




96 


LDA 


A 


DIR 


D6 


LDA 


B 


DIR 


17 


TBA 






57 


ASR 


B 




97 


STA 


. A 


DIR 


D7 


STA 


B 


DIR 


18 








58 


ASL 


B 




98 


EOR 


A 


DIR 


D8 


EOR 


B 


DIR 


19 


DAA 






59 


ROL 


B 




99 


ADC 


A 


DIR 


D9 


ADC 


B 


DIR 


1A 






5A 


DEC 


B 




9A 


ORA 


A 


OIR 


DA 


ORA 


B 


DIR 


IB 


ABA 






5B 








9B 


ADD 


A 


DIR 


DB 


ADD 


B 


DIR 


1C 








5C 


INC 


B 




9C 


CPX 




DIR 


DC 








1D 








5D 


TST 


B 




9D 








DD 








1E 








5E 








9E 


LDS 




DIR 


DE 


LDX 




DIR 


1F 








5F 


CLR 


B 




9F 


STS 




DIR 


DF 


STX 




DIR 


20 


BRA 




REL 


60 


NEG 




IND 


AO 


SUB 


A 


IND 


E0 


SUB 


B 


IND 


21 








61 








A1 


CMP 


A 


IND 


E1 


CMP 


B 


IND 


22 


BHI 




REL 


62 








A2 


SBC 


A 


IND 


E2 


SBC 


B 


IND 


23 


BLS 




REL 


63 


COM 




IND 


A3 








E3 








24 


BCC 




REL 


64 


LSR 




IND 


A4 


AND 


A 


IND 


E4 


AND 


B 


IND 


25 


BCS 




REL 


65 








A5 


BIT 


A 


IND 


E5 


BIT 


B 


IND 


26 


BNE 




REL 


66 


ROR 




IND 


A6 


LDA 


A 


IND 


E6 


LDA 


B 


IND 


27 


BEQ 




REL 


67 


ASR 




IND 


A7 


STA 


A 


IND 


E7 


STA 


B 


IND 


28 


BVC 




REL 


68 


ASL 




IND 


A8 


EOR 


A 


INO 


E8 


EOR 


a 


IND 


29 


BVS 




REL 


69 


ROL 




IND 


A9 


ADC 


A 


IND 


E9 


ADC 


B 


IND 


2A 


BPL 




. REL 


6A 


DEC 




IND 


AA 


ORA 


A 


IND 


EA 


ORA 


B 


IND 


2B 


BMI 




REL 


6B 








AB 


ADD 


A 


IND 


EB 


ADD 


B 


IND 


2C 


BGE 




REL 


6C 


INC 




IND 


AC 


CPX 




IND 


EC 








2D 


BLT 




REL 


6D 


TST 




IND 


AD 


JSR 




IND 


ED 








2E 


BGT 




REL 


6E 


JMP 




IND 


AE 


LDS 




IND 


EE 


LDX 




IND 


2F 


BLE 




REL 


6F 


CLR 




IND 


AF 


STS 




IND 


EF 


STX 




IND 


30 


TSX 






70 


NEG 




EXT 


B0 


SUB 


A 


EXT 


FO 


SUB 


B 


EXT 


31 


INS 






71 








B1 


CMP 


A 


EXT 


F1 


CMP 


B 


EXT 


32 


PUL 


A 




72 








B2 


SBC 


A 


EXT 


F2 


SBC 


B 


EXT 


33 


PUL 


B 




73 


COM 




EXT 


B3 








F3 








34 


DES 






74 


LSR 




EXT 


B4 


AND 


A 


EXT 


F4 


AND 


B 


EXT 


35 


TXS 






75 








B5 


BIT 


A 


EXT 


F5 


BIT 


B 


EXT 


36 


PSH 


A 




76 


ROR 




EXT 


B6 


LDA 


A 


EXT 


F6 


LDA 


B 


EXT 


37 


PSH 


B 




77 


ASR 




EXT 


B7 


STA 


A 


EXT 


F7 


STA 


B 


EXT 


38 








78 


ASL 




EXT 


B8 


EOR 


A 


EXT 


F8 


EOR 


B 


EXT 


39 


RTS 






79 


ROL 




EXT 


B9 


ADC 


A 


EXT 


F9 


ADC 


B 


EXT 


3A 








7A 


DEC 




EXT 


BA 


ORA 


A 


EXT 


FA 


ORA 


B 


EXT 


3B 


RTI 






7B 








BB 


ADD 


A 


EXT 


FB 


ADD 


B 


EXT 


3C 








7C 


INC 




EXT 


BC 


CPX 




EXT 


FC 








3D 








7D 


TST 




EXT 


BD 


JSR 




EXT 


FD 








3E 


WAI 






7E 


JMP 




EXT 


BE 


LOS 




EXT 


FE 


LDX 




EXT 


3F 


SWI 






7F 


CLR 




EXT 


BF 


STS 




EXT 


FF 


STX 




EXT 




Notes: 1 . Addressing Modes. 



B 

REL 
IND 
IMM 
DIR 



= Accumulator A 
= Accumulator B 
= Relative 
= Indexed 
= Immediate 
- Direct 



2. Unassigned code indicated by ' 



MOTOROLA MICROPROCESSOR DATA 
3-73 



MC6800 



TABLE 2 - ACCUMULATOR AND MEMORY OPERATIONS 



ADDRESSING MODES 



BOOLEAN/ARITHMETIC OPERATION CONO. CODE REG. 



OPERATIONS 


MNEMONIC 


OP 


Add 


ADDA 


8B 




ADDB 


ce 


Add Acmltrs 


A8A 




Add with Carry 


, ADCA 


89 




ADCB 


C9 


And 


ANDA 


84 




AND 8 


C4 


Bit Test 


. BITA 


85 




BITB 


C5 


Clear 


' CLR 






' . CLRA 






CLRB 




Compare 


CMPA 


81 




• CMPB 


Ct 


Compare Acmltrs 


CBA 




Complement, Ts 


COM 






COMA 






COMB 




Complement. 2's 


NEG 




(Negate) 


NEGA 






NEGB 




Decimal Adjust, A 


OAA 





Exclusive OR 
Increment 

Load Acmltr 
Or. Inclusive 
Push Data 
Pull Oata 
Rotate Left 

Rotate Right 

Shift Left, Arithmetic 

Shift Right, Arithmetic 

Shift Right, Logic 

Store Acmltr. 
Subtract 

Subtract Acmltrs. 
Subtr. with Carry 

Transfer Acmltrs 

Test, Zero or Minus 



OEC 
OECA 
DECS 
EORA 
EORB 
INC 
INCA 
INCB 
LDAA 
LDAB 
ORAA 
ORAB 
PSHA 
PSHB 
PULA 
PUL8 
ROL 
ROLA 
ROLB 
ROR 
RORA 
RORB 
ASL 
ASLA 
ASLB 
ASR 
ASRA 
ASRB 
LSR 
LSRA 
LSRB 
STAA 
STAB 
SU6A 
SU86 
SBA 
SBCA 
SBCB 
TAB 
TBA 
TST 
TSTA 
TSTB 



BA 4 

FA ; 4. 



B7 5 3 

F7 S 3 

BO 4 3 

FO. 4 3 

B2 4 3 

F2 4 ,3 



(All register labels 
refer to contents) 



B + M + C -6 
A • M -A 
B " M ' B 
A ■ M 
B - M 
OD • M 



ffl * M 
S -A 
B *B . 
00 M >M 
00 ■ A -A 
00 B • B 

Converts Binary Add. of BCD Characters 
into BCD Format 
M - 1 • M 
A 1 -A 



A©M -A 
B©M — B 



M ' B 



B + M .- B 

A -Msp, SP - 1 - SP 
B 'M S p, SP - I -SP 
SP + 1 -SP, Msp -A 

sp * i -sp, msp -b 

B J C b7 - 



B-A 

- M - C - A 



LEGEND: 

OP Operation Code (Hexadecimal); 

Number of MPU Cycles; 
# Number of Program Bytes; 
+ Arithmetic Plus; 

Arithmetic Minus; 

Boolean AND; 

M$p Contents of memory location pointed to be Stack Pointer; 

+ Boolean Inclusive OR; 

© Boolean Exclusive OR; 

M Complement of M; 

-* Transfer Into; 

0 Bit = Zero; 

00 Byte « Zero; 



CONDITION CODE SYMBOLS: 

H ', Half-carry from bit 3; 

I . Interrupt mask 

N Negative (sign bit) 

Z Zero (byte) 

V Overflow, 2's complement 

C Carry from bit 7 

R Reset Always 

S Set Always 

t Test and set if true, cleared otherwise 

• Not Affected 



CONDITION CODE REGISTER NOTES: 

(Bit set if test is true and cleared otherwise) 



(Bit V) 
(Bit 0 
(Bit 0 



(Bit V) 
(Bit V) 
(Bit V) 



Test: Result = 10000000? 

Test: Result = 00000000? 

Test: Decimal value of most significant BCD 

Character greater than nine? 

(Not cleared if previously set.) 

Test: Operand = 10000000 prior to execution? 

Test: Operand = 01111111 prior to execution? 

Test: Set equal to result of N©C after shift has occurred. 



Note - Accumulator addressing mode instructions are included in the column for IMPLIED addressing 



MOTOROLA MICROPROCESSOR DATA 
3-74 



MC6800 



PROGRAM CONTROL OPERATIONS 



Program Control operation can be subdivided into two 
categories: (1) Index Register/ Stack Pointer instructions; (2) 
Jump and Branch operations. 

Index Register/ Stack Pointer Operations 

The instructions for direct operation on the MPU's Index 
Register and Stack Pointer are summarized in Table 3. 
Decrement (DEX, DES), increment (INX, INS), load (LDX, 
LDS), and store (STX, STS) instructions are provided for 
both. The Compare instruction, CPX, can be used to com- 
pare the Index Register to a 16-bit value and update the Con- 
dition Code Register accordingly. 

The TSX instruction causes the Index Register to be load- 
ed with the address of the last data byte put onto the 
"stack." The TXS instruction loads the Stack Pointer with a 
value equal to one less than the current contents of the Index 
Register. This causes the next byte to be pulled from the 
"stack" to come from the location indicated by the Index 
Register. The utility of these two instructions can be clarified 
by describing the "stack" concept relative to the M6800 
system. 

The "stack" can be thought of as a sequential list of data 
stored in the MPU's read/write memory. The Stack Pointer 
contains a 16-bit memory address that is used to access the 
list from one end on a last-in-first-out (LIFO) basis in contrast 
to the random access mode used by the MPU's other ad- 
dressing modes. 

The MC6800 instruction set and interrupt structure allow 
extensive use of the stack concept for efficient handling of 
data movement, subroutines and interrupts. The instructions 
can be used to establish one or more "stacks" anywhere in 
read/write memory. Stack length is limited only by the 
amount of memory that is made available. 

Operation of the Stack Pointer with the Push and Pull in- 
structions is illustrated in Figures 15 and 16. The Push in- 
struction (PSHA) causes the contents of the indicated ac- 
cumulator (A in this example) to be stored in memory at the 
location indicated by the Stack Pointer. The Stack Pointer is 
automatically decremented by one following the storage 
operation and is "pointing" to the next empty stack location. 
The Pull instruction (PULA or PULB) causes the last byte 
stacked to be loaded into the appropriate accumulator. The 



Stack Pointer is automatically incremented by one just prior 
to the data transfer so that it will point to the last byte stack- 
ed rather than the next empty location. Note that the PULL 
instruction does not "remove" the data from memory; in the 
example, 1 A is still in location (m + 1) following execution of 
PULA. A subsequent PUSH instruction would overwrite that 
location with the new "pushed" data. 

Execution of the Branch to Subroutine (BSR) and Jump to 
Subroutine (JSR) instructions cause a return address to be 
saved on the stack as shown in Figures 18 through 20. The 
stack is decremented after each byte of the return address is 
pushed onto the stack. For both of these instructions, the 
return address is the memory location following the bytes of 
code that correspond to the BSR and JSR instruction. The 
code required for BSR or JSR may be either two or three 
bytes, depending on whether the JSR is in the indexed (two 
bytes) or the extended (three bytes) addressing mode. 
Before it is stacked, the Program Counter is automatically in- 
cremented the correct number of times to be pointing at the 
location of the next instruction. The Return from Subroutine 
Instruction, RTS, causes the return address to be retrieved 
and loaded into the Program Counter as shown in Figure 21 . 

There are several operations that cause the status of the 
MPU to be saved on the stack. The Software Interrupt (SWI) 
and Wait forjnterrupt (WAD instru ction s as well as the 
maskable (IRQ) and non-maskable (NMD hardware inter- 
rupts all cause the MPU's internal registers (except for the 
Stack Pointer itself) to be stacked as shown in Figure 23. 
MPU status is restored by the Return from Interrupt, RTI, as 
shown in Figure 22. 

Jump and Branch Operation 

The Jump and Branch instructions are summarized in 
Table 4. These instructions are used to control the transfer or 
operation from one point to another in the control program. 

The No Operation instruction, NOP, while included here, 
is a jump operation in a very limited sense. Its only effect is to 
increment the Program Counter by one. It is useful during 
program development as a "stand-in" for some other in- 
struction that is to be determined during debug. It is also us- 
ed for equalizing the execution time through alternate paths 
in a control program. 



TABLE 3 - INDEX REGISTER AND STACK POINTER INSTRUCTIONS 



C0N0.C00E REG. 



POINTER OPERATIONS 


MNEMONIC 


IMMEO 


OIRECT 


INDEX 


EXTND 


IMPLIED 


BOOLEAN/ARITHMETIC OPERATION 


5 


4 


3 


2 


i 


0 


OP 






OP 






OP 






OP 






OP 






H 


1 


N 


Z 


v 


C 


Compare Index Reg 


CPX 


8C 


3 




3 


9C 


4 


2 


AC 


6 


2 


EC 


5 


3 








XH 


-M,X L - 


m* 


11 


• 


• 


© 


J 




• 


Oecrement Index Reg 


DEX 




























09 


4 


1 


X - 


1 -X 






• 


• 


• 


t 


• 


• 


Decrement Stack Pntr 


DES 




























34 


4 


1 


SP- 


1 -SP 


















Increment Index Reg 


INX 




























08 


4 


1 


X + 


1 - X 






• 


• 


• 


: 


• 


• 


Increment Stack Pntr 


INS 




























31 


4 


1 


SP + 


1 -SP 


















Load Index Reg 


LDX 


CE 


3 




3 


DE 


4 


2 


EE 


6 


2 


FE 


5 


3 








M - 


Xh.(M + 


11- 


<L 


• 


• 




j 


R 


• 


Load Stack Pntr 


LDS 


8E 


3 




3 


9E 


4 


2 


AE 


6 


2 


BE 


5 


3 








M- 


sph. im + 


1) - 


spl 


• 


• 


® 


i 


R 


• 


Store Index Reg 


STX 










DF 


5 


2 


EF 


7 


2 


FF 


6 


3 








XH 


-M. X L - 


(M + 


1) 


• 


• 


<D 


! 


R 


• 


Store Stack Pntr 


STS 










9F 


5 


2 


AF 


7 


2 


BF 


6 


3 








sp h 


-M.SPl 


— (M 


-HI 


• 


• 


(3) 


i 


R 


• 


Indx Reg - * Stack Pntr 


TXS 




























35 


4 


1 


X - 


1 -SP 


















Stack Pntr -Indx Reg 


TSX 




























30 


4 


1 


SP + 


1 - X 



















© (Bit N) Test: Sign bit of most significant (MS) byte of result = 1? 

@ (Bit V) Test: 2's complement overflow from subtraction of ms bytes? 

@) (Bit N) Test: Result less than zero? (Bit 15= 1) 



MOTOROLA MICROPROCESSOR DATA 

3-75 



MC6800 



FIGURE 16 - STACK OPERATION, PUSH INSTRUCTION 

MPU MPU 




- 2 

- 1 



Previously 
Stacked 
Data 





V 



ACCA | F3 | 



SP »- i 

New Data 



Previously 
Stacked 
Data 





4 



(a) Before PSHA 



(b) After PSHA 



FIGURE 16 - STACK OPERATION, PULL INSTRUCTION 

MPU MPU 



DEI 



Previously 
Stacked 
Data 



m - 2 




m - 1 




» m 




m + 1 


1A 


m + 2 


3C 


m + 3 


D5 




EC 



u 



ACCA I 1A | 



Previously 
Stacked 
Data 



m - 2 
m - 1 
m 

m + 1 
m + 2 
m + 3 




<•) Before PULA 



(b) After PULA 



MOTOROLA MICROPROCESSOR DATA 
3^76 



MC6800 



TABLE 4 - JUMP AND BRANCH INSTRUCTIONS 



CONO. CODE REG. 



*WAI puts Address Bus, R/W, and Data Bus in the three-state made while VMA is held low. 

© (All) Load Condition Code Register from Stack. (See Special Operations) 
(2) (Bit 1) Set when interrupt occurs. If previously set, a Non-Maskable Interrupt 
is required to exit the wait state. 







RELATIVE 


INOEX 


EXTND 


IMPLIED 




S 


4 


3 


2 


1 


0 


OPERATIONS 


MNEMONIC 


OP 




# 


OP 






OP 






OP 




# 


BRANCH TEST 


H 


1 


N 


Z 


V 


c 


Branch Always 


BRA 


20 


4 


? 




















None 








# 


# 




Branch If Carry Clear 


BCC 


24 


4 


2 




















C = 0 










# 


# 


Branch If Carry Set 


BCS 


25 


4 


2 




















C = 1 


# 






# 








BEQ 


27 


4 


2 




















Z = 1 








# 






Branch If > Zero 


B6E 


2C 


4 


2 




















N © V = 0 














Branch If ^Zero 


BGT 


2E 


4 


2 




















Z + (N © V) = 0 












# 




BHI 


22 


4 


2 




















C +<Z " 0 






* 








Branch If <S Zero 


BLE 


2F 


4 


2 




















Z + (N © V) = 1 




# 










Branch If Lo r Or Sam 




23 


4 


2 




















C + Z ■ 1 












# 


Branch If <zT ' 


BLT 


2D 


4 


2 




















' N © V = 1 














Branch If Min" 0 




2B 


4 


2 




















N = 1 














Branch If Not E I Zer 


BNE 


26 


4 


2 




















2 = 0 














Branch If Overflow Clear" 


BVC 


























V = 0 














Branch If Overflow Set 


BVS 


29 


4 


2 




















V= 1 














Branch If Plus 


BPL 


2A 


4 


2 




















N = 0 














Branch To Subroutine 


BSR 


80 


8 


2 


































Jump 


JMP 








6E 


4 


2 


7E 


3 


3 








| See Special Operations 














Jump To Subroutine 


JSR 








AD 


8 


2 


BD 


9 


3 






















No Operation 


NOP 




















01 


2 




Advances Prog. Cntr. Only 














Return From Interrupt 


RTI 






















10 




























3B 








- © 


Return From Subroutine 


RTS 




















39 


5 










• 








Software Interrupt 


SWI 




















3F 


12 




| See Special Operations 






• 








Wait for Interrupt* 


WAI 




















3E 


9 








• 









B 



Execution of the Jump Instruction, JMP, and Branch 
Always, BRA, affects program flow as shown in Figure 17. 
When the MPU encounters the Jump (Indexed) instruction, 
it adds the offset to the value in the Index Register and uses 
the result as the address of the next instruction to be ex- 
ecuted. In the extended addressing mode, the address of the 
next instruction to be executed is fetched from the two loca- 
tions immediately following the JMP instruction. The Branch 
Always (BRA) instruction is similar to the JMP (extended) in- 
struction except that the relative addressing mode applies 
and the branch is limited to the range within - 125 or + 127 
bytes of the branch instruction itself. The opcode for the 
BRA instruction requires one less byte than JMP (extended) 
but takes one more cycle to execute. 

The effect on program flow for the Jump to Subroutine 
(JSR) and Branch to Subroutine (BSR) is shown in Figures 
18 through 20. Note that the Program Counter is properly in- 
cremented to be pointing at the correct return address 
before it is stacked. Operation of the Branch to Subroutine 
and Jump to Subroutine (extended) instruction is similar ex- 
cept for the range. The BSR instruction requires less opcode 
than JSR (2 bytes versus 3 bytes) and also executes one cy- 



cle faster than JSR. The Return from Subroutine, RTS, is 
used as the end of a subroutine to return to the main pro- 
gram as indicated in Figure 21 . 

The effect of executing the Software Interrupt, SWI, and 
the Wait for Interrupt, WAI, and their relationship to the 
hardware interrupts is shown in Figure 22. SWI causes the 
MPU contents to be stacked and then fetches the starting 
address of the interrupt routine from the memory locations 
that respond to the addresses FFFA and FFFB. Note that as 
in the case of the subroutine instructions, the Program 
Counter is incremented to point at the correct return address 
before being stacked. The Return from Interrupt instruction, 
RTI, (Figure 22) is used at the end of an interrupt routine to 
restore control to the main program. The SWI instruction is 
useful for inserting break points in the control program, that 
is, it can be used to stop operation and put the MPU 
registers in memory where they can be examined. The WAI 
instruction is used to decrease the time required to service a 
hardware interrupt; it stacks the MPU contents and then 
waits for the interrupt to occur, effectively removing the 
stacking time from a hardware interrupt sequence. 



INDXD 



n+1 



FIGURE 17 - PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS 

PC Main Program 



PC Main Program 



6E=JMP 



K = Offset 



X+ K I Next Instruction 



EXTND 



(a) Jump 



n + 1 
n + 2 



7E = JMP 



Kn = Next Address 



K[_=Next Address 



Next Instruction 



n + 1 



Main Program 



2*= BRA 



K = Offset* 



(n + 2)±K I Next Instruction 



*K = Signed 7-bit value 
(b) Branch 



MOTOROLA MICROPROCESSOR DATA 

3-77 



MC6800 



3 



FIGURE 18 - PROGRAM FLOW FOR BSR 



m - 2 
m - 1 

SP *~ m 

m + 1 



n + 1 
n + 2 



±K - Offset* 



Next Main Instr. 



*K = Signed 7-Bit Value 



(a) Before Execution 



-m - 2 
m - 1 



n + 1 
n + 2 



(n + 2)L 



±K = Offset 



Next Main Instr. 



PC-*-(n + 2) ±K 1st Subr. Instr. 



(b) After Execution 



FIGURE 19 - PROGRAM FLOW FOR JSR (EXTENDED) 







m-a 




m - 1 




SP s»m 




m. ♦ 1 


7E 


m + 2 


7A 




TO M 






PC *- n 


JSR ' BO 


n + 1 


S H - Subr. Addr. 


n + 2 


S|_ « Subr. Addr. 


n + 3 


Next Main Instr. 








(a) Before Execution 



S H «: Subr. Addr. 



Sl " Subr. Addr. 



Next Main Inttr. 



(S formed from 
S H and S L ) 



1st Subr. tn$t 



Figure 20 - program flow for jsr (indexed) 



Next Main Instr. 



* K - 8-Bit Unsigned Valu 



(a) Before Execution 



Next Main Instr. 



PC — »-X - + K 1st Subr. I 



'Contents of Index Register 
(b) After Execution 



(b) After Execution 



MOTOROLA MICROPROCESSOR DATA 
3-78 



MC6800 



3 



FIGURE 21 - PROGRAM FLOW FOR RTS 



SP— >-m - 2 

m - 1 



n + 1 
n + 2 
n + 3 



(n + 3)H 



(n + 3)L 



»H 



Sl " Subr. Addr. 



Next Main Instr. 



Last Subr. Instr. 



(a) Before Execution 



m - 2 
m - 1 

SP m 

m + 1 



n + 1 
n + 2 
- n + 3 



S H - Subr. Addr. 



S L = Subr. Addr. 



Next Main Instr. 



Last Subr. Instr. 



(b) After Execution 



m — 5 
m — 4 
m - 3 
m - 2 
m - 1 



FIGURE 22 - PROGRAM FLOW FOR RTI 



X H (Index Reg) 



X L (Index Reg) 



PC(n+1)H 



PC(n+1)L 



Next Main Instr. 



Last Inter. Instr. 



m - 7 
m — 6 
m — 5 
m — 4 
m — 3 
m - 2 



*L 




(a) Before Execution 



(b) After Execution 



MOTOROLA MICROPROCESSOR DATA 
3-79 



MC6800 



FIGURE 23 - PROGRAM FLOW FOR INTERRUPTS 



Software Interrupt 
Main Program 



Wait For 
Interrupt 
Main Program 



Hardware Interrupt or 
Non-Maskable Interrupt (NMD 
Main Program 




Stack MPU 
Register Contents 



SP -» 


m 


- 7 




:> 


m 


- 6 


Condition Code 


m 


- 5 


Acmltr. B 




m 


- 4 


Acmltr. A 




m 


- 3 


Index Register (X^) 




m 


- 2 


Index Register (X|J 




m 


- 1 


PC(n + 1)H 








PC(n + 1)L 



SWI 



FFFA 
FFFB 



HOWR 
INT 




< 



Wait Loop 



> 



FFF8 
' f FFF9 



Interrupt Memory Assignment^ 


FFF8 


IRQ 


MS 


FFF9 


IRQ 


LS 


FFFA 


SWI 


MS 


FFFB 


SWI 


LS 


FFFC 


NMI 


MS 


FFFD 


NMI 


LS 


FFFE 


Reset 


MS 


FFFF 


Reset 


LS 



I 



Q Restart ^ 



FFFC FFFE 
FFFD FFFF 



Set Interrupt 
Mask(CCR4l 



First Instr. 
Addr. Formed 
By Fetching 
2-Bytes From 
Per. Mem. 
Assign. 



Load Interrupt 

Vector Into 
Program Counter 



J. 



Interrupt Program 



NOTE: MS » Most Significant Address Byte; 
LS = Least Significant Address Byte; 



1st Interrupt Instr. 



MOTOROLA MICROPROCESSOR DATA 
3-80 



MC6800 



FIGURE 24 - CONDITIONAL BRANCH INSTRUCTIONS 







BEQ : 


2 at 1 • 


BPL : 


N=« ; 


BNE : 


Z = « ; 


BVC : 


V = 0 ; 


BCC : 


C = 0 ; 


BVS : 


V - 1 ; 


BCS : 


C = 1 ; 


BHI : 


C+Z=« ; 


BLT : 


N®V = 1 


BLS : 


C+Z=1 ; 


BGE : 






BLE : 


Z + (N®V) = 1 






BGT : 


Z+(N«V) = 0 





The conditional branch instructions, Figure 24, consists of 
seven pairs of complementary instructions. They are used to 
test the results of the preceding operation and either con- 
tinue with the next instruction in sequence (test fails) or 
cause a branch to another point in the program (test suc- 
ceeds) . 

Four of the pairs are used for simple tests of status bits N, 
Z, V, and C: 

1. Branch on Minus (BMI) and Branch On Plus (BPL) tests 
the sign bit, N, to determine if the previous result was 
negative or positive, respectively. 

2. Branch On Equal (BEQ) and Branch On Not Equal 
(BNE) are used to test the zero status bit, Z, to determine 
whether or not the result of the previous operation was equal 
to zero. These two instructions are useful following a Com- 
pare (CMP) instruction to test for equality between an ac- 
cumulator and the operand. They are also used following the 
Bit Test (BIT) to determine whether or not the same bit posi- 
tions are set in an accumulator and the operand. 

3. Branch On Overflow Clear (BVC) and Branch On 
Overflow Set (BVS) tests the state of the V bit to determine 
if the previous operation caused an arithmetic overflow. 

4. Branch On Carry Clear (BCC) and Branch On Carry Set 
(BCS) tests the state of the C bit to determine if the previous 
operation caused a carry to occur. BCC and BCS are useful 



for testing relative magnitude when the values being tested 
are regarded as unsigned binary numbers, that is, the values 
are in the range 00 (lowest) to FF (highest). BCC following a 
comparison (CMP) will cause a branch if the (unsigned) 
value in the accumulator is higher than or the same as the 
value of the operand. Conversely, BCS will cause a branch if 
the accumulator value is lower than the operand. 

The fifth complementary pair, Branch On Higher (BHI) and 
Branch On Lower or Same (BLS) are, in a sense, com- 
plements to BCC and BCS. BHI tests for both CandZ = 0; if 
used following a CMP, it will cause a branch if the value in 
the accumulator is higher than the operand. Conversely, 
BLS will cause a branch if the unsigned binary value in the 
accumulator is lower than or the same as the operand. 

The remaining two pairs are useful in testing results of 
operations in which the values are regarded as signed two's 
complement numbers. This differs from the unsigned binary 
case in the following sense: in unsigned, the orientation is 
higher or lower; in signed two's complement, the com- 
parison is between larger or smaller where the range of 
values is between - 128 and + 127. 

Branch On Less Than Zero (BLT) and Branch On Greater 
Than Or Equal Zero (BGE) test the status bits for N e V = 1 
and Ne V = 0, respectively. BLT will always cause a branch 
following an operation in which two negative numbers were 
added. In addition, it will cause a branch following a CMP in 
which the value in the accumulator was negative and the 
operand was positive. BLT will never cause a branch follow- 
ing a CMP in which the accumulator value was positive and 
the operand negative. BGE, the complement to BLT, will 
cause a branch following operations in which two positive 
values were added or in which the result was zero. 

The last pair, Branch On Less Than Or Equal Zero (BLE) 
and Branch On Greater Than Zero (BGT) test the status bits 
forZ*(N + V) = 1 and Z»(N + V)=0, respectively. The ac- 
tion of BLE is identical to that for BLT except that a branch 
will also occur if the result of the previous result was zero. 
Conversely, BGT is similar to BGE except that no branch will 
occur following a zero result. 




CONDITION CODE REGISTER 
OPERATIONS 



The Condition Code Register (CCR) is a 6-bit register 
within the MPU that is useful in controlling program flow 
during system operation. The bits are defined in Figure 25. 

The instructions shown in Table 5 are available to the user 
for direct manipulation of the CCR. 

A CLI-WAI instruction sequence operated properly, with 
early MC6800 processors, only if the preceding instruction 
was odd (Least Significant Bit = 1 ) . Similarly it was advisable 



to precede eny SEI instruction with an odd opcode — such 
as NOP. These precautions are not necessary for MC6800 
processors indicating manufacture in November 1977 or 
later. 

Systems which require an interrupt window to be opened 
under program control should use a CLI-NOP-SEI sequence 
rather than CLI-SEI. 



MOTOROLA MICROPROCESSOR DATA 
3-81 



MC6800 



FIGURE 25 - CONDITION CODE REGISTER BIT DEFINITION 



b 5 


b 4 


b3 


b 2 


bl 


b0 


H 


1 


N 


Z 


V 


C 



H = Half-carry; set whenever a carry from 63 to D4 of the result is generated 
by ADD, ABA, ADC; cleared if no b3 to D4 carry; not affected by other 
instructions. 

I m Interrupt Mask; set by hardware or software interrupt or SEI instruction; 
cleared by CLI instruction. (Normally not used in arithmetic operations.) 
Restored to a zero as a result of an RT1 instruction if l m stored on the 
stacked is low. 




N = Negative; set if high order bit {by) of result is set; cleared otherwise. 
Z = Zero; set if result = 0; cleared otherwise. 

V = Overlow;set if there was arithmetic overflow as a result of the operation; 
cleared otherwise. 

C = Carry; set if there was a carry from the most significant bit (by) of the 
result; cleared otherwise. 



TABLE 5 - CONDITION CODE REGISTER INSTRUCTIONS 



CONO. CODE REG. 



OPERATIONS 



BOOLEAN OPERATION 



5 4 3 2 1 



Clear Carry 
Clear Interrupt Mask 
Clear Overflow 
Set Carry 
Set Interrupt Mask 
Set Overflow 
Acmltr A-CCR 
CCR -> Acmltr A 



CLV 
SEC 
SEI 
SEV 
TAP 
TPA 



0-C 

0- 1 
Q-V 

1- C 

1-1 

I'-V 
A-CCR 
CCR-A 



-©- 
» I » 



R = Reset 
S = Set 

• = Not affected 

© (ALL) Set according to the contents of Accumulator A. 

ADDRESSING MODES 



The MPU operates on 8-bit binary numbers presented 
to it via the data bus. A given number (byte) may rep- 
resent either data or an instruction to be executed, de- 
pending on where it is encountered in the control program. 
The M6800 has 72 unique instructions; however, it rec- 
ognizes and takes action on 197 of the 256 possibilities 
that can occur using an 8-bit word length. This larger 
number of instructions results from the fact that many of 
the executive instructions have more than one address- 
ing mode. 

These addressing modes refer to the manner in which 
the program causes the MPU to obtain its instructions 
and data. The programmer must have a method for ad- 
dressing the MPU's internal registers and all of the ex- 
ternal memory locations. 

Selection of the desired addressing mode is made by 
the user as the source statements are written. Translation 



into appropriate opcode then depends on the method 
used. If manual translation is used, the addressing mode 
is inherent in the opcode. For example, the immediate, 
direct, indexed, and extended modes may all be used 
with the ADD instruction. The proper mode is determined 
by selecting (hexadecimal notation) 8B, 9B, AB, or BB, 
respectively. 

The source statement format includes adequate infor- 
mation for the selection if an assembler program is used 
to generate the opcode. For instance, the immediate mode 
is selected by the assembler whenever it encounters the 
"#" symbol in the operand field. Similarly, an "X" in the 
operand field causes the indexed mode to be selected. 
Only the relative mode applies to the branch instructions; 
therefore, the mnemonic instruction itself is enough for 
the assemble to determine addressing mode. 



MOTOROLA MICROPROCESSOR DATA 

3-82 



MC6800 



For the instructions that use both Direct and Extended 
modes, the Assembler selects the Direct mode if the operand 
value is in the range 0-255 and Extended otherwise. There 
are a number of instructions for which the Extended mode is 
valid but the Direct is not. For these instructions, the 
Assembler automatically selects the Extended mode even if 
the operand is in the 0-255 range. The addressing modes are 
summarized in Figure 26. 

Inherent (Includes "Accumulator Addressing" Mode) 

The successive fields in a statement are normally 
separated by one or more spaces. An exception to this rule 
occurs* for instructions that use dual addressing in the 
operand field and for instructions that must distinguish be- 
tween the two accumulators. In these cases, A and B are 



"operands" but the space between them and the operator 
may be omitted. This is commonly done, resulting in ap- 
parent four character mnemonics for those instructions. 

The addition instruction, ADD, provides an example of 
dual addressing in the operand field: 

Operator Operand Comment 

ADDA MEM12 ADD CONTENTS OF MEM12 TO ACCA 

or 

ADDB MEM12 ADD CONTENTS OF MEM12 TO ACCB 

The example used earlier for the test instruction, TST, also 
applies to the accumulators and uses the "accumulator ad- 
dressing mode" to designate which of the two accumulators 
is being tested: 



FIGURE 26 - ADDRESSING MODE SUMMARY 



Direct: n 


DQ Instruction 


Immediate: 


n 


Instruction 


Example: SUBB Z 

Addr. Range = 0-255 n + 1 

n + 2 


Z = Oprnd Address 


Example: LDAA #K 
(K = One-Byte Oprnd) 


n+1 


K = Operand 


Next Instr. 




n + 2 


Next Inst. 




• 






OR 




• 


(K = Two-Byte Oprnd) 
(CPX, LDX, and LDS) 


n 


Instruction 




• 




n + 1 


K H = Operand 


(K = One-Bvte Oprnd) Z 


K - Operand 




n + 2 


K |_ ■ Operand 




OR 




n + 3 


Next Instr. 


(K = Two-Byte Oprnd) Z 


K|_| = Operand 








Z + 1 


K|_ = Operand 






















Relative: 


n 


Instruction 


/j\ If Z ^255, Assembler Select Direct Mode 


Example: BNE K 


n + 1 


+ K = Brnch Offset 






(K = Signed 7-Bit Value) n + 2 


Next Instr. 






Addr. Range: 
-125 to +129 
Relative to n. 




• 
• 










• 


Extended: n 


FO Instruction 








(n + 2) ±K 


Next Instr. /K 


Example: CMPA Z n+1 


Zh = Oprnd Address 


Addr. Range: n + 2 
f^S 256-65535 


Z L = Oprnd Address 


ft\ If Brnch Tst False, 


/3\ If Brnch Tst True. 


n + 3 


Next Instr. 










• 


Indexed: 


n 


Instruction 




• 


Example: ADDA Z, X 


n + 1 


Z = Offtet 




• 


Addr. Range: 
0—255 Relative to 
index Register, X 


n + 2 


Next Instr. 


(K = One-Byte Oprnd) Z 


K = Operand 




• 




(K = Two-Byte Oprnd) 



K H = Operand 



<L = Operand 



(Z = 8-Bit Unsigned X + Z 

Value) 



MOTOROLA MICROPROCESSOR DATA 

3-83 



MC6800 



Operator Comment 

TSTB TEST CONTENTS OF ACCB 

or 

TSTA TEST CONTENTS OF ACCA 

A number of the instructions either alone or together with 
an accumulator operand contain all of the address informa- 
tion that is required, that is, "inherent" in the instruction 
itself. For instance, the instruction ABA causes the MPU to 
add the contents of accmulators A and B together and place 
the result in accumulator A. The instruction INCB, another 
example of "accumulator addressing," causes the contents 
of accumulator B to be increased by one. Similarly, INX, in- 
crement the Index Register, causes the contents of the Index 
Register to be increased by one. 

Program flow for instructions of this type is illustrated in 
Figures 27 and 28. In these figures, the general case is shown 
on the left and a specific example is shown on the right. 
Numerical examples are in decimal notation. Instructions of 
this type require only one byte of opcode. Cycle-by-cycle 
operation of the inherent mode is shown in Table 6. 

Immediate Addressing Mode — In the Immediate address- 
ing mode, the operand is the value that is to be operated on . 
For instance, the instruction 

Operator Operand Comment 

LDAA #25 LOAD 25 INTO ACCA 

causes the MPU to "immediately load accumulator A with 
the value 25"; no further address reference is required. The 
Immediate mode is selected by preceding the operand value 
with the "$" symbol. Program flow for this addressing mode 
is illustrated in Figure 29. 

The operand format allows either properly defined sym- 
bols or numerical values. Except for the instructions CPX, 
LDX, and LDS, the operand may be any value in the range 0 
to 255. Since Compare Index Register (CPX), Load Index 
Register (LDX), and Load Stack Pointer (LDS), require 16-bit 
values, the immediate mode for these three instructions re- 
quire two-byte operands. In the Immediate addressing 



mode, the "address" of the operand is effectively the 
memory location immediately following the instruction itself. 
Table 7 shows the cycle-by-cycle operation for the im- 
mediate addressing mode. 

Direct and Extended Addressing Modes - In the Direct 
and Extended modes of addressing, the operand field of the 
source statement is the address of the value that is to be 
operated on. The Direct and Extended modes differ only in 
the range of memory locations to which they can direct the 
MPU. Direct addressing generates a single 8-bit operand 
and, hence, can address only memory locations 0 through 
255; a two byte operand is generated for Extended address- 
ing, enabling the MPU to reach the remaining memory loca- 
tions, 256 through 65535. An example of Direct addressing 
and its effect on program flow is illustrated in Figure 30. 

The MPU, after encountering the opcode for the instruc- 
tion LDAA (Direct) at memory location 5004 (Program 
Counter = 5004), looks in the next location, 5005, for the ad- 
dress of the operand. It then sets the program counter equal 
to the value found there (100 in the example) and fetches the 
operand, in this case a value to be loaded into accumulator 
A, from that location. For instructions requiring a two-byte 
operand such as LDX (Load the Index Register), the operand 
bytes would be retrieved from locations 100 and 101 . Table 8 
shows the cycle-by-cycle operation for the direct mode of 
addressing. 

Extended addressing, Figure 31, is similar except that a 
two-byte address is obtained from locations 5007 and 5008 
after the LDAB (Extended) opcode shows up in location 
5006. Extended addressing can be thought of as the "stan- 
dard" addressing mode, that is, it is a method of reaching 
any place in memory. Direct addressing, since only one ad- 
dress byte is required, provides a faster method of process- 
ing data and generates fewer bytes of control code. In most 
applications, the direct addressing range, memory locations 
0-255, are reserved for RAM. They are used for data buffer- 
ing and temporary storage of system variables, the area in 
which faster addressing is of most value. Cycle-by-cycle 
operation is shown in Table 9 for Extended Addressing. 



FIGURE 27 - INHERENT ADDRESSING FIGURE 28 - ACCUMULATOR ADDRESSING 



MPU MPU MPU MPU 



PC 




GENERAL FLOW EXAMPLE 



MOTOROLA MICROPROCESSOR DATA 
3-84 



MC6800 



Relative Address Mode - In both the Direct and Extended 
modes, the address obtained by the MPU is an absolute 
numerical address. The Relative addressing mode, im- 
plemented for the MPU's branch instructions, specifies a 
memory location relative to the Program Counter's current 
location. Branch instructions generate two bytes of machine 
code, one for the instruction opcode and one for the 
"relative" address (see Figure 32). Since it is desirable to be 
able to branch in either direction, the 8-bit address byte is in- 
terpreted as a signed 7-bit Value; the 8th bit of the operand is 
treated as a sign bit, "0" = plus and "1" = minus. The re- 
maining seven bits represent the numerical value. This 
results in a relative addressing range of ± 127 with respect to 
the location of the branch instruction itself. However, the 
branch range is computed with respect to the next instruc- 
tion that would be executed if the branch conditions are not 
satisfied. Since two bytes are generated, the next instruction 
is located at PC + 2. If D is defined as the address of the 
branch destination, the range is then: 

(PC + 2)-127<sD<(PC + 2) + 127 

or 

PC-125sSD:£PC+129 
that is, the destination of the branch instruction must be 
within - 125 to + 129 memory locations of the branch in- 
struction itself. For transferring control beyond this range, 



the unconditional jump (JMP), jump to subroutine (JSR), 
and return from subroutine (RTS) are used. 

In Figure 32, when the MPU encounters the opcode for 
BEQ (Branch if result of last instruction was zero), it tests the 
Zero bit in the Condition Code Register. If that bit is "0," in- 
dicating a non-zero result, the MPU continues execution 
with the next instruction (in location 5010 in Figure 32). If the 
previous result was zero, the branch condition is satisfied 
and the MPU adds the offset, 15 in this case, to PC + 2 and 
branches to location 5025 for the next instruction. 

The branch instructions allow the programmer to efficient- 
ly direct the MPU to one point or another in the control pro- 
gram depending on the outcome of test results. Since the 
control program is normally in read-only memory and cannot 
be changed, the relative address used in execution of branch 
instructions is a constant numerical value. Cycle-by-cycle 
operation is shown in Table 10 for relative addressing. 

Indexed Addressing Mode - With Indexed addressing, 
the numerical address is variable and depends on the current 
contents of the Index Register. A source statement such as 



Operator Operand 

STAA X 



Comment 

PUT A IN INDEXED LOCATION 



causes the MPU to store the contents of accumulator A in 
TABLE 6 - INHERENT MODE CYCLE-BY-CYCLE OPERATION 



Address Mode 




Cycle 


VMA 




R/W 




and Instructions 


Cycles 


# ■ 


Line 


Address Bus 


Line 


Data Bus 




ABA 


DAA 


SEC 


ASL 


DEC 


SEI 


ASR 


INC 


SEV 


CBA 


LSR 


TAB 


CLC 


NEG 


TAP 


CLI 


NOP 


TBA 


CLR 


ROL 


TPA 


CLV 


ROR 


TST 


COM 


SBA 




DES 






DEX 






INS 






INX 







TSX 



Op Code Address 
Op Code Address + 1 



Op Code Address 
Op Code Address + 1\ 
Previous Register Contents 
New Register Contents 



Op Code Address 
Op Code Address + 1 
Stack Pointer 
Stack Pointer - 1 



Op Code Address 
Op Code Address + 1 
Stack Pointer 
Stack Pointer + 1 



Op Code Address 
Op Code Address + 1 
Stack Pointer 
New Index Register 



Op Code Address 
Op Code Address + 1 
Index Register 
New Stack Pointer 



Op Code Address 
Op Code Address + 1 
Stack Pointer 
Stack Pointer + 1 

Stack Pointer + 2 



Op Code 

Op Code of Next Instruction 



Op Code 

Op Code of Next Instruction 
Irrelevant Data (Note 1 ) 
Irrelevant Data (Note 1) 



Op Code 

Op Code of Next Instruction 
Accumulator Data 
Accumulator Data 



Op Code 

Op Code of Next Instruction 
Irrelevant Data (Note 1 ) 
Operand Data from Stack 



Op Code 

Op Code of Next Instruction 
Irrelevant Data (Note 1) 
Irrelevant Data (Note 1 ) 



Op Code 

Op Code of Next Instruction 
Irrelevant Data 
Irrelevant Data 



Op Code 

Irrelevant Data (Note 2) 

Irrelevant Data (Note 1) 

Address of Next Instruction (High 
Order Byte) 

Address of Next Instruction (Low 
Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-85 



MC6800 



TABLE 6 — INHERENT MODE CYCLE-BY-CYCLE OPERATION (CONTINUED) 



Address Mode 
and Instructions 


Cycles 


Cycle 

# 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 




WAI 




1 

2 


1 
1 


Op Code Address 
Op Code Address +1 


1 
1 


Op Code 

Op Code of Next Instruction 






3 


1 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


1 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 




9 


5 


1 


Stack. Pointer - 2 


0 


Index Register (Low Order Byte) 






6 


1 . 


Stack Pointer — 3 


o 


Index Register (High Order Byte) 






. 7 


1 


Stack Pointer - 4 


0 


Contents of Accumulator A 






8 


1 


Stack Pointer — 5 


0 


Contents of Accumulator B 






9 


1 


Stack Pointer - 6 (Note 3) 


1 1 


Contents of Cond. Code Register 


RTI 




1 
2 


1 

1 


Op Code Address 
Op Code Address + 1 


1 
1 


Op Code 

Irrelevant Data (Note 2) 






3 


0 


Stack Pointer 


1 


Irrelevant Data (Note 1) 






4 


1 


Stack Pointer + 1 


1 


Contents of Cond. Code Register from 
Stack 




10 


5 
6 
7 

8 

9 

10 


1 
1 

1 

1 
1 
1 


Stack Pointer + 2 
Stack Pointer + 3 
Stack Pointer + 4 

Stack Pointer + 5 

Stack Pointer + 6 

Stack Pointer + 7 


1 
1 
1 

1 

1 

1 


Contents of Accumulator B from Stack 

Contents of Accumulator A from Stack 

Index Register from Stack (High Order 
Byte) 

Index Register from Stack (Low Order 
Byte) 

Next Instruction Address from Stack 
(High Order Byte) 

Next Instruction Address from Stack 
(Low Order Byte) 


SWI 




1 

2 


1 

1 


Op Code Address 
Op Code Address + 1 


1 
1 


.Op Code 

Irrelevant Data (Note 1 ) 






3 


1 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


1 


Stack Pointer — 1 


0 


Return Address (High Order Byte) 






5 


1 


Stack Pointer - 2 


0 


Index Register (Low Order Byte) 




12 


g 




Stack Pointer 3 


o 


Index Register (High Order Byte) 




7 


1 


Stack Pointer - 4 


0 


Contents of Accumulator A 






8 


1 


Stack Pointer - 5 


0 


Contents of Accumulator B 






9 


1 


Stack Pointer - 6 


0 


Contents of Cond. Code Register 






10 


0 


Stack Pointer - 7 


1 


Irrelevant Data (Note 1) 






11 


1 


Vector Address FFFA (Hex) 


1 


Address of Subroutine (High Order 
Byte) 






12 


1 


Vector Address FFFB (Hex) 


1 


Address of Subroutine (Low Order 
Byte) 



Note 1. If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition. 

Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. 
Note 2. Data is ignored by the MPU. 

Note 3. While the MPU is waiting for the interrupt. Bus Available will go high indicating the following states of the control lines: VMA is 
low; Address Bus, R/w", and Data Bus are all in the high impedance state. 



the memory location specified by the contents of the Index 
Register (recall that the label "X" is reserved to designate the 
Index Register). Since there are instructions for manipulating 
X during program execution (LDX, INX, DEC, etc.), the In- 
dexed addressing mode provides a dynamic "on the fly" way 
to modify program activity. 

The operand field can also contain a numerical value that 
will be automatically added to X during execution. This for- 
mat is illustrated in Figure 33. 

When the MPU encounters the LDAB (Indexed) opcode in 



location 5006, it looks in the next memory location for the 
value to be added to X (5 in the example) and calculates the 
required address by adding 5 to the present Index Register 
value of 400. In the operand format, the offset may be 
represented by a label or a numerical value in the range 0-255 
as in the. example. In the earlier example, STAA X, the 
operand is equivalent to 0, X, that is, the 0 may be omitted 
when the desired address is equal to X. Table 11 shows the 
cycle-by-cycle operation for the Indexed Mode of Address- 
ing. 



MOTOROLA MICROPROCESSOR DATA 
3-86 



MC6800 



FIGURE 29 - IMMEDIATE ADDRESSING MODE 

MPU MPU 



FIGURE 30 - DIRECT ADDRESSING MODE 

MPU MPU 




GENERAL FLOW 



EXAMPLE 




1<X1 



PC = 5004 
5005 



TABLE 7 - IMMEDIATE MODE CYCLE-BY-CYCLE OPERATION 



Address Mode 




Cycle 


VMA 




R/W 




and Instructions 


Cycles 


# 


Line 


Address Bus 


Line 


Data Bus 



ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


2 


1 
2 


1 
1 


Op Code Address 
Op Code Address + 1 


1 
1 


Op Code 
Operand Data 


CPX 
LDS 
LDX 


3 


1 
2 
3 


1 
1 
1 


Op Code Address 
Op Code Address + 1 
Op Code Address + 2 


1 
1 
1 


Op Code 

Operand Data (High Order Byte) 
Operand Data ( Low Order Byte) 


TABLE 8 - DIRECT MODE CYCLE-BY-CYCLE OPERATION 


Address Mode 
and Instructions 


Cycles 


Cycle 

# 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 



ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


3 


1 

2 
3 




Op Code Address 
Op Code Address +1 
Address of Operand 




Op Code 

Address of Operand 
Operand Data 


CPX 
LDS 
LDX 


4 


1 
2 
3 
4 




Op Code Address 
Op Code Address + 1 
Address of Operand 
Operand Address + 1 




Op Code 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 


STA 


4 


1 
2 
3 
4 




Op Code Address 
Op Code Address + 1 
Destination Address 
Destination Address 




Op Code 

Destination Address 
Irrelevant Data (Note 1) 
Data from Accumulator 


STS 
STX 


5 


1 
2 
3 
4 
5 




Op Code Address 
Op Code Address + 1 
Address of Operand 
Address of Operand 
Address of Operand + 1 


0 
0 


Op Code 

Address of Operand 
Irrelevant Data (Note 1) 
Register Data (High Order Byte) 
Register Data (Low Order Byte) 



Note 1. If device which is address during this cycle uses VMA, then the Data Bus will 
Depending on bus capacitance, data from the previous cycle may be retained 



go to the high impedance three-state condition, 
on the Data Bus. 



MOTOROLA MICROPROCESSOR DATA 
3-87 



MC6800 



FIGURE 31 - EXTENDED ADDRESSING MODE 

MPU MPU 




ADDR S 256 

GENERAL FLOW EXAMPLE 

TABLE 9 - EXTENDED MODE CYCLE-BY-CYCLE 



Address Mode 
and Instructions 


Cycles 


Cycle 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 


STS 
STX 


6 


1 

2 
3 
4 
5 
6 


• 


Op Code Address 
Op Code Address + 1 
Op Code Address +. 2 
Address of Operand 
Address of Operand 
Address of Operand + 1 


; 


Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Bytel 
Irrelevant Data (Note 1) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


JSR 


9 


1 

2 
3 
4 
5 
6 
7 
8 
9 


1 ' 


Op Code Address 
Op Code Address + 1 
Op Code Address + 2 • 
Subroutine Starting Address 
Stack Pointer 
Stack Pointer - 1 
Stack Pointer - 2 
Op Code Address + 2 
Op Code Address + 2 


; 


Op Code 

Address of Subroutine (High Order Byte) 
Address of Subroutine (Low Order Byte) 
Op Code of Next Instruction 
Return Address (Low Order Byte) 
Return Address (High Order Byte) 
Irrelevant Data (Note 1 ) 
Irrelevant Data (Note 1) 
Address of Subroutine (Low Order Byte) 


JMP 


3 


1 

2 
3 




Op Code Address 
Op Code Address + 1 
Op Code Address + 2 




Op Code 

Jump Address (High Order Byte) 
Jump Address (Low Order Byte) 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


4 


1 

2 
3 
4 




Op Code Address 
Op Code Address +1 
Op Code Address + 2 
Address of Operand 




Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Operand Data 


CPX 
LDS 
LDX 


5 


1 

2 
3 
4 
5 




Op Code Address 
Op Code Address + 1 
Op Code Address + 2 
Address of Operand 
Address of Operand + 1 




Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


STA A 
STA B 


5 


1 

2 
3 
4 
5 




Op Code Address 
Op Code Address + 1 
Op Code Address + 2 
Operand Destination Address 
Operand Destination Address 




Op Code 

Destination Address (High Order Byte) 
Destination Address (Low Order Byte) 
Irrelevant Data (Note 1 ) 
Data from Accumulator 


ASL LSR 
ASR NEG 
CLR ROL 
COM ROR 
DEC TST 
INC 


6 


1 
2 
3 
4 
5 
6 


0 

1/0 
(Note 
2) 


Op Code Address 
Op Code Address + 1 
Op Code Address + 2 
Address of Operand 
Address of Operand 
Address of Operand 


0 


Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Current Operand Data 
Irrelevant Data (Note 1 ) 
New Operand Data (Note 2) 



Note 1 . If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition. 

Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. 
Note 2. For TST, VMA = 0 and Operand data does not change. 



MOTOROLA MICROPROCESSOR DATA 
3-88 



3 



MC6800 



FIGURE 32 - RELATIVE ADDRESSING MODE 

MPU MPU 



SAM 



1C=; 



Program 
Memory 



Next Instr. 



(PC + 2) + (Offset) 



PC 5025 



FIGURE 33 - INDEXED ADDRESSING MODE 

MPU MP U 



ADOR = INDX 
+ OFFSET 





TABLE 10 - RELATIVE MODE CYCLE-BY-CYCLE OPERATION 



Address Mode 
and Instructions 


Cycles 


Cycle 

# 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 




BCC BHI BNE 
BCS BLE BPL . 
BEQ BLS BRA 
BGE BLT BVC 


4 


1 

2 
3 


1 
1 
0 


Op Code Address 
Op Code Address + 1 
Op Code Address + 2 


1 
1 

1 


Op Code 
Branch Offset 
Irrelevant Data (Note 1 ) 


BGT BMI BVS 




4 


0 


Branch Address 


1 


Irrelevant Data (Note 1) 


BSR 




1 

2 


1 
1 


Op Code Address 
Op Code Address + 1 


1 
1 


Op Code 
Branch Offset 






3 


0 


Return Address of Main Program 


1 


Irrelevant Data (Note 1) 




8 


4 


1 


Stack Pointer 


0 


Return Address (Low Order Byte) 






5 


1 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






6 


0 


Stack Pointer - 2 


1 


Irrelevant Data (Note 1 ) 






7 


0 


Return Address of Main Program 


1 


Irrelevant Data (Note 1) 






8 


0 


Subroutine Address 


1 


Irrelevant Data (Note 1) 



If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition. 
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. 



MOTOROLA MICROPROCESSOR DATA 
3-89 



MC6800 



TABLE 11 - INDEXED MODE CYCLE-BY-CYCLE 



Address Mode 
and Instructions 


Cycles 


Cycle 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 


INDEXED 


JMP 






1 


Op Code Address 




Op Code 




4 


2 


1 


Op Code Address + 1 


■■ 


Offset 






3 


0 


Index Register 


1 


Irrelevant Data (Note 1 ) 






4 


0 


Index Register Plus Offset (w/o Carry) 




(rrelevant Data (Note 1 ) 


ADC EOR 
ADD LDA 

Afciri ADA 

BIT SBC 


5 


1 
2 
3 


1 

1 
0 


Op Code Address 
Op Code Address + 1 
Index Register 


'; 

) 


Op Code 
Offset 

Irrelevant Data (Note 1 ) 


CMP SUB 




4 

5 


0 

1 


Index Register Plus Offset (w/o Carry) 
Index Register Plus Offset 


1 


Irrelevant Data (Note 1) 
Operand Data 


CPX 




1 


1 


Op Code Address 


i 


Op Code 


LDS 
LDX 




2 


1 


Op Code Address + 1 


1 


Offset 


6 


3 


0 


Index Register 


! 


Irrelevant Data (Note 1 ) 




4 

5 
6 


0 

1 
1 


Index Register Plus Offset (w/o Carry) 
Index Register Plus Offset 
Index Register Plus Offset + 1 


! 
1 


Irrelevant Data (Note 1) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


STA 




1 

2 


1 
1 


Op Code Address 
Op Codo Address + 1 


— 

1 


Op Code 
Offset 




6 


3 


o 


Index Register 


1 


Irrelevant Data (Note 1) 




4 


0 


Index Register Plus Offset (w/o Carry) 


; 


Irrelevant Data (Note 1) 






5 


0 


Index Register Plus Offset 




Irrelevant Data (Note 1) 






6 


1 


Index Register Plus Offset 




Operand Data 


ASL LSR 




1 


1 


Op Code Address 


i 


Op Code 


ASR NEG 
n o o r\ i 
ILn MUL 

COM ROR 


7 


2 
3 


1 

0 


Op Code Address + 1 
Index Register 


1 


Offset 

Irrelevant Data (Note 1) 


DEC TST 
INC 




4 


0 


Index Register Plus Offset (w/o Carry) 




Irrelevant Data (Note 1 ) 




: 5 


1 


Index Register Plus Offset 




Current Operand Data 






6 


0 


Index Register Plus Offset 


1 


Irrelevant Data (Note 1) 






7 


1/0 
(Note 
2) 


Index Register Plus Offset 


0 


New Operand Data (Note 2) 


STS 






1 


Op Code Address 


1 


Op Code 


STX 




2 


1 


Op Code Address + 1 


1 


Offset 




7 




0 


Index Register 


1 


Irrelevant Data (Note 1 ) 






4 


o 


Index Register Plus Offset (w/o Carry) 


1 


Irrelevant Data (Note 1) 






5 


o 


Index Register Plus Offset 


1 


Irrelevant Data (Note 1) 






6 


1 


Index Register Plus Offset 


0 


Operand Data (High Order Byte) 






7 


1 


Index Register Plus Offset + 1 


0 


Operand Data (Low Order Byte) 


JSR 




1 

2 


1 
1 


Op Code Address 
Op Code Address + 1 


1 
1 


Op Code 
Offset 






3 


0 


Index Register 


1 


Irrelevant Data (Note 1 ) 




8 


4 


1 


Stack Pointer 


0 


Return Address (Low Order Byte) 




5 


1 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






6 


0 


Stack Pointer - 2 


1 


Irrelevant Data (Note 1) 






7 


0 


Index Register 


1 


Irrelevant Data (Note 1) 






8 


0 


Index Register Plus Offset (w/o Carry) 


1 


Irrelevant Data (Note 1) 



Note 1. If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition. 

Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. 
Note 2. For TST, VMA = 0 and Operand data does not change. 



MOTOROLA MICROPROCESSOR DATA 
3-90 



MC6800 



ORDERING INFORMATION 



Package Type 


Frequency (MHz) 


Temperature 


Order Number 


Cerdip 


1.0 


0°C to 70°C 


MC6800S 


S Suffix 


1.0 


-40°Cto 85°C 


MC6800CS 




1.5 


0°C to 70°C 


MC68A00S 




1.5 


-40°Cto85°C 


MC68AO0CS 




2.0 


0°C to 70°C 


MC68B00S 


Plastic 


1.0 


0°C to 70°C 


MC6800P 


P Suffix 


1.0 


-40°Cto85°C 


MC6800CP 




1.5 


0°C to 70°C 


MC68A00P 




1.5 


-40°Cto85°C 


MC68AO0CP 




2.0 


0°C to 70°C 


MC68B00P 



PIN ASSIGNMENT 





MOTOROLA MICROPROCESSOR DATA 
3-91 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 




Microcontroller/Microprocessor (MCU/MPU) 

The MC6801 is an 8-bit single-chip microcontroller unit (MCU) which significantly enhances the 
capabilities of the M6800 Family of parts. It includes an upgraded M6800 microprocessor unit 
(MPU) with upward-source and object-code compatibility. Execution times of key instructions have 
been improved and several new instructions have been added including an unsigned multiply. The 
MCU can function as a monolithic microcontroller or can be expanded to a 64K byte address space. 
It is TTL compatible and requires one +5-volt power supply. On-chip resources include 2048 bytes 
of ROM, 128 bytes of RAM, a serial communications interface (SCI), parallel I/O, and a three-func- 
tion programmable timer. The MC6803 can be considered as an MC6801 operating in modes 2 or 3. 
An EPROM version of the MC6801, the MC68701 microcontroller, is available for systems develop- 
ment. The MC68701 is pin and code compatible with the MC6801/MC6803 and can be used to emu- 
late the MC6801/MC6803. The MC68701 is described in a separate Advanced Information 
publication. 

• Enhanced MC6800 Instruction Set 

• 8x8 Multiply Instruction 

• Serial Communications Interface (SCI) 

• Upward Source and Object Code Compatibility with the M6800 

• 16-Bit Three-Function Programmable Timer 

• Single-Chip or Expanded Operation to 64K Byte Address Space 

• Bus Compatibility with the M6800 Family 

• 2048 Bytes of ROM (MC6801 Only) 

• 128 Bytes of RAM 

• 64 Bytes of RAM Retainable During Powerdown 

• 29 Parallel I/O and Two Handshake Control Lines 

• Internal Clock Generator with Divide-by-Four. Output 

• - 40 to 85°C Temperature Range 



MC6801 
MC6803 



This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-92 



MC680 1/6803 



FIGURE 1 - M6801 MICROCOMPUTER FAMILY BLOCK DIAGRAM 



r 



Expanded Multiplexed 
Expanded Non-Multiplexed 
Single Chip 



P37 


A7/D7 


D7 


I/O 




P36 


A6/D6 


D6 


I/O 




P35 


A5/D5 


D5 


I/O 




P34 


A4/D4 


D4 


I/O 




P33 


A3/D3 


D3 


I/O 




P32 


A2/D2 


D2 


I/O 




P31 


A1/D1 


D1 


I/O 




P30 


AO/ DO 


DO 


I/O 




SC2 


R/W 


R/W 


0"S3 




SC1 


AS 


IOS 


rs"3 





>- P24 



P47 


A15 


A7 


I/O 




P46 


A14 


A6 


I/O 




P45 


A13 


A5 


I/O 




P44 


A12 


A4 


I/O 




P43 


A11 


A3 


I/O 




P42 


A10 


A2 


I/O 




P41 


A9 


A1 


I/O 


-*> 


P40 


A8 


AO 


I/O 






Vqc Standby- 
NOTE.: No functioning ROM in MC6803. 











128 x 8 
RAM 




2048 x 8 
ROM 
(See Note) 






POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj=T A +(P D .e JA ) (i) 

where: 

T A = Ambient Temperature, °C 

6j A = Package Thermal Resistance, Junction-to-Ambient, °C/W 
P D =p INT +p PORT 

P INT = 'CC X V CC' Watts — Chip Internal Power 

PpORT = Port Power Dissipation, Watts — User Determined 

For most applications PpoRT <p INT anc ' can be neglected. PpORT ma Y become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpoRT is neglected) is: 

P D = K-(Tj I 273X) (2) 

Solving equations (1) and (2) for K gives: 

K = P D * < T A + 273 ° c ) + 0JA-PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pq (at 
equilibrium) for a known T A . Using this value of K, the values of Pp and Tj can be obtained by solving equations 
(1) and (2) iteratively for any value of T A 



MOTOROLA MICROPROCESSOR DATA 
3-93 



MC6801/6803 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


vcc 


-0.3 to +7.0 


V 


Input Voltage 


Yin 


-0.3 to +7.0 


V 


Operating Temperature Range 
MC6801, MC6803 
MC6801C, MC6803C 


T A 


T L to T H 
0to70 
-40 to +85 


°C 


Storage Temperature Range 


T stg 


-55 to +150 


°c 



This device contains circuitry to protect the 
inputs against damage due to high static volt- 
ages or electric fields; however, it is advised 
that normal precautions be taken to avoid 
application of any voltage higher than max- 
imum rated voltages to this high-impedance 
circuit. For proper operation it is recom- 
mended the Vj n and V 0U ( be constrained to 
the range Vgs =s (Vj n or V out ) s V cc . Input 
protection is enhanced by connecting un- 
used inputs to either Vrjrj or Vgs- 



THERMAL CHARACTERISTICS 



Characteristic 


Symbol 


Value 


Unit 


Thermal Resistance 






°c/w 


Plastic 




50 




Cerdip 




50 





CONTROL TIMING (V cc = 5.0 V ±5%, V S s = 0) 



Characteristic 


Symbol 


MC6801 


MC6801-1 


MC68B01 


Unit 


Min 


Max 


Min 


, Max 


Min 


Max 


Frequency of Operation 


fo 


0.5 


1.0 


0.5 


1.25 


0.5 


2.0 


MHz 


Crystal Frequency 


fXTAL 


2.0 


4.0 


2.0 


5.0 


2.0 


8.0 


MHz 


External Oscillator Frequency 


4f 0 


2.0 


4.0 


2.0 


5.0 


2.0 


8.0 


MHz 


Crystal Oscillator Start Up Time 


trc 




100 




100 




100 


ms 


Processor Control Setup Time 


tpcs 


200 




170 




110 




ns 



DC ELECTRICAL CHARACTERISTICS (Vcc = 5.0 Vdc ±5%, Vss = 0, Ta = T|_ to T H , unless otherwise noted) 



Characteristic 




Symbol 


MC6801 
MC6803 


MC6801C 
MC6803C 


Unit 








Min 


Max 


Min 


Max 




Input High Voltage 


RESET 
Other Inputs 


V|H 


Vss + 4.0 
VsS + 2.0 


vcc 
vcc 


VSS + 4.0 
Vss + 2.2 


vcc 
vcc 


V 


Input Low Voltage 


All Inputs 


V|L 


Vss-0.3 


Vss + 0.8 


Vss-0.3 


Vss + 0.8 


V 


Input Load Current 
(Vj n = 0 to 2.4 V) 


Port 4 
SC1 


■in 




0.5 
0.8 




0.8 
1.0 


mA 


Input Leakage Current 




■in 










(J.A 


(V in = 0 to 5.25 V) 


NMI, IRQ1, RESET 




2.5 




5.0 




Hi-Z (Off State) Input Current 
(V in = 0.5to2.4 V) 


Ports 1, 2, and 3 


'TSI 




10 




20 


(xA 


Output High Voltage 
dLoad= -65|xA, V C c = Min)* 
dLoad= -100 (xA, V C c = Min) 


Port 4, SC1, SC2 
Other Outputs 


VOH 


Vss + 2.4 
Vss + 2.4 




VSS + 2.4 
Vss + 2.4 




V 


Output Low Voltage 
(l Loa d = 2.0 mA, V C C = Min) 


All outputs 


vol 




Vss + 0.5 




Vss + 0.6 


V 


Darlington Drive Current (Vq = 1.5 V) 


Port 1 


'OH 


1.0 


4.0 


1.0 


5.0 


mA 


Internal Power Dissipation 
(Measured at T/\ = T|_ in Steady-State Operation) 


pint 




1200 




1500 


mW 


Input Capacitance 
< v in = 0, T A = 25°C, f 0 = 1 .0 MHz) 


Port 3, Port 4, SC1 
Other Inputs 






12.5 
10 




12.5 
10 


pF 


Vcc Standby 


Powerdown 
Powerup 


VSBB 
VSB 


4.0 
4.75 


5.25 
5.25 


4.0 
4.75 


5.25 
5.25 


V 


Standby Current 


Powerdown 


ISBB 




6.0 




8.0 


mA 



*Negotiable to - 100 ijlA (for further information contact the factory) 



MOTOROLA MICROPROCESSOR DATA 
3-94 



MC680 1/6803 



PERIPHERAL PORT TIMING (Refer to Figures 2-5) 



Characteristic 


Symbol 


MC6801 
MC6803 


MC6801-1 
MC6803-1 


MC68B01 
MC68B03 


Unit 


Min 


Max 


Min 


Max 


Min . 


Max 


Peripheral Data Setup Time 


tpDSU 


200 




200 




100 




ns 


Peripheral Data Hold Time 


tPDH 


200 





200 


, 


TOO 





ns 


Delay Time, Enable Positive Transition to OS3 Negative 
Transition 


tOSD1 





350 


_ 


350 


• _ 


250 


ns 


Delay Time, Enable Positive Transition to OS3 Positive 
Transition 


l OSD2 




350 




350 




250 


ns 


Delay Time, Enable Negative Transition to Peripheral Data Valid 


tpWD 




350 




350 




250 


ns 


Delay Time, Enable Negative Transition to Peripheral 
CMOS Data Valid 


tCMOS 




2.0 




2.0 




2.0 


|JLS 


Input Strobe Pulse Width 


tpwis 


200 




200 




100 




ns 


Input Data Hold Time 


t|H 


50 




50 




30 




ns 


Input Data Setup Time 


t|S 


20 




20 




20 




ns 



FIGURE 2 - DATA SETUP AND HOLD TIMES 
(MPU READ) 



FIGURE 3 - DATA SETUP AND HOLD TIMES 
(MPU WRITE) 



l PDSU 



P10-P17 . 
P20-P24 
P40-P47 
Inputs 

P30-P37 
Inputs* 



MPU Read 



4~ 



x °«"^X 



l PDH 



tPDSU 4* — ** 
Data 



Data Valid 



'PDH 



X 



•Port 3 non-latched operation (LATCH ENABLE = 0) 



All Data 
Port Outputs 



f 



MPU Write 



\ f 



-'CMOS - 
-tPWD> 



> 0.7 V CC 



Data Valid 



notes. ' - 

1. 10 k pullup resistor required for port 2 to reach 0.7 Vrjc- 

2. Not applicable to P21. 

3. Port 4 cannot be pulled above Vqc 



FIGURE 4 - PORT 3 OUTPUT STROBE TIMING 
(MC6801 SINGLE-CHIP MODE) 



FIGURE 5 - PORT 3 LATCH TIMING 
(MC6801 SINGLE-CHIP MODE) 



r 



MPU access of Port 3* 



\ f 



Address 
Bus _ 

533 



($0006) 



X 



J 



X 



v 



<tQSD1 



: l 0SD2 



* Access matches output strobe select (OSS = 0, a read; 
OSS = 1, a write) 



P30-P37 
Input: 



-tis- 



•t.PWIS -* 
■t|H 



Data Valid 



X 



NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. 



MOTOROLA MICROPROCESSOR DATA 
3-95 



MC6801/6803 



BUS TIMING (See Notes 1 and 2) 



• 

Ident. 
Number 


Characteristics 


Symbol 


MC6801 
MC6803 


MC6801-1 
MC6803-1 


MC68B01 
MC68B03 


Unit 


Min 


Max 


Min 


Max 


Min 


Max 


1 


Cycle Time 


tcyc 


1 .0 


2.0 


0.8 


2.0 


0.5 


2.0 


(IS 


2 


Pulse Width, E Low 


PWel 


430 


1000 


360 


1000 


210 


1000 


ns 


3 


Pulse Width, E High 


pw eh 


450 


1000 


360 


1000 


220 


1000 


ns 


4 


Clock Rise and Fall Time 






25 




25 




20 


ns 


9 


Address Hold Time 


tAH 


20 




20 




10 




ns 


12 


Non-Muxed Address Valid Time to E* 


tAV 


200 




150 




70 




ns 


17 


Read Data Setup Time 


tDSR 


80 




70 




40 




ns 


18 


Read Data Hold Time 


tDHR 


10 




1 0 




10 




ns 


19 


Write Data Delay Time 


tDDW 




225 




200 




120 


ns 


21 


Write Data Hold Time 


( DHW 


20 




20 




1 0 




ns 


22 


Muxed Address Valid Time to E Rise* 


tAVM 


200 




150 




80 




ns 


24 


Muxed Address Valid Time to AS Fall* 


tASL 


60 




50 




20 




ns 


25 


Muxed Address Hold Time 


tAHL 


20 




20 




10 




ns 


26 


Delay time, E to AS Rise* 


tASD 


90** 




70** 




45** 




ns 


27 


Pulse Width, AS High* 


PWASH 


220 




170 




110 




ns 


28 


Delay Time, AS to E Rise* 


tASED 


90 




70 




45 




ns 


29 


Usable Access Time* 


tACC 


595 




465 




270 




ns 



*At specified cycle time. 

* l ASD parameters listed assume external TTL clock drive with 50% ±5% duty cycle. Devices driven by an external TTL clock with 
50% ± 1% duty cycle or which use a crystal have the following t^SD specifications: 100 nanoseconds minimum (1.0 MHz devices), 
80 nanoseconds minimum (1.25 MHz device), 50 nanoseconds minimum (2.0 MHz devices). 



FIGURE 6 - BUS TIMING 



IOS, 
R/W, Address 
(Non-Muxed) 




Addr/Data 
Muxed 



NOTES 



1. Voltage levels shown are V(_s0.5 V, Vh&2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. 

3. Usable access time is computed by: 12 + 3- 17 + 4. 

4. Memory devices should be enabled only during E high to avoid port 3 bus contention. 



MOTOROLA MICROPROCESSOR DATA 
3-96 



MC6801/6803 



FIGURE 7 - CMOS LOAD 



FIGURE 8 - TIMING TEST LOAD PORTS 1, 2, 3, 4 



vcc 



RL 1.8 kO 



Test Point o- 



Test Point o- 



1 



^ 30 pF 



MMD6150 
or Equivalent 

R ▼ MMD7000 
or Equivalent 



C = 90 pF for P30-P37, P40-P47, E, SC1, SC2 

= 30 pF for P10-P17, P20-P24 
R = 37 kl) for P40-P47, SC1, SC2 

= 24 kl) for P10-P17, P20-P24 

= 24 kll for P30-P37, E 



INTRODUCTION 



The MC6801 is an 8-bit monolithic microcomputer which 
can be configured to function in a wide variety of applica- 
tions. The facility which provides this extraordinary flexibility 
is its ability to be hardware programmed into eight different 
operating modes. The operating mode controls the con- 
figuration of 18 of the 40 MCU pins, available on-chip 
resources, memory map, location (internal or external) of in- 
terrupt vectors, and type of external bus. The configuration 
of the remaining 22 pins is not dependent on the operating 
mode. 

Twenty-nine pins are organized as three 8-bit ports and 
one 5-bit port. Each port consists of at least a data register 
and a write-only data direction register. The data direction 
register is used to define whether corresponding bits in the 
data register are configured as an input (clear) or output 
(set). 



The term "port," by itself, refers to all of the hardware 
associated with the port. When the port is used as a "data 
port" or "I/O port," it is controlled by the port data direction 
register and the programmer has direct access to the port 
pins using the port data register. Port pins are labeled as Pij 
where i identifies one of four ports and j indicates the par- 
ticular bit. 

The microprocessor unit (MPU) is an enhanced MC6800 
MPU with additional capabilities and greater throughput. It is 
upward source and object code compatible with the 
MC6800. The programming model is depicted in Figure 9, 
where accumulator D is a concatenation of accumulators A 
and B. A list of new operations added to the M6800 instruc- 
tion set are shown in Table 1 . 

The MC6803 can be considered an MC6801 that operates 
in Modes 2 and 3 only. 



MOTOROLA MICROPROCESSOR DATA 
3^97 



MC6801/6803 



FIGURE 9 - PROGRAMMING MODEL 



7 A 


°U 7 


0 


15 


D 


0 




15 


X 


0 






SP 


1 




5 


PC 


0 



8-Bit Accumulators A and B 
Or 16-Bit Double Accumulator D 



Index Register (X) 



Stack Pointer (SP> 



Program Counter IPC) 



rr i h i n 











Condition Code Register (CCR) 

Carry/ Borrow from MSB 

Overflow 

Zero 

Negative 

Interrupt 

Half Carry (From Bit 3) 



The MC6801 provides eight different operating modes (0 
through 7) and the MC6803 provides two operating modes (2 
and 3). The operating modes are hardware selectable and 
determine the device memory map, the configuration of port 
3, port 4, SC1, SC2, and the physical location of the inter- 
rupt vectors. 

FUNDAMENTAL MODES 

The eight operating modes can be grouped into three fun- 
damental modes which refer to the type of bus it supports: 
single chip, expanded non-multiplexed, and expanded 
multiplexed. Single-chip modes include 4 and 7, expanded 
non-multiplexed mode is 5, and the remaining five modes are 



MODES 

expanded multiplexed modes. Table 2 summarizes the char- 
acteristics of the operating modes. 



MC6801 Single-Chip Modes (4, 7) 

In the single-chip mode, the four MCU ports are con- 
figured as parallel input/output data ports, as shown in 
Figure 10. The MCU functions as a monolithic microcom- 
puter in these two modes without external address or data 
buses. A maximum of 29 I/O lines and two port 3 control 
lines are provided. Peripherals or another MCU can be inter- 
faced to port 3 in a loosely coupled dual processor configura- 
tion, as shown in Figure 11. 



TABLE 1 - NEW INSTRUCTIONS 



Instruction 


Description 


ABX 


Unsigned addition of accumulator B to index register 


ADDD 


Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator 


ASLD or LSLD 


Shifts the double accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C bit 


BHS 


Branch if higher or same; unsigned conditional branch (same as BCC) 


BLO 


Branch if lower; unsigned conditional branch (same as BCS) 


BRN 


Branch never 


JSR 


Additional addressing mode: direct 


LDD 


Loads double accumulator from memory 


LSL 


Shifts memory or accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C bit 




(same as ASL) 


LSRD 


Shifts the double accumulator right (towards LSB) one bit, the MSB is cleared and the LSB is shifted into the C bit 


MUL 


Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator 


PSHX 


Pushes the index register to stack 


PULX 


Pulls the index register from stack 


STD 


Stores the double accumulator to memory 


SUBD 


Subtracts memory from the double accumulator and leaves the difference in the double accumulator 


CPX 


Internal processing modified to permit its use with any conditional branch instruction 



MOTOROLA MICROPROCESSOR DATA 
3-98 



MC6801/6803 



In single-chip test mode (4), the RAM responds to $XX80 
through $XXFF and the ROM is removed from the internal 
address map. A test program must first be loaded into the 
RAM using modes 0, 1 , 2, or 6. If the MCU is reset and then 
programmed into mode 4, execution will begin at 
$XXFE:XXFF. Mod e 5 can be irreversibly entered from mode 
4 without asserting RESET by setting bit 5 of the port 2 data 
register. This mode is used primarily to test ports 3 and 4 in 
the single-chip and non-multiplexed modes. 
MC6801 Expanded Non-Multiplexed Mode (5) 

A modest amount of external memory space is provided in 
the expanded non-multiplexed mode while significant on- 
chip resources are retained. Port 3 functions as an 8-bit 



bidirectional data bus and port 4 is configured initially as an 
input data port. Any combination of the eight least-signifi- 
cant address lines may be obtained by writing to the port 4 
data direction register. Stated alternatively, any combination 
of AO to A7 may be provided while retaining the remainder as 
input data lines. Internal pullup resistors pull the port 4 lines 
high until the port is configured. 

Figure 12 illustrates a typical system configuration in the 
expanded non-multiplexed mode. The MCU interfaces 
directly with M6800 Family parts and can access 256 bytes of 
external address space at $100 through $1FF. IOS provides 
an address decode of external memory ($100-$1FF) and can 
be used as a memory-page select or chip-select line. 



TABLE 2 - SUMMARY OF MC6801/03 OPERATING MODES 



Common to all Modes: 

Reserved Register Area 
Port 1 
Port 2 

Programmable Timer 
Serial Communications Interface 
Single Chip Mode 7 

128 bytes of RAM; 2048 bytes of ROM 

Port 3 is a parallel I/O port with two control lines 

Port 4 is a parallel I/O port 

SC1 is Input Strobe 3 (IS3) 

SC2 is Output Strobe 3 (OS3) 

Expanded Non-Multiplexed Mode 5 

128 bytes of RAM; 2048 bytes of ROM 
256 bytes of external memory space 
Port 3 is an 8-bit data bus 
Port 4 is an input port/addre ss b us 
SC1 is Input/Output Select (IOS) 

SC2 is Read/Write (R/W) 

Expanded Multiplexed Modes 1 , 2, 3, 6* 

Four memory space options (64K address space): 

(1) No internal RAM or ROM (Mode 3) 

(2) Internal RAM, no ROM (Mode 2) 

(3) Internal RAM and ROM (Mode 1) 

(4) Internal RAM, ROM with partial address bus (Mode 6) 
Port 3 is a multiplexed address/ data bus 

Port 4 is an address bus (inputs/address in Mode 6) 
SC1 is Address Strobe JAS) 

SC2 is Read/Write (R/W) 

Test Modes 0 and 4 

Expanded Multiplexed Test Mode 0 

May be used to test RAM and ROM 
Single Chip and Non-Multiplexed Test Mode 4 

(1) May be changed to Mode 5 without going through Reset 

(2) May be used to test Ports 3 and 4 as I/O ports 



*The MC6803 operates only in modes 2 and 3. 



MOTOROLA MICROPROCESSOR DATA 
3-99 




FIGURE 10 - SINGLE-CHIP MODE 



FIGURE 11 - SINGLE-CHIP DUAL PROCESSOR CONFIGURATION 



VCC 



Vcc Standby - 
RESET - 



Port 1 
8 I/O Lines 



Port 4 
8 I/O Lines 



XTAL 
EXTAL 



~J7 

vss 



• NMI 
-IRQ1 



Port 3 
8 I/O Lines 
iS3 



-+>OSl 



Port 2 
5 I/O Lines 
Serial I/O 
16-Bit Timer 



Port 1 
8 I/O 
Lines 



Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 



VCC 



Vcc Standby ^ 

RESET > 



XTAL 
EXTAL 

MC6801 



OS3 
IS3< 



-E 

NMI 
IRQ1 



VccStandby- 
RESET- 



VCC 

I 



XTAL 
EXTAL 



IS3 
0S3 



VSS 



Port 4 Port 2 

8 I/O 5 I/O Lines 

Lines SCI 

1 6-Bit Timer 



"X" 

vss 



• E 
NMI 
IRQ1 



Port 1 
8 I/O 
Lines 



Port 4 
8 I/O 
Lines 



FIGURE 12 - EXPANDED NON-MULTIPLEXED CONFIGURATION 



Vcc Standby 
RESET - 



Port 1 
8 I/O Lines 

Port 2 
5 I/O 
Lines 
Serial I/O 
16-Bit Timer 



VCC 



XTAL 
EXTAL 
MC6801 



"X" 

vss 



»-E 

•NMI 
IRQ1 



Port 3 
'8 Data Lines 
>-R/W 



>■ IOS 

Port 4 
To 8 
Address Lines 



VCC 



Vcc Standby 

RESET > 

NMI 



IRQ1- 



Port 1 
8 I/O 

Port 2 
5 I/O 

SCI 
Timer 



XTAL 
EXTAL 
MC6801 



vss 



Port 4 



ICS 



-7* 



-►(D0-D7) 
-»(AO-A7) 
->>lOS_ 
->R/W 



-►E 



ACIA 



MC680 1/6803 



Expanded-Multiplex Modes (0, 1, 2, 3, 6) 

A 64K byte memory space is provided in the ex- 
panded-multiplex modes. In each of the expanded-mul- 
tiplexed modes port 3 functions as a time multiplexed 
address/data bus with address valid on the negative 
edge of address strobe (AS), and data valid while E is 
high. In modes 0 to 3, port 4 provides address lines A8 
to A15. In mode 6, however, port 4 initially is configured 
at RESET as an input data port. The port 4 data direction 
register can then be changed to provide any combi- 
nation of address lines, A8 to A15. Stated alternatively, 
any subset of A8to A15can be provided while retaining 
the remaining port 4 lines as input data lines. Internal 
pullup resistors pull the port 4 lines high until software 
configures the port. 

In mode 0, the reset vector is ext ernal fo r the first two 
E cycles after the positive edge of RESET, and internal 
thereafter. In addition, the internal and external data 
buses are connected so there must be no memory map 
overlap in order to avoid potential bus conflicts. Mode 
0 is used primarily to verify the ROM pattern and mon- 
itor the internal data bus with the automated test equip- 
ment. 

Only the MC6801 can operate in each of the ex- 
panded-multiplexed modes. The MC6803 operates only 
in modes 2 and 3. 

Figure 13 depicts a typical configuration for the ex- 
panded-multiplexed modes. Address strobe can be used 
to control a transparent D-type latch to capture ad- 
dresses A0-A7, as shown in Figure 14. This allows port 
3 to function as a data bus when E is high. 



PROGRAMMING THE MODE 

The operating mode is determined at RESET by the 
levels asserted on P22, P21, and P20. These levels are 
latched into PC2, PC1, and PCO of the p rogram control 
register on the positive edge of RESET. The operating 
mode may be read from the port 2 data register as 
shown below, and programming levels and timing must 
be met as shown in Figure 15. A brief outline of the 
operating modes is shown in Table 3. Note that if diodes 
are used to program the mode, the diode forward volt- 
age drop must not exceed the V|\/|PDD minimum. 

PORT 2 DATA REGISTER 



PC2 


PC1 


PCO 


P24 


P23 


P22 


P21 


P20 



Circuitry to provide the programming levels is de- 
pendent primarily on the normal system usage of the 
three pins. If configured as outputs, the circuit shown 
in Figure 16 may be used; otherwise, three-state buffers 
can be used to provide isolation while programming 
the mode. 




TABLE 3 - MODE SELECTION SUMMARY 





P22 


P21 


P20 






Interrupt 


Bus 


Operating 


Mode* 


PC2 


PC1 


PCO 


ROM 


RAM 


Vectors 


Mode 


Mode 


7 


H 


H 


H 


I 


I 


I 


I 


Single Chip 


6 


H 


H 


L 


I 


I 


I 


MUX<5, 6) 


Multiplexed/ Partial Decode 


5 


H 


L 


H 


. J 


I 


I 


NMUX( 5 ' 6 > 


Non-Multiplexed/ Partial Decode 


4 


H 


L 


L 


|(2) 


Id) 


I 


■ I 


Single-Chip Test 


3 


L 


H 


H 


E 


E 


E 


MUXM) 


Multiplexed/ No RAM or ROM 


2 


L 


H 


L 


E 


I 


E 


MUX< 4 > 


Multiplexed/ RAM 


1 


L 


L 


H 


I 


I 


E 


MUX< 4 > 


Multiplexed/ RAM and ROM 


0 


L 


L 


L 


I 


I 


|(3) 


MUXW) 


Multiplexed Test 



NOTES: 

(1) Internal RAM is addressed at $XX80. 

(2) Interna l ROM is disabled. 

(3) RESET vector is external for two cycles after RESET goes high. 

(4) Addresses associated with ports 3 and 4 are considered external in modes 0, 
1,2, and 3. 

(5) Addresses associated with port 3 are considered external in modes 5 and 6. 

(6) Port 4 default is user data input; address output is optional by writing to port 4 
data direction register. 

•The MC6803 operates only in modes 2 and 3. 



Legend: 
I — Internal 
E - External 
MUX - Multiplexed 
NMUX - Non-Multiplexed 
L - Logic Zero 
H - Logic One 



MOTOROLA MICROPROCESSOR DATA 
3-101 



MC6801/6803 



FIGURE 13 - EXPANDED MULTIPLEXED CONFIGURATION 



[ZD 



Vcc S tandby - 
RESET - 



Port 1 
8 I/O Lines 

Port 2 
5 I/O Lines 
Serial I/O 
16-Bit Timer 



vcc 
J 



XTAL 
EXTAL 



MC6801 
MC6803 



vss 



•E 

•NMi 

•moi 



Port 3 8 Lines 
Multiplexed Data/ Address 



'R/W 
►AS 



Port 4 
8 Lines 
Address Bus 



9 



Vcc Standby >• 



RESET - 
NMI - 
IRQ1- 



Port 1 
8 I/O 
Port 2 
5 I/O 
SCI 
Timer 



VCC 
I 



XTAL 
EXTAL 



MC6801 
MC6803 



"X" 

vis 



Port 3 8 



AS 



Latch j 
Port 4 f 



u7 16 



R/W 



Data Bus 
* (D0-D7) 

Address Bus 



(A0-A15) 
-»-R/W 



ROM 




RAM 




PIA 



NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory devices should be enabled only during E high time. 



FIGURE 14 - TYPICAL LATCH ARRANGEMENT 



GND >- 



AS >- 



Port 3 
Address/ Data 



G OC 
D1 01 

SN74LS373 
(Typical) 



D 8 



Address: A0-A7 



Data: D0-D7 



MOTOROLA MICROPROCESSOR DATA 
3-102 



MC6801/6803 



FIGURE 15 — MODE PROGRAMMING TIMING 



rTseT 



PWrsTL— 
-tMPS- 



Mode Inputs . 
(P20, P21, P22) 



VMPH 



VMPL 



See Figure 16 
for Diode Arrangement 



V MPDD 



l MPH 



V MPH Mm 



Vmpl Max 



(P20, P21, P22) 
RTsTf 




MODE PROGRAMMING (Refer to Figure 15) 



Characteristic 


Symbol 


Min 


Max 


Unit 


Mode Programming Input Voltage Low* (for Ta=0 to,70°C) 






1.7 


V 


Mode Programming Input Voltage High 


vmph 


4.0 




V 


Mode Programming Diode Differential (If Diodes are Used) (for Ta = 0 to 70X) 


V MPDD 


0.4 




V 


RESET Low Pulse Width 


PWRSTL 


3.0 




E Cycles 


Mode Programming Setup Time 


IMPS 


2.0 




E Cycles 


Mode Programming Hold Time 
RESET Rise TimesM us 
RESET Rise Time<1 m-s 


tMPH 


0 

100 




ns 



Note: ForTA= -40 to 85°C, Maximum V|yip|_ = 1.7, and Minimum V|y]pDD = 0 - 4 - 

FIGURE 16 - TYPICAL MODE PROGRAMMING CIRCUIT 

V CC 





NOTES: 

1. Mode 7 as shown 

2. R2 • C = Reset time constant 

3. Ri = 10 k (typical) 

4. D = IN914, IN4001 in the 0 to 70°C range 
D=1N270, MBD201 in the -40 to 85°C range 

5. Diode Vf should not exceed VmpdD min. 



0 6 6 




D! ! D. f . D ! '. 



Mode 
Control 
Switches 



RESET 
P20 (PC0) 
P21 (PCD 
P22 (PC2) 



MC6801 
MC6803 




MEMORY MAPS 

The M6801 Family can provide up to 64K byte address 
space depending on the operating mode. A memory 
map for each operating mode is shown in Figure 17. 
The first 32 locations of each map are reserved for the 
internal register area, as shown in Table 4, with excep- 
tions as indicated. 



MOTOROLA MICROPROCESSOR DATA 
3103 



MC680 1/6803 



FIGURE 17 - MC6801/03 MEMORY MAPS (Sheet 1 of 3) 



a 



Multiplexed- Test Mode 



MC6801 
Mode 



$0000(1) 
$001 F 



$00FF 




$F800 



$FFFF<2) 




Internal Registers 
External Memory Space 

Internal RAM 



External Memory Space 



Internal ROM 

Internal Interrupt Vectors' 2 ' 



NOTES: 

1 ) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07, and $0F. 

2) Addresses $FFFE and $FFFF are considered 
external if acce ssed wi thin two cycles after a 
positive edge of RESET and internal at all other 
times. 

3) After two MPU cycles, there must be no over- 
lapping of internal and external memory spaces 
to avoid driving the data bus with more than one 

device. 

4) This mode is the only mode which may be used 
to examine the int errupt v ectors in internal ROM 
using an external RESET vector. 



MC6801 
Mode 



1 



Multiplexed/RAM and ROM 

$0000(D ypp 



$001 F 
$0080 
$00FF 




$F800 

$FFEF 
$FFF0 
$FFFF 




Internal Registers 
External Memory Space 
Internal RAM 

External Memory Space 

Internal ROM 

External Interrupt Vectors 



NOTES: 

1) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07, and $0F. 

2) Internal ROM addresses $FFF0 to $FFFF are not 
usable. 



MOTOROLA MICROPROCESSOR DATA 
3-104 



FIGURE 17 - 



MC6801/03 MEMORY MAPS (Sheet 2 of 3) 



MC6801 
MC6803 
Mode 



Multiplexed/ RAM 




$00FF 



$FFF0 
$FFFF 



Internal Registers 
External Memory Space 

Internal RAM 



External Memory Space 



External Interrupt Vectors 



NOTES: . 

1) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07, and $0F. 



MC6801 
MC6803 
Mode 



Multiplexed/No RAM or ROM 
$0000d) 



$001 F 



$FFF0 
$FFFF 



Internal Registers 



External Memory Space 



External Interrupt Vectors 



NOTES: 

1) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07, and $0F 



MC6801 
Mode 



Single-Chip Test 



$0000 
$001 F 



Internal Registers 



Unusable l 1 >W) 



$XX80 
$XXFF 



} Internal RAM 
Internal Interrupt Vectors 



NOTES: 

1) The internal ROM is disabled. 

2) Mode 4 may be chang ed to Mode 5 without hav- 
ing to assert RESET by writing a one into the 
PCO bit of the port 2 data register. 

3) Addresses A8 to A15 are treated as "don't cares" 
to decode internal RAM. 

4) Internal RAM will appear at $XX80 to $XXFF. 





FIGURE 17 - MC6801/03 MEMORY MAPS (Sheet 3 of 3) 




Non-Multiplexed/ Partial Decode 
$0000' D 



$001 F 



$0080 



Unusable 




Internal Registers 



Internal RAM 

External Memory Space 



$F800 



$FFFF 



Internal ROM 



Internal Interrupt Vectors 



NOTES: ■ 

1 ) Excludes the following addresses which may not 
be used externally: $04, $06, and $0F (no IQS). 

2) This m ode ma y be: entered without going 
through RESET by using mode 4 and subse- 
quently writing a one into the PCO bit of the port 
2 data register, 

3) Address lines AO to A7 will not contain addresses 
until the data direction register for port 4 has 
been written with ones in the appropriate bits. 
These address lines will assert ones until made 
outputs by writing the data direction register. 



MC6801 
Mode 



Multiplexed/Partial Decode 



$00001! > 
$001 F 
$0080 

$00FF 




$F800 



$FFFF 




Internal Registers 
External Memory Space 



Internal RAM 



External Memory Space 



Internal ROM 



Internal Interrupt Vectors 



NOTES: 

1 ) Excludes the following addresses which may be 
used externally: $04, $06, and $0F. 

2) Address lines A8-A15 will not contain addresses 
until the data direction register for port 4 has 
been written with ones in the appropriate bits. 
These address lines will assert ones until made 
outputs by writing the data direction register. 



MC6801 
Mode 



Single Chip 



$0000 
$001 F 
$0080 

$00FF 



Internal Registers 



Unusable 

Internal RAM 



Unusable 



$F800 



$FFFF 




o 

O) 
00 

© 

— 1 

o> 

00 

o 

CO 



Internal ROM 

Internal Interrupt Vectors 



MG6801/6803 



MC6801/03 INTERRUPTS 

The M6801 Family supports two types of interrupt re- 
quest s: m askable and non-maskable. A non-maskable inter- 
rupt (NMD is always recognized and acted upon at the com- 
pletion of the current instruction. Maskable interrupts are 
controlled by the condition code register I bit and by in- 
dividual enable bits. The I bit controls all maskable i nter- 
rupt s. Of the maskable interrupts, there are two types: IRQ1 
and IRQ2. The programmable time r and serial communica- 
tions interface use an internal IRQ2 interr upt lin e, a s sho wn 
in Figure 1. External devic es (an d IS3) use IRQ1. An IRQ1 in-- 
terrup t is se rviced before IRQ2 if both are pending. 

All IRQ2 interrupts use hardware prioritized vectors. The 
single SGI interrupt and three timer interrupts are serviced in 
a prioritized order and each is vectored to a separate loca- 
tion. All interrupt vector locations are shown in Table 5. 

The interrupt flowchart is depicted in Figure 18 and is 
common to every interrupt excluding reset. During interrupt 
servicing the program counter, index register, A accumu- 
lator, B accumulator, and condition code. register are pushed 
to the stack. The I bit is set to inhibit maskable interrupts and 
a vector is fetched corresponding to the current highest 
priority interrupt. The vector is transferred to the program 
counte r and instruction execution is resumed. Interrupt and 
RESET timing are illustrated in Figures 19 and 20. 



FUNCTIONAL PIN DESCRIPTIONS 

V C C AND V S S 

Vcc an d Vgs P rov 'd e power to a large portion of the 
MCU. The power supply should provide + 5 volts ( ± 5%) to 
Vcc, ar| d Vss snou 'd ^ e t ' ecl t0 9 rouncl - Total power 
dissipation (including Vcc standby), will not exceed Pq 
milliwatts. 



between them to prevent supplying power to Vcc during 
powerdown operation. Vcc standby should be tied to 
ground in mode 3. 



TABLE 4 - INTERNAL REGISTER AREA 



Register 


Address 


Port 1 Data Direction Register*** 


00 


Port 2 Data Direction Register* * * 


01 


Port 1 Data Register 


02 


Port 2 Data Register 


03 


Port 3 Data Direction Register* * * 


04* 


Port 4 Data Direction Register* * * 


05** 


Port 3 Data Register 


06* 


Port 4 Data Register 


07** 


Timer Control and Status Register 


08 


Counter (High Byte) 


09 


Counter (Low Byte) 


OA 


Output Compare Register (High Byte) 


0B 


Output Compare Register (Low Byte) 


0C 


Input Capture Register (High Byte) 


0D 


Input Capture Register (Low Byte) 


0E 


Port 3 Control and Status Register 


OF* 


Rate and Mode Control Register 


'10 


Transmit/ Receive Control and Status Register 


11 


Receive Data Register 


12 


Transmit Data Register 


13 


RAM Control Register 


14 


Reserved 


15-1 F 



•External addresses in modes 0, 1, 2, 3, 5, and 6; cannot be ac- 
cessed in mode 5 (no IOS). 
** External addresses in modes 0, 1,2, and 3. 
= *1= Output, 0= Input. 



V C C STANDBY 

Vcc standby provides power to the standby portion ($80 
through $BF) of the RAM and the STBY PWR and RAME 
bits of the RAM control register. Voltage requirements de- 
pend on whether the device is in a powerup or powerdown 
state. In the powerup state, the power supply should provide 
+ 5 volts (±5%) and must reach V$B v °l ts before RESET 
reaches 4.0 volts. During powerdown, Vcc standby must re- 
main above VsBB (rnin) to sustain the standby RAM and 
STBY PWR bit. While in powerdown operation, the standby 
current will not exceed isBB- 

It is typical to power both Vcc an d Vcc standby from the 
same source during normal operation. A diode must be used 



TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS 



MSB 


LSB 


Interrupt 


FFFE 


FFFF 


RESET 


FFFC 


FFFD 


NMl 


FFFA 


FFFB 


Software Interrupt (SWI) 


FFF8 


FFF9 


IRQl (orlS3) 


FFF6 


FFF7 


ICF (Input Capture)* 


FFF4 


FFF5 


OCF (Output Capture)* 


FFF2 


FFF3 


TOF (Timer Overflow)* 


FFF0 


FFF1 


SCI (RDRF + ORFE + TDRE)* 



*IRQ2 Interrupt 



MOTOROLA MICROPROCESSOR DATA 
3-107 



FIGURE 19 - INTERRUPT SEQUENCE 




#2 



#3 



#5 



#8 



#9 



#10 



l-Bit Set 



OpCode OpCode SP(n) SP(n-1) SP(n-2) SP(n-3) SP(n-4) SP(n-5) SP(n-6) SP(n-7) Vector Vector New PC 
Addr Addr MSB Addr LSB Addr Address 



NMI or IRQ2 



— »-) \<— IPCS 



Internal — y ' y y y V V V' V y V V 'Y V V V" 

Data Bus A A A A A AA A A A A A AAA 



Op Code Op Code PC 0-7 PC8-15 X 0-7 X8-15 ACCA ACCB CCR Irrelevant Vector Vector First Inst, of 

Data MSB LSB Interrupt Routine 



Internal R/W 



■v 



S 



FIGURE 20 - RESET TIMING 

^ Mn\\\\\\\\\\\ UU~l JlJ~UnJTJTi~l rLTLTLT 

.5 25 V 



v «7l 



4 75 V 



■4 h 



-tRC- 



RESET 



-I h 



tPCS 



/ 4 0 V 



08 



•tPCS 



Internal 
Address 



L WWWWWWNWW Sj l\ \\\\\\ \ \\\\\\\\\\\\\\\\\\\ XZZ^ ; ^3CIIDCZXZDCZDCZ3(iJZX 



FFFE 1 FFFE FFFE FFFE FFFF New PC 



FFFE FFFE 



n,erna,R/W ^\ \\\\\\\\ \ \\\\^ 



Internal 
Data Bus 



Not Valid 



PC 8-15 PC 0-7 First 

Instruction 



5 
o 

o> 
00 
o 

o> 

00 




MC6801/6803 



XTAL AND EXTAL 

These two input pins interface either a crystal orTTL- 
compatible clock to the MCU internal clock generator. 
Divide-by-four circuitry is included which allows use of 
the inexpensive 3.58 MHz or 4.4336 MHz Color Burst TV 
crystals. A 20 pF capacitor should be tied from each 
crystal pin to ground to ensure reliable startup and op- 
eration. Alternatively, EXTAL may be driven by an ex- 
ternal TTL-compatible clock at 4f 0 with a duty cycle of 
50% (±5%) with XTAL connected to ground. 

The internal oscillator is designed to interface with an AT- 
cut quartz crystal resonator operated in parallel resonance 
mode in the frequency range specified for fxTAL- The 
crystal should be mounted as close as possible to the input 
pins to minimize output distortion and startup stabilization 
time.* The MCU is compatible with most commercially 
available crystals. Nominal crystal parameters are shown in 
Figure 21. 




RESET 

This input is used to reset the internal state of the device 
and pro vide an orderly startup procedure. During powerup, 
RESET must be held below 0.8 volts: (1) at least tRc after 
Vrjc reaches 4.75 volts in order to provide sufficient time for 
the clock generato r to sta bilize, and (2) until Vcc standby 
reaches 4.75 volts. RESET must be held low at least three E 
cycles if asserted during powerup operation. 

E (ENABLE) 

This is an output clock used primarily for bus synchroniza- 
tion. It is TTL compatible and is the slightly skewed divide- 
by-four result of the device input clock frequency. It will 
drive one Schottky TTL load and 90 pF, and all data given in 
cycles is referenced to this clock unless otherwise noted. 

NON-MASKABLE INTERRUPT (NMI) 

An NMI negative edge requests an MCU interrupt se- 
quence, but the current instruction will be completed before 
it responds to the request. The MCU will then begin an inter- 
rupt sequence. Finally, a, vector is fetched from $FFFC and 
$FFFD, transferred to th e pro gram counter and instruction 
execution is resumed. NMI typically require s a 3.3 kfl 
(nominal ) res istor to VCC- There is no internal NMI pullup 
resistor. NMI must be held low for at least one E cycle to be 
recognized under all conditions. 

MASKABLE INTERRUPT REQUEST 1 (IRQI) 

IRO.1 is a level-sensitive input which can be used to re- 
quest an interrupt sequence. The MPU will complete the cur- 
rent instruction before it responds to the request. If the inter- 
rupt mask bit (I bit) in the condition code register is clear, the 
MCU will begin an interrupt sequence. A vector is fetched 
from $FFF8 and $FFF9, transferred to the program counter, 
an d ins truction execution is resumed. 

IRQ1 typically requires an external 3.3 kQ (nominal) 
resistor to Vcc for wire-OR applications. IRQ1 has no inter- 
nal pullup resistor. 

STROBE CONTROL 1 AND 2 (SC1 AND SC2) 

The function of SC1 and SC2 depends on the operating 
mode. SC1 is configured as an output in all modes except 
single-chip mode, whereas SC2 is always an output. SC1 
and SC2 can drive one Schottky load and 90 pF. 



SC1 and SC2 In Single-Chip Mode 

In single-chip mode, SC1 and SC2 are configured as an 
input and output, respectively, and both function as port 3 
control lines. SC1 functions as IS3 and can be used to indi- 
cate that port 3 input data is ready or output data has been 
accepted. Three options associated with IS3 are controlled 
by port 3 control and status register and are discussed in the 
PORT 3 (P30-P37). If u nused , TS3 can remain unconnected. 

SC2 is configured as OS3 and can be used to strobe out- 
put data or acknowledge input data. It is controlled by out- 
put strobe select (OSS) in the port 3 control and status 
register. The strobe is generated by a read (OSS = 0) or write 
(OSS =1) to the port 3 data register. OS3 timing is shown in 
Figure4. ; 

SC1 and SC2 In Expanded Non-Multiplexed Mode 

In the expanded . non-multiplexed mode, both SC1 and 
SC2 are configured as outputs. SC1 functions as input/out- 
put select "(iOS) and is asserted only when $0100 through 
$01 FF is sensed on the internal address bus. 

SC2 is configured as read/ write and is used to control the 
direction of data bus transfers. An MPU read is enabled 
when read/write and E are high. 

SC1 and SC2 In Expanded-Multiplexed Mode 

In the expanded-multiplexed mode, both SC1 and SC2 are 
configured as outputs. SC1 functions as address strobe and 
can be used to demultiplex the eight least-significant ad- 
dresses and the data bus. A latch controlled by address 
strobe captures address on the negative edge, as shown in 
Figure 14 

SC2 is configured as read/write and is used to control the 
direction of data bus transfers. An MPU read is enabled 
when read/write and E are high. 

PORT 1 (P10-P17) 

Port 1 is a mode independent 8-bit I/O port with each line 
an input or output as defined by the port 1 data direction 
register. The TTL compatible three-state output buffers can 
drive one Schottky TTL load and 30 pF, Darlington tran- 
sistors, or CMOS devices using ex ternal pu llup resistors. It is 
configured as a data input port by RESET. Unused lines can 
remain unconnected. : 

PORT 2 (P20-P24) 

PORT 2 DATA REGISTER 

6 5 4 3 2 



PC2 


PC1 


PCO 


P24 


P23 


P22 


P21 


P20 



$0003 



Port 2 is a mode-independent, 5-bit, multi-purpose I/O 
port. The volta ge leve ls present on P20, P21 , and P22 on the 
rising edge of RESET determine the operating mode of the 
MCU. The entire port is then configured as a data input port. 
The port 2 lines can be selectively configured as data output 
lines by setting the appropriate bits in the port 2 data direc- 
tion register. The port 2 data register is used to move data 
through the port. However, if P21 is configured as an out- 
put, it will be tied to the timer output compare function and 
cannot be used to provide output from the port 2 data 
register. 



t Devices made with masks subsequent to M5G, M8D, and T5P incorporate an advanced clock with improved startup characteristics. 



MOTOROLA MICROPROCESSOR DATA 
3-110 



MC6801/6803 



FIGURE 21 - M6801 FAMILY OSCILLATOR CHARACTERISTICS 
(a) Nominal Recommended Crystal Parameters 

Nominal Crystal Parameters* 





3.58 MHz 


4.00 MHz 


5.0 MHz 


6.0 MHz 


8.0 MHz 




60Q 


50Q 


30-50 0 


30-50 0 


20-40 0 


c 0 


3.5 pF 


6.5 pF 


4-6 pF 


4-6 pF 


4-6 pF 


C1 


0.015 pF 


0.025 pF 


0.01-0.02 pF 


0.01-0.02 pF 


0.01-0.02 pF 


Q 


>40 K 


>30 K 


>20 K 


>20 K 


>20 K 



* NOTE: These are representative AT-cut crystal parameters only. Crystals of other types of cut may also 
be used. 



MC6801 



jf-Wr- 



C1 




C|_ = 20pF (typical) 



C 0 

Equivalent Circuit 



NOTE 

TTL-compatible oscillators may be 
obtained from: 

Motorola Component Products 

Attn: Data Clock Sales 

2553 N. Edgington St. 

Franklin Park, IL 60131 

Tel: 312-451-1000 

Telex: 433-0067 



(b) Oscillator Stabilization Time (tRC> 
-fj- 




MOTOROLA MICROPROCESSOR DATA 
3-111 



MC680 1/6803 



Port 2 can also be used to provide an interface for the 
serial communications interface and the timer input edge 
function. These configurations are described in PROGRAM- 
MABLE TIMER and SERIAL COMMUNICATIONS INTER- 
FACE (SCI). 

The port 2 high-impedance TTL-compatible output buffers 
are capable of driving one Schottky TTL load and 30 pF, or 
CMOS devices using external pullup resistors. 

PORT 3 (P30-P37) 

Port 3 can be configured as an I/O port, . a bidirectional 
8-bit data bus, or a multiplexed address/data bus depending 
on the operating mode. The TTL-compatible high- 
impedance output buffers can drive one Schottky TTL load 
and 90 pF. Unused lines can remain unconnected. 

Port 3 In Single-Chip Mode 

Port 3 is an 8-bit I/O port in the single-chip mode, with 
each line configured byjhe port 3 d ata direction register. 
There are also two lines, I S3 and OS3, which can be used to 

9 control port 3 data transfers. 
Three port 3 options are controlled by the port 3 control 
and status register and are available only in single-chip 
mode: (1) port 3 i nput data can be latched using IS3 as a 
control signal, (2) 0S3 can be generated by either an M PU 
read or write to the port 3 data register, and (3) an IRQ1 in- 
terrupt can be enabled by an IS3 negative edge. Port 3 latch 
timing is shown in Figure 5. 

PORT 3 CONTROL AND STATUS REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 




IS3 














IS3 


IRQ1 


X 


OSS 


Latch 


X 


X 


X 


Flag 


Enable 






Enable 









Bit 0-2 Not used. 

Bit 3 LATCH ENABLE. This bit controls the 

input latch for port 3. If set, input data 
is latched by an I S3 negative edge. The 
latch is transparent after a read of the 
port 3 data register. LATCH ENABLE 
is cleared during reset. 

Bit 4 OSS (Output Strobe Select). This bit 

determines whether OS3 will be 
generated by a read or write of the port 
3 data register. When clear, the strobe 
is generated by a read; when set, it is 
generated by a write. OSS is cleared 
during reset. 

Bit 5 Not used. 

Bit 6 IS3 IRQ1 ENABLE. When set, an IRQT 

interrupt will be enabled whenever IS3 
FLAG is set; when clear, the interrupt 
is inhibited. This bit is cleared during 
reset. 

Bit 7 IS3 FLAG. Thjs read-only status bit is 

set by an I S3 negative edge. It is 
cleared by a read of the port 3 control 
and status register (with I S3 FLAG set) 
followed by a read or write to the port 
3 data register or during reset. 



Port 3 In Expanded Non-Multiplexed Mode 

Port 3 is configured as a bidirectional data bus (D7-D0) in 
the expanded non-multiplexed mode. The direction of data 
transfers is controlled by read/write (SC2). Data is clocked 
by E (enable). 

Port 3 In Expanded- Multiplexed Mode 

■.: Port 3 is configured as a time multiplexed address (A0-A7) 
and' data bus (D7-D0) in the expanded-multiplexed modes, 
where address strobe (AS) can be used to demultiplex the 
two buses. Port 3 is held in a high-impedance state between 
valid address and data to prevent bus conflicts. 

PORT 4 (P40-P47) 

Port 4 is configured as an 8-bit I/O port, as address out- 
puts, or as data inputs depending on the operating mode. 
Port 4 can drive one Schottky TTL load and 90 pF and is the 
only port with internal pullup resistors. Unused lines can re- 
main unconnected. 

Port 4 In Single-Chip Mode 

In single-chip mode, port 4 functions as an 8-bit I/O port 
with each line configured by the port 4 data direction 
register. Internal pullup resistors allow the port to directly 
interface with CMOS at 5 volt levels. External pullup resistors 
to more than 5 volts, however, cannot be used. 

Port 4 In Expanded Non-Multiplexed Mode 

Port 4 is configured from reset as an 8-bit input port, 
where the port 4 data direction register can be written to pro- 
vide any or all of eight address lines, AO to A7. Internal 
pullup resistors pull the lines high until the port 4 data direc- 
tion register is configured. 

Port 4 In Expanded-Multiplexed Mode 

In all expanded-multiplexed modes except mode 6, port 4 
functions as half of the address bus and provides A8 to A15. 
In mode 6, the port is configured from reset as an 8-bit 
parallel input port, where the port 4 data direction register 
can be written to provide any or all of upper address lines A8 
to A15. Internal pullup resistors pull the lines high until the 
port 4 data direction register is configured, where bit 0 con- 
trols A8. 

RESIDENT MEMORY 

The MC6801 provides 2048 bytes of on-chip ROM and 128 
bytes of on-chip RAM. 

One half of the RAM is powered through the Vcc standby 
pin and is maintainable during Vcc powerdown. This stand- 
by portion of the RAM consists of 64 bytes located from $80 
through $BF. 

Power must be supplied to Vcc standby if the internal 
RAM is to be used regardless of whether standby power 
operation is anticipated. 

The RAM is controlled by the RAM control register. 

RAM CONTROL REGISTER ($14) 

The RAM control register includes two bits which can be 
used to control RAM accesses and determine the adequacy 
of the standby power source dtiring powerdown operation. 
It is intended that RAME be cleared and STBY PWR be set 
as part of a powerdown procedure. 



MOTOROLA MICROPROCESSOR DATA 
3-112 



MC680 1/6803 



RAM CONTROL REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


STBY 
PWR 


RAME 


X 


X 


X 


X 


X 


X 



Bit 0-5 Not used. 

Bit 6 RAME RAM Enable. This read/write bit can 

be used to remove the entire RAM 
from the internal memory map. RAME 
is set (enabled) during reset provided 
standby po wer is av ailable on the posi- 
tive edge of RESET. If RAME is clear, 
any access to a RAM address is exter- 
nal. If RAME is set and not in mode 3, 
the RAM is included in the internal 
map. 

Bit 7 STBY PWR Standby Power. This bit is a 
read/write status bit which, when 
once set, remains set as long as Vqq 
standby remains above VsBB (mini- 
mum). As long as this bit is set follow- 
ing a period of standby operation, the 
standby power supply has adequately 
preserved the data in the standby 
RAM. If this bit is cleared during a 
period of standby operation, it indi- 
cates that Vcc standby had fallen to a 
level sufficiently below VsBB (mini- 
mum) to suspect that data in the 



standby RAM is not valid. This bit can 
be set only by software and is not af- 
fected during reset. 



PROGRAMMABLE TIMER 

The programmable timer can be used to perform input 
waveform measurements while independently generating an 
output waveform. Pulse widths can vary from several micro- 
seconds to many seconds. A block diagram of the timer is 
shown in Figure 22. 

COUNTER ($09:0A) 

The key timer element is a 16-bit free-running counter 
which is incremented by E (enable). It is cleared during reset 
and is read-only with one exception: a write to the counter 
($09) will preset it to $FFF8. This feature, intended for 
testing, can disturb serial operations because the counter 
provides the SCI internal bit rate clock. TOF is set whenever 
the counter contains all ones. 

OUTPUT COMPARE REGISTER ($OB:0C) 

The output compare register is a 16-bit read/write register 
used to control an output waveform or provide an arbitrary 
timeout flag. It is compared with the free-running counter on 
each E cycle. When a match occurs, OCF is set and OLVL is 
clocked to an output level register. If port 2, bit 1 , is con- 
figured as an output, OLVL will appear at P21 and the output 
compare register and OLVL can then be changed for the next 



\ IRQ2 

NTT 



FIGURE 22 - BLOCK DIAGRAM OF PROGRAMMABLE TIMER 



MC6801/MC6803 Internal Bus 




$0B:0C 



$O9:0A 



Output Compare 
Register 



Free Running 
16-Bit Counter 



Input Capture 
Register 




Output Compare Overflow Detect 



Timer 
Control 
And 

Status 
Register 



Edge Detect 



ICF 


OCF 


TOF 


EICI 


EOCI 


ETOI 


IEDG 


OLVL 




Output Compare Pulse 



r> 



Output 
Level 
Register 



Port 
DDR 



,ti >nl 

»rt2 

DR Ij 



Output 
Level 
Bit 1 
Port 2 



Input 
Edge 
BitO 
Port 2 



MOTOROLA MICROPROCESSOR DATA 
3-T13 



MC6801/6803 



compare. The function is inhibited for one cycle after a write 
to its high byte ($0B) to ensure a val id com pare. The output 
compare register is set to $FFFF at RESET. 

INPUT CAPTURE REGISTER ($0D:0E) 

The input capture register is a 16-bit read-only register 
used to store the free-running counter when a "proper" in- 
put transition occurs as defined by IEDG. Port 2, bit 0 should 
be configured as an input, but the edge detect circuit always 
senses P20 even when configured as an output. An input 
capture can occur independently of ICF: the register always 
contains the most current value. Counter transfer is in- 
hibited, however, between accesses of a double byte MPU 
read. The input pulse width must be at least two E cycles to 
ensure an input capture under all conditions. 

TIMER CONTROL AND STATUS REGISTER ($08) 

The timer control and status register (TCSR) is an 8-bit 
register of which all bits are readable, while only bits 0-4 can 
be written. The three most-significant bits provide the timer 
status and indicate if: 

• a proper level transition has been detected, 

• a match has occurred between the free-running 
counter and the output compare register, and 

• the free-running counter has overflowed. 

Each of the three events can generate an IRQ2 interrupt 
and is controlled by an individual enable bit in the TCSR. 

TIMER CONTROL AND STATUS REGISTER (TCSR) 



0 



ICF 


OCF 


TOF 


EICI 


EOCI 


ETOI 


IEDG 


OLVL 



$0008 



Bit 0 OLVL Output Level. OLVL is clocked to the 

output level register by a successful 
output compare and will appear at P21 
if bit 1 of the port 2 data direction 
register is set. It is cleared during reset. 

Bit 1 EIDG Input Edge. IEDG is cleared during 

reset and controls which level transi- 
tion will trigger a counter transfer to 
the input capture register: 
IEDG = 0 Transfer on a negative-edge 
IEDG= 1 Transfer on a positive-edge. 

Bit 2 ETOI Enable Tim er O verflow Interrupt. 

When set, an IRQ2 interrupt is enabled 
for a timer overflow; when clear, the 
interrupt is inhibited. It is cleared dur- 
ing reset. 

Bit 3 EOCI Enable Output Compare Interrupt. 

When set, an IRQ2 interrupt is enabled 
for an output compare; when clear, 
the interrupt is inhibited. It is cleared 
during reset. 

Bit 4 EICI Enable Input Capture Interrupt. When 

set, an IRQ2 interrupt is enabled for an 
input capture; when clear, the inter- 
rupt is inhibited. It is cleared during 
reset. 



Bit 5 TOF Timer Overflow Flag. TOF is set when 

the counter contains all ones. It is 
cleared by reading the TCSR (with 
TOF set) then reading the counter high 
byte ($09), or during reset. 

Bit 6 OCF Output Compare Flag. OCF is set 

when the output compare register 
matches the free-running counter. It is 
cleared by reading the TCSR (with 
OCF set) and then writing to the out- 
put compare register ($0B or $0C), or 
during reset. 

Bit 7 ICF Input Capture Flag. ICF is set to in- 

dicate a proper level transition; it is 
cleared by reading the TCSR (with ICF 
set) and then the input capture register 
high byte ($0D), or during reset. 



SERIAL COMMUNICATIONS INTERFACE (SCI) 

A full-duplex asynchronous serial communications inter- 
face (SCI) is provided with two data formats and a variety of 
rates. The SCI transmitter and receiver are functionally in- 
dependent, but use the same data format and bit rate. Serial 
data formats include standard mark/space (NRZ) and Bi- 
phase and both provide one start bit, eight data bits, and one 
stop bit. "Baud" and "bit rate" are used synonymously in 
the following description. 

WAKE-UP FEATURE 

In a typical serial loop multi-processor configuration, 
the software protocol will usually identify the addres- 
see^) at the beginning of the message. In order to per- 
mit uninterested MPU's to ignore the remainder of the 
message, a wake-up feature is included whereby all fur- 
ther SCI receiver flag (and interrupt) processing can be 
inhibited until its data line goes idle. An SCI receiver is 
re-enabled by an idle string of eleven consecutive ones 
or during reset. Software must provide for the required 
idle string between consecutive messages and prevent 
it within messages. 

PROGRAMMABLE OPTIONS 

■ The following features of the SCI are programmable: 

• format: standard mark/space (NRZ) or Bi-phase 

• clock: external or internal bit rate clock 

• Baud: one of four per E clock frequency, or external 
clock ( x 8 desired baud) 

• wake-up feature: enabled or disabled 

• interrupt requests: enabled individually for transmitter 
and receiver 

• clock output: internal bit rate clock enabled or disabled 
to P22 

SERIAL COMMUNICATIONS REGISTERS 

The serial communications interface includes four ad- 
dressable registers as depicted in Figure 23. It is controlled 
by the rate and mode control register and the transmit/ 
receive control and status register. Data is transmitted and 



MOTOROLA MICROPROCESSOR DATA 
3-114 



MC6801/6803 



received utilizing a write-only transmit register and a read- 
only receive register. The shift registers are not accessible to 
software. 

Rate and Mode Control Registers (RMCR) ($10) 

The rate and mode control register controls the SCI bit 
rate, format, clock source, and under certain conditions, the 
configuration of P22. The register consists of four write-only 
bits which are cleared during reset. The two least-significant 
bits control" the bit rate of the internal clock and the remain- 
ing two bits control the format and clock source. 

RATE AND MODE CONTROL REGISTER (RMCR) 



7 


6 


5 


4 


3 


2 


1 


0 




X 


X 


X 


X 


CC1 


ceo 


SS1 


sso 


$0010 



Bit 1 : Bit 0 SS1.SS0 Speed Select. These two 

bits select the baud rate when using 
the internal clock. Four rates may be 
selected which are a function of the 
MCU input frequency. Table 6 lists bit 



time and rates for three selected MCU 
frequencies. 

Bit 3:Bit 2 CC1.CC0 Clock Control and Format 

Select. These two bits control the for- 
mat and select the serial clock source. 
If CC1 is set, the DDR value for P22 is 
forced to the complement of CCO and 
cannot be altered until CC1 is cleared. 
If CC1 is cleared after having been set, 
its DDR value is unchanged. Table 7 
defines the formats, clock source, and 
use of P22. 

If both CC1 and CCO are set, an external TTL-compatible 
clock must be connected to P22 at eight times (8X) the 
desired bit rate, but not greater than E, with a duty cycle of 
50% (±10%). -If CC1:CC0=10, the internal bit rate clock is 
provided at P22 regardless of the values for TE or RE. 

NOTE: The source of SCI internal bit rate clock is the timer 
free-running counter. An MPU write to the counter 
can disturb serial operations. 



FIGURE 23 - SCI REGISTERS 

Bit 7 Rate and Mode Control Register BitO 





CC1 


CCO 


SS1 


SSO 


Transmit/ Receive Control and Status Register 


RDRF 


ORFE 


TDRE 


RIE 


RE . 


TIE 


TE 


WU 



Receive Data Register 



Rx 
Bit 
3 



i 



$12 



(Not Addressable) 



Receive Shift Register 



Clock 
Bit 
2 



Bit Rate 
Generator 



(Not Addressable) 



Transmit Shift Register 



Tx 
Bit 


12 4 


4 




I 



Transmit Data Register 



MOTOROLA MICROPROCESSOR DATA 
3-115 



MC6801/6803 



Transmit/ Receive Control And Status Register 
(TRCSR) ($11) 

The transmit/ receive control and status register controls 
the transmitter, receiver, wake-up feature, and two in- 
dividual interrupts and monitors the status of serial opera- 
tions. All eight bits are readable while bits 0 to 4 are also 
writable. The register is initialized to $20 by RESET. 

TRANSMIT/ RECEIVE CONTROL AND STATUS 
REGISTER (TRCSR) 



7 


6 


5 


, 4 


3 


2 


1 


0 




RDRF 


ORFE 


TDRE 


RIE 


RE 


TIE 


TE 


wu 


$0 ° 11 Bit 6 ORFE 



BitO WU 



Bit 1 TE 



Bit 2 TIE 



Bit 3 RE 



Bit 4 RIE 



"Wake-up" on Idle Line. When set, 
WU enables the wake-up function; 
it is cleared by eleven consecutive 
ones or during reset. WU will not 
set if the line is idle. 

Transmit Enable. When set, P24 DDR 
bit is set, cannot be changed, and will 
remain set if TE is subsequently 
cleared. When TE is changed from 
clear to set, the transmitter is con- 
nected to P24 and a preamble of nine 
consecutive ones is transmitted. TE is 
cleared during reset. 
Tra nsmit Interrupt Enable. When set, 
an IRQ2 interrupt is enabled when 
TDRE is set; when clear, the interrupt 
is inhibited. TE is cleared during reset. 
Receive Enable. When set, the P23 
DDR bit is cleared, cannot be chang- 
ed, and will remain clear if RE is subse- 
quently cleared. While RE is set, the 
SCI receiver is enabled. RE is cleared 
during reset. 

Rec eiver Interrupt Enable. When set, 
an IRQ2 interrupt is enabled when 



RDRF and/or ORFE is set; when clear, 
the interrupt is inhibited. RIE is cleared 
during reset. 

Bit 5 TDRE Transmit Data Register Empty. TDRE 

is set when the transmit data register is 
transferred to the output serial shift 
register or during reset. It is cleared by . 
reading the TRCSR (with TDRE set) 
and then writing to the transmit data 
register. Additional data will be 
transmitted only if TDRE has been 
cleared. 

Overrun Framing Error. If set, ORFE in- 
dicates either an overrun or framing er- 
ror. An overrun is a new byte ready to 
transfer to the receiver data register 
with RDRF still set. A receiver framing 
error has occurred when the byte 
boundaries of the bit stream are not 
synchronized to the bit counter. An 
overrun can be distinguished from a 
framing error by the state of RDRF: if 
RDRF is set, then an overrun has oc- 
curred; otherwise a framing error has 
been detected. Data is not transferred 
to the receive data register in an over- 
run condition. Unframed data causing 
a framing error is transferred to the 
receive data register. However, subse- 
quent data transfer is blocked until the 
framing error flag is cleared.* ORFE is 
cleared by reading the TRCSR (with 
ORFE set) then the receive data 
register, or during reset. 
Bit 7 RDRF Receive Data Register Full. RDRF is 

set when the input serial shift register 
is transferred to the receive data 
register. It is cleared by reading the 
TRCSR (with RDRF set), and then the 
receive data register, or during reset. 



TABLE 6 - SCI BIT TIMES AND RATES 



SS1:SS0 


4fo^ 


2.4676 MHz 


4.0 MHz 


4.9152 MHz 


E 


614.4 kHz 


1 .0 MHz 


1.2288 MHz 


0 


0 


+ 16 


26 /.s/38,400 Baud 


16 /is/62,500 Baud 


13.0ps/76,800 Baud 


0 


1 


+ 128 


208 ps/4,800 Baud 


128^/7812.5 Baud 


104.2 ^s/9,600 Baud 


1 


0 


+ 1024 


1 .67 ms/600 Baud 


1.024 ms/976.6 Baud 


833.3 ps/ 1,200 Baud 


1 


1 


+ 4096 


6.67 ms/150 Baud 


4.096 ms/244.1 Baud 


3.33 ms/300 Baud 


* External (P22) 


13.0^s/76,800 Baud 


8.0 us/ 125,000 Baud 


6.5^s/153,600 Baud 



•Using maximum clock rate 



TABLE 7 - SCI FORMAT AND CLOCK SOURCE CONTROL 



CC1:CCQ 


Format 


Clock 
Source 


Port 2 
Bit 2 


00 


Bi-Phase 


Internal 


Not Used 


01 


NRZ 


Internal 


Not Used 


10 


NRZ 


Internal 


Output 


11 


NRZ 


External 


Input 



* Devices made with mask number M5G, M8D, and T5P do not transfer unframed data to the receive data register. 



MOTOROLA MICROPROCESSOR DATA 
3-116 



MC6801/6803 



SERIAL OPERATIONS 

The SCI is initialized by writing control bytes first to the 
rate and mode control register and then to the transmit/ 
receive control and status register. When TE is set, the out- 
put of the transmit serial shift register is connected to P24 
and serial output is initiated by transmitting a 9-bit preamble 
of ones. 

At this point one of two situations exist: 1) if the transmit 
data register is empty (TDRE=1), a continuous string of 
ones will be sent indicating an idle line, or 2) if a byte has 
been written to the transmit-data register (TDRE = 0), it will 
be transferred to the output serial shift register (synchroniz- 
ed with the bit rate clock), TDRE will be set, and transmis- 
sion will begin. 

The start bit (0), eight data bits (beginning with bit 0) and a 
stop bit (1), will be transmitted. If TDRE is still set when the 
next byte transfer should occur, ones will be sent until more 
data is provided. In Bi-phase format, the output toggles at 
the start of each bit and at half-bit time when a one is sent. 
Receive operation is controlled by RE which configures P23 
as an input and enables the receiver. SCI data formats are il- 
lustrated in Figure 24. 

INSTRUCTION SET 

The MC6801/03 is upward source and object code com- 
patible with the MC6800. Execution times of key instructions 
have been reduced and several new instructions have been 
added, including a hardware multiply. A list of new opera- 
tions added to the MC6800 instruction set is shown in Table 
1. 

In addition, two new special opcodes, 4E and 5E, are pro- 
vided for test purposes. These opcodes force the program 
counter to increment like a 16- bit counter, causing address 
lines used in the expanded modes to increment until the 
device is reset. These opcodes have no mnemonics. 

The coding of the first (or only) byte corresponding to an 



executable instruction is sufficient to identify the instruction 
and the addressing mode. The hexadecimal equivalents of 
the binary codes, which result from the translation of the 82 
instructions in all valid modes of addressing, are shown in 
Table 8. There are 220 valid machine codes, 34 unassigned 
codes, and 2 codes reserved for test purposes. 

PROGRAMMING MODEL 

A programming model for the MC6801/03 is shown in 
Figure 10. Accumulator A can be concatenated with ac- 
cumulator B and jointly referred to as accumulator D where 
A is the most-significant byte. Any operation which modifies 
the double accumulator will also modify accumulator A 
and/or B. Other registers are defined as follows: 

Program Counter — The program counter is a 16-bit 
register which always points to the next instruction. 

Stack Pointer — The stack pointer is a 16-bit register 
which contains the address of the next available location in a 
pushdown/pullup (LIFO) queue. The stack resides in ran- 
dom access memory at a location defined by the program- 
mer. 

Index Register — The index register is a 16-bit register 
which can be used to store data or provide an address for the 
indexed mode of addressing. 

Accumulators - The M PL) contains two 8-bit accumu- 
lators, A and B, which are used to store operands and results 
from the arithmetic logic unit (ALU). They can also be con- 
catenated and referred to as the D (double) accumulator. 

Condition Code Registers - The condition code register 
indicates the results of an instruction and includes the 
following five condition bits: negative (N), zero (Z), overflow 
(V), carry/borrow from MSB (C), and half carry from bit 3 
(H). These bits are testable by the conditional branch in- 
structions. Bit 4 is the interrupt mask (I bit) and inhibits all 
maskable interrupts when set. The two unused bits, B6 and 
B7, are read as ones. 




FIGURE 24 - SCI DATA FORMATS 



Output 
Clock 



NRZ 
Format 



Bi-Phase 
Format 



uinnjinjuwLrm 



i i 
i i 



J~LT 



uinjirwuiJiJif 



Idle Start 



0 1 



Stop 



Data: 01001101 ($4D) 



MOTOROLA MICROPROCESSOR DATA 
3-117 



MC6801/6803 



ADDRESSING MODES 

Six addressing modes can be used to reference mem- 
ory. A summary of addressing modes for all instructions 
is present in Tables 9 through 12, where execution times 
are provided in E cycles. Instruction execution times are 
summarized in Table 13, With an input frequency of 4 
MHz, E cycles are equivalent to microseconds. A cycle- 
by-cycle description of bus activity for each instruction 
is provided in Table 14 and a description of selected 
instructions is shown in Figure 25. 

Immediate Addressing — The operand or "immediate 
byte(sj" is contained in the following byte(s) of the in- 
struction where the number of bytes matches the size 
of the register. These are two or three byte instructions. 

Direct Addressing — The least-significant byte of the 
operand address is contained in the second byte of the 
instruction and the most-significant byte is assumed to 
be $00. Direct addressing allows the user to access $00 
through $FF using two byte instructions and execution 
time is reduced by eliminating the additional memory 
access. In most applications, the 256-byte area is re- 
served for frequently referenced data. 

TABLE 8 - CPU 



Extended Addressing — The second and third bytes 
of the instruction contain the absolute address of the 
operand. These are three byte instructions. 

Indexed Addressing — The unsigned offset contained 
in the second byte of the instruction is added with carry 
to the index register and used to reference memory 
without changing the index register. These are two byte 
instructions. 

Inherent Addressing — The operand(s) are registers 
and no memory reference is required. These are single 
byte instructions. 

Relative Addressing — Relative addressing is used 
only for branch instructions. If the branch condition is 
true, the program counter is overwritten with the sum., 
of a signed single byte displacement in the second byte 
of the instruction and the current program counter. This 
provides a branch range of - 126 to +129 bytes from 
the first byte of the instruction. These are two byte in- 
structions. 



INSTRUCTION MAP 



OP 


MNEM 


MODE 


~ 


I 


OP 


MNEM 


MODE -. # 


OP 


MNEM 


MODE 


- 


* 


OP 


MNEM 


MODE 


- 




OP 


MNEM 


MODE 


~ 


* 


00 


• 










34 


DES , 


INHER 3 1 , 


68 


ASL 


NDXD 


6 


2 


9C 


CPX 


DIR 


5 


2 


DO 


SUBB 


DIR 


3 


2 


01 


NOP 


INHER 


2 


1 


35 


TXS' . 


I 


k 3 1 


69 


ROL 


I 




6 


2 


9D 


JSR 


! 




5 


2 


01 


CMPB 


t 




3 


2 


02 


• 










36 


PSHA 




3 1 


6A 


DEC 






6 


2 


9E 


LDS 






4 


2 


D2 


SBCB 






3 


2 


03 


• 










37 


PSHB 




3 . 1 


6B 


• 










9F 


STS 


DIR 


4 


2 


D3 


ADDD 






5 


2 


04 


LSRD 






3 


. 1 


38 


PULX 




5 1 


6C 


INC 






6 


2 


AO 


SUBA 


INDXD 


4 


2 


D4 


ANDB 






3 


2 


05 


ASLD 






3 


1 


39 


RTS 




5 1 


6D 


TST 






6 


2 


Al 


CMPA 


t 




4 


2 


D5' 


BITB 






3 


2 


06 


TAP 






2 


1 


3A 


ABX 




3 1 


6E 


JMP 


' 


f 


3 


2 


A2 


SBCA 






4 


2 


D6 


LDAB 






3 1 


2 


07 


TPA 






2 


1 


3B 


RTI 




10 1. 


6F 


CLR 


INDXD 


6 


2 


A3 


SUBD 






6 


2 


D7 


STAB 






3 


2 


08 


INX 






3 


1 


3C 


PSHX 




4 1 


70 


NEG 


EXTND 


6 


3 


A4 


ANDA 






4 


2 


D8 


EORB 






3 


2 


09 


DEX 






3 


1 ' 


3D 


MUL 




10 ' 1 


71 


• 


I 








A5 


BITA 






4 


2 


D9 


ADCB 






3 


2 


OA 


CLV 






2 


1 


3E 


WAI 




9 1 


72 


• 










A6 


LDAA 






4 


2 


DA 


ORAB 






3 


2 


OB 


SEV 






2 


1 


3F 


SWI 




12 1 


73 


COM 






6 


3 


A7 


STAA 






4 


2 


DB 


ADDB 






3 


2 


OC 


CLC 






2 


1 


40 


NEGA 




2 1 


74 


LSR 






6 


3 


A8 


EORA 






4 


2 


DC 


LDD 






4 


2 


OD 


SEC 






2 


1 


41 


• 






75 


• 










A9 


ADCA 






4 


2 


DD 


STD 






4 


2 


OE 


CLI 






2 


1 


42 








76 


ROR 






6 


3 


AA 


■ ORAA 






4 


2 


DE 


LDX 


1 




4 


2 




SEI 






2 




43 


COMA 




2 1 




ASR 






6 


3 


AB 


ADDA 






4 


2 


C5 F 


STX 


DIR 


4 


2 


10 


SBA 






2 


1 


44 


LSRA 




2 1 


78 


ASL 






6 


3 


AC 


CPX 






6 


2 


E0 


SUBB 


INDXD 


4 


2 


11 


CBA 






2 


1 


45 








79' 


ROL 






6 


3 


AD 


JSR 






6 


2 


El 


CMPB 


t 




4 


2 


12 












46 


RORA 




2 1 


7A 


DEC 






6 


3 


AE 


LDS ■ 






5 


2 


E2. 


SBCB 






4 


2 


13 












47 


ASRA 




2 1 


7B 












AF 


STS 


INDXD 


5 


2 


E3 


ADDD 






6 


2 


14 












48 


ASLA 




2 1 


7C 


INC 






6 


3 


B0 


SUBA 


EXTND 


4 


3 


E4 


ANDB 






4 


2 


15 












49 


ROLA 




2 1 


7D 


TST 






6 


3 


81 


CMPA 


1 


k 


4 


3 


E5 


BITB 






4 


2 


16 


TAB 






2 


1 


4A 


DECA 




2 1 


7E 


JMP 






3 


3 


B2 


SBCA 






4 


3 


E6 


LDAB 






4 


2 


17 


TBA 






2 


1 


4B 








7F 


CLR 


EXTND 


6 


3 


B3 


SUBD 






6 


3 


E7 


STA8 








2 


18 






1 






4C 


INCA 




2 1 


80 


SU8A 


IMMED 


2 


2 


B4 


ANDA 






4 


3 


E8 


EORB 






4 


2 


19 


DAA 


INHER 


2 


1 


4D 


TSTA 




2 1 


81 


CMPA 


/ 


I 


2 


2 


B5 


BITA 






4 


3 


E9 


ADCB 






4 


2 


1A 












4E 


T ■ 






82 


SBCA 






2 


2 


B6 


LDAA 






4 


3 


EA 


ORAB 






4 


2 


IB 


ABA 


INHER 


2 


1 


4F 


CLR A 




2 1 


83 


SUBD 






4 : 


3 


B> 


STAA 






4 


3 


EB 


ADDB 






4 


2 


1C 












50 


NEGB 




2 - 1 


84 


ANDA 






■2 


2 


B8 


EORA 






4 


3 


EC 


LDD 






5 


2 


10 
IE 












51 
52 








85 
86 


BITA 
LDAA 






2. 
2 


2 
2 


B9 
8A 


ADCA 
ORAA 






4 

4 


3 
3 


ED 
EE 


STD 
LDX 


* 


r 


5 
5 


2 
2 


IF 












53 


COMB 




2 1 


87 












BB 


ADDA 






4 


3 


EF 


STX 


INDXD 


5 


2 


20 


BRA 


REL 


3 


2 


54 


LSRB 




2 1 


88 


EORA 






.2' 


2 


BC 


CPX 






6 


3 


F0 


SUBB 


EXTND 


4 


3 


21 


BRN 


t 


{ 


3 


2 


55 








89 


ADCA 






2 


2 


BD 


JSR 






6 


3 


Fl 


CMPB 


t 




4 


3 


22 


BHI 






3 


2 


56 


RORB 




2 1 


8A 


ORAA 






2 


2 


BE 


LDS 


< 




5 


3 


F2 


SBCB 






4 


3 


23 


BLS 






3 


2 


57 


ASRB 




2 1 


8B 


ADDA 


) 


t 


2 


2 


BF 


STS 


EXTND 


5 


3 


F3 


ADDD 






6 


3 


24 


see 






3 


2 


58 


ASLB 




2 1 


8C 


CPX 


MMED 


4. 


3 


CO 


SU88 


IMMED 


2 


2 


F4 


ANDB 






4 


3 


25 


BCS 






3 


2 


59 


ROLB 




2 1 


8D 


BSR 


REL 


6 


2 


CI 


CMPB 


t 




2 


2 


F5 


BITB 






4 


3 


26 


BNE 






3 


2 


5A 


DECB 




2 ; 1 


at 


IDS 


IMMED 


3 


3 


C2 


SBC8 






2 


2 


F6 


LDAB 






4 


3 


27 


BEO 






3 


2 


5B , 








8F 












C3 


ADDD 






4 


3 


F7 


STAB 






4 


3 


28 


BVC 






3 


2 


5C 


INCB 




2 1 


90 


SUBA 


DIR 




3 


2 


C4 


ANOB 






2 


2 


F8 


EORB 






4 


3 


29 


BVS 






3 


2 


5D 


TSTB 




2 1 ■ 


91 


CMPA 


■ t 


i - 


3 


2 


C5 


BITB 






2 


2 


F9 


ADCB 






4 


3 


2A 


BPL 






3 


2 


5E 


T 


\ 


t 


92 


SBCA 






3 


2 


C6 


LDAB 






2 


2 


FA 


ORAB 






4 


3 


2B 


BMI 






3 


2 


5F 


CLRB 


INHER 2 1 


93 


SUBD 






5 


2 


n ' 












FB 


ADDB 






4 


3 


2C 


BGE 






3 


2 


60 


NEG 


INDXO 6 2 


94 


ANDA 






3 


2 


C8 


EORB 






2 


2 


FC 


LDD 






5 


3 


2D 


BLT 






3 


2 


61 




i 




95 


BITA 






3 


2 


C9 


ADCB 






2 


2 


FD 


STD 






5 


3 


2E 


BGT 


1 




3 


2 


62 








96 


LDAA 






3 


2 


CA 


ORAB 






2 


■ 2 


FE 


LDX 






5 


3 


2F 


BLE 


REL 


3 


2 


63 


COM 




6 2 


97 


STAA 






3 


2 


CB 


ADDB 






2 


2 


FF 


STX 


EXTND 


5 


3 


30 


TSX 


INHER 


3 


1 


64 


LSR 




6 2 


98 


EORA 






3 


2 


CC 


LDD 






3 


3 














31 


INS 






3 


1 


65 








99 


ADCA 






3 


2 


CD 




1 










* UNDEFINED OP CODE 




32 


PULA 


\ 






1 


66 


ROR 


> 


1 6 2 


9A 


ORAA 






3 


2 


CE 


LDX 


IMMED 


3 


3 














33 


PULB 






4 


1 


67 


ASR 


INDXD 6 2 


9B 


ADDA 


> 




3 


2 


CF 

























1 . Addressing Modes 

INHER ■ Inherent INDXO ■ Indexed IMMED ■ Immediate 
REL se Relative EXTND = Extended DIRaDirect 

2. Unassigned opcodes are indicated by "•" and should not be executed. 

3. Codes marked by "T" force the PC to function as a 16-bit counter. 



MOTOROLA MICROPROCESSOR DATA 
3-118 



3 



TABLE 9 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS 



Pointer Operations 


MNEM 


Immed 


Direct 


Index 


Extnd 


Inherent 


Boolean/ 
Arithmetic Operation 


Condition Codes 


5 


4 


3 


2 


1 


0 


Op 




» 


Op 




» 


Op 


- 


t 


Op 


- 


» 


Op 


~ 


* 


H 


1 


N 


Z 


V 


C 


Compare Index Register 


CPX 


8C 


4 


3 


9C 


5 


2 


AC 


6 


2 


BC 


6 


3 








X- M:M + 1 


• 


• 


J 


t 


t 


t 


Decrement Index Register 


DEX 


























09 


3 


1 


X- 1 — -X 


• 


• 


• 




• 


• 


Decrement Stack Pointer 


DES 


























34 


3 


1 


SP- 1 — sp 


• 


• 


• 


• 


• 


• 


Increment Index Register 


INX 


























08 


3 


1 


X + 1 — ► X 














Increment Stack Pointer 


INS 


























31 


3 


1 


1 SP+ 1 - *S'P 














Load Index Register 


LDX 


CE 


3 


3 


DE 


4 


2 


EE 


5 


2 


FE 


5 


3 








M — X H ,(M + D — X[_ 


* 


• 


t 


| 


R 




Load Stack Pointer 


LDS 


8E 


3 


3 


9E 


4 


2 


AE 


5 


2 


BE 


5 


3 








M — SP H ,(M+ 1).— SP L 






i 




R 




Store Index Register 


STX 








DF 


4 


2 


EF 


5 


2 


FF 


5 


3 








X H — M,X L — MM + 1) 






i 




R 




Store Stack Pointer 


STS 








9F 


4 


2 


AF 


5 


2 


BF 


5 


3 








SP H — M,SP|_— '(M + 1) 






t 




R 




Index Reg— » Stack Pointer 


TXS 


























35 


3 


■ 1 


X- 1 —SP 














Stack Pntr — Index Register 


TSX 


























30 


3 


1 


S P + 1 :~* X 














Add 


ABX 


























3A 


3 


1 


B + x — X 














Push Data 


PSHX 


























3C 


4 


1 


X L — M SP ,SP- 1 — SP 
X H — M SP ,SP-1— SP 














Pull Data 


PULX 


























38 


5 


1 


SP+ 1 — SP,M SP — X H 
SP+ 1 — SP,M SP — X L 















TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2) 



Accumulator and 
Memory Operations 


MNEM 


Immed 


Direct 


Index 


Extend 


Inher 


Boolean 
Expression 


Condition Codes 


5 


4 


3 


2 


1 


0 


Op 




* 


Op 




t 


Op 




0 


Op 




» 


Op 




* 


H 


I 


N 


Z 


V 


C 


Add Accumulators 


ABA 


























IB 


2 


1 


A+B — A 


t 




J 




i 


J 


Add B to X 


ABX 


























3A 


3 


1 


00 B + X— *X 














Add with Carry 


ADCA 


89 


2 


2 


99 


3 


2 


A9 


4 


2 


B9 


4 


3 








A,M + C- A 


i 




i 




t 


i 


ADCB 


C9 


2 


2 


D9 


3 


2 


E9 


4 


2 


F9 


4 


3 








B+M + C — B 


i 




J 




t 


t 


Add 


ADDA 


8B 


2 


2 


9B 


3 


2 


AB 


4 


2 


BB 


4 


3 








A+.M— 'A 


t 




t 




t 


t 


ADDB 


CB 


2 


2 


DB 


3 


2 


EB 


4 


2 


FB 


4 


3 








B+ M — A 


t 




i 




t 


J 


Add Double 


ADDD 


C3 


4 


3 


D3 


5 


2 


E3 


6 


2 


F3 


6 


3 








D + M M t 1 — D 






t 




1 


t 


And 


ANDA 


84 


2 


2 


94 


3 


2 


A4 


4 


2 


B4 


4 


3 








A.M — A 






1 




R 




ANDB 


C4 


2 


2 


D4 


3 


2 


E4 


4 


2 


F4 


4 


3 








B-M — B 






J 




R 




Shift Left, Arithmetic 


ASL, 














68 


6 


2 


78 


6 


3 














t 




t 


t 


AS LA 


























48 


2 


1 


MHIIMIMI- 






t 




i 


i 


ASLB 


























58 


2 


1 


b7 bO 






t 




i 


J 


Shift Left. Double 


ASLD 


























05 


3 


1 








J 




i 


1 


Shift Right, Arithmetic 


ASR 














67 


6 


2 


77 


6 


3 














t 




J 


t 


ASRA 


























47 


2 


1 


Q\ 1 1 1 1 1 1 hM 






t 




t 


t 


ASRB 


























57 


2 


1 


b7 bO 






t 




t 


t 


Bit Test 


BITA 


85 


2 


2 


95 


3 


2 


A5 


4 


2 


B5 


4 


3 








A-M 






1 




R 




BITB 


C5 


2 


2 


D5 


3 


2 


E5 


4 


2 


F5 


4 


3 








B-M 






t 




R 




Compare Accumulators 


CBA 


























11 


2 


1 


A- B , . 






J 




t 


J 


Clear 


CLR 














6F 


6 


2 


7F 


6 


3 








00 — M 






R 


s 


R 


R 


CLRA 


























4F 


2 


1 


00 — A 






R 


s 


R 


R 


CLRB 


























5F 


2 


.1 


00 — B 






R 


s 


R 


R 


Compare 


CMPA 


81 


2 


2 


91 


3 


2 


A1 


4 


2 


B1 


4 


3 








A-M 






J 


J 


J 


J 


CMPB 


CI 


2 


2 


Dl 


3 


2 


E1 


4 


2 


F1 


4 


3 








B-M 






t 


t 


t 


t 


Vs Complement 


COM 














63 


6 


2 


73 


6 


3 








M — M 






i 


i 


R 


S 


COMA 


























43 


2 


1 


A — A 






t 


t 


R 


S 


COMB 


























53 


2 


1 


B — B 






t 


t 


R 


s 



MOTOROLA MICROPROCESSOR DATA 
3-119 



MC6801/6803 



TABLE 11 - JUMP AND BRANCH INSTRUCTIONS 



Operations 



Op - 



Op 



Op 



Op - 



Op - 



Condition Code Reg. 



H I N Z V C 



3 2 10 



Branch Always 



Branch Never 



Branch If Carry Clear 



Branch If Carry Set 



Branch If = Zero 



B ranch If a Zero 



Branch if >Zero 



Z + (N © V) = 0 



Branch If Higher 



Branch If Higher or Same 



Branch If sZero 



Z + (N © V)=1 



Branch If Carry Set 



Branch If Lower Or Same 



Branch If <Zero 



Branch If Minus 



Branch If Not Equal Zero 



Branch If Overflow Clear 



Branch If Overflow Set 



Branch To Subroutine 



Jump 



Jump To Subroutine 



See Special Operations-Figure 25 



No Operation 



Return From Interrupt 



Return From Subroutine 



Software Interrupt 



Wait For Interrupt 



RTS 



See Special Operations-Figure 25 



TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS 



Operations 


Inherent 


Boolean Operation 


Condition Code Register 


5 


4 


3 


2 


1 


0 


MNEM 


Op 




« 


H 


I 


N 


Z 


V 


c 


Clear Carry 


CLC 


oc 


2 




0 — C 


• 


• 




• 


• 


R 


Clear Interrupt Mask 


CLI 


0E 


2 




0— I 


• 


R 




• 


• 


• 


Clear Overflow 


CLV 


OA 


2 




0 — V 


• 


• 




- • 


R 


• 


Set Carry 


SEC 


0D 


2 




1 — c 












s 


Set Interrupt Mask 


SEI 


OF 


2 




1 — 1 


• 


S 




• 


• 


• 


Set Overflow 


SEV 


OB 


2 




1— V 


• 






• 


S 


• 


Accumulator A— *CCR 


TAP 


06 


2 




A — CCR 


t 


t 


t 


t 


t 


t 


CCR— 'Accumulator A 


TPA 


07 


2 




CCR — A 















LEGEND 

Op Operation Code (Hexadecimal) 
- Number of MPU Cycles 

Contents of memory location pointed to by Stack Pointer 
Number of Program Bytes 
Arithmetic Plus 
Arithmetic Minus 
Boolean AND 
Arithmetic Multiply 
Boolean Inclusive OR 
Boolean Exclusive OR 
Complement of M 
Transfer Into 
Bit = Zero 



Msp 
I 



M 



CONDITION CODE SYMBOLS 

H Half-carry from bit 3 

I Interrupt mask 

N Negative (sign bit) 

Z Zero (byte) 

V Overflow, 2's complement 

C Carry/ Borrow from MSB 

R Reset Always 

S Set Always 

t Affected 

• Not Affected 



00 Byte = Zero 



MOTOROLA MICROPROCESSOR DATA 
3-121 



MC6801/6803 



TABLE 13 - INSTRUCTION EXECUTION TIMES IN E CYCLES 



ADDRESSING MODE 





Immediate 


Direct 


Extended 


Indexed 


Inherent 


Relative 


ABA 


_' 


a) 


a) 


_ 


2 




ABX 


# 


0 ■ 






3 


_ . 


ADC 




3 


4 


4 


• 




ADD 




3 


4 


4 


0 


_ 


ADDD 


4 


5 


6 




# 




AND 




3 






0 


# 


ASL 










2 


# 


ASLD 


— _— 

■ 


• — 


— =- 


— | 


3 


_- — 

■ 


ASR 




# 






2 




BCC 












3 


BCS 






■ # 




0 


3 


BEQ 












3 


BGE 




_ 




_ 




3 


BGT 










0 


3 


BHI 


j 


j — 


— ' 


^ 


0 


3 


BHS 










0 


3 


BIT 














BLE 










0 


3 


BLO 










0 


3 


BLS 










0 


3 


BLT 


- 








0 ' 


3 


BMI 


^ 


— 


— 


^ 


■ 0 


3 


BNE 










0 


3 


BPL 










0 


3 


BRA . . 










0 


3 


BRN 










0 


3 


BSR 










0 


g 


BVC 










0 


3 


BVS 




— a — ! 


i — j — 1 




0 


3 


CBA 










2 




CLC 










2 




CLI 










2 




CLR 








6 


2 




CLV 








• 


2 




CMP 








4 


• 




COM 








6 


2 




CPX 








6 


• 




DAA 








• 


2 




DEC 








6 


2 




DES 








• 


3 




DEX 








• 


3 




EOR 








4 


• 




INC 






6 


6 


• 




INS 






• 


• 


3 





ADDRESSING MODE 





Immediate 


u 


mded 


ixed 


(rent 


Relative 




£ 

5 


u5 


■o 
_c 


C 


INX 


0 


• 


0 


0 


3 


0 


JMP 


• 


• 


3 


3 


0 


0 


JSR 


0 




6 


6 


■ 


. 0 


LDA 


2 




4 


4 


0 


0' 


LDD 


3 


4 


5 


5 


0 


0 


LDS 


3 


4 


5 


5 


0 


0 


LDX 


3 


4 


5 


5 


0 


0 


LSL 




• 


6 


6 


2 


0 


LSLD 




• 


' 0 


• 


3 


0 


LSR 




• 


6 


6 


2 


0 


LSRD 




• 


0 


0 


3 


0 


MUL 


0 


0 


0 


0 


10 


0 


NEG 




• 






2 


, 0 


NOP 




• 


0 


0 


2 


' 0 


ORA 






4 


4 


0 


0 


PSH 


0 


• 


0 


0 


3 


0 


PSHX 






0 


0 . 


4 


• 


PUL 




• ■ 


0 


0 


4 


0 


PULX 


0 


• 


0 


0 


5 


• .0 " 


ROL 




• 






2 


0 


ROR 




• 






2 


0 


RTI 


0 


• 


0 


0 


10 


0 


RTS 


# 


• 


0 


0 


5 


0 


SBA 


0 


• 


0 


0 


2 


0 ' 


SBC 






4 


4 


• 


# 


SEC 


# 


• 


0 


0 


2 




SEI 


0 


• 


0 


0 


2 


0 


SEV 






0 


0 


2 


* 


STA 


1— 




4 


4 


0 




STD 




4 


5 


5 


: 




STS 




4 


5 


5 






STX 




4 


5 


5 






SUB 






4 


4 






SUBD 






6 


6 






SWI 










12 




TAB 










2 




TAP 










2 




TBA 










2 




TPA 










2 




TST 










2 




TSX 










3 




TXS 










3 




WAI 










9 





MOTOROLA MICROPROCESSOR DATA 
3-122 



MC6801/6803 



SUMMARY OF CYCLE- 

Table 14 provides a detailed description of the information 
present on the address bus, data bus, and the read/write 
(R/W) line during each cycle of each instruction. 

The information is useful in comparing actual with ex- 
pected results during debug of both software and hardware 
as the program is executed. The information is categorized in 
groups according to addressing mode and number of cycles 



BY-CYCLE OPERATION 

per instruction. In general, instructions with the same ad- 
dressing mode and number of cycles execute in the same 
manner. Exceptions are indicated in the table. 

Note that during MPU reads of internal locations, the 
resultant value will not appear on the external data bus ex- 
cept in mode 0. "High order" byte refers to the most- 
significant byte of a 16-bit value. 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5) 



Address Mode and 
Instructions 


Cycles 


Cycle 
* 


Address Bus 


R/W 
Line 


Data Bus 


IMMEDIATE 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


2 


1 
2 


Opcode Address 
Opcode Address + 1 


1 
1 


Opcode 
Operand Data 


LDS 
LDX 
LDD 


3 


1 

2. 
3 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 


1 
1 
1 


Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


CPX 

SUBD 

ADDD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Opcode Address +2 
Address Bus FFFF 


1 
1 
1 
1 


Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


DIRECT 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


3 


1 
2 
3 


Opcode Address 
Opcode Address + 1 
Address of Operand 


1 
1 
1 


Opcode 

Address of Operand 
Operand Data 


STA 


3 


1 

2 
3 


Opcode Address 
Opcode Address + 1 
Destination Address 


1 
1 

0 


Opcode 

Destination Address 
Data from Accumulator 


LDS 
LDX 
LDD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Address of Operand 
Operand Address + 1 


1 
1 
1 
1 


Opcode 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 


STS 
STX 
STD 


4 


1 

2 
3 
4 


Opcode Address 
Opcode Address + 1 
Address of Operand 
Address of Operand + 1 


1 
1 
0 
0 


Opcode 

Address of Operand 

Register Data (High Order Byte) 

Register Data (Low Order Byte) 


CPX 

SUBD 

ADDD 


5 


1 

2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Operand Address 
Operand Address + 1 
Address Bus FFFF 


1 
1 
1 
1 
1 


Opcode 

Address of Operand 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


JSR 


5 


1 
2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Subroutine Address 
Stack Pointer 
Stack Pointer- 1 


1 
1 
1 

0 
0 


Opcode 

Irrelevant Data 

First Subroutine Opcode 

Return Address (Low Order Byte) 

Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 

3-123 



MC6801/6803 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5) 



Address Mode and 
Instructions 


Cycles 


Cycle 
» 


Address Bus 


R/W 
Line 


Data Bus 


EXTENDED 


JMP 


3 


1 

2 
3 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 




Opcode 

Jump Address (High Order Byte) 
Jump Address (Low Order Byte) 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


4 


1 

2 
3 
4 


Opcode Address 
Opcode Address + 1 
Opcode Address+2 
Address of Operand 


; 


Opcode 

Address of Operand 

Address of Operand (Low Order Byte) 

Operand Data 


STA 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 
Operand Destination Address 


; 


Opcode 

Destination Address (High Order Byte) 
Destination Address (Low Order Byte) 
Data from Accumulator 


LDS 
LDX 
LDD 


5 


1 
2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 
Address of Operand 
Address of Operand + 1 


] 


Opcode 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


STS 
STX 
STD 


5 


1 

2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 
Address of Operand 
Address of Operand + 1 


J 


Opcode 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


ASL LSR 
ASR NEG 
CLR ROL 
COM ROR 
DEC TST* 
INC 


6 


1 
2 
3 
4 
5 
6 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 
Address of Operand 
Address Bus FFFF 
Address of Operand 


J 


Opcode 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Current Operand Data 
Low Byte of Restart Vector 
New Operand Data 


CPX 

SUBD 

ADDD 


6 


1 
2 
3 
4 
5 
6 


Opcode Address 
Opcode Address + 1 
Opcode Address+2 
Operand Address 
Operand Address + 1 
Address Bus FFFF 




Opcode 

Operand Address (High Order Byte) 
Operand Address (Low Order Byte) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


JSR 


6 


1 

2 
. 3 
4 
5 
6 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 
Subroutine Starting Address 
Stack Pointer 
Stack Pointer- 1 


0 
0 


Opcode 

Address of Subroutine (High Order Byte) 
Address of Subroutine (Low Order Byte) 
Opcode of Next Instruction 
Return Address (Low Order Byte) 
Return Address (High Order Byte) 



*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus=$FFFF: 



MOTOROLA MICROPROCESSOR DATA 
3-124 



MC6801/6803 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 


INDEXED 


JMP 


3 


1 


Opcode Address 




Opcode . 






2 


Opcode Address + 1 




Offset 






3 


Address Bus FFFF 




Low Byte of Restart Vector 


ADC EOR 


4 




~0 d Addr ss 


— 1 — 


Q p Code : 


ADD LDA 




2 


Opcode Address +1 




Offset 


AND ORA 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


DM JDL 




4 


Index Register Plus Offset 




Operand Data 


CMP SUB 












STA 


4 




— 

Upcooe Aooress 


— ■ — 


— — 

upcode 






2 






Offset ■ ■ • 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data 


LDS 


5 


1 


Opcode Address 


— — 




LDX 




2 


Opcode Address 4" 1 






LDD 




3 


AHHra<;Q Rii«s FFFF 
nuu'coo duo rrrr 




Low Byte o* nestart vector 






4 


Index Register Plus Offset 




OnpranH Data 1 Winh TVHor Rvtpl 






5 






Operand Data { Low Order Byte) 


STS 


g 


1 


Opcode Address 


— — 


Opcode 


STX 




2 


Opcode Address + 1 




Offset 


STD 




3 


nuuic^o duo rrrr 




Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data (High Order Byte) 






5 


InHoy Ronictor Pliic Of f Qot 4- 1 




Operand Data (Low Order Byte) . ; 


ASL LSR 


6 


1 


Opcode Address 




Opcode 


ACQ MFfS 
Hon INCVJ 




2 


Opcode Address + 1 




Offset 


n r roi 

^Ln nUL 




3 


Address Bus FFFF 




Low Byte of Restart Vector 


pom dhd 




4 


InHoy Ronictor Pli ic Offset 




Current Operand Data 






g 


AHHracc Rtic FFFF 
MUUlcob Duo rrrr 




Low Byte of Restart Vector 


INC 




g 


Index Register Plus Offset 




New Operand Data 


CPX 


6 


1 


Opcode Address 




Opcode 


SUBD 




2 


Opcode Address + 1 




Offset 


ADDD 




3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Index Register + Offset 




Operand Data (High Order Byte) 






5 


Index Register+0ffset+1 




Operand Data (Low Order Byte) 






6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 


6 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Offset 






3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Index Register + Offset 




First Subroutine Opcode 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 




*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF. 



MOTOROLA MICROPROCESSOR DATA 
3-125 



MC6801/6803 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


« 


Address Bus 


Line 


Data Bus 



INHERENT 



ABA 


DAA 


SEC 


ASL 


DEC 


SEI 


ASR 


INC 


SEV 


CBA 


LSR 


TAB 


CLC 


NEG 


TAP 


CLI 


NOP 


TBA 


CLR 


ROL 


TPA 


CIV 


ROR 


TST 


COM 


SBA 




ABX 



Opcode Address 
Opcode Address + 1 



Opcode 

Opcode of Next Instruction 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Irrelevant Data 

Low Byte of Restart Vector 



ASLD 
LSRD 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Irrelevant Data 

Low Byte of Restart Vector 



DES 
INS 



Opcode Address 
Opcode Address + 1 
Previous Stack Pointer Contents 



Opcode 

Opcode of Next Instruction 
Irrelevant Data 



INX 
DEX 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Opcode of Next Instruction 
Low Byte of Restart Vector 



PSHA 
PSHB 



Opcode Address 
Opcode Address + 1 
Stack Pointer 



Opcode 

Opcode of Next Instruction 
Accumulator Data 



TSX 



Opcode Address 
Opcode Address + 1 
Stack Pointer 



Opcode 

Opcode of Next Instruction 
Irrelevant Data 



TXS 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Opcode of Next Instruction 
Low Byte of Restart Vector 



PULA 
PULB 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer + 1 



Opcode 

Opcode of Next Instruction 

Irrelevant Data 

Operand Data from Stack 



PSHX 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer - 1 



Opcode 
Irrelevant Data 

Index Register (Low Order Byte) 
Index Register (High Order Byte) 



PULX 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer + 1 
Stack Pointer + 2 



Opcode 
Irrelevant Data 
Irrelevant Data 

Index Register (High Order Byte) 
Index Register (Low Order Byte) 



RTS 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer + 1 
Stack Pointer + 2 



Opcode 
Irrelevant Data 
Irrelevant Data 

Address of Next Instruction (High Order Byte) 
Address of Next Instruction (Low Order Byte) 



WAI 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer - 1 
Stack Pointer -2 
Stack Pointei-3 
Stack Pointer-4 
Stack Pointer - 5 
Stack Pointer -6 



Opcode 

Opcode of Next Instruction 
Return Address (Low Order Byte) 
Return Address (High Order Byte) 
Index Register (Low Order Byte) 
Index Register (High Order Byte) 
Contents of Accumulator A 
Contents of Accumulator B 
Contents of Condition Code Register 



MOTOROLA MICROPROCESSOR DATA 
3-126 



MC6801/6803 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


» 


Address Bus 


Line 


Data Bus 


INHERENT 


MUL 


10 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ 1 




Irrelevant Data 






3 


Address Bus FFFF 


■\ 


Low Byte of Restart Vector 






4 


Address Bus FFFF 




Low Byte of Restart Vector 






5 


Address Bus FFFF 


! 


Low Byte of Restart Vector 






6 


Address Bus FFFF 




Low Byte of Restart Vector 






7 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






8 


Address Bus FFFF 




Low Byte of Restart Vector 






9 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






10 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


RTI 


10 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 


1 


Irrelevant Data 






3 


Stack Pointer 


1 


Irrelevant Data. 






4 


Stack Pointer + 1 


1 


Contents of Condition Code Register from Stack 






5 


Stack Pointer +2 


1 


Contents of Accumulator B from Stack 






6 


Stack Pointer + 3 


! 


Contents of Accumulator A from Stack 






7 


Stack Pointer +4 


! 


Index Register from Stack (High Order Byte) 






8 


Stack Pointer + 5 




Index Register from Stack (Low Order Byte) 






9 


Stack Pointer + 6 




Next Instruction Address from Stack (High Order Byte) 






10 


Stack Pointer +7 




Next Instruction Address from Stack (Low Order Byte) 


SWI 


12 


1 


Opcode Address 


~T1 


Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






5 


Stack Pointer- 2 


0 


Index Register (Low Order Byte) 






6 


Stack Pointer- 3 


0 


Index Register (High Order Byte) 






7 


Stack Pointer -4 


0 


Contents of Accumulator A 






8 


Stack Pointer -5 


0 


Contents of Accumulator B 






9 


Stack Pointer- 6 


0 


Contents of Condition Code Register 






10 


Stack Pointer- 7 


1 


Irrelevant Data 






11 


Vector Address FFFA (Hex) 


1 


Address of Subroutine (High Order Byte) 






12 


Vector Address FFFB (Hex) 


1 


Address of Subroutine (Low Order Byte) 



RELATIVE 



BCC 


BHT 


BNE' 


BLO 


3 


1 . 


Opcode Address 


1 


Opcode 


BCS 


BLE 


BPL 


BHS 




2 


Opcode Address + 1 


1 


Branch Offset 


BEQ 


BLS 


BRA 


BRN 




3 


Address Buss FFFF 


1 


Low Byte of Restart Vector 


BGE 


BLT 


BVC 














BGT 


BMI 


BVS 














BSR 








6 


1 


Opcode Address 


1 


Opcode 












2 


Opcode Address + 1 


1 


Branch Offset 












3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 












4 


Subroutine Starting Address 


1 


Opcode of Next Instruction 












5 


Stack Pointer 


0 


Return Address (Low Order Byte) 












6 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-127 



CO 



FIGURE 25 - SPECIAL OPERATIONS 



JSR, Jump to Subroutine 



EC 



BSR, Branch To Subroutine 



Main Program 



Next Main Instr. 



K = Direct Address 
Main Program 



Next Main Instr. 



Main Program 



$BD = JSR 



SH = Subr. Addr. 



SL = Subr. Addr. 



Next Main Inst. 



Main Program 



$8D=BSR 



±K = Offset 



Next Main Instr. 



SP- 
SP- 



SP 
SP-2 
SP-1 

SP 



RTN H 



RTN L 



rtn h 



RTN|_ 



RTS, Return from Subroutine 
PC 



SE 

SP 
SP+1 
SP + 2 



RTN H 



RTN L 



Legend: 

RTN= Address of next instruction in Main Program to be executed upon return from subroutine 
RTNh = Most significant byte of Return Address 
RTN[_ = Least significant byte of Return Address 
-♦ = Stack Pointer After Execution 
K = 8-bit Unsigned Value 



SWI, Software Interrupt 



Main Program 



PC 
RTN 



WAI, Wait for Interrupt 



RTN 



RTI, Return from Interrupt 



JMP, Jump 



$3F=SWI 



Main Program 



$3E = WAI 



Interrupt Program 



$3B = RTI 



Main Program 



$6E = JMP 



X + K Next Instruction 



SP 


Stack 


SP-7 




SP-6 


Condition Codo 


SP- 5 


Acmltr B 


SP-4 


Acmltr A 


SP-3 


Index Register (Xh) 


SP — 2 


Index Register (X|_) 




n inn 


SP 


. 


SP 


Stack 


SP 




SP+ 1 


Condition Code 




Acmltr B 


SP + 3 


Acmltr A 


SP + 4 


Index Register (X|-|) 




Index Register IX(_) 


SP + 6 


RTN H 


SP + 7 


RTN L 


PC 


Main Program 


/ 


$7E = JMP 




Kh = Next Address 




<l= Next Address 






K 


Next Instruction | 



MC6801/6803 



ORDERING INFORMATION 



The following information is required when ordering 
a custom MCU. The information may be transmitted to 
Motorola using the following media: 
MDOS, disk file 
PC-DOS disk file (360K) 
EPROM(s) 2516, 2716, MC68701 
To initiate a ROM pattern for the MCU, it is necessary 
to first contact the local field service office, sales person, 
or a Motorola representative. 

FLEXIBLE DISKS 

Several types of flexible disks (MDOS® or PC-DOS 
disk file) may be submitted for pattern generation. They 
should be programmed with the customer's program, 
using positive logic sense for address and data. The 
diskette should be clearly labeled with the customer's 
name, date, project or product name, and the filename 
containing the pattern. 

In addition to the program pattern, a file containing 
the program source code listing can be included. This 
data will be kept confidential and used to expedite the 
process in case of any difficulty with the pattern file. 

MDOS Disk File 

MDOS is Motorola's Disk Operating System available 
on the EXORciser® development system. The disk me- 
dia submitted must be a single-sided, single-density, 8- 
inch MDOS compatible floppy diskette. The diskette must 
contain the minimum set of MDOS system files in ad- 
dition to the pattern file. 

The .LO output of the M6801 cross assembler should 
be furnished. In addition, the file must be produced 
using the ROLLOUT command, so that it contains the 
absolute image of the M6801 memory. It is necessary 
to include the entire memory image of both program 
and data space. All unused bytes, including those in the 
user space, must be set in logic zero. 

PC-DOS Disk File 

PC-DOS is the IBM® Personal Computer Disk Oper- 
ating System. Disk media submitted must be standard 
density (360K), double-sided 5-1/4 inch compatible floppy 
diskette. The diskette must contain the object file code 
in Motorola's S-record format. The S-record format is 
a character-based object file format generated by M6801 
cross assemblers and linkers on IBM PC style machines. 

EPROMS 

A single 2K EPROM is necessary to contain the entire 
MC6801 program. The EPROM is programmed with the 
customer program using positive logic sense for ad- 
dress and data. All unused bytes, including the user's 
space, must be set to zero. 

If the MC6801 MCU ROM pattern is submitted on a 
single 2516 or 2716 type EPROM, memory map ad- 
dressing is one-for-one. The data space ROM runs from 
EPROM address $000 to $7FF. If an MC68701 is used, 
the ROM map runs from $F800 to $FFFF. 

For shipment to Motorola, EPROMs should be placed 
in a conductive IC carrier and packed securely. Styro- 
foam is not acceptable for shipment. 



Verification Media 

All original pattern media, EPROMs or floppy disks, 
are filed for contractual purposes and are not returned. 
A computer listing of the ROM code will be generated 
and returned along with a listing verification form. The 
listing should be thoroughly checked and the verifica- 
tion form completed, signed, and returned to Motorola. 
The signed verification form constitutes the contractual 
agreement for the creation of the customer mask. To 
aid in the verification process, Motorola will program 
customer supplied blank EPROM(s) or DOS disks from 
the data file used to create the custom mask. 

ROM Verification Units (RVUs) 

Ten MCUs containing the customer's ROM pattern 
will be sent for program verification. These units will 
have been made using the custom mask, but are for the 
purpose of ROM verification only. For expediency, the 
MCUs are unmarked, packaged in ceramic, and tested 
with five volts at room temperature. These RVUs are 
free with the minimum order quantity, but are not pro- 
duction parts. These RVUs are not guaranteed by Mo- 
torola Quality Assurance. 

Ordering Information 

The following table provides generic information per- 
taining to the package type and temperature for the 
MC6801/MC6803. This MCU device is available only in 
the 40-pin dual-in-line (DIP) package in the Cerdip and 
Plastic packages. 



MDOS is a trademark of Motorola Inc. 
MS-DOS is a trademark of Microsoft, Inc. 
EXORciser is a registered trademark of Motorola Inc. 
IBM is a registered trademark of International Business 
Machines Corporation. 



GENERIC INFORMATION 



Frequency 


Temperature 


Cerdip Package 


Plastic Package 


(MHz) 


(Degrees C) 


(S Suffix) 


(P Suffix) 


1.0 


Oto 70 


MC6801S1 


MC6801P1 


1.0 


-40 to +85 


MC6801CS1 


MC6801CP1 


1.25 


Oto 70 


MC6801S1-1 


MC6801P1-1 


1.25 


-40 to +85 


MC6801CS-1 


MC6801CP-1 


2.0 


0 to 70 


MC68B01S1 


MC68B01P1 


1.0 


0 to 70 


MC6803S 


MC6803P 


1.0 


-40 to +85 


MC6803CS 


MC6803CP 


1.25 


0 to 70 


MC6803S-1 


MC6803P-1 


1.25 


-40 to +85 


MC6803CS-1 


MC6803CP-1 


2.0 


0 to 70 


MC68B03S 


MC68B03P 



MOTOROLA MICROPROCESSOR DATA 
3-129 



MC6801/6803 



a 



PIN ASSIGNMENT 




21{3 V CC 

Standby 



MOTOROLA MICROPROCESSOR DATA 
3-130 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 



MC6801U4 
MC6803U4 

Advance Information 

Microcontroller/Microprocessor (MCU/MPU) 

The MC6801U4 is an 8-bit single-chip microcontroller unit(MCU) that enhances the capabilities of 
the MC6801 and significantly enhances the capabilities of the M6800 Family of parts. It includes an 
MC6801 microprocessor unit (MPU) with direct object-code compatibility and upward object-code 
compatibility with the MC6800. Execution times of key instructions have been improved over the 
MC6800, and the new instructions found on the MC6801 are included. The MCU can function as a 
monolithic microcontroller or can be expanded to a 64K-byte address space. It is TTL compatible 
and requires one +5-volt power supply. On-chip resources include 4096 bytes of ROM, 192 bytes of 
RAM, a serial communications interface (SCI), parallel I/O, and a 16-bit six-function programmable 
timer. The MC6803U4 can be considered an MC6801 U4 operating in modes 2 or 3; i.e., those that 
do not use internal ROM. 

• Enhanced MC6800 Instruction Set 

• Upward Source and Object Code Compatibility with the MC6800 and MC6801 

• Bus Compatibility with the M6800 Family 

• 8x8 Multiply Instruction 

• Single-Chip or Expanded Operation to 64K-Byte Address Space 

• Internal Clock Generator with Divide-by-Four Output 

• Serial Communications Interface (SCI) 

• 16-Bit Six-Function Programmable Timer 

• Three Output Compare Functions ' 

• Two Input Capture Functions 

• Counter Alternate Address 

• 4096 Bytes of ROM (MC6801U4) 

• 192 Bytes of RAM 

• 32 Bytes of RAM Retainable During Powerdown 

• 29 Parallel I/O and Two Handshake Control Lines ' 

• NlVlT Inhibited Until Stack Load 

• -40°C to 85°C Temperature Range 




This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-131 



CO 



MC6801U4 MICROCOMPUTER FAMILY BLOCK DIAGRAM 



r 



Expanded Multiplexed 
Expanded Non-Multiplexed 
Single Chip 



P37 


A7/D7 


D7 


I/O 




P36 


A6/D6 


D6 


I/O 




P35 


A5/D5 


D5 


I/O 




P34 


A4/D4 


D4 


I/O 




P33 


A3/D3 


D3 


I/O 




P32 


A2/D2 


D2 


I/O 




P31 


A1/D1 


D1 


I/O 




P30 


AO/ DO 


DO 


I/O 




SC2 


R/W 


R/W 


OS3 




SC1 


AS 


IOS 


IS3 





P47 


A15 


A7 


I/O 




P46 


A14 


A6 


I/O 




P45 


A13 


A5 


I/O 




P44 


A12 


A4 


I/O 




P43 


A11 


A3 


I/O 




P42 


A10 


A2 


I/O 




P41 


A9 


A1 


I/O 




P40 


A8 


AO 


I/O 






TIN1 I/O 

TOUT1 I/O 

SCLK I/O 

RDATA I/O 

TDATA I/O 



Vcc Standby ■ 











160x8 
RAM 




4096 x8 
ROM 
(See Note) 




32x8 
Standby 
RAM 





TIN2 I/O 
TOUT2 I/O 
TOUT3 I/O 
I/O 
I/O 
I/O 
I/O 
I/O 



3 

o 

00 

o 
c 

00 

o 

w 

c 



NOTE: No functioning ROM in MC6803U4. 



MC6801U4 MICROCONTROLLER FAMILY BLOCK DIAGRAM 



MC6801U4/6803U4 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


v cc 


-0.3 to +7.0 


V 


Input Voltage 


Vin 


-0.3 to +7.0 


V 


Operating Temperature Range 
MC6801U4, MC6803U4 
MC6801U4C, MC6803U4C 


T A 


TL to T H 
-0to70 
-40 to 85 


°c 


Storage Temperature Range 


Tstg 


-55 to +150 


°c 


THERMAL CHARACTERISTICS 


Characteristic 


Symbol 


Value 


Rating 


Thermal Resistance 
Plastic 
Ceramic 


6ja 


50 
50 


°C/W 



POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj=T A +(P D -e JA ) (D 



where: 




t a 


= Ambient Temperature, °C 


*>ja 


= Package Thermal Resistance, 


Junction-to-Ambient, °C/W 


Pd 


= P|NT +p PORT 


Pint 


= lcC x ^CC' Watts — Chip Internal Power 


p PORT 


= Port Power Dissipation, Watts — User Determined 



For most applications PpoRT^INT anc * can ' 3e neglected. PpoRT may become significant if the device is conf igured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpoRT ' s neglected) is: 

P D = K + (Tj + 273°C) < 2 > 

Solving equations (1) and (2) for K gives: 

K = P D «(T A + 273°C) + ejA'PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at 
equilibrium) for a known T A . Using this value of K, the values of Pq and Tj can be obtained by solving equations 
(1) and (2) iteratively for any value of T A 



CONTROL TIMING (Vcc = 5 0 V±5%, Vss = 0) 



Characteristic 


Symbol 


MC6801U4 
MC6803U4 


MC6801U4-1 
MC6803U4-1 


Unit 


Min 


Max 


Min 


Max 


Frequency of Operation 


fo 


0.5 


1.0 


0.5 


1.25 


MHz 


Crystal Frequency 


f XTAL 


2.0 


4.0 


2.0 


5.0 


MHz 


External Oscillator Frequency 


4f 0 


2.0 


4.0 


2.0 


5.0 


MHz 


Crystal Oscillator Startup Time 


Vc 




100 




100 


ms 


Processor Control Setup Time 


tpcs 


200 




170 




ns 



MOTOROLA MICROPROCESSOR DATA 
3-133 



MC6801U4/6803U4 



DC ELECTRICAL CHARACTERISTICS (Vqc = 5.0 Vdc±5%, Vss = ". Ta = T l to Th, unless otherwise noted) 



a 



Characteristic 


Symbol 


MC6801U4, 
MC6803U4 


MC6801U4C, 
MC6803U4C 


Unit 


Min 


Max. 


Min 


Max 


Input High Voltage RESET 

Other Inputs* 


VlU 


V SS +4.U 

Vss + 2.0 


V CC 
Vcc 


Vss + 4.0 
Vss + 2-2 


V CC 

. . vcc 


V 


Input Low Voltage All Inputs* 


V|L 


Vss-0.3 


Vss + 0.8 


VSS-0.3, 


VsS + 0.8 


V 


Input Load Current Port 4 

SC1 


■in 


-r 


0.5 
0.8 


- 


0.8. 
1.0 


mA 


Input Leakage Current 
(V in = 0to5.5V) NMI, IRQ1, RESET 


'in 


- 


2.5 


- 


5.0 


„A 


Hi-Z (Off-State) Input Current 

(V in = 0.5to2.4V) Portl, Port2, Port 3 


■tsi 


- 


■ 10 


- 


20 


fA 


Output High Voltage 
dLoad= -65>A, V C c=Min) Port 4, SC1, SC2 
(l Load= _ 100 /*A, Vcc=Min) Other Outputs 


VOH 


Vss + 2.4 
Vss + 2.4 


- 


Vss + 2.4 
Vss + 2.4 


- 


V 


Output Low Voltage 
< l Load = 2 0mA, Vcc=Min) All Outputs 


vol 


- 


Vss + 0-5 


- 


Vss + 0.6 


V 


Darlington Drive Current 

(V 0 =1-5V) Portl 


'OH.. 


1 .0 


4.0 


1.0 


5.0 


mA 


Internal Power Dissipation 
(Measured at Ta = Tj_ in Steady-State Operation)* * * 


p INT 




1200 




1500 


mW , 


Input Capacitance 
(V in = 0, T A = 25°C, Port 3, Port 4, SC1 
f o =1.0MHz) Other Inputs 


Qn 




12.5 
10.0 




12.5 
10.0 


PF 


Vcc Standby Powerdown 

Powerup 


VSBB 
V S B 


4.0 
4.75 


5.25 
5.25 


4.0 
4.75 


5.25 
5.25 


V 


Standby Current Powerdown 


ISBB 




3.0 




3.5 


mA 



*Except mode programming levels; see Figure 16. 
**Negotiable to - 100 p.A (for further information contact the factory). . 
»**For the MC6801U4/MC6803U4 T L = 0°C and for the MC6801 U4C/MC6803U4C T L = 40°C. 

PERIPHERAL PORT TIMING (Refer to Figure 1-4) 



Characteristics 


Symbol 


Min 


Typ 


Max 


Unit 


Peripheral Data Setup Time 


tPDSU 


200 ' 






ns 


Peripheral Data Hold Time 


tPDH 


200 






ns 


Delay Time, Enable Positive Transition to OS3 Negative Transition 


'0SD1 






350 


ns 


Delay Time, Enable Positive Transition to 0S3 Positive Transition 


tOSD2 






350 


ns 


Delay Time, Enable Negative Transition to Peripheral Data Valid 
Port 1 

1 Port 2, 3, 4 


'PWD 






350 
350 


ns 


Delay Time, Enable Negative Transition to Peripheral CMOS Data Valid 


'CMOS 






2.0 ' ' 


US 


Input Strobe Pulse Width 


tpwis 


200 






ns 


Input Data Hold Time 


1IH 


50 






ns 


Input Data Setup Time 


'IS 


20 






ns 



MOTOROLA MICROPROCESSOR DATA 
3-134 



MC6801U4/6803U4 



MPU Read 



P10-P17 
P20-P24 
P40-P47 
Inputs* 



P30-P37 
Inputs* 



tPDSU- 



r , 



^ Data Valid ^ 



■'PDH 



tPDSU- 



^ Data Valid ^~~"*^ 



■tPDH 



*Port 3 nonlatched operation (Latch enable = 0) 

Figure 1. Data Setup and Hold Times 
(MPU Read) 



•MPU Write 



\ r 



-tCMOS- 
-tpWD' 



All Data 
Port Outputs 



3— 



vcc 



NOTES: . 
1.10k pullup resistor required for port 2 to reach 0.7 Vcc 

2. Not applicable to P21 

3. Port 4 cannot be pulled above Vcc 



Figure 2. Data Setup and Hold Times 
(MPU Write) 



Address 
Bus 



0S3 



£ 



MPU Access of Port 3* 



($0006) 



X 



tOSD1- 



X 



10302- 



x r 



iS3" 



P30-P37 - ~\ r 
Inputs A 



/ 



— tpwis- 

-t|H- 



Data Valid 



X 




•Access matches output strobe select (OSS = 0, a read; OSS =1, a write) 

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. 



Figure 3. Port 3 Output Strobe Timing 
(MC6801U4 Single-Chip Mode) 



Test Point o- 



30 pF 



Figure 4. Port 3 Latch Timing 
(MC6801U4 Single-Chip Mode) 



vcc 



R L =1.8 kQ 



Test Point c- 



W T MMD6150 
or Equiv 

R * MMD7000 
or Equiv 



C = 90 pF for P30-P37. P40-P47, E, SCI, SC2 

= 30 pF for P10-P17, P20-P24 
R = 37 kO for P40-P47, SC1, SC2 

= 24 kll for P10-P17, P20-P24 

= 24kOfor P30-P37, E 



Figure 5. CMOS Load Figure 6. Timing Test 

Load Ports 1, 2, 3, and 4 



MOTOROLA MICROPROCESSOR DATA 
3-135 



MC6801U4/6803U4 



BUS TIMING (See Notes 1 and 2, and Figure 7) 



Ident. 
Number 


Charactaristics 


Symbol 


MC6801U4 
MC6803U4 


MC6801U4-1 
MC6803U4-1 


Unit 


Min 


Max 


Min 


Max 


1 


Cycle Time 


t 

'eye 


1.0 


2.0 


0.8 


2.0 


uS 


2 


Pulse Width E Low 


PWci 


430 


1000 


360 


1000 




3 


Pulse Width, E High 


' VY tn 


450 


1000 


360 


1000 


ns 


4 


Plriok Ric» anri Fall Timf* 
V'lUi'R- ntoc ai iu run iiiiig 


l r< l t 




25 




25 




g 


Address Hold Time 


'AH 


20 




20 






12 


Nonmuxed Address Valid Time to E* 


'AV 


200 




150 






17 


Read Data Setup Time 


'DSR 


80 




70 






18 


□ Qa H riota Mr*IH Timp 
nodU UtSla nuiu 1 llllc 


'DHR 


10 




10 






19 


\Ayrito l^ata Holaw Timo 
vvnic U'dLa uotay Mine 


'DDW 




225 




200 




21 


Write Data Hold Time 


*DHW 


20 




20 




ns 


22 


Muxed Address Valid Time to E Rise* 


'AVM 


160 




120 




ns 


24 


Muxed Address Valid Time to AS Fall* 


<ASL 


40 




30 




ns 


L 25 


Muxed Address Hold Time 


*AHL 


20 




20 




ns 


26 


Delay Time, E to AS Rise* 


tASD 


200 




170 




. ns 


27 


Pulse Width, AS High* 


pwash 


100 




80 




ns 


28 


Delay Time, AS to E Rise* 


tASED 


90 




70 




ns 


29 


Usable Access Time* (See Note 3) 


tACC 


555 




435 




ns 



•At specified cycle time. 



■^4 



_IOS, 
R/W, Address 
(Nonmuxed) 



Addr/Data 
Muxed 



Addr/Data 
Muxed 



Address 
Strobe (AS) 



0 



See Note 5 



;e>— d 



See Note 4 



X 



29} 



See Note 3 



Read Data Muxed 



Write Data Muxed 



NOTES: 

1. Voltage levels shown are V[ s0.5 V, V(-|^2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. 

3. Usable access time is computed by 22 + 3- 17 + 4. 

4. Memory devices should be enabled only during E high to avoid port 3 bus contention. 

5. Item 26 is different from the MC6801 but it is upward compatible. 



Figure 7. Bus Timing 



MOTOROLA MICROPROCESSOR DATA 
3-136 



MC6801U4/6803U4 



INTRODUCTION 

The MC6801U4 is an 8-bit monolithic microcontroller 
that can be configured to function in a wide variety of 
applications. The facility that provides this extraordinary 
flexibility is its ability to be hardware programmed into 
eight different operating modes. The operating mode 
controls the configuration of 18 of the 40 MCU pins, avail- 
able on-chip resources, memory map, location (internal 
or external) of interrupt vectors, and type of external bus. 
The configuration of the remaining 22 pins is not de- 
pendent on the operating mode. 

Twenty-nine pins are organized as three 8-bit ports and 
one 5-bit port. Each port consists of at least a data register 
and a write-only data direction register. The data direc- 
tion register is used to define whether corresponding bits 
in the data register are configured as an input (clear) or 
output (set). 

The term "port" by itself refers to all of the hardware 
associated with the port. When the port is used as a "data 
port" or "I/O port," it is controlled by the port data di- 
rection register and the programmer has direct access to 
the port pins using the port data register. Port pins are 
labeled as Pij where i identifies one of four ports and j 
indicates the particular bit. 

The MPU is an enhanced MC6800 MPU with additional 
capabilities and greater throughput. It is upward source 
and object-code compatible with the MC6800 and the 
MC6801. The programming model is depicted in Figure 
8 where accumulator D is a concatenation of accumula- 
tors A and B. A list of new operations added to the MC6800 
instruction set are shown in Table 1. 

The MC6803U4 can be considered an MC6801U4 that 
operates in modes 2 and 3 only. 

OPERATING MODES 

The MC6801U4 provides seven different operating 
modes (modes 0 through 3 and 5 through 7), and the 



MC6803U4 provides two operating modes (modes 2 and 
3). The operating modes are hardware selectable and 
determine the device memory map, the configuration of 
port 3, port 4, SC1, SC2, and the physical location of the 
interrupt vectors. 

FUNDAMENTAL MODES 

The seven operating modes (0-3, 5-7) can be grouped 
into three fundamental modes which refer to the type of 
bus it supports: single chip, expanded nonmultiplexed, 
and expanded multiplexed. Single chip is mode 7, ex- 
panded nonmultiplexed is mode 5, and the remaining 5 
are expanded-multiplexed modes. Table 2 summarizes 
the characteristics of the operating modes. 

MC6801U4 Single-Chip Mode (7) 

In the single-chip mode, the four MCU ports are con- 
figured as parallel I/O data ports, as shown in Figure 9. 
The MCU functions as a monolithic microcontroller in this 
mode without external address or data buses. A maxi- 
mum of 29 I/O lines and two port 3 control lines are 
provided. Peripherals or another MCU can be interfaced 
to port 3 in a loosely coupled dual-processor configura- 
tion, as shown in Figure 10. 

MC6801U4 Expanded-Nonmultiplexed Mode (5) 

A modest amount of external memory space is pro- 
vided in the expanded-nonmultiplexed mode while sig- 
nificant on-chip resources are retained. Port 3 functions 
as an 8-bit bidirectional data bus, and port 4 is configured 
initially as an input data port. Any combination of the 
eight least-significant address lines may be obtained by 
writing to the port 4 data direction register. Stated alter- 
natively, and combination of AO to A7 may be provided 
while retaining the remainder as input data lines. Internal 
pullup resistors pull the port 4 lines high until the port is 
configured. 




7 


A 


0| | 7 


B 


0 


15 




D 




0 



8- Bit Accumulators A and B 
Or 16-Bit Double Accumulator D 



Index Register (X) 



15. 


SP 


0 




15 


PC 


°l 




7 


0 



0 Stack Pointer (SP) 



oj Program Counter (PC) 



n|z| V C] Condition Code Register (CCR) 



Carry /Borrow from MSB 
Overflow 
Zero 
Negative 
Interrupt 

Half Carry (From Bit 3) 



Figure 8. Programming Model 



MOTOROLA MICROPROCESSOR DATA 
3-137 



MC6801U4/6803U4 



Table 1. New Instructions 



Instruction 


Description 


ABX 


Unsigned addition of accumulator B to index register 


ADDD 


Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator 


ASLD or LSLD 


Shifts the double accumulator left (towards MSB) one bit, the LSB is cleared, and the MSB is shifted into the C bit 


BHS 


Branch if higher or same, unsigned conditional branch (same as BCC) 


BLQ 


Branch if lower, unsigned conditional branch (same as BCS) 


BRN 


Branch never 


JSR 


Additional addressing mode direct 


LDD 


Loads double accumulator from memory 


LSL 


Shifts memory or accumulator left (towards MSB) one bit, the LSB is cleared, and the MSB is shifted into the C bit 
(same as ASL) 


LSRD 


Shifts the double accumulator right (towards LSB) one bit, the MSB is cleared, and the LSB is shifted into the C bit 


MUL 


Unsigned multiply, multiplies the two accumulators and leaves the product in the double accumulator 


PSHX 


Pushes the index register to stack 


PULX 


Pulls the index register from stack 


STD 


Stores the double accumulator to memory 


SUBD 


Subtracts memory from the double accumulator and leaves the difference in the double accumulator 


CPX 


Internal processing modified to permit its use with any conditional branch instruction 



Table 2. Summary of MC6801U4/MC6803U4 Operating Modes 



Single-Chip (Mode 7) 

192 bytes of RAM, 4096 bytes of ROM 

Port 3 is a parallel I/O port with two control lines 

Port 4 is a parallel I/O port 

Expanded Non-Multiplexed (Mode 5) 

192 bytes of RAM, 4096 bytes of ROM 
256 bytes of external memory space 
Port 3 is an 8-bit data bus 
Port 4 is an input port/address bus 

Expanded Multiplexed (Modes 0, 1, 2, 3, 6*) 

Four memory space options (total 64K address space) 

(1) Internal RAM and ROM with partial address bus (mode 1) 

(2) Internal RAM, no ROM (mode 2) 

(3) Extended addressing of internal I/O and RAM 

(4) Internal RAM and ROM with partial address bus (mode 6) 
Port 3 is multiplexed address/data bus 

Port 4 is address bus (inputs/address in mode 6) 
Test mode (mode 0): 
May be used to test internal RAM and ROM 

May be used to test ports 3 and 4 as I/O ports by writing into mode 7 
Only modes 5, 6, and 7 can be irreversibly entered from mode 0 

Resources Common to All Modes 

Reserved register area 
Port 1 input/output operation 
Port 2 input/output operation 
Timer operation 

Serial communications interface operation 
*The MC6803U4 operates only in modes 2 and 3. 



MOTOROLA MICROPROCESSOR DATA 
3-138 



MC6801U4/6803U4 



vcc 



□ 



Vcc Standby 

RESET > 



Port 1 
8 I/O Lines 
16-Bit Timer 



Port 4 
8 I/O Lines 



XTAL 
EXTAL 
MC6801U4 



vss 



->-E 
-NMI 
-iRQi 



Port 3 
8 I/O Lines 



IS3 



Port 2 
5 I/O Lines 
Serial I/O 
16-Bit Timer 



Figure 9. Single-Chip Mode 



vcc 



vcc 



Port 1 
8 I/O 
Lines 
16-Bit Timer 

Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 



Vcc Standby 

RESET M 



XTAL 
EXTAL 

MC6801U4 



OS3 
Tsl 



v S s 



NMI | 1 

IRQ1 ^ 



VccStandby- 



RESET 

.Port 3, 8 I/O Lines, 



XTAL 
EXTAL 



MC6801U4 



-> IS3 

osl 



Port 4 
8 I/O 
Lines 



Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 



• E 
NMI 
IRQ1 



VSS 



Port 1 
8 1/0 
Lines 
16-Bit Timer 



Port 4 
8 I/O 
Lines 



Figure 10. Single-Chip Dual Processor Configuration 



Figure 11 illustrates a typical system configuration in 
the expanded-nonmultiplexed mode. The MCU interfaces 
directly with M6800 family parts and can access 256 bytes 
of external address space at $1 00 through $1 FF. IOS pro- 
vides an address decode of external memory ($1 00-$1 FF) 
and can be used as a memory-page select or chip-select 
line. 

Expanded-Multiplexed Modes (0, 1, 2, 3, 6) 

A 64K-byte memory space is provided in the expanded- 
multiplexed modes. In each of theexpanded-multiplexed 
modes, port 3 functions as a time-multiplexed address/ 
data bus with address valid on the negative edge of ad- 
dress strobe (AS) and data valid while E is high. In modes 
0, 2, and 3, port 4 provides address lines A8 to A15. In 
modes 1 and 6, however, port 4 initially is configured at 
reset as an input data port. The port 4 data direction 
register can then be changed to provide any combination 
of address lines A8 to A15. Stated alternatively, any sub- 
set of A8 to A15 can be provided while retaining the 



remaining port 4 lines as input data lines. Internal pullup 
resistors pull the port 4 lines high until software confi- 
gures the port. In mode 1, the internal pullup resistors 
will hold the upper address lines high, producing a value 
of $FFXX for a reset vector. A simple method of getting 
the desired address lines configured as outputs is to have 
an external EPROM not fully decoded so it appears at 
two address locations (i.e., $FXXX and $BXXX). Then, 
when the reset vector appears as $FFFE, the EPROM will 
be accessed and can point to an address in the top $100 
bytes of the internal orexteral ROM/EPROM that will con- 
figure port 4 as desired. 

In mode 0, the reset and interrupt vectors are located 
at $BFF0-$BFFF. In addition, the internal and external data 
buses are connected; therefore, there must be no mem- 
ory map overlap to avoid potential bus conflicts. By writ- 
ing the PC0-PC2 bits in the port 2 data register, modes 
5, 6, and 7 can be irreversibly entered from mode 0. Mode 
0 is used primarily to verify the ROM pattern and to mon- 
itor the internal data bus with the automated test equip- 
ment. 



MOTOROLA MICROPROCESSOR DATA 
3-139 



MC6801U4/6803U4 



* T~ 

Vcc Standby — 
RESET 



Port 1 
8 I/O Lines 
16-Bit Timer 

Port 2 
5 I/O 
Lines 
Serial I/O 
16-Bit Timer 



vcc 
I 

XTAL 
EXTAL 
MC6801U4 



vss 



-*-E 
-NMI 
- IRQ1 



Port 3 
'8 Data Lines 
R/W 



>- IOS 

Port 4 
To 8 
Address Lines 



VCC 



Vcc Standby > 

RESET > 

NMI > 

IRQi > 



Port 1 
8 I/O 
16-Bit Timer 
Port 2 
5 I/O 
SCI 
Timer 



XTAL 

EXTAL 

MC6801U4 



VSS 



Port 3 



Port 4 



R/W 



RAM 



S*>(D0-D7) 

(A0-A7) 



-**lOS_ 

R/W 



E 



Figure 11. Expanded-Nonmultiplexed Configuration 



Only the MC6801U4 can operate in each of the ex- 
panded-multiplexed modes. The MC6803U4 operates only 
in modes 2 and 3. 

Figure 12 depicts a typical configuration for the ex- 
panded-multiplexed modes. The AS can be used to con- 
trol a transparent D-type latch to capture addresses A0- 
A7, which allows port 3 to function as a data bus when 
E is high, as shown in Figure 13. 

PROGRAMMING THE MODE 

The operating mode is determined at RESET by the 
levels asserted on P22, P21, and P20. These levels are 
latched into PC2, PC1, and PCO of the p rogram control 
register on the positive edge of RESET. The operating 
mode may be read from the port 2 data register, as shown 
below, and programming levels and timing must be met 
as shown in Figure 14. A brief outline of the operating 
modes is shown in Table 3. 

Circuitry to provide the programming levels is de- 
pendent primarily on the normal system usage of the 



PORT 2 DATA REGISTER 



7 6 5 4 3 2 1 0 



PC2 


PC1 


PCO 


P24 


P23 


P22 


P21 


P20 



three pins. If configured as outputs, the circuit shown in 
Figure 1 5 may be used; otherwise, three-state buffers can 
be used to provide isolation while programming the mode. 
If diodes are used to program the mode, the diode for- 
ward voltage drop must not exceed the V|\/|PDD mini- 
mum. 

MEMORY MAPS 

The MC6801U4/MC6803U4 can provide up to 64K-byte 
address space, depending on the operating mode. A 
memory map for each operating mode is shown in Figure 
16. The first 32 locations of each map are reserved for 
the internal register area, as shown in Table 4, with ex- 
ceptions as indicated. 



MOTOROLA MICROPROCESSOR DATA 
3-140 



MC6801U4/6803U4 



Vcc Standby 



RESET- 



Port 1 
8 I/O Lines 
16-Bit Timer 

Port 2 
5 I/O Lines 
Serial I/O 
16-Bit Timer 



V C C 



vcc 

I 

XTAL 

EXTAL 

MC6801U4 
MC6803U4 



vss 



• E 
•NMI 

-irqT 

Port 3 
8 Lines 

^.p^iMultiplexed Data Address 
-*-AS 



Port 4 
8 Lines 
Address Bus 



Vcc Standby - 
RESET- 
NMI - 
IRQ1- 



Port 1 
8 I/O 
16-Bit Timer 
Port 2 
5 I/O 
SCI 
Timer 



XTAL 
EXTAL 



MC6801U4 
MC6803U4 



vis 



Port 3 8 



AS 



^ 



Latch 
Port 4' jf 



R/W 



ROM 



RAM 



PIA 



Data' Bus 
* (D0-D7) 



Address Bus 



(A0-A15) 
R/W 



-*-E 




NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory devices should be enabled only during E high time. 

Figure 12. Expanded-Multiplexed Configuration 



GND >~ 
AS >- 



Port 3 
Address/ Data 



>- 



G OC 
D1 Q1 



SN74LS373 
(Typical) 



D8 



08 



> Address A0-A7 



Data D0-D7 



Figure 13. Typical Latch Arrangement 



MOTOROLA MICROPROCESSOR DATA 
3-141 



MC6801U4/6803U4 



RESET 



PWRSTL— 
-tMPS" 



Mode Inputs . 
(P20, P21, P22) 



V MPH 



VMPL 



See Figure 15 
for Diode Arrangement 



V MPDD 



l MPH 



^ Data Valid 



V MPH Mm 



Vmpl Max 




MODE PROGRAMMING (Refer to Figure 14) 



Characteristic 


Symbol 


Min 


Max 


Unit 


Mode Programming Input Voltage Low (For Ta = 0-70°C) 


VMPL 




1.8 


V 


Mode Programming Input Voltage High 


Vmph 


4.0 




V 


Mode Programming Diode Differential (If Diodes are Used) (For Ta = 0-70°C) 


V MPDD 


0.6 




V 


RESET Low Pulse Width 


PWRSTL 


3.0 




E Cycles 


Mode Programming Setup Time 


IMPS 


2.0 




E Cycles 


Mode Programming Hold Time 
RESET Rise Times 1 its 
RESET Rise Time<T/is 


tMPH 


0 

100 




ns 



NOTE: 

For Ta= -40-85°C, Vry|p|_ Max =1.7, and Vmpdd M\n = 0.4 

Figure 14. Mode Programming Timing 



Table 3. Mode Selection Summary 





P22 


P21 


P20 






Interrupt 


Bus 




Mode* | 


PC2 


PC1 


PC0 


ROM 


RAM 


Vectors 


Mode 


Operating Mode 


7 


H 


H 


H 


I 


I 


I 


I 


Single Chip 


6 


H 


H 


L 


I 


I 


I 


MUX<2,3) 


Multiplexed/ Partial Decode 


5 


H 


L 


H 


I 


I 


I 


NMUX'2, 3) 


Nonmultiplexed/Partial Decode 


4 


H 


L 


L 










Undefined' 4 ' 


3 


L 


H 


H 


E 


I 


E 


MUX'1.5) 


Multiplexed/RAM 


2 


L 


H 


L 


E 


I 


E 


mux' 1 ' 


Multiplexed/RAM 


1 


L 


L 


H 


I 


I 


E 


MUX (2,3) 


Multiplexed/RAM and ROM 


0 


L 


L 


L 


I 


I 


E 


MUXd) 


Multiplexed Test 



LEGEND 

I — Internal 
E — External ' 
MUX — Multiplexed 

NMUX — Nonmultiplexed 

L — Logic "0" 
H — Logic "1" 

NOTES: 

1. Addresses associated with ports 3 and 4 are considered external in modes 0, 2, and 3. 

2. Addresses associated with port 3 are considered external in modes 1, 5, and 6. 

3. Port 4 default is user data input; address output is optional by writing to port 4 data direction 
register. 

4. Mode 4 is a nonuser mode and should not be used as an operating mode. 

5. Mode 3 has the internal RAM and internal registers relocated at $D000-$D0FF. 



MOTOROLA MICROPROCESSOR DATA 
3-142 



MC6801U4/6803U4 




RESET>— 
P20-*- 

P22M- 



NOTES: 

1. Mode 7 as shown 

2. R2»C = Reset time constant 

3. R1 = 10 k (typical) 

4. D=1N914, 1N4001 in the 0 to 70°C range 
D=1N270, MBD201 in the -40 to 85°C range 

5. Diode Vf should not exceed VmpdD min - 



6 6 6 



DV_ D! '. D ! [ 



Mode 
Control 
Switches 



MC6801U4 
MC6803U4 



RESET 
P20 (PCO) 
P21 (PCD 
P22 (PC2) 




Figure 15. Typical Mode Programming Circuit 



Multiplexed Test Mode 




$BFF0 
$BFFF 



$FFFF 



Internal Registers 
External Memory Space 

Internal RAM 



External Memory Space 

External Interrupt Vectors'2) 
External Memory Space 

nternal ROM 



MC6801U4 
Mode 



NOTES: 

1) Excludes the following addresses which may 
be used externally: $04, $05, $06, $07, and 
$0F. 

2) The interrupt vectors are at $BFF0-$BFFF. 

3) There must be no overlapping of internal and 
external memory spaces to avoid driving the 
data bus with more than one device. 



4) This mode is the only mode which may be 
used t o exam ine the entire ROM using an ex- 
ternal RESET vector. 

5) Modes 5-7 can be irreversibly entered from 
mode 0 by writing to the PC0-PC2 bits of the 
port 2 data register. 



Figure 16. MC6801 U4/MC6803U4 Memory Maps (Sheet 1 of 4) 



MOTOROLA MICROPROCESSOR DATA 
3-143 



MC6801U4/6803U4 



MC6801U4 
Mode 



1 



Multiplexed/RAM & ROM 

$ooood) 




nternal Registers 
External Memory Space 

Internal RAM 



> External Memory Space 



nternal ROM 

External Interrupt Vectors 



NOTES: 

1) Excludes the following addresses which 
may be used externally: $04, $06, and $0F. 

2) Internal ROM addresses $FFF0 tb $FFFF 
are not usable. 

3) Address lines A8-A15 will not contain ad- 
dresses until the data direction register 
for port 4 has been written with "1s" in 
the appropriate bits. These address lines 
will assert "Is" until made outputs by 
writing the data direction register. 



MC6801U4 
MC6803U4 
Mode 



Multiplexed/RAM 
$0000(1) 




$00FF 



$FFF0 
$FFFF 



Internal Registers 
External Memory Space 

Internal RAM 



S External Memory Space 



5 



External Interrupt Vectors 



NOTE: 

1) Excludes the following addresses which may 
be used externally: $04, $05, $06, $07, and 
$0F. 



Figure 16. MC6801 U4/MC6803U4 Memory Maps (Sheet 2 .of 4) 



MOTOROLA MICROPROCESSOR DATA 
3-144 



MC6801U4/6803U4 



MC6801U4 
MC6803U4 
Mode 



Multiplexed/ RAM 
$0000 ,1) 




> External Memory Space 

Internal Registered, 2) 
External Memory Space 
Internal RAM<1) 

External Memory Space 

External Interrupt Vectors 



NOTES: 

1 ) Relocating the internal registers and the inter- 
nal RAM to high memory allows the pro- 
cessor to make use of direct addressing. 

2) Excludes the following addresses which may 
be used externally: $D004, $D005, $D006, 
$D007, and $D00F. 



MC6801U4 
Mode 



Nonmultiplexed/Partial Decode 

$0000 n) t^v^ 



Internal Registers 



Unusable 



$0040 




Internal RAM 

External Memory Space 



$FFFF 



,> Internal ROM 
Internal Interrupt Vectors 




NOTES: 

1) Excludes the following addresses which may 
not be used externally: $04, $06, and $0F (no 
IOS). 

2) Address lines AO to A7 will not contain ad- 
dresses until the data direction register for 
port 4 has been written with "1s" in the ap- 
propriate bits. These address lines will assert 
"1s" until made outputs by writing the data 
direction register. 



Figure 16. MC6801 U4/MC6803U4 Memory Maps (Sheet 3 of 4) 



MOTOROLA MICROPROCESSOR DATA 
3-145 



MC6801U4/6803U4 



MC6801U4 
Mode 



Multiplexed/Partial Decode 



$0000d) 
$001 F 

$0040 
SOOFF 





$F000 



$FFFF 




Internal Registers 
External Memory Space 
Internal RAM 



> External Memory Space 



} Internal ROM 
Internal Interrupt Vectors 



NOTES: 

1 ) Excludes the following addresses which may 
be used externally: $04, $06, $0F. 

2) Address lines A8-A15 will not contain ad- 
dresses until the data direction register for 
port 4 has been written with "1s" in the ap- 
propriate bits. These address lines will assert 
"1s" until made outputs by writing the data 
direction register. 



MG6801U4 
Mode 



Single Chip 




Internal Registers 



Internal RAM 



$F00O 




Internal ROM 

Internal Interrupt Vectors 



Figure 16. MC6801U4/MC6803U4 Memory Maps (Sheet 4 of 4) 



MOTOROLA MICROPROCESSOR DATA 
3-146 



MC6801U4/6803U4 



Table 4. Internal Register Area 



MC6801U4/MC6803U4 INTERRUPTS 





Address 




Other 




Register 


Modes 


Mode 3 


Port 1 Data Direction Register* * * 


0000 


D000 


Port 2 Data Direction Register* * * 


0001 


D001 


Port 1 Data Register 


0002 


D002 


Port 2 Data Register 


ooo 


° 3 


Port 3 Data Direction Register* * * 


0004* 


D004* 


Port 4 Data Direction Register* * * 


0005** 


D005** 


Port 3 Data Register 


0006* 


D006* 


Port 4 Data Register 


0007* * 


D007* * 


Timer Control and Status Register 


0008 


D008 


Counter (High Byte) 


0009 


D009 


Counter (Low Byte) 


OOOA 


DOOA 


Output Compare Register (High Byte) 


OOOB 


DOOB 


Output Compare Register (Low Byte) 


000C 


DOOC 


Input Capture Register (High Byte) 


OOOD 


DOOD 


Input Capture Register (Low Byte) 


000E 


DOOE 


Port 3 Control and Status Register 


OOOF* 


DOOF* 


Rate and Mode Control Register 


0010 


D010 


Transmit/ Receive Control and Status Register 


0011 


D011 


Receive Data Register 


0012 


D012 


Transmit Data Register 


0013 


D013 


RAM Control Register 


0014 


D014 


Counter Alternate Address (High Byte) 


0015 


D015 


Counter Alternate Address (Low Byte) 


0016 


D016 


Timer Control Register 1 


0017 


D017 


Timer Control Register 2 


0018 


D018 


Timer Status Register 


0019 


D019 


Output Compare Register 2 (High Byte) 


001A 


D01A 


Output Compare Register 2 (Low Byte) 


001 B 


D01B 


Output Compare Register 3 (High Byte) 


001C 


D01C 


Output Compare Register 3 (Low Byte) 


001 D 


D01D 


Input Capture Register 2 (High Byte) 


001 E 


D01E 


Input Capture Register 2 (Low Byte) 


001 F 


D01F 



♦External addresses in modes 0, 1,2, 3, 5, and 6 cannot be 

accessed in mode 5 (no I OS). 
"♦External Addresses in Modes 0, 2, and 3. 
>*1 = Output, 0= Input 



The M6801 Family supports two types of interrupt re- 
quests: mas kable and nonmaskable. A nonmaskable in- 
terrupt (NMI) is always recognized and acted upon at the 
completion of the current instruction. Maskable inter- 
rupts are controlled by the condition code register I bit 
and by individual enable bits. The I bit controls all mask- 
able in terrup ts. Of the maskable interrupts, there are two 
types: IRQ1 and IRQ2. The programmable time r and se- 
rial communications interface use an internal IRQ2 in- 
terrupt line, as sho wn in the bloc k diagram. External 
device s and IS3 use IRQ1. An IRQ1 interrupt is serviced 
before IRQ2 if both are pending. 

NOTE 

After reset, an NMI will not be serviced unti l the 
first program load of the stack pointer. Any NMI 
generated before this load will be remembered by 
the processor and serviced subsequent to the stack 
pointer load. 

All IRQ2 interrupts use hardware-prioritized vectors. 
The single SCI interrupt and three timer interrupts are 
serviced in a prioritized order, and each is vectored to a 
separate location. All interrupt-vector locations are shown 
in Table 5. In mode 0, reset and interrupt vectors are 
defined as $BFF0-$BFFF. 

The interrupt flowchart, which is depicted in Figure 17, 
is common to every interrupt excluding reset. During in- 
terrupt servicing, the program counter, index register, A 
accumulator, B accumulator, and condition code register 
are pushed to the stack. The I bit is set to inhibit maskable 
interrupts, and a vector is fetched corresponding to the 
current highest-priority interrupt. The vector is trans- 
ferred to the program cou nter, an d instruction execution 
is resumed. Interrupt and RESET timing are illustrated in 
Figures 18 and 19. 



Table 5. MCU Interrupt-Vector Locations 



Mode 0 


Modes 1-3, 5-7 


Interrupt* * * 


MSB 


LSB 


MSB 


LSB 


BFFE 


BFFF 


FFFE 


FFFF 


RESET 


BFFC 


BFFD 


FFFC 


FFFD 


Nonmaskable Interrupt** 


BFFA 


BFFB 


FFFA 


FFFB 


Software Interrupt 


BFF8 


BFF9 


FFF8 


FFF9 


Maskable Interrupt Request 1 


BFF6 


BFF7 


FFF6 


FFF7 


Input Capture Flag* 


BFF4 


BFF5 


FFF4 


FFF5 


Output Compare Flag* 


BFF2 


BFF3 


FFF2 


FFF3 


Timer Overflow Flag* 


BFFO 


BFF1 


FFFO 


FFF1 


Serial Communications Interface* 



*IRQ2 interrupt 
* *NMI must be armed (by accessng stack pointer) before an 

NMI is executed. 
*** Mode 4 interrupt vectors are undefined. 



MOTOROLA MICROPROCESSOR DATA 
3-147 




CO 





o 

o> 
oo 
o 

C 

00 

o 

CO 

c 



SCI = TIE.TDRE + RIE-IRDRF + ORFEI 
ICI = [ICF1 •EICI1 ) + (ICF2-EICI2)- 
OCI = IOCF1«E'OCI1 ) + (OCF2»EOCI2> + IOCF3»EOCI3l 



Condition Code Register 

1 1 1 1 I h 1 1 |n | z | v | c | 



Vector -^PC 




Mode 0 


Modes 1-3, 5-7 




NMI 


BFFC-BFFD 


FFFC-FFFD 


Nonmaskable Interrupt 


SWI 


BFFA-BFFB 


FFFA-FFFB 


Software Interrupt 


IRQ1 


BFF8-BFF9 


FFF8-FFF9 


Maskable Interrupt Request 1 


ICF 


BFF6 BFF7 


FFF6-FFF7 


Input Capture Interrupt 


OCF 


BFF4 BFF5 


FFF4-FFF5 


Output Compare Interrupt 


TOF 


BFF2-BFF3 


FFF2-FFF3 


Timer Overflow Interrupt 


SCI 


BFF0-BFF1 


FFF0-FFF1 


SCI Interrupt 



Figure 17. Interrupt Flowchart 



Last Instr uction - 



Cycle 
#1 



#2 



#6 



ni 



#8 



#11 



#12 



Internal ~V" 
Address Bus _/\_ 



IRQ1 



NMI or IRQ2 



X X X X X X } ( )f x x~ X~ — X- — — X 



— H (<-tpcs 



rLTLTLT 



I Bit Set 



Op Code OpCode SP(n) SP(n-l) SP|n-2) SP(n-3)- SP(n-4) SP(n-5) SP(n-6) SP(n-7) Vector Vector New PC 
Addr Addr MSB Addr LSB Addr Address 



— »-) f**— tPCS 

oats Bus ~X X X X ~ X X X "X X X X! X X H — X — _ I X -X 

! F 

Internal R/W \ 



Op Code Op Code PC 0-7 PC8-15 X0 7 X 8-15 ACCA ACCB CCR Irrelevant Vector Vector First Inst of 

Data MSB LSB Interrupt Routine 

y — ~ 



Figure 18. Interrupt Sequence 



i n n.n nnnnnnnnr 



. 5.25 V 



_-^4 75 V 

/L 



•tRC" 



-j ) 0-8 '4.0 V 



■tpcs 



-J h 



— t K 

0.8 V-t 



Internal 
Address Bus 



FFFE 1 FFFE FFFE FFFE FFFF New PC 
nterna, R/W WWWWWWWW^ , j,\ \\\\\\\ \ \\\\\\\ \ \\\\\\ \ \\V — * 



Internal 
Data Bus ^ 



KW^CN] Not Valid 



PC 8-15 PC 0-7 First 

Instruction 




2 

o 

O) 
00 

o 

c 
*» 
o> 

00 

o 

w 

c 



Figure 19. RESET Timing 



CO 



MC6801U4/6803U4 




FUNCTIONAL PIN DESCRIPTIONS 

V C c AND Vss 

VCC and Vss provide power to a large portion of the 
MCU. The power supply should provide +5 volts (±5%) 
to Vco and Vss should be tied to ground. Total power 
dissipation (incuding Vcc standby) will not exceed Pq 
milliwatts. 

Vcc STANDBY 

Vcc standby provides power to the standby portion 
($40 through $5F in all modes except mode 3, which is 
$D040 through $D05F) of the RAM, and the STBY PWR 
and RAME bits of the RAM control register. Voltage re- 
quirements depend on whether the device is in a pow- 
erup or powerdown state. In the powerup state, the power 
supply should pr ovide + 5 volts (±5%) anr 1 must reach 
VsB volts before RESET reaches 4.0 volts. During pow- 
erdown, Vcc standby must remain above VsbB (mini- 
mum) to sustain the standby RAM and STBY PWR bit. 
While in powerdown operation, the standby current will 
not exceed IsBB- 

It is typical to power both Vcc and Vcc standby from 
the same source during normal operation. A diode must 
be used between them to prevent supply power to Vcc 
during powerdown operation. 

XTAL AND EXTAL 

These two input pins interface either a crystal or TTL- 
compatible clock to the MCU internal clock geneator. Di- 
vide-by-four circuitry is included which allows use of the 
inexpensive 3.58-MHz or 4.4336-MHz color-burst TV crys- 
tals. A 20-pF capacitor should, be tied from each crystal 
pin to ground to ensure reliable startup and operation. 
Alternatively, EXTAL may be driven by an external TTL- 
compatible clock at 4 f Q with a duty cycle of 50% (±5%) 
with XTAL connected ground. 

The internal oscillator is designed to interface with an 
AT-cut quartz crystal resonator operated in parallel res- 
onance mode in the frequency range specified forfxTAL- 
The crystal should be mounted as close as possible to 
the input pins to minimize output distortion and startup 
stabilization time. The MCU is compatible with most com- 
mercially available crystals. Nominal crystal parameters 
are shown in Figure 20. 



RESET 

This input is used to reset the internal state of the de- 
vice and provide an orderly startup procedure. During 
powerup, RESET must be held below 0.8 volts: 1 ) at least 
tRC after VCC reaches 4.75 volts to provide sufficient time 
for the clock genera tor to st abilize, and 2) until Vcc standby 
reaches 4.75 volts. RESET must be held low at least three 
E cycles if asserted during powerup operation. 

E (ENABLE) 

This is an output clock used primarily for bus synchro- 
nization. It is TTL compatible and is the slightly skewed 
divide-by-four result of the device input clock frequency. 
It will drive one Schottky TTL load and 90 pF, and all data 



given in cycles are referenced to this clock unless oth- 
erwise noted. 

NMI (NONMASKABLE INTERRUPT) 

An NMI negative edge requests an MCU interrupt se- 
quence, but the current instrution will be completed be- 
fore it responds to the request. The MCU will then begin 
an interrupt sequence. Finally, a vector is fetched from 
$FFFC and $FFFD ($BFFC and $BFFD in mode 0), trans- 
ferred to the prog ram counter, and instruction execution 
is resumed. NMI typically requires a 3. 3 kH (nominal) 
resis tor to Vcc- There is no internal NMI pullup resistor. 
NMI must be held low for at least one E cycle to be 
recognized under all conditions! 

NOTE 

After reset, an NMI will not be serviced unti l the 
first program load of the stack pointer. Any NMI 
generated before this load will remain pending by 
the processor. 

iRQI (MASKABLE INTERRUPT REQUEST 1) 

IRQ1 is a level-sensitive input that can be used to re- 
quest an interrupt sequence. The MPU will complete the 
current instruction before it responds to the request. If 
the interrupt mask bit (I bit) in the condition code register 
is clear, the MCU will begin an interrupt sequence. A 
vector is fetched from $FFF8 and $FFF9 ($BFF8 and $BFF9 
in mode 0), transferred to the program counter, and in- 
struction execution is resumed. 

IRQ1 typically requires an external 3.3 kfl (nominal) 
resistor to Vcc f° r wire-OR applications. IRQ1 has no 
internal pullup resistor. 

SC1 AND SC2 (STROBE CONTROL 1 AND 2) 

The function of SC1 and SC2 depends on the operating 
mode. SC1 is configured as an output in all modes except 
single-chip mode; whereas, SC2 is always an output. SC1 
and SC2 can drive one Schottky load and 90 pF. 

SC1 and SC2 in Single-Chip Mode 

In single-chip mode, SC1 and SC2 are configured as 
an input and output, respectively, and both function as 
port 3 control lines. SC1 functions as IS3 and can be used 
to indicate that port 3 input data is ready or output data 
has been accepted.Three options associated with IS3 are 
controlled by the port 3 contol and status register and 
are discussed in the port 3 description; refer to P30-P37 
(PORT 3). If unused, IS3 can remain unconnected. 

SC2 is configured as OS3 and can be used to strobe 
output data or acknowledge input data. It is controlled 
by output strobe select (OSS) in the port 3 control and 
status register. The strobe is generated by a read (OSS = 0) 
or write (OSS= 1 ) to the port 3 data register. OS3 timing 
is shown in Figure 3. 

SCI and SC2 in Expanded-Nonmultiplexed Mode 

In the expanded-nonmultiplexed mode, both SC1 and 
SC2 are configured as outputs. SC1 functions as input/ 
output select (IOS) and is asserted only when $0100 
through $01 FF is sensed on the internal address bus. 



MOTOROLA MICROPROCESSOR DATA 
3-150 



MC6801U4/6803U4 



(a) Nominal Recommended Crystal Parameters 



Nominal Crystal Parameters* 





3.58 MHz 


4.00 MHz 


5.0 MHz 


RS 


6011 


500 


30-501) 


CO 


3.5 pF 


6.5 pF 


4-6 pF 


CI 


0.015 pF 


0.025 pF 


0.01-0.02 pF 


Q 


>40 K 


>30 K 


>20 K 



*NOTE: These are representative AT-cut crystal parameters only. Crystals of other 
types of cut may also be used. 



MC6801U4 




Equivalent Circuit 



NOTE 

TTL-compatible oscillators may 
be obtain from: 

Motorola Component Prod- 
ucts 

Attn: Crystal Clock Oscillators 
2553 N. Edgington St. 
Franklin Park, IL 60131 

Tel: 312-451-1000 

Telex: 433-0067 



(b) Oscillator Stabilization Time Urc) 




Oscillator 



Time, tRc 

Figure 20. MC6801U4/MC6803U4 Family Oscillator Characteristics 



MOTOROLA MICROPROCESSOR DATA 
3-151 



MC6801U4/6803U4 



SC2 is configured as read/write and is used to control 
the direction of data bus transfers. An MPU read is en- 
abled when read/write and E are high. 

SC1 and SC2 in Expanded-Multiplexed Mode 

In the expanded-multiplexed modes, both SC1 nd SC2 
are configured as outputs. SC1 functions as address strobe 
and can be used to demultiplex the eight least-significant 
addresses and the data bus. A latch controlled by address 
strobe captures the lower address on the negative edge, 
as shown Figure 13. 

SC2 is configured as read/write and is used to control 
the direction of data bus transfers. An MPU read is en- 
abled when read/write and E are high. 

P10-P17 (PORT 1) 

Port 1 is a mode-independent 8-bit I/O and timer port. 
Each line can be configured as either an input or output 
as defined by the port 1 data direction register. Port 1 
bits 0, 1, and 2 (P10, P1 1, and P12) can also be used to 
exercise one input edge function and two output compare 
functions of the timer. The TTL-compatible three-state 
buffers can drive one Schottky TTL load and 30 pF, Dar- 
lington transistors or CMOS devices using external pul- 
lup res istors. It is configured as a data input port during 
RESET. Unused pins can remain unconnected. 

P20-P24 (PORT 2) 

Port 2 is a mode-independent 5-bit multipurpose I/O 
port. The voltage l evels p resent on P20, P21, and P22 on 
the rising edge of RESET determine the operating mode 
of the MCU. The entire port is then configured as a data 
input port. The port 2 lines can be selectively cofigured 
as data output lines by setting the appropriate bits in the 
port 2 data direction register. The port 2 data register is 
used to move data through the port. However, if P21 is 
configured as an output, it is tied to the timer output 
compare 1 function and cannot be used to provide output 
from the port 2 data register unless output enable 1 (OE1 ) 
is cleared in timer control register 1. 

Port 2 can also be used to provide an interface for the 
serial communications interface and the timer input edge 
function. These configurations are described in SERIAL 
COMMUNICATIONS INTERFACE and PROGRAMMABLE 
TIMER. 

The port 2 three-state TTL-compatible output buffers 
are capable of driving one Schottky TTL load and 30 pF 
or CMOS devices using external pullup resistors. 

PORT 2 DATA REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 




PC2 


PCI 


PCO 


P24 


P23 


P22 


P21 


P20 


$03 



P30-P37 (PORT 3) 

Port 3 can be configured as an I/O port, a bidirectional 
8-bit data bus, or a multiplexed address/data bus de- 
pending on the operating mode. The TTL-compatible 
three-state output buffers can drive one Schottky TTL 
load and 90 pF. Unused lines can remain unconnected. 



Port 3 in Single-Chip Mode 

, Port 3 is an 8-bit I/O port in the single-chip mode with 
each line configured by the port 3 data direction register. 
There are also two lines, IS3 and OS3, which can be used 
to control port 3 data transfers. 

Three port 3 options are controlled by the port 3 control 
and status register and are available only in single-chip 
mode: 1) port 3 input data can be latched using IS3 as a 
control signal, 2) OS3 can be generated by either an MPU 
read or write to the port 3 data register, and 3) an IRQ1 
interrupt can be enabled by an IS3 negative edge. Port 3 
latch timing is shown in Figure 4. 

PORT 3 CONTROL AND STATUS REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


IC3 


IS3 


X 


OSS 


Latch 


X 


X 


X 


Flag 


IRQ1 




Enable 





$0F 



Bits 0-2 Not used. 

Bit 3 Latch Enable — This bit controls the input latch 
for port 3. If set, input data is latched by an IS3 
negative edge. The latch is transparent after a 
read of the port 3 data register. Latch enable is 
cleared during reset. 

Bit 4 Output Strobe Select (OSS) — This bit deter- 
mines whether OS3 will be generated by a read 
or write of the port 3 data register. When clear, 
the strobe is generated by a read; when set, it 
is generated by a write. OSS is cleared during 
reset. 

Bit 5 Not used. 

Bit 6 IS3 IRQ1 Enable — When set, an IRQ1 interrupt 
will be enabled whenever the IS3 flage is set; 
when clear, the interrupt is inhibited. This bit is 
cleared during reset. 

Bit 7 IS3 Flag — This read-only status bit is set by an 
IS3 negative edge. It is cleared by a read of the 
port 3 data register or during reset. 

Port 3 in Expanded-Nonmultiplexed Mode 

Port 3 is configured as a bidirectional data bus (D7-D0) 
in the expanded-nonmultiplexed mode. The direction of 
data transfers is controlled by read/write (SC2). Data is 
clocked by E (enable). 

Port 3 in Expanded-Multiplexed Mode 

Port 3 is configured as a time-multiplexed address (A7- 
A0), and data bus (D7-D0) in the expanded-multiplexed 
mode where AS can be used to demultiplex the two buses. 
Port 3 is held in a high-impedance state between valid 
address and data to prevent bus conflicts. 

P40-P47 (PORT 4) 

Port 4 Is configured as an 8-bit I/O port, as address 
outputs, or as data inputs depending on the operating 



MOTOROLA MICROPROCESSOR DATA 
3-152 



MC6801U4/6803U4 



mode. Port 4, which can drive one Schottky TTL load and 
90 pF, is the only port with internl pullup resistors. Un- 
used lines can remain unconnected. 

Port 4 in Single-Chip Mode 

In single-chip mode, port 4 functions as an 8-bit I/O 
port with each line configured by the port 4 data direction 
register. Internal pullup resistors allow the port to directly 
interface with CMOS at 5-volt levels. However, external 
pullup resistors to more than 5 volts cannot be used. 

Port 4 in Expanded-Nonmultiplexed Mode 

Port 4 is configured from reset as an 8-bit input port 
where the port 4 data direction register can be written to 
provide any or all of eight address lines AO to A7. Internal 
pullup resistors pull the lines high until the port 4 data 
direction register is configured. 

Port 4 in Expanded-Multiplexed Mode 

In all expanded-multiplexed modes except modes 1 
and 6, port 4 functions as half of the address bus and 
provides A8 to A15. In modes 1 and 6, the port is confi- 
gured from reset as an 8-bit parallel input port where the 
port 4 data direction register can be written to provide 
any or all of upper address lines A8to A15. Internal pullup 
resistors pull the lines high until the port 4 data direction 
register is configured where bit 0 controls A8. 



RESIDENT MEMORY 

The MC6801U4 provides 4096 bytes of on-chip ROM 
and 192 bytes of on-chip RAM. ... 

Thirty-two bytes of the RAM ae powered through the 
VrjC standby pin and are maintainable during VfjC power- 
down. This standby portion of the RAM consists of 32 
bytes located from $40 through $5F in all modes except 
mode 3, which is $D040 through $D05F. 

Power must be supplied to VrjC standby if the internal 
RAM is to be used, regardless of whether standby power 
operation is anticipated. 

The RAM is controlled by the RAM control register. 

RAM CONTROL REGISTER ($14) 

The RAM control register includes two bits, which can 
be used to control RAM accesses and to determine the 
adequacy of the standby power source during power- 
down operation. It is intended that RAME be cleared and 
STBY PWR be set as part of a powerdown procedure. 

RAM CONTROL REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


STBY 
PWR 


RAME 


X' 


X 


X 


X 


X 


X 



$14 



Bits 0-5 Not used. 



Bit 6 RAM Enable — This read/write bit can be used 
to remove the entire RAM from the internal mem- 
ory map. RAME is set (enabled) during reset pro- 
vided standby power is available on the positive 



edge of RESET. If RAME is clear, any access to 
a RAM address is external. If RAME is set, the 
RAM is included in the internal map. 

Bit 7 Standby Power — This bit is a read/write status 
bit that, when cleared, indicates Vcc standby has 
decreased sufficiently below VsbB (minimum) to 
make data in the standby RAM suspect. It can be 
set only by software and is not affected during 
reset. 



PROGRAMMABLE TIMER 

The programmable timer can be used to perform meas- 
urements on two separate input waveforms while inde- 
pendently generating three output waveforms. Pulse 
widths can vary from several microseconds to many sec- 
onds. A block diagram of the timer is shown in Figure 
21. 

COUNTER ($09 :0A), ($15, $16) 

The key timer element is a 16-bit free-running counter 
that is incremented by E (enable). It is cleared during reset 
and is read-only with one exception: in mode 0 a write 
to the cou nter ($09) wi I I conf ig u re it to $FFF8. Th is f eatu re, 
intended for testing, can disturb serial operations be- 
cause the counter provides the SCI internal bit rate clock. 
The TOF is set whenever the counter contains all ones. 
If ETOI is set, an interrupt will occur when the TOF is set. 
The counter may also be read as $15 and $16 to avoid 
inadvertently clearing the TOF. 

OUTPUT COMPARE REGISTERS ($0B.0C), ($1A:1B), 
($1C:1D) ' 

The three output compare registers are 16-bit read/ 
write registers, each used to control an output waveform 
or provide an arbitrary time-out flag. They are compared 
with the free-running counter during the negative half of 
each E cycle. When a match occurs, the corresponding 
output compare flag (OCF) is set, and the corresponding 
output level (OLVL) is clocked to an output level register. 
If both the corresponding output enable bit and data di- 
rection register bit are set, the value represented in the 
output level register will appear on the corresponding 
port pin. The appropriate OLVL bit can then be changed 
for the next compare. . 

The function is inhibited for one cycle after a write to 
its high byte ($0B, $1 A, or $1C) to ensure a valid compare 
after a double-byte write. Writes can be made to either 
byte of the output compare register without affecting the 
other byte. The OLVL value will be clocked out inde- 
pendently of whether the OCF had previously been 
cleared. The output compare registers are set to $FFFF 
during reset. 

INPUT CAPTURE REGISTERS ($0D:0E), ($1E:1F) 

The two input capture registers are 16-bit read-only 
registers used to store the free-running counter when a 
"proper" input transition occurs as defined by the cor- 
responding input edge bit (IEDG1 or IEDG2). The input 
pin's data direction register should be configured as an 




MOTOROLA MICROPROCESSOR DATA 
3-153 




3> 



MC6801U4/MC6803U4 Internal Bus 



Output Compare 
Register 3 



Output Compare 
Register 2 



Output Compare 
Register 1 



$09:0A 
($15:16) 



Free-Running 
16- Bit Counter 



$0D:0E 



Input Capture 
Register 1 

7^ 



Input Capture 
Register 2 . 



IT 



Output Compares 
(Three) 



TCSR ($08) | 
| ICF1 | OCF1 | TOF | EICI1 |EOICil| ETOI | IEDG1 1 OLVL1 1 



tz 



Overflow 
Detect 



r 



z 



Edge Detects 
(Two) 



-7^ 



V 1 



L 



-7* 



rz 



| OE3 | 0E2 | 0E1 [lEDG2 |lEDG1 |0LVL3 [oLVL2 1 OLVL1 1 



^ > 



_^ j _ _ TSR ($191 

| ICF2 | ICF1 | OCF3 | OCF2 | OCF1 | TOF | 1 | 1 | 



_ _ s _ _ TCR2 ($18) 

| EICI2 | EICI1 I EOCI3 j EOCI2 | EOCI1 | ETOI | TEST |cLOCk[ 



° -o 



Output Level 
Register 1 



H> 



Output Level 
Register 2 



> 



Output Level 
Register 3 



Port Control 
Circuitry 



Input Edge 
_< P20 



Output Level 
~*~ P21 



Output Level 
P11 



Output Li 
P12 



Figure 21. Block Diagram of Programmable Timer 



MC6801U4/6803U4 



input, but the edge detect circuit always senses P10 and 
P20 even when configured as an output. The counter 
value will be latched into the into capture registers on 
the second negative edge of the E clock following the 
transition. 

As input capture can occur independently of ICF; the 
register always contains the most current value. How- 
ever, counter transfer is inhibited between accesses of a 
double-byte MPU read. The input pulse width must be at 
least two E cycles to ensure an input capture under all 
conditions. 

TIMER CONTROL AND STATUS REGISTERS 

Four registers are used to provide the MC6801U4/ 
MC6803U4 with control and status information about the 
three output compare functions, the timer overflow func- 
tion, and the two input edge functions of the timer. They 
are as follows: 

Timer Control and Status Register (TCSR) 

Timer Control Register 1 (TCR1) 

Timer Control Register 2 (TCR2) 

Timer Status Register (TSR) 

Timer Control and Status Register (TCSR) ($08) 

The timer control and status register is an 8-bit register 
in which, all bits are readable, while only bits 0-4 can be 
written. All the bits in this register are also accessible 
through the two timer control registers and the timer 
status register. The three most significant bits provide 
the timer status and indicate if 

1. a proper level transition has been detected at P20; 

2. a match has occurred between the free-running 
counter and output compare register 1 ; or 

3. the free-running counter has overflowed. 

Each of the three events can generate an IRQ2 interrupt 
and is controlled by an individual enable bit in the TCSR. 

TIMER CONTROL AND STATUS REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


ICF1 


0CF1 


TOF 


EICI1 


E0CI1 


ETOI 


IEDG1 


0LVL1 



Bit 0 Output Level 1 — OLVL1 is clocked to Output level 
register 1 by a successful output compare and will 
appear at P21 if bit 1 of the port 2 data direction 
register is set and the OE1 control bit in timer con- 
trol register 1 is set. OLVL1 and output level reg- 
ister 1 are cleared during reset. Refer to TIMER 
CONTROL REGISTER 1 (TCR1) ($17). 

Bit 1 Input Edge 1 — IEDGT is cleared during reset and 
controls which level transition on P20 will trigger 
a counter transfer to input capture register 1: 
IEDG1 =0 transfer on a negative-edge 
IEDG1 = 1 transfer on a positive-edge 
Refer to TIMER CONTROL REGISTER 1 (TCR1) ($17). 

Bit 2 Enab le Timer Overflow Interrupt — When set, an 
IRQ2 interrupt will be generated when the timer 
overflow flag is set; when clear, the interrupt is 



inhibited ETOI is cleared during reset. Refer to 
TIMER CONTROL REGISTER 2 (TCR2) ($18). 

Bit 3 En able O utput Compare Interrupt 1 — When set, 
an IRQ2 interrupt will be generated when output 
compare flag 1 is set; when clear,the interrupt is 
inhibited. EOCI1 is cleared during reset. Refer to 
TIMER CONTROL REGISTER 2 (TCR2) ($18). 

Bit 4 En able O utput Capture Interrupt 1 — When set, 
an IRQ2 interrupt will be generated when input 
capture flag 1 is set; when clear, the interrupt is 
inhibited. EICM is cleared during reset. Refer to 
TIMER CONTROL REGISTER 2 (TCR2) ($18). 



Bit 5 Timer Overflow Flag — - The TOF is set when the 
counter contains all ones ($FFFF). It is cleared by 
reading the TCSR or the TSR (with TOF set) and 
the counter high byte ($09), or during reset. Refer 
to TIMER STATUS REGISTER (TSR) ($19). 



Bit 6 Output Compare Flag 1 — OCF1 is set when output 
compare register 1 matches the free-running 
counter. OCF1 is cleared by reading the TCSR or 
the TSR (with OCF1 set) and then writing to output 
compare register 1 ($0B or $0C), or during reset. 
Refer to TIMER STATUS REGISTER (TSR) ($19). 



Bit 7 Input Capture Flag — ICF1 is set to indicate that a 
proper level transition has occurred; it is cleared 
by reading the TCSR or the TSR (with ICF1 set) and 
the input capture register 1 high byte ($0D), or 
during reset. Refer to TIMER STATUS REGISTER 
(TSR) ($19). 

Timer Control Register 1 (TCR1) ($17) 

Timer control register 1 is an 8-bit read/write register 
containing the control bits for interfacing the output com- 
pare and input capture registers to the corresponding I/ 
0 pins. 

TIMER CONTROL REGISTER 1 



7 


6 


5 


4 ■ 


3 


2 


1 


0 


0E3 


0E2 


0E1 


IEDG2 


IEDG1 


0LVL3 


0LVL2 


0LVL1 



Bit 0 Output Level 1 — OLVL1 is clocked to output level 
register 1 by a successful output compare and will 
appear at P21 if bit 1 of the port 2 data direction 
register is set and the OE1 control bit is set. OLVL1 
and output level register 1 are cleared during reset. 
Refer to TIMER CONTROL AND STATUS REGIS- 
TER (TCSR) ($08). 

Bit 1 Output Level 2 — OLVL2 is clocked to output level 
register 2 by a successful output compare and will 
appear at P11 if bit 1 of port 1 data direction reg- 
ister is set and the OE2 control bit is set. OLVL2 
and output level register 2 are cleared during reset. 




MOTOROLA MICROPROCESSOR DATA 
3-155 



MC6801U4/6803U4 



Bit 2 Output Level 3 — OLVL3 is clocked to output level 
register 3 by a successful output compare and will 
appear at P12 if bit 2 of port 1 data direction reg- 
ister is set and the OE3 control bit is set. OLVL3 
and output level register 3 are cleared during reset. 

Bit 3 Input Edge 1 — IEDG1 is cleared during reset and 
controls which level transition on P20 will trigger 
a counter transfer to inut capture register 1. 
IEDG1 = 0 transfer on a negative edge 
IEDG1 = 1 transfer on a positive edge 
Refer to TIMER CONTROL AND STATUS REGIS- 
TER (TCSR) ($08). 

Bit 4 Input Edge 2 — IEDG2 is cleared during reset and 
controls which level transition on P10 will trigger 
a counter transfer to input capture register 2. 
IEDG2 = 0 transfer on a negative edge 
IEDG2 = 1 transfer on a positive edge 




Bit 5 Output Enable 1 — OE1 is set during reset and 
enables the contents of output level register 1 to 
be connected to P21 when bit 1 of port 2 data 
direction register is set. 

OE1 =0 port 2 bit 1 data register output 

OE1 = 1 output level register 1 



Bit 6 Output Enable 2— OE2 is cleared during reset and 
enables the contents of output level register 2 to 
be connected to P11 when bit 1 of port 1 data 
direction register is set. . 

OE2 = 0 port 1 bit 1 data register output 

OE2 = 1 output level register 2 

Bit 7 Output Enable 3 — OE3 is cleared during reset and 
enables the contents of output level register 3 to 
be connected to P12 when bit 2 of port 1 data 
direction register is set 

OE3 = 0 port 1 bit 2 data register output 

OE3 = 1 output level register 3 

Timer Control Register 2 (TCR2) ($18) 

Timer control register 2 is an 8-bit read/write register 
(except bits 0 and 1), which enables the interrupts as- 
sociated with the free-running counter, the output com- 
pare registers, and the input capture registers. In test 
mode 0, two more bits (clock and test) are available for 
checking the timer. 

TIMER CONTROL REGISTER 2 
(Nontest Modes) 



7 


6 


5 


4 . 


3 


2 1 


0 


EICI2 


EICI1 


E0CI3 


E0CI2 


E0CI1 


ETOI 


• 1 


1 



Bits 0-1 Read-Only Bits — When read, these bits return 
a value of 1. Refer to TIIMER CONTROL REG- 
ISTER 2 (Test Mode). 

Bit 2 Enab le Timer Overflow Interrupt — When set, an 
IRQ2 interrupt will be generated when the timer 



overflow flag is set; when clear, the interrupt in- 
hibited. ETOI is cleared during rest. Refer to TIMER 
CONTROL AND STATUS REGISTER (TCSR) ($08). 

Bit 3 En able O utput Compare Interrupt 1 — When set, 
an IRQ2 interrupt will be generated when the out- 
put compare flag 1 is set; when clear, the inter- 
rupt is inhibited. EOCI1 is cleared during reset. 
Refer to TIMER CONTROL AND STATUS REG- 
ISTER (TCSR) ($08). 

Bit 4 En able O utput Compare Interrupt 2 — When set, 
an IRQ2 interrupt will be generated when the out- 
put compare flag 2 is set; when clear, the inter- 
rupt is inhibited. EOCI2 is cleared during reset. 

Bit 5 En able O utput Compare Interrupt 3 — When set, 
an IRQ2 interrupt will be generated when the out- 
put compare flag 3 is set; when clear, the inter- 
rupt is inhibited. EOCI3 is cleared during reset. 

Bit 6 Enab le Input Capture Interrupt 1 — When set, an 
IRQ2 interrupt will be generated when the input 
capture flag 1 is set; when clear, the interrupt is 
inhibited. EICI1 is cleared during reset. Refer to 
TIMER CONTROL AND STATUS REGISTER (TCSR) 
($08). 

Bit 7 Enab le Input Capture Interrupt 2 — When set, an 
IRQ2 interrupt will be generated when the input 
capture flag 2 is set; when clear, the interrupt is 
inhibited. EICI2 is cleaed during reset. 

The timer test bits (test and clock) allow the free-run- 
ning counter to be tested as two separate 8-bit counters 
to speed testing. 

TIMER CONTROL REGISTER 2 
(Test Modes) 



7 


6 


5 


4 


3 


2 


1 


0 


EICI2 


EICI1 


E0CI3 


E0CI2 


E0CI1 


ETOI 


TEST 


CLOCK 



Bit 0 CLOCK — The CLOCK control bit selects which 
half of the 16-bit free-running counter (MSB or 
LSB) should be clocked with E. The CLOCK bit is 
a read/write bit only in mode 0 and is set during 
reset. 

CLOCK = 0 — Only the eight most-significant bits 
of the free-running counter run with TEST=0. 

CLOCK = 1 — Only the eight least-significant bits 
of the free-running counter run when TEST = 0. 

Bit 1 TEST — The TEST control bit enables the timer 
test mode. TEST is a read/write bit in mode 0 and 
is set during reset. 

TEST=0 — Timer test mode enabled: 
a) The timer LSB latch is transparent, which 
allows the LSB to be read independently of 
the MSB. 



MOTOROLA MICROPROCESSOR DATA 
3-156 



MC6801U4/6803U4 



b) Either the MSB or the LSB of the timer is 
clocked by E, as defined by the CLOCK bit. 

TEST = 1 — Timer test mode disabled. 

Bits 2-7 See TIMER CONTROL REGISTER 2 (Nontest 
Modes). (These bits function the same as in the 
nontest modes.) 



Timer Status Register (TSR) ($19) 

The timer status register is an 8-bit read-only register 
which contains the flags associated with the free-running 
counter, the output compare registers, and the input cap- 
ture registers. 

TIMER STATUS REGISTER 



7 


6 


5 4 


3 2 1 


0 


ICF2 


ICF1 


0CF3 | 0CF2 


0CF1 | TOF 


1 


1 



$19 



Bits 0-1 Not used. 

Bit 2 Timer Overflow Flag — The TOF is set when the 
counter contais all ones ($FFFF). It is cleared by 
reading the TSR or the TCSR (with TOF set) and 
then the counter high byte ($09), or during reset. 
Refer to TIMER CONTROL AND STATUS REG- 
ISTER (TCSR) ($08). 

Bit 3 Output Compare Flag 1 — OCF1 is set when out- 
put compare register 1 matches the free-running 
counter. OCF1 is cleared by reading the TSR or 
the TCSR (with OCF1 set) and then writing to 
output compare register 1 ($0B or $0C), or during 
reset. Refer to TIMER CONTROL AND STATUS 
REGISTER (TCSR) ($08). 

Bit 4 Output Compare Flag 2 — OCF2 is set when out- 
put compare register 2 matches the free-running 
counter. OCF2 is cleared by reading the TSR (with 
OCF2 set) and then writing to output compare 
register 2 ($1A or $1B), or during reset. 

Bit 5 Output Compare Flag 3 — OCF3 is set when out- 
put compare register 3 matches the free-runing 
counter. OCF3 is cleared by reading the TSR (with 
OCF3 set) and then writing to output compare 
register 3 ($1C or $1D), or during reset. 

Bit 6 Input Capture Flag 1 — ICF1 is set to indicate that 
a proper level transition has occurred; it is cleared 
by reading the TSR or the TCSR (with ICF1 set) 
and the input capture register 1 high byte ($0D), 
or during reset. Refer to TIMER CONTROL AND 
STATUS REGISTER (TCSR) ($08). 

Bit 7 Input Capture Flag 2 — ICF2 is set to indicate that 
a proper level transition has occurred; it is cleared 
by reading the TSR (with ICF2 set) and the input 
capture register 2 high byte ($1 E), or during reset. 



SERIAL COMMUNICATIONS INTERFACE 

A full-duplex asynchronous SCI is provided with two 
data formats and a variety of rates. The SCI transmitter 
and receiver are functionally independent but use the 
same data format and bit rate. Serial data formats include 
standard mark/space (NRZ) and biphase; both provide 
one start bit, eight data bits, and one stop bit. "Baud" 
and "bit rate" are used synonymously in the following 
description. 

WAKE-UP FEATURE 

In a typical serial loop multiprocessor configuration, 
the software protocol will usually identify the addres- 
see^) at the begining of the message. To permit unin- 
terested MPUs to ignore the remainder of the message, 
wake-up feature is included whereby all further SCI re- 
ceiver flag (and interrupt) processing can be inhibited 
until its data line goes idle. An SCI receiver is re-enabled 
by an idle string of eleven consecutive ones or during 
reset. Software must provide for the required idle string 
between consecutive messages and must prevent it within 
messages. 

PROGRAMMABLE OPTIONS 

The following featues of the SCI are programmable: 

• Format: standard mark/space (NRZ) or biphase 

• Clock: external or internal bit rate clock 

• Baud: one of eight per E clock frequency or ex- 
ternal clock (x8 desired baud) 

• Wake-Up Feature: enabled or disabled 

• Interrupt Requests: enabled individually for trans- 
mitter and receiver 

. • Clock Output: internal bit rate clock enabled or 
disabled to P22 . 

SERIAL COMMUNICATIONS REGISTERS 

The SCI includes four addressable registers as depicted 
in Figure 22. It is controlled by the rate and mode control 
register and the transmit/receive control and status reg- 
ister. Data are transmitted and received utilizing a write- 
only transmit register and a read-only receive register. 
The shift registes are not accessible to software. 

Rate and Mode Control Register (RMCR) ($10) 

The rate and mode control register controls the SCI bit 
rate, format, clock source, and, under certain conditions, 
the configuration of P22. The register consists of five 
write-only bits which are cleared during reset. The two 
least-significant bits, in conjunction with bit 7, control the 
bit rate of the internal clock, and the remaining two bits 
control the format and clock source. 

RATE AND MODE CONTROL REGISTER 




7 


6 


5 


4 


3 


2 


1 


0 


EBE 


X 


X 


X 


CC1 


CCO 


SSI 


sso 



$10 



Bit 1 :Bit 0 SSI :SS0 Speed Select — These two bits select 
the baud when using the internal clock. Eight 



MOTOROLA MICROPROCESSOR DATA 
3-157 



MC6801U4/6803U4 



Bit 7 



Rate and Mode Control Register Bit 0 



EBE 




CC1 


CCO 


SS1 


SSO 


Transmit/ Receive Control and Status Register 


RDRF 


ORFE 


TDRE 


RIE 


RE 


TIE 


TE 


WU 



Receive Data Register 



Port 2 



Rx 
Bit 
3 



$12 



(Not Addressable) 



Receive Shift Register 




Clock 
Bit 
2 



10 



Bit Rate 
Generator 



Tx 
Bit 
4 



\ r (Not Addressable) 



Transmit Shift Register 



i 



$13 



Transmit Data Register 
Figure 22. SCI Registers 



rates may be selected (in conjunction with bit 
7) which are a function of the MCU input fre- 
quency. Table 6 lists bit times and rates for 
three selected MCU frequencies. 

Bit 3. Bit 2 CC1-.CC0 Clock Control and Format Select — 

These two bits control the format and select 
the serial clock source. If CC1 is set, the DDR 
value for P22 is forced to the complement of 
CCO and cannot be altered until CC1 is cleared. 
If CC1 is cleared after having been set, its DDR 
value is unchanged. Table 7 defines the for- 
mats, clock source, and use of P22. 



Bits 4-6 



Bit? 



Bit 1: Bit 1 
Bit 1 : Bit 1 



Not used. 

EBE Enhanced Baud Enable — EBE selects the 
standard MC6801 baud rates when clear and 
the additional baud rates when set (Table 6). 
This bit is cleared by reset and is a write-only 
control bit. 

EBE = 0 standard MC6801 baud rates 

EBE = 1 additional baud rates 



Ifboth CCI and CCO are set, an external TTL-compatible 
clock must be connected to P22 at eight times (8x) the 
desired bit rate, but not greater than E, with a duty cycle 



of 50% ( ± 1 0%). If CC1 :CC0 = 1 0, the internal bit rate clock 
is provided at P22 regardless of the values for TE or RE. 

NOTE 

The source of SCI internal bit rate clock is the 
timer free-running counter. An MPU write to the 
counter in mode 0 can disturb serial operations. 

Transmit/Receive Control and Status Register (TRCSR) 
($11) 

The transmit/ receive control and status register con- 
trols the transmitter, receiver, wake-up feature, and two 
individual interrrupts, and monitors the status of serial 
operations. All eight bits are readable; bits 0 to 4 are also 
writable. The register is initialized to $20 by RESET. 

TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


RDRF 


ORFE 


TDRE 


RIE 


RE 


TIE 


TE 


WU 



$11 



Bit 0 Wake-Up on Idle Line — When set, WU enables the 
wake-up function; it is cleared by eleven consecu- 
tive ones or during reset. WU will not be set if the 
line is idle. Refer to WAKE-UP FEATURE. 

Bit 1 Transmit Enable — When set, P24 DDR bit is set, 
cannot be changed, and will remain set if TE is 



MOTOROLA MICROPROCESSOR DATA 
3-158 



MC6801U4/6803U4 
Table 6. SCI Bit Times and Rates 



EBE 


SS1:SS0 


4f 0 — 


2.4576 MHz 


4.0 MHz 


4.9152 MHz 


E 


614.4 kHz 


1.0 MHz 


1.2288 MHz 


Baud 


Time 


Baud 


Time 


Baud 


Time 


0 


0 


0 


+ 16 


38400.0 


26 


62500.0 


16.0 ps 


76800.0 


1 13.0 M s! 


0 


0 


1 


+ 128 


4800.0 


208.3 us 


7812.5 


128.0 its 


9600.0 


104.2 us 


0 


1 


0 


+ 1024 


600.0 


1.67 ms 


976.6 


1.024 ms 


1200.0 


833.3 us 


0 


1 


1 


+ 4096 


150.0 


6.67 ms 


244.1 


4.096 ms 


300.0 


3.33 ms 


1 


0 


0 


+ 64 


9600.0 


104.2 ,ts 


15625.0 


64 fiS 


19200.0 


52.0 lis 


1 


0 


1 


+ 256 


2400.0 


416.6 us 


3906.3 


256 fis 


4800.0 


208.3 its 


1 


1 


0 


+ 512 


1200.0 


833.3 /is 


1953.1 


512 lis 


2400.0 


416.6 /is 


1 


1 


1 


+ 2048 


300.0 


3.33 ms 


488.3 


2.05 ms 


600.0 


1.67 ms 


External (P22)* 


76800.0 


13.0 its 


125000.0 


8.0 us 


153600.0 


6.5 us 



* Using maximum clock rate 



Table 7. SCI Format and Clock Source Control 



CC1:CC0 


Format 


Clock 
Source 


Port 2 
Bit 2 


00 


Biphase 


Internal 


Not Used 


01 


NRZ 


Internal 


Not Used 


10 


NRZ . 


Internal 


Output 


11 


NRZ 


External 


Input . 



subsequently cleared. When TE is changed from 
clear to set, the transmitter is connected to P24 and 
a preamble of nine consecutive ones is transmitted. 
TE is cleared during reset. 

Bit 2 Transmit Interrupt Enable — When set, an IRQ2 is 
set; when clear, the interrupt is inhibited. TE is 
cleared during reset. 

Bit 3 Receive Enable — When set, the P23 DDR bit is 
cleared, cannot be changed, and will remain clear 
if RE is subsequently cleared. While RE is set, the 
SCI receiver is enabled. RE is cleared during reset. 

Bit 4 Receiver Interrupt Enable — When set, an IRQ2 
interrupt is enabled when RDRF and/or ORFE is set; 
when clear, the interrupt is inhibited. RIE is cleared 
during reset. 

Bit 5 Transmit Data Register Empty — TDRE is set when 
the transmit data register is transferred to the out- 
put serial shift register or during reset. It is cleared 
by reading the TRCSR (with TDRE set) and then 
writing to the transmit data register. Additional data 
will be transmitted only if TDRE has been cleared. 

Bit 6 Overrun Framing Error — If set, ORFE indicates 
either an overrun or framing error. An overrun is 
a new byte ready to transfer to the receiver data 
register with RDRF still set. A receiver framing error 
has occurred when the byte boundaries of the bit 
stream are not synchronized to the .bit counter. An 
,., overrun can be distinguished from a framing error 
by the state of RDRF: if RDRF is set, then an overrun 



has occurred; otherwise, a framing error has been 
detected. Data are not transferred to the receive 
data register in an overrun condition. Unframed 
data causing a framing error are transferred to the 
receive data register. However, subsequent data 
transfer is blocked until the framing error flag is 
cleared. ORFE is cleared by reading the TRCSR (with 
ORFE set) then the receive data register, or during 
reset. 

Bit 7 Receive Data Register Full — RDRF is set when the 
input serial shift register is transferred to the receive 
data register, or during reset. 

SERIAL OPERATIONS 

The SCI is initialized by writing control bytes first to 
the rate and mode control register and then to the trans- 
mit/receive control and status register. When TE is set, 
the output of the transmit serial shift register is connected 
to P24, and serial output is initiated by transmitting a 9- 
bit preamble of ones. 

At this point, one of two situations exists: 1) if the 
transmit data register is empty (TDRE = 1), a continuous 
string of ones will be sent indicating an idle line; or 2) if 
a byte has been written to the transmit data register 
(TDRE = 0), it will be transferred to the output serial shift 
register (synchronized with the bit rate clock), TDRE will 
be set, and transmission will begin. 

The start bit (0), eight data bits (beginning with bit 0), 
and a stop bit (1) will be transmitted. If TDRE is still set 
when the next byte transfer occurs, ones will be sent until 
more data is provided. In biphase format, the output tog- 
gles at the start of each bit and at half-bit time when a 
one is sent. Receive operation is controlled by RE, which 
configures P23 as an input and enables the receiver. SCI 
data formats are illustrated in Figure 23. 



INSTRUCTION SET 

The MC6801U4/MC6803U4 is directly source compat- 
ible with the MC6801 and upward source and object code 
compatible with the MC6800. Execution times of key in- 
structions have been reduced, and several instructions 
have been added, including a hardware multiply. A list 



MOTOROLA MICROPROCESSOR DATA 
3-159 



MC6801U4/6803U4 



"<=' uinrLruimruuiriri 

1 1 i i • i i 

I | ! i : 

_TLT 



NRZ 

Format 



Biphase 
Format 



uirLJirLiui_rLn_ni 



Bit Bit 
Idle Start n , . „ c c Stop 



Data; 01001101 (S4D) 



0 1 2 3 4 5 6 7 



Figure 23. SCI Data Formats 



of new operations added to the MC6800 instruction set 
is shown in Table 1. 

In addition, two special opcodes, 4E and 5E, are pro- 
vided for test purposes. These opcodes force the program 
counter to increment like a 16-bit counter, causing ad- 
dress lines used in the expanded modes to increment 
until the device is reset. These opcodes have no mne- 
monics. 

The coding of the first (or only) byte corresponding to 
an executable instruction is sufficient to identify the in- 
struction and the addressing mode. The hexadecimal 
equivalents of the binary codes, which result from the 
translation of the 82 instructions in all valid modes of 
addressing, are shown in Table 8. There are 220 valid 
machine codes, 34 unassigned codes, and 2 codes re- 
served for test purposes. 

PROGRAMMING MODEL 

A programming model for the MC6801U4/MC6803U4 
is shown in Figure 8. Accumulator A can be concatenated 
with accumulator B and jointly referred to as accumulator 
D where A is the most-significant byte. Any operation 
that modifies the double accumulator will also modify 
accumulators A and/or B. Other registers are defined as 
follows: 

Program Counter 

The program counter is a 16-bit register which always 
pbints to the next instruction. 

Stack Pointer 

The stack pointer is a 16-bit register which contains the 
address of the next available location in a pushdown/ 
pullup (LIFO) queue. The stack resides in random-access 
memory at a location defined by the programmer. 

Index Register 

The index register is a 16-bit register that can be used 
to store data or provide an address for the indexed mode 
of addressing. 

Accumulators 

The MPU contains two 8-bit accumulators, A and B, 
which are used to store operands and results from the 



arithmetic logic unit (ALU). They can also be concaten- 
ated and referred to as the D (double) accumulator. 

Condition Code Register 

The condition code register indicates the results of an 
instruction and includes the following five condition bits: 
negative (N), zero (Z), overflow (V), carry/borrow from 
MSB (C), and half carry from bit 3 (H). These bits are 
testable by the conditional branch instructions. Bit 4 is 
the interrupt mask (I bit) and inhibits all maskable inter- 
rupts when set. The two unused bits, B6 and B7, are read 
as ones. 

ADDRESSING MODES 

Six addressing modes can be used to reference mem- 
ory. A summary of addressing modes for all instructions 
is presented in Table 9, 10, 11, and 12; execution times 
are provided in E cycles. Instruction execution times are 
summarized in Table 13. With an input frequency of 4 
MHz, one E cycle is equivalent to one microsecond. A 
cycle-by-cycle description of bus activity for each instruc- 
tion is provided in Table 14; descriptions of selected in- 
structions are shown in Figure 24. 

Immediate Addressing 

The operand or "immediate byte(s)" is contained in the 
following byte(s) of the instruction where the number of 
bytes matches the size of the register. These are two- or 
three-byte instructions. 

Direct Address 

The least-significant byte of the operand address is 
contained in the second byte of the instruction, and the 
most-significant byte is assumed to be $00. Direct ad- 
dressing allows the user to access $00 through $FF, using 
two-byte instructions, and execution time is reduced by 
eliminating the additional memory access. In most ap- 
plications, the 256-byte area is reserved for frequently 
referenced data. 

Extended Addressing 

The second and third bytes of the instruction contain 
the absolute address of the operand. These are three- 
byte instructions. 



MOTOROLA MICROPROCESSOR DATA 
3-160 



3 



MC6801U4/6803U4 



Table 8. CPU Instruction Map 



_0P_ 


MNEM 


MODE 




— L 


_0P_ 


— MNEM 


MODE - 


— L. 


-2L- 


MNEM 


MODE 




L 




MNEM 


MODE 




— — 


_OP_ 


— MNEM 


MODE 







00 


• 










34 


DES 


INHER 3 


1 


68 


ASL 


INDXD 


6 


2 


9C 


CPX 


DlR 


5 


2 


DO 


SUBB 


DlR 


3 


2 


01 


NOP 


INHER 


2 


1 


35 


TXS 




I 3 


i 


69 


ROL 


i 




6 


2 


90 


JSR 






5 


2 


D1 


CMPB 






3 


2 


02 


• 


i 








36 


PSHA 






i 


6A 


DEC 






6 


2 


9E 


LDS 


! 


S 


4 


2 


D2 


SBCB 






3 


2 


03 


• 










37 


PSHB 






1 


6B 


• 










9F 


STS 


DlR 


4 


2 


D3 


ADDD 






5 


2 


04 


LSRD 






3 


i 


38 


PULX 




5 


1 


6C 


INC 






6 


2 


AO 


SUBA 


INDXD 


4 


2 


D4 


ANDB 






3 


2 


06 


ASLD 






3 


i 


39 


RTS 




5 


1 


6D 


TST 






6 


2 


A1 


CMPA 






4 


2 


D5 


BITB 






3 


2 


06 


TAP , 






2 


1 


3A 


ABX 




3 


i 


6E 


JMP 


\ 




3 


2 


A2 


SBCA 






4 


2 


D6 


LDAB 






3 


2 


07 


TPA 






2 


i 


3B 


RTI 




10 


1 


6F 


CLR 


INDXD . 


6 


2 


A3 


SUBD 






6 


2 


D7 


STAB 






3 


2 


08 


INX 






3 


i 


3C 


PSHX 




4 


1 


70 


NEG 


EXTND 


6 


3 


A4 


ANDA 






4 


2 


D8 


EORB 






'■ 3 


2 


09 


DEX 






3 


1 


3D 


MUL 




10 


1 


71 


• 


i 








A5 


BITA 






4 


2 


D9 


ADCB 






3 


2 


OA 


CLV 






2 


i 


3E 


WAI 




9 


1 


72 


* 










A6 


LDAA 






4 


2 


DA 


ORAB 






3 


2 


OB 


SEV 






2 


1 


3F 


SWI 




12 


i 


73 


COM 






6 


3 


A7 


STAA 






4 


2 


DB 


ADDB 






3 


2 


OC 


CLC 






2 


1 


40 


NEGA 




2 


i 


74 


LSR 






■6 


3 


A8 


EORA 






4 


2 


DC 


LDD 






■ 4 


.2 


OD 


SEC 






2 


i 


41 


* 








75 


* 










A9 


ADCA 






4 


2 


DD 


STO 






4 


2 


OE 


CLI 






2 


i 


42 


* 








76 


ROR 






6 


3 


AA 


ORAA 






4 


2 


DE 


LDX 






4 


2 


OF 


SEI 






2 


i 


43 


COMA 




2 


i 


77 


ASR 






6 


3 


AB 


ADDA 






4 


2 


DF 


STX 


DlR 


4 


2 


10 


SBA 






2 


i 


44 


LSRA 




2 


i 


78 


ASL 






6 


3 


AC 


CPX 






6 


2 


EO 


SUBB 


INDXD 


4 


2 


11 


CBA 






2 


1 


45 


* 








79 


ROL 






6 


3 


AD 


JSR 






6 


2 


El 


CMPB 






4 


2 


12 


* 










46 


RORA 




2 


i 


7A 


DEC 






6 


3 


AE 


LDS 






5 


2 


E2 


SBCB 






4 


2 


13 


* 










47 


ASRA 






1 


7B 


* 










AF 


STS 


INDXD 


5 


2 


E3 


ADDD 






6 


2 


14 


* ' 










48 


ASLA 




2 


i 


7C 


' INC 






6 


3 


BO 


SUBA 


EXTND 


4 


3 


E4 


ANDB 






4 


2 


15 


• 










49 


ROLA 




2 


i 


7D 


TST 






6 


3 


Bl 


CMPA 


i 


i 


4 


3 


E5 


BITB 






4 


2 


16 


TAB 






2 


1 


4A 


DECA 




2 


1 ' 


7E 


JMP 


< 




3 


3 


B2 


SBCA 






4 


3 


E6 


LDAB 






4 


2 


17 


TBA 






2 


i 


4B 


'• 








7F 


CLR 


EX" 1 


ND 


6 


3 


B3 


SUBD 






6 


3 


E7 


STAB 






4 


2 


18 


* ' 


\ 








AC 


INCA 




2 


i 


80 


SUBA 


IMMED 


2 


2 


B4 


ANDA 






4 


3 


E8 


EORB 






4 


2 


19 


OAA 


INHER 


2 


1 


4D 


TSTA 




2 


i 


81 


CMPA 


. 




2 


2 


B5 


BITA 






4 


3 


E9 


ADCB 








2 


1A 


• 










4E 


T 








82 


SBCA 






2 


2 


B6 


LDAA 






4 


3 


EA 


ORAB 






4. 


2 


1B 


ABA 


INHER 


2 


i 


4F 


Cl.RA 




2 


1 


83 


SUBQ 






4 


3 


B7 


STAA 






4 


3 


EB 


ADDB 






4 


2 


1C 


• 










50 


NEGB 




2 


i 


84 


ANDA 






2 


2 


B8 


EORA 






4 


3 


EC 


LDD 






5 


2 


1D 


• 










51 


• 








85 


BITA 






2 


2 


B9 


ADCA 






4 


3 


ED 


STD 






5 


2 


IE 


• 










52 


• 








86 


LDAA 






2 


2 


BA 


ORAA 






4 


3 


EE 


LDX 






5 


2 


IF 


• 










53 


COMB 




2 


i 


87 


• 










BB 


ADDA 






4 


3 


EF 


STX 


INDXD 


5 


2 


20 


BRA 


REL 


3 


2 


54 


LSRB 




2 


i 


88 


. EORA 






2 


2 


BC 


CPX 






6 


3 


FO 


SUBB 


EXTND 


4 


3 


21 


BRN 


/ 




3 


2 


55 


• 








89 


ADCA 






2 


2 


BD 


JSR 






6 


3 


Fl 


CMPB 






4 


3 


22 


BHl 






3 


2 


56 


RORB 




2 


i 


8A ■ 


OR AA 






2 


2 


BE 


LDS 




' 


5 


3 


F2 


SBCB 






4 • 


3 


23 


BLS 






3 


2 


57 


ASRB- 




2 


i 


8B 


ADDA 






2 


2 


BF 


STS 


EXTND 


5 


3 


F3 


ADDD 






6' '■ 


3 


24 


BCC 






3 


2 


58 


ASLB 




2 


i 


8C 


CPX 


IMMED 


4 


3 


CO 


SUBB 


IMMED 


2 


2 


F4 


ANDB 






4 


,3' ■ 


25 


BCS 






3 - 


2 


59 


ROLB 




2 


1 


8D 


BSR' 


REL 




6 


2 


C1 


CMPB 


1 


i' ■ 


2 


2 


F5 


BITB 






4 


3 . 


26 


BNE . 






3 


2 


5A 


DECS 




2 


i 


8E 


IDS 


IMMED 


3 


3 


C2 


SBCB 






2 


2 


F6 


LDAB ' 






4 


3 


27 


BEQ 






3 


2 


5B 


• 








8F 


• 










C3 


ADDD 






4 


3 


F7 


STAB 






4 


3 


28 


BVC 






3 


2 


5C 


I'NCB 




2 


i 


90 


SUBA 


DlR 




3 


2 


C4 


ANDB 






2 


2 


F8 


EORB 






4 


3 




















2 








i 
































2A 


BPL 






3 


2 


5E 


T 


1 


r 




92 


SBCA 






3 


2 


C6 


LDAB 






2 


2. 


FA 


ORAB 






4 




2B 


BMI 






3 


2 


5F 


CLRB 


INHER 2 


i 


93 


SUBD 






5 


2 


C7 












FB 


ADDB 






4 




2C 


BGE 






3 


2 


60 


NEG 


INDXD 6 


2 


94 


ANDA 






3 


2 


C8 


EORB 






2 


2 


FC 


LDD 










2D 


BLT 






.3 


2 


61 




i 






95 


BITA 






3 


2 


C9 


ADCB 






2 


2 


FD 


STC 










2E 


BGT 




1 


3 


2 


62 










96 


LDAA 






3 


2 


CA 


ORAB 






2 


2 


FE 








5 .. 




2F 


BLE 


REL 


3 


2 


63 


COM 




6 


".2 ' 


97 


STAA 






3 


2 


CB 


ADDB 






2 


2 


FF 




ExTNC 




3 


30 


TSX 


INHER 


3 


1 


64 


LSR 




6 


2 


98 


EORA 






3 


2 


CC 


LDD 






3 


3 














31 


INS 






3 


1 


65 . 










99 


ADCA 






3 


2 


CD 






f 








* r z 


NED OP 


CODE 




32 


P'JLA 


1 




4 


1 


66 


ROR 




f 6 


2 


9A 


ORAA 






3 


2 


CE 


LDX 


IMMED 


3 


3 














33 


PULB 






4 


1 


67 


ASR 


NDXD 6 


2 


9B 


ADDA 






3 


2 


CF 

























NOTES: . 
1. Addressing Modes: 

INHER = Inherent INDXD = Indexed IMMED = Immediate 

REL = Relative EXTND = Extended DlR = Direct 



2. Unassigned opcodes are indicated by "•" and should not be executed. 

3. Codes marked by "T" force the PC to function as a 16-bit counter. 

Indexed Addressing 

The unsigned offset contained in the second byte of 
the instruction is added with carry to the index register 
and is used to reference memory without changing the 
index register. These are two-byte instructions. 

Inherent Addressing 

The operand(s) is a register, and no memory reference 
is required. These are single-byte instructions. 

Relative Addressing 

Relative addressing is used only for branch instruc- 
tions. If the branch condition is true, the program counter 



is overwritten with the sum of signed single-byte dis- 
placement in the second byte of the instruction and the 
current program counter. This provides a branch range 
of — 1 26 to +129 bytes from the first byte of the instruc- 
tion. These are two-byte instructions. 

SUMMARY OF CYCLE-BY-CYCLE OPERATION 

Table 14 provides a detailed description of the infor- 
mation present on the address bus, data bus, and the 
read/write (R W) line during each cycle of instruction. 

The information is useful in comparing actual results 
with expected results during debug of both software and 



MOTOROLA MICROPROCESSOR DATA 
3-161 



MC6801U4/6803U4 
Table 9. Index Register and Stack Manipulation Instructions 



3 



Pointer Operations 


MNEM 


Immed 


Direct 


Index 


Extnd 


Inherent 


Boolean/ 
Arithmetic Operation 


Condition Codes 














fin 

up 




ff 


fin 

up 




| 


Op 




0 


fin 
up 




0 


fin 

up 




0 




— 


~n" 


Y 


— 


"c" 


Compare Index Register 


CPX 


8C 


j 


3 


9C 


5 


2 


AC 




2 


BC 


g 


3 








X_ M:M+ 1 


— 




t 


y 




t 
* 


Decrement Index Register 


DEX 


























09 


3 


1 


X- 1 — »X 








y 

— 






Decrement Stack Pointer 


DES 


























34 


3 


1 


SP- 1 — *SP 




# 


• 




• 


^ 


Increment Index Register 


I NX 


























08 


3 


1 


X+1— X 


• 


• 


• 


i 


• 


• 


Increment Stack Pointer 


INS 


























31 


3 


1 


1 SP+1— SP 














Load Index Register 




CE 


3 


3 


DE 


4 


2 


EE 


5 


2 


FE 


5 


3 








m — ■* y . > t m j. 1 \ — — » y i 

PVi ^A|-j,liVI-r 1/ A [_ 


• 


• 


t 




R 


• 


Load Stack Pointer 


LDS 


8E 


3 


3 


9E 


4 


2 


AE 


5 


2 


BE 


5 


3 








M — SP H ,(M + D — SP L 






I 




R 




Store Index Register 


STX 








DF 


4 


2 


EF 


5 


2 


FF 


5 


3 








X|_j M,Xl (M + 11 






J 




R 




Store Stack Pointer 


STS 








9F 


4 


2 


AF 


5 


2 


BF 


5 


3 








SP H — M,SP L — (M+ 1) 






t 




R 




Index Reg — Stack Pointer 


TXS 


























35 


3 


1 


X- 1 — SP 














Stack Pntr— 'Index Register 


TSX 


























30 


3 


1 


SP+1— X 






• 




• 




Add 


ABX 


























3A 


3 


1 


B + X — X 














Push Data 


PSHX 


























3C 


4 


1 


X L — M SP ,SP-1— SP 
X H — M S p,SP-1— SP 














Pull Data 


PULX 


























38 


5 


1 


SP+ 1 — SP,M SP - X H 
SP + 1 — SP.Msp— -X L 






• 




• 


• 



Table 10. Accumulator and Memory Instructions (Sheet 1 of 2) 



Accumulator and 
Memory Operations 


MNEM 


Immed 


Direct 


Index 


Extend 


Inher 


Boolean 
Expression 


Condition Codes 


5 


4 


3 


2 


1 


0 


Op 






Op 




# 


Op 






Op 






Op 




* 


H 


I 


N 


Z 


V 


C 


Add Accumulators 


ABA 


























1B 


2 


1 


A+B~— A 


t 




i 


t 


i 


t 


Add B to X 


ABX 


























3A 


3 


1 


00:B + X-»X 














Add with Carry 


ADCA 


89 


2 


2 


99 


3 


2 


A9 


4 


2 


B9 


4 


3 








A+M + C— »A 


i 




i 


i 




t 


ADCB 


C9 


2 


2 


D9 


3 


2 


E9 


4 


2 


F9 


4 


3 








B + M + C— »B 


t 




i 


t 




t 


Add 


ADDA 


8B 


2 


2 


9B 


3 


2 


AB 


4 


2 


BB 


4 


3 








A+M— »A 


t 




t 






t 


ADDB 


CB 


2 


2 


DB 


3 


2 


EB 


4 


2 


FB 


4 


3 








B+M— -A 


t 




t 






i 


Add Double 


ADDD 


C3 


4 


3 


D3 


5 


2 


E3 


6 


2 


F3 


6 


3 








D+M-.M + 1— "D 






t 


i 




i 


And 


ANDA 


84 


2 


2 


94 


3 


2 


A4 


4 


2 


B4 


4 


3 








A.M— -A 






t 


i 


R 




ANDB 


C4 


2 


2 


D4 


3 


2 


E4 


4 


2 


F4 


4 


3 








B'M —* B 






t 


t 


R 




Shift Left, Arithmetic 


ASL 














68 


6 


2 


78 


6 


3 














t 


t 




t 


AS LA 


























48 


2 


1 


|cMIIIIIIII-o 






t 


J 




t 


ASLB 


























58 


2 


1 


b7 bO 






i 


1 




t 


Shift Left Double 


ASLD 


























05 


3 


1 








t 


t 




J 


Shift Right, Arithmetic 


ASR 














67 


6 


2 


77 


6 


3 














J 


t 




i 


ASRA 


























47 


2 


1 


^IllllllbW 






J 


t 




t 


ASRB 


























57 


2 


1 


b7 b0 






t 


t 


t 


t 


Bit Test 


BITA 


85 


2 


2 


95 


3 


2 


A5 


4 


2 


B5 


4 


3 








A.M 






{ 


t 


R 




BITB 


C5 


2 


2 


D5 


3 


2 


E5 


4 


2 


F5 


4 


3 








B'M 






t 


t 


R 




Compare Accumulators 


CBA 


























11 


2 


1 


A-B. 






t 


t 


t 


l 


Clear 


CLR 














6F 


6 


2 


7F 


6 


3 








00 — M 






R 


s 


R 


R 


CLRA 


























4F 


2 


1 


00 — A 






R 


s 


R 


R 


CLRB 


























5F 


2 


1 


00 — B 






R 


s 


R 


R 


Compare 


CMPA 


81 


2 


2 


91 


3 


2 


A1 


4 


2 


B1 


4 


3 








A-M 






t 


t 


t 


t 


CMPB 


C1 


2 


2 


D1 


3 


2 


El 


4 


2 


F1 


4 


3 








B-M 






J 


t 


t 


t 


1's Complement 


COM 














63 


6 


2 


73 


6 


3 








M — M 






i 


t 


R 


S 


COMA 


























43 


2 


1 


A — A 






t 


t 


R 


S 


COMB 


























53 


2 


1 


B — B 






t 


t 


R 


s 



MOTOROLA MICROPROCESSOR DATA 
3-162 



MC6801U4/6803U4 
Table 10. Accumulator and Memory Instructions (Sheet 2 of 2) 



3 



Accumulator and 
Memory Operations 




Immed 


Direct 


Index 


Extend 


Inher 


Boolean 


Condition Codes 


5 


4 


3 


2 


1 


0 


MNEM 


Op 






On 
up 






Od 




0 


fin 
up 






Op 






Expression 


H 


I 


N 


z 


v 


c 


Decimal Adjust, A 


DAA 


























19 


2 




Adj binary sum to BCD 










t 


t 


Decrement 


DEC 














6A 


Q 


2 


7A 


Q 


3 








M-l — »M 


a 


. 


1 


4 


t 




DECA 


























4A 


2 


— 


A- 1 — ► A 






j 


4 


t 




DECB 


























5A 


2 


1 


B- 1 — *B 






4 


4 


J 




Exclusive OR 


EORA 


88 


2 


2 


98 


3 


2 


A8 


4 


2 


B8 


4 


3 








A© M — A 






-r 


j 


R 




EORB 


C8 


2 


2 


D8 


3 


2 


E8 


4 


2 


F8 


4 


3 








B © M— ►B 








4 


R 




Increment 


INC 














6C 


g 


2 


7C 


g 


3 








M+ 1 — M 






t 


j 


J 




INCA 


























4C 


2 


1 


A+ 1 —A 








4 


J 




INCB 


























5C 


2 


1 


B+ 1 — ► B 






♦ 


4 


t 




Load Accumulators 
Load Double 


LDAA 


86 


2 


2 


96 


3 


2 


A6 


4 


2 


B6 


4 


3 








M— »A 






-r 


4 


R 




LDAB 


C6 


2 


2 


D6 


3 


2 


E6 


4 


2 


F6 


4 


3 








M— *B 






■v 


4 


R 




LDD 


CC 


3 


3 


DC 


4 


2 


EC 


5 


2 


FC 


5 


3 








M:M+ 1 — *D 






t 


4 


R 




Logical Shift, Left 


LSL 














68 


g 


2 


78 


g 


3 








EH 1 1 1 1 1 1 1 1 *-° 

b7 bO 


r-7- 




4 


4 




t 


LSLA 


























48 


2 


1 






1 


j" 


4 


( 


LSLB 


























58 


2 


1 . 


# 




♦ 


4 


J 


J 


LSLD 


























05 


3 


2 






j 


J 


J 


J 


Shift Right, Logical 


LSR 














64 


6 


2 


74 


6 


3 














R 


r 


4 


t 

t 


LSRA 


























44 


2 


1 


o — 1 1] M l MI-lcl 

1 1 1 1 1 1 1 1 1 LJ 






R 


j 


J 


t 


LSRB 


























54 


2 


1 


b7 bO 




m 


R 


j 


J 


| 


LSRD 


























04 


3 


1 




# 




R 


j 


j 


t 


Multiply 


MUL 
































Ax B — D 








. 




t 


2's Complement (Negate) 


NEG 














60 


6 


2 


70 


g 


3 








00- M — M 






4 


« 


4 


j 


NEGA 


























40 


2 


1 


00- A— ► A 






j 




j 


{ 


NEGB 


























50 


2 


1 


00- B — B 






j 


j 


J 


j 


No Operation 


NOP 


























01 


2 


1 


PC+ 1 — -PC 








1-7 




— 


Inclusive OR 


ORAA 


8A 


2 


2 


9A 


3 


2 


AA 


4 


2 


B A 


4 


3 








A* M — ► A 






-J- 


-r 






ORAB 


CA 


2 


2 


DA 


3 


2 


EA 


4 


2 


FA 


4 










B +■ M — B 






-J 


j 

— 






Push Data 
Pull Data 


PSHA 


























36 


3 


1 


A - * Stack 














PSHB 


























37 


3 


1 


B ~ * Stack 






# 


# 


m 




PULA 


























32 


4 


1 


Stack — • A 














PULB 


























33 


4 




Stack — B 














Rotate Left 


ROL 














69 


g 


2 


79 


g 


3 














J 


4 


j 


I 


ROLA 


























49 


— 


— 


ici h 1 1 1 1 1 1 1 H c l 

LJ 1 I II II 1 1 I LJ 






4 


4 


4 


j 


ROLB 




























— 




b7 bO 






4 




j 


t 


Rotate Right 


ROR 














66 


g 


2 


76 


g 


— 














t 


j 


j 


t 


RORA 


























46 


2 


1 


IcUM M I 1 Mhlcl 

LJ 1 1 1 1 1 1 1 1 1 LJ 








4 


4 


j 


RORB 


























56 


2 


1 


ti7 Mi 






4 


j 


4 


t 


Subtract Accumulator 


SBA 
































A- B— »A 






4 


j 


J 


J 


Subtract with Carry 
Store Accumulators 


SBCA 


82 


— 


2 


92 


3 


— 


A2 


— : 


2 


B2 


— 










A - M - C — * A 






J 


j 


4 


j 


SBCB 


C2 


— 


2 




3 


— 


E2 


— 


2 




4 


— 








B - M - C — » B 






4 


4 


j 


I 


STAA 








97 


3 


2 


A7 


4 


2 


B7 


4 


3 








A— »M 






4 


J 


H 




STAB 








D7 


3 


2 


E7 


4 


2 


f; 


4 


3 








B — *M 






J 


J 


R 


. 


STD 








DD 


4 


2 


ED 


5 


2 


FD 


5 


3 








D — M M * 1 










R 




Subtract 


SUBA 


80' 


2 


2 


90 


3 


2 


AO 


4 


2 


B0 


4 


3 








A- M — A 










J 


t 


SUBB 


CO 


2 


2 


DO 


3 


2 


EO 


4 


2 


FO 


4 


3 








B- M — B 










t 


t 


Subtract Double 


SUBD 


83 


4 


3 


93 


5 




A3 


6 


2 


B3 


6 


3 








D- VI- Mf 1 — »D 










t 


I 


Transfer Accumulator 


TAB 


























16 


2 


1 


A— >B 










R 




TBA 


























17 


2 


1 


B — A 










R 




Test, Zero or Minus 


TST 














6D 


6 


2 


7D 


6 


3 








M- 00 










R 


R 


TSTA 


























4D 


2 


1 


A-00 










R 


R 


TSTB 


























5D 


2 


1 


B-00 










R 


R 



The condition code register notes are listed after Table 12. 



MOTOROLA MICROPROCESSOR DATA 
3-163 



MC6801U4/6803U4 



Table 11. Jump and Branch Instructions 

























Condition Code Reg. 






Direct 


Relative 


Index 


Extend 


Inherent 




5 


4 


3 


2 


1 


0 


Operations 


MNEM 


Op 






Op 




# 


Op 




tt 


Op 






Op 




H 


Branch Test 














Branch Always 


BRA 








20 


3 


2 




















None 














Branch Never 


BRN 








21 


3 


2 




















None 














Branch If. Carry Clear 


BCC 








24 


3 


2 




















C = 0 














Branch If: Carry Set 


BCS 








25 


3 


2 




















C=1 














Branch lf = Zero 


BEQ 








27 


3 


2 




















Z= 1 














Branch If aZero 


BGE 








2C 


3 


2 




















N ffi V = 0 














Branch If >Zero 


BGT 








2E 


3 


2 




















Z+ (N © V) = 0 














Branch If Higher 


BHI 








22 


3 


2 




















C + Z = 0 














Branch If Higher or Same 


BHS 








24 


3 


2 




















C = 0 














Branch If sZero 


BLE 








2F 


3 


2 




















Z+ IN ® V) = 1 














Branch If Carry Set 


BLO 








25 


3 


2 




















C= 1 














Branch If Lower Or Same 


BLS 








23 


3 


2 




















C + Z= 1 














Branch If <Zero 


BIT 








2D 


3 


2 




















N © V = 1 














Branch If Minus 


BMI 








2B 


3 


2 




















N= 1 














Branch If Not. Equal Zero 


BNE 








26 


3 


2 




















Z = 0 














Branch If Overflow Clear 


BVC 








28 


3 


2 




















V = 0 














Branch If Overflow Set 


BVS 








29 


3 


2 




















V= 1 














Branch If Plus 


BPL 








2A 


3 


2 




















N = 0 














Branch To Subroutine 


BSR 








8D 


6 


2 


































Jump 


JMP 














6E 


3 


2 


7E 


3 


3 








See Special Operations-Figure 24 














Jump To Subroutine 


JSR 


9D 


5 


2 








AD 


6 


2 


BD 


6 


3 






















No Operation 


NOP 


























01 


2 


1 
















Return From Interrupt 


RTI 


























3B 


10 


1 




t 


t 


t 


\ 


t 


t 


Return From Subroutine 


RTS 


























39 


5 


1 


See Special Operations-Figure 24 














Software Interrupt 


SWI 


























3F 


12 


1 






S 










Wait For Interrupt 


WAI 


























3E 


9 


1 

















Table 12. Condition Code Register Manipulation Instructions 



Operations 


Inherent 


Boolean Operation 


Condition Code Register 


5 


4 


3 


2 


1 


0 


MNEM 


Op 




n 


H 


1 


N 


Z 


V 


C 


Clear Carry 


CLC 


00 


2 


. 1 


0 — C 












R 


Clear Interrupt Mask 


CLI 


OE 


2 


1 


0— I 




R 










Clear Overflow 


CLV 


OA 


2 


i 


0 — V 








• 


R 


• 


Set Carry 


SEC 


OD 


2 


i ■ 


1 — c ■ 












s 


Set Interrupt Mask 


SEI 


OF 


2 


1 


' 1 — 1 




S 










Set Overflow 


SEV 


OB 


2 


■ 1 


1 —V ' 




• 






S 




Accumulator A — * OCR 


TAP 


06 


2 


1 


A— .CCR' 


J 


t 


1 


t 


J 


J 


CCR —"Accumulator A 


TPA 


07 


2 


1 


CCR— A 















LEGEND 

Op Operation Code (Hexadecimal) 

- Number of MPU Cycles 

M$p Contents of memory location pointed to by Stack Pointer 

# Number of Program Bytes .. . 
+ Arithmetic Plus 

- Arithmetic Minus 

• Boolean AND 

X : Arithmetic Multiply 

+ Boolean Inclusive OR 

® Boolean Exclusive OR 

M Complement of M 

— Transfer Into 

0 Bit = Zero 

00 Byte = Zero 



CONDITION CODE SYMBOLS 

H Half-carry from bit 3 

I Interrupt mask 

N Negative (sign bit) 

Z Zero (byte) 

V Overflow, 2's complement 

C Carry/ Borrow from MSB 

R Reset Always 

S Set Always " 

t Affected 

• Not Affected 



MOTOROLA MICROPROCESSOR DATA 
3-164 



MC6801U4/6803U4 



Table 13. Instruction Execution Times in E Cycles 





ADDRESSING MODE 


















Bdiat 




ided 


« 


'ent 


• 




E 


u 
a> 


• 


a 


• 


JO 




£ 


Dir 


Ext 


Ind 


Inh 


© 
K 


ABA 




• 


• 


• 


2 


• 


ABX 




• 


• 


• 


3 


• 


ADC 


2 


3 


4 


4 


• 


• 


ADD 




3 


, 4 


4 


• 


• 


ADDD 




5 


6 


6 


• 


• 


AND 


2 


3 


4 


4 


• 


• 


ASL 




• 


6 


6 


2 


• 


ASLD 


— - — ■ 


• 


• 


• 


3 


• 


ASR 




• 


6 


6 


2 


• 


BCC 




• 


• 


• 


• 


3 


BCS 




• 


• 


• 


• 


3 


BEQ 




• 


• 


• 


• 


3 


BGE 




• 


• 


• 


• 


3 


BGT 




• 


• 


• 


• 


3 


BHI 


— - — 


• 


• 


• 


• 


3 


BHS 




• 


• 


• 


• 


3 


BIT 










• 


• 


BLE 


* 

■ 


• 


• 


• 


• 


3 


BLO 




• 


• 


• 


■ • 


3 


BLS 




• 


• 


• 




3 


BLT 




• 


• 


• 


• 


3 


BMI 


— - — 


• 


• 


• 


• 


3 


BNE 




• 


• 


• 


• 


3 


BPL 




• 


• 


• 


• 


3 


BRA 




• 


• 




• 


3 


BRM 




• 


• 


• 


• 


3 


BSR 




• 


• 


• 


• 


6 


BVC 












3 


BVS 


— — ■ 










3 


CBA 










2 , 


• 


CLC 










2 


• 


CLI 










2 




CLR 






6 


6 


2 




CLV 






• 


• 


2 




CMP 






4 


4 


• 




COM 






6 


6 


2 




CPX 






6 


6 


• 




DAA 






• 


• 


2 




DEC 






6 


6 


2 




DES 






• 


• 


3 




DEX 






• 


• 


3 




EOR 






4 


4 


• 




INC 






6 


6 


• 




INS 






• 


• 


3 





ADDRESSING MODE 





.... 

Immediate 


Direct 


Extended 


Indexed 


Inherent 


Relative 


INX 


• 


• 


• 


• 


3 


• 


JMP 


• 


• 


3 


3 




• 


JSR 


• 


5 


6 


6 


• 


• 


LDA 


2 


3 


4 


4 


• 




LDD 


3 . 


4 


5 


5 


• 


• 


LDS 


3 


4 


5 


5 


• 


• 


LDX 


3 


4 


5 


5 


• 


• 


LSL 


• 


• 


6 


6 


2 


• 


LSLD 


• 


• 


• 


• 


3 


• 


LSR 


• 


• 


6 


6 


2 




LSRD 


• 


• 


• 


• 


3 


• 


MUL 




• 


• 


• 


10 


• 


NEG 


• 




6 




2 


• 


NOP 


• 


• 


• 


• 


2 


• 


ORA 






4 


4 


• 


• 


PSH 


• 


• 


• 


• 


3 


• 


PSHX 


• 


• 


• 


• 


4 


• 


PUL 


• 


• 


• 


• 


4 


• 


PULX 






- • 




5 




ROL 






6 




2 




ROR 






6 




2 




RTI 


— «r~ 


—J 


• 


• 


10 


—J— 


RTS 






• 




5 




SBA 






• 




2 




SBC 






4 




• 




SEC 










2 




SEI 






• 




2 




SEV 






• 




2 




STA 




3 


4 








STD 




4 


5 


5 






STS 




4 


5 


5 






STX 




4 


5 


5 






SUB 




3 


4 


4 






SUBD 




5 


6 


6 






SWI 










12 




TAB 
TAP 
TBA 
TPA 
TST 
TSX 
TXS 
WAI 










2 
2 
2 
2 
2 
3 
3 
9 





B 



MOTOROLA MICROPROCESSOR DATA 
3-165 



MC6801U4/6803U4 



Table 14. Cycle-By-Cycle Operation (Sheet 1 of 5) 



a 



Address Mode and 
Instructions 


Cycles 


Cycle 
# 


Address Bus 


R/W 
Line 


Data Bus 


IMMEDIATE 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB. 


2 


1 

2 


Opcode Address 
Opcode Address + 1 


1 
1 


Opcode 
Operand Data 


LDS 
LDX 
LDD 


3 


1 
2 
3 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 




Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


CPX. 

SUBD 

ADDD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Opcode Address + 2 
Address Bus FFFF 




Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


DIRECT 


MUt tUn 

ADD LDA ' 
AND ORA 
BIT SBC 
CMP SUB 




2 
3 


Opcode Address 
Opcode Address + 1 ' 
Address of Operand 




Opcode 

Address of Operand 
Operand Data 


STA. 


3/ 


1 
2 
3 


Opcode Address 
Opcode Address + 1 
Destination Address 




Opcode 

Destination Address 
Data from Accumulator 


LDS 
LDX 
LDD 


4 


1 

2 
3 
4 


Opcode Address : 
Opcode Address + 1 -. 
Address of Operand 
Operand Address +1 . 




Opcode 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 


STS 
STX 
STD 


4 


1 

2 
3 
4 


Opcode Address 
Opcode Address + 1 
Address of Operand 
Address of Operand + 1 




Opcode 

Address of Operand 

Register Data (High Order Byte) 

Register Data (Low Order Byte) 


CPX 

SUBD 

ADDD 


. 5 


1 

2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Operand Address 
Operand Address + 1 
Address Bus FFFF 




Opcode 

Address of Operand 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


JSR 


5 


1 

2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Subroutine Address 
Stack Pointer 
Stack Pointer- 1 


0 
0 


Opcode 

Irrelevant Data 

First Subroutine Opcode 

Return Address (Low Order Byte) 

Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-166 



MC6801U4/6803U4 



Table 14. Cycle-By-Cycle Operation (Sheet 2 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 


EXTENDED 


JMP 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Jump Address (High Order Byte) 






3 


Opcode Address +2 


1 


Jump Address (Low Order Byte) 


ADC EOR 


4 


1 


Opcode Address 


1 


Opcode 


ADD LDA 




2 


Opcode Address + 1 


1 


Address of Operand 


AND ORA 




3 


Opcode Address +2 


1 


Address of Operand (Low Order Byte) 


BIT SBC 




4 


Address of Operand 


1 


Operand Data 


CMP SUB 












STA 


4 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ 1 


1 


Destination Address (High Order Byte) 






3 


Opcode Address+2 


1 


Destination Address (Low Order Byte) 






4 


Operand Destination Address 




Data from Accumulator 


LDS 


5 


1 


Opcode Address 


1 


Opcode 


LDX 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


LDD 




3 


Opcode Address+2 


1 


Address of Operand (Low Order Byte) 






4 


Address of Operand 


1 


Operand Data (High Order Byte) 






5 


Address of Operand + 1 


1 


Operand Data (Low Order Byte) 


STS 


5 


1 


Opcode Address 


1 


Opcode 


STX 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


STD 




3 


Opcode Address + 2 


1 


Address of Operand (Low Order Byte) 






4 


Address of Operand 




Operand Data (High Order Byte) 






5' 


Address of Operand + 1 




Operand Data (Low Order Byte) 


ASL LSR 


6 


1 


Opcode Address 


1 


Opcode 


ASR NEG 




2 


Opcode Address* 1 


1 


Address of Operand (High Order Byte) 


CLR ROL 




3 


Opcode Address + 2 


1 


Address of Operand (Low Order Byte) 


COM ROR 




4 


Address of Operand 


1 


Current Operand Data 


DEC TST* 




5 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


INC 




6 


Address of Operand 




New Operand Data 


CPX 


6 


i 


Opcode Address 




Opcode 


SUBD 




2 


Opcode Address + .1.. 




Operand Address (High Order Byte) 


ADDD 




3 


Opcode Address + 2 




Operand Address (Low Order Byte) 






4 


Operand Address 




Operand Data (High Order Byte) 






5 


Operand Address + 1 




Operand Data (Low Order Byte) 






6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 


6 


1 


Opcode Address 




Opcode 






2 ; 


Opcode Address + 1 




Address of Subroutine. (High Order Byte) 






3 


Opcode Address + 2 




Address of Subroutine (Low Order Byte) 






4 


Subroutine Starting Address 




Opcode of Next Instruction 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer- 1 


0 


Return Address (High Order Byte) 



*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF. 



MOTOROLA MICROPROCESSOR DATA 
3-167 



MC6801U4/6803U4 
Table 14. Cycle-By-Cycle Operation (Sheet 3 of 5) 



a 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


» 


Address Bus 


Line 


Data Bus 


INDEXED 


JMP 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Offset 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


ADC EOR 


4 


1 


Opcode Address 


! 


Opcode 


ADD LDA 




2 


Opcode Address+1: 


1 


Offset 


AND ORA 




3 


Address Bus FFFF. 


1 


Low Byte of Restart Vector 


SIT SBC 




4 


Index Register Plus Offset 


1 


Operand Data 


CMP SUB 












STA 


4 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+1 


1 


Offset 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data 


LDS 


5 


1 


Opcode Address 


1 


Opcode 


LDX 




2 


Opcode Address+1 


-I 


Offset 


LDD 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Index Register Plus Offset 


1 


Operand Data (High Order Byte) 






5 


Index Register Plus Offset + 1 


1 


Operand Data (Low Order Byte) 


STS 


5 . 


1 


Opcode Address 


1 


Opcode 


STX 




2 


Opcode Address + 1 


1 


Offset 


STD 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data (High Order Byte) 






5 


Index Register Plus Offset + 1 




Operand Data (Low Order Byte) 


ASL LSR 


6 


1 


Opcode Address 


1 


Opcode 


ASR NEG 




2 


Opcode Address+1 


1 


Offset 


CLR ROL 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


COM ROR 




4 


Index Register Plus Offset 


1 


Current Operand Data 


DEC TST* 




5 


Address Bus FFFF 




Low Byte of Restart Vector 


INC 




6 


Index Register Plus Offset 




New Operand Data 


CPX 


6 


1 


Opcode Address 




Opcode 


SUBD 




2 


Opcode Address + 1 




Offset 


ADDD 




3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Index Register+ Offset 




Operand Data (High Order Byte) 






5 


Index Register + Offset +1 




Operand Data (Low Order Byte) 






6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 


6 


1 


Opcode Address 




Opcode 






2 


■Opcode Address + 1 




Offset 






3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Index Register + Offset 




First Subroutine Opcode 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer- 1 


0 


Return Address (High Order Byte) 



*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus=$FFFF. 



MOTOROLA MICROPROCESSOR DATA 
3-168 




MC6801U4/6803U4 



Table 14. Cycle-By-Cycle Operation (Sheet 4 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 


INHERENT 


ABA DAA SEC 


2 


1 


Opcode Address 


1 


Opcode 


ASL DEC -SEI 




2 


Opcode Address +1 


1 


Opcode of Next Instruction 


ASR INC SEV 












CBA LSR TAB 












CLC NEG TAP 












CLI NOP TBA 












CLR ROL TPA 












CLV ROR TST 












HJM DBA 












ABX 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Irrelevant Data 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


ASLD 


3 


1 


Opcode Address 


1 


Opcode 


LSRD 




2 


Opcode Address + 1 


] 


Irrelevant Data 






3 


Address Bus FFFF 




Low Byte of Restart Vector 


DES 


3 


1 


Opcode Address 


1 


Opcode 


INS 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Previous Stack Pointer Contents 




Irrelevant Data ... 


INX 


3 


1 


Opcode Address 


1 


Opcode 


DEX 




2 


Opcode Address* 1 


1 


Opcode of Next Instruction 






3 


Address Bus FFFF 


I . 


Low Byte of Restart Vector 


PSHA 


3 


1 


Opcode Address 


1 


Opcode 


PSHB 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Stack Pointer 




Accumulator Data 


TSX 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Stack Pointer 


1 


Irrelevant Data 


TXS 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


PULA 


4 


1 


Opcode Address 


1 


Opcode 


PULB 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Stack Pointer 


1 


Irrelevant Data 






4 


Stack Pointer+1 


1 


Operand Data from Stack 


PSHX 


4 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Irrelevant Data 






3 


Stack Pointer 




Index Register (Low Order Byte) 






4 


Stack Pointer - 1 




Index Register (High Order Byte) 


PULX 


5 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 




Irrelevant Data 






4 


Stack Pointer + 1 


1 


Index Register (High Order Byte) 






5 


Stack Pointer + 2 


1 


Index Register (Low Order Byte) 


RTS 


5 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 




Irrelevant Data 






4 


Stack Pointer + 1 




Address of Next Instruction (High Order Byte) 






5 


Stack Pointer + 2 




Address of Next Instruction (Low Order Byte) 


WAI 


9 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Opcode of Next Instruction 






3 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






5 


Stack Pointer- 2 


0 


Index Register (Low Order Byte) 






6 


Stack Pointer- 3 


0 


Index Register (High Order Byte) 






7 


Stack Pointer- 4 


0 


Contents of Accumulator A 






8 


Stack Pointer- 5 


0 


Contents of Accumulator B 






9 


Stack Pointer -6 


0 


Contents of Condition Code Register 



MOTOROLA MICROPROCESSOR DATA 
3-169 



MC6801U4/6803U4 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 


INHERENT 


MUL 


10 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 


1 


Irrelevant Data 






3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Address Bus FFFF : 


1 


Low Byte of Restart Vector 






5 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






6 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






7 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






8 


Address Bus FFFF 


] 


Low Byte of Restart Vector 






g 


Address Bus FFFF 






—_ 




10 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


nil 


10 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Irrelevant Data 






3 


Stack Pointer 


1 


Irrelevant Data 






4 


Stack Pointer + 1 


1 


Contents of Condition Code Register from Stack 






5 


Stack Pointer+2 


1 


Contents of Accumulator B from Stack 






6 


Stack Pointer + 3 


1 


Contents of Accumulator A from Stack 






7 


Stack Pointer + 4 


1 


Index Register from Stack (High Order Byte) 






8 


Stack Pointer + 5 


1 


Index Register from Stack (Low Order Byte) 






9 


Stack Pointer+6 


1 


Next Instruction Address from Stack (High Order Byte) 






10 


Stack Pointer+ 7 


1 ! 


Next Instruction Address from Stack (Low Order Byte) 


SWI 


12 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


Stack Pointer- 1 , 


0 


Return Address (High Order Byte) 






5 


Stack Pointer- 2 


0 


Index Register (Low Order Byte) 






6 


Stack Pointer -3 


0 


Index Register (High Order Byte) 






7 


Stack Pointer- 4 


0 


Contents of Accumulator A 






8 


Stack Pointer- 5 


0 


Contents of Accumulator B 






9 


Stack Pointer -6 


0 


Contents of Condition Code Register 






10 


Stack Pointer -7 


1 


Irrelevant Data 






11 


Vector Address FFFA (Hex) 


1 


Address of Subroutine (High Order Byte) 






12 


Vector Address FFFB (Hex) 


1 


Address of Subroutine (Low Order Byte) 


RELATIVE 


BCC BHT BNE BLO 


3 


1 


Opcode Address 


1 


Opcode 


BCS BLE BPL BHS 




2 


Opcode Address + 1 


1 


Branch Offset 


BEQ BLS BRA BRN 




3 


Address Buss FFFF 


1 


Low Byte of Restart Vector 


BGE BLT BVC 












BGT BMI BVS 












BSR 


6 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Branch Offset 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Subroutine Starting Address 


1 


Opcode of Next Instruction 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3^170 



JSR, Jump to Subroutine 



SWI, Software Interrupt 



BSR, Branch To Subroutine 
PC 



RTS, Return from Subroutine 
PC 



Main Program 



$90 = JSR 



Next Main Instr 



. = Direct Address 
Main Program 



Next Main Instr. 



Main Program 



$BD=JSR 



SH=Subr. Addr. 



SI_=Subr. Addr. 



Main Program 



$8D = BSR 



Next Main Instr. 



SP 
SP-2 
SP-1 

SP 



SP 
SP-2 
SP - 1 

SP 

S£ 

SP 
SP+ 1 
SP + 2 



PC 
RTN 



RTN H 



RTN L 



WAI, Wait for Interrupt 



PC. 
RTN 



RTI, Return from Interrupt 



RTN H 



RTN L 



JMP, Jump 



RTN H 



RTN L 



Legend: 

RTN = Address of next instruction in Main Program to be executed upon return from subroutine 
RTNh = Most significant byte of Return Address 
RTNl = Least significant byte of Return Address 
"— • = Stack Pointer After Execution 
K = 8-bit Unsigned Value 



Main Program 



$3F=SWI 



Main Program 



Interrupt Program 



$38= RT! 



Main Program 



$6E = JMP 



X+ K Next Instruction 



SP 


Stack 


SP-7 




SP-6 


Condition Code 


SP-5 


Acmltr B 


SP-4 


Acmltr A . 


SP-3 


Index Register (X^) 


SP-2 


Index Register (Xi_) 


SP-1 


RTNh 


SP 


rtn l 


SP 


Stack 


SP 




SP + 1 


1 Cpndit|on Code 


SP + 2 


Acmltr B 


SP + 3 


Acmltr A 


SP + 4 


Index Register (X(-|l 


SP + 5 


Index Register (X|J 


SP + 6 


RTN H 


SP + 7 


rtn l 


PC 


Main Program 




$7E = JMP 




Kh = Next Address 




K|_= Next Address 






I K 


Next Instruction 



o 

O) 

oo 



C 

00 

o 

CO 

c 



Figure 24. Special Operations 



CO 



MC6801U4/6803U4 




ORDERING INFORMATION 

The following information is required when ordering a 
custom MCU. The information may be transmitted to Mo- 
torola using the following media: 

MDOS, disk file 

PC-DOS disk file (360K) 

EPROM(s) Two 2516 or 2716,or a single 2532, 2732, 
or MC68701U4 
To initiate a ROM pattern for the MCU, it is necessary to 
first contact the local field-service office, sales person, or 
Motorola representative. 

FLEXIBLE DISKS 

Several types of flexible disks (MDOS® or PC-DOS disk 
file) may be submitted for pattern generation. They should 
be programmed with the customer's program, using po- 
sitive logic sense for address and data. The diskette should 
be clearly labeled with the customer's name, date, project 
or product name, and the filename containing the pattern. 

In addition to the program pattern, a file containing the 
program source code listing can be included. This data 
will be kept confidential and used to expedite the process 
in case of any difficulty with the pattern file. 

MDOS Disk File 

MDOS is Motorola's disk operating system available 
on the EXORciser development system. The disk media 
submitted must be a single-sided, single-density, 8-inch, 
MDOS-compatible floppy diskette. The diskette must 
contain the minimum set of MDOS system files in ad- 
dition to the pattern file. 

The .LO output of the M6801 cross assembler should 
be furnished. In addition, the file must be produced using 
the ROLLOUT command, so that it contains the absolute 
image of the M6801 memory. The entire memory image 
of both program and data space must be included. All 
unused bytes, including those in the user space, must be 
set to logic zero. 

PC-DOS Disk File 

PC-DOS is IBM® personal computer disk operating sys- 
tem. Submitted disk media must be standard-density 
(360K), double-sided, 5-1/4-inch-compatible floppy dis- 
kette. The diskette must contain the object file code in 
Motorola's S-record format. The S-record format is a 
chracter-based object fi|e format generated by M6801 
cross assemblers and linkers on IBM PC-style machines. 

EPROMS 

Two K of EPROM are necessary to contain the entire 
MC6801U4 program. Two 2516 or 2716 type EPROMS, a 



single 2532 or 2732 type EPROM, or an MC68701U4 can 
be submitted for pattern generation. The EPROM is pro- 
grammed with the customer program, using positive logic 
sense for address and data. Submissions on two EPROMs 
must be clearly marked. All unused bytes, including the 
user's space, must be set to zero. 

Whether the MC6801U4 MCU ROM pattern is submit- 
ted on a single 2532 or 2732 type EPROM, an MC68701 U4, 
or on two 2516 or 2716 type EPROMs, memory map ad- 
dressing is one-for-one. When using a single 2532 or 2732 
EPROM, the ROM pattern to be copied runs from EPROM 
address $000 to$FFF. If an MC68701U4 is used, the ROM 
map runs from $F000 to $FFFF. If a pair of 2516 or 2716 
type EPROMs is used, then they must be clearly marked; 
the data-space ROM runs from EPROM address $000 to 
$7FF, and the program-space ROM from $7FF to $FFF. 

For shipment to Motorola, EPROMs should be placed 
in a conductive IC carrier and packed securely. Styrofoam 
is not acceptable for shipment. 

VERIFICATION MEDIA 

All original pattern media, EPROMs or floppy disks, are 
filed for contractual purposes and are not returned. A 
computer listing of the ROM code will be generated and 
returned along with a listing verification form. The listing 
should be thoroughly checked and the verification form 
should be completed, signed, and returned to Motorola. 
The signed verification form constitutes the contractual 
agreement for the creation of the customer mask. To aid 
in the verification process, Motorola will program cus- 
tomer-supplied blank EPROM(s) or DOS disks from the 
data file used to create the custom mask. 

ROM VERIFICATION UNITS (RVUs) 

Ten MCUs containing the customer's ROM pattern will 
be sent for program verification. These units will have 
been made using the custom mask, but are for the pur- 
pose of ROM verification only. For expediency, the MCUs 
are unmarked, packaged in ceramic, and tested with five 
volts at room temperature. These RVUs are free with the 
minimum-order quantity, but are not production parts. 
These RVUs are not guaranteed by Motorola Quality As- 
surance. 

ORDERING INFORMATION 

The following table provides generic information per- 
taining to the package type and temperatue for the MC6801 
and MC6803. These MCU devices are available in 40-pin 
CERDIP and plastic dual-in-line (DIP) packages. 



MDOS is a trademark of Motorola Inc. 

IBM is a registered trademark of International Business Machines Corporation. 



MOTOROLA MICROPROCESSOR DATA 
3-172 



MC6801U4/6803U4 



MECHANICAL DATA AND ORDERING INFORMATION 

The following table provides generic information per- and MC6803. These MCU devices are available in 40-pin 
taining to the package type and temperatue for the MC6801 CERDIP and plastic dual-in-line (DIP) packages. 



GENERIC INFORMATION 



Package Type 


Frequency (MHz) 


Temperature 


Part Number 


Cerdip 


1.0 


0° to 70°C 


MC6801U4S1 


(S Suffix) 


1.0 


-40°to85°C 


MC6801U4CS1 




1.25 


0° to 70°C 


MC6801U4S1-1 




1.25 


-40°to85°C 


MC6801U4CS1-1 




1.0 


0°to70°C 


MC6803U4S 




1.0 


-40°to85°C 


MC6803U4CS 




1.25 


0° to 70°C 


MC6803U4S-1 




1.25 


-40° to 85°C 


MC6803U4CS-1 


Plastic 


1.0 


0°to70°C 


MC6801U4P1 


(P Suffix) 


1.0 


-40°to85°C 


MC6801U4CP1 




1.25 


0° to 70°C 


MC6801U4P1-1 




1.25 


-40° to 85"C 


MC6801U4CP1-1 




1.0 


0° to 70°C 


MC6803U4P 




1.0 


-40° to 85°C 


MC6803U4CP 




1.25 


0° to 70°C 


MC6803U4P-1 




1.25 


-40° to 85"C 


MC6803U4CP-1 



PIN ASSIGNMENT 




2l[] v CC 

Standby 



MOTOROLA MICROPROCESSOR DATA 
3-173 



MOTOROLA 

SEMICONDUCTOR ■hhmhhhhhhhhhhh 

TECHNICAL DATA mm***-*** 

MC68701 



Advance Information 

MC68701 Microcontroller Unit (MCU) 

The MC68701 is an 8-bit single-chip EPROM microcontroller unit (MCU) which significantly en- 
hances the capabilities of the M6800 Family of parts. It can be used in production systems to allow 
for easy firmware changes with minimum delay or it can be used to emulate the MC6801/MC6803 
for software development. It includes an upgraded M6800 microprocessor unit (MPU) with upward 
source and object code compatibility. Execution times of key instructions have been improved and 
several new instructions have been added including an unsigned multiply. The MCU can function 
as a monolithic microcomputer or can be expanded to a 64K byte address space. It is TTL compati- 
ble and requires one +5 volt power supply for nonprogramming operation. An additional Vpp 
power supply is needed for EPROM programming. On-chip resoources include 2048 bytes of 
EPROM, 128 byte of RAM, Serial Communications Interface (SCI), parallel I/O, and a three function 
Programmable Timer. A summary of MCU features includes: 

• Enhanced MC6800 Instruction Set 

• 8x8 Multiply Instruction 

• Serial Communications Interface (SCI) 

• Upward Source and Object Code Compatibility with the MC6800 

• 16-Bit Three-Function Programmable Timer 

• Single-Chip or Expanded Operation to 64K Byte Address Space 

• Bus Compatibility with the M6800 Family 

• 2048 Bytes of UV Erasable, User Programmable ROM (EPROM) 

• 128 Bytes of RAM (64 Bytes Retainable on Powerdown) 

• 29 Parallel I/O and Two Handshake Control Lines 

• Internal Clock Generator with Divide-by-Four Output 

• -40 to 85°C Temperature Range 



This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-174 



MC68701 



MC68701 MICROCOMPUTER BLOCK DIAGRAM 



> 8 >^| Jllil 




Vcc Standby 




MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


vcc 


-0.3 to +7.0 


V 


Input Voltage 


V in 


-0.3 to +7.0 


V 


Operating Temperature Range 
MC68701 
MC68701C 


■ TA 


T L to T H 
0 to 70 
- 40 to 85 


°c 


Storage Temperature Range 


T stg 


0 to 85 


°c 


THERMAL CHARACTERISTICS 


Characteristic 


Symbol 


Value 


Rating 


Thermal Resistance 
Ceramic Package 
Cerdip Package 


8JA 


50 
50 


°C/W 



This device contains circuitry to protect the in- 
puts against damage due to high static voltages 
or electric fields; however, it is advised that nor- 
mal precautions be taken to avoid application of 
any voltage higher than maximum rated voltages 
to this high-i'fnpedance Circuit. For proper opera- 
tion it is recommended that Vj n and V ou t be con- 
strained to the range Vss < (Vj n or V 0U .)<Vcc- 
Reliability of operation is enhanced if Unused in- 
puts are tied t6 an appropriate logic voltage level 
(e.g., either V$s or Vcc)- 



POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj=T A +(P D -ejA) 



(1) 



where: 
e JA 



= Ambient Temperature, °C 
= Package Thermal Resistance, 
Junction-to-Ambient, °CAA/ 
P D = P|NT +p PORT 

P||MT ' ~ 'CC-^^CC' W a tts — Chip Internal Power 
PpORT = Port Power Dissipation, 

Watts — User Determined 

For most applications PprjRT^INT ar| d can De neglected. PpORT ma Y become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpoRT is neglected) is: 

P D = K + (Tj + 273°C) (2) 
Solving equations (1) and (2) for K gives: 1 

K=p D'< T A + 273 ° c ) + e JA-PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Prj (at 
equilibrium) for a known T^. Using this value of K, the values of Pq and Tj can be obtained by solving equations (1) 
and (2) iteratively for any value of T^ 



MOTOROLA MICROPROCESSOR DATA 
3-175 



MC68701 



CONTROL TIMING (V C c = 5.0 V ±5%, Vss = 0 to 70°C) 



Characteristic 


Symbol 


MC68701 


MC68701-1 


MC68B701 


Unit 


Min 


Max 


Min 


Max 


Min 


Max 


Frequency of Operation 


fo 


0.5 


1.0 


0.5 


1.25 


0.5 


2.0 


MHz 


Crystal Frequency 


fXTAL 


2.0 


4.0 


2.0 


5.0 


2.0 


8.0 


MHz 


External Oscillator Frequency 


4f 0 


2.0 


4.0 


2.0 


5.0 


2.0 


8.0 


MHz 


Crystal Oscillator Start Up Time 


trc 




100 




100 




100 


ms 


Processor Control Setup Time 


tpcs 


200 




170 




110 




ns 



DC ELECTRICAL CHARACTERISTICS (V C c = 5 0 Vdc ±5%, V S s = 0. T A = T L to T H , unless otherwise noted) 









MC68701 


MC68701C 




Characteristic 




Symbol 


Min 


Typ 


Max 




Typ 




Unit 


Input High Voltage 


RESET 
Other Inputs* 


V| H 


V SS + 4.0 
Vss + 2.0 




vcc 

V CC 


V S s + 4.0 
Vss + 2.2 




v C c 

V CC 


V 


Input Low Voltage 


RESET 
Other Inputs* 


V|L 


Vss-0.3 
Vss-0.3 


- ' 


Vss + 0.4 
Vss + 0.8 


Vss-0.3 
Vss-0.3 


- 


Vss + 04 
VSS + 0.8 


V 


Input Current, See Note 
(V in = 0to2.4V) 


Port 4 
SC1 


I'm 




- 


0.6 
1.0 




_ 


1.0 
1.6 


mA 


Input Current 
(V in = 0 to 5.25 V) 


NMl, IRQl 


'in 


- 


1.5 


2.5 


- 


1.5 


5 


/*A 


Input Current 
(V in = 0to0.4V) 
(V in = 4.0VtoV C C> 


RESET/Vpp 


"in 


— 


-2.0 


— 

8.0 


— . 


-2.0 


— 
8.0 


mA 


Hi-Z (Off State) Input Current 
(V in = 0.5to2.4V> 


Ports 1 , 2, and 3 


'TS I 


- 


2 


10 


- 


2 


20 


uA 


Output High Voltage 
d|_oad= -65MA. V cc =Min) 
(lLoad=-1°°>A, V cc =Min) 


Port 4, SC1, SC2 
Other Outputs 


VOH 


Vss + 2.4 
Vss + 2.4 






Vss + 2.4 
Vss + 2.4 






V 


Output Low Voltage 
l Load = 2.0mA, Vcc= Min) 


All Outputs 


vol 






Vss + 0.5 






Vss + 0.6 


V 


Darlington Drive Current 
(Vq=1.5V) 


Port 1 


lOH 


1.0 


2.5 


10.0 


1.0 


2.5 


10.0 


mA 


Internal Power Dissipation 
(Measured at T A =T|_ in Steady-State Operation) 


Pint 






1500 






1500 


mW 


Input Capacitance 
(V in = 0, T A = 25°C,f 0 =1 MHz) 


Port 3,l 
Port 4, SC1 
Other Inputsi 


Cjn 






12.5 
10.0 






12.5 
10.0 


pF 


Vcc Standby 


Powerdown 
Powerup 


VSBB 
VSB 


4.0 
4.75 




5.25 
5.25 


4.0 
4.75 




5.25 
5.25 


V 


Standby Current 


Powerdown 


ISBB 






6.0 






8.0 


mA 


Programming Time Per Byte (T A = 


25 °C) 


tpp 


25 




50 


25 




50 


ms 


Programming Voltage (T A = 25°C) 


Vpp 


20.0 


21.0 


22.0 


20.0 


21.0 


22.0 


V 


Programming Current 
<VRESET = Vp P . T A = 25°C) 


IPP . 




30 


50 




30 


50 


mA 



•Except mode programming levels; see Figure 15. 

NOTE: RESET/Vpp l jn differs from MC6801 and MC6803 values. 



PERIPHERAL PORT TIMING (Refer to Figures 3-6) 



Characteristic 


Symbol 


MC68701 


MC68701-1 


MC68B701 


Unit 


Min 


Max 


Min 


Max 


Min 


Max 


Peripheral Data Setup Time 


tpDSU 


200 




200 




100 




ns 


Peripheral Data Hold Time 


tPDH 


200 




200 




100 




ns 


Delay Time, Enable Positive Transition to OS3 Negative Transition 


tOSD1 




350 




350 




250 


ns 


Delay Time, Enable Positive Transition to OS3 Positive Transition 


tOSD2 




350 




350 




250 


ns 


Delay Time, Enable Negative Transition to Peripheral Data Valid 


tpwD 




350 




350 




250 


ns 


Delay Time, Enable Negative Transition to Peripheral CMOS Data Valid 


tCMOS 




2.0 




2.0 




2.0 


|XS 


Input Strobe Pulse Width 


tpwis 


200 




200 




100 




ns 


Input Data Hold Time 


t| H 


50 




50 




30 




ns 


Input Data Setup Time 


tis 


20 




20 




20 




ns 



MOTOROLA MICROPROCESSOR DATA 
3-176 



MC68701 



FIGURE 1 - DATA SETUP AND HOLD TIMES 
(MPU READ) 



MPU Read 



tPDsuT«^4r*~^ tpD , e V" 



P10-P17 
P20-P24 
P40-P47 
Inputs 

P30-P37 
Inputs* 



^ Data Valid ^ 



tPDSU- 



< >\ 



Data Valid ^ 



tPDH 



•Port 3 Non-Latched Operation ( LATCH E ENABLE = 0) 



FIGURE 2 - DATA SETUP AND HOLD TIMES 
(MPU WRITE) 

j— MPU Write 



\ f 



HtCMOS->) 

^PWD*|__. 07Vcc 



All Data 
Port Outputs 



I 



Data Valid 



NOTES: 

1. 10 k Pullup resistor required for Port 2 to reach 0.7 VqC 

2. Not applicable to P21 

3. Port 4 cannot be pulled above Vqc 



FIGURE 3 - PORT 3 OUTPUT STROBE TIMING 
(SINGLE-CHIP MODE) 



FIGURE 4 - PORT 3 LATCH TIMING 
(SINGLE-CHIP MODE) 



MPU access of Port 3* 



Address 
Bus . 



($0006) 



X 



X 



r«tosDi 



OS3 



(tOSD2 



IS3 



P30-P37 
Inputs 



-tis- 



*r tpwIS ■ 
t|H 



Data Valid 



•Access matches Output Strobe Select (OSS = 0, a read; 
OSS = 1 , a write) 



NOTE: Timing measurements are referenced to a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise noted. 



FIGURE 5 - CMOS LOAD 



FIGURE 6 - TIMING TEST LOAD PORTS 1, 2, 3, 4 

vcc 



R|_=1.8 kO 



Test Point o- 



Test Point o- 



i 30 pF 



M T MMD6150 
or Equiv 



C i > R 



J 



MMD7000 
or Equiv 



C = 90 pF for P30-P37, P40-P47, E, SC1, SC2 

= 30 pF for P10-P17, P20-P24 
R = 37 kB for P40-P47, SC1, SC2, 

= 24 kl) for P10-P17, P20-P24, P30-P37, E 



MOTOROLA MICROPROCESSOR DATA 
3-177 



MC68701 



BUS TIMING (See Notes 2 and 3) 




Ident 
Number 


Characteristic 


Symbol 


MC68701 


MC68701-1 


MC68B701 


Unit 


Min 








Min 


Max 


1 


Cycle Time 


tcyc 


1 n 




0.8 


z.u 


n t\ 


z.u 


|lS 


2 


Pulse Width, E Low 


PWel 


430 


1 000 




1000 


210 


1 000 


ns 


Q 

o 


ruise wiutn, b nign 


PWeh 


450 


1000 


360 


1000 


220 


1000 




4 


Clock Rise and Fall Time 


t r , tf 




25 




25 




20 


ns 


Q 


Address Hold Time 


l AH 


on 




20 




10 






12 


Non-Muxed Address Valid Time to E* 


*AV 


200 




150 




70 




ns 




Read Data Setup Time 


tDSR 


ou 




7(1 

/u 




Aft 




ns 


18 


Read Data Hold Time 


l DHR 


10 




10 




10 




ns 


1 9 


Write Data Delay Time 


l DDW 








200 




1 20 


ns 


21 


Write Data Hold Time 


l DHW 


20 




20 




10 




ns 




Multiplexed Address Valid Time to E Rise* 


f AVM 


200 




150 




80 




ns 


24 


Multiplexed Address Valid Time to AS Fall* 


tASL 


60 




50 




20 






25 


Multiplexed Address Hold Time 


l AHL 


20 




20 




10 




ns 


26 


Delay Time, E to AS Rise* 


l ASD 


90** 




70** 




45** 




ns 


27 


Pulse Width, AS High* 


pwash 


220 




170 




110 




ns 


28 


Delay Time, AS to E Rise* 


tASED 


90 




70 




45 




ns 


29 


Usable Access Time* 


tACC 


595 




465 




270 




ns 



*At specified cycle time. 

*tASD parameters listed assume external TTL clock drive with 50% ±5% duty cycle. Devices driven by an external TTL clock with 
50% ± 1% duty cycle or which use a crystal have the following t/\SD specification: 100 nanoseconds minimum (1 .0 MHz devices), 
80 nanoseconds minimum (1.25 MHz devices), 50 nanoseconds minimum (2.0 MHz devices). 

FIGURE 7 - BUS TIMING 

-©- 




NOTES: 

1. Voltage levels shown are V|_s0.5 V, Vh^2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. 

3. Usable access time is computed by 12+3 - 17+4. 

4. Memory devices should be enabled only during E high to avoid port 3 bus contention. 



MOTOROLA MICROPROCESSOR DATA 
3-178 



MC68701 



INTRODUCTION 



The MC68701 is an 8-bit monolithic microcomputer which 
can be configured to function in a wide variety of applica- 
tions. The facility which provides this extraordinary flexibility 
is its ability to be hardware programmed into eight different 
operating modes. The operating mode controls the con- 
figuration of 18 of the 40 MCU pins, available on-chip 
resources, memory map, location (internal or external) of in- 
terrupt vectors, and type of external bus. The configuration 
of the remaining 22 pins is not dependent on the operating 
mode. 

Twenty-nine pins are organized as three 8-bit ports and 
one 5-bit port. Each port consists of at least a Data Register 
and a write-only Data Direction Register. The Data Direction 
Register is used to define whether corresponding bits in the 
Data Register are configured as an input (clear) or output 
(set). 

The term "port," by itself, refers to all of the hardware 
associated with the port. When the port is used as a "data 
port" or "I/O port," it is controlled by the port Data Direc- 
tion Register and the programmer has direct access to the 
port pins using the port Data Register. Port pins are labled as 
Pij where i identifies one of four ports and j indicates the par- 
ticular bit. 

The Microprocessor Unit (MPU) is an enhanced MC6800 
MPU with additional capabilities and greater throughput. It is 
upward source and object code compatible with the 



MC6800. The programming model is depicted in Figure 8 
where Accumulator D is a concatenation of Accumulators A 
and B. A list of new operations added to the M6800 instruc- 
tion set are shown in Table 1 . 



The basic difference between the MC6801 and the 
MC68701 is that the MC6801 has an onboard ROM while the 
MC68701 has an onboard EPROM. The MC68701 is pin and 
code compatible with the MC6801 and can be used to 
emulate the MC6801, allowing easy software development 
using the onboard EPROM. Software developed using the 
MC68701 can then be masked into the MC6801 ROM. 

In order to support the onboard EPROM, the MC68701 dif- 
fers from the MC6801 as follows: 

(1) Mode 0 in the MC6801 is a test mode only, while in the 
MC68701 Mode 0 is also used to program the onboard 
EPROM and has interrupt vectors at $BFF0-$BFFF 
rather than $FFF0-$FFFF. 

(2) The MC68701 RAM/EPROM Control Register has two 
bits used to control the EPROM in Mode 0 that are not 
defi ned in t he MC6801 RAM Control Register. 

(3) The RESET/Vpp pin in the MC68701 is dual purpose, 
used to supply EPROM power as well as to r eset the 
device; while in the MC6801 the pin is called RESET 
and is used only to reset the device. 



FIGURE 8 — MC68701/6801/6803 PROGRAMMING MODEL 



Accumulators A and B 
Or 16-Bit Double Accumulator D 



h 


X 


°! 




15 


SP 


-ol 




|, 6 


PC 


0 




7 


0 



oj Index Register (X) 



0| Stack Pointer (SP) 





1 


H 


I 











Program Counter (PC) 



Carry/ Borrow from MSB 

Overflow 

Zero 

Negative 

Interrupt 

Half Carry (From Bit 3) 



MOTOROLA MICROPROCESSOR DATA 
3-179 



MC68701 



Instruction 



ABX 
ADOD 
ASLD or LSLD 
BHS 
BLO 
BRN 
JSR 
LDD 
LSL 

LSRD 
MUL 
PSHX 
PULX 
STD 
SUBD 
CPX 



TABLE 1 - NEW INSTRUCTIONS 



Description 



Unsigned addition of Accumulator B to Index Register 

Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator 

Shifts the double accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into, the C-bit 

Branch if Higher or Same; unsigned conditional branch (same as BCC) 

Branch if Lower; Unsigned conditional branch (same as BCS) 

Branch Never 

Additional addressing mode; direct 
Loads double accumulator from memory 

Shifts memory or accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C-bit (same as 
ASL) 

Shifts the double accumulator right (towards LSB) one bit; the MSB is cleared and the LSB is shifted into the C-bit 
Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator 
Pushes the Index Register to stack 
Pulls the Index Register from stack 
Stores the double accumulator to memory 

Subtracts memory from the double accumulator and leaves the difference in the double accumulator 
Internal processing modified to permit its use with any conditional branch instruction 



OPERATING MODES 

The MCU provides eight different operating modes which 
are selectable by hardware programming and referred to as 
Mode 0 through Mode 7. The operating mode controls the 
memory map, configuration of Port 3, Port 4, SC1 , SC2, and 
the physical location of interrupt vectors. 

FUNDAMENTAL MODES 

The eight MCU modes can be grouped into three fun- 
damental modes which refer to the type of bus it supports: 
Single Chip, Expanded Non-Multiplexed, and Expanded 
Multiplexed. Modes4 and 7 are single chip modes. Mode5 is 
the expanded non-multiplexed mode, and the remaining 
modes are expanded multiplexed modes. Table 2 sum- 
marizes the characteristics of the operating modes. 

Single-Chip Modes (4, 7) 

In the Single-Chip Mode, the four MCU ports are con- 
figured as parallel input/output data ports, as shown in 
Figure 9. The MCU functions as a monolithic microcom- 
puter in these two modes without external address or data 
buses. A maximum of 29 I/O lines and two Port 3 control 
lines are provided. Peripherals or another MCU can be inter- 
faced to Port 3 in a loosely coupled dual processor configura- 
tion, as shown in Figure 10. 

In Single-Chip Test Mode (4), the RAM responds to 
$XX80 through $XXFF and the EPROM is removed from the 
internal address map. A test program must first be loaded in- 
to the RAM using modes 0, 1, 2, or 6. If the MCU is reset 
and then programmed into Mode 4, execution will begin at 
$XXFE:XXFF. Mod e 5 can be irreversibly entered from Mode 
4 without asserting RESET by setting bit 5 of the Port 2 Data 
Register. This mode is used primarily to test Ports 3 and 4 in 
the Single-Chip and Non-Multiplexed Modes. 



TABLE 2 - SUMMARY OF MC68701 OPERATING MODES 



Common to all Modes: 

Reserved Register Area 
Port 1 
Port 2 

Programmable Timer 

Serial Communications Interface 



Single Chip Mode 7 

128 bytes of RAM; 2048 bytes of EPROM 

Port 3 is a parallel I/O port with two control lines 

Port 4 is a parallel I/O port 

SC1 is Input Strobe 3 (IS3) 

SC2 is Output Strobe 3 (OS3) 



Expanded Non-Multiplexed Mode 5 

128 bytes of RAM; 2048 bytes of EPROM 
256 bytes of external memory space 
Port 3 is an 8-bit data bus 
Port 4 is an input port/address bus 
SC1 is Input/Output Select (IOS) 
SC2 is Read/Write (R/W) 



Expanded Multiplexed Modes 1,2, 3, 6 

Four memory space options (64K address space): 

(1) No internal RAM or EPROM (Mode 3) 

(2) Internal RAM, no EPROM (Mode 2) 

(3) Internal RAM and EPROM (Mode 1) 

(4) Internal RAM, EPROM with partial address bus 
(Mode 6) 

Port 3 is a multiplexed address/data bus 
Port 4 is an address bus (inputs/address in Mode 6) 
SC1 is Address StrobeJAS) 
SC2 is Read/Write (R/W) 



Test Mode 4 

(1) May be changed to Mode 5 without going through 
Reset 

(2) May be used to test Ports 3 and 4 as I/O ports 



Expanded Multiplexed Mode 0 

(1) Internal RAM and EPROM 

(2) External interrupt vectors located at $BFF0-$BFFF 

(3) Used, to program EPROM 



MOTOROLA MICROPROCESSOR DATA 
3-180 



FIGURE 9 - SINGLE-CHIP MODE 



FIGURE 10 - SINGLE-CHIP DUAL PROCESSOR CONFIGURATION 



Vcc Standby - 
RESET - 



Port 1 
8 I/O Lines 



Port 4 
8 I/O Lines 



VCC 



EXTAL 



VCC 



MC68701/ 
MC6801 



vss 



•NMI 



-IRQ1 



Port 3 
8 I/O Lines 
IS3 



Port 2 
5 I/O Lines 
Serial I/O 
16-Bit Timer 



Vcc Standby >i 

RESET > 



Port 1 
8 I/O 
Lines 



Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 



XTAL 



EXTAL 



MC68701/ 
MC6801 



OS3 
IS3 *■ 



v S s 



► E f— 

NMI 

IRQ1 — f— 
VCC Standby - 
RFSET- 



VCC 
I 



XTAL 



EXTAL 



MC68701/ 
MC6801 



IS3 
OS3 



■ E 
NMI 
IRQ1 



Port 4 
8 I/O 
Lines 



Port 2 
5 I/O Lines 

SCI 
1 6- Bit Timer 



V S S 



Port 1 
8 I/O 
Lines 



Port 4 
8 I/O 
Lines 



2 
o 

o> 

00 



FIGURE 11 - EXPANDED NON-MULTIPLEXED CONFIGURATION 



Vcc Standby 
RESET - 



Port 1 
8 1/0 Lines 

Port 2 
5 I/O 
Lines 
Serial I/O 
16-Bit Timer 



VCC 
JL_ 



XTAL 
EXTAL 



MC68701/ 
MC6801 



"X" 

vis 



• NMI 
TRQ1 




Port 3 
'8 Data Lines 
R/W 



I0S 
Port 4 
To 8 
Address Lines 



VCC 



Port 1 
8 I/O 

Port 2 
5 I/O 

SCI 
Timer 



EXTAL 



MC68701/ 
MC6801 



vss 



Port 3 



Port 4 ^8 



io"s 



ram 



(DO D7) 
(A0-A7) 
I0S_ 
R/W 



E 



CO 



MC68701 



Expanded Non-Multiplexed Mode (5) 

A modest amount of external memory spce is provided in 
the Expanded Non-Multiplexed Mode while significat on-chip 
resources are retained. Port 3 functions as an 8-bit bidirectional 
data bus and Port 4 is configured initially as an input data port. 
Any combination of the eight least-significant address lines 
may be obtained by writing to the Port 4 Data Direction Reg- 
ister. Stated alternatively, any combination of AO to A7 may 
be provided while retaining the remainder as input data lines. 
Internal pullup resistors are intended to pull the Port 4 lines 
high until the port is configured. 

Figure 11 illustrates a typical system configuration in the 
Expanded Non-Multiplexed Mode. The MCU interfaces directy 
with M6800 Family parts and can access 256 bytes of external 
address space at $100 through $1 FF. IOS provides an address 
decode of external memory ($100-$1FF) and can be used as a 
memory page select or chip select line. 

Expanded-Multiplexed Modes (0, 1, 2, 3, 6) 

In the Expanded-Multiplexed Modes, the MCU has the ability 
to access a 64K bytes memory space. Port 3 functions as a 
time multiplexed address/data bus with address valid on the 
negative edge of Address Strobe (AS), and data valid while E 
is high. In Modes 0 to 3, Port 4 provides address line s A8 to 
A15. In Mode 6, however, Port 4 is initially configured at RESET 
as an input data port. The Port 4 Data Direction Register can 
then be changed to provide any combination of address lines, 
A8 to A15. Stated alternatively, any subset of A8 to A15 can 
be provided while retaining the remaining Port 4 lines as input 
data lines. Internal pullup resistors pull the Port 4 lines high 
until software configures the port. 

Figure 12 depicts a typical configuration for the Expanded- 
Multiplexed Modes. Address Strobe can be used to control a 
transparent D-type latch to capture addresses AO to A7, as 
shown in Figure 13. This allows Port 3 to function as a Data 
Bus when E is high. 



In Mode 0, the internal and external data buses are con- 
nected; there must therefore be no memory map overlap in 
order to avoid potential bus conflicts. Mode 0 is used to pro- 
gram the onboard EPROM. All interrupt vectors are external 
in this mode and are located at $BFF0-$BFFF. 

PROGRAMMING THE MODE 

The operating mode is determined at RESET by the levels 
asserted on P22, P21, and P20. These levels are latched into 
PC2, PC1, and PCO of the program control register on the po- 
sitive edge of RESET. The operating mode may be read from 
the Port 2 Data Register as shown below, and programming 
levels and timing must be met as shown in Figure 14. A brief 
outline of the operating modes is shown in Table 3. 

PORT 2 DATA REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


PC2 


PC1 


PCO 


P24 


P23 


P22 


P21 


P20 



Circuitry to provide the programming levels is dependent 
primarily on the normal system usage of the three pins. If 
configured as outputs, the circuits shown in Figure 15 may be 
used; otherwise, three-state buffers can be used to provide 
isolation while programming the mode. Note that if diodes are 
used to program the mode, the diode forward voltage drop 
must not exceed the Vmpdd minimum. 

MEMORY MAPS 

The MCU can provide up to 64K byte address space de- 
pending on the operating mode. A memory map for each op- 
erating mode is shown in Figure 16. The first 32 locations of 
each map are reserved for the MCU internal registers as shown 
in Table 4, with exceptions as indicated. 



TABLE 3 - MODE SELECTION SUMMARY 



Mode 


P22 
PC2 


P21 
PC1 


P20 
PCO 


EPROM 


RAM 


Interrupt 
Vectors 


Bus 
Mode 


Operating 
Mode 


7 


H 


H 


H 


I 


I 


I 


I 


Single Chip 


6 


H 


H 


L 


I 


I 


I 


mux' 5 - 61 


Multiplexed/Partial Decode 


5 


H 


L 


H 


I 


I 


I 


NMUX' 6 - 61 


Non-Multiplexed/Partial Decode 


4 


H 


L 


L 


,<2> 


|(1) 


I 


1 


Single Chip Test 


3 


L 


H 


H 


E 


E 


E 


MUX 14 ' 


Multiplexed/No RAM or EPROM 


2 


L 


H 


L 


E 


I 


E 


MUX< 4) 


Multiplexed/RAM 


1 


L 


L 


H 


I 


I 


E 


MUX' 4 ' 


Multiplexed/ RAM and EPROM 


0 


L 


L 


L 


I 


I 


K3> 


mux' 4 ' 


Multiplexed/ Programming 



Legend: Notes: 
I — Internal (1 ) Internal RAM is addressed at SXX80 

E — External (2) Internal EPROM is disabled 

MUX — Multiplexed (3) Interrupt vectors located at $BFF0-$BFFF 

NMUX — Non-Multiplexed (4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 

L — Logic "0" 1, 2, and 3 

H — Logic "1 (5) Addresses associated with Port 3 are considered external in Modes 5 and 6 

(6) Port 4 default is user data input; address output is optional by writing to Port 4 
Data Direction Register 



MOTOROLA MICROPROCESSOR DATA 
3-182 



MC68701 



FIGURE 12 - EXPANDED MULTIPLEXED CONFIGURATION 

vcc ...... 



Vcc Standby . 
RESET • 



Port 1 
8 I/O Lines 



Port 2 
5 I/O Lines 
Serial I/O 
16-Bit Timer 



XTAl 
EXTAL 

MC68701 



Vcc 



4T 

vss 



„ E 

-NMI 

-iRQI 



♦ R/W 
-^-AS 



Port 3 
8 Lines 
Multiplexed Data/ Address 



Port 4 
8 Lines 
Address Bus 



Vcc Standby — 

RESET 

NMI >■ 



Port 1 
8 I/O 

Port 2 
5 I/O 
SCI 
Timer 



XTAL 
EXTAL 

MC68701 



vis 



Port 3 8 



R/W 



Data Bus 
" (D0-D7) 



Address Bus 
(A0-A15) 

R/W 




->■ E 



ROM 




RAM 




PIA 



NOTE: To avoid data bus (Port 3) contention in the expanded multiplexed modes, memory devices should be enabled only during E high time. 

FIGURE 13 - TYPICAL LATCH ARRANGEMENT 
GND > 



AS >~ 



Port 3 
Address/Data 



>- 
>- 
>- 
>- 
>- 



G OC 
Di Qi 



SN74LS373 
(Typical) 



D 8 



Q8 



Address: A0-A7 



Data: D0-D7 



MOTOROLA MICROPROCESSOR DATA 
3-183 



MC68701 



FIGURE 14 - MODE PROGRAMMING TIMING 



RESIT 



— \ Vih cr 



PWrstl— 
■tMPS" 



Mode Inputs , 
(P20, P21, P22) 



VMPH 



VMPL 



See Figure 16 
for Diode Arrangement. 



tMPH 



^ C Data Valid ^ ]jL 



V MPH Min 



V MPL Max 



(P20, P21. P22) 
RESET 



vmpdd 




MODE PROGRAMMING (Refer to Figure 14) 




Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Mode Programming Input Voltage Low for Ta = 0 to 70°C 


VMPL 






1.8 


V 


Mode Programming Input Voltage High 


V MPH 


4.0 






V 


Mode Programming Diode Differential for Ta = 0 to 70°C 


Vmpdd 


0.6 






V 


RESET Low Pulse Width 


pwrstl 


3.0 






E-Cycles 


Mode Programming Set-Up Time 


*MPS 


2.0 






E-Cycles 


Mode Programming Hold Time 
RESET Rise Time&1 ixs 
RESET Rise Time<1 m-s 


tMPH 


0 

100 






ns 



Note: For Ta= -40 to 85°C, Maximum V|\/|pl= 1.7, and Minimum Vmpdd = 0.4. 

FIGURE 15 - TYPICAL MODE PROGRAMMING CIRCUIT 

v cc 




P20- 
P21 
P22- 









8 


« 


1 — 




9 




— » 


> — 


10 






— ( 


» 

V 



RESET 




P20 (PC0) 
P21 (PCD 
P22 (PC2) 



MC68701 



VppO 

"Program" 

Notes: 

1 . Mode 0 as shown (switches closed). _ 

2. R1 = 10k oh ms (typical). 

3. The RESET time constant is equal to RC where R is the equivalent parallel resistance of R2 and the number of resistors (R1) 
placed in the circuit by closed mode control switches. 

4. D=1N914, 1N4001 in the 0 to 70°C range 

D = 1 N270, MBD201 in the - 40 to 85°C range 

5. If V = Vco the R2 = 50 ohms (typical) to meet V|h for the RESET/Vpp pin. V = Vqc is also compatible with MC6801. The RESET 
time constant in this case is approxim ately R2 *C. 

6. Switch S1 allows selection of normal (RESET) or programming (Vpp) as the input to the RESET/Vpp pin. During switching, 
the input level is held at a value deter mined b y a diode (D), resistor (R2) and input voltage (V). 

7. While S1 is in t he "Pro gram" position, RESET should not be asserted. 

8. From powerup, RESET must be held low for at least tRQ. Tne capacitor, C, is shown for conceptual p urpose s only and is on 
the order of 1000 (iF for the circuit shown. Typically, a buffer with an RC input will be used to drive RESET, eliminating the 
need for the larger capacitor. 

9. Diode Vf should not exceed Vmpdd min - 



MOTOROLA MICROPROCESSOR DATA 
3-184 



FIGURE 16 - MC68701 MEMORY MAPS 





2 




O 




H 




O 




33 




O 

5 








o 


w 


31 


_1 


O 


00 


TJ 


U1 


33 




O 




O 




m 




(0 




0) 




O 




33 




O 















MC68701 
Mode 



Multiplexed Test mode 




SF800 



$FFFF' 



Internal Registers 
External Memory Space 

Internal RAM 

External Memory Space 

External Interrupt Vectors 
External Memory Space 

Internal EPROM 



Notes: 

1 ) Excludes the following addresses which may 
be used externally: $04, $05, $06, $07 and $0F. 

2) There must be no overlapping of internal and 
external memory spaces to avoid driving the 
data bus with more than one device. 

3) This mode is used to program the onboard 
EPROM. 



MC68701 
Mode 



1 



Multiplexed/ RAM & EPROM 




Internal Registers 
External Memory Space 

Internal RAM 



> External Memory Space 



Internal EPROM 

External Interrupt Vectors 



Notes: 

1 ) Excludes the following addresses which may 
be used externally: $04, $05, $06, $07 and 
$0F 

2) Internal EPROM addresses $FFF0 to $FFFF are 

not usable. 



MC68701 
Mode 



Multiplexed/RAM 
$0000"' 
$001 F 



$0080 7, 



SOOFF 




$FFF0 
$FFFF 



Internal Registers 
External Memory Space 



Internal RAM 



y External Memory Space 



External Interrupt Vectors 



Notes: 

1 ) Excludes the following addresses which may 
be used externally: $04, $05, $06, $07, and 
$0F 



/ 




FIGURE 16 - MC68701 MEMORY MAPS (CONTINUED) 



MC68701 
Mode 



Multiplexed/ No RAM or EPROM 
$0000* % 
$001 F 



• Internal Registers 



> External Memory Space 



> External Interrupt Vectors 



$FFF0 
SFFFF 

Notes: 

1 ) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07 and $0F. 



MC68701 
Mode 



Single Chip Test 



$0000p 
$001 F^ 



^Internal Registers' 5 ' 



i Internal RAM 
'Internal Interrupt Vectors. 

Notes: 

1) The internal EPROM is disabled. 

2) Mode 4 may b e chang ed to Mode 5 without hav- 
ing to assert RESET by writing a "1" into the 
PCO bit of Port 2 Data Register. 

3) Addresses A8 to A15 are treated as "don't 
cares" to decode internal RAM. 

4) Internal RAM will appear at $XX80 to $XXFF. 

5) MCU read of the Port 3 Data Direction Register 
will access the Port 3 Data Register. 



MC68701 
Mode 



Non-Multiplexed/ Partial Decode 

$0000 (1) 



vjg^J Internal Registers 



$0080 



Unusable 




Internal RAM 

External Memory Space 



O 
00 



$FFFF 



> Internal EPROM 



Internal Interrupt Vectors 



Notes: 

1 ) Excludes the following addresses which may NOT 
be used externally: $04, $06, and $0F (No IOS). 

2) This mo de ma y be entered without going 
through RESET by using Mode 4 and subse- 
quently writing a "1" into the PCO bit of Port 2 
Data Register. 

3) Address lines AO to A7 will not contain addresses 
until the Data Direction Register for Port 4 has 
been written with "Vs" in the appropriate bits. 
These address lines will assert "Vs" until made 
outputs by writing the Data Direction Register. 



MC68701 



FIGURE 16 - MC68701 MEMORY MAPS (CONCLUDED) 



MC68701 
Mode 



Multiplexed/Partial Decode 
SOOOO' 1 ' 
$001 F 
$0080 



$00FF 




$F800 



$FFFF 




Internal Registers 
External Memory Space 

Internal RAM 



> External Memory Space 



} Internal EPROM 
Internal Interrupt Vectors 



Notes: 

1) Excludes the following addresses which maybe 
used externally: $04, $06, $0F. 

2) Address lines A8-A15 will not contain 
addresses until the Data Direction Register for 
Port 4 has been written with "1 's" in the 
appropriate bits. These address lines will 
assert "1 's" until made outputs by writing the 
Data Direction Register. 



MC68701 
Mode 



Single Chip 
$0000053 




Internal Registers^' 



Internal RAM 



SF800 



SFFFF 




Internal EPROM 

Internal Interrupt Vectors 



Note: 

1) MCU read of the Port 3 Data Direction Register 
will access the Port 3 Data Register. 




TABLE 4 - INTERNAL REGISTER AREA 



Register 


Address 


Port 1 Data Direction Register* * * 


00 


Port 2 Data Direction Register* * * 


01 


Port 1 Data Register 


02 


Port 2 Data Register 


03 


Port 3 Data Direction Register* * * 


04* 


Port 4 Data Direction Register* * * 


05** 


Port 3 Data Register 


06* 


Port 4 Data Register 


07** 


Timer Control and Status Register 


08 


Counter (High Byte) 


09 


Counter (Low Byte) 


OA 


Output Compare Register (High Byte) 


OB 



Register 


Address 


Output Compare Register (Low Byte) 


OC 


Input Capture Register (High Byte) 


OD 


Input Capture Register (Low Byte) 


OE 


Port 3 Control and Status Register 


OF* 


Rate and Mode Control Register 


10 


Transmit/Receive Control and Status Register 


1 1 


Receive Data Register 


12 


Transmit Data Register 


13 


RAM/EPROM Control Register 


14 


Reserved 


1 5 -IF 



•External addresses in Modes 0, 1,2, 3, 5, 6; cannot be accessed in Mode 5 (No i0~5) 
** External addresses in Modes 0, 1, 2, 3 
* * * 1 = output, 0= Input 



MOTOROLA MICROPROCESSOR DATA 
3-187 



MC68701 



MC68701 INTERRUPTS 

The MCU supports two types of interrupt requests: 
maskable and non-maskable. A Non-Maskable Interrupt 
(NMD is always recognized and acted upon at the comple- 
tion of the current instruction. Maskable interrupts are con- 
trolled by the Condition Code Register's l-bit and by in- 
dividual enable bits. The l-bit controls all maskable i nter- 
rupt s. Of the maskable interrupts, there are two types: IRQ1 
and IRQ2. The Programmable Timer and Serial Communica- 
tions Interface use an intern al IR Q2 in terrupt line. External 
device s (and IS3) use IRQ1. An IRQ1 interrupt is serviced 
befor e IRQ 2 if both are pending. 

All IRQ2 interrupts use hardware prioritized vectors. The 
single SCI interrupt and three timer interrupts areserviced in 
a prioritized order and each is vectored to a separate loca- 
tion. All MCU interrupt vector locations are shown in Table 
5. 



TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS 



ModeO 


Modes 1-7 


Interrupt 


MSB 


LSB 


MSB 


LSB 


BFFE 


BFFF 


FFFE 


FFFF 


RESET 


BFFC 


BFFD 


FFFC 


FFFD 


NMI 


BFFA 


BFFB 


FFFA 


FFFB 


Software Interrupt (SWI) 


BFF8 


BFF9 


FFF8 


FFF9 


IROT (or 1S3I 


BFF6 


BFF7 


FFF6 


FFF7 


ICF (Input Capture)* 


BFF4 


BFF5 


FFF4 


FFF5 


OCF (Output Compare)* 


BFF2 


BFF3 


FFF2 


FFF3 


TOF (Timer Overflow)* 


BFFO 


BFF1 


FFFO 


FFF1 


SCI'(RDRF+ORFE+TDRE)» 



*IRQ2 Interrupt 



The Interrupt flowchart is depicted in Figure 17 and is 
common to every MCU interrupt excluding reset. During in- 
terrupt servicing the Program Counter, Index Register, A Ac- 
cumulator, B Accumulator, and Condition Code Register are 
pushed to the stack. The l-bit is set to inhibit maskable inter- 
rupts and a vector is fetched corresponding to the current 
highest priority interrupt. The vector is transferred to the 
Program C ounter a nd instruction execution is resumed. In- 
terrupt and RESET timing are illustrated in Figures 18 and 19. 

FUNCTIONAL PIN DESCRIPTIONS 

V C C AND VSS 

Vcc and Vss P r0Vlc ' e Power to a large portion of the 
MCU. The power supply should provide +5 volts (±5%) to 
Vcc. and Vss should be tied to ground. Total power 
dissipation (including Vcc Standby), will not exceed Pq 
milliwatts. 

Vcc STANDBY 

Vcc Standby provides power to the standby portion ($80 
through $BF) of the RAM and the STBY PWR and RAME 
bits of the RAM Control Register. Voltage requirements de- 
pend on whether the MCU is in a powerup or powerdown 
state. In the powerup state, the power supply should provide 
+ 5 volts (±5%) and must reach Vsb volts before RESET 
reaches 4.0 volts. During powerdown, Vcc Standby must 
remain above VsBB < m ' n > t0 sustain the standby RAM and 
STBY PWR bit. While in powerdown operation, the standby 
current will not exceed ISBB- 



It is typical to power both Vcc and Vcc Standby from the 
same source during normal operation. A diode must be used 
between them to prevent supplying power to Vcc during 
powerdown operation. Vcc Standby should be tied to 
ground in Mode 3. 

XTAL1 AND EXTAL2 

These two input pins interface either a crystal or TTL com- 
patible clock to the MCU internal clock generator. Divide-by- 
four circuitry is included which allows use of the inexpensive 
3.58 MHz or 4.4336 MHz Color Burst TV crystals. A 20 pF 
capacitor should be tied from each crystal pin to ground to 
ensure reliable startup and operation. Alternatively, EXTAL2 
may be driven by an external TTL compatible clock at 4f 0 
with a duty cycle of 50% ( ± 5%) with XTAL1 connected to 
ground. 

The internal oscillator is designed to interface with an AT- 
cut quartz crystal resonator operated in parallel resonance 
mode in the frequency range specified for fxTAL- The 
crystal should be mounted as close as possible to the input 
pins to minimize output distortion and startup stabilization 
time.** The MCU is compatible with most commercially 
available crystals. Nominal crystal parameters are shown in 
Figure 20. 



RESET/Vpp 

This input is used to reset the MCU internal state a nd pro- 
vide an orderly startup procedure. During powerup, RESET 
must be held below 0.4 volts: (1) at least tRc after Vcc 
reaches 4.75 volts in order to provide sufficient time for the 
clock generator to stabiliz e, and (2) until Vcc Standby 
reaches Vsb volts. RESET must be held low at least three 
E-cycles if asserted during powerup operation. 

This pin is also used to supply Vpp in Mode 0 for program- 
ming the EPROM, and supplies operating power to the 
EPROM during powerup operation. 

E (ENABLE) 

This is an output clock used primarily for bus synchroniza- 
tion. It is TTL compatible and is the slightly skewed divide- 
by-four result of the MCU input clock frequency. It will drive 
one Schottky TTL load and 90 pF, and all data given in cycles 
is referenced to this clock unless otherwise noted. 

NMI (NON-MASKABLE INTERRUPT) 

An NMI negative edge requests an MCU interrupt se- 
quence, but the current instruction will be completed before 
it responds to the request. The MCU will then begin an inter- 
rupt sequence. Finally, a vector is fetched from $FFFC and 
$FFFD (or $BFFC and $BFFD in Mode 0), transferred t o the 
Program Counter and instruction execution is resumed. NMI 
typically re quire s a 3.3 kO (nomi nal) r esistor to Vcc- There is 
no internal NMI pullup resistor. NMI must be held low for at 
least one E-cycle to be recognized under all conditions. 

IRQ! (MASKABLE INTERRUPT REQUEST 1) 

IRQ1 is a level-sensitive input which can be used to re- 
quest an interrupt sequence. The MPU will complete the cur- 
rent instruction before it responds to the request. If the inter- 

* * Devices made with masks subsequent to T7A and CB4 incorpor- 
ate an advanced clock with improved startup characteritics. 



MOTOROLA MICROPROCESSOR DATA 
3-188 



FIGURE 17 - INTERRUPT FLOWCHART 




CO 



FIGURE 18 - INTERRUPT SEQUENCE 



Last Instruction 



I Cycle 
— *H #1 



#3 



Internal 
Address Bus 



IRQ1 



NMI or IRQ2 



yzzy. 



^ x x x yc X" y y 



— H k-'pcs 



\ 



1-Bit Set 



OpCode OpCode SP(n) SP(n-1) SP(n-2) SP(n-3) SP(n-4) SP(n-5) SP(n-6) SP(n-7) Vector Vector New PC 
Addr Addr MSB Addr LSB Addr Address 



— >\ |^-tPCS 



Internal —\j V V V V V V y Y Y~ y v V y V ' Y 

Data Bus _J\ A A * A A A A A A A A A A A A 



OpCode OpCode PC 0-7 PC8-15 X 0-7 X 8-15 ACCA ACCB CCR Irrelevant Vector Vector First Inst of 

Data MSB LSB Interrupt Routine 



Internal R/vV 



y 



FIGURE 19 - RESET TIMING 



inn,,nnnnnn ; nnnr 

. 5.25 V 



v CC Z/^ 7 



H b 



•4 h 



-tRC- 



RESTf/Vpp 

Internal 
Address Bus 



wwwwvvwwwv 



4 b 



H h 



-i b 



•tpcs 



7" 4.0 V 



— 1 N 

0.4 V J t 



-tPCS 



[mm\m\TO\v\\ir — * — v — y. — y— y* »-y — y — -y— 

FFFE 1 'FFFE FFFE FFFE FFFF New PC 



FFFE i FFFE 



.nterna.R/w WWWWWWWW^ jsgSSmSSSSSSSSSy " ^ tUCZjr 

KWWVJ Not Valid 



Internal 
Data Bus 



PC 8-15 PC 0-7 First 

Instruction 



MC68701 



rupt mask bit (l-bit) in the Condition Code Register is clear, 
the MCU will begin an interrupt sequence. A vector is fetch- 
ed from $FFF8 and $FFF9 (or $BFF8 and $BFF9 in Mode 0), 
transferred to the Program Counter, and instruction execu- 
ti on is resumed. 

IRQ1 typically requires an external 3.3 kO (nominal) 
resistor to Vqc for wire-OR applications. IRQ1 has no inter- 
nal pullup resistor. 



SC1 AND SC2 (STROBE CONTROL 1 AND 2) 

The function of SC1 and SC2 depends on the operating 
mode. SC1 is configured as an output in all modes except 
single chip mode, whereas SC2 is always an output. SC1 
and SC2 can drive one Schottky load and 90 pF. 



SC1 and SC2 In Single Chip Mode 

In Single Chip Mode, SC1 and SC2 are configured as an 
input and output, respectively, and both function as Port 3 
control lines. SC1 functions as IS3 and can be used to in- 
dicate that Port 3 input data is ready or output data has been 
accepted. Three options associated with IS3 are controlled 
by the Port 3 Control and Status Register and are discussed 
in the Port 3 description. If unused, IS3 can remain uncon- 
nected. 

SC2 is configured as OS3 and can be used to strobe out- 
put data or acknowledge input data. It is controlled by Out- 
put Strobe Select (OSS) in the Port 3 Control and Status 
Register. The strobe is generated by a read (OSS = 0) or 
write (OSS=1) to the Port 3 Data Register. OS3 timing is 
shown in Figure 5. 



MC68701 



SC1 And SC2 In Expanded Non-Multiplexed Mode 

In the Expanded Non-Multiplexed Mode, both SC1 and 
SC2 are configured as outputs. SC1 functions as Input/Out- 
put Select (IOS) and is asserted only when $0100 through 
$01 FF is sensed on the internal address bus. 

SC2 is configured as Read/Write and is used to control 
the direction of data bus transfers. An MPU read is enabled 
when Read/ Write and E are high. 

SCI And SC2 In Expanded Multiplexed Mode 

In the Expanded Multiplexed Modes, both SC1 and SC2 
are configured as outputs. SC1 functions as Address Strobe 
and can be used to demultiplex the eight least significant ad- 
dresses and the data bus. A latch controlled by Address 
Strobe captures address on the negative edge, as shown in 
Figure 15. 

SC2 is configured as Read/Write and is used to control 
the direction of data bus transfers. An MPU read is enabled 
when Read/ Write and E are high. 

P10-P17 (PORT 1) 

Port 1 is a mode independent 8-bit I/O port with each line 
an input or output as defined by the Port 1 Data Direction 
Register. The TTL compatible three-state output buffers can 
drive one Schottky TTL load and 30 pF, Darlington tran- 
sistors, or CMOS devices using ext ernal p ullup resistors. It is 
configured as a data input port by RESET. Unused lines can 
remain unconnected. 

P20-P24(PORT 2) 

Port 2 is a mode-independent, 5-bit, multipurpose I/O 
port. The volta ge leve ls present on P20, P21 , and P22 on the 
rising edge of RESET determine the operating mode of the 
MCU. The entire port is then configured as a data input port. 
The Port 2 lines can be selectively configured as data output 
lines by setting the appropriate bits in the Port 2 Data Direc- 
tion Register. The Port 2 Data Register is used to move data 
through the port. However, if P21 is configured as an out- 
put, it will be tied to the timer Output Compare function and 
cannot be used to provide output from the Port 2 Data 
Register. 

Port 2 can also be used to provide an interface for the 
Serial Communications Interface and the timer Input Edge 
function. These configurations are described in the ap- 
propriate SCI and Timer sections of this publication. 

The Port 2 high-impedance, TTL compatible output buf- 
fers are capable of driving one Schottky TTL load and 30 pF 
or CMOS devices using external pullup resistors. 

PORT 2 DATA REGISTER 



7 6 5 4 3 2 1 0 



PC2 


PC1 


PC0 


P24 


P23 


P22 


P21 


P20 



P30-P37 (PORT 3) 

Port 3 can be configured as an I/O port, a bidirectional 
8-bit data bus, or a multiplexed address/data bus depending 
on the operating mode. The TTL compatible three-state out- 
put buffers can drive one Schottky TTL load and 90 pF. 
Unused lines can remain unconnected. 



Port 3 In Single-Chip Mode 

Port 3 is an 8-bit I/O port in the Single-Chip Mode, with 
each line configured by the Port 3 D ata Direction Register. 
There are also two lines, IS3 and OS3, which can be used to 
control Port 3 data transfers. 

Three Port 3 options are controlled by the Port 3 Control 
and Status Register and are available only in Single-Chip 
Mode: (1) Port 3 i nput data can be latched using IS3 as a 
control signal, (2) OS3 can be generated by either an M PU 
read or write to the Port 3 Data_Register, and (3) an IRQ1 in- 
terrupt can be enabled by an IS3 negative edge. Port 3 latch 
timing is shown in Figure 4. 

PORT 3 CONTROL AND STATUS REGISTER 



7 6 5 4 3 2 1 0 



IS3 
Flag 


IS3 
IRQ1 
Enable 


X 


OSS 


Latch 
Enable 


X 


X 


X 



$000F 



Bit 0-2 Not used. 

Bit 3 LATCH ENABLE. This bit controls the 

input latch for Port 3. If set, input data 
is latched by an IS3 negative edge. The 
latch is transparent after a read of Port 
3 Data Register. LATCH ENABLE is 
cleared during reset. 

Bit 4 OSS (Output Strobe S elect) . This bit 

determines whether 0S3 will be 
generated by a read or write of the Port 
3 Data Register. When clear, the 
strobe is generated by a read; when 
set, it is generated by a write. OSS is 
cleared during reset. 

Bit 5 Not used. 

Bit 6 I S3 IRQi ENABLE. When set, an IRQ1 

interrupt will be enabled whenever IS3 
FLAG is set; when clear, the interrupt 
is inhibited. This bit is cleared during 
reset. 

Bit 7 IS3 FLAG. This read-only status bit is 

set by an IS3 negative edge. It is 
cleared by a read of the Port 3 Control 
and Status Register (with IS3 FLAG 
set) followed by a read or write to the 
Port 3 Data Register or during reset. 

Port 3 In Expanded Non-Multiplexed Mode 

Port 3 is configured as a bidirectional data bus (D7-D0) in 
the Expanded Non-Multiplexed Mode. The direction of data 
transfers is controlled by Read/Write (SC2). Data is clocked 
by E (Enable). 

Port 3 In Expanded Multiplexed Mode 

Port 3 is configured as a time multiplexed address (A0-A7) 
and data bus (D7-D0) in the Expanded Multiplexed Modes 
where Address Strobe (AS) can be used to demultiplex the 
two buses. Port 3 is held in a high impedance state between 
valid address and data to prevent potentional bus conflicts. 



MOTOROLA MICROPROCESSOR DATA 
3-192 



MC68701 



P40-P47 (PORT 4) 

Port 4 is configured as an 8-bit I/O port, as address out- 
puts, or as data inputs depending on the operating mode. 
Port 4 can drive one Schottky TTL load and 90 pF and is the 
only port with internal pullup resistors. Unused lines can re- 
main unconnected. 

Port 4 In Single Chip Mode 

In Single Chip Mode, Port 4 functions as an 8-bit I/O port 
with each line configured by the Port 4 Data Direction 
Register. Internal pullup resistors allow the port to directly in- 
terface with CMOS at 5 volt levels. External pullup resistors 
to more than 5 volts, however, cannot be used. 

Port 4 In Expanded Non-Multiplexed Mode 

Port 4 is configured during reset as an 8-bit input port, 
where the Port 4 Data Direction Register can be written to 
provide any or all of eight address lines AO to A7. Internal 
pullup resistors pull the lines high until the Port 4 Data Direc- 
tion Register is configured. 

Port 4 In Expanded Multiplexed Mode 

In all Expanded Multiplexed modes except Mode 6, Port 4 
functions as half of the address bus and provides A8 to A15. 
In Mode 6, the port is configured during reset as an 8-bit 
parallel input port, where the Port 4 Data Direction Register 
can be written to provide any or all of upper address lines A8 
to A15. Internal pullup resistors pull the lines high until the 
Port 4 Data Direction Register is configured, where bit 0 con- 
trols A8. 



RESIDENT MEMORY 

The MC68701 has 128 bytes of onboard RAM and 2048 
bytes of onboard UV erasable EPROM. This memory is con- 
trolled by four bits in the RAM/EPROM Control Register. 

One half of the RAM is powered through the Vcc standby 
pin and is maintainable during Vcc powerdown. This stand- 
by portion of the RAM consists of 64 bytes located from $80 
through $BF. 

Power must be supplied to Vcc standby if the internal 
RAM is to be used, regardless of whether standby power 
operation is anticipated. In Mode 3, Vcc standby should be 
tied to ground. 

The RAM is controlled by the RAM/EPROM Control 
Register. 

RAM/EPROM CONTROL REGISTER ($14) 

The RAM/EPROM Control Register includes four bits: 
STBY PWR, RAME, PPC, and PLC. Two of these bits, 
STBY PWR and RAME, are used to control RAM access and 
determine the adequacy of the standby power source during 
power-down operation. It is intended that RAME be cleared 
and STBY PWR be set as part of a power-down procedure. 
RAME and STBY PWR are Read/Write bits. 

The remaining two bits, PLC and PPC, control the opera- 
tion of the EPROM. PLC and PPC are readable in all modes 
but can be changed only in Mode 0. The PLC bit can be writ- 
ten without restriction in Mode 0, but operation of the PPC 
bit is controlled by the state of PLC. 

Associated with the EPROM are an 8-bit data latch and a 
16-bit address latch. The data latch is enabled at all times, 
latching each data byte written to the EPROM. The address 
latch is controlled by the PLC bit. 

A description of the RAM/EPROM Control Register 
follows. 



MC68701 RAM/EPROM CONTROL REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


STBY 
PWR 


RAME 


X 


X 


X 


X 


PPC 


PLC 



$14 



BitO 



Bit 1 



Bit 2-5 

Bit 6 RAME 



. PLC. Programming Latch Control. 
This bit controls (a) a latch which cap- 
tures the EPROM address to be pro- 
grammed and (b) whether the PPC bit 
can be cleared. The latch is triggered 
by an MPU write to a location in the 
EPROM. This bit is set during reset 
and can be cleared only in Mode 0. The 
PLC bit is defined as follows: 

PLC = 0 EPROM address latch 
enabled; EPROM address is latched 
during MPU writes to the EPROM. 

PLC=1 EPROM address latch is 
transparent. 

PPC. Programming Power Control. 
This b it gates power from the 
RESET/Vpp pin to the EPROM pro- 
gramming circuit. PPC is set during 
reset and whenever the PLC bit is set. 
It can be cleared only if (a) operating in 
Mode 0, and (b) if PLC has been 
previously cleared. The PPC bit is 
defined as follows: 

PPC = 0 EPROM programming 
power (Vpp) applied. 

PPC=1 EPROM programming 
power (Vpp) is not applied. 
Unused. 

RAM Enable. This Read/Write bit can 
be used to remove the entire RAM 
from the internal memory map. RAME 
is, set (enabled) during reset provided 
standby power is available on the 
positive edge of reset. If RAME is 
clear, any access to a RAM address is 
. external. If RAME is set and not in 
Mode 3, the RAM is included in the in- 
ternal map. 

Bit 7 STBY PWR Standby Power. This bit is a read/ 
write status bit which, when once set, 
remains set as long as Vcc standby re- 
mains above VsBB (minimum). As 
long as this bit is set following a period 
of standby operation, the standby 
power supply has adequately preserv- 
ed the data in the standby RAM. If this 
bit is cleared during a period of stand- 
by operation, it indicates that Vcc 
standby had fallen to a level suffi- 
ciently below Vsbb (minimum) to 
suspect that data in the standby RAM 
is not valid. This bit can be set only by 
software and is not affected during 
reset. 

Note that if PPC and PLC are set, they cannot be 
simultaneously cleared with a single MPU write. The PLC bit 
must be cleared prior to attempting to clear PPC. If both PPC 
and PLC are clear, setting PLC will also set PPC. In addition, 



MOTOROLA MICROPROCESSOR DATA 
3-193 



MC68701 



it is assumed that Vpp is applied to the RESET/Vpp pin 
whenever PPC is clear. If this is not the case, the result is 
undefined. 

ERASING THE MC68701 EPROM 

Ultraviolet erasure will clear all bits of the EPROM to the 
"0" state. Note that this erased state differs from that of 
some other widely used EPROMs (such as the MCM68708) 
where the erased state is a "1". The MC68701 EPROM is 
programmed by erasing it to "0's" and entering "1's" into 
the desired bit locations. 

The MC6870T EPROM can be erased by exposure to high 
intensity ultraviolet light with a wave length of 2537A for a 
minimum of 30 minutes. The recommended integrated dose 
(UV intensity X exposure time) is 15 Ws/cm. The lamps 
should be used without shortwave filters and the MC68701 
should be positioned about one inch away from the UV 
tubes. 

The MC68701 transparent lid should always be covered 
after erasing. This protects both the EPROM and light- 
sensitive nodes from accidental exposure to ultraviolet light. 

PROGRAMMING THE MC68701 EPROM 

When the MC68701 is released from Reset in Mode 0, a 
vector is fetched from location $BFFE:BFFF. This provides a 
method for an external program to obtain control of the 
microcomputer with access to every location in the EPROM. 

To program the EPROM, it is necessary to operate the 
MC68701 in Mode 0 under the control of a program resident 
in external memory which can facilitate loading and pro- 
gramming of the EPROM. After the pattern has been loaded 
into external memory, the EPROM can be programmed as 
follows: 

a. Apply programming power (Vpp) to the RESET/Vpp 
pin. 

b. Clear the PLC control bit and set the PPC bit by 
writing $FE to the RAM/EPROM Control Register. 

c. Write data to the next EPROM location to be pro- 
grammed. Triggered by an MPU write to the 
EPROM, internal latches capture both the EPROM 
address and the data byte. 

d. Clear the PPC bit for programming time, tp p , by 
writing $FC to the RAM/EPROM Control Register 
and waiting for time, t pp . This step ga tes the pro- 
gramming power (Vpp) from the RESET/Vpp pin to 
the EPROM which programs the location. 

e. Repeat steps b through d for each byte to be pro- 
grammed. 

f. Set the PLC and PPC bits by writing $FF to the 
RAM/EPROM control register. 

g. Remov e the programming power (Vpp) from the 
RESET/Vpp pin. The EPROM can now be read and 
verified. 



Because of the erased state of an EPROM byte is $00, it is 
not necessary to program a location which is to contain $00. 
Finally, it should be noted that the result of inadvertently 
programming a location more than once is the logical OR of 
the data patterns. 

PRObug is a trademark of Motorola Inc. 



A routine which can be used to program the MC68701 
EPROM is provided at the end of this publication. This non- 
reentrant routine requires four double byte variables named 
IMBEQ, IMEND, PNTR, and WAIT to be initialized prior to 
entry to the routine. These variables indicate (a) the first and 
last memory locations which bound the data to be program- 
med into the EPROM, (b) the first EPROM location to be pro- 
grammed, and (c) a number which is used to generate 
the programming time delay. The last variable, WAIT, takes 
into account the MCU input crystal (or TTL-compatible 
clock) frequency to insure the programming time, tpp, is 
met. WAIT is defined as the number of MPU E-cycles that 
will occur in the real-time EPROM programming interval, 
t p p. For example, if t pp = 50 milliseconds and the MC68701 
is being driven with a 4.00 MHz TTL-compatible clock: 
WAIT (MPU E-cycles) = . t pp * (MCU INPUT FREQ/)4* 10® 

= 50000(4. 106)/4*106 

= 50000 

NOTE 

A monitor program called PRObug is available from 
Motorola Microsystems. PRObug contains a user option for 
programming the on-board MC68701 EPROM. 



PROGRAMMABLE TIMER 

The Programmable Timer can be used to perform input 
waveform measurements while independently generating an 
output waveform. Pulse widths can vary from several 
microseconds to many seconds. A block diagram of the 
Timer is shown in Figure 21. 

COUNTER ($09:0A) 

The key timer element is a 16-bit free-running counter 
which is incremented by E (Enable). It is cleared during reset 
and is read-only with one exception: a write to the counter 
($09) will preset it to $FFF8. This feature, intended for 
testing, can disturb serial operations because the counter 
provides the SCI internal bit rate clock. TOF is set whenever 
the counter contains all Vs. 

OUTPUT COMPARE REGISTER ($0B:0C) 

The Output Compare Register is a 16-bit Read/ Write 
register used to control an output waveform or provide an ar- 
bitrary timeout flag. It is compared with the free-running 
counter on each E-cycle. When a match occurs, OCF is set 
and OLVL is clocked to an output level register. If Port 2, bit 
1, is configured as an output, OLVL will appear at P21 and 
the Output Compare Register and OLVL can then be 
changed for the next compare. The function is inhibited for 
one cycle after a write to the high byte of the Compare 
Register ($0B) to ensure a valid compare. The Output Com- 
pare Register is set to $FFFF during reset. 

INPUT CAPTURE REGISTER ($0D:0E) 

The Input Capture Register is a 16-bit read-only register 
used to store the free-running counter when a "proper" in- 
put transition occurs as defined by IEDG. Port 2, bit 0 should 
be configured as an input, but the edge detect circuit always 



MOTOROLA MICROPROCESSOR DATA 
3-194 



MC68701 



FIGURE 21 - BLOCK DIAGRAM OF PROGRAMMABLE TIMER 



MC68701 Internal Bus 



H $09:OA 


H $0D:0E 


Free Running 


Input Capture 


16 Bit Counter 


Register 1 



Overflow Detect 



Timer b7y 
Control ' 
And 
Status 
Register 
$08 



ICF OCF TOF EICI EOCI ETOI IEDG OLVL 



Output 
Level 
Register 



Output Compare Pulse 




senses P20 even when configured as an output. An input 
capture can occur independently of ICF: the register always 
contains the most current value. Counter transfer is in- 
hibited, however, between accesses of a double byte MPU 
read. The input pulse width must be at least two E-cycles to 
ensure an input capture under all conditions. 

TIMER CONTROL AND STATUS REGISTER ($08) 

The Timer Control and Status Register (TCSR) is an 8-bit 
register of which all bits are readable while bits 0-4 can be 
written. The three most significant bits provide the timer 
status and indicate if: 

• a proper level transition has been detected, 

• a match has occurred between the free-running 
counter and the output compare register, and 

• the free-running counter has overflowed. 

Each of the three events can generate an IRQ2 interrupt 
and is controlled by an individual enable bit in the TCSR. 

TIMER CONTROL AND STATUS REGISTER (TCSR) 



7 


6 


5 


4 


3 . 


2 


1 


0 


ICF 


OCF 


TOF 


EICI 


EOCI 


ETOI 


IEDG 


OLVL 



Bit 0 OLVL Output level. OLVL is clocked to the 

output level register by a successful 
output compare and will appear at P21 
if Bit 1 of the Port 2 Data Direction 
■ ; ■ Register is set. It is cleared during 

reset. 

Bit 1 EIDG Input Edge. IEDG is cleared during 

reset and controls which level transi- 
tion will trigger a counter transfer to 
the Input Capture Register: 
IEDG = 0 Transfer on a negative-edge 
IEDG = 1 Transfer on a positive-edge. 

Bit 2 ETOI Enable Timer Overflow Interrupt. 

When set, an IRQ2 interrupt is enabled 
for a timer overflow; when clear, the 
interrupt is inhibited. It is cleared dur- 
ing reset. 

Bit 3 EOCI Enable Output Compare Interrupt. 

When set, an IRQ2 interrupt is enabled 
for an output compare; when clear, 
the interrupt is inhibited. It is cleared 
during reset. 

Bit 4 EICI Enable Input Capture Interrupt. When 

set, an IRQ2 interrupt is enabled for an 
input capture; when clear, the inter- 
rupt is inhibited. It is cleared during 
reset. 



MOTOROLA MICROPROCESSOR DATA 
3-195 



MG68701 



Bit 5 TOF Timer Overflow Flag. TOF is set when 

the counter contains all Vs. It is 
cleared by reading the TCSR (with 
TOF set) then reading the counter high 
byte ($09), or by RESET. 

Bit 6 OCF Output Compare Flag. OCF is set 

when the Output Compare Register 
matches the free-running counter., It is 
cleared by reading the TCSR (with 
OCF set) and then writing to the Out- 
put Compare Register ($0B or $0C), or 
by RESET. 

Bit 7 ICF Input Capture Flag. ICF is set to in- 

dicate a proper level transition; it is 
cleared by reading the TCSR (with ICF 
set) and then the Input Capture 
Register High Byte ($0D), or by 
RESET. 



SERIAL COMMUNICATIONS INTERFACE (SCI) 

A full-duplex asynchronous Serial Communications Inter- 
face (SCI) is provided with two data formats and a variety of 
rates. The SCI transmitter and receiver are functionally in- 
dependent, but use the same data format and bit rate. Serial 
data formats include standard mark/space (NRZ) and Bi- 
phase and both provide one start bit, eight data bits, and one 
stop bit. "Baud" and "bit rate" are used synonymously in 
the following description. 

WAKE-UP FEATURE 

In a typical serial loop multi-processor configuration, the 
software protocol will usually identify the addressee(s) at the 
beginning of the message. In order to permit uninterested 
MPU's to ignore the remainder of the message, a wake-up 
feature is included whereby all further SCI receiver flag (and 
interrupt) processing can be inhibited until the data line goes 
idle. An SCI receiver is re-enabled by an idle string of 11 
consecutive Ts or during reset. Software must provide for 
the required idle string between consecutive messages and 
prevent it within messages. • . 

PROGRAMMABLE OPTIONS \ 

The following features of the SCI are programmable: 

• format: standard mark/space (NRZ) or Bi-phase 

• clock: external or internal bit rate clock 

• Baud : one of 4 per E-clock frequency, or ex- 
ternal clock (X8 desired baud) 

• wake-up feature: enabled or disabled 

• interrupt requests: enabled individually for trans- 
mitter and receiver 

• clock output: internal bit rate clock enabled or dis- 
abled to P22 

SERIAL COMMUNICATIONS REGISTERS 

The Serial Communications Interface includes four ad- 
dressable registers as depicted in Figure 22. It is controlled 
by the Rate and Mode Control Register and the 



Transmit/ Receive Control and Status Register. Data is 
transmitted and received utilizing a write-only Transmit 
Register and a read-only Receive Register. The shift registers 
are not accessible to software. 

Rate and Mode Control Register (RMCR) ($10) 

The Rate and Mode Control Register controls the SCI bit 
rate, format, clock source, and under certain conditions, the 
configuration of P22. The register consists of four write-only 
bits which are cleared during reset. The two least significant 
bits control the bit rate of the internal clock and the remain- 
ing two bits control the format and clock source. 



RATE AND MODE CONTROL REGISTER (RMCR) 



X 



X 



X 



X CC1 ceo 



SS1 



0 

SSO I $0010 



Bit 1 :Bit 0 SS1.SS0 Speed Select. These two 

bits select the Baud rate when using 
the internal clock. Four rates may be 
selected which are a function of the 
MCU input frequency. Table 6 lists bit 
time and rates for three selected MCU 
frequencies. 

Bit 3:Bit 2 CC1:CC0 Clock Control and Format 

Select. These two bits control the for- 
mat and select the serial clock source. 
If CC1 is set, the DDR value for P22 is 
forced to the complement of CC0 and 
cannot be altered until CC1 is cleared. 
If CC1 is cleared after having been set, 
its DDR value is unchanged. Table 7 
defines the formats, clock source, and 
use of P22. 

If both CC1 and CC0 are set, an external TTL compatible 
clock must be connected to P22 at eight times (8X) the 
desired bit rate, but not greater than E, with a duty cycle of 
50% (±10%). If CC1:CC0= 10, the internal bit rate clock is 
provided at P22 regardless of the values for TE or RE. 
NOTE: The source of SCI internal bit rate clock is the timer 

free running counter. An MPU write to the counter 

can disturb serial operations. 

Transmit/ Receive Control And Status Register 
(TRCSR) ($11) 

The Transmit/ Receive Control and Status Register con- 
trols the transmitter, receiver, wake-up feature, and two in- 
dividual interrupts and monitors the status of serial opera- 
tions. All eight bits are readable while bits 0 to 4 are also 
writable. The register is initialized to $20 by RESET. 



TRANSMIT/RECEIVE CONTROL AND STATUS 
REGISTER (TRCSR) 



7 


6 


5 


4 


3 


2 


1 


0 




RDRF 


ORFE 


TDRE 


RIE 


RE 


TIE 


TE 


WU 


$0011 



MOTOROLA MICROPROCESSOR DATA 
3-196 



MC68701 



TABLE 6 - SCI BIT TIMES AND RATES 



SS1:SS0 


4f c - 


2.4576 MHz 


4.0 MHz 


4.9152 MHz 


E 


614.4 kHz 


1.0 MHz 


1.2288 MHz 


0 0 


+ 16 


26 *is/38,400 Baud 


16 ks/62,500 Baud 


13.0 /ts/76,800 Baud 


0 1 


+ 128 


208 >s/4,800 Baud 


128 ms/7812.5 Baud 


104.2 /ts/9,600 Baud 


1 0 


+ 1024 


1 .67 ms/600 Baud 


1 .024 ms/976.6 Baud 


833.3 ,iS/ 1,200 Baud 


1 1 


+ 4096 


6.67 ms/150 Baud 


4.096 ms/244.1 Baud 


3.33 ms/300 Baud 


, External 


P22) 


Up to 76,800 Baud 


Up to 125,000 Baud 


Up to 153,600 Baud 



TABLE 7 - SCI FORMAT AND CLOCK SOURCE CONTROL 



CC1:CC0 


Format 


Clock Source 


Port 2, Bit 2 


0 0 


Bi-Phase 


Internal 


Not Used 


0 1 


NRZ 


Internal 


Not Used 


1 0 


NRZ 


Internal 


Output 


1 1 


NRZ 


External 


Input 



FIGURE 22 - SCI REGISTERS 

Bit 7 Rate and Mode Control Register Bit O 





CC1 


CCO 


SS1 


sso 


Tran 


smit/Receive Control and Status Register 




RORF 


ORFE 


TORE 


RIE 


RE 


TIE 


TE 


wu 






Recei> 


re Data Register 




















^^^^ (Not Addressable) 


Receive Shift Register 




Clock 
Bit 
2 



Bit Rate 
Generator 



(Not Addressable) 



Transmit Shift Register 



on 



Transmit Data Register 



MOTOROLA MICROPROCESSOR DATA 
3-197 



MC68701 



Bit 0 WU 



Bit 1 TE 




Bit 2 TIE 



Bit 3 RE 



Bit 4 RIE 



Bit 5 TDRE 



Bit 6 ORFE 



"Wake-up" on Idle Line. When set, 
WU enables the wake-up function; it is 
cleared by 1 1 [consecutive 1's or dur- 
ing reset: WU will not set if the line is 
idle. 

Transmit Enable. When set, P24 DDR 
bit is set, cannot be changed, and will 
remain set if TE is subsequently 
cleared. When TE is changed from 
clear to set, the transmitter is con- 
nected to P24 and a preamble of nine 
consecutive 1's is transmitted. TE is 
cleared during reset. 
Tra nsmit Interrupt Enable. When set, 
an IRQ2 interrupt is enabled when 
TDRE is set; when clear, the interrupt 
is inhibited. TE is cleared during reset. 
Receive Enable. When set, the P23 
DDR bit is cleared, cannot be chang- 
ed, and will remain clear if RE is subse- 
quently cleared. While RE is set, the 
SCI receiver is enabled. RE is cleared 
during reset. 

Receiver Interrupt Enable. When set, 
an IRQ2 interrupt is enabled when 
RDRF and/or ORFE is set; when clear, 
the interrupt is inhibited. RIE is cleared 
during reset. 

Transmit Data Register Empty. TDRE 
is set when the Transmit Data Register 
is transferred to the output serial shift 
register or during reset. It is cleared by 
reading the TRCSR (with TDRE set) 
and then writing to the Transmit Data 
Register. Additional data will, be 
transmitted only if TDRE has -been 
cleared. 

Overrun Framing Error. If set, ORFE in- 
dicates either an overrun or framing er- 
ror. An overrun is a new byte ready to 
transfer to the Receiver Data Register 
with RDRF still set. A receiver framing 
error has occurred when the byte 
boundaries of the bit stream are not 



synchronized to the bit counter. An 
overrun can be distinguished from a 
framing error by the state of RDRF: if 
RDRF is set, then an overrun has oc- 
curred; otherwise a framing error has 
been detected. Data is not transferred 
to the Receive Data Register in an 
overrun condition. Unframed data 
causing a framed error is transferred to 
the Receive Data Register. However, 
subsequent data transfer is blocked 
until the framing error flag is cleared.* 
ORFE is cleared by reading the TRCSR 
(with ORFE set) then the Receive Data 
Register, or during reset. 
Bit 7 RDRF Receive Data Register Full. RDRF is 

set when the input serial shift register 
is transferred to the Receive Data 
Register. It is cleared by reading the 
TRCSR (with RDRF set), and then the 
Receive Data Register, or during reset. 

SERIAL OPERATIONS 

The SCI is initialized by writing control bytes first to the 
Rate and Mode Control Register and then to the 
Transmit/ Receive Control and Status Register. When TE is 
set, the output of the transmit serial shift register is con- 
nected to P24 and serial output is initiated by transmitting to 
9-bit preamble of Vs. 

At this point one of two situations exist: 1) if the Transmit 
Data Register is empty (TDRE= 1 ), a continuous string of 1's 
will be sent indicating an idle line, or 2) if a byte has been 
written to the Transmit-Data Register (TDRE = 0), it will be 
transferred to the output serial shift register (synchronized 
with the bit rate clock), TDRE will be set, and transmission 
will begin. 

The start bit (0), eight data bits (beginning with bit 0) and a 
stop bit (1), will be transmitted. If TDRE is still set when the 
next byte transfer should occur, . 1's will be sent until more 
data is provided. In Bi-phase format, the output toggles at 
the start of each bit and at half-bit time when a "1" is sent. 
Receive operation is controlled by RE which configures P23 
as an input and enables the receiver. SCI data formats are il- 
lustrated in Figure 23. 



FIGURE 23 - SCI DATA FORMATS 



Output 
Clock 



NRZ 
Format 



uiiwiiinATiwiA 



: : : | 



I 



I . ■ 

i i . i- 



Bi-Phase 
Format 



imjLTLJin_rir1_ru 

Bit Bit 
Idle Start n , 2 3 4 5 6 7 Stop 
Data: 01001101 ($4D) 



* Devices made with mask numbers T7A and CB4 do not transfer unframed data to the Receive Data Register. 



MOTOROLA MICROPROCESSOR DATA 
3-198 



MC68701 



INSTRUCTION SET 

The MC68701 is upward source and object code compati- 
ble with the MC6800. Execution times of key instructions 
have been reduced and several new instructions have been 
added, including a hardware multiply. A list of new opera- 
tions added to the MC6800 instruction set is shown in 
Table 1. In addition, two new special opcodes, 4E and 5E, 
are provided for test purposes. These opcodes force the pro- 
gram counter to increment like a 16-bit counter, causing ad- 
dress lines used in the expanded modes to increment until 
the device is reset. These opcodes have no mnemonics. 

The coding of the first (or only) byte corresponding to an 
executable instruction is sufficient to identify the instruction 
and the addressing mode. The hexadecimal equivalents of 
the binary codes, which result from the translation of the 82 
instructions in. all valid modes of addressing, are shown in 
Table 8. There are 220 valid machine codes, 34 unassigned 
codes, and 2 reserved for test purposes. 

PROGRAMMING MODEL 

A programming model for the MC68701 is shown in Figure 
9. Accumulator A can be concatenated with accumulator B 
and jointly referred to as accumulator D where A is the most 
significant byte. Any operation which modifies the double 
accumulator will also modify accumulator A and/or B. Other 
registers are defined as follows: 

Program Counter - The program counter is a 16-bit 
register which always points to the next instruction. 

Stack Pointer - The stack pointer is a 16-bit register 
which contains the address of the next available location in a 
pushdown/pullup (LIFO) queue. The stack resides in ran- 
dom access memory at a location defined by the program- 
mer. 

Index Register - The Index Register is a 16-bit register 
which can be used to store data or provide an address for the 
indexed mode of addressing. 

Accumulators - The MCU contains two 8-bit ac- 
cumulators, A and B, which are used to store operands and 
results from the arithmetic logic unit (ALU). They can also be 
concatenated and referred to as the D (double) accumulator. 

Condition Code Registers - The condition code register 
indicates the results of an instruction and includes the 
Overflow (V), Carry/Borrow from MSB (C), and Half Carry 
following five condition bits: Negative (N), Zero (Z), 



from bit 3 (H). These bits are testable by the conditional 
branch instructions. Bit 4 is the interrupt mask (l-bit) and in- 
hibits all maskable interrupts when set. The two unused bits, 
B6 and B7 are read as ones. 

ADDRESSING MODES 

The MC68701 provides six addressing modes which can be 
used to reference memory. A summary of addressing modes 
for all instructions is presented in Tables 9, 10, 11, and 12 
where execution times are provided in E cycles. Instruction 
execution times are summarized in Table 13. With an input 
frequency of 4 MHz, E cycles are equivalent to micro- 
seconds. A cycle-by-cycle description of bus activity for 
each instruction is provided in Table 14 and a description of 
selected instructions is shown in Figure 24. 

Immediate Addressing - The operand or "immediate 
byte(s)" is contained in the following byte(s) of the instruc- 
tion where the number of bytes matches the size of the 
register. These are two or three byte instructions. 

Direct Addressing - The least significant byte of the 
operand address is contained in the second byte of the in- 
struction and the most significant byte is assumed to be $00. 
Direct addressing allows the user to access $00 through $FF 
using two byte instructions and execution time is reduced by 
eliminating the additional memory access. In most applica- 
tions, the 256-byte area is reserved for frequently referenced 
data. 

Extended Addressing - The second and third bytes of the 
instruction contain the absolute address of the operand. 
These are three byte instrutions. 

Indexed Addressing - The unsigned offset contained in 
the second byte of the instruction is added with carry to the 
Index Register and used to reference memory without 
changing the Index Register. These are two byte instruc- 
tions. 

Inherent Addressing — The operand(s) are registers and 
no memory reference is required. These are single byte in- 
structions. 

Relative Addressing - Relative addressing is used only for 
branch instructions. If the branch condition is true, the Pro- 
gram Counter is overwritten with the sum of a signed single 
byte displacement in the second byte of the instruction and 
the current Program Counter. This provides a branch range 
of - 126 to 129 bytes from the first byte of the instruction. 
These are two byte instructions. 



MOTOROLA MICROPROCESSOR DATA 
3-199 



MC68701 



TABLE 8 - CPU INSTRUCTION MAP 



OP MNEM MODE - I OP MNEM MODE ~ 



OP MNEM MODE 



I OP MNEM MODE - I OP MNEM MODE - 



INHER 

A 



LSRD 

ASLD 

TAP 

TPA 

INX 

DEX : 

CLV 

SEV 

CLC 

SEC 



SBA 
CBA 



TAB 
TBA 



BRA 

BRN 

BHI 

BLS 

BCC 

BCS 

BNE 

BEQ 

BVC 

BVS 

BPL 

BMI 

8GE 

BLT 

BGT 

BLE 

TSX 

INS 

PULA 

PULB 



INHER 
INHER 



REL 
INHER 



DES 

TXS 

PS HA 

PSHB 

PULX 

RTS 

ABX 

RTI 

PSHX 

MUL 

WAI 

SWI 

NEGA 



COMA 
LSRA 

RORA 
ASRA 
ASLA 
ROLA 
DECA 

INCA 
TSTA 
T 

CLRA 
NEGB 



COMB 
LSRB 

RORB 
ASRB 
ASLB 
ROLB 
DEGB 

INCB 
TSTB 
T 

CLRB 
NEG 



INHER 

A 



COM 
LSR 



ROR 
ASR 



INHER 
INDXD 

A 



INDXD 

A 



INDXD 
EXTND 



t 

INDXD 



ASL 
ROL 
DEC 



TST 
JMP 
CLR 
NEG 



COM 
LSR 

ROR 
ASR 
ASL 
ROL 
DEC 



TST 
JMP 
CLR EXTND 
SUBA IMMED 
CMPA 
SBCA 
SUBD 
ANDA 
BITA 
LDAA 

EORA 
ADCA 
ORAA 
ADDA 
CPX IMMED 
BSR REL 
LDS IMMED 

SUBA DIR 
CMPA 
SBCA 
SUBD 
ANDA 
BITA 
LDAA 
STAA 
EORA 
ADCA 
ORAA 
ADDA 



CPX 

JSR 

LDS 

STS 

SUBA 

CMPA 

SBCA 

SUBD 

ANDA 

BITA 

LDAA 

STAA 

EORA 

ADCA 

ORAA 

ADDA 

CPX 

JSR 

LDS 

STS 

SUBA 

CMPA 

SBCA 

SUBD 

ANDA 

BITA 

LDAA 

STAA 

EORA 

ADCA 

ORAA 

ADDA 

CPX 

JSR 

LDS 

STS 

SUBB 

CMPB 

SBCB 

ADDD 

ANDB 

BITS 

LDAB 

EORB 
ADCB 
ORAB 
ADDS 
LDD 



INDXD 

A 



t 

INDXD 
EXTND 

A 



t 

EXTND 
IMMED 

A 



SUBB 
CMPB 
SBCB 
ADDD 
ANDB 
. BITB 
LDAB 
STAB 
EORB 
ADCB 
ORAB 
ADDS 
LDD 
STD 
LDX 

STX DIR 
SUBB INDXD 
CMPB 
SBCB 
ADDD 
ANDB 
BITB 
LDAB 
STAB 
EORB 
ADCB 
ORAB 
ADDB 
LDD 
STD . 
LDX 

STX INDXD 5 
SUBB EXTND 4 
CMPB 
SBCB 
ADDD 
ANDB 
BITB 
LDAB 
STAB 
EORB 
ADCB 
ORAB 
ADDB 
LDD 
STD 
LDX 

STX EXTND 5 . 
* UNDEFINED OP CODE 



NOTES: 

1 . Addressing Modes 

INHER -Inherent INDXD-lndexed IMMED-lmmediate 
REL« Relative EXTND "Extended DIR "Direct 

2. Unassigned opcodes are indicated by "•" and should not be executed. 

3. Codes marked by "T" force the PC to function as a 16-bit counter. 



MOTOROLA MICROPROCESSOR DATA 
3-200 



MC68701 



TABLE 9 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS 



Pointer Operations 


MNEM 


Immed 


Direct 


Index 


Extend 


Inherent 


Boolean/ 
Arithmetic Operation 


Condition Codes 


5 


4 


3 


2 


1 


0 


Op 


- 


# 


Op 


- 


I 


Op 


~ 


# 


Op 


- 


# 


Op 


~ 


# 


H 


1 


N 


Z 


V 


C 


Compare Index Register 


CPX 


8C 


4 


3 


9C 


5 


2 


AC 


6 


2 


BC 


6 


3 








X-M:M + 1 


• 


• 


i 


i 


t 


1 


Decrement Index Register 


DEX 


























09 


3 


1 


X-1-»X 


• 


• 


• 


t 


• 


• 


Decrement Stack Pointer 


DES 


























34 


3 


1 


SP-1— ►SP 














Increment Index Register 


INX 


























08 


3 


1 


X+1— X 




* 


* 


t 


• 


* 


Increment Stack Pointer 


INS 


























31 


3 


1 


1 SP+1 — SP 














Load Index Register 


LDX 


CE 


3 


3 


DE 


4 


2 


EE 


5 


2 


FE 


5 


3 








M-»X H ,(M + D — X|_ 


• 


• 


t 


1 


R 


• 


Load Stack Pointer 


LDS 


8E 


3 


3 


9E 


4 


2 


AE 


5 


2 


BE 


5 


3 








M.-*SP H ,(M + D — SP L 






1 


i 


R 




Store Index Register 


STX 








DF 


4 


2 


EF 


5 


2 


FF 


5 


3 








X H — M,X L — (M+1) 






i 


t 


R 




Store Stack Pointer 


STS 








9F 


4 


2 


AF 


5 


2 


BF 


5 


3 








SP H -*M,SP L -»IM + 1I 






t 


J 


R 




Index Reg — Stack Pointer 


TXS 


























35 


3 


1 


X-1— SP 














Stack Pntr- » Index Register 


TSX 


























30 


3 


1 


SP+1 —X 














Add 


ABX 


























3A 


3 


1 


B + X — X 














Push Data 


PSHX 


























3C 


4 


1 


X L — M SP ,SP-1 — SP 
X H — M SP ,SP-1— SP 














Pull Data 


PULX 


























38 


5 


1 


SP+1— ►SP,M S p-»X H 
SP+1 -»SP,M S p-»X L 















TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2) 



Accumulator and 
Memory Operations 


MNE 


Immed 


Direct 


Index 


Extend 


In her 


Boolean 
Expression 


Condition Codes 


Op 






Op 




# 


Op 






Op 






Op 


~ 


# 


H 


i 


N 


z 


V 


c 


Add Acmltrs 


ABA 


























1B 


2 


1 


A + B —A 


t 


• 


1 


I 


f 


1 


Add B to X 


ABX 


























3A 


3 


1 


OOB + X ~X 


• 


• 


• 


• 


• 


• 


Add with Carry 


ADCA 


89 


2 


2 


99 


3 


2 


A9 


4 


2 


B9 


4 


3 








A + M + C ~A 






• 
















ADCB 


C9 


2 


2 


D9 


3 


2 


E9 


4 


2 


F9 


4 


3 








B + M + C — B 






• 






- 


r 








Add 


ADDA 


8B 


2 


2 


9B 


3 


2 


AB 


4 


2 


BB 


4 


3 








A + M -A 






• 
















ADDB 


CB 


2 


2 


DB 


3 


2 


EB 


4 


2 


FB 


4 


3 








B + M — A 


II 


• 
















Add Double 


ADDD 


C3 


4 


3 


D3 


5 


2 


E3 


6 


2 


F3 


6 


3 








D + M:M + 1 — D 


□ 


• 




H 








t 


And 


ANDA 


84 


2 


2 


94 


3 


2 


A4 


4 


2 


B4 


4 


3 








A • M —A 


□ 


• 








R 


• 


ANDB 


C4 


2 


2 


D4 


3 


2 


E4 


4 


2 


F4 


4 


3 








B • M — B 


□ 


• 










R 


• 


Shift Left. 
Arithmetic 


ASL 














68 


6 


2 


78 


6 


3 
















r 






1 






ASLA 


























48 


2 


1 


ICI-H 1 1 1 1 1 1 1 l-»-o 






+ 






+ 






AS LB 


























58 


2 


1 


b7 bO 


















Shift Left Dbl 


ASLD 


























05 


3 


1 




□ 








1 


t 


Shift Right. 
Arithmetic 


ASR 














67 


6 


2 


77 


6 


3 










□ 








1 


t 


ASRA 


























47 


2 


1 


GlIIIIIIWsl 


□ 








I 


1 


ASRB 


























57 


2 


1 


b7 bO 


□ 








t 


1 


Bit Test 


BITA 


85 


2 


2 


95 


3 


2 


A5 


4 


2 


B5 


4 


3 








A • M 


□ 








R 


• 


BITB 


C5 


2 


2 


D5 


3 


2 


E5 


4 


2 


F5 


4 


3 








B • M 


□ 








R 


• 


Compare Acmltrs 


CBA 


























1 1 


2 


1 


A - B 


□ 








t 


} 


Clear 


CLR 














6F 


6 


2 


7F 


6 


3 








OO ■— M 


□ 




R 


s 


R 


R 


CLRA 


























4F 


2 


1 


00 - A 


□ 




R 


s 


R 


R 


CLR8 


























5F 


2 


1 


00 — B 


□ 




R 


s 


R 


R 


Compare 


CMPA 


81 


2 


2 


91 


3 


2 


A1 


4 


2 


B1 


4 


3 








A - M 


□ 










» 






CMPB 


C1 


2 


2 


D1 


3 


2 


E1 


4 


2 


F1 


4 


3 








B - M 


□ 










f 




h 


1 's Complement 


COM 














63 


6 


2 


73 


6 


3 








flA — M 


□ 










R 


S 


COMA 


























43 


2 


1 


tf-A 


□ 










R 


S 


COMB 


























53 


2 


1 


B-B 


□ 












R 


S 


Decimal Adj. A 


DAA 


























19 


2 


1 


Adj binary sum to BCD 
















1 


Decrement 


DEC 














6A 


6 


2 


7A 


6 


3 








M- 1 — M 


□ 






■ 








• 


DECA 


























4A 


2 


1 


A - 1 —A 


□ 










1 


• 


DECB 


























5A 


2 


1 


B - 1 — B 


□ 




t 




I 


• 


Exclusive OR 


EORA 


88 


2 


2 


98 


3 


2 


A8 


4 


2 


B8 


4 


3 








A © M —A 


□ 










R 


• 


EORB 


C8 


2 


2 


D8 


3 


2 


E8 


4 


2 


F8 


4 


3 








B © M — B 


□ 










R 


• 


Increment 


INC 














6C 


6 


2 


7C 


6 


3 








M+1 *-M 


□ 




t 








• 


INCA 


























4C 


2 


1 


A + 1 —A 


□ 




! 








• 


INCB 


























5C 


2 


1 


B + 1 — B 


□ 












• 


Load Acmltrs 


LDAA 


86 


2 


2 


96 


3 


2 


A6 


4 


2 


B6 


4 


3 








M —A 


□ 








R 


• 


LDAB 


C6 


2 


2 


D6 


3 


2 


E6 


4 


2 


F6 


4 


3 








M — B 


□ 








R 


• 


Load Double 


LDD 


CC 


3 


3 


DC 


4 


2 


EC 


5 


2 


FC 


5 


3 








M:M + 1 — D 


□ 








R 


• 


Logical Shift, 
Left 


LSL 














68 


6 


2 


78 


6 


3 








HHI III 1111-° 


□ 




I 




4 






LSLA 


























48 


2 


1 


□ 




1 


T 








LSLB 


























58 


2 


1 


b7 bO 


□ 






I 








LSLD 


























05 


3 


1 


□ 




i 


1 


i 







MOTOROLA MICROPROCESSOR DATA 
3-201 



MC68701 



TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2) 



Accumulator and 
Memory Operations 


MNE 


I m meet 


Direct 


Index 


Extend 


Inner 


Boolean 
Expression 


Condition Codes 


Op 




# 


Op 




# 


Op 




# 


Op 




# 


Op 


~ 


# 


H 


1 


N 


z 


V 


C 


Shift Right. 
Logical 


LSR 














64 


6 


2 


74 


6 


3 








—*. 




• 


R 


1 






1 


LSRA 


























44 


2 


1 


o-*l 1 1 1 1 1 1 1 Wd 

t>7 bO 




• 


R 


1 






| 


LSRB 


























54 


2 


1 




• 


R 










1 


LSRD 


























04 


3 


1 






• 


R 










1 


Multiply 


MUL 


























3D 


10 


1 


A X B — D 




• 


• 


• 


• 






2's Complement 
(Negate) 


NEG 














60 


6 


2 


70 


6 


3 








00 - M — M 




• 


1 


. | 


J 






NEGA 


























40 


2 


1 


00 - A —A 




• 


t 


} 


} 






NEGB 


























50 


2 


1 


00 - B — B 




• 


1 


1 


J 






No Operation 


NOP 


























01 


2 


1 


PC + 1 --PC 




• 


• 


• 


• 




Inclusive OR 


ORAA 


8A 


2 


2 


9A 


3 


2 


AA 


4 


2 


BA 


4 


3 








A + M— A 




• 






1 


R 




ORAB 


CA 


2 


2 


DA 


3 


2 


EA 


4 


2 


FA 


4 


3 








B + M -—B 




• 






1 


R 




Push Data 


PSHA 


























36 


3 


1 


A —Stack 




• 


• 


• 


• 




PSHB 


























37 


3 


1 


B —Stack 




• 


• 


• 


• 




Pull Data 


PULA 


























32 


4 


1 


Stack — A 




• 


• 


• 


• 




PULB 


























33 


4 


1 


Stack — B 




• 


• 


• 


• 




Rotate Left 


ROL 














69 


6 


2 


79 


6 


3 












• 


f 


f 


I 


1 


ROLA 


























49 


2 


1 


|iW I I I I I I I WiJ 

b7 . bO . 




• 






| 


I 


ROLB 


























59 


2 


1 




• 


| 




\ 


1 


Rotate Right 


ROR 














66 


6 


2 


76 


6 


3 












• 


t 




1 


1 


RORA 


























46 


2 


1 


fcUJI 1 1 1 1 1 1 UJcl 




• 


1 




i 


\ 


RORB 


























56 


2 


1 


07 bO 




• 


1 




1 




Subtract Acmltr 


SBA 


























10 


2 


1 


A - B — A 




• 








1 


X 


Subtract with 
Carry 


SBCA 


82 


2 


2 


92 


3 


2 


A2 


4 


2 


B2 


4 


3 








A - M - C -A 




• 




[ 










SBCB 


C2 


2 


2 


D2 


3 


2 


E2 


4 


2 


F2 


4 


3 








B - M - C — B 




• 














1 


Store Acmltrs 


STAA 








97 


3 


2 


A7 


4 


2 


B7 


4 


3 








A ■ — M 




• 










R 


• 


STAB 








D7 


3 


2 


E7 


4 


2 


F7 


4 


3 








B — M 




• 






1 


R 


• 


STD 








DD 


4 


2 


ED 


5 


2 


FD 


5 


3 








D — M:M + 1 










1 


R 


• 


Subtract 


SUBA 


80 


2 


2 


90 


3 


2 


AO 


4 


2 


BO 


4 


3 








A - M —A 










» 


1 


1 


SUBB 


CO 


2 


2 


DO 


3 


2 


EO 


4 


2 


FO 


4 


3 








B - M — B 








- 


4 


I 


1 


Subtract Double 


SUBD 


83 


4 


3 


93 


5 


2 


A3 


6 


2 


B3 


6 


3 








D - M M + 1 -»D 






H 






1 


t 


Transfer Acmltr 


TAB 


























16 


2 


1 


A -"-B 












R 


• 


TBA 


























17 


2 


1 


B —A 














R 


• 


Test, Zero or 
Minus 


TST 














6D 


6 


2 


7D 


6 


3 








M - 00 














R 


R 


TSTA 


























4D 


2 


1 


A - 00 














R 


R 


TST6 


























5D 


2 


1 


B 00 










1 


R 


R 



The condition code register notes are listed after Table 12. 



MOTOROLA MICROPROCESSOR DATA 
3-202 



MC68701 



TABLE 11 - JUMP AND BRANCH INSTRUCTIONS 

























Condition Code Reg. 






Direct 


Relative 


Index 


Extend 


Inherent 




5 


4 


3 


2 


1 


o 


Operations 


MNEM 


Op 


- 


# 


Op 


~ 


I 


Op 




I 


Op 


_ 


# 


Op 




I 


Branch Test 


H 


1 


N 


Z 


V 


c 


Branch Always 


BRA 








20 


3 


2 




















None 














Branch Never 


BRN 








21 


3 


2 




















None 














Branch If Carry Clear 


BCC 








24 


3 


2 




















C = 0 














Branch II Carry Set 


BCS 








25 


3 


2 




















C=1 














Branch If = Zero 


BEQ 








27 


3 


2 




















Z=1 














Branch If a Zero 


BGE 








2C 


3 


2 




















N © V = 0 














Branch If >Zero 


BGT 








2E 


;3 


2 




















Z+IN © V) = 0 














Branch If Higher 


BHI 








22 


3 


2 




















c+z=o 














Branch If Higher or Same 


BHS 








24 


3 


2 




















c = o 














Branch If sZero 


BLE 








2F 


3 


2 




















Z+IN © VI = 1 














Branch If Carry Set 


BLO 








25 


3 


2 




















C=1 














Branch If Lower Or Same 


BLS 








23 


3 


2 




















C + Z=1 














Branch If <Zero 


BLT 








2D 


3 


2 




















N © V = 1 














Branch If Minus 


BMI 








2B 


3 


2 




















N=1 














Branch If Not Equal Zero 


BNE 








26 


3 


2 




















Z = 0 














Branch If Overflow Clear 


BVC 








28 


3 


2 




















V = 0 














Branch If Overflow Set 


BVS 








29 


3 


2 




















V=1 














Branch If Plus 


BPL 








2A 


3 


2 




















N = 0 














Branch To Subroutine 


BSR 








80 


6 


2 


































Jump 


JMP, 














6E 


3 


2 


7E 


3 


3 








See Special Operations-Figure 24 














Jump To Subroutine 


JSR 


9D 


5 


2 








AD 


6 


2 


BD 


6 


3 






















No Operation 


NOP 


























01 


2 


1 
















Return From Interrupt 


RTI 


























3B 


10 


1 




t 


t 


t 


t 


i 


t 


Return From Subroutine 


RTS 


























39 


5 


1 


See Special Operations-Figure 24 














Software Interrupt 


SWI 


























3F 


12 


1 






S 










Wait For Interrupt 


WAI 


























3E 


9 


1 

















TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS 



Operations 


Inherent 


Boolean Operation 


Condition Code Register 


5 


4 


3 


2 


1 


0 


MNEM 


Op 






H 


I 


N 


Z 


V 


c 


Clear Carry 


CLC 


oc 


2 




0 — C 












R 


Clear Interrupt Mask 


CLI 


OE 


2 




0 — I 




R 






• 


• 


Clear Overflow 


CLV 


OA 


2 




0 — V 




• 






R 


■ • 


Set Carry 


SEC 


OD 


2 




1 — c 












s 


Set Interrupt Mask 


SEI 


OF 


2 




1 — 1 




s 






• 




Set Overflow 


SEV 


OB 


2 




1— V 




• 




• 


s 


. • 


Accumulator A— »CCR 


TAP 


06 


2 




A — CCR 


t 


t 


I 


t 


1 


t 


CCR — Accumulator A 


TPA 


07 


2 




CCR — A 















LEGEND CONDITION CODE SYMBOLS 



Op 


Operation Code (Hexadecimal) 


H 


Half-carry from bit 3 




Number of MPU Cycles 


1 


Interrupt mask 


Msp 


Contents of memory location pointed to by Stack Pointer 


N 


Negative (sign bit) 


# 


Number of Program Bytes 


Z 


Zero (byte) 


+ 


Arithmetic Plus 


V 


Overflow, 2's complement 




Arithmetic Minus 


c 


Carry/Borrow from MSB 


• 


Boolean AND 


R 


Reset Always 


X 


Arithmetic Multiply 


S 


Set Always 


+ 


Boolean Inclusive OR 


t 


Affected 


• 


Boolean Exclusive OR 


• 


Not Affected 


M 


Complement of M 








Transfer Into 






0 


Bit = Zero 






00 


Byte = Zero 







MOTOROLA MICROPROCESSOR DATA 
3-203 



MC68701 



TABLE 13 - INSTRUCTION EXECUTION TIMES IN E CYCLES 





ADDRESSING MODE 




ADDRESSING MODE 




Immediate 


Direct 


Extended 


Indexed 


Inherent 


Relative 




Immediate 


Direct 


Extended 


Indexed 


i 

Inherent 


Relative 


ABA 


• 


• 


• 


• 


2 


• 




I NX 


• 


• 


• 


• 


3 




ABX 


• 


. • 


• 




3 






JMP 


• 


• 


3 


3 


• 


• • 


ADC 




3 


4 


4 


• 


• 




JSR 


• 




6 


6 


• 


• 


ADD 




3 


4 


4 


• 


• 




LDA 


2 




4 


4 


• 


• 


ADDD 


4 


5 


6 




• 


• 




LDD 


3 


4 


5 


5 


• 


• 


AND 




3 


4 


4 


• ' 


• 




LDS 


3 


4 


5 


5 


• 


• 


ASL 


• 


• 


6 




2 


• 




LDX 


3 


4 


5 


5 


• 


• 


ASLD 


• 


• 


• 


• 


3 


• 




LSL 


• 


• 


6 


6 


2 


• 


ASR 


• 


• 


6 




2 


• 




LSLD 


• 


• 


• 


• 


3 


• 


BCC 


• 


• 


• 


• 


• 


3 




LSR 


• 


• 


6 


6 


2 


• 


BCS 


• 


• 


• 


• 


• 


3 




LSRD 


• 


• 


• 


• 


3 


• 


BEQ 


• 


• 


• 


• 


• 


3 




MUL 


• 


• 


• 


• 


10 


• 


BGE 


• 


• 


• 


• 


• 


3 




NEG 


• 


• 


6 




2 


• 


BGT 


• 


• 


• 


• 


• 


3 




NOP 


■ • 


• 


• 




2 


• 


BHI 


• 


• 


• 


• 


• 


3 




ORA 






4 




• 




BHS 


• 


• 


• 


• 


• 


3 




PSH 


• 


• 


• 


• 


3 


• 


BIT 






4 




• 


• 




PSHX 


• 


• 


• 


• 


4 


• 


BLE 


• 


• 


• 


• 


• 


3 




PUL 


• 


• 


• 


• 


4 


• 


BLO 


• 


• 


• 


• 


• 


3 




PULX 


• 


• 


• 


• 


5 


• 


BLS 


• 


• 


• 


• 


• 


3 




ROL 


• 


• 


6 




2 


• 


BLT 


• 


• 


• 


• 


• 


3 




ROR 


• 


• 


6 




2 


• ■ 


BMI 




• 


• 


• 


• 


3 




RTI 


• 


• 


• 


• 


10 


• 


BNE 


• 


• 


• 


• 


• 


3 




RTS 


• 


• 


• 




5 


• 


BPL 


• 


• 


• 


• 


• 


3 




SBA 


• 


• 


• 


• 


2 


• 


BRA 


• 


• 


• 


• 


• 


3 




SBC 






4 


4 


• 


• 


BRN 


• 


• 


• 


• 


• 


3 




SEC 


• 


• 


• 


• 


2 


• 


BSR 






• 






6 




SEI 






• 




2 




BVC 






• 






3 




SEV 






• 




2 




BVS 






• 






3 




STA 






4 


4 






CBA 






• 




2 






STD 






5 


5 






CLC 






• 




2 






STS 






5 


5 






CLI 






• 




2 






STX 






5 


5 






CLR 






6 




2 






SUB 






4 


4 






CLV 






• 




2 






SUBD 






6 


6 






CMP 






4 




• 






SWI 






• 




12 




COM 






6 




2 






TAB 






• 




2 




CPX 






6 




• 






TAP 






• 




2 




DAA 






• 




2 






TBA 






• 




2 




DEC 






6 




2 






TPA 






• 




2 




DES 






• 




3 






TST 






6 




2 




DEX 






• 




3 






TSX 






• 




3 




EOR 






4 




• 






TXS 






• 




3 




INC 






6 


6 


• 






WAI 






• 




S 




INS 






• 


• 


3 





















MOTOROLA MICROPROCESSOR DATA 
3-204 



MC68701 



SUMMARY OF 

Table 14 provides a detailed description of the information 
present on the Address Bus, Data Bus, and the Read/Write 
(R/W) line during each cycle of each instruction. 

The information is useful in comparing actual with ex- 
pected results during debug of both software and hardware 
as the program is executed. The information is categorized in 
groups according to addressing mode and number of cycles 



=-BY-CYCLE OPERATION 

per instruction. In general, instructions with the same ad- 
dressing mode and number of cycles execute in the same 
manner. Exceptions are indicated in the table. 

Note that during MPU reads of internal locations, the 
resultant value will not appear on the external Data Bus ex- 
cept in Mode 0. "High order" byte refers to the most signifi- 
cant byte of a 16-bit value. 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5) 



Address Mode and 
Instructions 


Cycles 


Cycle 
1 


Address Bus 


R/W 
Line 


Data Bus 


IMMEDIATE 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


2 


1 
2 


Opcode Address 
Opcode Address + 1 


1 
1 


Opcode 
Operand Data 


LDS 
LDX 
LDD 


3 


1 
2 
3 


Opcode Address 
Opcode Address +1 
Opcode Address +2 




Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


CPX 


4 


1 

2 
3 
4 


Opcode Address 
Opcode Address + 1 
Opcode Address +2 
Address Bus FFFF 




Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


SUBD 
ADDD 


DIRECT 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


3 


1 

2 
3 


Opcode Address 
Opcode Address + 1 
Address of Operand 




Opcode 

Address of Operand 
Operand Data 


STA 


3 


1 
2 
3 


Opcode Address 
Opcode Address + 1 
Destination Address 




Opcode 

Destination Address 
Data from Accumulator 


LDS 
LDX 
LDD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Address of Operand 
Operand Address + 1 




Opcode 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 


STS 
STX 
STD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Address of Operand 
Address of Operand + 1 




Opcode 

Address of Operand 

Register Data (High Order Byte) 

Register Data ( Low Order Byte) 


CPX 

SUBD 

ADDD 


5 


1 
2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Operand Address 
Operand Address + 1 
Address Bus FFFF 




Opcode 

Address of Operand 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


JSR 


5 


1 
2 
3 
4 
5 


Opcode Address 
Opcode Address + 1 
Subroutine Address 
Stack Pointer 
Stack Pointer - 1 


0 
0 


Opcode 

Irrelevant Data 

First Subroutine Opcode 

Return Address (Low Order Byte) 

Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-205 



MC68701 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5) 



a 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


» 


Address Bus 


Line 


Data Bus 


EXTENDED 


JMP 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ 1 


1 


Jump Address (High Order Byte) 






3 


Opcode Address + 2 


1 


Jump Address (Low Order Byte) 


ADC EOR 


4 


1 


Opcode Address 


— ^ — 


Opcode I 


ADD LDA 




2 


Opcode Address+ 1 


! 


Address of Operand 


AND ORA 




3 


Opcode Address +2 


1 


Address of Operand (Low Order Byte) 


BIT SBC 




4 


Address of Operand 


1 


Operand Data 


CMP SUB 












STA 


4 


1 


Opcode Address 


•I 


Opcode 






2 


Opcode Address + 1 


! 


Destination Address (High Order Byte) 






3 


Opcode Address+2 


1 


Destination Address (Low Order Byte) 






4 


Operand Destination Address 




Data from Accumulator 


LDS 


5 


1 


Opcode Address 


1 


Opcode 


LDX 




2 


Opcode Address + 1 


•I 


Address of Operand (High Order Byte) 


LDD 




3 


Opcode Address + 2 


1 


Address of Operand (Low Order Byte) 






4 


Address of Operand 


1 


Operand Data (High Order Byte) 






5 


Address of Operand + 1 


1 


Operand Data (Low Order Byte) 


STS 


5 


1 


Opcode Address 


1 


Opcode 


STX 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


STD 




3 


Opcode Address + 2 


1 


Address of Operand (Low Order Byte) 






4 


Address of Operand 




Operand Data (High Order Byte) 






5 


Address of Operand + 1 




Operand Data (Low Order Byte) 


ASL LSR 


6 


1 


Opcode Address 




Opcode 


ASR NEG 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


CLR ROL 




3 


Opcode Address + 2 


1 


Address of Operand (Low Order Byte) 


COM ROR 




4 


Address of Operand 


1 


Current Operand Data 


DEC TST* 




5 


Address Bus FFFF 


. 


Low Byte of Restart Vector 


INC 




6 


Address of Operand 




New Operand Data 


CPX 


6 


1 


Opcode Address 




Opcode 


SUBD 




2 


Opcode Address + 1 




Operand Address (High Order Byte) 


ADDD 




3 


Opcode Address + 2 




Operand Address (Low Order Byte) 






4 


Operand Address 




Operand Data (High Order Byte) 






5 


Operand Address + 1 




Operand Data (Low Order Byte) 






6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 


6 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Address of Subroutine (High Order Byte) 






3 


Opcode Address + 2 




Address of Subroutine (Low Order Byte) 






4 


Subroutine Starting Address 




Opcode of Next Instruction 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer- 1 


0 


Return Address (High Order Byte) 



•TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus=$FFFF. 



MOTOROLA MICROPROCESSOR DATA 
3-206 



MC68701 



TABLE 14 — CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 


INDEXED 


JMP 




3 


1 


Opcode Address 


1 


Opcode 








2 


Opcode Address + 1 


1 


Offset 








3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


ADC 


EOR 


4 


1 


Opcode Address 


1 


Opcode 


ADD 


LDA 




2 


Opcode Address + 1 


1 


Offset 


AND 


ORA 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


BIT 


SBC 




4 


Index Register Plus Offset 


1 


Operand Data 


CMP 


SUB 












STA 




4 


1 


Opcode Address 


1 


Opcode 








2 


Opcode Address +1 


1 


Offset 








3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 








4 


Index Register Plus Offset 




Operand Data 


LDS 




5 


1 


Opcode Address 


1 


Opcode 


LDX 






2 


Opcode Address + 1 


1 


Offset 


LDD 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 








4 


Index Register Plus Offset 


1 


Operand Data (High Order Byte) 








5 


Index Register Plus Offset + 1 


1 


Operand Data (Low Order Byte) 


STS 




5 


1 


Opcode Address 


1 


Opcode 


STX 






2 


Opcode Address + 1 


1 


Offset 


STD 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 








4 


Index Register Plus Offset 




Operand Data (High Order Byte) 








5 


Index Register Plus Offset + 1 




Operand Data (Low Order Byte) 


ASL 


LSR 


6 


. .1 


Opcode Address 


1 


Opcode 


ASR 


NEG 




2 


Opcode Address + 1 


1 


Offset 


CLR 


ROL 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


COM 


ROR 




4 


Index Register Plus Offset 


1 


Current Operand Data 


DEC 


TST« 




5 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


INC 






6 


Index Register Plus Offset 




New Operand Data 


CPX 




6 


1 


Opcode Address 




Opcode 


SUBD 






2 


Opcode Address + 1 




Offset 


ADDD 






3 


Address Bus FFFF 




Low Byte of Restart Vector . , 








4 


Index Register + Offset 




Operand Data (High Order Byte) 








5 


Index Register+ Offset+ 1 




Operand Data (Low Order Byte) 








6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 




6 


1 


Opcode Address 




Opcode 








2 


Opcode Address + 1 




Offset 








3 


Address Bus FFFF 




Low Byte of Restart Vector 








4 


Index Register + Offset 




First Subroutine Opcode 








5 


Stack Pointer 


0 


Return Address (Low Order Byte) 








6 


Stack Pointer- 1 


0 


Return Address (High Order Byte) 



*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF, 



MOTOROLA MICROPROCESSOR DATA 
3-207 



MC68701 



TABLE 14 — CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


I . 


Address Bus 


Line 


Data Bus 


INHERENT 


ABA DAA SEC 


2 


1 


Opcod6 Address 


1 


Opcode 


ASL DEC SEI 




2 


Opcode Address+T 


1 


Opcode of Next Instruction 


ASR INC SEV 












CBA LSR TAB 












CLC NEG TAP 












CLI NOP TBA 












CLP, ROL TPA 












CLV . ROR TST 












COM SBA 












ABX 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ 1 


1 


Irrelevant Data 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


ASLD 


3 


1 


Opcode Address 


1 


Opcode 


LSRD 




2 


Opcode Address + 1 


1 


Irrelevant Data 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


DES 


3 


1 


Opcode Address 


1 


Opcode 


INS 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Previous Stack Pointer Contents 


1 


Irrelevant Data 


INX 


3 


1 


Opcode Address 


1 


Opcode 


DEX 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


PSHA 


3 


1 


Opcode Address 


1 


Opcode 


PSHB 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Stack Pointer 




Accumulator Data 


TSX 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Stack Pointer 


1 


Irrelevant Data 


TXS 


3 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






.3 


Address Bus FFFF 




Low Byte of Restart Vector 


PULA 


4 


1 


Opcode Address 


1 


Opcode 


PULB 




2 


Opcode Address + 1 


1 


Opcode of Next Instruction 






3 


Stack Pointer 


■, 


Irrelevant Data 






4 


Stack Pointer + 1 


1 


Operand Data from Stack ■ ■ 


PSHX 


4 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 




Index Register (Low Order Byte) 




— - — 


4 


Stack Pointer— 1 




Index Register (High Order Byte) 




PU LX 


5 


1 


Opcode Address 


] 


Opcode 






2 


Opcode Address + 1 


] 


Irrelevant Data 






3 


Stack Pointer 


] 


Irrelevant Data 






4 


Stack Pointer + 1 




Index Register (High Order Byte) 






5 


Stack Pointer+2 




Index Register (Low Order Byte) 


RTS 


5 


1 


Opcode Address 


] 


Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 




Irrelevant Data 






4 


Stack Pointer + 1 




Address of Next Instruction (High Order Byte) 






5 


Stack Pointer+2 




Address of Next Instruction (Low Order Byte) 


WAI 


9 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Opcode of Next Instruction 






3 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






5 


Stack Pointer- 2 


0 


Index Register (Low Order Byte) 






6 


Stack Pointer- 3 


0 


Index Register (High Order Byte) 






7 


Stack Pointer -4 


0 


Contents of Accumulator A 






8 


Stack Pointer- 5 


0 


Contents of Accumulator B 






9 


Stack Pointer- 6 


0 


Contents of Cpndition Code Register 



MOTOROLA MICROPROCESSOR DATA 
3-208 



MC68701 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


» 


Address Bus 


Line 


Data Bus 



INHERENT 



MUL 


10 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ 1 


1 


Irrelevant Data 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






5 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






6 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






7 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






8 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






9 


Address Bus FFFF 


1 


'. Low Byte of Restart Vector 






10 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


RTI 


10 


1 


Opcode Address 


— j — 1 


Opcode 






2 


OpcodG Address + 1 


1 


Irrelevant Data 






3 


Stack Pointer 


. 


Irrelevant Data 






4 


Stdck Pointer+1 


1 


Contents of Condition Code Register from Stack 






5 


Stack Pointer + 2 


. 


Contents of Accumulator B from Stack 






6 


Stack Pointer + 3 


1 


Contents of Accumulator A from Stack 






7 


Stack Pointer + 4 


1 


Index Register from Stack (High Order Byte) 






8 


Stack Pointer + 5 




Index Register from Stack (Low Order Byte) 






g 


Stack Pointer + 6 




Next Instruction Address from Stack (High Order Byte) 






10 


Stack Pointer + 7 


1 


Next Instruction Address from Stack (Low Order Byte) 


SWI 


12 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






5 


Stack Pointer -2 


0 


Index Register (Low Order Byte) 






6 


Stack Pointer -3 


0 


Index Register (High Order Byte) 






7 


Stack Pointer -4 


0 


Contents of Accumulator A 






8 


Stack Pointer -5 


0 


Contents of Accumulator B 






9 


Stack Pointer -6 


0 


Contents of Condition Code Register 






10 


Stack Pointer- 7 


1 


Irrelevant Data 






11 


Vector Address FFFA (Hex) 


1 


Address of Subroutine (High Order Byte) 






12 


Vector Address FFFB (Hex) 


1 


Address of. Subroutine (Low Order Byte) 



RELATIVE 



BCC BHT BNE BLO 


3 


1 


Op Code Address 


1 


Op Code 


BCS BLE BPL BHS 




2 


Op Code Address +1 


1 


Branch Offset 


BEQ BLS BRA BRN 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


BGE BLT BVC 












BGT BMT BVS 












BSR 


6 


1 


Op Code Address 


1 


Op Code 






2 


Op Code Address +1 


1 


Branch Offset 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Subroutine Starting Address 


1 


Op Code of Next Instruction 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer -1 


O 


Return Address(High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-209 



to 



FIGURE 24 - SPECIAL OPERATIONS 



JSR, Jump to Subroutine 



PC 



EXTND 



BSR, Branch To Subroutine 



RTS, Return from Subroutine 
PC 



Main Program 



$9D = JSR 



Next Main Instr. 



K = Direct Address 
Main Program 



Next Main Instr 



Main Program 



$BD=JSR 



SH = Subr. Addr. 



SL=Subr. Addr. 



Main Program 



$8D=BSR 



± K = Offset 



Next Main Instr. 



SP 
SP-2 
SP-1 

SP 



SP 
SP-2 
SP-1 

SP 

SP 

SP 
SP+ 1 
SP + 2 



SWI, Software Interrupt 



PC 
RTN 



WAI, Wait for Interrupt 



RTN H 



RTN L 



RTN 



RTI, Return from Interrupt 



RTN H 



RTN L 



JMP. Jump 



RTN H 



RTN(_ 



Legend: 

RTN = Address of next instruction in Main Program to be executed upon return from subroutine 
RTNh = Most significant byte of Return Address 
RTNl= Least significant byte of Return Address 
— • = Stack Pointer After Execution 
K = 8-bit Unsigned Value 



Main Program 



Main Program 



S3E = WAI 



Interrupt Program 



S3B = RTI 



Main Program 



$6E=JMP 



Next Instruction 



SP 


Stack 


SP-7 




SP-6 


Condition Code 


SP-5 


Acmltr B 


SP-4 


Acmltr A 


SP-3 


Index Register 1X^1 


SP-2 


Index Register (Xl) 


SP- 1 


RTN H 


SP 


RTNl 


SP 


Stack 


SP 




SP+1 


. Condition Code 


SP + 2 


Acmltr B 


SP + 3 


Acmltr A : 


SP + 4 


Index Register (Xh) 


SP + 5 


Index Register (Xi_) 


SP + 6 


rtn h 


SP + 7 


rtn l 


PC 


Main Program 




$7E=JMP 




Kh= Next Address 




KL=Next Address 






^ K 


| Next Instruction 



o 

00 

o 



MC68701 



EPROM PROGRAMMING ROUTINE 





.SA:1 


EPROM 


*** ROUTINE TO PROGRAM THE MC68701 EPROM *** 


00001 




NAM 


EPROM 


00002 




OPT 


Z01,LLEN=80 


00003 




TTL 


*** ROUTINE TO PROGRAM THE MC68701 EPROM ** 


00004 








00005 


********************************************** 


00006 


* 






00007 


* 


E P R 0 


M — A NON-REENTRANT ROUTINE TO PROGRAM 


00008 


* 




THE MC68701 EPROM. 


00009 


* 






00010 


* 




THE ROUTINE PROGRAMS THE MC68701 EPROM 


00011 


* 




STARTING AT ADDRESS "PNTR" FROM A 


00012 


* 




BLOCK OF MEMORY STARTING AT "IMBEG" 


00013 


* 




AND ENDING AT "IMEND". 


00014 


* 






00015 


* 


CALLING 


CONVENTION: 


00016 


* 






00017 


* 


JSR 


EPROM 


00018 


* 






00019 


* 


NOTES: 




00020 


* 






00021 


* 


1. 


THE ROUTINE EXPECTS FOUR DOUBLE BYTE VALUES 


00022 


* 




TO BE INITIALIZED PRIOR TO BEING CALLED. 


00023 


* 




THESE VALUES ARE: 


00024 


* 






00025 


* 




IMBEG = A DOUBLE BYTE ADDRESS WHICH POINTS 


00026 


* 




TO THE FIRST BYTE TO BE PROGRAMMED 


00027 


* 




INTO THE EPROM. 


00028 


* 






00029 


* 




IMEND = A DOUBLE BYTE ADDRESS WHICH POINTS 


00030 


* 




TO THE LAST BYTE TO BE PROGRAMED IN- 


00031 


* 




INTO THE EPROM. 


0003 2 


* 






00033 


* 




PNTR - A DOUBLE BYTE ADDRESS WHICH POINTS 


00034 


* 




TO THE FIRST BYTE IN THE EPROM TO BE 


00035 


* 




PROGRAMMED . 


00036 


* 






00037 


* 




WAIT = A DOUBLE BYTE COUNTER VALUE WHICH IS 


00038 


* 




A FUNCTION OF THE MCU INPUT FREQUEN- 


00039 


* 




CY AND IS USED WITH THE OUTPUT COM- 


00040 


* 




PARE FUNCTION TO GENERATE A 50 MSEC 


00041 


* 




TIMEOUT. IT IS EQUIVALENT TO 


00042 


* 






00043 


* 




50000 * (MCU INPUT FREQ) / 4 * 10**6 


00044 








00045 


* 




VALUES FOR TYPICAL INPUT FREQS ARE: 


00046 


* 




00047 


* 




WAIT MCU INPUT FREQ 


00048 


* 






00049 


* 




30615 ($7797) 2.45 MHZ 


00050 


* 




50000 ($C350) 4.00 MHZ 


00051 


* 




61375 ($EFBF) 4.91 MHZ 


00052 


* 






00053 


* 


2. 


IT IS ASSUMED THAT POWER (VPP) IS AVAILABLE 


00054 


* 




TO THE RESET PIN FOR PROGRAMMING. 


00055 


* 






00056 


* 


3. 


THIS ROUTINE PERFORMS NO ERROR CHECKING. 


00057 


* 






00058 


* 


Routine parameter initialization, such as stack pointer, etc., must be done prior to 



(Use of PRObug will ensure all needed initialization ! 



MOTOROLA MICROPROCESSOR DATA 
3-211 



MC68701 



EPROM PROGRAMMING ROUTINE 



PAGE 002 EPROM .SA:1 EPROM *** ROUTINE TO PROGRAM THE MC68701 EPROM *** 



00060 














00061 






* E Q U A T 


E S 




00062 














00063 




0008 


A TCSR 


EQU 


$08 


TIMER CONTROL/STAT REGISTER 


00064 




0009 


A TIMER 


EQU 


$09 


COUNTER REGISTER 


00065 




000B 


A OUTCMP 


EQU 


$0B 


OUTPUT COMPARE REGISTER 


00066 




0014 


A EPMCNT 


EQU 


$14 


RAM/EPROM CONTROL REGISTER 


00067 














00068 






* L 0 


C A L 


V A R 


I A B L E S 


00069 














00070A 


0080 






ORG 


$80 




00071A 


0080 


0002 


A 1MB EG 


RMB 


2 


START OF MEMORY BLOCK 


00072A 


0082 


0002 


A IMEND 


RMB 


2 


LAST BYTE OF MEMORY BLOCK 


00073A 


0084 


0002 


A PNTR 


RMB 


2 


FIRST BYTE OF EPROM TO BE PGM' 


00074A 


0086 


0002 


A WAIT 


RMB 


2 


COUNTER VALUE 


00075 














00076 






* E P 


ROM 


S T A 


RTS HERE 


00077 














00078A 


3000 






ORG 


$3000 




00079A 


3000 


DE 84 


A EPROM 


LDX 


PNTR 


SAVE CALLING ARGUMENT 


00080A 


3002 


3C 




PSHX 




RESTORE WHEN DONE 


00081A 


3003 


DE 80 


A 


LDX 


IMBEG 


USE STACK 


00082 














00083A 


3005 


3C 


EPR002 


PSHX 




SAVE POINTER ON STACK 


00084A 


3006 


86 FE 


A 


LDAA 


#$FE 


REMOVE VPP, SET LATCH 


00085A 


3008 


97 14 


A 


STAA 


EPMCNT 


PPC=1 , PLC=0 


00086A 


300A 


A6 00 


A 


LDAA 


X 


MOVE DATA MEMORY-TO-LATCH 


00087A 


300C 


DE 84 


A 


LDX 


PNTR 


GET WHERE TO PUT IT 


00088A 


300E 


A7 00 


A 


STAA 


X 


STASH AND LATCH 


00089A 


3010 


08 




INX 




NEXT ADDR 


00090A 


3011 


DF 84 


A 


STX 


PNTR 


ALL SET FOR NEXT 


0009 1A 


3013 


86 FC 


A 


LDAA 


#$FC 


ENABLE EPROM POWER (VPP) 


0009 2A 


3015 


97 14 


A 


STAA 


EPMCNT 


PPC=0, PLC=0 


00093 














00094 






* NOW 


WAIT FOR 50 MSEC TIMEOUT USING OUTPUT COMPARE. 


00095 














00096A 


3017 


DC 86 


A 


LDD 


WAIT 


GET CYCLE COUNTER 


00097A 


3019 


D3 09 


A 


ADDD 


TIMER 


BUMP CURRENT VALUE 


00098A 


30 IB 


7F 0008 


A 


CLR 


TCSR 


CLEAR OCF 


00099A 


301E 


DD OB 


A 


STD 


OUTCMP 


SET OUTPUT COMPARE 


00100A 


3020 


86 40 


A 


LDAA 


#$40 


NOW WAIT FOR OCF 


00101 














00102A 


3022 


95 08 


A EPR004 


BITA 


TCSR 




00103A 3024 


27 FC 3022 


BEQ 


EPR004 


NOT YET 


00104A 


3026 


38 




PULX 




SETUP FOR NEXT ONE 


00105A 


3027 


08 




INX 




NEXT 


00106A 


3028 


9C 82 


A 


CPX 


IMEND 


MAYBE DONE 


00107A 


302A 


23 D9 3005 


BLS 


EPR002 


NOT YET 


00108A 


30 2C 


86 FF 


A 


LDAA 


#$FF 


REMOVE VPP, INHIBIT LATCH 


00109A 


30 2E 


97 14 


A 


STAA 


EPMCNT 


EPROM CAN NOW BE READ 


00110A 


3030 


38 




PULX 




RESTORE PNTR 


00111A 


3031 


DF 84 


A 


STX 


PNTR 




00112A 


3033 


39 




RTS 




THAT'S ALL 


00113 








END 






TOTAL 


ERRORS 00000- 


-00000 









MOTOROLA MICROPROCESSOR DATA 
3-212 



MC68701 



ORDERING INFORMATION 

The following table provides generic information pertaining to the package type and temperature for the MC68701 . 
The MCU device is available only in the 40-pin dual-in-line (DIP) package in the Cerdip and Plastic packages. 



GENERIC INFORMATION 



Frequency 


Temperature 


Cerdip Package 


Ceramic Package 


(MHz) 


(Degrees C) 


(S Suffix) 


(L Suffix) 


1.0 


0 to 70 


MC68701S 


MC68701L 


1.0 


-40 to +85 


MC68701CS 


MC68701CL 


1.25 


Oto 70 


MC68701S-1 


MC68701L-1 


1.25 


-40 to +85 


MC68701CS-1 


MC68701CL-1 


2.0 


O to 70 


MC68B701S 


MC68B701L 



3 



PIN ASSIGNMENT 




21pV C C 
Standby 



MOTOROLA MICROPROCESSOR DATA 
3-213 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 



MC68701U4 



Advance Information 

8-Bit EPROM Microcontroller/Microprocessor 
(MCU/MPU) 

The MC68701U4 is an 8-bit single-chip EPROM microcontroller unit (MCU) which enhances the 
capabilities of the MC6801 and significantly enhances the capabilities of the M6800 Family of parts. 
It includes an MC6801 microprocessor unit (MPU) with direct object-code compatibility and upward 
object-code compatibility with the MC6800. Execution times of key instructions have been improved 
over the MC6800 and the new instructions found on the MC6801 are included. The MCU can func- 
tion as a monolithic microcontroller or can be expanded to a 64K byte address space. It is TTL 
compatible and requires one +5-volt power supply for nonprogramming operation. An additional 
Vpp power supply is needed for EPROM programming. On-chip resources include 4096 bytes of 
EPROM, 192 bytes of RAM, a serial communications interface (SCI), parallel I/O, and a 16-bit six- 
function programmable timer. 

• Enhanced MC6800 Instruction Set 

• Upward Source and Object Code Compatibility with the MC6800, MC6801, and MC6801U4 

• Bus Compatibility with the M6800 Family 

• 8x8 Multiply Instruction 

• Single-Chip or Expanded Operation of 64K Byte Address Space 

• Internal Clock Generator with Divide-by-Four Output 

• Serial Communications Interface (SCI) 

• 16-Bit Six-Function Programmable Timer 

• Three Output Compare Functions 

• Two Input Capture Functions 

• Counter Alternate Address 

• 4096 Bytes of Use EPROM 

• 1 92 Bytes of RAM 

• 32 Bytes of RAM Retainable During Power Down 

• 29 Parallel I/O and Two Handshake Control Lines 

• NMl Inhibited Until Stack Load 



This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-214 



BLOCK DIAGRAM 



O C01- X 
> > X LU 



r 



Expanded Multiplexed 
Expanded Non-Multiplexed 
Single Chip 



I I ll t II f 



MPU 



P37 


A7/D7 


D7 


I/O 




P36 


A6/D6 


D6 


I/O 




P35 


A5/D5 


D5 


I/O 




P34 


A4/D4 


D4 


I/O 




P33 


A3/D3 


D3 


I/O 




P32 


A2/D2 


D2 


I/O 




P31 


A1/D1 


D1 


I/O 




P30 


AO/ DO 


DO 


I/O 




SC2 


R/W 


R/W 


OS3 




SCI 


AS 


IOS 


IS3 





Port 
3 



P47 


A15 


A7 


I/O 


•*> 




P46 


A14 


A6 


I/O 






P45 


A13 


A5 


I/O 






P44 : 


A12 


A4 


I/O 




Port 


P43 


A11 


A3 


I/O 




4 


P42 


A10 


A2 


I/O 






P41 


A9 


A1 


I/O 


-*> 




P40 


A8 


AO 


I/O 







IRQ1 



XT 



Mode 
Select 
Logic 



Port 
2 



Address 



SCI 



0 



P21 
-*~ P22 

P23 
P24 



OS2 



Vcc Standby 



160x8 
RAM 



32x8 
Standby 
RAM 



3 



Port 
1 



-► P10 

P11 
P12 
P13 



P14 
P15 
P16 
P17 



4096 x 8 
EPROM 



TIN1 

TOUT1 

SCLK 

RDATA 

TDATA 



I/O 
I/O 
I/O 
I/O 
I/O 



TIN2 

TOUT2 

TOUT3 



I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 



5 
o 

en 
oo 
«j 
o 

C 




MC68701U4 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


v C c 


-0.3 to +7.0 


V 


Input Voltage 


Tin 


-0.3 to +7.0 


V 


Operating Temperature Range 


T A 


0 to 70 


°c 


Storage Temperature Range 
Programmed 
Unprogrammed 


T stg 


-40 to +85 
-55 to +150 


°c 


THERMAL CHARACTERISTICS 


Characteristic 


Symbol 


Value 


Rating 


Thermal Resistance Cerdip 


«JA 


65 


°C/W 



This device contains circuitry to protect the 
inputs against damage due to high static 
voltages or electric fields; however, it is ad- 
vised that normal precautions be taken to 
avoid applications of any voltage higher than 
maximum rated voltages to this high- 
impedance circuit. For proper operation it is 
recommended that Vj n and V ou t be con- 
strained to the range GNDs(Vj n or 

VoutlsVcc- 

Unused inputs must always be tied to an 
appropriate logic voltage level (e.g., either 
GND or V CC ). 




POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj=T A +(P D .e JA ) 



where: 

Ta 



p int 

p PORT 



= Ambient Temperature, °C 
= Package Thermal Resistance, 
Junction-to-Ambient, °C/W 
= P|NT +p PORT 

= lcc x ^CC' Watts — Chip Internal Power 

= Port Power Dissipation, Watts — User Determined 



For most applications PpORT <p INT and can be neglected. PpORT mav become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpoRT ' s neglected) is: 

Pd =k ^( t j +273 ° c > (2) 

Solving equations (1) and (2) for K gives: 

K = P D • (T A + 273°C) + ejA'PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pq (at 
equilibrium) for a known T A . Using this value of K, the values of Pq and Tj can be obtained by solving equations 
(1 ) and (2) iteratively for any value of T A 



CONTROL TIMING (V C c = 5.0 V ±5%, V SS = 0) 



Characteristic 


Symbol 


MC68701U4 


MC68701U4-1 


Unit 


Min 


Max 


Min 


Max 


Frequency of Operation 


fo 


0.5 


10 


0.5 


1.25 


MHz 


Crystal Frequency 


f XTAL 


2.0 


4.0 


2.0 


5.0 


MHz 


External Oscillator Frequency 


4'o 


2.0 


4.0 


2.0 


5.0 


MHz 


Crystal Oscillator Startup Time 


trc 




100 




100 


ms 


Processor Control Setup Time 


'PCS 


200 




170 




ns 



MOTOROLA MICROPROCESSOR DATA 
3-216 



MC68701U4 



DC ELECTRICAL CHARACTERISTICS (V C c = 5.0 Vdc ±5%, V s $ = 0) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Input High Voltage R ES ET 

Other Inputs* 


V|H 


Vss + 4.0 
VSS + 2.0 


- 


vcc 
vcc 


V 


Input Low Voltage RESET 

Other Inputs* 


V IL 


Vss-0.3 
Vss -0.3 




Vss + 0.4 
Vss + 08 


V 


Input Current Port4 
(V ln = 0to2.4V) See Note SC1 


'in 




- 


0.5 
0.8 


mA 


Input Current 

(V in = 0 to 5.25 V) NMi, iRQI 


l.n 


- 


- 


2.5 


ma 


Input Current RESET/Vpp 
(V in = 0to0.4 V) See Note 
(V in = 4.0Vto V C c) 


■in 


- 


-2.0 


8.0 


mA 


Hi-Z (Off State) Input Current 
(V ln = 0.5to2.4V) P10-P17, P20-P24, P30-P37 


•tsi 






10 


dA 


Output High Volt3Q6 
(l|oad= -65^A, V C c=min) P40-P47, SC1, SC2 
(l load = _ 100 |tA, Vcc = min) Other Outputs 


V 0 H 


VsS + 2.4 
V S S + 2.4 


- 


- 


V 


Output Low Voltage 
(l|oad = 20mA,-Vcc=min) All Outputs 


vol 


— 


— ' 


V ss + 0.5 


V 


Darlington Drive Current 

(V(-\— 1 RVI P1f> P17 


'OH 


1.0 


■ - 


4.0 


mA 


Internal Power Dissipation (measured at Ta = 0°C in Steady-State Operation) 


Pint 






1200 


mW 


Input Capacitance 

(V in = 0, T A = 25 °C. f 0 = 1 .0 MHz) P30-P37, P40-P47, SC1 

Other Inputs 


Cin 


_ 


_ 


12.5 
10.0 


pF 


Vcc Standby Power Down 

Power Up 


VSBB 
V S B 


4.0 
4.75 




5.25 
5.25 


V 


Standby Current Power Down 


ISBB 






3.0 


mA 


Programming Time (Per Byte) (T A = 25°C) 


tpp 


25 




50 


ms 


Programming Voltage (Ta = 25°C) 


V PP 


20.0 


21.0 


22.0 


V 


Programming Current (VreSET = v PP ) (Ta = 25°C) 


l PP 




3O.0 


50.0 


mA 



•Except Mode Programming Levels; See Figure 16. 



NOTE: RESET/Vpp, V| L , and lj n values differ from MC6801U4 values. 



PERIPHERAL PORT TIMING (Refer to Figures 1-4) 



Characteristics 


Symbol 


Min 


Typ 


Max 


Unit 


Peripheral Data Setup Time 


tPDSU 


200 






ns 


Peripheral Data Hold Time 


tPDH 


200 






ns 


Delay Time, Enable Positive Transition to OS3 Negative Transition 


'OSD1 






350 


ns 


Delay Time, Enable Positive Transition to OS3 Positive Transition 


tOSD2 






350 


ns. 


Delay Time, Enable Negative Transition to Peripheral Data Valid 


tPWD 






350 


ns 


Delay Time, Enable Negative Tiansition to Peripheral CMOS Data Valid 


tCMOS 






2.0 


us 


Input Strobe Pulse Width 


<PWIS 


200 






ns 


Input Data Hold Time 


t|H 


50 






ns 


Input Data Setup Time 


'IS 


20 






ns 



MOTOROLA MICROPROCESSOR DATA 
3-217 



MC68701U4 



FIGURE 1 - DATA SETUP AND HOLD TIMES 
(MPU READ) 



FIGURE 2 - DATA SETUP AND HOLD TIMES 
(MPU WRITE) 



MPU Read 



P10-PT7 
P20-P24 
P40-P47 
Inputs 



P30 P37 
Inputs* 



r 



)j . Da,avaiid X 



''PDH 



'PDSU- 



^DataVaUd j( 



•'PDH 



' Port 3 non-latched operation ( Latch enable = 0) 



All Data 
Port Outputs 



I"! 



-'CMOS 
•IPWD-J 



•0.7 V C C 



Data Valid 



NOTES 

1 10 k pullup resistor required for port 2 to reach 07 V qq 

2 Not applicable to P21 

3 Port 4 cannot be pulled above Vqq 



FIGURE 3 - PORT 3 OUTPUT STROBE TIMING 
(SINGLE-CHIP MODE) 

• MPU Access of Port 3* 



Address 
Bus 



0S3 
(SC2) 



r 



($0006) 



X 



'OSD1- 



X 



'0SD2- 



\ r 



FIGURE 4 - PORT 3 LATCH TIMING 
(SINGLE-CHIP MODE) 



1S3 
(SC1) 



P30-P37 

Inputs 



■t|S-» 



— tpwis- 

-tlH- 



~ X Da,avahd X 



♦Access matches output strobe select (OSS = 0, a read; 0SS= 1, a write) 

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. 



FIGURE 5 - CMOS LOAD 



Test Point 



^30 pF 



FIGURE 6 - TIMING TEST 
LOAD PORTS 1, 2, 3, AND 4 



VCC 



R(_= 1.8 kfi 




% MMD7000 
or Equiv 



C = 90 pF for P30-P37, P40-P47, E, SC1, SC2 

= 30 pF for P10-P17, P20-P24 
R = 37 ktl for P40-P47, SC1, SC2 

= 24 kl) for P10-P17, P20-P24, P30-P37, E 



MOTOROLA MICROPROCESSOR DATA 
3-218 



MC68701U4 



BUS TIMING (See Notes 1 and 2, and Figure 7) 



Ident. 
Number 


Characteristics 


Symbol 


MC68701U4 


MC68701U4-1 


Unit 


JVlin 


Max 


Min 


Max 


1 


Cycle Time 


: icyc 


1.0 


2.0 


0.8 , 


2.0 


/*s 


2 


Pulse Width, E Low 


PWgL 


430 


1000 


360 


1000 


ns 


3 


Pulse Width, E High 


PW EH 


450 


1000 


360 


1000 


ns 


4 


Clock Rise and Fall Time 


t r , tf 




25 




25 


ns 


9 


Address Hold Time 


tAH 


20 




20 




ns 


12 


Non-Muxed Address Valid Time to E* 


,*AV 


200 




150 




ns 


17 . 


Read Data Setup Time 


'DSR 


80 




70 




ns 


18 


Read Data Hold Time 


'DHR 


10 




10 




ns 


19 


Write Data Delay' Time 


( DDW 




" 225 




200 


ns 


21 


Write Data Hold Time 


l DHW 


20 




20 




ns 


22 


Muxed Address Valid Time to E Rise* 


'AVM 


160 




120 




.ns 


24 


Muxed Address Valid Time to AS Fall* 


l ASL 


40 




30 




ns 


25 


Muxed Address Hold Time 


*AHL 


20 




20 




•ns 


26 


Delay Time, E to AS Rise* 


'ASD 


200 




170 




ns 


27 


Pulse Width, AS High* 


pwash 


100 




80 




ns 


28 


Delay Time, AS to E Rise* 


'ASED 


90 




70 




ns 


29 


Usable Access Time* (See Note 3) 


tACC 


530 




410 




ns 



* At specified cycle time. 



FIGURE 7 - BUS TIMING 



^4 



IOS, 



R/W, Address 
(Non-Muxed) - 



Addr/Data 
Muxed 



Addr/Data 
Muxed 



Address 
Strobe (AS) 



See Note 5 



< — (§> 

1C3 



©J 



D EI3 



See Note 4 



-©• 



29} 



See Note 3 



Read Data Muxed 



Write Data Muxed 



NOTES: 

1., Voltage levels shown are Vl<0.5 V, Vh^2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified 

3. Usable access time is computed by 22 + 3- 17. 

4. Memory devices should be enabled only during E high to avoid port 3 bus contention. 

5. Item 26 is different from the MC6801, but it is upward compatible. 



MOTOROLA MICROPROCESSOR DATA 
3-219 



MC68701U4 



INTRODUCTION 

The MC68701 U4 is an 8-bit monolithic microcontroller 
which an be configured to function in a wide variety of 
applications. The facility which provides this extraor- 
dinary flexibility is its ability to be hardware pro- 
grammed into seven different operating modes. The 
operating mode controls the configuration of 18 of the 
40 MCU pins, available on-chip resources, memory map, 
location (internal or external) of interrupt vectors, and 
type of external bus. The configuration of the remaining 
22 pins is not dependent on the operating mode. 

Twenty-nine pins are organized as three 8-bit ports 
and one 5-bit port. Each port consists of at least a data 
register and a write-only data direction register. The 
data direction register is used to define whether cor- 
responding bits in the data register are configured as 
an input (clear) or output (set). 



The term "port" by itself refers to all of the hardware 
associated with the port. When the port is used as a 
"data port" or "I/O port," it is controlled by the port 
data direction register and the programmer has direct 
access to the port pins using the port data register. Port 
pins are labeled as Pij where i identifies one of four 
ports and j indicates the particular bit. 

The microprocessor unit (MPU) is an enhanced 
MC6800 MPU with additional capabilities and greater 
throughput. It is upward source and object code com- 
patible with the MC6800 and the MC6801 . The program- 
ming model is depicted in Figure 8 where accumulator 
D is a concatenation of accumulators A and B. A list of 
new operations added to the MC6800 instruction set are 
shown in Table 1. 

The basic difference between the MC6801U4 and the 
MC68701U4 is that the MC6801U4 has an on-chip ROM 
while the MC68701U4 has an on-chip EPROM. The 




FIGURE 8 - PROGRAMMING MODEL 



7 


A 0|J7 B 


0 


15 


D 


0 




15 


X 


0 




15 


SP 


0 




5 


PC 


0 



8- Bit Accumulators A and B 
Or 1 6- Bit Double Accumulator D 



0 Index Register IX) 



0 Stack Pointer (SP) 



0 Program Counter (PC) 



1 1 


h| I N 


Z 


V C 




i t 


* J 


; 


ti: 













Condition Code Register (OCR) 

Carry/Borrow from MSB 

Overflow 

Zero 

Negative 
Interrupt 

Half Carry (From Bit 3) 



TABLE 1 - NEW INSTRUCTIONS 



Instruction 



Description 



ABX 
ADDD 
ASLD or LSLD 
BHS 
BLO 
BRN 
JSR 
LDD 
LSL 

LSRD 

MUL 
PSHX 
PULX 

STD 
SUBD 

CPX 



Unsigned addition of accumulator B to index register 

Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator 

Shifts the double accumulator left (towards MSB) one bit, the LSB is cleared, and the MSB is shifted into the C bit 

Branch if higher or same, unsigned conditional branch (same as BCC) 

Branch if lower, unsigned conditional branch (same as BCS) 

Branch never 

Additional addressing mode direct 
Loads double accumulator from memory 

Shifts memory or accumulator left (towards MSB) one bit, the LSB is cleared, and the MSB is shifted into the C bit 
(same as ASL) 

Shifts the double accumulator right (towards LSB) one bit, the MSB is cleared, and the LSB is shifted into the C bit 
Unsigned multiply, multiplies the two accumulators and leaves the product in the double accumulator 
Pushes the index register to stack 
Pulls the index register from stack 
Stores the double accumulator to memory 

Subtracts memory from the double accumulator and leaves the difference in the double accumulator 
Internal processing modified to permit its use with any conditional branch instruction 



MOTOROLA MICROPROCESSOR DATA 
3-220 



MC68701U4 



MC68701U4 is pin and code compatible with the MC6801U4 
and can be used to emulate the MC6801U4, allowing easy 
software development using the on-chip EPROM. Software 
developed using the MC68701U4 can then be masked into 
the MC6801U4 ROM. 

In order to support the on-chip EPROM, the MC68701U4 
differs from the MC6801U4 as follows: 

(1) ModeO in the MC6801U4 is a test mode only, while in 
the MC68701U4 mode 0 is also used to program the 
on-chip EPROM. 

(2) The MC68701U4 RAM/EPROM control register has 
two bits used to control the EPROM in mode 0 that are 
not defined in the MC6801U4 RAM control register. : 

(3) The RESET/Vpp pin in the MC68701U4 is dual pur- 
pose, used to supply EPROM power as well as to reset 
the dev ice; while in the MC6801U4 the pin is called 
RESET and is used only to reset the device. 



OPERATING MODES 

The MC68701U4 provides seven different operating modes 
(modes 0 through 3 and 5 through 7). The operating modes 



are hardware selectable and determine the device memory 
map, the configuration of port 3, port 4, SC1, SC2, and the 
physical location of the interrupt vectors. 

FUNDAMENTAL MODES 

The seven operating modes (0-3, 5-7) can be grouped into 
three fundamental modes which refer to the type' of bus it 
supports: single chip, expanded non-multiplexed, and ex- 
panded multiplexed. Single chip is mode 7, expanded non- 
multiplexed is mode 5, and the remaining 5 are expanded 
multiplexed modes. Table 2 summarizes the characteristics 
of the operating modes. 

SINGLE-CHIP MODE (7) - In the single-chip mode, 
the four MCU ports are configured as parallel input/ 
output data ports, as shown in Figure 9. The MCU func- 
tions as a monolithic microcontroller in this mode with- 
out external address or data buses. A maximum of 29 
I/O lines and two port 3 control lines are provided. Pe- 
ripherals or another MCU can be interfaced to port 3 in 
a loosely coupled dual-processor configuration, as 
shown in Figure 10. 



TABLE 2 - SUMMARY OF OPERATING MODES 




Single-Chip (Mode 7) 



192 bytes of RAM, 4096 bytes of EPROM 

Port 3 is a parallel I/O port with two control lines 

Port 4 is a parallel I/O port 



Expanded Non-Multiplexed (Mode 5) 



192 bytes of RAM, 4096 bytes of EPROM 
256 bytes of external memory space 
Port 3 is an 8-bit data bus; ... , 
Port 4 is. an input port/address bus 



Expanded Multiplexed (Modes 0, 1,2, 3, 6) 



Four memory space options (total 64K address space) 

(1) Internal RAM and EPROM with partial address bus (mode 1) 

(2) Internal RAM, no EPROM (mode 2) 

(3) Extended addressing of internal I/O and RAM 

(4) Internal RAM and EPROM with partial address bus (mode 6) 
Port 3 is multiplexed address/ data bus 

Port 4 is address bus (inputs/ address in mode 6) 
Test/Program mode (mode 0): 

May be used to test internal RAM and EPROM 

May be used to test ports 3 and 4 as I/O ports by writing into mode 7 

Used to program EPROM , 
Only modes 5, 6, and 7 can be irreversibly entered from mode 0 



Resources Common to All Modes 



Reserved register area 
Port 1 input/ output operation 
Port 2 input/ output operation 
Timer operation 

Serial communications interface operation 



MOTOROLA MICROPROCESSOR DATA 
3-221 



MC68701U4 



FIGURE 9 - SINGLE-CHIP MODE 

VCC 



Vgc Standby^- 

rtstt- 



Port 1 
8 I/O Lines 
16- Bit Timer 



Port 4 
8. Lines 



XTAL 
EXTAL 

MC68701U4 



a 



vss 



-iRQi 



Port 3 
8 I/O Lines 



IS3 



Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 



FIGURE 10 - SINGLE-CHIP DUAL PROCESSOR CONFIGURATION 

VCC v cc 



VCC Standby ► 

RESET *- 



Port 1 . 
8 I/O 
Lines 
16-Bit Timer 

Port 2 
5 I 0 Lines 

SCI 
16-Bit Timer 



XTAL 
EXTAL 

MC68701U4 



OS3 
IS3 



vss 



NMI | | 

IRQI -r 



VccStandby- 
RESET- 

iPort 3. 8 I/O Lines, 



XTAL 
EXTAL 



MC68701U4 



IS3 
OS3 



Port 4 
8 1/0 
Lines 



Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 



vss 



E 

NMI 
IRQ1 



Port 1 
8 I/O 
Lines 
16-Bit Timer 



Port 4 
8 I/O 
Lines 



EXPANDED NON-MULTIPLEXED MODE (5) - A modest 
amount of external memory space is provided in the expand- 
ed non-multiplexed mode while significant on-chip resources 
are retained. Port 3 functions as an 8-bit bidirectional data 
bus and port 4 is configured initially as an input data port. 
Any combination of the eight least significant address lines 
may be obtained by writing to the port 4 data direction 
register. Stated alternatively, any combination of AO to A7 
may be provided while retaining the remainder as input data 
lines. Internal pullup resistors pull the port 4 lines high until 
the port is configured. 

Figure 1 1 illustrates a typical system configuration in the 
expanded non-multiplexed mode. The MCU interfaces 
directly with M6800 Family parts and can access 256 bytes of 
external address space at $100 through $1FF. IOS provides 
an address decode of external memory ($100-$1FF) and can 
be used as a memory-page select or chip-select line. 



EXPANDED MULTIPLEXED MODES (0, 1, 2, 3, 6) - A 

64K byte memory space is provided in the expanded 
multiplexed modes. In each of the expanded multiplexed 
modes, port 3 functions as a time multiplexed address/ data 
bus with address valid on the negative edge of address 
strobe (AS) and data valid while E is high. In modesO, 2, and 
3, port 4 provides address lines A8 to A15. In modes 1 and 6, 
however, port 4 initially is configured at reset as an input 
data port: . The port 4 data direction register can then be 
changed to provide any combination of address lines A8 to 
A15. Stated alternatively, any subset of A8 to A15 can be 
provided while retaining the remaining port 4 lines as input 
data lines. Internal pullup resistors pull the port 4 lines high 
until software configures the port. 

In mode 0, the reset and interrupt vectors are located at 
$BFF0-$BFFF. In addition, the internal and external data 



MOTOROLA MICROPROCESSOR DATA 
3-222 



MC68701U4 



buses are connected, so there must be no memory map 
overlap in order to avoid potential bus conflicts. By writing 
the PC0-PC2 bits in the port 2 data register, modes 5, 6, and 
7 can be irreversibly entered from mode 0. Mode 0 is used to 
program the on-chip EPROM. 



Figure 12 depicts a typical configuration for the expanded 
multiplexed modes. Address strobe can be used to control a 
transparent D-type latch to capture addresses A0-A7, as 
shown in Figure 13. This allows port 3 to function as a data 
bus when E is high. 



FIGURE 11 - EXPANDED NON-MULTIPLEXED CONFIGURATION 

VCC 



CD 

Vcc Standby — 
RESET 



Port 1 
8 I/O Lines 
16-Bit Timer 

Port 2 
5 I/O 
Lines 
SCI 
i&Bit Timer 



XTAL 

EXTAL 

MC68701U4 



•NMI 
IRQ1 



Port 3 
'8 Data Lines 
>• R/W 



*- IOS 

Port 4 
To 8 
Address Lines 




VSS 



vcc 



□ 



Vcc Standby > 

RESET *■ 

NMI > 



IRQ1 ' 



Port 1 
8 I/O . 
16-Bit Timer 
Port 2 
5 I/O 
SCI 
Timer 



XTAL 

EXTAL 

MC68701U4 



Port4 ,o 



R W 



VSS 



-►(D0-D7) 
(A0-A7) 



R/W 
E 



MOTOROLA MICROPROCESSOR DATA 
3-223 



MC68701U4 



FIGURE 12 - EXPANDED MULTIPLEXED CONFIGURATION 

*" E 



Vqc Standby 



RESET - 



XTAL 
EXTAL 

MC68701U4 



Port 1 
8 I/O Lines 
16-Bit Timer 

Port 2 
5 I/O Lines 

SCI 
16-Bit Timer 

v C c 



vss 



- NMI 
-TROT 

Port 3 
8 Lines 

.^.p^ Multiplexed Data Address 



-*>AS 



Port 4 
8 Lines 
Address Bus 



a 



VqC Standby. 
RESET- 
NMI - 
IRQ1- 



Port 1 
8 I/O 
16-Bit Timer 
Port 2 
5 I/O 
SCI 
Timer 



XTAL 

EXTAL 

MC68701U4 



Port 3 8 
AS 



i\ai 16 



7^ 



R/W 



Data Bus 
- (D0-D7) 

Address Bus 



(A0-A15) 
-*-R/W 



->-E 



v S s 














ROM 




RAM 




PIA 



NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory devices should be enabled only during E high time. 

FIGURE 13 - TYPICAL LATCH ARRANGEMENT 



GND >- 
AS >- 



Port 3 
Address/ Data 



G OC 
D1 Q1 



SN74LS373 
(Typical) 



D8 



> Address A0-A7 



MOTOROLA MICROPROCESSOR DATA 
3-224 



MC68701U4 



PROGRAMMING THE MODE 

The operating mode is determined at RESET by the 
levels asserted on P22, P21, and P20. These levels are 
latched into PC2, PC1, and PCO of the p rogram control 
register on the positive edge of RESET. The operating 
mode may be read from the port 2 data register, as 
shown below, and programming levels and timing must 
be met a shown in Figure 14. A brief outline of the 
operating modes is shown in Table 3. 

PORT 2 DATA REGISTER 

7 6 5 4 3 2 1 0 
|PC2 I PC1 I PCO J P24 | P23 | P22 I P21 | P20| $03 



Circuitry to provide the programming levels is de- 
pendent primarily on the normal system usage of the 
three pins. If configured as outputs, the circuit shown 
in Figure 15 may be used; otherwise, three-state buffers 
can be used to provide isolation while programming 
the mode. Note that if diodes are used to program the 
mode, the diode forward voltage drop must not exceed 
the Vmpdd minimum. 

MEMORY MAPS 

The MC68701U4 can provide up to 64K byte address 
space depending on the operating mode. A memory 
map for each operating mode is shown in Figure 16. 
The first 32 locations of each map are reserved for the 
internal register area, as shown in Table 4, with excep- 
tions as indicated. 



RESET 



FIGURE 14 - MODE PROGRAMMING TIMING 



PWrsTL— 
-tMPS" 



Mode Inputs . 
(P20, P21. P22) 



VMPH 



VMPL 



See Figure 15 
for Diode Arrangement 



VMPDD 



<MPH 



Data Valid ^ 



V MPH Mm 



V M PL Max 




MODE PROGRAMMING (Refer to Figure 14) 



Characteristic 


Symbol 


Min 


Max 


Unit 


Mode Programming Input Voltage Low (for Ta = 0 to 70°C) 


V MPL 




1.8 


V 


Mode Programming Input Voltage High 


V MPH 


4.0 




V 


Mode Programming Diode Differential (If Diodes are Used) (for Ta = 0 to 70°C) 


V MPDD 


0.6 




V 


RESET Low Pulse Width 


pw rstl 


3.0 




E Cycles 


Mode Programming Setup Time 


»MPS 


2.0 




E Cycles 


Mode Programming Hold Time 
RESET Rise Time>1 /is 
RESET Rise Time< 1 /is 


tMPH 


0 

100 




ns 



NOTE: For T/\= -40 to 85°C, Maximum V|yjp|_ = 1.7, and Minimum Vmpdd = 0.4. 

TABLE 3 - MODE SELECTION SUMMARY 





P22 


P21 


P20 






Interrupt 


Bus 




Mode 


PC2 


PC1 


PCO 


EPROM 


RAM 


Vectors 


Mode 


Operating Mode 


7 


H 


H 


H 


I 


I 


I 


I 


Single Chip 


6 


H 


H 


L 


I 


I 


I 


MUX<2,3) 


Multiplexed/Partial Decode 


5 


H 


L 


H 


I 


I 


I 


NMUX' 2 ' 31 


Non-Multiplexed/ Partial Decode 


4 


H 


L 


L 










Undefined' 4 ' 


3 


L 


H 


H 


E 


I 


E 


MUX' 1-5) 


Multiplexed/RAM 


2 


L 


H 


L 


E 


I 


E 


MUX (1 > 


Multiplexed/RAM 


1 


L 


L 


H 


I 


I 


E 


MUX<2.3) 


Multiplexed/ RAM and EPROM 


0 


L 


L 


L 


I 


I 


E 


MUX' 1 ' 


Multiplex ed Test/ Programming 



LEGEND 
I - Internal 
E - External 
MUX - Multiplexed 



NMUX - N on -Multiplexed 
L - Logic "0" 
H - Logic "1" 



NOTES: 

1. Addresses associated with ports 3 and 4 are considered external in modes 0, 2, and 3. 

2. Addresses associated with port 3 are considered external in modes 1, 5, and 6. 

3. Port 4 default is user data input; address output is optional by writing to port 4 data direction register. 

4. Mode 4 is a non-user mode and should not be used as an operating mode. 

5. Mode 3 has the internal RAM and internal registers relocated at $D0O0-$D0FF. 



MOTOROLA MICROPROCESSOR DATA 

3-225 



MC68701U4 



FIGURE 15 - TYPICAL MODE PROGRAMMING CIRCUIT 




P21 
P22- 



< 






8 




1 — 


I — 


9 




— < 




. 1° 






— 1 


V 




P20 (PCO) 
P21 (PCD 
P22 (PC2) 



MC68701U4 



NOTES: 

1. Mode 0 as shown (switches closed). 

2. R1 = 10 kilo hms (typical). 

3. The RESET time constant is equal to RC where R 
is the equivalent parallel resistance of R2 and the 
number of resistors (R1) placed in the circuit by 
closed mode contol switches. 

4. D = 1N914, 1N4001 inthe0to70°C range 

D = 1N270, MBD201 in the -40 to 85°C range 

5. If V = V m, the R2 = 50 ohms (typical) to meet V|h 
for the RESET/Vpp pi n. V = Vr r is also compatible 
with MC6801U4. The RESET time constant in this 
case is approximately R2xC. 

6. Switch S1 allows selection of normal (RESET ) or 
programming (Vpp) as the input to the RESET/Vpp 
pin. During switching, the input level is held at a 
value determined by a diode (D), resistor (R2) and 
input voltage (V). 

7. While S1 in the "Program" position, RESET should 
not be asserted. 

8. From powerup, RESET must be held low for at 
least tRfj. The capacitor, C, is shown for concep- 
tual purposes only and is on the order of 1000 |xF 
for the circuit shown. Typical ly, a bu ffer with an 
RC input will be used to drive RESET, eliminating 
the need for the larger capacitor. 

9. Diode Vf should not exceed Vmpoq min. 



FIGURE 16 - MEMORY MAPS (Sheet 1 of 3) 



Multiplexed Test/Program Mode 
$0000< 1 > 



$001 F 



$0040 



$00FF 



$BFF0 
$BFFF 



$F000 



$FFFF 





Internal 
Registers 
External 
Memory Space 

Internal 
RAM 



External 
Memory Space 

External 

Interrupt Vectors'2) 
External 
Memory Space 
Internal 
EPROM 



MC68701U4 
Mode 



0 



NOTES: 

1 ) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07, and $0F. 

2) The interrupt vectors are at $BFF0-$BFFF. 

3) There must be no overlapping of internal and 
external memory spaces to avoid driving the, 
data bus with more than one device. 



4) This mode is used to program the on-chip 
EPROM. 

5) Modes 5-7 can be irreversibly entered from 
mode 0 by writing to the PC0-PC2 bits of the 
port 2 data register. 



MOTOROLA MICROPROCESSOR DATA 
3-226 



FIGURE 16 - MEMORY MAPS (Sheet 2 of 3) 




Multiplexed/ RAM and EPROM 



$0000(1) 
$001 F 

$0040 

$00FF 




$F000 

$FFEF 
$FFF0 
$FFFF 



Internal 

Registers 

External 

Memory Space 

Internal 

RAM 



External 
Memory Space 



Internal 
EPROM 

External 

Interrupt Vectors 



NOTES: 

1) Excludes the following addresses which may be 
used externally: $04, $06, and $0F. 

2) Internal EPROM addresses $FFF0 to $FFFF are not 
usable. 

3) Address lines A8-A15 will not contain addresses 
until the data direction register for port 4 has been 
written with "1s" in the appropriate bits. These 
address lines will assert "1s" until made outputs 
by writing the data direction register. 



MC68701U4 
Mode 



Multiplexed/ RAM 
SOOOOd) 

$001 F 

$0040 

$00FF 




$FFF0 
$FFFF 




External 
Memory Space 



External 

Interrupt Vectors 



NOTE: 

1) Excludes the following addresses which may be 
used externally: $04, $05, $06, $07, and $0F. 




Multipl exed/ RAM 
$0000(1) 




External 
Memory Space 



Internal 
Registers' 1. 2 ) 
External 
Memory Space 
Internal 
RAM'D 

External 
Memory Space 

External 

nterrupt Vectors 
NOTES: 

1 ) Relocating the internal registers and the inter- 
nal RAM to high memory allows the processor 
to make use of direct addressing. 

2) Excludes the following addresses which may be 
used externally: $0004, $D005, $D006, $D007, 
and $D00F. 



CO 



CO 



FIGURE 16 - MEMORY MAPS (Sheet 3 of 3) 



MC68701U4 
Mode 



Non-Multiplexed/Partial Decode 



External 
Memory Space 




$FFFF 



Internal 

Interrupt Vectors 



NOTES: 

1) Excludes the following addresses which may 
not be used externally: $04, $06, and $0F (no 

ioS). 

2) Address lines AO to A7 will not contain ad- 
dresses until the data direction register for port 
4 has been written with "1s" in the appropriate 
bits. These address lines will assert "1s" until 
made outputs by writing the data direction 
register. 




Multiplexed/Partial Decode 




$00FF 



SF000 



$FFFF 




Internal 

Registers 

External 

Memory Space 

Internal 

RAM 



External 
Memory Space 



Internal 
EPROM 
Internal 

Interrupt Vectors 



NOTES: 

1 ) Excludes the following addresses which may be 
used externally: $04, $06, $0F. 

2) Address lines A8-A15 will not contain ad- 
dresses until the data direction register for port 
4 has been written with "1s" in the appropriate 
bits. These address lines will assert "Is" until 
made outputs by writing the data direction 
register. 



MC68701U4 
Mode 



Single Chip 



$0000 
$001 F 




Internal 
RAM 



$F000 



$FFFF 



Unusable 



O 
o> 

00 

-J 
o 

C 




Internal 
EPROM 
Internal 
' Interrupt Vectors 



MC68701U4 



TABLE 4 - INTERNAL REGISTER AREA 



Register 


Address 


Port 1 Data Direction Register* * * 


00 


Port 2 Data Direction Register* * * 


01 


Port 1 Data Register 


02 


Port 2 Data Register 


03 


Port 3 Data Direction Register* * * 


04* 


Port 4 Data Direction Register* * * 


05** 


Port 3 Data Register 


06* 


Port 4 Data Register 


07** 


Timer Control and Status Register 


08 


Counter (High Byte) 


09 


Counter (Low Byte) 


OA 


Output Compare Register (High Byte) 


0B 


Output Compare Register (Low Byte) 


OC 


Input Capture Register (High Byte) 


0D 


Input Capture Register (Low Byte) 


0E 


Port 3 Control and Status Register 


OF* 


Rate and Mode Control Register 


10 


Transmit/ Receive Control and Status Register 


11 


Receive Data Register 


12 


Transmit Data Register 


13 


RAM Control Register 


14 


Counter Alternate Address (High Byte) 


15 


Counter Alternate Address (Low Byte) 


16 


Timer Control Register 1 


17 


Timer Control Register 2 


18 


Timer Status Register 


19 


Output Compare Register 2 (High Byte) 


1A 


Output Compare Register 2 (Low Byte) 


IB 


Output Compare Register 3 (High Byte) 


1C 


Output Compare Register 3 (Low Byte) 


1D 


Input Capture Register 2 (High Byte) 


1E 


Input Capture Register 2 (Low Byte) 


1F 



•External addresses in modes 0, 1,2, 3, 5, and 6; cannot be 
accessed in mode 5 (no IOS) 
** External addresses in modes 0, 2, and 3 
***1 = Output, 0= Input 



MC68701U4 INTERRUPTS 

The M6801 Family supports two types of interrupt re- 
quest s: m askable and non-maskable. A non-maskable inter- 
rupt (NMD is always recognized and acted upon at the com- 
pletion of the current instruction. Maskable interrupts are 
controlled by the condition code register I bit and by in- 
dividual enable bits. The I bit controls all maskable inter- 
rupt s. Of the maskable interrupts, there are two types: IRQ1 
and IRQ2. The programmable time r and serial communica- 
tions interface use an internal IRQ2 interrupt line, as sh own 
m th e block diagram. External de vices and IS3 use IRQ1. An 
IRQ1 interrupt is serviced before IRQ2 if both are pending. 



NOTE 

After reset, an NMI will not be servic ed un til the first 
program load of the stack pointer. Any NMI generated 
before this load will be remembered by the processor 
and serviced subsequent to the stack pointer load. 



All IRQ2 interrupts use hardware prioritized vectors. The 
single SCI interrupt and three timer interrupts are serviced in 
a prioritized order and each is vectored to a separate loca- 
tion. All interrupt vector locations are shown in Table 5. In 
mode 0, reset and interrupt vectors are defined as $BFF0- 
$BFFF. 

The interrupt flowchart is depicted in Figure 17 and is 
common to every interrupt excluding reset. During interrupt 
servicing, the program counter, index register, A ac- 
cumulator, B accumulator, and condition code register are 
pushed to the stack. The I bit is set to inhibit maskable inter- 
rupts and a vector is fetched corresponding to the current 
highest priority interrupt The vector is transferred to the 
program counter and instruction execution is resumed. Inter- 
rupt and RESET timing are illustrated in Figures 18 and 19. 




TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS 



ModeO 


Modes 1-3, 5-7 


Interrupt 


MSB 


LSB 


MSB 


LSB 


BFFE 


BFFF 


FFFE 


FFFF 


RESET 


BFFC 


BFFD 


FFFC 


FFFD 


Non-Maskable Interrupt* * 


BFFA 


BFFB 


FFFA 


FFFB 


Software Interrupt 


BFF8 


BFF9 


FFF8 


FFF9 


Maskable Interrupt Request 1 


BFF6 


BFF7 


FFF6 


FFF7 


Input Capture Flag* 


BFF4 


BFF5 


FFF4 


FFF5 


Output Compare Flag* 


BFF2 


BFF3 


FFF2 


FFF3 


Timer Overflow Flag* 


BFF0 


BFF1 


FFF0 


FFF1 


Serial Communications Interface* 



* FRQ2 interrupt 

'NMI must be armed (by accessing stack pointer) before an 
NMI is executed 



MOTOROLA MICROPROCESSOR DATA 
3-229 




FIGURE 17 - INTERRUPT FLOWCHART 




SCI = TIE«TDRE + RIE»(RDRF + ORFE) 
ICI = (ICF1«EICI1) + (ICF>EICI2) 
OCI = IOCF1»EOCI1) + (OCF2»EOCI2) + IOCF3«EOCI3l 



Vecux— PC 




Moda 0 


ModM 1-3. 5-7 






BFFC-BFFD 


FFFC-FFFD 


Non-Maskable Interrupt 


SWI 


BFFA-BFFB 


FFFA FFFB 


Software Interrupt 


rEOT 


BFF8-BFF9 


FFFB-FFF9 


Maskable Interrupt Request 1 


ICF 


BFF6-BFF7 


FFF6-FFF7 


Input Capture Interrupt 


OCF 


BFF4-BFF5 


FFF4-FFF5 


Output Compare Interrupt 


TOF 


BFF2-BFF3 


FFF2-FFF3 


Timer Overflow Interrupt 


SCI 


BFFO-BFF1 


FFF0-FFF1 


SCI Interrupt 



5 

o 
cr> 
oo 



G 



FIGURE 18 - INTERRUPT SEQUENCE 



Last Instruction • 



'Cycle 
#1 



#3 



#4 



#5 



#6 



#7 



#8 



#9 



#11 



#12 



Interal 
Address Bus 



IRQ1 



NMI or IRQ2 



H- tpcs 

^ 



i Bit Set 



IX X X X X X X X ^ X X~ X V 



OpCode OpCode SP(n) SP(n-1) SP(n-2) SPIn-3) SP(n-4) SP<n-5) SP(n-6) SP(n-7) Vector Vector New PC 
Addr Addr MSB Addr LSB Addr Address 



•tpcs 



Internal — w y — j y y — y y — y— y y Y Y Y y y y y 

Data Bus _A A A A A A A A A A A A_ . -A_ — . — A_ — , — A_ A— 



Internal R/W 



OpCode OpCode PC 0-7 PC 8-15 XO-7 X8-15 ACCA ACCB CCR Irrelevant Vector Vector First Inst, of 
Data MSB LSB Interrupt Routine 

\ . . / 



FIGURE 19 - RESET TIMING 



5.25 V 

vcc -/f 7 ™ 

h — 

RESET 



ltltl rLnLru~LrLn rLrurur 



-I h 



•tRC- 



W h 



H h 



0.8 V 



•tpcs 



4.0 V 



0.8V-C 



•tpcs 



Internal 
Address Bus 



Internal R/W 0 



wwwv^ fcssssmsssmssssmx — v.t~x — x — y — * — *. — v* ^ — v — y~~ 

FFFE FFFE FFFE FFFE FFFF New PC FFFE FFFE 



Internal 
Data Bus ^ 



KWX^XI Not Valid 



PC 8-15 PC 0-7 First 

Instruction 



2 
O 
O) 
CO 
•si 
O 

C 




MC68701U4 



FUNCTIONAL PIN DESCRIPTIONS 
Vcc AND Vss 

Vqc and VSS provide power to a large portion of the 
MCU. The power supply should provide + 5 volts ( ± 5%) to 
Vcc ancl V SS should be tied to ground. Total power dissipa- 
tion (including Vcc standby) will not exceed Pq milliwatts. 

Vcc STANDBY 

Vcc standby provides power to the standby portion ($40 
through $5F) of the RAM and the STBY PWR and RAME 
bits of the RAM control register. Voltage requirements de- 
pend on whether the device is in a power-up or power-down 
state. In the power-up state, the power supply should pro- 
vide + 5 volts (±5%) and must reach Vsb volts before 
RESET reaches 4.0 volts. During power down, Vcc standby 
must remain above VgBB (minimum) to sustain the standby 
RAM and STBY PWR bit. While in power-down operation, 
the standby current will not exceed ISBB- 

It is typical to power both Vcc and Vcc standby from the 
same source during normal operation. A diode must be used 
between them to prevent supplying power to Vcc during 
power-down operation. 

XTAL AND EXTAL 

These two input pins interface either a crystal or TTL- 
compatible clock to the MCU internal clock generator. 
Divide- by- four circuitry is included which allows use of the 
inexpensive 3.58 MHz or4.4336 MHz color burst TV crystals. 
A 20 pF capacitor should be tied from each crystal pin to 
ground to ensure reliable startup and operation. Alternative- 
ly, EXTAL may be driven by an external TTL-compatible 
clock at 4 f 0 with a duty cycle of 50% (±5%) with XTAL 
connected ground. 

The internal oscillator is designed to interface with an AT- 
cut quartz crystal resonator operated in parallel resonance 
mode in the frequency range specified for fxTAL- The 
crystal should be mounted as close as possible to the input 
pins to minimize output distortion and startup stabilization 
time. The MCU is compatible with most commercially 
available crystals. Nominal crystal parameters are shown in 
Figure 20. 



RESET/Vpp 

This input is used to reset the internal state of the device 
and pro vide an orderly startup procedure. During power up, 
RESET must be held below 0.8 volts: (1) at least tRC after 
Vcc reaches 4.75 volts in order to provide sufficient time for 
the clock generato r to sta bilize, and (2) until Vcc standby 
reaches 4.75 volts. RESET must be held low at least three E 
cycles if asserted during power-up operation. 

This pin is also used to supply Vpp in mode 0 for program- 
ming the EPROM. 

E (ENABLE) 

This is an output clock used primarily for bus synchroniza- 
tion. It is TTL compatible and is the slightly skewed divide- 
by-four result of the device input clock frequency. It will 
drive one Schottky TTL load and 90 pF, and all data given in 
cycles is referenced to this clock unless otherwise noted. 

NMI (NON-MASKABLE INTERRUPT) 

An NMI negative edge requests an MCU interrupt se- 
quence, but the current instruction will be completed before 



it responds to the request. The MCU will then begin an inter- 
rupt sequence. Finally, a vector is fetched from $FFFC and 
$FFFD ($BFFC and $BFFD in mode 0), transferred to the 
program counter, and instruction execution is resumed. NMI 
typically re quire s a 3.3 kO (nomi nal) r esistor to Vcc- There is 
no internal NMI pullup resistor. NMI must be held low for at 
least one E cycle to be recognized under all conditions. 

NOTE 

After reset, an NMI will not be servic ed un til the first 
program load of the stack pointer. Any NMI generated 
before this load will remain pending by the processor. 

iRQl" (MASKABLE INTERRUPT REQUEST 1) 

IRQ1 is a level-sensitive input which can be used to re- 
quest an interrupt sequence. The MPU will complete the cur- 
rent instruction before it responds to the request. If the inter- 
rupt mask bit (I bit) in the condition code register is clear, the 
MCU will begin an interrupt sequence. A vector is fetched 
from $FFF8 and $FFF9 ($BFF8 and $BFF9 in mode 0), 
transferred to the program counter, and instruction execu- 
ti on is resumed. 

IRQ1 typically requires an external 3.3 kQ (nominal) 
resistor to Vcc for wire-OR application. IRQ1 has no internal 
pullup resistor. 

SC1 and SC2 (STROBE CONTROL 1 AND 2) 

The function of SC1 and SC2 depends on the operating 
mode. SC1 is configured as an output in all modes except 
single-chip mode, whereas SC2 is always an output. SC1 
and SC2 can drive one Schottky load and 90 pF. 

SC1 AND SC2 IN SINGLE-CHIP MODE - In single-chip 
mode, SC1 and SC2 are configured as an input and output, 
respectively, and both function as port 3 control lines. SC1 
functions as I S3 and can be used to indicate that port 3 input 
data is ready or output data has been accepted. Three op- 
tions associated with I S3 are controlled by the port 3 control 
and status register and are discussed in the port 3 descrip- 
tion; refer to P30-P37 (PORT 3). If unused, IS3 can remain 
unconnected. 

SC2 is configured as OS3 and can be used to strobe out- 
put data or acknowledge input data. It is controlled by out- 
put strobe select (OSS) in the port 3 control and status 
register. The strobe is generated by a read (OSS = 0) or write 
(OSS = 1) to the port 3 data register. OS3 timing is shown in 
Figure 3. 

SC1 AND SC2 IN EXPANDED NON-MULTIPLEXED 
MODE - In the expanded non-multiplexed mode, both SC1 
and SC2 are configured as outputs. SC1 functions as in- 
put/output select (IOS) and is asserted only when $0100 
through $01 FF is sensed on the internal address bus. 

SC2 is configured as read/write and is used to control the 
direction of data bus transfers. An MPU read is enabled 
when read/write and E are high. 

SCI AND SC2 IN EXPANDED MULTIPLEXED MODE - 

In the expanded multiplexed modes, both SC1 and SC2 are 
configured as outputs. SC1 functions as address strobe and 
can be used to demultiplex the eight least significant ad- 
dresses and the data bus. A latch controlled by address 
strobe captures the lower address on the negative edge, as 
shown in Figure 13. 



MOTOROLA MICROPROCESSOR DATA 
3-232 



MC68701U4 



FIGURE 20 - OSCILLATOR CHARACTERISTICS 

(a) Nominal Recommended Crystal Parameters 
Nominal Crystal Parameters* 





3.58 MHz 


4.00 MHz 


5.0 MHz 


RS 


60 a 


500 


30-50 0 


CO 


3.5 pF 


6.5 pF 


4-6 pF 


C1 


0.015 pF 


0.025 pF 


0.01-0.02 pF 


Q 


>40 K 


>30 K 


>20K 



* NOTE: These are representative AT-cut crystal parameters only. Crystals of other 
types of cut may also be used. 



MC68701U4 



C[_ = 20 pF (typical) 



h0> 

-\<r 



C1 



VrV 

RS 




Equivalent Circuit 



NOTE 

TTL-compatible oscillators may be 
obtained from: 

Motorola Component Products 

Attn: Crystal Clock Oscillators 
2553 N. Edgington St. 

Franklin Park, IL 60131 

Tel: 312-451-1000 

Telex: 433-0067 



(b) Oscillator Stabilization Time Urc> 



VCC 



RESET 



4.75 V 



ss- 



-tRC- 



0.8 V 



Oscillator 
Stabilization 
Time, tRc 



MOTOROLA MICROPROCESSOR DATA 

3-233 



MC68701U4 



SC2 is configured as read/ write and is used to control the 
direction of data bus transfers. An MPU read is enabled 
when read/write and E are high. 

P10-P17 (PORT 1) 

Port 1 is a mode independent 8-bit I/O and timer port. 
Each line can be configured as either an input or output as 
defined by the port 1 data direction register. Port 1 bitsO, 1, 
and 2 (P10, P11, and P12) can also be used to exercise one 
input edge function and two output compare functions of 
the timer. The TTL compatible three-state buffers can drive 
one Schottky TTL load and 30 pF, Darlington transistors, or 
CMOS devices using external pu llup res istors. It is con- 
figured as a data input port during RESET. Unused pins can 
remain unconnected. 

P20-P24 {PORT 2) 

Port 2 is a mode-independent, 5-bit, multipurpose I/O 
port. The volta ge leve ls present on P20, P21 , and P22 on the 
rising edge of RESET determine the operating mode of the 
MCU. The entire port is then configured as a data input port. 
The port 2 lines can be selectively configured as data output 
lines by setting the appropriate bits in the port 2 data direc- 
tion register. The port 2 data register is used to move data 
through the port. However, if P21 is configured as an out- 
put, it is tied to the timer output compare 1 function and can- 
not be used to provide output from the port 2 data register 
unless output enable 1 (OE1) is cleared in timer control 
register 1 . 

Port 2 can also be used to provide an interface for the 
serial communications interface and the timer input edge 
function. These configurations are described in SERIAL 
COMMUNICATIONS INTERFACE and PROGRAMMABLE 
TIMER. 

The port 2 three-state TTL-compatible output buffers are 
capable of driving one Schottky TTL load and 30 pF, or 
CMOS devices using external pullup resistors. 

PORT 2 DATA REGISTER 

7 6 5 4 3 2 1 0 
|PC2 | PC1 | PCO | P24 | P23 | P22 | P21 | P20 | $03 

P30-P37 (PORT 3) 

Port 3 can be configured as an I/O port, a bidirectional 
8-bit data bus, or a multiplexed address/ data bus depending 
on the operating mode. The TTL compatible three-state out- 
put buffers can drive one Schottky TTL load and 90 pF. 
Unused lines can remain unconnected. 

PORT 3 IN SINGLE-CHIP MODE - Port 3 is an 8-bit I/O 
port in the single-chip mode with each line configured by the 
port 3 data direction register. There are also two lines, IS3 
and OS3, which can be used to control port 3 data transfers. 

Three port 3 options are controlled by the port 3 control 
and status register and are available only in single-chip 
mode: 1) port 3 input data can be latched using IS3 (SC1) as 
a control signal, 2) OS3 (SC2) can be generated by eith er an 
MPU read or write to the port 3 data register, and 3) an IRQ! 
interrupt can be enabled by an IS3 negative edge. Port 3 
latch timing is shown in Figure 4. 



PORT 3 CONTROL AND STATUS REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


IS3 
Flag 


IS3 
iRGl 


X 


OSS 


Latch 
Enable 


X 


X 


X 



$0F 



Bits 0-2 Not used. 

Bit 3 Latch Enable - This bit controls the input latch for 
port 3. If set, input data is latched by an IS3 
negative edge. The latch is transparent after a read 
of the port 3 data register. Latch enable is cleared 
during reset. 

Bit 4 OSS (Output Strobe Select) - This bit determines 
whether OS3 will be generated by a read or write of 
the port 3 data register. When clear, the strobe is 
generated by a read; when set, it is generated by a 
write. OSS is cleared during reset. 

Bit 5 Not used. 

Bit 6 IS3 IRQ1 Enable - When set, an IRQ1 interrupt 
will be enabled whenever the I S3 flag is set; when 
clear, the interrupt is inhibited. This bit is cleared 
during reset. 

Bit 7 IS3 Flag - This read-only status bit is set by an IS3 
negative edge. It is cleared by a read of the port 3 
control and status register (with I S3 flag set) 
followed by a read or write to the port 3 data 
register or during reset. 

PORT 3 IN EXPANDED NON-MULTIPLEXED MODE - 

Port 3 is configured as a bidirectional data bus (D7-D0) in the 
expanded non-multiplexed mode. The direction of data 
transfers is controlled by read/ write (SC2). Data is clocked 
by E (enable). 

PORT 3 IN EXPANDED MULTIPLEXED MODE - Port 3 is 
configured as a time multiplexed address (A7-A0) and data 
bus (D7-D0) in the expanded multiplexed mode where ad- 
dress strobe (AS) can be used to demultiplex the two buses. 
Port 3 is held in a high-impedance state between valid ad- 
dress and data to prevent bus conflicts. 

P40-P47 (PORT 4) 

Port 4 is configured as an 8-bit I/O port, as address out- 
puts, or as data inputs depending on the operating mode. 
Port 4 can drive one Schottky TTL load and 90 pF, and is the 
only port with internal pullup resistors. Unused lines can re- 
main unconnected. 

PORT 4 IN SINGLE-CHIP MODE - In single-chip mode, 
port 4 functions as an 8-bit I/O port with each line con- 
figured by the port 4 data direction register. Internal pullup 
resistors allow the port to directly interface with CMOS at 
5-volt levels. External pullup resistors to more than 5 volts, 
however, cannot be used. 

PORT 4 IN EXPANDED NON-MULTIPLEXED MODE - 

Port 4 is configured from reset as an 8-bit input port where 
the port 4 data direction register can be written to provide 
any br all of eight address lines AO to A7. Internal pullup 
resistors pull the lines high until the port 4 data direction 
register is configured. 



MOTOROLA MICROPROCESSOR DATA 
3-234 



MC68701U4 



PORT 4 IN EXPANDED MULTIPLEXED MODE - In all ex- 
panded multiplexed modes except modes 1 and 6, port 4 
functions as half of the address bus and provides A8 to A15. 
In modes 1 and 6, the port is configured from reset as an 
8-bit parallel input port where the port 4 data direction 
register can be written to provide any or all of upper address 
lines A8 to A15. Internal pullup resistors pull the lines high 
until the port 4 data direction register is configured where bit 
0 controls A8. 

RESIDENT MEMORY 

The MC68701 U4 has 192 bytes of on-chip RAM and 4096 
bytes of on-chip UV erasable EPROM. This memory is con- 
trolled by four bits in the RAM/EPROM control register. 

Thirty-two bytes of the RAM are powered through the 
Vcc standby pin and are maintainable during Vcc power- 
down. This standby portion of the RAM consists of 32 bytes 
located from $40 through $5F. 

Power must be supplied to Vcc standby if the internal 
RAM is to be used, regardless of whether standby power 
operation is anticipated. 

The RAM is controlled by the RAM/EPROM control 
register. 

RAM/EPROM CONTROL REGISTER ($14) 

The RAM/EPROM control register includes four bits: 
STBY PWR, RAME, PLC, and PPC. Two of these bits, 
STBY PWR and RAME, are used to control RAM access and 
determine the adequacy of the standby power source during 
power-down operation. It is intended that RAME be cleared 
and STBY PWR be set as part of a power-down procedure. 
RAME and STBY PWR are read/ write bits. 

The remaining two bits, PLC and PPC, control the opera- 
tion of the EPROM. PLC and PPC are readable in all modes 
but can be changed only in modeO. The PLC bit can be writ- 
ten without restriction in mode 0, but operation of the PPC 
bit is controlled by the state of PLC. 

Associated with the EPROM are an 8-bit data latch and a 
16-bit address latch. The data latch is enabled at all times, 
latching each data byte written to the EPROM. The address 
latch is controlled by the PLC bit. 

A description of the RAM/EPROM control register 
follows. 

RAM/EPROM CONTROL REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


STBY 
PWR 


RAME 


X 


X 


X 


X 


PPC 


PLC 



$14 



BitO Programming Latch Control (PLC). This bit con- 
trols the latch which captures the EPROM address 
to be programmed and whether the PCC bit can be 
cleared. The latch is triggered by an MPU write to a 
location in the EPROM. This bit is set during reset 
and can be cleared only in mode 0. The PLC bit is 
defined as follows: 

PLC = 0- EPROM address latch enabled; EPROM 
address is latched during MPU writes to 
the EPROM. 

PLC=1- EPROM address latch is transparent. 



Bit 1 Programming Po wer Con trol (PPC). This bit gates 
power from the RESET/Vpp pin to the EPROM 
programming circuit. PPC is set during reset and 
whenever the PLC bit is set. It can be cleared only if 
operating in modeO, and if PLC has been previous- 
ly cleared. The PPC bit is defined as follows: 
PPC = 0— EPROM programming power (Vpp) 
applied. 

PPC=1- EPROM programming power (Vpp) is 
not applied. 

Bit 2-5 Unused. 

Bit 6 RAM Enable (RAME). This read/write bit can be 
used to remove the entire RAM from the internal 
memory map. RAME is set (enabled) during reset 
provided standby power is available on the positive 
edge of reset. If RAME is clear, any access to a 
RAM address is external. If RAME is set, the RAM 
is included in the internal map. 

Bit 7 Standby Power (STBY PWR). This bit is a 
read/write status bit which when cleared indicates 
that Vcc standby has decreased sufficiently below 
VsBB (minimum) to make data in the standby 
RAM suspect. It can be set only by software and is 
not affected during reset. 

Note that if PPC and PLC are set, they cannot be 
simultaneously cleared with a single MPU write. The PLC bit 
must be cleared prior to attempting to clear PPC. If both PPC 
and PLC are clear, setting PLC will also set PPC. In addition, 
it is assumed that Vpp is applied to the RESET/Vpp pin 
whenever PCC is clear. If this is not the case, the result is 
undefined. 

ERASING THE MC68701U4 EPROM 

Ultraviolet erasure will clear all bits of the EPROM to the 
zero state. The MC68701U4 EPROM is programmed by eras- 
ing it to zeros and entering ones into the desired bit loca- 
tions. 

The MC68701U4 EPROM can be erased by exposure to 
high intensity ultraviolet light with a wave length of 2537 
angstroms for a minimum of 30 minutes. The recommended 
integrated dose (ultraviolet intensity times exposure time) is 
15 watts/centimeter. The lamps should be used without 
shortwave filters, the MC68701U4 should be positioned 
about one inch away from the ultraviolet tubes, and the 
transparent lid should not be covered. 

The MC68701U4 transparent lid should always be covered 
after erasing. This protects both the EPROM and light- 
sensitive nodes from accidental exposure to ultraviolet light. 

PROGRAMMING THE MC68701U4 EPROM 

When the MC68701U4 is released from reset in modeO, a 
vector is fetched from location $BFFE:$BFFF. This provides 
a method for an external program to obtain control of the 
microcomputer with access to every location in the EPROM. 

To program the EPROM, it is necessary to operate the 
MC68701U4 in mode 0 under the control of a program resi- 
dent in external memory which can facilitate loading and pro- 
gramming of the EPROM. After the pattern has been loaded 




MOTOROLA MICROPROCESSOR DATA 

3-235 



MC68701U4 



into external memory, the EPROM can be programmed as 
follows: 

a. Apply programming power (Vpp) to the RESET/Vpp 
pin. 

b. Clear the PLC control bit and set the PPC bit by writing 
$FE to the RAM/ EPROM control register. 

c. Write data to the next EPROM location to be program- 
med. Triggered by an MPU write to the EPROM, inter- 
nal latches capture both the EPROM address and the 
data byte. 

d. Clear the PPC bit for programming time, t pp , by writing 
$FC to the RAM/ EPROM control register and waiting 
for time, t pp . T his step gates the programming power 
(Vpp) from the RESET/Vpp pin to the EPROM which 
programs the location. 

e. Repeat steps b through d for each byte to be program- 
med. 

f. Set the PLC and PPC bits by writing $FF to the 
RAM/ EPROM control register. 

g. Remov e the programming power (Vpp) from the 
RESET/Vpp pin. The EPROM can now be read and 
verified. 

Because the erased state of an EPROM byte is $00, it is not 
necessary to program a location which is to contain $00. 
Finally, it should be noted that the result of inadvertently 
programming a location more than once is the logical OR of 
the data patterns. 

PROGRAMMABLE TIMER 

The programmable timer can be used to perform 
measurements on two separate input waveforms while in- 
dependently generating three output waveforms. Pulse 
widths can vary from several microseconds to many 
seconds. A block diagram of the timer is shown in Figure 21. 
COUNTER <$09:0A), ($15, $16) 

The key timer element is a 16-bit free-running counter 
which is incremented by E (enable). It is cleared during reset 
and is read-only with one exception: in mode 0 a write to the 
counter ($09) will preset it to $FFF8; This feature, intended 
for testing, can disturb serial operations because the counter 
provides the SCI internal bit rate clock. The TOF bit is set 
whenever the counter contains all ones. If ETOI is set, an in- 
terrupt will occur when the TOF is set. The counter may also 
be read at $15 and $16 to avoid inadvertently clearing the 
TOF. 



OUTPUT COMPARE REGISTERS ($0B:0C), ($1A:1B), 
($1C:1D) 

The three output compare registers are 16-bit read/write 
registers, each used to control an output waveform or pro- 
vide an arbitrary time-out flag. They are compared with the 
free-running counter during the negative half of each E cy- 
cle. When a match occurs, the corresponding output com- 
pare flag (OCF) is set and the corresponding output level 
(OLVL) is clocked to an output level register. If both the cor- 
responding output enable bit and data direction register bit 
are set, the value represented in the output level register will 
appear on the corresponding port pin. The appropriate OLVL 
bit can then be changed for the next compare. 

The function is inhibited for one cycle after a write to its 
high byte ($0B, $1A, or $1C) to ensure a valid compare after 
a double byte write. Writes can be made to either byte of the 
output compare register without affecting the other byte. 
The OLVL value will be clocked out independently of 
whether the OCF had previously been cleared. The output 
compare registers are set to $FFFF during reset. 

INPUT CAPTURE REGISTERS ($0D:0E), ($1E:1F) 

The two input capture registers are 16-bit read-only 
registers used to store the free-running counter when a 
"proper" input transition occurs as defined by the cor- 
responding input edge bit (IEDG1 or IEDG2). The input pin's 
data direction register should be configured as an input, but 
the edge detect circuit always senses P10 and P20 even 
when configured as an output. The counter value will be 
latched into the input capture registers on the second 
negative edge of the E clock following the transition. 

An input capture can occur independently of ICF; the 
register always contains the most current value. Counter 
transfer is inhibited, however, between accesses of a double 
byte MPU read. The input pulse width must be at Least .two € 
cycles to ensure an input capture under all conditions. 

TIMER CONTROL AND STATUS REGISTERS 

Four registers are used to provide the MC68701U4 with 
control and status information about the three output com- 
pare functions, the timer overflow function, and the two in- 
put edge functions of the timer. They are: 

Timer Control and Status Register (TCSR) 

Timer Control Register 1 (TCR1) 

Timer Control Register 2 (TCR2) 

Timer Status Register (TSR) 



MOTOROLA MICROPROCESSOR DATA 
3-236 



FIGURE 21 - BLOCK DIAGRAM OF PROGRAMMABLE TIMER 



MC68701U4 Internal Bus 



7t 



Output Compare 
Register 3 



$09:0A 
($15:16) 



Output Compare 




Output Compare 




Free 


Running 


Register 2 




Register 1 




16-Bit Counter 



Input Capture 
Register 1 



Input Capture 
Register 2 

7^ 



O 



Output Compares 
(Three) 



ICF1 | 0CF1 | TOF | EICI1 | E0ICI1 [ ETOI | IEDG1 1 0LVL1 1 



7 7 



Overflow 
Detect 



A 



£ 



-A 1 



Edge Detects 
(Two) 



V 1 



V 1 



rx 



| 0E3 | 0E2 | 0E1 | IEDG2 | IEDG1 1 0LVL3 |0LVL2 1 0LVL1 1 



^ > 



| ICF2 | ICF1 j 0CF3 | 0CF2 | 0CF1 | TOF | 1 | 1 | | EICI2 | EICI1 | EOCI3 1 E0CI2 1 E0CI1 | ETOI | TEST |cLQCk| 



D Q — J^> 



Output Level 
Register 1 



- — > 



Output Level 
Register 2 



Output Level 
Register 3 



Port Control 
Circuitry 



Input Edge 
_« P20 



Output Level 
P21 



Output Level 
•*■ P11 



Output Level 
-*• P12 



5 

o 

o> 

00 

-J 
o 

c 




MC68701U4 



TIMER CONTROL AND STATUS REGISTER (TCSR) 
($08) — The timer control and status register is an 8-bit 
register of which all bits are readable, while only bits 0-4 can 
be written. All the bits in this register are also accessible 
through the two timer control registers and the timer status 
register. The three most significant bits provide the timer 
status and indicate if: 

1 . a proper level transition has been detected at P20, 

2. a match has occurred between the free-running 
counter and output compare register 1, or 

3. the free-running counter has overflowed. 

Each of the three events can generate an IRQ2 interrupt 
and is controlled by an individual enable bit in the TCSR. 

TIMER CONTROL AND STATUS REGISTER 

7 6 5 4 3 2 1 0 
llCFI I OCF1 I TOF I EICI1 I EOCI1 I ETOI I IEDG1 |OLVL1 1 $06 



Bit 7 Input Capture Flag - ICF1 is set to indicate that a 
proper level transition has occurred; it is cleared by 
reading the TCSR or the TSR (with ICF1 set) and 
the input capture register 1 high byte ($0D), or dur- 
ing reset. Refer to TIMER STATUS REGISTER 
(TSR) ($19). 

TIMER* CONTROL REGISTER 1 (TCR1) ($17) - Timer 
control register 1 is an 8-bit read/write register which con- 
tains the control bits for interfacing the output compare and 
input capture registers to the corresponding I/O pins. 



TIMER CONTROL REGISTER 1 



7 


6 


5 


4 


3 


2 


1 0 


|OE3 


OE2 


OE1 


IEDG2 1 


IEDG1 


OLVL3 


0LVL2|0LVLl| 



Bit 0 Output Level 1 - OLVL1 is clocked to output level 
register 1 by a successful output compare and will 
appear at P21 if bit 1 of the port 2 data direction 
register is set and the OE1 control bit in timer con- 
trol register 1 is set. OLVL1 and output level 
register 1 are cleared during reset. Refer to TIMER 
CONTROL REGISTER 1 (TCR1) ($17). 

Bit 1 Input Edge 1 - IEDG1 is cleared during reset and 
controls which level transition on P20 will trigger a 
counter transfer to input capture register 1: 
IEDG1 =0 transfer on a negative-edge 
IEDG1 = 1 transfer on a positive-edge 
Refer to TIMER CONTROL REGISTER 1 (TCR1) 
($17). 

Bit 2 Enab le Timer Overflow Interrupt - When set, an 
IRQ2 interrupt will be generated when the timer 
overflow flag is set; when clear, the interrupt is in- 
hibited. ETOI is cleared during reset. Refer to 
TIMER CONTROL REGISTER 2 (TCR2) ($18). 

Bit 3 En able O utput Compare Interrupt 1 - When set, 
an IRQ2 interrupt will be generated when output 
compare flag 1 is set; when clear, the interrupt is in- 
hibited. EOCI1 is cleared during reset. Refer to 
TIMER CONTROL REGISTER 2 (TCR2) ($18). 

Bit 4 Enab le Input Capture Interrupt 1 - When set, an 
IRQ2 interrupt will be generated when input cap- 
ture flag 1 is set; when clear, the interrupt is in- 
hibited. EICI1 is cleared during reset. Refer to 
TIMER CONTROL REGISTER 2 (TCR2) ($18). 

Bit 5 Timer Overflow Flag — The TOF is set when the 
counter contains all ones ($FFFF). It is cleared by 
reading the TCSR or the TSR (with TOF set) and 
the counter high byte ($09), or during reset. Refer 
to TIMER STATUS REGISTER (TSR) ($19). 

Bit 6 Output Compare Flag 1 — OCF1 is set when output 
compare register 1 matches the free-running 
counter. OCF1 is cleared by reading the TCSR or 
the TSR (with OCF1 set) and then writing to output 
compare register 1 ($0B or $0C), or during reset. 
Refer to TIMER STATUS REGISTER (TSR) ($19). 



Bit 0 



Bit 1 



Output Level 1 - OLVL1 is clocked to output level 
register I by a successful output compare and will 
appear at P21 if bit T of the port 2 data direction 
register is set and the OE1 control bit is set. OLVL1 
and output level register 1 are cleared during reset. 
Refer to TIMER CONTROL AND STATUS 
REGISTER (TCSR) ($08). 



Output Level 2 - OLVL2 is clocked to output level 
register 2 by a successful output compare and will 
appear at P11 if bit 1 of port 1 data direction register 
is set and the OE2 control bit is set. OLVL2 and out- 
put level register 2 are cleared during reset. 

Bit 2 Output Level 3 - OLVL3 is clocked to output level 
register 3 by a successful output compare and will 
appear at P12 if bit 2 of port 1 data direction register 
is set and the OE3 control bit is set. OLVL3 and out- 
put level register 3 are cleared during reset. 

Bit 3 Input Edge 1 - IEDG1 is cleared during reset and 
controls which level transition on P20 will trigger a 
counter transfer to input capture register 1. 
IEDG1 =0 transfer on a negative-edge 
IEDG1 = 1 transfer on a ppsitive-edge 
Refer to TIMER CONTROL AND STATUS 
REGISTER (TCSR) ($08). 

Bit 4 Input Edge 2 - IEDG2 is cleared during reset and 
controls which level transition on P10 will trigger a 
counter transfer to input capture register 2. 
IEDG2 = 0 transfer on a negative-edge 
IEDG2= 1 transfer on a positive-edge 

Bit 5 Output Enable 1 - OE1 is set during reset and 
enables the contents of output level register 1 to be 
connected to P21 when bit 1 of port 2 data direc- 
tion register is set. 

OE1 =0 port 2 bit 1 data register output 

OE1 = 1 output level register 1 

Bit 6 Output Enable 2 — OE2 is cleared during reset and 
enables the contents of output level register 2 to be 
connected to P11 when bit 1 of port 1 data direc- 
tion register is set. 

OE2 = 0 port 1 bit 1 data register output 

OE2= 1 output level register 2 



MOTOROLA MICROPROCESSOR DATA 
3-238 



MC68701U4 



Bit 7 Output Enable 3 - OE3 is cleared during reset and 
enables the contents of output level register 3 to be 
connected to P12 when bit 2 of port 1 data direc- 
tion register is set 

OE3 = 0 port 1 bit 2 data register output 

OE3= 1 output level register 3 

TIMER CONTROL REGISTER 2 (TCR2) ($18) - Timer 
control register 2 is an 8-bit read/write register (except bits 0 
and 1) which enable the interrupts associated with the free- 
running counter, the output compare registers, and the input 
capture registers. In test mode 0, two more bits (clock and 
test) are available for checking the timer. 

TIMER CONTROL REGISTER 2 
(Non-Test Modes) 



BitO 



7 


6 5 


4 


3 


2 1 


0 


|EICI2 


EICI1 | EOCI3 


EOCI2 


EOCI1 


ETOI 


1 





$18 



Bits 0-1 Read-Only Bits - When read, these bits return a 
value of 1 . Refer to TIMER CONTROL REGISTER 2 
(Test Mode). 

Bit 2 Enab le Timer Overflow Interrupt - When set, an 
IRQ2 interrupt will be generated when the timer 
overflow flag is set; when clear, the interrupt is in- 
hibited. ETOI is cleared during reset. Refer to 
TIMER CONTROL AND STATUS REGISTER 
(TCSR) ($08). 

Bit 3 En able O utput Compare Interrupt 1 - When set, 
an IRQ2 interrupt will be generated when the out- 
put compare flag 1 is set; when clear, the interrupt 
is inhibited. EOCI1 is cleared during reset. Refer to 
TIMER CONTROL AND STATUS REGISTER 
(TCSR) ($08). 

Bit 4 En able O utput Compare Interrupt 2 - When set, 
an IRQ2 interrupt will be generated when the out- 
put compare flag 2 is set; when clear, the interrupt 
is inhibited. EOCI2 is cleared during reset. 

Bit 5 En able O utput Compare Interrupt 3 — When set, 
an IRQ2 interrupt will be generated when the out- 
put compare flag 3 is set; when clear, the interrupt 
is inhibited. EOCI3 is cleared during reset. 

Bit 6 Enab le Input Capture Interrupt 1 - When set, an 
IRQ2 interrupt will be generated when the input 
capture flag 1 is set; when clear, the interrupt is in- 
hibited. EICI1 is cleared during reset. Refer to 
TIMER CONTROL AND STATUS REGISTER 
(TCSR) ($08). 

Bit 7 Enab le Input Capture Interrupt 2 - When set, an 
IRQ2 interrupt will be generated when the input 
capture flag 2 is set; when clear,, the interrupt is in- 
hibited. EICI2 is cleared during reset. 

The timer test bits (test and clock) allow the free- running 
counter to be tested as two separate 8-bit counters to speed 
testing. 



TIMER CONTROL REGISTER 2 
(Test Mode) 



CLOCK - The CLOCK control bit selects which 
half of the 16-bit free-running counter (MSB or 
LSB) should be clocked with E. The CLOCK bit is a 
read/ write bit only in mode 0 and is set during 
reset. 

CLOCK = 0 - Only the eight most significant bits 
of the free-running counter run with TEST = 0. 

CLOCK = 1 - Only the eight least significant bits 
of the free-running counter run when 
TEST = 0. 



Bit 1 



TEST - the TEST control bit enables the timer test 
mode. TEST is a read/write bit in mode 0 and is set 
during reset. 
TEST = 0 — Timer test mode enabled: 

a) The timer LSB latch is transparent which 
allows the LSB to be read independently 
of the MSB. 

b) Either the MSB or the LSB of the timer is 
clocked by E, as defined by the CLOCK 
bit: 

TEST=1 - Timer test mode disabled. 

Bits 2-7 See TIMER CONTROL REGISTER 2 (Non-Test 
Modes). (These bits function the same as in the 
non-test modes.) 

TIMER STATUS REGISTER (TSR) ($19) - The timer 
status register is an 8-bit read-only register which contains 
the flags associated with the free-running counter, the out- 
put compare registers, and the input capture registers. 

TIMER STATUS REGISTER 



7 


6 


5 


4 


3' 


2 1 


0 


ICF2 


ICF1 


OCF3 


OCF2 


OCF1 


TOF 


1 


1 



$19 



EICI2 EICI1 | EOGI3 EOCI2 1 EOCI1 | ETOI | TESt|clOCK| $18 



Bits 0-1 Not used. 

Bit 2 Timer Overflow Flag — The TOF is set when the 
counter contains all ones ($FFFF). It is cleared by 
reading the TSR or the TCSR (with TOF set) and 
then the counter high byte ($09), or during reset. 
Refer to TIMER CONTROL AND STATUS 
REGISTER (TCSR) ($08). 

Bit 3 Output Compare Flag 1 — OCF1 is set when output 
compare register 1 matches the free-running 
counter. OCF1 is cleared, by reading the TSR or the 
TCSR (with OCF1 set) and then writing to output 
compare register 1 ($0B or $0C), or during reset. 
Refer to TIMER CONTROL AND STATUS 
REGISTER (TCSR) ($08) 

Bit 4 Output Compare Flag 2 - OCF2 is set when output 
compare register 2 matches the free-running 
counter. OCF2 is cleared by reading the TSR (with 
OCF2 set) and then writing to output compare 
register 2 ($1A or $1B), or during reset. 

Bit 5 Output Compare Flag 3 - OCF3 is set when output 
compare register 3 matches the free-running 
counter. OCF3 is cleared by reading the TSR (with 
OCF3 set) and then writing to output compare 
register 3 ($1C or $1D), or during reset. 

Bit 6 Input Capture Flag 1 - ICF1 is set to indicate that a 
proper level transition has occurred; it is cleared by 
reading the TSR or the TCSR (with ICF1 set) and 
the input capture register 1 high byte ($0D), or dur- 
ing reset. Refer to TIMER CONTROL AND 
STATUS REGISTER (TCSR) ($08). 




MOTOROLA MICROPROCESSOR DATA 
3-239 



MC68701U4 



Bit 7 Input Capture Flag 2 — ICF2 is set to indicate that a 
proper level transition has occurred; it is cleared by read- 
ing the TSR (with ICF2 set) and the input capture register 
2 high byte ($1E), or during reset. 



SERIAL COMMUNICATIONS INTERFACE 

A full-duplex asynchronous serial communications interface 
(SCI) is provided with two data formats and a variety of rates. 
The SCI transmitter and receiver are functionally independent 
but use the same data format and bit rate. Serial data formats 
include standard mark/space (NRZ) and bi-phase. Both provide 
one start bit, eight data bits, and one stop bit. "Baud" and "bit 
rate" are used synonymously in the following description. 

WAKE-UP FEATURE 

In a typical serial loop multiprocessor configuration, the soft- 
ware protocol will usually identify the addressee(s) at the be- 
ginning of the message. In order to permit uninterested MPUs 
to ignore the remainder of the message, wake-up feature is 
included whereby all further SCI receiver flag (and interrupt) 
processing can be inhibited until its data line goes idle. An SCI 
receiver is re-enabled by an idle string of eleven consecutive 



ones or during reset. Software must provide for the required 
idle string between consecutive messages and prevent it within 
messages. 

PROGRAMMABLE OPTIONS 

The following features of the SCI are programmable: 

• Format: standard mark/space (NRZ) or bi-phase 

• Clock: external or internal bit rate clock 

• Baud: one of eight per E clock frequency or external 
clock (x8 desired baud) 

• Wake-Up Feature: enabled or disabled 

• Interrupt Requests: enabled individually for transmitter 
and receiver 

• Clock Output: internal bit rate clock enabled or disabled 
to P22 

SERIAL COMMUNICATIONS REGISTERS 

The serial communications interface includes four address- 
able registers as depicted in Figure 22. It is controlled by the 
rate and mode contol register and the transmit/receive control 
and status register. Data is transmitted and received utilizing 
a write-only transmit register and a read-only receive register. 
The shift registers are not accessible to software. 



Rx 
Bit 
3 



Clock 
Bit 
2 



FIGURE 22 — SCI REGISTERS 

Bit 7 Rate and Mode Control Register Bit 0 



EBE 




CC1 


CCO 


SS1 


SSO 


Transmit/ Receive Control and Status Register 


RDRF 


ORFE 


TDRE 


RIE 


RE 


TIE 


TE 


wu 



Receive Data Register 



$12 



(Not Addressable) 



Receive Shift Register 



Bit Rate 
Generator 



' r (Not Addressable) 

Transmit Shift Register 

Transmit Data Register 



MOTOROLA MICROPROCESSOR DATA 
3-240 



MC68701U4 



RATE AND MODE CONTROL REGISTER (RMCR) ($10) 

- The rate and mode control register controls the SCI bit 
rate, format, clock source, and under certain conditions, the 
configuration of P22. The register consists of five write-only 
bits which are cleared during reset. The two least significant 
bits in conjunction with bit 7 control the bit rate of the inter- 
nal clock and the remaining two bits control the format and 
clock source. 

RATE AND MODE CONTROL REGISTER 



7 


6 


5 


4 


3 


2 


1 


0 


EBE 


X 


X 


X 


CC1 


CCO 


SSI 


SSO | 



Bit 1 :Bit 0 SS1 :SS0 Speed Select - These two bits select 
the baud when using the internal clock. Eight 
rates may be selected (in conjunction with bit 7) 
which are a function of the MCU input frequen- 
cy. Table 6 lists bit time and rates for three 
selected MCU frequencies. 

Bit 3: Bit 2 CC1:CC0 Clock Control and Format Select - 

These two bits control the format and select the 
serial clock source. If CC1 is set, the DDR value 



for P22 is forced to the complement of CCO and 
cannot be altered until CC1 is cleared. If CC1 is 
cleared after having been set, its DDR value is 
unchanged. Table 7 defines the formats, clock 
source, and use of P22. 

Bits 4-6 Not used. 

Bit 7 EBE Enhanced Baud Enable - EBE selects the 
standard MC6801 baud rates when clear and the 
additional baud rates when set (Table 6). This 
bit is cleared by reset and is a write-only control 
bit. 

EBE = 0 standard MC6801 baud rates 
EBE=1 additional baud rates 

If both CC1 and CCO are set, an external TTL-compatible 
clock must be connected to P22 at eight times (8x ) the 
desired bit rate, but not greater than E, with a duty cycle of 
50% (±10%). If CC1:CC0= 10, the internal bit rate clock is 
provided at P22 regardless of the values for TE or RE. 

NOTE 

The source of SCI internal bit rate clock is the timer 
free-running counter. An MPU write to the counter in 
mode 0 can disturb serial operations. 



TABLE 6 - SCI BIT TIMES AND RATES 



EBE 


SS1:SS0 


4f 0 ~ 


2.4576 MHz 


4.0 MHz 


4.9152 MHz 


E 


614.4 kHz 


1.0 MHz 


1 .2288 MHz 


Baud 


Time 


Baud 


Time 


Baud 


Time 


0 


0 


0 


+ 16 


38400.0 


26 us 


62500.0 


16.0 us 


76800.0 


13.0 /is 


0 


0 


1 


+ 128 


4800.0 


208.3 M s 


7812 5 


128.0 


9600.0 


, 104.2 its 


0 


1 


0 


+ 1024 


600.0 


1.67 ms 


976.6 


1 .024 ms 


1200.0 


833.3 ,is 


0 


1 


1 


+ 4096 


150.0 


6.67 ms 


244.1 


4,096 ms 


300.0 


3.33 ms 


1 


0 


0 


-64 


9600.0 


104.2 M s 


15625.0 


64 lis 


19200.0 


52.0 lis 


1 


0 


1 


+ 256 


2400.0 


416.6 us 


3906.3 


256 lis 


4800.0 


208.3 ps 


1 


1 


0 


+ 512 


1200.0 


833 .3 ,is 


1953.1 


512 us 


2400.0 


416.6 ^s 


1 


1 


1 


+ 2048 


300.0 


3.33 ms 


488.3 


2.05 ms 


600.0 


01 .67 ms 


External (P22)» 


76800.0 


13.0,is 


125000.0 


8.0 lis 


153600.0 


6.5 us 



* Using maximum clock rate 



TABLE 7 - SCI FORMAT AND CLOCK SOURCE CONTROL 







Clock 


Port 2 


CC1:CC0 


Format 


Source 


Bit 2 


00 


Bi-Phase 


Internal 


Not Used 


01 


NRZ 


Internal 


Not Used 


10 


NRZ 


Internal 


Output 


11 


NRZ 


External 


Input 



MOTOROLA MICROPROCESSOR DATA 
3-241 



MC68701U4 




TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER 
(TRCSR) ($11) — the transmit/receive control and status reg- 
ister controls the transmitter, receiver, wake-up feature, and 
two individual interrupts, and monitors the status of serial op- 
erations. All eight bits are readable while bi ts 0 to 4 are also 
writable. The register is initialized to $20 by RESET. 

TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER 

7 6 5 4 3 2 1 0 
|RDRF|ORFE [-TDRE | RIE | RE | TIE | TE | WU [ $11 

BitO "Wake-Up on Idle Line — When set, WU enables the 
wake-up function; it is cleared by eleven consecutive 
ones or during reset. WU will not be set if the line is 
idle. Refer to WAKE-UP FEATURE. 

Bit 1 Transmit Enable — When set, P24 DDR bit is set, cannot 
be changed, and will remain set if TE is subsequently 
cleared. When TE is changed from clear to set, the trans- 
mitter is connected to P24 and a preamble of nine con- 
secutive ones is transmitted. TE is cleared during reset. 

Bit 2 Transmit Interrupt Enable — When set, an IRQ2 is set; 
when clear, the interrupt is inhibited. TE is cleared during 
reset. 

Bit 3 Receive Enable — When set, the P23 DDR bit is cleared, 
cannot be changed, and will remain clear if RE is sub- 
sequently cleared. While RE is set, the SCI receiver is 
enabled. RE is cleared during reset. 

Bit 4 Receiver Interrupt Enable — When set, an IRQ2 interrupt 
is enabled when RDRF and/or ORFE is set; when clear, 
the interrupt is inhibited. RIE is cleared during reset. 

Bit 5 Transmit Data Register Empty — TDRE is set when the 
transmit data register is transfered to the output serial 
shift register or during reset. It is cleared by reading the 
TRCSR (with TDRE set) and then writing to the transmit 
data register. Additional data will be transmitted only if 
TDRE has been cleared. 



Bit 6 Overrun Framing Error — If set, ORFE indicates either 
an overrun or framing error. An overrun is a new byte 
ready to transfer to the receiver data register with RDRF 
still set. A receiver framing error has occurred when the 
stop bit (1) is not found in the tenth bit time. An overrun 
can be distinguished from a framing error by the state 
of RDRF: if RDRF is set, then an overrun has occurred; 
otherwise, a framing error has been detected. Data is 
not transferred to the receive data register in an overrun 
condition. Unframed data causing a framing error is 
transferred to the receive data register. However, sub- 
sequent data transfer is blocked until the framing error 
flag is cleared. ORFE is cleared by reading the TRCSR 
(with ORFE set) then the receive data register, or during 
reset. 

Bit 7 Receive Data Register Full — RDRF is set when the input 
serial shift register is transferred to the receive data reg- 
ister, or during reset. 



SERIAL OPERATIONS 

The SCI is initialized by writing control bytes first to the rate 
and mode control register and then to the transmit/receive 
control and status register. When TE is set, the output of the 
transmit serial shift register is connected to P24 and serial 
output is initiated by transmitting a 9-bit preamble of ones. 

At this point, one of two situations exists: 1 ) if the transmit 
data register is empty (TDRE = 1); a continuous string of ones 
will be sent indicating an idle line; or 2) if a byte has been 
written to the transmit data register (TDE = 0), it will be trans- 
ferred to the output serial shift register (synchronized with the 
bit rate clock), TDRE will be set, and transmission will begin. 

The start bit (0), eight data bits (beginning with bit 0), and a 
stop bit (1) will be transmitted. If TDRE is still set when the 
next byte transfer occurs, ones will be sent until more data is 
provided. In bi-phase format, the output toggles at the start of 
each bit and at half-bit time when a one is sent. Receive op- 
eration is controlled by RE which configures P23 as an input 
and enables the receiver. SCI data formats are illustrated in 
Figure 23. 



FIGURE 23 - SCI DATA FORMATS 



Output 
Clock 

Data 

NRZ 
Format 



Bi-Phase 
Format 



uuirmrLriarLruuin 

1 ! ! ! i .!.':.! : ! 
! i i • o . i . i i o i o 1 ■ o - 

. I ! ! ! ! : ! : • ! | 

L_ru i n_r 



I I I 



I I I 



iJTJTJinjinjHJiJif 



Idle Start 



Bit 

0 1 2 3 4 5 



Bit 
7 Stop 



Data 01001101 ($4D) 



MOTOROLA MICROPROCESSOR DATA 
3-242 



MC68701U4 



3 



INSTRUCTION SET 

The MC68701U4 is directly source compatible with the 
MG6801 and upward source and object code compatible 
with the MC6800. Execution times of key instructions have 
been reduced and several instructions have been added, in- 
cluding a hardware multiply. A list of new operations added 
to the MC6800 instruction set is shown in Table 1 . 

In addition, two special opcodes, 4E and 5E, are provided 
for test purposes. These opcodes force the program counter 



to increment like a 16-bit counter causing address lines used 
in the expanded modes to increment until the device is reset. 
These opcodes have no mnemonics. 

The coding of the first (or only) byte corresponding to an 
executable instruction is sufficient to identify the instruction 
and the addressing mode. The hexadecimal equivalents of 
the binary codes, which result from the translation of the 82 
instructions in all valid modes of addressing, are shown in 
Table 8. There are 220 valid machine codes, 34 unassighed 
codes, and 2 codes reserved for test purposes. 



TABLE 8 - CPU INSTRUCTION MAP 



OP 


MNEM 


MODE 




1 


OP 


MNEM 


MODE 




I 


OP 


MNEM 


MODE 


_ 


1 


OP 


MNEM 


MODE 


_ 




OP 


MNEM 


MODE 


_ 


* 


00 












34 


T^C 


INHER 








pn!~ 


INDXD 




—p 




'isr 


DIR 






DO 


SUBB 


DIR 


3 


2 


01 


NOP 


INHER 


2 


1 


35 




t 








69 




i 








qn 




! 












/ 


t 


| 




02 












36 


P^B 












DEC 










ac 












D2 


SBCB 








2 


03 
























BR 


* 














DIR 




2 


D3 


ADDD 






5 


2 










i* 






p V 






? 
















AO 


SUBA 


INDXD 




2 


D4 


ANDB 






3 


2 


05 


SI- 








■ 


TQ 


RTq 








1 




TST 








2 


Al 


CMPA 


> 


\ 


4 


2 


D5 


BITB 






3 


2 


06 


TAP 






2 


















IMP 




1 








SBCA 


















3 


2 


0/ 


TPA 






2 


1 


3B 


BT 






in 




RE 




INDXD 








SUBD 








2 


07 


STAB 






3 


2 


08 


INX 


















4 








EXTND 






A4 


ANDA 








2 


D8 


EORB 






3 


2 


09 


DEX 










3D 








in 








I 


\ 






A5 


BITA 








2 


D9 


ADCB 






3 


2 


OA 


CLV 






2 


1 


3E 
























A6 


LDAA 






■ ' 






ORAB 






3 


2 


0B 


SEV 






i? 












12 






COM 










A7 


STAA 








2 


D8 


ADDB 






3 


2 


OC 












40 


NFTA 










74 


LSR 










A8 


EORA 








2 


DC 


LDD 






4 


2 


0D 


SEC 








1 










. . 
















A9 


ADCA 








2 


DD 


STD 






4 


2 


0E 








\ 


1 


* 












76 


ROR 








3 


AA 


ORAA 








2- 


DE 


LDX 


' 


< 


'4 


2 




cc 




















1 


?7 


ASR 








3 


AB 


ADDA 






4 


2 


OF 


STX 


DIR 


4 


2 


10 


SBA 








1 


44 












78 


ASL 








3 


AC 








g 


2 


EO 


SUBB 


INDXD 


4 


2 


11 


CBA 






2 
















79 


ROL 








3 


AD 


JSR 






6 


2 


E! 


CMPB 


. t 




4 


2 


12 












4fi 


* PA 








1 


7A 


DEC 






g 




AE 


LDS 






5 


2 


E2 


SBCB 






4 


2 


13 






















1 














AF 


STS 


INDXD 


5 


2 


E3 


ADDD 








2 


14 












48 














INC 








3 






EXTND 


* 


3 


E4 


ANDB 






4 


2 


15 




































B1 


CMPA 


■ ) 


i 






E5 


BITB 






4 


2 




TAB 










4A 


DECA 








1 


? ° 


JMP 




' 


3 


3 


B2 


SBCA 






4-. 


. 3 


E6 


LDAB 






4 


2 


17 


TBA 






2 


1 


4B 


. 










7F 


CLR 


EXTND 


6 


3 


B3 


SUBD 






6 


3 


E7 


STAB 






4 


2 


18 




1 


t 






4C 


INCA 






2 


1 


80 


SUBA 


IMMED 


2 


2 


B4 


ANDA 






4 


3 


E8 


EORB 






4 


2 


19 


0AA 


INHER 


2 


1 


4D 


TSTA 






2 


1 


81 


CMPA 


, 




2 


2 


B5 


BITA 






4 


3 


E9 


ADCB 






4 


2 


1A 












4E 


T 










82 


SBCA 






2 


2 


B6 


LDAA 






4 


3 


EA 


ORAB 






4 


2 


1B 


ABA 


INHER 


2 


1 


4F 


CLRA 






2 


1 


83 


SUBD 






4 


3 


B7 


STAA 






4 


3 


EB 


ADDB 






4 


2 


1C 












50 


NEGB 






2 


1 


84 


ANDA 






2 


2 


B8 


EORA 






4 


3 


EC 


LDD 






5 


2 


1D 












51 












85 


BITA 






2 


2 


B9 


ADCA 






4 


3 


ED 


STD 






5 


2 


1E 












52 












86 


LDAA 






2 


2 


BA 


ORAA 






4 


3 


EE 


LDX 


\ 




5 


2 


IF 












53 


COMB 






2 


1 


87 












BB 


ADDA 






4 


3 


EF 


STX 


INDXD 


5 


2 


20 


BRA 


REL 


3 


2 


54 


LSRB 






2 


1 


88 


EORA 






2 


2 


BC 


CPX 






6 


3 


FO 


SUBB 


EXTND 


4 


3 


21 


BRN 


1 




3 


2 


55 












89 


AOCA 






2 


2 


BD 


JSR 






6 


3 


F1 


CMPB 


t 




4 


3 


22 


BHI 






3 


2 


56 


RORB 






2 . 


1 


8A 


ORAA 






2 


2 


BE 


LDS 


■ 1 




5 


3 


F2 


SBCB 






4 


3 


23 


BLS 






3. 


2 


57 


ASRB 






2 


1 


8B 


ADDA 


1 


' 


2 


2 


BF 


STS 


EXTND 


5 


3 


F3 


ADDD. 






6 


3 


24 


BCC 






3 


2 


58 


ASLB 






2 


1 


8C 


CPX 


IMMED 


4 


3 


CO 


SUBB 


IMMED 


2 


2 


F4 


ANDB 






4 


3 


25 


BCS 






3 


2 


59 


ROLB 






2 


1 


8D 


BSR 


REL 


6 


2 


CI 


CMPB 


i 




2 


2 


F5 


BITB 






4 


3 


26 


BNE 






3 


2 


5A 


DECB 






2 


1 


8E 


LDS 


MMED 


3 


3 


C2 


SBCB 






2 


2 


F6 


LDAB 








3 


27 


BEQ 






3 


2 


5B 












8F 












C3 


ADDD 






4 


3 


F7 


STAB 






4 


3 


28 


BVC 






3 


2 


5C 


INCB 






2 


1 


90 


SUBA 


DIR 




3 


2 


C4 


ANDB 






2 


2 


F8 


EORB 






. 4 


3 


29 


BVS 






3 


2 


5D 


TSTB 






2 


1 


91 


CMPA 


■i 


i 


3 


2 


C5 


BITB 






2 


2 


F9 


ADCB 






4 


3 


2A 


BPL 






3 


2 


5E 


T 




f 






92 


SBCA 






3 


2 


C6 


LDAB 






2 


2 


FA 


ORAB 






4 


3 


2B 


BMI 






3 


2 


5F 


CLRB 


INHER 


2 


1 


93 


SUBD 






5 


2 


C7 












FB 


ADDB 






4 


3 


2C 


BGE 






3 


2 


60 


NEG 


INDXD 


6 


2 


94 


ANDA 






3 


2 


C8 


EORB 






2- 


2 


FC 


LDD 






5 


3 


2D 


BLT 






3 


2 


61 




1 








95 


BITA 






3 


2 


C9 


ADCB 






2 


2 


FD 


STD 






5 


3 


2E 


BGT 




1 


3 


2 


62 












96 


LDAA 






3 


2 


CA 


ORAB 






2 


2 


FE 


LDX 


1 




5 


3 


2F 


BLE 


REL 


3 


2 


63 


COM 






6 


2 


97 


STAA 






3 


2 


CB 


ADDB 






2 


2 


FF 


STX 


EXTND 


5 


3 


30 


TSX 


INHER 


3 


1 


64 


LSR 






6 


2 


98 


EORA 






3 


2 


CC 


LDD 






3 


3 














31 


INS 






3 


1 


65 












99 


ADCA 






3 


2 


CD 




\ 


< 








* UNDEFINED OP CODE 




32 


PULA 


1 




4 


1 


66 


ROR 


\ 




6 


2 


9A 


ORAA 






3 


2 


CE 


LDX 


IMMED 


3 


3 














33 


PUL8 






4 


1 


67 


ASR 


INDXD 


6 


2 


9B 


ADDA 






3 


2 


CF 

























NOTES: 

1. Addressing Modes 

INHER m Inherent INDXD = lndexed IMMED -Immediate 
REL ■ Relative EXTND "Extended DIR- Direct 

2. Unassigned opcodes are indicated by "•" and should not be executed. 

3. Codes marked by "T" force the PC to function as a 16-bit counter. 



MOTOROLA MICROPROCESSOR DATA 
3-243 



MC68701U4 




PROGRAMMING MODEL 

A programming model for the MC68701U4 is shown in 
Figure 8. Accumulator A can be' concatenated with ac- 
cumulator B and jointly referred to as accumulator D where 
A is the most significant byte. Any operation which modifies 
the double accumulator will also modify accumulators A 
and/or B. Other registers are defined as follows: 

PROGRAM COUNTER - The program counter is a 16-bit 
register which always points to the next instruction. 

STACK POINTER - The stack pointer is a 16-bit register 
which contains the address of the next available location in a 
pushdown/ pullup (LIFO) queue. The stack resides in 
random-access memory at a location defined by the pro- 
grammer. 

INDEX REGISTER - The index register is a 16-bit register 
which can be used to store data or provide an address for the 
indexed mode of addressing. 

ACCUMULATORS - The MPU contains two 8-bit ac- 
cumulators, A and B, which are used to store operands and 
results from the arithmetic logic unit (ALU). They can also be 
concatenated and referred to as the D (double) accumulator. 

CONDITION CODE REGISTER - The condition code 
register indicates the results of an instruction and includes 
the following five condition bits: negative (N), zero (Z), 
overflow (V), carry/borrow from MSB (C), and half carry 
from bit 3 (H). These bits are testable by the conditional 
branch instructions. Bit 4 is the interrupt mask (I bit) and in- 
hibits all maskable interrupts when set. The two unused bits, 
B6 and B7, are read as ones. 

ADDRESSING MODES 

Six addressing modes can be used to reference memory. 
A summary of addressing modes for all instructions is 
presented in Tables 9, 10, 11, and 12 where execution times 
are provided in E cycles. Instruction execution times are 
summarized in Table 13. With an input frequency of 4 MHz, 
one E cycle is equivalent to. one microsecond. A cycle-by- 
cycle description of bus activity for each instruction is pro- 
vided in Table 14 and descriptions of selected instructions 
are shown in Figure 24. 

IMMEDIATE ADDRESSING - The operand or "im- 
mediate byte(s)" is contained in the following byte(s) of the 
instruction where the number of bytes matches the size of 
the register. These are two Or three byte instructions. 



DIRECT ADDRESSING - The least significant byte of the 
operand address is contained in the second byte of the in- 
struction and the most significant byte is assumed: to be $00. 
Direct addressing allows the user to access $00 through $FF 
using two byte instructions and execution time is reduced by 
eliminating the additional, memory access. In most applica- 
tions, the 256-byte area is reserved for frequently referenced 
data. 

EXTENDED ADDRESSING - The second and third bytes 
of the instruction contain the absolute address of the 
operand. These are three byte instructions. 

INDEXED ADDRESSING - The unsigned offset con- 
tained in the second byte of the instruction is added with 
carry to the index register and is used to reference memory 
without changing the index register. These are two byte in- 
structions. 

INHERENT ADDRESSING - The operand(s) is a register 
and no memory reference is required. These are single byte 
instructions. 

RELATIVE ADDRESSING - Relative addressing is used 
only for branch instructions. If the branch condition is true, 
the program counter is overwritten with the sum of a signed 
single byte displacement in the second byte of the instruc- 
tion and the current program counter. This provides a 
branch range of - 126 to + 129 bytes from the first byte of 
the instruction. These are two byte instructions. 



SUMMARY OF CYCLE-BY-CYCLE OPERATION 

Table 14 provides a detailed description of the information 
present on the address bus, data bus, and the read/write 
(R/W) line during each cycle of each instruction. 

The information is useful in comparing actual with ex- 
pected results during debug of both software and hardware 
as the program is executed. The information is categorized in 
groups according to addressing mode and number of cycles 
per instruction. In general, instructions with the same ad- 
dressing mode and number of cycles execute in the same 
manner. Exceptions are indicated in the table. 

Note that during MPU reads of internal locations, the 
resultant value will not appear on the external data bus ex- 
cept in mode 0. "High order" byte refers to the most signifi- 
cant byte of a 16-bit value. During unused bus cycles, the ad- 
dress bus is forced to $FFFF and R/W is high. 



MOTOROLA MICROPROCESSOR DATA 
3-244 



MC68701U4 



3 



TABLE 9 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS 



Pointer Operations 


MNEM 


Immed 


Direct 


Index 


Extend 


Inherent 


Boolean/ 
Arithmetic Operation 


Condition Codes 


5 




3 


2 




0 


An 

up 




D 


fin 
up 






Op 






fin 

up 










ff 




— 






— 




Compare Index Register 


CPX 






3 


9C 
























X-M:M+1 


— 


— 


T 


.... 
* 


♦ 




Decrement Index Register 


DEX 


























09 


3 


1 


X- 1 — X 






—. 






— 


Decrement Stack Pointer 


DES 


























34 


3 


1 


SP- 1 — »SP 














Increment Index Register 


INX 


























08 


3 


1 


X+1— X 


• 


• 


• 


i 


• 


• 


Increment Stack Pointer 


INS 


























31 


3 


1 


1 SP+1 -►sp 
















LDX 


CE 


3 


3 


DE 


4 


2 


EE 


5 


2 


FE 


5 


3 








M "— Xf-| (M + 1 ) — * Xl 


• 


• 


7 


! 


R 


• 


Load Stack Pointer 


LDS 


8E 


3 


3 


9E 


4 


2 


AE 


5 


2 


BE 


5 


3 








M — SP H ,(M+1) — SP L 








T 


R 






STX 








DF 


4 


2 


EF 


5 


2 


FF 


5 


3 








V. , — *• t\A Yi — HU i 11 

A |-| IVI , A |_ 11V1+ ]) 








t 


R 




Store Stack Pointer 


STS 








9F 


4 


2 


AF 


5 


2 


BF 


5 


3 








SP H - M,SP L - (M + 1) 








t 


R 




Index Reg— * Stack Pointer 


TXS 


























35 


3 


1 


X-1 — »SP 














Stack Pntr — Index Register 


TSX 


























30 


3 


1 


SP+1— X 














Add 


ABX 


























3A 


3 


1 


B + X— »X 














Push Data 


PSHX 


























3C 


4 


1 


X L — M s p,SP- 1 — "SP 
X H — M S p,SP- 1 — SP 














Pull Data 


PULX 


























38 


5 


1 


SP+1 — SP,M S p — X H 
SP+1 — SP,M SP — X L 















TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1of 2) 



Accumulator and 
Memory Operations 


MNEM 


Immed 


Direct 


Index 


Extend 


Inner 


Boolean 
Expression 


Condition Codes 


5 


4 


3 


2 


1 


0 


Op 






Op 




* 


Op 






Op 






Op 




# 


H 


1 


N 


Z 


V 


C 


Add Accumulators 


ABA 


























1B 


2 


1 


A+B — A 


t 






i 


i 




Add B to X 


ABX 


























3A 


3 


1 


00:B + X — X 














Add with Carry 


ADCA 


89 


2 


2 


99 


3 


2 


A9 


4 


2 


B9 


4 


3 








A+ M + C — A 


i 








i 




ADCB 


C9 


2 


2 


D9 


3 


2 


E9 


4 


2 


F9 


4 


3 








B + M + C— B 


t 








t 




Add 


ADDA 


8B 


2 


2 


9B 


3 


2 


AB 


4 


2 


BB 


4 


3 








A+M — A 


i 








t 




ADDB 


CB 


2 


2 


DB 


3 


2 


EB 


4 


2 


FB 


4 


3 








B + M — A 


t 












Add Double 


ADDD 


C3 


4 


3 


D3 


5 


2 


E3 


6 


2 


F3 


6 


3 








D+M:M+1 — □ 










t 




And 


ANDA 


84 


2 


2 


94 


3 


2 


A4 


4 


2 


B4 


4 


3 








A.M — A 










R 




ANDB 


C4 


2 


2 


D4 


3 


2 


E4 


4 


2 


F4 


4 


3 








B.M — B 










R 




Shift Left; Arithmetic 


ASL 














68 


6 


2 


78 


6 


3 


















J 




ASLA 


























48 


2 


1 


MHIIIIIIN -° 










i 




ASLB 


























58 


2 


1 


b7 bO 










i 




. Shift Left Double 


ASLD 


























05 


3 


1 












1 




Shift Right; Arithmetic 


ASR 














67 


6 


2 


77 


6 


3 


















t 




ASRA 


























47 


2 


1 


^IMIIIIhM 










t 




ASRB 


























57 


2 


1 


t>7 . . bO 










t 




Bit Test 


BITA 


85 


2 


2 


95 


3 


2 


A5 


4 


2 


B5 


4 


3 








A.M 










R 




BITB 


C5 


2 


2 


D5 


3 


2 


E5 


4 


2 


F5 


4 


3 








B.M 










R 




Compare Accumulators 


CBA 


























11 


2 


1 


A- B 










t 




Clear 


CLR 














6F 


6 


2 


7F 


6 


3 








00 — M 






Ft 


s 


R 


R 


CLRA 


























4F 


2 


1 


00 — A 






R 


s 


R 


R 


CLRB 


























5F 


2 


1 


00 — B 






R 


s 


R 


R 


Compare 


CMPA 


81 


2 


2 


91 


3 


2 


A1 


4 


2 


B1 


4 


3 








A- M 










} 


t 


CMPB 


C1 


2 


2 


D1 


3 


2 


E1 


4 


2 


F1 


4 


3 








B-M 










t 


t 


1's Complement 


COM 














63 


6 


2 


73 


6 


3. 








VI — M •■ 










R 


S 


COMA 


























43 


2 


1 


A — A 










R 


S 


COMB 


























53 


2 


1 


B — B 










R 


s 



MOTOROLA MICROPROCESSOR DATA 
3-245 



MC68701U4 



TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2. of 2) 



Accumulator and 




Immed 


Direct 


Index 


Extend 


Inher 


Boolean 
Expression 


Condition Codes 




4 


3 


2 






MNEM 


Op 






Op 






Op 






Op 






Op 








1 


N 




y 


c 


Decimal Adjust, A 


DAA 






— 






— 






— 






— 


Ji 






Adj binary sum to BCD 








( 


I 


J 


Decrement 


DEC 














6A 


6 


2 


7A 


6 


3 




— 


— 


M - 1 "" • M 






j 


J 


1 




DECA 


























4A 


2 


1 


A — 1 — * A 






♦ 


J 


j 




DECB 


























5A 


2 


1 


B - 1 ~ T * B 






t 


t 
♦ 


t 
♦ 




Exclusive OR 


EORA 


88 


2 


2 


98 


3 


2 


A8 


4 


2 


B8 


4 


3 








A® M — A 






{ 


♦ 






EORB 


C8 


2 




D8 


3 


2 


E8 


4 


2 


F8 


4 


3 








B © M — ► B 






i 


t 






Increment 


INC 














6C 


6 


2 


7C 


6 


3 








M+1— -M 






l 


J 


j 




INCA 


























4C 


2 


1 


A + 1 - * A 


• 


• 


i 


i 


t 






INCB 


























5C 


2 




B+1— B 






t 


t 


t 


• 


Load Accumulators 
Load Double 


LDAA 


86 


2 


2 


96 


3 


2 


A6 


4 


2 


B6 


4 


3 








M — A 






t 

* 


t 

♦ 






LDAB 


C6 


2 


2 


D6 


3 


2 


E6 


4 


2 


F6 


4 


3 








M T* B 


• 


• 


t 


t 


R 




LDD 


CC 


3 


3 


DC 


4 


2 


EC 


5 


2 


FC 


5 


3 








M:M+ 1 — ►D 


• 




t 


i 


R 




Logical Shift, Left 


LSL 














68 


6 


2 


78 


6 


3 








IsHIIIIIMI - 

b7 bO 






t 


t 


J 


t 


LSLA 


























48 


2 


1 


• 




t 


t 


t 


t 


LSLB 


























58 


2 


1 


• 


• 


i 


i 


I 


t 


LSLD 


























05 


3 


2 


• 




t 


i 


t 


t 


■ • 




/ 


;,\ 












- 


\A 

£k 
•'■ '. 




<" 

•■\ - 


i 

y " 

X 'i 




* 

- 






/ 

yy 













' ' "\ , ----- - . '- 



I" iff/ •* y',y»-^, , \y £ "- -. - j 



- - ' .: 

- ill 



> , .-V-- •.♦-•>- i .->; 

■ -■ .«;:%•.' v. i'..v. ' i , 
1 ,' - , 



MC68701U4 



TABLE 11 - JUMP AND BRANCH INSTRUCTIONS 



Operations 


MNEM 


Direct 


Relative 


Index 


Extend 


Inherent 


Branch Test 


Condition Code Reg. 


5 


4 


3 


2 


1 


0 


Op 


- 


» 


Op 


- 


# 


Op 


- 


* 


Op 


- 


# 


Op 


- 




H 


1 


N 


Z 


V 


C 


Branch Always 


BRA 








20 


3 


2 




















None 














Branch Never 


BRN 








21 


3 


2 




















None 














Branch If Carry Clear 


BCC 








24 


3 


2 




















C = 0 














Branch If Carry Set 


BCS 








25 


3 


2 




















C=1 














Branch If = Zero 


BEQ 








27 


3 


2 




















Z=1 














Branch If aZero 


BGE 








2C 


3 


2 




















N©V = 0 














Branch If >Zero 


BGT 








2E 


3 


2 




















Z+IN © V) = 0 














Branch If Higher 


BHI 








22 


3 


2 




















C + Z = 0 














Branch If Higher or Same 


BHS 








24 


3 


2 




















C = 0 














Branch If sZero 


BLE 








2F 


3 


2 




















Z+(N ffi V) = 1 














Branch If Carry Set 


BLO 








25 


3 


2 




















C=1 














Branch If Lower Or Same 


BLS 








23 


3 


2 




















C + Z=1 














Branch If <Zero 


BLT 








2D 


3 


2 




















N©V=1 














Branch If Minus 


BMI 








2B 


3 


2 




















N=1 














Branch If Not Equal Zero 


BNE 








26 


3 


2 




















Z = 0 














Branch If Overflow Clear 


BVC 








28 


3 


2 




















V = 0 














Branch If Overflow Set 


BVS 








29 


3 


2 




















V=1 














Branch If Plus 


BPL 








2A 


3 


2 




















N = 0 














Branch To Subroutine 


BSR 








8D 


6 


2 




















See Special Operations-Figure 24 














Jump 


JMP 














6E 


3 


2 


7E 


3 


3 




















Jump To Subroutine 


JSR 


9D 


5 


2 








AD 


6 


2 


BD 


6 


3 




















No Operation 


NOP 


























01 


2 


1 
















Return From Interrupt 


RTI 


























3B 


10 


1 


See Special Operations-Figure 24 


t 


t 


t 


i 


t 


t 


Return From Subroutine 


RTS 


























39 


5 


1 














Software Interrupt 


SWI 


























3F 


12 


1 




S 








• 


Wait For Interrupt 


WAI 


























3E 


9 


1 















TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS 













Condition Code Register 




Inherent 




5 


4 


3 


2 


1 


0 


Operations 


MNEM 


Op 




9 


Boolean Operation 


H 


1 


N 


Z 


V 


c 


Clear Carry 


CLC 


oc 


2 




0 — C 












R 


Clear Interrupt Mask 


CLI 


0E 


2 




0 — I 


• 


R 






• 


• 


Clear Overflow 


CLV 


OA 


2 




0 — V 




• . 






R 


• 


Set Carry 


SEC 


0D 


2 




1 — c 












S 


Set Interrupt Mask 


SEI 


OF 


2 




1 — 1 


• 


S 




• 


• 


• 


Set Overflow 


SEV 


OB 


2 




1 —V 










S 


• 


Accumulator A — ► CCR 


TAP 


06 


2 




A — CCR 


t 


t 


t 


t 


I 


t 


CCR — Accumulator A 


TPA 


07 


2 




CCR — A 















LEGEND CONDITION CODE SYMBOLS 



Op 


Operation Code (Hexadecimal) 


H 


Half-carry from bit 3 




Number of MPU Cycles 


I 


Interrupt mask 


Msp 


Contents of memory location pointed to by Stack Pointer 


N 


Negative (sign bit) 


# 


Number of Program Bytes 


Z 


Zero (byte) 


+ 


Arithmetic Plus 


V 


Overflow, 2's complement 




Arithmetic Minus 


c 


Carry/ Borrow from MSB 


• 


Boolean AND 


R 


Reset Always 


X 


Arithmetic Multiply 


S 


Set Always 


+ 


Boolean Inclusive OR 


I 


Affected 


e 


Boolean Exclusive OR 


• 


Not Affected 


M 


Complement of M 








Transfer Into 






0 


B it = Zero 






00 


Byte=Zero 







MOTOROLA MICROPROCESSOR DATA 
3-247 



MC68701U4 



TABLE 13 - INSTRUCTION EXECUTION TIMES IN E CYCLES 






ADDRESSING MODE 




Immediate 


Direct 


Extended 


Indexed 


Inherent 


Relative 


ABA 


• 




• 


• 


2 


• 


ABX 


• 


• 


• 


• 


3 


• 


ADC 




3 


4 


4 


• 


- • 


ADD 




3 


4 


4 


• 


• 


ADDD 


4 


5 




6 


■ • 


■. • 


AND 




3 


4 


4 


• 


• 


ASL 




• 




6 


2 


• 


ASLD 


• 


• 


• 


• 


3 


• 


ASR 


• 


• 




6 


2 


• 


BCC 


• 


• 


• 




• 


3 


BCS 


• 


• 


• 


• 


• 


3 


BEQ 


• 


• 


• 


• 


• 


3 


BGE 


• 


• 


• 


• 


• 


3 


BGT 


• 


• 


■ • 


• 


• 


3 


BHI 


• 


• 


• 


• 


... * 


3 


BHS 


• 


• 


• 


• 


• 


3 


BIT 






4 


4 


• 


• 


BLE 


• 


• 


• 


• 


• 


3 


BLO 


• 


• 


• 


• 


• 


3 


BLS 


• 


• 


• 


• 


• 


3 


BLT 


• 


• 


• 


• 




3 


BMI 


• 


• 


• 


• 


• 


3 


BNE 


• 


• 


• 


• 


• 


3 


BPL 


• 


• 


• 


• 


• 


3 


BRA 






• 


• 


• 


3 


BRN 


• 


• 


• 


• 


• 


3 


BSR 


• 


• 


• 


• 


• 


6 


BVC 








• 




3 


BVS 








• 




3 


CBA 








• 


2 




CLC 








• 


2 




CU 










2 




CLR 






6 


6 


2 




CLV 






• 


• 


2 




CMP 






4 


4 


• 




COM 






6 


6 


2 




CPX 






6 


6 


• 




DAA 






• 


• 


2 




DEC 






6 


6 


2 




DES 






• 


• 


3 




DEX 






• 


• 


3 




EOR 






4 


4 


• ' 




INC 






6 


6 


• 




INS 






• 


• 


3 





ADDRESSING MODE 





jdiate 




pepi 


s 


ent 


> 




lmm< 


Direc 


Extei 


lnde> 


Inhei 


Relat 


INX 


• 


• 


• 


• 


3 


• 


JMP 


- • 


• 


3 


3 


• 


• 


JSR 


• 




6 


6 


• 


• 


LDA 


2 




4 


4 


• 


• 


LDD 


3 


4 


5 


5 


• 


• 


LDS 


3 


4 


5 


5 


• 


• 


LDX ■ 


3 


4 


5 


5 


• 


• 


LSL 


.• 


• 


6 


6 


2 


• 


LSLD 


• 




• 


• 


3 


• 


LSR 


• 


• 


6 


6 


2 


• 


LSRD 




• 


• 


• 


3 


• 


MUL 


• 


• 


• 


• 


10 


• 


NEG 


■ • 




6 




2 


• 


NOP 


• 


• 


• 


• 


2 


• 


ORA 






4 


4 


• 


• 


PSH 


• 




• 


• 


3 


• 


PSHX 


• 


• 


• 


• 


4 


• 


PUL 


• 


• 


• 


• 


4 


• 




• 


• 


• 


• 


5 


• 


ROL 


• 


• 


6 




2 


• 


j? 0R 




• 


6 




2 


• 


RTI 


• 


• 


• 


• 


10 


• 


RTS 


• 


• 


; • 


• - 


5 


• 


SBA 


• 


• 


• 


• 


2 


• 


SBC 






4 


4 


• 


• 


SEC 






• 


J 


2 




SEI 


I 


• 


• 




2 




SEV 






• 




2 




STA 






4 


4 






STD 






5 


5 






STS 






5 


5 






STX 






5 


5 






SUB 






4 


4 






SUBD 






6 


6 






SWI 






• ■ 




12 




TAB 






• 




2 




TAP 






• 




2 




TBA 






• 




2 




TPA 






• 




2 




TST 






6 




2 




TSX 






• 




3 




TXS 






• 




3 




WAI 






• 




9 





MOTOROLA MICROPROCESSOR DATA 
3-248 



MC68701U4 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5) 



Address Mode and 
Instructions 


Cyclesi 


Cycle 
* 


Address Bus 


R/W 
Line 


Data Bus 


IMMEDIATE 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


2 


1 
2 


Opcode Address 
Opcode Address+ 1 


1 
1 


Opcode 
Operand Data 


LDS 
LDX 
LDD 


3 


1 

2 
3 


Opcode Address 
Opcode Address + 1 
Opcode Address +2 




Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


CPX 

SUBD 

ADDD 


4 


V 
2 
3 
4 


Opcode Address 
Opcode Address +1 
Opcode Address + 2 
Address Bus FFFF 




Opcode 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 
Low Byte of Restart Vector 


DIRECT 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


3 


1 

2 
3 


Opcode Address 
Opcode Address + 1 
Address of Operand 




Opcode 

Address of Operand 
Operand Data 


STA 


3 


1 
2 
3 


Opcode Address 
Opcode Address + 1 
Destination Address 




Opcode 

Destination Address 
Data from Accumulator 


LDS 
LDX 
LDD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address + 1 
Address of Operand 
Operand Address + 1 




Opcode 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 


STS 
STX 
STD 


4 


1 
2 
3 
4 


Opcode Address 
Opcode Address* 1 
Address of Operand 
Address of Operand + 1 




Opcode 

Address of Operand 

Register Data (High Order Byte) 

Register Data (Low Order Byte) 


CPX 

SUBD 

ADDD 


5 


1 
2 
3 
4 
5 


Opcode Address 
Opcode Address+1 
Operand Address 
Operand Address+1 
Address Bus FFFF 




Opcode 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 

Low Byte of Restart Vector 


JSR 


.5 


1 
2 
3 
4 
5 


Opcode Address 
Opcode Address+1 
Subroutine Address 
Stack Pointer 
Stack Pointer - 1 


0 
0 


Opcode 

Irrelevant Data 

First Subroutine Opcode 

Return Address (Low Order Byte) 

Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-249 



MC68701U4 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 


EXTENDED 


JMP 


3 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ T 


1 


Jump Address (High Order Byte) 






3 


Opcode Ad dress +2 


1 


Jump Address (Low Order Byte) 


ADC EOR 


4 


1 


Opcode Address 


1 


Opcode 


ADD LDA 




2 


Opcode Address+ 1 


1 


Address of Operand 


AND ORA 




3 


Opcode Address+2 


1 


Address of Operand (Low Order Byte) 


BIT SBC 




4 


Address of Operand 


1 


Operand Data 


CMP SUB 












STA 


4 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Destination Address (High Order Byte) 






.'3 


Opcode Address+2 


1 


Destination Address (Low Order Byte) 






4 


Operand Destination Address 




Data from Accumulator 


LDS 


5 


1 


Opcode Address 


1 


Opcode 


LDX 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


LDD 




""3 


Opcode Address+2 


1 


Address of Operand (Low Order Byte) 






4 


Address of Operand 


1 


Operand Data (High Order Byte) 






5 


Address of Operand + 1 


1 


Operand Data (Low Order Byte) 


STS 


5 


1 


Opcode Address 


1 


Opcode 


STX 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


STD 




3 


Opcode Address+2 


1 


Address of Operand (Low Order Byte) 






4 


Address of Operand 




Operand Data (High Order Byte) 






5 


Address of Operand + 1 




Operand Data (Low Order Byte) 


ASL LSR 


6 


1 


Opcode Address 


1 


Opcode 


ASR NEG 




2 


Opcode Address + 1 


1 


Address of Operand (High Order Byte) 


CLR ROL 




3 


Opcode Address+2 


1 


Address of Operand (Low Order Byte) 


COM ROR 




4 


Address of Operand 


1 


Current Operand Data 


DEC TST» 




5 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


INC 




6 


Address of Operand 




New Operand Data 


CPX 


6 


1 


Opcode Address 




Opcode 


SUBD 




2 


Opcode Address +,1 




Operand Address (High Order Byte) 


ADDD 




3 


Opcode Address+2 




Operand Address (Low Order Byte) 






4 


Operand Address 




Operand Data (High Order Byte) 






.5 


Operand Address + 1 




Operand Data (Low Order Byte) 






6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 


6 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Address of Subroutine (High Order Byte) 






3 


Opcode Address + 2 




Address of Subroutine (Low Order Byte) 






4 


Subroutine Starting Address 




Opcode of Next Instruction 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer- 1 


0 


Return Address (High Order Byte) 



*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus=$FFFF. 



MOTOROLA MICROPROCESSOR DATA 
3-250 



MC68701U4 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


tt 


Address Bus 


Line 


Data Bus 


INDEXED 


JMP 




1 


Opcods Address 




Opcode 






2 


Opcode Address + 1 




Offset 








Address Bus FFFF 




Low Byte of Restart Vector 


ADC EOR 


4 


1 


Opcode Address 


1 


Opcode 


ADD LDA 




2 


Opcode Address + 1 


1 


Offset 


Awn nRA 






AH/Hroec Riic FFFF 

MQuress Dub rrrr 




Low Byte of Restart Vector 


BIT cor 




4 


Index Register Plus Offset 




Operand Data 














STA 


4 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address+ 1 


] 


Offset 






3 


MUUlcoa duo rrrr 




Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data 


LDS 


5 


1 


Opcode Address 


1 


Opcode 


LDX 




2 


Opcode Address + 1 


1 


Offset 


LDD 




3 


Address Bus FFFF 


] - 


Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data (High Order Byte) 






5 


Index Register Plus Offsets 1 




Operand Data (Low — rder Byte) 


STS 


5 


1 


Opcode Address 


1 


Opcode 


STX 




2 


Opcode Address + 1 


1 


Offset 


STD 




3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Index Register Plus Offset 




Operand Data (High Order Byte) 






§ 


Index Register Plus Offset + 1 




Operand Data (Low Order Byte) 


ASL LSR 


6 


1 


Opcode Address 


1 


Opcode 


ASR NEG 




2 


Opcode Address + 1 


! 


Offset 


CLR ROL 




3 


Address Bus FFFK 


1 


Low Byte of Restart Vector 


COM ROR 




4 


Index Register Plus Offset 


1 


Current Operand Data 


DEC TST* 




5 


Address Bus FFFF 




Low Byte of Restart Vector 


INC 




g 


Index Register Plus Offset 


0 


New Operand Data 


CPX 


6 


1 


Opcode Address 




Opcode 


SUBD 




2 


Opcode Address+1 




Offset 


ADDD 




3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Index Register + Offset 




Operand Data (High Order Byte) 






5 


Index Register+ Offset + 1 




Operand Data (Low Order Byte) 






6 


Address Bus FFFF 




Low Byte of Restart Vector 


JSR 


6 


1 


Opcode Address 




Opcode 






2 


Opcode Address+1 




Offset 






3 


Address Bus FFFF 




Low Byte of Restart Vector 






4 


Index Register+ Offset 




First Subroutine Opcode 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer- 1 


0 


Return Address (High Order Byte) 



*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF. 



MOTOROLA MICROPROCESSOR DATA 
3-251 



MC68701U4 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5) 



Address Mode and 




Cycle 




R/W 




Instructions 


Cycles 


# 


Address Bus 


Line 


Data Bus 



INHERENT 



ABA 


DAA 


SEC 


ASL 


DEC 


SEI 


ASR 


INC 


SEV 


CBA 


LSR 


TAB 


CLC 


NEG 


TAP 


CLI 


NOP 


TBA 


CLR 


ROL 


TPA 


CLV 


ROR 


TST 


COM 


SBA 




ABX 



Opcode Address 
Opcode Address + 1 



Opcode 

Opcode of Next Instruction 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Irrelevant Data 

Low Byte of Restart Vector 



ASLD 
LSRD 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Irrelevant Data 

Low Byte of Restart Vector 



DES 
INS 



Opcode Address 

Opcode Address + 1 

Previous Stack Pointer Contents 



Opcode 

Opcode of Next Instruction 
Irrelevant Data 



INX 
DEX 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Opcode of Next Instruction 
Low Byte of Restart Vector 



PSHA 
PSHB 



Opcode Address 
Opcode Address + 1 
Stack Pointer 



Opcode 

Opcode of Next Instruction 
Accumulator Data 



Opcode Address 
Opcode Address + 1 
Stack Pointer 



Opcode 

Opcode of Next Instruction 
Irrelevant Data 



TXS 



Opcode Address 
Opcode Address + 1 
Address Bus FFFF 



Opcode 

Opcode of Next Instruction 
Low Byte of Restart Vector 



PULA 
PULB 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer+ 1 



Opcode 

Opcode of Next Instruction 

Irrelevant Data 

Operand Data from Stack 



PSHX 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer - 1 



Opcode 
Irrelevant Data 

Index Register (Low Order Byte) 
Index Register (High Order Byte) 



PULX 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer+1 
Stack Pointer+2 



Opcode 
Irrelevant Data 
Irrelevant Data 

Index Register (High Order Byte) 
Index Register (Low Order Byte) 



RTS 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer + 1 
Stack Pointer + 2 



Opcode 
Irrelevant Data 
Irrelevant Data 

Address of Next Instruction (High Order Byte) 
Address of Next Instruction (Low Order Byte) 



Opcode Address 
Opcode Address + 1 
Stack Pointer 
Stack Pointer - 1 
Stack Pointer- 2 
Stack Pointer- 3 
Stack Pointer-4 
Stack Pointer -5 
Stack Pointer -6 



Opcode 

Opcode of Next Instruction 
Return Address (Low Order Byte) 
Return Address (High Order Byte) 
Index Register (Low Order Byte) 
Index Register (High Order Byte) 
Contents of Accumulator A 
Contents of Accumulator B 
Contents of Condition Code Register 



MOTOROLA MICROPROCESSOR DATA 
3-252 



MC68701U4 



TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5) 



Address Mode and 




Cycle 




R/V\7 




Instructions 


Cycles 


* 


Address Bus 


Line 


Data Bus 


INHERENT (Continued) 


MUL 


10 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address +1 


1 


Irrelevant Data 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






5 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






6 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






7 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






8 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






9 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






10 


Address Bus FFFF 


1 


Low Byte of Restart Vector 


RTI 


10 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address +1 


1 


Irrelevant Data 






3 


Stack Pointer 


1 


Irrelevant Data 






4 


Stack Pointer+ 1 


1 


Contents of Condition Code Register from Stack 






5 


Stack Pointer + 2 


1 


Contents of Accumulator B from Stack 






6 


Stack Pointer + 3 


1 


Contents of Accumulator A from Stack 






7 


Stack Pointer + 4 


1 


Index Register from Stack (High Order Byte) 






8 


Stack Pointer + 5 


1 


Index Register from Stack (Low Order Byte) 






9 


Stack Pointer+6 


1 


Next Instruction Address from Stack (High Order Byte) 






10 


Stack Pointer +7 


1 


Next Instruction Address from Stack (Low Order Byte) 


SWI 


12 


1 


Opcode Address 




Opcode 






2 


Opcode Address + 1 




Irrelevant Data 






3 


Stack Pointer 


0 


Return Address (Low Order Byte) 






4 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






5 


Stack Pointer- 2 


0 


Index Register (Low Order Byte) 






6 


Stack Pointer- 3 


0 


Index Register (High Order Byte) 






7 


Stack Pointer -4 


0 


Contents of Accumulator A 






8 


Stack Pointer- 5 


0 


Contents of Accumulator B 






9 


Stack Pointer- 6 


0 


Contents of Condition Code Register 






10 


Stack Pointer- 7 


1 


Irrelevant Data 






11 


Vector Address FFFA (Hex) 


1 


Address of Subroutine (High Order Byte) 






12 


Vector Address FFFB (Hex) 


1 


Address of Subroutine (Low Order Byte) 


RELATIVE 


BCC BHT BNE BLO 


3 


1 


Opcode Address 


1 


Opcode 


BCS BLE BPL BHS 




2 


Opcode Address+ 1 


1 


Branch Offset 


BEQ BLS BRA BRN 




3 


Address Buss FFFF 


1 


Low Byte of Restart Vector 


BGE BLT BVC 












BGT BMI BVS 












BSR 


6 


1 


Opcode Address 


1 


Opcode 






2 


Opcode Address + 1 


1 


Branch Offset 






3 


Address Bus FFFF 


1 


Low Byte of Restart Vector 






4 


Subroutine Starting Address 


1 


Opcode of Next Instruction 






5 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-253 




FIGURE 24 - SPECIAL OPERATIONS 



JSR, Jump to Subroutine 



RTN 

BSR, Branch To Subroutine 
PC 

RTN 

RTS, Return from Subroutine 
PC 



Main Program 



$9D = JSR 



Next Main Instr. 



= Direct Address 
Main Program 



Next Main Instr. 



Main Program 



$BD=JSR 



SH=Subr. Addr. 



SL=Subr. Addr. 



Main Program 



S8D=BSR 



±K = Offset 



Next Main Instr. 



$39= RTS 



SP 
SP-2 
SP-1 

SP 



SP 
SP-2 
SP-1 

SP 

2E 
SP 
SP+1 
SP + 2 



SWI, Software Interrupt 



PC 
RTN 



WAI, Wait for Interrupt 



RTN H 



RTN L 



RTN 



RTI, Return from Interrupt 



PC 



RTN H 



RTN L 



JMP, Jump 



RTN H 



RTN L 



Legend: 

RTN = Address of next instruction in Main Program to be executed upon return from subroutine 
RTNh = Most significant byte of Return Address 
RTNl= Least significant byte of Return Address 
— » = Stack Pointer After Execution 
K = 8-bit Unsigned Value 



Main Program 



$3F=SWi 



Main Program 



$3E = WAI 



Interrupt Program 



$3B = RTI 



Main Program 



$6E = JMP 



X+K Next Instruction 



SP 


Stack 


SP-7 




SP-6 


Condition Code 


SP-5 


Acmltr B 


SP-4 


Acmltr A 


SP-3 


Index Register (Xh) 


SP-2 


Index Register (Xl) 


SP-1 


rtn h 


SP 


RTN|_ 


SP 


Stack 


SP 




SP + 1 


Condition Code 


SP + 2 


Acmltr B 


SP + 3 


Acmltr A 


SP + 4 


Index Register (Xh> 


SP + 5 


Index Register (XjJ 


SP + 6 


RTN H 


SP + 7 


rtn l 


PC 


Main Program ^ 




$7E = JMP 




Kh = Next Address 




K|_=Next Address 






K 


Next Instruction 



5 

o 

s 

o 

c 



MC68701U4 



ORDERING INFORMATION 



GENERIC INFORMATION 

(T A -0°to70 o C) 



Package Type 


Frequency 


Generic Number 


Cerdip — S Suffix 


1.0 MHz 
1.25 MHz 


MC68701U4S 
MC68701U4S-1 



PIN ASSIGNMENTS 



XTAL [ 
EXTAL [ 



RESET/Vpp[ 

vcct 

P20 
P21 
P22 [ 
P23 [ 
P24 
P10 
P11 [ 
P12 [ 
P13[ 
P14 [ 
P15[ 
P16 [ 
P17[ 



1 • 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18' 

19 

20 



40 ]E 
]SC1 
]SC2 
]P30 
]P31 
]P32 
]P33 
]P34 
]P35 
]P36 
]P37 
]P40 

]P41 

27 ]P42 

26 ]P43 

25 ]P44 

24 ] P45 

23 ] P46 

22]P47 

21 3 V CC 
__T Standby 



MOTOROLA MICROPROCESSOR DATA 
3-255 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 



MC6802 



Microprocessor With Clock 
and Optional RAM 

The MC6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators 
of the present MC6800 plus an internal clock oscillator and driver on the same chip. In addition, the 
MC6802 has 128 bytes of on-board RAM located at hex addresses $0000 to $007F. The first 32 bytes 
of RAM, at hex addresses $0000 to $001 F, may be retained in a low power mode by utilizing VrjC 
standby; thus, facilitating memory retention during a power-down situation. 

The MC6802 is completely software compatible with the MC6800 as well as the entire M6800 
family of parts. Hence, the MC6802 is expandable to 64K words. 

• On-Chip Clock Circuit 

• 128x8 Bit On-Chip RAM 

• 32 Bytes of RAM are Retainable 

• Software-Compatible with the MC6800 

• Expandable to 64K Words 

• Standard TTL-Compatible Inputs and Outputs 

• 8-Bit Word Si2e 

• 16-Bit Memory Addressing 

• Interrupt Capability 



TYPICAL MICROCOMPUTER 



v C c 
o 



Counter/ 
Timer I/O 



RESET 



Parallel 
I/O 



Control 



MC6846 
ROM, I/O, Timer 

CS0 

2 k Bytes ROM 
10 I/O Lines 
3 Lines Timer 

D0-D7 





VCC 






_ VMA 




^ Clock 


_ R/W 



CP2 
CP1 



A0-A10, 
CS1 



T 



VCC 

T 



c 



A0-A15 



VCC 

o 



IRQ 
MR 
VMA 

E 

R/W 



RESET 
HALT 
RE 



MC6802 NMI 
MPU 

D0-D7 

EXTAL 



BA 



A0-A15 



XTAL 



IF 



This block diagram shows a typical cost ef- 
fective microcomputer. The MPU is the 
center of the microcomputer system and is 
shown in a minimum system interfacing with 
a ROM combination chip. It is not intended 
that this system be limited to this function 
but that it be expandable with other parts in 
the M6800 Microcomputer family. 



This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-256 



MC6802 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


vcc 


-0.3 to +7.0 


V 


Input Voltage 




-0.3 to +7.0 


V 


Operating Temperature Range 
MC6802, MC680A02, MC680B02 
MC6802C, MC680A02C 


T A 


Oto +70 
-40 to +85 


°c 


Storage Temperature Range 


T stg 


-55 to +150 


°c 



This input contains circuitry to protect the 
inputs against damage due to high static volt- 
ages or electric fields; however, it is advised 
that normal precautions be taken to avoid 
application of any voltage higher than max- 
imum rated voltages to this high-impedance 
circuit. Reliability of operation is enhanced if 
unused inputs are tied to an appropriate logic 
voltage level (e.g., either Vss or Vcc)- 



THERMAL CHARACTERISTICS 



Characteristic 


Symbol 


Value 


Unit 


Average Thermal Resistance (Junction to Ambient) 
Plastic 


9JA 


100 


°C/W 



POWER CONSIDERATIONS 



The average chip-junction temperature, Tj, in °C can be obtained from: 

Tj = T A +(P D .6 JA ) 



where: 

t a 
0ja 
p D 
pint 
p port 



d) 



= Ambient Temperature, °C 

= Package Thermal Resistance, Junction-to-Ambient, °C/W 
= P| NT +Pp 0 RT 

= l cc x Vcc- Watts — Chip Internal Power 
= Port Power Dissipation, Watts — User Determined 

For most applications PpORT <p INT and can De ne 9'ected. PpORT may become significant if the device is configured 
to drive Darlington bases or sink LED loads. 
An approximate relationship between Pq and Tj (if PpoRT ' s neglected) is: 

Pd =k ^< t j +273 ° c ) (2) 

Solving equations (1) and (2) for K gives: 

K = P D • (T A + 273°C) + 6 j A'PD 2 (3) 
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pq (at 
equilibrium) for a known T A . Using this value of K, the values of Pp and Tj can be obtained by solving equations (1) 
and (2) iteratively for any value of T A . 




MOTOROLA MICROPROCESSOR DATA 
3-257 



MC6802 



DC ELECTRICAL CHARACTERISTICS (V DD = +5.0 Vdc±0.5%, Vss = 0, Ta = 0 to 70°C, unless otherwise noted) 



a 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


| nn „t Uink' V/nltaftA 1 amis. CVTAI 

input mgn voltage Logic, caial 

RESET 


V IH 


Vss + 2-0 
Vss + 4.0 





V CC 

vcc 


V 


Input Low Voltage Logic, EXTAL, RESET 


V|L 


V S S -0.3 





Vss + 0.8 


V 


Input Leakage Current (Vj n = 0 to 5.25 V, VQD = max) Logic 


"in 


- . 


1.0 


2.5 


(xA 


Output High Voltage 
('Load= -205 jiA, Vcc = min) D0-D7 
('Load^ -145jiA,Vcc = mih) A0-A15, RA/V, VMA, E 
('Load= -100 nA, Vcc = min) BA 


v OH 


Vss + 2.4 
Vss + 2.4 
V S S + 2^ 




- 





V 


Output Low Voltage dLoad = 16 mA < Vcc = min) 


V 0 I 






Vss + 0.4 


V 


Internal Power Dissipation (Measured at T/v=0°C) 


Pint 




0.750 


1.0 


w 


Vqd Standby Power Down 

Power Up 


vsbb 

VSB 


4.0 
4.75 




5.25 
5.25 


V 


Standby Current 


'SBB 






8.0 


mA 


Capacitance # D0-D7 
Win = 0, Ta = 25°C, f = 1 .0 MHz) Logic Inputs^EXTAL 

A0-A15, R/W, VMA 


C in 
C 0 ut 




10 
6.5 


12.5 
10 
12 


PF 



*ln power-down mode, maximum power dissipation is less than 42 mW. 
#Capacitances are periodically sampled rather than 100% tested. 



CONTROL TIMING (V C c = 5.0 V ±5%, V S s = 0, Ta=T|_ to Th>, unless otherwise noted) 



Characteristic 


Symbol 


MC6802 


MC68A02 


MC68B02 


Unit 


Min 


Max 


Min 


Max 


Min 


Max 


Frequency of Operation 


fo 


0.1 


1.0 


0.1 


1.5 


0.1 


2.0 


MHz 


Crystal Frequency 


fXTAL 


1.0 


4.0 


1.0 


6.0 


1.0 


8.0 


MHz 


External Oscillator Frequency 


4xf 0 


0.4 


4.0 


0.4 


6.0 


0.4 


8.0 


MHz 


Crystal Oscillator Start Up Time 


trc 


100 




100 




100 




ms 


Processor Controls (HALT, MR, RE, RESET, IRQ NMD' 
Processor Control Setup Time 
Processor Control Rise and Fall Time 
(Does Not Apply to RESET) 


tpcs 

tPCr- 
tPCf 


200 


100 


140 


100 


110 


100 


ns 



MOTOROLA MICROPROCESSOR DATA 
3-258 



MC6802 



BUS TIMING CHARACTERISTICS 



Ident. 
Number 


Characteristic 


Symbol 


MC6802 


MC68A02 


MC68B02 


Unit 


Min 


Max 


Min 


Max 






1 


Cycle Time 


tcyc 


1 0 


10 


0.667 


10 


0.5 


10 




2 


ruioc vviQin, c low 


" W EL 


450 


5000 


280 


5000 


210 


5000 


— ^ — 


o 
o 


Pnlco \A/iHth P Uinh 

ruise vviain, c nign 


P\A/r-i i 

""EH 


450 


9500 


280 


9700 


220 


9700 




4 


Clock Rise and Fall Time 


l r« tf 




25 




25 




25 


ns 


g 


Address Hold Time* 


*AH 


20 




20 




20 






12 


Non-Muxed Address Valid Time to E (see Note 4) 


*AV1 
*AV2 


160 


270 


100 




50 




ns 


17 


Read Data Setup Time 


*DSR 


100 




70 




60 




ns 


18 


Read Data Hold Time 


l DHR 


10 




10 




10 




ns 


19 


Write Data Delay Time 


tDDW 




225 




170 




160 


ns 


21 


Write Data Hold Time* 


tDHW 


30 




20 




20 




ns 


29 


Usable Access Time (see Note 4) 


*ACC 


535 




335 




235 




ns 



*Address and data hold times are periodically tested rather than 100% tested. 



FIGURE 2 - BUS TIMING 




NOTES: 

1. Voltage levels shown are V|_«0.4 V, Vn&2.4 V, unless otherwise specified. 

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted. 

3. Usable access time is computed by: 12 + 3 + 4-17. 

4. If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board 
RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs cannot be 
executed from on-board RAM when using A and B parts (MC68A02, MC68B02). On-board RAM can be used for data storage 
with all parts. 

5. All electrical and control characteristics are referenced from: Tl = 0°C minimum and Th = 70°C maximum. 



MOTOROLA MICROPROCESSOR DATA 
3-259 



MC6802 



FIGURE 3 - BUS TIMING TEST LOAD 



4.75 V 



C=130pF for D0-D7, E _ 

= 90 pF for A0-A15, R/W, and VMA 

= 30 pF for BA 
R = 117 "kn for D0-D7, E 

= 16.5 kl) for A0-A15, R/W, and VMA 

= 24 Ml for BA 



Test Point o- 



r, 
V 



R L = 2.2 kO 

MMD6150 
or Equiv. 



MMD7000 
or Equiv. 



FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY 
versus CAPACITIVE LOADING 



FIGURE 5 - TYPICAL READ/WRITE, VMA AND 
ADDRESS OUTPUT DELAY versus CAPACITIVE LOADING 



600 

500 

- 400 

I 300 
< 

S 200 

too 



! 1 ! 

- IrjH =-205 iiiA max @ 2. 

10 L = 1.6 mA max@ 0.4 
' VrjC'5.0 V 
. Ta = M'-r 


4 V 
















V 














































































































































































































































Cl i 


nclude 


stray 
i 


capaci 
i 


ance 



200 300 400 

Cl. LOAO CAPACITANCE (pE) 



1 1 ! 

_ |Q H = -145 uA max Is 1 2. 

IfJL = 1.6 mA max @> 0.4 
"V C C = 5.0V 

Ta = K'T. 


4V 
















V 




































































Add 


ress, V 


VIA 






































































R/W 
































































































Cl includes stray capacitance 



Cl.LOAD CAPACITANCE (pF) 



FIGURE 6 - EXPANDED BLOCK DIAGRAM 

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 



Memory Ready 
Enable 
RESET I 

Non-Maskable Interrupt (NMD • 
HALT • 

Interrupt Request (IRQ) ■ 
EXTAL • 
XTAL • 
Bus Available 
Valid Memory Address 
Read/Write (R/W) 



Vcc=Pin 8 
Vss = Pins 1, 21 



Output 
Buffers 



Clock 
Instruction 
Decode 

and 
Control 



Instruction 
Register 



Program 
Counter 



Stack 
Pointer 



Index 
Register H 



Data 
Buffer 



TTTTTTTT 

D7 D6 D5 D4 D3 D2 D1 DO 



Output 
Butters 



RAM 
Control 



32 Bytes 
96 Bytes 



Program 
Counter 



Stack 
Pointer l 



Index 
Register 



Accumulator 
A 



Accumulator 
B 



Condition 

Code 
Register 



ALU 



' Vcc Standby 



MOTOROLA MICROPROCESSOR DATA 
3-260 



MC6802 



MPU REGISTERS 



A general block diagram of the MC6802 is shown in 
Figure 1. As shown, the number and configuration of 
the registers are the same as for the MC6800. The 1 28 x 8- 
bit RAM* has been added to the basic MPU. The first 
32 bytes can be retained during powerup and power- 
down conditions via the RE signal. 

The MPU has three 16-bit registers and three 8-bit 
registers available for use by the programmer (Figure 7). 

PROGRAM COUNTER 

The program confer is a two byte (16-bit) register that 
points to the current program address. 

STACK POINTER 

The stack pointer is a two byte register that contains 
the address of the next available location in an external 
pushdown/pop-up stack. This stack is normally a ran- 
dom access read/write memory that may have any lo- 
cation (address) that is convenient. In those applications 
that require storage of information in the stack when 
power is lost, the stack must be non-volatile. 



INDEX REGISTER 

The index register is a two byte register that is used 
to store data or a 16-bit memory address for the indexed 
mode of memory addressing. 

ACCUMULATORS 

The MPU contains two 8-bit accumulators that are 
used to hold operands and results from an arithmetic 
logic unit (ALU). 

CONDITION CODE REGISTER 

The condition code register indicates the results of an 
Arithmetic Logic Unit operation: Negative (N), Zero (Z), 
Overflow (V), Carry from bit 7 (C), and Half Carry from 
bit 3 (H). These bits of the Condition Code Register are 
used as testable conditions for the conditional branch 
instructions. Bit 4 is the interrupt mask bit (I). The un- 
used bits of the Condition Code Register (b6 and b7) 
are ones. 

Figure 8 shows the order of saving the microproces- 
sor status within the stack. 



*lf programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, 
TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs cannot be executed 
from on-board RAM when using A and B parts (MC68A02 and MC68B02). On-board RAM can be used for data storage with all 
parts. 



FIGURE 7 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT 



Accumulator A 



Accumulator B 



Index Register 



Program Counter 



Stack Pointer 



Condition Codes 
Register 



L Carry (From Bit 7) 



Carry I 
Overflow 
Zero 



Negative 
Interrupt 
■ Half Carry (From Bit 3) 



MOTOROLA MICROPROCESSOR DATA 
3-261 



MC6802 



FIGURE 8 - SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK 



SP = Stack Pointer 

CC = Condition Codes (Also called the Processor Status Byte! 
ACC B = Accumulator B 
ACCA « Accumulator A 

IXH = Index Register. Higher Order 8 Bits 

I XL = Index Register, Lower Order 8 Bits 

PCH = Program Counter, Higher Order 8 Bits 

PCL = Program Counter, Lower Order 8 Bits 



m - 9 
m - 8 
m - 7 
m - 6 
m - 5 
m - 4 
m,r 3 
m - 2 
m - 1 
m 

m + 1 
m + 2 



MPU SIGNAL DESCRIPTION 



Proper operation of the MPU requires that certain control 
and timing signals be provided to accomplish specific func- 
tions and that other signal lines be monitored to determine 
the state of the processor. These control and timing signals 
are similar to those of the MC6800 except that TSC, DBE, 
01, <t>2 input, and two unused pins have been eliminated, 
and the following signal and timing lines have been added: 

RAM Enable (RE) 

Crystal Connections EXTAL and XTAL 
Memory Ready (MR) 
Vcc Standby 
Enable <t>2 Output (E) 

The following is a summary of the MPU signals: 

ADDRESS BUS (A0-A15) 

Sixteen pins are used for the address bus. The outputs are 
capable of driving one standard TTL load and 90 pF. These 
lines do not have three-state capability. 

DATA BUS (D0-D7) 

Eight pins are used for the data bus. It is bidirectional, 
transferring data to and from the memory and peripheral 
devices. It also has three-state output buffers capable of 
driving one standard TTL load and 130 pF. 

Data bus will be in the output mode when the internal 
RAM is accessed and RE will be high. This prohibits external 
data entering the MPU. It should be noted that the internal 
RAM is fully decoded from $0000 to $007F. External RAM at 
$0000 to $007F must be disabled when internal RAM is ac- 
cessed. 

HALT 

When this input is in the low state, all activity in the 
machi ne will be halted. This input is level sensitive. In the 
HALT mode, the machine will stop at the end of an instruc- 



tion, bus available will be at a high state, valid memory ad- 
dress will be at a low state. The address bus will display the 
address of the next instruction. 

T o ensu re single instruction operation, transition of 
the HALT li ne mu st occur tpcs before the rising edge 
o f E and the HALT line must go high for one clock cycle. 

HALT should be tied high if not used. This is good 
engineering design practice in general and necessary to en- 
sure proper operation of the part. 

READ/WRITE (R/W) 

This TTL-compatible output signals the peripherals and 
memory devices whether the MPU is in a read (high) or write 
(low) state. The normal standby state of this signal is read 
(high). When the processor is halted, it will be in the read 
state. This output is capable of driving one standard TTL 
load and 90 pF. 

VALID MEMORY ADDRESS (VMA) 

This output indicates to peripheral devices that there is a 
valid address on the address bus. In normal operation, this 
signal should be utilized for enabling peripheral interfaces 
such as the PI A and ACIA. This signal is not three-state. One 
standard TTL load and 90 pF may be directly driven by this 
active high signal. 

BUS AVAILABLE (BA) - The bus available signal will nor- 
mally be in the low state; when activated, it will go to the 
high state indicating that the microprocessor has stopped 
and that the address bus is avail able (b ut not in a three-state 
condition) . This will occur if the HALT line is in the low state 
or the processor is in the WAIT state as a result of the execu- 
tion of a WAIT instruction. At such time, all three-state out- 
put drivers will go to their off-state and other outputs to their 
normally inactive level. The processor is removed from the 



MOTOROLA MICROPROCESSOR DATA 
3-262 



MC6802 



WAIT state by the occurrence of a maskable (mask bit 1 = 0) 
or nonmaskable interrupt. This output is capable of driving 
one standard TTL load and 30 pF. 

INTERRUPT REQUEST (IRQ) 

A low level on this input requests that an interrupt se- 
quence be generated within the machine. The processor will 
wait until it completes the current instruction that is being 
excuted before it recognizes the request. At that time, if the 
interrupt mask bit in the condition code register is not set, 
the machine will begin an interrupt sequence. The index 
register, program counter, accumulators, and condition 
code register are stored away on the stack. Next the MPU 
will respond to the interrupt request by setting the interrupt 
mask bit high so that no further interrupts may occur. At the 
end of the cycle, a 16-bit vectoring address which is located 
in memory locations $FFF8 and $FFF9 is loaded which 
causes the M PU to branch to an interrupt routine in memory. 

The HALT line must be in the high state for interru pts to 
be serviced. Interrupts will be latched internally while HALT 
is low. 

A nominal 3 Ml pullup resistor to Vqc should be used for 
wire-OR and optimum control of interrupts. IRQ may be tied 
directly to Vqc if not used. 



RESET 

This input is used to reset and start the MPU from a 
power-down condition, resulting from a power failure or an 
initial start-up of the processor. When this line is low, the 
MPU is inactive and the information in the registers will be 
lost. If a high level is detected on the input, this will signal 
the MPU to begin the restart sequence. This will start execu- 



tion of a routine to initialize the processor from its reset con- 
dition. All the higher order address lines will be forced high. 
For the restart, the last two ($FFFE, $FFFF) locations in 
memory will be used to load the program that is addressed 
by the program counter. During the restart routine, the inter- 
rupt mask bit is set and must be reset before the MPU can be 
interrupted by IRQ.. Power-up and reset timing and power- 
d own seq uences are shown in Figures 9 and 10, respectively. 

RESET, when brought low, must be held low at least three 
clock cycles. This allows adequate time to respond internally 
to the reset. This is independent of the t rc power-up reset 
that is re quired. 

When RESET is released it must go through the low-to- 
high threshold without bouncing, oscillating, or otherwise 
causing an erroneous reset (less than three clock cycles). 
This may cause improper MPU operation until the next valid 
reset. 

NON-MASKABLE INTERRUPT (NMI) 

A low-going edge on this input requests that a non- 
maskable interrupt sequence be generated within the pro- 
cessor. As with the interrupt request signal, the processor 
will complete the curre nt in struction that is being executed 
before it recognizes the NMI signal. The inter rupt m ask bit in 
the condition code register has no effect on NMI. 

The index register, program counter, accumulators, and 
condition code registers are stored away on the stack. At the 
end of the cycle, a 16-bit vectoring address which is located 
in memory locations $FFFC and $FFFD is loaded causing the 
MPU to branch to an interrupt service routine in memory. 

A nominal 3 kQ pullup resistor to Vqc sh ould be used for 
wire-OR and optimum control of interrupts. NMI may be tied 




FIGURE 9 - POWER-UP AND RESET TIMING 



nj~Lru~ijTJ~LTLn 




V|H 



-'PCS 



Option 1 
(See Note Below) 



Option 2 
(See Figure 10 for 
Power-down Condition) 



RE 



tPCr 



tPCf 



NOTE: If option 1 is chosen, RESET and RE pins can be tied together. 



MOTOROLA MICROPROCESSOR DATA 

3-263 



MC6802 



directly to Vcc if not used. 

Inputs IRQ and NMI are hardware interrupt lines that are 
sampled when E is high and will start the interrupt routine on 
a low E following the completion of an instruction. 

Figure 11 is a flowchart describing the major decision 
paths and interrupt vectors of the microprocessor. Table 1 
gives the memory map for interrupt vectors. 

TABLE 1 - MEMORY MAP FOR 
INTERRUPT VECTORS 



Vector 


Description 


MS 


LS 


$FFFE 


$FFFF 


Restart 


$FFFC 


$FFFD 


Non-Maskable Interrupt 


$FFFA 


$FFFB 


Software Interrupt 


$FFF8 


$FFF9 


Interrupt Request 



v C c 



FIGURE 10 - POWER-DOWN SEQUENCE 

4.75 V 



tCPS- 



RE 



Vil\ 



tPCf 

V|H" \ k*_3 Cycles- 



FIGURE 11 - MPU FLOWCHART 

RESET) 



Yes 




Fetch Instruction 






Exec 
Instrt 


;ute 
ction 



1 






1 


1 


NMT 




"Fro: 


$FFFC 
$FFFD 


$FFF8 
$FFF9 


1 




1 





MOTOROLA MICROPROCESSOR DATA 
3-264 



MC6802 



FIGURE 12 - CRYSTAL SPECIFICATIONS 



38 
Cout 



±iOt± 

1 " 1 



Y1 


Cin 


C 0 ut 


3.58 MHz 


27 pF 


27 pF 


4 MHz 


27 pF 


27 pF 


6 MHz 


20 pF 


20 pF 


8 MHz 


18 pF 


18 pF 



Crystal Loading 



-VNAr- 

L1 



Mb 

Y1 

-k- 



C1 
CO 



-Wv 1 

Rs 



Nominal Crystal Parameters* 





3.58 MHz 


4.0 MHz 


6.0 MHz 


8.0 MHz 


Rs 


600 


500 


30-50 0 


20-4011 


CO 


3.5 pF 


6.5 pF 


4-6 pF 


4-6 pF 


C1 


0.015 pF 


0.025 pF 


0.01-0.02 pF 


0.01-0.02 pF 


Q 


>40K 


>30K 


>20K 


>20K 



"These are representative AT-cut parallel resonance crystal parameters only. 
Crystals of other types of cuts may also be used. 




Figure 13 - SUGGESTED PC BOARD LAYOUT 

Example of Board Design Using the Crystal Oscillator 
— 20 mm max- 




Other Signals are Not Wired in this Area 



E Signal is Wired Apart from 38 Pin 
and 39 Pin 



MOTOROLA MICROPROCESSOR DATA 
3-265 



MC6802 



FIGURE 14 - MEMORY READY SYNCHRONIZATION 



4xf 0 
Oscillator 



EXTAL 
XTAL 
MC6802 

MR 



39 



Memory Ready 
Generated from 
CS Logic 



SN74LS74 



FIGURE 15 - MR NEGATIVE SETUP TIME REQUIREMENT 
E Clock Stretch 



H«— »t -tpcs 

■0.8 V 



K — »j -tpcs 

-0.8 V 



The E clock will be stretched at end of E high of the cycle during which MR negative meets the tpcs setup time. The tpcs setup time is 
referenced to the fall of E. If the tpcs setup time is not met, E will be stretched at the end of the next E-high V4 cycle. E will be stretched in in- 
tegral multiples of V4 cycles. 



Resuming E Clocking 



Stretched E 



K H tpcs [ < > t tpcs [ < >j tpcs [ < > j tpcs 

! ! ~ | 1 f L 



MR 



The E clock will resume normal operation at the end of the % cycle during which MR assertion meets the tpcs setup time. The tpcs setup time 
is referenced to transitions of E were it not stretched. If tpcs setup time is not met, E will fall at the second possible transition time after MR is 
asserted. There is no direct means of determining when the tpcs references occur, unless the synchronizing circuit of Figure 14 is used. 



MOTOROLA MICROPROCESSOR DATA 
3-266 



MC6802 



RAM ENABLE (RE) 

A TTL-compatible RAM enable input controls the on- 
chip RAM of the MC6802. When placed in the high state, 
the on-chip memory is enabled to respond to the MPU 
controls. In the low state, RAM is disabled. This pin may 
also be utilized to disable reading and writing the on- 
chip RAM during a powerdown situation. RAM Enable 
must be low three cycles before Vcc 9 oes below 4.75 
V during powerdown. RE should be tied to the correct 
high or low state if not used. 

EXTAL AND XTAL 

These inputs are used for the internal oscillator that may 
be crystal controlled. These connections are for a parallel 
resonant fundamental crystal (see Figure 12). (AT-cut.) A 
divide-by-four circuit has been added so a 4 MHz crystal may 
be used in lieu of a 1 MHz crystal for a more cost-effective 
system. An example of the crystal circuit layout is shown in 
Figure 13. Pin 39 may be driven externally by a TTL input 
signal four times the required E clock frequency. Pin 38 is to 
be grounded. 

An RC network is not directly usable as a frequency 
source on pins 38 and 39. An RC network type TTL or CMOS 
oscillator will work well as long as the TTL or CMOS output 
drives the on-chip oscillator. 

LC networks are not recommended to be used in place of 
the crystal. 

If an external clock is used, it may not be halted for 
more than tpw<()L- The MC6802 is a dynamic part except 
for the internal RAM, and requires the external clock to 
retain information. 

MEMORY READY (MR) 

MR is a' TTL-compatible input signal controlling the stret- 
ching of E. Use of MR requires synchronization with the4xf 0 
signal, as shown in Figure 14. When MR is high, E will be in 
normal operation. When MR is low, E will be stretched in- 
tegral numbers of half periods, thus allowing interface to 
slow memories. Memory Ready timing is shown in Figure 15. 

MR should be tied high (connected directly to Vqc' if not 
used. This is necessary to ensure proper operation of the 
part. A maximum stretch is t cyc . 

ENABLE (E) 

This pin supplies the clock for the MPU and the rest of the 
system. This is a single-phase, TTL-compatible clock. This 
clock may be conditioned by a memory read signal. This is 
equivalent to <t>2 on the MC6800. This output is capable of 
driving one standard TTL load and 130 pF. 

Vcc STANDBY 

This pin supplies the dc voltage to the first 32 bytes 
of RAM as well as the RAM Enable (RE) control logic. 
Thus, retention of data in this portion of the RAM on a 
power-up, power-down, or standby condition is guar- 
anteed. Maximum current drain at Vsb maximum is 
'SBB- 



MPU INSTRUCTION SET 

The instruction set has 72 different instructions. Included 
are binary and decimal arithmetic, logical, shift, rotate, load, 
store, conditional or unconditional branch, interrupt and 
stack manipulation instructions (Tables 2 through 6). The in- 
struction set is the same as that for the MC6800. 



MPU ADDRESSING MODES 

There are seven address modes that can be used by a pro- 
grammer, with the addressing mode a function of both the 
type of instruction and the coding within the instruction. A 
summary of the addressing modes for a particular instruction 
can be found in Table 7 along with the associated instruction 
execution time that is given in machine cycles. With a bus 
frequency of 1 MHz, these times would be microseconds.. 

ACCUMULATOR (ACCX) ADDRESSING 

In accumulator only addressing, either accumulator A or 
accumulator B is specified. These are one-byte instructions: 

IMMEDIATE ADDRESSING 

In immediate addressing, the operand is contained in the 
second byte of the instruction except LDS and LDX which 
have the operand in the second and third bytes of the in- 
struction. The MPU addresses this location when it fetches 
the immediate instruction for execution. These are two- or 
three-byte instructions. 

DIRECT ADDRESSING 

In direct addressing, the address of the operand is contain- 
ed in the second byte of the instruction. Direct addressing 
allows the user to directly address the lowest 256 bytes in the 
machine, i.e., locations zero through 255. Enhanced execu- 
tion times are achieved by storing data in these locations. In 
most configurations, it should be a random-access memory. 
These are two-byte instructions. 

EXTENDED ADDRESSING 

In extended addressing, the address contained in the se- 
cond byte of the instruction is used as the higher eight bits of 
the address of the operand. The third byte of the instruction 
is used as the lower eight bits of the address for the operand. 
This is an absolute address in memory. These are three-byte 
instructions. 

INDEXED ADDRESSING 

In indexed addressing, the address contained in the se- 
cond byte of the instruction is added to the index register's 
lowest eight bits in the MPU. The carry is then added to the 
higher order eight bits of the index register. This result is 
then used to address memory. The modified address is held 
in a temporary address register so there is no change to the 
index register. These are two-byte instructions. 




MOTOROLA MICROPROCESSOR DATA 
3-267 



MC6802 



IMPLIED ADDRESSING 

In the implied addressing mode, the instruction gives the 
address (i.e., stack pointer, index register, etc.). These are 
one-byte instructions. 

RELATIVE ADDRESSING 

In relative addressing, the address contained in the second 



byte of the instruction is added to the program counter's 
lowest eight bits plus two. The carry or borrow is then added 
to the high eight bits. This allows the user to address data 
within a range of - 125 to + 129 bytes of the present instruc- 
tion. These are two-byte instructions. 



TABLE 2 - MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE 



ABA 


Add Accumulators 


CLR 


Clear 


ADC 


Add with Carry 


CLV 


Clear Overflow 


ADD 


Add 


CMP 


Compare 


AND 


Logical And 


COM 


Complement 


ASL 


Arithmetic Shift Left 


CPX 


Compare Index Register 


ASR 


Arithmetic Shift Right 


DAA 


Decimal Adjust 


BCC 


Branch if Carry Clear 


DEC 


Decrement 


BCS 


Branch if Carry Set 


DES 


Decrement Stack Pointer 


BEQ 


Branch if Equal to Zero 


DEX 


Decrement Index Register 


BGE 
BGT 


Branch if Greater or Equal Zero 
Branch if Greater than Zero 


EOR 


Exclusive OR 


BHI 


Branch if Higher 


INC 


Increment 


BIT 


Bit Test 


INS 


Increment Stack Pointer 


BLE 


Branch if Less or Equal 


INX 


Increment Index Register 


BLS 


Branch if Lower or Same 


JMP 


BLT 


Branch if Less than Zero 


Jump 


BMI 


Branch if Minus 


JSR 


Jump to Subroutine 


BNE 


Branch if Not Equal to Zero 


LDA 


Load Accumulator 


BPL 


Branch if Plus 


LDS 


Load Stack Pointer 


BRA 


Branch Always 


LDX 


Load Index Register 


BSR 


Branch to Subroutine 


LSR 


Logical Shift Right 


BVC 


Branch if Overflow Clear 


NEG 
NOP 


Negate 

No Operation 


BVS 


Branch if Overflow Set 


CBA 

CLC 


Compare Accumulators 
Clear Carry 


ORA 


Inclusive OR Accumulator 


CLI 


Clear Interrupt Mask 


PSH 


Push Data 



PUL Pull Data 

ROL Rotate Left 

ROR Rotate Right 

RTI Return from Interrupt 

RTS Return from Subroutine 

SBA Subtract Accumulators 

SBC Subtract with Carry 

SEC Set Carry 

SEI Set Interrupt Mask 

SEV Set Overflow 

STA Store Accumulator 

STS Store Stack Register 

STX Store Index Register 

SUB Subtract 

SWI Software Interrupt 

TAB Transfer Accumulators 

TAP Transfer Accumulators to Condition Code Reg. 

TBA Transfer Accumulators 

TPA Transfer Condition Code Reg. to Accumulator 

TST Test 

TSX Transfer Stack Pointer to Index Register 

TXS Transfer Index Register to Stack Pointer 

WAI Wait for Interrupt 



MOTOROLA MICROPROCESSOR DATA 
3-268 



MC6802 



TABLE 3 - ACCUMULATOR AND MEMORY INSTRUCTIONS 



ADDRESSING MODES 



BOOLEAN/ARITHMETIC OPERATION COND. CODE REG. 

(AM flfiltn laMl 
rtftf to contents) 



Add Acmltrs 
Add with Carry 



Bit Test 
Clear 



Compare Acmltrs 
Complement, l's 



Complement. 2's 
(Negate) 

Decimal Adiust, A 
Decrement . 

Exclusive OR 
Increment 

Load Acmltr 
Or. Inclusive 
Push Data 
Pull Data 
Rotate Left 

Rotate Right 

Shift Lett, Arithmetic 

Shift Right. Arithmetic 

Shift flight/Logic 

Store Acmltr 
Subtract 

Subtract Acmltrs. 
Subtr. with Carry 

Transfer Acmltrs 

Test, Zero or Minus 



ADDA 
AODB 
ABA 
ADCA 
ADCB 
ANOA 
ANDB 
BITA 
BITB 
CLR 
CLRA 
CLRB 
CMPA 
CMPB 
CBA 
COM 
COMA 
COMB 
NEG 
NEGA 
NEGB 
DAA 

DEC 
DECA 
DECB 
EORA 
EQRB 

INC 
INCA 
INCB 
LOAA 
LDAB 
ORAA 
ORAB 
PSHA 
PSHB 
PULA 
PULB 

ROL 
RO LA 
R0L6 

ROR 
RORA 
RORB 

ASL 
ASLA 
ASLB 

ASR 
ASRA 
ASRB 

LSR 
LSRA 
LSRB 
STAA 
STAB 
SUBA 
SUBB 

SBA 
SBCA 
SBCB 

TAB 

TBA 

TST 
TSTA 
TSTB 



82 4 
f2 4 



00 M ■ M 
00 - A - A 
00 - B • B 

Converts Binary Add. of BCD Characters 
into BCD Format 
M - 1 -M 
A 1 -A 

e - 1 - b 

A©M -A 
B©M - B 
M t t -- M 
A ♦ 1 - A ' 
B * 1 ■ B 
M - A 
M • B 
A + M - A 
B + M • B 

A -MSP, SP l-SP 
B -Msp.SP l-SP 
SP < 1 • SP, MSP • A 
SP* 1 -SP, M S p ■ B 




B J b7 bO 



n- -n - □ 

b7 bO C 



A ■ M 

B ■ M 

A M -A 

B - M • B 

A B -A 

A - M - C -A 

B - M - C • B 

A -B 

B -A 

M - 00 

A -00 

B - 00 



(D® 



s 3) « 
: ® • 

t 3 « 



i © < 
i © • 
t © • 



© i 

: ® I 



© l 
© 
© 
© 
: ® 1 



LEGEND: 

OP Operation Code (Hexadecimal): 

Number of MPU Cycles: 
- Number of Program Bytes, 
+ Arithmetic Plus; 

Arithmetic Minus: 

Boolean AND, 

Msp Contents of memory location pointed to be Stack Pointer; 



Boolean Inclusive OR; 
Boolean Exclusive OR. 
Complement of M; 
Transfer Into: 
Bit = Zero: 
Byte = Zero; 



Note - Accumulator addressing mode instructions are included in the column for IMPLIED addressing 



CONDITION CODE SYMBOLS: 

H Half-carry from bit 3; 

I Interrupt mask 

N Negative (sign bit) 

Z Zero (byte) 

V Overflow, 2's complement 

C Carry from bit 7 

R Reset Always 

S Set Always 

1 Test and set if true, cleared otherwise 

• Not Affected 



MOTOROLA MICROPROCESSOR DATA 

3-269 



MC6802 



3 



TABLE 4 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS 



COND. COOE REG. 



POINTER OPERATIONS 


MNEMONIC 


IMMEO 


OIRECT 


INDEX 


EXTNO 


IMPLIED 


BOOLEAN/ARITHMETIC OPERATION 


s 


4 


3 


2 


1 


0 


OP 






OP 






OP 






OP 






OP 






H 


1 


N 


Z 


V 


C 


Compare Index Keg 


CPX 


8C 


3 


3 


9C 


4 


2 


AC 


6 


2 


BC 


5 


3 








Xh - M. X L - (M + 1) 


• 


• 


© 




® 


• 


Decrement Index Reg 


DEX 


























09 


4 


1 


X - 1 -X 


• 


• 


• 


I 


• 


• 


Oecrement Stack Pntr 


DES 


























34 


4 


1 


SP 1 - SP 














Increment Index Reg 


INX 


























08 


4 


1 


X + 1 -X 


• 


• 


• 




• 


• 


Increment Stack Pntr 


INS 


























31 


4 


1 


SP + 1 * SP 














Load Index Reg 


LOX 


CE 


3 


3 


DE 


4 


2 


EE 


6 


2 


FE 


6 


3 








M - Xh. (M * 1) -X L 


• 


• 


© 


I 


R 


• 


Load Stack Pntr 


LDS 


8E 


3 


3 


9E 


4 


2 


AE 


6 


2 


BE 




3 








M -SPh.IMVI) -SPl 


• 


• 


® 




R 


• 


Store Index Reg 


STX 








DF 


5 


2 


EF 


7 


2 


FF 


6 


3 








X H -M. X L -IM ♦ 11 


• 


• 


© 




R 


• 


Store Stack Pntr 


STS 








9F 


5 


2 


AF 


7 


2 


BF 


6 


3 








SPh "M, SPl -IM + 11 


• 


• 


® 




R 


• 


.ndx Reg -Stack Pntr 


TXS 


























35 


4 


1 


X I • SP 














Slack Pntr • Indx Reg 


TSX 


























30 


4 




SP* 1 -X 















TABLE 5 - JUMP AND BRANCH INSTRUCTIONS 

COND. COOE REG. 







RELATIVE 


INOEX 


EXTNO 


IMPLIED 




5 


4 


3 


2 


1 


0 


OPERATIONS 


MNEMONIC 


OP 






OP 






OP 






OP 




■ BRANCH TEST 


H 


1 


N 


Z 


V 


c 


Branch Always 


BRA 


20 


4 


2 


















None 














Branch If Carry Clear 


BCC 


24 


4 


2 


















C = 0 














Branch If Carry Set 


6CS 


25 


4 


2 


















C= 1 














Branch If = Zero 


8EQ 


27 


4 


2 


















Z- 1 














Branch If > Zero 


BGE 


2C 


4 


2 


















N©V = 0 














Branch If >2ero 


BGT 


2E 


4 


2 


















Z + (N@V> = 0 














Branch If Higher 


BHI 


22 


4 


2 


















c + z = o 














Branch If < Zero 


8LE 


2F 


4 


2 


















Z + IN©V> = 1 














Branch If Lower Or Same 


BLS 


23 


4 


2 


















C + Z-1 














Branch If < Zero 


BLT 


2D 


4 


2 


















N © V = 1 














Branch If Minus 


BMI 


2B 


4 


2 


















N= 1 














Branch If Not Equal Zero 


BNE 


26 


4 


2 


















Z = 0 














Branch If Overflow Clear 


BVC 


28 


4 


2 


















V=0 














Branch If Overflow Set 


BVS 


29 


4 


2 


















V= 1 














Branch If Plus 


BPL 


2A 


4 


2 


















N = 0 














Branch To Subroutine 


BSR 


8D 


8 


2 
































Jump 


JMP 








6E 


4 


2 


7E 


3 


3 






> See Special Operations 














Jump To Subroutine 


JSR 








AD 


8 


2 


BD 


9 


3 






) (Figure 16) 














No Operation 


NOP 




















01 


2 


Advances Prog. Cntr. Only 














Return From Interrupt 


RTI 




















3B 


10 






- ® 


























Return From Subroutine 


RTS 




















39 


5 
















Software Interrupt 


SWI 




















3F 


12 


> See Special Operations 


• 




• 


• 


• 


• 


Wait for Interrupt 


WAI 




















3E 


9 


) (Figure 16) 


• 




• 


• 


• 


• 



MOTOROLA MICROPROCESSOR DATA 
3-270 



MC6802 



3 



FIGURE 16 - SPECIAL OPERATIONS 



SPECIAL OPERATIONS 
JSR. JUMP TO SUBROUTINE: 
PC Main Program 



INOXO 



n + 1 
n + 2 



PC 



n + 2 

n + 3 



AO ■ JSR 



K - Offaef 



■ 8-Bit Untigned Value 
Main Program 



SH * Subr. Addr. 



SL * Subr. Addr. 



BSR, BRANCH TO SUBROUTINE: 
PC Main Program 



n + 1 
n + 2 



Next Main Instr. 



le 



SP 


Stack 


EC 


Subroutine 


-► SP-2 




INX + K 


lit Subr. Inttr. 


SP-I 


|n + 2l H 






SP 


ln + 2l L 






In + 2) 


H and ln + 2) l f o' m "* 2 




SP 


Stack 


EC 
s 


Subroutine 


- SP-2 




1st Subr. Instr. 


SP-1 


In + 3] H 






SP 


In + 31 L 


(S Formed From Su and Si 1 


Stack Pointer After Execution. 






SP 


Stack 


P£ 


Subroutine 


- SP-2 




n + 2 ± K 


1st Subr. Instr. 


SP-1 


In + 21 H 






SP 


ln + 21 L 







*K = 7-Bit Signed Value; 



n + 2 Formed From In + 2l H and In * 2] L 



f PC 


Main Program 


££ 


Main Program 




6E = JMP 






7E = JMP 


. n+1 


K = Offset 






= Next Address 






EXTENDED ■ 


n + 2 


K L = Next Address 


X + K 


Next Instruction | 










K | Nexi Instruction 



RTS, RETURN FROM SUBROUTINE: 
PC Subroutine 



PC Main Program 



RTI, RETURN FROM INTERRUPT: 

p£ Interrupt Program 



Next Mam Instr 





SP. 


Stack 




SP 




SP 


+ 1 


Condition Code 


SP 


+ 2 


Acmltr B \ 


SP 


♦ 3 


Acmltr A 


SP 


♦ 4 


Index Register (Xh) 


SP 


+ 5 


Index Register (X l) 


SP 


+ e 


PCh 


SP 


+ 7 


PC L 



p C Mam Program 
Next Main Instr. 



TABLE 6 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS 



CONO. CODE REG. 



OPERATIONS 


MNEMONIC 


IMPLIED 




5 


4 


3 


2 


1 


0 


OP 






BOOLEAN OPERATION 


H 




N 


Z 


V 


C 


Clear Carry 


CLC 


oc 


2 




0 -c 












R 


Clear Interrupt Mask 


CLI 


OE 


2 




0 -1 


• 


R 


• 


• 


• 


• 


Clear Overflow 


CLV 


OA 


2 




0 -V 


• 


• 


• 


• 


R 


• 


Set Carry 


SEC 


OD 


2 




1 -c 












S 


Set Interrupt Mask 


SEI 


OF 


2 




1 -1 


• 


S 


• 


• 


• 


• 


Set Overflow 


SEV 


OB 


2 




1 -V 


• 


• 


• 


• 


S 


• 


Acmltr A - CCR 


TAP 


06 


2 




A -CCR 






-©- 






CCR - Acmltr A 


TPA 


07 


2 




CCR - A 












. — 



CONDITION CODE REGISTER NOTES: (Bit set it test is true and cleared otherwisel 



1 


(Bit VI 


Test: Result = 10000000' 


7 


(Bit N) 


Test: Sign bit of most significant (MS) byte - 1? 


2 


(Bit CI 


Test Result t 00000000' 


8 


(Bit V) 


Test: 2's complement overflow from subtraction of MS bytes' 


3 


(Bit CI 


Test: Decimal value of most significant BCD Character greater than nine? 


9 


(Bit Nl 


Test: Result less than zero' (Bit IS = 11 






(Not cleared if previously set 1 


10 


(All) 


Load Condition Code Register from Stack. (See Special Operations) 


4 


(Bit VI 


Test: Operand = 10000000 prior to execution' 


11 


(Bit 1) 


Set when interrupt occurs. If previously set, a Non Maskable 


5 


(Bit VI 


Test Operand = 01 111111 prior to execution? 






Interrupt is required to exit the wait state. 


6 


(Bit V) 


Test: Set equal to result of N©C after shift has occurred. 


12 


(All) 


Set according to the contents of Accumulator A. 



MOTOROLA MICROPROCESSOR DATA 
3-271 



MC6802 



TABLE 7 - INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECUTION TIMES 
(Times in Machine Cycle) 





(Dual Oper; 


ACCX 


Immediate 


Direct 


Extended 


Indexed 


Implied 


Relative 




(Dual Oper. 


ACCX 


Immediate 


Direct 


Extended 


Indexed 


Implied 


ABA 




• 


• 


• 


• 


• 


2 


• 


INC 




2 


• 


• 


6 


7 


• 


ADC 


X 


• 


2 


3 


4 


5 




• 


INS 




• 


• 


• 


• 


• 


4 


ADD 


X 


• 


2 


3 


4 


5 


• ■ 


• 


INX 




< 


• 


• 


• 


• 


4 


AND 


X 


• 


2 


3 


4 


5 


• 


• 


JMP 




• 


• 


• 


3 


4 


• 


ASL 






• 


• 


6 


7 


• 


• 


JSR 




• 


• 


• 


9 


8 


• 


ASR 






• 


• 


6 


7 


• 


• 


LDA 


X 


• 


2 


3 


4 


5 


• 


BCC 




• 


• 


• 


• 


• 


• 


4 


LDS 




• 


3 


4 


5 


6 


• 


BCS 




• 


• 


• 




• 


• 


4 


LDX 




• 


3 


4 


5 


6 


• 


BEA 




• 


• 


• 


• 


• 


• 


4 


LSR 






• 


• 


6 


7 


• 


BGE 




• 


• 


• 


• 




• 


4 


NEG 






• 


• 


6 


7 


• 


BGT 




• 


• 


• 


• 


• 


• 


4 


NOP 




• 


• 


• 


• 


• 


2 


BHI 




• 


• 


• 


• 


• 


• 


4 


ORA 


X 


• 






4 


5 


• 


BIT 


X 


• 










• 


• 


PSH 




• 


• 


• 


• 


• 


4 


BLE 




• 


• 


• 


• 


• 


• 


4 


PUL 




• 


• 


• 


• 


• 


4 


BLS 




• 


• 


• 


• 


• 


• 


4 


ROL 






• 


• 


6 


7 


• 


BLT 




• 


• 


• 


• 


• 


• 


4 


ROR 






• 


• 


6 


7 


• 


BMI 




• 


• 


• 


• 


• 


• 


4 


RTI 




• 


• 


• 


'• ' 


• 


10 


BNE 
















4 


RTS 










• 


• 


5 


BPL 
















4 


SBA 










• 


• 


2 


BRA 
















4 


SBC 


X 








4 


5 


• 


BSR 
















8 


SEC 










• 


• 


2 


BVC 
















4 


SEI 










• 


• 


2 


BVS 
















4 


SEV 










• 


• 


2 


CBA 














2 




STA 


X 






4 


5 


6 


• 


CLC 














2 




STS 








5 


6 


7 


• 


CD 














2 




STX 








5 


6 


7 


• 


CLR 










6 


7 


• 




SUB 


X 






3 


4 


5 


• 


CLV 










• 


#. 


2 




SWI 














12 


CMP 


X 








4 


5 


• 




TAB 














2 


COM 










6 


7 


• 




TAP 














2 


CPX 










5 


6 


• 




TBA 














2 


DAA 










• 


• 


2 




TPA 














2 


DEC 










6 


7 


• 




TST 














• 


DES 










• 


• 


4 




TSX 














4 


DEX 










• 


• 


4 




TSX 














4 


EOR 


X 




2 


3 


4 


5 


• 




WAI 














9 



NOTE I nterrupt time is 1 2 cycles from the end of 

the instruction being executed, except following 
a WA I instruction. Then it is 4 cycles 



MOTOROLA MICROPROCESSOR DATA 
3-272 



MC6802 



SUMMARY OF CYCLE-I 

Table 8 provides a detailed description of the information 
present on the address bus, data bus, valid memory address 
line (VMA), and the read/write line (R/W) during each cycle 
for each instruction. 

This information is useful in comparing actual with ex- 
pected results during debug of both software and hardware 



-CYCLE OPERATION 

as the control program is executed. The information is 
categorized in groups according to addressing modes and 
number of cycles per instruction. (In general, instructions 
with the same addressing mode and number of cycles ex- 
ecute in the same manner; exceptions are indicated in the 
table.) 



TABLE 8 - OPERATIONS SUMMARY 



Address Mode 
and Instructions 


Cycles 


Cycle 

M • 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 


IMMEDIATE 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


2 


1 

2 




Op Code Address 
Op Code Address + 1 




Op Code 
Operand Data 


CPX 
LDS 
LDX 


3 


1 

2 
3 




Op Code Address 
Op Code Address + 1 
Op Code Address + 2 




Op Code 

Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 



DIRECT 



ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


3 


1 

2 
3 




Op Code Address 
Op Code Address + 1 
Address of Operand 




Op Code 

Address of Operand 
Operand Data 


CPX 
LDS 
LDX 


4 


1 
2 
3 
4 




Op Code Address 
Op Code Address + 1 
Address of Operand 
Operand Address + 1 




Op Code 

Address of Operand 

Operand Data (High Order Byte) 

Operand Data (Low Order Byte) 


ST A 


4 


1 
2 
3 
4 




Op Code Address 
Op Code Address + 1 
Destination Address 
Destination Address 




Op Code 

Destination Address 
Irrelevant Data (Note 1 ) 
Data from Accumulator 


STS 
STX 


5 


1 
2 
3 
4 
5 




Op Code Address 
Op Code Address + 1 
Address of Operand 
Address of Operand 
Address of Operand + 1 


0 
0 


Op Code 

Address of Operand 
Irrelevant Data (Note 1) 
Register Data (High Order Byte) 
Register Data (Low Order Byte) 



JMP 


4 


1 
2 
3 
4 




Op Code Address 
Op Code Address + 1 
Index Register 

Index Register Plus Offset Wo Carry) 




Op Code 
Offset 

Irrelevant Data (Note 1 ) 
Irrelevant Data (Note 1 ) 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


5 


1 

2 
3 
4 
5 




Op Code Address 
Op Code Address + 1 
Index Register 

Index Register Plus Offset (w/o Carry) 
Index Register Plus Offset 




Op Code 
Offset 

Irrelevant Data (Note 1) 
Irrelevant Data (Note 1) 
Operand Data 


CPX 
LDS 
LDX 


6 


1 
2 
3 
4 
5 
6 




Op Code Address 
Op Code Address + 1 
Index Register 

Index Register Plus Offset (w/o Carry) 
Index Register Plus Offset 
Index Register Plus Offset + 1 




Op Code 
Offset 

Irrelevant Data (Note 1) 
Irrelevant Data (Note 1 ) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 



MOTOROLA MICROPROCESSOR DATA 
3-273 



MC6802 



TABLE 8 - OPERATIONS SUMMARY (CONTINUED) 



Address Mode 
and Instructions 


Cycles 


Cycle 

# 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 


INDEXED (Continued) 


STA 




1 

2 


1 

1 


Op Code Address 
Op Code Address + 1 


1 


Op Code 
Offset 




6 


3 


0 


Index Register 


; 


Irrelevant Data (Note 1) 




4 


0 


Index Register Plus Offset (w/o Carry) 




Irrelevant Data (Note 1) 






5 


0 


Index Register Plus Offset 




Irrelevant Data (Note 1) 






6 


1 


Index Register Plus Offset 




Operand Data 


ASL LSR 
ASR NEG 
CLR ROL 
COM ROR 


7 


1 
2 
3 


1 

1 

0 


Op Code Address 
Op Code Address + 1 
Index Register 


1 


Op Code 
Offset 

Irrelevant Data (Note 1 ) 


DEC TST 
INC 




4 


0 


Index Register Plus Offset (w/o Carry) 




Irrelevant Data (Note 1 ) 




5 


1 


Index Register Plus Offset 




Current Operand Data 






6 


0 


Index Register Plus Offset 


1 


Irrelevant Data (Note 1 ) 






7 


1/0 
(Note 
3) 


Index Register Plus Offset 




New Operand Data (Note 3) 


STS 




1 


1 


Op Code Address 


; 


Op Code 


STX 




2 


1 


Op Code Address +1 '* 




Offset 




7 


3 


0 


Index Register 


1 


Irrelevant Data (Note 1 ) 






4 


0 


Index Register Plus Offset (w/o Carry) 


■ 1 


Irrelevant Data (Note 1 ) 






5 


0 


Index Register Plus Offset 




Irrelevant Data (Note 1) 






6 


1 


Index Register Plus Offset 




Operand Data (High Order Byte) 






7 


1 


Index Register Plus Offset + 1 




Operand Data (Low Order Byte) 


JSR 




1 

2 


1 
1 


Op Code Address 
Op Code Address + 1 




Op Code 
Offset 






3 


0 


Index Register 




Irrelevant Data (Note 1) 




8 


4 

5 


1 
1 


■ Stack Pointer 
Stack Pointer - 1 




Return Address (Low Order Byte) 
Return Address (High Order Byte) 






6 


0 


Stack Pointer - 2 




Irrelevant Data (Note 1) 






7 


0 


Index Register 




Irrelevant Data (Note 1) 






8 


0 


Index Register Plus Offset (w/o Carry) 




Irrelevant Data (Note 1) 



EXTENDED 



JMP 


3 


1 
2 
3 




Op Code Address 
Op Code Address + 1 
Op Code Address + 2 




Op Code 

Jump Address (High Order Byte) 
Jump Address (Low Order Byte) 


ADC EOR 
ADD LDA 
AND ORA 
BIT SBC 
CMP SUB 


4 


1 
2 
3 
4 




Op Code Address 
Op Code Address + 1 
Op Code Address + 2 
Address of Operand 




Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Operand Data 


CPX 
LDS 
LDX 


5 


1 
2 
3 
4 
5 




Op Code Address 
Op Code Address +1 
Op Code Address + 2 
Address of Operand 
Address of Operand + 1 




Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Operand Data (High Order Byte) 
Operand Data (Low Order Byte) 


STA A 
STA B 


5 


1 
2 
3 
4 
5 




Op Code Address 
Op Code Address +1 
Op Code Address + 2 
Operand Destination Address 
Operand Destination Address 




Op Code 

Destination Address (High Order Byte) 
Destination Address (Low Order Byte) 
Irrelevant Data (Note 1 ) 
Data from Accumulator 


ASL LSR 
ASR NEG 
CLR ROL 
COM ROR 
DEC TST 
INC 


6 


1 
2 
3 
4 
5 
6 


1/0 
(Note 


Op Code Address 
Op Code Address + 1 
Op Code Address + 2 
Address of Operand 
Address of Operand 
Address of Operand 


0 


Op Code 

Address of Operand (High Order Byte) 
Address of Operand (Low Order Byte) 
Current Operand Data 
Irrelevant Data (Note 1 ) 
New Operand Data (Note 3) 



MOTOROLA MICROPROCESSOR DATA 
3-274 



MC6802 



TABLE 8 - OPERATIONS SUMMARY (CONTINUED) 



Address Mode 
and Instructions 


Cycles 


Cycle 

# 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 


EXTENDED (Continued) 


STS 




1 


1 


Op Code Address 


1 


Op Code 


STX 




2 


1 


Op Code Address + 1 


1 


Address of Operand (High Order Byte) 




6 


3 


1 


Op Code Address + 2 


1 


Address of Operand (Low Order Byte) 






4 


0 


Address of Operand 


1 


Irrelevant Data (Note 1 ) 






5 


1 


Address of Operand 


0 


Operand Data (High Order Byte) 






6 


1 


Address of Operand + 1 


0 


Operand Data ( Low Order Byte) 


JSR 




1 
2 
3 
4 


1 
1 

1 

1 


Op Code Address 
Op Code Address + 1 
Op Code Address + 2 
Subroutine Starting Address 


1 
1 
1 
1 


Op Code 

Address of Subroutine (High Order Byte) 
Address of Subroutine (Low Order Byte) 
Op Code of Next Instruction 




9 


5 


1 


Stack Pointer 


0 


Return Address (Low Order Byte) 






6 


1 


Stack Pointer - 1 


0 


Return Address (High Order Byte) 






7 


0 


Stack Pointer - 2 


1 


Irrelevant Data (Note 1 ) 






8 

9 


0 

1 


Op Code Address + 2 
Op Code Address + 2 


1 
1 


Irrelevant Data (Note 1 ) 

Address of Subroutine (Low Order Byte) 


INHERENT 


ABA DAA SEC 
ASL DEC SEI 
ASR INC SEV 


2 


1 

2 


1 
1 


Op Code Address 
Op Code Address + 1 


1 
1 


Op Code 

Op Code of Next Instruction 


CBA LSR TAB 
CLC NEG TAP 
CLI NOP TBA 
CLR ROL TPA 
CLV ROR TST 
COM SBA 














DES 




1 


1 


Op Code Address 




Op Code 


DEX 
INS 


4 


2 


1 


Op Code Address + 1 




Op Code of Next Instruction 


INX 




3 


0 


Previous Register Contents 




Irrelevant Data (Note 1) 






4 


0 


New Register Contents 




Irrelevant Data (Note 1) 


PSH 




1 


1 


Op Code Address 




Op Code 




4 


2 


1 


Op Code Address + 1 




Op Code of Next Instruction 






3 


1 


Stack Pointer 




Accumulator Data 






4 


0 


Stack Pointer — 1 




Accumulator Data 


PUL 




1 


1 


Op Code Address 




Op Code 




4 


2 


1 


Op Code Address + 1 




Op Code of Next Instruction 






3 
4 


0 

1 


Stack Pointer 
Stack Pointer + 1 




Irrelevant Data (Note 1) 
Operand Data from Stack 


TSX 




1 


1 


Op Code Address 




Op Code 




4 


2 


1 


Op Code Address + 1 




Op Code of Next Instruction 






3 


0 


Stack Pointer 




Irrelevant Data (Note 1) 






4 


0 


New Index Register 




Irrelevant Data (Note 1) 


TXS 




1 


1 


Op Code Address 




Op Code 




4 


2 


1 


Op Code Address + 1 




Op Code of Next Instruction 






3 


0 


Index Register 




Irrelevant Data 






4 


0 


New Stack Pointer 




Irrelevant Data 


RTS 




1 

2 


1 
1 


Op Code Address 
Op Code Address + 1 




Op Code 

Irrelevant Data (Note 2) 




5 


3 
4 

5 


0 

1 
1 


Stack Pointer 
Stack Pointer + 1 

Stack Pointer + 2 


1 


Irrelevant Data (Note 1) 

Address of Next Instruction (High 
Order Byte) 

Address of Next Instruction (Low 
Order Byte) 



MOTOROLA MICROPROCESSOR DATA 

3-275 



MC6802 



TABLE 8 - OPERATIONS SUMMARY (CONCLUDED) 



Address Mode 
and Instructions 


Cycles 


Cycle 

# 


VMA 
Line 


Address Bus 


R/W 
Line 


Data Bus 


INHERENT (Continued) 


WAI 




1 

2 




Op Code Address 
Op Code Address + 1 


1 

1 


Op Code 

Op Code of Next Instruction 






3 




Stack Pointer 


0 


Return Address (Low Order Byte) 






4 




Stack Pointer — 1 


0 


Return Address (High Order Byte) 




9 


5 




Stack Pointer - 2 


0 


Index Register (Low Order Byte) 






6 




Stack Pointer - 3 


0 


Index Register (High Order Byte) 






7 




Stack Pointer - 4 


0 


Contents of Accumulator A 






8 




Stack Pointer - 5 


0 


Contents of Accumulator 8 






9 




Stack Pointer - 6 




Contents of Cond. Code Register 


RTI 




1 

2 
3 
4 




Op Code Address 
Op Code Address + 1 
Stack Pointer 
Stack Pointer + 1 




Op Code 

Irrelevant Data (Note 2) 

Irrelevant Data (Note 1) 

Contents of Cond. Code Register from 
Stack 




10 


5 
6 

7 

8 
9 
10 


1 
1 


Stack Pointer + 2 
Stack Pointer + 3 
Stack Pointer + 4 

Stack Pointer + 5 

Stack Pointer + 6 

Stack Pointer + 7 


1 

1 

1 
1 


Contents of Accumulator B from Stack 

Contents of Accumulator A from Stack 

Index Register from Stack (High Order 
Byte) 

Index Register from Stack (Low Order 
Byte) 

Next Instruction Address from Stack 
(High Order Byte) 

Next Instruction Address from Stack 
(Low Order Byte) 


SWI 




1 
2 


; 


Op Code Address 
Op Code Address +1 


J 


Op Code 

Irrelevant Data (Note 1 ) 






3 




Stack Pointer 


0 


Return Address (Low Order Byte) 






4 




Stack Pointer - 1 


0 


Return Address (High Order Byte) 






5 




Stack Pointer - 2 


0 


Index Register (Low Order Byte) 




12 


6 




Stack Pointer - 3 


0 


Index Register (High Order Byte) 




7 




Stack Pointer - 4 


0: 


Contents of Accumulator A 






8 




Stack Pointer - 5 


0 


Contents of Accumulator B 






9 




Stack Pointer - 6 


0 


Contents of Cond. Code Register 






10 




Stack Pointer - 7 


1 


Irrelevant Data (Note 1) 






11 




Vector Address FFFA (Hex) 


1 


Address of Subroutine (High Order 
Byte) 






12 




Vector Address FFFB (Hex) 


1 


Address of Subroutine (Low Order 
Byte) 



RELATIVE 



BCC BHI BNE 

BCS BLE BPL 

BEQ BLS BRA 

BGE BLT BVC 

BGT BMI BVS 



1 




Op Code Address 


1 


Op Code 


2 




Op Code Address + 1 


1 


Branch Offset 


3 




Op Code Address + 2 


1 


Irrelevant Data (Note 1) 


4 




Branch Address 


1 


Irrelevant Data (Note 1) 


1 




Op Code Address 


1 


Op Code 


2 




Op Code Address + 1 


1 


Branch Offset 


3 




Return Address of Main Program 


1 


Irrelevant Data (Note 1) 


4 




Stack Pointer 


0 


Return Address (Low Order Byte) 


••'5. 




Stack Pointer - 1 


0 


Return Address (High Order Byte) 


6 


0 


Stack Pointer - 2 


1 


Irrelevant Data (Note 1) 


7 


0 


Return Address of Main Program 


1 


Irrelevant Data (Note 1) 


8 


0 


Subroutine Address (Note 4) 


1 


Irrelevant Data (Note 1) 



BSR 



NOTES: 

1. If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high-impedance three-state condition. 
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. 

2. Data is ignored by the MPU. 

3. For TST, VMA = 0 and Operand data does not change. 

4. MS Byte of Address Bus= MS Byte of Address of BSR instruction and LS Byte of Address Bus= LS Byte of Sub-Routine Address. 



MOTOROLA MICROPROCESSOR DATA 
3-276 



MC6802 



MECHANICAL DATA AND ORDERING INFORMATION 

ORDERING INFORMATION 



Package Type 


Frequency MHz 


Temperature 


Order Number 


Plastic 


1.0 


0°C to 70X 


MC6802P 


P Suffix 


1.0 


-40°C to + 85X 


MC6802CP 




1.5 


OX to 70X 


MC68A02P 




1.5 


-40Xto +85X 


MC68A02CP 




2.0 


OX to 70X 


MC68B02R 


Cerdip 


1.0 


OX to 70X 


MC6802S 


S Suffix 


1.0 


-40Xto +85X 


MC6802CS 




1.5 


OX to 70X 


MC68A02S 




1.5 


-40Xto +85X 


MC68A02CS 




2.0 


OX to 70X 


MC68B02S 



PIN ASSIGNMENT 



vss 


[ 


1. ^ 


40 


) RESET 


halt 


[ 


2 


39 


] EXTAL 


MR 


[ 


3 


38 


3' XTAL 


IRQ 


[ 


4 


37 


3 E 


VMA 


c 


5 


36 


3 RE 


NMI 


c 


6 


35 


3 Vcc Standby 


BA 


c 


7 


34 


3 R/W 


vcc 


[ 


8 


33 


3 DO 


AO 


[ 


9 


32 


3 D1 


A1 


c 


10 


31 


] D2 


A2 


t 


11 


30 


] D3 


A3 


t 


12 


29 


] D4 


A4 


c 


•13 


28 


] D5 


A5 


[ 


14 


27 


] D6 


A6 


[ 


15 


26 


] D7 


A7 


[ 


16 


25 


] A15 


A8 


[ 


17 


24 


] A14 


A9 


[ 


18 


23 


] A13 


A10 


t 


19 


22 


] A12 


A11 


I 


20 


21 


3 v ss 



MOTOROLA MICROPROCESSOR DATA 
3-277 



MOTOROLA 

SEMICONDUCTOR 

TECHNICAL DATA 



MC6804J1 



Technical Summary 

8-Bit Microcomputer Unit 



MC6804J1 HMOS (high-density NMOS) microcomputer unit (MCU) is a member of the M6804 
Family of serial processing microcomputers. This device displays all the versatility of an MCU 
whose design-ability to process 8-bit variables one bit at a time already makes it tremendously cost 
effective. 

This technical summary contains limited information on the MC6804J1. For detailed information, 
refer to the advanced information data sheet for the MC6804J1, MC6804J2, MC6804P2, and 
MC68704P2 8-bit microcomputers (MC6804J1/D) Or to the M6804 MCU Manual (DLE404/D). 

Major hardware and software features of the MC6804P2 MCU are: 




• On-Chip Clock Generator 

• Memory Mapped I/O 

• Software Programmable 8-Bit Timer with 
7-Bit Prescaler 

• Single Instruction Memory Examine/ 
Change 

• 30 Bytes of Data RAM 



• True Bit Manipulation 

• Bit Test and Branch Instruction 

• 304 Bytes Self-Check ROM 

• Conditional Branches 

• Timer Pin is Software Programmable as 
Clock Input or Timer Output 

• 504 Bytes of User Program Space ROM 



User Selectable Constant Current Pullup Devices available on LSTTL and Open-Drain Interface 
Ports 

Mask Selectable Edge- or Level-Sensitive Interrupt Pin 



TIMER 



PRESCALER 


8 BIT 
COUNTER 


TIMER/! 
CONTROL 


STATUS 
REGISTER 





PA4 






PORT 








A 


PORT 


DATA 


I/O 




A 


DIR. 


LINES 


PA6 


REG. 


REG. 











504x8 
USER PROGRAM ROM 



304x8 
SELF-CHECK ROM 



BLOCK DIAGRAM 

XTAL EXTAL RESIT MOS IRQ 



J__L 



OSCILLATOR 



ACCUMULATOR 



INDIRECT 




REGISTER 


X 


INDIRECT 




REGISTER 


Y 


STACK 


PROGRAM 




COUNTER 




HIGH 


PCH 



PROGRAM 
COUNTER 
LOW PCL 



J 



f f t 



CPU 
CONTROL 



CPU 





This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-278 



MC6804J1 



SIGNAL DESCRIPTION 

V C c AND Vss 

Power is supplied to the microcomputer using these 
two pins. Vqc is +5 volts (±0.5 V) power, and Vss is 
ground. 

IRQ 

This pin provides the capability for asynchronously ap- 
plying an external interrupt to the microcomputer. 

EXTAL ANDXTAL 

These pins provide control input for the on-chip clock 
oscillator circuit. A crystal, a resistor/capacitor combi- 
nation, or an external signal is connected to these pins 
to provide a system clock. Selection is made by a man- 
ufacturing mask option. The different clock generator op- 
tions are shown in Figure 1, along with crystal 
specifications. 

Internal Clock Options 

The crystal oscillator start-up time is a function of many 
variables. To ensure rapid oscillator start-up, neither the 
crystal characteristics nor load capacitances should ex- 
ceed recommendations. When using the on-board oscil- 
lat or, the M CU should remain m a reset condition, with 
the RESET pin voltage below Vires + » until tne oscillator 
has stabilized at its operating frequency. See Figure 2 for 
resistor/capacitor oscillator options. 



TIMER 

The TIMER pin can be configured to operate in either 
the input or output mode. As input, this pin is connected 
to the prescaler input and serves as the timer clock. As 
output, the timer pin reflects the contents of the DOUT 
bit of the timer status/control register, the last time the 
TMZ bit was logic high. 



RESET 



The RESET pin is used to restart the processor to the 
beginning of a program. The program counter is loaded 
with the address of the restart vector. This should be a 
jump instruction to the first instructio n of the main pro- 
gram. Together with the MDS pin, the RESET pin selects 
the operating mode of the MCU. 

MDS 

The mode select (MDS) pin places the MCU into special 
operating modes. When this pin is logic high at the exit 
of the reset state, the decoded state of PA6 and PA7 is 
latched to determine the operating mode. This choice can 
be either the single-chip, self-check, or EPROM program- 
ming. However, if MDS is logic low at the end of the reset 
state, the single-chip operating mode is automatically 
selected. No external diodes, switches, transistors, etc. 
are required for single-chip mode selection. 

INPUT/OUTPUT LINES (PA4-PA7, PB0-PB7) 

These 12 lines are arranged into one 4-bit port (A) and 
one 8-bit port (B). All lines are programmable as either 




NC 

EXTERNAL 

CLOCK 
INPUT 



EXTAL 

MCU 

XTAL (CRYSTAL MASK 
OPTIONI 



EXTERNAL CLOCK 



MCU 

IRESISTOR CAPACITOR MASK 
OPTION; 



I 'DENOTES NCIGND. GROUNDING 
PIN 4 WILL REDUCE RFI NOISE.i 

EXTERNAL RESISTOR CAPACITOR 



CRYSTAL PARAMETERS 




CRYSTAL PARAMETERS 
AT CUT PARALLEL RESONANCE CRYSTAL 
C 0 = 7 pF MAXIMUM 
FREQ. - 11 MHz 
R S = 50 OHMS MAXIMUM 

PIEZOELECTRIC CERAMIC RESONATORS MAY BE 
SUBSTITUTED FOR THE CRYSTAL. FOLLOW 
MANUFACTURER 3 CERAMIC . RESONATOR 
SPECIFICATIONS. . 



XTAl 

MCU 

EXTAL (CRYSTAL MASK 
OPTION! 



NOTE Keep crystal leads and circuit connections as short as possible. .< ■ 

Figure 1. Clock Generator Options and Crystal Parameters 



MOTOROLA MICROPROCESSOR DATA 
3-279 



MC6804J1 




6 8 10 12 14 
R L , LOAD RESISTANCE Ikfl) 

(a) TYPICAL FREQUENCY VS RESISTANCE 



8.0 

_ 78 
I 7.6 

C_J 

5 7.4 

=5 

a 

£ 7.2 



7.0 =r 



6.6, 















































— U 


s ,AO 








































7.5° C 






— „ J 


— * 







- « 






-85°C 





















































4.5 .4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 
V C c. SUPPLY VOLTAGE (V) 

Ibl TYPICAL FREQUENCY VARIATIONS @ C L = 15 pF, 10 ku 





9.8 




9.6 




9.4 


X 




>- 

C_> 


9.2 


z 




=3 
o 


9.0 


tr 






8.8 




8.6 




8.4 

























































































■-•-'or 




- - 



































































4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 
Vcc. SUPPLY VOLTAGE IV) 

(cl TYPICAL FREQUENCY VARIATIONS @ C L = 50 pF, 3 kR 

Figure 2. Typical Frequency Selection for 
Resistor/Capacitor Oscillator Options 



inputs or outputs under software control of the data di- 
rection registers. 



PROGRAMMING 

INPUT/OUTPUT PROGRAMMING 

There are 12 input/output pins. All pins of each port 
are programmable as inputs or outputs under the control 
of the data direction registers (DDR). 

The port I/O programming is accomplished by writing 
the corresponding bit in the port DDR to a logic one for 
output, or a logic zero for input, as shown in Figure 3. 
When the registers are programmed as outputs, the 
latched data is readable regardless of the logic levels at 
the output pin due to output loading. 

All the I/O pins are LSTTL compatible as both inputs 
and outputs. In addition, both ports may use either or 
both of two manufacturing mask options; open drain out- 
put, or internal pull-up resistor for CMOS compatibility. 

Any write to a port writes to all of its data bits even 
though the port DDR may be set to input. This can be 
used as a tool to initialize the data registers and avoid 



undefined outputs. However, care must be exercised when 
using read-modify-write instructions. The data read cor- 
responds to the pin level if the DDR is an input or to the 
latched output data when the DDR is an output. 

The 12 bidirectional lines may be configured by port 
to be the standard configuration (LSTTL), or either mask 
option; LSTTL/CMOS, or open drain. Port B outputs are 
LED compatible. 

Port Data Registers ($00, $01) 

The port data registers are not initialized on reset. These 
registers should be initialized before changing the DDR 
bits to avoid undefined levels. 

Port A ($00) 



7 


6 


5 


4 


3 


2 


1 


0 










X 


X 


X 


X 


7 


6 


5 


Port B ($01) 

4 3 


2 


1 


0 



















MOTOROLA MICROPROCESSOR DATA 
3-280 



MC6804J1 



DATA 

DIRECTION REGISTER 
BIT 



LATCHED 
OUTPUT 
DATA 
BIT 






DATA 








DIRECTION 


OUTPUT 




INPUT 


REGISTER 


DATA 


OUTPUT 


TO 


BIT 


BIT 


STATE 


MCU 


1 
1 


0 
1 


0 


0 
1 


0 


X 


1 

HI Z 


PIN 



I/O 
PIN 




*For CMOS option transistor acts as resistor (approximately 40 kQ) to Vqc- 
For LSTTL/open-drain options transistor acts as low current clamping diode to Vrjc- 

Figure 3. Typical I/O Port Circuitry 



With regard to Port A only, the four LSB bits are unused. 
These bits are "don't care" (X) bits When written to but 
are always logic high when read. 

Port Data Direction Registers ($04, $05) 



MEMORY 



The MCU memory map (Figure 4) consists of 4352 bytes 
of addressable memory, I/O register locations, and four 
















'it 




1 \ 












$ 8 ■ 










1 ill 
m til 



MC6804J1 



BYTES 
0000 




2783 
2784 



3087 
3088 



3583 
3584 



4087 
4088 
4089 
4090 

4091 
4092 
4093 
4094 
4095 



RESERVED 
12784 BYTES) 



SELF-CHECK ROM 
(304 BYTES) 



RESERVED 
(496 BYTES) 



PROGRAM ROM 
(504 BYTES) 



SELF-CHECK 
IRQ VECTOR 



SELF-CHECK 
RESTART VECTOR 



USER 

IRQ VECTOR 



USER 
RESTART VECTOR 



PROGRAM SPACE 



STACK SPACE 



LEVEL 



LEVEL 2 
LEVEL 3 



ADDRESS 



$000 



$ADF 
$AEO 



$C0F 
$C10 



$DFF 
$E00 



$FF7 
$FF8 
$FF9 
$FFA 
$FFB 
$FFC 
$FFD 
SFFE 
$FFF 



BYTES 

000 
001 
002 
003 
004 
005 
006 
008 
009 
010,. 

023 
024 



095 

096^ 
127 
128 
129 



130. 



159 
160 

252 
253 
254 
255 



PORT A DATA REGISTER 



PORT B DATA REGISTER 



RESERVED 
(2 BYTES) 



PORT A DDR 



PORT B DDR 



RESERVED 
(3 BYTES) 



TIMER STATUS CONT. REG. 



RESERVED 
(14 BYTES) 



USER DATA SPACE ROM 
(72 BYTES) 



RESERVED 
(32 BYTES) 



INDIRECT REGISTER X 



INDIRECT REGISTER Y 



'4, USER DATA SPACE RAM 



(30 BYTES) 
—7 

RESERVED 
(93 BYTES) 



PRESCALER REGISTER 



TIMER COUNT REGISTER 



ACCUMULATOR 



DATA SPACE 



ADDRESS 
$00 

$01 
$02 
$03 
$04 

$05 
$06 
$08 
$09 
$0A 
$17 
$18 



$5F 
J60 
$7F 
$80 

$81 
J 82 
"$9F 

$A0 

$FC 
$FD 

$FE 

$FF 



LEVEL 4 



Figure 4. Memory Map 



MOTOROLA MICROPROCESSOR DATA 
3-282 



MC6804J1 



REGISTERS 

ACCUMULATOR (A) 

The accumulator is a general purpose 8-bit register 
used to hold operands and results of arithmetic calcu- 
lations or data manipulations. 

7 0 



INDIRECT REGISTERS (X,Y) 

These two registers are used to maintain pointers to 
other memory locations in data space. They are used in 
the register-indirect addressing mode and can be ac- 
cessed with the direct, indirect, short direct, or bit set/ 
clear modes. 

.:. 7 ■ 0 



PROGRAM COUNTER (PC) 

The program counter is a 12-bit register that contains 
the address of the next byte to be fetched. The program 
counter is contained in low byte (PCL) and high nibble 
(PCH). 



8 7 



PCH 



PCL 



STACK 

A last-in-first-out (LIFO) stack is incorporated in the MCU 
that eliminates the need for a stack pointer. This non- 
accessible subroutine stack space is implemented in sep- 
arate RAM, 12 bits wide. Whenever a subroutine call or 
interrupt occurs, the contents of the PC are shifted into 
the top register of the stack. At the same time, the top 
register is shifted one level deeper. This happens to all 
registers, with the bottom register falling out of the stack. 

Whenever a return from subroutine or interrupt occurs, 
the top register is shifted into the PC and all lower reg- 
isters are shifted one level higher. The stack RAM is four 
levels deep. If the stack is pulled more than four times 
with no pushes, then the address that was stored in the 
bottom level of the stack is shifted into the PC. 



SELF CHECK 

The MCU implements two forms of internal check: self 
check and ROM verify. Self check performs an extensive 
functional check of the MCU using a signature analysis 
technique. ROM verify uses a similar method to check 
the contents of program ROM. 

Self-check mode is selected by holding the M PS and 
PA7 pins logic high and the PA6 pin logic low as RESET 
goes low to high. ROM verify mode is ente red by holding 
MDS, PA7, and PA6 logic high as RESET* goes low to 
high. Unimplemented program space ROM locations are 
also tested. Monitoring the self-check mode's stages for 
successful completion requires external circuitry, see 
M6804 MCU Manual (DLE404/D). 



RESET 



FLAGS (OZ) 

The first flag, the carry (C) bit, is set on a carry or borrow 
out of the arithmetic logic unit (ALU). It is cleared if the 
arithmetic operation does not result in a carry or borrow. 
The C bit is also set to the value of the bit tested in a bit 
test instruction. It participates in the rotate left (ROLA) 
instruction, as well. 

The second flag, the zero (Z) bit, is set if the result of 
the last arithmetic or logic operation was equal to zero. 
Otherwise, it is cleared. Bit test instructions do not affect 
the Z bit. 



NORMAL FLAGS : 








C 


Z 



INTERRUPT FLAGS 



There are two sets of these flags. One set is for interrupt 
processing (interrupt mode flags). The other set is for 
normal operations (program mode flags). When an in- 
terrupt occurs, a context switch is made from the pro- 
gram flags to the interrupt flags. An RTI forces the context 
switch back. While in either mode, only the flags for that 
mode are available. A context switch does not affect the 
value o f the C or Z bits. Both sets of flags are cleared by 
RESET. 



RESET 

All resets of the M C6804J1 are caused by the external 
res et input (RESET). A reset can be achieved by pulling 
the RESET pin to logic low for a minimum of 96 oscillator 
cycles. 

During reset, a de lay of 9 6 oscillator cycles is needed 
before allowin g the R ESET input to go high. If power is 
being applied, RESET must be held low long enough for 
the oscillator to stabilize and then provide the 96 c locks. 
Connecting a capacitor and resistor to the RESET input, 
as shown in Figure 5 below, typically provides sufficient 
delay. 



+ 5 V 



RESET 



4.7 k 



: 1.0 



MCU 



Figure 5. Powerup RESET Delay Circuit 



MOTOROLA MICROPROCESSOR DATA 
3-283 



MC6804J1 



INTERRUPT 

The MCU can be interrupted by applying a logic low 
signal to the IRQ pin. However, a manufacturing mask 
option determi nes w hether the falling edge or the actual 
low level of the IRQ pin is sensed to indicate an interrupt. 

EDGE-SENSITIVE OPTION 

When the IRQ pin is pulled low, the internal interrupt 
request latch is set. Prior to each instruction fetch, this 
interrupt request latch is tested. If its output is low, an 
interrupt sequence is initiated at the end of the current 
instruction, provided the interrupt mask is cleared. Figure 
6 contains a flowchart that illustrates both the reset and 
interrupt sequences. 

The interrupt sequence consists of one cycle during 
which: 

The interrupt request latch is cleared; 

The interrupt mode flags are selected; 

The program counter (PC) is saved on the stack; 

The interrupt mask is set; and 

The IRQ vector jump address is loaded into the PC. 

The IRQ vector jump address is $FFC-$FFD in the single- 
chip mode and $FF8-$FF9 in the self-check mode. The 
contents of these locations are not decoded as an address 
to which the PC should jump. Instead, they are decoded 
like any other EPROM program word. So, it is essential 



that the vector contents specify a JMP instruction in ad- 
dition to the starting address of the interrupt service rou- 
tine. If required, this routine should save the values of 
the accumulator and the X and Y registers, since these 
values are not stored on the stack. 

Internal processing of the interrupt continues until a 
return from interrupt (RTI) instruction is processed. Dur- 
ing RTI the interrupt mask is cleared and the program 
mode flags are selected. The next instruction of the pro- 
gram is then fetched and executed. 

When the interrupt was initially detected and the in- 
terrupt sequence started, the interrupt request latch was 
cleared so that the next interrupt could be detected. These 
steps occurred even as the first interrupt was being serv- 
iced. However, even though the second interrupt edge 
set the interrupt request latch during the first interrupt's 
processing, the second interrupt's sequence can not be- 
gin until completion of the interrupt service routine for 
the first interrupt. Completion of an interrupt service rou- 
tine is always accomplished using an RTI instruction to 
return to the main program. The interrupt mask, which 
is not directly available to the programmer, is cleared 
during the last cycle of the RTI instruction. 

LEVEL-SENSITIVE OPTION 

Actual operation of the level-sensitive and edge-sen- 
sitive options are similar. However, the level-sensitive 
option does not have an interrupt request latch. Since 
ther e is no interrupt request latch, the logic level of the 
IRQ pin is checked to detect the interrupt. Also, in the 
interrupt sequence there is no need to clear the interrupt 
request latch. These differences are shown in Figure 6. 




MOTOROLA MICROPROCESSOR DATA 
3-284 



MC6804J1 



POWERUP AND TIMING 

During the powerup sequence, the interrupt mask is 
closed. This precludes any false interrupts. The PC is also 
loaded with the appropriate restart vector (jump instruc- 
tion). 

To open the interrupt mask, the user should do a JSR 
to an initialization subroutine that ends with an RTI in- 
stea d of an RTS. The RTI opens the interrupt mask. Typ- 
ical RESET and IRQ processes and their relationship to 
the interrupt mask are shown in Figure 7. 

Maximum interrupt response time is six machine cycles. 
This includes five cycles for the longest instruction plus 
one for stacking the PC and switching flags. 



TIMER 

A block diagram of the MC6804J1 timer circuitry is 
shown in Figure 8. The timer logic in the MCU is com- 
prised of a simple 8-bit counter called the timer counter. 
This counter is decremented by a 7-bit prescaler at a rate 
determined by the timer status/control register (TSCR). 

PRESCALER 

The prescaler is a 7-bit counter used to extend the max- 
imum interval of the overall timer. This counter is clocked 
by a signal from the TIMER pin or by the internal sync 
pulse. It divides the frequency received by some factor 



JMP-START 
VECTOR (FFE-FFF) 



START (ROUTINE) 
INSTRUCTION (l-N) 






LAST INST 
JSR 


"RUCTION 
INIT 



PROGRAM 



IRQ 
RECOGNIZED 



IRQ 
SERVICE 
ROUTINE 



PROGRAM 



LAST INSTRUCTION 
RTI 



\ 



INTERRUPT 
y MASK 
CLOSED 




INIT 
INITIALIZATION 
SUBROUTINE 



LAST INSTRUCTION 
RTI 



MASK 
OPEN 



INTERRUPT 
MASK 
CLOSED 



MASK 
OPEN 



Figure 7. Interrupt Mask 



MOTOROLA MICROPROCESSOR DATA 
3-285 



— •■ 




READ 



WRITE 



READ 



WRITE 



MICROCOMPUTER INTERNAL BUS 
READ 



WRITE 



TIMER PIN STATUS 



TOUT 


PRESCALER 
CLOCK 


TIMER 
PIN 


0 
1 


TIMER PIN 
SYNC 


INPUT MODE 
OUTPUT MODE 



/ 8 



PRESCALER 


SELECT 




8-BIT COUNTER 




1 OF 8 


*" 


TIMER COUNT REGISTER 


INITIALIZE 




(TCR) 



b3 



TIMER STATUS/CONTROL 
REGISTER (TSCR) 



TMZ 



NOT 
USED 



TOUT DOUT 



PSI 



PS 2 



V CLK 



TRANSPARENT 
LATCH 



PS1 



bO 



PSO 



) ) ) 



Figure 8. Timer Block Diagram 



MC6804J1 



to create the prescaler output. The factor by which the 
TIMER pin signal is divided is called the prescaler tap. 
The value of this tap is selected by three bits of the TSCR 
(PS0-PS2). These bits control the division of the prescaler 
input within the range of divide-by-2°, to divide-by-2 7 . 

TIMER COUNTER 

The timer counter, which may be read or loaded under 
program control, is decremented from a maximum value 
of 256 toward zero by the prescaler output. Both are dec- 
remented on rising clock edges. 

The prescaler register and timer count register are 
readable and writeable. A write to either one will take 
precedence over the normal counter function. For ex- 
ample, if a value is written to the timer count register, 
and this write and a decrement-to-zero occur at the same 
time, the write takes precedence. TSCR bit one (TMZ) is 
not set until the next timer time out. 

TIMER PIN 

The TIMER pin may be programmed as either an input 
or an output. Its status depends on the value of TSCR bit 
5 (TOUT). This relationship is shown in the TIMER pin 
status section of Figure 8. The frequency of the internal 
clock applied to the TIMER pin must be less than tbyte- 
which is (fosc^S). 

TIMER INPUT MODE 

In the timer input mode, TOUT is logic zero and the 
TIMER pin is connected directly to prescaler input. So, 
the prescaler is clocked by the signal from the TIMER pin. 
The prescaler divides the TIMER pin clock input by the 
prescaler tap. The prescaler output then clocks the 8-bit 
timer count register. When this register is decremented 
to zero, it sets TSCR bit one (TMZ). This TMZ bit can be 
tested under program control. 

TIMER OUTPUT MODE 

In the output mode, the TIMER pin is output. TOUT is 
a logic one. The prescaler is clocked by the internal sync 
pulse. This pulse is a divide-by-48 of the internal oscillator 
(fosc/48). From this point on, operation is similar to that 
described for the input mode. However, in the output 
mode, once the prescaler decrements the timer counter 
to zero, the high TMZ bit state is used to latch the data 
at TSCR bit 4 (DOUT), onto the TIMER pin. 

NOTE 

TMZ is normally set to logic one when TCR dec- 
rements to zero and the timer times out. However, 
it may be set by a write of $00 to the timer counter 
or by a write to bit 7 of TSCR. 

TIMER COUNT REGISTER ($FE) 

The timer count register reflects the current count in 
the internal 8-bit counter. The register is the timercounter 
and can be read or written. 



7 , . ■ ___ 0 

MSB LSB 

RESET: 

1 1 1 1 1 11 1 



TIMER STATUS/CONTROL REGISTER (TSCR) ($09) 



7 


6 


5 


4 


3 


2 


1 


0 


TMZ 




TOUT 


DOUT 


PSI 


PS2 


PS1 


PSO 


RESET: 
0 


0 


0 


0 


0 


0 


0 


0 



TMZ — Timer Zero 

1 = Timer count register has decremented to zero 
since the last time the TMZ bit was read. 

0 = This bit is cleared by a read of the TSCR if TMZ 

is read as logic one. 

Bit 6 

Not used by this register. 

TOUT — Timer Output 

1 = Output mode is selected for the timer. 
0= Input mode is selected for the timer. 

DOUT — Data Output 

Latched data at this bit is sent to the TIMER pin when 
both the TMZ and TOUT bits are logic high. 

PSI — Prescaler Initialization 

1 = Prescaler begins to decrement. 

0 = Prescaler is initialized and counting is inhibited. 

PS0-PS2 

These bits are used to select the prescaler tap, The 
coding of the bits is shown below: 



PS2 


PS1 


PSO 


Divide By 


0 


0 


0 


1 


0 


0 


1 


2 


0 


1 


0 


4 


Q 


1 


1 


8 


1 


0 


0 


16 


1 


0 


1 


32 


1 


1 


0 


64 


1 


1 


1 


128 



It is recommended that MVI or loading and storing 
instructions be used when changing bit values in the 
TSCR. Read-modify-write instructions can cause the TMZ 
to assume an unexpected state. 

During reset, the TSCR is set to all zeroes; the TIMER 
pin is in the high impedance input mode; and DOUT 
LATCH is forced to a logic high. At the same time, PS0- 
PS2 coding sets the prescaler tap at divide-by-one, and 
bit 3 initializes the prescaler. 



MOTOROLA MICROPROCESSOR DATA 
3-287 



MC6804J1 



TIMER PRESCALER REGISTER ($FD) 

The timer prescaler register reflects the current count 
of the 7-bit prescaler. This register is the prescaler counter 
and can be read or written. 



MSB 



LSB 



RESET: 

1 1 



INSTRUCTION SET 

The MCU has a set of 42 basic instructions. They can 
be divided into five different types: register/memory, read- 
modify-write, branch, bit manipulation, and control. The 
following paragraphs briefly explain each type. 



REGISTER/MEMORY INSTRUCTIONS 

Most of these instructions use two operands. One op- 
erand is the accumulator; the other is obtained from 
memory using one of the addressing modes. Refer to the 
following list of instructions. 



Function 


Mnemonic 


Load A from Memory 


LDA 


Load XP from Memory 


LDX 


Load YP from Memory 


LDY 


Store A in Memory 


STA 


Add to A 


ADD 


Subtract from A 


SUB 


AND Memory to A 


AND 


Transfer A to XP 


TAX 


Transfer A to YP 


TAY 


Transfer YP to A 


TYA 


Transfer XP to A 


TPA 


Clear A 


CLRA 


Clear XP 


CLRX 


Clear YP 


CLRY 


Arithmetic Compare with Memory 


CMP 


Move Immediate Value to Memory 


MVI 


Arithmetic Left Shift of A 


ASLA 


Complement A 


COMA 


Rotate A Left and Carry 


ROLA 



value back to memory or to the register. All INC and DEC 
forms along with all bit manipulation instructions use this 
method. Refer to the following list of instructions. 



Function 


Mnemonic 


Increment Memory Location 


INC 


Increment A 


INCA 


Increment XP 


INCX 


Increment YP 


INCY 


Decrement Memory Location 


DEC 


Decrement A 


DECA 


Decrement XP 


DECX 


Decrement YP 


DECY 



BRANCH INSTRUCTIONS 

This set of instructions branches if a particular condi- 
tion is met; otherwise, no operation is performed. Branch 
instructions are two byte instructions. Refer to the fol- 
lowing list of instructions. 



Function 


Mnemonic 


Branch if Carry Clear 


BCC 


Branch if Higher or Same 


(BHS) 


Branch if Carry Set 


BCS 


Branch if Lower 


(BLO) 


Branch if Not Equal 


BNE 


Branch if Equal 


BEQ 



BIT MANIPULATION INSTRUCTIONS 

The MCU is capable of setting or clearing any bit which 
resides in the 256 bytes of data space, where all port 
registers, port DDRs, timer, timer control, and on-chip 
RAM reside. An additional feature allows the software to 
test and branch on the state of any bit within these 256 
locations. The bit set, bit clear, and bit test and branch 
functions are all implemented with a single instruction. 
For the test and branch instructions, the value of the bit 
tested is also placed in the carry bit of the condition code 
register. Refer to the following list of instructions. 



Function 


Mnemonic 


Branch If Bit n is Set 


BRSET n(n = 0 ... 7) 


Branch If Bit n is Clear 


BRCLR n(n = 0. .. 7) 


Set Bit n 


BSET n(n = 0 . . . 7) 


Clear Bit n 


BCLR n(n = 0...7) 



READ-MODIFY-WRITE INSTRUCTIONS 

These instructions read a memory location or a reg- 
ister, modify or test its contents, and write the modified 



CONTROL INSTRUCTIONS 

These instructions are used to control processor op- 
eration during program execution. The jump conditional 



MOTOROLA MICROPROCESSOR DATA 
3-288 



MC6804J1 



(JMP) and jump to subroutine (JSR) instructions have no 
register operand. Refer to the following list of instruc- 
tions. 



Function 


Mnemonic 


Return from Subroutine 


RTS 


Return from Interrupt 


RTI 


No Operation 


NOP 


Jump to Subroutine 


JSR 


Jump Unconditional 


JMP 



IMPLIED INSTRUCTIONS 

Since the accumulator and all other registers are located in 
RAM, many implied instructions exist. Some of the instructions 
recognized and translated by the assembler are shown below: 



Mnemonic 


Becomes 


Mnemonic 


Becomes 


AS LA 


ADD $FF 


INCX 


INC $80 


BHS 


BCC 


INCY 


INC $81 


BLO 


BCS 


LDXI 


MVI $80 DATA 


CLRA 


SUB $FF 


LDYI 


MVI $81 DATA 


CLRX 


MVI $80 #0 


NOP 


BEQ (PC) + 1 


CLRY 


MVI $81 #0 


TAX 


STA$80 


DECA 


DEC $FF 


TAY 


STA$81 


DECX 


DEC $80 


TXA 


LDA$80 


DECY 


DEC $81 


TYA 


LDA $81 


INCA 


INC $FF 







Some examples of valuable instructions not specifi- 
cally recognized by the assembler are shown below: 



Mnemonic 


Meaning 


BCLR 7,$FF 


Ensures A is plus 


BSET 7, $FF 


Ensures A is minus 


BRCLR 7, $FF 


Branch if A is plus 


BRSET 7, $FF 


Branch if A is minus 


BRCLR 7, $80 


Branch if X is plus (BXPL) 


BRSET 7, $80 


Branch if X is minus (BXMI) 


BRCLR 7, $81 


Branch if Y is plus (BYPL) 


BRSET 7, $81 


Branch if Y is minus (BYMI) 



OPCODE MAP 

Table 1 is a listing of all the instruction set opcodes 
applicable to the MC6804J1 MCU. 



ADDRESSING MODES 

The MCU has nine different addressing modes to pro- 
vide the programmer with an opportunity to optimize the 
code for all situations. It deals with objects in three dif- 
ferent address spaces: program space, data space, and 



stack space. The term "effective address" (EA) is used in 
describing the various addressing modes. Effective ad- 
dress is defined as the address from which the argument 
for an instruction is fetched or stored. 

IMMEDIATE 

In the immediate addressing mode, the operand is lo- 
cated in program ROM. It is contained in the byte im- 
mediately following the opcode. The immediate 
addressing mode is used to access constants that do not 
change during program execution, such as a constant 
used to initialize a loop counter. 

DIRECT 

In the direct addressing mode, the effective address of 
the argument is contained in a single byte following the 
opcode byte. Direct addressing allows the user to directly 
address the 256 bytes of data space with a single two- 
byte instruction. 

SHORT DIRECT 

In the short direct addressing mode, the MCU has four 
locations in data space RAM it can use, ($80, $81, $82, 
and $83). The opcode determines the data space RAM 
location, and the instruction is only one byte. Short direct 
addressing is a subset of the direct addressing mode. 
The X and Y registers are at locations $80 and $81, re- 
spectively. 

EXTENDED 

In the extended addressing mode, the effective address 
of the argument is obtained by concatenating the four 
least-significant bits of the opcode with the byte following 
the opcode to form a 12-bit address. Instructions using 
the extended addressing mode, such as JMP or JSR, are 
capable of branching anywhere in program space. An 
extended addressing mode instruction is two bytes long. 

RELATIVE 

The relative addressing mode is only used in condi- 
tional branch instructions. In relative addressing, the con- 
tents of the 8-bit signed byte (the offset) following the 
opcode is added to the PC if, and only if, the branch 
conditions are true/Otherwise, control proceeds to the 
next instruction. The span of relative addressing is from 
- 15 to + 16 from the opcode address. The programmer 
need not calculate the offset when using the Motorola 
assembler, since it calculates the proper offset and checks 
to see that it is within the span of the branch. 

BIT SET/CLEAR 

In the bit set/clear addressing mode, the bit to be set 
or cleared is part of the opcode. The byte following the 
opcode specifies the direct addressing of the byte in which 
the specified bit is to be set or cleared. Thus, any bit in 
the 256 locations of data space memory that can be writ- 
ten to can be set or cleared with a single two-byte in- 
struction. 



MOTOROLA MICROPROCESSOR DATA 
3-289 



Table 1. Opcode Map 





Branch Instructions 


Register/ Memory, Control, and 
Read/Modify/Write Instructions 


Bit Manipulation 
Instructions 


Register/ Memory and 
Read/ Modify/ Write 




v \' " H" 

Low~"~-^_ 


0 

0000 


1 


2 


3 


1 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


F 




0000 


BNE 


BNE 


BEQ 


BEQ 


BCC 


2 

BCC 


BCS 


BCS 


JSRn 


■■ JMPn 




MVI 


" BRCLR0 

3 BTB 


BCLRO 


LDA' 


LDA 

1 BIND 


0 

oooo 




BNE 

1 BEL 


BNE 


BEQ 


2 

BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 

2 EXT 


JMPn 

2' EXT 






BRCLR1 

3 BIS 


BCLR1 

2 BSC 


STA 


STA 

1 B IND; 


0001 


0010 


2 

BNE 

1 REL 


BNE - 

1 REL 


BEQ 


BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 


JMPn 




RTI 


BRCLR2 


BCLR2 

2 BSC 


ADD 

1 R IND 


ADD 


-0010 


Mil 


2 

BNE 

1 REL 


BNE 


BEQ 


BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 


JMPn 




RTS 


BRCLR3 


BCLR3 


SUB 


SUB 


m, 


0100 


2 

BNE 

1 , R EL 


BNE - 

1 . REL 


BEQ 


BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 


JMPn 




COMA 


BRCLR4 


BCLR4 


CMP 


CMP 


°™ 


0101 


. BNE 


BNE 

1 REL 


BEQ 

1 REL 


BEQ 

1 REL 


BCC 


BCC 


BCS 


BCS 


JSRn 


'. JMPn 




ROLA 


8RCLR5 


BCLR5 


AND 


AND 




"6 

0110 


. BNE 

1 . REL 


BNE 

1 REL 


BEQ 

1 REL 


BEQ 

1 REL 


BCC 

1 REL 


BCC 

1 .BEL 


BCS 

1 .REL 


BCS 

1 1 BEL 


JSRn 

2 EXT 


JMPn 

2 EXT 






BRCLR6 

3 6TB 


BCLR6 

2 BSC 


INC 


. INC 




out 


BNE 

1 REL 


BNE 


BEQ 


2 

BEQ 


BCC 


BCC 


BCS 


BCS 

1 BEL 


JSRn 

2 EXT 


JMPn 

2 EXT 






BRCLR7 


BCLR7 


DEC 


DEC 




1000 


BNE 

1 BEL 


BNE 

1 REL 


BEQ 

1 REL 


BEQ 

1 REL 


BCC. 


BCC 


BCS 

1 • "EL 


BCS 

1 REL 


JSRn 

2 . EXT 


JMPn 

2 EXT 


INC 

1 so 


DEC 

i so 


BRSETO 

3 e II 


BSETO 

2 BSC 


LDA 


LDA 

2 DIR 




9 

1001 


BNE 


BNE 


BEQ 


BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 


JMPn 


INC 


DEC 


5 

BRSET1 


BSET1 


* 


STA 


9 


A • 

1010' 


BNE 

1 REL 


BNE 

2 BEL 


BEQ 


2 BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 


JMPn 


INC 

1 S O 


DEC 


BRSET2 


BSET2 

2 BSC 


ADD 


ADD 


A 


B 

ion 


2 BNE 

1 BEL 


BNE 

1 BEL 


BEQ 


BEQ 


BCC 


BCC 

1 BEL 


BCS 


BCS 


JSRn 


JMPn 


INC 


DEC 


BHSET3 


BSET3 


SUB 


SUB 


B 


C 

1100 


BNE 

1 REL 


BNE 

1 REL 


BEQ 

1 BEL 


BEQ 

1 REL 


BCC 


BCC 

1 BEL 


BCS 

1 BEL 


BCS 

1 BEL 


JSRn 


JMPn 


LDA 

1 S D 


STA 

1 S D 


8RSET4 

3 BTB 


BSET4 

2 BSC 


CMP 

2 IMM 


CMP 

DIR 


C 


D 


2 

BNE 


BNE 


BEQ 


2 

BEQ 


BCC 


BCC 


BCS 


BCS 


JSRn 


JMPn 


LDA 


STA 


BRSET5 


BSET5 


AND 


AND 


D 

1101 


E 

1110 


2 

BNE 


BNE 

1 REL 


BEQ 

i REL 


2 

BEQ 


BCC 


BCC 


BCS 

1 BEL 


BCS 


JRSn 

2 EXI 


JMPn 


LDA 


STA 

1 S D 


BRSET6 

3 6 T 8 


BSET6 

2 BSC 


» 


INC 


E 


F 


2 

BNE 


BNE 


BEQ 


2 

BEQ 


BCC 


BCC 


BCS 

1 REL 


BCS 

1 BEL 


JSRn 


JMPn 

2 EXT 


LDA 


STA 

1 . S 0 


BRSET7 

3 BTB 


BSET7 

2 BSC 


* 


DEC 


F 



Abbreviations for Address Modes 

INH inherent 

S-D Short Direct 

B-T-B Bit Test and Branch 

IMM Immediate 

DIR Direct 

EXT Extended 

REL Relative 

BSC Bit Set/Clear 

R IND Register Indirect 



Indicates Instruction Reserved for Future Use 
Indicates Illegal Instruction 



Opcode in Hexadecimal 




MC6804J1 



CAUTION 

The corresponding DDRs for ports A and B are write 
only registers (registers at $04 and $05). A read 
operation on these registers is undefined. Since 
BSET and BCLR are read-modify-write functions, 
they cannot be used to set or clear a DDR bit; all 
"unaffected" bits would be set. Write all DDR bits 
in a port using a single-store instruction. 

BIT TEST AND BRANCH 

The bit test and branch addressing mode is a combi- 
nation of direct addressing and relative addressing. The 
bit that is to be tested and its condition (set or clear) is 
included in the opcode. The data space address of the 
byte to be tested is in the single byte immediately fol- 
lowing the opcode byte. The third byte is sign extended 
to 12 bits and becomes the offset added to the PC if the 
condition is true. This single three-byte instruction allows 



the program to branch based on the condition of any 
readable bit in the 256 locations of data space. The span 
of branching is from -125 to +130 from the opcode 
address. The state of the tested bit is also transferred to 
the carry flag. 

REGISTER-INDIRECT 

In the register-indirect addressing mode, the operand 
is at the address in data space pointed to by the contents 
of one of the indirect registers, X or Y. The particular 
indirect register is selected by bit 4 of the opcode. Bit 4 
decodes into an address that represents the register, $80 
or $81. A register-indirect instruction is one byte long. 

INHERENT 

In the inherent addressing mode, all the information 
necessary to execute the instruction is contained in the 
opcode. These instructions are one byte long. 



ELECTRICAL SPECIFICATIONS 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Supply Voltage 


vcc 


-0.3 to +7.0 


V 


Input Voltage 


V in 


-0.3 to +7.0 


V 


Operating Temperature Range (Comm.) 


ta 


0 to 70 


°c 


Operating Temperature Range (Ind.) 


ta 


-40 to +85 


°c 


Storage Temperature Range 


T stg 


- 55 to + 1 50 


°c 


Junction Temperature 


Tj 


150 


°c 


THERMAL CHARACTERISTICS 


Characteristic 


Symbol 


Value 


Unit 


Thermal Resistance 


ejA 


70 


°c/w 



This device contains circuitry to protect the in- 
puts against damage due to high static voltages 
or electric fields; however, it is advised that nor- 
mal precautions be taken to avoid application of 
any voltage higher than maximum-rated voltages 
to this high-impedance circuit. For proper oper- 
ation it is recommended that Vj n and V ou t be con- 
strained to the range Vgs * (Vj n or V ou t) s Vcc- 
Reliability of operation is enhanced if unused in- 
puts except EXTAL are connected to an appro- 
priate logic voltage level (e.g., either Vss or Vcc)- 



POWER CONSIDERATIONS 

The average chip-junction temperature, Tj, in °C can 
be obtained from: 

Tj=T A +(P D .e JA ) (1) 



where: 




T A 


= Ambient Temperature, °C 


6JA 


= Package Thermal Resistance, 


Junction-to-Ambient, °C/W 


PD 


= P|NT +p PORT 


p int 


- 'CC X ^CC' Watts — Chip Internal Power 


PPORT 


= Port Power Dissipation, 



Watts — User Determined 



For most applications PpoRT <p INT and can be ne- 
glected. PpoRT ma y become significant if the device is 
configured to drive Darlington bases or sink LED loads. 

An approximate relationship between Pq and Tj (if 
PpORT is neglected) is: 

P D = K + (Tj + 273°C) (2) 

Solving equations (1) and (2) for K gives: 

K = P d .(T a +273 0 C) + 6ja-Pd 2 (3) 

where K is a constant pertaining to the particular part. 
K can be determined from equation (3) by measuring Pq 
(at equilibrium) for a known T A . Using this value of K, 
the values of Pq and Tj can be obtained by solving equa- 
tions (1) and (2) iteratively for any value of T A . 



MOTOROLA MICROPROCESSOR DATA 
3-291 



MC6804J1 



ELECTRICAL CHARACTERISTICS 

(Vcc= +5.0 Vdc±0.5 Vdc, Vss = GND, Ta = 0°C to 70°C, unless otherwise noted) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Internal Power Dissipation — No Port Loading 


pint 




120 


165 


mW 


Input High Voltage 


vih 


2.0 




v C c 


V 


Input Low Voltage 


V| L 


-0.3 




0.8 


V 


Input Capacitance 


Cin 




10 




PF 


Input Current (IRQ, RESET) 


■in 




2 


20 





SWITCHING CHARACTERISTICS 

(Vcc= +5.0 Vdc±0.5 Vdc, Vss = GND, Ta=0°C to 70°C, unless otherwise noted) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Oscillator Frequency 


f osc 


4.0 




11.0 


MHz 


Bit Time 


tbit 


0.364 




1.0 


(AS 


Byte Cycle Time 


tbyte 


4.36 




12.0 


|XS 


IRQ and TIMER Pulse Width 


tWL- tWH 


2xt bv te 








RESET Pulse Width 


tRWL 


2 x t bvte 








RESET Delay Time (External Capacitance = 1.0 jiF) 


tRHL 


100 






ms 



TEST 
POINT 



40 | 

(TOTAL) 



MM061S0 
OR EQUIV. 



P 

^ 4 



V C C = 6.2 V 
kO 



MM07000 
OR EQUIV. 



TEST POINT o- 



?k 30 pF (TOTAL) 



TEST 
POINT 



MM06150 

OR EQUIV. 







30 pF _ 


> i 46 kQ , r 


(TOTAL) " 







9 V CC = 5.2 V 
10 kfi 



MMD7000 
OR EQUIV 



Figure 9. LSTTL Equivalent 
Test Load (Port B) 



osc 



Figure 10. CMOS Equivalent 
Test Load {Ports A, B, C) 



lal OSCILLATOR - *1-*2 TIMING 



Figure 11. LSTTL Equivalent 
Test Load (Ports A, C, 
and TIMER) 



*1 | " 

*2 L 




MOTOROLA MICROPROCESSOR DATA 
3-292 



MC6804J1 



PORT DC ELECTRICAL CHARACTERISTICS 

(Vcc= +5.0 Vdc±0.5 Vdc, Vss = GND, Ta=0°C to 70°C, unless otherwise noted) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


Ports A and Timer (Standard) 


Output Low Voltage, lLoad = °-4 mA 


vol 






0.5 


V 


Output High Voltage, lLoad = -50 |iA 


VOH 


2.3 






V 


Input High Voltage 


V| H 


2.0 




vcc 


V 


Input Low Voltage 


V| L 


-0.3 




0.8 


V 


Hi-Z State Input Current 


'TSI 




4 


40 


|xA 


Port A (Open Drain) 


Output Low Voltage, lLoad= 0 - 4 mA 


vol 






0.5 


V 


Input High Voltage 


V|H 


2.0 




vcc 


V 


Input Low Voltage 


V|L 


-0.3 




0.8 


V 


Hi-Z State Input Current 


'TSI 




4 


40 


pA 


Open Drain Leakage (V 0Ut =Vcc) 


lLOD 




4 


40 


(jA 


Port A (CMOS Drive 




Output Low Voltage, ILoad = Q.4 mA (Sink) 


vol 






0.5 


V 


Output High Voltage, li_oad= _1 ° M-A 


voh 


v C c -io 






V 


Output High Voltage, lLoad= -50 jiA 


V 0 H 


2.3 






V 


Input High Voltage, lLoad= -300 fA Max 


V|H 


2.0 




v cc 


V 


Input Low Voltage, lLoad= -300 f«A Max 


Vil 


-0.3 




0.8 


V 


Hi-Z State Input Current (Vj n =0.4 V to Vcc) 


Itsi 






-300 


. .M-A 


Port B (Standard) 


Output Low Voltage, iLoad = 1-0 mA 


vol 






0.5 


V 


Output Low VoltageJLoad = 10 mA (Sink) 


vol 






1.5 


V 


Output High Voltage, li_oad= _ 1° 0 pA 


VOH 


2.3 






V 


Input High Voltage 


V| H 


2.0 




vcc 


V 


Input Low Voltage 


V|L 


-0.3 




0.8 


V 


Hi-Z State Input Current 


Itsi 




8 


80 


|jlA 


Port B (Open Drain) 


Output Low Voltage, lLoad = 10 mA 


vol 






0.5 


V 


Output Low Voltage, lLoad = 10 mA (Sink). 


vol 






1.5 


V 


Input High Voltage 


V|H 


2.0 




vcc 


V 


Input Low Voltage 


vil 


-0.3 




0.8 


V 


Hi-Z State Input Current 


'tsi 




8 


80 


|xA 


Open Drain Leakage (V out =Vcc) 


ilod 




8 


80 


[x,A 


Port B (CMOS Drive) 


Output Low Voltage, l|_ 0 ad = 1 0 mA 


vol 






0.5 


V 


Output High Voltage, l|_oad = 10 mA (Sink) 


vol 






1.5 


V 


Output High Voltage, lLoad = _ 10 fA 


voh 


v C c -io 






V 


Output High Voltage, l[.oad = - 100 pA 


voh 


2.3 






V 


Input High Voltage, >Load= -300 pA Max 


vih 


2.0 




vcc 


V 


Input Low Voltage, lLoad= -300 f- A Max 


V|L 


-0.3 




0.8 


V 


Hi-Z State Input Current (Vj n = 0.4 V to Vcc) 


'TSI 






-300 


(xA 


Ports A and B (Low Current Clamping Diode*) 


Input High Current V|h=Vcc+10 V 


l|H 






100 


(J.A 


Input Low Current V||_ = 0.8 V 


hL 






-4.0 


IxA 



•Denotes not tested unless specified on ordering form. 



MOTOROLA MICROPROCESSOR DATA 
3-293 



MC6804J1 





I I 
EXPECTED 1 


I 

TYPICAI 








MAX 5.5 V 
«noi> > 


5.0 V 
S itor 


















xpfr.TFr 


■ 












MIN 4.5 V 

iikop 




/ 

/ 






























— 
























X (0.5 V, 400 /iA) 
1 1 





0 

= SPEC PT. 



0 200 300 400 500 600 
V 0L . LOW-LEVEL OUTPUT VOLTAGE (mV| 

Figure 13. Typical Vol vs Iol 
for Port A and TIMER 



-400 



(2.3 


/. -5 
X — 


0 pA) 


i 












' 


/ 












N 4.5 










/ 


r — 










— i £j 
: M 


V 


T TYPICAL 

/ 5.0 V 


T EXPECTED 
( MAX 5.5 V 










95°C 






25°C 




1 
/ 


-40 


°C 




















~T~ 
/ 










— i 














/ 
1 










— /- 














/ 

1 — 































2.0 

X = SPECPT. 



2.5 3.0 . 3.5 4.0 4. 

V 0H . HIGH-LEVEL OUTPUT VOLTAGE (V) 

Figure 14. Typical VrjH vs loH 
for Port A and TIMER 




3 4 5 

V 0H . HIGH-LEVEL OUTPUT VOLTAGE (VI 

Figure 15. Typical Vqh vs lrjH 
for Port A with CMOS Pullups 



10 
« 9 



h- 6 

£ 

£ 5 



Sj 4 

1 3 
2 

1 

0 



i 





1 1 


/TYPICAL 














EXPECT 
MX 5. 
-40° 


ED / 


f— 5.0 V 
25°C/ 















?T 


















/ 




















/ 

-/— 






*EXPE 


:teo 












t . 






MIN 4.5 V 

ocor _ 










— /* 
/ 











































































1 1 



0 100 200 300 400 500 

Vol. LOW-LEVEL OUTPUT VOLTAGE ImV) 

X = SPECPT. 

Figure 16. Typical Vql vs Iql for Port B 




2.0 2.5 3.0 3.5 4.0 4.5 

V 0H . HIGH-LEVEL OUTPUT VOLTAGE (VI 

= SPEC PT. 

Figure 17. Typical Vqh vs Iqh f <> r Port B 



-500 



I I I 


















-• 




(2.3 V, - 


100 


/•A) 














-r 
/ 


























1 
















.■EXPECTED 
• MIN 4.5 V 


TYPICAL 
5.0 V 


EXPECTED 
MAX 5.5 V 










85 


°C 




25 


°C 


—1 
I 




40°C 


















I 






1 




























T 
1 




























1 



































































"2.0 2.5 3.0 3.5 4.0 , 4.5 5.0 
Vqh. HIGH-LEVEL OUTPUT VOLTAGE (VI 
X = SPECPT 



Figure 18. typical VfjH vs Iqh 
for Port B with CMOS Pullups 



MOTOROLA MICROPROCESSOR DATA 
3-294 



MC6804J1 



ORDERING INFORMATION 



The following information is required when ordering a 
custom MCU. The information may be transmitted to Mo- 
torola using the following media: 
MDOS®, disk file 
MS®-DOS/PC-DOS disk file (360K) 
EPROM(s) 2516, 2716, 2532, 2732 
To initiate a ROM pattern for the MCU, it is necessary 
to first contact the local field service office, sales person, 
or Motorola representative. 

FLEXIBLE DISKS 

Several types of flexible disks (MDOS or MS-DOS/PC- 
DOS disk file) may be submitted for pattern generation. 
They should be programmed with the customer program, 
using positive logic sense for address and data. The dis- 
kette should be clearly labeled with the customer's name, 
date, project or product name, and the filename contain- 
ing the pattern. 

In addition to the program pattern, a file containing the 
program source code listing can be included. This data 
will be kept confidential and used to expedite the process 
in case of any difficulty with the pattern file. 

MDOS Disk File 

MDOS is Motorola's Disk Operating System available 
on the EXORciser® development system. The disk media 
submitted must be a single-sided, single-density, 8-inch 
MDOS compatible floppy diskette. The diskette must con- 
tain the minimum set of MDOS system files in addition 
to the pattern file. 

The .LO output of the M6804 cross assembler should 
be furnished. In addition, the file must be produced using 
the ROLLOUT command, so that it contains the absolute 
image of the M6804 memory. It is necessary to include 
the entire memory image of both program and data space. 
All unused bytes, including those in the user space, must 
be set to logic zero. 

MS-DOS/PC-DOS Disk File 

MS-DOS is Microsoft's Disk Operating System. PC-DOS 
is IBM®'s Personal Computer Disk Operating System. Disk 
media submitted must be standard density (360K), dou- 
ble-sided 5 1/4 inch compatible floppy diskette. The dis- 
kette must contain the object file code in Motorola's S- 
record format. The S-record format is a character-based 
object file format generated by M6804 cross assemblers 
and linkers on IBM PC style machines. 



EPROMS 

Four K of EPROM are necessary to contain the entire 
MC6804J1 program. Two 2516 or 2716 type EPROMs or 
a single 2532 or 2732 type EPROM can be submitted for 
pattern generation. The EPROM is programmed with the 
customer program using positive logic sense for address 
and data. Submissions on two EPROMs must be clearly 
marked. All unused bytes, including the user's space, 
must be set to zero. 

If the MC6804J1 MCU ROM pattern is submitted on 
one 2532 or 2732 EPROM, or on two 2516 or 2716 type 
EPROMs, memory map addressing is one-for-one. The 
data space ROM runs from EPROM address $018 to $05F 
and program space ROM runs from EPROM address $E00 
to $FF7, with vectors from $FFC to $FFF. 

For shipment to Motorola, EPROMs should be placed 
in a conductive IC carrier and packed securely. Styrofoam 
is not acceptable for shipment. 

Verification Media 

All original pattern media, EPROMs or floppy disks, are 
filed for contractual purposes and are not returned. A 
computer listing of the ROM code will be generated and 
returned along with a listing verification form. The listing 
should be thoroughly checked and the verification form 
should be completed, signed, and returned to Motorola. 
The signed verification form constitutes the contractual 
agreement for the creation of the customer mask. To aid 
in the verification process, Motorola will program cus- 
tomer supplied blank EPROM(s) or DOS disks from the 
data file used to create the custom mask. 

ROM Verification Units (RVUs) 

Ten MCUs containing the customers ROM pattern will 
be sent for program verification. These units will have 
been made using the custom mask, but are for the pur- 
pose of ROM verification only. For expediency, the MCUs 
are unmarked, packaged in ceramic, and tested with five 
volts at room temperature. These RVUs are free with the 
minimum order quantity, but are not production parts. 
These RVUs are not guaranteed by Motorola Quality As- 
surance. 

Ordering information 

The following table provides generic information per- 
taining to the package type and temperature for the 
MC6804J1. This MCU device is available in the 20-pin 
dual-in-line (DIP) package. 



Generic Information 



Package Type 


Temperature 


Order Number 


Plastic 
(P Suffix) 


OX to 70°C 
-40°Cto +85°C 


MC6804J1P 
MC6804J1CP 



MDOS is a trademark of Motorola Inc. 
MS-DOS is a trademark of Microsoft, Inc. 
EXORciser is a registered trademark of Motorola Inc. 

IBM is a registered trademark of International Business Machines Corporation. 



MOTOROLA MICROPROCESSOR DATA 
3-295 



MC6804J1 



MECHANICAL DATA 



PIN ASSIGNMENTS 



a 




MOTOROLA MICROPROCESSOR DATA 
3-296 



MOTOROLA 

I SEMICONDUCTOR 

TECHNICAL DATA 



MC6804J2 



Technical Summary 

8-Bit Microcomputer Unit 



MC6804J2 HMOS (high-density NMOS) microcomputer unit (MCU) is a member of the M6804 
Family of serial processing microcomputers. This device displays all the versatility of an MCU 
whose design-ability to process 8-bit variables one bit at a time already makes it tremendously cost 
effective. 

This technical summary contains limited information on the MC6804J2. For detailed information, 
refer to the advanced information data sheet for the MC6804J1, MC6804J2, MC6804P2, and 
MC68704P2 8-bit microcomputers (MC6804J1/D) or to the M6804 MCU Manual (DLE404/D). 

Major hardware and software features of the MC6804J2 MCU are: 



On-Chip Clock Generator 

Memory Mapped I/O 

Software Programmable 8-Bit Timer with 

7-Bit Prescaler 

Single Instruction Memory Examine/ 
Change 

30 Bytes of Data RAM 



• True Bit Manipulation 

• Bit Test and Branch Instruction 

• 304 Bytes Self-Check ROM 

• Conditional Branches 

• Timer Pin is Software Programmable as 
Clock Input or Timer Output 

• 1000 Bytes of User Program Space ROM 



User Selectable Output Drive Options, LSTTL, LSTTL/CMOS, and Open-Drain Interface Ports 
Mask Selectable Edge- or Level-Sensitive Interrupt Pin 




BLOCK DIAGRAM 



TIMER • 



PRESCALER 


8 BIT 
COUNTER 


TIMER/! 
CONTROL 


iTATUS 
REGISTER 



PORT 
A PA5 

I/O 

LINES m 



PORT 


0ATA 


A 


DIR. 


REG. 


REG. 



1000x8 
USER PROGRAM ROM 



304x8 
SELF-CHECK ROM 



XTAL EXTAL RESET MDS IRQ 

J__t 



OSCILLATOR 



ACCUMULATOR 



INDIRECT 




REGISTER 


X 


INDIRECT 




REGISTER 


Y 


STACK 


PROGRAM 




COUNTER 




HIGH 


PCH 



PROGRAM 
COUNTER 
LOW PCL 



CPU 
CONTROL 



CPU 





This document contains information on a new product. Specifications and information herein are subject to change without notice. 



MOTOROLA MICROPROCESSOR DATA 
3-297 



MC6804J2 



SIGNAL DESCRIPTION 

V C C AND V S S 

Power is supplied to the microcomputer using these 
two pins. Vqc is +5 volts (±0.5 V) power, and VsS <s 
ground. 

iRQ 

This pin provides the capability for asynchronously ap- 
plying an external interrupt to the microcomputer. 

EXTAL AND XTAL 

These pins provide control input for the on-chip clock 
oscillator circuit. A crystal, a resistor/capacitor combi- 
nation, or an external signal is connected to these pins 
to provide a system clock. Selection is made by a man- 
ufacturing mask option. The different clock generator op- 
tions are shown in Figure 1, along with crystal 
specifications. 

Internal Clock Options 

The crystal oscillator start-up time is a function of many 
variables. To ensure rapid oscillator start-up, neither the 
crystal characteristics nor load capacitances should ex- 
ceed recommendations. When using the on-board oscil- 
lato r, the M CU should remain in a reset condition, with 
the RESET pin voltage below Vires + / until the oscillator 
has stabilized at its operating frequency. See Figure 2 for 
resistor/capacitor oscillator options. 



TIMER 

The TIMER pin can be configured to operate in either 
the input or output mode. As input, this pin is connected 
to the prescaler input and serves as the timer clock. As 
output, the timer pin reflects the contents of the DOUT 
bit of the timer status/control register, the last time the 
TMZ bit was logic high. 

RESET 



The RESET pin is used to restart the processor to the 
beginning of a program. The program counter is loaded 
with the address of the restart vector. This should be a 
jump instruction to the first instructio n of the main pro- 
gram. Together with the MDS pin, the RESET pin selects 
the operating mode of the MCU. 

MDS 

The mode select (MDS) pin places the MCU into special 
operating modes. When this pin is logic high at the exit 
of the reset state, the decoded state of PA6 and PA7 is 
latched to determine the operating mode. This choice can 
be either the single-chip, self-check, or EPROM program- 
ming. However, if MDS is logic low at the end of the reset 
state, the single-chip operating mode is automatically 
selected. No external diodes, switches, transistors, etc. 
are required for single-chip mode selection. 

INPUT/OUTPUT LINES (PA4-PA7, PB0-PB7) 

These 12 lines are arranged into one 4-bit port (A) and 
one 8-bit port (B). All lines are programmable as either 



NC 

EXTERNAL 
CLOCK 
INPUT 



MCU 
[CRYSTAL MASK 
OPTION) 



EXTERNAL CLOCK 



MCU 

(RESISTOR-CAPACITOR MASK 
OPTIONI 



I * DENOTES NCIGNO. GROUNDING 
PIN 4 WILL REDUCE RFI NOISE. I 

EXTERNAL RESISTOR CAPACITOR 




CRYSTAL PARAMETERS 



EXTAL 4 



CRYSTAL PARAMETERS 
AT - CUT PARALLEL RESONANCE CRYSTAL 
Co = 7 pF MAXIMUM 
FREQ. = 1 1 MHz . 
R S = SO OHMS MAXIMUM 

PIEZOELECTRIC CERAMIC RESONATORS MAY BE 
SUBSTITUTED FOR THE CRYSTAL. FOLLOW 
MANUFACTURER'S CERAMIC RESONATOR 
SPECIFICATIONS. 




NOTE: Keep crystal leads and circuit connections as short as possible. 

Figure 1. Clock Generator Options and Crystal Parameters 



MOTOROLA MICROPROCESSOR DATA 
3-298 



MC6804J2 











I I 












— — 15 pF AT 25°C 

22 pF AT 25°C 

27 pF AT 25°C 

• — ■— 36 pF AT 25°C 
50 P F AT 25°C 














'.\ V 











































































































2 4 6 8 10 12 14 16 18 
R L , LOAD RESISTANCE (ku> 

(al TYPICAL FREQUENCY VS RESISTANCE 



8.0 
7.8 

1 7.6 
u 

2 7.4 
o 

E 7.2 
7.0 
6.8 



6.6 















































— u 


















































■ — 




r"""" 





























































4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 

V C c supply voltage ivi 

lb) TYPICAL FREQUENCY VARIATIONS @ C L = 15 pF. 10 kO 



£ 9.4 
2 

5 9.2 

§ 9.0 



8.4 

























































































--"'or 














— 




.-" 1 "Tr 





















































4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 
Vcc. SUPPLY VOLTAGE (VI 

(el TYPICAL FREQUENCY VARIATIONS @ C L =50 pF, 3 k« 

Figure 2. Typical Frequency Selection for 
Resistor/Capacitor Oscillator Options 




inputs or outputs under software control of the data di- 
rection registers. 



PROGRAMMING 

INPUT/OUTPUT PROGRAMMING 

There are 12 input/output pins. All pins of each port 
are programmable as inputs or outputs under the control 
of the data direction registers (DDR). 

The port I/O programming is accomplished by writing 
the corresponding bit in the port DDR to a logic one for 
output, or a logic zero for input, as shown in Figure 3. 
When the registers are programmed as outputs, the 
latched data is readable regardless of the logic levels at 
the output pin due to output loading. 

All the I/O pins are LSTTL compatible as both inputs 
and outputs. In addition, both ports may use either or 
both of two manufacturing mask options; open drain out- 
put, or internal pull-up resistor for CMOS compatibility. 

Any write to a port writes to all of its data bits even 
though the port DDR may be set to input. This can be 



used as a tool to initialize the data registers and avoid 
undefined outputs. However, care must be exercised when 
using read-modify-write instructions. The data read cor- 
responds to the pin level if the DDR is an input or to the 
latched output data when the DDR is an output. 

The 12 bidirectional lines may be configured by port 
to be the standard configuration (LSTTL), or either mask 
option; LSTTL/CMOS, or open drain. Port B outputs are 
LED compatible. 

Port Data Registers ($00, $01) 

The port data registers are not initialized on reset. These 
registers should be initialized before changing the DDR 
bits to avoid undefined levels. 

Port A ($00) 



7 


6 


5 


4 


3 


2 


1 


0 










X 


X 


X 


X 


7 


6 


5 


Port B ($01) 

4 3 


2 


1 


0 



















MOTOROLA MICROPROCESSOR DATA 
3-299 



MC6804J2 



DATA 
DIRECTION REGISTER 
BIT 



LATCHED 
OUTPUT 

DATA 

BIT 






I/O 
PIN 




DATA 








DIRECTION 


OUTPUT 




INPUT 


REGISTER 


DATA 


OUTPUT 


TO 


BIT 


BIT 


STATE 


MCU 


1 
1 


0 


0 


0 


0 


1 
X 


1 

Hl-Z 


1 

PIN 



*For CMOS option transistor acts as resistor (approximately 40 kfi) to VqC- 
For LSTTL/open-drain options transistor acts as low current clamping diode to Vrjc- 

Figure 3. Typical I/O Port Circuitry 



With regard to Port A only, the four LSB bits are unused. 
These bits are "don't care" (X) bits when written to but 
are always logic high when read. 

Port Data Direction Registers ($04, $05) 

Port DDRs configure the port pins as either outputs or 
inputs. Each port pin can be programmed individually to 
bean input or an output. A zero inthe pin's corresponding 
DDR bit programs it as an input; a logic one programs it 
as an output. On reset, all the DDRs are initialized to a 
logic zero state to put the ports in the input mode. 

Port A ($04) 



7 6 


5 


4 


3 


2 


1 


0 










0 


0 


0 


0 


7 6 


5 


Port B ($05) 

4 3 


2 


1 


0 



















With regard to Port A only, the four LSB bits are cleared 
(logic zero) by reset. These bits must not be set (logic 
one). 



MEMORY 

The MCU memory map (Figure 4) consists of 4352 bytes 
of addressable memory, I/O register locations, and four 
levels of stack space. This MCU has three separate mem- 
ory spaces: program space, data space, and stack space. 

The MCU is capable of addressing 4096 bytes of pro- 
gram space memory with its program counter and 256 
bytes of data space memory with its instructions. Pro- 
gram space memory includes self-check ROM, program 
ROM, self-check and user program vectors, and reserved 
memory locations. 

A non-accessible subroutine stack space RAM is pro- 
vided. This stack space consists of a last-in-first-out (LIFO) 
register. This register is used with inherent addressing 
to stack the return address for subroutines. 

Indirect X and Y register locations $80 and $81 are 
generally used as pointers for such tasks as indirect ad- 
dressing to data space locations. Short direct addressing 
allows access to the four data space addresses $80-$83 
with single-byte opcodes. The operations allowed are in- 
crement, decrement, load, and store. Data space loca- 
tions $82 and $83 can be used for 8-bit counter locations. 



MOTOROLA MICROPROCESSOR DATA 
3-300 



MC6804J2 



BYTES 
0000 



2783 
2784 



3087 
3088 



4087 
4088 
4089 
4090 
4091 
4092 
4093 
4094 
4095 



RESERVED 
(2784 BYTES) 



SELF-CHECK ROM 
(304 BYTES) 



PROGRAM ROM 
(1000 BYTES) 



SELF-CHECK 
IRQ VECTOR 



SELF-CHECK 
RESTART VECTOR 



_USER 
IRQ VECTOR 



USER 
RESTART VECTOR 



PROGRAM SPACE 

STACK SPACE 

LEVEL 1 
LEVEL 2 
LEVEL 3 



ADDRESS 



$000 



BYTES 



ADDRESS 



$ADF 
$AEO 



$COF 
$C10 



$FF7 
$FF8 
$FF9 
$FFA 
$FFB 
$FFC 
SFFO 
$FFE 
$FFF 



000 


PORT A DATA REGISTER 


$00 


001 


PORT B DATA REGISTER 


$01 


002 




RESERVED 




$02 


003 




(2 BYTES) 




$03 


004 


PORT A DDR 


$04 


005 


PORT B DOR 


$05 


006 




RESERVED 




$06 


008 




(3 BYTES) 




$08 


009 


TIMER STATUS CONT. REG. 


$09 


01C L 




RESERVED 




$0A 

s» 


03f 




(14 BYTES) 




It* 

$17 


032 








$18 






USER DATA SPACE ROM 










(72 BYTES) 






095 








$5F 


096, 




RESERVED 




$60 


127 




(32 BYTES) 




$7F 


128 


INDIRECT REGISTER X 


$80 


129 


INDIRECT REGISTER Y 


$81 


130^ 




USER DATA SPACE RAM 




$82 


159 




(30 BYTES) 




~$9F 


160 








$A0 






RESERVED 










(93 BYTES) 




w 


252 








$FC 


253 


PRESCALER REGISTER 


$FD 


254 


TIMER COUNT REGISTER 


$FE 


255 


ACCUMULATOR 


$FF 



DATA SPACE 



LEVEL 4 



(UFO) 



Figure 4. Memory Map 



MOTOROLA MICROPROCESSOR DATA 
3-301 



MC6804J2 



REGISTERS 

ACCUMULATOR (A) 

The accumulator is a general purpose 8-bit register 
used to hold operands and results of arithmetic calcu- 
lations or data manipulations. 

7 0 



INDIRECT REGISTERS (X,Y) 

These two registers are used to maintain pointers to 
other memory locations in data space. They are used in 
the register-indirect addressing mode and can be ac- 
cessed with the direct, indirect, short direct, or bit set/ 
clear modes. 

7 . ... ' ' 0 



PROGRAM COUNTER (PC) 

The program counter is a 12-bit register that contains 
the address of the next byte to be fetched. The program 
counter is contained in low byte (PCL) and high nibble 
(PCH). 



11 



8 7 



PCH 



PCL 



STACK 

A last-in-first-out (LIFO) stack is incorporated in the MCU 
that eliminates the need for a stack pointer. This non- 
accessible subroutine stack space is implemented in sep- 
arate RAM, 12 bits wide. Whenever a subroutine call or 
interrupt occurs, the contents of the PC are shifted into 
the top register of the stack. At the same time, the top 
register is shifted one level deeper. This happens to all 
registers, with the bottom register falling out of the stack. 

Whenever a return from subroutine or interrupt occurs, 
the top register is shifted into the PC and all lower reg- 
isters are shifted one level higher. The stack RAM is four 
levels deep. If the stack is pulled more than four times 
with no pushes, then the address that was stored in the 
bottom level of the stack is shifted into the PC. 



SELF CHECK 

The MCU implements two forms of internal check: self 
check and ROM verify. Self check performs an extensive 
functional check of the MCU using a signature analysis 
technique. ROM verify uses a similar method to check 
the contents of program ROM. 

Self-check mode is selected by holding the M PS and 
PA7 pins logic high and the PA6 pin logic low as RESET 
goes low to high. ROM verify mode i s entere d by holding 
MDS, PA7, and PA6 logic high as RESET goes low to 
high. Unimplemented program space ROM locations are 
also tested. Monitoring the self-check mode's stages for 
successful completion requires external circuitry, see 
M6804 MCU Manual (DLE404/D). 



RESET 



FLAGS (C,Z) 

The first flag, the carry (C) bit, is set on a carry or borrow 
out of the arithmetic logic unit (ALU). It is cleared if the 
arithmetic operation does not result in a carry or borrow. 
The C bit is also set to the value of the bit tested in a bit 
test instruction. It participates in the rotate left (ROLA) 
instruction, as well. 

The second flag, the zero (Z) bit, is set if the result of 
the last arithmetic or logic operation was equal to zero. 
Otherwise, it is cleared. Bit test instructions do not affect 
the Z bit. 



NORMAL FLAGS 



INTERRUPT FLAGS 








C 


Z 



There are two sets of these flags. One set is for interrupt 
processing (interrupt mode flags). The other set is for 
normal operations (program mode flags). When an in- 
terrupt occurs, a context switch is made from the pro- 
gram flags to the interrupt flags. An RTI forces the context 
switch back. While in either mode, only the flags for that 
mode are available. A context switch does not affect the 
value o f the C or Z bits. Both sets of flags are cleared by 
RESET. 



RESET 

All resets of the M C6804J2 are caused by the external 
res et input (RESET). A reset can be achieved by pulling 
the RESET pin to logic low for a minimum of 96 oscillator 
cycles. 

During reset, a de lay of 9 6 oscillator cycles is needed 
before allowin g the R ESET input to go high. If power is 
being applied, RESET must be held low long enough for 
the oscillator to stabilize and then provide the 96 c locks. 
Connecting a capacitor and resistor to the RESET input, 
as shown in Figure 5 below, typically provides sufficient 
delay. 

+ 5 V 



RESET 



> 4.7 k 
28 ? 



MCU 



Figure 5. Powerup RESET Delay Circuit 



MOTOROLA MICROPROCESSOR DATA 
3-302 



MC6804J2 



INTERRUPT 

The MCU can be interrupted by applying a logic low 
signal to the IRQ pin. However, a manufacturing mask 
option determines whether the falling edge or the actual 
low level of the IRQ pin is sensed to indicate an interrupt. 

EDGE-SENSITIVE OPTION 

When the IRQ pin is pulled low, the internal interrupt 
request latch is set. Prior to each instruction fetch, this 
interrupt request latch is tested. If its output is low, an 
interrupt sequence is initiated at the end of the current 
instruction, provided the interrupt mask is cleared. Figure 
6 contains a flowchart that illustrates both the reset and 
interrupt sequences. 

The interrupt sequence consists of one cycle during 
which: 

The interrupt request latch is cleared; 

The interrupt mode flags are selected; 

The program counter (PC) is saved on the stack; 

The interrupt mask is set; and 

The IRQ vector jump address is loaded into the PC. 

The IRQ vector jump address is $FFC-$FFD in the single- 
chip mode and $FF8-$FF9 in the self-check mode. The 
contents of these locations are not decoded as an address 
to which the PC should jump. Instead, they are decoded 
like any other EPROM program word. So, it is essential 



that the vector contents specify a J MP instruction in ad- 
dition to the starting address of the interrupt service rou- 
tine. If required, this routine should save the values of 
the accumulator and the X and Y registers, since these 
values are not stored on the stack. 

Internal processing of the interrupt continues until a 
return from interrupt (RTI) instruction is processed. Dur- 
ing RTI the interrupt mask is cleared and the program 
mode flags are selected. The next instruction of the pro- 
gram is then fetched and executed. 

When the interrupt was initially detected and the in- 
terrupt sequence started, the interrupt request latch was 
cleared so that the next interrupt could be detected. These 
steps occurred even as the first interrupt was being serv- 
iced. However, even though the second interrupt edge 
set the interrupt request latch during the first interrupt's 
processing, the second interrupt's sequence can not be- 
gin until completion of the interrupt service routine for 
the first interrupt. Completion of an interrupt service rou- 
tine is always accomplished using an RTI instruction to 
return to the main program. The interrupt mask, which 
is not directly available to the programmer, is cleared 
during the last cycle of the RTI instruction. 

LEVEL-SENSITIVE OPTION 

Actual operation of the level-sensitive and edge-sen- 
sitive options are similar. However, the level-sensitive 
option does not have an interrupt request latch. Since 
there is no interrupt request latch, the logic level of the 




0 — OORl 
1 — » INTERRUPT MASK 
0 — * INTERRUPT REQUEST 
LATCH (EDGE 
SENSITIVE OPTION) 
»FF — ICR 
S00 — TSCR 
JFF— • PRESCALER 



SELECT 
PROGRAM 
MODE 
FLAGS 




LOAD PROGRAM 
COUNTER FROM 
. RESET VECTOR 
LOCATION 
SFFEISFFF 






CHECK 
LEVE 

m 


LOGIC 
OF 









Figure 6. Reset and Interrupt Flowchart 



MOTOROLA MICROPROCESSOR DATA 
3-303 



MC6804J2 



IRQ pin is Checked to detect the interrupt. Also, in the 
interrupt sequence there is no need to clear the interrupt 
request latch. These differences are shown in Figure 6. 



Maximum interrupt response time is six machine cycles. 
This includes five cycles for the longest instruction plus 
one for stacking the PC and switching flags. 



POWERUP AND TIMING 

During the powerup sequence, the interrupt mask is 
closed. This precludes any false interrupts. The PC is also 
loaded with the appropriate restart vector (jump instruc- 
tion). 

To open the interrupt mask, the user should do a JSR 
to an