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XT-4000E 


Document 1011004 
Revision B 
September 1988 


Product Specification 
and 

OEM Manual 




REVISION RECORD 


Revision 

Date Published 

Revised Contents 

01 

February 1987 

Preliminary Issue 

A 

July 1987 

General Changes 

B 

September 1988 

General Changes 


Document No : 1011004 


WARRANTY 

Maxtor warrants the XT-4000E Family of disk drives against defects in materials and workmanship for 
a period of twelve months, for the original purchaser. Direct any questions regarding the warranty to 
your Maxtor Sales Representative. Maxtor maintains Customer Service Centers for the re- 
pair/reconditioning of all Maxtor products. Direct all requests for repair to the Maxtor Service Center 
in San Jose. This assures you of the fastest possible service. 


APPROVALS 

File Number E87276 
File Number LR54048 
Registration Number 37230G 


Maxtor Corporation 

Technical Publications 
21 1 River Oaks Parkway 
San Jose, California 95134-1913 
Telephone: (408) 432-1700 
Telex: 171074 
FAX: (408)433-0457 


REGULATORY 

UL Recognition obtained: 

CSA Certification obtained: 

VDE Recognition obtained: 

Address comments concerning this manual to: 







The contents of this manual may be revised without prior notice. 

© Copyright 1987 by Maxtor Corporation, San Jose, California, USA. All rights reserved 



PREFACE 


Maxtor reserves the right to make changes and/or improvements to its products without incurring 
any obligation to incorporate such changes or improvements in units previously sold or shipped. 

Maxtor publishes descriptive Brochures and Data Sheets, an OEM Manual, and a Quick Reference 
Guide for each product line. In addition, important changes to a product are conveyed in the form of a 
Technical Bulletin sent to all product customers of record. Changes that affect the content of any 
manual are covered by publishing addendum or revisions to the affected manual. 




XT-4000E Product Specification & OEM Manual 


TABLE OF CONTENTS 

1.0 INTRODUCTION 1 

1 . 1 General Description 1 

1 .2 Drive Features 2 

2.0 PRODUCT SPECIFICATIONS 3 

2 . 1 Performance Specifications 3 

2 . 2 Functional Specifications 3 

2.3 Physical Dimensions 4 

2.4 Environmental Limits 4 

2.5 DC Power Requirements 5 

2.6 Reliability Specifications 6 

2.7 Error Rates 7 

2.6 Standards and Regulations 7 

3.0 FUNCTIONAL CHARACTERISTICS 9 

3.1 Read/Write and Control Electronics 9 

3 . 2 Drive M echanism 10 

3.3 Air Filtration System 10 

3.4 Positioning Mechanism 1 1 

3.5 Read/Write Heads and Disks 12 

4.0 THEORY OF OPERATION 14 

4.1 Spindle Motor Control. i 15 

4.1.1 Hardware Configuration 1 6 

4.1 .2 Spindle Modes of Operation 1 7 

4. 2 Actuator Control 19 

4.2.1 Servo Pattern 20 

4.2.2 Block Description 21 

A Read Amplifier/Pulse Detector 23 

B Phase-Locked Oscillator 24 

C Synchronization Detector and Servo Data Separator 24 

D Data and Index Decoder 24 

E Hard Sector Control 25 

F Position Demodulator Control 25 

G Main Servo Control Loop 25 

H Microprocessor Controller 26 

I Jumpers 26 

4.3 Read/Write Channel 27 

4.3.1 HDA Flex Circuit Interface 27 

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TABLE OF CONTENTS 

A Preamplifier Integrated Circuit 27 

B Power 27 

C Head Selection 27 

D Read Signal 31 

E WRITE Mode and Write Unsafe 31 

4.3.2 Pulse Detector 31 

A Signal Amplification Using AGC 32 

B Signai Filtering 32 

C Puise Qualification/Peak Detection 32 

D Write-to-Read and Head Switch Recovery 34 

4.3.3 Clock Recovery and Decoding 35 

A Data Separator 36 

B ENDEC, READ Mode 37 

4.3.4 Write Path and Encoding 37 

A Soft Sector WRITE 38 

B Hard Sector WRITE 38 

C Encoding Data 39 

D Encoding Rules 39 

4.3.5 Address Mark Detection 39 

5.0 FUNCTIONAL OPERATION 41 

5 . 1 Power Up Sequence 41 

5.2 Drive Selection 42 

5.3 Drive Termination 43 

6.0 ELECTRICAL INTERFACE 44 

6.1 Control Input Lines 51 

6.1 .1 HEAD SELECT 20, 21 , 22, and 23 52 

6.1.2 WRITE GATE 52 

6.1.3 READ GATE 56 

6.1.4 COMMAND DATA 56 

6.1.5 TRANSFER REQ 61 

6.1.6 ADDRESS MARK ENABLE 62 

A Soft Sector Mode Only 62 

B Hard and Soft Sector Modes 63 

6.2 Control Output Lines 63 

6.2.1 DRIVE SELECTED 63 

6.2.2 READY 64 

6.2.3 CONFIG-STATUS DATA 64 

6.2.4 TRANSFER ACK 70 

6.2.5 ATTENTION 70 


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TABLE OF CONTENTS 

6.2.6 INDEX 71 

6.2.7 ADDRESS MARK FOUND (Soft Sector) 71 

6.2.8 SECTOR MARK (Hard Sector) 72 

6.2.9 COMMAND COMPLETE 73 

6.3 Spindle Synchronization Control Option 73 

6.4 Data Transfer Lines 74 

6.4.1 NRZ READ DATA 75 

6.4.2 NRZ WRITE DATA 75 

6.4.3 READ/REFERENCE CLOCK 76 

6.4.4 WRITE CLOCK 77 

7.0 PHYSICAL INTERFACE 7 8 

7.1 J1/P1 Connector 79 

7.2 J2/P2 Connector 80 

7.3 J3/P3 Connector 81 

7.4 J4/P4 Frame Ground Connector 82 

7.5 J6/P6 Auxiliary Connector 82 

8.0 PHYSICAL SPECIFICATIONS 84 

8.1 Mounting Orientation 84 

8.2 Mounting Holes 84 

8.3 Physical Dimensions 85 

8.4 Shipping Requirements 87 

8.5 Removable Faceplate 87 

9.0 PCB JUMPER OPTIONS 8 8 

9.1 Drive Address Selection Jumper 88 

9.2 Data Head Selection Jumpers (JP32-JP36) 90 

9.3 Write Protect Selection Jumper (JP14) 91 

9.4 Option for Sequential Spindle Motor Spinup Jumper (JP6) 91 

9.5 Test Jumpers (JP1 , JP41 , JP42) 91 

9.6 Hard Sector Configuration Jumpers (JP1 6-29) 91 

10.0 MEDIUM DEFECTS AND ERRORS 93 

APPENDIX: UNITS OF MEASURE 9 5 

GLOSSARY 9 7 


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FIGURES 

Figure 1 Typical 1 2 Volt Current Power Up Cycle 6 

Figure 2 Air Filtration System 1 1 

Figure 3 Head Positioning System 12 

Figure 4 General Block Diagram 15 

Figures Spindle Control Hardware 16 

Figure 6 Spindle Control Flow Chart 17 

Figure 7 Servo Pattern and Read-Back Signal 1 21 

Figure 8 Servo System 22 

Figure 9 Main Servo Control Loop 23 

Figure 1 0 Head and Drive Selection 28 

Figure 1 1 Preamplifier Head Selection and Read-Back Signal 29 

Figure 1 2 Head Selection Map 30 

Figure 13 Peak Detection 33 

Figure 14 Pulse Detector 35 

Figure 1 5 ENDEC/Data Separator READ Mode 36 

Figure 16 Write Path 38 

Figure 17 Power Up Sequence (Jumper JP6 Open)... 41 

Figure 18 Drive Select Circuit 42 

Figure 19 Control Cable J1/P1 Signals 45 

Figure 20 Data Cable J2/P2 Signals 47 

Figure 21 Typical Auxiliary Cable and Spindle Synchronization Connection 49 

Figure 22 Typical Multidrive Connection 51 

Figure 23 Control Signals, Driver/Receiver Combination 52 

Figure 24 Soft Sector Address Mark, WRITE GATE, PLO Synchronous Format Timing 53 

Figure 25 Hard Sector WRITE GATE, PLO Synchronous Format Timing, Using ADDRESS MARK 

ENABLE 54 

Figure 26 WRITE GATE Termination 55 

Figure 27 Hard Sector WRITE GATE, PLO Synchronous Format Timing 55 

Figure 28 One Bit T ransfer Timing — ^To Drive 58 

Figure 29 COMMAND DATA Word Structure 58 

Figure 30 One Bit Transfer Timing — From Drive 62 

Figure 31 Write Address Mark Timing 63 

Figure 32 CONFIG-STATUS DATA Word Structure 64 

Figure 33 Typical Serial Operation(s) 65 

Figure 34 INDEX Timing 71 

Figure 35 Read Address Mark Timing (Hard Sector) 72 

Figure 36 Sector Pulse Timing (Hard Sector) 73 

Figure 37 Data Line Driver/Receiver Combination 74 

Figure 38 NRZ READ/WRITE DATA Timings 76 

Figure 39 Interface Connector Physical Location 79 

Figure 40 J1 Connector Dimensions 80 

Figure 41 J2 Connector Dimensions 81 

Figure 42 J3 Connector (Drive PCB Solder Side) 81 

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FiGURES 

Figure 43 Mechanical Outline and Mounting Hole Locations 85 

Figure 44 Mechanical Outline, Bottom and Side Views 86 

Figure 45 Removable Faceplate 87 

Figure 46 Drive Jumper Options 89 

Figure 47 Defect List Format 94 


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TABLES 

T able 1 Performance Specifications 3 

Table 2 Functional Specifications 4 

Table 3 Physical Dimensions 4 

Table 4 Environmental Limits 5 

Table 5 DC Power Requirements 5 

Table 6 Reliability Specifications 7 

Table 7 Error Rates 7 

Table 8 Drive Selection Matrix 43 

Table 9 Control Cable J1/P1 Pin Assignments 46 

Table 1 0 Data Cable J2/P2 Pin Assignments 48 

Table 1 1 Auxiliary Cable (J6) Pin Assignments 50 

Table 1 2 COMMAND DATA Definition 57 

Table 13 REQUEST STATUS Modifier Bits 59 

Table 14 REQUEST CONFIGURATION Modifier Bits 60 

Table 15 CONTROL Command Modifier Bits 60 

Table 16 TRACK OFFSET Command Modifier Bits 61 

Table 17 Standard Status Response Bits 66 

Table 18 Vendor Unique Status Response Bits 67 

Table 19 Motor Status 68 

Table 20 SEEK Calibration Error Code 68 

Table 21 General Configuration Response Bits 69 

Table 22 Specific Configuration Response Bits 70 

Table 23 Power Connector (J3) Requirements 82 

Table 24 J6 Auxiliary Signal Cable Pin Assignments 83 

Table 25 Drive Select Jumpers 88 

Table 26 Jumper Selections 90 

Table 27 Data Head Number Selection Jumpers 90 

Table 28 Test Pin Jumpers 91 

Table 29 Customer Selectable Jumpers 92 

Table 30 Maximum Number of Defects 93 


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1.0 INTRODUCTION 


1.1 General DESCRiPTiON 

The XT-4000E™ Family disk drives are high capacity, high performance random access 
storage devices using from five to eight nonremovable 5V4-inch disks as storage media. 
Each disk surface employs one moveable head to access 1 ,224 data tracks. The total 
unformatted capacity of the drive ranges from 179 to 385 megabytes. 

The drive incorporates the Enhanced Small Device Interface (ESDI) high performance 
5V4-inch standard. Among the resultant benefits are a 1 0 megabit per second transfer 
rate, status and configuration reporting across the interface, and nonreturn to zero (NRZ) 
data transfer. 

Low cost and high performance are achieved through the use of a rotary voice coil actua- 
tor and a closed loop servo system using a dedicated servo surface. The innovative 
MAXTORQ™ rotary voice coil actuator provides an average access time of 16 millisec- 
onds, typical, for the eight-disk model (14 milliseconds, typical, for the five-disk model). 
Track-to-track access time is 2.5 milliseconds for all models. This level of performance is 
usually achieved only with larger, higher powered, linear actuators. The closed loop 
servo system and dedicated servo surface combine to allow state of the art recording 
densities (1,070 tracks per inch, and 14,043 flux changes per inch) in a 5V4-inch pack- 
age. 

High capacity is achieved through a balanced combination of high areal recording den- 
sity, mn-length limited (RLL) data encoding techniques, and high density packaging 
techniques. Maxtor's advanced MAXPAK™ electronic packaging techniques use sur- 
face mount devices to aliow all electronic circuitry to fit on one printed circuit board (PCB). 
Advanced 3380 Whitney-type flexures allow closer spacing of disks, and therefore ailow 
a higher number of disks in a 5V4-inch package. Maxtor's unique integrated drive mo- 
tor/spindle design allows a deeper head/disk assembly (HDA) casting than conventional 
designs, thus permitting more disks to be used. 

The electrical interface is compatible with the industry standards established by the ESDI 
committee. The same basic drive/HDA is also available with a Small Computer System In- 
terface (SCSI). The drive size and mounting conform to the industry standard 5V4-inch 
floppy and Winchester disk drives, and the drive uses the same direct current (DC) volt- 
ages and connectors. No AC power is required. 


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1.2 DRiVE FEATURES 

The key features of the drive are as follows: 

• storage capacity of 1 79 to 385 megabytes unformatted 

• same physical size and mounting as standard floppy disk drives 

• same control and data cabling as ST506/41 2 interface drives 

• same DC voltages as standard floppy disk drives 

• no AC voltage required 

• rotary voice coil actuator and closed loop servo system for fast, accurate head posi- 
tioning 

• microprocessor-controiled servo for fast access time, high reliability, and high density 
functional packaging 

• 10.0 megabit per second transfer rate 

• ESDI interface 

• track capacity of 20,940 bytes, unformatted 

• thin film metallic media for higher bit density and resolution plus improved durability 

• single PCB for improved reliability 

• automatic actuator lock 

• brushless DC spindle motor inside disk hub 

• microprocessor-controlled spindle motor for precision speed control (±0.1%) under 
all load conditions 

• dynamic braking during power down cycle 

• user selectable hard or soft sectors 

• synchronization of spindle motors for parallel data transfer of multiple drives 


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2.0 PRODUCT SPECIFICATIONS 


This section lists all specifications for the XT-4000E Family disk drives. 


2.1 Performance Specifications 


Table 1, Performance Specifications, lists the performance specifications for the drive. 



XT-41 70 E 

XT-4380E 

Capacity, Unformatted 



Per Drive (Mbytes) 

179.45 

384.53 

Per Surface (Mbytes) 

25.64 

25.64 

Per Track (bytes) (minimum) 

20,940 

20,940 

Capacity, Formatted (512 bytes/sector) 



Per Drive (Mbytes) 

157.93 

338.4 

Per Surface (Mbytes) 

22.56 

22.56 

Per Track (Mbytes) 

18,432 

18,432 

Sector/Track 

36 

36 

Transfer Rate, Mbits/Sec 

10.0 

10.0 

Typical Seek Time, msec* 



Average 

14 

16 

Track-to-Track 

2.5 

2.5 

Full Stroke 

27 

29 

Max Seek Time, msec* 



Average 

16 

18 

Track-to-Track 

3 

3 

Full Stroke 

34 

34 


* Includes Settling 


Table 1 

Performance Specifications 


2.2 Functional Specifications 


Table 2, Functional Specifications, lists the functional specifications for the drive. 


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Rotational Speed (rpm)* 
Average Latency 
Recording Density (bpi) 
Rux Density (fci) 

Track Density (tpi) 

Cylinders 

Tracks 

Sectors (36 sectors/track) 
Data Heads 
Servo Heads 
Disks 


XT-41 TOE 

XT-4380E 

3,600 

3,600 

8.33 

8.33 

21,064 

21,064 

14,043 

14,043 

1,070 

1,070 

1,224 

1,224 

8568 

18,360 

308,448 

660,960 

7 

15 

1 

1 

5 

8 


'Accurate to ± 0.1% 


Table 2 

Functional Specifications 


2.3 Physical Dimensions 


Table 3, Physical Dimensions, lists the physical dimensions of the drive. 


HEIGHT 

= 3.25 in. (82.55 mm) 

WIDTH 

= 5.75 in. (146.05 mm) 

DEPTH 

= 8.20 in. (208.28 mm) 

WEIGHT 

= 7.1 lb (3.2 kg) 

SHIPPING WEIGHT 

= 9.3 lb (4.2 kg) 

HEAT DISSIPATION 

= 27 W Typical, 

35 W Max. 


Table 3 

Physical Dimensions 


2.4 Environmental Limits 

Table 4, Environmental Limits, lists the environmental limits of the drive. 


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OPERATING 

NONOPERATING 

AMBIENT TEMPERATURE 

50°Fto122^F(10<='C to50°C) 

-40° F to 140° F (-40° C to 60° C) 

MAXIMUM TEMPERATURE 
GRADIENT 

18’’ F/hr (10° C/hr), 

Below Condensation 

18° F/hr (10° C/hr), 

Below Condensation 

RELATIVE HUMIDITY 

8 to 80% Noncondensing with 

Max Gradient of 

10% /hr 

8 to 80% Noncondensing with 

Max Gradient of 

10% /hr 

MAXIMUM ELEVATION 

10,000 ft 

-1,000 ft to 40,000 ft 

VIBRATION (INPUTS TO 
FRAME OF DRIVE) 

All axes, 5-25 Hz, 0.006 in. P-P 
25-500 Hz, 0.20 G Peak Acceleration 

All axes, 5-31 hz, 0.02 inches P-P 
31-500 Hz, 1.0 G Peak Acceleration 

SHOCK (INPUTS TO 
FRAME OF DRIVE) 

2 G with 1 1 msec Pulse Width, Half 
Sine Wave, (all axes) 

20 G MVn 1 1 msec Pulse Width, Half 
Sine Wave, (all axes) 


Tabie 4 

Environmentai Limits 


2.5 DC POWER REQUiREMENTS 

Table 5, DC Power Requirements, lists the DC power requirements of the drive. 


VOLTAGE (NOMINAL) 

+12 V DC 

+5V DC 

Regulation 

±5% 

±5% 

Current (Typical) 

1.5 A 

1.7 A 

Current (Maximum) 

4.5 A* 

1.9 A 

Ripple (Maximum, P-P) 

120 mV 

50 mV 


* Potential Current Surge for 1st 100 to 200 p^sec to 
Charge Capacitors Dependent on Power Supply 
at Power On 


Table 5 

DC Power Requirements 


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NOTE: WHEN A FULL-LENGTH SEEK IS DONE, ONE ADDITIONAL 
AMP IS REQUIRED FOR A DURATION OF 15 MILLISECONDS 


Figure 1 

Typical 12 Volt Current Power Up Cycle 


2.6 Reliability Specifications 

Table 6, Reliability Specifications, lists the reliability specifications for the drive. 


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MTBF 

PM 

MTTR 

COMPONENT DESIGN UFE 


30,000 POH, Typical Usage 
Not Required 
30 Minutes 
5 Years 


Tabie 6 

Reiiabiiity Specifications 


2.7 Error Rates 


Table 7, Error Rates, lists the error rate specifications for the drive. 


SOFT READ ERRORS 

10 per 10 Bits Read 

HARD READ ERRORS* 

10 per 10 ^3 Bits Read 

SEEK ERRORS 

10 per 10' Seeks 


‘Not Recoverable Within 16 Retries 


Table 7 
Error Rates 


2.6 Standards and Regulations 

The Maxtor XT-4000E Family disk drives satisfy the following standards and regulations: 

UNDERWRITERS LABORATORIES (UL) = United States safety: UL 478, Standard for 
Safety, Electronic Processing Units and Systems. 

CANADIAN STANDARDS ASSOCIATION (CSA) = Canadian safety: CSA C22.2 No. 220, 
1986, Information Processing and Business Equipment (Consumer and Commercial 
Products). 

VERBAND DEUTSCHER ELECTROTECHNIKER (VDE) = German safety: VDE 
0806/8.81 , Safety of Office Appliances and Business Equipment. 

INTERNATIONAL ELECTROTECHNICAL COMMISSION (lEC) = International safety 
commission: lEC 950 (formerly 380), Safety of Information Technology Equipment. 


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FEDERAL COMMUNICATIONS COMMISSION (FCC) * United States radiation emis- 
sions; Part 15, Subpart J, Class B Consumer Computing Devices. 

CAUTION: Connections between equipment must be made with shieided cabies, and 
a shieided power cord nujst me used to connect AC power to the unit. 

CAUTION: This equipment generates and uses radio frequency energy, and may 
cause interference to radio and teievisbn reception if not installed and used in strict ac- 
cordance with the instructions in this manual and in XT-4000S Service Manual . 

The drive has been tested and found to comply with the limits for a Class B computing 
device, in accordance with the specifications in Subpart J of Part 15 of FCC Rules, which 
are designed to provide reasonable protection against radio and television reception 
interference in a residential installation. However, there is no guarantee that interference 
will not occur in a particular installation. If this equipment does cause interference to radio 
or television reception, which can be determined by turning the equipment off and on, 
the user is encouraged to try to correct the interference using one or more of the 
following measures: 

• reorient the receiving antenna 

• reorient the computer with respect to the receiver 

• move the computer away from the receiver 

• plug the computer into a different outlet, so that the computer and receiver are on 
different branch circuits 

If necessary, consult the dealer, or an experience radio/television technician, for addi- 
tional suggestions. You may find the FCC booklet How to identify and Resolve Radio TV 
Interference Problems helpful. This booklet is available from the United States Govern- 
ment Printing Office, Washington, D.C., 20402, stock number 004-000-00345-4. 

Maxtor is not responsible for any radio or television interference caused by unautho- 
rized modifications to the drive. It is the responsibility of the user to correct such interfer- 
ence. 


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3.0 FUNCTIONAL CHARACTERISTICS 

The XT-4000E Family disk drive consists of read/write and control electronics, read/write 
heads, a servo head, a head positioning actuator, media, and an air filtration system. The 
components perform the following functions: 

• interpret and generate control signals 

• position the heads over the desired track 

• read and write data 

• provide a contamination-free environment 

3.1 Read/Write and Control Electronics 

Drive electronics are packaged on a single PCB. This board, which includes two micro- 
processors, performs the following functions: 

• reading/writing of data 

• index detection 

• head positioning 

• head selection 

• drive selection 

• fault detection 

• voice coil actuator drive circuitry 

• track zero detection 

• recalibration to track zero on power up 

• track position counter 

• power and speed control for spindle drive motor 

• braking for spindle drive motor 

• drive up-to-speed indication circuit 

• monitoring for write fault conditions 

• control of ail internal timing 

• generation of seek complete signals 

• RLL encoding/decoding 

• data separation 

• address mark detection (soft sector) 

• sector detection (hard sector) 

• spindle synchronization 


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3.2 DRiVE MECHANiSM 

A brushless DC drive motor, contained within the spindle hub, rotates the spindle at 
3,600 revolutions per minute. The spindle is direct driven, with no belt or pulleys being 
used. Dynamic braking is used to quickly stop the spindle motor when power is removed. 
The HDA is shock mounted to minimize transmission of vibration through the chassis or 
frame. 


3.3 Air Filtration System 

The disks and read/write heads are assembled in an ultra clean-air environment and then 
seaied within the moduie. The module contains an internai absolute filter, mounted in- 
side the casting, to provide constant internal air fiitration (see Figure 2, Air Filtration Sys- 
tem). A second fiiter, located on top of the base casting, permits pressure equalization 
between internai and ambient air. 


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RECIRCULATING FILTER 


ROTARY 
VOICE 
COIL V 



AIR FLOW PATH 


Figure 2 

Air Fiitration System 


3.4 POSmONiNG MECHANiSM 

The read/write heads are mounted on a head arm assembly, which is then mounted to a 
bail bearing supported shaft. The voice coil, an integral part of the head/arm assembly, 
lies inside the magnet housing when installed in the drive. Current from the power ampli- 
fier, controlled by the servo system, causes a magnetic field in the voice coil which either 
aids or opposes the field around the permanent magnets. This reaction causes the voice 
coil to move within the magnetic field. Since the head arm assemblies are mounted on 
the voice coil, the voice coil movement is translated through the pivot point directly to the 
heads, and positions the head over the desired cylinder. See Figure 3, Head Positioning 
System. 


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READ/WRITE HEADS 


SERVO 

HEAD 


Figure 3 

Head Positioning System 

Actuator movement is controlled by the servo feedback signal from the servo head. The 
servo head is located on the lower surface of the fourth disk from the top, where servo 
information is prewritten at the factory. This servo information is used as a control signal 
for the actuator to provide track-crossing signals during a seek operation, track-following 
signals during on cylinder operation, and timing information, such as index, sector pulses 
(hard sector), and servo clock. 

3.5 Read/Write Heads and Disks 

The drive employs thin film heads and Whitney-type flexures. This configuration of sliders 
and flexures provides improved aerodynamic stability, superior head/disk compliance, 
and a higher frequency response than conventional ferrite heads. 

The medium uses thin metallic film deposited on 130 millimeter diameter aluminum sub- 
strates. The metallic surface, together with the low load force/low mass Whitney-type 
heads, permit highly reliable contact start/stop operation. The metallic recording film 
yields high amplitude signals, and very high resolution performance compared to con- 
ventional oxide coated media. The metallic medium also provides a highly abrasion- 


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resistant surface, decreasing the potential for damage caused by shipping shock and vi- 
bration. 

Data on each of the data surfaces is read by one of fifteen read/write heads, each of 
which accesses 1,224 tracks. There is one surface dedicated to servo information in 
each drive. 


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4.0 THEORY OF OPERATION 

The drive PCB assembly provides four major functions, 1) spindle motor control; 2) 
actuator control for head/positioning; 3) the read and write data channel; and 4) ESDI 
hardware and protocol implementation. In addition, power conditioning and monitoring is 
provided. Figure 4, General Block Diagram, shows the organization of these functions 
and the major subsections of each. The following paragraphs describe each of these in 
more detail. 


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L j 


Figure 4 

General Block Diagram 


4.1 Spindle Motor Control 

The spindle motor in the drive uses a three-phase delta-wound brushless DC motor lo- 
cated inside the hub. Commutation is determined by three hall effect sensors which are 
mounted on a flex circuit at the bottom of the casting. These hall effect sensors sense 
magnets under the spindle motor. 


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4.1.1 Hardware Configuration 

Figure 5, Spindle Control Hardware, presents a component block diagram of the spindle 
system. The hardware provides the functions described below. The Z8 microcontroller is 
the central element in this diagram, serving to coordinate, direct, and control all of the ac- 
tivity of the spindle. 



Figure 5 

Spindie Controi Hardware 


The output of the hall sensors is mapped by the Z8 microcontroller into a three phase 
commutation sequence. This sequence continuously commutates the in-the-hub four- 
pole three phase spindle drive motor through the three phase H-bridge power module 
(six power transistors). The current through the motor is monitored by the voltage across 
the 0.1 ohm sense resistor. Current control is obtained by comparing the sense voltage 
with the digital analog converter (DAC) output at a high gain op-amp, and then closing the 
analog control loop through the (lower) power transistors; an integrating capacitor around 
the op-amp stabilizes the loop. The net effect of this loop is to desensitize the circuit to 
variations in the power transistor parameters. 


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Additional analog circuitry shown in Figure 5, Spindle Control Hardware, provides current 
limiting of the motor current, and provides graceful shutdown (homing of the actuator and 
dynamic braking of the spindle) in the event of loss of power, or if the spindle motor is 
turned off by a STOP command in remote mode. 


4.1.2 Spindle Modes of Operation 

Figure 6, Spindle Control Flow Chart, is a diagrammatic description of the in-line/real-time 
microcontroller diagnostics for the spindle control system. 



The flowchart describes the sequence of microcontroller activity required during each of 
the spindle modes of operation; this sequence provides a detailed overview of the di- 
verse control and auxiliary functions of the spindle. The sequence, programmed as 
algorithms in the microcontroller, provides three basic modes of operation for the drive: 
START mode, RUN mode, and SYNCSP (synchronous spindle) mode. 


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START Mode : At power up with the spindle at rest, full current (limited to 4.0 amps) is ap- 
plied to the spindle motor. Progressive diagnostic and timing checks are performed to 
detect a spindle drive malfunction and to take corrective action as follows: 

• Detect a Stalled Spindle Motor 

The hall sensors are tested for (commutation) motion. If one second elapses without 
motion, either a "stuck” spindle or a power module failure is indicated; actuator dither 
is invoked to free up the spindle, and STATUS 2 is posted. At the end of two sec- 
onds of dither, motion is checked again and if not detected, STATUS 2 is posted and 
the spindle aborts (powers down). 

• Detect a Hall Sensor Failure 

The states of the hall sensors are continuously checked at commutation until velocity 
lock on. If an illegal state occurs in two consecutive revolutions, STATUS 1 is posted 
and the spindle aborts. 

• Check 1 ,000 revolutions per minute at 7 Seconds 

The commutation is timed for 1 ,000 revolutions per minute to occur within 7 seconds. 
If 1 ,000 revolutions per minute do not occur, this indicates excessive drag forces 
from the head or bearings, or a motor/driver failure; STATUS 3 is posted and the 
spindle aborts. 

• Check 3,000 revolutions per minute at 21 Seconds: 

The commutation is timed for 3,000 revolutions per minute to occur within 21 sec- 
onds. If above 3,000 revolutions per minute, the spindle tries to achieve 3,600 rev- 
olutions per minute; in contrast to the stalled spindle motor and 1 ,000 revolutions per 
minute in 7 seconds checks, a sufficient back electromotive force from the motor has 
reduced the voltage overhead across the drivers in the power module such that the 
reduced power dissipation of the drivers allows multiple retries. (A RETRY is per- 
formed beyond this point for any return into the START mode.) 

RUN Mode : Upon entering RUN mode, the microcontroller sequentially enters a) an 
adaptive routine to compute the quiescent drag force of the bearing/disks and to com- 
pute the dynamic system constant from the DAC input to motor velocity; b) an electronic 
commutation routine; and c) a velocity lock-on-routine (in thirty revolutions) to insure 
(monitored) velocity operation of 3,600 revolutions per minute ±0.1%. The system is 
then given a STATUS 0 identification of normai mode operation. If a failure occurs at any 
point between a) and c), the system goes into RETRY mode (into START mode) and is 
monitored for five successive failures without velocity iock-on before ABORT. 

At velocity lock-on, a READY signal is posted to the interface microcontroller to signal that 
the spindle is at recording veiocity (3,600 revolutions per minute). 


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A feature of the drive is the capability of synchronous spindle operation (spindle locked 
operation) in which INDEX lock is achieved between a master drive and up to forty eight 
slave drives. This feature allows serial data streams to operate in parallel and thereby 
multiplies the system data transfer rate (drive-to-host computer) by the number of slave 
drives. 

When the drive is in RUN mode, the code of the microcontroller provides two simultane- 
ous functions: 1) generation of a MAPOUT (master pulse out); and 2) search for a MAPIN 
(master pulse in). Normal operation implies the lack of a MAPIN pulse, and while in this 
mode, the drive defaults to a master drive designation. 

If a MAPIN pulse is detected, the drive is posted with a slave drive designation (MAPIN 
available) and the drive goes into SYNCSP mode. 

SYNCSP Mode : Upon detection of MAPIN by the microcontroller, the slave drive enters 
a high-speed CAPTURE mode to bring the MAPIN pulse to the MAP (master pulse) win- 
dow. Normal velocity control is in effect during this operation (NORMAL mode). 

As MAPIN approaches the outer boundaries of the MAP window, a velocity adjustment is 
made to the slave drive to return the drive to normal velocity prior to entering the MAP 
window and subsequent phase lock. Within the MAP window, bounds are tested for ve- 
locity error and phase error. When the two are within their tolerance zones, the system 
switches to a phase controlled configuration, wherein the slave drive is locked to the 
MAPIN pulse, and synchronous spindle operation (spindle locked) STATUS 8 is posted. 

In the SYNCSP mode, the velocity and phase error are constantly monitored to assure 
velocity and INDEX phase tolerances as follows: 
velocity: 3,600 revolutions per minute ±0.1% 
master INDEX/slave INDEX lock ±40 microseconds 

If the SYNCSP lock error (MAPERR) is out of tolerance (STATUS 10), the system reverts 
to CAPTURE mode. If the velocity is out of tolerance (spindle control lost), RETRIES are 
performed via START mode (recalibration of the adaptive loop) and if SYNCSP is not 
achieved (with MAPIN available), a SYNCSP inoperative condition error (STATUS 10) is 
posted and the system attempts operation in NORMAL mode. 


4.2 ACTUATOR Control 

This section describes the servo system used in the XT-4000E Family disk drives. The 
same servo system is used for both models, with small modifications made to accom- 
modate the different number of heads unique to each model. Two functions are pro- 
vided, precision track following, and carriage motion to specific tracks in response to in- 


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terface commands. Typical track-to-track and average access times are 14 milliseconds 
for the XT-4170E and 16 milliseconds for the XT-4380E. 

A dedicated servo surface and quadrature servo pattern is used. This servo incorporates 
evolutionary and detail improvements over prior generations of Maxtor servos. 

The level of electronics integration is very high. Three custom analog integrated circuits, 
an actuator driver integrated circuit, and a standard cell servo logic chip (SLC), are used to 
implement the servo functions. In addition, the servo uses a microcontroller, which is 
shared with the drive interfacing function. 


4.2.1 Servo Pattern 

The servo pattern consists of 3,808 servo frames per track with twenty-two servo clock 
intervals per frame. This yields a 228 kilohertz frame rate for the system. Four dibit pulses 
encode the quadrature position information, and one pulse each is used for syn- 
chronization and data (see Figure 7, Servo Pattern and Read-Back Signal I). When the 
data pulse is present, the frame has a logical "1 " value. When the pulse is not present, 
the frame has a logical "0" value. This serial pulse stream is decoded in 16-bit words, with 
parity, and is used to encode the absolute track address, index, and configuration data 
used by the drive and the servo. Thus, the words are repeated 238 times per revolution 
for a word rate of 14.3 kilowords per second. The synchronization pulse, which follows 
the data pulse, is present in every frame and is used to synchronize to the servo pattern. 
The first pair of position pulses, A and B, are used for positioning on even numbered data 
tracks. The second pair of pulses, C and D, are used for positioning on odd numbered 
tracks. 


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□C 

LU 

CD 


^5 o 

ccQ CO 


< o 
S >“ 

Q CO 


S >- 

Q CO 




Figure 7 

Servo Pattern and Read-Back Signal I 


4.2.2 Block Description 

Refer to Figure 8, Servo System, and Figure 9. Main Servo Loop, when reading the fol- 
lowing descriptions. 


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Figure 8 
Servo System 


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POSITION 

DEMODULATOR GAIN ACTUATOR 



A READ AMPLIFIER/PULSE DETECTOR 

The read amplifier and pulse detector provides automatic gain control (AGO) a buffer am- 
plifier for the servo filter and a pulse detector for the dibit pulses. The raw servo signal 
from the preamplifier enters the read amplifier and is applied to the AGO amplifier. The 
AGO loop is closed through the position demodulator. The amplified and normalized 
servo signal then passes through a filter for noise reduction and then on to the pulse de- 
tector and peak detector. 

The pulse detector detects the zero crossing between the positive and negative going 
portions of the dibit pulses. The digital output of this detector is used to decode data 
pulses and issued as the input for the phase-locked oscillator. The peak detector sam- 
ples the peak values of the position pulses and establishes a reference baseline from 
which to measure these peak values. The discharge current of the peak detector is 
switchable to allow the use of a long time constant (peak hold) during servoing, and a 
shorter time constant which is used to facilitate lock up of the AGC loop at power on. 


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B PHASE-LOCKED OSCiLLATOR 

The phase-locked oscillator (PLO) harmonically locks to the incoming pulse stream from 
the pulse detector. During synchronization the oscillator locks in phase and frequency 
mode to a reference clock generated in the SLC. Also, in the SLC, the oscillator output is 
divided and used to generate the 5 megahertz master clock from which timing gates are 
derived. This clock is divided again to provide the 2.5 megahertz feedback clock for the 
PLO. The fundamental oscillator output frequency is 20 megahertz. 

Since the PLO output is synchronized with the physical rotation of the disk stack, it is 
used as the write clock and as the clock for the sector counter for hard sector mode oper- 
ation. 


C SYNCHRONIZATION DETECTOR AND SERVO DATA SEPARATOR 

The synchronization detector and servo data separator in the SLC detect the data and 
synchronization transitions, which are the first two dipulses present in each servo frame. 
The extracted synchronous transitions are used to create the absolute frame reference 
for synchronizing the servo frame and for decoding servo position information. Capability 
is provided for tolerating servo surface defects which may cause missing synchronization 
pulses. The serial data stream of data pulse transitions is used to verify lock by virtue of its 
limited run length of zeros when proper lock is in effect. Parity of the data words is also 
checked. The microprocessor constantly monitors synchronization and data and initiates 
relocking the PLO and reinitializing the servo if synchronization is lost. 


D DATA AND INDEX DECODER 

The data and index decoder in the SLC is a 16-bit shift register whose contents are read 
every sixteen frames. If all the frames are valid the word is passed on to other logic in the 
SLC and then to the microprocessor controller. Index is delineated by a preindex and in- 
dex word sequence. Absolute track information is also encoded with redundancy. The 
absolute track information is constantly monitored to verify that the servo is positioned on 
the correct track. In addition to index and track coding, the guard bands contain configu- 
ration data which is used to configure a given PCS for a given HDA. In this way, the same 
PCB may be used for a family of products. Configuration data includes the number of 
data tracks and heads, the servowriter version and drive capacity, and the dynamic 
constants to be used when seeking. 


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E HARD SECTOR CONTROL 

The hard sector capability of the drive is provided by a programmable counter in the SLC. 
This counter is clocked by the PLO and is synchronized with index. User defined 
jumpers on the PCB are used to set the desired number of bytes per sector. Alterna- 
tively, the desired number of bytes per sector may be set via the drive interface. The mi- 
croprocessor either reads the jumpers or receives the interface command, and in turn 
sets the decode logic for the proper sector size. The sector pulses are very accurately 
timed to data since the sector clock is locked to disk rotation. 


F POSITION DEMODULATOR CONTROL 

Timing windows are created in the SLC to gate the synchronization pulses, data pulses, 
and servo position dipulses. The servo master clock derived from the PLO divides each 
servo frame into twenty-two equal segments, and is used as the reference for generating 
these gates. A nominal disk rotation speed of 3,600 and 3,808 frames per revolution 
results in a 5 megahertz servo master clock. 

The synchronization pulse is used to align the gates to the servo frames. The gate gen- 
erated for synchronization is used to verify lock to synchronization. If lock is lost, syn- 
chronization pulses stop appearing in the proper synchronization window and a relock 
process is initiated by the microprocessor. The gate generated for data pulses is used to 
decode servo data. When no transition is detected in the window, the frame has a logical 
"0" value, and when a data transition does occur in the window, the frame has a logical "1" 
value. 

The four gates generated for the four position dipulses (A, B, C, and D) are used to 
switch the peak detectors in the position demodulator from a tracking mode to a hold 
mode, providing position information to the control system. 


G MAIN SERVO CONTROL LOOP 

The peak-detected A, B, C, and 0 dipulses are used to create the locking edges for the 
position loop. Difference signals corresponding to A-B, B-A, C-D, and D-C are synthe- 
sized and used for servoing on the appropriate data tracks. 

With the quadrature pattern, track zero uses A-B, track one uses C-D, track two uses B-A, 
and track three uses D-C. This pattern is repeated every fourth track so that tracks zero, 
four, eight, twelve, etc., use A-B for generating the position error signal. 

Digital to analog converters in the SLC are controlled by the microprocessor. During 
SEEKS, position and velocity control trajectories are calculated by the microprocessor 


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and output to the servo control loops via these DAC's. These trajectories are calculated 
based on the configuration data which is read at power up. The configuration data con- 
tains the dynamic constants which are used in calculating the SEEK trajectories. 

During track following, the position error is monitored by hardware to obtain fast response 
to shut down the write current should an off track condition occur during a write opera- 
tion. 


H MICROPROCESSOR CONTROLLER 

The servo microprocessor exercises supervisory control over the sen/o during track fol- 
lowing mode, and active control while seeking. In addition to the servo function, the mi- 
croprocessor performs interface control functions per ESDI specifications. 

The various peripherals, such as the SLC and configuration jumpers, are memory 
mapped. The microprocessor makes use of registers inside the SLC for drive status, 
control, seek current DAC output, position offset current DAC output, track address, 
servo data words, and peripheral control via output port pins in the SLC. 

The microprocessor also controls the recalibration sequence when power is first applied 
to the drive. When the drive is jumpered to enable starting and stopping the spindle mo- 
tor via the interface, the microprocessor controls the reset line to the spindle control mi- 
croprocessor. The status of the spindle control microprocessor is monitored by the servo 
microprocessor to determine status and detect any error conditions in the system. Such 
status information is then available to the host through the drive interface. 

The servo microprocessor also controls the actuator latch and releases the actuator when 
the spindle is locked to the proper speed. After power is removed from the drive, or a 
spindle stop command is received from the interface, the actuator driver pushes the 
headstack into the landing zone and the latch is enabled. This action takes place while 
the spindle is still spinning and before dynamic braking begins. 


I JUMPERS 

Two classes of servo jumpers are used in the drive. The first class includes factory 
jumpers which configure the PCS to work properly for the particular model of drive on 
which it is installed. These jumpers program the number of heads, the data transfer rate, 
and the synchronization field required by the data separator. The microprocessor reads 
these jumpers and performs accordingly. 

The second class of jumpers comprises user selectable jumpers. These jumpers are for 
setting a hard or soft sectored mode of operation, selecting the sector size in hard sector 


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mode, enabling or disabling the ability to set the hard sector size through the drive inter- 
face, and enabling or disabling automatic spinup. 


4.3 Read/Write Channel 

The read/write channel is described in the following paragraphs. 


4.3.1 HDA Flex Circuit Interface 

A description of the HDA flex circuit interface, including the preamplifier integrated circuit, 
power, head selection, the READ signal, and the WRITE mode and write unsafe, follow. 


A PREAMPLIFIER INTEGRATED CIRCUIT 

The preamplifier/write driver that is used on the flex circuit is the SSI 521 integrated cir- 
cuit. This is a thin film head compatible circuit capable of interfacing with up to six heads. 
There are three SSI 521 chips used on the flex circuit so that a maximum number (fifteen) 
of heads for a drive can be selected. 


B POWER 

Power is supplied from the main drive PCB through the flex circuit connector, J4. The 
voltage requirements are Vcc = +5 volts, Vdd = +12 volts. 


C HEAD SELECTION 

The head selection circuitry starts at the ESDI interface connector, J1. There are four 
head select lines used at the ESDI interface (Figure 10, Head and Drive Selection). 

-Headselect 2^ 

-Headselect 2*' 

-Headselect 2^ 

-Headselect 2^ 


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HEADSEUECT 2^ 
HEADSELECT ^ 
HEADSELECT 2^ 
HEADSELECT 2° 


DRIVE SELECT 1 

DRIVE SELECT 2 

DRIVE SELECTS 



CSO 

CS1 

CS2 

HSO 

HS1 

HS2 


Figure 10 

Head and Drive Selection 


These are then encoded by the SLC into three chip select lines and three head select 
lines that are used by the flex circuit. These lines are listed below (also, see Figure 1 1 , 
Preamplifier Head Selection and Read-Back Signal). 


CSO* 

CS1* 

CS2* 

HSO 

HS1 

HS2 


* Negative true 


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The encoding for the heads is listed in Figure 12, Head Selection Map. Also shown is the 
mapping of the heads within the HDA. 


HD 

CS2 

CS1 

cso 

HS2 

HS1 

HSO 

0 

1 

0 

1 

1 

0 

0 

1 

1 

0 

1 

1 

0 

1 

2 

0 

1 

1 

0 

0 

0 

3 

0 

1 

1 

0 

0 

1 

4 

0 

1 

1 

0 

1 

0 

5 

0 

1 

1 

0 

1 

1 

6 

0 

1 

1 

1 

0 

0 

7 

0 

1 

1 

1 

0 

1 

8 

1 

0 

1 

0 

1 

1 

9 

1 

0 

1 

0 

1 

0 

10 

1 

0 

1 

0 

0 

1 

11 

1 

0 

1 

0 

0 

0 

12 

1 

1 

0 

1 

0 

1 

13 

1 

1 

0 

1 

0 

0 

14 

1 

1 

0 

0 

1 

1 


TOP 

7 
6 
5 

4 
3 
2 
1 

5 HEADSTACK 
0 

8 

9 

10 

Il- 
ia 

- 19 - 

14 

BOnOM 


Figure 12 

Head Selection Map 











SPINDLE 










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D READ SIGNAL 

The amplified read-back signal is output from the flex on the RDX (read data x) line. RDY 
(read data y) lines are shown in Figure 12, Head Selection Map. The nominal gain from 
the head input, HnX and HnY (where n is the head number), of the preamplifier to the 
RDX and RDY outputs is 100. 


E WRITE MODE AND WRITE UNSAFE 

Write data is sent by the main PCB to the flex circuit via the WDI (write data input) pin on 
J4. A negative transition on the WDI line changes the direction of the write current in the 
SSI 521 , causing a data transition to be written. (The SSI 521 integrated circuit has a di- 
vide-by-two flip-flop internally in the write data path). Write current is selected by three 
programming resistors on the main PCB, one resistor per SSI 521 . 

The WUS (write unsafe output) is normally HIGH (unsafe) when in READ or IDLE mode. 
When a WRITE mode is initiated, WUS goes low after a period of up to 1 microsecond: 
this indicates a safe condition when in WRITE mode. An unsafe condition exists if any of 
the following occur; 

• the WDI frequency is too low 

• there is no write current 

• the device is in READ mode 

• the chip is disabled 


4.3.2 Pulse Detector 

The primary function of the pulse detector is to detect "legitimate" peaks of the read-back 
signal from the head, disk, and preamplifier. A legitimate peak corresponds to a written 
flux transition on the disk. Other undesired peaks can be caused by noise. The pulse 
detector must detect these legitimate peaks while preserving the timing associated with 
them. Each peak is represented by the presence of a narrow pulse on the +ENDATA 
(encoded data) line, with timing information in the leading edge. This pulse stream, rep- 
resenting encoded data, is ultimately time synchronized by the PLL data separator so 
that it can be decoded by the encoder/decoder (ENDEC). 

The pulse (or peak) detection function is implemented with an 8464 pulse detector inte- 
grated circuit. 

The following functions are used to achieve the primary purpose of this circuitry as stated 
above. 

NOTE: Differential signals are denoted by pin pairs. 


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A SIGNAL AMPLIFICATION USING AGO 

Figure 14, Pulse Detector, shows the preamplified head signal as the input to a gain- 
controlled amplifier in the 8464 pulse detector. AGO is used to maintain a constant, 
predetermined signal level at the input to the hysteresis comparator in the 8464 (pins 
twenty-one and twenty-two). 

This is important because a DC voltage level on the SET HYSTERESIS line (pin three) 
programs a comparator hysteresis which is intended to be a fixed percentage of the av- 
erage zero-to-peak signal amplitude at the comparator input. 

This hysteresis comparator provides the means to amplitude-quality signal peaks as le- 
gitimate. This is illustrated below, in Section 4.3.2 C, Pulse Qualification/Peak Detection. 

A gain-control signal for the first amplifier stage is derived from the signal at pins twenty- 
one and twenty-two by full-wave rectifying that signal, filtering it by means of the AGC ca- 
pacitor on pin sixteen, and comparing it to a reference level, VREF (voltage reference), at 
pin four. The VREF thus determines the signal amplitude at pins twenty-one and twenty- 
two, while the DC level on pin three, SET HYSTERESIS, determines the amplitude 
qualification level for peak detection. The discharge circuit connected to pin sixteen 
allows AGC discharge current to flow only when pulses are present at +ENDATA, thereby 
allowing the graceful detection of address marks without perturbing the AGC loop. 


B SIGNAL FILTERING 

The amplified read-back signal at pins eighteen and nineteen is processed by a 6.5 
megahertz Bessel filter before being input to the differentiator input (pins two and 
twenty-three). An additional 8 megahertz Bessel filter is placed before the hysteresis 
comparator (pins twenty-one and twenty-two) to compensate for the additional group 
delay in the differentiator, as well as some internal delay within the system. 

The differentiator network is a two pole Bessel configuration. 


C PULSE QUALIFICATION/PEAK DETECTION 

Figure 13, Peak Detection, shows pertinent wave forms which are referenced to the 
pulse detector integrated circuit. The gate channel input signal (to the hysteresis com- 
parator) is shown with the SET HYSTERESIS level on pin three. This is essentially the 
same wave form that is input to the time channel differentiator stage at pins two and 
twenty-three. The time differentiated version of this wave form has zero crossings that 
represent the peaks of the input wave form. These zero crossings are detected by a 
level comparator which triggers a bidirectional one-shot. The resulting pulses at pins 


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twelve and thirteen thus have leading edges which carry the timing information of the 
signal peaks. 



Figure 13 
Peak Detection 


These clocks toggle the pulse-qualifier flip-fiop in the 8464 oniy if the AMPLITUDE 
QUALIFICATION signal at pin fifteen (D of the flip-flop) has changed state since the last 
clock was received. Every flip-flop toggle produces a pulse on pin fourteen (+ENDATA) 
whose leading edge retains the timing of the corresponding signal peak. 


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Note that the flip-ftop D changes state, and thus qualifies the next flip-flop clock only if the 
gate channel input signal exceeds the preset hysteresis level. 

Note that "shoulders" on the differentiator input produce "droop" on the differentiated 
output which can generate spurious zero crossing. Figure 13, Peak Detection, illustrates 
the pulse amplitude qualification. 


D WRITE-TO-READ AND HEAD SWITCH RECOVERY 

Referring to Figure 14, Pulse Detector, the drive uses a -SQUELCH command, derived in 

the SLC, which is related to the system WRITE command in the following manner; 

• when WRITE is true, -SQUELCH is true (low) and pin eleven is held high, which puts 
the 8464 in WRITE mode. The 8464 reacts by lowering its internal input impedance 
at pins eighteen and nineteen, and maintaining the AGC voltage at pin sixteen 

• when WRITE is false, -SQUELCH remains true for 5 microseconds and then be- 
comes false. This maintains the reduced input impedance across pins six and seven 
for the 5 microseconds by virtue of the 8464’s internal circuit, as well as an external 
circuit shown as "squelch net" 


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J4 


FROM 

HDA 


^RDY 1 


SQLCH - 
(FROM SLC) 




-C>o 


SQUELCH 

CIRCUIT 


11 


AGLCK - 
(FROM SLC) 


DISCHARGE 

CIRCUIT 


16 


V 


10 


W/-R 


OUT 


GATE 


TIME 


PULSE 

DETECTOR 

CHIP 


VOLTAGE 

REFERENCE 


V 


18 


TIME 

FILTER 


1 22 

2 


GATE 

FILTER 


COUPLING 

NETWORK 


i- 


24 


DIFFERENTIATOR 

NETWORK 


14 


BUFFER 


T 


El 


+ ENDATA 
TO DATA 
SEPARATOR 


Figure 14 
Puise Detector 


When a head switch occurs, -SQUELCH becomes true for 5 microseconds with the same 
result as described above. 

The reduced input impedance during squelch permits the input coupling capacitors to 
pins six and seven to discharge more quickly after any new DC offset voltage which may 
be the result of write-to-read mode switching or head switching. If these capacitors are 
not discharged by the time the next read data comes along, the resulting pin six and 
seven differential input voltage hinders a read operation. 


4.3.3 Clock Recovery and Decoding 

The clock recovery and data standardization functions are provided by the DP8459 inte- 
grated circuit which receives +ENDATA from the pulse detector. Decoding is provided 
by the DP8463B ENDEC integrated circuit according to the rules of (2, 7) 1/2 code. Fig- 
ure 15, ENDEC/Data Separator, READ Mode, illustrates the system in READ mode. The 


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additional logic in the read gate synchronization block and the data resynchronizer en- 
sures that the data separator/ENDEC combination meets all ESDI specifications. 


-READ GATE 

DVSLTO 

CMOCMP 

WRTCLK 

+EN0ATA 


-ADDRESS 
MARK ENABLE 

HARD SECTOR 

WCS 

DATA BUS 





Figure 15 

ENDEC/Data Separator READ Mode 


A DATA SEPARATOR 

The data separator uses a phase-lock loop (PLL) to recover the write clock information 
from the encoded data stream, +ENDATA. It operates in three modes under control of 
the read gate synchronization circuits. When not reading or writing (IDLE mode), or when 
in WRITE mode, the data separator is locked to the write clock from the servo PLL, and 
operates in a wide band width, phase/frequency mode. This insures proper PLL lock-up, 
both for phase and frequency. When READ GATE is asserted, RDGAT to the data sepa- 
rator becomes true at the same time, beginning a lock-up sequence: the voltage con- 
trolled oscillator (VCO) in the data separator stops and then restarts synchronously with 
the incoming data stream on +ENDATA, and the phase detector goes into phase only 
mode. Stopping and restarting the VCO ensures that a relatively low initial phase error 
occurs so that the lock-up time is well below the time allotted by the 11 -byte preamble 
field. After preamble is detected in the data separator, PRDET becomes true, which re- 
duces the loop gain so that the band width is reduced. Additionally, the PRDET signal is 
sent to the read gate synchronization logic. The data standardizer in the data separator 
uses the recovered clock to decide if a +ENDATA pulse has occurred In each window. 


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XT-4000E Product Specification & OEM Manuai 


The window is nominally 50 nanoseconds wide for 10 megabits per second NRZ data 
rate. The data standardizer then resynchronizes -i-ENDATA to the recovered clock, using 
the window constraint, and sends synchronous data and synchronization clock to the 
ENDEC. 

When -READ GATE becomes false, the RDGAT to the data separator is delayed for about 
seven write clock periods. This ensures that stopping the VCO does not interfere with 
the READ/REF clock switch over. The VCO is stopped and then restarted syn- 
chronously with write clock to ensure minimal initial phase error. The data separator locks 
to the write clock in phase/frequency mode and wide band width. After power up, the 
data separator is initialized through U63 and the microwire bus (National trade mark) on 
the data separator. This establishes the window centering for the data standardizer in the 
data separator. 


B ENDEC, READ MODE 

After the read gate synchronization logic receives a preamble-detected signal from the 
PLL, along with READ GATE true, it issues RGATE to the ENDEC. The ENDEC then 
switches the READ/REF clock output from the reference clock (servo PLL write clock) to 
the PLL derived read clock, with no more than two clock periods missing, and no glitches 
allowed at the switch over point. Additionally, the read gate synchronization logic sends 
EXPRCMP to the ENDEC after approximately 500 nanoseconds from the leading edge 
of RGATE. At this point, the ENDEC has acquired code framing and can decode the 
(2,7) 1/2 encoded data to NRZ data. The NRZ data at the MSOUT output on the ENDEC 
is then reclocked with the data resynchronizer before going to the line driver. The 
RDR-FCK output of the ENDEC is also sent to another line driver which then goes to the 
ESDI interface. When READ GATE becomes false, RGATE and EXPRCMP to the 
ENDEC both become false at the same time, but RDGAT to the data separator is delayed 
for about seven write clock periods. This is to ensure that a proper switch over occurs on 
the READ/REF clock output of the ENDEC. The switch over from the read clock to the 
reference clock (write clock) occurs at the same time that -READ GATE (or RGATE at the 
ENDEC) becomes false. 


4.3.4 Write Path and Encoding 

Figure 16, Write Path, details the write path. The ENDEC receives NRZ data from the line 
receivers and encodes it to (2,7) 1/2 code according to the encoding rules, using write 
clock as the master clock. 


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+NRZ WRITE DATA 
-NRZ WRITE DATA 

+WRITE CLOCK 
-WRITE CLOCK 

WRTCLK 
(FROM SERVO) 

-ADDRESS MARK 
ENABLE 

HARD SECTOR 

-WRITE GATE 

-READ GATE 



WDI 

WRITE* 


10 +READ/REF 
CLOCK 




+READ/REF 

CLCXIK 

-AMF/SECTOR 

-AMF/SECTOR 


Figure 16 
Write Path 


A SOFT SECTOR WRITE 

When the drive is configured for soft sector operation (JP31 installed), address marks are 
written on the drive through the -AME (address mark enable) line along with -WRITE 
GATE. An address mark is a dc erased portion of the track of 3 bytes. When the con- 
troller initiates a WRITE in soft sector mode, the -WRITE GATE input becomes true and 
-AME is enabled at the time an address mark is to be written. The ENDEC does not send 
pulses out on the WDI lines during this time so that the dc erased mark is written on the 
disk. 


B HARD SECTOR WRITE 

When the drive is configured for hard sector operation (JP31 removed), address marks 
are not written on the disk and the start of a sector is indicated by the drive with the sector 
mark output. The number of sectors per track is selected by jumpers, or can be config- 
ured through the interface if the drive is jumpered for this option. -WRITE GATE again 
initiates a write operation. 


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C ENCODING DATA 

The NRZ WRITE DATA and WRITE CLOCK from the controller are received by the line 
receivers on the drive, and are converted to TTL levels before being sent to the ENDEC. 
The ENDEC then encodes the NRZ data to (2,7) 1/2 code that is sent out of the COD- 
OUT output of the ENDEC. This then goes to the WDI input of the flex circuit. 


D 


ENCODING RULES 


The ENDEC, when in WRITE mode, encodes the NRZ write data using (2, 7) 1/2 encod- 
ing rules. The NRZ code is encoded to meet the desired run constraints of no fewer than 
two, and no more than seven, encoded zeros written between transitions. By doing this, 
any long runs of NRZ zeros are encoded such that transitions are present for the clock 
regeneration circuitry (the data separator PLL). 

If the code did not place a bound on the longest period between transitions, as with the 
NRZ data, the data separator would not have any data to lock to, resulting in the data sep- 
arator losing synchronization over a period of time. Most importantly, the (2, 7) 1/2 code 
has properties which improve the performance of the read channel. 

The period of time between transitions for various (2, 7) 1/2 code lengths can be deter- 
mined by the following: 


(N) T = (Td/2) (N+1 ) n = 2, 3, 4, 5, 6, 7 


Where: N = n + 1 

Td = NRZ data clock period 


10 Mbps 
Td = 100.00 

(3) T=150 

(4) T=200 
(8) T = 400 


nanoseconds 

nanoseconds 

nanoseconds 

nanoseconds 


For the (2, 7) 1/2 code, (3) T is the shortest period that can be written, also known as 
Tmin, and (8) T is the longest period that can be written, also known as Tmax. 


4.3.5 Address Mark Detection 

When a drive has been formatted in soft sector mode, address marks are used to estab- 
lish the start of sectors. An address mark is a 3-byte dc erased gap written on the track. 
Interface signals tell the drive to search for an address mark by making -AME true, along 


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with -DRIVE SELECT. These interface commands are then converted to AME and are 
sent to the ENDEC input AMENBL. This starts an address mark search within the 
ENDEC. When the ENDEC detects an address mark, it sends out AMF (address mark 
found). This signal is then sent out to the SLC which, in turn, sends it to a buffer and 
then to the interface as -AMF/SECTOR. The SLC controls which signal is sent to the - 
AMF/SECTOR, depending on whether the drive is jumpered for soft sector (-AMF is out- 
put) or hard sector (-SECTOR is output). 

After the controller receives the -AMF signal, the controller sets -AME to false. When 
-AME becomes false, the AMF signal to the SLC becomes false. The address mark has 
been detected and the controller turns on -READ GATE to the interface. -READ GATE is 
conditioned, along with -DRIVE SELECT and CMDCMP (command complete), before it is 
input to the read gate synchronizing block as RDGT. The read process then starts as de- 
scribed above. 


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5.0 FUNCTIONAL OPERATION 


5.1 Power Up Sequence 

DC power (+5 volt and +12 volt) may be supplied to the drive in any order, but +12 volts 
DC is required to start the spindle motor. The motor power up is controlled by the status 
of jumper JP6 on the drive electronics PCB assembly. (The location and function of all 
PCB jumpers are shown in Figure 46, Drive Jumper Options, and Table 26, Jumper Se- 
lections.) 

If jumper JP6 is open, the spindle power up sequencing is initiated by the issuance of the 
START MOTOR CONTROL command. 

When the spindle reaches full speed, the actuator lock automatically disengages and the 
heads then recaiibrate to track zero. Upon a successful recalibration, READY and COM- 
MAND COMPLETE status signals are true. The unit does not perform any read, write, or 
seek functions untii READY is true. (If after starting, 1,000 revolutions per minute is not 
reached in ten seconds, an automatic shutdown procedure is initiated; power to the 
spindle motor is shut off and the drive does not become READY.) 


DC POWER ON 

SPiNUP COMMAND 
+ COMMAND COMPLETE 

-READY 

-DRIVE SELECT 


I 



- ' NOMINAL TIME 


FRONT PANEL LED 


Figure 17 

Power Up Sequence (Jumper JP6 Open) 


If jumper JP6 is installed, the spindle power up sequencing is initiated by the application 
of DC power. (When shipped, the JP6 jumper is installed.) 


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5.2 DmVE SELECTiON 

Drive selection occurs when the controller places the address of the drive to be selected 
on the three drive select lines. See Figure 18, Drive Select Circuit. Only the selected 
drive responds to the input signals, and only that drive's output signals are then gated to 
the controller. The details of setting the drive selection jumper are covered in Section 
9.1 , Drive Address Selection Jumper. 

150 OHM 


+5 V 


A TERMINATORS ARE LOCATED 
IN LAST DRIVE ONLY. 


Figure 18 

Drive Select Circuit 



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CONTROLLER 



FLAT RIBBON OR 

TWISTED PAIR (3 METERS MAX) 


-HEAD SELECT 2^ 

-HEAD SELECT 2^ 

-WRITE GATE 
-CONFIG-STATUS DATA 

-TRANSFER ACK 
-ATTENTION 

-HEAD SELECT 2Q 

-SECTOR/ADDRESS MARK FOUND 

-HEAD SELECT 2^ 

-INDEX 
-READY 
-TRANSFER REQ 
-DRIVE SELECt 1 
-DRIVE SELECT 2 
-DRIVE SELECT 3 
-READ GATE 
-COMMAND DATA 


> 








¥ 


DRIVE 


2 


4_ 

6 _ 

£ 

10 

12 


3 — 
5 — 

9 — 
11 — 


13— J 


14 


15-H 


16 


17 —^ 


Ji. 

20 _ 

22 

24 

— 

30 

34 


19 — 
21 — 
23 — 
25 — 
27 — 
29 — 


31 —^ 


33 — 



A 


>-J1/P1 


J 


Figure 19 

Controi Cabie J1/P1 Signais 


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SiGNALNAME 

SIGNAL 

PIN 

GROUND 

PIN 

-HEAD SELECT 2 3 

2 

1 

-HEAD SELECT 2 2 

4 

3 

-WRITE GATE 

6 

5 

-CONFIG-STATUS DATA 

8 

7 

-TRANSFER ACK 

10 

9 

-ATTENTION 

12 

11 

-HEAD SELECT 20 

14 

13 

-SECTOR/ADDRESS MARK FOUND 

16 

15 

-HEAD SELECT 2l 

18 

17 

-INDEX 

20 

19 

-READY 

22 

21 

-TRANSFER REQ 

24 

23 

-DRIVE SELECT 1 

26 

25 

-DRIVE SELECT 2 

28 

27 

-DRIVE SELECT 3 

30 

29 

-READ GATE 

32 

31 

-COMMAND DATA 

34 

33 


Tabie 9 

Controi Cabie J1/P1 Pin Assignments 


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CONTROLLER 


FLAT RIBBON OR 

TWISTED PAIR (3 METERS MAX) 


t 


-DRIVE SELECTED 


+NRZ WRITE DATA 


-NRZ WRITE DATA 


+NRZ READ DATA 


-NRZ READ DATA 


-INDEX 


A 


MUST BE GROUNDED 


^ -SECTOR/ADDRESS MARK FOUND 

'Z -COMMAND COMPLETE 

-ADDRESS MARK ENABLE 


HHSSSSRMHHHH 




-WRITE CLOCK 


-WRITE CLOCK 


LU 

> 

DC 

LU 

LU 

DC 


^ +READ REFERENCE CLOCK 

^ -READ REFERENCE CLOCK 


1 

2 

3 

4 

5 


7 

8 

9 

10 
11 


13 

14 


17 

18 


20 


DRIVE 


6-1 


12 - 


1 £ 

16- 


19- 


Figure 20 

Data Cabie J2/P2 Signais 


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SIGNAL NAME 

SIGNAL 

PIN 

GROUND 

PIN 

-DRIVE SELECTED 

1 


-SECTOR/ADDRESS MARK FOUND (not gated w/drive select) 

2 


-COMMAND COMPLETE 

3 


-ADDRESS MARK ENABLE (not gated w/drive select) 

4 


-Reserved 

5 

6 

-WRITE CLOCK 

7/8 


-Reserved 

9 


-READ/REF CLOCK 

10/11 

12 

-NRZ WRITE DATA 

13/14 

15/16 

-NRZ READ DATA 

17/18 

19 

-INDEX (not gated w/drive select) 

20 



Table 10 

Data Cable J2/P2 Pin Assignments 


Figure 21, Typical Auxiliary Cable and Spindle Synchronization Connection, and Table 
11, Auxiliary Cable (J6) Pin Assignments, show connector pin assignments, and 
interconnection of cabling between drives, for the auxiliary signals. 


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2. UP TO 48 SLAVE DRIVES ARE ALLOWED 

3. THE MAXIMUM LED CURRENT IS 40 mA 

4. THE TERMINATOR IS APPLIED AT THE DRIVE 
CONNECTOR FARTHEST FROM THE MASTER DRIVE 


Figure 21 

Typicai Auxiiiary Cabie and Spindie Synchronization Connection 


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SIGNAL NAME 

PIN 

MAPOUT 

1 

MAPIN 

2 

GND 

3 

MAPIN 

4 

GND 

5 

KEY (N.C.) 

6 

- REMOTE WRITE PROTECT 

7 


8 

-LED 

9 

+ LED 

10 


Tabie 11 

Auxiiiary Cabie (J6) Pin Assignments 


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6.1 Control Input Lines 

The control input signals are one of two types: those to be multiplexed in a multidrive 
system, and those intended to do the multiplexing. The signals to be multiplexed are 
WRITE GATE, TRANSFER REQ, and COMMAND DATA. The signals which do the multi- 
plexing are DRIVE SELECT 1, DRIVE SELECT 2, and DRIVE SELECT 3. 

The input lines have the following electrical specifications (see Figure 23, Control Sig- 
nals, Driver/Receiver Combination, for the recommended circuit): 


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TRUE; 0.0VDCto0.4VDC@1 =-48 mA(max) 

FALSE: 2.5 V DC to 5.25 V DC @ 0 = +250 pA (open collector) 


+5V 



(SEE SECTION 5.1 .2, WRITE GATE, 

AND THE FIGURE, WRITE GATE TERMINATION, 
FOR WRITE GATE DIFFERENCES) 

NOTE: TERMINATORS ARE LOCATED 
OBLAST DRIVE ONLY 


Figure 23 

Control Signals, Driver/Receiver Combination 


6.1.1 HEAD SELECT 2°, 2^ , 22, and 23 

The four HEAD SELECT lines allow selection of each individual read/write head in a bi- 
nary coded sequence. HEAD SELECT 2^ is the least significant line. Data heads are 
numbered and addressed continuously from zero through the maximum head number. 
When all HEAD SELECT lines are high (inactive), head zero is selected. 

Addressing more heads than contained in the drive results in a write fault when at- 
tempting to perform a write operation. 

A 150 ohm terminator pack allows for line termination. 


6.1.2 WRITE GATE 

The active state of this signal, or low level, enables write data to be written on the disk. 

The HI to LO transition of this signal creates a write splice and initiates the writing of the 
data phase-locked oscillator (PLO) synchronization field by the drive. See Figure 24, 
Soft Sector Address Mark, WRITE GATE, PLO Synchronous Format Timing. When for- 


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matting, WRITE GATE should be deactivated for 2 bit times minimum between the ad- 
dress area and the data area, to alert the drive to the beginning of the data PLO synchro- 
nization field. 


NOTE: The controller rhust send zeros during the writing of a PLO synchronization field. 



12 BYTES 3 BYTES 12 BYTES 




PAD 

PLO 

BYTE 

SYNC 


A 


14 BYTES 


ISQ 


ADDRESS 

MARK 


BYTE 
SYNC 
PATTERN 
1 BYTE 


ADDRESS 

FIELD 


ADR 

CHECK 

BYTES 


ADR 

PAD 

2 

BYTES 


WRITE 
SPLICE 
1 BYTE! 


PLO 

SYNC 


BYTE 
SYNC 
PATTERN 
1 BYTE 


DATA 

FIELD 


DATA 

ICHECK 

BYTES 


DATA 

PAD 

BYTES 


END OF 
TRACK/ 
SECTOR 
GAP 


ISG 



-WRITE TH 
GATE ,[ 


.12 BYTES 



-ADDRESS 

MARK 

ENABLE 



A 




A. TRAIUNG EDGE OF ADDRESS MARK ENABLE SIGNIFIES START OF HEADER PLO SYNC FIELD. 

A transition required only if disk read after format and prior to data field write update. 
A controller MUST SEND zeros during PLO SYNC TIME 


Figure 24 

Soft Sector Address Mark, WRITE GATE, PLO Synchronous Format Timing 


An alternate format timing in hard sector mode, using the ADDRESS MARK ENABLE 
signal, is shown in Figure 25, Hard Sector WRITE GATE, PLO Synchronous Format Tim- 
ing, Using ADDRESS MARK ENABLE. 


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ADDRESS MARK ENABLE A 




A TRANSITION REQUIRED ONLY IF DISK IS READ AFTER FORMAT AND PRIOR TO DATA 
FIELD WRITE UPDATE 

A CONTROLLER MUST REINITIALIZE TIMING WITH EACH SECTOR RELATIVE TO SECTOR PULSE 
^ (NEED NOT NEGATE WRITE GATE) 

A TRAILING EDGE OF ADDRESS MARK ENABLE (1 to 0) SIGNIFIES START OF HEADER PLO SYNC 
FIELD. DRIVE DOES NOT WRITE ADDRESS MARK ON DISK MEDIUM. 

NOTE: THE USE OF ADDRESS MARK ENABLE ALLOWS WRITING OF AN ADDRESS AREA 
WITHOUT A WRITE SPUCE IN THE PRECEDING GAP. 

Figure 25 

Hard Sector WRITE GATE, PLO Synchronous Format Timing, Using ADDRESS 

MARK ENABLE 


This line is protected from terminator power loss by implementation of the circuit shown in 
Figure 26, WRITE GATE Termination. 


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+5 V 



A PART OF THE TERMINATOR IN THE LAST DRIVE OF THE DAISY CHAIN. 
A permanently located IN THE DRIVE. 

Apr eouivalent part. 


Figure 26 

WRiTE GATE Termination 


ISG 


WRITE 
SPLICE 
1 BYTE 


PLO 

SYNC 


BYTE 

SYNC ADRESS 
PATTERN field 
1 BYTE 


ADR 

CHECK 

BYTES 


ADR 

PAD 

2 

BYTES 


WRITE 
SPLICE 
1 BYTE 


PLO 

SYNC 


BYTE 
SYNC 
PATTERN 
1 BYTE 


DATA 

FIELD 


DATA 

CHECK 

BYTES 


DATA 

PAD 

2 

BYTES 


ISG 


I 


INDEX/“Tn 

I 


I 

SECTOR 

1 1 

I 







[ 4 — 2 BITS MIN 

WRITE " 

T" 

I 



GATE _ 

1 

I 




A 




Afn 


^ TRAILING EDGE OF ADDRESS MARK ENABLE (1 TO 0) SIGNIFIES START OF HEADER PLO 
SYNCHRONIZATION FIELD. DRIVE DOES NOT WRITE ADDRESS MARK ON DISK MEDIUM. 

^ TRANSITION REQUIRED ONLY IF DISK IS READ AFTER FORMAT AND PRIOR TO DATA 
FIELD WRITE UPDATE. 

^ CONTROLLER MUST REINITIALIZE TIMING WITH EACH SECTOR PULSE (NEED NOT 
NEGATE WRITE GATE). 

^ LEADING EDGE OF WRITE GATE (0 TO 1) DEFINES A WRITE SPLICE AND START OF A PLO 
SYNCHRONIZATION FIELD. 


Figure 27 

Hard Sector WRITE GATE, PLO Synchronous Format Timing 


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6.1.3 READ GATE 

The active state of this signal, or low level, enables data to be read from the disk. This 
signal should be activated only during a PLO synchronization field and at least 10 bytes 
prior to the ID, or data synchronization bytes. The PLO synchronization field length is 1 1 
bytes and is indicated by the response to the REQUEST PLO SYNC FIELD LENGTH 
command. Read gate must be deactivated when passing over a write splice area. 

A 150 ohm terminator pack allows for line termination. 


6.1.4 COMMAND DATA 

When presenting a command, sixteen information bits of serial data, plus parity, are pre- 
sented on this line. This data is to be controlled by the handshake protocol with signals 
TRANSFER REQ and TRANSFER ACK (see Figure 33, Typical Serial Operation(s)). 
Upon receipt of this serial data, the drive performs the required function, as specified by 
the bit configuration. Data is transmitted most significant byte first. See Table 12, COM- 
MAND DATA Definition, for the meaning of the various bit combinations. See Figure 28, 
One Bit Transfer Timing — ^To Drive, for timing. Odd parity must be maintained. (The 
number of bits set to one in a command, including parity, must be odd.) 

No communications should be attempted unless the COMMAND COMPLETE line is true. 

Reading and writing are inhibited during the execution of commands. 

NOTE: The COMMAND DATA line must be at a logic zero when not in use. 

A 150 ohm resistor pack allows for line termination. 


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CMD 

FUNCTION 

BIT 15 14 13 12 

CMD 

FUNCTION 

DEFINITION 

CMD 

MODIFIER 
APPLICABLE 
(BITS 11-8) 

CMD 

PARAMETER 
APPLICABLE 
(BITS 11-0) 

STATUS 
CONFIGURATION 
DATA RETURNED 
TO CONTROLLER 

0 0 0 0 

Seek 


Yes 

No 

0 0 0 1 

Recalibrate 


No 

No 

0 0 10 

Request Status 


No 

Yes 

0 0 11 

Request Configuration 


No 

Yes 

0 10 0 

Reserved 

- 

- 

- 

0 10 1 

Control 

Yes 

No 

No 

0 110 

Reserved 

- 

- 

- 

0 111 

Track Offset 

Yes 

No 

No 

10 0 0 

Initiate Diagnostics 

No 

No 

No 

10 0 1 

Set Byte per Sector 

No 

Yes 

No 

10 10 

Reserved 

- 


- 

10 11 

Reserved 

- 


- 

110 0 

Reserved 

- 


- 

110 1 

Reserved 

- 


- 

1110 

Reserved 

- 


- 

1111 

Reserved 

- 


- 


NOTES: 1. All unused or not applicable lower order bits must be zero. 
2. Any reserved or command function received is treated as 
an invalid command. 


Tabie 12 

COMMAND DATA Definition 


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A EXCEPT ON LAST BIT 
Figure 28 

One Bit Transfer Timing— To Drive 


See Figure 29, COMMAND DATA Word Structure, for a diagram of the COMMAND DATA 
bytes. 


MOST LEAST 

SIGNIFICANT SIGNIFICANT 



Figure 29 

COMMAND DATA Word Structure 


SEEK fOOOOi: This command causes the drive to seek to the cylinder indicated in bits 
eleven through zero. A SEEK command restores track offsets to zero. 

RECALIBRATE fOPOfi: This command causes the actuator to return to cylinder 0000. A 
RECALIBRATE command restores track offsets to zero. 


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REQUEST STATUS f00l0^: This command causes the drive to send 16 bits (see Table 
16, TRACK OFFSET Command Modifier Bits) of standard status information to the con- 
troller, as determined by the command modifier bits. 

When the command modifier bits (11-8) of the REQUEST STATUS command are 0000, 
the drive responds with 16 bits of standard status. See Table 13, REQUEST STATUS 
Modifier Bits. Bits fifteen through twelve of this status are defined as state bits which do 
not cause ATTENTION to be asserted. Bits eleven through zero of this status are fault, or 
change of status, bits that cause ATTENTION to be asserted each time one is set. 

When the command modifier bits (11-8) of the REQUEST STATUS command are 0001 
through 0111, the drive responds with the vendor unique status. The number of vendor 
unique status words is specified by the configuration data. 


COMMAND MODIFIER BITS 

FUNCTION 

11 

10 

9 

8 


0 

0 

0 

0 

Request Standard Status 

0 

X 

X 


Request Vendor Unique Status 

1 

X 

X 


Reserved 


Table 13 

REQUEST STATUS Modifier Bits 

REQUEST CONFIGURATION (00111: This command causes the drive to send 1 6 bits of 
configuration data to the controller. The specific configuration requested is specified by 
bits eleven through eight of the command, as shown in Table 14, REQUEST CONFIGU- 
RATION Modifier Bits. Furthermore, the drive responds to the subscripted command, 
REQUEST FOR CONFIGURATION with Are synchronized spindles configured? (0011 
0000 0000 0001). The response is 1000 0000 0000 0000 (Yes) or 0000 0000 0000 
0000 (No). 


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COMMAND MODIFIER BITS 

FUNCTION 

11 

10 

9 

8 


0 

0 

0 

0 

General Configuration of Drive and Format 

0 

0 


1 

Number of Cylinders 

0 

0 

1 

0 

Reserved 

0 

0 

1 

1 

Number of Heads 

0 

1 

0 

0 

Minimum Unformatted Bytes per Track 

0 

1 

0 

1 

Number of Unformatted Bytes per Sector (hard sector) 

0 

1 

1 

0 

Number of Sectors per Track (hard sector) 

0 

1 

1 

1 

Minimum Bytes in ISG Field ■ 

1 

0 

0 

0 

Minimum Bytes per PLO Synchronization Field 

1 

0 

0 

1 

Number of Words of Vendor Unique Status Available 

1 

0 

1 

0 

Reserved 

1 


1 

1 

Reserved 

1 

1 

0 

0 

Reserved 

1 

1 

0 

1 

Reserved 

1 

1 

1 

0 

Reserved 

1 

1 

1 

1 

Reserved 


Table 14 

REQUEST CONFIGURATION Modifier Bits 


CONTROL (0101V. This command causes the control operations specified by bits eleven 
through eight to be performed as described in Table 15, CONTROL Command Modifier 
Bits. 


COMMAND MODIRER BITS 

FUNCTION 

11 

10 

9 

8 


0 


0 

■i 

Reset Interface Attention and Standard Status 

0 

0 


■■ 

Reserved 

0 


1 

0 

Stop Motor (when jumper J6 not installed) 

0 

0 

1 

1 

Start Motor (when jumper J6 not installed) 

0 

1 

0 

0 

Reserved 

0 

1 

0 

1 

Reserved 

0 

1 

■■ 

0 

Reserved 

0 

1 


1 

Reserved 

1 

X 

II 

X 

Reserved 


Table 15 

CONTROL Command Modifier Bits 


TRACK OFFSET This command causes the drive to perform a track offset in the 
direction and amount specified by bits eleven through eight, as outlined in Table 16, 


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TRACK OFFSET Command Modifier Bits. Each offset value is 5% of the track width. 
SEEK and RECALIBRATE commands restore track offsets to zero. 


COMMAND MODIHER BITS 

FUNCTION 

11 

10 

9 

8 


0 

0 

0 

0 

Restore Offset to Zero 

0 

0 

0 

1 

Restore Offset to Zero 

0 

0 

1 

0 

Positive Offset One 

0 

0 

1 

1 

Negative Offset One 

0 

1 

0 

0 

Positive Offset Tw/o 

0 

1 

0 

1 

Negative Offset Two 

0 

1 

1 

0 

Positive Offset Three 

0 

1 

1 

1 

Negative Offset Three 

1 

X 

X 

X 

Reserved 


Table 16 

TRACK OFFSET Command Modifier Bits 


INITIATE DIAGNOSTICS (1000L This command causes the drive to perform 10,000 ran- 
dom seeks as a diagnostic aid. Successful completion of the diagnostics is indicated by 
COMMAND COMPLETE with no ATTENTION. 

SET UNFORMATTED BYTES PER SECTOR (lOOIt: This optional command causes the 
drive to set the number of unformatted bytes per sector indicated in bits eleven through 
zero (if implemented). This command is valid only if the drive is configured in the hard 
sectored mode and jumper JP30 is installed. 


6.1.5 TRANSFER REQ 

This line functions as a handshake signal, in conjunction with TRANSFER ACK, during 
command and configuration/status transfers. See Figure 28, One Bit Transfer Timing — 
To Drive, and Figure 30, One Bit Transfer Timing — From Drive, for timing. The transfer 
speed (one complete handshake) takes typically 11.76 microseconds per bit. Longer 
times may be experienced depending on the overhead experienced at the controller. 


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- TRANSFER REQ 


0 fisec MIN 
10 msec MAX 




EXCEPT ON LAST BIT 


Figure 30 

One Bit Transfer Timing— From Drive 


6.1.6 ADDRESS MARK ENABLE 


A SOFT SECTOR MODE ONLY 

This signal, when active with WRITE GATE, causes an address mark to be written. AD- 
DRESS MARK ENABLE is active for 24 bit times. See Figure 31, Write Address Mark 
Timing. 

ADDRESS MARK ENABLE, when active without WRITE GATE or READ GATE, causes a 
search for address marks. 


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-WRITE GATE 

-ADDRESS MARK ENABLE 



0 

1 

0 

1 


100 nsec MIN ^ 

24-BIT TIMES ±1 -BIT TIME 



Figure 31 

Write Address Mark Timing 


B HARD AND SOFT SECTOR MODES 

If WRITE GATE is true, the LO to HI transition, or deassertion of ADDRESS MARK EN- 
ABLE, causes the drive to begin writing the ID PLO synchronization field. See Figure 24, 
Soft Sector Address Mark, WRITE GATE, PLO Synchronous Format Timing. The con- 
troller must send zeros during the writing of the PLO synchronization field. 

A 150 ohm terminator pack allows for line termination. 

6.2 Control Output Lines 

The output control signals are driven with an open collector output stage capable of 
sinking a maximum of 48 milliamps at low level, or true state, with maximum voltage of 0.4 
volts, measured at the driver. When the line driver is in the high level, or false state, the 
driver transistor is off and collector leakage current is a maximum of 250 microamps. 

All J1 output lines are enabled by the drive select decoder. 

Figure 23, Control Signals, Driver/Receiver Combination, shows the recommended cir- 
cuit. 


6.2.1 DRIVE SELECTED 

A status line is provided at the J2/P2 connector to inform the host system of the selection 
status of the drive. The DRIVE SELECTED line is driven by a TTL open collector driver. 


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as shown in Figure 23, Control Signals, Driver/Receiver Combination. This signal goes 
active only when the drive is selected, as defined in Section 5.2, Drive Selection. The 
DRIVE SELECT lines at J1/PI are activated by the host system. 


6.2.2 READY 

This signal indicates that the spindle is up to speed. This interface signal, when true, to- 
gether with COMMAND COMPLETE, indicates that the drive is ready to read, write, or 
seek. When the line is false, all writing and seeking is inhibited. 


6.2.3 CONFIG-STATUS DATA 

The drive presents serial data on this line upon request from the controller. See Figure 
33, Typical Serial Operation(s), for typical operation. CONFIG-STATUS serial data is pre- 
sented to the interface and transferred using the handshake protocol with signals 
TRANSFER REQ and TRANSFER ACK; see Figure 30, One bit Transfer Timing— From 
Drive. Once initiated, 16 bits, plus parity, are transmitted, most significant byte first. Odd 
parity is maintained. 


MOST LEAST 

SIGNIFICANT SIGNIFICANT 


Q 


BIT 


BIT 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

□ 




Figure 32 

CONFIG-STATUS DATA Word Structure 


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-TRANSFER REQ 
(FROM CONTROLLER) 

-COMMAND DATA 
(FROMCONTRaLER) 

-TRANSFER ACK 
(FROM DRIVE) 

-CONFIG -STATUS DATA 
(FROM DRIVE) 

-COMMAND COMPLETE 
(FROM DRIVE) 

-ATTENTION 
(FROM DRIVE) 



16 COMMAND BITS 


A 

16 INFORMATION BITS 

■^1 


~ PLUS 1 PARITY BIT “ 

•r 

PLUS 1 PARITY BIT 




TRANSFER 
FROM CONTROLLER 
TO DRIVE 


A COMMAND COMPLETE IS DEACTIVATED FOR ALL COMMANDS TO THE DRIVE 

A COMMAND COMPLETE IS ACTIVATED TO SIGNIFY COMPLETION OF EXECUTION OF A 
COMMAND. APPLICABLE FOR ALL COMMANDS. 

A COMMAND COMPLETE IS ACTIVATED TO SIGNIFY COMPLETION OF THE REQUESTED 
CONFIGURATION/STATUS TRANSFER. 

A APPLICABLE FOR ALL REQUEST STATUS AND CONFIGURATION COMMANDS. 

A IF AN ERROR IS ENCOUNTERED DURING THE CURRENT COMMAND, AHENTION 
IS ACTIVATED AT LEAST 100 nsec BEFORE COMMAND COMPLETE IS ACTIVATED. 


Figure 33 

Typicai Seriai Operation(s) 


In response to the REQUEST STATUS command, 16 bits of status information is re- 
turned to the controller. Odd parity is maintained. 

If the command modifier bits (eleven through eight) are 0000, the standard status infor- 
mation is returned (see Tabie 17, Standard Status Response Bits). 


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BIT 

POSITION 

BIT 

VALUE 

FUNCTION 

15 

0 

Reserved 

14 

0 

Reserved 

13 

0 

Reserved 

12 

c 

Write Protected, Fixed Medium 

11 

c 

Spindle Synchronized (multiple spindles) 

10 

0 

Reserved 

9 

c 

Spindle Motor Stopped by STOP Command 

8 

c 

POWER ON RESET Conditions Exist 

7 

c 

COMMAND DATA Parity Fault 

6 

c 

Interface Fault 

5 

c 

Invalid or Unimplemented Command Fault 

4 

c 

SEEK Fault 

3 

c 

WRITE GATE with TRACK OFFSET Fault 

2 

c 

Vendor Unique Status Available 

1 

c 

WRITE Fault 

0 

0 

Reserved 


C = Condition Dependent 


Table 17 

Standard Status Response Bits 


Bits fifteen through twelve of the status are defined as state bits, which do not cause AT- 
TENTION to be asserted. Bits eleven through zero are fault, or change of status, bits 
which cause ATTENTION to be asserted. 

Conditions that can cause WRITE FAULT are: 

• write current in a head without WRITE GATE active or no write current with WRITE 
GATE active and the drive selected 

• writing before a COMMAND COMPLETE signal is received 

• writing while the head is off track 

• having DC voltages grossly out of tolerance 

• having WRITE GATE active to a write protected drive 

• having nonzero data during a PLO synchronization field write 

• simultaneously activating READ GATE and WRITE GATE 

If the command modifier bits (eleven through eight) are used, the vendor unique status 
information shown in Table 18 , Vendor Unique Status Response Bits. 


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BIT 

POSTION 

BIT 

VALUE 

FUNCTION 

15 

c 


14 

13 

c r 

Motor Status 

12 

c J 


11 

c 

Motor Synchronization 

10 

c 

Unable to Read Configuration Data 

9 

c 

SEEK Calibration Failure 

8 

c 

Head Offset Out of Tolerance 

7 

c 

Multiple Preamplifiers Selected 

6 

c 

WRITE GATE without COMMAND COMPLETE 

5 

c 

WRITE GATE without Offtrack 

4 

c 

Write to Protected Drive 

3 

c 

Preamplifier Write Unsafe 

2 

c 

READ GATE Before AMF 

1 

c 

Nonzero Data During PLO Write 

0 

c 

Simultaneous READ and WRITE GATE 


C = Condition Dependent WORD 1 


BIT 

POSTION 

BIT 

VALUE 

FUNCTION 

15 

0 

Reserved 

14 

1 

XT-4000E 

13 

c 

SEEK Calibration Error Code 

12 

c 

SEEK Calibration Error Code 

11 




10 

9 

c 1 

C ( 

> 

Number of Heads 

8 

C J 



7 

C ^ 



6 

c 



5 

c 



4 

3 

c 

c 


Servo Writer Version 

2 

c 



1 

c 



0 

C J 




C = Condition Dependent WORD 2 


Table 18 

Vendor Unique Status Response Bits 


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BIT POSITION 



15 

14 

13 

12 



BIT VALUES 


FUNCTION 

0 

0 

0 

0 

Normal Run Mode 

0 

0 

0 

1 

Bad Spindle Position Sensor 

0 

0 

■■ 

0 

Reserved 

0 

0 

WM 

1 

Excessive Time to 1,000 rpm 

0 

1 

0 

0 

Excessive Time to 3,000 rpm 

0 

1 

0 

mm 

Cannot Lock to Speed 

0 

1 

mm 


Abnormal Accel/Decel Condition at Start 

0 

1 

n 

1 

Motor Running at Wrong Speed 

1 

0 

0 

0 

Normal Run Mode with Locked Spindle, 

Synchronized Feature Active 

1 

0 

0 

1 

Locked Spindle Feature Active 

Spindle Not Synchronized 

1 

0 

■■ 

0 

Locked Spindle Synchronization Lost 

1 

0 

■■ 

■■ 

Spindle Stuck 

1 

■■ 

■■ 

mm 

Reserved 

1 


0 

H 

Locked Spindle Sync Up Mode Active 

1 

II 

II 

0 

Locked Spindle Feature Active, but No MAPIN Pulse 
Provided for Synchronization 

1 

■ 

■ 

1 

Reserved 


Tabie 19 
Motor Status 


The SEEK calibration error portion of word two is only valid with bit nine of word one set. 
With this bit set, the error code is interpreted as in Table 20, SEEK Calibration Error 
Code. 


1 BIT POSITION 

FUNCTION 

13 

112 

BIT VALUES 

0 

0 

SEEK Error During Calibration 


1 

SEEK Calibration Time Excessive 

HI 

0 

Torque Profile Error 

■I 

1 

Head Calibration Error 


Tabie 20 

SEEK Caiibration Error Code 


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BIT 

POSiTION 

BIT 

VALUE 

FUNCTION 

15 

0 

Magnetic Disk Drive 

14 

0 

End of Track/Sector Gap 

13 

1 

Track Offset Option Available 

12 


Reserved 

11 

0 

Reserved 

10 

0 

Reserved 

9 

1 

Transfer Rate > 5 MHz or < 10 MHz 

8 

0 

Reserved 

7 

0 

Reserved 

6 

1 

Fixed Drive 

5 

p 

Spindle Motor Control Option Implemented 

4 

0 

Reserved 

3 

1 

RLL Encoded (not MFM) 

2 

p 

Soft Sectored (address mark) 

1 

p 

Hard Sectored (sector mark) 

0 

1 

Spindle Synchronization Subscripted 

Configuration Supported 


P = Programmable 


Tabie 21 

Generai Configuration Response Bits 


The motor status portion of word one of the vendor unique response is translated as in 
Table 22, Specific Configuration Response Bits. 


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COMMAND MODIRER BITS 

CONFIGURATION RESPONSE 

VALUE 

11 

10 

9 

8 



0 


0 

1 

Number of Cylinders, Fixed 

1,224 

0 


■■ 

0 

Number of Cylinders, Removable 

0 

0 


■■ 

1 

Number of Heads, Bits 7-0 

7 or 15 

0 

1 

0 

0 

Minimum Unformatted Bytes per Track 

20,940 

0 

1 

0 

1 

Number of Unformatted Bytes per Sector (hard sector) 

P 

0 

1 


0 

Number of Sectors per Track (hard sector) 

P 

0 

1 

1 

1 

Minimum Bytes in ISG Field (not including intersector 
speed tolerance) 

Bits 15-8: ISG Types After Index 

Bits 7-0: Bytes per ISG Field 

12 

14 

1 

0 

0 

0 

Minimum Bytes per PLO Synchronization Field 

Bits 7-0; Bytes per PLO Synchronization Field 

11 

1 

0 

0 

1 

Number of Words of Vendor Unique 

Status Available 

2 

1 

0 

■■ 

0 

Reserved 


1 

0 

■■ 

1 

Reserved 


1 

1 

0 

0 

Reserved 


1 

1 

0 

1 

Reserved 


1 

1 

■■ 

0 

Reserved 


1 

1 

n 

■ 

Reserved 



P = Programmable 


Table 22 

Specific Configuration Response Bits 


6.2.4 TRANSFER ACK 

This signal functions as a handshake signal, along with TRANSFER REQ, during com- 
mand and configuration-status transfers. See Figure 28, One Bit Transfer Timing— To 
Drive, and Figure 30, One Bit Transfer Timing — From Drive. 


6.2.5 ATTENTION 

This output is asserted when the drive wants the controlier to request its standard status. 
Generaily, this is a result of a fault condition or a change of status. Writing is inhibited 
when ATTENTION is asserted. ATTENTION is deactivated by the reset interface atten- 
tion command modifier, under the CONTROL command (see Section 6.1 .4, COMMAND 
DATA). 


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6.2.6 INDEX 

This pulse is provided by the drive once each revolution to indicate the beginning of a 
track. Normally, this signal is high and makes the transition to low to indicate INDEX. Only 
the transition at the leading edge of the signal is reciprocal of the rotational speed (see 
Figure 34, INDEX Timing). This signal is available on the command cable J1/P1 (gated) 
and on the data cable J2/P2 (ungated). 


0 


-INDEX 


1 


(16.633 msec MIN) 
(16.700 msec MAX) 


k- 


70 Msec or 2.8 psec 
(FACTORY OPTION) 




Figure 34 
INDEX Timing 


6.2.7 ADDRESS MARK FOUND (Soft Sector) 

This signal indicates the detection of the end of an address mark. See Figure 35, Read 
Address Mark Timing (Hard Sector), for timing. 


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HEAD SWITCH OR 
WRITE GATE OFF 

-ADDRESS MARK 
ENABLE 


-ADDRESS MARK 
ENABLE 


-READ GATE 


1 ^ >10Msec^ 


0 nsec MIN 


0 nsec MIN 

r n 




100 nsec MAX 

0 





1 

T 







0 

A 



1 





ADDRESS MARK 

V PLO SYNC 


1^ 

1 BYTE MAX 

0 



A T, =16 BIT TIMES MINIMUM 

^ LEADING EDGE INDICATES THE LOCATION OF THE END OF AN ADDRESS MARK 


Figure 35 

Read Address Mark Timing (Hard Sector) 


6.2.8 SECTOR MARK (Hard Sector) 

This optional interface signal indicates the start of a sector. No short sectors are allowed. 
The leading edge of the asserted sector pulse is the only edge that is accurately con- 
trolled. The INDEX pulse indicates sector zero. See Figure 36, Sector Pulse Timing 
(Hard Sector). 


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6.2.9 COMMAND COMPLETE 

COMMAND COMPLETE is a Status line provided at the J2/P2 connector. This is an un- 
gated output from the drive, which allows the host to monitor the drive’s COMMAND 
COMPLETE status during overlapped commands, without selecting the drive. This sig- 
nal line goes false in the following cases; 

• a recalibration sequence is initiated (by drive logic) at power on if the read/write heads 
are not over track zero 

• the signal line goes false upon receipt of the first COMMAND DATA bit. COMMAND 
COMPLETE stays false during the entire command sequence 

This signal is driven by an open collector driver, as shown in Figure 23, Control Signals, 
Driver/Receiver Combination. 


6.3 Spindle Synchronization Control Option 

This feature allows up to forty-eight drives to synchronize the angular position of their 
spindles such that their INDEX signals line up to within +20 microseconds of the leading 
edge of the INDEX signal on the master drive. In the absence of a MAPIN signal, the drive 
synchronizes to its internal clock. The drive indexes lead the leading edge of MAPiN by 
215 milliseconds (typical). The MAPIN signal is derived from either an external 60 hertz 
signal, or from the MAPOUT signal available on J6 from one drive defined as the master 
drive. 

MAPOUT is a TTL signal at 60 hertz with a pulse width of 20 microseconds. 


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The light-emitting diode (LED) output on J6 is an optional drive selected signal that is 
available for use in systems that cannot use the LED on the faceplate. 

The remote write protect input allows the drive to be write protected via the J6 connector. 
The active state of this signal, or low level, prohibits data from being written to the drive. 

See Figure 21 , Typical Auxiliary Cable and Spindle Synchronization Connection, for a 
typical configuration. 


6.4 Data Transfer Lines 

All lines associated with the transfer of data between the drive and the host system are 
differential, and are not multiplexed. These lines are provided at the J2/P2 connectors on 
all drives. 

Four pairs of balanced signals are used for the transfer of data and clock: NRZ WRITE 
DATA, NRZ READ DATA, WRITE CLOCK, and READ/REFERENCE CLOCK. Figure 37, 
Data Line Driver/Receiver Combination, illustrates the recommended driver/receiver cir- 
cuit. 


HIGH TRUE 



HIGH TRUE 


Z = 105 Q FLAT RIBBON OR TWISTED PAIR 

ANY DRIVER AND RECEIVER WHICH COMPLIES WITH 

EIA STANDARD RS-422 MEETS THESE REQUIREMENTS. 



NOMINAL LINE 
NOMINAL V LINE 


LOGIC ^ 


LOGIC 


0 1 


Figure 37 

Data Line Driver/Recelver Combination 


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6.4.1 NRZ READ DATA 

The data recovered by reading a prerecorded track is transmitted to the host system via 
the differential pair of NRZ READ DATA lines. This data is clocked by the READ CLOCK 
signal. See Figure 38, NRZ READ/WRITE DATA Timings, for timing. These lines are held 
at a zero level until PLO synchronization has been obtained and data is valid. 


6.4.2 NRZ WRITE DATA 

This is a differential pair that defines the data to be written on the track. This data is 
clocked by the WRITE CLOCK signal. See Figure 38, NRZ READ/WRITE DATA Timings, 
for timing. These lines must be held at a zero level during the writing of PLO 
synchronization. 


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REFERENCE CLOCK 


WRITE 

TIMING 


NRZ 

WRITE 

DATA 


WRITE 

CLOCK 


lALTiruiJiJiJxmn^ 

50nsec±5nsec -#1 


A 





A 


20 nsec 


20 nsec 
MIN ^ 


TJUUU 


LmUTi 

50 ±_ 

100± 29nsec 

7 nsec 


-A 



READ 

CLOCK 

A 

0(A] 

A 

_n 

•^100 ±10 nsec 

LTUITU 

rLTLTLrU 

READ 

TIMING 

NRZ 

READ 

A T A 

1 

0 J 


31 nsec— ► 

1 ^ A 

^ — 31 nsec 


) 

» 1 ' L” ' 

”1 0 0 0 


/K ALL TIMES IN nsec MEASURED AT I/O CONNECTOR OF THE DRIVE. 

^ SIMILAR PERIOD SYMMETRY IS IN ±4 nsec BETWEEN ANY TWO ADJACENT CYCLES 
DURING READING OR WRITING. 

^ EXCEPT DURING A HEAD CHANGE OR PLO SYNCHRONIZATION THE CLOCK VARIANCES FOR 
SPINDLE SPEED AND CIRCUIT TOLERANCES DO NOT VARY MORE THAN +0% TO -.2%. 

PHASE RELATIONSHIP BETWEEN REFERENCE CLOCK AND NRZ WRITE DATA OR WRITE CLOCK 
IS NOT DEFINED. 

A TIMING APPLICABLE DURING READING OR WRITING. 

A REFERENCE CLOCK IS VALID WHEN READ GATE IS INACTIVE. READ CLOCK IS VALID 
WHEN READ GATE IS ACTIVE AND PLO SYNCHRONIZATION HAS BEEN ESTABLISHED. 

NOTE: SEE THE FIGURE, DATA LINE DRIVER/RECEIVER COMBINATION, FOR DEFINITION OF 
0 AND 1 ON THESE DIFFERENT SIGNAL LINES. 


Figure 38 

NRZ READ/WRiTE DATA Timings 


6.4.3 READ/REFERENCE CLOCK 

The timing diagram as shown in Figure 38, NRZ READ/WRITE DATA Timings, depicts the 
necessary sequence of events, with associated timing restrictions, for proper read/write 
operation of the drive. The REFERENCE CLOCK signal from the drive determines the 


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data transfer rate. The transitions from REFERENCE CLOCK to READ CLOCK must be 
performed without glitches. Two missing clock cycles are permissible. 

The REFERENCE CLOCK rate is 10.0 + 0.10% megahertz. 

The READ CLOCK rate is 10.0 + 0.30% megahertz. 


6.4.4 WRITE CLOCK 

WRITE CLOCK is provided by the controller and must be at the bit data transfer rate. This 
clock frequency is dictated by the READ/REFERENCE CLOCK during the write opera- 
tion. See Figure 38, NRZ READ/WRITE DATA Timings, for timing. 

WRITE CLOCK need not be continuously supplied to the drive. WRITE CLOCK should 
be supplied before beginning a write operation and must last for the duration of the write 
operation. 


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7.0 PHYSICAL INTERFACE 

The electrical interface between the drive and the host controller is via four connectors: 

• J1 - control signals (multiplexed) 

• J2 - read/write signals (radial) 

• J3 - DC power input 

• J4 - frame ground 

Jumper J6 is the spindle synchronization connector and is connected to the drives using 
this option. 

Refer to Figure 26, Interface Connector Physical Location, for connector locations. 


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Figure 39 

interface Connector Physical Location 


7.1 J1/P1 CONNECTOR 

Connection to J1 is via a thirty-four-pin PCB edge connector. The dimensions for this 
connector are shown in Figure 40, J1 Connector Dimensions. The pins are numbered 
one through thirty-four, with the even pins located on the component side of the PCB. 
Pin two is located on the end of the PCB connector closest to the DC power connector 
J3/P3. A key slot is provided between pins four and six. The recommended mating con- 
nector for P1 is AMP ribbon connector part number 88373-3, or equivalent. 


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Figure 40 

J1 Connector Dimensions 


7.2 J2/P2 Connector 

Connection of J2 is via a twenty-pin PCB edge connector. The dimensions for the con- 
nector are shown in Figure 41, J2 Connector Dimensions. The pins are numbered one 
through twenty, with the even pins located on the component side of the PCB. The rec- 
ommended mating connector for P2 is AMP ribbon connector, part number 88373-6. A 
key slot is provided between pins four and six. 


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7.3 J3/P3 Connector 

The DC power connector (J3), Figure 42, J3 Connector (Drive PCB, Solder Side), is a 
four-pin AMP MATE-N-LOCK connector, part number 350543-1, mounted on the solder 
side of the PCB. The recommended mating connector (P3) is AMP part number 
1-480424-0, using AMP pins part number 350078-4 (strip) or part number 61173-4 
(loose piece). J3 pins are numbered as shown in Figure 42. 



Figure 42 

J3 Connector (Drive PCB Solder Side) 


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J3 CONNECTOR 


PIN 4 

+5 VOLTS DC ±5% 
PIN 3 

+5 VOLT RETURN 


PIN1 

+12 VOLTS DC ±5% * 
PIN 2 

+12 VOLT RETURN 


* ±10% AT POWER ON 
OR SEEKING 


Table 23 

Power Connector (J3) Requirements 


7.4 J4/P4 Frame Ground Connector 

The frame ground connection is a Faston-type connection, AMP part number 61761-2. 
The recommended mating connector is AMP 62187-1. if wire is used, the hole in J4 
accommodates a wire size of 18 AWG maximum. 

7.5 J6/P6 Auxiliary Connector 

The auxiliary connector is a Berg 68451-121 ten-pin connector. The mating connector is 
a 3M 3473-601 0. See Table 24, J6 Auxiliary Signal Cable Pin Assignments, for pin as- 
signments. 


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SIGNAL NAME 

PIN 

MAPOUT 

1 

MAPIN 

2 

GND 

3 

MAPIN 

4 

GND 

5 

KEY (N.C.) 

6 

- REMOTE WRITE PROTECT 

7 


8 

- LED 

9 

+ LED 

10 


Tabie 24 

J6 Auxiiiary Signal Cable Pin Assignments 


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8.0 PHYSICAL SPECIFICATIONS 

This section describes the mechanical and mounting recommendations for the XT- 
4000E Family disk drives. 

8.1 MOUNTING Orientation 

The drive may be mounted in any orientation. In any final mounting configuration, insure 
that the operation of the three shock mounts, which isolate the base casting from the 
frame are not restricted. Certain switching power supplies may emanate electrical noise 
which degrades the specified read error rate. For best results, it is suggested that the 
drive be oriented so that the PCB assembly is not adjacent to these noise sources. 

8.2 MOUNTING HOLES 

Eight mounting holes, four on the bottom and two on each side, are provided for mount- 
ing the drive into an enclosure. The size and location of these holes, shown in Figure 43, 
Mechanical Outline and Mounting Hole Locations, are identical to industry standard 
floppy drives. 

CAUTION: The casting is very dose to the frame mounting hoies in some iocations. 
Mounting screw lengths must be chosen such that no more than 0. 125 inches of the 
screw is available to enter the frame mounting hole. The torque applied to the mounting 
screws should be at least 9 inch-pounds; but to avoid stripping the threads, the maximum 
torque applied should not exceed 12 inch-pounds. 


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REF = REFERENCE. FOR EXACT MEASUREMENTS 
SEE FIGURE 8, MECHANICAL OUTLINE, 
BOnOMAND SIDE VIEWS. 


Figure 43 

Mechanicai Outiine and Mounting Hoie Locations 


8.3 PHYSiCAL DiMENSiONS 

Overall height, width, and depth, along with other key dimensions, are shown in Figure 
43, Mechanical Outline and Mounting Hole Locations, and Figure 44, Mechanical Out- 
line, Bottom and Side Views. 


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NOTE: PROTRUSION OF SCREWS 
THROUGH SIDE HOLES IS 

0.06 ± 0.01 UMITED TO 0. 125 INCH 



Figure 44 

Mechanical Outline, Bottom and Side Views 


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8.4 SHiPPiNG REQUiREMENTS 

At power down the heads are automatically positioned over the nondata, dedicated 
landing zone on each disk surface. The automatic shipping lock solenoid is also en- 
gaged at this time. Maxtor ships the drive in single- and multipack shipping containers. 

8.5 REMOVABLE FACEPLATE 

The faceplate may be removed in installations that require it. Remove the two C-clips and 
unplug the LED cable from the PCB. See Figure 45, Removable Faceplate. 



Figure 45 

Removable Faceplate 


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9.0 PCB JUMPER OPTIONS 


9.1 Drive Address Selection Jumper 

In multidrive configurations, it is necessary to configure each drive with a unique address. 
A maximum of seven drives are permitted per single host controller. The address for the 
drive is determined by installing the jumper plug in the appropriate jumper location 
(Figure 46, Drive Jumper Options). Table 25, Drive Select Jumpers, shows the drive 
selection jumpers. As shipped from the factory, the drive is configured as logical unit 
number one. Removing the jumper entirely is equivalent to a "no select.” 


DRIVE SELECT 
NUMBER 

JUMPER 

INSTALLED 

1 

DS1 

2 

DS2 

3 

DS3 

4 

DS4 

5 

DS5 

6 

DS6 

7 

DS7 


Table 25 

Drive Select Jumpers 


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Figure 46 

Drive Jumper Options 


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JUMPER 

DESCRIPTION 

JP1 (in) 

Used for Manufacturing Testing 

JP6 (in) 

In = Motor Spinup Option Disabled 

Out = Remote Motor Spinup Option Enabled 

DS1-DS7 (DS1 in) 

Drive Select 

JP14 (out) 

In = Write Protected 

Out = No Write Protection 

JP16-JP29 

Unformatted Hard Sector Size in Bytes 

Jumpers, LSB = JP16, MSB = JP29 

(refer to the table Customer Selectable Jumpers) 

JP30 

In = Enables Programming of the Hard Sector Size 

Through the Interface 

Out = Disable this Function 

JP31 

In = Soft Sector Mode 

Out = Hard Sector Mode 

JP32-35 

PCB Head Configuration 

JP41 

Test Connection, Not a Jumperable Option 

JP42 (in) 

Used for Manufacturing Testing 

NOTE: JP4. JP5, JP15. JP36, JP37, JP38, JP39, JP40, JP41 ARE NOT JUMPERABLE OPTIONS. 

THE ONLY CUSTOMER CONFIGURABLE OPTIONS ARE JP1&JP29, 

JP30, JP31, DS1-DS7, JP6, AND JP14. 


Table 26 

Jumper Selections 


9.2 Data Head Selection jumpers (JP32-JP36) 

Jumpers have been provided to allow the number of usable data heads to be selected. 
In order for the drive to respond correctly to the request configuration command - number 
of heads, these jumpers are set at the factory to correspond with the model of the drive. 
Table 27, Data Head Number Selection Jumpers, shows the various configuration op- 
tions. 


DRIVE 

NUMBER OF 

JUMPER CO 

NFIGURAT 

ON 

MODEL 

DATA HEADS 

JP 32 

JP 33 

JP 34 

JP 35 

XT-41 70 E 

bbhh 

In 

In 

In 

Out 

XT-4380E 

15 

In 

In 

In 

In 


Table 27 

Data Head Number Selection Jumpers 


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9.3 WRiTE PROTECT SELECTION JUMPER (JP14) 

Jumper JP14 is the write protect jumper. When the jumper is present (installed), the 
drive is write-protected and can only be read; no writing may take place. The drive does 
not have this jumper installed when it is shipped from the factory. 

9.4 Option for Sequential Spindle Motor Spinup Jumper (JP6) 

The spindle motor spinup jumper (JP6) allows a string of drives to be started sequentially 
by the controller. When the jumper is present (installed), the drive automatically spins up 
as soon as power is applied. If JP6 is removed, the drive is started by issuing the appro- 
priate command from the controller. As shipped from the factory, jumper JP6 is installed. 

9.5 Test Jumpers (JP1, JP41, JP42) 

These jumpers provide access to certain test signals. The specific signals and the normal 
factory settings are shown in Table 28, Test Pin Jumpers. 


JUMPER 

FACTORY 

SEHING 

NOTES ON FUNCTION 

JP1 

In 

Write Data 

JP41 

N/A 

Test Pins, Not Jumperable 

JP42 

In 

Write Gate 


Table 28 
Test Pin Jumpers 


9.6 Hard Sector configuration Jumpers (JP16-29) 

Jumper JP31 selects the mode of operation. Jumper JP31 installed configures the drive 
as a soft sector drive; removed, it configures the drive as a hard sectored drive. 

Jumpers JP1 6 through JP29 allow the user to configure the drive’s hard sector size. The 
sector size can range from a minimum of 123 to a maximum of 10,470 bytes per sector, 
with 1 byte granularity. 


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The hard sector configuration jumpers are encoded in a binary fashion, with JP16 being 
the least significant byte, and JP29 being the most significant byte. An installed jumper 
equates to a one. 

Jumper JP30, if installed, enables setting the hard sector size over the ESDI Interface. 


JUMPER 

# BYTES/SECTOR 

J16 

1 

J17 

2 

J18 

4 

J19 

8 

J20 

16 

J21 

32 

J22 

64 

J23 

128 

J24 

256 

J25 

512 

J26 

1,024 

J27 

2,048 

J28 

4,096 

J29 

8,192 


Example: 36 Sectors Desired 


1. 2. Q ,2 4&„|yl . es/Ifac li.^ 581 Byles/Sector 
00 ^^ctors 

2. Install Jumpers J25, J22, J18, +J16 
Number Bytes/Sector = 512 + 64 + 4 + 1 = 581 


Table 29 

Customer Selectable Jumpers 


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10.0 MEDIUM DEFECTS AND ERRORS 

Defects on the medium surface are identified on both a paper defect map and a defect 
map, written on the drive according to the ESDI format rules. These defect maps indicate 
the head number, track number, and number of bytes from index for each defect. 

The maximum allowable number of defects per drive does not exceed an average of fifty 
per disk surface. Cylinder zero is certified to be defect-free. 

The maximum number of encoded (NRZ) defects per drive is listed in Table 30, Maximum 
Number of Defects. 


DRIVE 

MODEL 

NO. OF 
DISKS 

NUMBER OF 

DATA SURFACES 

MAXIMUM NO. 

OF DEFECTS 

XT-41 70E 

5 

7 

140 

XT-4380E 

8 

15 

300 


Table 30 

Maximum Number of Defects 


As shipped, the disk drive contains two copies of the defect map, written on different 
locations on the disks. 

One complete defect list resides on sector zero of cylinder 1 ,223. An identical copy is 
located on sector zero of cylinder 1,215. This allows for redundancy should an error oc- 
cur on cylinder 1 ,223. Sector zero of any surface contains the defects for that surface. 
The format for the data field portion (see Figure 47, Defect List Format) of this sector is 
256 bytes, with 2 bytes of cyclic redundancy check (CRC) (x"'® + x'*^ + + 1). 

Defect locations are identified by fields 5 bytes long. Other byte definitions are shown in 
Figure 47, Defect List Format. Byte count is the number of bytes from INDEX. 

The location of the start of the actual defect may vary from the location specified on the 
defect list by up to + 1 byte due to the rotational speed tolerance of the drive motor. 

The end of the defect list for each surface is indicated by 5 bytes of ones in the defect 
location field, or the end of the sector. 


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The CRC check bytes should be used, if that capability exists, but may be ignored if 
multiple reads are a more desirable approach. 


"1_1 INDEX 


A 


A 




00 


PLO SYNC 
00 


ID SYNC 
BYTE 
FIELD 


CHECK 

BYTES 


PAD 


PLO SYNC 


DATA SYNC 
BYTE 
FIELD 


DEFECT 

LIST* 


CHECK 

BYTES 


PAD 


^1 

00 



A 

A 


PLO SYNC FIELD AND ISO ARE AS 
REPORTED IN RESPONSE TO THE 
REQUEST CONFIGURATION 
COMMAND 

FORMAT AND DEFECT LIST 
ARE WRITTEN AT CYLINDERS 
1,223 AND 1,215 


CYL 

MSB 


CYL 

LSB 


BYTE 

COUNT 

MSB 


BYTE 

COUNT 

LSB 


ERROR 

LENGTH 

(BITS) 


END OF LISTING IS ONES FILLED TO 
END OF DATA FIELD (5 BYTES 
OF ONES MINIMUM TO TERMINATE) 
OR END OF SECTOR 


BYTE COUNT FROM INDEX TO DEFINE START OF DEFECT 


NOTE: THE DRIVE REPORTS 1 1-BYTE PLO SYNCHRONIZATION 
FIELD. HOWEVER, THE DEFECT MAP IS WRITTEN WITH 
16 BYTES. 


Figure 47 
Defect List Format 


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APPENDIX: UNITS OF MEASURE 


Abbreviation Meaning 


A/m 

amps per meter 

AWG 

average wire gauge 

bpi 

bits per inch 

dBA 

decibel, a-weighted 

fci 

flux changes per inch 

g 

gram 

Gbyte 

gigabyte 

Hz 

hertz 

mA 

milliamp 

pA 

microamp 

Mbit 

megabit 

Mbyte 

megabyte 

pm 

micrometer 

msec 

miliisecond 

psec 

microsecond 

nsec 

nanosecond 

Oe 

oersted 

RH 

relative humidity 

rpm 

revolutions per minute 

tpi 

tracks per inch 

xxb 

binary values 

xxh 

hexadecimal values 


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GLOSSARY 

3RDPTY. Third party 
ACK. Acknowledge 
ADR. Address 
AGO. Automatic gain control 
AM. Address mark 
AM2. Address mode two 

AME. Address mark enable 
AMENBL. Address mark enable (to U60) 

AMF. Address mark found 

AMFD. Address mark found (from U60) 

ANSC. American National Standards Committee 
ANSI. American National Standards Institute 
ASSERT. A signal driven to the true state. 
ASYNC. Asynchronous 
BIT. Binary digit 

BYTE. Eight consecutive binary digits 
CLK. Clock 
CMD. Command 
CMDCMP. Command complete 
CODEIN. Code input 


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CODOUT. Code output 

CRC. Control register clock, or cyclic redundancy check 

CRD. Control register data 

CRE. Control register enable 

CSA. Canadian Standards Association 

D/A. Digital-to-analog 

DAC. Digital analog converter 

DB (7-0, P). Eight data-bit signals, plus a parity-bit signal, that form a DATA BUS. 

DC. Direct current 

DEMOD. Demodulator 

DET. Determination 

DMA. Direct memory access 

DTE. Disable transfer on error 

DVSLTD. Device select 

ECC. Error correction code 

ECL. Emitter-coupled logic 

EEC. Enable early connection 

EIA. Electrical Industry Association 

ENCRD. Encoded read data 

ENDATA. Encoded data 

ENDEC. Encoder/decoder 

EPROM. Erasable programmable read only memory 


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ESDI. Enhanced Small Device Interface 

EXPRCMP. External preamble complete 

FCC. Federal Communication Commission 

FIRMWARE. Computer programs encoded permanently into a ROM 

FW. Firmware 

G. Constant of gravitation 

GND. Ground 

HARD ERROR. An error due to faulty equipment, transmission techniques, recording me- 
dia, etc. 

HDA. Head/disk assembly 
HEX. Hexadecimal 

HNX, HNY. Head (zero through five) input x, head (zero through five) input y 

HW. Hardware 

I/O. Input and/or output 

ISG. Inter-sector gap 

ISO. International Standardization Organization 

LBA. Logical block address 

LED. Light-emitting diode 

LSB. Least significant bit 

MAP. Master pulse 

MAPERR. Master pulse error 

MAPIN. Master pulse in 

MAPOUT. Master pulse out 


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pC. Microcomputer 
^.COMPUTER. Microcomputer 
MSB. Most significant bit 
MSIN. Message in 
MTBF. Mean time between failures 
MTTR. Mean time to repair 
N.C. No connection 

NEGATE. A signal driven to the false state 

NOM. Nominal 

NRZ. Nonreturn to zero 

OEM. Original equipment manufacturer 

ONE. True signal value 

P/N. Part number 

P-P. Peak to peak 

PARITY. A method of checking the accuracy of binary numbers 

PC. Polycarbonate 

PCB. Printed-circuit board 

PCF. Page control field 

PES. Position error signal 

PLL. Phase-locked loop 

PLO. Phase-locked oscillator 

PM. Preventive maintenance 


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PMI. Partial medium indicator 

POH. Power On hours 

PRDET. Preamble detected 

PREAMP. Preamplifier 

PROM. Programmable read only memory 

PTRN. Pattern 

QUAL. Qualification 

R/W. Read and/or write (heads) 

RAM. Random-access memory 
RD/REF CLK. Read/reference clock 
RDGAT. Read gate (to U262) 

RDGT. Read gate 
RDRFCK. Read/reference clock 
RDX,Y. Read data x, read data y 
REF. Reference 

RESERVED. Bits, bytes, fields and code values that are set aside for future standardiza- 
tion. 

REVS. Revolutions 
RFCLK. Reference clock 
RGATE. Read gate (to U60) 

RLL. Run-length limited 
ROM. Read-only memory 
RSRV. Reserved 


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SCSI. Small Computer Systems Interface 

SLC. Servo/logic chip 
SPEC. Specification 

SRDX.Y. Servo read data x, servo read data y 
STD. Standard 
SVOCLK. Servo clock 
SW. Software 

SYNC. Synchronization, synchronous 
SYNCLK. Synchronized clock 
SYNCSP. Synchronous spindle 
SYNDET. Synchronized data 

TBD. To be determined. Values which are not defined as of the date this manual is pub- 
lished. 

TLA. Top level assembly 
TTL. Transistor-transistor logic 
TYP. Typical 

UL. Underwriter's Laboratories, Inc. 

UNC. Unified National Coarse 
UNF. Unified National Fine 
UNSCODE. Unsynchronized code 
VCO. Voltage controlled oscillator 
VCOCLK. VCO clock 

VDE. Verband Deutscher Electrotechniker 

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VEL. Velocity 

VENDOR UNIQUE. The bits, fields, or code values that are vendor specific. 

VREF. Voltage reference 

WCLK. Write clock (to U60 from interface) 

WCS. Write current select 
WDI. Write data input 
WGATE. Write gate (to U60) 

WRITE*. -WRITE to preamplifier chip 

WRT. Write 

WRTCLK. Write clock 

WUS. Write unsafe output 

XFER. Transfer 

ZERO. False Signal code 


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