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Operation and maintenance manual 



Kennedy co. Model 9800 

Digital Tape Transport 



006-9801-300 



CONTENTS 



SECTION I — APPLICATION DATA 



1.1 Introduction » 1-1 

1.2 Electrical & Mechanical Specifications 1-1 

1.3 Controls & Indicators 1-4 

1.4 Interface Connections . . » 1-6 

1.5 Interface Signal Characteristics .... 1-6 

1.6 Input Signal Description . . 1-6 

1.7 Output Signal Description 1-6 

1.8 Tape Motion Commands 1-6 

1. 9 Interface Input Signals 1-6 

1.9.1 Setup Commands 1-6 

1.9.2 Tape Motion Commands .... 1-9 

1.9.3 Write Commands 1-9 

1.9.4 Read Commands 1-10 

1. 10 Interface Output Signals 1-10 

1.10.1 Status Outputs 1-10 

1.10.2 Read Outputs 1-11 

1.11 Summary of Interface Characteristics 1-11 

SECTION II — INSTALLATION AND OPERATION 

2.1 Installation 2-1 

2.1.1 Inspection 2-1 

2.1.2 Mounting 2-1 

2.1.3 Service Access . . . 2-1 

2.1.4 Intercabling 2-1 

2.1.5 Power Connections 2-1 

2.2 Operation 2-1 

2.2.1 Interface 2-1 

2.2.2 Controls and Indicators 2-1 

2.2.3 Preliminary Procedures .... 2-1 

2.2.4 Tape Threading 2-1 

2.2.5 Tape Loading .. 2-2 

2.2.6 Placing Tape Unit On Line . . . 2-2 

2.2.7 Tape Unloading and Rewind . .. 2-2 

2.2.8 Power Shutdown 2-2 

SECTION III — THEORY OF OPERATION 

3.1 Introduction 3-1 

3.2 Control Logic 3-1 

3.2.1 Introduction 3-1 

3.2.2 Control Logic Operation During 

a Write Sequence ......... 3-1 

3.2.3 Test Panel 3-3 

3.2.4 Control Logic Adjustments . . 3-3 

3.3 Servo System 3-4 

3.3.1 Introduction 3-4 

3.3.2 Reel Servos 3-4 

3.3.3 Capstan Servo 3-5 



3.3.3 Capstan Servo 3-5 

3.3.4 Servo System Adjustments ... 3-5 
3.4 Data Section . o 3-6 

3.4.1 Introduction 3-6 

3.4.2 Write Electronics 3-6 

3.4.3 Read Electronics 3-6 

3.4.4 Data Section Adjustments ... 3-7 

SECTION IV — MAINTENANCE INSTRUCTIONS 

i 

4. 1 General 4-1 

4.2 Preventive Maintenance 4-1 

4.2.1 Daily Check 4-1 

4.2.2 Cleaning 4-1 

4.2.2.1 Head Cleaning 4-1 

4.2.2.2 Tape Path Cleaning 4-1* 

4.2.2.3 Other Cleaning 4-2 

4.2.3 Visual Check 4-2 

4. 3 Routine Adjustment . . 4-2 

4.4 Lubrication 4-2 

4.5 Wear 4-2 

4. 5. 1 Head Wear . 4-2 

4. 5.2 Guide Wear . . . 4-2 

4.5.3 Reel Hubs 4-2 

4. 6 Periodic Inspection . . 4-2 

4.7 Checks and Adjustments 4-4 

4.7.1 Test Panel 4-4 

4.7.2 Skew Adjustment 4-4 

4.7.2.1 Introduction 4-4 

4.7.2.2 Read Skew Adjustment ... 4-4 

4.7.2.3 Write Skew Adjustment . . . 4-4 

4.7.2.4 Tape Speed Check . . 0 . . . 4-5 

4.7.3 Tape Path Checks 4-5 

4.7.4 Tape Path Adjustments .... 4-5 
4. 7. 4. 1 Tension Arm Roller Guide . 4-5 
4.7.4.2 Direction Reversing Idler . 4-6 

4.7.5 Tape Tension Check 4-6 

4.7.6 Tension Arm Position Check. 4-7 

4.7.7 Electrical Adjustments .... 4-8 

4.7.7.1 Introduction . . 4-8 

4.7.7.2 Control Section 

Adjustments 4-8 

4.7.7.3 Servo System 

Adjustments 4-8 

4.7.7.4 Data Section 

Adjustments 4-9 

4.8 Parts Replacement 4-9 

4.8.1 Head Replacement 4-9 

4.8.2 Capstan Motor Replacement . 4-9 

4.8.3 Reel Motor Replacement . . . 4-9 



iii 



006-9801-400 



CONTENTS 

(continued) 



4.8.4 Tension Magpot 

Replacement 4-9 

4.8.5 Voltage Regulator/ Servo 
Power Assembly 

Replacement 4-10 

SECTION V - PARTS IDENTIFICATION 

5. 1 Ordering Information 5-1 

5„2 Export Orders 5-1 

5.3 Parts List 5-1 

5.4 Field Kits 5-1 



SECTION VI — WIRING AND SCHEMATIC 
DIAGRAMS 



SECTION VII — GENERAL INFORMATION AND 
APPENDIX 



1600 cpi Data Electronics Schematics 

i 

or 

Dual Density 800/1600 cpi Schematics 



FIGURES 



l-l 

1-2 
1-3 

1-4 
1-5 
1-6 

1-7 



1-9 



Model 9800 Outline and Installation 3-2 

Drawing 1-3 3-3 

Controls and Indicators 1-4 3-4 

Test Panel Controls and Indicators ... 1-5 4-1 

Typical Receiver Circuit 1-6 4-2 

Typical Interface Configuration 1-7 4-3 

Read after Write Tape Transport 

Write Start and Stop Delays . . 1-7 4-4 

Read after Write Tape Transport 4-5 

Reading Forward 1-8 4-6 

Read after Write Tape Transport 4-7 

Reading in Reverse 1-8 5-1 

Summary of Interface 5-2 

Characteristics 1-12 5-3 

Tape Threading Diagram 2-2 5-4 

Control Logic Block Diagram ....... 3-2 5-5 



Reel Servo System 3-5 

Write Data Section 3-7 

Read Data Section 3-8 

Opening of Head Shield 4-1 

Head Skew Adjustment . 4-4 

Write and Read Amplifier Channel 

Locations * 4-5 

Skew Adjustment Waveforms 4-5 

Roller Guide Adjustment 4-6 

Idler Adjustment .... * 4-6 

Magpot Position Sensor 4-7 

Parts Identification, Front View 5-2 

Parts Identificati6n, Front View 5-3 

Parts Identification, Rear View. ..... 5-4 

Parts Identification, Rear View. ..... 5-5 

Parts Identification, Top View ...... 5-6 



TABLES 



1-1 Model 9800 Series Tape Transport 

Electrical & Mechanical Specifications < 1-1 



3- 1 Transport Status 

4- 1 Routine Maintenance Schedule 



3- 4 

4- 1 



iv 



SECTION I 
APPLICATION DATA 



106-9801-100 A 



SECTION I 



APPLICATION DATA 



1.1 INTRODUCTION 

The Kennedy Model 9800 is a synchronous digital 
magnetic tape unit that with proper external format- 
ting control is capable of reading and writing IBM 
compatible tapes, and is used in applications re- 
quiring high reliability at moderate tape speeds. 
Typical applications include operation with mini- 
computers, high speed data collection systems, and 
computer peripherals. 

The Model 9800 is equipped with the electronics 
necessary for reading and writing tapes and for 
controlling the tape motion 0 The head specifications 
and the mechanical and electrical tolerances of the 
Model 9800 meet the requirements for IBM compati- 
bility. However, the formatting electronics, parity 
generator, cyclic redundancy check character (CRCC) 
generator, gap control, etc , are not included and 
must be provided by the tape control and formatter 



in order to generate properly formatted IBM com- 
patible tapes. 

The standard Model 9800 is available in 7 or 9 track 
NRZI and 9 track phase encoded recording configu- 
rations. Standard data recording densities are: 
200/556 cpi or 556/800 cpi for 7 track NRZI, 800 
cpi for 9 track NRZI, 1600 cpi for 9 track phase 
encoded and 800/1600 cpi for dual density 9 track 
NRZI (density select switch, supplied). 

The standard tape speed is 12.5 ips; however, tape 
speeds from 10 to 25 ips are available. The data 
transfer rate at 12.5 ips, 800 cpi is 10 kHz. 

Read- after- write electronics, using a dual gap, 
write- an d-read head assembly with a side- mounted 
full width erase head, are available in both seven- 
and nine -track configurations, allowing for read- 
after-write operation. 



1.2 ELECTRICAL AND MECHANICAL SPECIFICATIONS 



Tape (computer grade) 

Width . ...... 0.5 inch (1.27 cm) 

Thickness 1. 5 mil (0 o 038 mm) 

Tension „ 8.0 ounces (227 gm) 

Reel diameter 0 . <> . to 8.5 inches (21 0 53 cm) 

Capacity 1200 feet (360m) 

Reel hub 3.69 inches (9.37 cm) dia 

per IBM standards 

Reel braking Dynamic 

Recording mode (IBM compatible) .... NRZI 

Tape drive Single capstan 

Tape speed .... 10-25 ips (25 0 4-63. 5 cm/sec) 

Instantaneous speed variation . . . ±3% 

Long term speed variation . . ±1% 

Start/stop displacement 0. 1875 inch (0.476 cm) 

Start/stop time @ 12.5 ips . 30 ms 

Rewind speed . . . 0 . 120 ips (3.05m) (nominal) 

Magnetic head assembly 
(Write to read gap displacement) 

Dual gap seven-track read after write 

0.30 inch (0. 76 cm) 

Dual gap nine-track read after write 

0.15 inch (0.38 cm) 

Interchannel displacement error . . (measured 
with IBM master skew tape PN 432362) 
Write (maximum) . . . 150 finches (3.8 Jim) 
Read (maximum) . . . 150 finches (3.8 |im) 



Erase head » 0 Full width 

Load point and end of tape reflective strip 

detection Photoelectric 

(IBM compatible) 

Broken tape detection Photoelectric 

Dimensions (see Figure 1-1) 

Transport mounting (horizontal) 

. . . Standard 19-inch (48.26 cm) RETMA rack 

Height . . 12.5 inches (31.75 cm) 

Width 19.0 inches (48.26 cm) 

Depth (from mounting surface) 

13.37 inches (33.96 cm) 

Depth (overall) . 15.87 inches (40.31 cm) 
Weight (transport only) . 45 pounds (20.25 kg) 
Shipping weight 60 pounds (27.00 kg) 

Operating environment 

Ambient temperature +2 to +50 C 

Relative humidity (noncondensing) . 15% to 95% 
Altitude . o to 30,000 feet (9120m) 

Power requirements » . . . 115/230 vac 

50 to 500 Hz, single phase 

Volt amps nominal 200 

Volt amps maximum 300 



Table 1-1. Model 9800 Series Tape Transport Electrical and Mechanical Specifications 



i-l 



106-9801-200 




DUST COVER OPENS 
APPROXIMATELY 
140 DEGREES. 




1.49 
(3. 78) 



4. 99 

12.57) 



2.25 
(5.86: 



3.50 
(8.89) 

4.99 
! 12 . 57 ) 



1.49 
(3. 78) 



-©- 



51 



J2 




©0 ©< 

)®0 



A Jl CONTROL V 



18 J3 READ 1 



5.25 
(13.33) 



8.25 
(20. 95 ) 



1.25 
(3. 18) 



3.84 
(9.75) 



2.81 . I _ 4. 
"(7. 13) — *T" ( 11 A 



1.81 * 
(4.59) 



17.00 
(43. 18) 



©INPUT POWER. CONNECTOR 0.P1. CONTROL CONNECTOR © P2 WRITE CONNECTOR 0 P3 READ CONNECTOR 

(POWER CABLE 125-0068-001 MATING CONNECTOR PART MATING CONNECTOR PART MATING CONNECTOR PART 

SUPPLIED WITH UNIT) NUMBER 12 1-0O96-036 . NUMBER 121-0096-036 NUMBER 12 1-0096-036 



410-4015 



106-9801-300 



19.00 
(48.26 ) ' 




12.22 
(31.03) 



MOUNTING HOLES ARE FOR 
ZERO NONTILT TYPE SLIDE 
NO. C300- 14(KENNEDY PART 
NO. 198- 00 14- 00 1, OPTIONAL) 





- -25(.63) 



.45 \~* 



(1.14) 



DETAI L © 
TYPICAL SLOT 
PATTERN 



410-4015 



NOTE: DIMENSIONS SHOWN ARE IN 

INCHES. DIMENSIONS IN PARENTHESES 
ARE IN CENTIMETERS. 



Figure 1-1. 
Outline and Installation Drawing, 
Model 9800 



106-9801-400 



1.3 CONTROLS AND INDICATORS 



ON LINE LOAD REWIND 

• WRITE STATUS • • • 



• READ STATUS 

• WRITE ENABLE 



ON LINE PUSHBUTTON/INDICATOR 

A momentary pushbutton, which functions as alternate action. When first activated 
the tape unit is placed in an on-line condition; when the tape unit is on line it can be 
remotely selected and will be ready if tape is loaded to or past the load point. When 
activated again it takes the unit off line. The LED indicator is illuminated in the on- 
line condition. A short time lag is built in between closure and action to prevent 
accidental operation. 

LOAD PUSHBUTTON/INDICATOR 

The momentary pushbutton activates the reel servos (tensions tape) and starts the 
load sequence. The LED indicator is illuminated when the reel servos are activated 
and tape is tensioned. 

REWIND PUSHBUTTON/INDICATOR 

The momentary pushbutton activates a rewind operation. This control is enabled 
only when tape is tensioned and unit is off line. The LED indicator is illuminated 
during either a local or remote rewind operation. 

WRITE STATUS INDICATOR 

Indicator is illuminated whenever tape unit is on line, selected, and write status is 
selected. 

READ STATUS INDICATOR 

Illuminated when tape unit is on line, selected, and read selected. 

WRITE ENABLE INDICATOR 

Illuminated whenever a reel with a write enable ring is mounted on the supply (file) 
hub. 

LOAD and REWIND pushbuttons are disabled when the tape unit is on line. 



Figure 1-2. Controls and Indicators 



1-4 



106-9801-500A 



0 



O TEST MODE 



O WRITE TEST 



LOAD 
POINT 



EOT 

O 



STOP 



FORWARD 
RUN 



REVERSE 
RUN 



DATA 

O 

FAST 
SKEW FORWARD 



FAST 
REVERSE 



© 

Df 

0©' 



Note 

Tape transport must be off line and STOP pushbutton 
depressed before test panel can become functional. 



TEST MODE pushbutton and indicator. A momentary pushbutton se- 
lects test mode and activates test panel. When indicator (LED) is 
illuminated, test panel is active. (Tape unit must be off line and 
STOP pushbutton depressed before test panel will function. ) 



WRITE TEST pushbutton and indicator. A momentary pushbutton 
which programs l's to be written on all channels in order to facilitate 
write skew adjustment. WRITE TEST remains active in FORWARD 
RUN mode only. (STOP pushbutton must be depressed and TEST 
MODE selected to actuate this feature.) The indicator (LED) will 
remain illuminated while unit is in this mode. 

STOP pushbutton. An interlocked pushbutton switch which terminates 
all tape motion. 

FORWARD RUN pushbutton. An interlocked pushbutton switch that 
allows tape unit to proceed forward at normal speed. Depressing 
STOP pushbutton or EOT marker will terminate this operation. 

REVERSE RUN pushbutton. An interlocked pushbutton switch which 
allows tape unit to run in reverse at normal speed. Depressing STOP 
pushbutton or BOT marker will terminate this operation. 

FAST FORWAKD pushbutton. An interlocked pushbutton switch that 
allows tape unit to run forward at 150 ips. Depressing STOP push- 
button or EOT marker will terminate this operation,, 

FAST REVERSE pushbutton. An interlocked pushbutton switch that 
allows tape unit to run in reverse at 150 ips. Depressing STOP push- 
button or BOT marker will terminate this operation. 



^) LOAD POINT indicator (LED). Indicates when tape is at load point. 
@ EOT indicator (LED). Indicates when tape is at EOT. 



DATA indicator (LED), 
read/ write electronics. 



Indicates when data is being processed by 



SKEW indicator (LED) and TEST point. Indicator lights if tape skew 
exceeds the appropriate skew (read or write) gate setting. An oscil- 
loscope TEST point is available for monitoring all read pulse outputs 
simultaneously, displaying total bit scatter. 



Figure 1-3. Test Panel Controls and Indicators (Optional) 



106-9801-600 



1.4 INTERFACE CONNECTIONS 



1.7 OUTPUT SIGNAL DESCRIPTION 



The interface connectors on the Model 9800 are de- 
signed for twisted pair inputs and outputs. For each 
active pin there is a ground pin. The mating inter- 
face connectors, three 36-pin edge connectors (PN 
121-0096) are supplied with the tape unit. 



Each output line is driven with an open collector 
current sinking logic driver which is c apable of sink- 
ing up to 40 ma in the true state. All outputs are 
disabled (false) when the tape unit is not on line and 
selected. 



1.5 INTERFACE SIGNAL CHARACTERISTICS 

The tape unit responds to zero true inputs and pro- 
vides zero true outputs. Each signal input is termi- 
nated in such a manner as to provide matching for 
twisted pair cables. See Figure 1-4. Each output 
line is driven with an open collector driver. For 
best results the typical interfacing circuit config- 
urations shown in Figure 1-5 should be used. The 
recommended twisted pair cable will reduce the 
magnitude of intercable crosstalk. Unless otherwise 
specified all wires should be 24 AWG minimum, with 
a minimum insulation thickness of 0.1 inch. Each 
pair should have not less than one twist per inch and 
the input-output cables should not exceed 20 feet in 
length, 



1.6 INPUT SIGNAL DESCRIPTION 

The input receiver circuits, due to zero true current 
sinking logic design, will interpret a disconnected 
wire or removal of power at the transmitter as a 
logic 0 or false condition. The logic 1 or true state 
requires 25 ma current sink with less than 0.4v. 

The logic 0 or false state will be 3v due to the input" 
matching resistors (see Figure 1-4). The recom- 
mended input pulse width is 2 microseconds. The 
rise and fall times for pulses arid levels must be 
less than 0.5 microsecond. Each input iS enabled 
when the tape transport is on line and selected. 



+ 5V 



TAPE TRANSPORT 
RECEIVER 



220 



4> 



1330 5 TTL 7400. 

f DTL 836 1 

OR EQUI V 



1.8 TAPE MOTION COMMANDS 

For maximum interface convenience, Model 9.S00 is 
configured to control tape motion and direction using 
the SYNCHRONOUS FORWARD command and SYN- 
CHRONOUS REVERSE commajnd. The tape transport 
capstan servo accelerates the tape to the required 
speed with a linear ramp. The tape is also deceler- 
ated to a stop with a linear ramp. Start and stop 
occurs within the interrecord gaps. The ramp time 
is 'AO ms for 12.5 ips and varies inversely with tape 
speed. The amount of tape travel during the ramp 
up or ramp down is always 0. 1875 inch. 

These two factors are to be taken into consideration 
when writing and gapping. A delay is required be- 
fore writing to insure that tape is up to speed and to 
allow read after write. Timing diagrams for perti- 
nent commands to provide properly formatted tapes 
are shown in Figures 1-6 through 1-8. 

Figure 1-6 shows the timing requirements for writing 
a block in a read after write system (dual gap head) 
in the write mode with read occurring immediately 
after writing. Figure 1-7 shows the timing require- 
ments for reading a block on a read after write sys- 
tem in the forward direction. Figure 1-8 shows the 
timing requirements for reading a block on a read 
after write system in the reverse direction. 

1.9 INTERFACE INPUT SIGNALS 

All commands from and to the input/output connector 
are preconditioned by loading the machine and plac- 
ing it on line using the front panel controls. The 
next commands set up the recorder, 

1.9.1 SETUP COMMANDS 



TRANSPORT SELECT 

SLT Level 



Pl-J 



Figure 1-4. Typical Receiver Circuit 



Alevel that when true enables all the interface driv- 
ers and receivers in the transport, thus connecting 
the transport to the controller. Transport must also 
be on line, and SLT must be true for entire write 
sequence (until tape motion stops). The SLT level 
may be removed to disconnect the machine from the 
system. The machine will remain in the last condi- 
tion established by SWS. 



1-6 



106-9801-700 



DTL 858 
OR EQUIV 



TAPE TRANSPORT 



+ 5V 



20 FT MAX 



+ 5V 



220 




330 



DTL 836 
OR EQUIV 



TAPE CONTROL UNIT 



DTL 836 
OR EQUIV 



220 



330 
+ < 




<1 



DTL 858 
OR EQUIV 



1 



Figure 1-5. Typical interface Configuration 



STOP 
RUN 



WRITE START 
DELAY 

t WSD* t R +t GD 

t - - 450 
WSD S 



WRITE 
GAP DELAY 
.075 



TAPE 

VELOCITY 



WRITE DATA 
STROBE 



READ DATA 
STROBE 



t=TIME-SECONDS 
S=SPEED-IPS 



GAP DETECT 



RAMP 
*R- 



375" 



FIRST DATA BYTE \^J|__ ||| I I 

READ DELAY — _____ ' ' ^ 
t RD*^F (9 TRACK ) 

{7 TRACK) I ^ 



FIRST DATA 
BYTE 



LAST DATA BYTE 



10 CHARACTER 
TIMINGS MINIMUM |„. j 



RAMP 
_. . 375 
t R" S 




CHECK CHARACTER ( S ) 
LAST DATA BYTE 



CHECK CHARACTE R ( S ) 



WRITE STOP DELAY 

.025 
tSD*~~T 



Figure 1-6. Read after Write Tape Transport Write Start and Stop Delays 



1-7 



106-9801-800 



STOP 



RUN 



TAPE 

VELOCITY 



READ DATA 
STROBE 



GAP DETEC 




CHECK CjHARACTER(S) 

10 CHARACTER 
TIMINGS MINIMUM 



t=TlME-SECONDS 
S=SPEED-IPS 



Figure 1-7. Read after Write Tape Transport Reading Forward 



STOP 
RUN 



TAPE 

VELOCITY 

READ DATA 
STROBE 



RAMP 



375 



RAMP 

t «ai5 



CHECK CHARACTE R ( S ) 

LAST DATA BYTE 



LLJIIIU -JIIIK 



GAP DETECT 




FIRST DATA BYTE 



READ STOP DELAY 
tRSD-T 1 O TRA CK) 

^sp-j 2 (7 TRACK > 



10 CHARACTER 
TIMINGS MINIMUM 



t=TIME-SECONDS 
S=SPEED-IPS 



Figure 1-8. Read after Write Tape Transport Reading in Reverse 



1-8 



106-9801-900 



DATA DENSITY SELECT 

(Dual Density only) 

DDS Level Pl-D 

Used when the TRANSPORT DENSITY SKLECT switch 
is in the remote position. When true, this level 
selects the high read density (dual density). 

1.9.2 TAPE MOTION COMMANDS 
OVERWRITE (optional) 

OVW Level Pl-B 

A level that when true conditions appi'opriate circuitry 
in the trans|x>rt to allow updating- (rewriting) of. a 
selected record. The transport must be in the write 
mode of operation to utilize the OYW feature. 

SYNCHRONOUS FORWARD COMMAND 

SEC Level Pl-C 

A level that when true, and the transport is ready 
and on line, causes tape to move forward at the spec- 
ified speed. When the level goes false, tape motion 
ramps down and ceases. 

SYNCHRONOUS REVERSE COMMAND 

SRC Level Pl-E 

A level that when ti'ue, and the transport is ready 
and on line, causes tape to move in a reverse direc- 
tion at the specified speed. When the level goes false, 
tape motion ceases. If the load point marker is de- 
tected during an SRC, the SRC will be terminated. 
If an SRC is given when the tape is at load point, it 
will be ignored. 

REWIND COMMAND 

RWC Pulse Pl-H 

A pulse input will rewind the tape past the load point 
and stop. The transport will then initiate a load for- 
ward sequence and return the tape to the load point 
marker. This input will be accepted only if the load 
point output is false. The transport may be taken 
off line while rewind is still in process. Rewind will 
continue normally. 

1.9.3 WRITE COMMANDS 
SET WRITE STATUS 

SWS Level Pl-K 

A level that must be true at the leading edge of an 
SFC (or RUN and FWD) when the write mode of oper- 
ation is required, and must remain true for a mini- 
mum of to fisec after the leading edge of the SFC 
(or RUN and FWD). SWS is sampled at the leading 



edge of the SFC or SRC (or RUN and FWD), toggling 
the read/write flip-flop to the appi'opriate state. In- 
ternal interlocks in the 9800/9700 will prevent writ- 
ing in the reverse direction, when the write enable 
ring is missing, when the tape unit is off line, when 
loading to a load point, and during a rewind. 

WRITE DATA INPUTS 



Nine Track 


Seven Track 




WDP 


WDC 


P2-L 


WD0 




P2-M 


WD1 




P2-N 


WD2 


WDB 


P2-P 


WD.'} 


wda 


P2-R 


WD4 


WD8 


P2-S 


WD5 


WD4 


P2-T 


WD6 


WD2 


P2-1 


WD7 


WD1 


P2-Y 



Nine lines for nine-track operation, seven lines for 
seven-track operation. These are levels that if true 
at WDS time will result in a flux transition being re- 
corded on tape (transport is in the write mode). Data 
inputs must have settled 0.5 pisec before the leading 
edge of the WDS pulse and must remain quiescent 
0.5 jLisec beyond the trailing edge of the WDS pulse. 
The CRCC is written by providing the correct data 
character together with a WDS four character times 
after the last data character of the record. 

The LRCC is written using the WARS signal. The 
LRCC can also be written by providing the correct 
data character together with a WDS. If the LRCC is 
written (DATA-WDS) in this manner a WARS should 
be given one character time after the LRCC to insure 
proper IRG erasure in case of data input error. 

WRITE DATA STROBE 

WDS Pulse P2-A 

A pulse of 2 /Usee nominal width for each character 
to be written. Writing occurs on the leading edge of 
the WDS. WDS may be a 1 /isec minimum, 3 /isec 
maximum pulse. Data inputs must have settled for 
at least 0.5 /isec before the leading edge of WDS 
and remain quiescent for at least 0. 5 fisec beyond 
the trailing edge. 

WRITE AMPLIFIER RESET 

WARS Pulse P2-C 

A pulse of 2 fisec nominal width that, when true, re- 
sets the write amplifier circuits on the leading edge. 
The purpose of this line is to enable writing of the 
longitudinal redundancy check character (LRCC) at 
the end of a record. This insures that all tracks are 
properly erased in an interrecord gap (IRG). 



1-9 



106-9H02-000 



In a seven-track system, the leading edge of the WARS 
pulse should be four character times after the lead- 
ing edge of the WDS associated with the last data 
character in the block. In a nine-track system, the 
leading edge of the W ARS pulse should be eight char- 
acter times after the leading edge of the WDS asso- 
ciated with the last data character in the block (four 
character times after the CRCC is written). 

1.9.4 READ COMMANDS 

A read after write machine will always have read 
selected. When write is selected (SWS) the data just 
written will be read back using a high threshold level 
on the read amplifiers. When SWS is false the nor- 
mal threshold is applied to the read amplifiers. 



AUTOMATIC CLIPPING LEVEL DISABLE 

ACLD Level 



P3-6 



When true this level overrides the automatic clipping 
level electronics and holds the read electronics in 
the normal clipping level. 

1.9.5 SHUTDOWN COMMANDS 

The use of a given magnetic tape unit may be termi- 
nated by an OFF LINE command. Once this command 
is given the tape unit may be returned to an interface 
command only by operating the front panel ON LINE 
switch. 



OFF LINE COMMAND 

OFFC 



Pulse 



Pl-L 



A level or pulse (minimum width 2 J/sec) that resets 
the on-line flip-flop to the zero state, placing the 
transport under manual control. It is gated only by 
SELECT in the transport logic, allowing an OFFC 
to be given while a rewind is in progress. An OFFC 
should be separated from a rewind command by at 
least 2 Jisec. 



TRANSPORT READY 

RDY 



Level 



Pl-T 



A level that is true when the tape transport is on tape; 
that is, when the initial load sequence is complete 
and the transport is not rewinding. When true, the 
transport is ready to receive a remote command. 



HIGH DENSITY INDICATOR 

(Dual Density only) 

HDI Level 



Pl-F 



A level that is true only when the high- density mode 
of operation is selected. 



FILE PROTECT 

FPT 



Level 1 



Pl-P 



A level that is true when a reel of tape without a 
write- enable ring is mounted on the transport supply 
(or file) hub. 



WRITE ENABLE 

WEN 



Level 



Pl-S 



A level that is true when a reel of tape with a write- 
enable ring is mounted on the transport supply (or 
file) hub. Opposite of file protect. 



LOAD POINT 

LDP 



Level 



Pl-R 



A level that is true when the load point marker is 
under the photosensor and the transport is not re- 
winding. After receipt of an SFC the signal will 
remain true until the load point marker leaves the 
photosense area. (Circuitry using this output should 
not use the transitions to and from the true state. ) 



TAPE RUNNING 

RNG 



Level 



Pl-V 



This is a level that is true when tape is being moved 
under capstan control and remains true until tape 
motion has ceased. (Includes forward, reverse, and 
rewind tape motion. ) 



1.10 INTERFACE OUTPUT SIGNALS 

All output signals are enabled only when the tape 
transport is on line and selected. 

1.10.1 STATUS OUTPUTS 



ON LINE 

ONL 



Level 



Pl-M 



A level that is true when the on-line flip-flop is set. 
When true, the transport is under remote control. 
When false, the transport is under local control. 



END OF TAPE 

EOT 



Level 



Pl-U 



A level that is true for the duration of the EOT mark- 
er. (Circuitry using this output should not use the 
transitions to and from the true state. ) 



REWINDING 

RWD 



Level 



Pl-N 



A level that is true only when the transport is engaged 
in a rewind operation or returning to the load point. 
(Goes true approximately 5 ^isec after a rewind com- 
mand is given* ) 



1-10 



106-9802-100 



1.10.2 READ OUTPUTS 

Read outputs are present at all times in tape units 
when a dual gap head is used (read after write). The 
high threshold level is selected internally when SWS 
is selected. In a read/ write tape unit (single gap 
head) read outputs are inhibited when SWS is true. 

READ DATA STROBE 

RDS Pulse P3-B 

A pulse of 2 /isec minimum width for each data char- 
acter read from tape. Although the average time 
between two read data strobes is 



T (sec) — — - 
1 s • d 

where 

s - tape speed in inches per second 
d - density characters per inch 



the minimum time between consecutive read data 
strobes is less than this figure due to skew and bit 
crowding effects. A guaranteed safe value for the 
minimum time is 1/2 r^. 

READ GAP DETECT 

RGAP Level P3-N 

A level that is true approximately nine character 
spacings after the last data byte (five character spac- 
ings on seven- channel), and remains true until the 
first data byte of the subsequent data block. Note: 
This level will be true whenever tape motion is at 
rest. 



READ DATA LEVEL 



Nine Track 


Seven Track 




RDP 


R DC 


P3-1 


RD0 




P3-3 


RD1 




P3-4 


RD2 


RDB 


P3-« 


RD3 


RDA 


P3-9 


111)4 


RD8 


P3-14 


RDS 


RD4 


P3-15 


RD6 


RD2 


P3-17 


RD7 


xRDl 


P3-1* 



Nine lines, nine track; seven lines, seven track. 
Nine (or seven) staticisers; are provided, which act 
as a one-stage read deskewing buffer. Each output 
is a level that changes to the appropriate state ap- 
proximately 1 /usee before the read data strobe and 
remains in that state until 1 /isec before the next 
read data strobe. Data lines return to false condi- 
tion in the IRG when tape motion stops regardless 
of the last character read. 

It is recommended that read data strobes and the 
read gap detect be ignored during the first read or 
write operation from load point for msec after 
the load point output goes false, where 1000/s 
(s speed of tape unit). 

The read gap in a read after write tape unit is down- 
stream from the write gap. Thus when the write gap 
is initially energized the read gap may detect a flux 
change depending on the initial state of magnetism 
on the tape. 

1.11 SUMMARY OF INTERFACE CHARACTERISTICS 

Figure 1-9 shows the location of connectors and pin 
numbers with signal names. 



1-11 



106-9802-200A 



3 



V «>2 WRITE A A Jl CONTROL V 



18 J3 READ 



ACTIVE 
A 
B 
C 
D 
E 
F 
H 
J 
K 
L 
M 
N 
P 
R 
S 
T 
U 
V 



ACTIVE 
A 



ACTIVE 
1 
2 
3 
4 
5 
6 
7 



9 
10 
11 
12 
13 
14 
15 
16 
17 
18 



GROUND 
1 ■ 



GROUND 
1 

2 • 

3 • 

4 • 

5 - 

6 ■ 

7 • 

8 ■ 

9 ■ 

10 - 

11 ■ 

12 - 

13 ■ 

14 ■ 

15 • 

16 ■ 

17 • 

18 ■ 



GROUND 
A • 
B • 
C ■ 
D ■ 
E 

F ■ 

H 

J ■ 
K • 
L 
M 

N • 

P 

R • 

S ■ 
T 

U • 
V ' 



INPUT 
■OUTPUT 



WHITE CONNECTOR J2 



SIGNAL 
WRITE DATA STROBE 
N. C. 

WRITE AMPLIFIER RESET 

NOT USED 

NOT USED 

NOT USED 

NOT USED 

NOT USED 

NOT USED 

WRITE DATA CHANNEL P 
WRITE DATA CHANNEL 0 
WRITE DATA CHANNEL 1 
WRITE DATA CHANNEL 2 
WRITE DATA CHANNEL 3 
WRITE DATA CHANNEL 4 
WRITE DATA CHANNEL 5 
WRITE DATA CHANNEL 6 



WRITE DATA CHANNEL 7 

CONTROL CONNECTOR II 



REM CONNECTOR J3 



SIGNAL 
READ DATA CHANNEL P 
READ DATA STROBE 
READ DATA CHANNEL 0 
READ DATA CHANNEL 1 
NOT USED 
AUTO DISABLE 
NOT USED 

READ DATA CHANNEL 2 
READ DATA CHANNEL 3 
NOT USED 
NOT USED 
GAP DETECT 
NOT USED 

READ DATA CHANNEL 4 
READ DATA CHANNEL 5 
NOT USED 

READ DATA CHANNEL 6 
READ DATA CHANNEL 7 



MNEMONI C 
WDS 



WDP 
WDO 
WD1 
WD2 
WD3 
WD4 
WD5 
WD6 
WD7 



SIGNAL 


MNEMONI C 


SPARE 




OVERWRI TE 


OVW 


SYNCHRONOUS FORWARD 


SFC 


DATA DENSITY SELECT 


DDS 


SYNCHRONOUS REVERSE 


SRC 


DATA DENSITY INDICATOR 


DDI 


REWIND COMMAND 


RWC 


SELECT 


SLT 


SET WRITE STATUS 


SWS 


OFF LINE COMMAND 


OFFC 


ON LINE 


ONL 


REWINDING 


RWD 


FILE PROTECT 


FPT 


LOAD POINT 


LP 


WRITE ENABLE 


WEN 


TRANSPORT READY 


RDY 


END OF TAPE 


EOT 


TAPE RUNNING 


RNG 



MNEMONIC 
RDP 
RDS 
RDO 
RD1 



RD2 
RD3 



RD4 
RD5 



RD6 
RD7 



Figure 1-8. Summary of Inimrfmem Chmrmcfristics 



1-12 



SECTION II 
INSTALLATION AND OPERATION 



206-9801-100 



SECTION II 
INSTALLATION AND OPERATION 



2.1 INSTALLATION 

2.1.1 INSPECTION 

Prior to installation, inspect thoroughly for foreign 
material that may have become lodged in the tension 
arms, reel hubs, and other moving parts. 

2.1.2 MOUNTING 

Physical dimensions and outline of the tape transport 
are shown in Figure 1-1. The transport requires 
12.22 inches vertical mounting space on the standard 
19 inch rack. Transports in a system configuration 
should be arranged to require less than 20 feet of 
cabling between the Format Control Unit and the 
furthest tape unit. 

2.1.3 SERVICE ACCESS 

Access to the plug- in cards, the power supply, and 
the control electronics is available from the top of 
the unit. The voltage regulator and the servo power 
assembly are mounted on the inside of the heatsink 
on the rear of the transport. The voltage selection 
switch, fuse, power connector, and interface con- 
nectors are also accessible from the rear of the unit. 
For servicing electronics, test points are provided 
by standoff pins on circuit boards and are identified 
by upper case letters near each test point. 

2.1.4 INTERCABLING 

Installation of the tape transport requires fabrication 
of interconnection cables between the Format Control 
Unit and the tape transport. Three 36-pin cable con- 
nectors that mate with the connectors on the units 
are supplied with the system. 

The connector pin assignments are shown in Figure 
1-9. Twisted pair cabling should be used to reduce 
intercable crosstalk. AH wires should be 24 AWG, 
minimum, with a minimum insulation thickness of 
0.01 inch. Each pair should have no less than one 
twist per inch, and maximum cable length should not 
exceed 20 feet. 

2*1.5 POWER CONNECTIONS 



; CAUTION : 
1 ************* »» 

Before connecting the unit to the power 
source, make certain the line voltage 
selector switch, near power connector 



on rear flange, is set to correct volt- 
age (115 or 230 VAC) and that proper 
fuse has been installed (3A 3 AG for 
115 VAC, 1.5A 3 AG for 230 VAC). 

A detachable power cord is supplied with the tape unit. 
The power cord is 7.5 feet long and has a NEMA 
three-prong (two power, one chassis ground) plug 
for connection to the power Source. 

i 

2. 1. 6 TERMINATION OF INPUT LINES 

Terminator cards are provided to terminate input 
lines for minimum reflection. When machines are 
used singly or in a radial interface, terminators re- 
main in place. 

In a daisychain installation of two or more machines, 
terminators are removed from all machines except the 
machine at the greatest distance from the interface. 

2.2 OPERATION 

2.2.1 INTERFACE 

Before placing the unit in operation, make certain 
that the interface connection procedures outlined in 
Section I have been performed. 

2.2.2 CONTROLS AND INDICATORS 

Paragraph 1. 3 lists the controls and indicators for 
the tape transport and describes the functions of each. 
The optional test panel controls are shown in Figure 
1.3. 

2.2.3 PRELIMINARY PROCEDURES 

Before placing the unit in operation, proceed as fol- 
lows: 

a. Clean the tape transport read/write head, 
capstan, and idlers to prevent degradation 
of magnetic tapes. 

b. Check for correct setting of line voltage 
selector switch on rear flange, and make 
sure that correct fuse is installed (para- 
graph 2. 1.5). 

c. Set primary power switch on control panel 
to ON. 



2-1 



206-9801-200A 



2.2.4 TAPE THREADING 

To thread the tape on the transport, proceed as fol- 
lows: 

a. Raise the latch of the quick-release hub and 
place the tape file reel to be used on the 
supply hub (Figure 2-1) with the write- enable 
ring side next to the transport deck. 

b. Hold the reel flush against the hub flange 
and secure it by pressing the hub latch down. 

c. Thread the tape along the path as shown by 
the threading diagram (Figure 2-1). 

d. Holding the end of the tape with a finger, 
wrap a few turns counterclockwise around 
the takeup hub 0 

2.2.5 TAPE LOADING 

Pressing the LOAD pushbutton energizes the reel 
servos and initiates a load sequence. Tape advances 
to the load point marker and stops. 

If for some reason the load point marker is already 
past the sensor as, for example, in restoring power 
after a shutdown, tape will continue to move. Under 
these conditions, press REWIND and tape will rewind 
to load point. 



Once pressed, the LOAD switch is illuminated and 
is inactive until power has been turned off or tape is 
removed from the machine. 

2.2.6 PLACING TAPE UNIT ON LINE 

After the tape is properly threaded and has been 
loaded and brought to the load point, press the ON 
LINE pushbutton and check that the ON LINE indicator 
illuminates. (LOAD and REWIND pushbuttons are 
disabled when the tapeunitison line.) On-line status 
enables the tape unit to be remotely selected and to 
perform all normal operations under remote control. 

2.2. 7 TAPE UNLOADING 1 AND REWIND 

Provision is made in the 9000-series transports for 
rewinding a tape to the load point under remote con- 
trol. However, this operation may also be performed 
manually. Proceed as follows. 



a. If the ON LINE indicator is illuminated, 
press the ON LINE pushbutton. Check that 
the indicator extinguishes when pressure is 
removed. 

b. Press the REWIND pushbutton. The tape 
will now rewind to the load point marker. 




Figure 2-1. Tip* threading Dimgrmm 

2-2 



206-9801-300 



c. After the tape has been positioned at the load 
point under remote or local control, press 
the REWIND pushbutton to rewind the tape 
past the load point to the physical beginning 
of the tape. 

NOTE 

The rewind sequence cannot be stopped 
until the tape has rewound either to 
the load point or until tension is lost 
at the physical beginning of the tape. 



and to minimize operator error which could destroy 
recorded data. In the event of power failure during 
tape unit operation, manually wind the tape forward 
several feet before restoring power. When power 
has been restored, press the LOAD pushbutton, then 
the REWIND pushbutton. This will rewind the tape 
to the load point. If desired, the tape can then be 
advanced to the data block nearest the point at which 
the power failure occurred, by initiating the appro- 
priate control commands o 



2.2.8 POWER SHUTDOWN 

A tape transport should not be turned off when tape 
is loaded and is past the load point marker. Kennedy 
9000- series transports are designed to prevent physi- 
cal damage to the tape in the event of power failure, 



Although it is possible to develop procedures which 
would allow power shutdown; between files or record 
blocks on a tape, this is not recommended. Where 
data files are short, it is preferable to use smaller 
tape reels. 



2-3 



SECTION III 
THEORY OF OPERATION 



306-9801-100 



SECTION III 
THEORY OF OPERATION 



3.1 INTRODUCTION 

This section describes the tape transport on a func- 
tional basis. The description applies to the standard 
model using the 800 cpi NRZ1 data electronics and 
covers all tape speeds. Models using the 1600 cpi 
phase encoded electronics, the dual density 800/1600 
cpi electronics, or the seven- track NRZ1 electronics 
include a different set of data electronics, and these 
are described in special supplements that accompany 
the standard manual. 

Each circuit card schematic is preceded by a detailed 
circuit description that explains the operation of the 
card on the component level. The description offered 
in this section is more in the nature of a block dia- 
gram description, and divides the transport into three 
main functional subsections — control logic, servo 
system, and data electronics. 

3.2 CONTROL LOGIC 

3.2.1 INTRODUCTION 

The control logic section of the tape transport gener- 
ates the appropriate internal tape motion commands 
in response to input commands from the transport 
interface, the main pushbutton panel, and from the 
test panel pushbuttons. The control electronics re- 
ceive these commands and generate transport motion 
if all internal interlocks are satisfied. In addition, 
the control electronics return the transport status 
outputs to the interface and illuminate the respective 
indicators on the main panel and on the test panel. 

Five plug-in circuit cards constitute the control 
section logic: Control Terminator Type 3841, Push- 
button Control Type 3843, Ramp Generator Type 
3645, and Sensor Amplifier/ Driver Type 3844. The 
modules are housed in the card cage assembly and 
plug into the master board. Figure 3-1 is a simpli- 
fied block diagram of the control logic, showing the 
signal flow between the control modules,, As can be 
seen, the input signals from the interface are. sup- 
plied, after being terminated on the Control Termi- 
nator module, to the Control Interface module, where 
these signals are acknowledged if certain interlocks 
are satisfied. The motion commands are then sup- 
plied to the Pushbutton Control module. This card 
also includes the interlocks for the main panel push- 
buttons and for the test panel pushbuttons. If the 



interlocks are satisfied, the Pushbutton Control mod- 
ule encodes all tape motion commands onto three 
command lines: RUN NORMAL (RNN1), RUN FAST 
(RNFST1), and REVERSE SELECT (RVS1). The 
three command lines are then supplied to the Ramp 
Generator module which produces accurate analog 
voltage output. The output of the Ramp Generator 
is then supplied to the Capstan Servo Amplifier mod- 
ule in the servo system, described below. The volt- 
age output of the Ramp Generator in conjunction with 
the feedback from the capstan tachometer is used to 
energize the capstan motor and to advance the tape 
in the desired speed and direction. The Ramp Gen- 
erator provides linear ramp-ups to speed and linear 
ramp-downs to standstill in order to minimize the 
stress on the tape and maintain accurate speeds. 

The Sensor Amplifier/ Driver module receives the 
inputs from the file protect switch, the load point 
sensor, end of tape sensor, and broken tape sensor. 
These signals are amplified and supplied to the other 
modules in the control section where they provide 
the inputs to the interlocks. The Sensor Amplifier/ 
Driver module also contains the drivers for the front 
panel indicators, the driver for the file protect sole- 
noid, and the write and erase head drivers. 

3.2.2 CONTROL LOGIC OPERATION DURING A 
WRITE SEQUENCE 

A write operation will be used as an example to dem- 
onstrate the interaction of the different components 
of the control logic. The whole operation is described, 
showing the flow of commands and the required con- 
trol interlocks. 

The main pushbutton panel is used to prepare the 
transport for operation. After the power is turned 
on and the tape is properly threaded, the front panel 
LOAD pushbutton is pressed. This sets the LOAD 
flip-flop on the Pushbutton Control modules, gener- 
ating a RUN NORMAL RNNltrue to the Ramp Gener- 
ator card. The Ramp Generator outputs a linear 
ramp voltage to the Capstan Servo Amplifier card, 
initiating forward tape motion at normal running 
speed. The Ramp Generator also supplies TAPE 
RUNNING status true through the Interface Control 
card to the transport interface. When the load point 
reflector marker is detected by the respective photo 
cell, the signal is amplified by the Sensor Amplifier/ 
Driver card and is supplied as LOAD POINT DETECT 



i 



3-1 



306-9801-200 



[on l ine 1 j load \ 
r~i rp 



REWIND 



SFC, SRC 
OR — 
FWD, RUN 



TO/ FROM 
TAPE 

CONTROL""] 
UNIT 



CONTROL 
INTERFACE 

SLT, ONL 

♦ 



RAMP GENERATOR 
PLUG-IN MODULE 



n 



MOTION 

CONTROL 

LOGIC 



OFFC r 
RWC - 



SWS 



RVS 



I t—: — r — 

H ±j_± 



RUNN 



-►RUNN 

(TO DATA 
SECTION) 



WRITE 

SELECT 

LOGIC 



DRIVE 
CONTROL 
LOGIC . 



NORMAL 



FAST 



REVERSE 



RAMP 

GENERATOR 
LOGIC & 
AMPLIFIERS 



RAMP 

OUTPUT 

(TO CAPSTAN 

SERVO 



►BUSY 
-ON LINE 
-REWINDING 

• TEST MODE 

• WRITE TEST 

■ STOP 

■ FWD RUN 
' REV RUN 

• FAST FWD 
- FAST REV 



TAPE , 
RUNNING 



WRITE 



SELECT 



SLT, 
ONL 



ONL 
RDY 
WEN 
FPT 
RNG 
RWD 
LDP 
EOT 



BUSY 



WRITE 

CONTROL 

LOGIC 



ON 



LINE 



I PU! 

[coi 



PUSHBUT 
CONTROL 



STATUS 
LOGIC & 
OUTPUT 
DRIVERS 



FILE PROTECT 



TON 
BOARD 



TAPE RUNNING 
REWINDING 



SENSOR AMPL/DRl VER 



FILE 
PROTECT 
SWITCH 



i 




FILE 
PROTECT 
CIRCUIT 



FPT 



PHOTO 
SENSOR 
AMPLIFIERS 



LDP 



EOT 



FROM 
TEST 
PANEL 

PUSHBUTTONS 



WRITE 
READY 
•(TO DATA 
SECTION) 



,1 



ERASE 
CIRCUIT 



BKN 



INDICATOR 
DRIVERS 



ERASE 
HEAD 

— K> 



WRITE 
STATUS 



SELECT 



ADDRESS SWITCH 
| (OPTIONAL) j 



WRITE 
ENABLE 



READ 
STATUS 



PHOTO SENSORS 



Figure 3-1. Control Logic Block Diagram 



3-2 



306-9801-300 



(LP) true to the Pushbutton Control module. LOAD 
POINT true sets the ON TAPE flip-flop to the true 
condition which terminates the synchronous forward 
motion by setting RUN NORMAL RNN1 false. The 
tape is stopped at load point and is properly loaded. 
Pressing the front panel ON LINE pushbutton now 
places the transport on line, preparing the transport 
to respond to interface commands once it is selected 
by the interface. When the transport is selected 
(input line SELECT going true) the transport can ac- 
cept commands from the interface and return the 
transport status outputs back to the interface. At 
this time the transport status lines would be in the 
states shown in Table 3-1. 

In addition to the status lines, the front panel ON, 
LINE and SELECT indicators are illuminated, as is 
the WRITE ENABLE indicator if the supply reel con- 
tains a write enable ring. 

If the write operation is to be initiated, the interface 
now supplies SET WRITE STATUS level true and 
then a SYNCHRONOUS FORWARD COMMAND. The 
SET WRITE STATUS (SWS) level is sampled on the 
leading edge of the SYNCHRONOUS FORWARD COM- 
MAND. If the level is true this sets a flip-flop on 
the Interface Control module and generates WRITE 
SELECT WSEL true. WRITE SELECT is supplied 
to the Pushbutton Control module where it generates 
WRITE READY true provided that FILE PROTECT 
is false (supplied from the Sensor Amplifier/Driver 
module), BUSY is false (this signal is generated on 
the Pushbutton Control and is true whenever the trans- 
port is searching for load point and is rewinding), 
and no reverse command is given. These interlocks 
ensure that the transport writes data on tape only 
when the tape is properly loaded, the reel has a write 
enable ring, and the tape is moving forward at nor- 
mal running speed. WRITE READY true is supplied 
to the Sensor Amplifier/ Driver module where it turns 
on write and erase head current drivers and illumi- 
nates the WRITE indicator on the front panel. WRITE 
READY and SELECT 1 (combining ON LINE true and 
SELECT true) are also supplied to the data electron- 
ics card cage where they enable the write and read 
amplifier stages. 

When the tape is properly loaded and not rewinding 
and WRITE READY is false, a read operation is 
selected and the Sensor Amplifier/Driver module 
illuminates the front panel READ indicator. 

If WRITE READY does go true the interface supplies 
the properly formatted data to be written on tape. 
The write operation can be interrupted in case of 
broken tape; when the BROKEN TAPE signal is sup- 
plied from the Sensor Amplifier/ Driver module, all 



servos are disabled immediately. Note that an END 
OF TAPE indication does not terminate a write oper- 
ation, but leaves it up to the interface to do so. When 
the write operation is terminated by the interface, 
the tape is rewound to load point when the interface 
issues a REWIND COMMAND. Note that the tape 
cannot be rewound past the load point by a command 
from the interface. In order to rewind the tape off 
the takeup reel the transport must be taken off line, 
either through an interface command or by pressing 
the front panel ON LINE pushbutton again. Once the 
transport is off line the front panel REWIND push- 
button can be activated to rewind the tape completely 
off the takeup reel. 

3.2.3 TEST PANEL (optional) 

The test panel provides a means of exercising, test- 
ing, and adjusting the tape transport while it is off 
line, eliminating the need for a separate test fixture 
or for the use of valuable computer time. The test 
panel can initiate forward and reverse tape motions 
at either normal or high tape speeds. It can also 
initiate a write test, generating a crystal controlled 
all-1 test pattern on tape. The test panel also pro- 
vides indicators for load point, end of tape, and data 
available. An additional indicator monitors excessive 
skew, and is used in the aligning of the read/ write 
head when using an 800 cpi skewmaster tape. When 
the head is properly aligned and the data is written 
on tape properly the SKEW indicator is extinguished. 

The controls and interlocks for the test panel are 
located on the Pushbutton Control card. The skew 
detect network is located on the Delay Timing module 
in the read logic section of the transport. The test 
panel becomes operational only when the transport 
is OFF LINE, with the test panel STOP pushbutton 
depressed. If these conditions are satisfied the test 
panel pushbuttons are enabled when the TEST MODE 
pushbutton is pressed. 

3.2. 4 CONTROL LOGIC ADJUSTMENTS 

The Kennedy tape transport requires very few ad- 
justments. These are preset in the factory and 
should not be changed unless there is a very strong 
reason to believe that they are required. The fol- 
lowing adjustments are made on the control logic 
modules: 

Adjustment Location 

Normal running speed Ramp Generator 
Ramp-up time Ramp Generator 

Ramp- down time Ramp Generator 

End of Tape/Beginning of 

Tape sensor adjustment Sensor/ Amplifier Driver 



3-3 



306-9801-400 



STATUS LINE 


STATE 


POINT OF ORIGIN 


ON LINE 


true 


Supplied from the load point flip-flop on the Pushbutton Control mod- 
ule, routed through the Interface Control module. 


TRANSPORT READY 


true 


This signal, generated on the Interface Control module, combines 
BUSY false (meaning the transport is loaded and not rewinding or 
searching for load point) and SELECT 1 true (meaning the transport 
is ON LINE and SELECT is true). 


TAPE RUNNING 


false 


This signal goes true on the Ramp Generator when tape motion is 
initiated. 


REWINDING 


false 


At this time the Rewind flip-flop on the Pushbutton Control module is 
in the cleared state. 


FILE PROTECT 




This signal is true if the reel of tape mounted on the supply hub does 
not contain a write enable ring. It is false if the reel does contain 
the ring and is available for writing. The signal originates on the 
Sensor Amplifier/ Driver module. 


LOAD POINT 


true 


Since the tape is at load point the Sensor Amplifier/ Driver supplies 
this signal true. When LOAD POINT is true the transport does not 
acknowledge a REWIND command or a SYNCHRONOUS REVERSE 
COMMAND from the interface, but must be taken off line and re- 
wound off tape by using the front panel pushbutton. 


WRITE ENABLE 




This signal is equivalent to the inverse of the FILE PROTECT signal 
and is true whenever the other is false; e.g. , whenever the supply 
reel contains a write enable ring. The signal originates on the 
Interface Control module. 


END OF TAPE 


false 


This signal goes true only when the end of tape reflective marker is 
detected by the respective photosensor. The signal is supplied to the 
Sensor Amplifier/ Driver module. 



Table 3-1. Transport Status 



The adjustment procedures are outlined in the main- 
tenance section of the manual and in the circuit de- 
scriptions of the individual schematics. 

3.3 SERVO SYSTEM 

3,3.1 INTRODUCTION 

The transport servo system consists of the electron- 
ics and electromechanical components that are re- 
quired to advance the tape past the magnetic head at 
accurately controlled speeds while maintaining con- 
stant tape tension. The servo system includes two 
subsections — the capstan servo system, whose func- 
tion is to drive the tape at accurately controlled 
speed, and the reel servo system that maintains 



constant tape tension. High performance servos are 
required to drive the reel motors and the capstan 
drive motor. Considerable power is required, re- 
sulting in substantial heat dissipation. This requires 
the use of heatsinks which are mounted for optimum 
cooling. All servo components are modular in nature 
and may be replaced with minimum effort. 

3.3.2 REEL SERVOS 

Two identical reel servos are employed for the supply 
and the takeup reels. A block diagram is shown in 
Figure 3-2. Each reel servo includes a spring loaded 
buffer arm, a magnetic position sensor coupled to 
the buffer arm shaft, a servo amplifier, located on 
the Servo Preamplifier Type 4306 module, power 



306-9801-500 



transistors located on the chassis heatsink, and a 
high power dc motor. The dc motors operate from 
±24 volt supplies capable of providing up to 30 am- 
peres peak output current. 

The tape tension is maintained by the interaction of 
the spring loaded buffer arms, the capstan, and the 
respective reel motors. The magnetic position sen- 
sors, called magpots, produce a corrective voltage 
whenever the buffer arms swing away from the center 
of their arcs. Each magpot consists of an oscillator 
circuit, a stationary transformer with a rotating flux 
linkage, and a discriminator circuit. When the re- 
spective buffer arm is in the center of its arc the 
rotating flux linkage coupled to the buffer arm shaft 
is adjusted so that the oscillator induces equal volt- 
ages into the two stationary secondary coils of the 
transformer. When equal voltage is induced to both 
coils the voltage of each cancels out and the total 
output of the position sensor is 0 volt. When the 
buffer arm swings away from the center of its arc 
the rotating flux linkage induces more voltage into 
one of the secondary coils than the other, generating 
either positive or negative corrective voltage to the 
amplifier circuit of the respective reel, located on 
the Servo Preamplifier Type 4306 module. The 
magpot corrective voltage is then summed with the 
modified output of the capstan tachometer to produce 
the energizing output for the reel motors. The effect 
of the modified tachometer output is to speed up the 
response of the reel motors to the capstan motion, 
to compensate for the lag in the magpot output to tape 
motion. 

The relative effect of the modified tachometer output 
on the reel motor response is adjusted by a poten- 
tiometer located on the Servo Preamplifier module. 
The adjustment minimizes the buffer arm travel 
during the ramp-ups to normal running speed by 
optimizing the interaction of the magpot corrective 
voltage and the capstan tachometer voltage. Reducing 
the buffer arm travel prevents the arms from bot- 
toming and ensures accurate ramp speeds. 



BUFFER 

ARM SPRING 
MAGPOT 
P0S] 




REEL 
MOTOR 



PREAMPL P0WER 
AMPL 



Figure 3-3. Reel Servo System 

motor the capstan servo system includes a dc tachom- 
eter, coupled to the capstan motor shaft, and the 
capstan amplifier, located on the Servo Preamplifier 
Type 4306 module. The linear analog ramp voltage 
produced by the Ramp Generator card (in the control 
logic section) is supplied to the Servo Preamplifier 
module where it is compared with the feedback sup- 
plied from the capstan tachometer. Any resulting 
difference is amplified and is supplied to the capstan 
power transistors, located on the chassis heatsink. 
The output of the power transistors energizes the 
capstan motor, advancing tape at accurately con- 
trolled speeds. 

3.3.4 SERVO SYSTEM ADJUSTMENTS 



The summed magpot and modified tachometer volt- 
ages are amplified on the Servo Preamplifier module. 
The amplified output is then supplied to power tran- 
sistors located on the chassis heatsink whose output 
energizes the reel motor. The reel motor then pro- 
duces the proper torque to return the buffer arm to 
the center of its arc, where the magpot position 
sensor output is again reduced to zero. 

3.3.3 CAPSTAN SERVO 

The single capstan drive motor is part of a high per- 
formance velocity servo system. In addition to the 



The following adjustments are preset in the factory 
and should not be changed unless there is a strong 
reason to believe that they are required. The ad- 
justment procedures are outlined in the maintenance 
section of the manual and in the circuit descriptions 
of the particular schematics. 



Adjustment 
Capstan servo offset 
(to prevent capstan creep) 
Buffer arm position 
Buffer arm travel 



Location 
Type 4306 Servo 
Preamplifier 
Type 4210 Magpot 
Type 4306 Servo 
Preamplifier 



3-5 



306-9801-600 



3.4 DATA SECTION 

3.4.1 INTRODUCTION 

The data section includes read and write amplifiers 
and interface cards providing output drivers and 
timing controls. Block diagrams are shown in Fig- 
ures 3-3 and 3-4. 



The data section consists of eight circuit cards that 
plug into the master board. These include a Timing 
Delay module, a Read Amplifier/ Clipping Control 
card, a pair of Quad Read Amplifier modules, a Four 
Channel Write Amplifier card, a Five Channel Write 
Amplifier card, and a Data Terminator card. 



3.4.2 WRITE ELECTRONICS 

A write amplifier channel is provided for each tape 
channel. Four such channels and the circuitry com- 
mon to all write amplifiers are contained on Write 
Amplifier Type 3848, and the five remaining write 
amplifier stages are located on Write Amplifier Type 
3849. These cards plug into the master board, from 
which the necessary head connections are made. Two 
of the channels on Write Amplifier Type 3848 are 
not used in seven-track operation. 



Each write amplifier channel consists of an input 
buffer, a digitally adjustable deskewing circuit, a 
clocked flip-flop, and a head driver. The skew char- 
acteristics of each read/write head are tested at the 
factory and the write amplifier switches are set to 
compensate for the skew, using channel P as the 
fixed reference channel. Normally the write deskew 
switch settings should never be changed. When a 
new head is installed the factory furnishes a tag dis- 
playing the new deskew switch settings required to 
compensate for the characteristics of the new head. 



The write electronics section also includes the write 
data strobe buffer which clocks the write amplifier 
flip-flops, and a write amplifier reset circuit to clear 
all write amplifier flip-flops. The write amplifier 
reset is used to write the longitudinal redundancy 
check character. During a write test mode, initiated 
by the test panel with the recorder off line, the write 
electronics generates an all-1 test pattern on tape 
derived from a crystal controlled reference frequency 
Fj^, supplied from the Delay Timing module in the 
read electronics. The test pattern can be used to 
test the write deskewing, as well as the other func- 
tions of the data electronics. 



3.4.3 READ ELECTRONICS 

The function of the read electronics is to convert 
the data recovered from the tape into digitized wave 
forms, deskew it and supply it to the interface with 
its respective read clock. The read electronics also 
detect the interrecord gap and excessive skew. The 
components comprising the read section include the 
magnetic read head, the Read Preamplifier module, 
Delay Timing module, Read Amplifier/ Clipping Con- 
trol module, and a pair of Quad Read Amplifier mod- 
ules. Figure 3-4 is a functional block diagram of 
the read section, showing the general signal flow 
between the cards. A detailed circuit description of 
each circuit card accompanies the schematic of the 
card. 

The low level analog signals, on the order of tens of 
millivolts, are supplied from the read head to the 
Read Preamplifier module where they are linearly 
amplified to an output voltage (adjusted by a poten- 
tiometer for each read preamplifier stage) of ap- 
proximately 9 volts peak to peak in 800 cpi NRZ1 
read operation. The amplified analog signals are 
then supplied to the nine read amplifier stages, eight 
of which are located on the Quad Read Amplifier 
modules while that of channel P is located on the 
Read Amplifier/Clipping Control module. Each Read 
Amplifier stage includes a peak detection circuit, a 
filtering network, an output data register, and a pulse 
generator. 

The analog signals from the preamplifier are detected 
only when they exceed the positive or negative clip- 
ping levels provided by the Read Amplifier/ Clipping 
Control module. They are then rectified and peak 
detected, with the resulting digitized waveforms 
cbntaining negative-going transitions corresponding 
to the peaks of the input analog signals, e.g., one 
bits in the NRZ1 code. The digitized waveforms are 
supplied to a filtering network which eliminates spur- 
ious pulses between transitions. The data of each 
channel is then stored in a register and generates a 
PULSE OUT to the Delay Timing module. Following 
the skew delay the Delay Timing card supplies a 
DATA TRANSFER output to clock the data registers 
of all nine channels simultaneously, supplying the 
data character to the interface. 

When an error is detected, and the transport is 
commanded by the interface to reread a block, the 
read amplifier/clipping levels are switched automat- 
ically by the Read Amplifier/Clipping Control module 
to maximize the recoverability of marginally re- 
corded data. The clipping levels are kept normal on 
the first reread; on the second reread are switched 
to lower levels in order to recover possible partial 



3-6 



306-9801-700 



WRITE 
CONTROL 
(FROM READ 
BUFFER) 



r _r 

un<; 1 



FROM 
TAPE 
CONTROL 
UNIT 



WDS 
WARS 



WDP 
WDO 
WD1 
WD2 



WRITE AMPLIFIER/CONTROL 
PLUG-IN MODULE 



WRITE 
LOGIC 



LRCC 
CONTROL 



TIMING 

(PARITY 

CHANNEL) 



WRITE AMPLIFIERS 
(PARITY, 0, 1, 2) 



GATING 



WRITE LRCC 



5-CHANNEL WRITE AMPLIFIER 
PLUG- IN MODULE 



WD3 
WD4 
WD5 
WD6 
WD7 



WRITE 

AMPLIFIERS 
(3 THRU 7) 



GATING 



TT 



WRITE LRCC 



WRITE 
GATING 

(ALL CHANNELS) 

WRITE LRCC 
(ALL CHANNELS) 



WRITE 
HEAD 



Figure 3-3. Write Data Section 



dropouts. If the block is still in error and a third 
reread is commanded the clipping levels are switched 
to higher levels to eliminate possible baseline spikes. 
During read- after- write operations higher clipping 
levels are used. 

The Delay Timing module contains circuitry common 
to all nine channels. It includes a crystal controlled 
oscillator and divider network which produces the 
synchronous clocks used in the skew delay network, 
the data strobe generation, the gap detect network, 
and are also supplied to the Write Amplifier Type 
3848 module to generate the write test pattern. The 
crystal controlled clocks ensure high precision in 
the performance of all data synchronized functions. 



3. 4.4 DATA SECTION ADJUSTMENTS 

These adjustments are preset at the factory and 
should not be changed unless there is a strong reason 
to believe that a readjustment is required. The ad- 
justment procedures are outlined in the maintenance 
section of the manuals and in the circuit descriptions 
of the individual schematics. 



Adjustment 
Read preamplifier amplitude 



Skew alignment 



Location 
Type 3631 
Read Preamplifier 

Read/write head, 
write amplifiers 



3-7 



306-9801-800 



TO TEST PANEL 
i i I i 



</i — i 



DELAY TIMING 



nil 



TO 
WRITE H 
LOGIC 



CRYSTAL 
OSCILLATOR 
& DIVIDING 
NETWORK 



r BSY 



FROM 
CONTR i 
LOGIC 



SLT1 



LP 



RNN 



READ 

SELECT 

DELAY 



SLT2 



CHANNEL 



0 <g- 

1 <a- 

2 
3 



p O- 



READ 
PRE- 
AMPLIFIER 



CHAN 0 



CHAN 1 



CHAN 2 



CHAN 3 



CHAN 4 



CHAN ,5, 



CHAN 6 



CHAN 7 



READ GAP 

DETECT 

NETWORK 



SKEW 

DETECt 

NETWORK 



RGAP -i 



READ I 
CLOCK 

GENERATION 



PULSE 
OUT (4- 7) 

. SLT2 



SLT2 



PULSE 
OUT (P) 

SLT2 



CHAN P 



0 



PULSE 
,0UT (0-2) 



QUAD 
READ 

AMPLIFIER 
NO. 1 




QUAD 
READ 

AMPLIFIER 
NO. 2 



CHANNEL P 
AMPLIFIER 
STAGE 



READ 

AMPLIFIER 

CLIPPING 

CONTROL 



RDS 



DATA I 
TRANSFER 



/ 



READ CHAN 0 



READ CHAN 1 



READ CHAN 2 



READ CHAN 3 



READ CHAN 5 



READ CHAN 6 



READ CHAN 7 



READ 



CHAN P, 



TO 

"INTERFACE 



AUTO 

CLIPPING 

LEVEL 

CONTROL 



RNN 



RVST 



BSY 



WRDY 



AUTO 
DISABLE" 



FROM 
h CONTROL 
SECTION 

FROM 

INTERFACE 



Figure 3-4. Read Data Section 



3^8 



SECTION IV 
MAINTENANCE INSTRUCTIONS 



406-9801-100 



SECTION IV 
MAINTENANCE INSTRUCTIONS 



4.1 GENERAL 

Kennedy Company tape transports are highly reliable 
precision instruments which will provide years of 
trouble-free performance when properly maintained. 
A planned program of routine inspection and main- 
tenance is essential for optimum performance and 
reliability. The units require very few adjustments 
and these should not be performed unless there is 
strong reason to believe they are required. All elec- 
trical adjustments are preset at the factory and should 
not require readjustment except after long periods of 
time* 

4.2 PREVENTIVE MAINTENANCE 

To assure continuing trouble-free operation a pre- 
ventive maintenance schedule should be kept. The 
items involved are few and simple but very important 
to proper tape transport operation. The frequency of 
performance will vary somewhat with the environment 
and degree of use of the transport so a rigid schedule 
applying to all machines is difficult to define. The 
recommended periods below apply to units in constant 
operation in ordinary environments. They should be 
modified if experience shows other periods are more 
suitable. 

4.2.1 DAILY CHECK 

Visually check the machine for cleanliness and ob- 
vious misadjustment. If items in the tape path show 
evidence of dirt or oxide accumulation, clean thor- 
oughly. 

4.2.2 CLEANING 

AH items in the tape path must be kept scrupulously 
clean. Thi sis particularly true of the head and guides . 
The inside of the dust cover must not be allowed to 
accumulate dirt since transfer to the tape will cause 
malfunction. 

In cleaning it is important to be thorough yet gentle 
and to avoid certain dangerous practices. 

4.2.2.1 Head Cleaning 

Oxide or dirt accumulations on the head surfaces are 
removed using a mile organic solvent and a swab. 
Q tips are convenient for this use but must be used 



with caution. Be sure the wooden portion does not 
contact head surfaces. Figure 4-1 shows access to 
the head by lifting the face shield. 

An ideal solvent is 1. 1. 1 triehlorothane contained in 
Kennedy K21 maintenance kit. However, others such 
as isopropyl alcohol will do. 

DO NOT USE - acetone or lacquer thinner 

- aerosol spray cans 

- rubbing alcohol 

Do not use an excess of any solvent, and be extremely 
careful not to allow solvent to penetrate ball bearings 
of tension rollers, capstan motor, etc. , since it will 
destroy their lubrication. 

4.2.2.2 Tape Path Cleaning 

Other items in the tape path should be cleaned at the 
same time as the magnetic head. These include: 




BEAD COm REMOVED F01 CLillTV 



Figure 4-1. Opmnmg of Hmmd ShhU 



4-1 



406-9801-200 



Tension rollers 
Tape guides 
Capstan 

Tape cleaner surface 

The techniques are similar to those outlined above 
for head cleaning. 

4.2.2.3 Other Cleaning 

For removing accumulations of dust inside the dust 
cover or elsewhere in the unit, use of a vacuum cleaner 
is recommended. Compressed air may be used if 
caution is exercised to avoid blowing dirt into bear- 
ings. Antistatic cleaners are available for cleaning 
the plexiglass dust cover window. 

4.2.3 VISUAL CHECK 

Check visually to determine if all appears to be right 
with the machine. It is helpful to run tape forward 
and reverse observing smooth tape motion, proper 
tension arm operation, etc. It is well to remember 
that if things look right they probably are right, and 
the converse. 

4.3 ROUTINE ADJUSTMENT 

There are no routine adjustments. Need for adjust- 
ment will be manifest if malfunction occurs. Under 
normal circumstances adjustment will be more likely 
to cause trouble than prevent it. 

4.4 LUBRICATION 

No bearing lubrication is required. All bearings are 
lubricated for life and introduction of oil may destroy 
their lubrication. 

4.5 WEAR 

Magnetic tape is an abrasive and in time wear will be 
noted on items over which the oxide surface slides. 

4.5.1 HEAD WEAR 

Head wear is generally signaled by an increase in 
error rate. Confirmation is a sizable increase in 
output voltage, measured at the preamplifier, from 
the read head. When the head becomes worn it must 
be replaced. Head replacement procedure is outlined 
in paragraph 4. 8. 1. 

Worn heads usually can be resurfaced at least bnce 
if returned to the factory. This is more economical 
than replacement with a new head. Consult Section 
V for details of head return. 



4.5.2 GUIDE WEAR 

Guides wear principally at the point of contact with 
the>front guide surface. Although guides are hard 
anodized with a coating equivalent to sapphire, in time 
grooves will appear. Since guides are symmetrical 
it is only necessary to loosen the guide mounting 
screw, rotate the guide, and tighten to present an 
unworn surface to the tape. 

4.5*3 REEL HUBS 

Quick release hubs are adjustable to assure a firm 
clamping action. They are designed to make it im- 
possible to mount a reel in wrong or cocked posi- 
tion. If the locking action should become weak, the 
hub may be adjusted by tightening the nut at the rear 
end of the hub shaft. O ring clamps used in the hub 
may tend to hang up after long periods of use. This 
can be corrected as follows: 

a. Remove O ring from hub. 

b. Clean thoroughly with mild solvent. 

ci Lubricate ring with silicone grease. Wipe 
off as thoroughly as possible, leaving a 
light lubricating film. 

d. Snap O ring back in place. 
4.6 PERIODIC INSPECTION 

At regular intervals, approximately every two 
months, it is advisable to make a more thorough check 
of machine operating parameters. This will Insure 
that no progressive degradation will go unnoticed. Of 
great assistance in making these checks is the test 
panel (standard equipment on Model 9000, optional 
with Models 9700 and 9800) which allows control of 
tape motion off line for test purposes and provides 
certain useful indicators and test signals as well. 
The test panel connector plugs into a connector on 
the control electronics. It does not require that inter- 
face cables be disconnected. Using the test panel or 
other appropriate means, the following should be 
checked periodically. 

Tape speed 
Ramp times 
Ramp level 
Skew 

Photosensor adjustment 
Servo zero adjustment 

The suggested adjustment sequence is shown in Table 
4-1. ■: 



4^2 



406-9801-300 















i 


) 




UNKNOWN MACHINE 
(PARTS ASSUMED GOOD) 






TAPE SPEED 
ADJUST 
Paragraph 4.7.2.4 




1 




< 






TAPE PATH 
MECHANICAL ALIGNMENT 
Paragraphs 7. 3-4. 7. 6 






RAMP TIME 
ADJUST 
Paragraph 4. 7. 7. 2 




1 










POWER ON 
CHECK SUPPLIES 






READ LEVEL 
ADJUST 
Paragraph 4.7.7 0 4 








.< 






REEL SERVO SETUP 
(MAG POT ADJUST) 
Paragraph 4. 7. 6 






READ SKEW 
ADJUST 
Paragraph 4.7.2.2 




< 










PHOTOSENSOR 

ADJUST 
Paragraph 4. 7. 2 






WRITE SKEW 
CHECK/ADJUST 
Paragraph 4.7.2.3 




■1 










CAPSTAN SERVO 
ZERO ADJUST 
Paragraph 4.7.7.3 

























Table 4-1 . Adjustment Sequence 

4-3 



406-9801-400 



4.7 CHECKS and ADJUSTMENTS 

4. 7. 1 TEST PANEL (optional) 

All adjustments described below are preset at the 
factory and should not be performed unless there is 
a strong reason to believe they are required. When 
the adjustments have to be performed it is recom- 
mended that the test panel be used. The test panel 
provides a flexible means of exercising the tape deck 
off-line without requiring computer time. It can 
initiate tape motion in normal and high speeds, in 
forward and reverse directions, as required for the 
particular adjustment. In addition, it includes a skew 
indicator to monitor excessive skew that should be 
used in the head alignment procedure described be- 
low, and a write test mode that automatically gener- 
ates an all-1 test, pattern on tape. The test panel 
also includes load point, end of tape, and data avail- 
able indicators. The test panel pushbuttons and indi- 
cators are described on page 1-4 of the manual. 

In order to use the test panel the transport must be 
off line and the test panel STOP pushbutton must be 
depressed. The recorder is then placed under test 
panel control by depressing the TEST MODE push-* 
button. If all interlocks are satisfied the TEST MODE 
indicator is then illuminated and the other pushbuttons 
on the test panel become active. Any tape motion 
can then be commanded by the respective pushbutton 
and can be terminated by the STOP pushbutton. 



4. 7. 2 SKEW ADJUSTMENT 



4.7.2.1 Introduction 

The skew adjustment on this model is simplified 
considerably by the use of the test panel. The SKEW 
light on the test panel indicates excessive skew when 
illuminated, while the adjacent skew test point sup- 
plies the wire- OR' d pulse outputs of all the read 
amplifier stages, displaying the entire range of bit 
scatter. When excessive skew is detected, follow 
the skew adjustment procedure outlined below. Nor- 
mally only the read skew adjustment should be made, 
since the write amplifiers are digitally deskewed in 
the factory, using the write amplifier switches to 
control the write skew delay. The switch settings 
should never have to be changed under normal use. 
When the magnetic head needs replacement, the fac- 
tory supplied head is accompanied by a tag displaying 
the new write amplifier switch positions required to 
match the new head characteristics. 



4.7.2.2 Read Skew Adjustment 

a. Mount a master skew tape on the supply 
hub. 

b. Adjust skew adjusting screw (Figure 4-2) 
in the head mounting plate until the skew 
lamp is extinguished. Alternately an oscil- 
loscope probe may be connected to the test 
panel skew test point, displaying the wire- 
OR'd read peaks. The read skew should 
then be adjusted until minimum peak scatter 
is detected. 

4.7.2.3 Write Skew Adjustment 

As mentioned above, this adjustment is made in the 
factory and normally should not be changed. Should 
a readjustment be required, follow these steps: 

a. Place the write amplifier card containing 
the channel to be adjusted on an extender. 

b. Mount a blank reel of tape on the supply 
hub, and advance to load point. 

c. Connect channel 1 of a dual channel oscillo- 
scope to test point P(C) on the read pre- 
amplifier card. 




NT 



Figure 4-2. Head Skew Adjustment 



4-4 



406-9801-500 



d. Connect scope probe channel 2 to test point 
channel 7(1) of the read preamplifier. Se- 
lect added sweep, synchronizing on channel 
1 only, positive slope trigger (Figure 4-4). 

e. Place recorder in the write test mode by 
first pressing the TEST MODE pushbutton 
on the test panel, and then the WRITE TEST 
pushbutton. The recorder will then write 
consecutive all l's pattern. 

f. Adjust the channel 7 switches on the write 
amplifier card (see Figure 4-3) until the 
channel P and channel 7 traces coincide. 

g. Repeat the above steps for the remaining 
channels , leaving the scope probe oh channel 
P as the reference channel. 

h. Recheck the read skew following the proce- 
dure outlined in the preceding paragraph. 

4.7.2.4 Tape Speed Check 

With master skew tape mounted and scope connected 
(paragraph 4. 7.2.2), check tape speed by measuring 
the time of one sine wave period, or the time be- 
tween corresponding points in the sine wave. In 
NRZ1 recording this time is equal to two bit periods. 



WRITE READ 
AMPLIFIER AMPLIFIER 
MODULES MODULES 




Figure 4-3. Write and Read Amplifier 
Channel Locations 



— H \<m SKEW t s 








^ PERIOD 






T : 




2 x 10 6 

uo-0033 T " DENSITY x TAPE SPEED (IPS) USEC 



Figure 4-4. Skew Adjustment Waveforms 



Measured time in microseconds should be 

6 

= 2 x 10 ge 

density x tape speed (ips) ^ S€ 



4.7.3 TAPE PATH CHECKS 

It is important to maintain a correct tape path at all 
times. Items influencing tape path are: tension arm 
roller guides, tape guides, and direction-reversing 
idler. All must be correctly set for satisfactory 
operation. To check tape path, proceed as follows: 

a. Observe that tape enters both reels without 
touching reel flanges. 

b. Depress the spring-loaded (inside) portion 
of the top tape guide. Tape should have a 
slight tendency to follow the guide. 

c. Operate the transport in alternate forward 
and reverse direction, moving about 1 foot 
of tape. The tape should stay centered on 
direction-reversing idler in both directions. 

d. If these cheeks indicate need for adjustment, 
the following procedure should be used. 

4. 7.4 TAPE PATH ADJUSTMENTS 

4.7.4.1 Tension Arm Roller Guide 

(Symptom: Tape touches reel flange. ) 

a. Be sure reel installed is not warped. 



406-9801-600 



b. Remove tension arm roller guide nearest 
reel. 

c. Insert a 4 inch rod of 0. 187 inch diameter 
ground stock in place of the roller guide 
shaft and thread tape over the rod. 

d. Run tape forward continuously. Hold the 
end of the rod and loosen lockscrew (A, 
Figure 4-5). This will allow the rod to be 
angularly adjusted. 

e. Adjust the position of the rod so that tape 
is guided into the center of the reel without 
touching reel flanges. Tighten lockscrew. 

f. Remove rod and replace roller guide (B). 
Do not change setting established in step e. 
Roller guide height should be set so tape is 
in center of reel. On most decks the tape 
edge should be set to 0.434 inch from the 
painted surface, a measurement that can 
easily be made with the tape height gauge 
included in the K21 maintenance kit. In re- 
corders with cast decks this measurement 
cannot be made, and tape height should 
simply be adjusted to center of reel. The 
roller height adjustment on all decks should 
be made as follows: 

(1) Pull roller guide outward so tape nearly 
touches the outside edge of the reel. 

(2) Partially tighten roller guide retaining 
screw (C) until the roller guide shaft 
cannot be moved by hand. 



(3) Using the adjustment nut and washer 
(D), (No. 10 flat washer and 10-32 nut 
should be used) , move the roller guide 
inward until the tape is at the center of 
the reel (0.434 inch on most decks). 

(4) Lock the roller guide retaining screw 
(C) ; remove adjustment nut and washer. 

4.7.4.2 Direction-Reversing Idler 

(Symptom: Tape moves back and forth on direction- 
reversing idler when run alternately forward and 
reverse. ) 

a. Loosen locknut on idler adjusting screw (see 
(Figure 4-6). 

b. Loosen setscrew in idler collar. 

c. Run tape alternately forward and reverse. 

d. Tighten locknut and idler collar. 

4. 7. 5 TAPE TENSION CHECK 

a* Turn power off and remove tape from ma- 
chine. 

b. Using a spring scale, measure return force 
of tension arm at the approximate center of 
its arc. Force should be 16 ±2 ounces (450 
±55 grams) corresponding to tape tension 
of 8 ±1 ounces (225 ±27 grams). 




4-6 



406-9801-700 



NOTE 

Spring anchor adjustment can be var- 
ied to produce small corrections. If 
a large correction is required, tension 
arm spring should be replaced. 



corrective voltage output by the magpot is 0 volt. 
When the arm swings away from the center of its arc 
the voltage put out by the magpot should be either 
positive or negative, depending on the position of the 
arm. The adjustment procedure is as follows: 

a. Turn the transport power on. 



To adjust spring tension, loosen anchor lug 

nut slightly and adjust anchor for correct b. Remove the shell from the magpot to be 

reading on spring scale. adjusted (as shown in Figure 4-7). 



4. 7. 6 TENSION ARM POSITION CHECK 

When the transport is at rest with a tape loaded, the 
tension arms should be located in the approximate 
center of their respective arcs. If the arms drift 
away from their proper position they may hit the end 
of their arcs when the tape ramps up to running speed. 
The magpot position sensors, coupled to the buffer 
arms as shown in Figure 4-7, control the position of 
the arms. When the tension arms drift away from 
their proper position the magpots should be adjusted 
as follows: 



c. Loosen the transformer linkage retaining 
screw (point A on v Figure 4-7) so linkage 
can be turned on the tension arm shaft. 

d. Connect an oscilloscope probe to the magpot 
output. A convenient point is resistor R8 
(point B on Figure 4-7). 

e. Move the tension arm to the approximate 
center of its arc and turn the linkage on the 
tension arm shaft so that the output voltage 
of the oscillator (measured at R8) is 0 volt. 



Magpot Adjustment 

The magpot should be adjusted so that when the re- 
spective tension arm is in the center of its arc the 



f. Ascertain that when tension arm is in the 
rest position (under spring pull only) the 
output voltage of the magpot is between -5 



MAWOT OUTER SHELL 



ROTATING LINKAGE 




Figure 4-7. Magpot Position Sensor 



406-9801-800 



and -6 volts. When the buffer arm is at the 
other extreme of its arc the magpot output 
voltage should be between +5 and +6 volts. 
Though the total output voltage swing of the 
magpot is not critical, it should be between 
10 and 12 volts. This amplitude is deter- 
mined by the distance of the rotating linkage 
from the stationary transformer section and 
is permanently fixed in the factory by using 
plastic spacers. The amplitude swing can 
be readjusted by moving the rotating flux 
linkage toward the stationary transformer 
section to increase the amplitude or away 
from the stationary section to decrease the 
amplitude. 

g. After adjusting the rotating linkage position 
lock the linkage retaining screw and replace 
the magpot outer shell. It is recommended 
that the retaining screw be secured with 
Loctite. 



4. 7.7 ELECTRICAL ADJUSTMENTS 
4.7.7.1 Introduction 

The electrical adjustments outlined below are also 
conveniently located on the circuit descriptions of 
the individual circuit boards on which the adjustments 
are performed. 

4. 7. 7.2 Control Section Adjustments 
Speed Adjustment 

The tape speed adjustment is performed on the Ramp 
Generator card as described in paragraph 4.4.2.4. 

Ramp Time Adjustments 

The ramp time adjustments are also performed on 
the Ramp Generator module. The stop and start 
ramps should be adjusted according to the formula 

0.375 millisecond 

ramp time = — ; — 

transport speed 

Consequently in transports with synchronous running 
speeds of 25 inches per second the start and stop 
ramps should each be 

°*5J 5 = 15 milliseconds 
25 

and the ramp time varies inversely with speed. The 
adjustment procedure is as follows: 



a. Arrange the input signals to the tape trans- 
port to start and stop the transport repeat- 
edly. The rate must be such as to allow 
full ramp time. 

b. Adjust start ramp potentiometer R3 on the 
Ramp Generator card for the required time, 
observing the ramp output at test point A of 
the Ramp Generator. The ramp start time 
is measured from 0 volt to the maximum 
output voltage. 

c. Adjust the stop ranip potentiometer R4 for 
the required time. The stop ramp time is 
measured from maiximum volts to 0 volt. 

Beginning of Tape, End of Tape Sensor Adjustment 

This adjustment is performed on the Sensor Ampli- 
fier/Driver Type 3844 module. The adjustment be- 
comes necessary if the Beginning of Tape or End of- 
Tape markers are not detected by their respective 
sensors. To adjust the sensors, turn potentiometer 
R16 on the Sensor Amplifier/ Driver card until the 
voltage between test points E and F on that card 
measures 0 volt. 

4.7.7.3 Servo System Adjustments 
Capstan Creep Adjustment 

This adjustment is performed on the Servo Pream- 
plifier Type 4306 when capstan creep is observed 
during standstill. To adjust, follow these steps: 

a. Connect oscilloscope to observe voltage at 
the amplifier output. A convenient point is 
output pin X. 

b. With transport on line and loaded but in a 
stopped condition, adjust R56 so that a 
straight-line trace is produced. Use 0.5v/ 
cm scale on oscilloscope. 

c. Observe that capstan does not rotate. 
Buffer Arm Travel Adjustment 

This adjustment is performed on the Servo Pream- 
plifier Type 4306 module, and is required when the 
buffer arms exhibit excessive travel during ramp- 
ups to running speed. In that case potentiometer 
R57 or R58 on the Servo Preamplifier Type 4306 
should be adjusted to minimize buffer arm travel 
during the ramps , preventing the arm from bottom- 
ing and overshooting. To adjust, follow these steps: 



4-8 



406-9801-900 



a. Load a full reel of tape on the supply reel. 

b. With the transport off line, press the test 
panel TEST MODE pushbutton, placing the 
transport under the test panel control. 

c. Alternately press the FORWARD RUN and 
then the REVERSE RUN pushbuttons on the 
test panel, initiating synchronous forward 
and reverse tape motions. 

d. Adjust potentiometer R57 until the travel of 
the SUPPLY buffer arm is at a minimum 
during ramp-ups and ramp-downs. 

e. Repeat the above procedure for theTAKEUP 
Servo Preamplifier, adjusting R58. 

4. 7. 7. 4 Data Section Adjustments 

The data read/write deskewing adjustments are de- 
scribed in paragraph 4. 7.2 of this section. The only 
other adjustment required is the output voltage ad- 
justment of the read preamplifier stages. This ad- 
justment should be made after the transport speed 
has been checked and, if necessary, adjusted (see 
paragraph 4. 7. 2. 4) . The output voltage of each read 
preamplifier stage should then be adjusted, using 
the potentiometer associated with that stage, until 
the output voltage is 9 volts peak to peak in 800 cpi 
operation. 

4.8 PARTS REPLACEMENT 

Over extended periods replacement of certain parts 
may be required. While disassembly and assembly 
are for the most part obvious upon inspection, the 
following information will simplify repair procedures 
for certain parts. 

4.8.1 HEAD REPLACEMENT 

a. Unplug head and remove screws holding 
head connectors to deck. 

b. Remove head cover. 

c. Remove head mounting screw. 

d. Pass connectors through hole provided in 
the deck. 

NOTE 

Do not remove head from head mount- 
ing plate. Replacement heads are 
furnished with mounting. 



e. Replace head and connectors. Make Cer- 
tain adjusting screw is aligned with hole 
provided on the deck. 

f. For procedures to deskew head and adjust 
write amplifiers, follow procedures given 
earlier in this section. 

4. 8. 2 CAPSTAN MOTOR REPLACEMENT 

a. Unplug motor. 

b. Remove capstan locking screw. 

c. Pull capstan off shaft. (This requires the 
use of a special fuller available from the 
factory on purchase or loan. ) 

d. Remove four motor mounting screws and 
motor. 

e. Replace the motor, being careful to orient 
motor mounting so that the motor brush 
holders do not strike the control card cage. 

f . Replace capstan and tighten capstan lock- 
screws. 

4.8.3 REEL MOTOR REPLACEMENT 

a. Disconnect terminal block from cable. 

b. Remove four motor mounting nuts and reel 
motor. 

c. Replace motor. 

d. Adjust belt tension so that when belt is 
squeezed in the center about 1/4 inch (6.3 
mm) deflection occurs. 

4.8.4 TENSION MAG POT REPLACEMENT 

a. Remove buffer arm roller guide. 

b. Unplug magpot cable. 

c. Remove spring from anchor. 

d. Remove two mounting screws to free the 
magpot assembly. 

NOTE 

Replacement magpot assemblies are 
supplied prealigned. If position align- 
ment is required see paragraph 4. 4. 6. 



4-9 



406-9802-OOOA 



e. Install replacement assembly. 

f. Check tape path. If adjustment is needed see 
paragraph 4.7.4. 



4.8.5 VOLTAGE REGULATOR/SERVO POWER 
ASSEMBLY REPLACEMENT 

a. Remove eight mounting screws. 

b. Unplug molex connectors from the master 4 
board. 

c. Plug in replacement unit and reassemble. 



4.9 TEST PANEL USE 

The test panel, standard equipment in Model 9000, is 
packaged in a box and supplied as Model 9900 for use 
with Model 9700/9800 transports (see Figure 4-8). Its 
use is identical in all transports. 

A diagrammatic representation of the controls and 
indicators, together with brief descriptions of their 
purpose, is given in Figure 4-9. It will be noted that 
the box allows tape to be moved in either direction, 
normal speed or fast speed. Motion is interlocked to 
prevent running off reels at either end. Additionally, 
the 9900 allows writing an all ones pattern on the 
tape and provides indicators for skew, data, load 
point, and EOT. 

The test panel is intended to be used in checking the 
machine when off line or, for that matter, when 
completely isolated from the operating system. The 
controls provided are useful under these 
circumstances but under normal operation they would 
be confusing and invite possible operator error. For 
this reason the panel is accessible only by opening a 
sliding cover on Model 9800. 

Because of the special nature of phase encoded and 
dual density transports, use of the test panel is 
slightly modified. The above discussion applies to 
NRZI only. Test panel use with other units is 
discussed in portions of the manual applicable to 
these types. 



4.9.1 OPERATION 

The test panel becomes operational only in test mode, 
selected by pressing the alternate action TEST MODE 
pushbutton. For the TEST MODE button to be 
operational the machine must be: 

a. Offline 

b. STOP must be depressed 




Figure 4-8. Test Panel Installation 



Test mode is terminated by either: 

a. Pressing alternate action TEST MODE button 

b. Pressing ON LINE pushbutton 

A characteristic of Series 9000 electronics is that 
when LOAD is pressed the machine feeds forward to 
load point. If tape is already wound on the machine 
arid the load point marker has been passed, search 
will continue to end of tape unless REWIND is 
pressed. This characteristic is sometimes 
troublesome when servicing the machine. Under 
these circumstances, pressing TEST MODE will 
terminate search and induce an ON TAPE status in 
the control electronics. If ON LINE is subsequently 
pressed, the ON TAPE status is retained. This 
feature can be adapted to allow power turn-off while 
tape is loaded. 

When using tape motion pushbuttons the STOP button 
should be pressed between changes in motion speed or 
direction. No harm will result if this is not done, but 
on occasion switch bounce will cause the command 
not to be recognized and the last motion signaled will 
be retained. 



4-10 



406-9802-100A 



4.9.2 SKEW INDICATOR 

An LED indicator is provided which flashes if skew is 
being encountered. Logic in the data section detects 
skew to two different criteria and lights the 
indicator. The skew gate in the NRZI read 
electronics is normally open for 50 percent of one 
character time (see discussion of read electronics). If 
pulses fall outside the skew gate they trigger the 
indicator. In test mode the skew gate is narrowed to 
5/32 of a character time. An all ones pattern on a 
properly adjusted machine should fall inside the 
shortened gate. A tape with random data suffers 
from pulse crowding effects and will not, in general, 
fall inside the gate. Thus in test mode the skew 
indicator is valid for an all ones data pattern only. In 
normal operation it is valid for all data patterns. 



4.9.3 DATA INDICATOR 

The DATA INDICATOR is illuminated when the tape 
being read has data written on it of a level sufficient 
to activate the read electronics. It of course blinks 
when reading gapped data. 

4.9.4 LOAD POINT INDICATOR 

This LED lights when load point is sensed. 

4.9.5 EOT INDICATOR 

EOT is indicated when the end of tape marker is 
sensed in the forward direction and remains true until 
it is passed in the reverse direction. All indicators 
operate whether or not test mode is selected. 



4-11 



SECTION V 
PARTS IDENTIFICATION 



SECTION V 



PARTS IDENTIFICATION 



5.1 SPARE PARTS ORDERING INFORMATION 

This section describes the replaceable parts in your 
tape unit which are available only from Kennedy 
Company. Many parts of the unit are common 
commercial parts which can be obtained directly 
from the manufacturer. 

The serial number and part number of the tape unit 
are the keys to numerous engineering details applying 
to your unit. These numbers are located on the serial 
number tag located on the rear panel of the unit. 
When ordering spare parts, accessories, or tools, 
always specify the serial number and part number of 
your unit. 

Changes to Kennedy units are sometimes made to 
accommodate improved components as they become 
available, and to give you the benefit of the latest 
circuit improvements developed in our engineering 
department. If a part you have ordered has been 
replaced by a new part, a Kennedy representative will 
contact you concerning any change in part number. 

All parts orders should be addressed directly to 
Kennedy Company, Parts Order Department, 540 
West Woodbury Road, Altadena, Ca 91001, telephone 
(213) 798-0953, TWX 910-588-3751. 



5.2 IN-WARRANTY REPAIR PARTS ORDERING 
INFORMATION 

Repair parts for in-warranty units are made available 
on an exchange basis through the Kennedy Company 
Customer Engineering Department. 

The serial number and part number of the tape unit 
are necessary in order to insure shipment of the 
proper replacement parts. 



All inquiries should be directed to Kennedy Company, 
Customer Engineering Department, 540 West Wood- 
bury Road, Altadena, Ca 91001, telephone (213) 798- 
0953, TWX 910-588-3751. 

5.3 EXPORT ORDERS 

Customers outside the United States and Canada are 
served by Kennedy Company international sales 
agents. All correspondence regarding your tape unit 
should be directed to your sales agent. If you prefer, 
correspondence may be addressed directly to Kennedy 
Company, Parts Order Department, 540 West Wood- 
bury Road, Altadena, Ca 91001, TWX 910-588-3751, 
cable KENNEDYCO. 

5.4 ILLUSTRATED PARTS LIST 

To assist in parts identification, an illustrated parts 
list is included with references to photographs of the 
machine. Part numbers beginning with an 8 or 198 
are listed again in the Recommended Spare Parts List 
at the end of this section. Kennedy Company 
recommends that these parts be ordered as spares to 
minimize machine downtime due to equipment 
failure. Certain parts on this list have no quantity 
indicated. We recommend ordering one of each such 
parts for remote installations where parts delivery is 
time consuming. 

5.5 FIELD KITS 

Some replacement components may be supplied in the 
form of repair or field change kits. The repair kits 
contain parts that are matched or assembled and 
adjusted at the factory because of complexity or to 
aid the field technician. The components ordered as 
field kits either by correspondence with Kennedy 
service engineers or by direct order will be supplied 
with complete installation instructions. The change 
kits are intended for standard or special options not 
originally included in the unit. 



5-1 



506-9801-200B 





ILLUSTRATED PARTS BREAKDOWN FOR FIGURE 5-1 



Item No. Part No. Description 

190- 3373-004 Dust Cover Assy (includes control panel) 
890-3371-004 Control Panel Assy 

191- 2915-001 Door Latch 
128-0003-002 Door Catch 

Not shown 198-0014-001 Slide Set 




5-2 



506-9801-300D 




ILLUSTRATED PARTS BREAKDOWN FOR FIGURE 5-2 



Item no. 


Part No. 


5- 


-2 


-1 


19Q- 


-3955- 


-002 


5- 


-2 


-2 


890- 


-2744- 


-001 


5- 


-2 


-2 


198- 


-0010- 


-001 


5- 


-2 


-2 


825- 


-0030 


-006 


5 


-2 


-2 


828 


-0090 


-001 


5 


-2 


-3 


890 


-1138 


-001 


5 


-2 


-4 


890 


-2627 


-001 


5 


-2 


-5 


890 


-2772 


-002 


5 


-2 


-6 


291 


-2964 


-005 


5 


-2 


-7 


191 


-2966 


-001 


5 


-2 


-8 


890 


-2647 


-002 


5 


-2 


-9 


851 


-0038 


-001 


5 


-2 


-10 


890 


-1509 


-001 


5 


-2 


-11 


190 


-2747 


-001 


5 


-2 


-12 


890 


-1139 


-001 


5 


-2 


-13 


198 


-2399 


-010 


5 


-2 


-13 


198 


-2399 


-003 


5 


-2 


-14 


890 


-2605 


-001 



Description 

Deck Assy 

Quick Release Hub 

Hub Bearing Assy 

O-Ring 

Spring Washer 

Load Point/EOT Photosensor Assy 
Idler Assy 
Takeup Hub Assy 
Dust Cover Mount 
Hinge Pin 

Tension Roller Guide Assy 

Power Switch 

Split Tape Guide Assy 

Tape Cleaner Assy 

Broken Tape Photosensor Assy 

Head and Head Mounting Assy, 9 Track Read and Write 
Head and Head Mounting Assy, 7 Track Read and Write 
Capstan 



5-3 



506r9801-400B 




10 9 8 



Figure 5-3. Model 9800 Chassis: Rear View (Assembled) 
ILLUSTRATED PARTS BREAKDOWN FOR FIGURE 5-3 



ITEM 


PART NO. 


DESCRIPTION 


5-3- 


-1 


148- 


-0122- 


-001 


Power Transistor, Type MJ802 Motorola 


5-3- 


-2 


148- 


-0121- 


-001 


Power Trarisistor, Type MJ4502 Motorola 


5-3- 


-3 


148- 


-0102- 


-003 


Power Transistor, Type MJ900 Motorola 


5-3- 


-4 


148- 


-0102- 


-004 


Power Transistor, Type MJ1000 Motorola 


5-3- 


-5 


148- 


-0053- 


-001 


Power Transistor, Type 2N3055 


5-3- 


-6 


148- 


-0075- 


-001 


Power Transistor, Type 2N4910 


5-3- 


-7 


890- 


-4352- 


-001 


Voltage Regulator PC Board 


5-3- 


-7 


890- 


-4441- 


-001 


Regulator and Servo Assembly 


5-3- 


-8 


127- 


-0003- 


-001 


Power Receptacle 


5-3- 


-9 


151- 


-0802- 


-001 


Fuseholder 


5-3- 


-9 


851- 


-0133- 


-030 


Fuse, 3 AG, 3 A (115 vac operation) (box of 5) 


5-3- 


-9 


851 


-0133 


-015 


Fuse, 3 AG, 1.5A (220 vac operation) (box of 5) 


5-3- 


-10 


851- 


-5001 


-103 


Switch, 115/220 vac 



5-4 



506-9801-500D 




Figure 5-4. 



Model 9800 Chassis: Rear View (Power Supply Removed) 

ILLUSTRATED PARTS BREAKDOWN FOR FIGURE 5-4 



ITEM 


PART NO. 


DESCRIPTION 


5-4-1 


825-0017-003 


Extension Spring 


5-4-2 


890-4438-002 


Takeup Reel Motor Assembly, 16 Tooth 


5-4-3 


825-0004-002 


Takeup Reel Drive Belt 


5-4-4 


191-0805-001 


Takeup Reel Drive Pulley 


5-4-5 


890-4013-001 


Connector PC Board Assembly 


5-4-6 


825-0004-003 


Supply Reel Drive Belt 


5-4-7 


191-2643-001 


Supply Reel Drive Pulley 


5-4-8 


890-2641-001 


File Protect Switch Assembly 


5-4-9 


198-0009-011 


Supply Reel Magpot Sensor 


5-4-9 


890-4210-002 


Magpot PC Board Assembly 


5-4-9 


891-4198-001 


Cover 


5-4-10 


828-0067-001 


Recessed Bumper 


5-4-11 


890-3631-xxx 


Read Preamplifier Assembly 


5-4-12 


890-2484-004 


Capstan Motor Assembly 


5-4-13 


121-0145-004 


20 Pin Connector 


5-4-14 


198-0009-012 


Takeup Reel Magpot Sensor Assembly, complete 


5-4-14 


890-4210-002 


Magpot PC Board 


5-4-14 


891-4198-001 


Cover 


5-4-15 


890-4438-001 


Supply Reel Motor Assembly, 14 Tooth 



NOTE 



NOTE 1: Refer to dash number stamped on circuit board to determine complete part number. 
NOTE 2: In 37.5 ips machines, the takeup reel motor is numbered 890-4438-002. The supply 
reel motor is still numbered 890-4438-001 in 37.5 ips units. 



5-5 



506-9801-600C 



1 3 4 5 6 7 8 9 10 18 11121314151617 




Figure 5-5. Model 9800 Tape Transport: Top View 



ILLUSTRATED PARTS BREAKDOWN FOR FIGURE 5-5 



ITEM 


PART NO. 


DESCRIPTION 


5-5-1 


815-3625-199 


Capacitor, Aluminum, Electrolytic; 19K mfd, 25 vdc 


5-5-2 


815-3610-449 


Capacitor, Electrolytic, 44K mfd, 10 vdc 


5-5-3 


890-4474-001 


Power Transformer Assembly 


5-5-10 


190-3841-001 


Control Terminator PC Board 


5-5-15 


190-3860-001 


Data Terminator PC Board 


5-5-5 




For part number, see Recommended Spare Parts List 


thru 




(5-5-10 and 5-5-15 listed above) 


5-5-17 







5-6 



506-9801-700E 



RECOMMENDED SPARE PARTS LIST 



Item 


No. 


Part No. 


Description 




5- 


i „ 
i 


.o 

L 




-■^^71- 

JO I 1 


-find 

UU4 


Control Panel Assy 




5- 


o. 

L 


9 




-fim n- 

UU1U 


UU 1 


Hub Bearing Assy 




5- 


O. 

L 


Q 

o 




-1 1 ^fi- 
ll Jo 


_nn i 


Load Point/EOT Photosensor Assy 




5- 


0. 


-4 


RQfl- 


-9fi97- 

L U L ( 


_nn i 

UU 1 


Idler Assy 




5- 


0- 

L 


.0 

o 




Li O i 


UU L 


Tension Roller Guide Assy 




5- 


2- 


1 u 


8^1 - 


uuoo 


-nm 

UU 1 


Power Switch 




5- 


0. 


-1 9 




-1 1 ^Q- 


_nn i 

UU X 


Broken Tape Photosensor Assy 




5- 


9- 


-1 T 


1 I/O 


- 9 ^ Q Q - 


U 1 u 


Head and Head Mounting Assy, 9 Track RAW 


5- 


9- 




1 Q8- 


LOW 


UU o 


Head and Head Mounting Assy, 7 Track RAW 


5- 


2- 


-14 


890- 


-2605- 


-001 


Capstan 




5- 


3- 


-7 


890- 


-4441- 


-001 


Regulator and Servo Assy, complete 




5- 


O 




8=11 - 


-01 

Uluu 




Fuse, 3 AG, 3 A (115 vac use, box of 


5) 


5- 


■3- 


-9 


851- 


-0133 


-015 


Fuse, 3 AG, 1.5 A (220 vac use, box 


of 5) 


5- 


3- 


-10 


851- 


-5001 


-103 


Switch, 115/220 vac 




5- 


4- 




825- 


-0017- 


-003 


Extension Spring 




5- 


4- 


-2 


890- 


-4438- 


-002 


Reel Motor Assy 




5- 


4- 


-3 


825- 


-0004 


-002 


Takeup Reel Drive Belt 




5- 


•4- 


-5 


890- 


-4013 


-001 


Connector PC Board Assy 




5- 


4- 


-6 


825- 


-0004 


-003 


Supply Reel Drive Belt 




5- 


4- 


-8 


890- 


-2641 


-001 


File Protect Switch Assy 




5- 


4- 


-9 


198- 


-0009- 


-011 


Supply Reel Magpot Sensor, complete 




5- 


-4- 


-9 


890- 


-4210 


-002 


Magpot PC Board Assy 




5- 


-4- 


-1 1 


oon. 

O «7 U 




-YYV 
AAA 


Read Preamplifier Assy 




5- 


■4- 


-12 


890- 


-2484 


-004 


Capstan Motor Assy 




5- 


4- 


-14 


198- 


-0009 


-012 


Takeup Reel Magpot Sensor Assy, complete 


5- 


-4- 


-14 


890- 


-4210 


-002 


Magpot PC Board Assy 




5- 


4- 


-15 


890- 


-4438 


-001 


Supply Reel Motor Assy, 14 tooth 




5- 


-5- 


-1 


815- 


-3625 


-199 


Capacitor, Electrolytic, 19K mfd, 25 


vdc 


■5- 


-5- 


-2 


815- 


-3610 


-449 


Capacitor, Electrolytic, 44K mfd, 10 


vdc 


5- 


5- 


-3 


890- 


-4474 


-001 


Power Transformer Assy 




5- 


•5- 


5 


890- 


-4306 


-xxx 


Servo Preamplifier PC Board 




5- 


5- 


-6 


890- 


-3844 


-xxx 


Sensor Amplifier/Driver PC Board 




5- 


5- 


-7 


890- 


-3645 


-xxx 


Ramp Generator PC Board 




5- 


5- 


-8 


890- 


-3843 


-xxx 


Pushbutton Control PC Board 




5- 


-5- 


-9 


890- 


-3842 


-xxx 


Interface Control PC Board 





Qty. 



Notes 



NOTES 



PC board dash number will vary depending upon machine specifications. Refer to the circuit board 
identification card in the machine or check the PC board for a stamped dash number. 

In 37.5 ips machines, the supply and takeup reel motors are both numbered 890-4438-001. 



s-7 



506-9801-800H 



RECOMMENDED SPARE PARTS LIST 

(Continued) 



Item No. 


Part No. 


Description 


5- 


5-11 


890- 


-3845- 


-xxx 


UcLay llllllllg ITK-s DUdl U 


5- 


-5-11 


890- 


-4118- 


-XXX 


< 1 1 atK Lfnidy i lining tjoai a 


5- 


5-11 


890- 


-4365- 


-xxx 


uuai uensiiy iw/Oiiiroi ru ooara vouai aensity rnocieis/ 


5- 


5-11 


890- 


-4209- 


XXX 


IxGaO l^OIHIOI ljOglC 


5- 


-5-12 


890- 


-4179- 


-xxx 


Read Amplifier/Clipping* Level Control 


5- 


-5-12 


890- 


-4188- 


-xxx 


Read Amplifier/Clipping* Level Control (1600 epi models) 


5- 


5-12 


890- 


-4367- 


-xxx 


Replaced by; 






890- 


-6367- 


-xxx 


Dual P Channel Clipping Control (dual density models) 


5- 


-5-13 


890- 


-4178- 


-xxx 


yuao rteaa Ampin ler rt rjoara 


5- 


-5-13 


890- 


-4139- 


-xxx 


yuaa rii neaa uetector yfr, moaeisy 


5- 


-5-13 


890- 


-4385- 


-xxx 


Replaced by: 






890- 


-6385- 


-xxx 


Quad Read Amplifier (dual density models) 


5- 


-5-14 


890- 


-4178- 


-xxx 


Quad Read Amplifier PC Board 


5- 


-5-14 


890- 


-4139- 


-xxx 


v^uaa rt Keaa uetector irt moaeis/ 


5- 


-5-14 


890- 


-4385 


-xxx 


Quad Read Amplifier PC Board (dual density models) 


5- 


-5-16 


890- 


-3848- 


-xxx 


Four Channel Write Amplifier PC Board 


5- 


-5-16 


890- 


-4207- 


-xxx 


four unannei Ft, write Ampiiiier \trc. moaeis ,j 


5- 


-5-16 


890- 


-4366- 


-xxx 


Four Channel Write Amplifier (dual density models) 


5- 


-5-17 


890- 


-3849 


-xxx 


rive onannei write /vmpimer 


5- 


-5-17 


890- 


-4208- 


-xxx 


Five Channel PE Write Amplifier (PE models) 


5- 


-5-17 


890- 


-4368 


-xxx 


Five Channel Write Amplifier (dual density models) 


5- 


-5-18 


890- 


-4206 


-xxx 


Masterboard 


5- 


-5-18 


890- 


-4509 


-001 


Masterboard (dual density models) 


Not 


shown 


825- 


-0068 


-001 


Power Cord 


Not 


shown 


821- 


-9000 


-003 


Power Cord (230 vac or dc power) 


Not 


shown 


198- 


-0103 


-001 


Brush Replacement Kit, Capstan Motor Tachometer 


Not 


shown 


198- 


-0075 


-001 


Brush Replacement Kit ^ Reel Motor (4 brushes) 


Not 


shown 


198- 


-0100 


-001 


Hub Repair Kit 


Not 


shown 


198- 


-0014 


-002 


24" Rack Slide Set 


Not 


shown 


198- 


-0014 


-001 


18" Rack Slide Set 



Qty 



Notes 



NOTES 



1. PC board dash number will vary depending upon machine specifications. Refer to the circuit board 
identification card in the machine or check the PC board for a stamped dash number. 



Hub repair kit contains items subject to wear; i.e., O ring, reel drive latch, and thrust washer. 



5-8 



SECTION VI 
WIRING AND SCHEMATIC DIAGRAMS 



606-9801-100B 



SECTION VI 
WIRING AND SCHEMATIC DIAGRAMS 



This section contains the wiring diagrams, schematic 
diagrams, and circuit descriptions for the individual 
circuit cards used in the transport. The schematics 
are arranged by functional group as shown below. 



Electronics symbols used in the drawings conform 
to MIL-STD-15. Abbreviations conform to MIL- 
STD-12 unless otherwise specified. Logic diagrams 
conform to MIL-STD-H06C. 



Overall 



Power Supply 



Control Electronics 



Control Terminator 
Interface Control 
Tape Motion Controls, including 
Pushbutton Control, Main Control Panel, 

iand Test Panel 
Ramp Generator 
Sensor Amplifier/ Driver 
Connector Board 



Servo System 



Servo Preamplifier 

Magpot Tension Arm Position Sensor 



Read Electronics 



Data Terminator 

Read Preamplifier 

Read Control Logic, including 
Nine Track Delay Timing 
Seven Track Delay Timing 

Quad Read Amplifier 

Read Amplifier/ Clipping Control 



Write Electronics 



Write Amplifier, Section A 
Write Amplifier, Section B 



6-1 



CIRCUIT CARD IDENTIFICATION 


LOC 


TYPE 


FUNCTION 


READ/WRITE SECTION 


1 


3849-001 


5 CHANNEL HEAD DRIVER 


2 


3848-001 


4 CHANNEL HEAD DRIVER 


3 


3860-001 


DATA TERMINATOR 


4 


4178-001 


QUAD READ AMPLIFIER 


5 


4178-001 


QUAD READ AMPLIFIER 


6 


4179-001 


P CHANNEL/CLIPPING 


7 


3845-001 


DELAY TIMING 


CONTROL SECTION 


8 


3841-001 


CONTROL TERMINATOR 


9 


3842-001 


INTERFACE CONTROL 


10 


3843-001 


PUSHBUTTON CONTROL 


11 


3645-001 


RAMP GENERATOR 


12 


3844-001 


SENSOR AMPLIFIER/DRIVER 


13 


4306-001 


SERVO PREAMPLIFIER 



MODEL 
9832 


PART NO. 
192-9832-094 


INTERFACE 
STD 


SPEED 
25 IPS 


DENSITY 
800 CPI 


TRACKS 
9 


MODIFICATIONS 
512 BUFFER 



606-0001-300 

NOTES TO SCHEMATIC SECTION 



Certain conventions have been observed in preparing 
schematics for this manual: 

1. Resistor values are given in ohms. If wattage 
is unspecified the resistor may be either 1/4 or 
1/2 watt. 

2. Capacitor values may be given in picofarads or 
microfarads. Those values for which neither 
designation is provided are assumed to be ob- 
vious from circuit function. Filter capacitors 
on certain supply lines do not have logic signifi- 
cance. In general, they are not shown on sche- 
matics. On PC board silkscreens they are des- 
ignated as CF. 

3. Normally, IC power connections are on pins 14 
(+5v) and 7 (ground) for 14 pin packages, and 16 
(+5v) and 8 (ground) for 16 pin packages. Some 
ICs — 7476, 7492, 7493 for example — have power 
connections on pin 5 (+5v) and pin 10 (ground). 
Operational amplifiers in the 8 pin package have 
power connections on pin 4 (-Vcc) and pin 7 
(+Vcc). Power connections are not shown unless 
they are nonstandard. 

4. Where multiple inputs are tied together only one 
pin may be designated on the schematic. 

5. Unused inputs that are tied high are not normally 
indicated unless the connection has logic signifi- 
cance. 

6. From and to designations are intended to describe 
inputs and outputs only. The same signal may 
be connected to several other points not shown 
on a particular drawing. 

7. Abbreviations used in from and to designations 
are as follows: 



8. Positive logic is shown for all internal connec- 
tions. Interface connections are zero true but 
the bar is omitted. 

9. Integrated circuit symbols contain a circuit 
designator that corresponds to the number silk- 
screened onto the circuit module above an under- 
lined number representing the IC type. 

The IC type number is abbreviated and omits 
the portions of the manufacturer's type number 
pertaining to case arid vendor identification. 
Further, since the TTL 7400 series makes up 
most of the circuitry, the 74 is omitted on these. 
Thus a 00 designation indicates a 7400 quad two 
input NANI) gate. T.I.'s complete part number 
is SN7400N. In multifunctional units in close 
proximity to each other the type designation may 
be omitted. The type designation may appear 
outside the symbol if the symbol is too small. 

Military Standard 806C is the base for logic 
symbols. Additional conventions are shown be- 
low. 



Line indicates buffer or power driver 




Line indicates open collector 

A 



Triangle indi- 
cates response 
to edge (in this 
case positive) 




CI 


Control Interface 




PBC 


Pushbutton Control 




RG 


Ramp Generator 


10. Semiconductor types on schematics may be re- 


SA 


Sensor Amplifier/ Driver 


placed by their functional equivalents. If not 


DT 


Delay Timing 


indicated, diodes, are 1N914, NPN transistors 


RA/CL 


Read Amplifier/ Clipping Level 


are 2N2714, and PNP transistors are MPS6517. 


RA 


Quad Read Amplifier 




WA1 


Four Channel Write Amplifier 


11. Unless otherwise specified, light emitting diodes 


WA2 


Five Channel Write Amplifier 


are FLV102 or equivalent. 



6-3 



606-0001-400 



12. Module connector pins are shown as 

>E 

where no further connection is shown on the 
schematic, and as 

22 



when there is a connection shown. 

13. Where an input is represented by an arrow in- 
stead of a complete line, the input source is 
designated. Where outputs are so shown their 
destinations may not be shown. 

14. Some schematics of modules include certain ex- 
ternal elements which aid in understanding the 



circuit function. In this case all the connections 
to the element may not be shown in the interest 
of clarity. 

15. designates a test point provided on the 
module. Letters proceed from top to 

Y bottom of card with the ground test 
■ ■ # point, if present, as the bottommost 
terminal. 

16. Socket terminals are designated with numbers 
for component side connections and letters for 
circuit side connections when a double sided 
socket is used. These are the designations on 
the socket. When ajsingle sided socket is pro- 
vided, all connectionjs are designated by letters 
regardless of which side of the board they lie on 
the etch. Letters follow the 22 pin. alphabet, 
ABCDEFHJKLMNPRSTUVWXYZ; numbers are 
1 through 22. 



6-4 



806-9800-100 



MODEL 9800 POWER SUPPLY 
CIRCUIT DESCRIPTION 



Power supply in Model 9800 produces the unregulated 
and regulated voltages required by motors and elec- 
tronics* 

PRIMARY POWER 

Primary power is switchable to allow either 115v or 
220V mains. Frequency is not critical and may be 
from 48 Hz to 500 Hz. 220 volt mains predominate 
in Europe, hence this selection of voltages. A sim- 
ple modification allows 230v operation if required. 
For 115v operation the two 115v primary windings 
of are connected in parallel by S2. For 220v 
operation a 105v tap on primary winding 2 is con- 
nected in series with primary 1. Modification for 
230v operation requires removal of the violet wire 
and installation of a jumper from S2-6 to S2-3. 

SECONDARY POWER 

Transformer secondary voltages are rectified to 
produce nominal unregulated voltages of ±24v (±26v 
under light load) and +8v„ ± 24v regulated is supplied 
to motor drive circuits and provides sources from 
which ±10v regulated is produced. +8v is the source 
for a high efficiency +5v regulator. 

+10 VOLT REGULATOR 

Pass transistor Q3 is fed from +24v and its base is 
driven by a monolithic regulator IC2 . Voltage output 
is determined by R8 and R9. Q7 and Q8 control power 
supply tracking when powering down. As +24v drops 
owing to discharge of CI, Q8 cuts off at approximately 
13 volts on the +24v line. When this happens Q7 is 



turned on shorting outR9 and dropping the regulator 
reference voltage to zero. The +10 output is cut off 
and drops to zero. Since +I0v is the reference for 
-lOv, -lOv also drops to zero. This action occurs 
before the +5v supply has dropped sufficiently to 
cause indeterminate logic states; turn-off transient 
motions are prevented. * 

-10 VOLT REGULATOR , 

The -lOv supply is regulated by pass transistor Q4 
driven by Q6. Its reference is +10v as determined 
by R13, R14. In this way the two regulated voltages 
are made to track or retain a constant relationship 
to each other. 

+5 VOLT REGULATOR 

An integrated circuit regulator IC1 controls +5v out- 
put in conjunction with pass transistor Ql and driver 
Q2. Output voltage is set by R4, R5. An inset on 
the schematic shows the internal circuitry of IC1, 
IC2. It will be noted that it consists of a differential 
amplifier with built-in zener reference together with 
facilities for short circuit protection. Q2 assures 
that sufficient base drive is available for Ql. 

SHORT CIRCUIT PROTECTION 

Drop through series resistors, for example R10 in 
the -lOv supply, provides short circuit protection. 
If the drop across R10 exceeds approximately 0.6v, 
Q5 is turned on connecting Q4 base to emitter and 
cutting off Q4. This corresponds to approximately 
1. 5 amperes under short circuit conditions. Similar 
circuits are provided in IC1 and IC2. 



806-3842-100 C 



TYPE 3842 INTERFACE CONTROL 
CIRCUIT DESCRIPTION 



This module contains a set of receivers for the inter- 
face control commands: 

SYNCHRONOUS FORWARD SFC 

SYNCHRONOUS REVERSE SRC 

OVERWRITE OVW 

REWIND RWC 

SELECT SLT 

SET WRITE STATUS SWS 

OFF LINE OFFC 

It also contains drivers that return the recorder 
status outputs to the interface: 

ON LINE ONL 
REWINDING RWDG 
FILE PROTECT FPT 
LOAD POINT LP 
WRITE ENABLE WEN 
READY RDY 
END OF TAPE EOT 
TAPE RUNNING TNG 

Certain controls and delays are also provided to en- 
sure proper tape motion and transport operation. 

TAPE MOTION CONTROLS 

The motion control commands from the interface, 
SFC and SRC, are translated on this card into the 
internal motion commands of the transport — RUN 
NORMAL RNN, FORWARD FWD, and REVERSE 
RVS. These internal motion commands are supplied 
to the Pushbutton Control module, where they are 
combined with commands supplied from the trans- 
port pushbuttons and internal interlocks to generate 
the commands that initiate actual tape motion on the 
Ramp Generator module. 

On this module SFC and SRC are supplied to an inter- 
locking network that ensures that the tape comes to 
a stop before its direction of motion is reversed. 
The interlocking network includes flip-flop I CI- 3, 
edge circuits IC2- 6 and IC2- 8, NAND gate IC3-6, and 
interlocking flip-flop IC3-10. Whenever flip-flop 
IC1 changes states due to a change in the direction 
of motion, for example from a reverse command 
SRC to a forward command SFC, its output generates 
a pulse through the edge circuits consisting of invert- 
ers IC2 and the associated capacitors. The pulse is 
gated through IC3-6 to the set input of interlocking 



flip-flop IC3-10. Th e flip-flop can be set only if 
TAPE RUNNING TNG is tru e, ind icating that the tape 
is still moving. In .this case TNG low at input pin W 
is inverted by IC18-12 and supplies a high input to 
the clear of IC3. The flip-flop can then be set by 
the pulse on its set input, its 0 output going low. The 
0 output of IC3 then inhibits the RUN N ORMA L gate 
IC15 at pin 2, setting RUN NORMAL RNN false. 
After the tape has ramped down to a stop, TAPE 
RUNNING TNG goes falsfe, clearing interlocking 
flip-flop IC3, whose output then enables the RUN 
NORMAL gate. RUN NORMAL RNN then goes true 
if the following conditions are satisfied: SELECT 
SLT1 is true, indicating that the transport is on line 
and selected by the interface; BUSY BSY is false, 
indicating the transport is not rewinding or searching 
for load point; and SRC command is not given at load 
point. (This would activate NAND gate IC15-8 and 
would disable the RUN NORMAL gate at IC15-1.) If 
the above conditions are satisfied, RUN NORMAL 
RNN goes true at output pin V, and is supplied to 
the Pushbutton Control module where it initiates 
tape motion at the normal running speed. The direc- 
tion of motion is determined by the state of flip-flop 
IC1. If a forward command SFC has been given, the 
flip-flop is set and its 1-output enables NAND gate 
IC14-8, provided that SLT 1 is tr ue and BSY is false. 
This generates FORWARD FWD true at output pin U. 
If a reverse command SRC has been given, flip-flop 
IC1 is cleared and enables NAND gate IC14-6, gen- 
erating REVERSE RTS true, providing SLT1 is true, 
BSY is false, and LOAD POINT LP is false. No 
interface reverse command is acknowledged by the 
transport when the load point is detected. 

WRITE SELECT 

During a write operation the interface supplies SET 
WRITE STATUS SWS true at pin K; SWS is inverted 
by IC9-4 and is supplied to the D input of flip-flop 
IC7. The flip-flop is toggled provided that the trans- 
port is selected and on line, after NOR gate IC1-11 
is activated by a synchronous motion command. This 
would activate NAND gate IC1-8 and trigger one-shot 
IC4-1, generating a 2jLiSec pulse. On the trailing 
edge of the pulse the <3 output of the one- shot toggles 
IC7-3, the Q output of the flip-flop going high and 
activating NAND gate IC10-11, generating WRITE 
SELECT WSELtrue at output pinH. During an over- 
write operation OVERWRITE OVW true is inverted 
by IC18-8 and sets the D input of flip-flop IC7-12 



806-3842-200C 



high. On the trailing edge of the pulse generated by 
one-shot IC4-4 the flip-flop is set and enables NAND 
gate IC8-12. One-shot IC4-4 also direct-sets flip- 
flop IC11, whose Q output enables the overwrite gate 
at IC8-9 0 If write status is true, the gate is enabled 
at IC8-13 and it is kept activated as long as a syn- 
chronous motion command is activating NAND gate 
IC1-8. IC8-8 then goes low and supplies WSEL for 
the duration of the motion command only. When a 
WRITE AMPLIFIER RESET pulse is given at pin P, 
it toggles flip-flop IC11 to the cleared state and dis- 
ables the overwrite gate. 

REWIND FLIP-FLOP 

When a REWIND COMMAND RWC is given by the 
interface, it sets the rewind flip-flop IC5-3, provided 
that the transport is selected, on line, and not at 
load point. The 1-dutput of the flip-flop then goes 
high, generating REWINDING R WDG tr ue to the in- 
terface, and a rewind command RWC1 through an 
edge circuit consisting of inverter IC6-6, NAND 
gate IC6-8, and capacitor C5. RWC1 is supplied to 
the Pushbutton Control module. The flip-flop is 
cleared when the tape returns to and stops at load 
point, or when BROKEN TAPE BKN is detected. 

END OF TAPE 

An end of tape indication is set when the EOT marker 
is encountered in forward direction and remains set 



until the marker is passed in the reverse direction. 



A tru e EOT signal at pin Z if machine status is 
RWDG (IC10-5,8) and RVS (IC14-6) causes IC11 to 
be preset by IC19-8. An EOT status is then signaled 
at the interface by IC16-3. 



Upon passing the EOT marker in the reverse direc- 
tion IC13-3 is high and the EOT signal clocks ICll 
clear on the trailing edge of the EOT signal dropping 
the EOT signal at the interface. ICll is preset to 
the clear state by BKN signal at pin X. 

OUTPUT STATUS 



Most status gates on this module are preconditioned 
by SELECT and ON LINE being true; consequently, 
the transport returns status indications only when it 
is selected and on line. The READY status is gener- 
ated when BUSY BSY supplied from the Pushbutton 
Control module is false and the transport is not re- 
winding. The LOAD POINT output is also precon- 
ditioned by the rewinding status being false. The 
only status gate not preconditioned is the rewind 
via the REWIND pushbutton. If the pushbutton is 
used to rewind, that status is made available to the 
interface without being selected and on line. 



806-4842-100 



TYPE 4842 INTERFACE PC BOARD 
CIRCUIT DESCRIPTION 



This board contains receivers and gating circuits for 
developing tape transport commands from incoming 
controller commands., It also contains line drivers for 
outputting tape transport status commands to the 
controller. In addition, type D flip-flop IC10 outputs 
EBDIS/, the Erase Bar Disable signal required during 
tape editing. 



Tape Motion Control Circuitry 

SFC, SRC, FAST tape motion commands from the 
controller are translated into internal tape transport 
motion commands RNN/, RNF/ and RVS/ by quad 2x1 
multiplexer IC15. These internal commands are 
supplied to the Pushbutton Control module where 
they are combined with commands from the transport 
pushbuttons and the internal interlocks to develop the 
actual tape motion commands issued to the 
transport's Ramp Generator PC board. 

SRC, SFC and FAST are supplied to an interlocking 
network On this PC board to insure that tape motion 
ceases prior to accepting a new direction command. 
The interlock network consists of a high frequency 
sampling oscillator (IC11 and related components), 
and a directional interlock flip-flop (IC14 and related 
components) to select and generate the appropriate 
RUN NORMAL, RUN FAST and REVERSE signals 
required by the transport. The oscillator monitors 
the state of TNG/ (Turning) signal. This signal 
disables oscillator output when the capstan is turning 
and enables Oscillator output when tape and capstan 
motion ceases. 

Table 1 indicates the controller inputs and interface 
board outputs required to initiate a given tape 
motion. 

To generate RNN true for forward tape motion, SFC 
(Synchronous Fofward Command) from the controller 
must be true. This is supplied to the D input of 
interlock flip-flop IC14 and pin 3 of multiplexer IC15. 
After capstan motion : ceases, TNG/ goes false, 
enabling the high frequency oscillator at IC11, pin 3 
to clock out Q high at 1C14-5. This is applied to 
multiplexer IC15-1 to select its B inputs. Since SFC 



Tape Mode Controller Command 

Forward = SFC true 

Reverse = SRC true 

Fast Forward = SFC true + FAST true 

Fast Reverse = SRC true + FAST true 



high is applied to the IB input of the multiplexer, the 
output at IC15-4 goes high. This is inverted low at 
inverter IC16-11 to produce RNN/ (Run Normal) true 
at pin V. 

Should the Synchronous Reverse Command (SRC) be 
issued to the transport, it will not be able to produce 
a RVS/ transport command until capstan rotation 
ceases. SRC true is gated "With LP/ false to enable 
1C6-6. IC6-6 high is applied to inputs 1A and 2 A of 
the multiplexer. After tape motion stops, TNG/ false 
enables the sampling oscillatpr, clocking the Q output 
of IC15-5 low, since SFC would now be low false 
after inversion at IC14. IC15-1 of the multiplexer 
goes low, selecting the A multiplexer inputs. IC15-4 
again goes high to issue RNN/ true at pin V IC15-7 
also goes high and is inverted low at IC16-3 to 
produce RVS/ true. 

Fast forward tape motion does not require a stopped 
tape, if a direction change is not required since the 
requisite RNN true is routed back to pin 11 of the 
multiplexer IC and output whenever the A inputs are 
selected by IC14-5 low. TCI 5-9 goes high at this 
point, making NAND gate IC16-10 high. FAST true 
from the interface will enable IC16, which outputs 
RNF/ true at pin U. RNN/ at pin V will also be true 
as required by the ramp generator for fast forward 
tape motion. When the End of Tape mark is reached, 
EOT/, connected to pin 10 of the multiplexer, will go 
low true, causing IC15-9 to go low to disable a run 
fast operation (now being interpreted as normal run). 

Fast reverse tape operation is initiated by generating 
RNN/ true, RNF/ true and RVS/ true. Thus, the 
controller must issue SRC true and FAST true. After 
capstan rotation ceases and TNG/ goes false, Q low is 
clocked out of IC14-5, selecting the B multiplexer 
inputs. Then RNN/, RNF/ and RVS/ at pins V,U and T 
all go low true. 

Tape motion will be disabled whenever BSY true or 
SLT/ false signals are issued. This would disable 
NAND gate IC3-6, resulting in a high false STROBE 
signal at IC15-15, which disables all multiplexer 
outputs. 



Interface PCB Output 
RNN/true 



RNN/true + RVS/true 
RNN/true + RNF/true 
RNN/true + RNF/true + RVS/true 



Table 1 



806-4842r200 



Write Select 

Control of the write amplifier is performed by SWS 
(Set Write Status), OVW (Overwrite) and internally 
generated WARS1 (Write After Read Strobe) signals 
which generate WSEL/ (Write Select) and EBDIS/ 
(Erase Bar Disable). WSEL/ and EBDIS/ are output to 
the sensor amplifier and pushbutton control cards. 

A sampling scheme is employed to permit the 
interface to issue tape motion and WSEL commands 
simultaneously. RNN/ true and RNN true are delayed 
16 and 8 usee respectively by RC networks R8/C1 and 
R9/C2 prior to being applied to Schmitt trigger 
NAND gate IC13. As a result, IC13-8 outputs an 
approximate 8 usee low clockpulse to the sampling 
flip-flops and the preset of IC8. Thus the write 
commands are sampled 15 to 20 usee after the 
leading edges of the tape motion commands, allowing 
the Controller to output tape motion and write 
amplifier commands simultaneously. 

Set Write Status (SWS) true is loaded into the D input 
at IC10-12 from 15 to 20 usee after RNN goes true. 
SWS high true and EBDIS high false are applied to 
AND/OR inverter IC9 at pins 9,10 and 11, producing 
WSEL/ true at IC9-8. OVW will be false during a 
normal write operation. 

Note that WSEL/ is not reset on termination Of a 
motion command; instead it is only sampled at the 
beginning of a motion command. This avoids 
potential glitches from being written while writing 
consecutive blocks, since the write amplifier is not 
being constantly turned on and off during this 
operation. 

Overwrite 

Overwriting or editing is performed by backspacing 
over the block to be rewritten to determine its exact 
length then presenting OVW true and SWS true 
concurrent with the beginning of a run command. 
This sets the Q outputs at ICl 0-9 low false and IC10- 
5 true. Reset flip-flop IC8-9 is also set high true. 
AND/OR inverter 9 is enabled, outputting WSEL/ 
true for the duration of the overwrite operation. 
Note that Erase Bar Disable (EBDIS/) true is output 
to the sensor amplifier from pin 18 during an 
overwrite operation which disables (turns off) the 
upstream erase bar. 

After a block is written in NRZI format, WARS goes 
true at the write amplifier to produce an LRC 
character; then WARS1 true is issued to the 
interface, toggling IC8-9 false to disable Write Select 
and turn off the write current before writing can 
continue into the next data block. 

Rewind and Unload 

The rewind status flip-flop is a SR flip-flop IC7 and 
related circuitry. A Rewind Command (RWC) is 
accepted whenever the tape is not at load point (LP 
false). IC7-8,2 go high, causing RWDG true status 
signal to be output to the interface through driver 
IC5-6. Simultaneously a 5 usee RWC1/ true pulse is 



output from Schmitt trigger NAND gate IC11*11. 
RWC1 is output to the Pushbutton Control PC board 
to set the REWIND flip-flop. The pushbutton control 
card then issues a RWDG1 true level which is applied 
to IC7-10 to keep the rewind status flip-flop set. , 

When the tape rewinds to loadpoint (LP true) and 
capstan motion ceases (TNG/ true), or a broken tape 
is detected (BKN true), the rewind status flip-flop is 
cleared. IC7-11,12 goes high, which is applied to 
AND gate IC6-12. If the unit is selected, online, and 
not busy, IC6 and IC 13 will be enabled to return a 
RDY true status signal to inform the interface that 
the transport is ready for the next data and/or tape 
motion command. ^ 

During an unload operation, the tape is slowly 
rewound off the takeup reel. To accomplish this, 
UNLD/ true is issued from the controller. UNLD/ 
true is inverted high at IC4-12; then gated with SLT 
SLT and ONL, or just . UNLD/ itself. (This is 
determined by the strapping of ST1/ST2: See table ori 
schematic.) The high output at IC6-8 is inverted low 
by IC4, then used to set, unload flip-flop IC8 at pin 4, 
IC8-5 high is gated at IC11 with IC7-11,12 high^ 
which indicates the transport is not rewinding. IC11- 
6 outputs UNLOAD/ true for vacuum column 
9100/9300 transports. Strap ST5 is connected on 
interface PC boards used in 9100/9300 transports to 
output UNLOAD/ true to the Sequence Control PC 
board through pin 7. 

With strap ST3 installed, RVS and RNN/ true signals 
are output to the Pushbutton Control PC board on 
9000/9700 transport through pins V and T. A BKN 
true status signal will clear both the rewind status 
and unload flip-flops, when the tape completely 
unloads. 

Diodes CR3/CR4 at pins 10 and 12 cause UNLD/ true 
from the interface to initiate a rewind operation if 
the tape was not already at load point. The tape 
drive will also be taken offline (OFFC true). RC 
network R21/C7 delays SLT and ONL true signals 4 to 
6 usee to insure correct timing during this 
combination unload-rewind-off line operation. 

EOT Flip-Flop • 

IC14 is the EOT flip-flop which Outputs EOT1 high, 
true status signal to the Pushbutton Control PC board 
whenever the EOT tab has been detected. EOT true 
also is gated with SLT and ONL true at ICl, then 
returned to the interface via pin U as EOT. EOT lbw 
false trailing edge from the Sensbr Amplifier clears 
ICl 4 by clocking the flip-flop if arid only if a reverse 
motion command is initiated. (EOT is delayed by 
R10/C3 for TTL timing considerations.) EOT1 at 
IC14-8 now goes false. Load POint true or Broken 
Tape true, which are applied to preset pin 10, will 
also clear the EOT flip-flop. 

Status Gates 

All status gates on this PC board are preconditioned 
by SLT and ONL being true. The gating of these 
signals is self-explanatory. 



806-9000-100 A 



MODEL 9000 SERIES TAPE MOTION CONTROLS 
CIRCUIT DESCRIPTION 



The circuitry used to carry out the motion commands 
issued by the interface or by the pushbutton panels, 
both the main control panel and the test panel, is 
located on Pushbutton Control Type 3843 module. 
This module generates the motion command lines 
RUN NORMAL RNN1, RUN FAST RNF1, and RE- 
VERSE RVS1, which are supplied to the ramp gener- 
ator module to initiate actual tape motion. 

FRONT PANEL PUSHBUTTON CONTROLS 

The LOAD, ON LINE, and REWIND pushbuttons, 
situated on the main control panel, are connected to 
respective flip-flops on the Pushbutton Control Card 
Type 3843. When the LOAD pushbutton is activated, 
it grounds the input to inverter IC12-1, setting the 
LOAD flip-flop consisting of NOR gate IC13-6 and 
inverter IC12-1. Once the LOAD flip-flop is set 
IC13-6 goes low, is inverted by IC12-4 and removes 
the direct-clear from the ON LINE flip-flop IC10-3. 
Thus the ON LINE flip-flop can be set only after the 
transport has been loaded. When the ON LINE push- 
button is activated the first time, it toggles IC10-1 
to the set, or ON LINE, position, the outputs of the 
flip-flops generating ONL and ONL true. Inverters 
IC12-8 and IC12-10 are connected as a protective 
flip-flop on the clock input to IC10-1. Once the ON 
LINE flip-flop has been set, ONL true is inverted 
twice by IC9 setting the common of the REWIND 
pushbutton on the control panel high, disabling that 
pushbutton. The ON LINE flip-flop can be cleared 
by pressing the front panel pushbutton a second time, 
or by an interface OFF LINE COMMAND OFFC1, 
supplied from the interface control module. 

The REWIND pushbutton can be activated only when 
the transport is off line. When activated the RE- 
WIND pushbutton sets the flip-flop consisting of gates 
IC8-8 andIC8-6, provided that the transport is loaded 
at the time (LOAD true at IC8-13) and test mode is 
not selected (IC7-8 high). Consequently the trans- 
port cannot be rewound by the pushbutton during test 
mode, or when on line, or when LOAD is false. When 
the transport is on line the rewind flip-flop can be 
altern ately set by interface REWIND COMMAND 
RWC1, supplied from the interface control module. 
The ou tput of the rewind flip-flop, REWINDING 
RWDG1, activates NOR gates IC15-8 and IC14-6, 
generating RNF1 and RVS1 true to the ramp gener- 
ator module, initiating a fast reverse motion to load 
point. When load point is detected the photosensor 



amp driver module supplies the load point pulse at 
input pin H of the pushbutton control module, clearing 
the rewind flip-flop. 

An additional flip-flop, IC1-6, is used to locate the 
tape position. Before the tape is loaded, the flip- 
flop is cleared by LOAD false at IC10-8. When the 
transport is loaded the direct- clear is removed and 
NAND gate IC14-11 is enabled. Since the on tape 
flip-flop is still cleared, its Q output high activates 
NAND gate IC14-8, generating a RUN NORMAL RNN1 
at output pin Y, advancing the tape to load point. 
When the load point marker is detected, LP true at 
input pin 21 from the photosensor module is gated 
through IC16-3 and direct-sets flip-flop IC10-7 to 
the ON TAPE state, terminating the tape motion. 
Similarly, whenloadpoint is detected during reverse 
tape motion, the ON TAPE flip-flop is toggled by 
NAND gate IC16-11 to the clear state, initiating for- 
ward tape motion back to load point. 

BUSY 

This module generates a BUSY output when the tape 
is not loaded, when it is advancing to load point, or 
when the transport is off line and not in test mode. 
In any of these cases NOR gate IC4-8 is activated and 
supplies BSY true to the interface control module. 

WRITE READY 

WRITE READY true is generated in two different 
cases: when the interface supplies WRITE SELECT 
true and the transport is not in test mode (TM false) , 
or when the transport is in the write test mode and 
flip-flop IC6-14 is set. In either case NOR gate 
IC1-8 is activated, enabling NAND gate IC4-5. The 
gate is activated provided that BUSY BSY is false, 
FILE PROTECT FPT is false, and the transport is 
not in reverse motion (RVS1 is false). IC4-3 then 
goes low, is inverted by IC5-12 and generates WRDY 
true at output pin J to Write Amplifier Type 3848. 

TEST PANEL CONTROL 

In order to activate the test panel the transport must 
be off line, and the test panel STOP pushbutton must 
be depressed. In that case the TEST MODE push- 
button on the test panel can be activated, setting the 
flip-flop consisting of inverters IC 11- 8 and IC11-10, 
which in turn toggles the test mode flip-flop IC6-6 



806-9000-200A 



to the test mode state, generating TM and TM true. 
The test mode flip-flop is direct- cleared when the 
transport is placed on line, or when the TEST MODE 
pushbutton is activated a second time. After the test 
mode flip-flop has been set the other test panel push- 
buttons are enabled. The WRITE TEST pushbutton 
may then be activated, setting the protective flip-flop 
consisting of inverters IC11-4 and ICll-6, which in 
turn toggles the write test flip-flop IC6-1 to the write 
test mode, provided that forward motion is selected. 
The Q output of the write test flip-flop then activates 
NOR gate I CI- 8, in turn activating the write ready 
gate IC5-3, provided that FILE PROTECT FPT, 
REVERSE RVS1, and BUSY BSY are all false. In 
that case WRITE READY WRDY true is generated at 
output pin J to the write amplifier module, where it 
enables the write data strobe circuitry. During; the 
write test the write amplifiers generate consecutive 
all-1 characters which may be used to adjust the 
skew. 

Additional test panel pushbuttons are FORWARD 
RUN, a normal forward run button, FAST FOR- 
WARD, a high speed forward button, REVERSE and 



FAST REVERSE buttons. The reverse motion but- 
tons can be activated only if the on tape flip-flop 
IC1Q is set and the tape is not at load point, activat- 
ing NAND gate IC3-3, which in turn activates NAND 
gate IC7-6 (when the test mode flip-flop is set) and 
setting the common of the reverse buttons low. 
The forward motion commands are terminated when 
either the STOP pushbutton is activated, clearing the 
test mode flip-flop, or end of tape is detected, in 
which case EOT1 true is inverted by IC17-4; dis- 
abling NAND gate IC7-3, and setting the common of 
both forward motion buttons high. Similarly the re- 
verse motion can be terminated by activating the 
STOP pushbutton, which terminates all test mode 
operations, or when load point is detected, in which 
case LP true is inverted} by IC17-3 and disables 
NAND gates IC3-3 and IC7-6, setting the common of 
the reverse buttons high. The pushbutton control 
module also drives the test panel indicators, lighting 
the data lamp when any data is being processed by 
the write/read electronics, illuminating the skew 
indicator when the skew is out of adjustment, illum- 
inating the EOT indicator when the transport is at 
end of tape, and illuminating the LOAD POINT indi- 
cator when the transport is at the beginning of tape. 



806-4843-100 



TYPE 4843 AUTO POWER RESTART PC BOARD 
CIRCUIT DESCRIPTION 
(OPTIONAL PC BOARD) 



Introduction 

When incorporated in any of the Kennedy Model 9000, 
9100, 9300, 9700, 9800, or 9832 recorders, the type 
4843 Pushbutton Control module allows use of several 
factory optional features. These functions are 
determined by optional straps and the use of 
components in the APR field. Not all functions 
and/or combinations of such are available with every 
9000 series recorder. Refer to schematic 401-4843- 
001 and the dash number of your particular 4843 
module for features that have been incorporated and 
tested at the time your unit was built. Due to the 
interaction of several of these options the user is 
advised to consult the factory in writing if he desires 
to incorporate any additional optional features 
through field modification. Failure to do so invites 
the possibility of voiding the warranty of the 
particular recorder involved. 

The major optional features along with suggested 
usage are outlined below. (Reference is made to 
schematic 401-4843-001.) 

ON TAPE (Of) 

Determined by the placement of option strap 1. If 
this option is specified at the time of factory order, 
the operator cannot place the tape unit on line until a 
reel of tape is loaded and positioned at or past the 
BOt tab. 

ONLINE LOCK (ONLL) 

Determined by the placement of option strap 2. 
When specified at the time of factory order, this 
feature prevents the operator from manually taking 
the tape unit off line via the front panel switch, 
unless the tape controller has allowed him to do so. 
This signal is not normally gated with select and is an 
input signal line on interface connector Jl-A. 



FAST (FST) 

Determined by diode CR2 and a special control 
interface module. When specified at the time of 
factory order, this feature allows interface control of 
high speed forward and high speed reverse motion of 
tape. It is used in conjunction with the Synchronous 
Forward, Synchronous Reverse, and the optional Fast 
line at the control interface connector of the deck. 
High speed forward and reverse commands will be 
accepted when the tape is on line and selected. The 
high speed reverse command will be implemented at 
any time when tape is positioned past the BOT tab 
and the high speed forward command will be carried 
out only when tape is positioned ,at or between the 
BOT and EOT tabs (past EOT, a fast forward 



command Will cause tape to advance at the normal 
synchronous forward speed). Note: This feature 
should be used only for purposes of high speed search, 
as writing cannot be done at high speeds. 

AUTO POWER RESTART (APR) 

Determined by the configuration of components in 
the APR field and external assemblies (in some 
models) driven by this modujle. When specified at the 
time of factory order, this! option will protect the 
tape unit against "brownout" and will automatically 
power up, load, and set the deck on line under certain 
conditions. With the standard APR option this 
circuitry continually monitors the line voltage and 
whether the tape unit is on line or off line. If the 
external line voltage falls below a minimum value 
required by the tape deck, this option will force the 
deck into an off-line state along with issuing a 
BROKEN TAPE command (i.e., the reel and capstan 
servos will be disabled and any write current is 
inhibited). When the input power level returns to an 
acceptable value, the APR circuitry will do one of 
two things, depending on whether the deck was on 
line before the power fell: (1) nothing, if the deck 
was in an off-line state, or (2) load, advance tape 
several inches and place the deck on line if it was 
previously in an on-line state. Additionally, if APR 
circuitry is used in the Model 9832 buffer, it will 
issue an INITIALIZE signal (i.e., clear the buffer 
memory) when power is returned. 

OPTIONAL LOAD ON LINE FEATURE 

A factory variation (to be specified at time of order) 
of the standard APR option is the LOAD ON LINE 
(LOL) feature. If specified, this allows the user, 
through a control interface signal, to load and place 
the tape deck on lihe. The LOL signal is 
acknowledged only after external power has dropped 
and returned to an acceptable level and the deck is in 
an unloaded State. If the LOL feature is used, it is 
the user's responsibility to provide a TTL logic low- 
going pulse (minimal pulse duration 500 milliseconds) 
after power is returned to an acceptable level. The 
LOL signal is not gated with SELECT and appears as 
an input signal on interface connector J1A. 

SUGGESTED USAGE OF APR FEATURE 

The standard APR circuitry is activated only when 
the deck is placed on line and is deactivated when the 
deck is placed off line. (Irt the case of the LOL 
variation, circuitry is activated only when power has 
failed and then returned when the deck is in an 
unloaded state.) Thus, when manually loading a reel 
of tape on the deck, the APR feature is transparent 
to the operator and only comes into play when 



806-4843-200A 



external power has failed with the tape deck in an on- 
line state. The tape deck must be mounted in a 
vertical positon to avoid spilling of tape in the case 
of power failure. Proper positioning of commands 
after the APR circuitry has repowered the deck 
depends on the particular mode of operation and 
should be determined by the application. If a rewind 
was in process at the time of power failure, the tape 
may stop and become repositioned up to 5 feet before 
load point. For proper operation in this case, tape 
should be spaced forward 6 feet and then rewound. 
For any other mode of operation, it is suggested that 
a REWIND command be issued immediately after an 
APR power-up. The LOL signal is not gated with 
SELECT and appears as an input signal on interface 
connector J1A. 

The APR circuitry is designed to operate under 
conditions of power failure external to the tape deck. 
Power failure simulations made "via the front panel 
power switch do not come under the above category 
since this power switch is located between an input 
power RFI filter and the power transformer. 



preregulated +5 vdc and will appear on the scope 
as illustrated below: 

. voltage TP- A 



Ov 



Vmin 

_L_ 



time 



3. Adjust the input power voltage to the machine so 
that the value of V . (as shown above) equals 
the value stated on^chematic 401-4843-001 of 
the APR PC board. 

4. Turn R18 CCW until jthe voltage appearing at 
TP- 13 goes low. 

APR OPERATION IN MODELS 9100/9300 

APR operation in these vacuum column tape 
transports is identical to the above description with 
the following exceptions: 



AUTO POWER RESTART ADJUSTMENT 

Normal field adjustment of the Auto Power Restart 
board is not required unless a new APR board is 
placed in a machine or an existing board has been 
refurbished. If this is the case, the following field 
procedure is recommended: 

1. Power up machine and adjust R18 fully CW. 

2. Monitor TP-A and TP-B with a scope. TP-B is a 
logic level and will be high. TP-A is the 



a) Manual and power failure initiated load 
sequences take approximately twice as long 
due to the increased tape tensioning time 
required to prevent oversized tape loops 
from forming in the vacuum columns during 
a power failure. 

b) The manual and APR load sequences are now 
as follows: Tension Tape; Load Columns, 
Search forward to load point; if load point is 
not found after a given time out period, 
rewind to load point; then place unit online. 



806-3645- 100A 



TYPE 3194/3645 RAMP GENERATOR 
CIRCUIT DESCRIPTION 



The ramp generator produces the proper analog sig- 
nal inputs to the capstan servo system to control the 
direction and velocity of tape motion. The outputs 
are voltages that rise and fall linearly at controlled 
rates to highly stable levels. These analog signals 
are controlled by digital logic outputs from the con- 
trol section. Waveforms produced are shown with 
the schematic. 

Two similar ramp generator circuits are provided: 
one for normal speed operation and one for high speed 
operation. IC4 is an operational amplifier in the 
RUN NORMAL SPEED circuit. The amplifier output 
is normally saturated in the negative direction. When 
its positive input at pin 5 is high, the output saturates 
at +10 volts. This occurs when the RUN NORMAL 
input sets flip-flop IC7. IC4 feeds FETs Ql, Q2 which 
are connected in a constant-current circuit. The 
magnitude of current flow in the circuit is controlled 
by R3 and R4. R3 controls current in the positive- 
going direction, or start ramp, while R4 controls 
the negative-going stop ramp. 

Since CI is charged by a constant current, its volt- 
age rises linearly until clamped by CR1 to a value 
one diode drop below +5 volts. Q3 is an emitter fol- 
lower whose output rises to a value of +5 volts, since 
the emitter can rise one diode drop higher than the 
base. When the input from IC7 to IC4 drops, the 
yoltage fed to Ql, Q2 goes to -10 volts and CI is dis- 
charged linearly until clamped by the base-collector 
diode of Q3. Since Q3 base goes one diode drop 
negative, and the emitter is at zero, a positive-going 
ramp has been generated. 

The ramp voltage output from Q3 is fed to the FET 
switches Q4 and Q5. If forward direction has been 
selected, Q4 is on and Q5 is off. The ramp is then 
amplified by unity gain operational amplifier IC3, 
without inversion, and appears as a positive- going 
ramp at test point A. If reverse is selected, Q5 is 
on and Q4 is off. The ramp is then fed to the invert- 
ing input of IC3 and appears as a negative- going ramp 
at test point A. Forward/reverse selection is con- 
trolled by Slip-flop IC6 and Q9, Q10. 

Ramp amplitude and, therefore, tape speed is con- 
trolled by normal speed control R14 and output sum- 
ming resistor R15. The fast forward and reverse 
ramps are produced by a similar circuit involving 
amplifiers IC1 and IC2. However, since rewind 



speed and ramp time need not be precisely con- 
trolled, resistors are used instead of FETs to charge 
and discharge C4 and produce an approximate 0.5 
sec rise/ fall time. CR9 and CR10 isolate the ramp 
output from any small offsets that may be present 
in IC2. Rewind speed is controlled by summing re- 
sistor R16. Operational amplifier IC5 at zero ramp 
output has a slight bias produced by R37 and R38, 
keeping its output negative. When the ramp rises 
above the bias, IC5 switches to positive output, indi- 
cating that the tape is running. This output is used 
to gate off the input circuits through IC10 and IC9. 
Flip-flops IC7 and ICS may be reset by run normal 
or run fast inputs going false, but cannot beset again 
until the tape comes to a stop. This prevents damage 
from illegal commands and reduces timing require- 
ments. 

Type 3645 Ramp Generator includes an additional 
flip-flop, IC11-8, whose function is to enable con- 
secutive RUN NORMAL commands to be received 
without requiring the tape to ramp down to a stop 
following each normal speed operation. Following a 
RUN FAST command, however, flip-flop IC11 is set 
byIC8, inhibiting any RUN NORMAL commands until 
the tape comes to a stop, at which point IC9-6 clears 
IC11-9, and the 0 output at IC11-8 enables IC7-2. 



ADJUSTMENT PROCEDURE 
Start/ stop time adjustment: 

a. Arrange input signals to the tape transport 
to start and stop machine. Rate must be 
such as to allow full ramp time. 

b. Adjust start ramp (R3) for required time, 
observing with oscilloscope at test point A* 

c. Adjust stop ramp (R4) for required time. 
Time is measured from maximum volts to 
zero volts. 

Speed adjustment: 

a. Using a master skew tape, drive the trans- 
port in a forward direction at normal speed. 

b. Observe data rate at read amplifiers and 
adjust R14 for correct timing. 



806-3844-100C 



TYPE 3844 SENSOR AMPLIFIER DRIVER 
CIRCUIT DESCRIPTION 



This module responds to signals from photoresistive 
cells Which sense load point and end of tape reflective 
strips, and broken tape. In addition, this module 
contains the file protect circuitry, the write and the 
erase head drives. 

BOT, EOT, AND BKN SENSOR AMPLIFIERS 

The load point sensor amplifier and the end of tape 
sensor* amplifier operate interdependently to detect 
the load point and the end of tape markers. The ac- 
tive components in detecting EOT and load point are 
two operational amplifiers, IC6 and IC8, and two 
transistors, Ql and Q2, in conjunction with associ- 
ated components. Transistors Ql and Q2 act as 
current sources; potentiometer R16 is used to adjust 
the transistor base currents to equalize the voltage 
at the inputs of IC8, the load point sensor amplifier, 
and IC6, the end of tape sensor amplifier. Resistors 
R18, R19, R20, and R21 are used to bias the ampli- 
fiers' inputs when plain tape is in front of the photo 
sensors. When either the load point marker or the 
end of tape marker is detected, the resistance of the 
respective photoresistive cell is lowered by approxi- 
mately 60 percent of its unilluminated value. Each 
cell is returned to +10 volts, and a 30 percent change 
in its resistance, causing a 30 percent change in the 
input potential, will be sufficient to switch the output 
of the respective operational amplifier. Resistors 
R17 and R22 serve as feedback loops for noise pro- 
tection. Thus when load point is detected, the load 
point sensor output as input pin Y of this module 
saturates IC8, causing its output to go high, and is 
inverted twice by IC7 to generate LOAD POINT LDP 
true at output pin 19 to the Pushbutton Control mod- 
ule. The output of inverter IC7-8 is also supplied 
to an edge circuit which produces a 1 /isec pulse on 
the trailing edge of LDP. This pulse is output at pin 
8 to the Pushbutton Control module. The EOT sensor 
amplifier* operates in the same manner, generating 
a high output whe^n the EOT marker is detected, and 
supplying EOT true at output pin X to the Pushbutton 
Control and Control Interface modules. 

When the broken tape photoresistive cell is illumi- 
nated the resistance of the cell is reduced enough for 
the +10 volts to turn on transistor Q3. The collector 
of the transistor goes to ground, generating BROKEN 
TAPE BKN true at output pin 18. When LOAD is high 
at input pin U the output of IC4-8 is low. This causes 
the collector of Q3 to be low through diode CR3 and 



the BKN output will be true at output pin 18. Also 
when power is initially turned on capacitor C9 will 
cause the BKN output to be high which presets the 
LOAD flip-flop on the Interface Control module. 

FILE PROTECT CIRCUITS 

The file protect switch output is supplied to this 
module at input pin T. When a reel is loaded without 
a write enable ring, the switch contact remains 
grounded; the switch input at pin T is inverted by 
IC2-6 and enables NAND gate IC4-13. The gate is 
activated when BKN is true before the transport is 
loaded. Whenever the LOAD pushbutton has not been 
energized, IC4-8 low grounds the clear input of flip- 
flop IC4-1 through diode CR14. IC4-2 then issues 
FILE PROTECT FPTtrue at output pin 9 to the Inter- 
face Control card, while the 0 output of IC4 high is 
inverted by IC2-8 to turn off transistor Q5, disabling 
the file protect solenoid output at pin P, 

When a reel with a write enable ring is used, the 
file protect switch is opened, setting input pin T 
high and enabling NAND gate IC2-13. Again the gate 
can be activated only when BKN is high, before the 
transport is loaded. The output of the gate then goes 
low to set flip-' f lop IC4-5; the flip-flop can be set 
only after LOAD has gone false. This provision is 
made to ensure that the write mode can be selected 
only at the time tape is first loaded. Once flip-flop 
IC4 is set, its 1 output issues FPT false, and after 
being inverted by IC1-10 lights the WRITE ENABLE 
LAMP through output pin H. The 0 output of the 
flip-flop low is inverted by IC2-8 and turns on tran- 
sistor Q5, activating the file protect solenoid through 
pin P. The file protect solenoid then draws in the 
switch pin, and the transport is ready for the write 
operation. 

WRITE, ERASE DRIVES 

When the file protect switch is grounded, it also 
turns off transistor Q7, in turn shutting off the cur- 
rent at the base of Q8. This cuts off the write head 
and erase head drive currents supplied by transistor 
Q8. In order for the write and erase drives to be 
turned on, the file protect switch must be opened 
and WRITE READY must be true at input pin 2. 
This will activate NAND gate IC2-3, causing op amp 
IC3 to turn off transistor Q9, in turn enabling tran- 
sistor Q8 to turn on and supply the write and erase 
head drives at pins 22 and J. 



806-3844-200 C 



The zener diode into the base of Q7 detects when remove the head voltage supplied by Q8. This avoids 
power is being dropped. This turns off Q7 early putting unwanted remnants on tape during a power 
enough in the power down sequence to turn on Q9 and failure. 



806-4306-100A 



TYPE 4306 SERVO PREAMPLIFIER 

CIRCUIT DESCRIPTION 
(25 IPS Models and Lower) 



This module contains the capstan servo and reel servo 
amplifier stages. The following paragraphs describe 
their operation. 

CAPSTAN SERVO AMPLIFIER STAGE 

The capstan servo amplifier portion of this module is 
a part of a velocity servo system which produces 
accurately controlled capstan speeds with linear 
ramp-ups and ramp-downs. The analog linear signal 
supplied from the Ramp Generator module is input at 
pin N of this module and is summed with the output 
of the DC tachometer coupled to the capstan motor 
shaft. Tachometer output is supplied at pin P of this 
module. Any difference between the two voltages is 
amplified by operational amplifier IC5. The amplifi- 
cation of IC5 is controlled by two negative feedback 
loops, one supplied directly from the output of IC5 
through resistors R39, R40 and capacitor C9, and the 
other from the capstan motor through resistor R71. 
The zero offset of the amplifier is adjusted by 
potentiometer R56 to eliminate capstan creep during 
standstill as described below. 

The output of amplifier IC5 is supplied to a pair of 
complementary driver stages, including transistors 
Qll, Q12, Q17, and Q18. The output of these stages 
is supplied to a pair of power transistors located on 
the heatsink servo power assembly, at the rear of the 
unit. The power transistors' output then energizes 
the capstan motor, advancing tape at accurately 
controlled speeds. 

REEL SERVO AMPLIFIERS 

Takeup and supply reel servos are provided to 
maintain tape tension at a constant value. Three 
main components are included: magpot position 
sensor, reel servo amplifier, and reel motor. 

The magpot position sensor measures tape tension by 
the position of a spring loaded buffer arm. At the 
approximate center of the arc, sensor output is zero. 
As the buffer arm moves off center, a positive or 
negative voltage is produced which is proportional to 
the error. This error voltage is summed with the 
modified capstan tachometer signal and is amplified 
to energize the respective reel motor, producing 
sufficient torque to return the buffer arm to the 
center of its arc. Only the takeup amplifier stage 
will be described below; the operation of the supply 
amplifier stage is identical. 



The takeup magpot signal is supplied at pin F of this 
module. The magpot corrective voltage is fed 
through R9 and AC coupling C3 and R8 to the 
inverting input of operational amplifier IC1. In order 
to speed up the response of the reel servo in higher 
speed machines, the output of the tachometer 
capstan motor is summed with the magpot corrective 
voltage through summing resistor RIO. The tach- 
ometer signal is modified by the network, which 
includes operational amplifiers IC6 and IC7, to reduce 
the tachometer's effect during high speed operations. 
The response of the reel servos to capstan acceler- 
ation is only critical during ramp-ups to normal 
running speed. During high speed operations, how- 
ever, the ramp times are very long (approximately 0.5 
sec) and the tachometer signal is very large. Con- 
sequently, the signal is modified so that up to 
approximately 40 ips it increases linearly, but at 
speeds exceeding 40 ips it decreases, reducing its 
effect. 

Potentiometer R58 controls the effect of the modi- 
fied tachometer signal 6n takeup reel response. This 
potentiometer is adjusted to reduce the buffer arm 
travel to a minimum, optimizing the reel response to 
both the capstan motion and to the buffer arm 
position. The adjustment is described below. 

The output of the reel servo amplifier on this module 
is supplied to a pair of power transistors located on 
the servo power assembly on the heatsink at the rear 
of the unit. The output of the power transistors 
energizes the respective reel motor, returning the 
buffer arms to their proper locations as described 
above. 

SERVO ADJUSTMENTS 

Capstan Zero Offset 

This adjustment becomes necessary when capstan 
creep is detected during standstill. To adjust follow 
these steps: 

a. Connect an oscilloscope probe to monitor the 
voltage at output pin X, measuring the output of 
the capstan servo amplifier stage. 

b. With the transport ON LINE and loaded but in a 
stopped condition, adjust potentiometer R56 so 
that a straight-line trace is produced. Use the 
0.5v/cm scale on the oscilloscope. 

c. Observe that the capstan does not rotate. 



806-4306-200A 



Buffer Arm Travel 

Potentiometers R57 (supply arm) and R58 (takeup 
arm) are adjusted on this card to minimize the 
respective buffer arm travel, preventing arm bottom- 
ing and overshooting. The adjustment procedure is as 
follows: 

a. Load a full reel of tape on the supply reel. 

b. With the transport off line, press the test panel 
TEST MODE pushbutton. 

c. Press the FORWARD RUN and REVERSE RUN 
pushbuttons alternately, initiating synchronous 
forward and reverse tape motions. (A remote 
tape control unit may be used if the test panel is 
not available.) 



d. Adjust potentiometer R57 on this module until 
the travel of the SUPPLY buffer arm is at 
minimum during the ramp-ups and ramp-downs. 

e. Repeat the above steps for the TAKEUP arm, 
adjusting potentiometer R58. 

f . If a test box or computer diagnostic program is 
available this adjustment can be more easily 
performed doing a write/backspace/write, using 
a very long data block length (16K if available). 
Adjust for minimum arm travel. When adjusting 
supply servo arm response (R57) all the tape 
should be on the supply reel. When adjusting the 
response of the takeupi servo arm at R58, all the 
tape should be on this iakeup reel at EOT. 



806-4606-100 



TYPE 4606 SERVO PREAMPLIFIER 

CIRCUIT DESCRIPTION 
(37.5 IPS Models and Higher) 



This module contains the capstan servo and reel servo 
amplifier stages. The following paragraphs describe 
their operation. 

CAPSTAN SERVO AMPLIFIER STAGE 

The capstan servo amplifier portion of this module is 
a part of a velocity servo system which produces 
accurately controlled capstan speeds with linear 
ramp-ups and ramp-downs. The analog linear signal 
supplied from the Ramp Generator module is input at 
pin N of this module and is summed with the output 
of the DC tachometer coupled to the capstan motor 
shaft. Tachometer output is supplied at pin P of this 
module, Any difference between the two voltages is 
amplified by operational amplifier IC5. The amplifi- 
cation of IC5 is controlled by two negative feedback 
loops, one supplied directly from the output of IC5 
through resistors R39, R40 and capacitor C9, and the 
other from the capstan motor through resistor R71. 
The zero offset of the amplifier is adjusted by 
potentiometer R56 to eliminate capstan creep during 
standstill as described below. ~~ 

The output of amplifier IC5 is supplied to a pair of 
complementary driver stages, including transistors 
Qll, Q12, Q17, and Q18. The output of these stages 
is supplied to a pair of power transistors located on 
the heatsink servo power assembly, at the rear of the 
unit. The power transistors' output then energizes 
the capstan motor, advancing tape at accurately 
controlled speeds. 

REEL SERVO AMPLIFIERS 

Takeup and supply reel servos are provided to 
maintain tape tension at a constant value. Three 
main components are included: magpot position 
sensor, reel servo amplifier, and reel motor. 

The magpot position sensor measures tape tension by 
the position of a spring loaded buffer arm. At the 
approximate center of the arc, sensor output is zero. 
As the buffer arm moves off center, a positive or 
negative voltage is produced which is proportional to 
the error. This error voltage is summed with the 
modified capstan tachometer signal and is amplified 
to energize the respective reel motor, producing 
sufficient torque to return the buffer arm to the 
center of its arc. Only the takeup amplifier stage 
will be described below; the operation of the supply 
amplifier Stage is identical. 



The takeup magpot signal is supplied at pin F of this 
module. The magpot corrective voltage is fed 
through R9 and AC coupling C3 and R8 to the 
inverting input of operational amplifier IC1. In order 
to speed up the response of the reel servo in higher 
speed machines, the output of the tachometer 
capstan motor is summed with the magpot corrective 
voltage through summing resistor RIO. The tach- 
ometer signal is modified by the network, which 
includes operational amplifiers IC6 and IC7, to reduce 
the tachometer's effect during high speed operations. 
The response of the reel servos to capstan acceler- 
ation is only critical during ramp-ups to normal 
running speed. During high speed operations, how- 
ever, the ramp times are very long (approximately 0.5 
sec) and the tachometer signal is very large. Con- 
sequently, the signal is modified so that up to 
approximately 40 ips it increases linearly, but at 
speeds exceeding 40 ips it decreases, reducing its 
effect. 

Potentiometer R58 controls the effect of the modi- 
fied tachometer signal on takeup reel response. This 
potentiometer is adjusted to reduce the buffer arm 
travel to a minimum, optimizing the reel response to 
both the capstan motion and to the buffer arm 
position. The adjustment is described below. 

The output of the reel servo amplifier on this module 
is supplied to a pair of power transistors located on 
the servo power assembly on the heatsink at the rear 
of the unit. The output of the power transistors 
energizes the respective reel motor, returning the 
buffer arms to their proper locations as described 
above. 

SERVO ADJUSTMENTS 

Capstan Zero Offset 

This adjustment becomes necessary when capstan 
creep is detected during standstill. To adjust follow 
these steps: 

a. Connect an oscilloscope probe to monitor the 
voltage at output pin X, measuring the output of 
the capstan servo amplifier stage. 

b. With the transport ON LINE and loaded but in a 
stopped condition, adjust potentiometer R56 so 
that a straight-line trace is produced. Use the 
0.5v/cm scale on the oscilloscope. 

c. Observe that the capstan does not rotate. 



806-4606-200 



Buffer Arm Travel 

Potentiometers R57 (supply arm) and R58 (takeup 
arm) are adjusted on this card to minimize the 
respective buffer arm travel, preventing arm bottom- 
ing and overshooting. The adjustment procedure is as 
follows: 

a. Load a full reel of tape on the supply reel. 

b. With the transport off line, press the test panel 
TEST MODE pushbutton. 

c. Press the FORWARD RUN and REVERSE RUN 
pushbuttons alternately, initiating synchronous 
forward and reverse tape motions. (A remote 
tape control unit may be used if the test panel is 
not available.) 



d. Adjust potentiometer R57 on this module until 
the travel of the SUPPLY buffer arm is at 
minimum during the ramp-ups and ramp-downs. 

e. Repeat the above steps for the TAKEUP arm, 
adjusting potentiometer R58. 

f. If a test box or computer diagnostic program is 
available this adjustment can be more easily 
performed doing a write/backspace/ write, using 
a very long data block length (16K if available). 
Adjust for minimum arm travel. When adjusting 
supply servo arm response (R57) all the tape 
should be on the supply reel. When adjusting the 
response of the takeup servo arm at R58, all the 
tape should be on this takeup reel at EOT. 



TYPE 4210 MAGPOT TENSION ARM POSITION SENSOR 
CIRCUIT DESCRIPTION 



in the reel servo system it is necessary to produce 
an analog signal representing tension arm position. 
The signal must be zero at the nominal resting posi- 
tion of the tension arms and should linearly represent 
angular deviations from the center of arm travel by 
positive and negative voltages. A common method 
utilizes lamps, photocells, and a shutter to produce 
the required voltage* This method suffers from the 
mortality of lamps and the relatively slow response 
of photocells. 

The magpot Operates as a differential transformer, 
an example of which is shown below. 



MOVABLE ARMATURE - 




Magnetic flux produced by current in winding (1) will 
product voltages E 2 and Eg in the other windings. 
If the armature is symmetrically located with re- 
spect to (2) and (3), flux in the two windings will be 
equal, and since they have the same number of turns, 
E 2 = Eg* If the armature is displaced as shown, E 2 

> Eg since the flux coupling Eg has been reduced. 
Displacement in the opposite direction produces Eg 

> E 2 . Displacement from denter then is repre- 
sented by Eq - E 2 ^ Eg. In the configuration shown 
this relation is linear only for very small displace- 
ments because area relations are not linear. 

The magpot is an adaptation of the above scheme in 
that there are three windings on a magnetic core. 
The core in this case is a ferrite pot core while the 
armature is half a pot core. The windings (2) and 
(3) are around legs of the pot core while (1) is around 



the center portion common to the two legs. Winding 
(1) is energized by a high frequency oscillator (ap- 
proximately 200 kHz). The magpot is in balance and 
E 2 = E3 when the armature couples equally to the 
two legs. As the armature is rotated the area avail- 
able for magnetic flux increases linearly for one leg 
and decreases linearly for the other leg. Thus the 
difference in induced voltages is a linear represent 
tation of angular movement. 

The. 200 kHz oscillator is a Hartley circuit com- 
prising Ql, CI, C2, Rl, R2. It produces a 40 volt 
ptp sine wave across the primary winding. 

The two secondary windings are connected in series 
and their voltages are rectified by CR1, CR2. The 
two rectified voltages are subtracted and referenced 
to ground. Thus the input to IC1 operational ampli- 
fier is a dc voltage equal to E 2 - Eg. This voltage 
is null when E^ = Eg and is positive or negative de- 
pending upon which is larger. Secondary voltages 
induced are at all times large enough to overcome 
the diode drops in CR1, CR2. 

DC output of the rectifier circuit is amplified by IC1 
and fed from the output to the appropriate reel servo 
amplifier. 

Voltage output for a given angular deflection depends 
upon coupling between the fixed core and armature 
at that setting. The gain relations are such that a 
spacing of 0.030 inch between core and armature 
results in ± 5v output for full arm travel. Spacing 
is established by two 0. 015 inch thick plastic spacer 
washers on the shaft. 

Adjustment Procedure 

If adjustment should be required: 

1. Remove tape from machine. 

2. Place a short length of tape in front of broken 
tape sensor. 

3. Turn power on, press LOAD. Reels will rotate. 

4. Hold tension arm in approximate center of arc. 
Reel rotation should stop. 

5. If reel continues to rotate lobsen setscrew hold- 
ing the armature to the tension arm shaft. 



806-4210-200 



6. Rotate armature until reel hub motion ceases. 
Press firmly against the fixed core to maintain 
core to armature spacing. 

7. Tighten setscrew. 

8. Move arm to limits of travel and observe direc- 
tions of reel hub rotation. There are two null 



positions 180° apart. The sense of the output 
is reversed for one null causing hub rotation to 
be wrong. If this null has been chosen, loosen 
setscrew, rotate armature 180 , and repeat. 

9. Check output at pin 4 using a voltmeter. Total 
output swing should be between 10 and 12 volts 
( ±5v nominal) . 



806-3631-100 B 



TYPE 3631 READ PREAMPLIFIER 
CIRCUIT DESCRIPTION 



Read Preamplifier Type 3631 includes nine identical 
amplifier Stages which accept the analog signals from 
the read head winding and supply the amplified out- 
puts to the rdad amplifier modules. In seven-track 
recorders the channel 0 and 1 stages are left out. 

The 0 channel amplifier stage is shown in the sche- 
matic; the other channels are identical. The ampli- 
fier stage consists of high gain operational amplifier 
IC1 arid negative feedback including resistors R2, 
R3, R4, It5, and capacitor C2. The input head signal 
is filtered by resistor Rl and capacitor CI, and is 
supplied to the noninverting input of IC1. The negative 



feedback network controls the output amplitude and 
response. 

In NRZ only tape units, potentiometer R4, located 
in the feedback network, is adjusted so that the am- 
plified analog output at test' point A is 9 volts peak to 
peak while writing 800 flux reversals per inch* In 
phase encoded only tape units, potentiometer R4 is 
adjusted for 5 volts peak to s peak output while writing 
3200 flux reversals per inch. In dual density tape 
units, potentiometer R4 is adjusted for 9 volts peak 
to peak output while writing 800 flux reversals per 
inch. 



806-3845-100B 



TYPE 3845 DELAY TIMING MODULE 
CIRCUIT DESCRIPTION 



This module contains the crystal oscillator and divid- 
ing network which produce the synchronous clocks 
used by the read and write electronics. In addition, 
this module includes the read data strobe generation 
network, a read skew delay counter, the gap detect 
network, and the SELECT 2 circuitry. These func- 
tions are discussed in detail below. 

CRYSTAL CONTROLLED OSCILLATOR AND 
DIVIDING NETWORK 

The oscillator consists of crystal Yl used in a feed- 
back loop between two inverter sections of IC5. The 
oscillator output is supplied to a dividing network 
which provides the synchronous clocks used in the 
transport. The dividing network includes divide by 
2 and 8 counter IC2, flip-flops IC1, and divide by 16 
counter IC4. The clocks generated by the network 
are a function of tape speed and a series of switches 
is provided to divide the master oscillator frequency 
according to the tape speed of the particular trans- 
port. The switch positions for the different tape 
speeds are tabulated on the schematic diagram. The 
clocks output by the network are f^, a square wave 
at 32 times the character frequency, and f r , a square 
wave at the character frequency. 

SKEW CHECK COUNTER AND READ DATA 
STROBE GENERATION 

The wire-OR'd peak pulses supplied from the read 
amplifier stages are input at pin R of this module, 
and after being inverted by IC14 are supplied to NAND 
gate IC14-10. At this time the Q output of flip-flop 
IC15-3 is high, enabling IC14-9, and the peak pulses 
are gated through IC14-8 to the direct-clear input of 
flip-flop IC15-13. During each data character the 
pulse of the leading channel direct-clears flip-flop 
IC15-13, setting the Q output high to enable the skew 
counter, divide^by-16 IC16. The counter is clocked 
by fj at 32 times the data frequency. During a test 
mc-de, TEST MODE true at input pin H (from the 
pushbutton control module) direct- sets the skew 
counter to the count of 11. The counter then counts 
froiii 11 to 16, at which point its output toggles 
flip-flop IC15-12, locking itself. The skew tolerance 
is restricted to the period of the count; any peak 
coming in after the skew counter has set flip-flop 
IC15 would cause a skew indication, as explained 
below* Once IC15 flip-flop has been toggled to the 
set state, its ~Q output goes low and toggles flip-flop 



IC12-12. The ~Q output of IC12-2 goes low, is in- 
verted by IC10-12 and supplies DATA TRANSFER 
true to the read amplifier module, shifting the data 
to the output buffer on those modules. The next f^ 
pulse after DATA TRANSFER toggles the second 
IC12 flip-flop to the Set state; the Q output of IC12-6 
goes low, is inverted twice, by two IC10 inverters 
and is output as the READ DATA STROBE RDS at 
output pin A to the interiace.j IC12-61ow also direct- 
clears the first IC12 flip-flop; consequently the next 
fj pulse also toggles the second IC12 flip-flop to the 
cleared state and terminates the data strobe. Should 
the skew tolerance be exceeded and a pulse arrive 
after flip-flop IC15 has been set, the lagging pulse 
will direct- clear IC15-13 again and enable NAND 
gate IC13-12. The gate is activated when IC12-5 
goes high and fires the skew one- shot IC1 1-4, illum- 
inating the skew lamp on the test panel. During a 
normal write mode the skew tolerance is increased, 
as WRITE READY true and TEST MODE false acti- 
vate NAND gate IC 14- 6 and direct-set the skew coun- 
ter to the count of four. This increases the skew 
tolerance from the five counts used during the test 
mode to 12 counts. During the read only mode both 
WRDY and TEST MODE are false, and the skew tol- 
erance count is increased to 16, or half a character 
space. 

GAP DETECT COUNTER 

The gap detect counter consists of two divide-by- 16 
counters in tandem: IC6 and IC7. It is clocked by 
fj at 32 times the data frequency. After each data 
pulse flip-flop IC15- 13 is direct- cleared, its Q output 
goes high and resets the gap counter. After the skew 
delay IC15 is set again and the gap counter is enabled. 
Following the last data character of a record, the 
gap counter is not reset immediately but keeps count- 
ing. When it reaches the count of 32, one character 
time after the last data character of the block, the 
output of IC7 activates NAND gate IC9- 13 . IC9- 11 
goes low and direct-clears flip-flop IC8-13. The Q 
output of the flip-flop in turn direct-sets the gap de- 
tect flip-flop IC15- 10, generating GAP DETECT true 
at output pin H to the interface, provided that the 
transport is selected and on line (SLTl true). The 
Q output of IC8-3 low also activates NOR gate IC9-1, 
keeping the counter enabled and counting while the 
check characters are being read; otherwise the LRC 
and CRC characters will have reset the gap counter, 
signifying end of gap. When the gap counter reaches 



806-3845-200B 



the count of 256 it toggles flip-flop IC8-9, enabling 
NAND gate IC9-10. Thirty-two counts later, equiv- 
alent to the tenth character space of the interrecord 
gap, IC9-8 goes low and toggles flip-flop IC8-12 
to the set state. The Q output of the flip-flop goes 
high and activates NAND gate IC9-4, so that the gap 
counter will clear when the next data character is 
detected (IC15-2 high). 



SELECT 2 GENERATION 

SELECT 2 is used to enable the output data gates on 
the read amplifier modules. SLT2 is generated by 
combining BUSY BSY false, LOAD POINT LP false, 



SELE CT 1 SLT1 true, and RUN NORMAL RNN true. 
Once RNN goes true, initiating synchronous tape 
motion, a delay count consisting of divide -by -16 
counters IC18 and IC19is enabled. The counters are 
advanced by data frequency clock f r . On the count 
of 128 the output of IC19 goes high and activates 
NAND gate IC20 if all the requirements mentioned 
above are met. IC20-8 goes low, is inverted by 
IC20-6, and generates SLT2 true at output pin L to 
the read amplifiers. The purpose of the SLT2 delay 
is to disable the output data gates during the tape 
ramp-up. When IC19-11 goes high IC17-8 goes low 
preventing further clocks to v the counter. The coun- 
ter is reset to the count of zero when RUN NORMAL 
RNN goes high. 



806-4118-100A 



TYPE 4118 DELAY TIMING MODULE 
CIRCUIT DESCRIPTION 



This module contains the crystal oscillator and divid- 
ing network which produce the synchronous clocks 
used by the read and write electronics. In addition, 
this module includes the read data strobe generation 
network, a read skew check counter, the gap detect 
network, and the SELECT 2 circuitry. These func- 
tions are discussed in detail below. 

CRYSTAL CONTROLLED OSCILLATOR AND 
DIVIDING NETWORK 

The oscillator consists of crystal Yl used in a feed- 
back loop between two inverter sections of ICll.The 
oscillator output is supplied to a dividing network 
which provides the synchronous clocks used in the 
transport. The dividing network includes divide 
by 2 and 8 counter IC3, and divide by 16 counter 
IC12. The clocks generated by the network are 
a function of tape speed and a series of switches 
is provided to divide the master oscillator frequency 
according to the tape speed of the particular trans- 
port. The switch positions for the different tape 
speeds are tabulated on the schematic diagram. Jhe 
clocks output by the network are f^, a square wave 
at 32 times the character frequency, and f r , a square 
wave at the character frequency. 

SKEW CHECK COUNTER AND READ DATA 
STROBE GENERATION 

The wire-OR'd peak pulses supplied from the read 
amplifier stages are input at pin R of this module. 
After being inverted by IC15 they are supplied to 
1C15-10* At this time the Q output of flip-flop 
IC16-3 is high, enabling IC15-9, and the peak pulses 
are gated through IC 15- 8 to the direct- clear input of 
flip-flop 1C16-13. During each data character the 
pulse of the leading channel direct-clears flip-flop 
IC16-13, setting the Q output high to enable the skew 
counter, divide-by-16 IC17. The counter is clocked 
by f-j, at 32 times the data frequency. During a test 
mode, TEST MODE true at input pin H (from the 
pushbutton control module) direct- sets skew counter 
IC17 to the count of 11. The counter then counts 
from 11 to 16, at which point its output toggles 
flip-flop IC16-"12, locking itself. The skew tolerance 
is restricted to the period of the count; any peak 
coining in after the skew counter has set flip-flop 
IC16 would cause a skew indication, as explained be- 
low. Once the IC16 flip-flop has been toggled to the 
set state, its ^ output goes low and toggles flip-flop 



IC14-12. The Q output at IC14-2 goes low, is in- 
verted by IC12*-12 and supplies DATA TRANSFER 
true to the read amplifier module, shifting the data 
to the output buffer on those modules. The next f^ 
pulse after DATA TRANSFER toggles the second 
IC14 flip-flop to the set state; the Q output of IC14-6 
goes low, is inverted twice by two IC12 inverters 
and is output as the READ DATA STROBE RDS at 
output pin A to the interface!. IC14-6 low also direct- 
clears the first IC14 flip-fljop; consequently the next 
f j pulse also toggles the second IC14 flip-flop to the 
cleared state and terminates the data strobe. Should 
the skew tolerance be exceeded and a pulse arrive 
after flip-flop IC16 has been set, the lagging 
pulse will direct-clear IC16-13 again. The gate 
is activated when IC14-5 goes high and fires 
the skew one - shot IC11 - 4 , illuminating the 
skew lamp on the test panel. During a normal 
write mode the skew tolerance is increased, 
as WRITE READY true and TEST MODE false acti- 
vate NANDgateIC15-6 and direct-set the skew coun- 
ter to the count of four. This increases the skew 
tolerance from the five counts used during the test 
mode to 12 counts. During the read only mode both 
WRDY and TEST MODE are false, and the skew tol- 
erance count is increased to 16, or half a character 
space. 

GAP DETECT COUNTER 

The gap detect counter consists of two divide-by-16 
counters in tandem: IC 8 and IC9. It is clocked by 
fj at 32 times the data frequency. After each data 
pulse flip-flop IC16-13 is direct - cleared, its Q 
output goes high and resets the gap counter. The skew 
delay IC16 is reset and the gap counter is enabled. 
Following the last data character of a record, the 
gap counter is not reset immediately but keeps count- 
ing. When it reaches the count of 32, one character 
time after the last data character of the block, the 
output of IC9 activates NAND gate IC11-13. 
IC11-11 goes low and direct-clears flip-flop IC 10- 13. 
The Q output of the flip-flop in turn direct-clears the 
gap detect flip-flop IC16-10 , generating GAP DETECT 
true at output pinH to the interface, provided that the 
transport is selected and on line (SLT1 true). The Q 
output of IC10-3 low also activates NOR gate IC18-10, 
keeping the counter enabled and counting while the 
check characters are being read. Otherwise theLRC 
and CRC characters will have reset the gap counter, 
signifying end of gap. When the gap counter reaches 



806-4118-200A 



the count of 256 it toggles flip-flop IC10-9, enabling 
NAND gate IC11-3. Sixty- four counts later, equiv- 
alent to the tenth character space of the interrecord 
gap, IC10-8is activated and toggles flip-flop IC12-12 
to the set state. The Q output of the flip-flop goes 
higli and activates NAND gate IC18-4, clearing the 
gap counter, and keeping it cleared until the first 
character of the next block is read. 



SELECT 2 GENERATION 

SLT2 Delay disables the output data gates during tape 
ramp-up. SELECT 2 is used to enable the output 



data gates on the read amplifier modules. SLT2 is 
generated by combining BUSY BSY false, LOAD 
POINT L P fals e, SELEC T 1 S LT1 true, and RUN 
NORMAL RNN true. Once RNN goes true, initiating 
synchronous tape motion, a delay counter consisting 
of divide-by-16 counter IC20 and IC21 is enabled. 
The counter is advanced by data frequency clock f r . 
On the count of 128 the Q(j output of IC21 goes high 
and activates NAND gate IC22 if all the requirements 
mentioned above are met. IC22-8 goes low, is in- 
verted by IC12-6, and generates SLT2 true at out- 
put pin L to the read amplifiers* The purpose of the 
SLT2 delay is to disable the output data gates during 
the tape ramp-up. 



806-4178- 100 A 



TYPE 4178 QUAD READ AMPLIFIER 
CIRCUIT DESCRIPTION 



Quad Read Amplifier Type 4178 accepts amplified 
head signals from the head preamplifier module and 
supplies decoded and deskewed data outputs to the 
interface. Each module contains four amplifier 
stages, and each recorder contains two of these mod- 
ules. The channel P amplifier stage is located on 
Read Amplifier/ Clipping Control module. The oper- 
ation of the channel A amplifier stage is explained 
in the following paragraphs. The other amplifier 
stages operate identically. 

The amplified analog signal is supplied from the read 
preamplifier at input pin E. The signal is filtered 
through Rl, CI; the negative half waves are routed 
through diode CR1 while the positive half waves are 
routed through CR2. CR1 and CR2 are back biased 
respectively by the negative and positive clipping 
levels, supplied from the Read Amplifier/ Clipping 
Control Module, to eliminate spurious baseline 
pulses. The negative half waves are then differen- 
tiated by C4 and R6 and are input at the inverting 
input of operational amplifier IC1. At the leading 
edge of the negative analog half wave the differen- 
tiated output of C4 and R6 swings negative, crossing 
zero at the peak of the analog signal and then going 
positive until the trailing edge of the analog signal. 
Normally the op amp output is low, since the non- 
inverting input of IClis negatively biased through R7 
and R9. When the leading edge of the differentiated 
signal exceeds the input threshold, the output of the 
amplifier swings positive. The amplifier output re- 
turns to Ov at the zero crossover of the differen- 
tiated signal, corresponding to the peak of the input 
analog signal. A similar transition occurs for the 
positive half wave, since it is input at the noninvert- 
ing input of the amplifier. Consequently the amplifier 
output goes high and returns low for each 1 character, 
with the negative-going transition occurring at the 
analog peak. The output of the amplifier is limited 
by diodes CR3 and CR4 and is inverted by NAND gate 



IC2-3. IC2-3 output is supplied to a filtering network 
consisting of C6, Rll, R12, and CR5, whose output 
is in turn supplied to the Schmitt trigger input of 
one- shot IC3. The output Of IC2-3 is normally high, 
and the voltage at the input of IC3-5is at3.3v. When 
the output of IC1 swings positive, IC2-3 goes low and 
capacitor C6 discharges through R12 with a slow time 
constant, approximately 5; /isec at 25 ips. The volt- 
age is clamped at Ov by diode CR5. When the output 
of IClgoes low again at the peak of the analog input, 
IC2-3 goes high and C6 charges with a much faster 
time constant, approximately 300 nsec. When C6 
charges up to 1.8v, one- shot IC3 triggers, generat- 
ing a 300 nsec pulse. The Q output of the one- shot 
is connected back to IC2-2, disabling the gate and 
preventing the one- shot from being retriggered by 
spurious pulses on the input. 

The positive pulse generated by the Q output of IC3 
is inverted by IC2-11 and is output as PULSE OUT 
at pin V. The pulses of all the amplifier stages are 
wire-OR'd and supplied to the Delay Timing module 
where they are used for read deskewing and read 
data strobe generation. The Q output of one- shot 
IC3 direct- sets flip-flop IC4-4, the data storage 
register. The Q output of IC4-5 sets the D input of 
the output register IC4-12 high. A skew delay time 
is provided for all channels to be read after the leading 
data pulse is detected. DATA TRANSFER (supplied 
from the Delay Timing module) toggles the output 
register flip-flops of all channels simultaneously 
after the allowed skew delay time, outputing the de- 
skewed, decoded data to NAND gate IC2-9 and, on 
its trailing edge, clears the first stage of IC4. The 
gate is enabled by SELECT 2 true, supplied from the 
Delay Timing module at input pin S. IC2-8 supplies 
the output data at pin Z to the interface. The length 
of the skew delay time is varied depending on the 
operation being performed. This is described in the 
Delay Timing module circuit description. 



806-4179-100A 



TYPE 4179 READ AMPLIFIER CLIPPING CONTROL 
CIRCUIT DESCRIPTION 



This module contains the P channel read amplifier 
stages and the read amplifier clipping level control. 
The operation of the P channel amplifier is explained 
in the circuit description of the Quad Read Amplifier 
module, and the read amplifier clipping level control 
is explained below. 

The read amplifier clipping control provides four 
clipping levels to the read amplifier: normal, low, 
high, and Very high. When an error is detected dur- 
ing a read operation the transport may be commanded 
by the tape control unit to backspace over the erro- 
neous block to reread it. The clipping level. is kept 
at a normal level during the first reread. If a second 
reread is commanded, the clipping level is switched 
from normal to a lower clipping level, to compensate 
for a possible partial dropout. If a third reread is 
initiated, the clipping level is switched to a higher 
thah normal level to eliminate possible baseline noise 
spikes. During a read after write operation the nor- 
mal and high clipping levels are combined to supply 
a still higher clipping level which is not used during 
a read operation. The switching of the clipping levels 
is explained in detail below. 

The initial state of the circuitry will be both IC10 
flip-flops set and both IC11 flip-flops clear. This is 
established by BUSY BSY at pin Y true when tape is 
initially loaded or rewound. Since the first command 
from load point is always a run forward command, 
RUN NORMA L RNN at pin H true and REVERSE SE- 
LECT RVSlatpinW false cause IC8-8 to be low clear- 
ing IC9 flip-flop. The IC10 flip-flops remain in the 
set state when clocked by IC9-3 high. The circuitry 
remains in the states just described until a reverse 
command is given to the tape unit. When RNN and 
RVS1 are true IC8-6 goes low direct-clearing the 
IC10 flip-flops which causes IC10-8 to go high re- 
moving the direct-clear from the IC11 counter flip- 
flops. AlsoIC8-6 low setsIC9 flip-flop which makes 
IG9-6 low; IC11-12 toggles causing IC1 1-3 to go high 
putting the counter in the "01" state. The clipping 
level does not change because the IC12, IC13 gating 
described in the next paragraph establishes the same 
clipping level. The circuitry will now remain in this 
state until a forward command is given. The next 
forward command causes IC8-8 to go low clearing 
IC9 flip-flop and toggling IC10-5 high. At this point 
two things could happen: The tape unit will be com- 
manded to go forward to continue reading the next 
data block, or to backspace if the interface decides 



to reread the data block. If the tape unit is commanded 
to go forward to continue reading, then IC8-8 low 
makes IC9-3 high causing IC10-8 to go low which 
direct-clears the IC11 counter to its initial state. 
If instead the tape unit is commanded to go in reverse 
IC11-12 goes low toggling the IC11 counter to its 
next state. This establishes the next clipping level 
in the sequence. The IC10 flip-flops are cleared as 
described above. The ICjjLl counter will continue to 
toggle every time the tape unit is commanded to 
backspace after being commanded to go forward once. 
Two forward commands in succession will reset the 
IC11 counter by setting IC10-8 low, and reading con- 
tinues at the normal clipping level. 

The clipping levels established by the IC11 counter 
through IC12 and IC13 are as follows: (a) 00 and 01 
cause IC13-6and IC13-11 to be low and IC13-3 to be 
high establishing the normal read clipping level; (b) 
10 causes IC13-6 and IC13-3 to be low and IC13-11 
to be high establishing the low clipping level; (c) 11 
causes IC13-3 and IC13-11 to be low and IC13-6 to 
be high establishing the high read clipping level. 

During a read after write operation WRITE READY 
at input pin J is inverted by IC7-12 and disables the 
automatic clipping level control by direct- setting 
IC10 flip-flops, keeping the IC11 counter direct- 
cleared. At the same time WRDY true activates 
NOR gate IC13-4, enabling the higher clipping level, 
while the Q output of IC11-5 low enables the normal 
clipping level. Thus the normal and high clipping 
levels are combined to generate a still higher clip- 
ping level used during read after write only. 

The automatic clipping level control is also disabled 
when the interface supplies AUTO DISABLE true at 
input pin N, or when BUSY BSY is true at input pin 
Y of the module* In either case NOR gate IC7-6 is 
high, and direct- sets the IC10 flip-flops which in 
turn keep the reread counter IC11 cleared. 

Operational amplifier IC6 is connected with negative 
feedback through R26, establishing its gain at a value 
determined by the ratio of the input resistance to 
+10v switched by IC13 to the value of R26 (22K). 

Capacitor C10 acts as an integrator slowing the re- 
sponse of IC6 to a change in input, which avoids 
coupling enough signal through C4 and C5 into IC1 
to cause a spurious output. IC5 is connected as an 



806-4179-200A 



inverter outputingan equal but opposite polarity volt- 
age to that voltage at IC6-10. The negative clipping 
level voltage (TPD) and positive clipping level volt- 
age (TPC) are then applied to each read amplifier 



: through a reteistor dividing network to backbias diodes 
CR1 and CR2. This establishes the amplitude of 
analog: input from the read preamplifier required 
for IC1 to switch and thus detect data. 



806-3848-100A 



TYPE 3848 WRITE AMPLIFIERS 
CIRCUIT DESCRIPTION 



This module generates the internal write data strobe 
and contains the write amplifier stages for four of 
the data channels — channel P through channel 2. 
These are explained in detail below. 

WRITE DATA STROBE GENERATION 

The Write Data Strobe WDS is input from the inter- 
face at pin N and is supplied to an edge circuit con- 
sisting of inverters IC5 and IC6, capacitor C8, and 
NAND gate IC6-8. If Write Ready WRDY and Select 
SLT1 are true at input pins 12 and 13 of IC6, - the gate 
transmits a short pulse on the leading edge of each 
input WDS. The pulse is gated through NOR gate 
IC5-6 and triggers one- shot IC1-1 on its trailing 
edge. The Q output of the one-shot supplies a posi- 
tive 0.5 /usee pulse which is gated through NAND 
gate IC7-3, provided that the transport is not in a 
test mode. The pulse then enables the write NAND 
gates IC11 and IC15, gating the input write data to 
the write amplifier stages. It is also supplied as 
WDS1 to Type 3849 Write Amplifier module. When 
IC1-13 generates the write strobe, its Q output trig- 
gers the second IC1 one-shot, which in turn inhibits 
IC6 for a 3.5 jusec duration, inhibiting any pulses 
during that time. 

If the transport is in test mode, TM true at pin K 
enables NAND gates IC5-2 and IC7-10, 12 while dis- 
abling NAND gate IC7-2. If Write Ready WRDY is 
true, crystal controlled data frequency f r , supplied 
from the Delay Timing module, is gated through 
NAND gate IC5-12 and NOR gate IC5-6 to generate 
the test mode strobes. These are gated through the 
two IC7 NAND gates and direct- clear the write am- 
plifier flip-flops on this module and on the other 
Write Amplifier module, writing the all- 1 characters 
of the test mode. 

WRITE AMPLIFIER STAGES 

The data inputs are supplied from the data terminator 
card at pins R, S, T, and U, are inverted and then 
strobed through NAND gates IC11 and IC15 by the 
write data strobe WDS1, generated at test point B. 
The write channels are then supplied to the amplifier 
stages, each consisting of a divide-by- 16 counter, a 
pair of flip-flops, and a pair of drivers. The am- 
plifier stages are digitally deskewable, where the 
delay of channels 0 through 7 is adjusted to coincide 
with that of the reference channel, channel P, when 
read back. 



The delay of channel Pis permanently set to the count 
of eight, equivalent to a quarter character delay, by 
counter IC8. Whenever the input data is 1, the WDS 
pulse is gated through ICl 1-8 and direct-clears flip- 
flop IC9-13. The "Q output of the flip-flop goes high, 
removing the direct-clear from the IC8 counter. The 
counter is then clocked by f-^ at 32 times the data 
frequency until the count of eight, at which point the 
output of the counter; goes low and toggles IC9 
flip-flop to the set state. \ The "Q output of IC9 then 
goes low, locking the counter and toggling the output 
flip-flop IC9-9. During the next 1 character the same 
process is repeated with the output flip-flop IC9-9 
toggling to the opposite state. When a 0 is input, the 
input NAND gate IC11-8 does not transmit the write 
data strobe, and consequently the write amplifier 
flip-flops are not toggled. The outputs of flip-flop 
IC9-5, 6 are then supplied to a pair of drivers IC10 
which energize the write head, reversing the flux 
for each 1 while remaining unchanged for each 0, as 
required for NRZ1. 

The operation of the amplifier stages of the eight 
other channels is identical to that of channel P, ex- 
cept that their delay is digitally adjustable. Four 
switches are connected to the parallel inputs of the 
skew delay counters of the eight channels, as Shown 
for data channel 0. The skew of each channel can be 
measured and adjusted during the write test mode, 
which writes all l's characters, by observing the 
analog outputs at the Type 3631 Read Preamplifier 
module. 

Trigger channel 1 of a dual trace oscilloscope on the 
P channel so that one peak is easily observed. With 
channel 2 Of the oscilloscope, observe the preampli- 
fier channel that is to be checked or adjusted. Set 
the switches on the write amplifier channel so that 
the peaks of the two observed channels coincide. A 
small amount of jitter will be seen on the channel 
being adjusted due to tape recorder dynamics. Re- 
peat the observations fOr all eight channels leaving 
the P channel as the reference. 

Opening the switches reduces the count while closing 
them increases it. Thus when the switches are all 
opened the counter is direct- set to 16, gating the data 
character to the output without any delay. When the 
switches are all closed the skew counter is set at 0 
and the character will be delayed 16 counts, or a 
quarter of a character time behind channel P. 



806-3848-200A 



WARS 

The Write Amplifier Reset pulse WARS is input at 
pin P from the data terminator card, and is gated 
through NAND gate IC2-3, provided that Select 1 is 
true, to set flip-flop IC2-12. The 1 output of the 
flip-flop goes high, removing the direct-clear from 
shift register IC3. The register is then clocked by 
f r at 32 times the data frequency. On the seventh 



pulse, the Q output of the register goes high and is 
inverted by IC4-8 to issue WARS1, resetting the 
write amplifier flip-flops on this module. WAR SI is 
also output at pin H to Type 3849 Write Amplifier 
where it resets the flip-flops of the other amplifier 
stages. On the eighth pulse to the register the 
output goes high and is inverted by IC4-11,' clearing 
flip-flop IC2 and locking itself until the next WARS 
is issued by the interface. 



401-9700-001B1 



SI 
POME* 
(CONTROL PANEL) 




(6)4dVrtf (5 

NON-INVERT 
INPUT 



3d(7)SdVEE 62(4) 
VERTING INVERTING 



'CURRENT 
"°SENSE 



INPUT 



PIN NUMBERS ADJACENT TO TERMINALS FOR THE METAL AND CERAMIC FLAT PACKAGE. 
PIN NUMIERS IN PARENTHESIS ARE FOR THE CERAMIC DUAL IN-LINE PACKAGE. 



notes: 

1. line voltage selection as shown is 115/220v, 48-soohz 

2. to wire for 100 vac operation: 

hove s2-2 (blk) to j5-4 

S2-3 (VIO) TO S2-4 
S2-5 (WHT) TO J5-2 

3. TO WIRE FOR 230VAC OPERATION: 

CONNECT J5-2 (WHT) TO J5-3 (ORG); 
J5-5 (VIO) UNUSED 



■10V 



♦ 10 V 



♦sv 



Power Supply, 
Model 9700 J 9800 



3288 
DASH NO 


-224F 


- 228F 


-248C 


-260B 


INPUT D.C. 
VOLTAGE +10% 


24VDC 


28VDC 


48VDC 


60VDC 


R15, R16, 
R17, R18 


120 5W 


150 5W 


500 5W 


2.2K 


R4 


OMIT 


OMIT 


2.2K 


2.2K 


CI 


.22 


.22 


.47 


.47 


REFERENCE 


Q7, Q8, 


MJ802 


MJ802 


2N3442 


MJ410 


Q9, Q10 


HJ802 


MJ802 


2N6340 


2N6341 


Fl 


15A 


ISA 


7.5A 


7.5A 


Tl 


156-4561 


156-3909 


156-3626 




R15 


100 3W 


150 3W 


400 10W 


400 10 


5193 DASH NO. 


-002A 


-002A 


-001A 




Rl,>sW 


33 


33 


100 




R2.5W 


500 


500 


3.5K 




R3.5W 


Ltl 


Lrv 


3/\ 





r 



40 1- 3288-003 J 




5193 CURRENT LIMITTER 



D.C. TOP HAT 



3288 DRIVER BOARD 

+v 



R2 

2.2K 



" n T WTABLE J 



iok5 qi f 22K C2 ^ 

+ TABLE C3 _|_ \ 

^ /CK 1. 001T " V /j ( 




CR3 

1N1200A 



SEE 
TABLE 
Q9 



SEE 
TABLE 
Tl 



.5 BLUE 



[6 BROWN 




jjl-2 /g ^SEE YELL 

1 — €jfcr 



'8 RED 



CR4 

1N1200A 



FACTORY SELECT FOR 
OPERATING FREQ AT Jl-1 
- 430Hz 600Hz. 



_, OMITTED WHEN"! 
5 NOT REQ'D 



r; 



RUSSEL AND STOLL 8943R 
POWER CONNECTOR 
FRONT VIEW 




Fl, 3AB 
SEE TABLE 



R15 
SEE 
TABLE 



C5 -U 
.33* 



6<r 
i 

i4- 



2,3<- 



I 



C4 
.33 



CR7 

1N2070 



7" 

J POWER 

t — HI" 

T+ / PM17 
4 V I 4PDT 




1721 - CMCUIT KMRMTIC 



«2»" r 



vcc vc 

(1?)8Q 97(11) 




f IN NUMNERS AOJACENT TO TERMINALS F0« THE METAL ANO CERAMIC FLAT PACKASE. 
fK NUNIERS IN PARENTHESIS ANE FOR THE CERAMIC DUAL IN-LINE PACKAGE. 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



P4 J4 

— ^ 10 >— : * -10V 



■4 +10V 



+5V 



D.C. Power Supply, 
Model 9700/9800, 
Schematic Diagram 



□ 




TYPICAL 

4.7K 

B ^ ' Wr 

4 c i 

+ 5 D ^ 1 



301- 384 1-00 1 0 




R <— [7] 

- <r-{7\ 

" * — H 
« <-[jj 

2 H3 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



Control Terminator, 
Type 384U001C, 
Schematic Diagram 



CONTROL TERMINATOR CARD, 3841 

WARSl (FROM WA1-M) 

ri 



CONTROL INTERFACE 
CONNECTOR J1 

ovw B ^ 



SFC C ^ 



SRC E * 



RHC H * 



SLT J ^ 



sws K 4 



OFFC L ^ 



ONL M < 



RWD6 N <■ 



FPT P ^ 



LP R < 



WEN S ^ 



RDY t 4: 



EOT 



u < 



v <- 




401-3842-001J 



> D +5V 



) W Ti (FROM RAMP 

GENERATOR-Z) 



> v 



> T 



RNN (TO PUSHBUTTON 
C0NTR0L-18) 



^ U FWD (NOT USED) 



RVS (TO PUSHBUTTON 
C0NTR0L-16) 







(FROM PUSHBUTTON 




N 


BSY CONTROL -13) 


> 


f 


WRDY (FROM PUSHBUTTON 






CONTROL- J ) 




F 


SLT1(J0 DATA TERMI NATOR-V ) 




K 


RWDGI (FROM PUSHBUTTON 






CONTROL-L) 




Y 


LP (FROM SENSOR 



AMP/DRIVER- 19) 



^ L RWC1 (TO PUSHBUTTON 
CONTROL-N) 

^ tt OFFC1 (TO PUSHBUTTON 
CONTROL-12) 



^ H WSEL (TO PUSHBUTTON 
C0NTR0L-7) 



^ R ONL (FROM PUSHBUTTON 
CONTROL- 14) 



^ X BKN (FROM SENSOR 

AMP/DRIVER- 18) 



(FROM SENSOR 
7 Z EOT AMP/DRIVER-X) 

v , rr^ (FROM SENSOR 
' J l " M AMP/DRIVER-9) 



EOT1 (TO PUSHBUTTON 
CONTROL-2.2) 



CONTROL TERMINATOR CARD HAS 
TFRMINATORS (T) 220-330 OHM 
AND PULL-UPS (P) 4.7K AS SHOWN 



DASH NO. 


CT1 


ST5 


001H 


NO CUT 


OMIT 


004 


SEE SEPARATE SCHEM. 


005 


SEE SEPARATE SCHEM. 


006A 


CUT | STRAP 



Interface Control, 
Type 3842, 
Schematic Diagram 



CONTROL 
CONTROL INTERFACE TERM 
CONNECTOR J1 3*41 

SFC C<- 



SRC E ^ 



R7 

4.7K 



H SFC 



FAST A ^ 



RWC H<- 



UNLD 



sws K<- 



OVW i<" 



OFFC . L 4* 



C7 
.027 



WARS I 9 <- 



FROM PBC-14 ONL R <- 



08 




o 

I 

I ST2 
QSEE 
TABLE 



-* LP 



HRDY V- 



3a> 



22 

-O- 



CONTROL 
TERM 
3841 



BKN 



8,2 



1U12 



R14 
470 



i 



LS132 



-4 RWC I 



C6 

0.01 



8 
1 

K "c7^ 



< — C CK 

LS112 



I ST3 

1 — o- -< 



■A. UNLOAD 



CR1 
— M— 



SEE TABLE 



CR2 
— M 

1N270 



4 RVS 



FROM PBC-13 BSY N 



FROM PBC-J WRDY S 



- Lii 
13 



-I HRDY 



FROM PBC-L RWDGI K <- 



-* RWDGI 



FROM SA-19 LP Y <- 



FROM SA-X EOT Z ^- 



-.13 
L^LS132 



FROM SA-18 BKN X <" 



-t TOT 



t_pn 



.6 



o Q 
irtCK 8 



CLR 




-4 USEL 



-\ EBOIS 



^ lp 



4.5 



_L2 



FROM RG-C TNG W <- 



TNG 



RVS 
RWDGI 



3 Ml 12, 
_U>J 00 



RIO 
IK 



12,13J^Sjf L 



An 



CLR 



C3 
560 T 



LS132 



■CK n 
ft 



E0T1 



E0T1 



T»«*- 



12,13JI>^ 



R15 
IK 



38 



RNN 




SRC * 



LP V 



i — 

* — 


5 




5 


4 



6 \6 



E0T1 V- 



BSY V- 



6 )n 
SI 



LP V 



FPT V- 



EOTl 



10 



1A 1Y 
IB 

2A 15 

ih 157 

" ~Y 
3A 

3B 3Y 
SEL B 
STROBE 



FAST Y- 



-1 a J* 



R16 
4.7K 



, 2 26 



RVS V 
RWC1 V 



UNLOAD V- 



ST4 

— o 



SEE TABLE 



9 10 



2& 



38 



ST5 

-o — o- 



OFFC V- 
E0T1 V 



FROM SA-9 FPT J 



—I FPT 
+5 



+5V 4,D <- 



GRD 3,C f 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



1 



DASH 


ST1 


ST2 


ST3 


ST4 


REMARKS 


ST5 


CR3 


CR4 


C4 


R3 


R4 


-001F 


OMIT 


OMIT 


OMIT 


STRAP 


STD 


OMIT 


OMIT 


OMIT 


OMIT 


220 


330 


-002B 


OMIT 


OMIT 


OMIT 


OMIT 


NO BACK STAT 


OMIT 


OMIT 


OMIT 


OMIT 


220 


330 


-0038 


OMIT 


STRAP 


STRAP 


OMIT 


UNLOAD FOR 30/9700 


OMIT 


OMIT 


OMIT 


OMIT 


220 


330 


-004B 


OMIT 


STRAP 


OMIT 


OMIT 


UNLOAD FOR 91/9300 


STRAP 


OMIT 


OMIT 


OMIT 


220 


330 


-013F 


OMIT 


STRAP 


OMIT 


OMIT 


UNL.RH, OFFL-9100 


STRAP 


IN270 


TN270 


.001 


220 


330 


-014E 


OMIT 


STRAP 


STRAP 


OMIT 


UNL.RW, 0FFL-9000 


OMIT 


IN270 


IN270 


.001 


220 


330 


-023C 


OMIT 


STRAP 


OMIT 


OMIT 


OFFL-UNL, RM-9100 


STRAP 


STRAP 


IN270 


OMIT 


OMIT 


OMIT 


-024B 


OMIT 


STRAP 


STRAP 


OMIT 


OFFL-UNL, RN-9000 


OMIT 


STRAP 


IN270 


OMIT 


OMIT 


OMIT 



















































USEL V- 



EBDIS V- 



15 

-O- 



20 

-O- 



19 

-O- 



17 

-O- 



R17 
4.7K 
P 



16 

-O- 



14 

-O- 



+5 



21 

-o- 



R18 
4.7K 



-> V RNN TO PBC-18 



+ 5 



.R19 
•4.7K 



+5 



U RNF TO PBC-17 



R20 
470 



T RVS TO PBC-16 



-> L RWC1 TO PBC-N 



7 UNLOAD 



F SLT1 TO DT-V 



401-4842-001F 

CONTROL INTERFACE 
CONNECTOR J1 

^ WRSTAT 



-> M 0FFC1 TO PBC-12 



E EOTl TO PBC-22 



-> H WSEL TO PBC-7 



-> 18 EBDIS TO SA-16 



-> N RWDG 



U EOT 



"> T RDY 



-> R LP 



-> $ WEN 



-> P FPT 



4 M ONL 



V TNG 



Interface Control Type 4842 , 
(General with Edit) 
Schematic Diagram 



401-9800 -003E 




Tape Motion Controls, 
Type 3843. 4129. 
Schematic Diagram 



401-4843-00 1R 



onl 14 4r 



17 <- 



ON LINEy Z. 
SWITCH 1 ~ 



m 2 



ONL m Z_ 
LAW r v 



LOAD y y_ 
SN V ^ 



MN II <- 



U 214" 



E»n224- 



157 1$4- 
6TfTI 124- 

RW SW/ i ^_ 
LAMP L ^ 

B5ET 7 <- 
W( 104- 



m ie<- 

5wTi M<- 

WRDY J 4" 



■4 rnt 



C2 
3. 3 



f-qjj> 5 - TT jf>o— o 




p-o-- T --o- 

[TeE TABLE 

< ^ rr- 



. R4 
• IK 



ST2 

o- — -o- 



MASCLR^- 



Y4V— C 9 



J ST6 



-J Onl SET 



SEE TABLE 



4 4V 

08 f 



0~NT 



LOAD FF 



_$BKN SET 




10j 08 JO Tj ' 



1 \ ITS 




'02 



ON 

TTNE 
IoTk 



OT 



Z 13 £2 



< — JTff 





-1157 



■4 en 



■4ot 



-$RWD61 



CR10 

— M— 

SEE TABLE 



-J HRDV 



— TO DATA SECTION 
TM 1 < 

SKEW F < 




TM START J- 



DATA E <- 
TP/ST 5 4- 



TEST PULSES/SKEW TEST 



-f ONL SET 




D Q 
12 

74 



CR1 
1N270 



UPT 5- 



CR2 
-44- 



SEE TABLE 



RWD61J- 



4 WRDY 



TM START 



IS 



R8 

220 



3 

TM 
LAMP 




TM FF 
4 



1+^ 

1 CLR ' 

TO 



-fTW 



foTT 



R12 

220 



R14 
IK 



6 X6 

00 



-^Y RNNl 



-^Z RNFl 



->X RVS1 



+5 



$ CR3 
1N270 



n • ?U 

is L-m 



+5V 
+5V 



-^3 GRD 
-^C GRD 



3 

X6/16 



R13 

220 



LT 



OT 



13 1 



V 



TEST 
PULSES/ 
SKEW 
TEST 



1 I 



GRD WT NT 
LAMP SW 



STOP EOT Tim DATA TM PO'REN SKEW TffRT +5V SKEW TfilV TMREVEN 



LAMP SW LAMP 



LAMP 



LAMP 



TEST 



TEST CONNECTOR 



APR Pushbutton Control 

Type 4843, 

Schematic Diagram 
Sheet 1 of 2 



r 



401-4843-001R 



X TABLE 



Y TABLE 



• •USED 



STATE 


FUNCTION 


NEXT 
(JUMP) 


JUMP 
CONDITION 


0 


BKN S^T 


1 (0) 


MAS CLR 


1 


BKN SET 


2 (0) 


MAS CLR 


2 




3 




3 




4 




4 




F (7) 


UoT 


5 




6 




6 




7 




7 




8 




8 


LDSET 


9 




9 


LD5ET 


A 




A 


OTSET 


B 




B 


OTSET 


C 




C 


ONLSET 


D 




D 


ONLSET 


E 




E 


ENABLE 


E (0) 


HAS CLR 


F 


ENABLE 


F (0) 


BKN 



Mo 4 



TO SUPPLY 
REEL MOTOR 



M* 5 



TO TAKE UP 
REEL MOTOR 



+24V 



_L3 

•en 



♦ jo VW- 



d0 



150R 
3W 



MODEL 9700/ 
9800 ONLY 



TO A12-A MODEL 9000 ONLY 



DASH NO. 


-OYZ 


-1YZ 


-2YZ 


-3YZ 


-4YZ 


-5YZ 


-6YZ 


-7YZ 


-8YZ 


SPEED(IPS] 




10 


12.5 


15 


18.75 


25 


37.5 


45 


75+ 


R25 


OMIT 


180K 


150K 


100K 


82K 


68K 


47K 


39K 


2.2M 



DASH NO. 


-xoz 


-X1Z 


-X2Z 


-X3Z 


-X4Z 


-X5Z 


-X6Z 


-X7Z 


-X8Z 


FIRST USED ON 


9000 


9100/9300 


9000/9700/9800 


9832 


9700/9800 


9100/9300 


9100/9300 


FUNCTION 


STD 


LOL 


LOL 


AUTO 


LOL 


AUTO 


AUTO RW 


AUTO 


AUTO / OT 


APR CIRCUIT 




















ST3, RELAY Kl 








• 




• 


• 


• 


• 


ST4 






• 


• 


• 


• 


• 




• 


ST5 










• 


• 








ST6 


• 




• 


• 


• 


• 


• 






ST7 




• 












• 


• 


ST8 


• 




• 


• 


• 


• 


• 






ST9 




• 












• 


• 


DIODE CR10 














1N270 
















DASH NO. 


-XY1 


-XY2 


-XY3 


-XY4 


-XY5 


-XY6 


-XY7 


-XY8 




FUNCTION 


STD 


OT 


ONLL 


OT/ONLL 


FAST 


OT/FAST 


ONLL/FAST 


OT/ONLL/FAST 




ST1 (OT) 




• 




• 




• 




• 




ST2 (ONLL) 






• 


• 






• 


• 




CR2 (FAST) 










1N270 


1N270 


1N270 


1N270 






♦ADJUST R18 SUCH THAT SIGNAL 
AT TEST POINT B GOES LOW 
WHEN VOLTAGE FALLS BELOW 6.25 
±.15V MIN AT TEST POINT A (NOTE 
SCHMITT ACTION OF IC5-3) 
♦♦FACTORY SELECT 



-/A 



r 



APR CIRCUIT (SEE TABLE FOR USE] 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



APR Pushbutton Control, 
Type 4843, 

Schematic Diagram 
Sheet 2 of 2 



401-3645-0010 



DASH NO. 


00 IE 


002E 


010F 


101B 


10 2A 


110A 


SPEED 


18-39 


10-17 


40-49 


LB - 33 


10-17 


40-49 


R3 


2K 


10K 


2K 


2K 


10K 


2K 


R4 


2K 


10K 


2K 


2K ^ 


10K 


2K 


R15 


15K 


27K 


10K 


15K 


27K 


10K 
















CR15, 16 


OMIT 


OMIT 


OMIT 


IN 270 


IN 270 


IN 270 



+ 5V 



R15 

SEE TABLE 




TW5 

TAPE RUNNING 

(TO CI-W) 



-C8 
^£0.001 



^ |_ RAMP OUTPUT 

(TO CAPSTAN 
SERVO PIN NJ 



> A -lov 



> B +iov 



» D +5V 



> C GRD 



Ramp Generator, Type 3645 
Schematic Diagram 



+24 




WRDY 7 4- 
(FROM 
&BC-J) 



SPARE 16 ^ 



% CR2 
1N914 



R25 
100 



'%P\CR12 
/1N751A 
5.1V 



IKl 12 _846 ^ 1 He 0 



BKN 



f i 


l 1 


: 


, CR14 


N 


■ 1N270 


12) 





3,4 



R30 



CR13 

1N2069 



Q5 

148-0094-001 
(SEE NOTES) 



LP 
SENS\ 



EOT 
SENS w 



R17 
1M 
-Wv- 



V 



2N2714 -± C7 
Q2 ^ 



ft.12 
1.5K 



R14 
10K 



R16' 
IK 



1000 



ZERO ADJUST 



< R13 _L 
>1.5K " £ R 15 
>10K 

<b 

Ql : 
2N2714 



-:CR6 
1N914 

;:cr7 

1N914 



C8 -10 
1000 



A 



R21 
10OK 



+ 10 



R18' 
200K! 




R22 
1M 
-Wr 



R20 
200K 



cr9 

1N914 




; r crio 

1N914 



14 



CR11 
1N914 




401-3844-001T 



22 W.HEAO DRIVE 

(TO DATA SECTION) 



WRDY 
(PIN 7) 



J ERASE HEAD DRIVE 
(TO DECK) 



(FROM PBC-13) BSY 13 ^- 



R26 
10 
-VW- 



R2 7 
10 



N WRITE INDICATOR 



K READ INDICATOR 



(TO CONTROL PANEL) 



(FROM CI-F) SLT 1 12 ^- 



Us* 



R28 
10 
■Wv 



V SELECT INDICATOR 



(FROM PBC-V) LOAD U ^~ 

9 FT? A +10 

(TO PBC-K) T 



BKN / 
SENS A 



H 



TO WRITE ENABLE 
INDICATOR 
(TO CONTROL PANEL) 

P FILE PROT. SOL. 
(TO DECK) 



CR14 



RIO 
10K 



■t CR3 

1N270 



,Q3 + 
2N2714 J-C9 



CR5 I 
1N914 



SEE TABLE 
BKN 



-^13 BKN (TO PBC-U) 



8 LP PULSE 
(TO PBC-H) 



19 LP (TO PBC-21) 



-10V A <- 



+10V b 4r 



C <r 



+5V D 



R32 
IK 



R33 
IK 



V 



R34 
IK 



1 



DASH NO. 


C9 


-001U 


10 


-002C 


47 



NOTES: UNLESS OTHERWISE SPECIFIED 
1. EQUIVALENT TRANSISTORS 

148-0094-001 EQUALS MJE4922, MJE2523, SJE5052K, TIP31A 



X EOT (TO INTERFACE BD-Z) 



24V F <- 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



Sensor Amp Driver, 

Type 3844, 
Schematic Diagram 



301-4013-001 01 



(FROM SA-J) ERASE HEAD 
DRIVE 



A7J2 

i 

2 <r 



(FROM SA-P) FILE PROTECT „ , 
SOLENOID » V" 



(TO SA-T) FILE PROTECT g s 
SWITCH (FPT) ^ 



(TO SA-W) BROKEN TAPE 1 <- 
SENSOR 



(TO SA-Y) LOAD POINT 7 4r 
SENSOR i 



(TO SA-Z) END OF TAPE 10 <r 
SENSOR I 



NOT USED 8 ir 



+ iov 4 



+ 24V 12 



GRD 11 > 



R2 
-wv- 



R3 

SEE TABLE 
*vW 



Rl 
22 
VvV- 



r 



♦ 24V 



♦ 10V 



■vW- 
R4 

56 
3W 



A7J5 

I 

-» l > 



BLACK 




ERASE HEAD 
(REF) 



A7J1 

-<4<- 



^ 3> 



">2> 



FILE PROTECT 
SWITCH 



» 1> 



A7J4 

I 

-» l >- 



PR3 
CL904 



\ — ' 



<2<- 



A7J3 

I 

2>- 



PR1 

CL904 



4 1> 



PR2 
CL904 



0 

04 / 



■» 3> 



SENSOR 
LAMPS 



J 



FILE PROTECT 
SOLENOID 



| O RING IN 



3 



RING 
MISSING 



BROKEN TAPE 
SENSOR 



LOAD POINT 
SENSOR 



END OF TAPE 

SENSOR 



DASH NO. 


R2 


R3 


001C 


STRAP 


2. 2K 


002B 


15 ,3W 


2. 2K 


003A 


STRAP 


CMIT 



NOTE 



FOR CIRCUIT CONVENTIONS USED, 
SEE NOTES TO SCHEMATIC SECTION. 



Connector Board, Type 4013 
Schematic Diagram 



- io v A < 



+ 10V B ^ 



TAKE-UP 
190-42 10-001 

MAGPOT • , , 

OR < F 4 

190-4218-001 

MAGPOT 




401-4306-001-H2 



TACHOMETER p ^ 



-24V Y < 



>V Z <- 



DASH NO. 


DESCRIPTION 


C1.C5 


R1.R22 


R8.R30 


-001H 


SCHEMATIC AS SHOWN 


100 


10M 


4700 


-002H 


OMIT OUTLINE CIRCUTRY AS SHOWN 


330 


6. 8M 


100K 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



Servo Preamplifier, 

Type 4306, 
Schematic Diagram 



-lov A 



- 10V 



TAKE-UP 
190-4210-001 
MAGPOT 




NOTES: UNLESS OTHERWISE SPECIFIED 
1. EQUIVALENT TRANSISTORS 

148-0094-001 EQUALS MJE4922, MJE2523, 
SJE5052K, TIP31A. 

148-0095-001 EQUALS MJE2491, SJE5053K, 
TIP32A. 



> E > 




4= 



40 1- 4606-001C1 



J7 



190-4206-001 
9700 MASTER BOARD 




190-4441-001^1 
I REGULATOR AND I 
'SERVO 1 
I ASSEMBLY f 

L -jil _ J 



L_J 



> w > 




ll90-4441-001^V 
REGULATOR AND 
SERVO 1 
ASSEMBLY f 
I -Ji 



J I 




NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



Servo Preamplifier, 
Type4606-001C , 
Schematic Diagram 



30 1- 42 10-00 1 D2 



C8 

SEE TABLE 




k 10 1 <- 

io 2 <- 

•io 5 <- 

■io 6 4- 



GRB 3 ^- 



R3 
22 
-WV- 



C4 
luF 



R4 
22 
-Wv- 



C5 
luF 



1 



UNLESS OTHERWISE SPECIFIED: 

- RESISTOR VALUES ARE IN OHMS ±5% 

- CAPACITOR VALUES ARE IN PICOFARADS ±5% 

- NPN TRANSISTORS ARE 2N2714 

- PNP TRANSISTORS ARE MPS6517 

- DIODES ARE 1N914 

- IC ARE TTL, 7400 SERIES 

-- NUMBER IN LOGIC SYMBOL IS REFERENCE 
DESIGNATOR, UNDERLINED NUMBER IS IC 
TYPE. (IF 7400 SERIES, 74 IS OMITTED) 

-- IC PIN 7 IS CONNECTED TO GROUND 

-- IC PIN 14 IS CONNECTED TO +5V 

-- UNUSED INPUTS OF IC MAY BE TIED TOGETHER 
OR TO + 5V THROUGH RESISTOR (+V) 

- (*) DENOTES FACTORY SELECTED VALUE. 
TYPICAL VALUE IS SHOWN 

- FILTER CAPACITORS ARE NOT SHOWN BUT ARE 
IDENTIFIED BY CF ON PC BOARD 



DASH NO. 


MODELS 


C8 


-001C 


ALL OTHERS 


. 033uF 


-002A 


9800/9801 


.OluF 



Magpot, 
Type 4210 
Schematic Diagram 



301- 3860-00 1C 



W DATA 1 P 



+ 5 0^- 



HI 



V YPICA L R2 

0 



WDS H ^- 



Rl 
330 
-Wv « i 



W DATA 2 R 



HI 



W DATA 7 V 



MI] 



HI 



W DATA 6 W 



I 1 

HI 



W DATA 5 X 



HI 



W DATA 4 Y 



HI 



W DATA P M 



HI 



W DATA 3 2 



HI] 



W DATA 0 N 



HI 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



Data Terminator, 
Type 3860-001B, 
Schematic Diagram 



301-3631-001E3 




<< 



< 



<< 



■< 34 <r 



< 15 £- 



< 32 <r 



< 13 <r 



< 30 4" 



< ^ < ii 4 



< 21 <r 



^ ( 9 4 



< 264- 



v. a v 



-< 24 <- 



~< 5 4- 



< 22 4- 



< 3 4- 



< 20 4- 



< 1 4- 



-10<- 



^04- 



NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



9 IDENTICAL CHANNELS 



CHAN. 1 



-4 > 8 



CHAN. P(C) 



I- 



CHAN. 2(B) 



CHAN. 4(8) 



CHAN. 6(2) 



CHAN. 7(1) 



CHAN . 5(4) 



CHAN. 3(A) 



C7 
.047 



C9 
.047 



C6 
.047 



_L C5 
-7>4.7 



T 



C8 
047 



10 



yTO READ 
AMPLIFIERS 



-4 — » ii 



-4 > 12 



-4 > 13 



-4 > 14 



15 



3 -io 



> 2 + io 



-±-C4 X/GRO 



DASH NO. 


-001D 


-002E 


-004E 


-005E 


-006E 


-003A 


SPEED 


9 TRACK 


Z0-30IPS 


30-401PS 


15-20IPS 


10- 15 IPS 


75IPS 




7 TRACK 


15-20IPS 


20-30IPS 


10- 151 PS 






30-40 


R3 


150K 


UOK 


220K 


300K 


6BK 


82 K 


CI 


470PF 


330PF 


680PF 


1000PF 


68PF 


270PF 



Read Preamplifier, 

Type 3631, 
Schematic Diagram 



DELAY TIMING CARD 
TYPE 3845 



401-970O-O02 »1 



TEST 
PULSES 

(TO PBC-5) 



TEST MODE 
(FROM PBC-1) 



(FROM PBC-J) 



(FROM PBC-13) 



ANALOG SIGNALS 
FROM PREAMP 




OASH NO. 


-001A 


-002A 


-004A 


-005A 


SWITCH POSITION 


1 


2 


3 


4 


5 


6 


7 


SPEED 
IPS 


7 -..00 




30.00 




• 






• 








37. 50 


45.00 


15.00 


18. 75 


• 




• 






• 




2 5.03 




10.00 






• 






• 






12. 50 




5.00 






• 








• 


• 


Yl 


3. 84MHz 


4.608MHz 


1. 336MHI 


1.92MHz 





NOTE: FOR CIRCUIT CONVENTIONS USED, 

SEE NOTES TO SCHEMATIC SECTION. 



9 Track Read Control Logic, 
Schematic Diagram 



SEE Va8L£ 



TEST 
PULSES 



TEST 
MODE 



SKEW 
LAMP 



DATA 
LAMP 



SjLT 1 
BTJST 

LP 



DELAY TIMING P.C. BOARD 
TYPE 4118 
(POSITION N0.7) 



ANALOG SIGNALS FROM 

PREAMPLIFIER > 

B A " 8 4 2 1"] 



401-9700-005A2 



-T--T-f 

-io +io X 




f POSITIVE 
< CLIPPING LEVEL 

J NEGATIVE 
\ CLIPPING LEVEL 



7 Track Read Control Logic, 
Schematic Diagram 



•INDICATES CLOSED POSITION OF SWITCH 

» 2. DASH -103 TO USE SAME SWITCHING ARRANGEMENT AS -003. 



-CLIP R < 
(FROM P CHAN- ft) 



ANALOG p 4- 
INPUT C ^ 
(FROM READ PREAMP) 



+CLIP P ^ 
(FROM P CHAN-P) 



ANALOG c Z. 

INPUT ~ N 



ANALOG H 4- 
INPUT ^ 



ANALOG J C 
INPUT N 



+5.0 <: 




GRD C 4r 
♦10 " B <- 
-10 A 



V 



r 



DASH NO. 


-004C 


-005C 


-001B 


-002B 


-0038 


FIRST USED 


9000 


9000 


9000 


9000 


9000 


SPEED IPS 


10- 14.99 


15-19.99 


20-29.99 


30- 39. 99 


40-49. 99 


CI 


3900 


3000 


2200 


1500 


1000 


C4.C5 


1000 


680 


470 


3 30 


270 


C6 


.022 


.015 


.01 


6800 


4700 



> s 



> v 



> z 



> T 



> U 



40 1- 4 1 78- 001D 



SLT2 

(FROM DT-L) 



PEAK PULSE 
(TO DT-R) 



DATA OUT 

(TO INTERFACE CONN J3) 



RESET 

(FROM DT-Kj 



DATA TRANSFER 
( FROM DT-M) 



> Y 



DATA OUT 



^ X DATA OUT 



^ W DATA OUT 



Quad Read Amp, 
Type 4178, 
Schematic Diagram 



40 1- 4 1 79- 00 i E 



SLT? S ^~ 
( FROM DT-L) 



ANALOG e Z 
INPUT c ~ 

(FROM PRE AMP 
P CHAN) 




V 



PR 
D Q 
4 


5 


12 


0 Q 






4 


IS. 

>CK 
CLR 




11 


74 

>CK 

CLR 



R15 
2.2K 



13 k 

2 Xll 
12ji 38 



;rh 

►2.2K 



;R22 
•IK 



I 



► R21 

'IK 



A V PEAK PULSE 
(TO DT- R) 



A Z DATA OUT 
(TO J3-1) 



A J RESET 

(FROM DT-K) 



U DATA TRANSFER 
(FROM DT-M) 



GRD 

1 



T 



A D +5 



C GRD 



B 



A A -io 




Read Amp/ Clipping Level Control, 
Type 4179, 
Schematic Diagram 



DATA . 
TERMINATOR 
CARD 



WRITE AMPS CARD 



401- 3848-001 J 



WDS N <: 




DATA TERMINATOR CARD HAS .rwR 
TERMINATORS (T) 22Q-330 OHM & 



Write Amps, 
Type 3848, 
Schematic Diagram 



WRITE AMPS CARD 



401-3849-00 )C 



DATA 
TERMINATOR 
CARD 



DATA 3 V ^ — O 



WARS 1 



DATA 4 W <■ 



DATA 5 X 



DATA 6 Y ^ 



DATA 7 Z ^ 




DATA TERMINATOR CARD HAS 
TERMINATORS (T) 220-330 OHM 



GRD O 



Write Amps, 
Type 3849-001C, 
Schematic Diagram 



SECTION VII 
GENERAL INFORMATION AND APPENDIX 



706-9000-1-00 



DIGITAL RECORDING ON MAGNETIC TAPE USING NRZ1 CONVENTIONS AND FORMAT 



1.1 INTRODUCTION 

There are many recording techniques that may be 
employed to record digital information onto magnetic 
tape. Some of these are: non-return- to-zero (NRZ), 
return- to- zero, phase- encoded, Manchester coding, 
and NRZ1. Of these methods the NRZ1, non-return- 
to-zero change at logic 1, has been most widely ac- 
cepted for recording parallel data onto multitrack 
recorders. This method has been used by IBM and 
other computer manufacturers for many years, and 
packing densities, formats, and mechanical dimen- 
sions have been fairly well standardized by usage 
throughout the industry. 

1.1.1 IBM COMPATIBLE 

The term IBM compatible, or more specifically IBM 
compatible 2400 series, is found frequently in speci- 
fications of tape units manufactured by companies 
other than IBM. This means that a tape written on a 
machine that is IBM compatible can be successfully 
entered into an IBM computer utilizing the IBM 2400 
series of magnetic tape units. The converse, of 
course, is also true. Tapes written on an IBM 2400 
can be read on IBM compatible tape units equipped 
with the read function. 

This common denominator between systems is im- 
portant, for often it is the only common point between 
computer systems and data acquisition systems. The 
parameters that ensure this compatibility relate to 
track width, number of tracks, position of the tracks 
on the "width of the tape, form of check characters, 
spacing of check characters from data, length of 
interblock gaps, length of file gaps, and the charac- 
ter used to identify a file gap, as well as the mechan- 
ical dimensions of reels and hubs. This note de- 
scribes these factors for the IBM compatible NRZ1 
method of recording. 

1. 1. 2 ADVANTAGES OF NRZ1 RECORDING 
METHOD 

In the NRZ 1 method of recording, current is flowing 
in one direction in the magnetic head at all times it 
is' writing. This factor makes it possible to record 
over old data, erasing the old data as the recording 
is taking place. Head current also flows in a uniform 
direction during the interrecord gap. This is useful 
when it is necessary to rewrite a record or skip a 



bad area of tape found on re-read and allows the head 
current to be turned on again in a known direction 
without causing unwanted spikes. 

Another advantage of the NRZ1 system is that the 
electronics for writing and reading are simpler than 
those required for other recording techniques, such 
as phase encoding. 

A disadvantage of the NRZ1 system is that it is not 
self-clocking and is useful only where multiple track 
recording is employed. A further restriction is that 
in order to derive a clock from the multiple tracks, 
at least one of the tracks must have a one in it for 
each byte or character recorded. This last factor 
is ensured when a parity check is employed and the 
parity is odd. If even parity is used, then of course 
the all- zero character must be declared invalid and 
not used during the block. 



1.2 WRITING NRZ1 TAPES 

To record digital data on magnetic tape, it is neces- 
sary to magnetize the tape discretely to indicate bi- 
nary ones and zeros. In the NRZ1 method, current 
is flowing in the head at all times the magnetic tape 
unit is in the write mode. As long as the head cur- 
rent does not change, the data will be written such 
that it will be interpreted as zeros. When a transi- 
tion occurs between saturation magnetism (plus and 
minus) on the tape, this will be interpreted as a one. 
Figur e 1-1 shows typical waveforms for data recorded 
on tape in the pattern 011010. The data is entered 
together with write clocks as shown, with a write 
clock for each bit recorded. With tape in continuous 
motion, a flux pattern corresponding to the tape mag- 
netization will appear on the tape as shown. 

NRZ1 recording is implemented by driving current 
through the head winding in a direction determined 
by a flip-flop that toggles for each one, gated in by 
coincidence between data and a write clock. 



1.3 READING NRZ1 RECORDINGS 

■«> 

To recover the data written in NRZ1 format, the 
tape is moved at a constant velocity past the gap in 
the head. Refer to Figure 1-2. If the same pattern 
shown above is present on the tape, the head voltage 



A-1 



706-9000-2-00 



0 1 1 0 1 0 



DATA 



WRITE 
CLOCK 



+ SAT 



TAPE 

MAGNETIZATION 
(HEAD CURRENT) 



SAT- 



Figure 1-1 NRZ1 Waveforms - Writing 



DATA 



+ SAT 



TAPE 

MAGNETIZATION 
(HEAD CURRENT) 



SAT 



PLAYBACK 
SIGNAL 



A 



V 



A 



RECTIFIED 
SIGNAL 



JLJV 



A 



Figure 1-2. NRZ1 Waveforms - Reading 

A-2 



will look like the playback signal since the voltage 
induced in the head is the differential of the fluxpat- 
tern on the tape. The characteristic half sine wave 
results from the fact that the gap on the head has a 
finite width. 

The pattern shown is typical of what would be seen 
with 200 bits per inch (bpi) recording. As the re- 
cording density increases, the mechanical dimen- 
sions of the head remain the same, resulting in the 
same waveform but with the individual waves crowded 
close together. This ultimately presents a limit be- 
yond which this type of recording is useful with state- 
of-the-art tapes and magnetic heads. Recording of 
800 bpi seems to be a practical limit and is the maxi- 
mum density utilized in present-day systems. 

The playback signal is then rectified and, as can be 
seen from the figures, a pulse is present for every 
one recorded and the base line remains stationary 
for all zeros recorded. Note, however, that it is not 
practical to derive an accurate clock from the signal 
on the basis of a single-track recording. However, 
since this is a multiple track system and employs a 
parity generator, a data bit will be found on one of 
the multiple tracks for each character written, as- 
suming that an all-zeros character is not employed 
in conjunction with even parity. 

Considering the above factors, a typical read ampli- 
fier consists of an analog amplifier, a rectifier, a 
peak detector, suitable logic to create a clock, and 
an output buffer stage to enable interfacing to the 
customer's unit. 



1. 3. 1 SKEW AND GAP SCATTER 



assure compatibility with other magnetic tape units. 
These adjustments take the following form. 

1.3.1.1 Read Head Alignment 

The read head is adjusted so that its gaps are per- 
pendicular to the direction of tape motion using an 
IBM skewmaster tape. A mechanical adjustment is 
provided consisting of a spring loaded mounting plate 
working against a fine pitch adjusting screw. (On 
incremental and some low density machines this ad- 
justment is either not required or is made by shim- 
ming tape guides. ) 

1. 3.1.2 Read Electronic Deskew Register 

All Kennedy read amplifiers are provided with a de- 
skewing register. This register allows a total skew 
of 50 percent for all reasons including write head gap 
scatter, dynamic read skew, read head misalignment, 
and speed variation in writing or reading. 

1. 3. 1. 3 Write Electronic Deskewing (continuous tape 
units only) 

The mechanical relationship between the read gap and 
the write gap is fixed in any given read after write 
head. Since the read head is adjusted perpendicular 
to tape motion (paragraph 1. 3. 1. 1), the write time 
for each channel may be delayed selectively so that a 
character is written on the tape perpendicular to tape 
motion. In Kennedy continuous tape units a fixed de- 
lay is inserted for one channel and individual delays 
are provided for the remaining channels. This ar- 
rangement allows each channel to be adjusted in exact 
relationship to the fixed channel and allows adjust- 
ment for skew and gap scatter as well. 



Another major factor that limits the design of an 
NRZ1 multiple track system is that heads are not 
perfect because of gap scatter and head mounting to 
decks is not perfect causing skew. Both these fac- 
tors have the same eff ect in that the signals from all 
the tracks do not occur perfectly in 'unison. The 
problem is minimal if the same head and deck are 
used for reading and writing a given tape, but since 
interchangeability of tapes between machines is man- 
datory provisions must be made to cancel out these 
effects. The allowable tolerances in head manufac- 
ture have practical limits and are typically in the 
±50 microinch region for high quality heads. Fixed 
heads without adjustment are practical with 200 bpi 
and 556 bpi recording, but 800 bpi recording requires 
adjustments. 

All Kennedy recorders are equipped with the neces- 
sary deskewing adjustment to enable operation and 



1.4 TAPE FORMATS 

There are other factors that affect compatibility in 
addition to density and recording method: 

a. Tape markers 

b. Gaps 

c. Check characters 

d. Codes 

1.4.1 TAPE MARKERS 

When recording on magnetic tape, care must be taken 
to avoid physical handling and damage to the recorded 
surface. A portion of tape — at least 10 feet — at each 
end is reserved for threading and loading and is not 
used for storing data. To define the recorded area, 
pressure sensitive reflective markers are applied to 
the nonoxide side of the tape as shown in Figure 1-3. 



A-3 



706-9000-4-00 



14 FT(MIN) 



4 FT (MAX)- 



NOTE 



1 EOT I 

. RECORDING 
AREA 



LPG 

0.5 IN. 
(MIN) 



10 FT (MIN ) 



1^- 

I 

I 



FORWARD t 

TAPE MOTION W 

TAPE VIEWED FROM TOP. RECORDING IS DONE 

ON UNDERSIDE OR OXIDE SIDE OF MAGNETIC TAPE. 




0.031 IN. 
(MAX) 



These markers are sensed optically and define the 
recorded area in a standardized manner. 

The BOT marker signal is used internally to define 
the load point or starting of recording. The EOT 
marker signal is not used internally but is available 
to the interface as an end of tape warning signal and 
should be used by the unit interfaced to the magnetic 
units to terminate recording within the next 4 feet of 
tape. 

1.4.2 GAPS 

Tape reading can only take place reliably when tape 
is moving at a known speed across the head. To al- 
low tape to start and stop while the computer manip- 
ulates data, a section of tape with no data is provided 
between records or blocks of data and at the begin- 
ning and end of tape. This section is recorded with 
the head current turned on in the direction defined 
as erased and results in a constant flux in a pre- 
determined direction which is independent of tape 
speed or motion. The direction of current in the 
heads defining the erased condition is also controlled 
to be uniform in all recorders. On readback this 
flux is constant as the tape accelerates and deceler- 
ates. Since a change in flux is required for the read 
head to sense data, no signal occurs and orderly 
starts and stops may be made. 

Mechanical limitations preclude instantaneous starts 
and stops, and a distance of tape must be reserved, 
conditioned by the requirements of the "worst case" 
machines, to use the standards. While high speed 
units (IBM 2400 series) set the length of the gaps, 
Kennedy recorders utilize the full gap length to ad- 
vantage by providing controlled acceleration and de- 
celeration, resulting in minimum stresses to the tape. 



Figure 1-3. Tape Markers 

1.4.2.1 Beginning of Tape Gap 



An erased section of tape is required surrounding 
the BOT marker. This serves as a defined area 
within which data recording or reading can start. To 
comply with IBM specifications this section extends 
a minimum of 1. 7 inches ahead of the trailing edge 
of the BOT marker and extends a minimum of 0. 5 
inch past the trailing edge of the BOT marker. In 
nearly all systems (including IBM) this erased sec- 
tion totals about 3.5 inches (Figure 1-3). 

1.4.2.2 Interrecord Gaps 

Interrecord gaps are areas, without data, placed be- 
tween data blocks or records as shown in Figure 1-4. 
The length of the gap is 0. 75 inch minimum for seven- 
track systems and 0. 60 inch minimum for nine- track 





ONE BLOCK 




I DATA 
{ RECORD 


IRG 




DATA 
RECORD 


IRG 


DATA ( 
RECORD } 



LRCC CRCC 



IRG 



ONE BLOCK 



DATA 
RECORD 



LRCC CRCC 



DATA 
RECORD 



DATA 
RECORD 



DATA 
RECORD 



IRG J| 



Figure 1-4. Interrecord Gaps 



A-4 



706-9000-5-00 



systems. The maximum length is not critical. The 
USA Standard Institute specifies the maximum length 
at 25 feet. 

If records are short it can be seen that a large por- 
tion of the tape is used for interrecordgaps. In many 
cases computers are programmed to handle records 
in batches as shown in Figure 1-4. In this case the 
IRG and check characters are inserted on a block 
basis. 

Figure 1-5 shows the format of the file mark for seven- 
and nine-track tapes. The distinguishing feature of 
the block is the fact that it is a single specific char- 
acter record with a check character. The erased 
gap itself is nearly always used but IBM standards 
state that it is optional. 



1.4.3 CHECK CHARACTERS 



The NRZ1 format provides for both vertical and hor- 
izontal parity checks. In the nine-track system an 
additional check called the cyclic redundancy check 
character is used. Refer to Figures 1-6 and 1-7 for 
the location of the check characters. 



NINE-TRACK NRZ1 FILE MARK 



The check characters define to a very high level of 
confidence that a block that is read is accurate. 

1. 4.3.1 Vertical Parity 

Seven-track andnine- track systems use six and eight 
tracks respectively for recording data. The remain- 
ing track is redundant and carries the parity infor- 
mation. When the data is written on tape, a parity 
generator senses the input data and determines if the 
number of bits in the byte is odd or even. It outputs 
a "1" or a "0" to the redundant track to make the 
count odd if odd parity is selected, or even if even 
parity is selected. 

On readback a similar circuit can be used to count 
the number of bits in each byte and determine if the 
count is odd or even. Depending on which is defined 
as correct, it signals the error line if the count is 
wrong. Thus each byte is checked. However, if an 
even number of bits is dropped the test will not re- 
sult in an error signal, so an additional check called 
longitudinal parity is employed. 

Odd or even parity may be selected on seven- track 
recorders. Nine-track recorders are always odd 
parity. 



SEVEN-TRACK NRZ1 FILE MARK 



I I 

I I 

I I 

I I 



EIGHT BYTE SPACES 



FILE MARK 



CHECK CHARACTER(S) 



/ 



FOUR BYTE SPACES 



BLOCK 



IRG 



EOF GAP 



BLOCK 



IRG 



3.75 IN. 
(NINE-TRACK) 
3.90 IN 
(SEVEN-TRACK) 



TAPE MOTION 



NOTE 



TAPE VIEWED FROM TOP. RECORDING IS DONE 
ON UNDERSIDE OR OXIDE SIDE OF MAGNETIC 
TAPE. ONE OR MORE FILE MARKS MAY OCCUR 
ON ONE REEL OF TAPE. 



Figure 1-5. NRZ1 File Marks 

A-5 



706-9000-6-00 



INTERREC- 
ORD GAP 
n 7 , n +0. 156 
0. 750_o.063 
(NOTE 2) 



III 
III 
III 
III 
III 

III 



REFERENCE EDGE 




LRC 



INITIAL GAP 
0.5 IN. MI N 
(NOTE 2) 



NOTES: 1. TAPE IS SHOWN WITH OXIDE SIDE DOWN. NRZ1 RECORDING. 
BIT PRODUCED BY REVERSAL OF FLUX POLARITY. 

2. TAPE TO BE FULLY SATURATED IN THE ERASED DIRECTION 
IN THE INITIAL GAP AND THE INTERRECORD GAP. ERASURE 
SUCH THAT A NORTH SEEKING END OF COMPASS WILL POINT 
TO START OF TAPE. 

3. LRC (LONGITUDINAL REDUNDANCY CHECK CHARACTER) ODD OR 
EVEN-SPACED FOUR BITS FROM DATA CHARACTER. 

4. PARITY BIT (A VERTICAL PARITY BIT IS WRITTEN FOR 
EACH BYTE). 



Figure 1-6. Data Format - Seven Track 



INTERRECORD - 
GAP 

+ 0. 15 
0.6 -Q.IOIN. 



LAST 
BIT 

FIRST 
BIT 



I I 



in 
in 
in 
in 
in 
in 
in 
in 
in 



ACTUAL SKEW 
WRITE SKEW 

CHARACTER GATE 



REFERENCE EDGE 



RECORD -• 

DATA 
BYTES 



I I 



I I 
I I 

rl I 



III 
III 
III 
III 
III 
III 
III 
III 
III 



LRC CRC 



HI 

rr in 
in 
in 
in 
in 
in 



TAPE MOTION 



PARITY 
(ODD) 
(NOTE 3) 



I LP MARKER I 



INITIAL 
0.5 IN. 



GAP 
MIN 



NOTE: 1. CRC (CYCLIC REDUNDANCY CHECK CHARACTER). PARITY OF CRC CHARACTER IS 
DETERMINED BY THE NUMBER OF DATA CHARACTERS IN RECORD. ODD NUMBER OF 
DATA CHARACTERS-EVEN CRC CHARACTER, ETC. CRC USED ONLY IN IBM SYSTEM 
SYSTEM/360 800BP.I. CRC CHARACTER SPACED FOUR BITS FROM DATA CHARACTERS . 

2. LRC (LONGITUDINAL REDUNDANCY CHARACTER) ALWAYS ODD PARITY. SPACED FOUR 
BITS FROM CRC. 

3. PARITY BIT (A VERTICAL PARITY BIT IS WRITTEN FOR EACH CHARACTER CONTAINING 
AN EVEN NUMBER OF BITS). 



Figure 7-7. Data Format - Nine Track 

A- 6 



lUU-i/vvv > 



1.4.3.2 Longitudinal Parity 

A longitudinal redundancy check character is written 
at the end of each block. It is separated from the 
end of each block as shown in Figure 1-8. This char- 
acter is made up on a per-track basis. The number 
of l's recorded in a given track of a block is counted 
and a "1" is written in the track as the LRCC if the 
count was odd, and, therefore, the number of l's re- 
corded in each track becomes even for any given 
block. On readback this is checked and an error is 
detected if the count is odd in any track. The possi- 
bility of not detecting an erroneous block still exists 
if an even number of bits in a given track of a block 
is dropped. However, when this test is combined 
with the vertical parity test the probability of not de- 
tecting an error is reduced. 

1.4.3.3 Cyclic Redundancy Check Character (CRCC) 

In the nine-track system another check character 
must be written. This character is derived with rela- 
tively complex logic, the result of which, in combi- 
nation with the LRCC and vertical parity information, 
enables a computer to determine in which track a 
dropout occurred. If the dropout occurred in only 
one track in the given block, the computer can then 
nullify that track and generate the information in that 
track from the data in the remaining tracks, which 
includes the parity track. 

This check character follows the last data byte by 
four cell positions, as shown in Figure 1-8. 

1.4.3.4 Codes 

The recorder will accept and read back any code set 
applied (six-bit for seven-track, eight-bit for nine- 
track)* The only restriction is that the 000000 char- 
acter in a seven-track system using even parity must 
not be used. This is a blank position or missing 
character, and most IBM systems will register an 
error condition if it is found in a block. 

Two code sets are shown in Figure 1-9. These are 
the graphic symbols portion of the codes usedbylBM 
for nine-track and seven-track systems. They are 
shown for reference only. Systems may use differ- 
ent code structures when they are programmed for 
them. 

In the seven- track system the 000000 character may 
be converted to the 001010 character by use of the 



"BCD 0 to 10" option which is available for most 
Kennedy recorders. This senses the 000000 charac- 
ter on the data lines in conjunction with a write clock 
and converts it internally to record the IBM character 
for the number 0 (001010). 

1. 4. 4 SUMMARY OF FORMAT 

A summary of the above factors is shown in Figure 
1-6 for seven- track data format and Figure 1-7 for 
nine-track data format. Record blocks and tape 
markers are shown in Figure 1-10. 



1.4.5 REFERENCES 

Additional information may be found in the following 
publications: 

a. IBM 2400- Series Magnetic Tape Units Orig- 
inal Equipment Manufacturers' Information, IBM 
Form 226862-4 

b. USA Standard Recorded Magnetic Tape for 
Information Interchange (800 cpi, NRZ1), United 
States of America Standards Institute, 10 East 40th 
Street, New York 10016 



LRCC 
BYTE 



DATA 
BLOCK 



CRCC 
BYTE 



0.60 



IRG 
+ 0. 15 



0 . 10 



EIGHT BYTE — 1 3 l| 3 
POSITIONS 

LRCC 
BYTE 



NINE-TRACK 
DATA BLOCK 



TAPE MOTION 



(DATA 
.BLOCK 



IRG 

n 7 c n +0.156 
°' 750 -0.063 



FOUR BYTE' 
POSITIONS 



SEVEN-TRACK 
DATA BLOCK 



Figure 1-8. Check Characters 



A-7 



706-9000-8-00 



mi 1 A T T MP 




EXTENDED BINARY CODED DECIMAL 


BINARY CODED DECIMAL 




GRAPHICS 


INTERCHANGE CODE (EBCDIC) 




INTERCHANGE 


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(BCD) 


SEQUENCE 


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1 




4 


4 










0 


1 


0 


0 


0 


0 


0 


1 


0 


0 


59 


5 


5 










0 


1 


0 


1 


0 


0 


0 


1 


0 


1 


60 


6 


6 










0 


1 


1 


0 


0 


0 


0 


1 


1 


0 


61 


7 


7 










0 


1 


1 


1 


0 


0 


0 


1 


1 


1 


62 


8 


8 










1 


0 


0 


0 


0 


0 


1 


0 


0 


0 


63 


9 


9 










I 


0 


0 


1 


0 


0 


1 


0 


0 


1 



Figure 1-9. Typical IBM Codes 

A- 8 



NINE-TRACK NRZ1 TAPE MARK 

TAPE 
TRACKS 




EIGHT 
BIT SPACES 

A NINE-TRACK NRZ1 TAPE MARK IS 
A SPECIAL CONTROL BLOCK THAT 
CONSISTS OF A CHARACTER WITH 
1-BITS IN DATA TRACKS 3, 6, 
AND 7, AND AN IDENTICAL LRC 
CHARACTER EIGHT BIT SPACES FROM 
IT. NO CRC CHARACTER IS WRITTEN 
ALTHOUGH THE TAPE MARK IS PRE- 
CEDED BY APPROXIMATELY 3.75 
INCHES OF ERASED TAPE, THIS GAP 
IS NOT A REQUIREMENT. 



SEVEN-TRACK NRZ1 TAPE MARK 

TAPE 
TRACKS 




FOUR 
BIT SPACES 

A SEVEN-TRACK NRZ1 TAPE MARK 
IS A SPECIAL CONTROL BLOCK 
THAT CONSISTS OF A CHARACTER 
WITH 1-BITS IN A DATA TRACKS 8, 
4, 2, AND 1, AND AN IDENTICAL 
LRC CHARACTER FOUR BIT SPACES 
FROM IT. ALTHOUGH THE TAPE 
MARK IS PRECEDED BY APPROXI- 
MATELY 3.90 INCHES OF ERASED 
TAPE, THIS GAP IS NOT A RE- 
QUIREMENT. 



RECORD PHOTOSENSING WRITE READ 

BLOCK DEVICE GAP GAP 




210-2013 



Figure 1-10. Record Blocks and Tape Marks 

A- 9 



706-9000-11-00 



PHASE ENCODED RECORDING 



Introduction 

For many years, NRZ1 recording has been used in 
most computer tape systems. Density has increased 
from 200 cpi to 556 cpi and 800 cpi in the quest to 
increase data storage capability of tape and to achieve 
higher data rates. 



With higher densities mechanical tolerances become 
more and more critical, however, and 800 cpi is 
probably the practical limit for NRZ1 recording. If 



higher densities were to be achieved, a new record- 
ing method was required. 

Phase encoding was chosen. Its advantages were well 
known from use of similar systems on drums and 
specialized tape drives. In computer use, tape den- 
sity of 1600 cpi was- selected, and a tape format was 
established first by IBM and later adopted by ANSI 
as a proposed American national standard. 

Figure 1 shows graphically the effect of density on 
tape storage capacity as a function of block length. 



50x10° 



CHARACTERS PER REEL 



40xl0 6 



30xl0 6 



20xl0 6 



lOxlO 6 

































































¥ 

s 


w 


















/ * 


* 




















A 




7*— 


20C 


cpi 









10 20 40 80 160 320 640 1280 2560 5120 10240 20480 40960 

BLOCK LENGTH 



Figure 1. Comparison of Packing Density, Phase Encoded and NRZ1 Formats 

'lB-lj 



706-9000-12-00 



Phase Encoded Recording 

Each of the nine tracks on a PE tape is recorded in 
such a manner as to allow recovery of a track clock 
plus the data. This removes the requirement for 
close skew alignment as in NRZ1 recording, since 
clocked data can be assembled in a register to re- 
move the effects of skew. 

Saturation recording is used. Tape is dc erased with 
a polarity such that the rim end of the tape becomes 
a north seeking pole. A one bit is defined as a flux 
reversal to the reference polarity. A zero bit is de- 
fined as a flux reversal toward the opposite polarity. 
A "phase flux reversal" is written at the nominal 
midpoint between successive ones or successive 
zeros to establish proper polarity. 

Figure 2 shows the resulting pattern of reversals on 
tape. It will be seen that the recording results in 
two bit densities being recorded, 1600 flux reversals 
per inch (frpi) and 3200 frpi. Phase shift of these 
two frequency components is of the utmost importance 
for decoding after playback. 

Figure 3 is a logic diagram of a write amplifier that 
generates the required waveforms. 



Tape Format 

For IBM compatibility, tapes must be written in the 
proper format. This includes conventions on gap- 
lengths and special marks on tape. These have been 
chosen to ensure compatibility with nine-track 800 
cpi NRZ1 on the same transport but with different 
electronics. 

PE Format Requirement 

a. Identification burst . A burst of recording 
in track 4 (P channel) only starting a mini- 
mum of 1.7 inches before the load point 
marker and extending past load point, but 
ending at least 0. 5 inch before the first data 
block. Used to identify PE tapes. 

b. Initial gap . A gap of at least 3 inches be- 
tween the load point marker and the begin- 
ning of the first data block. 

c. Preamble . A burst of 40 zero characters 
in each track followed by a character con- 
taining ones in each track. 

d. Data . Nine tracks, channel assignments 
same as 800 cpi. 



10 1 1 0 0 1 0 1 11 

DATA 0T 

INTERNAL 
WRI 
CL0C 



HEAD 
CURRENT 
(FLUX) 
REF. 



"i_n_j is 

L 

« mrLimmiJwiJWLrir 
ijnjLJiru^JiJiJ^ 



READ 
SIGNAL 



PEAK 
DETECTED - 

SIGNAL 
(INVERTED) 

DATA 
TRANSITION 
TIME - 




LnjuiTLnmjir 

JU1XJ1XIUXIUUUUL 



110-0112 1 0 1 1 0 0 1 0 1 1 1 0 0 - — -DATA 

NOTE: IF TAPE IS READ IN REVERSE DIRECTION, ONES AND 
ZEROS ARE INTERCHANGED. POLARITY REVERSAL IS REQUIRED. 



Figure 2. Phase Encoded Waveforms 

!B-2| ' 



~L_n_ 

DATA 



WDS 



J Q 
T 

K Q 



JL 



WCLK 



J Q 
T 

K Q 



TO HEAD 
DRIVER 




\ 



_n_n_ 



EXCLUSIVE 
OR 



Figure 3. Write Amplifier Logic 



e. Postamble. An all ones character followed 
by 40 all zero characters. 

f . Interrecord gap. A gap 0. 6 inch long nomi- 
nal (0. 5 inch minimum, 25 feet maximum) 
erased in the reference direction. 

g. Tape marks. Tape marks are special con- 
trol blocks used to identify portions of the 
tape. As opposed to NRZ1 format which 
has only one tape mark, there are eight 
possible marks in PE format. Tape mark 
blocks may be from 64 to 256 characters 
in length and are recorded in the format 
shown in Table 1. 



Amplified head signal waveforms are shown in Fig- 
ure 4 for a typical data block. Preamble and post- 
amble are easily identified at the beginning and end 
of the block. Purpose of the preamble is to allow 
synchronization with the signal by a phase-locked 
oscillator before data begins. It is written at 3200 
frpi (all zeros). 

Because of tape and head response limitations, the 
high frequency components are of lower amplitude 
than the low frequency components. 

Differentiation of the amplified signal is performed 
in read electronics. Signal is then crossover de- 
tected, and digitized. A new signal envelope detector 
is used to detect "dropouts" in order to precisely 
determine defective parts of tape. Up to three char- 
acters may be lost at the beginning of the block and 
some noise can be seen at the end of the block (after 
the last zero) for up to two characters time. 

Two conditions should be met before signals are 
recognized as valid data: (a) Signals must be present 
in all tracks; (b) a number of zeros (approximately 
25) must be followed by an all ones character pre- 
amble detected). 

Once detected, the preamble combination of all ones 
must be treated as a valid character. All zeros is 
not a valid character unless the single track dropout 
line is active. 

One phase-locked oscillator and associated electron- 
ics is recommended for better tolerance to tape deck 



Reflective Strips 

Load point and end-of-tape reflective strips are 
attached to the tape in the same positions and with 
the sa^ne meaning as in NRZ1 recording. 

Check Characters 

All PE tapes are written with odd vertical parity. 
There are no LRC or CRC characters in the PE sys- 
tem. They are not needed since the location of the 
track in error can be easily detected through the 
coding system. 

Reading Phase Encoded Tapes 

Reading methods for PE tapes differ, naturally, from 
NRZ1 methods. Following is a general discussion 
of means employed to extract recorded information. 
More specific circuit descriptions will be found in 
instruction manuals for Kennedy Company PE units. 



. TRACK CHANNEL 12 3 4 5 6.7*8 

1 5 X - X - X - X - 

2 7 XXXXXXXX 

3 3 - - 

4 P - X X - - X X - 

5 2 XXXXXXXX 

6 1 - - - 

7 0 ---XXXX- 

8 6 XXXXXXXX 

9 4 

- dc erased 110-0113 

x recorded at 320K) frpi 

* most frequently used combination 



Table 1. Tape Mark Combinations 



B-3, 



706-9000-14-00 




1 10-0059 



Figure 4. Read Signal 



speed variation and write data timing. Two detec- 
tors, a one detector and a zero detector, are used 
to develop data. If, in the required time, neither 
detector has an output, a single track dropout is 
signaled and data correction ensues. 

Each read channel has three output lines: one, zero, 
clock. These three lines are fed to a four- stage 



shift register controlled by an up-down counter. 
Upon entering the shift register, the 1 or 0 bit is 
shifted to the right to occupy the last open shift reg- 
ister cell. As data characters are read out, the 
shift register contents are shifted to the right. This 
allows up to four characters of skew. An error is 
posted if the skew register overflows. 

Since single track dropouts are detected on a per bit 
basis and since the track in error is known, the 
character in the SR output stage can be corrected. 
This is done by reconstructing the missing bit by 
placing the remaining bits in a parity generator and 
adjusting the missing bit so that odd parity is achieved. 
If more than one track drops out, a multiple track 
error condition is flagged. In this case correction 
is not possible. 

It can be seen from the preceding discussion that 
some complexity is required in the PE read elec- 
tronics. If possible, it is desirable to share read 
electronics among several tape units as in Kennedy 
System 9000. If a customer wishes to build his own 
PE electronics, licenses are available to use Ken- 
nedy Company designs, thereby saving a considerable 
amount of engineering time. 



B-4 



Warranty 



Kennedy Company products are warranted to be free from defects 
in materials and workmanship for a period of one year. 

Kennedy Company reserves the right to inspect any defective 
parts or material to determine damage and cause of failure. 

This warranty does not apply to any Kennedy equipment that 
has been subject to neglect, misuse, improper installation and main- 
tenance, or accident. 

Liability under warranty is limited to no charge repair of defective 
units when equipment is shipped prepaid to factory or authorized 
service center after authorization from Kennedy Company to make 
such return. 

Kennedy Company is continually striving to provide improved 
performance, value and reliability in their products, and reserves 
the right to make these improvements without being obligated to 
retrofit delivered equipment. 



KENNEDY CO 



KENNEDY CO. 

5^0 WEST WOODBURY ROAD, ALTADENA. CALIFORNIA