Skip to main content

Full text of "intel :: dataBooks :: 1984 Intel Microsystem Components Handbook Volume 1"

See other formats


LITERATURE 



In addition to the product line Handbooks listed below, the INTEL PRODUCT GUIDE (no charge, Order 
No. 210846) provides an overview of Intel's complete product line and customer services. 

Consult the INTEL LITERATURE GUIDE for a complete listing of Intel literature. TO ORDER literature 
in the United States, write or call the Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 
95051, (800) 538-1876, or (800) 672-1833 (California only). TO ORDER literature from international 
locations, contact the nearest Intel sales office or distributor (see listings in the back of most any Intel 
literature). 

1984 HANDBOOKS U.S. PRICE* 

Memory Components Handbook (Order No. 210830) $15.00 

Contains all application notes, article reprints, data sheets, and other design information 
on RAMs, DRAMs, EPROMs, E^PROMs, Bubble Memories. 

Telecommunication Products Handbook (Order No. 230730) 7.50 

Contains all application notes, article reprints, and data sheets for telecommunication 
products. 

Microcontroller Handbook (Order No. 210918) 15.00 

Contains allapplication notes, article reprints, data sheets, and design information for the 
MCS-48, MCS-51 and MCS-96 families. 

Microsystem Components Handbook (Order No. 230843) 20.00 

Contains application notes, article reprints, data sheets, technical papers for micropro- 
cessors and peripherals. (2 Volumes) (Individual User Manuals are also available on the 
8085, 8086, 8088, 186, 286, etc. Consult the Literature Guide for prices and order 
numbers.) 

Military Handbook (Order No. 210461) 10.00 

Contains complete data sheets for all military products. Information on Leadless Chip 
Carriers and on Quality Assurance is also included. 

Development Systems Handbook (Order No. 210940) 10.00 

Contains data sheets on development systems and software, support options, and design 
kits. 

OEM Systems Handbook (Order No. 210941) 15.00 

Contains all data sheets, application notes, and article reprints for OEM boards and 
systems. 

Software Handbook (Order No. 230786) 10.00 

Contains all data sheets, applications notes, and article reprints available directly 
from Intel, as well as 3rd Party software. 



* Prices are for the U.S. only. 



MICROSYSTEM 
COMPONENTS HANDBOOK 

VOLUME 1 



1984 



Intel Corporation makes no warranty for the use of Its products and assumes no responsibility for any errors which may appear in 
this document nor does it make a commitment to update the information contained herein. 



Intel retains the right to make changes to these specifications at any time, without notice. 

s Contact your local sales office to obtain the latest specifications before placing your order. 

The following are trademarks of Intel Corporation and may only be used to identify Intel Products: 

BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS, i, f, ICE, iCS, iDBP, 
iDIS, l 2 ICE, iUBX, i m , iMMX, Insite, Intel, int e l, intelBOS, Intelevision, int e ligent 
Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPDS, iSBC, iSBX, 
iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MUL- 
TIBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT, 
Promware, QUEST, QUEX, Ripplemode, RMX/80, RUPI, Seamless, SOLO, 
SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or 
UPI and a numerical suffix. 

MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data 
Sciences Corporation. K 

* MULTIBUS is a patented Intel bus. 

Additional copies of this manual or other Intel literature may be obtained from: 

Intel Corporation 
Literature Department 
3065 Bowers Avenue 
Santa Clara, CA 95051 



© INTEL CORPORATION, 1983 



Table of Contents 



CHAPTER 1 

OVERVIEW 

Introduction 1-1 

CHAPTER 2 

MCS®-80/85 MICROPROCESSORS 

DATA SHEETS 

8080A/8080A-1/8080A02, 8-Bit N-Channel Microprocessor 2-1 

8085AH/8085 AH-2/8085AH-1 8-Bit HMOS Microprocessors 2-10 

8085A/8085A-2 Single Chip 8-Bit N-Channel Microprocessors 2-26 

8155H/8156H/8155H-2/8156H-2, 2048-Bit Static HMOS RAM 

with I/O Ports and Timer 2-30 

8155/8156/8155-2/8156-2, 2048-Bit Static MOS RAM with I/O Ports and Timer 2-42 

8185/8185-2, 1024 x 8-Bit Static RAM for MCS-85 2-45 

8205 High Speed 1 Oyt of 8 Binary Decoder 2-50 

8212 8-Bit Input/Output Port 2-55 

8216/8226, 4-Bit Parallel Bidirectional Bus Driver 2-63 

8218/8219 Bipolar Microcomputer Bus Controllers for MCS-80 and MCS-85 FamHy . . . 2-68 

8224 Clock Generator and Driver for 8080A CPU 2-79 

8228/8238 System Controller and Bus Driver for 8080A CPU 2-84 

8237A/8237A-4/8237A-5 High Performance Programmable DMA Controller 2-88 

8257/8257-5 Programmable DMA Controller 2-103 

8259A/8259A-2/8259A-8 Programmable Interrupt Controller ; 2-120 

8355/8355-2, 16,384-Bit ROM with I/O 2-138 

8755A/8755A-2, 16,384-Bit EPROM with I/O 2-146 

CHAPTER 3 

IAPX 86, 88, 186, 188 MICROPROCESSORS 

APPLICATION NOTES 

AP-113 Getting Started with the Numeric Data Processor 3-1 

AP-122 Hard Disk Controller Design Using the Intel 8089 3-62 

AP-123 Graphic CRT Design Using the iAPX 86/11 3-123 

AP-143 Using the iAPX 86/20 Numeric Data Processor 

in a Small Business Computer , 3-194 

AP-144 Three Dimensional Graphics Application of the 

iAPX 86/20 Numeric Data Processor 3-217 

AP-186 Introduction to the 80186 3-256 

DATA SHEETS 

iAPX 86/10 16-Bit HMOS Microprocessor 3-334 

iAPX 186 High Integration 16-Bit Microprocessor 3-358 

iAPX 88/10 8-Bit HMO$ Microprocessor 3-412 

iAPX 188 High Integration 8-Bit Microprocessor , 3-439 

8089 8/16-Bit HMOS i/O Processor 3-494 

8087 Numeric Data Coprocessor 3-508 

80130/80130-2 iAPX 86/30, 88/30, 186/30, 188/30 iRMX 86 

Operating System Processors '. 3-529 

80150/80150-2 iAPX 86/50, 88/50, 186/50, 188/50 CP/M*-86 

Operating System Processors 3-551 

8282/8283 Octal Latch . . , 3-562 

82?4A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors , 3-567 

8286/8287 Octal Bus Transceiver 3-575 

8288 Bus Controller for iAPX 86, 88 Processors 3-580 

8289/8289-1 Bus Arbiter 3-587 



CHAPTER 4 

iAPX 286 MICROPROCESSORS 

DATA SHEETS 

iAPX 286/10 High Performance Microprocessor 



with Memory Management and Protection 4-1 

80287 80-Bit HMOS Numeric Processor Extension 4-52 

82284 Clock Generator and Ready Interface for iAPX 286 Processors 4-76 

82288 Bus Controller for iAPX 286 Processors 4-83 



XP/M-86 is a Trademark of Digital Researchjnc. 



CHAPTER 5 

iAPX 432 MICROMAINFRAME™ 

DATASHEETS 

iAPX 43201/43202 Fault Tolerant General Data Processor ; 5-1 

iAPX 43203 Fault Tolerant Interface Processor 5-53 

iAPX 43204/43205 Fault tolerant Bus Interface and Memory Control Units 5-85 

CHAPTER 6 

MEMORY CONTROLLERS 

APPLICATION NOTES 

AP-97A Interfacing Dynamic RAM to iAPX 86/88 Using the 8202A & 8203 6-1 

AP-141 8203/8206/21 64 A Memory Design . 6-37 

AP-167 Interfacing the 8207 Dynamic RAM Controller to the iAPX 186 6-43 

AP-168 Interfacing the 8207 Advanced Dynamic RAM Controller to the iAPX 286 6-48 

ARTICLE REPRINTS 

AR-231 Dynamic RAM Controller Orchestrates Memory Systems 6-55 

TECHNICAL PAPERS 

System Oriented RAM Controller ' 6-62 

NMOS DRAM Controller 6-73 

DATASHEETS 

8202A Dynamic RAM Controller . . 6-77 

8203 64K Dynamic RAM Controller r 6-91 

82C03 CMOS 64K Dynamic RAM Controller 6-106 

8206/8206-2 Error Detection and Correction Unit 6-119 

8207 Advanced Dynamic RAM Controller 6-152 

8208 Dynamic RAM Controller 6-199 

USERS MANUAL 

Introduction 6-218 

Programming the 8207 6-219 

RAM Interface : 6-224 

Microprocessor Interfaces 6-233 

8207 with ECC (8206) : 6-241 

Appendix '. 6-244 

— VOLUME 2 — 

SUPPORT PERIPHERALS 

APPLICATION NOTES 

AP-153 Designing with the 8256 6-248 

DATASHEETS 

8231A Arithmetic Processing Unit 6-321 

8253/8253-5 Programmable Interval Timer 6-331 

8254 Programmable Interval Timer >. . . 6-342 

8255A/8255A-5 Programmable Peripheral Interface 6-358 

8256AH Multifunctional Universal Asynchronous Receiver Transmitter (MUART) 6-379 

8279/8279-5 Programmable Keyboard/Display Interface : 6-402 

82285 Clock Generator and Ready Interface for I/O Coprocessors 6-414 

FLOPPY DISK CONTROLLERS 
APPLICATION NOTES 

AP-116 An Intelligent Data Base System Using the 8272 6-421 

AP-121 Software Design and Implementation of Floppy Disk Systems 6-455 

DATA SHEETS 

8271/8271-6 Programmable Floppy Disk Controller 6-524 

8272A Single/Double Density Floppy Disk Controller 6-553 

HARD DISK CONTROLLERS 

DATASHEETS * 

82062 Winchester Disk Controller 6-572 



UPI USERS MANUAL 

Introduction 6-598 

Functional Description . 6-602 

Instruction Set 6-619 

Single-Step, Programming, and Power-Down Modes 6-646 

System Operation 6-651 

Applications 6-657 

DATA SHEETS 

8041 A/8641 A/8741 A Universal Peripheral Interface 8-Bit Microcomputer 6-777 

8042/8742 Universal Peripheral Interface 8-Bit Microcomputer 6-789 

8243 MCS-48 Input/Output Expander 6-803 

8295 Dot Matrix Printer Controller 6-809 

SYSTEM SUPPORT 

ICE-42 8042 In-Circuit Emulator 6-818 

MCS-48 Diskette-Based Software Support Package 6-826 

iUP-200/iUP-201 Universal PROM Programmers 6-828 

CHAPTER 7 

DATA COMMUNICATIONS 

INTRODUCTION 

Intel Data Communications Family Overview 7-1 

GLOBAL COMMUNICATIONS 
APPLICATION NOTES 

AP-16 Using the 8251 Universal Synchronous/Asynchronous Receiver/Transmitter 7-3 

AP-36 Using the 8273 SDLC/HDLC Protocol Controller 7-33 

AP-134 Asynchronous Communications with the 8274 Multiple Protocol 

f Serial Controller 7-79 

AP-145 Synchronous Communications with the 8274 Multiple Protocol 

Serial Controller 7-116 

DATASHEETS 

8251 A Programmable Communication Interface .' 7-155 

8273/8273-4 Programmable HDLC/SDLC Protocol Controller 7-172 

8274 Multi-Protocol Serial Controller (MPSC) 7-200 

82530/8253-6 Serial Communications Controller (SCC) 7-237 

LOCAL AREA NETWORKS 
ARTICLE REPRINTS 

AR-186 LAN Proposed for Work Stations 7-266 

AR-237 System Level Functions Enhance Controller 7-272 

DATA SHEETS 

82501 Ethernet Serial Interface 7-276 

82586 Local Area -Network Coprocessor 7-287 

OTHER DATA COMMUNICATIONS 
APPLICATION NOTES 

AP-66 Using the 8292 GPIB Controller 7-322 

AP-166 Using the 8291AGPIB Talker/Listener 7-375 

ARTICLE REPRINTS 

AR-208 LSI Transceiver Chips Complete GPIB Interface 7-407 

AR-113 LSI Chips Ease Standard 488 Bus Interfacing 7-414 

TUTORIAL 

Data Encryption Tutorial ' 7-424 

DATA SHEETS 

8291A GPIB Talker/Listener 7-425 

8292 GPIB Controller 7-454 

8293 GPIB Tranceiver 7-469 

8294A Data Encryption Unit 7-481 



CHAPTER 8 

ALPHANUMERIC TERMINAL CONTROLLERS 

APPLICATION NOTES 

AP-62 A Low Cost CRT Terminal Using the 8275 8-1 

ARTICLE REPRINTS 

AR-178 A Low Cost CRT Terminal Does More with Less 8-43 

DATASHEETS 

8275 Programmable CRT Controller 8-50 

-8276 Small System CRT Controller : 8-74 

GRAPHICS DISPLAY PRODUCTS 
ARTICLE REPRINTS 

AR-255 Dedicated VLSI Chip Lightens Graphic Display Design Load 8-91 

AR-298 Graphics Chip Makes Low Cost High Resolution, Color Displays Possible 8-99 

DATA SHEETS 

82720 Graphics Display Controller 8-106 

TEXT PROCESSING PRODUCTS 
ARTICLE REPRINTS 

AR-305 Text Coprocessor Brings Quality to CRT Displays 8-144 

AR-296 Mighty Chips 8-151 

AR-297 VLSI Coprocessor Delivers High Quality Displays 8-156 

DATA SHEETS 

82730 Text Coprocessor : . 8-159 

82731 Video Interface Controller 8-199 

CHAPTER 9 

PACKAGING 9-1 



Overview 



inteT 



INTRODUCTION 

Intel microprocessors and peripherals provide a complete 
solution in increasingly complex application environ- 
ments. Quite often, a single peripheral device will replace 
anywhere from 20 to 100 TTL devices (and the associated 
design time that goes with them). 

Built-in functions and a standard Intel microprocessor/ 
peripheral interface deliver very real time and perfor- 
mance advantages to the designer of microprocessor- 
based systems. 

REDUCED TIME TO MARKET 

When you can purchase an off-the-shelf solution that 
replaces a number of discrete devices, you're also re- 
placing all the design, testing, and debug time that goes 
with them. ' 

INCREASED RELIABILITY 

At Intel, the rate of failure for devices is carefully tracked. 
> Reliability is a tangible goal, and today we're measuring 
field failures in terms of parts per million/ That translates 
to higher reliability for your product, reduced downtime, 
and reduced repair costs. And as more and more func- 
tions are integrated on a single VLSI device, the resulting 
system requires less power, produces less heat, and 
requires fewer mechanical connections— again resulting 
in greater system reliability. 

LOWER PRODUCT COST 

By minimizing design time, increasing reliability, and 



replacing numerous parts, microprocessor and peripheral 
solutions can contribute dramatically to a lower product 
cost. 

HIGHER SYSTEM PERFORMANCE 

Intel microprocessors and peripherals provide the highest 
system performance for the demands of today's (and 
tommorrow's) microprocessor-based applications. For 
example, the iAPX 286 CPU, with its on-chip memory 
management and protection, offers the highest perfor- 
mance for multitasking, multiuser systems. 

HOW TO USE THE GUIDE 

The following application guide illustrates the range of 
microprocessors and peripherals that can be used for the 
applications in the vertical column on the left. The peri- 
pherals are grouped by the I/O function they control: 
CRT, datacommunication, universal (user programma- 
ble), mass storage, dynamic RAM's, and CPU/ bus 
support. 

An "X M in a horizontal application row indicates a poten- 
tial peripheral or CPU, depending upon the features 
desired. For example, a conversational terminal could 
use either of the three display controllers, depending 
upon features like the number of characters per row or 
font capability. A "Y M indicates a likely candidate, for 
example, the 8272A Floppy Disk Controller in a small 
business computer. 1 




1-1 



POTENTIAL CANDIDATE X— TYPICAL CANDIDATE Y 




POTENTIAL CANDIDATE X-TYPICAL CANDIDATE Y (CONTINUED) 



APPLICATION 



TERMINALS 
Conversational 
Graphics CRT 
Editing 



^PROCESSOR 



90 co co 

O 00 GO 

00 T- 1- 



MM 



DISPLAY 



lO CM CO 
f«- 

CM CM CM 

00 00 00 



UPI DISKS DRAM CONTROL SUPPORT 



T 




Intelligent 


X 


X 


Y 


Y 








Videotex 


X 


X 


r*l 


X 






X 


Printing, Laser, Impact 


X 


X 


X 


X 






X 


Portable 


X 


X i 


Y 








X 


INDUSTRIAL AUTO 
















Robotics 






Y 


Y 


k X 






Network 


X 


X 


X 


X 


X 






Num Control 




X 


X 


Xi 


f*; 




Y 


Process Control 


X 


X 


X 


X 


X 




Y 


Instrumentation 


X 


X 


X 


X 






Y 


Aviation/Navig 




X 


"x 


X 


? x 






INDUST/DATA ACQ 
















Laboratory Instr 


X 


: X l 


X 


X 


X 






Source Data 


X 




X 










Auto Test 


X 


X 


m 


X 


Y 






Medical 


X 


X 


X 


X 


X 




Y 


Test Instr 


X 


X 


mi 


X 


f*i 






Security 




X 


X 


X 








COMMERCIAL DATA 
















PROCESSING 
















POS Terminal 
















Financial Transfer 




X 


X 


X 




X 


X 


Automatic Teller 












X 


X 


Document Processing 


X 


X 


X 


X 


X 


X 


X 


WORKSTATIONS 
















Office 


IP 


m 


If 


* 


X 




Y 


Engineering 










X 

v 






CAD 


m 


m 


m% 








MINI MAINFRAME 
















Processor & Control Store 








v 


; 


Y 


M 


Database Subsys 




X 

x 




Y 




X 




I/O Subsystem 


m 




v 


Y 


Y 


111 




Comm. Subsystem 




X 




Y 


Y 







■DaOHHOHQaHDBQBDBHDEiQaiJDDaM 

□oduh 




■□HUB 

HbUHBIbIbH 




MCS®-80/85 
Microprocessors 



Microprocessors 
Section 



\ 



intel 



8080 A/8080 A- 1/8080A-2 
8-BIT N-CHANNEL MICROPROCESSOR 



TTL Drive Capability . 1 6-Bit Stack Pointer and Stack 

2 - ( - 1:1.3 M s, - 2:1.5 ,s) Instruction "2SEl£% fiMSSSJ KJKK 



Cycle 



Switching of the Program Environment 



. Powerful Problem Solving Instruction ■ %^f x £ inaT), > and Double Precision 

. BGeneral Purpose Registers and an ■ {^llty * Provide Priorlty Vectored 
Accumulator inierrupis 

4oo *o a t ai ■ ■ 512 Directly Addressed I/O Ports 

■ 16-Bit Program Counter for Directly , 

Addressing up to 64K Bytes of ■ Available in EXPRESS 

Memory - Standard Temperature Range 

The Intel® 8080A is a complete 8-bit parallel central processing unit (CPU). It*is fabricated on a single LSI chip using 
Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing 
applications. 

The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose registers may be 
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions 
set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation. 

The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out stack to 
store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general purpose registers. The 16-bit 
stack pointer controls the addressing of this external stack. This stack gives the 8080A the ability to easily handle multiple 
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine 
nesting. 

This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bidirectional data 
busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are 
provided directly by the 8080A. Ultimate control of the address and data busses resides with the HOLD signal. It provides 
the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits 
OR-tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation. 

NOTE: 

The 8080A is functionally and electrically compatible with the Intel® 8080. 



[ accumulator! 




EE 



EE 



MACHINE 

CYCLE 
ENCOOING 



TTTTT 

INT HOLD HOLOWAIT I 



STACK POINTER 



PROGRAM COUNTER 





Figure 1. Block Diagram 



Figure 2. Pin Configuration 



2-1 




8080 A/8080 A- 1/8080A-2 



Table 1. Pin Description 



Symbol 


Type 


Name and Function 


A15-A0 


0 


Address Bus: The address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O 
device number for up to 256 input and 256 output devices. A 0 is the least significant address bit. 


D 7 -D 0 


I/O 


Data Bus: The data bus provides bi-directional communication betweeen the CPU, memory, and I/O 
devices for instructions and data transfers. Also, during the first clock cycle of each machine cycle, the 
8080A outputs a status word on the data bus that describes the current machine cycle. D 0 is the least 
signiiicani on. < 


SYNC 


0 


Synchronizing Signal: The SYNC pin provides a signal to indicate the beginning of each machine cycle. 


DBIN 


0 


Data Bus In: The DBIN signal indicates to external circuits that the data bus is in the input mode. This 
signal should be used to enable the gating of data onto the 8080A data bus from memory or I/O- 


READY 


1 


Ready: The READY signal indicates to the 8080A that valid memory or input data is available on the 8080A 
data bus. This signal is used to synchronize the CPU with slower memory or I/O devices. If after sending 
an address out the 8080A does not receive a READY input, the 8080A will enter a WAITstate for as long as 
the READY line is low. READY can also be used to single step the CPU 


WAIT 


0 


Wait: The WAIT signal acknowledges that the CPU is in a WAITstate. 


WR 


0 


Write: The WR signal is used for memory WRITE or I/O output control. The data on the data bus is stable 
while the WR signal is active low (WR = 0). 


HOLD 


1 


Hold: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state allows an external 
device to gain control of the 8080A addres&and data bus as soon as the 8080A has completed its use of 
these busses for the current machine cycle. It is recognized under the following conditions: 

• the CPU is in the HALT state. 

• the CPU is in the T2 or TW state and the READY signal is active. As a result of entering the HOLD state 
the CPU ADDRESS BUS (A-, 5 -A 0 ) and DATA BUS (D 7 -D 0 ) will be in their high impedance state. The CPU 
acknowledges its state with the HOLD ACKNOWLEDGE (HLDA) pin. 


HLDA 


0 


Hold Acknowledge: The HLDA signal appears in response to the HOLD signal and indicates that the data 
and address bus will go to the high impedance state. The HLDA signal begins at: 

• T3 for READ memory or input. 

• The Clock Period following T3 for WRITE memory or OUTPUT operation. 
In either case, the HLDA signal appears after the rising edge of fa. 


INTE 


0 , 


Interrupt Enable: Indicates the content of the internal interrupt enable flip/flop. This flip/flop may be set 
or reset by the Enable and Disable Interrupt instructions and inhibits interrupts from being accepted'by 
the CPU when it is reset. It is automatically reset (disabling further interrupts) at time T1 of the instruction 
Teicn cycie ^iviiy wnen an inierrupi is accepieu aim is aiso re&ei Dy trie ncoci siynai. 


INT 


1 


ln#Arnint Q am toot ■ Tho O D I 1 rap/^nni^ac an intarrnnt camioct r\r\ tKic lir>o sat t h o anH nf t h o 01 1 rront 

interrupt nequest. i ne v/r u recognizes an inierrupi requesi on ims line ai ine enu 01 uie ourreru 
instruction or while halted. If the CPU is in the HOLD state or if the Interrupt Enable flip/flop is reset it will 
not honor the request. 


, — 

RESET 


1 


Reset: While the RESETsignal is activated, the content of the program counter is cleared. After RESET, 
the program will start at location 0 in memory. The INTE and HLDA flip/flops are also reset. Note that the 
flags, accumulator, stack pointer, and registers are not cleared. 


v S s 




Ground: Reference. 


Vdd 




Power: +12 ±5% Volts. 


v C c 




Power: +5 ±5% Vblts 


Vbb 4 




Power: -5 ±5% Volts. 


<Al. <f>2 




Clock Phases: 2 externally supplied clock phases, (non TTL compatible) 



2-2 



AFN-00735C 



8080A/8080A-1/8080A-2 



ABSOLUTE MAXIMUM RATINGS* 

Temperature Under Bias 0°C to +70° C 

Storage Temperature -65°C to +150°C 

All Input or Output Voltages 

, With Respect to V BB -0.3V to +20V 

Vcc» V DD and V S s With Respect to V B b -0.3V to +20V 
Power Dissipation 1.5W 



'NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
d.evice. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this 
specification is not implied. Exposure to absolute maxi- 
mum rating conditions for extended periods may affect 
device reliability. 



D.C. CHARACTERISTICS (T A = o°c to to°c, v dd = +12V ±5%, 

V C C = *5V ±5%, V B B = -5V ±5%, V S s : 



=0V; unless otherwise noted) 



Symbol 


Parameter 


Min. 


Typ. 


Max. 


Unit 


Test Condition 

,) 


VlLC ' 


Clock Input Low Voltage 


Vss-1 




Vss+0.8 


V 




V IHC 


Clock Input High Voltage 


9.0 




V DD +1 


V 




VlL 


Input Low Voltage 


Vss-1 




Vss+0.8 


V 




V,H 


Input High Voltage 


3.3 




V CC +1 


V 




v 0L 


Output Low Voltage 






0.45 


V 


Iql = 1 -9mA on all outputs, 


V 0 H 


Output High Voltage 


3.7 






V , 


"Ioh^-iboma. 


•dd (AV) 


Avg. Power Supply Current (Vqd) 




40 


70 


mA 


Operation 
Tqy = -48 /usee 


'CC (AV) 


Avg. Power Supply Current (Vcc) 




60 


80 


mA 


'bb(av) 


Avg. Power Supply Current (V B b) 




.01 


1 


mA 


IlL 


Input Leakage 






±1Q 


juA 


Vss ^ V|n < Vcc 


»CL 


Clock Leakage 






±10 


.ma 


Vss < VcLOCK ^ V DD 


l DL t2] 


Data Bus Leakage in Input Mode 






-100 
-2.0 , 


ma 

mA 


Vss<V, N <V ss +0.8V 
V ss +0.8V<V| N <Vp C 


«FL 


Address and Data Bus Leakage 
During HOLD 






+ 10 
-100 


MA 


Vaddr/data = v cc 
Vaddr/data * V S s + 0.45V 



CAPACITANCE (T A = 25°c, v cc = v DD =v ss = ov, v BB = -5V) 



Symbol 


Parameter 


Typ. 


Max. 


Unit 


Test Condition 




Clock Capacitance 


17 


25 


Pf 


f c = 1 MHz 


C IN 


Input Capacitance 


6 


10 


Pf 


Unmeasured Pins 


C OUT 


Output Capacitance 


10 


20 


Pf 


Returned to Vss 



NOTES: 

1 . The RESET signal must be active for a minimum of 3 clock cycles. 

2. AI supply / AT a = -0.45%/° C. 




AMBIENT TEMPERATURE (°CJ 



Typical Supply Current vs. 
Temperature, Normalized^ 



,13] 



2-3 



irrtel 



8080A/8080A-1 /8080A-2 



A.C. CHARACTERISTICS (8080A) <t a = o°c to 70°c, v DD 

Vbb = -5V±5%,V SS = 



= +12V +5%, V C c = +5V ±5%, 
OV; unless otherwise noted) 



Symbol 


Parameter 


Mir). 


Max. 


•1 
Min. 


•1 
Max. 


•2 

Min. 


2 
Max. 


Unit 


tcY [3] 


Clock Period 


0.48 


2.0 


0.32 


2.0 


0.38 


2.0 


^sec 


tr, tf 


Clock Rise and Fall Time 


0 


50 


0 


25 


0 


50 


nsec 


t 0 i 


0-j Pulse Width 


60 




50 




60 




nsec 


t02 


0 2 Pulse Width 


220 




145 




175 




nsec 


*D1 


Delay 0-\ to 02 


0 




0 




0 




nsec 


tD2 


Delay 02 to 0-| 


70 




60 




70 




nsec 


*D3 


Delay 0-j to 02 Leading Edges 


80 




60 




70 




nsec 


*DA 


Address Output Delay From 02 




200 




150 




175 


nsec 


tDD 


Data Output Delay From 02 




220 




180 




200 


nsec 


tDC 


Signal Output Delay From 0\ or 0 2 (SYNC, WR, WAIT, HLDA) 




120 




110 




120 


nsec 


tDF 


DBIN Delay From 02 


25 


140 


25 


130 


25 


140 


nsec 


t D l™ 


Delay for Input Bus to Enter Input Mode 




tDF 




tDF 




tDF 


nsec 


tDS1 


Data Setup Time During 0-) and DBIN 


30 




10 




20 




nsec 


*DS2 


Data Setup Time to 0 2 During DBIN 


150 




120 




130 




nsec 


*DH [1] 


Data Holt time From 02 During DBIN 


[1] 




[1] 




[1] 




nsec 


t|E 


INTE Output Delay From 02 




200 




200 




200 


nsec 


tRS 


READY Setup Time During 02 


120 




90 




90 




nsec 




HOLD Setup Time to 0 2 


140 




120 




120 




nsec 


tis 


INT Setup Time During 0 2 


120 




100 




100 




nsec 


tH 


Hold Time From 0 2 (READY, INT, HOLD) 


0 




0 




0 




nsec 


*FD 


Delay to Float During Hold (Address and Data Bus) 




120 




120 




120 


nsec 


*AW 


Address Stable Prior to WR 


[5] 




[5] 




[5] 




nsec 


*DW 


Output Data Stable Prior to WR 


[6] 




[6] 




[6] 




nsec 


tWD 


Output Data Stable From WR 


[7] 




[7] 




[7] 




nsec 


*WA 


Address Stable From WR 


[7] 




[7] 




[7] 




nsec 


tHF 


HLDA to Float Delay 


[8] 




[8] 




[8] 




nsec 


tWF 


WR to Float Delay 


[91 




[9] 




[9] 




nsec 


tAH 


Address Hold Time After DBIN During HLDA,. 


-20 




-20 




-20 




nsec 



Test Condition 



C L =100 pF 
C L = 50 pF 



C L = 50 pF 



C|_= 100 pF: Address, Data 
C L = 50 pF: WR,HLDA,DBIN 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 



C L 100 pF 

C L INCLUDES JIG CAPACITANCE 



2-4 



AFN-00735C 



inteT 



8080 A/8080 A- 1 /8080 A-2 



WAVEFORMS 



D r D 0 - 
SYNC 

DBIN 



A 



A 



DZZT 



jT_ *2Z "jfpATA IN 



r 



DC^* — 



t DSlj*- 



A 



— f 

— *OF-— I 



3 




A 



--'bo— 

30 



DATA OUT 



—I l HS 




NOTE: 

Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V, 
"0" = 1.0V; INPUTS "1" = 3.3V, "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V. 



2-5 



AFN-00735C 



8080A/8080A-1/8080A-2 



WAVEFORMS (Continued) 



V D 0 1-4.- 1 -(--*- 



/, i in j «- — . - %F "*" 



NOTES: (Parenthesis gives -1, -2 specifications, respectively) 

1. Data input should be enabled with DBIN status. No bus con- 
flict can then occur and data hold time is assured. 

toH = 50 ns or toF. whichever is less. 

2. t C Y = t D3 + t r< £ 2 + + tty2 + t D2 + t r<M » 480 ns ( - 1 :320 
ns, - 2:380 ns). 

TYPICAL A OUTPUT DELAY VS. A CAPACITANCE 























^SPEC 













A CAPACITANCE (pf) 
* C ACTUAL ~ C SPEC* 



3. The followrhg are relevant when interfacing the 8080A to 
devices having Vm = 3.3V: 

a) Maximum output rise time from ,8V to 3.3V = 100ns @ Cl 
= SPEC. 

b) Output delay when measured to 3.0V = SPEC +60ns @ C L 
= SPEC. 

c) If C L = SPEC, add .6ns/pF if C L > C S pec subtract .3ns/pF 
(from modified delay) if Cl < Cspec- 

4. tAW = 2 tcy- trj3 - t r ^2 - 140 ns ( - 1 :1 10 ns, - 2:130 ns). 

5. tow * *cy ~ *D3 ~ ^2 - 170 ns ( - 1 :150 ns, - 2:170 ns). 

6. If not HLDA, twD = twA = tD3 + tr<j>2 + 10 ns. If HLDA, twD 
= twA " *WF- 

7. t HF = t D 3 + t r ^2 -50 ns). 

8. twF = tb3 + k<f>2 - 10ns. 

9. Data in must be stable for this period during DBIN T 3 . 
Both tpsi and tos2 must be satisfied. 
Ready signal must be stable for this period during T 2 or Tw- 
(Must be externally synchronized.) 
Hold signal must be stable for this period during T 2 or Tw 
when entering hold mode, and during T3, T4, T5 and Twh 
when in hold mode. (External synchronization is not re- 
quired.) 

Interrupt signal must be stable during this period of the last 
clock cycle of any instruction in order to be recognized on the 
following instruction. (External synchronization is not re- 
quired.) 

This timing diagram shows timing relationships only; it does 
not represent any specific machine cycle. 



10. 



11 



12. 



13, 



2-6 



AFN-00735C 



8080 A/8080 A- 1/8080A-2 



INSTRUCTION SET 

The accumulator group instructions include arithmetic and 
logical operators with direct, indirect, and immediate ad- 
dressing modes. 

Move, load, and store instruction groups provide the ability 
to move either 8 or 16 bits of data between memory, the 
six working registers and the accumulator using direct, in- 
direct, and immediate addressing modes. 

The ability to branch to different portions of the program 
is provided with jump, jump conditional, and computed 
jumps. Also the ability to call to and return from sub- 
routines is provided both conditionally and unconditionally. 
The RESTART (or single byte call instruction) is useful for 
interrupt vector operation. 

Double precision operators such as stack manipulation and 
double add instructions extend both the arithmetic and 
interrupt handling capability of the 8080A. The ability to 



increment and decrement memory, the six general registers 
and the accumulator is provided as well as extended incre-. 
ment and decrement instructions to operate on the register 
pairs and stack pointer. Further capability is provided by 
the ability to rotate the accumulator left or right through 
or around the carry bit. 

Input and output may be accomplished using memory ad- 
dresses as l/O'ports or the directly addressed I/O provided 
for in the 8080A instruction set. 

The following special instruction group completes the 8080A 
instruction set: the NOP instruction, HALT to stop pro- 
cessor execution and the DAA instructions provide decimal 
arithmetic capability. STC allows the carry flag to be di- 
rectly set, and the CMC instruction allows it to be comple- 
mented. CMA complements the contents of the accumulator 
and XCHG exchanges the contents of two 16-bit register 
pairs directly. 



Data and Instruction Formats 

Data in the 8080A is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be in the 
same format, 

D 7 D 6 D 5 D 4 D3 D2 Pi Dp 
DATA WORD 

The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored 
in successive words in program memory. The instruction formats then depend on the particular operation 
executed. 



One Byte Instructions • 








TYPICAL INSTRUCTIONS 


D 7 D 6 D5D4 D 3 D 2 




Do 


OP CODE 


Register to register, memory refer- 


Two Byte Instructions 








ence, arithmetic or logical, rotate, 
return, push, pop, enable or disable 
Interrupt instructions 


D 7 D 6 D 5 D 4 D 3 D 2 


Dl 


Do 


OPCODE 




D 7 D 6 D 5 D 4 D 3 D 2 


D1 


Do 


OPERAND 


Immediate mode or I/O instructions 


Three Byte Instructions 










D 7 D 6 D 5 D 4 D 3 D 2 


D1 


Do 


OP CODE 


Jump, call or direct load and store 


D 7 D 6 D 5 D 4 D 3 D 2 


Dl 


Do 


LOW ADDRESS OR OPERAND 1 


instructions 


D 7 D 6 D 5 D 4 D 3 D 2 


.Dl 


Do 


HIGH ADDRESSOR OPERAND 2 





For the 8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level. 



2-7 



AFN-00735C 



8080A/8080A-1/8080A-2 



Table 2i Instruction Set Summary 























Clock* 






Instruction Code [1] 




Operations 


Cycles 


Mnemonic 


D7 De D 5 D 4 D3 D2 D1 Dq 


Description 


[2] 


MOVE, LOA 


0, AND STORE' 












MOVr1,r2 


0 


1 


D 


D 


D 


S 


s 


s 


Move register to register 


5 


MOV M,r 


9 


1 


1 


1 


0 


s 


s 


s 


Move register to 






















memory 


7 


MOV r,M 


0 


1 


D 


D 


D 


1 


1 


0 


Move memory to regis- 






















ter 


7 


MVI r 


0 


0 


D 


D 


D 


1 


1 


0 


Move immediate regis- 






















ter 


7 


MVIM 


0 


0 


1 


1 


0 






0 


Move immediate 






















memory 


10 


LXIB 


0 


0 


0 


0 


0 


0 


0 


1 


Load immediate register 


10 




















PairB&C 




LXID 


0 


0 


0 


1 


0 


0 






Load immediate register 


10 




















PairD&E 




LXIH 


0 


0 


1 


0 


0 


0 






Load immediate register 


10 




















Pair H & L 




STAXB 


0 


0 


0 


0 


0 


0 


■j 


0 


Store A indirect 


7 


STAXD 


0 


0 


0 


1 


0 


Q 


1 


0 


Store A indirect 


7 


LDAXB 


0 


0 


0 


0 


1 


0 


] 




Load A indirect 


7 


LOAXD 


0 


0 


0 


1 


1 






Q 


Load A indirect 


7 


STA 


0 


0 


1 


1 


6 


0 




0 


Store A direct 


13 


LDA 


0 


0 


1 


1 


1 


0 


■J 


Q 


Load A direct 


13 


SHLD 


0 


0 


1 


0 


0 


0 


•J ' 


g 


Store H & L direct 


16 


LHLD 


0 


0 


1 


0 


1 


0 


1 


0 


Load H & L direct 


16 


XCHG 




1 


1 


0 


1 


Q 


-] 


1 


Exchange 0 & E, H & L 


4 




















Registers 




STACK OPS 




















PUSHB 




1 


0 


0 


0 


1 


0 


■J 


Push register Pair B & 


11 




















C on stack 




PUSH D 




1 


0 


1 


0 


■J 


0 


■( 


Push register Pair D & 


11 




















E on stack 




PUSHH 




1 


1 


0 


0 


"I 


X) 


"1 


Push register Pair H & 


11 




















L on stack 




PUSH 




1 


1 


1 


0 


1 


0 


■\ 


Push A and Flags 


11 


PSW 


















on stack 




POPB 




1 


0 


0 


0 








Pop register Pair B & 


10 - 




















C off stack 




POPD 




1 


0 


1 


0 


0 


0 




Pop register Pair D & 


10 




















E off stack 




POPH 




1 


1 


0 


0 


0 


0 


"1 


Pop register Pair H & 


10 




















L off stack 




POP PSW 




1 


1 


1 


0 


0 


Q 


1 


Pop A and Flags 


10 . 




















off stack 




XTHL 




1 


1 


0 


0 


0 


■j 




Exchange top of 


18 




















stack, H & L 




SPHL 






1 


1 


1 


0 


0 


1 


H & L to stack pointer 


5 


LXI SP 


0 


0 


1 


1 


0 


0 


0 


1 


Load immediate stack 


10 




















pointer 




INX SP 


0 


0 


1 


1 


0 


0 


1 


1 


Increment stack pointer 


5 


DCX SP 


0 


0 


1 


1 


1 


0 


1 


1 


Decrement stack 


5 




















pointer 




JUMP 






















JMP 




1 


0 


0 


0 


0 


1 


1 


Jump unconditional 


10 


JC 




1 


0 


1 


1 


0 


1 


0 


Jump on carry 


10 


JNC 




1 


0 


1 


0 


0 


1 


0 


Jump on no carry 


10 


JZ 




1 


0 


0 


1 


0 


1 


0 


Jump on zero 


10 


JNZ 




1 


0 


0 


0 


0 


1 


0 


Jump on no zero 


10 


JP 




1 


1 


1 


0 


0 


1 


0 


Jump on positive 


10 


JM 




1 


1 


1 


1 


0 


1 


0 


Jump on minus 


10 


JPE 




1 


1 


0 


1 


0 


1 


0 


Jump on parity even 


10 



JPO 
PCHL 



CALL 

be 

CNC 

CZ 

CNZ 

CP 

CM 

CPE 

CPO 



RETURN 

RET 

RC 

RNC 

RZ 

RNZ 

RP 

RM 

RPE 

RPO 



RESTART 

RST 



Instruction Code [1] 
D7 D 6 D 5 D4 D3 D2 D1 Dq 



1 1 
1 1 



0 0 0 1 0 
0 10 0 1 



0 0 1 

0 1 1 

0 1 0 

0 0 1 

0 0 0 

1 1 0 

1 1 1 

1 0 

1 0 



1 
1 
1 
1 
1 
1 
1 

1 1 
0 1 



0 1 

1 1 



1 1 
1 1 



1 1 A A A 1 1 1 



INCREMENT AND 



INRr 

DCRr 

INRM 

DCRM 

INXB. 

INXD 

INXH 

DCXB 
DCXD 
DCXH 



ADD 

ADD r 
ADC r 

ADD M 
ADC M 

ADI 
ACI 

DAD B 
DADD 
DADH 
DAD SP 



DECREMENT 

D D D 1 
D D D 1 
110 1 
110 1 
0 0 0 0 



0 0 0 1 0 0 

0 0 1 0 0 0 

0 0 0 0 1 0 

0 0 0 1 1 0 

0 0 10 10 



1 1 

1 1 

1 1 

1 1 



0 0 0 0 s 

0001s 



s s 
s s 



1 0 0 0 0 1 

1 0 0 0 1 1 

1 1 0 0 0 1 

110 0 11 

0 0 0 0 1 0 

0 0 0 1 1 0 

0 0 10 10 

0 0 1110 



Operations 
Description 



Jump on parity odd 
H & L to program 
counter 



Call unconditional 
Call on carry 
Call on no carry 
Call on zero 
Call on no zero 
Call on positive 
Call on minus 
Call on parity even 
Call on parity odd 



Return 
Return 
Return 
Return 
Return 
Return 
Return 
Return 
Return 



on carry 
on no carry „ 
on zero 
on no zero 
on positive 
on minus 
on parity even 
on parity odd 



Restart 



Increment register 
Decrement register 
Increment memory 
Decrement memory 
Increment B & C 
registers 
Increment D & E 
registers 
Increment H & L 
registers 
Decrement B & C 
Decrement D & E 
Decrement H & L 



Add register to A 

Add register to A 

with carry 

Add memory to A 

Add memory to A 

with carry 

Add immediate to A 

Add immediate to A 

with carry 

Add B & C to H & L 

Add D & E to H & L 

Add H & L to H & L . 

Add stack pointer to 

H&L 



Clock 
Cycles 

[2] 



10 
5 



17 
11/17 
11/17 
11/17 
11/17 
11/17 
11/17 
11/17 
11/17 



10 

5/11 
5/11 
5/11 
5/11 
5/11 
5/11 
5/11 
5/11 



11 



5 
5 
10 
10 
5 

5 

5 

5 
5 
5 



4 
4 

7 
7 

7 
7 

10 
10 
10 
10 



2-8 



AFN-00735C 



8080 A/8080 A- 1/8080A-2 



Summary of Processor Instructions (Cont.) 





~T 
















Clock 






Instruction Code [1] 


Operations 


Cycles 


Mnomonic 


D7 D 6 D 5 D4 D3 D 2 D-\ Dq 


Description 


[2] 


SUBTRACT 




















SUB r 


1 


0 


0 1 


0 


s 


s 


s 


Subtract register 
from A 


4 


SBBr 


1 


0 


0 1 


1 


s 


s 


s 


Subtract register from 
A with borrow 


4 


SUB M 


1 


0 


0 1 


0 


1 


1 


0 


Subtract memory 
from A 


7 


SBB M 


1 


0 


0 1 


1 • 


1 


1 


0 


Subtract memory from 
A with borrow 


7 


SUI 


1 


1 


0 1 


0 


1 


1 


0 


Subtract immediate 
from A 


7 


SBI 


1 


1 


a 1 


1 


1 


1 


0 


Subtract immediate 
from A with borrow 


7 


LUUIUAL. 




















ANAr 


1 


0 


1 0 


0 


s 


s 


s 


And register with A 


4 


XRA r 


1 


0 


1 0 


1 


s 


s 


s 


Exclusive Or register 
with A 


4 


ORAr 


1 


0 


1 1 


0 


s 


s 


s 


Or register with A 


4 


CMPr 


1 


0 


1 1 


1 


s 


s 


s 


Compare register with A 


4 


ANAM 


1 


0 


1 0 


0 


1 


1 


0 


And memory with A 


7 


XRA M 


1 


0 


1 0 


1 


1 


1 


0 


Exclusive Or memory 
with A 


7 


ORAM 


1 


0 


1 1 


0 


1 


1 


0 


Or memory with A 


7 


CMPM 


1 


0 


1 1 


1 


1 


1 


0 


Compare memory with 
A 


7 


ANI 


1 


1 


1 0 


0 


1 


1 


0 


And immediate with A 


7 


XRI 


1 


1 


1 0 


1 


1 


1 


0 


Exclusive Or immediate 
with A 


7 


ORI 


1 


1 


1 1 


0 


1 


1 


0 


Or immediate with A 


7 


CPI 


1 


1 


1 1 


1 


1 


1 


0 


Compare immediate 
with A 


7 



ROTATE 

RLC 
RRC 
RAL 

RAR 



SPECIALS 

CMA 
STC 
CMC 
DAA 



Instruction Code 11] 
D7 D6 D5 D 4 D3 D2 D1 D 0 



0 0 
0 0 
0 0 



000111 

0 0 1111 
0 10 111 



0 0 0 1 1 1 1 1 



0 0 

0 0 

0 0 

0 0 



10 1111 
110 111 

111111 

10 0 111 



INPUT/OUTPUT 

IN 1 1 

OUT 1 1 



CONTROL 

El 
Dl 

NOP 
HLT 



NOTES: 

1. DDDor SSS: B=000, C=001, D=010, E=011, H=100, L=101, Memory=110, A=111. 

2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags. 
*AII mnemonics copyright ®lntel Corporation 1977 



0 110 11 
0 10 0 11 



1 1 

1 1 

0 0 

0 1 



1110 11 
110 0 11 
0 0 0 0 0 0 
110 110 



Operations 
Description 



Rotate A left 
Rotate A right 
Rotate A left through 
carry 

Rotate A right through 
carry 



Complement A 
Set carry 

Complement carry 
Decimal adjust A 



Input 
Output 



Enable Interrupts 
Disable Interrupt 
No-operation 
Halt 



Clock 
Cycles 

(2] 



10 
10 



2-9 



AFN-00735C 



inter 



8085AH/8085AH-2/8085AH-1 
8-BIT HMOS MICROPROCESSORS 



■ On-Chip System Controller; Advanced 
Cycle Status Information Available for 
Large System Control 

■ Four Vectored Interrupt Inputs (One is 
Non-Maskable) Plus an 
8080A-Compatible Interrupt 

■ Serial In/Serial Out Port 

■ Decimal, Binary and Double Precision 
Arithmetic 

■ Direct Addressing Capability to 64K 
Bytes of Memory 

■ Available in EXPRESS 

- Standard Temperature Range 

- Extended Temperature Range 

The Intel® 8085AH is a complete 8 bit parallel Central Processing Unit (CPU) implemented in N-channel, 
depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the8080A 
microprocessor, and it is designed to improve the present 8080A's performance by higher system speed. Its 
high level of system integration allows a minimum system of three IC's [8085AH (CPU), 8156H (RAM/IO) and 
8355/8755A (ROM/PROM/IO)] while maintaining total system expandability. The 8085AH-2 and 8085AH-1 are 
faster versions of the 8085AH. ' 

The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) 
provided for the 8080A, thereby offering a high level of system integration: 

The 8085AH uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data 
bus. The on-chip address latches of 8155H/8156H/8355/8755A memory products allow a direct interface with 
the 8085AH. 



Single +5V Power Supply with 10% 
Voltage Margins 

3 MHz, 5 MHz and 6 MHz Selections 
Available 

20% Lower Power Consumption than 
8085A for 3 MHz and 5 MHz 

1.3 fis Instruction Cycle (8085AH); 0.8 
fis (8085AH-2); 0.67 M s (8085AH-1) 

100% Compatible with 8085A 

100% Software Compatible with 8080A 

On-Chip Clock Generator (with 
External Crystal, LC or RC Network) 



t L t 



INTERRUPT CONTROL 



SERIAL I/O CONTROL 



T INTERNAL DATA BUS 




MACHINE 

CYCLE 
ENCODING 



STACK POINTER 



PROGRAM COUNTER 



ADDRESS BUFFER 



3 Z 



DATA/ADDRESS BUFFER 



X1 C 


1 


40 


3 


vcc 


x 2 c 


2 


39 


3 


HOLD 


RESET OUT C 


3 


38 


3 


HLDA 


SOD C 


4 


37 


3 


CLK (OUT) 


SID C 


5 


36 


3 


RESET IN 


TRAP C 


6 


35 


3 


READY 


RST7 5 C 


7 


34 


3 


IO/M 


RST6 5 C 


8 


33 


3 


Si 


RST5 5 C 


9 


32 


3 


RD 


INTR C 






3 


WR 


INTA C 


;> 




3 


ALE 


AD 0 C 


12 


29 


3 


so 


AD! C 


13 


28 


3 


A15 


AD 2 C 


14 


27 


3 


Al4 


AD 3 C 


15 


26 


3 


A13 


AD4 C 


16 


25 


3 


A12 


AD 5 C 


17 


24 


3 


A11 


AD6 C 


18 


23 


3 


A10 


AD 7 C 


19 


22 


3 


A9 


V S S C 


20 


21 


3 


A8 



Figure 1. 8085AH CPU Functional Block Diagram 



Figure 2. 8085AH Pin 
Configuration 



Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied. 
®INTEL CORPORATION, 1981 



2-10 



8085AH/8085AH-2/8085AH-1 



Table 1. Pin Description 



Symbol 



A8-A15 



AD0--7 



ALE 



S 0 , S-f,and IO/M 



RD 



WR 



Type 



I/O 



Name and Function 



Address Bus: The most significant 
8 bits of the memory address or the 
8 bits of the I/O address, 3-stated 
during Hold and Halt modes and 
during RESET. 



Multiplexed Address/Data Bus: 

Lower 8 bits of the memory address 
(or I/O address) appear on the bus 
during the first clock cycle (T state) 
of a machine cycle. It then becomes 
the data bus during the second and 
third clock cycles. 



Address Latch Enable: It occurs 
during the first clock state of a ma- 
chine cycle and enables the address 
to get latched into the on-chip latch 
of peripherals. The falling edge of 
ALE is set to guarantee setup and 
hold times for the address informa- 
tion. The falling edge of ALE can 
also be used to strobe the status 
information. ALE is never 3-stated. 



Machine Cycle Status: 



IO/M 


Si 


So 


Status 


0 


0 


1 


Memory write 


0 


1 


0 


Memory read 


1 


0 


1 


I/O write 


1 


1 


0 


I/O read 


0 


1 


1 


Opcode fetch 


1 ' 


1 


1 


Opcode fetch 


1 


1 


1 


Interrupt 








Acknowledge 




0 


0 


Halt 




X 


X 


Hold 




x \ 


X 


Reset 



* = 3-state (high impedance) 
X = unspecified 

S-i can be used as an advanced R/W 
status. IO/M, S 0 and Si become 
valid at the beginning of a machine 
cycle and remain stable throughout 
the cycle. The falling edge of ALE 
may be used to latch the state of 
these lines. 



Read Control: A low level on RD 
indicates the selected memory or 
I/O device is to be read and that the 
Data Bus is available for the data 
transfer, 3-stated during Hold and 
Halt modes and during RESET. 



Write Control: A low level on WR 
indicates the data on the Data Bus is 
to be written into the selected 
memory or I/O location. Data is set 
up at the trailing edge of WR. 3- 
stated during Hold and Halt modes 
and during RESET. 





Type 


NsiiMk and Function 


READY 


I 


Ready: If READY is high during a 
read or write cycle, it indicates that 
, the memory or peripherals ready to 
send or receive data. If READY is 
low, the cpu will wait an integral 
number of clock cycles for READY 
to go high before completing the 
read or write cycle. READY must 
conform to specified setup and hold 
times. 


HOLD 




Hold: Indicates that another master 
is r&quesiing ins use 01 ins aouress 
and data buses. The cpu, upon 
receiving the hold request, will 
relinquish the use of the bus as 
soon as the completion of the cur- 
rent bus transfer. Internal process- 
ing can continue. The processor 
can regain the bus only after the 
HOLD is removed. When the HOLD 
is acknowledged, the_Address, 
Data RD, WR, and IO/M lines are 
3-stated. 


HLDA 


0 


Hold Acknowledge: Indicates that 
the cpu has received the HOLD re-* 
quest and that it will relinquish the 
bus in the next clock cycle. HLDA 
goes low after the Hold request is 
removed. The cpu takes the bus one 
half clock cycle after HLDA goes 
low. 


INTR 




Interrupt Request: Is used as a 
general purpose interrupt. It is 
sampled only during the next to the 

la^t rlopk rvrlp of an instruction 

and during Hold and Halt states, if it 
is active, the Program Counter (PC) 
will be inhibited from incrementing 
and an INTA will be issued. During 
this cycle a RESTART or CALL in- 
struction can be inserted to jump to 
the interrupt service routine. The 
INTR is enabled and disabled by 
software. It is disabled by Reset and 
immediately after an interrupt is ac- 
cepted 


Tnta 


0 


Interrupt Acknowledge: Is used in- 
stead of (and has the same timing 
as) RD during the Instruction cycle 
after an INTR is accepted. It can be 
used to activate an 8259A Interrupt 
chip or some other interrupt port. 


RST 5.5 
RST 6.5 
RST 7.5 


i 
i 


Restart Interrupts: These three in- 
puts have the same timing as INTR 
except they cause an internal 
RESTART to be automatically 
inserted 


* 




The priority of these interrupts is 
ordered as shown in Table 2. These 
interrupts have a higher priority 
than INTR. In addition, they may be 
individually masked out using the 
SIM instruction. 



2-11 



AFN-01835C 



irrteT 



8085AH/8085AH-2/8085AH-1 



Table 1. Pin Description (Continued) 



Symbol 



TRAP 



&ESET IN 



Type 



Name and Function 



Trap: Trap interrupt is a non- 
maskable RESTART interrupt. It is 
recognized at the same time as 
INTR or RST 5.5-7.5. It is unaffected 
by any mask or Interrupt Enable. It 
has the highest priority of any inter- 
rupt. (See Table 2 ) 



Reset In: Sets the Program 
Counter to zero and resets the Inter- 
rupt Enable and HLDA flip-flops. 
The data and address buses and the 
control lines are 3-stated during 
RESET and because of the asyn- 
chronous nature of RESET, the pro- 
cessor's internal registers and flags 
may be altered by R ESET with un- 
predictable results. RESET IN is a 
Schmitt-triggered input, allowing 
connection to an R-C network for 
power-on RESET d elay (see F igure 
3). Upon power-up, RESET IN must 
remain low for at least 10 ms after 
minimum Vcc has been reached. 
For proper reset operati on after the 
power-up duration, RESET IN 
should be kept low a minimum of 
three clock periods. The CPU is held 
in the res et condition as long as 
RESET IN is applied. 



Symbol 


Type 


Name and Function 


RESET OUT 


0 


Reset Out: Reset Out indicates cpu 
is being reset. Can be used 
as a system reset. The signal is 
synchronized to the processor 
clock and lasts an integral number 
of clock periods. 


Xf, X2 


I 


X1 and X?: Are connected to a 
crystal, LC, or RC network to drive 
the internal clock generator. X-, can 
also be an external clock input from 
a logic gate. The input frequency is 
divided by 2 to give the processor's 
internal operating frequency. 


CLK 


0 


Clock: Clock output for use as a sys- 
tem clock. The period of CLK is 
twice the X 1( X 2 input period. 


SID 


I 


Serial Input Data Line: The data on 
this line is loaded into accumulator 
bit 7 whenever a RIM instruction is 
executed. 


SOD 


0 


Serial Output Data Line; The out- 
put SOD is set or reset as specified 
by the SIM instruction. 


Vcc 




Power: +5 volt supply. 


v S s 




Ground: Reference. 



Table 2. Interrupt Priority, Restart Address, and Sensitivity 



Name 


Priority 


Address Branched To (1) 
When Interrupt Occurs 


Type Trigger 


TRAP 


1 


24H 


Rising edge AND high level until sampled. 


RST 7.5 


2 


3CH 


Rising edge (latched). 


RST 6.5 


3 


34H 


High level until sampled. 


RST 5.5 


4 


2CH . 


High-level until sampled. 


INTR 


5 


See Note (2). 


High level until sampled. 



NOTES: 

1. The processor pushes the PC on the stack before branching to the indicated address. 

2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged^ 



VccO- 



R1 



TYPICAL POWER-ON RESET RC VALUES* 

R-l =75Kn 
C, * 1 mF 

♦VALUES MAY HAVE TO VARY DUE TO 
APPLIED POWER SUPPLY RAMP UP TIME. 



Figure 3. Power-On Reset Circuit 

2-12 



AFN-01835C 



8085AH/8085AH-2/8085AH-1 



FUNCTIONAL DESCRIPTION 

The 8085AH is a complete 8-bit parallel central pro- 
cessor. It is designed with N-channel, depletion 
load, silicon gate technology (HMOS), and requires 
a single +5 volt supply. Its basic clock speed is 
3 MHz (8085AH), 5 MHz (8085AH-2), or 6 MHz 
(8085AH-1), thus improving on the present 8080A's 
performance with higher system speed. Also it is 
designed to fit into a minimum system of three IC's: 
The CPU (8085AH), a RAM/IO (8156H), and a ROM or 
EPROM/IO chip (8355 or 8755A). 

The 8085AH has twelve addressable 8-bit registers. 
Four of them can function only as two 16-bit register 
pairs. Six others can be used interchangeably as 
8-bit registers or as 1 6-bit register pairs. The 8085AH 
register set is as follows: 

Mnemonic Register Contents 

ACCorA Accumulator 8 bits 

PC Program Counter 16-bit address 

BC.DE.HL General-Purpose 8 bits x 6 or 

Registers; data 1 6 bits x 3 

pointer (HL) 

SP Stack Pointer 16-bit address 

Flags or F Flag Register 5 flags (8-bit space) 

The 8085AH uses a multiplexed Data Bus. The 
address is split between the higher 8-bit Address 
Bus and the lower 8-bit Address/Data Bus. During 
the first T state (clock cycle) of a machine cycle the 
low order address is sent out on the Address/Data 
bus. These lower 8 bits may be latched externally by 
the Address Latch Enable signal (ALE). During the 
rest of the machine cycle the data bus is used for 
memory or I/O data. 

The 8085AH provides RD, WR, S 0 , S^ and IO/M 
signals for b us control. An Interrupt Acknowledge 
signal (INTA) is also provided. HOLD and all Inter- 
rupts are synchronized with the processor's internal 
clock. The 8085AH also provides Serial Input Data 
(SID) and Serial Output Data (SOD) lines for simple 
serial interface. 

In addition to these features, the 8085AH has three 
maskable, vector interrupt pins, one nonmaskable 
TRAP interrupt, and a bus vectored interrupt, INTR. 

INTERRUPT AND SERIAL I/O 

The 8085AH has 5 interrupt inputs: INTR, RST 5.5, 
RST 6.5, RST 7.5, and TRAP. INTR is identical in 
function to the 8080A INT Each of the three RE- 
START inputs, 5.5, 6.5, and 7.5, has a programmable 
mask. TRAP is also a RESTART interrupt but it is 
nonmaskable. 



The three maskable interrupts cause the internal 
execution of RESTART (saving the program counter 
in the stack and branching to the RESTART address) 
if the interrupts are enabled and if the interrupt mask 
is not set. The nonmaskable TRAP causes the inter- 
nal execution of a RESTART vector independent 
of the state of the interrupt enable or masks. (See 
Table 2.) 

There are two different types of inputs in the restart 
interrupts. RST 5.5 and RST 6.5 are high level- 
sensitive like INTR (and INT on the 8080) and are 
recognized with the same timing as INTR. RST 7.5 is 
rising edge-sensitive. 

For RST 7.5, only a pulse is required to set an inter- 
nal flip-flop which generates the internal interrupt 
request (a normally high level signal with a low 
going pulse is recommended for highest system 
noise immunity). The RST 7.5 request flip-flop 
remains set until the request is serviced. Then 
it is reset automatically. This flip-flop may also be 
reset by u sing the SIM instruction or by issuing a 
RESET IN to the 8085AH. The RST 7.5 internal flip- 
flop will be set by a pulse on the RST 7.5 pin even 
when the RST 7.5 interrupt is masked out. 

The status of the three RST interrupt mas ks can only 
be affected by the SIM instruction and RESET IN. 
(See SIM, Chapter 5 of the MCS-80/85 User's 
Manual.) 

The interrupts are arranged in a fixed priority that 
determines which interrupt is to be recognized if 
more than one is pending as follows: TRAP — 
highest priority, RST 7.5, RST 6.5, RST 5.5, INTR— 
lowest priority. This priority scheme does not take 
into account the priority of a routine that was started 
by a higher priority interrupt. RST 5.5 can interrupt 
an RST 7.5 routine if the interrupts are re-enabled 
before the end of the RST 7.5 routine. 



The TRAP interrupt is useful for catastrophic events 
such as power failure or bus error. The TRAP input is 
recognized just as any other interrupt but has the 
highest priority. It is not affected by any flag or mask. 
The TRAP input is both edge and level sensitive. The 
TRAP input must go high and remain high until it is 
acknowledged. It will not be recognized again until it 
goes low, then high again. This avoids any false 
triggering due to noise or logic glitches. Figure 4 
illustrates the TRAP interrupt request circuitry 
within the 8085AH. Note that the servicing of any 
interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) 
disables all future interrupts (except TRAPs) until an 
El instruction is executed. 



( 



2-13 



intef 



8085AH/8085AH-2/8085AH-1 



EXTERNAL 
TRAP 

INTERRUPT 
REQUEST 



INSIDE THE 



P4 



INTERRUPT 
REQUEST 



INTERNAL 
TRAP 
ACKNOWLEDGE 



Figure 4. TRAP and RESET IN Circuit 

The TRAP interrupt is special in that it disables inter- 
rupts, but preserves the previous interrupt enable 
status. Performing the first RIM instruction follow- 
ing a TRAP interrupt allows you to determine 
Whether interrupts were enabled or disabled prior to 
the TRAP. All subsequent RIM instructions provide 
current interrupt enable status. Performing a RIM 
instruction following INTR, or RST 5.5-7.5 will 
provide current Interrupt Enable status, revealing 
that Interrupts are disabled. See the description of 
the RIM instruction in the MCS-80/85 Family User's 
Manual. 

The serial I/O system is also controlled by the RIM 
and SIM instructions. SID is read by RIM, and SIM 
sets the SOD data. 



Parallel resonance at twice the clock frequency 
desired 

Cl (loac- capacitance) ^ 30 pF 

Cs (shunt capacitance) *s 7 pF 

Rs (equivalent shunt resistance) ^ 75 Ohms 

Drive level: 10 mW 

Frequency tolerance: ±.005% (suggested) 

Note the use of the 20 pF capacitor between X 2 and 
ground. This capacitor is required with crystal fre- 
quencies below 4 MHz to assure oscillator startup at 
the correct frequency. A parallel-resonant LC circuit 
may be used as the frequency-determining network 
for the 8085AH, providing that its frequency 
tolerance of approximately ±10% is acceptable. The 
components are chosen from the formula: 



f = 



1 



27A/L(C e xt + Gjrit) 

To minimize variations in frequency, it is recom- 
mended that you choose a value for C ex t that is at 
least twice that of Cj n t, or 30 pF. The use of an LC 
circuit is not recommended for frequencies higher 
than approximately 5 MHz. 

An RC circuit may be used as the frequency- 
determining network for the8085AH if maintaining a 
precise clock frequency is of no importance. Var- 
iations in the on-chip timing generation can cause a 
wide variation in frequency when using the Rp 
mode. Its advantage is its low component cost. The 
driving frequency generated by the circuit shown is 
approximately 3 MHz. It is not recommended that 
frequencies greatly higher or lower than this be 
attempted. 



DRIVING THE X 1 AND X 2 INPUTS 

You may drive the clock inputs of the 8085AH, 
8085AH-2, or 8085AH-1 with a crystal, an LC tuned 
circuit, an RC network, or an external clock source. 
The crystal frequency must be at least 1 MHz, and 
must be twice the desired internal clock frequency; 
hence, the 8085AH is operated with a 6 MHz crystal 
(for 3 MHz clock), the 8085AH-2 operated with a 10 
MHz crystal (for 5 MHz clock), and the 8085AH-1 can 
be operated with a 12 MHz crystal (for 6 MHz clock). 
"If a crystal is used, it must have the following 
characteristics: 



Figure 5 shows the recommended clock driver cir- 
cuits. Note in D and E that pullup resistors are re- 
quired to assure that the high level voltage of the 
input is at least 4V and maximum low level voltage 
of 0.8V. 

" For driving frequencies up to and including 6 MHz 
you may supply the driving signal to X-j and leave X 2 
open-circuited (Figure 5D). If the driving frequency 
is from 6 MHz to 12 MHz, stability of the clock 
generator will be improved by driving both X-, and X 2 
with a push-pjjll source (Figure 5E). To prevent 
self-oscillation of the 8085AH, be sure that X 2 is not 
coupled back to X 1 through the driving circuit, 
t 



2-14 



AFN-01835C 



8085AH/8085AH-2/8085AH-1 



I 1 



20pp"y 



I C|nt 
_L »15pF 



.{p ! 



*20 pF CAPACITORS REQUIRED FOR 
CRYSTAL FREQUENCY « 4 MHz ONLY. 

a. Quartz Crystal Clock Driver 



-cp — 

1 



l-EXT *T* C EX T 



1 



C|NT 
. -15pF 



I 



b. LC Tuned Circuit Clock Driver 



^ 20pF^ 



2 

-L> 



c. RC Circuit Clock Driver 



470O 
TO < 

1Kft < 



LOW TIME > 60 ns 



*X 2 LEFT FLOATING 

d. 1-6 MHz Input Frequency External Clock 
Driver Circuit 



LOWTIME>40ns 



-O 



e. 1-12 MHz Input Frequency External Clock 
Driver Circuit 



Figure 5. Clock Driver Circuits 



GENERATING AN 8085AH WAIT STATE 



If your system requirements are such that slow 
memories or peripheral devices are being used, the 
circuit shown in Figure 6 may be used to insert one 
WAIT state in each 8085AH machine cycle. 



The D flip-flops should be chosen so that 

• CLK is rising edge-triggered 

• CLEAR is low-level active. 



I 








CLEAR 


8085AH 






TO 

8085AH 


CLK 


CLK OUTPUT* — - 


CLK 




"D" 




"D" 




READY 


F/F 


Q 


F/F 


Q 


INPUT 


D 




D 







*ALE AND CLK (OUT) SHOULD BE BUFFERED IF CLK INPUT OF LATCH 
EXCEEDS 8085AH IOL OR IOH. 



Figure 6. Generation of a Wait State for 8085AH 
CPU 



\ 



2-15 



AFN-01835C 



8085AH/8085AH-2/8085AH-1 



/L. 

f Am 



f. ADO-7 
\T- — 



7Y 



7% 



8156H 

[RAM + I/O + COUNTER/TIMER] 



•NOTE OPTIONAL CONNECTION 



A8- 



-vw-*v cc 
-vw — *-v cc 



SdiowclkrstIrdy 



8355 [ROM + I/O] 
OR 

8755A [PROM + I/O] 



Figure 8. MCS-85® Minimum System (Memory Mapped I/O) 



TRAP 
RST7 
RST6 
RST5 
INTR 

iroTA 

ADDR 



HOLD 
HLDA 
SOD 



RESET - 

ADDR/ OUT a 0 

DATA ALE RD'WR IO/M RDYCLK 




CLK 
RESET 
IO/M (CS) 

Wr 



DATA 
STANDARD 



control: 

0 



-AM — +- v cc 



Figure 9. MCS-85® System (Using Standard Memories) 

2-16 



AFN-01835C 



inteT 



8085AH/8085AH-2/8085AH-1 



1 1 





TRAP 


X, x 2 


RESET IN 

HOLD 






RST7.5 




HLDA 






RST6.5 


8085 


AH 






RST5.5 




SID 






INTR 
THIS. 
ADDR 


ADDR/ 

DATA ALE RB 


S, 

RESET - 
OUT S 0 
WR lO/ffl RDY CLK 





7v 



c 



c 



_L_L 



PORT 
B 8158H 



-\ DATA/ 
ADDR 



too 



IO/W TIMER - 

OtCCT OUT" 



•NOTE OPTIONAL CONNECTION 



Jow 

RD ' 
ALE 
Cf 
A 8-10 

8355/ 
8755A 

DATA/ 
ADDR 

io/fii | 

RESET 
RDY 
CLK 



;<a> 



TTT 

V S S V CC V OD PROG 
WV V CC 



-vw 



As in the 8080, the READY line is used to extend the 
read and write pulse lengths so that the 8085AH can 
be used with slow memory. HOLD causes the CPU to 
relinquish the bus when it is through with it by float- 
ing the Address and Data Buses. 

SYSTEM INTERFACE 

The 8085AH family includes memory components, 
which are directly compatible to the 8085AH CPU. 
For example, a system consisting of the three chips, 
8085AH, 8156H, and 8355 will have the following 
features: 

• 2K Bytes ROM 

• 256 Bytes RAM 

• 1 Timer/Counter 

• 4 8-bit I/O Ports 

• 1 6-bit I/O Port 

• 4 Interrupt Levels 

• Serial In/Serial Out Ports 

This minimum system, using the standard I/O tech- 
nique is as shown in Figure 7. 

In addition to standard I/O, the memory mapped I/O 
offers an efficient I/O addressing technique. With 
this technique, an area of memory address space is 
assigned for I/O address, thereby, using the memory 
address for I/O manipulation. Figure 8 shows the 
system configuration of Memory Mapped I/O using 
8085AH. 

The 8085AH CPU can also interface with the stan- 
dard memory that does not have the multiplexed 
address/data bus. It will require a simple 8212 (8-bit 
latch) as shown in Figure 9. 

\ 



Figure 7. 8085AH Minimum System (Standard I/O 
Technique) 



2-17 



AFN-01835C 



8085AH/8085AH-2/8085AH-1 



BASIC SYSTEM TIMING 

The 8085AH has a multiplexed Data Bus. ALE is used 
as a strobe to sample the lower 8-bits of address on 
the Data Bus. Figure 10 shows an instruction fetch, 
memory read and I/O write cycle (as would occur 
during processing of the OUT instruction). Note that 
during the I/O write and redd cycle that the I/O port 
address is copied on both the upper and lower half 
of the address. 

There are seven possible types of machine cycles. 
Which of these seven takes place _is defined by the 
status of the three status l ines (IO/ M, S 1t So) and the 
three control signals (RD, WR, and INTA). (See Table 
3.) The status lines can be used as advanced con- 
trols (for device selection, for example), since they 
become active at the Ti state, at the outset of each 
machine cycle: Control lines RD and WR become 
active later, at the time when the transfer of data is to 
take place, so are used as command lines. 

A machine cycle normally consists of three T states, 
with the exception of OPCODE FETCH, which nor- 
mally has either four or six T states (unle ss WAIT or 
HOLD states are forced by the receipt of READY or 
HOLD inputs). Any T state must be one of ten 
possible states, shown in Table 4. 



Table 3. 8085AH Machine Cycle Chart 



MACHINE CYCLE 


STATUS 


CON 


TROI 




IO/M 


SI 


SO' 


RD 


WR 


INTA 


OPCODE FETCH 


(OF) 




0 


1 




0 


1 


1 


MEMORY READ 


(MR) 




0 


,1 




0 


1 


1 


MEMORY WRITE 


(MW) 




0 


0 




1 


0 


1 


I/O READ 


(IOR) 




1 


1 




0 


1 


1 


I/O WRITE 


(IOW) 




1 


0 




1 


0 


1 


ACKNOWLEDGE 


















OF INTR 


UNA) 




1 


1 




1 


1 


0 


BUS IDLE 


(Bl) 


DAD 
ACK OF 
RST.TRAP 


0 
1 


1 
1 




1 
1 


1 
1 


1 
1 






HALT 


TS 


0 


0 


TS 


TS 


1 



Table 4. 8085AH Machine State Chart 





Status & Buses 


Control 


Machine 
















State 


S1,S0 


IO/M 


A 8 -Ai5 


AD 0 -AD 7 


RD,WR 


IIMTA 


ALE 


Ti 


X 


X 


X 


X 


1 


1 , 


1* 


T 2 


X 


X 


X 


X 


X 


X 


0 


T WAIT 


X 


X 


X 


X 


X 


X 


0 


T 3 


X 


X 


X 


X 


X 


X 


0 


T 4 


1 


0 t 


X 


TS 


1 


1 


0 


T 5 


1 


0t 


X 


TS 


1 


1 


0 


T 6 


1 


0t 


X 


TS 


1 ' 


1 


0 


T RESET 


X 


TS 


TS 


TS 


TS 


1 


0 


Thalt 


0 


TS 


TS 


TS 


TS 


1 


0 


Thold 


X 


TS 


TS 


TS 


TS 


1 


0 



0 = Logic "0" TS = High Impedance 

1 = Logic "1" X = Unspecified 

* ALE not generated during 2nd and 3rd machine cycles of DAD instruction 
t IO/M = 1 during T4-T6 of INA machine cycle 



PC H (HIGH ORDER ADDRESS) 



(LOWC Dnco 
ADDF 



(LOW ORDER DATA FROM 

ADDRESS) MEMORY 

(INSTRUCTION) 



StSq (FETCH) 



X 



n 



DATA FROM MEMORY 
(I/O PORT ADDRESS) 



~\ F 



X 



x: 



x 



DATA TO MEMORY 
OR PERIPHERAL 



~\ f 



I 



X 



Figure 10. 8085AH Basic System Timing 

2-18 



AFN-01835C 



8085AH/8085AH-2/8085AH-1 



ABSOLUTE MAXIMUM RATINGS* 

* 

Ambient Temperature Under Bias 0°C to 70°C 

Storage Temperature , . . . -65°C to +150°C 

Voltage on Any Pin 

With Respect to Ground -0.5V to +7V 

Power Dissipation 1 .5^ Watt 



'NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS 

8085AH, 8085AH-2: ,(T A = 0°C to 70°C, V cc = 5V ±10%, V ss =0V; unless otherwise specified)* 
8085AH-1 : (T A = 0°C to 70°C, V cc = 5V ±5%, V S s = 0V; unless otherwise specified) 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 


+0.8 


V 




V| H 


Input High Voltage 


2.0 


V CC +05 


V 




Vol 


Output Low Voltage 




0.45 


V 


Iql = 2mA 


V 0 H 


Output High Voltage 


2.4 




V 


Iqh = -400/xA 


■cc 


Power Supply Current 




135 


mA 


8085AH, 8085AH-2 




200 


mA 


8085AH-1 (Preliminary) 


IlL 


input Leakage 




±10 


fiA 


0*sV, N ^V cc 


Ilo 


Output Leakage 




±10 


(jlA 


0.45V ^ V 0U T < V CC 


V,LR 


Input Low Level, RESET 


-0.5 


+0.8 


V 




V| H R 


Input High Level, RESET 


2.4 


V CC +0-5 


V 




V H Y 


Hysteresis, RESET 


0.15 




V 





A.C. CHARACTERISTICS 

8085AH, 8085AH-2: (T A = 0°C to 70°C, V CC = 5V ±10%, V ss = OV)* 
8085AH-1 : (T A = 0°C to 70°C, V C c = 5V ±5%, V S s = 0V) 



Symbol 


Parameter 


8085AH [2] 
(Pinal) 


8085AH-2 [2] 
(Final) 


8085AH-1 
(Preliminary) 


Units 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


tCYC 


CLK Cycle Period 


320 


2000 


200 


2000 


167 


2000 


ns 


tl . 


CLK Low Time (Standard CLK Loading) 


80 




40 




20 




ns 


t 2 


CLK High Time (Standard CLK Loading) 


120 




70 




50 




ns 


tr-tf 


CLK Rise and Fall Time 




30 




30 




30 


ns 


*XKR 


X-| Rising to CLK Rising 


20 


120 


20 


100 


20 


100 


ns 


*XKF 


X 1 Rising to CLK Falling 


20 


150 


20 


110 


20 


110 


ns 


tAC 


Ae-15 Valid to Leading Edge of Control 111 


270 




115 




70 




ns 


UCL 


Ag-7 Valid to Leading Edge of Control 


240 




115 




60 




ns 


Ud 


A 0 _i 5 Valid to Valid Data in 




575 




350 




225 


ns 


Ufr 


Address Float After Leading Edge of 
READ (INTA) 




0 




0 




0 


ns 


tAL 


Aq.15 Valid Before Trailing Edge of ALE 113 


115 




50 




.25 




ns 



*Note: For Extended Temperature EXPRESS use M8085AH Electricals Parameters. 



2-19 



AFI^-01835C 



8085AH/8085AH-2/8085AH-1 



A.C. CHARACTERISTICS (Continued) 



Symbol 


Parameter 


8085AH C2] 
(Final) 


8085AH-2 [21 
(Final) 


8085AH-1 
(Preliminary) 


Units 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


t^LL 


A0.7 Valid Before Trailing Edge of ALE 


90 




50 




25 




ns 


*ARY 


READY Valid from Address Valid 




220 




100 




40 


ns 


tCA 


Address (Ae-15) Valid After Control 


120 




60 




30 




ns 


*cc 


Width of Control Low (ED, WR, INTa") 
Edge of ALE 


400 




230 




150 




ns 




Trailing Edge of Control to Leading Edge 
of ALE 


50 




25 




0 




ns 


tow 


Data Valid to Trailing Edge of WRITE 


420 




230 




140 




ns 


*HABE 


HLDA to Bus Enable 




210 




150 




150 


ns 


*HABF 


Bus Float After HLDA 




210 




150 




150 


ns 


tfHACK 


HLDA Valid to Trailing Edge of CLK 


110 




40 




0 




ns 


*HDH 


HOLD Hold Time 


0 




0 




0 




ns 


*HDS 


HOLD Setup Time to Trailing Edge of CLK 


170 




120 




120 




ns 


t|NH 


INTR Hold Time 


0 




0 




0 




ns 


t|NS 


INTR, RST, and TRAP Setup Time to 
Falling Edge of CLK 


160 




150 




150 




ns 


tLA 


Address Hold Time After ALE 


100 




50 




20 




ns 


*LC 


Trailing Edge of ALE to Leading Edge 
of Control 


130 




60 




25 




ns 


*LCK 


ALE Low During CLK High 


100 




50 




15 




ns 


t|_DR 


ALE to Valid Data During Read 




460 




270 




175 


ns 


*LDW 


ALE to Valid Data During Write 




200 




140 




110 


ns 


t|_i_ 


ALE Width 


140 




80 




50 




ns 


*LRY 


ALE to READY Stable 




110 




30 




10 


ns 


*RAE 


Trailing Edge of READ to Re-Enabling 
of Address 


150 




90 




50 




ns 


*RD 


FTEAB (or INTS) to Valid Data 




300 




150 




75 


' ns 


*RV 


Control Trailing Edge to Leading Edge 
of Next Control 


400 




220 




160 




ns 


tRQH 


Data Hold Time After ReTO fFTTR 


0 




0 




0 




ns 


tRYH 


READY Hold Time 


0 




0 




5 




ns 


*RYS 


READY Setup Time to Leading Edge 
of CLK 


110 




100 




100 




ns 


t WD 


Data Valid After Trailing Edge of WRITE 


100 




60 




30 




ns 


*WDL 


LEADING Edge of WRITE to Data Valid 




40 




20 




30 


ns 



2-20 



AFN-01835C 



8085AH/8085AH-2/8085AH-1 



NOTES: 

1. Ag-A-15 address Specs apply IO/Fi/f, So, and S-| except Aq-A^ 
are undefined during T 4 -T 6 of OF cycle whereas IO/M, So, and 
S-| are stable. 

2. Test Conditions: t CY c = 320 ns (8085AH)/200 ns (8085AH-2);/ 
167 ns (8085AH-1); C L = 150 pF. 

A.C. TESTING INPUT, OUTPUT WAVEFORM 



INPUT/OUTPUT 



^> TEST POINTS <^ 




AC TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR 
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC 1 
AND 0 8V FOR A LOGIC 0 



3. For all output timing where Ct ¥ 150 pF use the following 
correction factors: 

25 pF C L < 150 pF: -0.10 ns/pF 
150 pF < C|_ « 300 pF: +0.30 ns/pF 

4. Output timings are measured with purely capacitive load. 

5. To calculate timing specifications at other values of t C yc use 
Table 5. 

A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 



1 



150 pF 



C L = 150 pF 

C u INCLUDES JIG CAPACITANCE 



Table 5. Bus Timing Specification as a T CY c Dependent 



Symbol 


8085AH 


8085AH-2 


8085AH-1 




tAL 


(1/2) T - 45 


(1/2) T - 5G 


(1/2) T - 58 


Minimum 


t|_A 


(1/2) T - 60 


(1/2) T - 50 


(1/2) T- 63 


Minimum 


tLL 


(1/2) T- 20 


(1/2) T - 20 


(1/2) T - 33 


Minimum 


t|_CK 


(1/2) T - 60 


(1/2) T- 50 


(1/2) T - 68 


Minimum 


tLC 


(1/2) T - 30 


(1/2) T- 40 


(1/2) T- 58 


Minimum 


*AD 


(5/2 + N) T - 225 


(5/2 + N)T - 150 


(5/2 + N)T-192 


Maximum 


*RD 


(3/2 + N)T - 180 


(3/2 + N)T-150 


(3/2 + N)T-175 


Maximum 


*RAE 


(1/2) T- 10 


(1/2) T- 10 


(1/2) T - 33 


Minimum - 


tCA 


(1/2) T - 40 


(1/2) T - 40 


(1/2) T- 53 


Minimum 


tpw 


(3/2 + N) T - 60 


(3/2 + N) T - 70 


(3/2 + N)T - 110 


Minimum 




(1/2) T - 60 


(1/2JT-40 


(1/2) T- 53 


Minimum 


tec 


(3/2 + N) T - 80 


(3/2 + N) T - 70 . 


(3/2 + N)T - 100 


Minimum 


tCL 


(1/2) T - 110 


(1/2)T-75 


(1/2) T - 83 


Minimum 


*ARY 


(3/2) T - 260 


(3/2) T - 200 


(3/2) T - 210 


Maximum 


*HACK 


(1/2) T - 50 


' (1/2) T - 60 


(1/2) T- 83 


Minimum 


*HABF 


(1/2) T + 50 


(1/2)T + 50 


(172) T + 67 


Maximum 


tHABE 


(1/2) T + 50 


(1/2)T + 50 


(1/2) T + 67 


Maximum 


tAC 


(2/2) T - 50 


(2/2) T - 85 


(2/2) T - 97 


Minimum 


tl 


(1/2) T - 80 


(1/2) T - 60 


(1/2) T - 63 


Minimum 


t2 


(1/2) T- 40 


(1/2) T- 30 


(1/2) T- 33 


Minimum 


*RV 


(3/2) T - 80 


(3/2) T- 80 


(3/2) T - 90 


Minimum 


*LDR 


(4/2) T - 180 


(4/2) T - 130 


(4/2) T - 159 


Maximum 



NOTE: ' N is equal to the total WAIT states. T = t CY c- 



2-21 



8085AH/8085AH-2/8085AH-1 



WAVEFORMS (Continued) 

READ OPERATION WITH WAIT CYCLE (TYPICAL) — SAME READY TIMING APPLIES 





' \ 

— *LCK -»- 


\ 


\ * 


f \ i 


\ / 

t CA -^1 




ADDRESS 












s 

— t AD 




<RDH *■ 


*RAE ► 

:> — 






ADDRESS 


5 < 




; /////> 


DATA IN 


( 




•* 'la ► 

l AFR -» 


f 

*LDR 












\ 




t R0 

t cc 










- I | 


<LC — 

•* *LRY " 

AC ► 

*ARY 


V 

1, 

■»< *RYS 




*RYM 






mum 


/ 



NOTE 1 READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES 



INTERRUPT AND HOLD 




2-22 



AFN-01835C 



inter 



8085AH/8085AH-2/8085AH-1 



Table 6. Instruction Set Summary 









Instruction Code 




Operations 


Mnemonic 


D 7 D 6 D 5 


P 4 D 3 D 2 Di D 0 


Do script ion 


MOVE, LOAD, AND STORE 












MOVrl r2 


0 


1 


D 


D 


D 


s 


s 


s 


Move register to register 


MOV M.r 


0 


1 


1 


1 


0 


s 


s 


s 


Move register to memory 


MOV r.M 


0 


1 


D 


D 


D 


1 


1 


0 


Move memory to register 


MVI r 


0 


0 


D 


D 


D 


1 


1 


o 


Move immediate register 


MVI M 


0 


0 


1 


1 


0 


1 


1 


o 


Move immediate memory 


LXI B 


0 


0 


0 


0 


o 


o 


o 


1 


Load immediate register 




















Pair B & C 


LXI D 


0 


0 


0 


1 


0 


o 


o 


1 


Load immediate register 




















Pair D & E 


LXI H 


0 


0 


1 


0 


o 


o 


o 


1 


Load immediate register 




















Pair H & L 


STAX B 


0 


0 


0 


0 


0 


o 


1 


o 


Store A indirect 


STAX D 


0 


0 


0 


1 


0 


0 


1 


o 


OlUlt? r\ IllVllltfUl 


LDAX B 


0 


0 


0 


0 


1 


o 


1 


o 


Load A indirect 


LDAX D 


0 


0 


0 


1 


1 


o 


1 


o 


Load A indirect 


STA 


0 


0 


1 


1 


0 


o 


1 


o 


Store A direct 


LDA 


0 


0 


1 


1 


1 


o 


1 


o 


Load A direct 


sHld 


0 


0 


1 


0 


o 


o 


1 


o 


Store H & L direct 


LHLD 


0 


0 


1 


0 


1 


0 


1 


o 


Load H & L direct 


XCHG 


1 


1 


, 1 


0 


1 


o 


1 


1 


Exchange D & E, H & L 




















Registers 


STACK OPS 




















PUSH B 


1 


1 


0 


0 


0 


1 


0 


1 


Push register Pair B & 




















C on stack 


PUSH D 


1 


1 


0 


1 


0 


1 


0 


1 


Push register Pair D & 




















E on stack 


PUSH H 


1 


1 


1 


0 


o 


1 


o 


1 


Push register Pair H & 




















L on stack 


PUSH PSW 


1 


1 


1 


1 


o 


1 


o 


1 


Push A and Flags 




















on stack 


POP B 


1 


1 


0 


0 


o 


o 


0 


1 


Pop register Pair B & 




















C off stack 


POP D 


1 


1 


0 


1 


o 


o 


o 


1 


Pop register Pair D & 




















E off stack 


POP H 


1 


1 


1 


0 


o 


o 


o 


1 


Pop register Pair H & 




















L off stack 


POP PSW 


1 


1 


1 


1 


o 


o 


o 


1 


Pop A and Flags 




















off stack 


XTHL 


1 


1 


1 


0 


0 


0 


1 


1 


Exchange top of 




















stack, H & L 


SPHL 


1 


1 


1 


1 


1 


o 


o 


1 


H & L to stack pointer 


LXI SP 


0 


0 


1 


1 


o 


o 


o 


1 


Load immediate stack 




















pointer 


INX SP 


0 


0 


1 


1 


0 


0 


1 


1 


Increment stack pointer 


DCX SP 


0 


0 


1 


1 


1 


0 


1 


1 






















pointer 


JUMP 




















JMP 


1 


1 


0 


0 


0 


0 


1 


1 


Jump unconditional 


JC 


1 


1 


0 


1 


1 


0 


1 


0 


Jump on carry 


JNC 


1 


1 


0 


1 


0 


0 


1 


0 


Jump on no carry 


JZ 


1 


1 


0 


0 


1 


0 


1 


0 


Jump on zero 


JNZ 


1 


1 


0 


0 


0 


0 


1 


0 


Jump on no zero 


JP 


1 


1 


1 


1 


0 


0 


1 


0 


Jump on positive 


JM 


1 


1 


1 


1 


1 


0 


1 


0 


Jump on minus 


JPE 


1 


1 


1 


0 


1 


0 


1 


0 


Jump on parity even 


JPO 


1 


1 


1 


0 


0 


0 


1 


0 


Jump on parity odd 


PCHL 


1 


1 


1 


0 


1 


0 


0 


1 


H & L to program 




















counter 


CALL 




















CALL 


1 


1 


0 


0 


1 


1 


0 


1 


Call unconditional 


CC 


1 


1 


0 


1 


1 


1 


0 


0 


Call on carry 


CNC 


1 


1 


0 


1 


0 


1 


0 


0 


Call on no carry 









Instruction Code 




Operations 


Mnemonic 


D7 D 6 D 5 D 4 D3 D 2 D 1 


Do 


Description 


CZ 




1 


0 


0 


1 


1 


0 


0 


Call on zero 


CNZ 




1 


0 


0 


0 


1 


0 


0 


Call on no zero 


CP 




1 


1 


1 


0 


1 


0 


0 


Call on positive 


CM 




1 


1 


1 


1 


1 


0 


0 


Call on minus < 


CPE 




1 


1 


0 


1 


1 


0 


0 


Call on parity even 


CPO 




1 


1 


9 


0 


1 


Q 


Q 


Call on Daritv odd 


RETURN 




















RET 




1 


0 


0 


1 


0 


0 


1 


Return 


RC 




1 


0 


1 


1 


0 


0 


0 


Return on carry 


RNC 




1 


0 


1 


0 


0 


0 


0 


Return on no carry 


RZ 




1 


0 


0 


1 


0 


0 


0 


Rsturn on zero 


RNZ 




1 


0 


0 


0 


0 


0 


0 


Return on no zero 


RP 




1 


1 


1 


0 


0 


0 


0 


Return on positive 


RM 




1 


1 


1 


1 


0 


0 


0 


Return on minus 


RPE 




1 


1 


0 


1 


0 


0 


0 


Return on parity even 


RPO 




1 


1 


0 


0 


0 


0 


0 


Return on parity odd 


RESTART 




















RST 




1 


A 


A 


A 


1 


1 




Restart 


INPUT/OUTPUT 


















IN 




1 


0 


1 


1 


0 


1 




Input 


OUT 




1 


0 


1 


0 


0 


1 


1 


Output 


INCREMENT AND DECREMENT 








INR'r 


0 


0 


D 


D 


D 


1 


0 


0 


Increment register 


DCR r 


0 


0 


D 


D 


D 


1 


0 


1 


Decrement register 


INRM 


0 


0 


1 


1 


0 


1 


0 


0 


Increment memory 


DCR M 


0 


0 


1 


1 


0 


1 


0 


1 


Decrement memory 


INX B 


0 


0 


0 


0 


0 


0 


1 


1 


Increment B & C 
registers 


INXD 


0 


0 


0 


1 


0 


0 


1 


1 


Increment D & E 
registers 


INXH 


0 


0 


1 


0 


0 


0 


1 


1 


Increment H & L 
reg isters 


DCX B 


0 


0 


0 


0 


1 


0 


1 


1 


Decrement B & C 


DCXD 


0 


0 


0 


1 


1 


0 


1 


1 


Decrement D & E 


DCX H 


0 


0 


1 


0 


1 


0 


1 


1 


Decrement H & L 


ADD 




















ADD r 


1 


0 


0 


0 


0 


s 


s 


s 


Add register to A 


ADC r 


1 


0 


0 


0 


1 


s 


s 


s 


Add register to A 
with carry 


ADD M 


1 


0 


c 


0 


0 


1 


1 


0 


Add memory to A 


ADC M 


1 


0 


0 


0 


1 


1 


1 


0 


Add memory to A 
with carry 


ADI 


1 


1 


0 


0 


0 


1 


1 


0 


Add immediate to A 


ACI 


1 


1 


0 


0 


1 


1 


1 


0 


Add immediate to A 
with carry 


DAD B 


0 


0 


0 


0 


1 


0 


0 


1 


Add B & C to H & L 


DADD 


0 


0 


0 


1 


1 


0 


0 


1 


Add D & E to H & L 


DADH 


0 


0 


1 


0 


1 


0 


0 


1 


Add H & L to H & L 


DAD SP 


0 


0 


1 


1 


1 


0 


0 


1 


Add stack pointer to 
H & L 


SUBTRACT 




















SUB r 


1 


0 


0 


1 


0 


s 


s 


s 


Subtract register 
from A 


SBB r 


1 


0 


0 


1 


1 


s 


s 


s 


Subtract register from 
A with borrow 


SUBM 


1 


0 


0 


1 


0 


1 


1 


0 


Subtract memory 
from A 


SBB M 


1 


0 


0 


1 


1 


1 


1 


0 


Subtract memory from 
A with borrow 


SUI 


1 


1 


0 


1 


0 


1 


1 


0 


Subtract immediate 
from A 


SBI 


1 


1 


0 


1 


1 


1 


1 


0 


Subtract immediate 
from A with borrow 



2-23 

i 



irrteT 



8085AH/8085AH-2/8085AH-1 



Table 6. Instruction Set Summary (Continued) 







Instruction Code 




Operations 


Mnemonic 


D7 D 6 


D5 


D4 D3 D 2 D-\ D 0 


Description 


LOGICAL 


















ANA r 


1 0 


1 , 


0 


0 


s 


s 


s 


And register with A 


XRAr 


1 , 0 


1 


0 


1 


s 


s 


s 


Exclusive OR register 
with A 


ORA r 


1 0 


1 


1 


0 


s 


s 


s 


OR register with A 


CMP r 


1 " 0 


1 






s 




g 


Compare register with A 


ANAM 


1 0 


1 


0 


0 


1 


1 


0 


And memory with A 


XRAM 


1 .0 


1 


0 


1 


1 


1 


0 


Exclusive OR memory 
with A 


ORAM 


1 0 


1 


1 


0 


1, 


1 


0 


OR memory with A 


CMPM 


1 0 


1 


1 


1 


1 


1 


0 


Compare 
memory with A 


ANI 


1 1 


1 


0 


0 


1 


1 


0 


And immediate with A 


XRI 


1 1 


1 


0 


1 


1 


1 


0 


Exclusive OR immediate 
with A 


ORI 


1 1 


1 


1 


0 


1 


1 


0 


OR immediate with A 


CPI 


1 1 


1 


1 


1 


1 


1 


0 


Compare immediate 
with A 


ROTATE 


















RLC 


0 0 


0 


0 


0 


1 


1 


1 


Rotate A left 


RRC 


0 0 


0 


0 


1 


1 


1 


1 


Rotate A right 


RAL 


0 0 


0 


1 


0 


1 


1 


1 


Rotate A left through 
carry 


RAR 


0 0 


0 


1 


1 


1 


1 


1 


Rotate A right through 
carry 



Mnemonic 


Instruction Code 
D 7 D 6 D 5 D 4 D 3 D 2 t>1 D 0 


OnAratlAiift 
wfjvratiufis 

Description 


SPECIALS 
CMA 

* 

STC 
CMC 

DAA 


0 0 10 1111 

0 0 110 111 
0 0 111111 

0 0 1 0 0 1 1 1 


Complement 
A 

Set carry 

Complement 

carry 

Decimal adjust A 


CONTROL 

El 

Dl 

NOP 
HLT 


1 1 1 1 1 0 1 '1 

11110 0 11 
00000000 
0 1110 110 


Enable Interrupts 
Disable Interrupt 
No-operation 
Halt 


NEW 8085A INSTRUCTIONS 

RIM I 0 0 1 0 0 0 0 0 

SIM 0 0 1 1 0 0 0 0 


Read Interrupt Mask 
Set Interrupt Mask 



NOTES; 

1. DDS or SSS: B 000, C 001, D 010, E011, H 100, L 101, Memory 110, A 111. 

2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags. 



*AII mnemonics copyrighted ©Intel Corporation 1976. 



2-24 

AFN-P1835C 



inteT 



8085AH/8085AH-2/8085AH-1 



WAVEFORMS 



CLOCK 



CLK 
OUTPUT 



READ 



\ i — \_r~\ r — \ / — \ 



X 



A / \ f — \ I V. 



Do " A ° 7 Z5 1 



WRITE 



a /—"^j — v_y — v 



3: 



\ 



HOLD 



(ADDRESS, CONTROLS) 



J \ 



f 



j — \ r 



< 



j 



2-25 



AFN-01835C 




8085A/8085A-2 
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSORS 



Single +5V Power Supply 

100% Software Compatible with 8080A 

1.3 fxs Instruction Cycle (8085A); 
0.8 fxS (8085A-2) 

On-Chip Clock Generator (with External 
Crystal, LC or RC Network) 

On-Chip System Controller; Advanced 
Cycle Status Information Available for 
Large System Control 



Four Vectored Interrupt Inputs (One is 
Non-Maskable) Plus an 8080A- 
Compatible Interrupt 

Serial In/Serial Out Port 

Decimal, Binary and Double Precision 
Arithmetic 

Direct Addressing Capability to 64k 
Bytes of Memory 



The Intel® 8085A is a complete 8 bit parallel Central Processing Unit (CPU). Its instruction set is 100% software compatible 
with the 8080A microprocessor, and it is designed to improve the present 8080A's performance by higher system speed. 
Its high level of system integration allows a minimum system of three IC's [8085A (CPU), 8156(RAM/I0) and 8355/8755A , 
(ROM/PROM/IO)] while maintaining total system expandability. The 8085A-2 is a faster version of the 8085A. 

The 8085A incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provided for the 
8080A, thereby offering a high level of system integration. 

The 8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The 
on-chip address latches of 8 155/81 56/8355/8755 A memory products allow a direct interface with the 8085A. 



I NT A RST6S TRAP 

INTR f RSTSS I RST7S I 



INTERRUPT CONTROL 



r-L L_ 

SERIAL I/O CONTROL 



8 BIT INTERNAL DATA BUS 



I accumulator! 




culSTcr 



MACHINE 

CYCLE 
ENCODING 



STACK POINTER 



PROGRAM COUNTER 



TIMING AND CONTROL 



ADDRESS BUFFER 



3 C 



X1 C 


1 


40 


X 2 C 


2 


39 


RESET OUT C 


3 


38 


SOD C 


4 


37 


SID C 


5 


36 


TRAP C 


6 


35 


RST7 5 C 


7 


34 


RST6.5 C 


8 


33 


RST5.5 C 


9 


32 


INTR' C 




31 


INTA C 


n 8085A 


30 


ADo C 


12 


29 


ADi C 


13 


28 


AD 2 C 


14 


27 


AD 3 C 


15 


26 


AD 4 E 


16 


25 


AD 5 C 


17 


24 


AD6 C 


18 


23 


AD 7 C 


19 


22 


vss C 


20 


21 



TTT 



Figure 1. 8085A CPU Functional Block Diagram 



3 V C C 

3 HOLD 

□ HLDA 

3 CLK (OUT ) 

3 RESET IN 



3 §L 

□ RD 

3 WR 
3 ALE 
3 So 
3 A 15 
3 A 14 
A13 

□ A 12 
3 An 
3 A 10 
3 A 9 
3 A„ 



Figure 2. 8085A Pin 
Configuration 



2-26 



AFN-01242C 



intgl 8085A/8085A-2 



ABSOLUTE MAXIMUM RATINGS* 'NOTICE: Stresses above those listed under "Absolute 

Maximum Ratings" may cause permanent damage to the 

A , „. ~ _, ~ device. This is a stress rating only and functional opera- 
Ambient Temperature Under B.as ^ 0 C to 70 C f/o „ Qf WQ devjcQ flf fhese Qr Qny Qther conditions above 

Storage Temperature . . -65 C to +150 C tnose indicated in the operational sections of this 

Voltage on Any Pin specification is not implied. Exposure to absolute 

With Respect to Ground —0.5V to +7V maximum rating conditions for extended periods may 

Power Dissipation 1.5 Watt affect device reliability. 



D.C. CHARACTERISTICS (T A = 0°C to 70°C, V C c = 0V ±5%, V S s = 0V; unless otherwise specified) 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


V IL 


Input Low Voltage 


-0.5 


+0.8 


V 




V IH 


Input High Voltage 


2.0 


Vrjc+0.5 


V 




Vol 


Output Low Voltage 




0.45 


V 


l 0L = 2mA 


V 0 h 


Output High Voltage 


2.4 




V 


l 0H = -400M 


'cc 


Power Supply Current 




170 


mA 




'lL 


Input Leakage 




±10 


HA 


0^ V, N *sV C c 


Ilo 


Output Leakage 




±10 


MA 


0.45V <V out <V CC 


V tL R 


Input Low Level, RESET 


-0.5 


+0.8 


V 




V,HB 


Input High Level, RESET 


2.4 


V cc +0.5 


V 




Vhy 


Hysteresis, RESET 


0.25 




V 





2-27 



AFN-01242C 



8085A/8085A-2 



A.C. CHARACTERISTICS (T A = o°c to 70°c, v C c = ov ±5%, v ss = ov) 



Symbol 


Parameter 


8085A 121 


8085A-2 12 ! 


Units 


Min. 


Max. 


Mln. 


Max. 


l CYC 


CLK Cycle Period 








<UUU 


ns 


tl 


CLK Low Time (Standard CLK Loading) 


80 




40 




ns 


t 2 


CLK High Time (Standard CLK Loading) 


120 




70 




ns 


tr,tf 


CLK Rise and Fall Time 




30 




30 


ns 


*XKR 


X A Rising to CLK Rising 


30 


120 


30 


100 


ns 


*XKF , 


Xi Rising to CLK Falling 


30 


150 


30 


110 


ns 




A a -15 Valid to Leading Edge of Control™ 


270 




11*1 




ns 


^CL 


A 0 _7 Valid to Leading Edge of Control 


240 




115 




ns 




A 0 _ 15 Valid to Valid Data In 




575 




350 


ns 




Address Float After Leading Edge of 
READ (INTAV 




0 




0 


ns 




A 8 _ 15 Valid Before Trailing Edge of ALE™ 


115 




50 ■ 




ns 


tALL 


A 0 _ 7 Valid Before Trailing Edge of ALE 


do 




50 




ns 


Ury 


READY Valid from Address Valid 




220 




100 


ns 


tr,A 


Address (Aa-15) Valid After Control 


120 




60 




ns 


tec 


Width of Control Low (RD, WR, INTA) 
Edge of ALE 


400 




230 




ns 


t C L 


Trailing Edge of Control to Leading Edge 
of ALE 


50 




25 

„ .„ 




ns 


tow 


Data Valid to Trailing Edge of WRITE 


420 




230 




ns 


^HABE 


HLDA to Bus Enable 




210 




150 


ns 


tHABF 


Bus Float After HLDA 




210 




150 


ns 


^AQK 


HLDA Valid to Trailing Edge of CLK 


110 




40 




ns 


*HDH 


HOLD Hold Time 


0 




0 




ns 


*HDS 


HOLD Setup Time to Trailing Edge of CLK 


170 




120 




ns 


t|NH 


INTR Hold Time 


0 




0 




ns 


t|NS 


INTR, RoT, and TRAP Setup Time to 
Falling Edge of CLK 


160 




150 




ns 




Address Hold Time After ALE 


100 




50 




ns 


tuo 


Trailing Edge of ALE to Leading Edge 
of Control 


130 




60 




ns 


^LCK 


ALE Low During CLK High 


100 




50 




ns 


t|_DR 


ALE to Valid Data During Read 




460 




270 


ns 


^LDW 


ALE to Valid Data During Write 




200 




120 


ns 


t L L 


ALE Width 


140 




80 




ns 


t|.RY 


ALE to READY Stable 




110 




30 


ns 



2-28 



AFN-01242C 



8085A/8085A-2 



A.C. CHARACTERISTICS (Continued) 



Sum hoi 


Pft rtk motor 


8085A13 


8085A-2^ 


Units 


Mln. 


Max. 


Mln. 


Max. 


*RAE 


Trailing Edge of READ to Re-Enabling 
of Address 


150 




90 




ns 




READ (or INTA) to Valid Data 




300 




150 


ns 


*RV 


Control Trailing Edge to Leading Edge 
of Next Control 


400 




220 




ns 


tRDH 


Data Hold Time After READ INTA 1 '* 


0 




0 




ns 


*RYH 


READY Hold Time 


0 




0 




ns 


*RYS 


READY Setup Time to Leading Edge 
of CLK 


110 




100 




ns 


twD 


Data Valid After Trailing Edge of WRITE 


100 




60 




ns 


*WDL 


LEADING Edge of WRITE to Data Valid 




40 


s 


20 


ns 



NOTES: _ 

1. A 8 -A-j5 address Specs apply to IO/M, S 0 , and S-j except Ag-A^ are undefined during T 4 -Te of OF cycle 
whereas IO/M, Sq, andS-| are stable. 

2. Test conditions: t CYC = 320 ns (8085 A)/200ns (8085 A-2); C L = 1 50 pF. 

3. For all output timing where C L = 150pF use the following correction factors: 
25pF< C L < 150 pF: -0.10ns/pF 

150pF< C L < 300 pF: +0.30 ns/pF 

4. Output timings are measured with purely capacitive load. 

5. All timings are measured at output votage V L =* 0.8V, V H = 2.0V, and 1.5V with 20ns rise and fall time on inputs. 

6. To calculate timing specifications at other values of t^yc use Table 7. 

7. Data hold time is guaranteed under all loading conditions. 



A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 



INPUT/OUTPUT 



X^> TEST POINTS <^ V 

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 0 45V FOR 
A LOGIC "0 " TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC "1" 
AND 0.8V FOR A LOGIC "0 " 



DEVICE 
. UNDER 
TEST 



"T 
I 



C u = 150 pF 



C L = 150 pF 

C u INCLUDES JIG CAPACITANCE 



2-£9 



81 55H/81 56H/81 55H-2/81 56H-2 
2048-BIT STATIC HMOS RAM 
WITH I/O PORTS AND TIMER 



■ Single +5V Power Supply with 10% 
Voltage Margins 

■ 30% Lower Power Consumption than 
the 8155 and 8156 

■ 100% Compatible with 8155 and 8156 

■ 256 Word x 8 Bits 

■ Completely Static Operation 

■ Internal Address Latch 

■ 2 Programmable 8-Bit I/O Ports 



■ 1 Programmable 6-Bit I/O Port 

■ Programmable 14-Bit Binary Counter/ 
Timer * 

■ Compatible with 8085AH, 8085A and 
8088 CPU 

■ Multiplexed Address and Data Bus 

■ Available in EXPRESS 

- Standard Temperature Range 

- Extended Temperature Range 



The Intel® 8155H and 8156H are RAM and I/O chips Implemented in N-Channel, depletion load, silicon gate technology 
(HMOS), to be used in the 8085AH and 8088 microprocessor systems. The RAM portion is designed with 2048 static cells 
organized as 256 x 8. They have a maximum access time of 400 ns to permit use with no wait states in 8085AH CPU.The 
8155H-2 and 8156H-2 have maximum access times of 330 ns for use with the 8085AH-2 and the 5 MHz 8088 CPU. 

The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status 
pins, thus allowing the other two ports to operate in handshake mode. 

A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse 
for the CPU system depending on timer mode. 



■<=> 



WR- 
RESET- 



256 X 8 
STATIC 
RAM 



^PORTAK 
PORT 



V^-v> PC " 



TIMER CLK — 



*8155H/8155H-2 = CE, 8156H/8156H-2 «= CE 



V cc (+5V) 
V ss (0V) 



pc 3 


C 


1 




40 


D 


v cc 


pc 4 


C 


2 




39 


3 


pc 2 


TIMER IN 


c 


3 




38 


3 


PC, 


RESET 


c 


4 




37 


2 




p c 5 


c 


5 




36 


3 


pb 7 


TIMEROUT 


c 


6 




35 


3 




IO/M 


c 






34 


3 


p B 5 


CEORCE* 


c 


8 




33 


3 


PB 4 


RD 
WR 


c 
c 


9 
10 


8155H/ 
8156H 


32 
31 


3 
3 


PB 3 
PB 2 


ALE 
AD Q 


c 
c 


11 

12 


8155H-2/ 
8156H-2 


30 
29 


3 
3 


PB, 
PB 0 


AD, 


c 


13 




28 


3 


PA 7 


AD 2 


c 


14 




27 


3 


p A 6 


AD 3 


c 


15 




26 


3 


PA 5 


AD 4 


c 


16 




25 


3 


PA 4 


, AD 5 


c 


17 




24 


3 


PA 3 


AD 6 


c 


18 




23 


3 


PA 2 


AD ? 


c 


19 




22 


3 


PA, 


v ss 


c 


20 




21 


3 


PA 0 



Figure 1. Block Diagram Figure 2. Pin Configuration 

Intel Corporation Assumes No Responsibly for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied. 
©INTEL CORPORATION, 1981. 2-30 




81 55H/81 56H/81 55H-2/81 56H-2 



Table 1 . Pin Description 



Symbol 


Type 


Name and Function 


RESET 


I 


Reset: Pulse provided by the 8085AH to initialize the system (connect to 8085AH RESET OUT). Input 
high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET 
pulse should typically be two 8085AH clock cycle times. 


AD 0 _7 


I/O 


Address/Data: 3-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. 
The 8-bit address is latched into the address latch inside the 81 55H/56H on the falling_edge of ALE. The 
address can be either for the memory section or the I/O section depending on the IO/M input. The 8-bit 
data is either written into the chip or read from the chip, depending on the WR or RD input signal. 


= 

CE or CE 


I 


Chip Enable: On the 8155H, this pin is CE and is ACTIVE LOW. On the 8156H, this pin is CE and is 
ACTIVE HIGH. 


RD 


I 


Read Control: Input low on this line with the Chip Enable active enables and AD 0 _7 buffers. If IO/M pin 
is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or 
command/status registers will be read to the AD bus. 


WR 


I 


Write Control: Input low on this line with the Chip Enable active causes the data on the Address/Data 
bus to be written to the RAM or I/O ports and command/status register, depending on IO/M. 


ALE 


I 


Address Latch Enable: This control signal latches both the address on the AD 0 _7 lines and the state 
of the Chip Enable and IO/M into the chip at the falling edge of ALE. 


IO/M 


I 


I/O Memory: Selects memory if low and I/O and command/status registers if high. 


PA 0 - 7 (8) 


I/O 


Port A: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming 
the command register. 


PB 0 - 7 (8) 


I/O 


Port B: These 8 pins are general purpose I/O pins The in/out direction is selected by programming 
the command register 


r M)-5\ 0 / 


I/O 


Port fV Thpcp fi nine ran fimrtmn acoithor inni it nnrt rti itm it nrtrt nr ac rrintrnl cinnalcfnr PA anrl PR 
rui i w . ii iGoc? ufjiiioisCiii luiivsiiuii cio ciiiid ni|jui ^jui i, uuifjui }Jwi i, ui do isL/iiiiwi oi^i 1010 i ui rn ell iu r D . 

Programming is done through the command register. When PC0-5 are used as control signals, they 

will provide the following: 

PCq — A INTR (Port A Interrupt) 

PC1 — ABF (Port A Buffer Full) 

PC 2 — A STB (Port A Strobe) 

PC 3 — B INTR (Port B Interrupt) 

PC 4 — B BF (Port B Buffer Full) 

PC 5 — B STB (Port B Strobe) 


TIMER IN 


I 


Timer Input: Input to the counter-timer. 


TIMER OUT 


0 


Timer Output: This output can be either a square wave or a pulse, depending on the timer mode. 


v C c 




Voltage: +5 volt supply. 


v ss 




Ground: Ground reference. 



FUNCTIONAL DESCRIPTION 

The 8155H/8156H contains the following: 

• 2k Bit Static RAM organized as 256 x 8 

• Tw6 8-bit I/O ports (PA & PB) and one 6-bit I/O port ( PC ) 

• 14-bit timer-counter 

The IO/M (IO/Memory Select) pin selects either the five 
registers (Command, Status, PA0-7, PB0-7, PC0-5) or 
the memory (RAM) portion. 

The 8-bit address on the Address/Data lines, Chip Enable 
input CE or CE, and IO/M^re all latched on-chip at the 
falling edge of ALE 



7v 



7v 



8 BIT INTERNAL DATA BUS 



I 



7> 



7v 



77 



V V 



TIMER 
MODE 



TV 



.v.. , 

PC 




PB 






PA 






TIMER 
MSB 


TIMER 
LSB 






S\ 









: I 



Figure 3. 8155H/8156H Internal Registers 



2-31 



AFN-01960C 



81 55H/81 56H/81 55H-2/81 56H-2 



CE (8155H) \ 

\ 

CE(S1S6H) / 




/ 












\ 


/ 








y 

IO/M \ 
\ > 


/ 


\ 




> < 




AD 0-7 ^ 


ADDRESS 


DATA VALID ^ ^ 










/ 


\ 


/ 










RD OR WR 




\ 


/ 



NOTE: FOR DETAILED TIMING INFORMATION, SEE FIGURE 12 AND A.C. CHARACTERISTICS 



Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle 



jTM 2 [TMi| IEB[ IEA[ PC 2 | PCt | PB | PA j 

J I u 



DEFINES PA0.7 
DEFINES PB0-7 



0 = INPUT 

1 = OUTPUT 



00 = ALT 1 
11 = ALT 2 

01 = ALT 3 
10 = ALT 4 



. ENABLE PORT A 
INTERRUPT 

ENABLE PORT B 
' INTERRUPT 



1 = ENABLE 
0 = DISABLE 



►TIMER COMMAND— 



00 = NOP - DO NOT AFFECT COUNTER 

6PERATION 

01 = STOP - NOP IF TIMER HAS NOT STARTED; 

STOP COUNTING IF THE TIMER IS 
RUNNING 

10 = STOP AFTER TC - STOP IMMEDIATELY 

AFTER PRESENT TC IS REACHED (NOP 
IF TIMER HAS NOT STARTED) 

11 = START - LOAD MODE AND CNT LENGTH 

AND START IMMEDIATELY AFTER 
LOADfNG (IF TIMER IS NOT PRESENTLY 
RUNNING) IF TIMER IS RUNNING, START N 
THE NEW MODE AND CNT LENGTH 
IMMEDIATELY AFTER PRESENT TC 
IS REACHED 



PROGRAMMING OF THE 
COMMAND REGISTER 

The command register consists of eight latches. Four 
bits (0-3) define the mode of the ports, two bits (4-5) 
enable or disable the interrupt from port C when it acts 
as control port, and the last two bits ( 6-7 ) are for the timer. 

The command register contents can be altered at any 
time by using the I/O address XXXXX000 durm£a WRITE 
operation with the Chip Enable active and IO/M = 1. The 
meaning of each bit of the command byte is defined in 
Figure 5. The contents of the command register may 
never be read. 



READING THE STATUS REGISTER 

The status register consists of seven latches, one for each 
bit, six (0-5) for the status of the ports and one (6) for the 
status of the timer. 

The status of the timer and the I/O section can be polled 
by reading the Status Register (Address XXXXX000). 
Status word format is shown in Figure 6. Note that you 
may never write to the status register since the command 
register shares the same I/O address and the command 
register is selected when a write to that address is issued. 



Figure 5. Command Register Bit Assignment 



2-32 



AFN-Q1960C 



inteT 



81 55H/81 56H/81 55H-2/81 56H-2 



AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 ADt ADq 



PORT A INTERRUPT REQUEST 

PORT A BUFFER FULL/EMPTY 
(INPUT/OUTPUT) 

PORT A INTERRUPT ENABLE 

PORT B INTERRUPT REQUEST 

PORT B BUFFER FULL/EMPTY 
(INPUT/OUTPUT) 

PORT B INTERRUPT ENABLED 

TIMER INTERRUPT (THIS BIT 
IS LATCHED HIGH WHEN 
TERMINAL COUNT IS 
REACHED, AND IS RESET TO 
LOW UPON READING OF THE 
C/S REGISTER AND BY 
HARDWARE RESET) 



Both registers are 
The C/S address 



Figure 6. Status Register Bit Assignment 



INPUT/OUTPUT SECTION 

The I/O section of the 8155H/8156H consists of five regis- 
ters: (See Figure 7.) 

• Command/Status Register (C/S) - 

assigned the address XXXXX000. 
serves the dual purpose. 

When the C/S registers are selected during WRITE 
operation, a command is written into the command 
register. The contents of this register are not accessible 
through the pins. 

When the C/S (XXXXXOOO) is selected during a READ 
operation, the status information of the I/O ports and 
the timer becomes available on the ADo-7 lines. 

• PA Register — This register can be programmed to be 
either input or output ports depending on the status of 
the contents of the C/S Register. Also depending on 
the command, this port can operate in either the basic 
mode or the strobed mode (See timing diagram). The 
I/O pins assigned in relation to this register are PAo-7. 
The address of this register is XXXXX001. 

• PB Register — This register functions the same as PA 
Register. The I/O pins assigned are PB0-7. The address 
of this register is XXXXX010. 

• PC Register — This register has the address XXXXXOT 1 
and contains only 6 bits. The 6 bits can be program- 
med to be either input ports, output ports or as control 
signals for PA and PB by properly programming the 
AD2 and AD3 bits of the C/S register. 

When PC0-5 is used as a control port, 3 bits are 
assigned for Port A and 3 for Port B. The first bit is an 



interrupt that the 8155H sends out. The second is an 
output signal indicating whether the buffer is full or 
empty, and the third is an input pin to accept a strobe 
for the strobed input mode. (See Table 2.) 

When the 'C port is programmed to either ALT3 or ALT4, 
the control signals for PA and PB are initialized as follows: 



CONTROL 


INPUT MODE 


OUTPUT MODE 


BF 


Low 


Low 


INTR 


Low 


High 


STB 


Input Control 


Input Control 



I/O ADDRESS 1 


SELECTION 


A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 


X 


X 


X 


X 


X 


0 


0 


0 


Interval Command/Status Register 


X 


X 


X 


X 


X 


0 


0 


1 


General Purpose I/O Port A 


X 


X 


X 


X 


X 


0 


1 


0 


General Purpose I/O Port B 


X 


X 


X 


X 


X 


0 


1 


1 


Port C — General Purpose I/O or Control 


X 


X 


X 


X 


X 


1 


0 


0 


Low-Order 8 bits of Timer Count 


X 


X 


X. 


X 


X 


1 


0 


1 


High 6 bits of Timer Count and 2 bits 


















of Timer Mode 



X Don't Care 

t I/O Address must be qualified by CE = 1 (8156H) or CE = 0 (8155H) and IO/M = 1 in 
order to select the appropriate register 



Figure 7. I/O Port and Timer Addressing Scheme 



Figure 8 shows how I/O PORTS A and B are structured 
within the 8155H and 8156H: 



8155H/8156H 
ONE BIT OF PORT A OR PORT B 



OUTPUT 
LATCH 



5 



OUTPUT 
ENABLE 



<2 



) (2) | 



CLK 



STB 



NOTES- 

(3) STROBED INPUT J C0NTR0L 
READ PORT = (lO/Mf 1) • (RDfO) • {CE ACTIVE) • (PORT ADDRESS SELECTED) , 
WRITE PORT= (IO/M=1) • (WR=0) • (CE ACTIVE) • (PORT ADDRESS SELECTED) 



(4) = 1 FOR OUTPUT MODE 
= 0 FOR INPUT MODE 



Figure 8. 8155H/8156H Port Functions 



2-33 



AFN-0T960C 



81 55H/81 56H/81 55Ht 2/81 56H-2 



Table 2. Port Control Assignment 



Pin 


ALT 1 


ALT 2 


ALT 3 


ALT 4 


PCO 


Input Port 


Output Port 


A INTR (Port A Interrupt) 


A INTR (Port A Interrupt) 


PC1 


Input Port 


Output Port 


A BF (Port A Buffer Full) 


A BF (Port A Buffer Full) 


PC2 


Input Port 


Output Port 


A STB (Port A Strobe) 


A STB (Port A Strobe) 


PC3 


Input Port 


Output Port 


Output Port 


B INTR (Port B Interrupt) 


PC4 


Input Port 


Output Port 


Output Port 


B BF (Port B Buffer Full) 


PC5 


Input Port 


Output Port 


Output Port 


B STB (Port B Strobe) 



Note in the diagram that when the I/O ports are pro- 
grammed to be output ports, the contents of the output 
ports can still be read by a READ operation when appro- 
priately addressed. 

The outputs of the 81 55H/81 56H are "glitch-free" meaning 

that you can write a "1" to a bit position that was previ- 
ously "1" and the level at the output pin will not change. 

Note also that the output latch is cleared when the port 
enters the input mode. The output latch cannot be loaded 
by writing to the port if the port is in the input mode. The 
result is that each time a port mode is changed from input 
to output, the output pins will go low. When the 81 55H/56H 
is RESET, the output latches are all cleared and all 3 ports 
enter the input mode. 

When in the ALT 1 or ALT 2 modes, the bits of PORT C 
are structured like the diagram above in the simple input 
or output mode, respectively. , 

Reading from an input port with nothing connected to the 
pins will provide unpredictable results. 

Figure 9 shows how the 8155H/8156H I/O ports might be 
configured in a typical MCS-85 system, 



8155H/8156H 

' PORTC- 



TO 8085AH RST INPUT 



A INTR (SIGNALS DATA RECEIVED) 



A BF (SIGNALS DATA READY) 



A STB (ACKNOWL DATA RECEIVED) 



_ B STB (LOADS PORT B LATCH) 



B BF (SIGNALS BUFFER IS FULL) 



B INTR (SIGNALS BUFFER 



READY FOR READING) 



TO/FROM 
-PERIPHERAL 
INTERFACE 



TO INPUT PORT (OPTIONAL) 
TO 8085AH RST INPUT 



TIMER SECTION 

The timer is a 14-bit down-counter that.counts the TIMER 
IN pulses and provides either a square wave or pulse 
when terminal count (TO is reached. 

The timer has the I/O address XXXXX1 00 for the low order 
byte of the register and the I/O address XXXXX101 for 
the high order byte of the register. (See Figure 7.) 

To program the timer, the COUNT LENGTH REG is 
loaded first, one byte at a time, by selecting the timer 
addresses. Bits 0-13 of the high order count register will 
specify the length of the next count and bits .14-15 of the 
high order register will specify the timer output mode 
(see Figure 10). The value loaded into the count length 
register can have any value from 2H through 3FFH in 
Bits 0-13. 



7 


6 


5 


4 


3 


2 


1 


0 




M 2 


Mi 


T13 




Tn 


Tio 


T 9 


T 8 


I 


1 1 












TIMER MODE 


MSB OF CNT LENGTH 






6 


5 


4 


3 


2 


,1 


0 


I" 




T 5 


T 4 


T 3 




T^ 


To 


I 

















LSB OF CNT LENGTH 



Figure 10. Timer Format 

There are four modes to choose from: M2 and M1 define 
the timer mode, as shown in Figure 1 1 . 



TIMER OUT WAVEFORMS 



MODE 
BITS 



START 
COUNT 



\ SINGLE 

SQUARE WAVE 



2 CONTINUOUS 
SQUARE WAVE 



3 SINGLE 
PULSE ON 
TERMINAL COUNT 

4 CONTINUOUS 
PULSES 



TERMINAL / TERMINAl\ 
COUNT ^ COUNT ) 

\ 




~U — 



IT 



Figure 9. Example: Command Register = 00111001 



Figure 11. Timer Modes 



2-34 



intef 



81 55H/81 56H/81 55H-2/81 56H-2 



Bits 6-7 (TM2 and'TMi) of command register contents 
are used to start and stop the counter. There are four 
commands to choose from: 



TM2 
0 
0 

1 



TM1 
0 
1 



NOP — Do not affect counter operation. 

STOP — NOP if timer has not started.; 
stop counting if the timer is running. 

STOP AFTER TC — Stop immediately 
after present TC is reached ( NOP if timer 
has not started ) 

START — Load mode and CNT length 
and start immediately after loading (if 
timer is not presently running). If timer 
is running, start the new mode and CNT 
length immediately after present TC is 
reached. 



Note that while the counter is counting, you may load a 
new count and mode into the count length registers. 
Before the new count and mode will be used by the 
counter, you must issue a START command to the 
counter. This applies even though you may only want to 
change the count and use the previous mode. 

In case of an odd-numbered count, the first half-cycle 
of the squarewave output, which is high, is one count 
longer than the second (low) half-cycle, as shown in 
Figure 12. 



I 



NOTE 5 AND 4 REFER TO THE NUMBER OF CLOCKS IN THAT TIME PERIOD 



The counter in the 81 55H is not initialized to any particular 
mode or count when hardware RESET occurs, but RESET 
does stop the counting. Therefore, counting cannot begin 
following RESET until a START command is issued via the 
C/S register. 

Please note that the timer circuit on the 81 55H/81 56H chip 
is designed to be a square-wave timer, not an event 
counter. To achieve this, it counts down by twos twice 
in completing one cycle. Thus, its registers do not con- 
tain values directly representing the number of TIMER IN 
pulses received. You cannot load an initial value of 1 into 
the count register and cause the timer to operate, as its 
terminal count value is 10 (binary) or 2 (decimal). (For 
the detection of single pulses, it is suggested that one 
of the hardware interrupt pins on the 8085AH be used.) 
After the timer has started counting down, the values 
residing in the count registers can be used to calculate 
the actual number of TIMER IN pulses required to com- 
plete the timer cycle if desired. To obtain the remaining 
count, perform the following operations in order: 

1. Stop the count 

2. Read in the 16-bit value from the count length registers 

3. Reset the upper two mode bits 

4. Reset the carry and rotate right one position all 16 bits 
through carry 

5. If carry is set, add 1/2 of the full original count (1/2 full 
count — 1 if full count is odd). 



Note: If you started with an odd count and you read the 
count length register before the third count pulse occurs, 
you will not be able to discern whether one or two counts 
has occurred. Regardless of this, the 8155H/56H always 
counts. out t he right number of pulses in generating the 
TIMER OUT waveforms. 



Figure 12. Asymmetrical Square- Wave Output 
Resulting from Count of 9 



2-35 



AFN-01960C 



81 55H/8156H/8155H-2/81 56H-2 



8085A MINIMUM SYSTEM CONFIGURATION 

Figure 13a shows a minimum system using three chips, 
containing: 

• 256 Bytes RAM 

• 2K Bytes ROM 

• 38 I/O Pins 

• 1 Interval Jimer 

• 4 Interrupt Levels 



8085 MINIMUM SYSTEM CONFIGURATION 



TIMER 
OUT 



256 x 8 
RAM 















j PC | | P 


B | | PA | 



7V 



RDIOW CLK 



8355 | ROM + I/O | 
OR 

8755 A [PROM + I/O] 



1(6)1 1(8)1 1(8)1 



Figure 13a. 8085AH Minimum System Configuration (Memory Mapped I/O) 



2-36 



AFN-01960C 



intel 



81 55H/81 56H/81 55H-2/81 56H-2 



8088 FIVE CHIP SYSTEM • 38 I / O Pins 

Figure 13b shows a five chip system containing: * 1 ,nterval Timer 

• 1.25K Bytes RAM * 2 Interrupt Levels 

• 2k Bytes ROM 




CLK 
READY 



8284 
RESET 



As— A19 



8088 
READY 

MN/MX 
ALE 

RST /jn RD 



r-RST^ 



WR 

IO/M 



GND 

(V SS ) 



MANUAL 
RESET 



Vcc 



-6 



c 



<: 



V 7 \7 



CE 


PORT 


WR 






PORT 


RD 




8155H-2 


ALE 


PORT 


DATA/ 




ADDR 






IN 


IO/M 


TIMER 


RESET 


OUT 



IOW 
RD 
ALE 
CE 



A 8-10 
8355-2/ 
8755A-2 

~N DATA/ 
-I,/ ADDR 



IO/M PORT 
RESET B 
READY 

io"R 



Vcc 
_J 



■I L 



V SS V CC V DD 



V 



WR 
RD 

CEi 

818 

ALE 

£s\ 

CE 2 
A 6 ,A 9 



AD, 



'0-7 



V ss Vcc 



Figure 13b. 8088 Five Chip System Configuration 

2437 



AFN-01960C 



8155H/8156H/8155H-2/8156H-2 



ABSOLUTE MAXIMUM RATINGS* *NOTICE: Stresses above those listed Orider "Absolute 



Maximum Ratings" may cause permanent damage to the 
device. This is a stress, rating only and functional opera- 
Temperature Under Bias 0°C to +70° C tion of the device at these or any other conditions above 

Storage Temperature . -65°Cto +150°C those indicated in the operational sections of this 

Voltage on Any Pin specification is not implied. Exposure to absolute maxi- 

With Respect to Ground -0.5V to +7V mum rating conditions for extended periods may affect 

Power Dissipation 1.5W device reliability. 



D.C. CHARACTERISTICS (T A = o°c to 70°c, v cc = sv ± 10%) 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 




V, H 


Input High Voltage 


2.0 


V CC +0-5 


V 




Vol 


Output Low Voltage 




0.45 


V 


lOL = 2mA 


Voh 


Output High Voltage 


2.4 




V 


Iqh = -400juA 


IlL 


Input Leakage 




±10 


MA 


0V^ V, N V C c 




Output Leakage Current 




±10 




0.45V < V 0 UT < Vcc 


Ice 


Vcc Supply Current 




125 


mA 




Iil(CE) 


Chip Enable Leakage 
8155H 
8156H 




+100 
-100 


MA 

ma 


0V V, N =s v cc 



A.C- CHARACTERISTICS (T A = o°c to 70°c, v cc = 5V ±10%) 





8155H/8156H 


8155H-2/8156H-2 




Symbol 


Parameter 


Min. 


Max. 


Min. 


Max. 


Units 


tAL 


Address to Latch Set Up Time 


50 




30 




ns 


tLA 


Address Hold Time after Latch 


80 




30 




ns 


tLC 


Latch to READ/WRITE Control 


100 




40 




ns 


*RD 


Valid Data Out Delay from READ Control 




170 




140 


ns 


tAD 


Address Stable to Data Out Valid 




400 




330 


ns 


tLL 


Latch Enable Width 


100 




70 




ns 


tRDF 


Data Bus Float After READ 


0 


100 


0 


80 


ns 


tCL 


READ/WRITE Control to Latch Enable 


20 




10 




ns 


tec 


READ/WRITE Control Width 


250 




200 




ns 


tow 


Data In to WRITE Set Up Time 


150 




100 




ns 


two 


Data In Hold Time After WRITE 


25 




25 




ns 


tRV 


Recovery Time Between Controls 


300 




200 




ns 


twp 


WRITE to Port Output 




400 




300 


ns 


tPR 


Port Input Setup Time 


70 




50 




ns 


tRP 


Port Input Hold Time 


50 




10 




ns 


tSBF 


Strobe to Buffer Full 




400 




300 


ns 


tss 


Strobe Width 


200 




150 




ns 


tRBE 


READ to Buffer Empty 




400 




300 


ns 


tsi 


Strobe to INTR On 




400 




300 


hs 



2-38 



AFN-01960C 



inteT 



81 55H/81 56H/81 55H-2/81 56H-2 



A.C. CHARACTERISTICS (Continued) (T A = 0°C to 70°C, V cc = 5V : 



:10%] 





8155H/8156H 


8155H-2/8156H-2 




Symbol 


Parameter 


Mln. 


Max. 


Min. 


Max. 


Units 


tRDI 


READ to INTR Off 




400 




300 


ns 


tpss 


Port Setup Time to Strobe Strobe 


50 




. 0 




ns 


tPHS 


Port Hold Time After Strobe 


120 




100 




ns 


tSBE 


Strobe to Buffer Empty 




400 




300 




t WBF 


WRITE to Buffer Full 




400 




300 


ns 


*WI 


WRITE to INTR Off 




400 




300 


ns 


tTL 


TIMER-IN to TIMER-OUT Low 




400 




300 


ns 


tTH 


TIMER-IN to TIMER-OUT High 




400 




300 


ns 


*RDE 


Data Bus Enable from READ Control 


10 




10 




ns 


tl 


TIMER-IN Low Time 


80 




40 




ns 


t 2 


TIMER-IN High Time 


120 




70 




ns 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



INPUT/OUTPUT 




^> TEST POINTS <^ 



AC TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR 
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC 1 
AND 0 8V FOR A LOGIC 0 . 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 



"1 
1 



C L = 150 pF 



C L = 150 pF 

C L INCLUDES JIG CAPACITANCE 



WAVEFORMS 



READ 



CE(8155H) 

OR 
CE(8156H) 



r 



T 



> <y ^ DATA VALID ^ ^ 



RD 



tRD- 



y 



- L 



2-39 



AFN-01960C 



8155H/8156H/8155H-2/8156H-2 



WAVEFORMS (Continued) 



WRITE 

CE(8155H) 

OR 
CE (8156H) 



\ 



/ \ 



z 



z 



X 



DATA VALID 



/ 



STROBED INPUT 



STROBE 



INPUT DATA 
FROM PORT 




2-40 



AFN-01960C 



irrteT 



81 55H/81 56H/81 55H-2/81 56H-2 



WAVEFORMS (Continued) 



STROBED OUTPUT 



OUTPUT DATA 
TO PORT 



\J—T 



Z 



BASIC INPUT 



■ \- - 



x 



l RP f* 

J 



ZZZZZDC 



BASIC OUTPUT 



— — \_ 
ZZZZZZX1 



•DATA BUS TIMING IS SHOWN IN FIGURE 7 



€1 



TIMER OUTPUT COUNTDOWN FROM 5 TO 1 



LOAD COUNTER FROM CLR 




2-41 



8155/8156/8155-2/8156-2 
2048 BIT STATIC MOS RAM WITH I/O PORTS AND TIMER 

■ 256 Word x 8 Bits 

■ Single +5V Power Supply 

■ Completely Static Operation 

■ Internal Address Latch 

■ 2 Programmable 8 Bit I/O Ports 



■ 1 Programmable 6-Bit I/O Port 

■ Programmable 14-Bit Binary Counter/ 
Timer 

■ Compatible with 8085A and 8088 CPU 

■ Multiplexed Address and Data Bus 

■ 40 Pin DIP 



The 8155 and 8156 are RAM and I/O chips to be used in the 8085A and 8088 microprocessor systems. The RAM portion 
is designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit use with 
no wait states in 8085A CPU. The 81 55-2 and 81 56-2 have maximum access times of 330 ns for use with the 8085 A-2 and the 
5 MHz 8088 CPU. 

The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status 
pins, thus allowing the other two ports to operate in handshake mode. 

A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse 
for the CPU system depending on timer mode. 



D - < v=i > 



WR- 
RESET- 



256 X 8 
STATIC 
RAM 



| TIMER | 



y1 P0RTA K 

V±v PA ^ 7 

PORT 



V 



r 



V cc (+5V) 
V ss (0V) 



* 8155/8155-2 = CE, 8156/8156-2 = CE 



PC 3 

pc 4 

TIMER IN 
RESET 

PC5 

TIMER OUT 
IO/M 
CEORCE* 
RD 
WR 
ALE 
AD 0 
AD, 
AD 2 
AD 3 
AD 4 
AD 5 
AD 6 
AD 7 

Vcc 



C 1 

C 2 

C 3 

C 4 

C 5 

C 6 

C 7 

C 8 

C 9 

c 
c 
c 
c 
c 
c 
c 
c 
c 
c 
c 



40 

39 
38 
37 
36 
35 
34 
33 
32 

8155/ 
8156 J1 

8155- 2/ 30 

8156- 2 29 

28 
27 
26 
25 
24 
23 
22 
21 



□ V C C 

1 pc 2 
D pc, 
3 pc 0 

□ PB 7 

3 pb 6 
3 pb 5 
3 pb 4 
3 pb 3 

□ PB 2 

3 pb, 
3 pb 0 
3 pa 7 
3 pa § 
13 pa 5 
3 pa 4 
3 pa 3 
3 pa 2 

□ PA, 

3 pAq 



Figure 1. Block Diagram 



Figure 2. Pin Configuration 



2-42 



AFN-00201D 



8155/8156/8155-2/8156-2 



ABSOLUTE MAXIMUM RATINGS* 'NOTICE: Stresses above those listed under "Absolute 



Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
Temperature Under Bias 0° C to +70° C tion of the device at these or any other conditions above 

Storage Temperature -65°Cto+150°C those indicated in the operational sections of this 

Voltage on Any Pin specification is not implied. Exposure to absolute maxi- 

With Respect to Ground -0.5V to +7V mum rating conditions for extended periods may affect 

Power Dissipation 1.5W device reliability. 



D.C. CHARACTERISTICS (T A - o°c to 70°C; v cc - 5V ± 5%) 



SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 




V| H 


Input High Voltage 


2.0 


Vcc+0.5 


V 




Vol 


Output Low Voltage 




0.45 


V 


Iql = 2mA 




Output High Voltage 


2.4 




V 


Iqh = -400/iA 




Input Leakage 




±10 


JLtA 


0V V| N *s V C c 


Ilo 


Output Leakage Current 




±10 


MA 


0.45V < VouT < Vcc 


•cc 


Vcc Supply Current 




180 


mA 




Iil(CE) 


Chip Enable Leakage 
8155 
8156 




+100 
-100 


MA 

ma 


0V V, N < V CC 



2-43 



AFN-Q02Q1D 



8155/8156/8155-2/8156-2 



A.C. CHARACTERISTICS <t a = o°c to 70°c ; v cc - 5V ± 5%) 





8155/8156 


8155-2/8156-2 




J SYMBOL 


PARAMETER 


MIN. 


MAX. 


MIN. 


MAX. 


UNITS 


tAL 


Address to Latch Set Up Time 


50 




30 




ns 


tLA 


Address Hold Time after Latch 


80 




30 




ns 


tLC 


Latch to READ/WRITE Control 


100 




40 




ns 


*RD 


Valid Data Out Delay from READ Control 




170 




140 


ns 


1-AD 


Address Stable to Data Out Valid 




400 




330 


ns 


t|_L 


Latch Enable Width 


100 




70 




ns 


T.RDF 


Data Bus Float After, READ 


0 


100 


0 


80 


ns 


*CL 


READ/WRITE Control to Latch Enable 


20 




10 




ns 


tfJC 


READ/WRITE Control Width 


250 




200 




ns 


tow 


Data In to WR ITE Set Up Time 


150 




100 




ns 


tyVD 


Data In Hold Time After WRITE 


25 




25 




ns 


f-R V 


Recovery Time Between Controls 


300 




200 




ns 


tyyp 


WRITE to Port Output 




400 




300 


ns 


tpp 


Port Input Setup Time 


70 




50 




ns 


tRp 


Port Input Hold Time 


50 




10 




ns 


tsBF 


Strobe to Buffer Full 




400 




300 


ns 


tss 


Strobe Width 


200 




150 




ns 


tRBE 


R EAD to Buffer Empty 




400 




300 


ns 


tsi f 


Strobe to INTR On 




400 




300 


ns , 


T-RDI 


READ to INTR Off 




400 




300 


ns 


tpss 


Port Setup Time to Strobe Strobe 


50 




0 




ns 


tPHS 


Port Hold Time After Strobe 


120 




100 




ns 


tSBE 


Strobe to Buffer Empty 




400 




300 


ns 


tWBF 


WRITE to Buffer Full 




400 




300 


ns 


*WI 


WRITE to INTR Off 




400 




300 


ns 


tTL 


TIMER-IN to TIMER-OUT Low 




400 




300 


ns 


tTH 


TIMER-IN to TIMER-OUT High 




400 




300 


ns 


tRDE 


Data Bus Enable from READ Control 


10 




10 




ns 


tl 


TIMER-IN Low Time 


80 




40 




ns 


t 2 


TIMER-IN High Time 


120 




70 




ns 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



A.C. TESTING LOAD CIRCUIT 



INPUT/OUTPUT 




TEST POINTS 




A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 " AND 0 45V FOR 
A LOGIC 0 ' TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC 1 
AND 0 8V FOR A LOGIC 0 



DEVICE 
UNDER 
TEST 



"T 
I 



C L = 150 pF 



C L = 150 pF 

C L INCLUDES JIG CAPACITANCE 



2-44 



AFN-00201P 



8185/8185-2 
1024 x 8-BIT STATIC RAM FOR MCS-85* 



m Multiplexed Address and Data Bus 

m Directly Compatible with 8085A 
and iAPX 88 Microprocessors 

■ Low Operating Power Dissipation 



■ Low Standby Power Dissipation 

■ Single +5V Supply 

■ High Density 18-Pin Package 



The Intel® 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using N-channel 
Silicon-Gate MOS technology. The multiplexed address and data bus allows the 81 85 to interface directly to the 8085A and 
iAPX 88 microprocessors to provide a maximum level of system integration. 

The low standby power dissipation minimizes system power requirements when the 8185 is disabled. 

The 81 85-2 is a high-speed selected version of the 81 85 that is compatible with the 5 MHz 8085A-2 and the5 MHz iAPX 88. 



cs - 

CE, - 
CE 2 - 
RD - 
WR - 



AD0-AD7 



A6.A9- 
ALE - 



DATA 
BUS 
BUFFER 



ADDRESS 
LATCH . 



1Kx8 
RAM 
MEMORY 
ARRAY 



X-Y DECODE 



ADoC 1 
AD 1 C 
AD2C 
AD3C 
AD4 j~ 
ADsQ 
AD 6 £ 
ADyQ 

Vss C 



19 



□ v cc 

□ RD 

□ WR 

□ ALE 

□ cs 

□ CEt 

□ CE 2 

□ As 



AD0-AD7 


ADDRESS/DATA LINES 


Aa,A 9 


ADDRESS LINES 


cs 


CHIP SELECT 


CE! 


CHIP ENABLE (IO/M) 


CE 2 


CHIP ENABLE 


ALE 
WR 


ADDRESS LATCH ENABLE 
WRITE ENABLE 



Figure 1. Block Diagram Figure 2. Pin Configuration 



Intel Corporation Assumes No Responsibly for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other Circuit Patent Licenses are Implied 
©INTEL CORPORATION, 1980 2 _ 45 AFN-01230C 



8185/8185-2 



FUNCTIONAL DESCRIPTION 

The 8185 has been designed to provide for direct interface 
to the multiplexed bus structure and bus timing of the 
8085A microprocessor. 

At the beginning of an 8185 memory access cycle, the 8- 
bit address on ADo-7, As and A9, and the status of CE1 and 
CE2 are all latched internally in the 81 85 by the falling edge 
of ALE. If the latched status of both CE1 and CE2 are 
active, the 8185 powers itself up, but no action occurs until 
the OS line goes low and the appropriate RD or WR control 
signal input is activated. 

The CS input is not latched by the 8185 in order to allow 
the maximum amount of time for address decoding in 
selecting the 8185 chip. Maximum po wer c onsumption 
savings will occur, however, only when CE1 and CE2 are 
activated selectively to power down the 81 85 when it is not 
in use. A possible connection would be to wire the 8085A*s 
IO/M line to the 8185's CE1 input, thereby keeping the 
8185 powered down during I/O and interrupt cycles. 



Table 1. 
Truth Table for 
Power Down and Function Enable 



CE, 


CE 2 


CS 


(CS*) [2] 


8185 Status 


1 


X 


X 


0 


Power Down and 
Function Disable[i] 


X 


0 


X 


0 


Power Down and 
Function Disables ] 


0 


1 


1 


0 


Powered Up and 
Function Disable! 1] 


0 


1 


0 


1 


Powered Up and 
Enabled 



NOTES: 9 

X: Don't Care. 

1: Function Disable implies Data Bus in high impedance state 

and not writing. 

2: CS* = (CE1 = 0) • (CE2 = 1 ) • (CS = 0) 

CS* = 1 signifies all chip enables and chip select active 



Table 2. 
Truth Table for 
Control and Data Bus Pin Status 



(CS*) 


RD 


WR 


AD0.7 During Data 
Portion of Cycle 


8185 Function 


0 


X 


X 


Hi-Impedance 


No Function 


1 


0 


1 


Data from Memory 


Read 


1 


1 


0 


Data to Memory 


Write 


1 


1 


1 


Hi-Impedance 


Reading, but not- 
Driving Data Bus 



NOTE: 

X: Don't Care. 



li 





TRAP 


x, x 2 


RESET IN 

HOLD 






RST7.S 




HLDA 






RST6.5 
RST5.5 


8085A 


SOD 
SID 






INTR 
TRTA 
ADDR 


ADDR/ 

DATA ALE R~D WR" 


s, 

RESET c 
OUT *<> 
IO/M RDY CLK 





7> 

(8) 



V 



\7 V 



V 



I I 



PORT 

^8156 

ALE 



\|data/ VV 

^ ADDR Y 



IO/M TIMER 
occct OUT 



CE ' 
A 8 10 

8355/ 
8755A 

DATA/ 
ADDR 

IO/M po RT 
RESET 
RDY 
CLK 



<A> 



TT 

Vss V cc V D D PROG 



> 



UB1 8185 

ALE 
CS,CE 2 
A 8 , A 9 



TT 

v ss V CC 



Figure 3. 8185 in an MCS-85 System 

4 Chips: 
2K Bytes ROM 
1.25K Bytes RAM 
38 I/O Lines 

1 Counter/Timer 

2 Serial I/O Lines 
5 Interrupt Inputs 



2-46 



AFN-01230C 



8185/8185-2 



iAPX 88 FIVE CHIP SYSTEM: 

• 1.25 K Bytes RAM 

• 2 K Bytes ROM 

• 38 I/O Pins 

• 1 Internal Timer 

• 2 Interrupt Levels 



s- 




\ 

\ GND 
MANUAL 
GND RESET 

(V SS ) 



CLK 
READY 



8284A 

RESET 



READY 

MN/MX 
ALE 

RST (g) RD 
WR 
IO/M 



-<3 6- 

® 



c 



\7 



CE 


PORT 
A 


WR 






PORT 


RD 




8155-2 


ALE 


PORT 


DATA/ 




ADDR 






IN 


IO/M 


TIMER 


RESET 


OUT 



V a 



V 



0v> 



8355-2/ 
8755A-2 

-N DATA/ 
ADDR 



IO/M PORT 
RESET 
READY 

iOR 



Vcc 



MIL, 

V SS V CC V DD 



WR 
RD 

1 811 

ALE 

CS, 
CE 2 

A 8 , A 9 
AD 0 . 7 



V SS v cc 



Figure 4. iAPX 88 Five Chip System Configuration 



2-47 



AFN-01230C 



8185/8185-2 



ABSOLUTE MAXIMUM RATINGS* *NOTICE: Stresses above those- listed under "Absolute „ 



Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
Temperature Under Bias 0° C to +70° C tion of the device at these or any other conditions above 

Storage Temperature -65° C to +1 50° C those indicated in the operational sections of this specif i- 

Voltage on Any Pin cation is not implied. Exposure to absolute maximum 

with Respect to Ground -0.5V to +7V rating conditions for extended periods may affect device 

Power Dissipation 1.5W reliability. 



D.C. CHARACTERISTICS (T A = o°c to 70°c, v C c = 5V ± 5%) 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 




V| H 


Input High Voltage 


2.0 


Vcc+0.5 


V 




Vol 


Output Low Voltage 




0.45 


V 


lOL = 2mA 


Voh 


Output High Voltage 


2.4 






Ioh = - 400/uA 


Iil . 


Input Leakage 




±10 


MA 


0V ^V )N ssVcc 


lLO 


Output Leakage Current 




±10 


ma 


0.45V < Vout < Vcc 


Ice 


Vcc Supply Current 
Powered Up 
Powered Down 




100 


mA 






35 


mA 





A.C. CHARACTERISTICS (T A = o°c to 70°c, Vcc = 5V ± 5%) 



Symbol 


Parameter 


8185 


8185-2 




Min. 


Max. 


Min. 


Max. 


Units 


tAL 


Address to Latch Set Up Time 


50 




30 




ns 


tLA 


Address Hold Time After Latch 


80 




30 




ns 


tLC 


Latch to READ/WRITE Control 


100 




40 




ns 


tRD 


Valid Data Out Delay from READ Control 




170 




140 


ns 


tLD 


ALE to Data Out Valid 




300 




200 


ns 


tLL 


Latch Enable Width 


100 




70 




ns 


tRDF 


Data Bus Float After READ 


0 


100 


0 


80 


ns 


tCL 


READ/WRITE Control to Latch Enable 


20 




10 




ns 


tec 


READ/WRITE Control Width 


250 




200 




ns 


tDW 


Data In to WRITE Set Up Time 


150 




150 




ns 


tWD 


Data In Hold Time After WRITE 


20 




20 




ns 


tsc 


Chip Select Set Up to Control Line 


10 




10 




ns 


tcs , 


Chip Select Hold Time After Control 


10 




10 




ns 


tALCE 


Chip Enable Set Up to ALE Falling 


30 




10 




ns 


tLACE 


Chip Enable Hold Time After ALE 


50 




30 




ns 



2-48 



AFN-01230C 



8185/8185-2 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



A.C. TESTING LOAD CIRCUIT 



INPUT/OUTPUT 



^> TEST POINTS <^ 



A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC " 1 " AND 0 45V FOR 
A LOGIC "0 " TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC "1" 
AND 0 8V FOR A LOGIC "0 " 



DEVICE 
UNDER 
TEST 



1" 
1 



C L = 150'pF 

C L INCLUDES JIG CAPACITANCE 



WAVEFORM 



(CEt-OW 

(CE2-1) 



AD0-AD7 

(A 8 ,A 9 ) 



X 



/ 



\ 



\ / 



X 



(READ CYCLE) 



(WRITE CYCLE) 



X 



(DESELECTED) 



2-49 



AFN-01230C 



inteT 

8205 

HIGH SPEED 1 OUT OF 8 BINARY DECODER 



I/O Port or Memory Selector 

Simple Expansion — Enable Inputs 

High Speed Schottky Bipolar 
Technology — 18ns Max. Delay 

Directly Compatible with TTL Logic 
Circuits 



■ Low Input Load Current — .25 mA 
max., 1/6 Standard TTL Input Load 

■ Minimum Line Reflection — Low 
Voltage Diode Input Clamp 

■ Outputs Sink 10 mA min. 

■ 16-Pin Dual- 1 n-Line Ceramic or 
Plastic Package 



The Intel® 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory 
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low," thus a single row 
of a memory system is selected. The 3-chip enable inputs on the 8205 allow easy system expansion. For very large systems, 
8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory expansions. 

The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature 
range of 0°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to obtain fast switching speeds 
results in higher performance than equivalent devices made with a gold diffussion process. 





A 0 


O 0 














Ai 


Oi 








16 


Z]v C c 




A 2 


0 2 




Aid 


2 


15 


Z]Oo 






o 3 




A 2 d 


3 


14 


□ o, 






8205 
















0 4 




Eid 


4 


13 


ZJo 2 














8205 






Ei 


o 5 




E,d 


5 


12 


Zlo 3 




E 2 


o 6 




E 3 d 


6 


11 


Z]o 4 




E 3 


0 7 




0;d 




10 


d|o 5 










grd| 


8 


x 9 


□ o 6 



A 0 a 2 address inputs 



E, E 3 ENABLE INPUTS 



O 0 0 7 DECODED OUTPUTS 



Figure 1. Logic Symbol 



Figure 2. Pin Configuration 



2-50 



intel 



8205 



FUNCTIONAL DESCRIPTION 
Decoder 

The 8205 contains a one out of eight binary decoder. It ac- 
cepts a three bit binary code and by gating this input, creates 
an exclusive butput that represents the value of the input 
code. 

For example, if a binary code of 101 was present on the AO, 
A1 and A2 address input lines, and the device was enabled, 
an active low signal would appear on the 05 output line. 
Note that all of the other output pins are sitting at a logic 
high, thus the decoded output is said to be exclusive. The 
decoders outputs will follow the truth table shown below in 
the same manner for all other input variations. 

Enable Gate 

When using a decoder it is often necessary to gate the out- 
puts with timing or enabling signals so that the exclusive 
output of the decoded value is synchronous with the overall 
system. 

The 8205 has a built-in function for such gating. The three 
enable inputs (El, E2, E3) are ANDed together and create 
a single enable signal for the decoder. The combination of 
both active "high" and active "low" device enable inputs 
provides the designer with a powerfully flexible gating func- 
tion to help reduce package count in his system. 



ENABLE GATE 



(E1 E2E3) 



Figure 3. Enable Gate 



ADDRESS 


ENABLE 


OUTPUTS 


A 0 


A, 


A 2 


E 


E 2 




0 


1 


2 


3 


4 


5 


6 


7 


L 


L 


L 


L 


L 


H 


L 


H 


H 


H 


H 


H 


H 


H 


H 


L 


L 


L 


L 


H 


H 


L 


H 


H 


H 


H 


H 


H 


L 


H 


L 


L 


L 


H 


H 


H 


L 


H 


H 


H 


H 


H 


H 


H 


L 


L 


L 


H 


H 


H 


H 


L 


H 


H 


H 


H 


L 


L 


H 


L 


L 


H 


H 


H 


H 


H 


I 


H 


H 


H 


H 


L 


H 


L 


L 


H 


H 


H 


H 


H 


H 


L 


H 


H 


L 


H 


H 


L 


L 


H 


H 


H 


H 


H 


H 


H 


L 


H 


H 


H 


H 


L 


L 


H 


H 


H 


H 


H 


H 


H 


H 


L 


X 


X 


X 


L 


L 


L 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


X 


H 


L 


L 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


X 


L 


H, 


L 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


X 


H 


H 


L 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


X 


H 


L 


H 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


X 


L 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


X 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 



2-51 



AFN-00204C 



8205 



Applications of the 8205 

The 8205 can be used in a wide variety of applications in 
microcomputer systems. I/O ports can be decoded from the 
address bus, chip select signals can be generated to select 
memory devices and the type of machine state such as in 
8008 systems can be derived from a simple decoding of the 
state lines (SO, S1 , S2) of the 8008 CPU. 

I/O PORT DECODER 

Shown in the figure below is a typical application of the 
8205. Address input lines are decoded by a group of 8205s 
(3). Each input has a binary weight. For example, AO is as- 
signed a value of 1 and is the LSB; A4 is assigned a value of 
16 and is the MSB: By connecting them to the decoders as 
shown, an active low signal that is exclusive in nature and 
represents the value of the input address lines, is available at 
the outputs of the 8205s. 

This circuit can be used to generate enable signals for I/O 
ports or any other decoder related application. 

Note that no external gating is required to decode up to 24 
exclusive devices and that a simple addition of an inverter 
or two will allow expansion to even larger decoder net- 
works. 

CHIP SELECT DECODER 

Using a very similar circuit to the I/O port decoder, an ar- 




ray of 8205s can be used to create a simple interface to a 
24K memory system. 

The memory devices used can be either ROM or RAM and 
are 1K in storage capacity. 2708s and 2114As are devices 
typically used for-this application. This type of memory 
device has ten (10) address inputs and an active "low" 
chip select (CS). The lower order address bits A0-A9 
which come from the microprocessor are "bussed" to all 
memory elements and the chip select to enable a specific 
device or group of devices comes from the array of 8205s. 
The output of the 8205 is active low so it is directly compat- 
ible with the memory components. 

Basic operation is that the CPU issues an address to identify 
a specific memory location in which it wishes to "write" or 
"read" data. The most significant address bits A10-A14 are 
decoded by the array of 8205s and an exclusive, active low, 
chip select is generated that enables a specific memory de- 
vice. The least significant address bits A0-A9 identify a 
specific location within the selected device. Thus, all ad- 
dresses throughout the entire memory array are exclusive 
in nature and are non-redundant. 

This technique can be expanded almost indefinitely to sup- 
port even larger systems with the addition of a few inverters 
and an extra decoder (8205). 




Figure 4. I/O Port Decoder 



Figure 5. 24K Memory Interface 



2-52 



irry 



8205 



ABSOLUTE MAXIMUM RATINGS* 'NOTICE: Stresses above those listed under "Absolute ' 
Temperature Under Bias: Maximum Rapngs" may cause permanent damage to the 
Ceramic -65°C to +125°C device. This is a stress rating only and functional opera- 
Plastic -65°C to +75°C tion of the device at these or at any other condition above 

Storage Temperature -65°C to + 1 60°C those indicated in the operational sections of this specif i- 

All Output or Supply Voltages -0.5 to +7 Volts cation is not jmplied. Exposure to absolute maximum 

All Input Voltages -1 .0 to +5.5 Volts rating conditions for extended periods may affect device 

Output Currents 125 mA reliability. 

D.C. CHARACTERISTICS (T A = 0°C to +75°C, V C c = 5V ±5%) 



Symbol 


Parameter 


Lim 

~Mln: 


it 

Maxi 


Unit 


Test Conditions 


'f 


INPUT LOAD CURRENT 




-0 25 


mA 


V cc = 5.25V, V F = 0.45V 


■r 


INPUT LEAKAGE CURRENT 




10 


HA 


V cc = 5 25V, V R = 5.25V 


v c 


INPUT FORWARD CLAMP VOLTAGE 




-1 0 


V 


V cc = 4 75V, l c = -5.0 mA 


V OL 


OUTPUT "LOW" VOLTAGE 




0 45 


V 


V cc = 4.75V, l QL = 10.0 mA 


V OH 


OUTPUT HIGH VOLTAGE 


24 




V 


v CC =4 - 75V, OH = - 1 - 5mA 


V 


INPUT "LOW" VOLTAGE 




0 85 


V 


V cc = 5 0V 




INPUT "HIGH" VOLTAGE 


20 




V 


V cc = 5.0V 


'sc 


OUTPUT HIGH SHORT 
CIRCUIT CURRENT 


-40 


-120 


mA 


V cc = 5.0V, V QUT = 0V 


v ox 


OUTPUT "LOW" VOLTAGE 
@ HIGH CURRENT 




08 


V 


V CC =5 " 0V - 'ox = 40mA 


'cc 


POWER SUPPLY CURRENT 




70 


mA 


V cc = 5 25V 



A.C. CHARACTERISTICS (T A = 0°C to +75°C, V cc = 5V ±5%; unless otherwise specified) 



Symbol 


Parameter 


Max. Limit 


Unit 


Test Conditions 


t + + 


ADDRESS OR ENABLE TO 
OUTPUT DELAY 


18 


ns 




t_ + 


18 


ns 




t + _ 


18 


ns 




t__ 


18 


ns 




c u> 


INPUT CAPACITANCE P8205 


4(typ.) 


pF 


f = 1 MHz, Vcc = ov 
V BIAS = 2.0V.T A ^25°C 


C8205 


5(typ ) 


pF 



1 This parameter is periodically sampled and is not 100% tested 

TYPICAL CHARACTERISTICS 



OUTPUT CURRENT VS. 
OUTPUT "LOW" VOLTAGE 

! I I 




OUTPUT CURRENT VS. 
OUTPUT "HIGH" VOLTAGE 



K ~ 30 



-40 



1 

— ^cc 


! 1 

= 5 0V 


1 1 
-* — U 




- ! 

1 


|~ -i 
T A - 


: 1 


(J/>^ T A " 25 C 


0°C~t *7 




T A - 75°C 


t 


+ ^ 


~* * m 












+ - f- 












I_ - 


-+- -»- 












t - 






- - 












tt 










4.. 














1 /I 


tr 


1 







DATA TRANSFER FUNCTION 




OUTPUT ' LOW" VOLTAGE (V) 



OUTPUT HIGH VOLTAGE (V» 



0 2 4 6 8 101214161820 
INPUT VOLTAGE (V) 



2-53 



AFN-00204C 



8205 



TYPICAL CHARACTERISTICS (Continued) 



ADDRESS OR ENABLE TO OUTPUT 
DELAY VS. LOAD CAPACITANCE 



g 15 

5? 



V CC = 5.0V 
T A - 25°C 


W „ - ^ 




— U-+ 












I I 



50 100 150 

LOAD CAPACITANCE (pF) 



ADDRESS OR ENABLE TO OUTPUT 
DELAY VS. AMBIENT TEMPERATURE 



g 15 

Is 

§° 10 



CL = 30pF 



t+_, t_ 



0 25 50 

AMBIENT TEMPERATURE (°C) 



SWITCHING CHARACTERISTICS 



CONDITIONS OF TEST: 
Input pulse amplitudes: 2.5V 

Input rise and fall times: 5 nsec 
between 1V and 2V 

Measurements are made at 1.5V 



TEST LOAD 



TEST LOAD: 



7 



All Transistors 2N2369 or Equivalent C L = 30 pF 



WAVEFORMS 



ADDRESS OR ENABLE 
INPUT PULSE 



/ 



\ 



2-54 



AFN-00204C 



8212 

8-BIT INPUT/OUTPUT PORT 



Fully Parallel 8-Bit Data Register and Buffer 

Service Request Flip-Flop for 
Interrupt Generation 

Low Input Load Current — .25mA Max. 

Three State Outputs 

Outputs Sink 15 mA 

3.65V Output High Voltage for 
Direct Interface to 8008, 8080A, or 
8085A CPU 



Asynchronous Register Clear 

Replaces Buffers, Latches and 
Multiplexers In Microcomputer 
Systems 

Reduces System Package Count 

Available in EXPRESS 

- Standard Temperature Range 

- Extended Temperature Range 



The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection 
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor. 

The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the 
principal peripheral and input/output functions of a microcomputer system can be implemented with this device. 




2-55 



8212 



FUNCTIONAL DESCRIPTION 
Data Latch 

The 8 flip-flops that make up the data latch are of a "D" 
type design. The output (Q) of the flip-flop will follow the 
data input (D) while the clock input (C) is high. Latching 
will occur when the clock (C) returns low. 

The la tche d data is cleared by an asynchrono us re set 
input (CLR). (Note: Clock (C) Overrides Reset (CLR).) 



Output Buffer 

The outputs of the data latch (Q) are connected to 3-state, 
non-inverting output buffers. These buffers have a 
common control line (EN); this control line either enables 
the buffer to transmit the data from the outputs of the data 
latch (Q) or disables the buffer, forcing the output into a 
high impedance state. (3-state) 

The high-impedance state allows the designer to connect 
the 8212 directly onto the microprocessor bi-directional 
data bus. 



Control Logic 

The 8212 has control inputs DS1, DS2, MD and STB. 
These inputs are used to control device selection, data 
latching, output buffer state and service request flip-flop. 



DS1, DS2 (Device Select) 

These 2 inputs are used for device selection. When DS1 is 
low and DS2 is high (DS1 • DS2) the device is selected. In 
the selected state the output buffer is enabled and the 
service request flip-flop (SR) is asynchronously set. 



MD (Mode) 

This input is used to control the state of the output buffer 
and to determine the source of the clock input (C) to the 
data latch. / 

When MD is high (output mode) the output buffers are 
enabled and the source of clock (C) to the data latch is 
from the device selection logic (DS1 • DS2). 

When MD is low (input mode) the output buffer state is 
determined by the device selection logic (DS1 • DS2) and 
the source of clock (C) to the data latch is the STB 
(Strobe) input. 



STB (Strobe) 

This input is used as the clock (C) to the data latch for the 
input mode MD = 0) and to synchronously reset the 
service request flip-flop (SR). 

Note that the SR flip-flop is negative edge triggered. 



Service Request Flip-Flop 

The (SR) flip-flop is used to generate and control 
interrupts in microc omputer systems. It is asynchron- 
. ously set by the CLR input (active low). When the (SR) flip- 
flop is set it is in the non-interrupting state. 

The output of the (SR) flip-flop (Q) iS/ connected to an 
inverting input of a "NOR" gate. The other input to the 
"NOR" gate is non-inverting and is connected to the 
device selection logic (DS1 • DS2). The output of the 
"NOR" gate (INT) is active low (interrupting state) for 
connection to active low input priority generating circuits. 

SERVICE REQUEST FF 



LECTION F * 4 ^ i — C 



Q> DS1-op-^ 

|T?> n<;?- J J " 

(T> MD - 

JTT> stb- 



GE>D'l- 

GE> DI : 

E>di : 
GE> D, « 

[T6>DI 5 - 
E>DI 6 - 

d2>Di 7 - 

(H>D1 8 - 



[U>CLR —3 \> 

(ACTIVE LOW) L-/ 




- INT {23> , 



(ACTIVE LOW) 




D Q -~T"^4 °° 5 ^> 



-D0 6 (T7> 



- oo 7 (Ts£> 



• do 8 (!£> 



I l__J 



I STB 

I 0 



CLR - 



MD (DS, DS 2 ) DATA OUT EQUALS 

0 0 ' 3 STATE 

0 0 3 STATE 

1 0 DATA LATCH 
1 0 DATA LATCH 

0 1 DATA LATCH , 

0 1 DATA IN 

1 1 DATA IN 

1 1 DATA IN _ 

RESETS DATA LATCH 

SETSSR FLIP FLOP 

(NO EFFECT ON OUTPUT BUFFER) 



CLR | 


D§TDS 2 ) STB 


•SR 


INT 


0 


0 " 0 


1 


1 


0 t 


1 ' 0 




0 


1 




0 


0 


1 


1 . 0 




0 


1 


o ; 0 


1 


1 






1 


0 



•INTERNAL SR FtIP FLOP 



2-56 



8212 



ABSOLUTE MAXIMUM RATINGS* 



Temperature Under Bias Plastic 0°C to +70° C 

Storage Temperature -65? C to -1-1 60° C 

All Output or Supply Voltages -0.5 to +7 Volts 

All Input Voltages -1.0 to 5.5 Volts 

Output Currents 100mA 



*NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (T A =o°c to +75°c, v cc = +5V ± 5%) 



Symbol 


Parameter 


Limits 


Unit 


Test Conditions 


Min. 


Typ. 


Max. 


If 


Input Load Current, ACK, DS2, CR, 
DI1-DI8 Inputs 






-.25 


mA 


\/_ ARM 

VF — .40V 


If 


Input Load Current MD Input 






-.75 


mA 


Vf = .45V 


If 


Input Load Current DS1 Input 






-1.0 


mA 


Vf = .45V 


Ir 


Input Leakage Current, ACK, DS, CR, 
DI1-DI8 Inputs 






10 


mA 


Vr < Vcc 


Ir 


Input Leakage Current MO input 






30 


/iA 


Vr < Vce 


Ir 


Input Leakage Current DS1 Input 






40 


M A 


Vr < Vcc 


Vc 


Input Forward Voltage Clamp 






-1 


V 


lc = -5mA 


Vil 


Input "Low" Voltage 






.85 


V 




V IH 


Input "High" Voltage 


2.0 






V 




Vol 


Output "Low" Voltage 






.45 


V 


lOL = 15mA 


Voh 


Output "High" Voltage 


3.65 


4.0 




V 


lOH = -1mA 


isc 


Short Circuit Output Current 


-15 




-75 


mA 


Vo = 0V, Vcc = 5V 


Hoi 


Output Leakage Current High 
Impedance State 






20 


MA 


Vo = .45V/5.25Vcc 


ice 


Power Supply Current 




90 


130 


mA 





CAPACITANCE* (F = 1 MHz, V BIAS = 2.5V, 
V cc = +5V, T A = 25°C) 



Symbol 


Test 


Limits 


Typ. 


Max. 


ClN . 


DS1 MD Input Capacitance 


9pF 


12pF 


ClN 


DS 2 ,CLR, STB, Dh-DI 8 
Input Capacitance 


5pF 


9pF 


COUT 


DOi-DOs Output Capacitance 


8pF 


12pF 



"This parameter is sampled and not 100% tested. 



A.C. TESTING LOAD CIRCUIT 



SWITCHING CHARACTERISTICS 

Conditions of Test 

Input Pulse Amplitude = 2.5V 

Input Rise and Fall Times 5ns 

Between 1V and 2V Measurements made at 1.5V 

with 15mA and 30pF Test Load 



NOTE: 

1. 




Test 




R1 


R 2 


tPD, twE, tR, ts, tC 


30pF 


30on 


6oon 


tE, ENABLEI 


30pF 


10KH 


1Kf) 


tE, ENABLE 1 


. 30pF 


30on 


6oon 


tE, DISABLEt 


5pF ! 


30on 


60on 


tE, DISABLE! 


5pF 


10KH 


ikh 



'Includes probe and jig capacitance. 



2-57 



AFN-00731C 



inteT 



8212 



A.C. CHARACTERISTICS (T A = o°c to +70°d v cc = +5V ± 5%) * 



Symbol 


Parameter 


Limits 


Unit 


Test Conditions , 


Mln. 


Typ. 


Max. 


tpw 


Pulse Width 


30 






ns 




tPD 


data to Output Delay 






30 


ns 


Note 1 


tWE 


Write Enable to Output Delay 






40 


ns 


Note 1 


tSET 


Data Set Up Time 


15 






ns 




tH 


Data Hold Time 


20 






ns 




tR 


Reset to Output Delay 






40 


ns 


Note 1 


ts 


Set to Output Delay 






30 


ns 


Note 1 


tE 


Output Enable/Disable Time 






45 


ns 


Note 1 


tc 


Clear to Output Delay 






55 


ns 


Note 1 



*Note: For extended Temperature EXPRESS use M8212 AC Electricals Parameters. 
APPLICATIONS 



Basic Schematic Symbols 

Two examples of ways to draw the 8212 on system schematics — (1) the top being the detailed view showing pin numbers, 
and (2) the bottom being the symbolic view showing the system input or output as a system bus (bus containing 
8 parallel lines). The output to the data bus is symbolic in referencing 8 parallel lines. 



INPUT DEVICE 



22. CLR I 
14 /_ MD 
° DS, | DS 2 



INPUT 
STROBE 



SYSTEM 
INPUT 



GND 

~2 



~ (SYMBOLIC) 



OUTPUT DEVICE 



OUTPUT 
" FLAG 



SYSTEM 
OUTPUT 



Figure 3. Basic Schematic Symbols 



Gated Buffer (3-State) 

The simplest use of the 8212 is that of a gated buffer. By 
tying the mode signal low and the strobe input high, the 
data latch js acting as a straight through gate. The output 
buff ers are then enabled from the device selection logic 
DS1 and DS2. 

When the device selection logic is false, the outputs are 3- 
state. 

When the device selection logic is true, the input data from 
the system is directly transferred to the output. The input 
data load is 250 micro amps. The output data can sink 15 
milli amps. The minimum high output is 3.65 volts. 



GATING 

CONTROL 

(OS1.DS2) 



{ 





STB 


INPUT K 

DATA C ) 
(250 M A) * 1/ 


8212 




CLR 




_9 1 


GND 



OUTPUT 

DATA 

<15mA) 

(3 65VMIN) 



Figure 4. Gated Buffer 



2-58 



AFN-00731C 



8212 



Bi-Directlonal Bus Driver 

A pair of 821 2's wired (back-to-back) can be used as a 
symmetrical drive, bi-directional bus driver. The devices 
are controlled Jby the data bus input control which is 
connected to DS1 on the first 8212 and to DS2 on the 
second. One device is active, and acting as a straight 
through buffer the other is in 3-state mode. This is a very 
useful circuit in small, system design. 



DATA ( 
BUS L 



7% 



0 



DATA BUS 
CONTROL — 
{0= L - R) 
(I = R — L) 



CLR 



r ~P r 



I DATA 
I BUS 



Figure 5. Bidirectional Bus Driver 
Interrupting Input Port 

This use of an 8212 is that of a system input port that 
accepts a strobe from the system input source, which in 
turn clears the service request flip-flop and interrupts the 
processor. The processor then goes through a service 
routine, identifies the port, and causes the device 
selection logic to go true — enabling the system input data 
onto'the data bus. 



INPUT 
STROBE " 



DATA 
BUS 



SYSTEM 
INPUT 



SYSTEM 
RESET " 



PORT r _ 

SELECTION -j 
(DSLDS2) L- 



XT 



TO PRIORITY CKT 
" (ACTIVE LOW) 

TO CPU 

INTERRUPT INPUT 



Figure 6. Interrupting Input Port 



Interrupt Instruction Port 

The 8212 can be used to gate the interrupt instruction, 
normally RESTART instructions, onto the data bus. The 
device is enabled from the interrupt acknowledge signal 
from the microprocessor and from a port selection signal. 
This signal is normally tied to ground. (DS1 could be used 
to multiplex a variety of interrupt instruction ports onto a 
common bus). 



RESTART 
INSTRUCTION 
(RST 0 



RT J__K 
JCTION C > 

- rst 7) '~r~v 



DATA 
BUS 



(DSI) PORT SELECTION • 
INTERRUPT ACKNOWLEDGE 



CLR 

TT 



Figure 7. Interrupt Instruction Port 
Output Port (With Hand-Shaking) 

The 821 2 can be used to transmit data from the data bus to 
a system output. The output strobe could be a hand- 
shaking signal such as "reception of data" from the device 
that the system isoutputting to. It in turn, can interrupt the 
system signifying the reception of data. The selection of 
the port comes from the device selection logic.( DS1 • DS2) 



DATA 
BUS 



OUTPUT STROBE 



SYSTEM 
INTERRUPT" 



TT 



SYSTEM OUTPUT 



• SYSTEM RESET 



PORT SELECTION 
(LATCH CONTROL) 
(DS1.DS2) 



Figure 8. Output Port 



2-59 



8212 



808A Status Latch 

Here the 8212 is used as the status latch for an 8080A 
microcomputer system. The input to the 8212 latch is 
directly from the 8080A data bus. Timing shows that when 
the SYNC signal is true, which is connected to the DS2 
input and the phase 1 signal is true, which is a TTL level 
coming from the clock generator; then, the status data will 
be latched into the 8212. 




8080A 



12V 
OV 



TV 



SYNC 
DBIN 

02 

15 



CLOCK GEN. 
& DRIVER 



(01TTL) 



- DATA BUS 



STATUS 
LATCH 



3 
5 

7 

9 
16 
18 
20 
22 



INTA 
WO 

• STACK 
HLTA 

■ OUT 

■ M1 

■ INP 

• MEMR 



BASIC 

CONTROL 

BUS 



Note: The mode signal is tied high so that the output on the 
latch is active and enabled all the time. 



It is shown that the two areas of concern are the bi- 
directional data bus of the microprocessor and the control 
bus. 



2-60 



AFN-00731C 



8212 





DATA TO OUTPUT DELAY 
VS. TEMPERATURE 



$ 18h 



WRITE ENABLE TO OUTPUT DELAY 
VS. TEMPERATURE 



5 

O 25 



S 15 



TEMPERATURE (°C) 



TEMPERATURE CC) 



2-61 



AFN-00731C 




2-62 



AFN-00731C 



inter 



821 6/8226 

4-BIT PARALLEL BIDIRECTIONAL BUS DRIVER 



■ Data Bus Buffer Driver for 8080 CPU 

■ Low Input Load Current — 0.25 mA 
Maximum 

■ High Output Drive Capability for 
Driving System Bus 



■ 3.65V Output High Voltage for Direct 
Interface to 8080 CPU 

■ 3-State Outputs 

■ Reduces System Package Count 

■ Available in EXPRESS 

- Standard Temperature Range 



The 8216/8226 is a 4-bit bidirectional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS, the 
DO outputs provide a high 3.65V V 0 h. and for high capacitance terminated bus structures, the DB outputs provide a 
high 50 mA Iol capability. A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applica- 
tions for buffering in microcomputer systems. 

'Note: The specifications for the 3216/3226 are identical with those for the 8216/8226. 



8216 



8226 



Dlo O- 



2=£ 



-O DB„ 



-O OB 3 



Dl 2 O- 



D0 2 O- 



D0 3 O- 



-O DB 0 



C§[ 
OOoC 
D «o[ 

D, oCZ 



GNO 



JVcC 
15 1 | OlfN 



4 8216/ 13 

5 8226 12 

0B iCZ|« 11 

01, fZ 7 10 
8 



Z3° B 3 
Ol, 

Z) °°2 
Z)0B 2 
Zl D«2 



DB^DB, 


DATA BUS 
BIDIRECTIONAL 


Dl0«>«3 


DATA INPUT 


OO 0 OOj 


DATA OUTPUT 


5ili5" 


OATA IN ENABLE 
DIRECTION CONTROL 


S 


CHIP SELECT 



Figure 1. Block Diagrams Figure 2. Pin Configuration 



2-63 



inteT 



8216/8226 



FUNCTIONAL DESCRIPTION 

Microprocessors like the 8080 are MOS devices and are 
generally capable of driving a single TTL load. The same is 
true for MOS memory devices. While this type of drive is 
sufficient in small systems with few components, quite often 
it is necessary to buffer the microprocessor and memories 
when adding components or expanding to a multi-board 
system. 

The 8216/8226 is a four bit bi-directional bus driver specif- 
ically designed to buffer microcomputer system components. 

Bidirectional Driver 

Each buffered line of the four bit driver consists of two 
separate buffers that are tri-state in nature to achieve direct 
bus interface and bi-directional capability. On one side of 
the driver the output of one buffer and the input of another 
are tied together (DB), this side is used to interface to the 
system side components such as memories, I/O, etc., be- 
cause its interface is direct TTL compatible and it has high 
drive (50mA). On the other side of the driver the inputs 
and outputs are separated ^to provide maximum flexibility. 
Of course, they can be tied together so that the driver can 
be used to buffer a true bi-directional bus such as the 8080 
Data Bus. The DO outputs on this side of the driver have a 
special high voltage output drive capability (3.65V) so that 
direct interface to the 8080 and 8008 CPUs is achieved with 
an adequate amount of noise immunity (350m V worst case). 




Control Gating DIEN, CS 

The CS input is actually a device select. When it is "high" 
the output drivers are all forced to their high-impedance 
state. When it is at "zero" the device is selected (enabled) 
and t he direction of the data flow is determined by the 
DIEN input. 

The DIEN input controls the direction of data flow (see 
Figure 3) for complete truth table. This direction control 
is accomplished by forcing one of the pair of buffers into its 
high impedance state and allowing the other to transmit its 
data. A simple two gate circuit is used for this function. 

The 8216/8226 isadevicethat will reduce component count 
in microcomputer systems and at th» same time enhance 
noise immunity to assure reliable, high performance op- 
eration. 



Figure 3a. 8216 Logip Diagram 



3*. 



-=3) — r- 



HIGH IMPEDANCE 



Figure 3b. 8226 Logic Diagram 



2-64 



AFN-00733C 



8216/8226 



ABSOLUTE MAXIMUM RATINGS* 



Temperature Under Bias , 0°C to 70°C 

Storage Temperature -65°C to +150°C 

All Output and Supply Voltages -0.5V to +7V 

All Input Voltages -1.0V to +5.5V 

Output Currents 125mA 



*NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (T A = o°cto +70°c, v cc = +5V ± 5%) 



Symbol 


Parameter 


Limits 


Unit 


Conditions 


Min. 


Typ. 


Max. 


»F1 


Input Load Current DIE'N, CS 




-0.15 


-.5 


mA 


V F =0.45 


«F2 


Input Load Current All Other Inputs 




-0.08 


-.25 


mA 


V F =0.45 


«R1 


Input Leakage Current DIEN, CS 






80 


MA 


V R = 5.25V 


•r2 


Input Leakage Current Dl Inputs 






40 


ma 


V R = 5.25V 


v c 


Input Forward Voltage Clamp 






-1 


V 


l c = -5mA 




Input "Low" Voltage 






.95 


V 




V,h 


Input "High" Voltage 


2.0 






V 




ii 0 1 


Output Leakage Current DO 
(3-State) DB 






20 
100 


/iA 


Vo = .45V/5.25Vcc 


•cc 


8216 




95 


130 


mA 




Power Supply Current 

8226 




85 


120 


mA 




V 0 L1 


Output "Low" Voltage 




0.3 


.45 


V 


DO Outputs loL=15mA 
DB Outputs l 0 L = 25mA 


V 0 L2 


8216 




0.5 


.6 


V 


DB Outputs lQL = 55mA 


Output "Low" Voltage 

8226 




0.5 


.6 


V 


DB Outputs loL = 50mA 


V0H1 


Output "High" Voltage 


3.65 


4.0 




V 


DO Outputs Iqh = -1mA 


V0H2 


Output "High" Voltage 


2.4 


3.0 




V 


DB Outputs Iqh = -10mA 


!0S 


Output Short Circuit Current , 


-15 
-30 


-35 
-75 


-65 
-120 


mA 
mA 


DO Outputs V 0 =s 0V, 
DB Outputs V CC =5.0V 



NOTE: 



Typical values are for = 25° C, Vcc = 5.0V. 



2-65 



AFN-00733C 



8216/8226 



CAPACITANCE' 5 ' (v B , AS = 2.5V, Vcc = s.ov, t a = 25°c. f = 1 mhz) 



Symbol 


Parameter 


Limits 


Unit 


Min. 


Typ.m 


Max. 




Input Capacitance 




4 


8 


pF 


C OUT1 


Output Capacitance 




6 


10 


pP 


C0UT2 


Output Capacitance 




13 


18 


pF 



A-C. CHARACTERISTICS (t a = o°c to +7o°c, v cc = +5V ± 5%) 



Symbol 


Parameter 


Limits 


Unit 


Conditions 


Min. 


Typ.HJ 


Max. 


T PD1 


Input to Output Delay DO Outputs 




15 


25 


ns 


C L =30pF,R 1 ^300n 
R 2 =600n 


Tpd2 


Input to Output Delay DB Outputs 
8216 




19 


30 


ns 


C L =300pF, R ! =9012 
R 2 = 180ft 


8226 




16 


25 


ns 


T E 


Output Enable Time 

8216 




42 - 


65 


ns 


(Note 2) 


8226 




36 


54 


ns 


(Note 3) 


T D 


Output Disable Time 




16 


35 


ns 


(Note 4) 



NOTE: 

Input pulse amplitude of 2.5V. 

Input rise and fall times of 5 ns between 1 and 2 volts. 

Output loading is 5 mA and 10 pF. 

Speed measurements are made at 1.5 volt levels. 



NOTES: * 

1. Typical values are for ■ 25° C, Vfjc ~ 5.0V. 

2. DO Outputs, C L - 30pF, Rj - 300/10 Kf2, R 2 - 180/1KJ2; DB Outputs, C L - 300pF, R, = 90/10 Krt, R 2 = 180/1 Kfi. 

3. DO Outputs, C|_ - 30pF, Rj - 300/10 KSl, R 2 - 600/1K; DB Outputs, C L = 300pF, R-j = 90/10 Kn, R 2 = 180/1 Kft. 

4. DO Outputs, Cl - 5pF, Rj - 300/10 KSl, R 2 = 600/1 KfZ; DB Outputs, C L = 5pF, R 1 = 90/10 Kfi, R 2 = 180/1 Kft. 

5. This parameter is periodically sampled and not 100% tested. 

\ 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 




inteT 



2-66 



AFN-00733C 



8216/8226 



WAVEFORM 



OUTPUT 
ENABLE 



X 



2-67 



AFN-00733C 



irrtel 



8218/8219 
BIPOLAR MICROCOMPUTER BUS 
CONTROLLERS FOR MCS-80® AND MCS-85® FAMILIES 



8218 for Use in MCS-80® Systems 

8219 for Use inMCS-85® Systems 

Coordinates the Sharing of a Common 
Bus Between Severai CPU's 



■ Reduces Component Count in 
Multimaster Bus Arbitration Logic 

■ Single +5 Volt Power Supply 

■ 28 Pin Package 



The 821 8 and 821 9 Microcomputer Bus Controllers consist of control logic which allows a bus master device such as a CPU 
or DMA channel to interface with other masters on a common bus, sharing memory and I/O devices. The 8218 and 8219 
consist of: 

1 . Bus Arbitration Logic which operates from the Bus Clock (BCLK) and resolves bus contention between devices sharing 
a common bus. 

2> Timing Logic which when initiated by the bus arbitration logic generates timing signals for the memory and I/O 
command lines to guarantee set-up and hold times of the address/data lines onto the bus. The timing logic also signals 
- to the bus arbitration logic when the current data transfer is completed and the bus is no longer needed. 
3. Output Drive Logic which contains the logic and output drivers for the memory and I/O command lines. 

An external RC time constant is used with the timing logic to generate the guaranteed address set-up and hold times on the 
bus. The 8219 can interface directly to the 8085A CPU and the 8218 interfaces to the 8080A CPU chip and the 8257 DMA 
controller. 



BCR1- 
(E)- 

RSTB — 
ADEN* 
OVRD- 



TOTHE /L_ 

BUS < XSTR - 

MASTER N 



BUS ARBITRATION 
LOGIC 



► BUSY 

- BREQ 
-BPRN 

- BPRO 

- INIT 

- BCLK 



TIMING LOGIC 



ANYR - 

(A) - 

(B) - 
(O- 
(D)- 

RDD - 



TO THE 
BUS 





OUTPUT DRIVE LOGIC 












». 









► MRDC 

► MWTC 

► iORC 

► iowc 



inTt C 

N.C.C 

xstrC 
xcpT 
Xc?C 

(A) C 

(B) C 

(OC 

(D>C 

anyrC 
rddC 

MRDC C 

iORcC 
gndC 



□ v C c 

IjOVRD 

□ rstb 

□ bcri 

□ (E) 

Dbpro 

□ bprTj 

□ breq 

□ bclk 

3 ADEN 

□ busy 

□ iowc 

□ mwtc 

□ DLYADJ 



8219 
IO/M 



§218 

(A) iOWR 

(B) MVVTR 

(C) IORR 

(D) MRDR 

(E) BCR2 



N.C. = NO CONNECT 



Figure 1. Block Diagram 



Figure 2. Pin Configuration 



2-68 



AFN-00208C 



iiteT 



8218/8219 



Table 1. Pin Description 



Signals Interfaced Directly to the System Bus 


- Symbol 


Type 


Name and Function 


BREQ 


0 


Bus Request: The Bus Request is used 
with a central parallel priority resolution 
circuit. It indicates that the device needs to 
access the bus for one or more data trans- 
fers. It is synchronized with the Bus Clock. 


BUSY 


I/O 


Bus Busy: Bus Busy indicates to all master 
devices on the bus that the bus is in use. It 
inhibits any other device from getting the 
bus. It is synchronized with Bus Clock. 


BCLK 


1 


Bus Clock: The negative edge of Bus Clock 
is used to synchronize the bus contention 
resolution circuit asynchronously to the 
CPU clock. It has 100ns min. period, 35%- 
65% duty cycle. It may be slowed, single 
stepped or stopped. 


BPRN 


1 


Bus Priority In: The Bus Priority In indi- 
cates to a device that no device of a higher 
priority is requesting the bus. It is syn- 
chronous with the Bus clock. 


BPRO 


0 


Bus Priority Out: The Bus Priority Out is 
used with serial priority resolution circuits. 
Priority may be transferred to the next lower 
in priority as BPRN. 


INTf 


1 


Initialize: The Initialize resets the 8218/ 
8219 to a known internal sta"te. 


MRDC 


0 


Memory Read Control: The Memory Read 
Control indicates that the Master is request- 
ing a read operation from the addressed 
location. It is asynchronous to the Bus 
Clock. 


MWTC 


0 


Memory Write Control: The Memory Write 
Control indicates that data and an address 
have been placed on the bus by the Master 
and the data is to be deposited at that loca- 
tion. It is asynchronous to the Bus Clock. 


iORC 


0 


I/O Read Control: The I/O Read Control in- 
dicates that the Master is requesting a read 
operation from the I/O device addressed. It 
is asynchronous to the Bus Clock. 


iowc 


0 


I/O Write Control: The I/O Write Control in- 
dicates that Data and an I/O device address 
has been placed on the bus by the Master 
and the data is to be deposited to the I/O 
device. It is asynchronous to the Bus Clock. 


Signals Generated or Received by the Bus Master 


BCR1/ 
BCR2 


1 


Bus Control Request: Bus Control Re- 
quest 1 or Bus Control Request 2 indicate to 
the 821 8/821 9 that the Master device is mak- 
ing a request to control the bus. BCR2 is 
active low in the 8218 (BCR2). BCR2 is ac- 
tive high in the 8219. 


RSTB 




Request Strobe: Request Strobe latches 
the status of BCR1 and BCR2 into the 
8218/8219. The strobe is active low in the 
8218 and negative edge triggered in the 
8219. 



Signals Generated or Received by the Bus Master 
(Continued) 


Symbol 


Type 


Name and Function 


atjer 


0 


Address and Data Enable: Address and 
Data Enable indicates the Master has con- 
trol of the bus. It is often used to enable 
Address and Data Buffers on the bus, It is 
synchronous with Bus Clock. 


RDD 


0 


Read Data: Read Data controls the direc- 
tion of the bi-directional data bus drivers. It 
is asynchronous to the Bus Clock. A high on 
RDD indicates a read mode by the master. 


OVRD 


I 

*> 


Override: Override inhibits automatic de- 
select between transfers caused by a higher 
priority bus request. May be used for con- 
secutive data transfers such as read- 
modify-write operations. It is asynchronous 
to the Bus Clock. 


XSTR 




Transfer Start Request: Transfer Start Re- 
quest indicates to the 8218/8219 that a new 
data transfer cycle is requested to start. It is 
raised for each new word transfer in a mul- 
tiple data word transfer. It is asynchronous, 
to the Bus Clock. 


XCP 


I 


Transfer Complete: Transfer Complete in- 
dicates to the 8218/8219 that the data has 
been received by the slave device in a write 
cycle or transmitted by the slave and re- 
ceived by master in a read cycle. It is asyn- 
chronous to the Bus Clock. 


XCY 


0 


Data Transfer: Indicates that a data trans- 
fer is in progress. It is asynchronous to the 
Bus Clock. 


WR, RD, 
IO/M 




Write, Read, IO/Memory: WRITE, READ, 
IO/Memory are the control request inputs 
used by the 8085 and are internally decoded 
by the 8219 to produce the request signals 
MRDR, MWTR, IORR, IOWR. They are asyn- 
chronous to the Bus Clock. (8219 only) 


ASRQ 


I 


Asynchronous Bus Request: Can be used 
for interrupt status from the 8085. Acts like a 
level sensitive asynchronous bus 
request — no RSTB needed. It is asynchron- 
ous to the Bus Clock. (8219 only) 


MRDR, 
MWTR, 
IORR, 
IOWR 


I 

)' 


Memory Read Request, Memory Write 
Request, I/O Read Request, or I/O Write 
Request: Indicate that address and data 
have been placed on the bus and the appro- 
priate request is being made to the ad- 
dressed device. Only one of these inputs 
should be active at any one time. They are 
synchronous to the Bus Clock. (8218 only) 


ANYR 


0 


Any Request: Any Request is the logical 
OR of the active state of MRDR, MWTR, 
IORR, IOWR. It may be tied to XSTR when 
the rising edge of ANYR is used to initiate a 
transfer. 


DL.YADJ 


I 


Delay Adjust: Delay Adjust is used for con- 
nection of an external capacitor and resis- 
tor to ground to adjust the required set-up 
and hold time of address to control signal. 



2-69 



AFN-00208C 



8218/8219 



[pemoMoiMiif 



FUNCTIONAL DESCRIPTION 

The 6218/8219 is a bipolar Bus Control Chip which 
reduces component count in the interface between a 
master device and the system Bus. (Master device: 8080, 
8085, 8257 (DMA).) 

The 8218 and 8219 serve three major functions: 

1. Resolve bus contention. 

2. Guarantee set-up and hold time of address/data lines 
to I/O and Memory read/write control signals 
(adjustable by external capacitor). 

3. Provide sufficient drive on all bus command lines. 



BPRO is used to allow lower priority devices to gain the 
bus »w hen a seria l prior ity resolving structure is used. 
BPRO would go to &PRN of the next lower priority Master. 

When prio rity is granted to the Master (a low on BPRN and 
a high on BUSY) the Master outpu ts a BU SY signal on the 
next falling edge of BCLK. The BUSY signal locks the 
master onto the bus and prohibits the enable of any other 
masters onto the bus. 

At the same ti me BUSY goes active, Address and Data 
Enable (ADEN) goe s activ e signifying that the Master has 
control of the bus. ADEN is often used to, enable the bus 
drivers. 



Bus Arbitration Logic 

Bus Arbitration Logic activity begins when the Ma ster 
makes a request for use of the bu s on BCR1 or BCR2. The 
request is strobed in by RSTB. Following the next two 
falling edges of the bus clo ck (BCLK) the 8218/8219 
outputs a bus request (BREQ) and forces Bus Priority Out 
inactive (BPRO). See Figures 1a and 1b. 

BREQ is used for requesting the bus when priority is 
decided by a parallel priprity resolver circuit. 



The Bus will be released only if the master loses priority; is 
not in the middle of a transfer, and Override is not active 
or, if the Master stops requesting the bus, is not in the 
middle of a data transfer, and Override is not active. ADEN 
then goes inactive. 

Provision has been made in the 8218 to allow bus- 
synchro nous reques ts. Th is mode is activated when 
BCR1, BCR2 and RSTB are all low. This action 
asynchronously sets the synchronization flip flop (FF2) in 
Figure 3a. 



ADEN- 



*> — ;=D 



RSTB- 



t> 



3>i 



ASYNCH. 
REQUEST 



SYNCH. 
REQUEST 



PRIORITY 

AND 
REQUEST 
LOGIC 



► BUSY 

► BREQ 



-BCLK 

-inTt 



Figure 3a. 8218 Bus Arbitration Logic 



2-70 



AFN-00208C 



8218/8219 



ADEN - 
OVRIDE - 



8CR1- 
BCR2- 



RSTB - 



ASYNCH. 
REQUEST 



SYNCH 
REQUEST 



PRIORITY 

AND 
REQUEST 
LOGIC 



- BUSY 
► BREQ 



- BPRN 



- BCLK 

-inTt 



Figure 3b. 8219 Bus Arbitration Logic 



Timing Logic 

Timing Logic activity begins with th e rising edge of XSTR 
(Transfer Start Request) or with ADEN going a ctive, 
whichever occurs second. This action causes XCY 
(Transfer Cycle) to go active. 50-200ns later (depending on 
resistance and capacitance at DLYADJ) the appropriate 
Control Outputs will go active if the control input is active. 

XSTR can be raised after the command goes active in the 
current transfer cycle so that a new transfer can be 
initiated immediately after the current transfer is 
complete. 

A negative going edge on X CP (Tr ansfer Complete) will 
cause the Control Outputs (MRDC, etc.) to go inactive. 
50-20 0ns later (depending on capacitance at DLYADJ) 
XCY will go inactive indicating the transfer cycle is 
completed. 

Additionallbgic within t he 82 18/8219 guarantees that if a 
transfer cy cle is st arted (XCY is active), but the bus is not 
requested (BREQ is inactive) and there is no command 
request input (ANYR is output low), then the transfer cycle 
will be cleared. This allows the bus to be released in 
applications where advanced bus recfuests are generated 
but the processor enters a HALT mode. 



Control Logic 

The control outputs are generated in the 821 9 by decoding 
the 8085 system control outputs (i.e., RD, WR, IO/M) or in 
the 8218 by directly buffering the control inputs to the 
control outputs for use in an 8080 or DMA system (see 
Figures 4a and 4b). The control outputs may be held high 
(inactive) by the Timing Logic. Also the control outputs are 
enabled when the Master gains control of the bus and 
disabled when control is relinquished. 

The Control Logic also has two other outputs, ANYR (Any 
Request) and RDD (Read Data). ANYR goes high (active) if 
any control requests (IOWR, etc.) are active. RDD controls 
the direction of the Masters Bi-directional Data Bus 
Drivers. The Bus Driver will always be in the Write mode 
(RDD = Low) except from the start of a Read Control 
Request to 25 to 70ns after XCP is activated. 



MRDR- 
IORR- 

MWTR- 
IOWR- 



OUTPUT 
CONTROL 
LOGIC 



- MRDC 

► iORC 

► MWTC 

- iowc 



CONTROL 

OUTPUT 

INACTIVE 



Figure 4a. 8218 Control Logic 



DECODING 
AND 
OUTPUT 
CONTROL 
LOGIC 



► MRDC 

► IORC 

► MWTC 
- IOWC 



CONTROL 

OUTPUT 

INACTIVE 



Figure 4b. 8219 Control Logic 



2-71 



AFN-00208C 



int^l 8218/8219 IPl^iyiMflM«^ 



ABSOLUTE MAXIMUM RATINGS* 



Ambient Temperature Under Bias 0°C to 70° C 

Storage Temperature -65° C to +150° C 

Supply Voltage (Vcc) -0.5V to +7V 

Input Voltage -1.0V to Vcc + 0.25V 

Output Current 100mA 



D.C. CHARACTERISTICS (T A = 0°C to 70°C; V cc 



*NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 

$V ± 5%) 







Limits 






Symbol 


Parameter 


Min. 


Typ. 


Max. 


Unit 


Test Conditions 


Vc 


Input Clamp Voltage 






-1.0 


V 


V C c = 0.0V, l c = -5 mA 


If 


Input Load Current 
MRDR/INTA/MWTR/WR 
IORR/RD, IOWR/IO/M 






-0.5 


mA 


Vcc = 5.25V 
Vf — 0.45V 




Other 






-u.o 


mA 




Ir 


Input Leakage Current 






100 


AiA 


Vcc = 5.25 
Vr = 5.25 


Vth ■ 


Input Threshold Voltage 


0.8 




2.0 


V 


Vcc = 5V 


Ice 


Power Supply Current 




200 


,240 


mA 


Vcc = 5.25V 


Vol 


Output Low Voltage 










Vcc = 4.75 




MRDC, MWTC, IORC, IOWC 






0.45 


V 


lOL - 32mA 




BREQ, BUSY 






0.45 


V 


Iol = 20mA 




XCY, RDD, ADEN 






0.45 


V 


Iol = 16mA 




BPRO, ANYR 






0.45 


V 


jOL = 3.2mA 


Voh 


Output High Voltage 










Vcc = 4.75V 




MRDC, MWTC, IORC, IOWC 


2.4 








Ioh = -2mA 




All Other Outputs 


2.4 








I OH = -400/xA 


los 


Short Circuit Output Current 


-10 




-90 


mA 


Vcc = 5.25V, Vo = 0V 


lO (OFF) 


Tri-State Output Current 






-100 


mA 


Vcc = 5.25V, Vo = ,0.45V 










+100 


mA 


Vcc = 5.25V, Vo = 5.25V 




Input Capacitance Except Busy 




10 


20 


. pF 




C|0 


Input Capacitance Busy 




25 


35 


PF 





8218/8219 XSTR TO OUTPUT DELAY (T SC d) 



175 




0 100 200 300 400 500 600 700 800 900 
OHMS 



One Shot Delay Versus Delay Adjust Capacitance And Resistance 

2-72 



AFN-00208C 



8218/8219 



[PG&OIMOIMIW 



A.C. CHARACTERISTICS (T A = o°c to 70°C; v cc = 5V ± 5%) 



Symbol 


Parameter 


Limits 


Unit 


Toftt Conditions 


Min. 


Tvd 


Max. 


tBCY 


Ru^ filnok Ox/pIp Time» 


100 










tpw 


Rnc f*.\r\r\t Pi ilea WiHth 


35 




0.65 tBCY 






tRQS 


RSTB to BCLK Set-Up Time 


25 






ns 




tcss 


RHRi nnrl RP.Ro tn RQTR 
Dun i aliU Dun2 IW no 1 D 

Set-Up Time 


15 


• 




ns 




tCSH 


□ pp. onrl RPPo tn PCTR 
DOn1 alio IU no 1 D 

Hold Time 


15 






ns 




tRQD 


BCLK to BREQ Delay 






35 


ns 




tPRNS 


BPRN to BCLK Set-UD Time 


23 






ns 




tBNO 


BRPN to BPRO Delay 






30 


ns 




tBYD 


BCLK to BUSY Delay 






55 


ns 




tCAD 


MRDR, MWTR, IORR, IOWR 
to ANYR Delay 






30 


ns 




tsxD 


XSTR to XCY Delay 






40 


ns 




tSCD 


XSTR to MRDC, MWTC, IORC, 
IOWC Delay 


50 




200 


ns 


Adjustable by External R/C 


txsw 


XSTR Pulse Width 


30 






ns 




tXCD 


XCP to MRDC, MWTC, IORC, 
IOWC Delav 

1 VVV w L/vl CI y 






50 


ns 




txcw 


VHP PiiIqp WiHth 


35 






ns 




tCCD 


XCP to XCY Delay 


50 




200 


ns 


Adjustable by External R/C 


tCMD 


MRDR, MWTR, IORR, IOWR 
to MRDC, MWTC, IORC, IOWC 






35 


ns 




tCRD 


MRDR, MWTR, IORR, IOWR 
to RDD Delay 






25 


ns 




tRW 


RSTB Min. Neg. Pulse Width 


30 






ns 




tCPD 


BCLK to BPRO Delay 






40 


ns 




tXRD 


XCP to RDD Delay 


25 




70 


ns 





A.C. TESTING INPUT, OUTPUT WAVEFORM 



A.C. TESTING LOAD CIRCUIT 




A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 ' AND 0 45V FOR 
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A 
LOGIC 1 AND 0 ' 



DEVICE 
UNDER 
TEST 



Vi = 2 4V 
R L = 750ft 
C L = 100 pF 

Cl INCLUDES JIG CAPACITANCE 



2-73 



AFN-00208C 



8218/8219 



WAVEFORMS 



SYNCHRONOUS BUS TIMING (System Bus Previously Not In Use) 



k— tpw— 4 



"\ r 



/ REQUEST FOR ACQUISITION OF THE BUS 



«BNO"^» k 'BNO 



J 



tcPD 



CONTROL CYCLE (System Bus Previously Not In Use) 



MRDR MWTR 
iORR IOWR 



MRDC MWTC 
IORC iowc 



f 



Jf 

X 



X 



J 



x 



j 



X 



2-74 



AFN-00208C 



8218/8219 



WAVEFORMS (Continued) 

__ — , 1— 

BUS CONTROL EXCHANGE (Master No. 1 Leaving Bus And Master No. 2 Getting On Bus) 




2-75 



AFN-00208C 



8218/8219 



MEUBflll 



8224 
READY 



6 



01 

02 

READY 



V 



MEMR 

MEMW 

STSB IOR 



i 



MRDR 


MRDC 


MWTR 


MWTC 


IORR 


IORC 


IOWR 


IOWC 


BCR1 


BREQ 


BCR2 


BUSY 


8218 






BCLK 


RSTB 
ADEN 


BPRN 


DLYADJ 


BPRO 


XCP 




XSTR 




ANYR , N|T 





- RESET 

- XACK 
(TRANSFER 
ACKNOWLEDGE) 



MCS-80® CPU With 8218 



A- 
V 



WR 
RD 
IO/M 
INTA 
ALE 
So 



T 



WR 


MRDC 


RD 


MWTC 


\0/Nl 


IORC 


ASRQ 


IOWC 


RSTB 




BCR1 


BREQ 


BCR2 






BUSY 


8219 






BCLK 


ADEN 


§PRN 


DLYADJ 




XCP 


BPRO 


XSTR 




ANYR j^pf 





- RESET 
-XACK 

(TRANSFER 

ACKNOWLEDGE) 



MCS-85® CPU With 8219 



2-76 



AFN-00208C 



intel 



8218/8219 IPKILOIMIONlM^f 



J 



c 



WR 
RD 
IO/M 

Inta 

ALE 
So 
Si 



READY IS SET UP 
FOR LOCAL 
MEMORY THAT 
NEEDS NO WAIT 
STATES 



BUS 
ACCESS 
DECODE 
LOGIC 




USE FALLING EDGE OF ALE TO INITIATE DECODE 
LOGIC'S SELECTION OF THE BUS 



m 

- / 



1Z 



c 



WR RDD MRDC 
RD MWTC 
IO/M IORC 










ASRQ IOWC 
RSIB 

BCR1 BREQ 

BCR2 BUSY 
8219 

BCLK 










ADEN BPRN 
DLYADJ 

BPRQ 

xcp DrMU 

XSTR 

ANYR TNTf 







✓ 



LEVEL ACTIVATED 
LATCH 
, "TRANSPARENT" 
FLIP FLOP 



T0BCR2 
AND XSTR 
AND GATE 



- RESET 

-Rack 

(TRANSFER 
ACKNOWLEDGE) 



MCS-85® CPU With 8219 Using Local Memory 



2-77 



AFN-00208C 



8218/8219 



TO/FROM HIGHEST 
PRIORITY BUS MASTER 



li 



REQUEST 


ADEN 


8218 

BUSY BPR 


0" BCLK 



li 



REQUEST 


ad~en 


8219 




BUSY BPRN" BP? 


(0 ICTK 



"DAISY CHAIN " CONFIGURATION 



li 



REQUEST 


ADEN 


8219 




§U§Y BREQ BPRN 


BCLK 



11 



REQUEST ADEN 
8218 

BUSY BREQ BPRN BCLK 



PRIORITY 

RESOLVING 

LOGIC 



PARALLEL REQUEST CONFIGURATION 



11 



REQUEST 


ADEN 


8218 




BUSY BPRN 


BCLK 



REQUEST ADEN 
8219 

BUSY BREQ BPRN BCLK 



TWo Methods of Connecting Multiple 821 8/821 9' s To Resolve Bus Contention Among Multiple Masters 



2-78 



8224 

CLOCK GENERATOR AND DRIVER 
FOR 8080A CPU 



Single Chip Clock Generator/Driver for 
8080A CPU 

Power-Up Reset for CPU 
Ready Synchronizing Flip-Flop 
Advanced Status Strobe 



■ Oscillator Output for'External System 
Timing 

■ Crystal Controlled for Stable System 
Operation 

■ Reduces System Package Count 

■ Available in EXPRESS 

- Standard Temperature Range 



The Intel® 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by the 
designer to meet a variety of system speed requirements. 

Also included are circuits to provide power-up reset, advance status strobe, and synchronization of ready. 

The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A. 



|Tf> XTAL1 
[l4> XTAL2 — 
[l?> TANK 



CLOCK 
GEN. 



4> 2 D 0,A 



[|^> SYNC - 
f£> RESIN ^» 

(T> RDYIN 



SCHMITT 
INPUT 




D Q 



-OSC [T?> 

-*i E> 

-0 2 [l0> 
-0 2 (TTL)[?> 

STSTB [7> 

- RESET (T> 

- READY [7> 



RESET | " 


1 


16 


ZZKc 


RESIN j 


2 


15 


I XTAL 1 


RDYIN | 


3 


14 


I XTAL 2 


READY | 


4 


13 


| TANK 


SYNC| 




8224 




5 


12 


lose 


0 2 (TTU | 


6 


11 




STSTB [ 


7 


10 




gnd| 


8 


9 


Z1 V DD 



RESIN 


RESET INPUT 






RESET 


RESET OUTPUT 




XTAL 1 


( CONNECTIONS 


RDYIN 


READY INPUT 




XTAL 2 


( FOR CRYSTAL 


READY 


READY OUTPUT 




TANK 


USED WITH OVERTONE XTAL 


SYNC 


SYNC INPUT 




OSC 


OSCILLATOR OUTPUT 


STSTB 


STATUS STB 




02 (TTL) 


<t> 2 CLK (TTL LEVEL) 




(ACTIVE LOW) 




V CC * 


+5V 


4>\ 


{8080 




v DD 


+12V 


02 


i CLOCKS 




GND 


ov 



Figure 1. Block Diagram 



Figure 2. Pin Configuration 



2-79 



8224 



ABSOLUTE MAXIMUM RATINGS* 'NOTICE: Stresses above those listed under "Absolute 

Maximum Ratings" may cause permanent damage to the 
Temperature Under Bias 0°C to 70°C device. This is a stress rating only and functional opera- 
Storage Temperature -65°C to 1 50°C . tion of the device at these or any other conditions above 

Supply Voltage, V C c -0.5V to +7V those indicated in the operational sections of this specifi- 

Supply Voltage, Vdd -0.5V to +1 3.5V car/on is not implied. Exposure to absolute maximum 

I nput Voltage - 1 .5V to +7V rating conditions for extended periods may affect device 

Output Cu rrent « 1 00mA reliability. 



D.C. CHARACTERISTICS (T A = o°c to 70°c, v C c = +5.0V ±5%, v DD = +12V ±5%) 







Limits 






Symbol 


Parameter 


Min. 


Typ. 


Max. 


Units 


Test Conditions 


If 


Input Current Loading 






-.25 


mA 


V F = .45V 


Ir 


Input Leakage Current 






10 


liA 


V R = 5.25V 


v c 


Input Forward Clamp Voltage 






1.0 


V 


lc = -5mA 


V|L 


Input "Low" Voltage 






.8 


V 


V cc = 5.0V 


V| H 


Input "High" Voltage 


2.6 
2.0 






V 


Reset Input 
All Other Inputs 


V|H-V, L 


RESIN Input Hysteresis 


.25 






V 


V CC = 5.0V 


Vol 


Output "Low" Voltage 






.45 
.45 


V 
V 


(01,02)* Ready, Reset, ST STB 

Iql =2.5mA , 

All Other Outputs 

Iql = 15mA 


VfJH 


Output "High" Voltage 

01 , 02 

READY, RESET 
All Other Outputs 


9.4 
3.6 
2.4 






V 
V 
V 


Iqh = -100mA 
I 0 h = - 100m A 
Iqh = -1mA 


lsc [1] 


Output Short Circuit Current 
(All Low Voltage Outputs Only) 


-10 




-60 


mA 


V 0 =ov 

V CC = 5.0V 


•cc 


Power Supply Current 






115 


mA 




•dd 


Power Supply Current 






12 


mA 





Note: 1 . Caution, 0-j and 02 output drivers do not have short circuit protection 



Crystal Requirements 

Tolerance: 0.005% at 0°C-70°C 
Resonance: Series (Fundamental)* 
Load Capacitance: 20-35 pF 
Equivalent Resistance: 75-20 ohms 
Power Dissipation (Min): 4 mW 

*With tank circuit use 3rd overtone mode. 



2-80 



AFN-00732C 



8224 



A.C. CHARACTERISTICS (v cc = +5.0V ±5%, v D0 = +12.OV ±5%, T A = o°c to 70°C) 



Symbol 


Parameter 


Limits 


Units 


Test 
Conditions 


Min. 


Typ. 


Max. 




01 Pulse Width 


?£Y-20ns 
9 






ns 


Ci = 20 dF to 50 nF 


t02 


02 Pulse Width 


5tcy OI - 
=— 35ns 
9 






tD1 


01 to 02 Delay 


0 






t-02 


02 to 0-j Delay 


14ns 

9 






tQ3 


01 to 02 Delay 


2tcy 
9 




^ + 20ns 
9 


tR 


01 and 02 Rise Time 






20 




(hi anH d)^ Fall Timp 

Y'J 01 IW TTV Oil 1 IIIIC 






20 


*D</>2 


02 to 02 (TTL) Delay 


-5 




+15 


ns 


0 2 TTL,CL=3O 
R 1=30012 
R 2 =600n 


*DSS 


02 to STSTB Delay 
• 


^V-30ns 
9 




6tcy 
9 






tpw 


STSTB Pulse Width 


— — 1 ons 
9 








STSTB, CL=15pF 
R1 = 2K 
R 2 = 4K 


*DRS 


RDYIN Setup Time to 
Status Strobe 


CA 4tcy 

50ns - 

9 






*DRH 


RDYIN Hold Time 
After STSTB 


4tcy 
9 






*DR 


RDYIN or RESIN to 
02 Delay 


^-25ns 
9 








Ready & Reset 
CD=10pF 
Rl=2K 
R 2 =4K 


tCLK 


CLK Period 




tcy 
9 








fmax 


Maximum Oscillating 
Frequency 






27 


MHz 




C ln 


Input Capacitance 






8 


PF 


V CC =+5.0V 
V DD =+12V 
V B IAS=2.5V 
f=1MHz 



2-81 AFN-00732C 



8224 



A.C. CHARACTERISTICS (Continued) (For t C y = 488.28 ns) (t a = o°c to 70°c, v DD = +5V ±5%; 

V DD = +12V±5%) 







Limits 






Symbol 


Parameter 


Min. 


Typ. 


Max. 


Units 


Test Conditions 


V1 


0! Pulse Width 


89 






ns 




t CY =488.28ns 


x 4>2 


02 Pulse Width 


236 






ns 






tD1 


Delay 0i to 0 2 


0 






ns 






tQ2 


Delay 02 to 01 


95 






ns 




_ 01 & 02 Loaded to 


tD3 


Delay 01 to 02 Leading Edges 


109 




129 


ns 




\-»L — £\j to oupr 


tr 


Output Rise Time 






20 


ns 






tf 


Output Fall Time 






20 


ns 






tDSS 


0 2 to STSTB Delay 


296 




326 


ns 




x O<t>2 


02 to 02 (TTL) Delay 


-5 




+15 


ns 




tpw 


Status Strobe Pulse Width 


40 






ns 


Ready & Reset Loaded 
to 2mA/10pF 


tDRS 


RDYIN SetupTimeto STSTB 


-167 






ns 


tQRH 


RDYIN Hold Time after STSTB 


217 






ns 


AM measurements 


tDR 


READY or RESET 
to 02 Delay 


192 






ns 


referenced to 1.5V 
unless specified 
otherwise. 


f MAX 


Oscillator Frequency 






18.432 


MHz 





A.C. TESTING INPUT, OUTPUT WAVEFORM 



INPUT/OUTPUT 



/ 4 

^> TEST POINTS <^ 



A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC " 1 " AND 0.45V FOR 
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1 " 
AND 0.8V FOR A LOGIC "0" (UNLESS OTHERWISE NOTED). 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 



C L INCLUDES JIG CAPACITANCE 



2-82 



AFN-00732C 



8224 



WAVEFORMS 



/ 



i3F 



RDYINOR RESIN 



|s, C3t i 



X 



VOLTAGE MEASUREMENT POINTS: <*>2 Logic "0" = 1.0V, Logic "1" = 8.0V. All other signals measured at 1.5V. 



2-83 



8228/8238 

SYSTEM CONTROLLER AND BUS DRIVER 
FOR 8080A CPU 



■ Single Chip System Control for 
MCS-80® Systems 

■ Built-in Bidireotional Bus Driver for 
Data Bus Isolation 

■ Allows the Use of Multiple Byte 
Instructions (e.g. CALL) for Interrupt 
Acknowledge 



■ User Selected Single Level Interrupt 
Vector (RST7) 

■ 28-Pin Dual In-Line Package 

■ Reduces System Package Count 

■ 8238 Had Advanced IOW/MEMW for 
Large System Timing Control 

■ Available in EXPRESS 

- Standard Temperature Range 



The Intel 9 8228 is a single chip system controller and bus driver for MCS-80. It generates all signals required to 
directly Interface MCS-80 family RAM, ROM, and I/O components. 

A bidirectional bus driver is included to provide high system TTL fan-out. It also provides isolation of the 8080 data bus 
from memory and I/O. This allows for the optimization of control signals, enabling the systems designer to use slower 
memory and I/O. The isolation of the bus driver also provides for enhanced system noise immunity. 

A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small system 
requirements. The 8228 also generates the correct control signals to allow the use of multiple byte instructions (e.g., 
CALL) in response to an interrupt acknowledge by the 8080A. This feature permits large, interrupt driven systems to 
have an unlimited number of interrupt levels. 

The 8228 is designed to support a wide variety of system bus structures and also reduce system package count for 
cost effective, reliable design of the MCS-80 systems. 

Note: The specifications for the 3228/3238 are identical with those for the 8228/8238 



CPU 
DATA 
BUS 



— OB 6 

— OB 7 



SYSTEM DATA BUS 



DRIVER CONTROL 



StStB • 
DBIN - 

m ■ 

HLDA - 



MEM R 
MEM W 

l76~R 

iTow 

60517} 

inTa 



STSTB 
HLDA C 
WR C 

DBIN f~ 
DB4 C 

04 C 
DB7 C 

D7 £ 
DB3 C 

03 C 
DB2 (3 

DB0C 

gndC 



2p 



□ v cc 

I]i76vv 

□ mTmw 
3 iTor 

^2 MEMR 
3 INTA 
2} BUSEN 

□ D6 

□ DB6 

□ OB 

D° 85 

□ oi 

□ DB| 

□ d* 



D7D0 


DATA BUS (8080 SIDE) 




INTA 


INTERRUPT ACKNOWLEDGE 


DB7 DBO 


DATA BUS (SYSTEM SIDE) 




HLDA 


HLDA (FROM 8080) 


l/OR 


I/O READ 




m 


WR (FROM 8080) 


l/OW 


I/O WRITE 




BUSEN 


BUS ENABLE INPUT 


MEMR 


MEMORY READ 




STSTB 


STATUS STROBE (FROM 8224) 


MEMW 


MEMORY WRITE 




Vcc 


♦5V 


DBIN 


DBIN (FROM 8080) 




GND 


0 VOLTS 



Figure 1. Block Diagram 



Figure 2. Pin Configuration 



2-84 




8228/8238 



'NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device, this is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not limited. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (T A = o°c to 70°c, v C c = 5V ±5%) 



Symbol 


Parameter 


Limits 


Unit 


Test Conditions 


Mm. 


1 yp.i • j 


Max. 


v c 


Input Clamp Voltage, All Inputs 




.75 


-1.0 


V 


V CC =4.75V; l c =-5mA 


If , 


Input Load Current, 
STSTB 






500 


uA 


= 5 25V 
V CC 3,wv 

V F =0.45V 


D 2 &D 6 






750 


MA 


D 0 , D^D^ D 5 , 
& D7 






250 


ma 


All Other Inputs 






250 


ma 


•r 


Input Leakage Current 
STSTB 






100 


/iA 


V CC = 5.25 V 
V R = 5.25V 


L)Bo-DB 7 






20 


MA 


All Other Inputs 






100 


ma 




V T h 


Input Threshold Voltage, All Inputs 


0.8 




2.0 


V 


V CC = 5V 


•cc 


Power Supply Current 




140 


190 


mA 


V CC =5.25V 


Vol 


Output Low Voltage, 
D0-D7 






.45 


V 


V CC =4.75V; l 0L =2mA 


All Other Outputs 






.45 


V 


l O L = 10mA 


V 0 H 


Output High Voltage, 
D 0 -D 7 


3.6 


3.8 




V 


V C c=4.75V;l O H=-10iuA 


All Other Outputs 


2.4 






V 


l 0 H = -1mA 


tos 


Short Circuit Current, All Outputs 


15 




90 


mA 


V CC =5V 


to (off) 


Off State Output Current, 
All Control Outputs 






100 


MA 


V C c=5.25V;V 0 =5.25 


-100 


ma 


V 0 =.45V 


l|NT 


INTA Current 






5 


mA 


(See INTA Test Circuit) 



Note 1 • Typical values are for Ta - 25°C and nominal supply voltages. 



ABSOLUTE MAXIMUM RATINGS 4 



Temperature Under Bias -0°C to 70 °C 

Storage Temperature -65°C to 150°C 

Supply Voltage, V cc - 0.5V to + 7V 

Input Voltage -1.5V to +7V 

Output Current 100 m A 



2-85 



AFN-00213C 




8228/8238 



CAPACITANCE (V B | A S = 2.5V, V C c = 5.0V, T A = 25°C, f = 1 MHz) 
This parameter is periodically sampled and not 100% tested. 







Limits 




Symbol 


Parameter 


Min. 


Typ.m 


Max. 


Unit 


C|N 


Input Capacitance 




8 


12 


pF 


COUT 


Output Capacitance 
Control Signals 




7 


15 


PF 


I/O 


I/O Capacitance 
(Dor DB) 




8 


15 


PF 



A.C. CHARACTERISTICS (T A = o°c to 70°c, v c c = 5V ±5%) 



Symbof 


Parameter 


Limits 


Units 


Condition 


Min. 


. Max. 


tpw 


Width of Status Strobe 


22 




ns 




tss 


Setup Time, Status Inputs D0-D7 


8 




ns 




tSH 


Hold Time, Status Inputs Dq-D 7 


5 




ns 




*DC 


Delay from STSTB to any Control Signal 


20 


60 


ns 


C L « 100pF 


*RR 


Delay from DBIN to Control Outputs 




30 


ns 


C L = 100pF 


tRE 


Delay from DBIN to Enable/Disable 8080 Bus 




45 


ns 


C L = 25pF 


tRD 


Delay from System Bus to 8080 Bus during Read 




30 


ns 


C L = 25pF 


tWR 


Delay from WR to Control Outputs 


5 


45 


ns 


C L = 100pF 


t WE 


Delay to Enable System Bus DB 0 -DB 7 after STSTB 




30 


ns 


C L = 100pF 


twD 


Delay from 8080 Bus D 0 -D 7 to System Bus 
DB0-DB7 during Write 


5 


40 


ns 


C L = lOOpF 


tE 


Delay from System Bus Enable to System Bus DB0-DB7 




30 


ns 


C L = 100pF 


tHD 


HLDA to Read Status Outputs 




25 


ns 




X DS 


Setup Time, System Bus Inputs to HLDA 


10 




ns 






Hold Time, System Bus Inputs to HLDA 


20 




ns 


C L = 100pF 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 




For D0-D7: R1 = AKfl, R2 = 

Cl - 25pF. For all other outputs: 

R1 =500f2, R 2 = 1K.n,CL= 100pF. 




INTA Test Circuit (for RST 7) 



2-86 



AFN-00213C 



8228/8238 



WAVEFORM 



SYSTEM BUS DURING READ 



8080 BUS DURING READ 



IOW OR MEM W 



8080 BUS DURING WRITE 



SYSTEM BUS ENABLE 



SYSTEM BUS DURING WRITE f> < 



<z>c > 



-4 



TV 



SYSTEM BUS OUTPUTS < 



> 




VOLTAGE MEASUREMENT POINTS: Dq-D 7 (when outputs) Logic "0" = 0.8V, Logic "1" = 3.0V. All other signals measured 

at 1.5V. 



*ADVANCED IOW/MEMW FOR 8238 ONLY. 



2-87 



AFN-00213C 



intel 



8237A/8237A-4/8237A-5 
HIGH PERFORMANCE 
PROGRAMMABLE DMA CONTROLLER 



i Enable/Disable Control of Individual 
DMA Requests 

Four Independent DMA Channels 

Independent Autoinitialization of all 
Channels 

Memory-to-Memory Transfers 
Memory Block Initialization 
Address Increment or Decrement 



High performance: Transfers up to 1.6M 
Bytes/Second with 5 MHz 8237A-5 
Directly Expandable to any Number of 
Channels 

End of Process Input for Terminating 
Transfers 

Software DMA Requests 

i Independent Polarity Control for DREQ 

and DACK Signals 
i Available in EXPRESS 

- Standard Temperature Range 



The 8237A Multimode Direct Memory Access (DMA) Controller Is a peripheral interface circuit for microprocessor sys- 
tems. It is designed to improve system performance by allowing external devices to directly transfer information from 
the system memory. Memory-to-memory transfer capability is also provided. The 8237A offers a wide variety of pro- 
grammable control features to enhance data throughput and system optimization and to allow dynamic reconfigura- 
tion under program control. 

The 8237A is designed to be used in conjunction with an external 8-bit address register such as the 8282. It contains 
four independent channels and may be expanded to any number of channels by cascading additional controller chips. 

The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be 
individually programmed to Autoinitialize to its original condition following an End of Process (EOP). 

Each channel has a full 64K address and word count capability. 

The 8237A-4 and 8237A-5 are 4 MHz and 5 MHz selected versions of the standard 3 MHz 8237A respectively. 




Figure 1. Block Diagram 



Figure 2. 
Pin Configuration 



2-88 



8237A/8237A-4/8237A-5 



Table 1. Pin Description 



Symbol 


Type 


Name and Function 


v C c 




Power: + 5 volt supply. 


Vss 




Ground: Ground. 


CLK 




Clock Input: Clock Input controls 
the internal operations of the 
8237A and its rate of data trans- 
fers. The input may be driven at up 
to 3 MHz for the standard 8237A 
and up to 5 MHz for the 8237A-5. 


CS 


I 


Chip Select: Chip Select is an ac- 
tive low input used to select the 
8237A as an I/O device during the 
idle cycle. This allows CPU com- 
munication on the data bus. 


RESET 


I 


Reset: Reset is an active high in- 
put which clears the Command, 
Status, Request and Temporary 
registers. It also clears the 
first/last flip/flop and sets the 
Mask register. Following a Reset 
the device is in the Idle cycle. 


READY 


I 


Ready: Ready is an input used to 
extend the memory read and write 
pulses from the 8237A to accom- 
modate slow memories or I/O per- 
ipheral devices. Ready must not 
make transitions during its speci- 
fied setup/hold time. 


HLDA 




Hold Acknowledge: The active 
high Hold Acknowledge from the 
CPU indicates that it has relin- 
quished control of the system 
busses. 


DREQ0-DREQ3 


I 


DMA Request: The DMA Request 
lines are individual asynchronous 
channel request inputs used by pe- 
ripheral circuits to obtain DMA 
service. In fixed Priority, DREQO 
has the highest priority and 
DREQ3 has the lowest priority. A 
request is generated by activating 
the DREQ line of a channel. DACK 
will acknowledge the recognition 
of DREQ signal. Polarity of DREQ 
is programmable. Reset intializes 
these lines to active high. DREQ 
must be maintained until the corre- 
sponding DACK goes active. 


DB0-DB7 


I/O 


Data Bus: The Data Bus lines are 
bidirectional three-state signals 
connected to the system data bus. 
The outputs are enabled in the Pro- 
gram condition during the I/O Read 
to output the contents of an Ad- 
dress register, a Status register, 
the Temporary register or a Word 
Count register to the CPU. The out- 
puts are disabled and the inputs 
are read during an I/O Write cycle 
when the CPU is programming the 
8237A control registers. During 
DMA cycles the most significant 8 
bits of the address are output onto 
the data bus to be strobea into an 
external latch by ADSTB. In mem- 



Symbol 



IOR 



IOW 



EOP 



A0-A3 



Type 



I/O 



I/O 



I/O 



I/O 



Name and Function 



ory-to-memory operations, data 
from the memory comes into the 
8237A on the data bus during the 
read-from-memory transfer. In the 
write-to-memory transfer, the data 
bus outputs place the data into the 
new memory location. 



I/O Read: I/O Read is a bidirec- 
tional active low three-state line. In 
the Idle cycle, it is an input control 
signal used by the CPU to read the 
control registers. In the Active cy- 
cle, it is an output control signal 
used by the 8237A to access data 
from a peripheral during a DMA 
Write transfer. 



I/O Write: I/O Write is a bidirec- 
tional active low three-state line. In 
the Idle cycle, it is an input control 
signal used by the CPU to load in- 
formation into the 8237 A. In the Ac- 
tive cycle, it is an output control 
signal used by the 8237A to load 
data to the peripheral during a 
DMA Read transfer. 



End of Process: End of Process is 
an active low bidirectional signal. 
Information concerning the com- 
pletion of DMA services is a vail- 
able at the bidirectional EOP pin. 
The 8237A allows an external sig- 
nal to terminate an active DMA 
service. Th is is accomplished' by 
pulling t he E OP input low with an 
external EOP signal. The 8237A al- 
so generates a pulse when the ter- 
minal count (TC) for any channel is 
reached. This generates an EOP 
sign al which is output throug h the 
EOP Line. The reception of EOP, 
either internal or external, will 
cause the 8237A to terminate the 
service, reset the request, and, if 
Autoinitialize is enabled, to write 
the base registers to the current 
registers of that channel. The mask 
bit and TC bit in the status word 
will be set for t he currently active 
channel by EOP unless the channel 
is programmed for Autoinitialize. In 
that case, the mask bit remains un- 
changed. During memory-to-memory 
transfers, EOP will be output when 
the TC for channel 1 occurs. EOP 
should be tied high with a pull-up 
resistor if it is not used to prevent 
erroneous end of process inputs. 



Address: The four least significant 
address lines are bidirectional 
three-state signals. In the Idle cy- 
cle they are inputs and are used by 
the CPU to address the register 
to be loaded or read. In the Active 
cycle they are outputs and provide 
the lower 4 bits of the output 
address. 



2-89 



AFN-00789D 



8237A/8237A-4/8237A-5 



Table 1. Pin Description (Continued) 



Symbol 


Type 


Name and Function 


A4-A7, 


0 


Address: The four most significant 
address lines are three-state out- 
puts and provide 4 bits of address. 
These lines are enabled only during 
the DMA service. 


HRQ 


0 


Hold Request: This is the Hold Re- 
quest to the CPU and is used to re- 
quest control of the system bus. If 
the corresponding mask bit is 
clear, the presence of any valid 
DREQ causes 8237A to issue the 
HRQ. After HRQ goes active at 
least one clock cycle (TCY) must 
occur before HLDA goes active. 


DACK0-DACK3 


0 


DMA Acknowledge: DMA Ac- 
knowledge is used to notify the in- 
dividual peripherals when one has 
been granted a DMA cycle. The 
sense of these lines is program- 
mable. Reset initializes them to ac- 
tive low. 



FUNCTIONAL DESCRIPTION 

The 8237A block diagram includes the major logic 
blocks and all of the internal registers. The data inter- 
connection paths are also shown. Not shown are the 
various control signals between the blocks. The 8237A 
contains 344 bits of internal memory in the form of 
registers. Figure 3 lists these registers by name and 
shows the size of each. A detailed description of the 
registers and their functions can be found under 
Register Description. 



Name 


Size 


Number 


Base Address Registers 


16 bits 




Base Word Count Registers 


16 bits 




Current Address Registers 


16 bits 




Current Word Count Registers 


16 bits 




Temporary Address Register 


16 bits 




Temporary Word Count Register 


16 bits 




Status Register 


8 bits 




Command Register 


8 bits 




Temporary Register 


8 bits 




Mode Registers 


6 bits 




Mask Register 


4 bits 




Request Register 


4 bits 





Figure 3. 8237A Internal Registers 

The 8237A contains three basic blocks of corttrol logic. 
The Timing Control block generates internal timing and 
external control signals for the 8237A. The Program 
Command Control block decodes the various com- 
mands given to the 8237A by the microprocessor prior 
to servicing a DMA Request. It also decodes the Mode 
Control word used to select the type of DMA during the 
servicing. The Priority Encoder block resolves priority 
contention between DMA channels requesting service 
simultaneously. 

The Timing Control block derives internal timing from 
the clock input. In 8237A systems this input will usually 



Symbol 


Type 


Name and Function 


AEN 


0 


Address Enable: Address Enable 
enables the 8-bit latch containing 
the upper 8 address bits onto the 
system address bus. AEN can also 
be used to disable other system bus 
drivers during DMA transfers. AEN 
is active HIGH. 


ADSTB 


0 


Address Strobe: The active high, 
Address Strobe is used to strobe the 
upper address byte into an external 
latch. 


MEMR 


0 


Memory Read: The Memory Read 
signal is an active low three-state 
output used to access data from the 
selected memory location during a 
DMA Read or a memory-to-memory 
transfer. 


MEMW 


0 


Memory Write: The Memory Write 
is an active low three-state output 
used to write data to the selected 
memory location during a DMA 
Write or a memory-to-memory 
transfer. 



be the <£2 TTL clock from an 8224 or CLK from an 
8085AH or 8284A. For 8085AH-2 systems above 3.9 M Hz, 
the 8085 CLK(OUT) does not satisfy 8237A-5 clock LOW 
and HIGH time requirements. In this case, an external 
clock should be used to drive the 8237A-5. 

DMA Operation 

The 8237A is designed to operate in two major cycles. 
These are called Idle and Active cycles. Each device cy- 
cle is made up of a number of states. The 8237A can 
assume seven separate states, each composed of one 
full clock period. State I (SI) is the inactive state. It is 
entered when the 8237A has no valid DMA requests 
pending. While in SI, the DMA controller is inactive but 
may be in the Program Condition, being programmed by 
the processor. State SO (SO) is the first state of a DMA 
service. The 8237A has requested a hold but the pro- 
cessor has not yet returned an acknowledge. The 8237A 
may still be programmed until it receives HLDA from the 
CPU. An acknowledge from the CPU will signal that 
DMA transfers may begin. S1, S2, S3 and S4 are the 
working states of the DMA service. If more time is 
needed to complete a transfer than is available with nor- 
mal timing, wait states (SW) can be inserted between S2 
or S3 and S4 by the use of the Ready line on the 8237A. 
Note that the data is transferred directly fr om the I/O 
device to m emor y (or vice versa) with IOR and MEMW (or 
MEMR and (OW) being active at the same time. The data 
is not read into or driven out of the 8237A in l/O-to- 
memory or memory-to-l/O DMA transfers. 

Memory-to-membry transfers require a read-from and a 
write-to-memory to complete each transfer. The states, 
which resemble the normal working states, use two 
digit numbers for identification. Eight states are re- 
quired for a single transfer. The first four states (S11, 
S12, S13, S14) are used for the read-from-memory half 



2-90 



AFN-00789D 



8237A/8237A-4/8237A-5 



and the last four states (S21, S22, S23, S24) for the write- 
to-memory half of the transfer. 

IDLE CYCLE 

When no channel is requesting service, the 8237A will 
enter the Idle cycle and perform "SI" states. In this 
cycle the 8237A will sample the DREQ lines every clock 
cycle to determine if any channel is requesting a DMA 
service. The device will also sample CS, looking for an 
attempt by the microprocessor tojyvrite or read the inter- 
nal registers of the 8237 A. When CS is low and HLDA is 
low, the 8237A enters the Program Condition. The CPU 
can now establish, change or inspect the internal defini- 
tion of the part by reading from or writing to the internal 
registers. Address lines A0-A3 are inputs to the device 
and sele ct w hich registers will be read or written. The 
IOR and IOW lines are used to select and time reads or 
writes. Due to the number and size of the internal regis- 
ters, an internal flip-flop is used to generate an addi- 
tional bit of address. This bit is used to determine the 
upper or lower byte of the 16-bit Address and Word 
Count registers. The flip-flop is reset by Master Clear or 
Reset. A separate software command can also reset this 
flip-flop. 

Special software commands can be executed by the 
8237A in the Program Condition. These com mands are 
decoded as sets of addresses with the CS and IOW. The 
commands do not make use of the data bus. Instruc- 
tions include Clear First/Last Flip-FLop and Master 
Clear. 

ACTIVE CYCLE 

When the 8237 A is in the Idle cycle and a non-masked 
channel requests a DMA service, the device will output 
an HRQ to the microprocessor and enter the Active cy- 
cle. It is in this cycle that the DMA service will take 
place, in one of four modes: 

Single Transfer Mode — In Single Transfer mode the 
device is programmed to make one transfer only. The 
word count will be decremented and the address dec- 
remented or incremented following each transfer. When 
the word count "rolls over" from zero to FFFFH, a Ter- 
minal Count (TC) will cause an Autoinitialize if the chan- 
nel has been programmed to do so. 

DREQ must be held active until DACK becomes active in 
order to be recognized. If DREQ is held active through- 
out the single transfer, HRQ will go inactive and release 
the bus to the system. It will again go active and, upon 
receipt of a new HLDA, another single transfer will be 
performed, in 8080A, 8085AH, 8088, or 8086 system this 
will ensure one full machine cycle execution between 
DMA transfers. Details of timing between the 8237A and 
other bus control protocols will depend upon the char- 
acteristics of the microprocessor involved. 

Block Transfer Mode — In Block Transfer mode the 
device is activated by DREQ to continue making trans- 
fers during the service until a TC, caused by word count 
going to FFFFH, or an external End of Process (EOP) is 
encountered. DREQ need only be held active until DACK 



becomes active. Again, an AutoinitiaiJzation will occur 
at the end of the service if the channel has been pro- 
grammed for it. 

Demand Transfer Mode — In Demand Transfer mode the 
device is programm ed to continue making transfers 
until a TC or external EOP is encountered or until DREQ 
goes inactive. Thus transfers may continue until the I/O 
device has exhausted its data capacity. After the I/O 
device has had a chance to catch up, the DMA service is 
re-established by means of a DREQ. During the time 
between services when the microprocessor is allowed 
to operate, the intermediate values of address and word 
count are stored in the 8237A Curren t Ad dress and Cur- 
rent Word Count registers. Only an E OP c an cause an 
Autoinitialize at the end of the service. EOP is generated 
either by TC or by an external signal. 

Cascade Mode-This mode is used to cascade more than one 
8237 A together for simple system expansion. The HRQ and 
HLDA signals from the additionaf8237A are connected to the 
DREQ and DACK signals of a channel of the initial 8237A. 
This allows the DMA requests of the additional device to 
propagate through the priority network circuitry of the preced- 
ing device. The priority chain is preserved and the new device 
must wait for its turn to acknowledge requests. Since the 
cascade channel of the initial 8237A is used only for prior- 
itizing the additional device, it does not output any address 
or control signals of its own. These could conflict with the 
outputs of the active channel in the added device. The 8237A 
will respond to DREQ and DACK but all other outputs except 
HRQ will be disabled. The ready input is ignored. 

Figure 4 shows two additional devices cascaded into an 
initial device using two of the previous channels. This 
forms a two level DMA system. More 8237 As could be 
added at the second level by using the remaining chan- 
nels of the first level. Additional devices can also be 
added by cascading into the channels of the second 
level devices, forming a third level. 



2ND LEVEL 



MICROPROCESSOR 


1ST LEVEL 


8237A 














HRQ DREQ 




HRQ 












HLDA DACK 




HLOA 


\ 










8237A 










DREQ 




HRQ 








DACK 




HLDA 








INITIAL DEVICE 


8237A 



ADDITIONAL 
DEVICES 



Figure 4. Cascaded 8237As 



2-91 



AFN-00789D 



8237A/8237A-4/8237A-5 



TRANSFER TYPES 

Each of the three active transfer modes can perform three 
different types of transfers. These are Read, Write and Verify. 
Write transfe rs move data from and I/O device to the memory 
by activating MEMW and R5R. Read tr ansfers mov e dat a from 
memory to an I/O device by activating MEMR and IOW. Verify 
transfers are pseudo transfers. The 8237A operates as in 
Read or Write transfers generating addresses, and responding 
to EOP, etc. However, the memory and I/O control lines all 
remain inactive. The ready input is ignored in verify mode. 



which fixes the channels in priority order based upon the 
descending value of their number. The channel with the lowest 
priority is 3 followed by 2, 1 and the highest priority channel, 
0. After the recognition of any one channel for service, the 
other channels are prevented from interferring with that ser- 
vice until it is completed. 

The second scheme is Rotating Priority. The last chan- 
nel to get service becomes the lowest priority channel 
with the Others rotating accordingly. 



Memory-to-Memory-To perform block moves of data from 
one memory address space to another with a minimum of 
program effort and time, the 8237A includes a memory-to- 
memory transfer feature. Programming a bit in the Command 
register selects channels 0 to 1 to operate as memory-to- 
memory transfer channels. The transfer is initiated by setting 
the software DREQ for channel 0. The 8237A requests a DMA 
service in the normal manner. After HLDA is true, the device, 
using four state transfers in Block Transfer mode, reads data 
from the memory. The channel 0 Current Address register is 
the source for the address used and is decremented or incre- 
mented in the normal manner. The data byte read from the 
memory is stored in the 8237A internal Temporary register. 
Channel 1 then performs a four-state transfer of the data from 
the Temporary register to memory using the address in its 
Current Address register and incrementing or decrementing it 
in the normal manner. The channel 1 current Word Count is 
decremented. When the word coun t of c hannel 1 goes to 
FFFFH, a TC is generated causing an EOP output terminating 
the service. 

Channel 0 may be programmed to retain the same ad- 
dress for all transfers. This allows a single word to be 
written to a block of memory. 

The 8237A will respond to external EOP signals during 
memory-to-memory transfers. Data comparators in 
block search schemes may use this input to terminate 
the service when a match is found. The timing of 
memory-to-memory transfers is found in Figure 12. 
Memory-to-memory operations can be detected, as an 
active AEN with no DACK outputs. 

Autoinitialize- By programming a bit in the Mode register, a 
channel may be set up as an Autoinitialize channel. During 
Autoinitialize initialization, the original values of the Current 
Address and Current Word Count registers are automatically 
restored from the Base Ad dress and Base Word count registers 
of that channel following EOP. The base registers are loaded 
simultaneously with the current registers by the micropro- 
cessor and remain unchanged throughout the DMA service. 
The mask bit is not altered when the channel is in Autoinitialize. 
Following Autoinitialize the channel is ready to perform 
another DMA service, without CPU intervention, as soon as a 
valid DREQ is detected. In order to Autoninitialize both chan- 
nels in a memory-to-memory transfer, both word counts should 
be programmed identically. If interrupted externally, EOP 
pulses should be applied in both bus cycles. 

Priority-The 8237A has two types of priority encoding avail- 
able as software selectable options. The first is Fixed Priority 



1st 

Service 

highest 0 
1 
2 

lowest 3 



2nd 
Service 

2*4- 
3-4- 



3rd 
Service 



3 -\ ° 



- service 

- request 



V 



- service 



With Rotating Priority in a single chip DMA system, any 
device requesting service is guaranteed to be recog- 
nized after no more than three higher priority services 
have occurred. This prevents any one channel from 
monopolizing the system. 

Compressed Timing — In order to achieve even greater 
throughput where system characteristics permit, the 
8237A can compress the transfer time to two clock 
cycles. From Figure 11 it can be seen that state S3 is 
used to extend the access time of the read pulse. By 
removing state S3, the read pulse width is made equal to 
the write pulse width and a transfer consists only of 
state S2 to change the address and state S4 to perform 
the read/write. S1 states will still occur when A8-A15 
need updating (see Address Generation). Timing for 
compressed transfers is found in Figure 14. 

Address Generation — In order to reduce pin count, the 
8237A multiplexes the eight higher order address bits 
on the data lines. State S1 is used to output the higher 
order address bits to an external latch from which they 
may be placed on the address bus. The falling edge of 
Address Strobe (ADSTB) is used to load these bits from 
the data lines to the latch. Address Enable (AEN) is used 
to enable the bits onto the address bus through a three- 
state enable. The lower order address bits are output by 
the 8237A directly. Lines A0-A7 should be connected to 
the address bus. Figure 11 shows the time relationships 
between CLK, AEN, ADSTB, DB0-DB7 and A0-A7. 

During Block and Demand Transfer mode services, 
which include multiple transfers, the addresses gener- 
ated will be sequential. For many transfers the data held 
in the external address latch will remain the same. This 
data need only change when a carry or borrow from A7 
to A8 takes place in the normal sequence of addresses. 
To save time and speed transfers, the 8237A executes 
S1 states only when updating of A8-A15 in the latch is 
necessary. This means for long services, S1 states and 
Address Strobes may occur only once every 256 trans- 
fers, a savings of 255 clock cycles for each 256 
transfers. 



2^92 



AFN-00789D 



8237A/8237A-4/8237A-5 



REGISTER DESCRIPTION 



Command Register 

7 6 5 4 3 2 1 



-Bit Number 



Current Address Register — Each channel has a 16-bit 
Current Address register. This register holds the value 
of the address used during DMA transfers. The address 
is automatically incremented or decremented after each 
transfer and the intermediate values of the address are 
stored in the Current Address register during the trans- 
fer. This register is written or read by the micro- 
processor in successive 8-bit bytes. It may also be reini- 
tialized by an Autoinitialize back to its original value. 
Autoinitialize takes place only after an EOP. 

Current Word Register — Each channel has a 16-bit Cur- 
rent Word Count register. This register determines the 
number of transfers to be performed. The actual number 
of transfers will be one more than the number pro- 
grammed in the Current Word Count register (i.e., pro- 
gramming a count of 100 will result in 101 transfers). The 
word count is decremented after each transfer. The 
intermediate value of the word count is stored in the reg- 
ister during the transfer. When the value in the register 
goes from zero to FFFFH, a TC will be generated. This 
register is loaded or read in successive 8-bit bytes by 
the microprocessor in the Program Condition. Follow- 
ing the end of a DMA service it may also be reinitialized 
by an Autoinitialization back to i ts or iginal value. Auto- 
initialize can occur only when an EOP occurs. If it is not 
Autoinitialized, this register will have a count of FFFFH 
after TC. 

Base Address and Base Word Count Registers — Each 
channel has a pair of Base Address and Base Word 
Count registers. These 16-bit registers store the original 
value of their associated current registers. During Auto- 
initialize these values are used to restore the current 
registers to their original values. The base registers are 
written simultaneously with their corresponding current 
register in 8-bit bytes in the Program Condition by the 
microprocessor. These registers cannot be read by the 
microprocessor. 

Command Register — This 8-bit register controls the 
operation of the 8237 A. It is programmed by the micro- 
processor in the Program Condition and is cleared by 
Reset or a Master Clear instruction. The following table 
lists the function of the command bits. See Figure 6 for 
address coding. 

Mode Register — Each channel has a 6-bit Mode regis- 
ter associated with it. When the register is being written 
to by the microprocessor in the Program Condition, bits 
0 and 1 determine which channel Mode register is to be 
written. 

Request Register — The 8237A can respond to requests 
for DMA service which are initiated by software as well 
as by a DREQ. Each channel has a request bit associ- 
ated with it in the 4-bit Request register. These are non- 
maskable and subject to prioritization by the Priority 
Encoder network. Each register bit is set or reset sepa- 



0 Memory-to-memory disable 

1 Memory-to-memory enable 

0 Channel 0 address hold disable 

1 Channel 0 address hold enable 
X If bit 0=0 

0 Controller enable 

1 Controller disable 



Normal timing 
Compressed timing 
If bit 0=1 

Fixed priority 
Rotating priority 



0 Late write selection 

1 Extended write selection 
X If bit 3=1 



Mode Register 

7 6 5 4 3 



2 1 0 



DREQ sense active high 
DREQ sense active low 

DACK sense active low 
DACK sense active high 



- Bit Number 



' j ( 00 Channel 0 select 

J I 01 Channel 1 select 

| 10 Channel 2 select 
I 11 



Request Register 

7 6 5 4 3 2 1 0 



Channel 3 select 

[00 Verify transfer 

| 01 Write transfer 

. 10 Read transfer 

11 Illegal 

I XX If bits 6 and 7 = 11 

0 Autoinitialization disable 

1 Autoinitialization enable 

0 Address increment select 

1 Address decrement select 

00 Demand mode select 

01 Single mode select 
10 Block mode select 

, 11 Cascade mode select 



-Bit Number 




| .* / 00 Select channel 0 
~ ' Select channel 1 
| 10 Select channel 2 
Select channel 3 

0 Reset request bit 

1 Set request bit 

rately under software cont rol or is cleared upon genera- 
tion of a TC or external EOP. The entire register is 
cleared by a Reset. To set or reset a bit, the software 
loads the proper form of the data word. See Figure 5 for 
register address coding. In order to make a software re- 
quest, the channel must be in Block Mode, 



2-93 



AFN-00789D 



inteT 



8237A/8237A-4/823tA-5 



Mask Register — Each channel has associated with it a 
mask bit which can be set to disable the incoming 
DREQ. Each mask bit is set when its associated channel 
produces an ,EOP if the channel is not programmed for 
Autoinitialize. Each bit of the 4-bit Mask register may 
also be set or cleared separately under software control. 
The entire register is also set by a Reset. This disables 
all DMA requests until a clear Mask register instruction 
allows them to occur. The instruction to separately set 
or clear the mask bits is similar in form to that used with 
the Request register. See Figure 5 for instruction ad- 
dressing. 



7 0 5 4 3 2 10' 



7 6 5 4 3 2 1 0* 



Don't Care 



— Bit Number 

00 Select channel 0 mask bit 

01 Select channel 1 mask bit 

10 Select channel 2 mask bit 

1 1 Select channel 3 mask bit 

0 Clear mask bit 

1 Set mask bit 



All four bits of the Mask register may also be written 
with a single command. 




7 6 5 4 3 2 

n 



-Bit Number 



Don't Care 



— i? 
— I 



Clear channel 0 mask bit 
Set channel 0 mask bit 



Clear channel 1 mask bit 
Set channel 1 mask bit 



0 Clear channel 2 mask bit 

1 Set channel 2 mask bit 



Clear channel 3 mask bit 
Set channel 3 mask bit 



Register 


Operation 


Signals 


CS 


IOR 


I0W 


A3 


A2 


A1 


AO 


Command 


Write 


0 




0 


1 


0 


0 


0 


Mode 


Write 


0 




0 


1 


0 


1 


1 


Request 


Write 


0 




0 


1 


0 


0 


1 


Mask 


Set/Reset 


0 




0 


1 


0 


1 


0 


Mask 


Write 


0 




0 


1 


1 


1 


1 


Temporary 


Read 


b 


0 


1 


1 


1 


0 


1 


Status 


Read 


0 


0 


1 


' 1 


0 


0 


0 



Figure 5. Definition of Register Codes 

Status Register — The Status register is available to be 
read out of the 8237A by the microprocessor. It contains 
information about the status of the devices at this point. 
This information includes which channels have reached 
a terminal count and which channels have pending DMA 
requests. Bits 0-3 are set every time a TC is reached by 
that channel or an external EOP is applied. These bits 
are cleared upon Reset and on each Status Read. Bits 
4-7 are set whenever their corresponding channel is 
requesting service. 



Bit Number 

- 1- Channel 0 has reached TC 

• 1 Channel 1 has reached TC 

- 1 Channel 2 has reached TC 

- 1 Channel 3 has reached TC 



Channel 0 request 
Channel 1 request 
Channel 2 request 
Channel 3 request 



Temporary Register — The Temporary register is used 
to hold data during memory-to-memory transfers. Fol- 
lowing the completion of the transfers, the last word 
moved can be read by the microprocessor in the Pro- 
gram Condition. The Temporary register always con- 
tains the last byte transferred in the previous memory- 
to-memory operation, unless cleared by a Reset. 

Software Commands-These are additional special software 
commands which can be executed in the Program Condition. 
They do not depend on any specific bit pattern on the data 
bus. The three software commands are: 

Clear First/Last Flip-Flop: This command is executed 
prior to writing or reading new address or word count 
information to the 8237A. This initializes the flip-flop 
to a known state so that subsequent accesses to reg- 
ister contents by the microprocessor will address 
upper and lower bytes, in the correct sequence. 

Master Clear: This software instruction has the same 
effect as the hardware Reset. The Command, Status, 
Request, Temporary, and Internal First/Last Flip-Flop 
registers are cleared and the Mask register is set. The 
8237A will enter the Idle cycle. 

Clear Mask Register: This command clears the mask 
bits of all four channels, enabling them to accept 
DMA requests. 

Figure 6 lists the address codes for the software com- 
mands: 



Signals 


Operation 


A3 


A2 


A1 


AO 


IOR 


iow 




O 


0 


0 


0 




Read Status Register 




0 


0 


0 






Write Command Register 




0 


0 








Illegal 




0 


0 








Write Request Register 




0 










Illegal 




0 


1 








Write Single Mask Register Bit 




0 


1 








Illegal 




0 


1 








Write Mode Register • 






0 








Illegal 






0 








Clear Byte Pointer Flip /Flop 






0'. 








Read Temporary Register 






0 








Master Clear 






1 








Illegal 






1 








Clear Mask Register 






1 








Illegal 






1 








Write A'l Mask Register Bits 



Figure 6. Softwa 



e Command Codes 



2-94 



AFN-00789D 




8237A/8237A-4/8237A-5 















Signals 












Channel 
























Register 


Operation 


CS 






A3 


A2 


A1 


AO 


Internal Fllp-Flop 


Data Bus DB0-DB7 




IOR 


IOW 




0 


Base and Current Address 


Write 


0 


1 


0 


0 


0 


0 


0 


0 


A0-A7 








0 


1 


0 


0 


0 


0 


0 


t 


A8-A15 




Current Address 


Read 


0 


0 


1 


0 


0 


0 


0 


0 


A0-A7 








0 


0 


1 


0 


0 


0 


0 


1 


A8-A15 




Base and Current Word Count 


Write 


0 


1 


0 


0 


0 


0 


1 


0 


W0-W7 








0 


1 


0 


0 


0 


0 


1 


1 


W8-W15 




Current Word Count 


Read 


0 


0 


1 


0 


0 


0 


1 


0 


W)0-W7 








0 


0 


1 


0 


0 


0 


1 


1 


W8-W15 


1 


Base and Current Address 


Write 


0 


1 


0 


0 


0 


1 


0 


0 


A0-A7 








0 


1 


0 


0 


0 


1 


0 


1 


A8-A15 




Current Address 


Read 


0 


0 


1 


0 


0 


1 


0 


0 


A0-A7 








0 


0 


1 


0 


0 


1 


0 


1 


A8-A15 




Base and Current Word Count 


Write 


0 


1 


0 


0 


0 


1 


1 


0 


W0-W7 








0 


1 


0 


-o 


0 


1 


1 


1 


W8-W15 




Current Word Count 


Read 


0 


0 


1 


0 


0 


1 


1 


0 


W0-W7 








0 


0 


1 


0 


0 


1 


1 


1 


W8-W15 


2 


Base and Current Address 


Write 


0 


1 


0 


0 


1 


0 


0 


0 


A0-A7 








0 


1 


0 


0 


1 


0 


0 


1 


A8-A15 




Current Address 


Read 


0 


0 


1 


0 


1 


0 


0 


0 


A0-A7 








0 


0 


1 


0 


1 


0 


0 


1 


A8-A15 




Base and Current Word Count 


Write 


0 


1 


0 


0 


1 


0 


1 


0 


W0-W7 








0 


1 


0 


0 


1 


0 


1 


1 


W8-W15 




Current Word Count 


Read 


0 


0 


1 


0 


1 


0 


1 


0 


W)0-W7 








0 


0 


1 


0 




0 


1 


1 


W8-W15 


3 


Base and Current Address 


Write 


0 


1 


0 


0 






0 


0 


A0-A7 








0 


1 


0 


0 






0 


1 


A8-A15 




Current Address 


Read 


0 


0 


1 


0 > 






0 


0 


A0-A7 








0 


0 


1 


0 






0 


1 


A8-A15 




Base and Current Word Count 


Write 


0 


1 


0 


0 






1 


0 


W0-W7 








0 


1 


0 


0 






1 


1 


W8-W15 




Current Word Count 


Read 


0 


0 


1 


0 






1 


0 


W)0-W7 








0 


0 


1 


0 






1 


1 


W8-W15 



Figure 7. Word Count and Address Register Command Codes 



PROGRAMMING 

The 8237A will accept programming from the host proc- 
essor any time that HLDA is inactive; this is true even if 
HRQ is active. The responsibility of the host is to assure 
that programming and HLDA are mutually exclusive. 
Note that a problem can occur if a DMA request occurs, 
on an unmasked channel while the 8237A is being pro- 
grammed. For instance, the CPU may be starting to 
reprogram the two byte Address register of channel 1 
when channel 1 receives a DMA request. If the 8237A is 
enabled (bit 2 in the command register is 0) and channel 
1 is unmasked, a DMA service will occur after only one 
byte of the Address register has been reprogrammed. 
This can be avoided by disabling the controller (setting 
bit 2 in the command register) or masking the channel 
before programming any other registers. Once the pro- 
gramming is complete, the controller can be enabled/un- 
masked. 

After power-up it is suggested that all internal locations, 
especially the Mode registers, be loaded with some 
valid value. This should be done even if some channels 
are unused. 



2-95 



AFN-00789D 



inter 



8237A/8237A-4/8237A-5 



APPLICATION INFORMATION 

Figure 8 shows a convenient method for configuring a 
DMA system with the 8237A controller and an 8080A/ 
808.5AH microprocessor system. The multimode DMA 
controller issues a HRQ to the processor whenever 
there is at least one valid DMA request from a peripheral 
device. When the processor replies with a HLDA signal, 
the 8237A takes control of the address bus, the data bus 
and the control bus. The address for the first transfer 



operation comes out in two bytes — the least signifi- 
cant 8 bits on the eight address outputs and the most 
significant 8 bits on the data bus. The contents of the 
data bus are then latched into the 8282 8-bit latch to 
complete the full 16 bits of the address bus. The 8282 is 
a high speed, 8-bit, three-state latch in a 20-pin package. 
After the initial transfer takes place, the latch is updated 
only after a carry or borrow is generated in the least sig- 
nificant address byte. Four DMA channels are provided 
when one 8237A is used. 



ADDRESS BUS AO- A1 5 



HLDA 
HOLD 



CLOCK — 
RESET — 
MEMR 0- 
MEMW 0- 
IOR O- 
iow 0- 



-tx- 



CUE 



HLDA 
HRQ 



AEN A0-A3 A4-A7 CS ADSTB 

8237A DBO- 

« « DB7 

8 I I 1 i I 1 I 



0 0 0 0 



CONTROL 
BUS 



SYSTEM DATA BUS 



Figure 8. 8237A System Interface 

2-96 



AFN-00789D 



8237A/8237A-4/8237A-5 



ABSOLUTE MAXIMUM RATINGS* 



Ambient Temperature under Bias 0°C to 70 °C 

Storage Temperature -65°Cto + 150°C 

Voltage on any Pin with 

Respect to Ground - 0.5 to 7V 

Power Dissipation 1.5 Watt 



'NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (T A = 0°C to 70°C, V cc = 5.0V ±5%, GND = 0V) 



Symbol 


Parameter 


Min. 


Typ.O) 


Max. 


Unit 


Test Conditions 


VOH 


Output High Voltage 


2.4 






V 


Iqh = -200 juA 


3.3 






V 


l OH = -100^A(HRQ Only) 


Vol 


Output LOW Voltage 






45 


V 


Iol = 2.0mA (data Bus)EDF 

Iql = 3.2mA (other outputs) (Note 8) 

l 0L = 2.5mA (ADSTB) (Note 8) 


V|H 


Input HIGH Voltage 


2.2 




V CC + 0.5 


V 




V|L 


Input LOW Voltage 


-0.5 




0.8 


V 




«LI 


Input Load Current 






±10 


1* 


0V < V, N < V cc 


Ilo 


Output Leakage Current 






±10 


^A 


6.45V <V 0U T^ V cc 


•cc 


V cc Supply Current 




110 


130 


mA 


T A =+25°C 




130 


150 


mA 


T A = 0°C 


Co 


Output Capacitance 




4 


8 


PF 


fc=1.0 MHz, Inputs = 0V 


Ci 


Input Capacitance 




8 


15 


PF 


C10 


I/O Capacitance 




10 


18 


PF 



NOTES: 

1 Typical values are for = 25°C, nominal supply voltage and nominal processing parameters 

2. Input liming parameters assume transition times of 20 ns or less. Waveform measurement points for both input and output signals are 2 0V for HIGH and 0 8V 
for LOW, unless otherwise noted. 

3. Output loading is 1 TTL gate plus 1 50pF capacitance, unless otherwise noted. 

4. The net IOW or MEMW Pulse width for normal write will be TCY-100 ns and for extended write will be 2TCY-100 ns. The net IOR or MEMR pulse width for 
normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns. * 

5. TDQ is specified for two different output HIGH levels TDQ1 is measured at 2.0V. TDQ2 is measured at 3.3V. The value for TDQ2 assumes an external 3.3kQ 
pull-up resistor connected form HRQ to Vcc- 

6. DREQ should be held active until DACK is returned. 

7 DREQ and DACK signals may be active high or active low. Timing diagrams assume the active high mode. 

8. A revision of the 8237A is planned for shipment in April 1 984, which will improve the following characteristics. 

1. V| H from 2.2V to 2.0V 

2. Vol from 0 45V to °- 4v on alt outputs. Test condition Iql = 3 2 mA 
Please contact your local sales office at that time for more information. 

9. Successive read and/or write operations by the external processor to program or examine the controller must be timed to allow at least 600 ns for the 8237A, 
at least 500 ns for the 8237 A-4 and at least 400 ns for the 8237A-5, as recovery time between active read or write pulses 

1 0. EOP is an open collector output. This parameter assumes the presence of a 2.2K pullup to Vcc- 

11. Pin 5 is an input that should always be at a logic high level An internal pull-up resistor will establish a logic high when the pin is left floating. It is recom- 
mended however, that pin 5 be tied to Vcc- 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



INPUT/OUTPUT 



^> TEST POINTS <^ 



A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1 " AND 0 45V FOR 
A ^.° GI £, "2 " TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC "1 " 
AND 0 8V FOR A LOGIC "0 " (Note 2) 



2-97 



AFN-00789D 



8237A/8237A-4/8237A-5 



A.C. CHARACTERISTICS— DMA (MASTER) MODE (T A =o°C to 7<rc, 

Vcc= +5V±5%, GND = 0V) 







8237A 


8237A-4 


8237A-5 


Unit 


Symbol 


Parameter 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


TAEL 


AEN HIGH from CLK LOW (S1) Delay Time 




300 




225 




200 


ns 


TAET 


AEN LOW from CLK HIGH (SI) Delay Time 




200 




150 




130 


ns 


TAFAB 


ADR Active to Float Delay from CLK HIGH 




150 




120 




90 


ns 


TAFC 


READ or WRITE Float from CLK HIGH 




150 




120 




120 


ns 


TAFDB 


DB Active to Float Delay from CLK HIGH 




250 




190 




170 


ns 


TAHR 


ADR from READ HIGH Hold Time 


TCY-100 




TCY-100 




TCY-100 




ns 


TAHS 


DB from ADSTB LOW Hold Time 


50 




40 




30 




ns 


TAHW 


ADR from WRITE HIGH Hold Time 


TCY-50 




TCY-50 




TCY-50 




ns 




DACK Valid from CLK LOW Delay Time (Note 7) 




250 




220 




170 


ns 


TAK 


EOP HIGH from CLK HIGH Delay Time (Note 10) 




250 




190 




170 


ns 




FOP I OW from CA K HlfiH Dplav Timp 




250 




190 




. 170 


ns 


TASM 


ADR Stable from CLK HIGH 




250 




190 




170 


ns 


TA§S 


DB to ADSTB LOW Setup Time 


100 • 




100 




100 




ns 


TCH 


Clock High Time (Transitions^ 10 ns) 


120 




100 




80 




ns 


TCL 


Clock LOW Time (Transitions^ 10 ns) 


150 




110 




68 




ns 


TCY 


CLK Cycle Time 


320 




250 




( 200 




ns 


TDCL 


CLK HIGH to READ or WRITE LOW Delay (Note 4) 




270 




200 




190 


ns 


TDCTR 


READ HIGH from CLK HIGH (S4) Delay Time 




270 




210 




190 


ns 


TDCTW 


WRITE HIGH from CLK HIGH fS41 DpIavTimp 
(Note 4) 




200 




150 




130 


ns 


TDQ1 


MDOValiri f rrvm PI if Mir^U riolau Timo (tdr\ta t\\ 

nnvj vaiiu irom vyi_r\ nivan ueiay i ime ^fNrOie 0/ 




160 




120 




120 


ns 


TDQ2 




250 




190 




120 


ns 


TEPS 


EOP LOW from CLK LOW Setup Time 


60 




45 




40 




ns 


TEPW 


EOP Pulse Width 


300 




225 




220 




ns 


TFAAB 


ADR Float to Active Delay from CLK HIGH 




250 




190 




170 


ns 


TFAC 


READ or WRITE Active from CLK HIGH 




200 




150 




150 


ns 


TFADB 


DB Float to Active Delay from CLK HIGH 




309 




225 




200 


ns 


THS 


HLDA Valid to CLK HIGH Setup Time 


100 




75 




75 




ns 


TIDH 


Input Data from MEMR HIGH Hold Time 


0 




0 




0 




ns 


TIDS 


Input Data to MEMR HIGH Setup Time 


250 




190 




170 




ns 


TODH 


Output Data from MEMW HIGH Hold Time 


20 




20 




10 




ns 


TODV 


Output Data Valid to MEMW HIGH 


200 




125 




125 




ns 


TQS 


DREQ to CLK LOW (SI, S4) Setup Time (Note 7) 


0 




0 




0 




ns 


TRH 


CLK to READY LOW Hold Time 


20 




20 




J20 




ns 


TRS 


READY to CLK LOW Setup Time 


100 




60 




60 




ns 


TSTL 


ADSTB HIGH from CLK HIGH Delay Time 




200 




150 




• 130 


ns 


TSTT 


ADSTB LOW from CLK HIGH Delay Time 




140 




110 




| 90 


ns 



2-98 



AFN-00789D 



inter 



8237A/8237A-4/8237A-5 



A.C. CHARACTERISTICS— PERIPHERAL (SLAVE) MODE Oa = o°e to 70°c, v cc 

GND = OV)' 



5.0V ±5%, 



Symbol 


Parameter 


8237A 


8237A-4 


8237A-5 


Unit 


Mln. 


Max. 


Min. 


Max. 


Min. 


Max. 


TAR 


ADR Valid or CS LOW to READ LOW 


50 




50 




50 




ns 


TAW 


ADR Valid to WRITE HIGH Setup Time 


200 




150 




130 




ns 


TCW 


CS LOW to WRITE HIGH Setup Time 


200 




150 




130 




ns 


TDW 


Data Valid to WRITE HIGH Setup Time 


200 




150 




130 




ns 


TRA 


ADR or CS Hold from WRE> HIGH * 


0 




0 




0 




ns 


TRDE 


Data Access from READ LOW (Note 3) 




200 




200 




140 


ns 


TRDF 


DB Float Delay from READ HIGH 


20 


100 


20 


100 


0 


70 


ns 


TRSTD 


Power Supply HIGH to RESET LOW Setup Time 


500 




500 




500 




ns 


TRSTS 


iRESETto First lOWR 


2TCY 




2TCY 




2TCY 




ns 


TRSTW 


RESET Pulse Width 


300 




300 




300 




ns 


TRW 


READ Width 


300 




250 




200 




ns 


TWA 


ADR from WRITE HIGH Hold Time 


20 




20 




20 




ns 


TWC 


CS HIGH from WRITE HIGH Hold Time 


20 




20 




20 




ns 


TWD 


Data from WRITE HIGH Hold Time 


30 




30 




30 




ns 


TWWS 


Write Width 


200 




200 




160 




ns 



WAVEFORMS 



SLAVE MODE WRITE TIMING 



i-, 



TWC 
(NOTE 9) 



5C 



Figure 9. Slave Mode Write 



SLAVE MODE READ TIMING 



■zx 



ADDRESS MUST BE VALID 



Figure 10. Slave Mode Read 



x 



-TRA 
(NOTE 9) 



DATA OUT VALID 



2-99 



AFN-00789D 



8237A/8237A-4/8237A-5 



WAVEFORMS (Continued) 



DMA TRANSFER TIMING 



I 



ADDRESS VALID 



\ 

(FOR EXTENDED WRITE)' 



TOS|- 

(NOTE 6) 



X 



TASM 
-TAHW 



\\\\\\\\vv\v -// /////////// 



ADDRESS VALID 



Figure 11. DMA Transfer 



2-100 



AFN-00789D 



8237A/8237A-4/8237A-5 



WAVEFORMS (Continued) 



MEMORY-TO-MEMORY TRANSFER TIMING 



ADDRESS VALID 



TIDH- 

b^f 



TEPS— » 
TEPW 



ADDRESS VALID 



< 



TDCTW 
— TDCL-*- 



> 



J////////// 



Figure 12. Memory-to-Memory Transfer 



READY TIMING 



WRITE 




EXTENDED 

WRITE TRH 
TRS- 



f 



r 



Figure 13. Ready 



2-101 



AFN-00789D 



inteT 



8237A/8237A-4/8237A-5 



WAVEFORMS (Continued) 



COMPRESSED TRANSFER TIMING 



INT 
EOP 



EXT 
EOP 



! - I 



X 



\ 




TDCTR |tOCL| 



I 



Figure 14. Compressed Transfer 



RESET TIMING 

v C c 



A 



iORORlQW 



Figure 15. Reset 



2^102 



AFN-00789D 



8257/8257-5 
PROGRAMMABLE DMA CONTROLLER 

■ MCS-85® Compatible 8257-5 ■ Single TTL Clock 

■ 4-Channel DMA Controller 

■ Priority DMA Request Logic 

■ Channel Inhibit Logic 

■ Terminal Count and Modulo 128 
Outputs 

The Inter 8257 is a 4-channel direct memory access (DMA) controller. It is specifically designed to simplify the 
transfer of data at high speeds for the Intel® microcomputer systems. Its primary function is to generate, upon a 
peripheral request, a sequential memory address which will allow the peripheral to read or write data directly to or 
from memory. Acquisition of the system bus in accomplished via the CPU's hold function. The 8257 has priority logic 
that resolves the peripherals requests and issues a composite hold request to the CPU. It maintains the DMA cycle 
count for each channel and outputs a control signal to notify the peripheral that the programmed number of DMA 
cycles is complete. Other output control signals simplify sectored data transfers. The 8257 represents a significant 
savings in component count for DMA-based microcomputer systems and greatly simplifies the transfer of data at 
high speed between peripherals and memories. 



■ Single + 5V Supply 

■ Auto Load Mode 

■ Available in EXPRESS 

- Standard Temperature Range 



"CO 



DATA 
BUS 
BUFFER 



READ/ 
WRITE 
LOGIC 



CONTROL 
LOGIC 
AND 
MODE 



c 



c 



c 



0 



BIT 
AOOR 
CNTR 



l/ORC 1 

l/OWC 2 

MEM RC 3 

MEM wC 4 

MARKC 5 

READYC 6 

HLDAC 7 

ADSTBC 8 



AENC 


9 


HRQC 


10 


esc 




clkC 


12 


resetC 


13 


DACK 2 C 


14 


PACK 3C 


,15 


DRQ3C 


16 


DRQ2C 


17 


DRQ C 


18 


DRQOC 


19 


GNOC 


20 



I □ A 7 
9 D A 6 

7 D A 4 

6 3tc 

5 D A 3 

4 D A 2 

3 D A i 
2 D A o 

ii H v cc 

0 Dd 0 
9 Do, 

8 3o 2 

7 3d 3 ' 

6 DD 4 

5 Udack 0 

4 30ACK 1 

2 3o 6 

1 Do 7 



Figure 1. Block Diagram Figure 2. Pin Configuration 



2-103 



8257/8257-5 



FUNCTIONAL DESCRIPTION 
General 

The 8257 is a programmable, Direct Memory Access 
(DMA) device which, when coupled with a single Intel® 
8212 I/O port device, provides a complete four-channel 
DMA controller for use in Intel® microcomputer systems. 
After being initialized by software, the 8257 can transfer a 
block of data, containing up to 16,384 bytes, between 
memory and a peripheral device directly, without further 
intervention required of the CPU. Upon receiving a DMA 
transfer request from an enabled peripheral, the 8257: 

1. Acquires control of the system bus. 

2. Acknowledges that requesting peripheral which is 
connected to the highest priority channel. 

3. Outputs the least significant eight bits of the memory 
address onto system address lines A0-A7, outputs 
the most significant eight bits of the memory address 
to the 8212 I/O port via the data bus (the 8212 
places these address bits on lines A 8 -A 15 ), and 

4. Generates the appropriate memory and I/O read/ 
write control signals that cause the peripheral to 
receive or deposit a data byte directly from or to the 
addressed location in memory. 

The 8257 will retain control of the system bus and repeat 
the transfer sequence, as long as a peripheral maintains its 
DMA request. Thus, the 8257 can transfer a block of data 
to/from a high speed peripheral (e.g., a sector of data on a 
floppy disk) in a single "burst". When the specified 
number of data bytes have been transferred, the 8257 
activates its Terminal Count (TC) output, informing the 
CPU that the operation is complete. 

The 8257 offers three different modes of operation: 
(1) DMA read, which causes data to be transferred from 
memory to a peripheral; (2) DMA write,, which causes 
data to be transferred from a peripheral to memory; 
and (3) DMA verify, which does not actually involve the 
transfer of data. When an 8257 channel is in the DMA verify 
mode, it will respond the same as described for transfer 
operations, except that no memory or I/O read/write 
control signals will be generated, thus preventing the 
transfer of data. The 8257, however, will gain control of the 
system bus and will acknowledge the peripheral's DMA 
request for each DMA cycle. The peripheral can use these 
acknowledge signals to enable an internal access of each 
byte of a data block in order to execute some verification 
procedure, such as the accumulation of a CRC (Cyclic 
Redundancy Code) checkword. For example, a block of 
DMA verify cycles might follow a block of DMA read cycles 
(memory to peripheral) to allow the peripheral to verify its 
newly acquired data. 



Block Diagram Description 
1. DMA Channels 

The 8257 provides four separate DMA channels (labeled 
CH-0 to CH-3). Each channel includes two sixteen-bit 
registers: (1) a DMA address register, and (2) a termi- 
nal count register. Both registers must be initialized 
before a channel is enabled. The DMA address register is 
loaded with the address of the first memory location to be 
accessed. The value loaded into the low*order 14-bits of 
the terminal count register specifies the number of DMA 
cycles minus one before the Terminal Count (TC) output 
is activated. For instance, a terminal count of 0 would 
cause the TC output to be active in the first DMA cycle for 
that channel. In general, if N = the number of desired DMA 
cycles, load the value N-1 into the low-order 14-bits of the 
terminal count register. The most significant two bits of the 
terminal count register specify the type of DMA operation 
for that channel. 



Figure 3. 8257 Block Diagram Showing DMA 
Channels 



-co 



DATA 
BUS 
BUFFER 



READ/ 
WRITE 
LOGIC 



CO 



CONTROL 
LOGIC 
ANO 
MODE 




c 







' — •> 







— van 



T 



2-104 



inte 1 



8257/82575 



These two bits are not modified during a DMA cycle, but 
can be changed between DMA blocks. 

Each channel accepts a DMA Request (DRQn) input and 
provides a DMA Acknowledge (DACKn) output. 

(DRQ O-DRQ 3) 

DMA Request: These are individual asynchronous chan- 
nel request inputs used by the peripherals to obtain a DMA 
cycle. If not in the rotating priority mode then DRQ 0 has 
the highest priority and DRQ 3 has the lowest. A request 
can be generated by raising the request line and holding it 
high until DMA acknowledge. For multiple DMA cycles 
(Burst Mode) the request line is held high until the DMA 
acknowledge of the last cycle arrives. 



(DACK 0 - DACK 3) 

DMA Acknowledge: An active low level on the acknowl- 
edge output informs the peripheral connected to that 
chann el that it has been selected for a DMA cycle. The 
DACK output acts as a "chip select" for the peripheral 
device requesting service. This line goes active (low) 
and inactive (high) once for each byte transferred even If 
a burst of data is being transferred. 

2. Data Bus Buffer 

This three-state, bi-directional, eight bit buffer interfaces 
the 8257 to the system data bus. 

<D 0 -D 7 ) 

Data Bus Lines: These are bi-directional three-state lines. 
When the 8257 is being programmed by the CPU, eight- 
bits of data for a DMA address register, a terminal count 
register or the Mode Set register are received on the data 
bus. When the CPU reads a DMA address register, a 
terminal count register or the Status register, the data is 
sent to the CPU over the data bus. During DMA cycles 
(when the 8257 is the bus master), the 8257 will output the 
most significant eight-bits of the memory address (from 
one of the DMA address registers) to the 821 2 latch via the 
data bus. These address bits will be transferred at the 
beginning of the DMA cycle; the bus will then be released 
to handle the memory data transfer during the balance of 
the DMA cycle. 



BIT 15 


BIT 14 


TYPE OF DMA OPERATION 


0 


0 


Verify DMA Cycle 


0 


1 


Write DMA Cycle 


1 


0 


Read DMA Cycle 


1 


1 


(Illegal) 



Figure 4. 8257 Block Diagram Showing Data Bus 
Buffer 




2-105 



AFN-01840D 



8257/8257-5 



3. Read/Write Logic 

When the CPU is programming or reading one of the 
8257's registers (i.e., when the 8257 is a "slave" device on 
the sy stem bus), the Read/Write Logic accepts the I/O 
Read (T70F?) or I/O Write (l/OW) signal, decodes the least 
significant four address bits, (A 0 -A 3 ), and either writes 
th e cont ents of the data bus into the addressed register 
(if l/OW is true) or places the conte nts of the addressed 
register onto the data bus (if 1/bR is true). 

During DMA cycles (i.e., when the 8257 is the bus 
"master"), the Read/Write Logic generates the I/O read 
and memory write (DMA write cycle) or I/O Write and 
memory read (DMA read cycle) signals which control the 
data link with the peripheral that has been granted the 
DMA cycle. 

Note that during DMA transfers Non-DMA I/O devices 
should be de-selected (disabled) using "AEN" signal to 
inhibit I/O device decoding of the memory address as an 
erroneous device address. 

(T/OR) 

J/O Read; An active-low, bi-directional three-state line. In 
the "slave" mode, it is an input which allows the 8-bit 
status register or the upper/lower byte of a 16-bit DMA 
address register or term inal count register to be read. In 
the "master" mode, l/OR is a control output which is used 
to access data from a peripheral during the DMA write 
cycle. 



(l/OW) 

I/O Write: An active-low, bi-directional three-state line. In 
the "slave" mode, it is an input which allows the contents 
of the data bus to be loaded into the 8-bit mode set register 
or the upper/lower byte of a 16-bit DMA address register 
or terminal count register In the "master" mode, l/OW is a 
control output which allows data to be output to a 
peripheral during a DMA read cycle 

(CLK) 

Clock Input: Generally from an Intel® 8224 Clock Gen- 
erator device. (<t>2 TTL) or Intel® 8085A CLK output 

(RESET) 

Reset: An asynchronous input (generally from an 8224 
or 8085 device) which disables all DMA channels by 
clearing the mode register and 3-states all control lines. 



(A0-A3) 

Address Lines: These least significant four address lines 
are bi-directional. In the "slave" mode they are inputs 
which select one of the registers to be read or 
programmed. In the "master" mode, they are outputs 
which constitute the least significant four bits of the 1 6-bit 
memory address generated by the 8257. 

(CS) 

Chip Select: An active-low input which enables the I/O 
Read or I/O Write input when the 8257 is being read or 
programmed in the "slave" mode. In the "master" mode, 
CS is automatically disabled to prevent the chip from 
selecting itself while performing the DMA function. 

4. Control Logic 

This block controls the sequence of operations during ail 
DMA cycles by generating the appropriate control signals 
and the 16-bit address that specifies the memory location 
to be accessed 



Figure 5. 8257 Block Diagram Showing 
Read/Write Logic Function 



CLK - 
RES£T — 



CO 




CONTROL 
LOGIC 
AND 
MODE 



C3 



c 



c 



c 



CNTR 



2-106 



AFN-01840D 



8257/8257-5 



(A4-A 7 ) 

Address Lines: These four address lines are three-state 
outputs which constitute bits 4 through 7 of the 16-bit 
memory address generated by the 8257 during all DMA 
cycles. 

(READY) 

Ready: This asynchronous input is used to elongate the 
memory read and write cycles in the 8257 with wait 
states if the selected memory requires longer cycles. 
READY must conform to specified setup and hold 
times. 

(HRQ) 

Hold Request: This output requests control of the 
system bus. In systems with only one 8257, HRQ will 
normally be applied to the HOLD input on the CPU. HRQ 
must conform to specified setup and hold times. 

(HLDA) 

Hold Acknowledge: This input from the CPU indicates 
that the 8257 has acquired control of the system bus. 

(MEMR) 

Memory Read: This active-low three-state output is used 
to read data from the addressed memory location during 
DMA Read cycles. 

(MEMW) 

Memory Write: This active-low three-state output is used 
to write data into the addressed memory location during 
DMA Write cycles, 

(ADSTB) 

Address Strobe. This output strobes the most significant 
byte of the memory address into the 8212 device from the 
data bus. 

(AEN) 

Address Enable. This output is used to disable (float) the 
System Data Bus and the System Control Bus. It may also 
be used to disable (float) the System Address Bus by use 
of an enable on the Address Bus drivers in systems to 
inhibit non-DMA devices from responding during DMA 
cycles. It may be further used to isolate the 8257 data bus 
from the System Data Bus to facilitate the transfer of the 8 
most significant DMA address bits over the 8257 data I/O 
pins without subjecting the System Data Bus to any 
timing constraints for the transfer. When the 8257 is used 
in an I/O device structure (as opposed to memory 
mapped), this AEN output should be used to disable the 
selection of an I/O device when the DMA address is on the 
address bus. The I/O device selection should be 
determine^ by the DMA acknowledge outputs for the 4 
channels. 



(TC) 

Terminal Count: This output notifies the currently 
selected peripheral that the present DMA cycle should be 
the last cycle for this data block. If the TC STOP bit in the 
Mode Set register is set, the selected channel will be 
automatically disabled at the end of that DMA cycle. TC is 
activated when the 14-bit value in the selected channel's 
terminal count register equals zero. Recall that the low- 
order 14-bits of the terminal count register should be 
loaded with the values (n-1 ), where n = the desired number 
of the DMA cycles. 

(MARK) 

Modulo 128 Mark: This output notifies the selected 
peripheral that the current DMA cycle is the 128th cycle 
since the previous MARK output. MARK always occurs at 
128 (and all multiples of 128) cycles from the end of ttie 
data block Only if the total number of DMA cycles (n) is 
evenly divisable by 128 (and the terminal count register 
was loaded with n-1), will MARK occur at 128 (and each 
succeeding multiple of 128) cycles from the beginning of 
the data block 



Figure 6. 8257 Block Diagram Showing Control 
Logic and Mode Set Register 




2-107 



AFN-01840D 



8257/8257-5 



5. Mode Set Register 

When set, the various bits in the Mode Set register enable 
each of the four DMA channels, and allow four different 
options for the 8257: 



Enables AUTOLOAD 

Enables TC STOP 1 

Enables EXTENOEO WRITE 

Enables ROTATING PRIORITY- 



rr 



X 



Enables DMA Channel 0 
Enables DMA Channel 1 
Enables DMA Channel 2 
Enables DMA Channel 3 



The Mode Set register is normally programmed by the 
CPU after the DMA address register(s) and terminal 
Count register(s) are initialized. The Mode Set Register is 
cleared by the RESET input, thus disabling all options, 
inhibiting all channels, and preventing bus conflicts on 
power-up. A channel should not be left enabled unless its 
DMA address and terminal count registers contain valid 
values; otherwise, an inadvertent DMA request (DRQn) 
from a peripheral could initiate a DMA cycle that would 
destroy memory data. 

The various options which can be enabled by bits in the 
Mode Set register are explained below. 

Rotating Priority Bit 4 

In the Rotating Priority Mode, the priority of the channels 
has a circular sequence After each DMA cycle, the 
priority of each channel changes. The channel which had 
just been serviced will have the lowest priority 




If the ROTATING PRIORITY bit is not set (set to a zero), 
each DMA channel has a fixed priority In the fixed priority 
mode, Channel 0 has the highest priority and Channel 3 
has the lowest priority If the ROTATING PRIORITY bit is 
set to a one, the priority of each channel changes after 
each DMA cycle (not each DMA request). Each channel 
moves up to the next highest priority assignment, while 
the channel which has just been serviced moves to the 
lowest priority assignment 





CHANNEL— ► 


CH-0 


CH-1 


CH-2 


CH-3 




JUST SERVICED 










Priority — ► 


Highest 


CH-t 


CH-2 


CH-3 


CH-0 


Assignments 




CH-2 


CH-3 


CH-0 


CH-1 




* 


CH-3 


CH-0 


CH-1 


CH-2 




Lowest 


CH-0 


CH-1 


CH-2 


CH-3 



Note that rotating priority will prevent any one channel 
from monopolizing the DMA mode; consecutive DMA 
cycles will service different channels if more than one 
channel is enabled and requesting service. There is no 
overhead penalty associated with this mode of opera- 
tion. All DMA operations began with Channel 0 initially 
assigned to the highest priority for the first DMA cycle. 

Extended Write Bit 5 

If the E XTEN DED WRITE bit is set, the duration of both the 
MEMW and l/OW signals is extended by activating them 
earlier in the DMA cycle. Data transfers within micro- 
computer systems proceed asynchronously to allow 
use of various types of memory and I/O devices with 
different access times. If a device cannot be accessed 
within a specific amount of time it returns a "not ready" 
indication to the 8257 that causes the 8257 to insert one or 
more wait states in its internal sequencing. Some devices 
are fast enough to be accessed without the use of wait 
states, but if they generate their RE ADY re sponse with the 
leading edge of the l/OW or MEMW signal (which 
generally occurs late in the transfer sequence), they 
would normally cause the 8257 to enter a wait state 
because it does not receive READY in time. For systems 
with these types of devices, the Extended Write option 
provides alternative timing for the I/O and memory write 
signals which allows the devices to return an early READY 
and prevents the unnecessary occurrence of wait states in 
the 8257, thus increasing system throughput 



TC Stop Bit 6 

If the TC STOP bit is set, a channel is disabled (i.e., its 
enable bit is reset) after the Terminal Count (TC) output 
goes true, thus automatically preventing further DMA 
operation on that channel. The enable bit for that channel 
must be re-programmed to continue or begin another 
DMA operation If the TC STOP bit, is not set, the 
occurrence of the TC output has no effect on the channel 
enable bits. In this case, it is generally the responsibility of 
the peripheral to cease DMA requests in order to terminate 
a DMA operation 

Auto Load Bit 7 

The Auto Load mode permits Channel 2 to be used for 
repeat block or block chaining operations, without 
immediate software intervention between blocks Chan- 
nel 2 registers are initialized as usual for the first data 
block, Channel 3 registers, however, are used to store the 
block re-initialization parameters (DMA starting address, 
terminal count and DMA transfer mode). After the first 
block of DMA cycles is executed by Channel 2 (i.e., after 
the TC output goes true), the parameters stored in the 
Channel 3 registers are transferred to Channel 2 during, an 
"update" cycle Note that the TC STOP feature, described 
above, has no effect on Channel 2 when the Auto Load bit 
is set 



2-108 



AFN-01840D 



8257/8257-5 



If the Auto Load bit is set, the initial parameters for 
Channel 2 are automatically duplicated in the Channel 3 
registers when Channel 2 is programmed. This permits 
repeat block operations to be set up with the programming 
of a single channel. Repeat block operations can be used 
in applications such as CRT refreshing. Channels 2 and 3 
can still be loaded with separate values if Channel 2 is 
loaded before loading Channel 3. Note that in the Auto 
Load mode, Channel 3 is still available to the user if the 
Channel 3 enable bit is set, but use of this channel will 
change the values to be auto loaded into Channel 2 at 
update time. All that is necessary to use the Auto Load 
feature for chaining operations is to reload Channel 3 
registers at the conclusion of each update cycle with the 
new parameters for the next data block transfer. 

Each time that the 8257 enters an update cycle, the update 
flag in the status register is set and parameters, in Channel 
3 are transferred to Channel 2, non-destructively for 
Channel 3. The actual re-initialization of Channel 2 occurs 
at the beginning of the next channel 2 DMA cycle after the 
TC cycle. This will be the first DMA cycle of the new data 
block for Channel 2. The update flag is cleared at the 
conclusion of this DMA cycle. For chaining operations, 
the update flag in the status register can be monitored by 
the CPU to determine when the re-initialization process 
has been completed so that the next block parameters can 
be safely loaded into Channel 3. 

6. Status Register 

The eight-bit status register indicates which channels 
have reached a terminal count condition and includes the 
update flag described previously. 



1 o I o| o I I I I I I 



UPDATE FLAG 



J 



L—TC STATUS FOR CHANNEL 0 
TC STATUS FOR CHANNEL 1 



-TC STATUS FOR CHANNEL 2 
-TC STATUS FOR CHANNEL 3 



The TC status bits are set when the Terminal Count (TC) 
output is activated for that channel. These bits remain set 
until the status register is read or the 8257 is reset. The 
UPDATE FLAG, however, is not affected by a status 
register read operation. The UPDATE FLAG can be 
cleared by resetting the 8257, by changing to the non-auto 
load mode (i.e., by resetting the AUTO LOAD bit in the 
Mode Set register) or it can be left to clear itself at the 
completion of the update cycle. The purpose of the 
UPDATE FLAG is to prevent the CPU from inadvertently 
skipping a data block by overwriting a starting address or 
terminal 'count in the Channel 3 registers before those 
parameters are properly auto-loaded into Channel 2. 



The user is cautioned against reading the TC status 
register and using this information to reenable chan- 
nels that have not completed operation. Unless the 
DMA channels are inhibited a channel could reach ter- 
minal count (TC) between the status read and the mode 
write. DMA can be inhibited by a hardware gate on the 
HRQ line or by disabling channels with a mode word 
before reading the TC status. 



(PARAMETERS 1_ (PARAMETERS) 
FOR BLOCK 1 P" FOR BLOCK 2 



JUUlTLJUUin 



[PARAMETERS I 

FOR BLOCK 3 | | 
CHANNEL 2 UPDATE CHANNEL 2 UPDATE 

OCCURS HERE \ I I OCCURS HERE w I 



^rLnn 




Figure 7. Autoload Timing 



2-109 



8257/S257-5 



OPERATIONAL SUMMARY 

Programming and Reading the 8257 Registers 

There are four pairs of "channel registers": each pair 
consisting o(a 16-bit DMA address register and a 16-bit 
terminal count register (one pair for each channel). The 
8257 also includes two "general registers": one 8-bit 
Mode Set register and one 8-bit Status register. The 
registers are, loaded or read when the CPU executes a 
write or read instruction that addresses the 8257 device 
and the appropriate register within the 8257. The 8228 
generates the appropriate read or write control signal 
(generally l/OR or l/OW while the CPU places a 16-bit 
address on the system address bus, and either outputs the 
data to be written onto the system data bus or accepts the 
data being read from the data bus. All or some of the most 
significant 12 address bits A4-A15 (depending on the 
systems memory, I/O configuration) are usually decoded 
to produce the chip select (CS) input to the 8257. An I/O 
Write input (or Memory Write in memory mapped I/O 
configurations, described below) specifies that the 
addressed register is to be programmed, while an I/O 
Read input (or Memory Read) specifies that the addressed 
register is to be read. Address bit 3 specifies whether a 
"channel register" (A3, = 0) or the Mode Set (program 
only)/Status (read only),register (A3 = 1 ) is to be accessed. 

The least signif icant three address bits, A0-A2, indicate the 
specific register to be accessed. When accessing the 
Mode Set or Status register, A0-A2 are all zero. When 
accessing a channel register bit Ao differentiates between 
the DMA address register (Ao = 0) and the terminal count 
register (Ao = 1), while bits Ai and A 2 specify one of the 



CONTROL. INPUT 


CS 


l/OW 


l/OR 


A3 


Program Half of a 
Channel Register 


0 


0 


1 


0 


Read Half of a 
Channel Register 


0 


1 


0 


0 


Program Mode Set 
Register 


0 


0 


1 


1 


Read Status Register 


0 


1 


0 


1 



four channels. Because the "channel registers" are 16- 
bits, two program instruction cycles are required to load 
or read an entire register. The 8257 contains a first/last 
(F/L) flip flop which toggles at the completion of each 
channel program or read operation. The F/L flip flop 
determines whether the upper or lower byte of the register 
is to be accessed. The F/L flip flop is reset by the RESET 
input and whenever the Mode Set register is loaded. To 
maintain proper synchronization when accessing the 
"channel registers" all channel command instruction 
operations should occur in pairs, with the lower byte of a 
register always b eing a cc essed first! Do not allow CS to 
clock while either l/OR or l/OW is active, as this will cause 
an erroneous F/L flip flop state. In systems utilizing an 
interrupt structure, interrupts should be disabled prior to 
any paired programming operations to prevent an 
interrupt from splitting them. The result of such a split 
would leave the F/L F/F in the wrong state. This problem is 
particularly obvious when other DMA channels are 
programmed by an interrupt structure. 



8257 Register Selection 



REGISTER 



ADDRESS INPUTS 



A2 At Ao 



F/L 



BI-DIRECTIONAL DATA BUS 



n 6 D 5 



D 3 D 2 D-i Do 



CH-0 DMA Address 

CH-0 Terminal Count 

CH-1 DMA Address 

CH-1 Terminal Count 

CH-2 DMA Address 

CH-2 Terminal Count 

CH-3 DMA Address 

CH-3 Terminal Count 

MODE SET (Program only) 
STATUS (Read only) 



LSB 
MSB 

LSB 
MSB 

LSB 
MSB 

LSB 
MSB 

LSB 
MSB 

LSB 
MSB 

LSB 
MSB 

LSB 
MSB 



A 7 
A15 

C 7 
Rd 



Ae 

A 14 

C 6 



A 5 

A13 
C 5 
C|3 



A4 

A12 

c 4 

C12 



AL 
0 



TCS 
0 



EW 

0 



A3 
A11 

c 3 

C11 



Same as Channel 0 



Same as Channel 0 



Same as Channel 0 



EN3 

TC3 



A 2 . 
A 10 
C 2 

C10 



EN2 
TC2 



EN1 
TC1 



ENO 
TCO 



*A 0 -Ai 5 : DMA Starting Address, Cq-Ci 3 : Terminal Count value (ISM ), Rd ancl Wr: DMA Verify (00), Write (01 ) or Read (1 0) cycle selection, 
AL: Auto Load, TCS: TC STOP, EW: EXTENDED WRITE, RP: ROTATING PRIORITY, EN3-EN0: CHANNEL ENABLE MASK, UP: UPDATE 
FLAG, TC3-TC0: TERMINAL COUNT STATUS BITS. / 



2-110 



AFN-01840D 



inter 



8257/8257-5 



SAMPLE HLDA 
RESOLVE DROn PRIORITIES 



PRESENT AND LATCH 
UPPER AOORESS 
PRESENT LOWER ADDRESS 



ACTIVATE READ COMMAND 
ADVANCED WRITE COMMAND 
AND DACKn 



ACTIVATE WRITE COMMAND 
ACTIVATE MARK AND TC 
IF APPROPRIATE 



DROn HLDA 



READY 
VERIFY 



SAMPLE 
READY 
LINE 



READY ♦ VERIFY 



RESET ENABLE FOR CHANNEL N IF 
TC STOP AND TC ARE ACTIVE 
DEACTIVATE COMMANDS 
DEACTIVATE DACKn, MARK AND TO 
SAMPLE DROn AND HLDA 
RESOLVE DROn PRIORITIES 
RESET HRQ IF HL0A = 0 OR DRO * 0 



HLDA ♦ DRQn 



1 DRQn REFERS TO ANY DRQ LINE ON AN ENABLED DMA CHANNEL. 



Figure 8. DMA Operation State Diagram 

DMA OPERATION 
Single Byte Transfers 

A single byte transfer is initiated by the I/O device rais- 
ing the DRQ line of one channel of the 8257. If the chan- 
nel is enabled, the 8257 will output a HRQ to the CPU. 
The 8257 now waits until a HLDA is received insuring 
that the sys tem bu s is free for its use. Once HLDA is 
received the DACK line fo r the requesting channel is ac- 
tivated (LOW). The DACK line acts as a chip select for 
the requesting I/O device. The 8257 then generates the 



read and write commands and byte transfer occurs be- 
tween the selected I/O device and memory. After the 
transfer is complete, the DACK line is set HIGH and the 
HRQ line is set LOW to indicate to the CPU that t he bus 
is now free for use. DRQ must remain HIGH until DACK 
is issued to be recognized and must go LOW before S4 
of the transfer sequence to prevent another transfer 
from occuring. (See timing diagram.) 

Consecutive Transfers 

If more than one channel requests service simultaneous- 
ly, the transfer will occur in the same way a burst does. 
No overhead is incurred by switching from one channel 
to another. In each S4 the DRQ lines are sampled and 
the highest priority request is recognized during the 
next transfer. A burst mode transfer in a lower priority 
channel will be overridden by a higher priority request. 
Once the high priority transfer has completed control 
will return to the lower priority channel if its DRQ is still 
active. No extra cycles are needed to execute this se- 
quence and the HRQ line remains active until all DRQ 
lines go LOW. 

Control Override 

The continuous DMA transfer mode described above 
can be interrupted by an external device by lowering the 
HLDA line. After each DMA transfer the 8257 samples 
the HLDA line to insure that it is still active. If it is not 
active, the 8257 completes the current transfer, releases 
the HRQ line (LOW) and returns to the idle state. If DRQ 
lines are still active the 8257 will raise the HRQ line in 
the third cycle and proceed normally. (See timing 
diagram.) 

Not Ready 

The 8257 has a Ready input similar to the 8080A and the 
8085A. The Ready line is sampled in State 3i If Ready is 
LOW the 8257 enters a wait state. Ready is sampled dur- 
ing every wait state. When Ready returns HIGH the 8257 
proceeds to State 4 to complete the transfer. Ready is 
used to interface memory or I/O devices that cannot 
meet the bus set up times required by the 8257. 

Speed 

The 8257 uses four clock cycles to transfer a byte of 
data. No cycles are lost in the master to master transfer 
maximizing bus efficiency. A 2MHz clock input will 
allow the 8257 to transfer at a rate of 500K bytes/second. 

Memory Mapped I/O Configurations 

The 8257 can be connected to the system bus as a memory 
device instead of as an I/O device for memory mapped I/O 
configurations by connecting the system memory control 
lines to the 8257's I/O control lines and the system I/O 
control lines to the 8257's memory control lines 

This configuration permits use of the 8080 s considerably 
larger repertoire of memory instructions when reading or 
loading the 8257's registers Note that with this 
connection,, the programming of the Read (bit 15) and 
Write (t?it 1 4) bits in the terminal count register will have a 
different meaning 



2-111 



8257/8257-5 





MEMRD 




MEMWR 


8257 






l/ORD 




i/OWR 



■ l/ORD 
• l/OWR 

■ MEMRD 
-MEMWR 



BIT 15 


BIT 14 




READ 


WRITE 




0 


0 


DMA Verify Cycle 


0 


1 


DMA Read Cycle 


1 


0 


DMA Write Cycle 


1 


1 


Illegal 



Figure 9. System Interface for Memory 
Mapped I/O 

SYSTEM APPLICATION EXAMPLES 



Figure 10. TC Register for Memory Mapped 
I/O Only 



ADDRESS BUS 



IE 



CONTROL BUS 



i7ow i7o"r 





DRQO 




DACK 0 




DRQ 1 


8257 




AND 


DACK 1 


8212 


DRQ 2 




DACK 2 




DRQ 3 




DACK 3 



SYSTEM 

RAM 
MEMORY 



DMA CONTROLLER 



Figure 11. Floppy Disk Controller (4 Drives) 



ADDRESS BUS 



CONTROL BUS 



8257 
AND 
8212 



8251 
USART 



SYSTEM 

RAM 
MEMORY 



TELEPHONE 
LINES 



Figure 12. High-Speed Communication Controller 

2-112 



AFN-01840D 



intel 



8257/8257-5 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



INPUT/OUTPUT 



^> TEST POINTS <^ 



A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR 
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC '1 
AND 0 8V FOR A LOGIC 0 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 



1 
I 



C L = 150 pF 



C L INCLUDES JIG CAPACITANCE 



Tracking Parameters 

Signals labeled as Tracking Parameters (footnotes 1 and 5-7 under A.C. Specifications) are signals that follow similar 
paths through the silicon die. The propagation speed of these signals varies in the manufacturing process but the 
relationship between all these parameters is constant. The variation is less than or equal to 50 ns. 

Suppose the following timing equation is being evaluated, 

T A(MiN) + T^max) < 150 ns 

and only minimum specifications exist for T A and T B . If T A(M|N) is used, and if T A and Tb are tracking parameters, 
Tb<max) can be taken as T^min) + 50 ns. 

T A (min) + 0"b(Min)* + 50 ns) < 150 ns 

*if T A and T B are tracking parameters 



WAVEFORMS— PERIPHERAL MODE 



WRITE 



CHIP SELECT 



ADDRESS BUS 



Of 





*• T AW * 

<- 
















t , 






< 


(<• T AW ► 


— 


t wa|* — 



3C 



\4 



RESET 



♦"'RSTW-*-! -* — 

Jrt 



■-Jr 



READ 



CHIP SELECf 



ADDRESS BUS 



RO 



o- 



2-113 



AFN-01840D 



irrteT 



8257/8257-5 




intgl 8257/8257-5 



WAVEFORMS (Continued) 
CONTROL OVERRIDE SEQUENCE 




NOT READY SEQUENCE 




2-115 



AFN-01840D 



inteT 



8257/8257-5 



10/R 
HOLD 
HLDA 
CLK (OUT) 
SIS!? IN 
RESET OUT 



11 


STB ° 0 '- 00 ' 








DS2 


2 


8212 




JT 


MO 

Ol t — 01, 


5si 



V cc 



B, 
A, 



. RESET 



Y 



IQW 



MEMR 

^ CONTROL 



± 



MEMR 

iOT* 

MEMW 

iow 

HRQ 
HLDA 

CLK 
RESET 



READY 
Ao 



DROo 
DACKo 

DRQ, 
DACK, 

DRQ, 
DACK i 

DRQj 
DACKj 
TC 



. DROo 
. DACKo 
. DRQ, 
' DACK, 
- DRQ} 

■ DACK? 
• DRQ] 

■ DACKj 

■ TC 



DS2 


CLR STB 


Dl, 


DO, 




8212 i 


01, 


DO, 


MO 


OTl 



rr 



Figure 13. Detailed System Interface Schematic 

2-116 



AFN-01840tD 



ABSOLUTE MAXIMUM RATINGS* 



Ambient Temperature Under Bias 0°C to 70°C 

Storage Temperature -65°C to +150°C 

Voltage on Any Pin 

With Respect to Ground -0.5V to +7V 

Power Dissipation 1 Watt 



'NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (8257: T A = 0°C to 70°C, V C c = 5.0V ±5%, GND = 0V) 

(8257-5: T A = 0°C to 70°C, V C c = 5.0V ±10%, GND = 0V) 



Symbol 


Parameter 


Mln. 


Max. 


Unit 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 


0.8 


Volts 




V, H 


Input High Voltage 


2.0 


V CC +.5 


Volts 




Vol 


Output Low Voltage 




0.45 


Volts 


Iol = 1 .6 mA 


V 0 H 


Output High Voltage 


2.4 


Vcc 


Volts 


Ioh = -150mA for AB, 
DB and AEN 
k)H = -80jLiA for others 


V H h 


HRQ Output High Voltage 


3.3 


v cc 


Volts 


i 0 H = -80/iA 


•cc 


Vcc Current Drain 




120 


mA 




»IL 


Input Leakage 




±10 


MA 


0V*£V, N *sV cc 


'OFL 


Output Leakage During Float 




±10 


ma 


0.45V V 0U T * V CC 



CAPACITANCE (T A = 25°C; v C c = gnd = ov) 



Symbol 


Parameter 


Mln. 


Typ. 


Max. 


Unit 


Test Conditions 


C|N 


Input Capacitance 






10 


pF 


fc= 1MHz 


C|/0 


I/O Capacitance 






20 


pF 


Unmeasured pins 
returned to GND 



2-117 



AFN-01840D 



8257/8257-5 



A.C. CHARACTERISTICS — PERIPHERAL (SLAVE) MODE 

(8257: T A - 0°C to 70°C, V cc « 5.0V ±5%, GND = 0V) 
(8257-5: T A = 0°C to 70°C, V cc = 5.0V ±10%, GND = 0V) 

8080 Bus Parameters 
READ CYCLE 



Symbol 


Parameter 


8257 


82575 


Unit 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


Tar 


Adr or CS4 Setup to RD4 


0 




0 




ns 




Tra 


Adror CSt Hold from RDt 


0 




0 




ns 




Trd 


Data Access from RD4 


0 


300 


0 


220 


ns 




Tdf 


DB-»Float Delay from RDt 


20 


150 


20 


120 


ns 




T RR 


RD Width 


250 




250 




ns 





WRITE CYCLE 



Symbol 


Parameter 


8257 


82575 


Unit 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


T AW 


Adr Setup to WR4 


20 




20 




ns 




T WA 


Adr Hold from WRt 


0 




0 




ns 




T DW 


Data Setup to WRt 


200 




200 




ns 




T WD 


Data Hold from WRt 


10 




10 




ns 




T WW 


WR Width 


200 




200 




ns 





OTHER TIMING 



Symbol 


Parameter 


8257 


8257-5 


Unit 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


Trstw 


Reset Pulse Width 


300 




300 




ns 




T RSTD 


Power Supply t (V C c) Setup to Reset i 


500 




500 




/is 




T r 


Signal Rise Time 




20 




20 


ns 




Tf 


Signal Fall Time 




20 




20 


ns 




Trsts 


Reset to First l/OWR 


2 




2 




tCY 





A.C. CHARACTERISTICS— DMA (MASTER) MODE 

(8257: T A 0°C to 70°C, V cc = 5.0V ±5%, GND = 0V) 
(8257-5: T A = 0°C to 70°C, V cc = 5.0V ±10%, GND = 0V) 

TIMING REQUIREMENTS 



Symbol 


Parameter 


8257 


8257-5 


Unit 


Min. 


Max. 


Min. 


Max. 


T C Y 


Cycle Time (Period) 


0.320 


4 


0.320 


4 


us 


T e 


Clock Active (High) 


120 


.8T CY 


80 


.8T CY 


ns 


T QS 


DRQt Setup to CLKl (SI, S4) 


120 




120 




ns 


T QH 


DRQI Hold from HLDAt t1] 


0 




0 




ns 


T HS 


HLDAI or ISetup to CLKl(SI, S4) 


100 




100 




ns 


T RS 


_ READY Setup Time to CLKt(S3, Sw) 


30 




30 




ns 


T RH 


READY Hold Time from CLKf (S3, Sw) 


30 




30 




ns 



2-118 



AFN-01840D 



8257/8257-5 



A.C. CHARACTERISTICS— DMA (MASTER) MODE 

(8257: T A = 0°C to 70°C, V C c = 5.0V ±5%, GND = 0V) 
(8257-5: T A « 0°C to 70°C, Vcc = 5.0V ±10 %. GND = ov ) 
TIMING RESPONSES 



Symbol 


Parameter 


8257 


8257-5 


Unit 


Mln. 


Max. 


Mln. 


Max. 


T DQ 


HRQ| or IDelay from CLKt (SI, S4) 
(measured at 2.0V) 




160 




160 


ns 


T DQ1 


HRQt or IDelay from CLKt (SI, S4) 
(measured at3.3V) [al 








ocn 

£v>U 


ns 


Tael 


AENf Delay from CLK| (S1) 




300 




300 


ns 


T AET 


AEN| Delay from CLKt (SI) 




200 




200 


ns 


T AEA 


Ml 

Adr (AB) (Active) Delay from AENf (S1) m 


20 




20 




ns 


T FAAB 


Adr (AB) (Active) Delay from CLKf (S1) [2] 




250 




250 


ns 


T AFAB 


Adr (AB) (Float) Delay from CLKt (Sl) [2] 




150 




150 


ns 


Tasm 


Adr (AB) (Stable) Delay from CLKf (S1) [2] 




250 




250 


ns 


Tah ' 


Adr (AB) (Stable) Hold from CLKt (S1) [2] 


Tasm -50 




Tasm -so 




ns 


T AHR 


Adr (AB) (Valid) Hold from RDf (S1, Sl) [11 


60 




60 




ns 


T AHW 


Adr (AB) (Valid) Hold from Wrf (S1, Sl) [1] 


300 




300 




ns 


T FADB 


Adr (DB) (Active) Delay from CLKt (S1) L 1 




300 




300 


ns 


T AFDB 


Adr (DB) (Float) Delay from CLKt (S2) [21 


Tstt + 20 


250 


Tstt + 20 


170 


ns 


TaSS 


Adr (DB) Setup to Adr Stbi (S1-S2) [1] 


100 




100 




ns 


T AHS 


Adr (DB) (Valid) Hold from Adr Stb| (S2) [1] 


20 




20 




ns 


T STL 


Adr Stbt Delay from CLKt (S1) 




200 




200 


ns 


T STT 


Adr Stb| Delay from CLKt (S2) 




140 




140 


ns 


T SW 


Adr Stb Width (S1-S2) [1] 


T CY -100 




T CY -100 




ns 


T ASC 


Rdj or Wr(Ext)| Delay from Adr Stb| 










/ 

ns 


T DBC 


(Float) (S2) l1] 


20 




20 




ns 


T A K 


DACKt or IDelay from CLK| (S2, S1) and 
TC/Markt Delay from CLKt (S3) and 
TC/Markl Delay from CLKt (S4) [41 




250 




250 


ns 


T DCL 


RD| or Wr(Ext)4 Delay from CLKt (S2) and 
Wr| Delay from CLKt (S3) [2 ' 5] 




200 




200 


ns 


T DCT 


Rdt Delay from CLK| (S1, SI) and 
Wrf Delay from. CLKt (S4)t 2 ' 6 ^ 




200 




200 


ns 


T FAC 


Rdor Wr (Active) from CLKt (S1) [2] 




300 




300 


ns 


T AFC 


Rd or Wr (Active) from CLKt (S1) l2] 




150 




150 


ns 


T RWM 


Rd Width (S2-S1 orSI) m 


2T CY +T0-5O 




2T C Y+T0-5O 




ns 


T WWM 


Wr Width (S3-S4) 111 


Tcy-50 




Tcy-50 




ns 


T WWME 


WR(Ext) Width (S2-S4) [1] 


2T CY -50 




2T CY -50 




ns 



NOTES: 

1. Tracking Parameter. 3. Load = V 0H = 3.3V. 5. AT DCL < 50 ns. 

2. Load = + 50 pF. 4". AT AK < 50 ns. 6. AT DCT < 50 ns. 



2-119 



AFN-01840D 



8259A/8259A-2/8259A-8 
PROGRAMMABLE INTERRUPT CONTROLLER 



■ IAPX 86, iAPX 88 Compatible 

■ MCS-80®, MCS-85® Compatible 

■ Eight-Level Priority Controller 

■ Expandable to 64 Levels 

a Programmable Interrupt Modes 



■ Individual Request Mask Capability 

■ Single + 5V Supply (No Clocks) 

■ 28-Pin Dual-ln-Line Package 

■ Available in EXPRESS 

- Standard Temperature Range 

- Extended Temperature Range 



The Intel® 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is 
cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses 
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input. 

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has 
several modes, permitting optimization for a variety of system requirements. 

The 8259A is fully upward compatible with the Intel® 8259. Software originally written for the 8259 will operate the 
8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered). 



D 7 -D c 



DATA 
BUS 
BUFFER 



RD -C 






WR ^*<J 


READ/ 




WRITE 




LOGIC 






A 0 * 




CS 


? 



CASO - 
CAS1 - 
CAS 2 « 



CASCADE 
BUFFER/ 
COMPARATOR 



CONTROL LOGIC 



SERVICE 
REG 
<»SR> 



/-A 
W 



n 



INTERRUPT 
REQUEST 
REG 
(IRR) 



-IRO 
-IR1 
-IR2 

«• IR3 

-IR4 
-IR5 
-IR6 
-IR7 



INTERRUPT MASK REG 
(IMR) 



. INTERNAL BUS 



csC 
wrC 
rdC 

D3C 

D,C 

CASOC 
CAS 1 f~ 

gndC 



DVcc 

□ iNTA 

□ IR7 

□ IR6 
DlR5 
DIR4 
IJ1R3 

□ »R2 

□ mi 
Diro 

□ «NT 
3 CAS 2 



Figure 1. Block Diagram 



Figure 2. Pin Configuration 



Intel Corporation Assumes No Responsibly for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other Circuit Patent Licenses are Implied. 
©INTEL CORPORATION. 1980 2-120 AFN-00221C 




8259A/8259A-2/8259A-8 



Table 1. Pin Description 



Symbol 


Pin No. 


Typo 


Nam© and Function 


v C c 


28 


' 


Supply: +5V Supply. 


GND 


14 




Ground. 


OS 


1 




Chip Soloct: A low on this pin enables RD and WR communication between the CPU and the 8259A, 
INTA functions are independent of CS. 


Wn 


0 
c. 




Write: A low on this pin when CS is low enables the 8259A to accept command words from the CPU. 


RD 


3 


1 


Road: A low on this pin when CS is low enables the 8259A to release status onto the data bus for the 
CPU. 


D7-D0 


4-11 


I/O 


Bidirectional Data Bus: Control, status and interrupt-vector information is'transferred via this bus. 


CASq— CAS2 


12,13,15 


I/O 


Cascade Lines: The CAS lines form a private 8259A bus to control a multiple 8259A structure. These 
pins are outputs for a master 8259A and inputs for a slave 8259A. 


SP/EN 


16 


I/O 


Slave Program/Enable Buffer: This is a dual function pin. When in the Buffered Mode it can be used 
as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input 
to designate a master (SP = 1) or slave (SP = 0). 


INT 


17 


0 


Interrupt: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the 
CPU, thus it is connected to the CPUte interrupt pin. 


IR0-IR7 


18-25 


1 


Interrupt Requests: Asynchronous inputs. An interrupt request is executed by raising an IR input 
(low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high 
level on an IR input (Level Triggered Mode). 


INTA 


26 


1 


Interrupt Acknowledge: This pin is used to enable 8259A interrupt-vector data onto the data bus by 
a sequence of interrupt acknowledge pulses issued by the CPU. 


Ao 


27 


1 


AO Address Line: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 8259A 
to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically 
connected to the CPU AO address line (A1 for iAPX 86, 88). 



2-121 



AFN-00221E 



8259A/8259A-2/8259A-8 



FUNCTIONAL DESCRIPTION 
Interrupts in Microcomputer Systems 

Microcomputer system design requires that I/O devices 
such as keyboards, displays, sensors and other com- 
ponents receive servicing in an efficient manner so that 
large amounts of the total system tasks can be assumed 
by the microcomputer with little or no effect on through- 
put. 

The most common method of servicing such devices is 
the Polled approach. This is where the processor must 
test each device in sequence and in effect "ask" each 
one if it needs servicing. It is easy to see that a large por- 
tion of the main program is looping through this con- 
tinuous polling cycle and that such a method would 
have a serious, detrimental effect on system through- 
put, thus limiting the tasks that could be assumed by 
the microcomputer and reducing the cost effectiveness 
of using such devices. 

A more desirable method would be one that would allow 
the microprocessor to be executing its main program 
and only stop to service peripheral devices when it is 
told to do so by' the device itself. In effect, the method 
would provide an external asynchronous input that 
would inform the processor that it should complete 
whatever instruction that is currently being executed 
and fetch a new routine that will service the requesting 
device. Once this servicing is complete, however, the 
processor would resume exactly where it left off. 

This method is called Interrupt. It is easy to see that 
system throughput would drastically increase, and thus 
more tasks could be assumed by the microcomputer to 
further enhance its cost effectiveness. 

The Programmable Interrupt Controller (PIC) functions 
as an overall manager in an Interrupt-Driven system 
environment. It accepts requests from the peripheral 
equipment, determines which of the incoming requests 
is of the highest importance (priority), ascertains 
whether the incoming request has a higher priority value 
than the level currently being serviced, and issues an 
interrupt to the CPU based on this determination. 
Each peripheral device or structure usually has a special 
program or "routine" that is associated with its specific 
functional or operational requirements; this is referred 
to as a "service routine". The PIC, after issuing an Inter- 
rupt to the CPU, must somehow input information into 
the CPU that can "point" the Program Counter to the 
service routine associated with the requesting device. 
This "pointer" is an address in a vectoring table and will 
Often be referred to, in this document, as vectoring data. 

The 8259A 

The 8259A is a device specifically designed for use in 
real time, interrupt driven microcomputer systems. It 
manages eight levels or requests and has built-in fea- 
tures for expandability to other 8259A's (up to 64 levels). 
It is programmed by the system's software as ah I/O 
peripheral. A selection of priority modes is available to 
the programmer so that the manner in which the re- 
quests are processed by the 8259A can be configured to 



match his system requirements. The priority modes can 
be changed or reconfigured dynamically at any time dur- 
ing the main program. This means that the complete 
interrupt structure can be defined as required, based on 
the total system environment. 



7v 



CPU DRIVEN 
MULTIPLEXOR 



O 



I I 

I I 



Figure 3a. Polled Method 



CPU INT 



7^ 



n 

i 

I/O (N) I- 



\7 



Figure 3b. Interrupt Method 



2-122 



AFN-00221E 



8259A/8259A-2/8259A-8 




CONTROL LOGIC 



is 



21 



INTERNAL BUS 



INTERRUPT REQUEST REGISTER (IRR) AND 
IN-SERVICE REGISTER (ISR) 

The interrupts at the IR input lines are handled by two 
registers in cascade, the interrupt Request Register 
(IRR) and the In-Service Register (ISR). The IRR is used 
to store all the interrupt levels which are requesting ser- 
vice; and the ISR is used to store all the interrupt levels 
which are being serviced. 

PRIORITY RESOLVER 

This logic block determines the priorities of the bits set 
in the IRR. The highest priority is selected and s trobed 
into the corresponding bit of the ISR during INTA pulse. 

INTERRUPT MASK REGISTER (I MR) 

The IMR stores the bits which mask the interrupt lines 
to be masked. The IMR operates on the IRR. Masking of 
a higher priority input will not affect the interrupt 
request lines of lower priority. 

INT (INTERRUPT) 

This output goes directly to the CPU interrupt input. The 
Vqh level on this line is designed to be fully compatible 
with the 8080A, 8085A and 8086 input levels. 

INTA (INTERRUPT ACKNOWLEDGE) 

INTA pulses will cause the 8259 A to release vectoring 
information onto the data bus. The format of this data 
depends on the system mode (mPM) of the 8259A. 

DATA BUS BUFFER 

This 3-state, bidirectional 8-bit buffer is used to inter- 
face the 8259 A to the system Data Bus. Control words 
and status information are transferred through the Data 
Bus Buffer. 

READ/WRITE CONTROL LOGIC 

The function of this block is to accept OUTput com- 
mands from the CPU. It contains the Initialization Com- 
mand Word (ICW) registers and Operation Command 
Word (OCW) registers which store the various control 
formats for device operation. This function block also 
allows the status of the 8259A to be transferred onto the 
Data Bus. 

CS (CHIP SELECT) 

A LOW on this input enables the 8259A. No reading or 
writing of the chip will occur unless the device is 
selected. 

WR (WRITE) 

A LOW on this input enables the CPU to write control 
words (ICWs and OCWs) to the 8259A. 

RD (READ) 

A LOW on this input enables the 8259A to send the 
status of the Interrupt Request Register (IRR), In Service 
Register (ISR), the Interrupt Mask Register (IMR), or the 
Interrupt level onto the Data Bus. 



Figure 4b. 8259 A Block Diagram 



A 0 _ 

This input signal is used in conjunction with WR and RD 
signals to write commands into the various command 
registers, as well as reading the various status registers 
of the chip. This line can be tied directly to one of the ad- 
dress lines. 



2-123 



AFN-00221E 



8259A/8259A-2/8259A-8 



THE CASCADE BUFFER/COMPARATOR 

This function block stores and compares the IDs of all 
8259A's used in the system. The associated three I/O 
pins (CASO-2) are outputs when the 8259A is used as a 
master and are inputs when the 8259A is used as a 
. slave. As a master, the 8259A sends the ID of the inter- 
rupting slave device onto the CASO-2 lines. The slave 
thus selected will send its preprogrammed subroutine 
address ont o the Data Bus during the next one or two 
consecutive INTA pulses. (See section "Cascading the 
8259A".) 



INTERRUPT SEQUENCE 

The powerful features of the 8259A in a microcomputer 
system are its programmability and the interrupt routine 
addressing capability. The latter allows direct or indirect 
jumping to the specific interrupt routine requested 
without any polling of the interrupting devices. The nor- 
mal sequence of events during an interrupt depends on 
the type of CPU being used. 

The events occur as follows in an MCS-80/85 system: 

1.0ne or more of the INTERRUPT REQUEST lines 
(IR7-0) are raised high, setting the corresponding IRR 
bit(s). 

2. The 8259A evaluates these requests, and sends an 
INT to the CPU, if appropriate. 

3. The C PU acknowledges the INT and responds with an 
INTA pulse. 

4. Upon receiving an INTA from the CPU group, the 
highest priority ISR bit is set, and the corresponding 
IRR bit is reset. The 8259A will also release a CALL in- 
struction code (11001101) onto the 8-bit Data Bus 
through its D7-0 pins. 

5. This CALL instruction will initiate two more INTA 
pulses to be sent to the 8259A from the CPU group. 

6. These two INTA pulses allow the 8259A to release its 
preprogrammed subroutine address onto the Data 
Bus. The lower 8-bit address is released at the first 
INTA pulse and and the h igher 8-bit address is re- 
leased at the second INTA pulse. 

7. This completes the 3-byte CALL instruction released 
by the 8259A. In the AEO I mode the ISR bit is reset at 
the end of the third INTA pulse. Otherwise, the ISR bit 
remains set until an appropriate EOI command is 
issued at the end of the interrupt sequence. 

The events occurring in an iAPX 86 system are the same 
until step 4. 

4. Upon receiving an INTA from the CPU group, the high- 
est priority ISR bit is set and the corresponding IRR 
bit is reset. The 8259A does not drive the Data Bus 
during this cycle. 

5. The iAPX 86/10 will initiate a second INTA pulse. 
During this pulse, the 8259A releases an 8-bit pointer 
onto the Data Bus where it is read by the CPU. 

6. This completes the interrupt cycle. In the AEOI mode 
the l$R bit is reset at the end of the second INTA 
pulse. Otherwise, the ISR bit remains set until an 
appropriate EOI command is issued at the end of the 
interrupt subroutine. 



If no interrupt request is present at step 4 of either 
sequence (i.e., the request was too short in duration) the 
8259A will issue an interrupt level 7. Both the vectoring 
bytes and the CAS lines will look like an interrupt level 7 
was requested. 



■°.o 



READ/ 
WRITE 
LOGIC 



CONTROL LOGIC 



hi 



EI 



INTERRUPT MASK REG 



INTERNAL BUS 



Figure 4c. 8259A Block Diagram 



ADDRESS BUS (16) 



CONTROL BUS 



INTA 



CASCADE 
LINES 



A 0 D 7 D„ R~5 WR" INT INTA 



CAS 2 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 
§P/6N 7 6 5 4 3 2 1 0 



SLAVE PROGRESS/ L 
ENABLE BUFFER 



INTERRUPT 
REQUESTS 



Figure 5. 8259A Interface to Standard 
System Bus 



2-124 



AFN-00221E 



8259A/8259A-2/8259A-8 



INTERRUPT SEQUENCE OUTPUTS 
MCS-80®, MCS-85® 

This sequ ence is timed by three INTA pulses. During the 
first INTA pulse the CALL opcode is enabled onto the 
data bus. 

Content of First Interrupt 
Vector Byte 

D7 06 OS 04 D3 02 01 DO 



CALL CODE 110 0 110 1 



During the second INTA pulse the lower address of the 
appropriate service routine is enabled onto the data bus. 
When Interval = 4 bits A 5 -A 7 are programmed, while A 0 - 
A 4 are automatically inserted by the 8259A. When Inter- 
val = 8 only A 6 and A 7 are programmed, while A 0 -A 5 are 
automatically inserted. 



Content of Second Interrupt 
Vector Byte 



IR 


Interval * 4 




D7 


06 


05 


04 


03 


D2 


01 


00 


7 


A7 


A6 


A5 


1 


1 


1 


0 


0 


6 


A7 


A6 


A5 


1 


1 


0 


0 


0 


5 


A7 


A6 


A5 


1 


0 


1 


0 


0 


4 


A7 


A6 


A5 


1 


0 


0 


0 


0 


3 


A7 


A6 


A5 


0 


1 


1 


0 


0 


2 


A7 


A6 


A5 


0 


1 


0 


0 


0 


1 


A7 


A6 


A5 


0 


0 


1 


0 


0 


0 


A7 


A6 


A5 


0 


0 


0 


0 


0 




IR 


Interval = 8 




D7 


D6 


05 


D4 


D3 


D2 


D1 


DO 


7 


A7 


A6 


1 


1 


1 


0 


0 


0 


6 


A7 


A6 


1 


1 


0 


0 


0 


0 


5 


A7 


A6 


1 


0 


1 


0 


0 


0 


4 


A7 


A6 


1 


0 


0 


0 


0 


0 


3 


A7 


A6 


0 


1 


1 


0 


0 


0 


2 


A7 


A6 


0 


1 


0 


0 


0 


0 


1 


A7 


A6 


0 


0 


1 


0 


0 


0 


0 


A7 


A6 


0 


0 


0 


0 


0 


0 



During the third INTA pulse the higher address of the 
appropriate service routine, which was programmed as 
byte 2 of the initialization sequence (A 8 -A 15 ), is 
enabled onto the bus. 



Content of Third Interrupt 
Vector Byte 

D7 D6 PS 04 D3 D2 D1 DO 

| A15 | A14 | A13 | A12 | A11 | A10 | A9 | A8 | 

iAPX 86, iAPX 88 

iAPX 86 mode is similar to MCS-80 mode except that only 
two Interrupt Acknowledge cycles are issued by the pro- 
cessor and no CALL opcode is sent to the processor. The 
first interrupt acknowledge cycle is similar to that of 
MCS-80, 85 systems in that the 8259A uses it to internally 
freeze the state of the interrupts for priority resolution and 
as a master it issues the interrupt code on the cascade 
lines at the end of the INTA pulse. On this f irst cycle it does 



not issue any data to the processor and leaves its data bus 
buffers disabled. On the second interrupt acknowledge 
cycle in iAPX 86 mode the master (or slave if so pro- 
grammed) will send a byte of data to the processor with 
the acknowledged interrupt code composed as follows 
(note the state of the ADI mode control is ignored and 
A5-A11 are unused in iAPX 86 mode): 



Content of Interrupt Vector Byte 
for IAPX 86 System Mode 





07 


D6 


D5 


04 


03 


02 


D1 


DO 


IR7 


T7 


T6 


T5 


T4 


T3 


1 


1 


1 


IR6 


T7 


T6 


T5 


T4 


T3 


1 


1 


0 


IR5 


T7 


T6 


T5 


T4 


T3 


1 


0 


1 


IR4 


T7 


T6 


T5 


T4 


T3 


1 


0 


0 


IR3 


T7 


T6 


T5 


T4 


T3 


0 


1 


1 


IR2 


T7 


T6 


T5 


T4 


T3 


0 


1 


0 


IR1 


17 


T6 


T5 


T4 


T3 


0 


0 


1 


IRQ 


17 


T6 


T5 


T4 


T3 


0 


0 


0 



PROGRAMMING THE 8259A 

The 8259A accepts two types of command words gener- 
ated by the CPU: 

1. Initialization Command Words (ICWs): Before normal 
operation can begin, each 8259A in the system must 
be brought to a starting point — by a sequence of 2 to 
4 bytes timed by WE pulses. 

2. Operation Command Words (OCWs): These are the 
command words which command the 8259A to oper- 
ate in various interrupt modes. These modes are: 

a. Fully nested mode 

b. Rotating priority mode 

c. Special mask mode 

d. Polled mode 

The OCWs can be written into the 8259A anytime after 
initialization. 

INITIALIZATION COMMAND WORDS 

(ICWS) 

GENERAL 

Whenever a command is issued with A0 = 0 and D4 = 1, 
this is, interpreted as Initialization Command Word 1 
(ICW1). ICW1 starts the initialization sequence during 
which the following automatically occur. 

a. The edge sense circuit is reset, which means that fol- 
lowing initialization, an interrupt request (IR) input 
must make a low-to-high transition to generate an 
interrupt. 

b. The Interrupt Mask Register is cleared. 

c. IR7 input is assigned priority 7. 

d. The slave mode address is set to 7. 

e. Special Mask Mode is cleared and Status Read is set to 
IRR. 

f. If IC4=0, then all functions selected in ICW4 are set to 
zero. (Non-Buffered mode*, no Auto-EOI, MCS-80, 85 
system). 

•Note: Master/Slave in ICW4 is only used in the buffered mode 



2-125 



AFN-00221E 



inteT 



8259A/8259A-2/8259A-8 



INITIALIZATION COMMAND WORDS 1 AND 2 
(ICW1, ICW2) 

A 5 -A 15 : Page starting address of service routines. In an 
MCS 80/85 system, the 8 request levels will generate 
CALLS to 8 locations equally spaced in memory. These 
can be programmed to be spaced at intervals of 4 or 8 
memory locations, thus the 8 routines will occupy a 
page of 32 or 64 bytes, respectively. 

The address format is 2 bytes long (A 0 -A 15 ). When the 
routine interval is 4, A 0 -A 4 are automatically inserted by 
the 8259A, while A 5 -A 15 are programmed externally. 
When the routine interval is 8, A 0 -A 5 are automatically 
inserted by the 8259A, while A 6 -A 15 are programmed 
externally. 

The 8-byte interval will maintain compatibility with cur- 
rent software, while the 4-byte interval is best for a com- 
pact jump table. 

In an iAPX 86 system A-15-A-n are inserted in the five most 
significant bits of the vectoring byte and the 8259A sets 
the three least significant bits according to the interrupt 
level. A-10-A5 are ignored and ADI (Address interval) has 
no effect. 



LTIM: 



ADI: 



If LTIM = 1, then the 8259A will operate in the 
level interrupt mode. Edge detect logic on the 
interrupt inputs will be disabled. 



CALL address interval. ADI = 
ADI = 0 then interval = 8. 



1 then interval = 4; 



SNGL: Single. Means that this is the only 8259A in the 
system. If SNGL= 1 no ICW3 will be Issued. 



IC4: 



If this bit is set - ICW4 has to be read. If ICW4 
is not needed, set IC4 = 0. 



INITIALIZATION COMMAND WORD 3 (ICW3) 

• This word is read only when there is more than one 
8259A in the system and cascading is used, in which 
case SNGL = 0. It will load the 8-bit slave register. The 
functions of this register are: 

a. In the master mode (either when SP = 1 , or in buffered 
mode when M/S=1 in ICW4) a "1" is set for each 
slave in the system. The master then will release byte 
1 of the call sequence (for MCS-80/85 system) and 
will enable the corresponding slave to release bytes 2 
and 3 (for iAPX 86 only byte 2) through the cascade 

. lines. 

b. In the slave mode (either when 3F=0, or if BUF= 1 
and M/S = 0 in ICW4) bits 2-0 identify the slave. The 
slave compares its cascade input with these bits and, 
if they are equal, bytes 2 and 3 of the call sequence (or 
just byte 2 for iAPX 86 are released by it on the Data 
Bus. 

' INITIALIZATION COMMAND WORD 4 (ICW4) 

SFNM: If SFNM = 1 the special fully nested mode is 
programmed. 

BUF: If BUF= 1 the buffered mode is programmed. In 
buffered mode SP/EN becomes an enable output 
and the master/slave determination is by M/S. 

MIS: If buffered mode is selected: M/S = 1 means the 
8259A is programmed to be a master, M/S = 0 
means the 8259A is programmed to be a slave. If 
BUF = 0, M/S has no function. 

AEOI: If AEOI = 1 the automatic end of interrupt mode 
is programmed. 

j4PM: Microprocessor mode: /uPM = 0 sets the 8259A for 
MCS-80, 85 system operation, /xPM = 1 sets the 
8259A for iAPX 86 system operation. 






NEEDED 

TyES (IC4 = 1) 
ICW4 j 












.READY TO ACCEPT 
INTERRUPT REQUESTS 



Figure 6. Initialization Sequence 

2-126 



AFN-00221E 



8259A/8259A-2/8259A-8 



D, Dj 



LTIM ADI SNGL IC4 



CALL ADDRESS INTERVAL 
1 - INTERVAL OF 4 
0- INTERVAL OF 8 



A 7 -A 6 of INTERRUPT 
VECTOR ADDRESS 
(MCS-80/85 MODE ONLY) 



1 


X 


A 'X. 




X 


X 


































A, s -A 8 OF INTERRUPT 
VECTOR ADDRESS 

(MCS80/85 MODE) 
T 7 -T 3 OF INTERRUPT 
VECTOR ADDRESS 

(8086/8088 MODE) 


A 0 D 


ICW3 (MASTER DEVICE) 
7 °6 °S °« D 3 D, D, Dg 



= IR INPUT HAS A SLAVE 
- IR INPUT DOES NOT HAVE 
A SLAVE 



ICW3 (SLAVE DEVICE) 

D 4 Dj Dj D, 



ICW4 

Ao D7 D6 O5 0« D3 O2 Dl 





0 


0 


0 


SFNM 


BUF 


M/S 


AEOI 


UPM 



NOTE 1; SLAVE ID IS EQUAL TO THE CORRESPONDING 
MASTER IR INPUT. 



AUTO EOI 
= NORMAL EOI 



NON BUFFERED MODE 
8UFFEREO MODE/SLAVE 
BUFFERED MODE /MASTER 



1 = SPECIAL FULLY NESTED 
MODE 

0 = NOT SPECIAL FULLY 
NESTED MODE 



Figure 7. Initialization Command Word Format 



2-127 



AFN-O0221E 



8259A/8259A-2/8259A-8 



OPERATION COMMAND WORDS (OCWs) 

After the Initialization Command Words (ICWs) are pro- 
grammed into the 8259A, the chip is ready to accept 
interrupt requests at its input lines. However, during the 
8259A operation, a selection of algorithms can com- 
mand the 8259A to operate in various modes through 
the Operation Command Words (OCWs). 



OPERATION CONTROL WORDS (OCWs) 



0CW1 

AO 07 06 05 04 03 02 01 DO 

| 1 | | M7 M6 MS M4 M3 M2 M1 MO | 



0CW2 

0~| | R SL EOI 0 0 12 L1 LP | 



0CW3 

| 0 | | 0 ESMM SMM 0 1 P RR RIS | 



OPERATION CONTROL WORD 1 (0CW1) 

0CW1 sets and clears the mask bits in the interrupt \ 
Mask Register (IMR). M 7 - Mo represent the eight mask 
bits. M = 1 indicates the channel is masked 
(inhibited), M = 0 indicates the channel is enabled. 



OPERATION CONTROL WORD 2 (0CW2) 

R, SL, EOI — These three bits control the Rotate and 
End of Interrupt modes and combinations of the two. A 
chart of these combinations can be found on the Opera- 
tion Command Word Format. 

L 2 , L-i, Lq — These bits determine the interrupt level acted 
upon when the SL bit is active. 



OPERATION CONTROL WORD 3 (0CW3) 

ESMM — Enable Special Mask Mode. When this bit is 
set to 1 it enables the SMM bit to set or reset the Special 
Mask Mode. When ESMM = 0 the SMM bit becomes a 
"don't care". 

SMM — Special Mask Mode. If ESMM = 1 and SMM = 1 
the 8259A will enter Special Mask Mode. If ESMM = 1 
and SMM = 0 the 8259A will revert to normal mask mode. 
When ESMM = 0, SMM has no effect. 



2-128 



AFN-00221E 



8259A/8259A-2/8259A-8 



M3 M2 Ml MO 



INTERRUPT MASK 
1 ■= MASK SET 
0 = MASK RESET 




ROTATE ON NON-SPECIFIC EOI COMMAND 
ROTATE IN AUTOMATIC EOI MODE (SET) 
ROTATE IN AUTOMATIC EOI MODE (CLEAR) 
•ROTATE ON SPECIFIC EOI COMMAND 
'SET PRIORITY COMMAND 
NO OPERATION 

•LO-L2 ARE USED 



END OF INTERRUPT 



AUTOMATIC ROTATION 



SPECIFIC ROTATION 



READ REGISTER COMMAND 



READ 
IR REG 
ON NEXT 
RD PULSE 



READ 
IS REG 
ON NEXT 
RD PULSE 



SPECIAL MASK MODE 



Figure 8. Operation Command Word Format 



2-159 



AFN-00221E 



inter 



8259A/8259A-2/8259A-8 



FULLY NESTED MODE 

this mode is entered after initialization unless another 
mode is programmed. The interrupt requests are 
ordered in priority form 0 through 7 (0 highest). When an 
interrupt is acknowledged the highest priorjty request is 
determined and its vector placed on the bus. Additional- 
ly, a bit of the Interrupt Service register (ISO-7) is set. 
This bit remains set until the microprocessor issues an 
End of Interrupt (EOI) command immediately before 
returning from the service routine, or if AEOI (Automatic 
End of Interrupt) bit is set, until the trailing edge of the 
last INTA. While the IS bit is set, all further interrupts of 
the same or lower priority are inhibited, while higher 
levels will generate an interrupt (which will be 
acknowledged only if the microprocessor internal Inter- 
rupt enable flip-flop has been re-enabled through soft- 
ware). 

After the initialization sequence, IRO has the highest 
priority and IR7 the lowest. Priorities can be changed, as 
will be explained, in the rotating priority mode. 

END OF INTERRUPT (EOI) 

The In Service (IS) bit can be reset either automat ically 
following the trailing edge of the last in sequence INTA 
pulse (when /(EOI bit in ICW1 is set) or by a command 
word that must be issued to the 8259A before returning 
from a service routine (EOI command). An EOI command 
must be issued twice if in the Cascade mode, once for the 
master and once for the corresponding slave. 

There are two forms of EOI command: Specific and Non- 
specific. When the 8259A is operated in modes which 
preserve the fully nested structure, it can determine 
which IS bit to reset on EOI. When a Non-Specific EOI 
command is issued the 8259A will automatically reset 
the highest IS bit of those that are set, since in the 
fully nested mog'e the highest IS level was necessarily the 
last level acknowledged and serviced. A non-specific EOI 
can be issued with OCW2 (EOI = 1, SL = 0, R = 0). 

When a mode is used which may disturb the fully nested 
structure, the 8259A may no longer be able to determine 
the last level acknowledged. In this case a Specific End of 
Interrupt must be issued which includes as part of the 
command the IS level to be reset. A specific EOI can be is- 
sued with OCW2 (EOI = 1, SL = 1, R = 0 v and LO-L2 is the 
binary level of the IS bit to be reset). 

It should be noted that an IS bit that is masked by an 
IMR bit will not be cleared by a non-specific EOI if the 
8259A is in the Special Mask Mode. 

AUTOMATIC END OF INTERRUPT (AEOI) MODE 

If AEOI = 1 in ICW4, then the 8259A will operate in AEOI 
mode continuously until reprogrammed by ICW4. In this 
mode the 8259A will automatically perform a non- 
specific EOI operation at the trailing edge of the last 
interrupt acknowledge pulse (third pulse in MCS-80785, 
second in iAPX 86). Note that from a system standpoint, 
this mode should be used only when a nested multilevel 
interrupt structure is not required within a single 8259A. 

The AEOI mode can only be used in a master 8259A and 
not a slave. 



AUTOMATIC ROTATION 
(Equal Priority Devices) 

In some applications there are a number of interrupting 
devices of equal priority. In this mode a device, after 
being serviced, receives the lowest priority, so a device 
requesting an interrupt will have to wait, in the worst 
case until each of 7 other devices are serviced at most 
once. For example, if the priority and "in service" status 
is: 

Before Rotate (IR4 the highest priority requiring service) 



IS7 


IS6 ISS 


IS4 IS3 IS2 IS1 ISO 


l» 


,|o 


1 | 0 | 0 | 0 | 0 | 


Low* 


•t Priority 


Highost Priority 




'.|. 


4 | 3 | 2 | 1 fo | 



After Rotate (IR4 was serviced, ail other priorities 
rotated correspondingly) 



IS7 IS6 IS5 IS4 IS3 IS2 IS1 ISO 



Priority Status 



Highest Priority 

i „ i 



Lowest Priority 



There are two ways to accomplish Automatic Rotation 
using OCW2, the Rotation on Non-Specific EOI Command 
(R = 1 , SL = 0, EOI = 1) and the Rotate in Automatic EOI 
Mode which is set by (R = 1 , SL = 0, EOI = 0) and cleared 
by (R = 0, SL = 0, EOI = 0). 

SPECIFIC ROTATION 
(Specific Priority) 

The programmer can change priorities by programming 
the bottom priority and thus fixing all other priorities; 
i.e., if IR5 is programmed as the bottom priority device, 
then IR6 will have the highest one. 

The Set Priority command is issued in OCW2 where: 
R = 1 , SL = 1 ; LO-L2 is the binary priority level code of the 
bottom priority device. 

Observe that in this mode internal status is updated by 
software control during OCW2. However, it is independent 
of the End of Interrupt (EOI) command (also executed by 
OCW2). Priority changes can be executed during an EOI 
command by using the Rotate on Specific EOI command 
in OCW2 (R = 1, SL = 1, EOI = 1 and LO-L2 = IR level to 
receive bottom priority). 

INTERRUPT MASKS 

Each Interrupt Request input can be masked individu- 
ally by the Interrupt Mask Register (IMR) programmed 
through OCW1. Each bit in the IMR masks one interrupt 
channel if it is set (1). Bit 0 masks IRO, Bit 1 masks IR1 
and so forth. Masking an IR channel does not affect the 
other channels operation. 



2-1Q0 



AFN-00221E 



8259A/8259A-2/8259A-8 



SPECIAL MASK MODE 

Some applications may require an interrupt service 
routine to dynamically alter the system priority struc- 
ture during its execution under software control. For 
example, the routine may wish to inhibit lower priority 
requests for a portion of its execution but enable some 
of them for another portion. 

The difficulty here is that if an Interrupt Request is 
acknowledged and an End of Interrupt command did not 
reset its IS bit (i.e., while executing a service routine), 
the 8259A would have inhibited all lower priority 
requests with no easy way for the routine to enable 
them 

That is where the Special Mask Mode comes in. In the 
special Mask Mode, when a mask bit is set in OCW1, it 
inhibits further interrupts at that level and enables inter- 
rupts from all other levels (lower as well as higher) that 
are not masked. 

Thus, any interrupts may be selectively enabled by 
loading the mask register. 

The special Mask Mode is set by OCW3 where: 
SSMM=1, SMM=1, and cleared where SSMM = 1, 
SMM = 0. 



POLL COMMAND 

In this mode the INT output is not used or the micropro- 
cessor internal Interrupt Enable flip-flop is reset, disabling 
its interrupt input. Service to devices is achieved by 
software using a Poll command. 

The Poll command is issued by setting P= "1" in OCW3. 
The 8259A treats the next pulse to the 8259A (i.e., 
R5 = 0, C5 = 0) as an interrupt acknowledge, sets the 
appropriate IS bit if there is a request, and reads the 
priority level. Interrupt is frozen from Wft to 

The word enabled onto the data bus during RE is: 

07 D6 PS 04 D3 02 01 DO 

| I - - - - W2 W1 WO | 

W0-W2: Binary code of the highest priority level 
requesting service. 
I: Equal to a "1" if there is an interrupt. 

This mode is useful if there is a r outine command com- 
mon to several levels so that the INTA sequence is not 
needed (saves ROM space). Another application is to 
use the poll mode to expand the number of priority 
levels to more than 64. 



LTIM BIT 
0=EOGE 
1 ~ LEVEL 



TO OTHER PRIORTY CELLS 



- CLR II 

- ISR Bl 



MCS-80, 85 
MODE ' 



IAPX86 
MODE 




■3 



SET 



PRIORITY 
RESOLVER 

\ CON 



INTERNAL 
* DATA BUS 



*99 



NOTES 

1 MASTER CLEAR ACTIVE ONLY DURING ICW1 

2 FREEZE/ IS ACTIVE DURING INTA/ AND POLL SEQUENCES ONLY 

3 TRUTH TABLE FOR D LATCH 

CIO I 0 I OPERATION 



Figure 9. Priority Cell — Simplified Logic Diagram * 

2_f31 AFN-00221E 



8259A/8259A-2/8259A-8 



READING THE 8259A STATUS 

The in put status of several internal registers can be read to 
update the user information on the system. The following 
registers can be read via OCW3 (IRR and ISR or OCW1 
[IMRJ). 

Interrupt Request Register (IRR): 8-bit register which con- 
tains the levels requesting an interrupt to be acknowl- 
edged. The highest request level is reset from the IRR 
when an interrupt is acknowledged. (Not affected by IMR.) 

In-Service Register (ISR): 8-bit register which contains the 
priority levels that are being serviced. The ISR is updated 
when an End of Interrupt Command is issued. 

Interrupt Mask Register: 8-bit register which contains the 
interrupt request lines which are masked. 

The IRR can be read when, prior to the RD pulse, a Read 
Register Command is issued with OCW3 (RR = 1 , RIS = 0.) 

The ISR can be read when, prior to the RD pulse, a Read 
Register Command is issued with OCW3 (RR = 1 , RIS = 1 ). 

There is no need to write an OCW3 before every status 
read operation, as long as the status read corresponds 
with the previous one; i.e., the 8259A "remembers" 
whether the IRR or ISR has been previously selected by 
the OCW3. This is not true when poll is used. 

After initialization the 8259A is set to IRR. 

For reading the IMR, no OCW3 is needed. The output data 
bus will contain the IMR whenever RD is active and AO = 1 
(OCW1). 

Polling overrides status read when P = 1, RR = 1 in OCW3. 



EDGE AND LEVEL TRIGGERED MODES 

This mode is programmed using bit 3 in ICW1. 

If LTIM = '0\ an interrupt request will be recognized by a 
low to high transition on an IR input. The IR input can re- 
main high without generating another interrupt. 

If LTIM = '1', an interrupt request will be recognized by a 
'high' level on IR Input, and there is no need for an edge 
detection. The interrupt request must be removed before 
the EOI command is issued or the CPU interrupt is enabled 
to prevent a second interrupt from occurring. 

The priority cell diagram shows a conceptual circuit of the 
level sensitive and edge sensitive input circuitry of the 
8259A. Be sure to note that the request latch is a transpar- 
ent D type latch. 

In both the edge and level triggered modes the IR inputs 
must remain high until after the falling edge of the first 
INTA. If the IR input goes low before this time a DEFAULT 
IR7 will occur when the CPU acknowledges the interrupt. 
This can be a useful safeguard for detecting interrupts 
caused by spurious noise glitches on the IR inputs. To im- 
plement this feature the IR7 routine is used for "clean up" 
simply executing a return instruction, thus ignoring the 
interrupt. If IR7 is needed for other purposes a default IR7 
can still be detected by reading the ISR. A normal IR7 
interrupt will set the corresponding ISR bit, a default IR7 
won't. If a default IR7 routine occurs during a normal IR7 
routine, however, the ISR will remain set. In this case it is 
necessary to keep track of whether or not the IR7 routine 
was previously entered. If another IR7 occurs it is a 
default. 



J K 



/ 




8086/8088 



EARLIEST IR 
CAN BE REMOVED 



EDGE TRIGGERED MODE ONLY 



Figure 10. IR Triggering Timing Requirements 

2-132 



AFN-00221E 



intel 



8259A/8259A-2/8259A-8 



THE SPECIAL FULLY NESTED MODE 

This mode will be used in the case of a big system 
where cascading is used, and the priority has to be con- 
served within each slave. In this case the fully nested 
mode will be programmed to the master (using ICW4). 
This mode is similar to the normal nested mode with the 
following exceptions: 

a. When an interrupt request from a certain slave is in 
service this slave is not locked out from the master's 
priority logic and further interrupt requests from 
higher priority IR's within the slave will be recognized 
by the master and will initiate interrupts to the proc- 
essor. (In the normal nested mode a slave is masked 
out when its request is in service and no higher 
requests from the same slave can be serviced.) 

b. When exiting the Interrupt Service routine the soft- 
ware has to check whether the interrupt serviced was 
the only one from that slave. This is done by sending 
a non-specific End of interrupt (EOI) command to the 
slave and then reading its In-Service register and 
checking for zero. If it is empty, a non-specific EOI 
can be sent to the master too. If not, no EOI should be 
sent. 

BUFFERED MODE 

When the 8259A is used in a large system where bus 
driving buffers are required on the data bus and the cas- 
cading mode is used, there exists the problem of enabl- 
ing buffers. 

The buffered mode will structure the 8259A to send an 
enable signal on SP/EN to enable the buffers. In this 



mode, whenever the 8259A's data bus outputs are ena- 
bled, the SP/EN output becomes active. 

This modification forces the use of software program- 
ming to determine whether the 8259A is a master or a 
slave. Bit 3 in ICW4 programs the buffered mode, and bit 
2 in ICW4 determines whether it is a master or a slave. 

CASCADE MODE 

The 8259A can be easily interconnected in a system of one 
master with up to eight slaves to handle up to 64 priority 
levels. 

The master controls the slaves through the 3 line cascade 
bus. The c ascad e bus acts like chip selects to the slaves 
during the INTA sequence. 

In a cascade configuration, the slave interrupt outputs are 
connected to the master interrupt request inputs. When a 
slave request line is activated and afterwards acknowl- 
edged, the master will enable the corresponding slave to 
release the device routine address during bytes 2 and 3 of 
INTA. (Byte 2 only for 8086/8088). 

The cascade bus lines are normally low and will contain 
the slave address code from the trailing edge of the first 
INTA pulse to the trailing edge of the third pulse. Each 
8259A in the system must follow a separate initialization 
sequence and can be programmed to work in a different 
mode. An EOI command must be issued twice: once for 
the master and once for the corresponding slave. An 
address decoder is required to activate the Chip Select 
(CS) input of each 8259A. 

The cascade lines of the Master 8259A are activated only 
for slave inputs, non slave inputs leave the cascade line 
inactive (low). 



ADDRESS BUS (16) 



CONTROL BUS 



7S 



DATA BUS (8) 



CS A,, D0-7 INTA 



8259A 
SLAVE A 



CASO 
CAS 1 



CAS 2 

SP/EN 7 6 5 4 3 2 1 0 



7 6 5 4 3 2 1 0 



7X 



V 1 V 



CS A 0 



8259A 
SLAVE B 



IN r 
CASO 

CAS 1 

CAS 2 



SP~/EN7 6 5 4 3 2 1 



7 6 5 4 3 2 1 0 



INTERRUPT REQUESTS 



CS A 0 DO-7 INTA ' 
CASO 

•8259A 

CAS1 MASTER 
CAS 2 

SP/EN M7 M6 M5 M4 M3 M2 Ml MO 



3,2 1 0 



Figure 11. Cascading the 8259A 

2-133 



AFN-00221E 



8259A/8259A-2/8259A.8 



ABSOLUTE MAXIMUM RATINGS* 

Ambient Temperature Under Bias 0°C to 70°C 

Storage Temperature -65°C to + 150°C 

Voltage on Any Pin 

with Respect to Ground . . i -0.5V to +7V 

Power Dissipation 1 Watt 



*NOTICE: Stressed above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. 



D.C. CHARACTERISTICS [T A « 0°C to 70°C, V C c = 5V ±5% (8259A-8), V cc =» 5V ±10% (8259A, 8259A-2)] 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 




V| H 


Input High Voltage 


2.0* 


V C c +05V 


V 




Vol 


Output Low Voltage 




0.45 


V 


Iol - 2.2mA 


V 0 H 


Output High Voltage 


2.4 




V 


lOH = -400/u.A 


v OH(INT) 


Interrupt Output High 
Voltage 


3.5 




V 


<OH = -100/uA 


2.4 




V 


lOH = -400/wA 


«LI 


Input Load Current 


-10 


+10 


fiA 


ov ^V, N ^v C c 


'lol 


Output Leakage Current 


-10 


+10 


fiA 


0.45V ssVqut^ v cc 


f cc 


Vcc Supply Current 




85 


mA 




'lir 


IR Input Load Current 




-300 


fiA 


V| N = 0 




10 


fiA 


V|N = V CC 



*Note: For Extended Temperature EXPRESS V IH = 2.3V. 

CAPACITANCE (T A = 25°c ; v cc - gnd = ov) 



Symbol 


Parameter 


Min. 


Typ. 


Max. 


Unit 


Test Conditions 




Input Capacitance 






10 


PF 


fc = 1 MHZ 


C|/0 


I/O Capacitance 






20 


PF 


Unmeasured pins returned to V ss 



A.C. CHARACTERISTICS [T A = 0°C to 70°C, V C c = 5V ±5% (8259 A-8), V C c = 5V ± 10% (8259A, 8259 A-2)] 
TIMING REQUIREMENTS 



Symbol 


Parameter 


8259A-8 


8259A 


8259A-2 


Units 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


TAHRL 


AO/CS Setup to RD/INTAi 


50 




0 




0 




ns 




TRHAX 


AO/CS Hold after RO/lRTA| 


5 




0 




0 




ns 




TRLRH 


RD Pulse Width 


420 




235 




160 




ns 




TAHWL 


AO/CS Setup to WR| 


50 




0 




0 




ns 




TWHAX 


AO/CS Hold after WR| 


20 




0 




0 




ns 




TWLWH 


WR Pulse Width 


400 




290 




190 




ns 




TDVWH 


Data Setup to WRf 


300 




240 




160 




ns 




TWHDX 


Data Hold after WRf 


40 




0 




0 




ns 




TJLJH 


Interrupt Request Width (Low) 


100 




100 




100 




ns 


See Note 1 


TCVIAL 


Cascade Setup to Second or Third 
INTA1 (Slave Only) 


i 

55 




55 




40 




ns 




TRHRL 


End of RD to next RD 

End of INTA to next INTA within 

an INTA sequence only 


160 




160 




160 




ns 




TWHWL 


End ofWRto nextWR 


190 




190 




190 




ns 





2-134 



AFN-00221E 



8259A/8259A-2/8259A-8 



A.C. CHARACTERISTICS (Continued) 



Symbol 


Parameter 


8259A-8 


8259A 


8259A-2 


Units 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


*TCHCL 


End of Command to next Command 
(Not same command type) 

End of INTA sequence to next 
INTA sequence. 


500 




500 




500 




- ns 





* Worst case timing forTCHCL in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085A = 1.6/us, 
8085 A-2 = 1 ixs, 8086 = 1/xS, 8086-2 = 625 ns) 

NOTE: This is the low time required to clear the input latch in the edge triggered mode. 



TIMING RESPONSES 



Symbol 


Parameter 


8259A-8 


8259A 


8259A-2 


Units 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


TRLDV 


Data Valid from RD/INTA| 




300 




200 




120 


ns 


C of Data Bus = 
100 pF 

C of Data Bus 

Max text C = 100 pF 

Mm. test C = 15 pF 

Cint = 100 pF 
c cascade - 100 pF 


TRHDZ 


Data Float after RD/ INTAj 


10 


200 


10 


100 


10 


85 


ns 


TJHIH 


Interrupt Output Delay 




400 




350 




300 


ns 


TIALCV 


Cascade Valid from First INTAj 
(Master Only) 




565 




565 




360 


ns 


TRLEL 


Enable Active from RDj or INTAj 




160 




125 




100 


ns 


TRHEH 


Enable Inactive from RDj or INTA] 




325 




150 




150 


ns 


TAHDV 


Data Valid from Stable Address 




350 




200 




200 


ns 


TCVDV 


Cascade Valid to Valid Data 




300 




300 




200 


ns 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



INPUT/OUTPUT 




^> TEST POINTS <^ 




A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR 
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1 
AND 0 8V FOR A LOGIC 0 " 



A.C. TESTING LOAD CIRCUIT 



DEVICE 
UNDER 
TEST 



I 



C L = 100 pF 

C L INCLUDES JIG CAPACITANCE 



WAVEFORMS 



WRITE 



t 



7 



, ADDRESS BUS 



X 



X 



X 



X 



2^135 



AFN-00221E 




8259A/8259A-2/8259A-8 



WAVEFORMS (Continued) 

READ/INTA 




OTHER TIMING 




2-136 



AFN-00221E 



8259A/8259A-2/8259A-8 



WAVEFORMS (Continued) 



INTA SEQUENCE _ 

J 



INT - 
INTA- 



OB- 



TCVIAL 



A 



NOTES: Interrupt output must remain HIGH at least until leading edge of first INTA. 
1 . CVcle 1 in iAPX 86, iAPX 88 systems, the Data Bus is not active. 



2-137 



AFN-00221E 



8355/8355-2 
16,384- BIT ROM WITH I/O 



■ 2048 Words x 8 Bits ■ Each I/O Port Line Individually 

Programmable as Input or Output 

■ Single + 5V Power Supply 

■ Multiplexed Address and Data Bus 

■ Directly Compatible with 8085A 

and iAPX 88 Microprocessors ■ Internal Address Latch 

■ 2 General Purpose 8-Bit I/O Ports ■ 40-Pin DIP 

The Intel® 8355 Is a ROM and I/O chip to be used in the 8085A and iAPX 88 microprocessor systems. The ROM portion is 
organized as 2048 words by 8 bits. It has a maximum access time of 450 ns to permit use with no wait states in the 8085A 
CPU. 

The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 lines and each I/O port line is individually pro- 
grammable as input or output. 

The 8355-2 has a 300 ns access time for compatibility with the 8085A-2 and 5 MHz iAPX 88 microprocessors. 



CEi~ 
IO/M- 
ALE- 
RD- 

iow- 

RESET- 
iOR- 



2KX 8 
ROM 



<5> 



rn 



V cc (+5V) 
V ss (0V) 



Figure 1. Block Diagram 



CE,C 


1 


^ 40 


=» V CC 


CE 2 C 


2 


39 


Dpb 7 


clkC 


3 


38 


>B 6 


RESET C 


4 


37 


3pb 5 


N C (NOT CONNECTED)* C 


5 


36 


1PB 4 


READY C 


6 


35 


JPB 3 


io/mC 




34 


2PB 2 


JOR C 


8 


33 


Dpb, 


RDC 


9 8355/8355-2 32 


□ pb 0 


iowC 


10 


31 


3pa 7 


aleC 


11 


30 


□ pa 6 


AD 0 C 


12 


29 


□ pa 5 


AD^ 


13 


28 


Dpa 4 


AD 2 C 


14 


27 


Dpa 3 


AD 3 C 


15 


26 


>A 2 


AD 4 C 


16 


25 


□ pa. 


AD 5 C 


17 


24 


hpa 0 


AD eC 


18 


23 


Da 10 


°°AD 7 C 


19 


22 


□ a 9 


v ssC 


20 


21 


3a 8 



*For 8755A compatibility, pi.n 5 should be directly tied to VCC> 



Figure 2. Pin Configuration 



> 2-138 



AFN-00234D - 



8355/8355-2 



Table 1. Pin Description 



Symbol 


Type 


Name and Function 


ALE 


I 


AddressLatch Enable: When high, AD0-7, IO/M, As— 10, CE2, and CE~i enter the address latches. The signals 
(AD, l/OM, Ae-10, CE 2 , CE1) are latched in at the trailing edge of ALE. 


AD 0 _7 


I 


Address/Data Bus (Bidirectional): The lower 8-bits of the ROM or I/O address are applied to the bus lines when 
ALE is high. During an I/O cycle, Port A or B is selected based on the latched value of AD 0 . If RD or IOR is low when 
the latched chip enables are active, the output buffers present data on the bus. 


A8-10 


I 


Address Bus: High order bits of the ROM address. They do not affect I/O operations. 


CE 2 


I 


Chip Enable Inputs: CE1 is active low and CE2 is active high. The 8355 can be accessed only when BOTH Chip 
Enables are active at the time the ALE signal latches them up. If either Chip Enable input is not active, the 
A Do— 7 and READY outputs will be in a high impedance state. 


IO/M 


I 


I/O Memory: If the latched IO/M is high when RD is low, the output data comes from an I/O port. If it is low, the out- 
put data comes from the ROM, 


RD 




Read: If the latched Chip Enables are active when RD goes low, the AD0-7 output buffers are enabled and output 
either the selected ROM location or I/O port. When both RD and IOR are high, the AD0-7 output buffers are 3-stated. 


IOW 


i 


I/O Write: If the latched Chip Enables are active, a low on IOW causes the output port pointed to by the latched 
value of ADo to be written with the data on AD0-7. The state of IO/M is ignored. 


CLK 


I 


Clock: Used to force the READY into its high impedance state after it has been forced low by CE1 low, CE 2 high 

and Al F hinh 


READY 


0 


READY: A 3-state output controlled by CE~i , CE 2 , ALE and CLK. READY is forced low when the Chip Enables are 
active during the time ALE is high, and remains low until the rising edge of the next CLK. 


PAo-7 


I/O 


Port A: General purpose I/O pins. Their input/output direction is determined by the contents of Data Direction 
negisier ^uunj. non m is selected ior wrue operations wnen ine onip cnaijies are acuve anu hjvv is iuw anu a 
0 was previously latched from ADo, ADi. 

Read operation is selected by either IOR low and active Chip Enables and ADo and ADi low, or IO/M high, RD 
low, active chip enables, and AD 0 and AD^ LOW. 


PBo-7 


I/O. 


Port B: This general purpose I/O port is identical to Port A except that it is selected by a 1 latched from ADo 
and a 0 from ADi. 


RESET 




Reset: An input high causes ail pins in Port A and B to assume input mode. (Clear DER Register). 


IOR 


I 


I/O Read: When the Chip Enables are active, a low on IOR will output the selected I/O port onto the AD bus. IOR low 
performs the same function as the combination IO/M high and RD low. When IOR is not used in a system, IOR 
should be tied to Vcc (""•")• 


v C c 




Voltage: +5 volt supply. 


v S s 




Ground: Ground Reference. * 



2-139 



AFN-00234D 



irrteT 



8355/8355-2 



FUNCTIONAL DESCRIPTION 
ROM Section 

The 8355 contains an 8-bit address latch which allows it 
to interface directly to MCS-48, MCS-85, and iAPX 88/10 
Microcomputers without additional hardware. 

The ROM section of the chip Ts addressed by an 11-bit 
address and the Chip Enables. The address and levels on 
the Qhip Enable pins are latched into the address latches 
on the falling edge of ALE. If the latched Chip Enables 
are active and IO/M is low when RD goes low, the contents 
of the ROM location addressed by the latched address 
are put but through AD0-7 output buffers. 

I/O Section 

The I/O section of the chip is addressed by the latched 
value of ADo-1. Two 8-bit Data Direction Registers (DDR ( ) 
in 8355 determine the input/output status of each pin in 
the corresponding ports. A "0" in a particular bit position 
of a DDR signifies that the corresponding I/O port bit is 
in the input mode. A "1" in a particular bit position signi- 
fies that the corresponding I/O port bit is in the output 
mode. In this manner the I/O ports of the 8355 are bit-by- 
bit programmable as inputs or outputs. The table sum- 
marizes port and DDR designation. DDR's cannot be 
read. 



ADi 


ADo 


Selection 


0 


0 


Port A 


0 


1 


Port B 


1 


0 


Port A Data Direction Register (DDR A) 


1 


1 


Port B Data Direction Register (DDR B) 



When IOW goes low and the Chip Enables are active, the 
data on the ADo-7 is written into I/O port selected by the 
latched value of ADo-1 During this operation all I/O bits 
of the selected port are affected, regardless of their I/O 
mode and the sta te of IO/M The actual output level does 
not change until IOW returns high (glitch free output). 

A port can be read out when the latched Chip Enables are 
active and either RD goes low with IO/M high, or IOR 
goes low. Both input and output mode bits of a selected 
port will appear on lines AD0-7. 

To clarify the function of the I/O ports and Data Direction 
Registers, the following diagram shows the configurat'on 
of one bit of PORT A and DDR A. The same logic applies 
to PORT B and DDR B 

Note that hardware RESET or writing a zero to the DDR 
latch will cause the output latch's output buffer to be 
disabled, preventing the data in the output latch from 
being passed through to the pin. This is equivalent to 
putting the port in the input mode. Note also that the data 
can be written to the Output Latch even though the Out- 
put Buffer has been disabled. This enables a port to be 
initialized with a value prior to enabling the output. 

The diagram also shows that the contents of PORT A and 
PORT B can be read even when the ports are configured 
as outputs. 



ONE BIT OF PORT A AND DDR A 



OUTPUT 
ENABLE 



DDR 
LATCH 



CLR CLK 



-a 



READ PA 

WRITE PA = (iOW=0) • (CHIP ENABLES ACTIVE) • (PORT A ADDRESS SELECTED) 

WRITE DDR A = (IOW=0) •JCHIP ENABLES ACTIVE) • (DDR A A00RESS SELECTED) 

READ PA = { [(I0/M=1) • (RD=0)] + (IOR=0)} • (CHIP ENABLES ACTIVE) • (PORT A ADDRESS SELECTED) 

NOTE WRITE PA IS NOT QUALIFIED BY 10/M 



Figure 3. 8355 One Bit of Port A and DDR A 
SYSTEM APPLICATIONS 
System Interface with 8085A and iAPX 88 

A system using the 8355 can use either one of the two 
I/O Interface techniques. 

• Standard I/O 

• Memory Mapped I/O 

If a standard I/O technique is used, the system can use 
the feature of both CE 2 and CE^ By using a combina- 
tion of unused address lines An-15 and the Chip 
Enable inputs, the system can use up to 5 each 8355' s 
without requiring a CE decoder. See Figure 5a and 5b. 

If a memory mapped I/O approach is used the 8355 will 
be selected by the combination of both the Chip En- 
ables and IO/M using AD 8 _ 15 address lines. See Figure 
4. 



<5 




,D 0-7 A 8-10 RD CLK « I0/M_ 
ALE iOW READY CE 



Figure 4. 8355 in 8085A System 
(Memory-Mapped I/O) 



2-140 



AFN-00234D 



8355/8355-2 



iAPX 88 FIVE CHIP SYSTEM: 



• 1.25 K Bytes RAM 

• 2 K Bytes ROM 

• 38 I/O Pins 

• 1 Internal Timer 

• 2 Interrupt Levels 




CLK 
READY 



8284A 

RESET 



MN/MX 
ALE 



WR 
IO/M 



GND 

(Vss) 



MANUAL 
RESET 



-6 6- 



c 



V \7 



Vss v cc 



CE 


PORT 


WR 

PORT 
RD B 
8155-2 


ALE 


PORT 


DATA/ 




ADDR 


IN 


IO/M" 


TIMER 


RESET 


OUT 



IOW 




RD 




ALE 




CE 


POR I 


A 8-10 




8355-2 


DATA/ 




ADDR 




IO/M 


PORT 


RESET 




READY 


IOR 



1<A> 



TIL 



v S s v cc v DD 



-N 
V 



WR 

RD 

CE~i 

811 

ALE 

CS, 
CE 2 
A 8 , A 9 

AD 0 _ 7 



V SS Vcc 



Figure 5a. iAPX 88 Five Chip System Configuration 



2-141 



AFN-00234D 



RD CLK 10/M 
ALE IOW READY CE 2 
8355 
(2K BYTES) 



A/D o-7 A 8-10 RD CLK 10/M 

ALE IOW READY CE, 
8355 
(2K BYTES) 



A/D 0-7 A »-1Q R° CLK 10/M 
1 ALE iOW READY CE, 



(2K BYTES) 



A/Dp. 7 A W8 RD CLK IO/K 

ALE iOW READY CE 2 
8355 

(2K BYTES) 



RD CLK IO/H 
ALE IOW READY CE 2 



(2K BYTES) 



NOTE: Use CE^ for the first 8355 in the system, and CE2 for the other 8355's. Permits up to 5-8355's in a system without CE decoder. 



Figure 5b. 8355 in 8085A System (Standard I/O) 



irrtel 



8355/8355-2 



ABSOLUTE MAXIMUM RATINGS 4 



Temperature Under Bias 0°Cto+70°C 

Storage Temperature -65° C to +150° C 

Voltage on Any Pin 

With Respect to Ground -0.5V to +7V 

Power Dissipation 1.5W 

D.C. CH ARACTERISTICS (t a = o°c to 70°c ; v cc = 5V ± 5%) 



'NOTICE: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



Symbol 


Parameter 


Min. 


Max. 


Unit 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 


V CC = 5.0V 


V| H 


Input High Voltage 


2.0 


Vcc+0.5 


V 


V CC = 5.0V 


Vol 


Output Low Voitage 




0.45 


V 


Iol = 2mA 


Voh 


Output High Voltage 


2.4 




V 


Iqh = -400mA 


IlL 


Input Leakage 




10 


ma 


0V ^ V IN ^ V cc 


Ilo 


Output Leakage Current 




±10 


ma 


0.45V <V 0U T <V CC 


•cc 


Vcc Supply Current 




180 


mA 





A.C. CHARACTERISTICS (T A = o°cto 70°c ; v cc = 5V ± 5%) 



Symbol 


Parameter 


8355 


8355-2 




Min. 


Max. 


Min. 


Max. 


Units 


tCYC 


Clock Cycle Time 


320 




200 




ns 


Ti 


CLK Pulse Width 


80 




40 




ns 


T 2 


CLK Pulse Width 


120 




70 




ns 


tf.tr 


CLK Rise and Fall Time 




30 




30 


ns 


tAL , 


Address to Latch Set Up Time 


50 




30 




ns 


t|_A 


Address Hold Time after Latch 


80 




45 




ns 


tLC 


Latch to READ/WRITE Control 


100 




40 




ns 


tRD 


Valid Data Out Delay from READ Control* 




170 




140 


ns 


tAD 


Address Stable to Data Out Valid** 




450 




300 


ns 


tLL 


Latch Enable Width 


100 




70 




ns 


tRDF 


Data Bus Float after READ 


0 


100 


0 


85 


ns 


tCL 


READ/WRITE Control to Latch Enable 


20 




10 




ns 


tec 


READ/WRITE Control Width 


250 




200 




ns 


tDW 


Data In to Write Set Up Time 


150 




150 




ns 


tWD 


Data In Hold Time After WRITE 


30 




10 




ns 


tWP 


WRITE to Port Output 




400 




300 


ns 


tPR 


Port Input Set Up Time 


50 




50 




ns 


tRP 


Port Input Hold Time 


So 




50 




ns 


tRYH 


READY HOLD Time 


0 


160 


0 


160 


ns 


tARY 


ADDRESS (CE) to READY 




160 




160 


ns 


tRV 


Recovery Time Between Controls 


300 




200 




ns 


tRDE 


READ Control to Data Bus Enable 


10 




10 




ns 



*Or Tad-(Tal + T|_c), whichever is greater. 

** Defines ALE to Data out Valid in conjunction with TaL- 



2-143 



AFN-00234D 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



A.C. TESTING LOAD CIRCUIT 



INPUT/OUTPUT 



^> TEST POINTS <^ 



A C TESTING INPUTS ARE DRIVEN AT 2 4 V FOR A LOGIC T' AND 0 45V FOR 
A LOGIC "0 " TIMING MEASUREMENTS ARE MADE AT 2 0V FOR A LOGIC 1 " 
AND 0 8V FOR A LOGIC "0 " 



WAVEFORMS 



DEVICE 
UNDER 
TEST 



I 



C L = 150 pF 



C = 150 pF 

C L INCLUDES JIG CAPACITANCE 



ROM READ AND I/O READ AND WRITE 



A 8-1_0 \/ 
IO/M fi v 



(CE^O -CE 2 = 1) 



J 



X 



x 



X 



\_ / \ / V J V 



* Please note that for 8755A compatibility, CEi should remain low for the entire read cycle. 



|* T 2 - 



XI 



) G 



J 



I 




2-144 



AFN-00234D 



8355/8355-2 



WAVEFORMS (Continued) 



INPUT MODE 



OUTPUT MODE 



RD OR 

ion 



PORT 
INPUT 



3: 



X 



DATA 
BUS 



:::::::x 



\ 



PORT 
OUTPUT 



::::::::::::x 



GLITCH FREE 
' OUTPUT 



DATA* 
BUS 



:::::x 



x 



*DATA BUS TIMING IS SHOWN IN FIGURE 4. 





~> 



f- V 



- *RYH 



NOTE: Ready = 0. 



2-145 



AFN-00234D 



8755A/8755A-2 
16, 384- BIT EPROM WITH I/O 



2048 Words x 8 Bits 

Single + 5V Power Supply (V cc ) 

Directly Compatible with 8085 A 
and 8088 Microprocessors 

U.V. Erasable and Electrically 
Reprogrammable 

Internal Address Latch 



■ 2 General Purpose 8-Bit I/O Ports 

■ Each I/O Port Line Individually 
Programmable as Input or Output 

■ Multiplexed Address and Data Bus 

■ 40-Pin DIP 

■ Available in EXPRESS 

- Standard Temperature Range 

- Extended Temperature Range 



The Intel® 8755A is an erasable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the 8085A and 
iAPX 88 microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum access 
time of 450 ns to permit use with no wait states in an 8085A CPU. 

The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and each I/O port line is individually 
programmable as input or output. 

The 8755A-2 is a high speed selected version of the 8755A compatible with the 5 MHz 8085A-2 and the 5 MHz iAPX 88 
microprocessor. 



READY 



A 8~10 ? ""^ 



CE 2 - 
IO/M- 
ALE- 
RD- 

ioW- 

RESET- 
iOR- 



1 



2Kx8 
EPROM 



3 



y lPORTAK 

yi P0RTB K 



•V cc (+5V) 
Vcc (0V) 



PROG AND CE-) £ 


1 


40 


3V CC 


CE 2 C 


2 


39, 


]PB 7 


CLK C 


3 


38 


DP B 6 


RESET C 


4 


37 


DPBb 




5 


36 


I]PB 4 


READY C 


6 


35 




IO/M C 


7 


, 34 


JPB 2 


ioR C 


8 


33 


D PB i 


rdC 


9 


32 


□ PBo 


iow C 


10 , 


8755A/ 31 


□ PA 7 


aleC 


11 


8755A-2 30 


□ PA 6 




12 


29 


□ PA 5 


AD lC 


13 


28 


□ PA 4 


ad 2 c 


14 


27 


□ PA 3 


AD 3 C 


15 


26 


□ p A 2 


AD 4 C 


16 


25 


D PA i 


AD 5 C 


17 


24 


3 PA o 




18 


23 


□ A 10 


AD 7 C 


19 


22 


□ A 9 


v ss q 


20 


21 


D A 8 



Figure 1. Block Diagram 



Figure 2. Pin Configuration 



Intel Corporation Assumes No Responsibly for the, Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other Circuit Patent Licenses are Implied 
©INTEL CORPORATION, 1980 



2-146 



8755A/8755A-2 



Table 1. Pin Description 



Symbol 


Type 


Name and Function 


ALE 




Address Latch Enable: When Address 
Latch Enable goes high, AD 0 ~7, IO/M, 
Ae-io, CE 2) and CE-i enter the address 
latches. The signals (AD, IO/M AD 8 _io, 
CE 2 , CE1) are latched in at the trailing 
edge of ALE. 


AD0-7 


1 


Bidirectional Address/Data Bus: The 

lower 8-bits of the PROM or I/O address 
are applied to the bus lines when ALE is 
high. 

During an I/O cycle, Port A or B is 
selected based on the latched value of 
AD 0 . IF RD or IOR is low when the latched 
Chip Enables are active, the output buf- 
fers present data on the bus. 


A3— *io 


1 


Address Bus: These are the high order 
bits of the PROM address. They do not 
affect I/O operations. 


PROG/CE^ 
CE2 


1 


Chip Enable Inputs: CE-| is active low 
and CE2 is active high. The 8755A can be 
accessed only when both Chip Enables 
are active at the time the ALE signal 
latches them up. If either Chip Enable 
input is not active, the AD0-7 and 
READY outputs will be in a high impe- 
dance state.CEi is also used as a pro- 
gramming pin. (See section on 
programming.) 


IO/M 


■ 


I/O Memory: If the latched IO/M is high 
when RD is low, the output data comes 
from an I/O port. If it is low the output 
data comes from the PROM. 


RD 


1 


Read: If the latched Chip Enables are 
active when RD goes low, the AD0-7 
output buffers are enabled and output 
either the selected PROM location or I/O 
port. When both RD and IOR are high, 
the AD 0 -7 output buffers are 3-stated. 


IOW 


1 


I/O Write: If the latched Chip Enables are 
active, a low on IOW causes the output 
port pointed to by the latched value of 
ADq to be writtenwith the data on AD0-7. 
The state of IO/M is ignored. 


CLK 


l 


Clock: The CLK is used to force the 
READY into its high impedance state 
after it has been forced low by CE-| low, 
CE 2 high, and ALE high. 



Symbol 


Type 


Name and Function 


READY 


0 


Ready is a 3-state output controlled by 
eEi, CE 2 , ALE and CLK. READY is forc- 
ed low when the Chip Enables are active 
during the time ALE is high, and re- 
mains low until the rising edge of the 
next LrLK. (oee rigure oc; 


PA0-7 


I/O 


Port A: These are general purpose I/O 
pins. Their input/output direction is de- 
termined by the contents of Data Direc- 
tion Register (DDR). Port A is selected for 
write operations when the Chip Enables 
are active and IOW is low and a 0 was 
previously latched from ADo, AD-j . 

Read Operation is selected by either TOR 
low and active Chip Enables and AD 0 
and AD-t low, or IO/M high, RD low, active 
Chip Enables, and ADq and AD-) low. 


PB0-7 


I/O 


Port B: This general purpose I/O port is 
identical to Port A except that it is 
selected by a 1 latched from ADq and a 0 
from AD-| . 


RESET 




Reset: in normal operation, an input 
high on RESET causes all pins in Ports A 
and B to assume input mode (clear DDR 
register). 


IOR 


I 


I/O Read: When the Chip Enables are 
active, a low on IOR will output the 
selected I/O port onto the AD bus. To"R* 
low performs the same function as the 
combination of IO/M high and RD low. 
When IOR is not used in a system, IOR 
should be tied to V C c (""•")• 


v C c 




Power: +5 volt supply. 


v S s 




Ground: Reference. 


V D D 




Power Supply: V DD is a programming 
voltage, and must be tied \Q Ycc when 
the 8755A is being read. 

For programming, a high voltage is 
supplied With Vdd = 25V, typical. (See 
section on programming.) 



2-147 



AFN-00843D 



irrteT 



8755A/8755A-2 



FUNCTIONAL DESCRIPTION 
PROM Section 

The 8755A contains an 8-bit address latch which allows it 
to interface directly to MCS-48, MCS-85 and iAPX 88/10 
Microcomputers without additional hardware. 

The PROM section of the chip is addressed by the 11 -bit 
address and the Chip Enables. The address, CE 1 and 
CE 2 are latched into the address latches on the falling 
edge of ALE. If the latched Chip Enables are active and 
IO/M is low when RO goes low, the contents of the 
PROM location addressed by the latched address are 
put out on the AD 0 _ 7 lines (provided that V DD is tied to 
Vcc-) 

I/O Section 

The I/O section of the chip is addressed by the latched 
value of AD0-1. Two 8-bit Data Direction Registers (DDR) 
in 8755 A determine the input/output status of each pin 
in the corresponding ports. A "0" in a particular bit posi- 
tion of a DDR signifies that the corresponding I/O port bit 
is in the input mode. A "1 " in a particular bit position signi- 
fies that the corresponding I/O port bit is in the output 
mode. In this manner the I/O ports of the 8755A are bit-by- 
bit programmable as inputs or outputs. The table 
summarizes port and DDR designation. DDR's cannot be 
read. 



87S5A 

ONE BIT OF PORT A AND DDR A 



ADi 


ADo 


Selection 


0 


0 


Port A 


0 


1 


Port B 


1 


0 


Port A Data Direction Register (DDR A) 


1 


1 


Port B Data Direction Register (DDR B) 



When IOW goes low and the Chip Enables are active, 
the data on the AD 0 _7 is written into I/O port selected 
by the latched value ofi AD 0 _i. During this operation all 
I/O bits of the selected port are affected, regardless of 
their I/O mode and the stat e of IO/M. The actual output 
level does not change until fOW returns high, (glitch free 
output) 

A port can be read out when the latched Chip E nable s are 
active and either RD goes low withJO/M high, or IOR goes 
low. Both input and output mode bits of a selected port 
will appear on lines ADo-7. 

To clarify the function of the I/O Ports and Data Direction 
Registers, the following diagram shows the configuration ' 
of one bit of PORT A and DDR A. The same logic applies 
to PORT B and DDR B. 



\7 





OUTPUT 
„ LATCH n 
D Q 

CLK 




Do 


— 1 

, , OUTPUT 
ENABLE 


i 

WRITE PA 


DDR 
0 LATCH Q 
CLR CLK 


n 

RESET 

D 0 




t 

WRITE DDR A 

r- 





WRITE PA < (IOW-0) • (CHIP ENABLES ACTIVE) • (PORT A ADDRESS SELECTED) 

WRITE DOR A * (iOW'O) • (CHIP ENABLES ACTIVE) • (ODR A AOORESS SELECTEO) 

REAO PA * { [(IO/ffi-1 ) • (TO-0)] + (IOR*0)} • (CHIP ENABLES ACTIVE) • (PORT A AOORESS SELECTED) 

NOTE: WRITE PA IS NOT QUALIFIED BY 10/M. 



Note that hardware RESET or writing a zero to the DDR 
latch will cause the output latch's output, buffer to be 
disabled, preventing the data in the Output Latch from 
being passed through to the pjn. This is equivalent to 
putting the port in the input mode. Note also that the data 
can be written to the Output Latch even though the Output 
Buffer has been disabled. This enables a port to be ini- 
tialized with a value prior to enabling the output. 

The diagram also shows that the contents of PORT A and 
PORT B can be read even when the ports are configured 
as outputs. 

TABLE 1. 8755A PROGRAMMING MODULE CROSS 
REFERENCE 



MODULE NAME 


USE WITH 


UPP 955 


UPP(4), 


UPP UP2(2) 


UPP 855 


PROMPT 975 ' 


PROMPT 80/85(3) 


PROMPT 475 


PROMPT 48(1) 


NOTES: 




1. Described on p. 13-34 of 1978 Data Catalog. 


2. Special adaptor socket. 


3. Described on p. 13-39 of 1978 Data Catalog. 


4. Described on p. 13-71 of 1978 Data Catalog. 



2*148 



AFN-00843D 



8755A/8755A-2 



ERASURE CHARACTERISTICS 

The erasure characteristics of the 8755A are such that 
erasure begins to occur when exposed to light with 
wavelengths shorter than approximately 4000 Angstroms 
(A). It should be noted that sunlight and certain types of 
fluorescent lamps have wavelengths in the 3000-4000A 
range. Data show that constant exposure to room level 
fluorescent lighting could erase the typical 8755A in 
approximately 3 years while it would take approximately 1 
week to cause erasure when exposed to direct sunlight. 
If the 8755A is to be exposed to these types of lighting 
conditions for extended periods of time, opaque labels 
are available from Intel which should be placed over the 
8755 window to prevent unintentional erasure. 

The recommended erasure procedure for the 8755A is 
exposure to shortwave ultraviolet light which has a wave- 
length of 2537 Angstroms (A). The integrated dose (i.e., 
UV intensity X exposure time) for erasure should be a 
minimum of 15W-sec/cm2. The erasure time with this 
dosage is approximately 15 to 20 minutes using an ultra- 
violet lamp with a 12000>W/cm2 power rating. The 
8755A should be placed within one inch from the lamp 
tubes during erasure. Some lamps have a filter on their 
tubes and this filter should be removed before erasure. 

PROGRAMMING 

Initially, and after each erasure, all bits of the EPROM 
portions of the 8755A are in the "1" state. Information is 
introduced by selectively programming "0" into the 
desired bit locations. A programmed "0" can only be 
changed to a "1" by UV erasure. 

The 8755A can be programmed on the Intel® Universal 
PROM Programmer (UPP), and the PROMPT™ 80/85 and 
PROMPT-48™ design aids. The appropriate programming 
modules and adapters for use in programming both 
8755A's and 8755's are shown in Table 1 . 

The program mode itself consists of programming a 
single address at a time, giving a single 50 msec pulse 
for every address. Generally, it is desirable to have a 
verify cycle after a program cycle for the same address 
as shown in the attached timing diagram. In the verify 
. cycle (i.e., normal memory read cycle) 'N/pp' should 
be at +5V. 

Preliminary timing diagrams and parameter values per- 
taining to the 8755A programming operation are con- 
tained in Figure 7, 



SYSTEM APPLICATIONS 

System Interface with 8085A and iAPX 88 

A system using the 8755A can use either one of the two I/O 
Interface techniques: 

• Standard I/O 

• Memory Mapped I/O 

If a standard I/O technique i s use d, the system can use 
the feature of both CE 2 and CE^ By using a combina- 
tion of unused address lines Ai-,_i 5 and the Chip 
Enable inputs, the 8085A system can use up to 5 each 
8755A's without requiring a CE decoder. See Figure 4a 
and 4b. 

If a memory mapped I/O approach is used the 8755A will 
be selected byjhe combination of both the Chip 
Enables and IO/M using AD 8 _ 15 address lines. See 
Figure 3. 



3 



ivv 



A 8 -10 RD CLK I0/M_ 
ALE I0W READY CE 



Figure 3. 8755A in 8085A System 
(Memory-Mapped I/O) 



2-149 



AFN-00843D 




8755A/8755A-2 



iAPX 88 FIVE CHIP SYSTEM 

Figure 4 shows a five chip system containing: 

• 1.25K Bytes RAM 

• 2K Bytes ROM 

• 38 I/O Pins 

• 1 Interval Timer 

• 2 Interrupt Levels 




T 

GND 

(Vss) 



CLK 
READY 



RES 



8284 
RESET 



A$— A19 



AD 0 -AD, 
CLK 



V 



8088 
READY 

MN/MX- 
ALE 

RST @ RD 
WR 
IO/M 



MANUAL 
RESET 



-c3 ?>- 



c 



C"E 


PORT 
PORT 


WR 


RD .,«-a B 


ALE 


PORT 


DATA/ 




ADDR 


IN 


IO/M 


TIMER 


RESET 


OUT 



iow 

RD 
ALE 

51 



A 8-10 

8355-2/ 
8755A-2 

-N DATA/ 
-j/ ADDR 

IO/M PORT 

RESET 

READY 

IOR 



■MIL, 

Vss Vcc v DD 



WR 
RD 

CE, 

81 C 

ALE 
CS, 
CE 2 
A 8 , A 9 
AD 0 . r 



V SS V C C 



Figure 4a. iAPX 88 Five Chip System Configuration 

2-150 



AFN-00843C 



00 

cn 
> 
CO 



a 
a. 



T<><> 



RD CLK 10/M 
ALE iOW READY CE, 



T V V 



RO CLK 10/M 
ALE IOW READY CE 2 



TV V 



A 13 



RD CLK 10/M 
ALE IOW READY CE 2 



RD CLK 10/fM 
ALE IOW READY CE 



8755A 
(2K BYTES) 



RD CLK 10/M 
ALE IOW READY CE 2 

8755A 
(2K BYTES) 



00 
■>! 

cn 
oo 
cn 
io 



Note: Use CE<j for the first 8755A in the system, and CE2 for the other 8755 A s. Permits up to 5-8755A's in a system without CE decoder. 



int^T 8755A/8755A-2 

ABSOLUTE MAXIMUM RATINGS* W/CE . stresses gbove fhose /fefed under .. Absolutg 

Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating oniy and functional opera- 
Temperature Under Bias 0° C to +70° C tion of the device at these or any other conditions above 

Storage Temperature -65°Cto +150°Q those indicated in the operational sections of this specifi- 

Voltage on Any Pin cation is not implied. Exposure to absolute maximum 

With Respect to Ground -0.5V to +7V rating conditions for extended periods may affect device 

Power Dissipation 1.5W reliability. 



D.C. CHARACTERISTICS (T A = o°c to 70°, v C c = v D d = 5V ± 5%; 

V C c = V DD = 5V ±10% for 8755A-2) 



SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 


V CC = 5.0V 


V,H 


Input High Voltage 


2.0 


Vcc+0.5 


V 


V CC = 5.0V 


Vol 


Output Low Voltage 




0.45 


V 


l 0 L = 2mA 


Voh 


Output High Voltage 


2.4 




V 


Iqh = -400juA 


IlL 


Input Leakage 




10 


ma 


Vss ^ V| N ^ V C c 


Ilo 


Output Leakage Current 




±10 


ma 


0.45V *s V 0U T < V CC 


'cc 


Vqc Supply Current 




180 


mA 




'dd 


Vdd Supply Current 




30 


mA 


Vdd = v cc 


C|N 


Capacitance of Input Buffer 




10 


pF 


f C = VHz 


C|/0 


Capacitance of I/O Buffer 




15 


PF 


f C = 1juHz 



D.C. CHARACTERISTICS— PROGRAMMING (T A = o°cto70°, v C c = 5V ± 5%, v S s = ov, v D d = 25V ±1V; 

Vcc = Vdd = 5V ±10% for 8755A-2) 



Symbol 


Parameter 


Mln. 


Typ. 


Max. 


Unit 


V D p 


Programming Voltage (during Write 
to EPROM) 


24 


25 


26 


V 


Idd 


Prog Supply Current 




15 


30 


mA 



2-152 



AFN-00843D 




8755A/8755A-2 



A.C. CHARACTERISTICS (T A = o°c to 70°, v C c = sv ± 5%; 

Vcc = V DD = 5V ±10% for 8755A-2) 



Symbol 


Parameter 


8755A 


8755A-2 
(Preliminary) 




Min. 


Max. 


Min. 


Max. 


Units 


tCYC 


Clock Cycle Time 


320 




200 




ns 


Ti 


CLK Pulse Width 


80 




40 




ns 


T 2 


CLK Pulse Width 


120 




70 




ns 


tf.tr 


CLK Rise and Fall Time 




30 




30 


ns 


tAL 


Address to Latch Set Up Time 


Kn 




on 
OU 




ns 


tLA 


Address Hold Time after Latch 


an 
ou 




At\ 
**D 




ns 


tLC 


Latch to READ/WRITE Control 


1 nn 




An 




ns. 


tRD 


Valid Data Out Delay from READ Control* 




170 




140 


ns 


tAD 


Address Stable to Data Out Valid*" 








inn 


ns 


tLL 


Latch Enable Width 


mn 
I uu 




70 




ns 


tRDF 


Data Bus Float after READ 


o 


100 


o 


8*5 


ns 


tCL 


READ/WRITE Control to Latch Enable 


20 




10 




ns 


tec 


READ/WRITE Control Width 


250 




200 




ns 


tDW 


Data In to Write Set Up Time 


150 




150 




ns 


tWD 


Data In Hold Time After WRITE 


30 




10 




ns 


tWP 


WRITE to Port Output 




400 




300 


ns 


tpR 


Port Input Set Up Time 


50 




50 




ns 


tRP 


Port Input Hold Time to Control 


50 




50 




ns 


tRYH 


READY HOLD Time to Control 


0 


' 160 


0 


160 


ns 


tARY 


ADDRESS (CE) to READY 




160 




160 


ns 


tRV 


Recovery Time Between Controls 


300 




200 




ns 


tRDE 


READ Control to Data Bus Enable 


10 




10 




ns 



NOTE: 

Cload = 150pF. 

*Or T AD - (T AL + T LC ), whichever is greater. 

"Defines ALE to Data Out Valid in conjunction withTAL- 



A.C. CHARACTERISTICS— PROGRAMMING (T A = o°cto70°, v C c = 5V ± 5%, v ss = ov, v DD = 25V ±1 V; 

V C c = Vdd = 5V ±10% for 8755A-2) 



Symbol 


Parameter 


Min. 


Typ. 


Max. 


Unit 


tps 


Data Setup Time 


10 






ns 


tPD 


Data Hold Time 


0 






ns 


ts 


Prog Pulse Setup Time 


2 






M s 


tH 


Prog Pulse Hold Time 


2 






MS 


tpR 


Prog Pulse Rise Time 


0.01 


2 




MS 


tpF 


Prog Pulse Fall Time 


0.01 


2 




MS 


tPRG 


Prog Pulse Width 


45 


50 




msec 



2-153 



AFN-00843D 



8755A/8755A-2 



A.C. TESTING INPUT, OUTPUT WAVEFORM 



A.C. TESTING LOAD CIRCUIT 



INPUT/OUTPUT 



^> TEST POINTS <^ 



A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR 
A LOGIC 0 ' TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1 
AND 0 8V FOR A LOQIC 0 



DEVICE 
UNDER 
TEST 



1 



C L = 150 pF 



C L = 150 pF 

C L INCLUDES JIG CAPACITANCE 



WAVEFORMS 




PROM READ, I/O READ AND WRITE 



A810 
IO/M- 



(PROO/CE, 



X 



X 



X 



>-o; 



x 



— — , — ADDRESS 



mum 



Please note that CEi must remain low for the entire cycle 



2-154 



AFN-00843D 



inter 



8755A/8755A-2 



WAVEFORMS (Continued) 



I/O PORT 



A. INPUT MODE 



RD OR 
IOR 



\ 



PORT 
INPUT 



x 



DATA* 
BUS 



:::::::x 



B. OUTPUT MODE 



\ 



PORT 
OUTPUT 



DATA* 
BUS 



GLITCH FREE 
' OUTPUT 



:::::x 



x 



WAIT STATE (READY = 0) 



(CE=1) -<CE=0) 



READY < 









/ — V 



2-155 



•AFN-00843D 



■nW. 



8755A/8755A-2 



WAVEFORMS (Continued) 



8755A PROGRAM MODE 



- PROGRAM CYCLE - 



- VERIFY CYCLE* 



- PROGRAM CYCLE 



— v — v v 



■DCZX 



CE 2 ^ 



+25 
V D D 



/OGEEXZ 



~) ( xzz 



V 



•VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH V DD = +5V FOR 8755A) 



2-156 



AFN-00843D 



iAPX 86, 88, 186, 188 
Microprocessors 



Microprocessors 
Section 



APPLICATION 
NOTE 



AP-113 



February 1981 




3-1 



AM 13 



INTRODUCTION 

This is an application note on using numerics in Intel's 
iAPX 86 or iAPX 88 microprocessor family. The nu- 
merics implemented in the family provide instruction 
level support for high-precision integer and floating 
point data types with arithmetic operations like add, 
subtract, multiply, divide, square root, power, log and 
trigonometries. These features are provided by members 
of the iAPX 86 or iAPX 88 family called numeric data 
processors. 

Rather than concentrate on a narrow, specific applica- 
tion, the topics covered in this application note were 
chosen for generality across many applications. The 
goal is to provide sufficient background information so 
that software and hardware engineers can quickly move 
beyond needs specific to the numeric data processor and 
concentrate on the special needs of their application. 
The material is structured to allow quick identification 
of relevant material without reading all the material 
leading up to that point. Everyone should read the in- 
troduction to establish terminology and a basic 
background. 

iAPX 86,88 BASE 

The numeric data processor is based on an 8088 or 8086 
microprocessor. The 8086 and 8088 are general purpose 
microprocessors, designed for general data processing 
applications. General applications need fast, efficient 
data movement and program control instructions. Ac- 
tual arithmetic on data values is simple in general appli- 
cations. The 8086 and 8088 fulfill these needs in a low 
cost, effective manner. 

However, some applications need more powerful arith- 
metic instructions and data types than a general purpose 
data processor provides. The real world deals in frac- 
tional values and requires arithmetic operations like 
square root, sine, and logarithms. Integer data types 
and their operations like add, subtract, multiply, and 
divide may not meet the needs for accuracy, speed, and 
ease of use. 

Such functions are not simple or inexpensive. The 
general data processor does not provide these features 
due to their cost to other less-complex applications that 
do not need such features?* A special processor is re- 
quired, one which is easy to use and has a high level of 
support in hardware and software. 

The numeric data processor provides these features. IV 
supports the data types and operations needed and 
allows use of all the current hardware and software sup- 
port for the iAPX 86/10 and 88/10 microprocessors. 

The iAPX 86 and iAPX 88 provide two imple- 
mentations of a numeric data processor. Each offers 
different tradeoffs in performance, memory size, and 
cost. 



One alternative uses a special hardware component, the 
8087 numeric processor extension, while the other is 
based on software, the 8087 emulator. Both component 
and software emulator add the extra numerics data 
types and operations to the 8086 or 8088. 

The component and its software emulator are com- 
pletely compatible. 



Nomenclature 

Table one shows several possible configurations 
of the iAPX 86 and iAPX 88 microprocessor, family. 
The choice of configuration will be decided by the 
needs of the application for cost and performance 
in the areas of general data processing, numerics, 
and I/O processing. The combination of an 8086 or 
8088 with an 8087 is called an iAPX 86/20 or 88/20 
numeric data processor. For applications requir- 
ing high I/O bandwidths and numeric perfor- 
mance, a combination of 8086, 8087 and 8089 is ah 
iAPX 86/21 numerics and I/O data processor. The 
same system with an 8088 CPU for smaller size 
and lower cost, due to the smaller 8-bit wide 
system data bus, is referred to as an iAPX 88/21. 
Each 8089 in the system is designated in the units 
digit of the system designation. The term 86/2X or 
88/2X refers to a numeric data processor with any 
number of 8089s. 

Throughout this application note, I will use the 
terms NDP, numeric data processor, 86/2X, and 
88/2X synonymously. Numeric processor exten- 
sion and NPX are also synonymous for the func- 
tions of either the 8087 component or 8087 
emulator. The term numeric instruction or 
numeric data type refers to an instruction or data 
type made available by the NPX. The term host will 
refer to either the 8086 or 8088 microprocessor. 



Table 1. Components Used in l/APX 86,88 
Configurations 



System Name 


8086 8087 8088 8089 


iAPX 86/10 


1 


iAPX 86/11 


1 1 


iAPX 86/12 


1 2 


iAPX 86/20 


1 1 


iAPX 86/21 


1 1 1 


iAPX 86/22 


1 1 2 


iAPX 88/10 




iAPX 88/11 


1 1 


iAPX 88/12 


1 2 


iAPX 88/20 


1 1 


iAPX 88/21 


11 1 


iAPX 88/22 


1 1 2 



3-2 



AM 13 



NPX OVERVIEW 

the 8087 is a coprocessor extension available to 
iAPX 86/1X or iAPX 88/ IX maximum mode 
microprocessor systems. (See page 7). The 8087 
adds hardware support for floating point and ex- 
tended precision integer data types, registers, and 
instructions. Figure 1 shows the register set 
available to the NDP. On the next page, the seven 
data types available to numeric instructions are 
listed (Fig 2). Each data type has a load and store 
instruction. Independent of whether an 8087 or its 
emulator are used, the registers and data types all 
appear the same to the programmer. 

All the numeric instructions and data types of the NPX 
are used by the programmer in the same manner as the 
general data types and instructions of the host. 

The numeric data formats and arithmetic operations 
provided by the 8087 conform to the proposed IEEE 
Microprocessor Floating Point Standard. All the pro- 
posed IEEE floating point standard algorithms, excep- 
tion detection, exception handling, infinity arithmetic 
and rounding controls are implemented. 1 

The numeric registers of the NPX are provided for fast, 
easy reference to values needed in numeric calculations. 
All numeric values kept in the NPX register file are held 
in the 80-bit temporary real floating point format which 
is the same as the 80-bit temporary real data type. 

All data types are converted to the 80-bit register file 
format when used by the NPX. Load and store instruc- 
tions automatically convert between the memory 
operand data type and the register file format for all 
numeric data types. The numeric load instruction 
specifies the format in which the memory operand is ex- 
pected and which addressing mode to use. 

All host base registers, index registers, segment 
registers, and addressing modes are available for 
locating numeric operands. In the same manner, the 
store instruction also specifies which data type to use 
and where the value is located when stored into 
memory. 

Selecting Numeric Data Types 

As figure 2 shows, the numeric data types are of dif- 
ferent lengths and domains (real or integer). Each 
numeric data type is provided for a specific function, 
they are: 

16-bit word integers —Index values, loop counts, 
and small program control 
values 



"An Implementation Guide to a Proposed Standard for Floating 
Point" by Jerome Coonen in Computer, Jan. 1980 or the Oct. 1979 
issue of ACM SIGNUM, for more information on the standard. 



32-bit short integers 

64-bit long integers 

18-digit packed 
decimal 

32-bit short real 



64-bit long real 

80-bit temporary 
real 



-Large integer general 
computation 

-Extended range integer 
computation 

-Commercial and decimal 
conversion arithmetic 

-Reduced range and 
accuracy is traded for 
reduced memory require- 
ments 

-Recommended floating 
point variable type 

-Format for intermediate 
or high precision calcu- 
lations 



Referencing memory data types in the NDP is not 
restricted to load and store instructions. Some arith- 
metic operations can specify a memory operand in one 
of four possible data types. The numeric instructions 
compare, add, subtract, subtract reversed, multiply, 
divide, and divide reversed can specify a memory 
operand to be either a 16-bit integer, 32-bit integer, 
32-bit real, or 64-bit real value. As with the load and 
store operations, the arithmetic instruction specifies the 
address and expected format of the memory operand. 

The remaining arithmetic operations: square root, 
modulus, tangent, arctangent, logarithm, exponentiate, 
scale power, and extract power use only register 
operands. 



EXPONENT 


SIGNIFICAND 































Figure 1. NDP Register Set for iAPX 86/20, 88/20 



3-3 



AP-113 



The register set of the host and 8087 are in separate 
components. Direct transfer of values between the two 
register sets in one instruction is not possible. To trans- 
fer values between the host and numeric register sets, 
the value must first pass through memory. The memory 
format of a 16-bit short integer used by the NPX is iden- 
tical to that of the host, ensuring fast, easy transfers. 

Since an 8086 or 8088 does not provide single instruc- 
tion support for the remaining numeric data types, host 
programs reading or writing these data types must con- 
form to the bit and byte ordering established by the 
NPX. 

Writing programs using numeric instructions is as sim- 
ple as with the host's instructions. The numeric instruc- 
tions are simply placed in line with the host's instruc- 
tions. They are executed in the same order as they ap- 
pear in the instruction stream. Numeric instructions 
follow the same fbrm as the host instructions. Figure 2 
shows the ASM 86/88 representations for different 
numeric instructions and their similarity to host instruc- 
tions. 



8087 EMULATOR OVERVrEW 

The NDP has two basic implementations, an 8087 com- 
ponent or with its software emulator (E8087). The deci- 
siori to use the emulator or component has no effect on 
programs at the source level. At the source level, all in- 
structions, data types, and features are used the same 
way. 

The emulator requires all numeric instruction opcodes 
to be replaced with an interrupt instruction. This 
replacement is performed by the LINK86 program. In- 
terrupt vectors in the host's interrupt vector table will 
point to numeric instruction emulation routines in the 
8087 software emulator. 

When using the 8087 emulator, the linker changes all the 
2-byt£ wait-escape, nop-escape, wait-segment override, 
or nop-segment override sequences generated by an 
assembler or compiler for the 8087 component with a 
2-byte interrupt instruction. Any remaining bytes of the 
numeric instruction are left unchanged. 



FILD 

FIADD 

FADD 



VALUE 
TABLE [BX] 
ST,ST(1) 



DATA 
FORMATS 



WORD INTEGER 



SHORT INTEGER 



10» 



LONG INTEGER 



PACKED BCD 



SHORT REAL 



TEMPORARY REAL 



MOST SIGNIFICANT BYTE 



7 07 07 07 07 07 07 07 07 07 0 



E 7 E 0 F 



F23 



S E10 E 0 F 



S E14 Eq Fo 



TWO'S COMPLEMENT 



TWO'S COMPLEMENT 



. TWO'S 
10 COMPLEMENT 



S 




D17 D 16 




D1 D 0 



F52 



F 0 IMPLICIT 



P 6 3 



INTEGER: 1 
PACKED BCD: ( - 1) S (D 17 . . . D 0 ) 

REAL: ( - 1)S(2E BIAS) (F0.F1 . . . ) 

BIAS m 127 FOR SHORT REAL 
1023 FOR LONG REAL 
16383 FOR TEMP REAL 



Figure 2. NPX Data Types 

3-4 



AM 13 



When the host encounters numeric and emulated in- 
struction, it will execute the software interrupt instruc- 
tion formed by the linker. The interrupt vector table will 
direct the host to the proper entry point in the 8087 
emulator. Using the interrupt return address and CPU 
register set, the host will decode any remaining part of 
the numeric instruction, perform the indicated opera- 
tion, then return to the next instruction following the 
emulated numeric instruction. 

One copy of the 8087 emulator can be shared by all pro- 
grams in the host. 

The decision to use the 8087 or software emulator is 
made at link time, when all software modules are 
brought together. Depending on whether an 8087 or its 
software emulator is used, a different group of library 
modules are included for linking with the program. 

If the 8087 component is used, the libraries do not add 
any code to the program, they just satisfy external refer- 
ences made by the assembler or compiler. Using the 
emulator will not increase the size of individual modu- 
les; however, other modules requiring about 16K bytes 
that implement the emulator will be automatically 
added.. 

Selecting between the emulator or the 8087 can be very 
easy. Different versions of submit files performing the 
link operation can be used to specify the different set of 
library modules needed. Figure 3 shows an example of 
two different submit files for the same program using 
the NPX with an 8087 or the 8087 emulator. 

iSBC 337™ MULTIMODULE™ Overview 

The benefits of the NPX are not limited to systems 
which left board space for the 8087 component or mem- 
ory space for its software emulator. Any maximum 
mode iAPX 86/1X or iAPX 88/1X system can be up- 
graded to a numeric processbr. The iSBC 337 MUL- 
TIMODULE is designed for just this function. The 
iSBC 337 provides a socket for the host microprocessor 
and an 8087. A 40-pin plug is provided on the underside 
of the 337 to plug into the original host's socket, as 
shown in Figure 4. Two other pins on the underside of 
the MULTIMODULE allow easy connection to the 
8087 INT and RQ/GT1 pins. 



8087 BASED LINK/LOCATE COMMANDS 

LINK86 :F1:PROG.OBJ, IO.LIB, 8087.LIB TO 

:F1:PROG.LNK 
LOC86 :F1:PROG.LNKTO :F1:PROG 



SOFTWARE EMULATOR BASED 
LINK/LOCATE COMMANDS 

LINK86 :F1:PROG.OBJ, IO.LIB, E8087. LIB, 

E8087 TO :F1:PROG.LNK 
LOC86 :F1:PROG.LNKTO :F1:PROG 



Figure 3. Submit File Example 



ISBC 337™ MULTIMODULE™ BOARD 



1 \ 1 I CO 



8087 INT 
CONNECTOR 



fQifOi 



HOST BOARD 



1 n 17 



8086 SOCKET 



/ 



BOARD OPTIONAL SOLDER 
0SBC86/12A™) MOUNT * 



Figure 4. MULTIMODULE™ Math Mounting Scheme 



3-5 



AM 13 



CONSTRUCTING AN iAPX 86/2X OR iAPX 
88/2X SYSTEM 

This section will describe how to design a micropro- 
cessor system with the 8087 component. The discussion 
will center around hardware issues. However, some of 
the hardware decisions must be made based upon how 
the software will use the NPX. To better understand 
how the 8087 operates as a local bus master, we shall 
cover how the coprocessor interface works later in this 
section. 



Wiring up the 8087 

The 8087 can be designed into any 86/1X or 88/1X 
system operating in maximum mode. Such a system 
would be designated an 86/2X or 88/2X. Figure 5 shows 
the local bus interconnections for an iAPX 86/20 (or 
iAPX 88/20) system. The 8087 shares the maximum 
mode host's multiplexed address/data bus, status sig- 
nals, queue status signals, ready status signal, clock and 
reset signal. Two dedicated signals, BUSY and INT, in- 
form the host of current 8087 status. The 10K pull-down 
resistor on the BUSY signal ensures the host will always 
see a "not busy" status if an 8087 is not installed. 

Adding the 8087 to your design has a minor effect on 
hardware timing. The 8087 has the exact same timing 
and equivalent DC and AC drive characteristics as a 
host or IOP on the local bus. All the local bus logic, 
such as clock, ready, and interface logic is shared. 

The 8087 adds 15 pF to the total capacitive loading on 
the shared address/data and status signals. Like the 

8086 or 8088, the 8087 can drive a total of 100 pF 
capacitive load above its own self load and sink 2.0 mA 
DC current on these pins. This AC and DC drive is suf- 
ficient for an 86/21 system with two sets of data 
transceivers, address latches, and bus controllers for 
two separate busses, an bn-board bus and an off-board 
MULTIBUS™ using the 8289 bus arbiter. 

Later in this section, what to do with the 8087 INT and 
RQ/GT pins, is covered. 

It is possible to leave a prewired 40-pin socket on the 
board for the 8087. Adding the 8087 to such a system is 
as easy as just plugging it in. If a program attempts to 
execute any numeric instructions without the 8087 in- 
stalled, they will be simply treated as NOP instructions 
by the host. Software can test for the existence of the 

8087 by initializing it and then storing the control word. 
The program of Figure 6 illustrates this technique. 




3-6 



Figure 5. System Diagram 



DOO 




DIO 


D01 




on 


D02 




DI2 


D03 


00 


DI3 


D04 


8 


DI4 


D05 


IO 


DIS 


D06 




DI6 


D07 




DI7 


OE 




STB 



D15 19 


BO 




AO 


014 18 


B1 




A1 


D13 17 


B2 




A2 


P12 16 
Oil 15 


B3 
B4 


8286 

Notel 


A3 
A4 


P10 14 


B5 


AS 


D9 13 


B6 




A6 


D8 12 


B7 
OE 




A7 
T 



z z 



ii- 



ii 

2§ 



D7 19 


BO 


AO 


06 18 


B1 


A1 


D5 17 


B2 


A2 


04 16 


B3 


00 A3 


D3 15 


B4 


g A4 


02 14 


B5 


°» A5 


01 13 


B6 


A6 


DO 12 


B7 


A7 




OE T 




9 





AUt) 
AD4 
AD3 
AD2 
AD1 
ADO 



HQ/ 
QSO GTO 



I" 



QS1 QSO RQ/GT1 TEST 
A18/S5 <SSO) BH1/S7 



A17/S4 
A16/S3 
AD15(A15)' 
AD14<A14) 
AD13(A13) 
AD12(A12) 
AD1KA11) ^ 
A01CHA10) 5? » 
AD9(A9) 



READY 
RESET 
CLK 
RD 
RQ7GT5 
LOCK 



^ INTR 



Vcc GND GNDMN/Wy 



> 



RQJGTo 

COCR 



CLK AEN 
S2 
S1 



iOB GND V C( 



+ 5V 



17 



CEN MCE/ 
PDEN 

iofic 

_ iowc 
so 09 Aidwc 

ALE DT/R DEN MRDC MWTC AMWC INTA 



AP-113 



WHAT IS THE iAPX 86, 88 
COPROCESSOR INTERFACE? 

The idea of a coprocessor is based on the observation 
that hardware specially designed for a function is the 
fastest, smallest, and cheapest implementation. But, it is 
too expensive to incorporate all desired functions in 
general purpose hardware. Few applications could use 
all the functions. To build fast, small, economical sys- 
tems, we need some way to mix and match components 
supporting specialized functions. 

Purpose of the Coprocessor Interface 

The coprocessor interface of the general purpose 8086 
or 8088 microprocessor provides a way to attach special- 
ized hardware in a simple, elegant, and efficient man- 
ner. Because the coprocessor hardware is specialized, it 
can perform its job much faster than any general pur- 
pose CPU of similar size and cost. The coprocessor 
interface simply requires connection to the host's local 
address/data, status, clock, ready, reset, test and re- 
quest/grant signals. Being attached to the host's local 
bus gives the coprocessor access to all memory and I/O 
resources available to the host. 

The coprocessor is independent of system configura- 
tion. Using the local bus as the connection point to the 
host isolates the coprocessor from the particular system 
configuration, since the timing and function of local bus 
signals are fixed. 

Software's View of the Coprocessor 

The coprocessor interface allows specialized hardware . 
to appear as an integral part of the host's architecture 
controlled by the host with special instructions. When 
the host encounters these special instructions, both the 
host and coprocessor recognize them and work together 
to perform the desired function. No status polling loops 
or command stuffing sequences are required by soft- 
ware to operate the coprocessor. 

More information is available to a coprocessor than 
simply an instruction opcode and a signal to begin exe- 



cution. The host's coprocessor interface can read a 
value from memory, or identify a region of memory the 
coprocessor should use while performing its function. 
All the addressing modes of the host are available to 
identify memory based operands to the coprocessor. 

Concurrent Execution of Host and 
Coprocessor 

After the coprocessor has started its operation, the host 
may continue on with the program, executing it in par- 
allel while the coprocessor performs the function started 
earlier. The parallel operation of the coprocessor does 
not normally affect that of the host unless the copro- 
cessor must reference memory or I/O-based operands. 
When the host releases the local bus to the coprocessor, 
the host may continue to execute from its internal in- 
struction queue. However, the host must stop when it 
also needs the local bus currently in use by the copro- 
cessor. Except for the stolen memory cycle, the opera- 
tion of the coprocessor is transparent to the host. 

This parallel operation of host and coprocessor is called 
concurrent execution. Concurrent execution of instruc- 
tions requires less total time then a strictly sequential 
execution would. System performance will be higher 
with concurrent execution of instructions between the 
host and coprocessor. 

SYNCHRONIZATION 

In exchange for the higher system performance made 
available by concurrent execution, programs must pro- 
vide what is called synchronization between the host 
and coprocessor. Synchronization is necessary whenever 
the host and coprocessor must use information available 
from the other. Synchronization involves either the host 
or coprocessor waiting for the other to finish an opera- 
tion currently in progress. Since the host executes the 
program, and has program control instructions like 
jumps, it is given responsibility for synchronization. To 
meet this need, a special host instruction exists to syn- 
chronize host operation with a coprocessor. 



Test for the existence of an 8087 in the system. This code will always recognize an 8087 
independent of the TEST pin usage on the host. No deadlock is possible. Using the 8087 
emulator will not change" the function of this code since ESC instructions are used. The word 
variable control is used for communication between the 8087 and the -host. Note: if an 8087 is 
present, it will be initialized. Register ax is not transparent across this code. 



ESC 

XOR 

MOV 

ESC 

OR 

JZ 



28, bx 
ax, ax 
control, ax 
15, control 
ax, control 
no_8087 



; FNINIT if 8087 is present . The contents of bx is irrelevant 

; These two instructions insert delay while the 8087 initializes itself 

; Clear intial control word value 

; FNSTCW if 8087 is present 

; Control = 03ffh if 8087 present 

; Jump if no 8087 is present 



Figure 6. Test for Existence of an 8087 



3-8 



AP113 



The host coprocessor synchronization instruction, 
called "WAIT", uses the TEST pin of the host. The 
coprocessor can signal that it is still busy to the host via 
this pin. Whenever the host executes a wait instruction, 
it will stop program execution while the TEST input is 
active. When the TEST pin becomes inactive, the host 
will resume program execution with the next instruction 
following the WAIT. While waiting on the TEST pin, 
the host can be interrupted at 5 clock intervals; how- 
ever, after the TEST pin becomes inactive, the host will 
immediately execute the next instruction, ignoring any 
pending interrupts between the WAIT and following 
instruction. 

COPROCESSOR CONTROL 

The host has the responsibility for overall program con- 
trol. Coprocessor operation is initiated by special in- 
structions encountered by the host. These instructions 
are called "ESCAPE" instructions. When the host en- 
counters an ESCAPE instruction, the coprocessor is 
expected to perform the action indicated by the instruc- 
tion. There are 576 different ESCAPE instructions, 
allowing the coprocessor to perform many different 
actions. 

The host's coprocessor interface requires the copro- 
cessor to recognize when the host has encountered an 
ESCAPE instruction. Whenever the host begins execut- 
ing a new instruction, the coprocessor must look to see 
if it is an ESCAPE instruction. Since only the host 
fetches instructions and executes them, the coprocessor 
must monitor the instructions being executed by the 
host. 

Host Queue Tracking 

The host can fetch an instruction at a variable length 
time before the host executes the instruction. This is a 
characteristic of the instruction queue of an 8086 or 
8088 microprocessor. An instruction queue allows pre- 
fetching instructions during times when the local bus 



would be otherwise idle. The end benefit is faster execu- 
tion time of host instructions for a given memory band- 
width. 

The host does not externally indicate which instruction 
it is currently executing. Instead, the host indicates 
when it fetches an instruction and when, some time 
later, an opcode byte is decoded and executed. To iden- 
tify the actual instruction the host fetched from its 
queue, the coprocessor must also maintain an instruc- 
tion stream identical to the host's. 

Instructions can be fetched in byte or word increments, 
depending on the type of host and the destination ad- 
dress of jump instructions executed by the host. When 
the host has filled its queue, it stops prefetching instruc- 
tions. Instructions are removed from the queue a byte at 
a time for decoding and execution. When a jump oc- 
curs, the queue is emptied. The coprocessor follows 
these actions in the host by monitoring the host's bus 
status, queue status, and data bus signals. Figure 7 
shows how the bus status signals and queue status 
signals are encoded. 

IGNORING I/O PROCESSORS 

The host is not the only local bus master capable of 
fetching instructions. An Intel 8089 IOP can generate 
instruction fetches on the local bus in the course of exe- 
cuting a channel program in system memory. In this 
case, the status signals S2, SI, and SO generated by the 
IOP are identical to those of the host. The coprocessor 
must not interpret these instruction prefetches as going 
to the host's instruction queue. This problem is solved 
with a status signal called S6. The S6 signal identifies 
when the local bus is being used by the host. When the 
host is the local bus master, S6 = 0 during T2 and T3 of 
the memory cycle. All other bus masters must set S6 = 1 
during T2 and T3 of their instruction prefetch cycles. 
Any coprocessor must ignore activity on the local bus 
when S6=l. 



S2 


S1 


SO 


Function 


QS1 


QSO 


Host Function 


Coprocessor Activity 


0 


0 


0 


Interrupt Acknowledge 


0 


0 


No Operation 


No Queue Activity 


0 


0 


1 


Read I/O Port 


0 


1 


First Byte 


Decode Opcode Byte 


0 


1 


0 


Write I/O Port 


1 


0 


Empty Queue 


Empty Queue 


0 


1 


1 


Halt 


1 


1 


Subsequent Byte 


Flush Byte or if 2nd 


1 


0 


0 


Code Fetch 








Byte of Escape 


1 


0 


1 


Read Data Memory 








Decode it 


1 


1 


0 


Write Data Memory 










1 


1 


1 


Idle 











Figure 7. 

3-9 



/ 

AP-113 



DECODING ESCAPE INSTRUCTIONS 

To recognize ESCAPE instructions, the coprocessor 
must examine all instructions executed by the host. 
When the host fetches an instruction byte from its inter- 
nal queue, the coprocessor must do likewise. 

The queue status state, fetch opcode byte, identifies 
when an opcode byte is being examined by the host. At 
the same time, the coprocessor will check if the byte fet- 
ched from its internal instruction queue is an ESCAPE 
opcode. If the instruction is not an ESCAPE, the 
coprocessor will ignore it. The queue status signals for 
fetch subsequent byte and flush queue let the 
coprocessor track the host's queue without knowledge 
of the length and function of host instructions and ad- 
dressing modes. 

Escape Instruction Encoding 

All ESCAPE instructions start with the high-order 
5-bits of the instruction being 11011. They have two 
basic forms. The non-memory form, listed here, in- 
itiates some activity in the coprocessor using the nine 
available bits of the ESCAPE instruction to indicate 
which function to perform. 



MOD 




Memory reference forms of the ESCAPE instruction, 
shown in Figure 8, allow the host to point out a memory 
operand to the coprocessor using any host memory ad- 
dressing mode. Six bits are available in the memory 
reference form to identify what to do with the memory 
operand. Of course, the coprocessor may not recognize 
all possible ESCAPE instructions, in which case it will 
simply ignore them. 

Memory reference forms of ESCAPE instructions are 
identified by bits 7 and 6 of the byte following the 
ESCAPE opcode. These two bits are the MOD field of 
the 8086 or 8088 effective address calculation byte. 



They, together with the R/M field, bits 2 through 0, 
determine the addressing mode and how many subse- 
quent bytes remain in the instruction. 

Host's Response to an Escape Instruction 

The host performs one of two possible actions when 
encountering an ESCAPE instruction: do nothing or 
calculate an effective address and read a word value 
beginning at that address. The host ignores the value of 
the word read. ESCAPE instructions change no regis- 
ters in the host other than advancing IP. So, if there is 
no coprocessor, or the coprocessor ignores the ESCAPE 
instruction, the ESCAPE instruction is effectively a 
NOP to the host. Other than calculating a memory ad- 
dress and reading a word of memory, the host makes no 
other assumptions regarding coprocessor activity. 

The memory reference ESCAPE instructions have two 
purposes: identify a memory operand and for certain in- 
structions, transfer a word from memory to the 
coprocessor. 

COPROCESSOR INTERFACE TO MEMORY 

The design of a coprocessor is considerably simplified if 
it only requires reading memory values of 16 bits or less. 
The host can perform all the reads with the coprocessor 
latching the value as it appears on the data bus at the 
end of T3 during the memory read cycle. The copro- 
cessor need never become a local bus master to read or 
write additional information. 

If the coprocessor must write information to memory, 
or deal with data values longer than one word, then it 
must save the memory address and be able to become a 
local bus master. The read operation performed by the 
host in the course of executing the ESCAPE instruction 
places the 20-bit physical address of the operand on the 
address/data pins during Tl of the memory cycle. At 
this time the coprocessor can latch the address. If the 
coprocessor instruction also requires reading a value, it 
will appear on the data bus during T3 of the memory 
read. All other memory b,ytes are addressed relative to 
this starting physical address. 



MOD R/M 16-blt direct displacement 

I 1 1 1 l 0 1 1 I 1 I I I | 0 1 0 1 I I M I 1 1 0 1 I I I I I I I I t I I I I I l | 

'15 *14 *13 '12 »11 'lO '9 '8 »7 '6 '5 U f 3 »2 N *0 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 °7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 

MOD R/M 16-bit displacement 

I 1 I 1 I 0 I 1 I 1 I I I | 1 I 0 I -l I I I 1 | I I 1 I I 1 1 | I » 1 I I I 1 | 

»15 '14 «13 '12 »11 '10 '9 •S »7 '6 »5 «4 "3 «2 «1 »0 D 15 D 14 °13 D 12 D 11 D 10 D 9 °8 °7 t>6 D 5 °4 °3 D 2 »1 D 0 

MOD R/M 8-bit displacement 

I 1 I 1 I 0 I 1 l 1 i l I |° I 1 I I l I I I I l l I I l l I | 

' »15 <14 '13 «12 «11 »10 »9 '8 ' »7 «6 «5 »4 »3 »2 H «0 ' °7 D 6 D 5 °4 °3 *> 2 D 0 * 

MOD R/M 

| 1 t 1 \ 0 i 1 I 1 I I I |° I 0 I I I I I t I 

'15 '14 ! 13 '12 'l1 '10 *9 '8 '7 '6 *5 *4 *3 f 2 ! 1 'o 

Figure 8. Memory Reference Escape Instruction Forms 

3-10 



AP-113 



Whether the coprocessor becomes a bus master or not, 
if the coprocessor has memory reference instruction 
forms, it must be able to identify the memory read per- 
formed by the host in the course of executing an 
ESCAPE instruction. 

Identifying the memory read is straightforward, requir- 
ing all the following conditions to be met: 

1) A MOD value of 00, 01, or 10 in the second byte 
of the ESCAPE instruction executed by the host. 

2) This is the first data reacl memory cycle performed 
by the host after it encountered the ESCAPE in- 
struction. In particular, the bus status signals 
S2-S0 will be 101 and S6 will be 0. 

The coprocessor must continue to track the instruction 
queue of the host while it calculates the memory address 
and reads the memory value. This is simply a matter of 
following the fetch subsequent byte status commands 
occurring on the queue status pins. 

HOST PROCESSOR DIFFERENCES 

A coprocessor must be aware of the bus characteristics 
of the host processor. This determines how the host will 
read the word operand of a memory reference ESCAPE 
instruction. If the host is an 8088, it will always perform 
two byte reads at sequential addresses. But if the host is 
an 8086, it can either perform a single word read or two 
byte reads to sequential addresses. 

The 8086 places no restrictions on the alignment of 
word operands in memory. It will automatically per- 
form two byte operations for word operands starting at 
an odd address. The two operations are necessary since 
the two bytes of the operand exist in two different mem- 
ory words. The coprocessor should be able to accept the 
two possible methods of reading a word value on the 
8086. 

A coprocessor can determine whether the 8086 will per- 
form one or two memory cycles as part of the current 
ESCAPE instruction execution. The ADO pin during Tl 
of the first memory read by the host tells if this is the 
only read to be performed as part of the ESCAPE in- 
struction. If this pin is a 1 during Tl of the memory 
cycle, the 8086 will immediately follow this memory 
read cycle with another one at the next byte address. 

Coprocessor Interface Summary 

The host ESCAPE instructions, coprocessor interface, 
and WAIT instruction allow easy extension of the host's 
architecture with specialized processors. The 8087 is 
such a processor, extending the host's architecture as 
seen by the programmer. The specialized hardware pro- 
vided by the 8087 can greatly improve system perfor- 
mance economically in terms of both hardware and 
software for numerics applications. 



The next section examines how the 8087 uses the 
coprocessor interface of the 8086 or 8088. 

8087 COPROCESSOR OPERATION 

The 8086 or 8088 ESCAPE instructions provide 64 
memory reference opcodes and 512 non-memory refer- 
ence opcodes. The 8087 uses 57 of the memory reference 
forms and 406 of the non-memory reference forms. Fig- 
ure 9 shows the ESCAPE instructions not used by the 
8087. 



1 | 1 | 0 


I 1 


| 1 


I 


I 


I 


1 


1 1 

I 


I I 


Ml! 


•15 '14 '13 


'12 


•11 


'10 


>9 


'8 


'7 


>6 


'5 '4 


>3 '2 '1 '0 


•10 l9 18 '5 U »3 l2 H 


io 


Available codes 


0 0 


1 


0 


1 


0 


0 


0 


1 




1 


0 0 


1 


0 


1 


0 


0 


1 






2 


0 0 


1 


0 


1 


0 


1 








4 


0 0 


1 


1 


0 


0 


0 


1 






2 


0 0 


1 


1 


0 


0 


1 


1 






2 


0 0 


1 


1 


0 


1 


1 


1 


1 




1 


0 0 


1 


1 


1 


0 


1 


0 


1 




1 


0 0 


1 


1 


1 


1 


0 


1 


1 




1 


0 0 


1 


1 


1 


1 


1 


1 






2 


0 1 


1 


1 


0 


0 


1 


0 


1 




1 


0 1 


1 


1 


0 


0 


1 


1 






2 


0 1 


1 


1 


0 


1 










8 


0 1 


1 


1 


1 












16 


1 0 


1 


1 














32 


1 1 


1 


1 


0 


0 


0 


0 


1 




i 


1 1 


1 


t 


0 


0 


0 


1 


0 




1 


1 1 


1 


1 


0 


0 


1 








4 


1 1 


1 


1 


0 


1 










8 


1 1 


1 


1 


1 












16 




















105 total 


Available Non-Memory Reference Escape Instructions 














MOD 




R/M 


1 |1,0 


| 1 


1 


i 


I 






I 


I I 


I I I I 


•l5 '14 '13 


«12 


'11 


'10 


>9 






'6 


>5 >4 


'3 '2 H »0 


h0 19 >8 >5 "4 l3 












0 0 


1 


0 


6 


1 












0 1 


1 


0 


0 


1 












0 1 


1 


1 


0 


0 












0 1 


1 


1 


1 


0 












1 0 


1 


0 


0 


1 












1 0 


1 


1 


0 


1 












1 1 


1 


0 


0 


1 












Available Memory Reference Escape Instructions 



Figure 9. 



3-11 



AM 13 



Using the 8087 With Custom 
Coprocessors 

Custom coprocessors, a designer max care to develop, 
should limit their use of ESCAPE instructions to those 
not used by the 8087 to prevent ambiguity about 
whether any one ESCAPE instruction is intended for a 
numerics or other custom coprocessor. Using any 
escape instruction for a custom coprocessor may con- 
flict with opcodes chosen for future Intel coprocessors. 

Operation of an 8087 together with other custom co- 
processors is possible under the following constraints: 

1) All 8087 errors are masked. The 8087 will update its 
opcode and instruction address registers for the un- 
used opcodes. Unused memory reference instruc- 
tions will also update the operand address value. 
Such changes in the 8087 make software-defined 
error handling impossible. 

2) If the coprocessors provide a pUSY signal, they must 
be ORed together for connection to the host TEST 
pin. When the host executes a WAIT instruction, it 
does not know which coprocessor will be affected by 
the following ESCAPE instruction. In general, all 
coprocessors must be idle before executing the 
ESCAPE instruction. 

Operand Addressing by the 8087 

The 8087 has seven different memory operand formats. 
Six of them are longer than one word. All are an even 
number of bytes in length and are addressed by the host 
at the lowest address word. 

When the host executes a memory reference ESCAPE 
instruction intended to cause a read operation by the 
8087, the host always reads the low-order word of any 
8087 memory operand. The 8087 will save the address 
and data read. To read any subsequent words of the 
operand, the 8087 must become a local bus master. 

When the 8087 has the local bus, it increments the 20-bit 
physical address it saved to address the remaining words 
of the operand. 

When the ESCAPE instruction is intended to cause a 
write operation by the 8087, the 8087 will save the ad- 
dress but ignore the data read. Eventually, it will get 
control of the local bus, then perform successive write, 
increment address operations writing the entire data 
value. 



8087 OPERATION IN IAPX 88,88 SYSTEMS 

The 8087 will work with either an 8086 or 8088 host. 
The identity of the host determines the width of the 
local bus path. The 8087 will identify the host and 
adjust its use of the data bus accordingly; 8 bits for an 

8088 or 16 bits for an 8086. No strapping options are 
required by the 8087; host identification is automatic. 

The 8087 identifies the host each time the host and 8087 
are reset via the RESET pin. After the reset signal goes 
inactive, the host will begin instruction execution at 
memory address FFFFO^. 

If the host is an 8086 it will perform a word read at that 
address; an 8088 will perform a byte read. 

The 8087 monitors pin 34 on the first memory cycle 
after power up. If an 8086 host is used, pin 34 will be the 
BHE signal, which will be low for that memory cycle. 
For an 8088 host, pin 34 will be the SS0 signal, which 
will be high during Tl of the first memory cycle. Based 
on this signal, the 8087 will then configure its data bus 
width to match that of the host local bus. 

For 88/2X systems, pin 34 of the 8087 may be tied to 
V C c tf not connected to the 8088 SS0 pin. 

The width of the data bus and alignment of data oper- 
ands has no effect, except for execution time and num- 
ber of memory cycles performed, on 8087 instructions. 
A numeric program will always produce the same results 
on an 86/2X or 88/2X with any operand alignment. All 
numeric operands have the same relative byte orderings 
independent of the host and starting address. 

The byte alignment of memory operands can affect the 
performance of programs executing on an 86/2X. If a 
word operand, or any numeric operand, starts on an 
odd-byte address, more memory cycles are required to 
access the operand than if the operand started on an 
even address. The extra memory cycles will lower system 
performance. 

The 86/2X will attempt to minimize the number of extra 
memory cycles required for odd-aligned operands. In 
these cases, the 8087 will perform first a byte operation, 
then a series of word operations, and finally a byte 
operation. 

88/2X instruction timings are independent of operand 
alignment, since byte operations are always performed. 
However, it is recommended to align numeric operands 
on even boundaries for maximum performance in case 
the program is transported to an 86/2X. 



3-12 



AP-113 



READY 

8284A 

CLK 
CLOCK 
GENERATOR 
RESET 



SYSTEM 
READY 



8088 

READY 



RESET 



STATUS 



RQ7GT1 QS TEST 



3l 



R13/GT5 QS BUSY 
A/D 



8087 



A/6 



8089 



4 



3 



-A 



-N 
V 



0) 8282 ' 

. ADDRESS 
LATCHES 



3 



8286 

DATA 
TRANSCEIVER 



4 I ° ATA K 



DT/R 
ALE DEN 

8288 

STATUS 

BUS 
CONTROLLER 

CLK 



3 



•SYSTEM! 

BUS 
L. I 



Figure 10. iAPX 88/21 

3-13 



AP-113 



RQ/GT CONNECTION 

Two decisions must be made when connecting the 8087 
to a system. The first is how to interconnect the RQ/GT 
signals of all local bus masters. The RQ/GT decision af- 
fects the response time to service local bus requests from 
other local bus masters, such as an 8089 IOP or other 
coprocessor. The interrupt connection affects the 
response time to service an interrupt request and how 
user-interrupt handlers are written. The implications of 
how these pins are connected concern both the hardware 
designer and programmer and must be understood by 
both. 

The RQ/GT issue can be broken into three general cate- 
gories, depending on system configuration: 86/20 or 
88/20, 86/21 or 88/21, and 86/22 or 88/22. Remote 
operation of an IOP is not effected by the 8087 RQ/GT 
connection. 

iAPX 86/20, 88/20 

For an 86/20 or 88/20 just connect the RQ/GT0 pin of 
the 8087 to RQ/GT1 of the host (see Figure 5), and skip 
forward to the interrupt discussion on page 15. 

iAPX 86/21, 88/21 

For an 86/21 or 88/21, connect RQ/GT0 of the 8087 to 
RQ/GT1 of the host, connect RQ/GT of the 8089 to 
RQ/GT 1 of the 8087 (see Figure 10, page 12), and skip 
forward to the interrupt discussion on page 15. 

The RQ/GT 1 pin of the 8087 exists to provide one I/O 
processor with a low maximum wait time for the local 
bus. The maximum wait times to gain control of the 
local bus for a device attached to RQ/GT 1 of an 8087 
for an 8086 or 8088 host are shown in Table 2. These 
numbers are all dependent on when the host will release 
the local bus to the 8087. 



As Table 2 implies, three factors determine when the 
host will release the local bus: 

1) What type of host is there, an 8086 or 8088? 

2) What is the current instruction being executed? 

3) , How is the lock prefix being used? 

An 8086 host will not release the local bus between the 
two consecutive byte operations performed for odd- 
aligned word operands. The 8088, in contrast, will never 
release the local bus between the two bytes of a word 
transfer, independent of its byte alignment. 

Host operations such as acknowledging an interrupt will 
not release the local bus for several bus cycles. 

Using a lock prefix in front of a host instruction 
prevents the host from releasing the local bus during the 
execution of that instruction. 

8087 RQ/GT Function 

The presence of the 8087 in the RQ/GT path from the 
IOP to the host has little effect on the maximum wait 
time seen by the IOP when requesting the local bus. The 
8087 adds two clocks of delay to the basic time required 
by the host. This low delay is achieved due to a preemp- 
tive protocol implemented by the 8087 on RQ/GT 1. 

The 8087 always gives higher priority to a request for 
the local bus from a device attached to its RQ/GT 1 pin 
than to a request generated internally by the 8087. If the 
8087 currently owns the local bus and a request is made 
to its RQ/GT 1 pin, the 8087 will finish the current 
memory cycle and release the local bus to the requestor. 
If the request from the devices arrives when the 8087 
does not own the local bus, then the 8087 will pass the 
request on to the hbst via its RQ/GT0 pin. 



Table 2. Worst Case Local Bus Request Wait Times in Clocks 



System 
Configuration 


No Locked 
Instructions 


Only Locked 
Exchange 


Other Locked 
Instructions 


iAPX 86/21 
even aligned words 


15! 


35, 


max (15!, *) 


iAPX 86/21 
odd aligned words 


15 1 


43 2 


max (43 2 , *) 


iAPX 88/21 


Hi 


43 2 


max (43 2 , *) 



Notes: 1. Add two clocks for each wait state inserted per bus cycle 
2. Add four clocks for each wait state inserted per bus cycle 
* Execution time of longest locked instruction 



3-14 



AP-113 



SYSTEM 
READY 



8284A 

CLK 

CLOCK 
GENERATOR 



£=4 



CLK (IOPA) 



rQ/St 



RQ/GTO 
READY AID 



QS 
r TEST 



8087 

CLK U 

aim ' 



V 

RESET STATUS ^~ 
ffg/QTf N 



RQ/5T 



8089 

CLK, (IOPB) 



3 



ADDRESS 
. LATCHES 

V (3)8282 



I 1 

' ADDRESS 



V (2)8286 



DATA 
TRANSCEIVERS 



ALE DT/R DEN 

8288 

STATUS 

BUS CONTROLLER 
CLK 



y 



jSYSTEMi 
L ^US J 



Figure 11. iAPX 86/22 System 



3-15 



AM 13 



IAPX 86/22, 88/22 

An 86/22 system offers two alternates regarding to 
which IOP to connect an I/O device. Each IOP will of- 
fer a different maximum delay time to servide an I/O re- 
quest. (See Fig. 11) 

The second 8089 (IOP A) must use the RQ/GTO pin of 
the host. With two IOPs the designer must decide which 
IOP services which I/O devices, determined by the max- 
imum wait time allowed between when an I/O device re- 
quests IOP service and the IOP can respond. The max- 
imum service delay times of the two IOPs can be very 
different. It makes little difference which of the two 
host RQ/GT pins are used. 

The different wait times are due to the non-preemptive 
nature of bus grants between the two host RQ/GT pins. 
No communication of a need to use the local bus is 
possible between IOPA and the 8087/IOPB combina- 
tion. Any request for the local bus by the IOPA must 
wait in the worst case for the host, 8087, and IOPB to 
finish their longest sequence of memory cycles. IOPB 
must wait in the worst case for the host and IOPA to 
finish their longest sequence of memory cycles. The 
8087 has little effect on the maximum wait time of 
IOPB. 

DELAY EFFECTS OF THE 8087 

The delay effects of the 8087 on IOPA can be signifi- 
cant. When executing special instructions (FSAVE, 
FNSAVE, FRSTOR), the 8087 can perform 50 or 06 
consecutive memory cycles with an 8086 or 8088 host, 
respectively. These instructions do not affect response 
time to local bus requests seen by an IOPB. 

If the 8087 is performing a series of memory cycles while 
executing these instructions, and IOPB requests the 
local bus, the 8087 will stop its current memory activity, 
then release the local bus to IOPB. 

The 8087 cannot release the bus to IOPA since it cannot 
know that IOPA wants to use the local bus, like it can 
for IOPB. 

REDUCING 8087 DELAY EFFECTS 

For 86/22 or 88/22 systems requiring lower maximum 
wait times for IOPA, it is possible to reduce the worst 
case bus usage of the 8087. If three 8087 instructions are 
never executed; namely FSAVE, FNSAVE, or 
FRSTOR, the maximum number of consecutive mem- 
ory cycles performed by the 8087 is 10 or 16 for an 8086 
, or 8088 host respectively. The function of these instruc- 
tions can be emulated with other 8087 instructions. 

Appendix B shows an example of how these three in- 
structions can be emulated. This improvment does have 
a cost, in the increased execution time of 427 or 747 ad- 



ditional clocks for an 8086 or 8088 respectively, for the 
equivalent save and restore operations. These opera- 
tions appear in time-critical context-switching functions 
of an operating system or interrupt handler. This tech- 
nique has no affect on the maximum wait time seen by 
IOPB or wait time seen by IOPA due to IOPB. 

Which IOP to connect to which I/O device in an 86/22 
or 88/22 system will depend on how quickly an I/O re- 
quest by the device must be serviced by the IOP. This 
maximum time must be greater than the sum of the 
maximum delay of the IOP and the maximum wait time 
to gain control of the local bus by the IOP. 

If neither IOP offers a fast enough response time, con- 
sider remote operation of the IOP. 

8087 INT Connection 

The next decision in adding the 8087 to an 8086 or 8088 
system is where to attach the INT signal of the 8087. 
The INT pin of the 8087 provides an external indication 
of software-selected numeric errors. The numeric pro- 
gram will stop until something is done about the error. 
Deciding where to connect the INT signal can have im- 
portant consequences on other interrupt handlers. 

WHAT ARE NUMERIC ERRORS? 

A numeric error occurs in the NPX whenever an opera- 
tion is attempted with invalid operands or attempts to 
produce a result which cannot be represented. If an in- 
correct or questionable operation is attempted by, a pro- 
gram, the NPX will always indicate the event. Examples 
of errors on the NPX are: 1/0, square root of - 1, and 
reading from an empty register. For a detailed descrip- 
tion of when the 8087 detects a numeric error, refer to 
the Numerics Supplement. (See Lit. Ref). 

WHAT TO DO ABOUT NUMERIC ERRORS 

Two possible courses of action are possible when a 
numeric error occurs. The, NPX can itself handle the 
error, allowing numeric program execution to continue 
undisturbed, or software in the host can handle the 
error. To have the 8087 handle a numeric error, set its 
associated mask bit in the NPX control word. Each 
numeric error may be individually masked. 

The NPX has a default fixup action defined for all pos- 
sible numeric errors when they are masked. The default 
actions were carefully selected, for their generality and 
safety. 

For example, the default fixup for the precision error is 
to round the result using the rounding rules currently in 
effect. If the invalid error is masked, the NPX will 
generate a special value called indefinite as the result of 
any invalid operation. 



3-16 



AM 13 



NUMERIC ERRORS (CO N'T) 

Any arithmetic operation with an indefinite operand 
will always generate an indefinite result. In this manner, 
the result of the original invalid operation will pro- 
pagate throughout the program wherever it is used. 

When a questionable operation such as multiplying an 
unnormal value by a normal value occurs, the NPX will 
signal this occurrence by generating an unnormal result. 

The required response by host software to a numeric 
error will depend on the application. The needs of each 
application must be understood when deciding on how 
to treat numeric errors. There are three attitudes 
towards a numeric error: 

1) No response required. Let the NPX perform the 
default fixup. 

2) Stop everything, something terrible has happened! 

3) Oh, not again! But don't disrupt doing something 
more important. 

SIMPLE ERROR HANDLING 

Some very simple applications may mask all of the 
numeric errors. In this simple case, the 8087 INT signal 
may be left unconnected since the 8087 will never assert 
this signal. If any numeric errors are detected during the 
course of executing the program, the NPX will generate 
a safe result. It is sufficient to test the final results of the 
calculation to see if they are valid. 

Special values like not-a-number (NAN), infinity, in- 
definite, denormals, and unnormals indicate the type 
and severity of earlier invalid or questionable opera- 
tions. 



The 8086 Family Numerics Supplement recommends 
masking all errors except invalid. (See Lit. Ref.). In this 
case the NPX will safely handle such errors as 
underflow, overflow, or divide by zero. Only truly ques- 
tionable operations will disturb the numerics program 
execution. 

An example of how infinities and divide by zero can be 
harmless occurs when calculating the parallel resistance 
of several values with the standard formula (Figure 12). 
If Rl becomes zero, the circuit resistance becomes 0. 
With divide by zero and precision masked, the NPX will 
produce the correct result. 

NUMERIC EXCEPTION HANDLING 

For some applications, a numeric error may not indicate 
a severe problem. The numeric error can indicate that a 
hardware resource has been exhausted, and the software 
must provide more. These cases are called exceptions 
since they do not normally arise. 

Special host software will handle numeric error excep- 
tions when they infrequently occur. In these cases, 
numeric exceptions are expected to be recoverable 
although not requiring immediate service by the host. In 
effect, these exceptions extend the functionality of the 
NDP. Examples of extensions are: normalized only 
arithmetic, extending the register stack to memory, or 
tracing special data values. 



SEVERE ERROR HANDLING 

For dedicated applications, programs should not gener- 
ate or use any invalid operands. Furthermore, all num- 
bers should be in range. An operand or result outside 
this range indicates a severe fault in the system. This 
situation may arise due to invalid input values, program 
error, or hardware faults. The integrity of the program 
and hardware is in question, and immediate action is re- 
quired. 

In this case, the INT signal can be used to interrupt the 
program currently running. Such an interrupt would be 
of high priority. The interrupt handler responsible for 
numeric errors might perform system integrity tests and 
then restart the system at a known, safe state. The 
handler would not normally return to the point of error. 

Unmasked numeric errors are very useful for testing 
programs. Correct use of synchronization, (Page 21), 
allows the programmer to find out exactly what 
operands, instruction, and memory values caused the 
error. Once testing has finished, an error then becomes 
much more serious. 



R 2 5 R 3 



Equivalent resistance = 



R-i + R2 + R3 



Figure 12. Infinity Arithmetic Example 



3-17 



AM13 



HOST INTERRUPT OVERVIEW 

The host has only two possible interrupt inputs, a non- 
maskable interrupt (NMI) and a maskable interrupt 
(INTR). Attaching the 8087 INT pin to the NMI input is 
not recommended. The following problems arise: NMI 
cannot be masked, it is usually reserved for more impor- 
tant functions like sanity timers or loss of power signal, 
and Intel supplied software for the NDP will not sup- 
port NMI interrupts. The INTR input of the host allows 
interrupt masking in the CPU, using an Intel 8259A 
Programmable Interrupt Controller (PIC) to resolve 
multiple interrupts, and has Intel support. 

NUMERIC INTERRUPT CHARACTERISTICS 

Numeric error interrupts are different from regular in- 
struction error interrupts like divide by zero. Numeric 
interrupts from the 8087 can occur long after the 
ESCAPE instruction that started the failing operation. 
For example, after starting a numeric multiply opera- 
tion, the host may respond to an external interrupt and 
be in the process of servicing it when the 8087 detects an 
overflow error. In this case the interrupt is a result of 
some earlier, unrelated program. 

From the point of view of the currently executing inter- 
rupt handler, numeric interrupts can cpme from only 
two sources: the current handler or a lower priority pro- 
gram. 



To explicitly disable numeric interrupts, it is recom- 
mended that numeric interrupts be disabled at the 8087. 
The code example Of Figure 13 shows how to disable 
any pending numeric interrupts then reenable them at 
the end of the handler. This code example can be safely 
placed in any routine which must prevent numeric inter- 
rupts from occurring. Note that the ESCAPE instruc- 
tions act as NOPs if an 8087 is not present in the system. 
It is not recommended to use numeric mnemonics since 
they may be converted to emulator calls, which run 
comparatively slow, if the 8087 emulator used. 

Interrupt systems have specific functions like fast 
response to external events or periodic execution of 
system routines. Adding an 8087 interrupt should not 
effect these functions. Desirable goals of any 8087 inter- 
rupt configuration are: 

— Hide numeric interrupts from interrupt handlers that 
don't use the 8087. Since they didn't cause the 
numeric interrupt why should they be interrupted? 

— Avoid adding code to interrupt handlers that don't 
use the 8087 to prevent interruption by the 8087. 

— Allow other higher priority interrupts to be serviced 
while executing a numeric exception handler. 

— Provide numeric exception handling for interrupt 
service routines which use the 8087. 

— Avoid deadlock as described in a later section 
(page 24) 



; Disable any possible numeric interrupt from the 8087. This code is safe to place in any 
; procedure. If an 8087 is not present, the ESCAPE instructions will act as nops. These 
; instructions are not affected by the TEST pin of the host. Using the 8087 emulator will not 
; convert these instructions into interrupts. A word variable, called control, is required to hold 
; the 8087 control word. Control must not be changed until it is reloaded into the 8087. 

ESC 15, control ; (FNSTCW) Save current 8087 control word 

NOP ; Delay while 8Q87 saves current control 

NOP ; register value 

ESC 28,cx ; (FNDISI) Disable any 8087 interrupts 

; Set IEM bit in 8087 control register 
; The contents of cx is irrelevant 
; Interrupts can now be enabled 

(Your Code Here) 

; Reenable any pending interrupts in the 8087. This instruction does not disturb any 8087 instruction 
; currently in progress since all it does is change the IEM bit in the control register. 

TEST control, 80H ; Look at IEM bit 

JNZ $ + 4 ; If IEM = 1 skip FNENI 

ESC 28,ax ; (FNENI) reenable 8087 interrupts 



Figure 13. Inhibit/Enable 8087 Interrupts 

3-18 



AM 13 



Recommended Interrupt Configurations 

Five categories cover most uses of the 8087 interrupt in 
fixed priority interrupt systems. For each category, an 
interrupt configuration is suggested based on the goals 
mentioned above. 

1. All errors on the 8087 are always masked. 
Numeric interrupts are not possible. Leave the 
8087 INT signal unconnected. 

2. The 8087 is the only interrupt in the system. Con- 
nect the 8087 INT signal directly to the host's 
INTR input. (See Figure 14 on page 19). A bus 
driver supplies interrupt vector 10 16 for com- 
patibility with Intel supplied software. 

3. The 8087 interrupt is a stop everything event. 
Choose a high priority interrupt input that will ter- 
minate all numerics related activity. This is a 
special case since the interrupt handler may never 
return to the point of interruption (i.e. reset the 
system and restart rather than attempt to continue 
operation). 

4. Numeric exceptions or numeric programming er- 
rors are expected and all interrupt handlers either 
don't use the 8087 or only use it with all errors 
masked. Use the lowest priority interrupt input. 
The 8087 interrupt handler should allow further 
interrupts by higher priority events. The PIC's 
priority system will automatically prevent the 8087 
from disturbing other interrupts without adding 
extra code to them. 



5. Case 4 holds except that interrupt handlers may 
also generate numeric interrupts. Connect the 8087 
INT signal to multiple interrupt inputs. One input 
would still be the lowest priority input as in case 4. 
Interrupt handlers that may generate a numeric in- 
terrupt will require another 8087 INT connection 
to the next highest priority interrupt. Normally the 
higher priority numeric interrupt inputs would be 
masked and the low priority numeric interrupt 
enabled. The higher priority interrupt input would 
be unmasked only when servicing an interrupt 
which requires 8087 exception handling. 

All of these configurations hide the 8087 from all inter- 
rupt handlers which do not use the 8087. Only those in- 
terrupt handlers that use the 8087 are required to per- 
form any special 8087 related interrupt control ac- 
tivities. 

A conflict can arise between the desired PIC interrupt 
input and the required interrupt vector of 10i$ for com- 
patibility with Intel software for numeric interrupts. A 
simple solution is to use more than one interrupt vector 
for numeric interrupts, all pointing at the same 8087 in- 
terrupt handler. Design the numeric interrupt handler 
such that it need not know what the interrupt vector was 
(i.e. don't use specific EOI commands). 

If an interrupt system uses rotating interrupt priorities, 
it will not matter which interrupt input is used. 



3-19 



AP-113 



| — IDI — | 



READY 


8284A 


RESET 


CLOCK 


GENERATOR 


CLK 





READY 






AID 




STATUS 


RESET 




808 


6 

INTR 


CLK 






TEST 


RQ/GT1 


QS 



or 



RQ/GTO 
READY 



8087 



-SYSTEM READY 



4 



r 



8288 D 

BUS 
CONTROLLER 



8286 

>E 

INT 
VECTOR 



0)8282 

ADDRESS 
LATCHES 



STB 



r 1 

I ADDRESS 



3 



(2) 8286 

DATA 
TRANSCEIVERS 



(System! 



Figure 14. iAPX 86/20 With Numerics Interrupt Only 



3-20 



AP'113 



GETTING STARTED IN SOFTWARE 

Now we are ready to run numeric programs. Developing 
numeric software will be a new experience to some pro- 
grammers. This section of the application note is aimed 
at describing the programming environment and pro- 
viding programming guidelines for the NPX. The term 
NPX is used to emphasize that no distinction is made 
between the 8087 component or an emulated 8087. 

Two major areas of numeric software can be identified: 
systems software and applications software. Products 
such as iRMX™ 86 provide system software as an off- 
the-shelf product. Some applications use specially 
developed systems software optimized to their needs. 

Whether the system software is specially tailored or 
common, they share issues such as using concurrency, 
maintaining synchronization between the host and 8087, 
and establishing programming conventions. Appli- 
cations software directly performs the functions of the 
application. All applications will be concerned with ini- 
tialization and general programming rules for the NPX. 
Systems software will be more concerned with context 
switching, use of the NPX by interrupt handlers, and 
numeric exception handlers. 

How to Initialize the NPX 

The first action required by the NPX is initialization. 
This places the NPX in a known state, unaffected by 
other activity performed earlier. This initialization is 
similar to that caused by the RESET signal of the 8087. 
All the error masks are set, all registers are tagged 
empty, the TOP field is set to 0, default rounding, pre- 
cision, and infinity controls are set. The 8087 emulator 
requires more initialization than the component. Before 
the emulator may be used, all its interrupt vectors must 
be set to point to the correct entry points within the 
emulator. 

To provide compatibility between the emulator and 
component in this special case, a call to an external pro- 
cedure should be used before the first numeric instruc- 
tion. In ASM86 the programmer must call the external 
function INIT87. (Fig. 15). For PLM86, the 
programmer must call the built-in function 
INIT$REAL$MATH$UNIT. PLM86 will call INIT87 
when executing the INIT$REAL$MATH$UNIT built- 
in function. 

The function supplied for INIT87 will be different, 
depending on whether the emulator library, called 
E8087.LIB, or component library, called 8087.LIB, 
were used at link time. INIT87 will execute either an 
FNINIT instruction for the 8087 or initialize the 8087 
emulator interrupt vectors, as appropriate. 



Concurrency Overview 

With the NPX initialized, the next step in writing a 
numeric program is learning about concurrent execution 
within the NDP. 

Concurrency is a special feature of the 8087, allowing it 
and the host to simultaneously execute different instruc- 
tions. The 8087 emulator does not provide concurrency 
since it is implemented by the host. 

The benefit of concurrency to an application is higher 
performance. All Intel high level languages automatic- 
ally provide for and manage concurrency in the NDP. 
However, in exchange for the added performance, the 
assembly language programmer must understand and 
manage some areas of concurrency. This section is for 
the assembly language programmer or well-informed, 
high level language programmer. 

Whether the 8087 emulator or component is used, care 
should be taken by the assembly language programmer 
to follow the rules described below regarding synchro- 
nization. Otherwise, the program may not function cor- 
rectly with current or future alternatives for implement- 
ing the NDP. 

Concurrency is possible in the NDP because both the 
host and 8087 have separate arithmetic and control 
units. The host and coprocessor automatically decide 
who will perform any single instruction. The existence 
of the 8087 as a separate unit is not normally apparent. 

Numeric instructions, which will be executed by the 
8087, are simply placed in line with the instructions for 
the host. Numeric instructions are executed in the same 
order as they are encountered by the host in its instruc- 
tion stream. Since operations performed by the 8087 
generally require more time than operations performed 
by the host, the host can execute Several of its instruc- 
tions while the 8087 performs one numeric operation. 



IN PLM86: 




CALL INIT$REAL$MATH$UNIT; 


IN ASM 86: 




EXTRN 
• 
• 


INIT87:FAR 


• 
• 

CALL 


INIT87 



Figure 15. 8087 Initialization 



3-21 



AM 13 



MANAGING CONCURRENCY 

Concurrent execution of the host and 8087 is easy to 
establish and maintain. The activities of numeric pro- 
grams can be split into two major areas: program con- 
trol and arithmetic. The program control part performs 
activities like deciding what functions to perform, calcu- 
lating addresses of numeric operands, and loop control. 
The arithmetic part simply performs the adds, sub- 
tracts, multiplies, and other operations on the numeric 
operands. The NPX and host are designed to handle 
these two parts separately and efficiently. 

Managing concurrency is necessary because the arithme- 
tic and control areas must converge to a well-defined 
state when starting another numeric operation. A well- 
defined state means all previous arithmetic and control 
operations are complete and valid. 

Normally, the host waits for the 8087 to finish the cur- 
rent numeric operation before starting another. This 
waiting is called synchronization. 

Managing concurrent execution of the 8087 involves 
three types of synchronization: instruction, data, and 
error. Instruction and error synchronization are 
automatically provided by the compiler or assembler. 
Data synchronization must be provided by the assembly 
language progammer or compiler. 



Instruction Synchronization 

Instruction synchronization is required because the 8087 
can only perform one numeric operation at a time. Be- 
fore any numeric operation is started, the 8087 must 
have completed all activity from previous instructions. 

The WAIT instruction on the host lets it wait for the 
8087 to finish all numeric activity before starting an- 
other numeric instruction. The assembler automatically 
provides for instruction synchronization since a WAIT 
instruction is part of most numeric instructions. A 
WAIT instruction requires 1 byte code space and 2.5 
clocks average execution time overhead. 

Instruction synchronization as provided by the assem- 
bler or a compiler allows concurrent operation in the 
NDP. An execution time comparison of NDP concur- 
rency and non-concurrency is illustrated in Figure 16. 
The non-concurrent program places a WAIT instruction 
immediately after a multiply instruction ESCAPE in- 
struction. The 8087 must complete the multiply opera- 
tion before the host executes the MOV instruction on 
statement 2. In contrast, the concurrent example allows 
the host to calculate the effective address of the next 
operand while the 8087 performs the multiply. The ex- 
ecution time of the concurrent technique is the longest 
of the host's execution time from line 2 to 5 and the ex- 
ecution time of the 8087 for a multiply instruction. The 
execution time of the non-concurrent example is the 
sum of the execution times of statements 1 to 5. 



; This code macro defines two instructions which do not allow any concurrency of execution with 
; the host. A register version and memory version of the instruction is shown. It is assumed that the 
; 8087 is always idle from the previous instruction. Allow space for emulator fixups. 
> 

R233 Record RF6:2, Mid3:3, RF7:3 

CodeMacro NCMUL dst:T, src:F 

RNfix 000B 

R233 (11B, 001 B, src) 

RWfix 

EndM 

CodeMacro NCMUL memop:Mq 
RNfixM 100B, memop 
ModRM 001 B, memop 
RWfix 
EndM 



Statement Concurrent Non Concurrent 

1 FMUL st(0),st(1) NCMUL st(0), st(1) 

2 MOV ax, size A MOV ax, size A 

3 MUL index MUL index 

4 MOV bx, ax MOV bx, ax 

5 FMUL A[bx] NCMUL A [bx] 



Figure 16. Concurrent Versus Non-Concurrent Program 

3-22 



AP-113 



Data Synchronization 

Managing concurrency requires synchronizing data ref- 
erences by the host and 8087. 

Figure 17 shows four possible cases of the host and 8087 
sharing a memory value. The second two cases require 
the FWAIT instruction shown for data synchronization. 
In the first two cases, the host will finish with the 
operand I before the 8087 can reference it. The 
coprocessor interface guarantees this. In the second two 
cases, the host must wait for the 8087 to finish with the 
memory operand before proceeding to reuse it. The 
FWAIT instruction in case 3 forces the host to wait for 
the 8087 to read I before changing it. In case 4, the 
FWAIT prevents the host from reading I before the 
8087 sets its value. 

Obviously, the programmer must recognize any form of 
the two cases shown above which require explicit data 
synchronization. Data synchronization is not a concern 
when the host and 8087 are using different memory 
operands during the course of one numeric instruction. 
Figure 16 shows such an example of the host performing 
activity unrelated to the current numeric instruction 
being executed by the 8087. Correct recognition of these 
cases by the programmer is the price to be paid for pro- 
viding concurrency at the assembly language level. 

Automatic Data Synchronization 

Two methods exist to avoid the need for manual recog- 
nition of when data synchronization is needed: use a 
high level language which will automatically establish 
concurrency and manage it, or sacrifice some perfor- 
mance for automatic data synchronization by the as- 
sembler. 

When a high level language is not adequate, the 
assembler can be changed to always place a WAIT in- 
struction after the ESCAPE instruction. Figure 18 
shows an example of how to change the ASM86 code 
macro for the FIST instruction to automatically place 
an FWAIT instruction after the ESCAPE instruction. 
The lack of any possible concurrent execution between 
the host and 8087 while the FIST instruction is executing 
is the price paid for automatic data synchronization. 

An explicit FWAIT instruction for data synchroniza- 
tion, can be eliminated by using a subsequent numeric 
instruction. After this subsequent instruction has 
started execution, all memory references in earlier 
numeric instructions are complete. Reaching the next 
host instruction after the synchronizing numeric instruc- 
tion indicates previous numeric operands in memory are 
available. 



The data synchronization purpose of any FWAIT or 
numeric instruction must be well documented. Other- 
wise, a change to the program at a later time may 
remove the synchronizing numeric instruction, causing ' 
program failure, as: 

FISTP I 
FMUL 

MOV AX, I ; I is safe to use 



Case 1: 


Case 3: 




MOV I, 1 


FILD 


I 


FILD I 


FWAIT 






MOV 


1, 5 


Case 2: 


Case 4: 




MOV AX, I 


FISTP 


I 


FISTP I 


FWAIT 






MOV 


AX,I 



Figure 17. Data Exchange Example 



Figure 18. Non-Concurrent FIST instruction 
Code Macro 



; This is a code macro to redefine the FIST 
; instruction to prevent any concurrency 
; while the instruction runs. A wait 
; instruction is placed immediately after the 
; escape to ensure the store is done 
; before the program may continue. This 
; code macro will work with the 8087 
; emulator, automatically replacing the 
; wait escape with a nop. 

CodeMacro FIST memop: Mw 
RfixM 111B, memop 
ModRM 010B, memop 
RWfix 
EndM 



3-23 



AP-113 



DATA SYNCHRONIZATION RULES EXCEPTIONS 

There are five exceptions to the above rules for data syn- ' 
chronization. The 8087 automatically provides data syn- 
chronization for these cases. They are necessary to 
avoid deadlock (described on page 24). The instructions 
FSTSW/FNSTSW, FSTCW/FNSTCW, FLDCW, 
FRSTOR, and FLDENV do not require any waiting by 
the host before it may read or modify the referenced 
memory location. 

The 8087 provides the data synchronization by prevent- 
ing the host from gaining control of the local bus while 
these instructions execute. If the host cannot gain con- 
trol of the local bus, it cannot change a value before the 
8087 reads it, or read a value before the 8087 writes into 
it. 

The coprocessor interface guarantees that, when the 
host executes one of these instructions, the 8087 will 
immediately request the local bus from the host. This 
request is timed such that, when the host finishes the 
read operation identifying the memory operand, it will 
always grant the local bus to the 8087 before the host 
may use the local bus for a data reference while execut- 
ing a subsequent instruction. The 8087 will not release 
the local bus to the host until it has finished executing 
the numeric instruction. 



Error Synchronization 

Numeric errors can occur on almost any numeric in- 
struction at any time during its execution. Page 15 
describes how a numeric error may have many inter- 
pretations, depending on the application. Since the re- 
sponse to a numeric error will depend on the applica- 
tion, this section covers topics common to all uses of the 
NPX. We will review why error synchronization is need- 
ed and how it is provided. 

Concurrent execution of the host and 8087 requires syn- 
chronization for errors just like data references and 
numeric instructions. In fact, the synchronization re- 
quired for data and instructions automatically provides 
error synchronization. 

However, incorrect data or instruction synchronization 
may not cause a problem until a numeric error occurs. A 
further complication is that a programmer may not ex- 
pect his numeric program to cause numeric errors, but 
in some systems they may regularly happen. To better 
understand these points, let's look at what can happen 
when the NPX detects an error. 



ERROR SYNCHRONIZATION FOR EXTENSIONS 

The NPX can provide a default fixup for all numeric 
errors. A program can mask each individual error type 
to indicate that the NPX should generate a safe, reason- 
able result. The default error fixup activity is simply 
treated as part of the instruction which caused the error. 
No external indication of the error will be given. A flag 
in the numeric status register will be set to indicate that 
an error was detected, but no information, regarding 
where or when will be available. 

If the NPX performs its default action for all errors, 
then error synchronization is never exercised. But this is 
no reason to ignore error synchronization. 

Another alternative exists to the NPX default fixup of 
an error. If the default NPX response to numeric errors 
is not desired, the host can implement any form of re- 
covery desired for any numeric error detectable by the 
NPX. When a numeric error is unmasked, and the error 
occurs, the NPX will stop further execution of the 
numeric instruction. The 8087 will signal this event on 
the INT pin, while the 8087 emulator will cause inter- 
rupt 10i 6 to occur. The 8087 INT signal is normally con- 
nected to the host's interrupt system. Refer to page 18 
for further discussion on wiring the 8087 INT pin. 

Interrupting the host is a request from the NPX for 
help. The fact that the error was unmasked indicates 
that further numeric program execution under the arith- 
metic and programming rules of the NPX is unreason- 
able. Error synchronization serves to insure the NDP is 
in a well defined state after an unmasked numeric error 
occured. Without a well defined state, it is impossible to 
figure out why the error occured. 

Allowing a correct analysis of the error is the heart of 
error synchronization. 

NDP ERROR STATES 

If concurrent execution is allowed, the state of the host 
when it recognizes the interrupt is undefined. The host 
may have changed many of its internal registers and be 
executing a totally different program by the time it is in- 
terrupted. To handle this situation, the NPX has special 
registers updated at the start of each numeric instruction 
to describe the state of the numeric program when the 
failed instruction was attempted. (See Lit. Ref. p. iii) 

Besides programmer comfort, a well-defined state is im- 
portant for error recovery routines. They can change the 
arithmetic and programming rules of the 8087. These 
changes may redefine the default flxup from an error, 
change the appearance of the NPX to the programmer, 
or change how arithmetic is defined on the NPX. 



3-24 



AP-113 



EXTENSION EXAMPLES 

A change to an error response might be to automatically 
normalize all denormals loaded from memory. A 
change in appearance might be extending the register 
stack to memory to provide an "infinite" number of 
numeric registers. The arithmetic of the 8087 can be 
changed to automatically extend the precision and range 
of variables when exceeded. All these functions can be 
implemented on the NPX via numeric errors and 
associated recovery routines in a manner transparent to 
the programmer. 

Without correct error synchronization, numeric 
subroutines will not work correctly in the above situa- 
tions. 

Incorrect Error Synchronization 

An example of how some instructions written without 
error synchronization will work initially, but fail when 
moved into a new environment is: 

FILD COUNT 
INC COUNT 
FSQRT 

Three instructions are shown to load an integer, calcu- 
late its square root, then increment the integer. The 
coprocessor interface of the 8087 and synchronous ex- 
ecution of the 8087 emulator will allow this program to 
execute correctly when no errors occur on the FILD in- 
struction. 

But, this situation changes if the numeric register stack 
is extended to memory on an 8087. To extend the NPX 
stack to memory, the invalid error is unmasked. A push 
to a full register or pop from an empty register will 
cause an invalid error. The recovery routine for the er- 
ror must recognize this situation, fixup the stack, then 
perform the original operation. 

The recovery routine will not work correctly in the ex- 
ample. The problem is that there is no guarantee that 
COUNT will not be incremented before the 8087 can in- 
terrupt the host. If COUNT is incremented before the 
interrupt, the recovery routine will load a value of 
COUNT one too large, probably causing the program to 
fail. 

Error Synchronization and WAITs 

Error synchronization relies on the WAIT instructions 
required by instruction and data synchronization and 
the INT and BUSY signals Of the 8087. When an un- 
masked error occurs in the 8087, it asserts the BUSY 
and INT signals. The INT signal is to interrupt the host, 
while the BUSY signal prevents the host from destroy- 
ing the current numeric context. 



The BUSY signal will never go inactive during a numeric 
instruction which asserts INT. 

The WAIT instructions supplied for instruction syn- 
chronization prevent the host from starting another 
numeric instruction until the current error is serviced. In 
a like manner, the WAIT instructions required for data 
synchronization prevent the host from prematurely 
reading a value not yet stored by the 8087, or over- 
writing a value not yet read by the 8087. 

The host has two responsibilities when handling 
numeric errors. 1.) It must not disturb the numeric con- 
text when an error is detected, and 2.) it must clear the 
numeric error and attempt recovery from the error. The 
recovery program invoked by the numeric error may 
resume program execution after proper fixup, display 
the state of the NDP for programmer action, or simply 
abort the program. In any case, the host must do 
something with the 8087. With the INT and BUSY 
signals active, the 8087 cannot perform any useful 
work. Special instructions exist for controlling the 8087 
when in this state. Later, an example is given of how to 
save the state of the NPX with an error pending. (See 
page 29) 



Deadlock 

An undesirable situation may result if the host cannot 
be interrupted by the 8087 when asserting INT. This sit- 
uation, called deadlock, occurs if the interrupt path 
from the 8087 to the host is broken. 

The 8087 BUSY signal prevents the host from executing 
further instructions (for instruction or data syn- 
chronization) while the 8087 waits for the host to service 
the exception. The host is waiting for the 8087 to finish 
the current numeric operation. Both the host and 8087 
are waiting on each other. This situation is stable unless 
the host is interrupted by some other event. 

Deadlock has varying affects on the NDP's perfor- 
mance. If no other interrupts in the system are possible, 
the NDP will wait forever. If other interrupts can arise, 
then the NDP can perform other functions, but the af- 
fected numeric program will remain "frozen". 

SOLVING DEADLOCK 

Finding the break in the interrupt path is simple. Look 
for disabled interrupts in the following places: masked 
interrupt enable in the host, explicitly masked interrupt 
request in the interrupt controller, implicitly masked in- 
terrupt request in the interrupt controller due to a higher 
priority interrupt in service, or other gate functions, 
usually in TTL, on the host interrupt signal. 



3-25 



AP-113 



DEADLOCK AVOIDANCE 

Application programmers should not be concerned with 
deadlock. Normally, applications programs run with 
unmasked numeric errors able to interrupt them. Dead- 
lock is not possible in this case. Traditionally , ; systems 
software or interrupt handlers may run with numeric in- 
terrupts disabled. Deadlock prevention lies in this do- 
main. The golden rule to abide by is: "Never wait on the 
8087 if an unmasked error is possible and the 8087 inter- 
rupt path may be broken." 

Error Synchronization Summary 

In summary, error synchronization involves protecting 
the state of the 8087 after an exception. Although not all 
applications may initially require error synchronization, 
it is just good programming practice to follow the rules. 
The advantage of being a "good** numerics program- 
mer is generality of your program so it can work in 
other, more general environments. 

Summary 

Synchronization is the price for concurrency in the 
NDP. Intel high level language compilers will auto- 
matically provide concurrency and manage it with syn- 
chronization. The assembly language programmer can 
choose between using concurrency or not. Placing a 
WAIT instruction immediately after any numeric in- 
struction will prevent concurrency and avoid synchro- 
nization concerns. 

The rules given above are complete and allow concur- 
rency to be used to full advantage. 

Synchronization and the Emulator 

The above discussion on synchronization takes on 
special meaning with the 8087 emulator. The 8087 emu- 
lator does not allow any concurrency. All numeric 
operand memory references, error tests, and wait for 
instruction completion occur within the emulator. As a 
result, programs which do not provide proper instruc- 
tion, data, or error synchronization may work with the 
8087 emulator while failing on the component. 

Correct programs for the 8087 work correctly on the 
emulator. 

Special Control Instructions of the NPX 

The special control instructions of the NPX: FNINIT, 
FNSAVE, FNSTENV, FRSTOR, FLDENV, FLDCW, 
FNSTSW, FNSTCW, FNCLEX, FNENI, and FNDISI 
remove some of the synchronization requirements men- 
tioned earlier. They are discussed here since they repre- 
sent exceptions to the rules mentioned on page 21 . 

The instructions FNINIT, FNSAVE, FNSTENV, 
FNSTSW, FNCLEX, FNENI, and FNDISI do not wait 



for the current numeric instruction to finish before they 
execute. Of these instructions, FNINIT, FNSTSW, 
FNCLEX, FNENI and FNDISI will produce different 
results, depending on when they are executed relative to 
the current numeric instruction. 

For example, FNCLEX will cause a different status 
value to result from a concurrent arithmetic operation, 
depending on whether is is executed before or after the 
error status bits are updated at the end of the arithmetic 
operation. The intended use of FNCLEX is to clear a 
known error status bit which has caused BUSY to be 
asserted, avoiding deadlock. 

FNSTSW will safely, without deadlock, report the busy 
and error status of the NPX independent of the NDP in- 
terrupt status. 

FNINIT, FNENI, and FNDISI are used to place the 
NPX into a known state independent of its current 
state. FNDISI will prevent an unmasked error from 
asserting BUSY without disturbing the current error 
status bits. Appendix A shows an example of using 
FNDISI. 

The instructions FNSAVE and FNSTENV provide spe- 
cial functions. They allow saving the state of the NPX in 
a single instruction when host interrupts are disabled. 

Several host and numeric instructions are necessary to 
save the NPX status if the interrupt status of the host is 
unknown. Appendix A and B show examples of saving 
the NPX state. As the Numerics Supplement explains, 
host interrupts must always be disabled when executing 
FNSAVE or FNSTENV. 

The seven instructions FSTSW/FNSTSW, FSTCW/ 
FNSTCW, FLDCW, FLDENV, and FRSTOR db not 
require explicit WAIT instructions for data synchro- 
nization. All of these instructions are used to interrogate 
or control the numeric context. 

Data synchronization for these instructions is 
automatically provided by the coprocessor interface. 
The 8087 will take exclusive control of the memory bus, 
preventing the host from interfering with the data values 
before the 8087 can read them. Eliminating the need for 
a WAIT instruction avoids potential deadlock pro- 
blems. 

The three load instructions FLDCW, FLDENV, and 
FRSTOR can unmask a numeric error, activating the 
8087 BUSY signal. Such an error was the result of a 
previous numeric instruction and is not related to any 
fault in the instruction. 

Data synchronization is automatically provided since 
the host's interrupts are usually disabled in context swit- 
ching or interrupt handling, deadlock might result if the 
host executed a WAIT instruction with its interrupts 
disabled after these instructions. After the host inter- 
rupts are enabled, an interrupt will occur if an unmask- 
ed error Was pending. 



3-26 



AP-113 



PROGRAMMING TECHNIQUES 

The NPX provides a stack-oriented register set with 
stack-oriented instructions for numeric operands. These 
registers and instructions are optimized for numeric 
programs. For many programmers, these are new re- 
sources with new programming options available. 

Using Numeric Registers and 
Instructions 

The register and instruction set of the NDP is optimized 
for the needs of numeric and general purpose programs. 
The host CPU provides the instructions and data types 
needed for general purpose data processing, while the 
8087 provides the data types and instructions for 
numeric processing. 

The instructions and data types recognized by the 8087 
are different from the CPU because numeric program 
requirements are different from those of general pur- 
pose programs. Numeric programs have long arithmetic 
expressions where a few temporary values are used in a 
few statements. Within these statements, a single value 
may be referenced many times. Due to the time involved 
to transfer values between registers and memory, a 
significant speed optimization is possible by keeping 
numbers in the NPX register file. 

In contrast, a general data processor is more concerned 
with addressing data in simple expressions and testing 
the results. Temporary values, constant across several 
instructions, are not as common nor is the penalty as 
large for placing them in memory. As a result it is 
simpler for compilers and programmers to manage 
memory based values. 



NPX Register UsagS 

The eight numeric registers in the NDP are stack ori- 
ented. All numeric registers are addressed relative to a 
value called the TOP pointer, defined in the NDP status 
register. A register address given in an instruction is ad- 
ded to the TOP value to form the internal absolute ad- 
dress. Relative addressing of numeric registers has ad- 
vantages analogous to those of relative addressing of 
memory operands. 

Two modes are available for addressing the numeric 
registers. Hie first mode implicitly uses the top and op- 
tional next element on the stack for operands. This 
mode does not require any addressing bits in a numeric 
instruction. Special purpose instructions use this mode 
since full addressing flexibility is not required. 

The other addressing mode allows any other stack ele- 
ment to be used together with the top of stack register. 
The top of stack or the other register may be specified as 
the destination. Most two-operand arithmetic instruc- 
tions allow this addressing mode. Short, easy to develop 
numeric programs are the result. 

Just as relative addressing of memory operands avoids 
concerns with memory allocation in other parts of a 
program, top relative register addressing allows registers 
to be used without regard for numeric register assign- 
ments in other parts of the program. 

STACK RELATIVE ADDRESSING EXAMPLE 

Consider an example of a main program calling a 
subroutine, each using register addressing independent 
of the other, (Fig. 19) By using different values of the 
TOP field, different software can use the same relative 
register addresses as other parts of the program, but 
refer to different physical registers. 



MAIN_PROGRAM: 




FLD 






FADD 


•ST, ST(1) 




CALL 


SUBROUTINE 


; Argument is in ST(0) 


FSTP 


B 




SUBROUTINE: 






FLD 


ST 


; ST<0) = ST(1) = Argument 


FSQRT 




; Main program ST(1) is 


FADD 


C 


; safe in ST(2) here 


FMULP 


ST(1), ST 




RET 







Figure 19. Stack Relative Addressing Example 



3-27 



AP-113 



Of course, there is a limit tolny physical resource. The 
NDP has eight numeric registers. Normally, program- 
mers must ensure a maximum of eight values are pushed 
on the numeric register stack at any time. For time- 
critical inner loops of real-time applications, eight regis- 
ters should contain all the values needed. 

REGISTER STACK EXTENSION 

This hardware limitation can be hidden by software. 
Software can provide "virtual* ' numeric registers, ex- 
panding the register stack size to 6000 or more. 

The numeric register stack can be extended into memory 
via unmasked numeric invalid errors which cause an in- 
terrupt on stack overflow or underflow. The interrupt 
handler for the invalid error would manage a memory 
image of the numeric stack copying values into and out 
of memory as needed. 

The NPX will contain all the necessary information to 
identify the error, failing instruction, required registers, 
and destination register. After correcting for the missing 
hardware resource, the original numeric operation 
could be repeated. Either the original numeric instruc- 
tion could be single stepped or the affect of the instruc- 
tion emulated by a composite of table-based numeric in- 
structions executed by the error handler. 

With proper data, error, and instruction synchroniza- 
tion, the activity of the error handler will be transparent 
to programs. This type of extension to the NDP allows 
programs to push and pop 'numeric registers without 
regard for their usage by other subroutines. 

Programming Conventions 

With a better understanding of the stack registers, let's 
consider some useful programming conventions. Fol- 
lowing these conventions ensures compatibility with 
Intel support software and high level language calling 
conventions. 

1) If the numeric registers are not extended to 
memory, the programmer must ensure that the 
number of temporary values left in the NPX stack 
and those registers used by the caller does not exceed 
8. Values can be stored to memory to provide enough 
free NPX registers. 

2) Pass the first seven numeric parameters to a subrou- 
tine in the numeric stack registers. Any extra param- 
eters can be passed on the host's stack. Push the 
values on the register or memory stack in left to right 
order. If the subroutine does not need to allocate any 
more numeric registers, it can execute solely out of 
the numeric register stack. The eighth register can be 
used for arithmetic operations. All parameters 
should be popped off when the subroutine com- 
pletes. 



3) Return all numeric values on the numeric stack. The 
caller may now take advantage of the extended preci- 
sion and flexible store modes of the NDP. 

4) Finish all memory reads or writes by the NPX before 
exiting any subroutine. This guarantees correct data 
and error synchronization. A numeric operation 
based solely on register contents is safe to leave run- 
ning on subroutine exit. 

5) The operating mode of the NDP should be transpar- 
ent across any subroutine. The operating mode is 
defined by the control word of the NDP. If the sub- 
routine needs to use a different numeric operating 
mode than that of the caller, the subroutine should 
first save the current control word^ set the new oper- 
ating mode, then restore the original control word 
when completed. 



PROGRAMMING EXAMPLES 

The last section of this application note will discuss five 
programming examples. These examples were picked to 
illustrate NDP programming techniques and commonly 
used functions. All have been coded, assembled, and 
tested. However, no guarantees are made regarding 
their correctness. 

The programming examples are: saving numeric 
context switching, save numeric context without 
FSAVE/FNSAVE, converting ASCII to floating point, 
converting floating point to ASCII, and trigonometric 
functions. Each example is listed in a different appendix 
with a detailed written description in the following text. 
The source code is available in machine readable form 
from the Intel Insite User's Library, "Interactive 8087 
Instruction Interpreter," catalog item AA20. 

The examples provide some basic functions needed to 
get started with the numeric data processor. They work 
with either the 8087 or the 8087 emulator with no source 
changes. 

The context switching examples are needed for 
operating systems or interrupt handlers which may use 
numeric instructions and operands. Converting between 
floating point and decimal ASCII will be needed to in- 
put or output numbers in easy to read form. The trigo- 
nometric examples help you get started with sine or 
cosine functions and can serve as a basis for optimiza- 
tions if the angle arguments always fall into a restricted 
range. 



3-28 



AM 13 



APPENDIX A 



OVERVIEW 

Appendix A shows deadlock-free examples of numeric 
context switching. Numeric context switching is re- 
quired by interrupt handlers which use the NPX and 
operating system context switchers. Context switching 
consists of. two basic functions, save the numeric con- 
text and restore it. These functions must work indepen- 
dent of the current state of the NPX. 

Two versions of the context save function are shown. 
They use different versions of the save context instruc- 
tion. The FNSAVE/FSAVE instructions do all the work 
of saving the numeric context. The state of host inter- 
rupts will decide which instruction to use. 

Using FNSAVE 

The FNSAVE instruction is intended to save the NPX 
context when host interrupts are disabled. The host does 
not have to wait for the 8087 to finish its current opera- 
tion before starting this operation. Eliminating the in- 
struction synchronization wait avoids any potential 
deadlock. 

The 8087 Bus Interface Unit (BIU) will save this instruc- 
tion when encountered by the host and hold it until the 
8087 Floating point Execution Unit (FEU) finishes its 
current operation. When the FEU becomes idle, the 
BIU will start the FEU executing the save context opera- 
tion. 

The host can execute other non-numeric instructions 
after the FNSAVE while the BIU waits for the FEU to 
finish its current operation. The code starting at 
NO_JNT_NPX_SAVE shows how to use the 
FNSAVE instruction. 

When executing the FNSAVE instruction, host inter- 
rupts must be disabled to avoid recursions of the in- 
struction. The 8087 BIU can hold only one FNSAVE in- 
struction at a time. If host interrupts were not disabled, 
another host interrupt might cause a second FNSAVE 
instruction to be executed, destroying the previous one 
saved in the 8087 BIU. 

It is not recommended to explicitly disable host inter- 
rupts just to execute an FNSAVE instruction. In 
general, such an operation may not be the best course of 
action or even be allowed. 

If host interrupts are enabled during the NPX context 
save function, it is recommended to use the FSAVE in- 
struction as shown by the code starting at NPX__SAVE. 
This example will always work, free of deadlock, in- 
dependent of the NDP interrupt state. 



Using FSAVE 

The FSAVE instruction performs the same operation as 
FNSAVE but it uses standard instruction synchroniza- 
tion. The host will wait for the FEU to be idle before 
initiating the save operation. Since the host ignores all 
interrupts between completing a WAIT instruction and 
starting the following ESCAPE instruction, the FEU is 
ready to immediately accept the operation (since it is not 
signalling BUSY). No recursion of the save context 
operation in the BIU is possible. However, deadlock 
must be considered since the host executes a WAIT in- 
struction. 

To avoid deadlock when using the FSAVE instruction, 
the 8087 must be prevented from signalling BUSY when 
an unmasked error exists. 

The Interrupt Enable Mask (IEM) bit in the NPX con- 
trol word provides this function. When IEM=1, the 
8087 will not signal BUSY or INT if an unmasked error 
exists. The NPX instruction FNDISI will set the IEM in- 
dependent of any pending errors without causing 
deadlock or any other errors. Using the FNDISI and 
FSAVE instructions together with a few other glue in- 
structions allows a general NPX context save function. 

Standard data and instruction synchronization is re- 
quired after executing the FNSAVE/FSAVE instruc- 
tion. The wait instruction following an FNSAVE/ 
FSAVE instruction is always safe since all NPX errors 
will be masked as part of the instruction execution. 
Deadlock is not possible since the 8087 will eventually 
signal not busy, allowing the host to continue on. 



PLACING THE SAVE CONTEXT FUNCTION 

Deciding on where to save the NPX context in an inter- 
rupt handler or context switcher is dependent on 
whether interrupts can be enabled inside the function. 
Since interrupt latency is measured in terms of the max- 
imum time interrupts are disabled, the maximum wait 
time of the host at the data synchronizing wait instruc- 
tion after the FNSAVE or the FSAVE instruction is im- 
portant if host interrupts are disabled while waiting. 

The wait time will be the maximum single instruction 
execution time of the 8087 plus the execution time of the 
save operation. This maximum time will be approxi- 
mately 1300 or 1500 clocks, depending on whether the 
host is an 8086 or 8088, respectively. The actual time 
will depend oh how much concurrency of execution bet- 
ween the host and 8087 is provided. The greater the 
concurrency, the lesser the maximum wait time will be. 



3-29 



AM 13 



If host interrupts can be enabled during the context save 
function, it is recommended to use the FSAVE instruc- 
tion for saving the numeric context in the interruptable 
section. The FSAVE instruction allows instruction and 
data synchronizing waits to be interruptable. This 
technique removes the maximum execution time of 8087 
instructions from system interrupt latency time con- 
siderations. 

It is recommended to delay starting the numeric save 
function as long as possible to maintain the maximum 
amount of concurrent execution between the host and 
the 8087. 



NPX_save 



Using FRSTOR 

Restoring the numeric context with FRSTOR does not 
require a data synchronizing wait afterwards since the 
8087 automatically prevents the host from interfering 
with the memory load operation. 

The code starting with NPX^RESTORfi illustrates the 
restore operation. Error synchronization is not 
necessary since the FRSTOR instruction itself does not 
cause errors, but the previous state of the NPX may in- 
dicate an error. 

If further numeric instructions are executed after the 
FRSTOR, and the error state of the new NPX context is 
unknown, deadlock may occur if numeric exceptions 
cannot interrupt the host. 



; General purpose save of NPX context. This function will work independent of the interrupt state of 


; the NDP. Deadlock can not occur. 47 words of memory are required by the variable save___area. 


; Register ax is not transparent across this code. • 


NPX_save: 




Save I EM bit status 


FNSTCW 


save_area 


NOP 




Delay while 8087 saves control register 


FNDISI 




Disable 8087 BUSY signal 


MOV 


ax, save_area 


Get original control word 


FSAVE 


save_area 


Save NPX context, the host can be safely interrupted while 






waiting for the 8087 to finish. Deadlock is not possible since 


FWAIT 




IEM = LWait for save to finish. Put original control word into 


MOV 


save_area, ax 


NPX context area. All done 



no_int_NPX_save 



Save the NPX context with host interrupts disabled. No deadlock is possible. 47 words of memory 
are required by the variable save_area. 



no_i nt_N PX_save: 

FNSAVE save_area 
FWAIT 



; Save NPX context. Wait for save to finish, no deadlock 
; is possible. Interrupts may be enabled now, all done 



NPX„restore 



Restore the NPX context saved earlier. No deadlock is possible if no further numeric instructions 
are executed until the 8087 numeric error interrupt is enabled. The variable save_area is assumed 
to hold an NPX context saved earlier. It must be 47 words long. 



NPX_restore: 
FRSTOR 



save_area 



Load new NPX context 



3-30 



AM 13 



APPENDIX B 



OVERVIEW 

Appendix B shows alternative techniques for switching 
the numeric context without using the FSAVE/ 
FNSAVE or FRSTOR instructions. These alternative 
techniques are slower than those of Appendix A but 
they reduce the worst case continuous local bus usage of 
the 8087. 

Only an iAPX 86/22 or iAPX 88/22 could derive any 
benefit from this alternative. By replacing all 
FSAVE/FNSAVE instructions in the system, the worst 
case local bus usage of the 8087 will be 10 or 16 con- 
secutive memory cycles for an 8086 or 8088 host, respec- 
tively. 

Instead of saving and loading the entire numeric context 
in one long series of memory transfers, these routines 
use the FSTENV/FNSTENV/FLDENV instructions 
and separate numeric register load/store instructions. 
Using separate load/store instructions for the numeric 
registers forces the 8087 to release the local bus after 
each numeric load/store instruction. The longest series 
of back-to-back memory transfers required by these 
instructions are 8/12 memory cycles for an 8086 or 8088 
host, respectively. In contrast, the FSAVE/ 
FNSAVE/FRSTOR instructions perform 50/94 back- 
to-back memory cycles for an 8086 or 8088 host. 

Compatibility With FSAVE/FNSAVE 

This function produces a context area of the same for- 
mat produced by FSAVE/FNSAVE instructions. Other 
software modules expecting such a format will not be 
affected. All the same interrupt and deadlock considera- 
tions of FSAVE and FNSAVE also apply to FSTENV 
and FNSTENV. Except for the fact that the numeric 
environment is 7 words rather than the 47 words of the 
numeric context, all the discussion of Appendix A also 
applies here. 



The state of the NPX registers must be saved in memory 
in the same format as the FSAVE/FNSAVE instruc- 
tions. The program example starting at the label 
SMALL_BLOCK_NPX_JSAVE illustrates a software 
loop that will store their contents into memory in the 
same top relative order as that of FSAVE/FNSAVE. 

To save the registers with FSTP instructions, they must 
be tagged valid, zero, or special. This function will force 
all the registers to be tagged valid, independent of their 
contents or old tag, and then save them. No problems 
will arise if the tag value conflicts with the register's 
content for the FSTP instruction. Saving empty regis- 
ters insures compatibility with the FSAVE/FNSAVE in- 
structions. After saving all the numeric registers, they 
will all be tagged empty, the same as if an 
FSAVE/FNSAVE instruction had been executed. 



Compatibility With FRSTOR 

Restoring the numeric context reverses the procedure 
described above, as shown by the code starting at 
SM ALL_BLOCK_NPX_RESTORE . All eight regis- 
sters are reloaded in the reverse order. With each 
register load, a tag value will be assigned to each 
register. The tags assigned by the register load does not 
matter since the tag word will be overwritten when the 
environment is reloaded later with FLDENV. 

Two assumptions are required for correct operation of 
the restore function: all numeric registers must be empty 
and the TOP field must be the same as that in the con- 
text being restored. These assumptions will be satisfied 
if a matched set of pushes and pops were performed bet- 
ween saving the numeric context and reloading it. 

If these assumptions cannot be met, then the code exam- 
ple starting at NPX__CLEAN shows how to force all the 
NPX registers empty and set the TOP field of the status 
word. 



3-31 



AM 13 



smalL_block_N PX_save 



; Save the NPX context independent of NDP interrupt state. Avoid using the FSAVE instruction to 
; limit the worst case memory bus usage of the 8087. The NPX context area formed will appear the 
; same as if an FSAVE instruction had written into it. The variable save_area will hold the NPX 
; context and must be 47 words long. The registers ax, bx, and cx will not be transparent. 

small_J>lock_N PX_save: 



FNSTCW 


save_area 




NOP 




Delav while 8087 saves control register 


FNDISI 




Disable 8087 BUSY signal 


MOV 


ax, save_area 


Get original control word 


MOV 


cx, 8 


Set numeric register count 


XOR 


bx, bx 


Tag field value for stamping all registers as valid 


FSTENV 


save_area 


Save NPX environment 


FWAIT 




Wait for the store to complete 


XCHG 


save__area+4, bx 


Get original tag value and set new tag value 


FLDENV 


save__area 


Force all register tags as valid. BUSY is still masked. No data 


MOV 


save_area, ax 


synchronization needed. Put original control word into NPX 


MOV 


save_area + 4, bx 


environment. Put original tag word into NPX environment 


XOR 


bx, bx 


Set initial register index 


reg___store__loop: 




FSTP 


saved__reg [bx] 


Save register 


ADD 


bx, type saved__reg 


Bump pointer to next register 


LOOP 


reg_store_loop 





; All done 



NPX clean 





W V «'-,v : ' <'<■'"; ' ' ' ' 
Force the NPX into a clean state with TOP matching the TOP field stored in the NPX context and all 




numeric registers tagged empty. Save. 


_area must be the NPX environment saved earlier. 




Temp_env is a 7 word temporary area used to build a prototype NPX environment. Register ax will 




not be transparent. 




NPX_clean: 




FINIT 


; Put NPX into known state 


MOV ax, save__area-f 2 


; Get original status word 


AND ax,3800H 


; Mask out the top field 


FSTENV temp_env 


; Format a temporary environment area with all registers 




; stamped empty and TOP field = 0. 


FWAIT 


■ Wait for the store to finish. 


OR temp__env+2, ax 


Put in the desired TOP value. 


FLDENV temp_env, 


, Setup new NPX environment. 




; Now enter small_block_NPX__restore 



3-32 



AM 13 



small_block_NPX_restore 



; Restore the NPX context without using the FRSTOR instruction. Assume the NPX context is in the 


; same form as that created by an FSAVE/FNSAVE instruction, ail the registers are empty, and that 


; the TOP field of the NPX matches the TOP field of the NPX context. The variable save_area must 


; be an NPX context save area, 47 words long. The registers bx and cx will not be transparent. 


small_block_NPXL_restore: 




MOV cx, 8 


; Set register count 


MOV bx, type saved_reg*7 


; Starting offset of ST(7) 


reg_Joad__loop: 




FLD saved_reg [bx] 


; Get the register 


SUB bx, type saved_reg 


; Bump pointer to next register 


LOOP reg__load_Joop 




FLDENV save_area 


; Restore NPX context 




; All done 



APPENDIX C 



OVERVIEW 

Appendix C shows how floating point values can be 
converted to decimal ASCII character strings. The func- 
tion can be called from PLM/86, PASCAL/86, FOR- 
TRAN/86, or ASM/86 functions. 

Shortness, speed, and accuracy were chosen rather than 
providing the maximum number of significant digits 
possible. An attempt is made to keep integers in their 
own domain to avoid unnecessary conversion errors. 

Using the extended precision real number format, this 
routine achieves a worst case accuracy of three units in 
the 1 6th decimal position for a non-integer value or in- 
tegers greater than 10 18 . This is double precision ac- 
curacy. With values having decimal exponents less than 
100 in magnitude, the accuracy is one unit in the 17th 
decimal position. 

Higher precision can be achieved with greater care in 
programming, larger program size, and lower perfor- 
mance. 

Function Partitioning 

Three separate modules implement the conversion. 
Most of the work of the conversion is done in the mod- 
ule FLOATING_TO__ASCII. The other modules are 
provided separately since they have a more general use. 
One of them, GET_POWER_10, is also used by the 
ASCII to floating point conversion routine. The other 
small module, TOS_STATUS, will identify what, if 
anything, is in the top of the numeric register stack. 



Exception Considerations 

Care is taken inside the function to avoid generating ex- 
ceptions. Any possible numeric value will be accepted. 
The only exceptions possible would occur if insufficient 
space exists on the numeric register stack. 

The value passed in the numeric stack is checked for ex- 
istence, type (NAN or infinity), and status (unnormal, 
denormal, zero, sign). The string size is tested for a 
minimum and maximum value. If the top of the register 
stack is empty, or the string size is too small, the func- 
tion will return with an error code. 

Overflow and underflow is avoided inside the function 
for very large or very small numbers. 

Special Instructions 

The functions demonstrate the operation of several 
numeric instructions, different data types, and precision 
control. Shown are instructions for automatic conver- 
sion to BCD, calculating the value of 10 raised to an in- 
teger value; establishing and maintaining concurrency, 
data synchronization, and use of directed rounding on 
the NPX. 

Without the extended precision data type and built-in 
exponential function, the double precision accuracy of 
this function could not be attained with the size and 
speed of the shown example. 

The function relies on the numeric BCD data type for 
conversion from binary floating point to decimal. It is 



3-33 



AfM13 



not difficult to unpack the BCD digits into separate 
ASCII decimal digits. The major work involves scaling 
the floating point value to the comparatively limited 
range of BCD values. To print a 9-digit result requires 
accurately scaling the given value to an integer between 
10 8 and 10 9 . For example, the number +0.123456789 
requires a scaling factor of 10 9 to produce the value 
+ 123456789.0 which can be stored in 9 BCD digits. The 
scale factor must be an exact power of 10 to avoid to 
changing any of the printed digit values. 

These routines should exactly convert all values exactly 
representable in decimal in the field size given. Integer 
values which fit in the given string size, will not be 
scaled, but directly stored into the BCD form. Non- 
integer values exactly representable in decimal within 
the string size limits will also be exactly converted. For 
example, 0.125 is exactly representable in binary or 
decimal. To convert this floating point value to decimal, 
the scaling factor will be 1000, resulting in 125. When 
scaling a value, the function must keep track of where 
the decimal point lies in the final decimal value. 

DESCRIPTION OF OPERATION 

Converting a floating point number to decimal ASCII 
takes three major steps: identifying the magnitude of 
the number, scaling it for the BCD data type, and con- 
verting the BCD data type to a decimal ASCII string. 

Identifying the magnitude of the result requires finding 
the value X such that the number is represented by 
PIO* where 1.0 < = I< 10.0. Scaling the number re- 
quires multiplying it by a scaling factor 10 s , such that 
the result is an integer requiring no more decimal digits 
than provided for in the ASCII string. 

Once scaled, the numeric rounding modes and BCD 
conversion put the number in a form easy to convert to 
decimal ASCII by host software. 

Implementing each of these three steps requires atten- 
tion to detail. To begin with, not all floating point 
values have a numeric meaning. Values such as infinity, 
indefinite, or Not A Number (NAN) may be en- 
countered by the conversion routine. The conversion 
routine should recognize these values and identify them 
uniquely. 

Special cases of numeric values also exist. Denormals, 
unnormals, and pseudo zero all have a numeric value 
but should be recognized since all of them indicate that 
precision was lost during some earlier calculations. 

Once it has been determined that the number has a 
numeric value, and it is normalized setting appropriate 
unnormal flags, the value must be scaled to the BCD 
range. 



Scaling the Value 

To scale the number, its magnitude must be determined. 
It is sufficient to calculate the magnitude to an accuracy 
of 1 unit, or within a factor of 10 of the given value. 
After scaling the number, a check will be made to see if 
the result falls in the range expected. If not, the result 
can be adjusted one decimal order of magnitude up or 
down. The adjustment test after the scaling is necessary 
due to inevitable inaccuracies in the scaling value. 

Since the magnitude estimate need only be close, a fast 
technique is used. The magnitude is estimated by multi- 
plying the power of 2, the unbiased floating point expo- 
nent, associated with the number by logio2. Rounding 
the result to an integer will produce an estimate of suffi- 
cient accuracy. Ignoring the fraction value can in- 
troduce a maximum error of 0.32 in the result. 

Using the magnitude of the value and size of the number 
string, the scaling factor can be calculated. Calculating 
the scaling factor is the most inaccurate operation of the 
conversion process. The relation 10 x = 2**(X*log2lO) is 
used for this function. The exponentiate instruction 
(F2XM1) will be used. 

Due to restrictions on the range of values allowed by the 
F2XM1 instruction, the power of 2 value will be split in- 
to integer and fraction components. The relation 
2**(I + F) = 2**I * 2**F allows using the FSCALE in- 
struction to recombine the 2**F value, calculated 
through F2XM1, and the 2**1 part. 

Inaccuracy in Scaling 

The inaccuracy of these operations arises because of the 
trailing zeroes placed into the fraction value when strip- 
ping off the integer valued bits. For each integer valued 
bit in the power of 2 value separated from the fraction 
bits, one bit of precision is lost in the fraction field due 
to the zero fill occurring in the least significant bits. 

Up to 14 bits may be lost in the fraction since the largest 
allowed floating point exponent value is 2 14 - 1. 

AVOIDING UNDERFLOW AND OVERFLOW 

The fraction and exponent fields of the number are sep- 
arated to avoid underflow and overflow in calculating 
the scaling values. For example, to scale 10 ~ 4932 to 10 8 
requires a scaling factor of 10 4950 which cannot be rep- 
resented by the NPX. 

By separating the exponent and fraction, the scaling 
operation involves adding the exponents separate from 
multiplying the fractions. The exponent arithmetic will 
involve small integers, all easily represented by the 
NPX. 



3-34 



AP-113 



FINAL ADJUSTMENTS 

It is possible that the power function (Get— Power_J0) 
could produce a scaling value such that it forms a scaled 
result larger than the ASCII field could allow. 
For example, scaling 9. 9999999999999999 e4900 
by 1.00000000000000010e-4883 would produce 
1.00000000000000009el8. The scale factor is within the 
accuracy of the NDP and the result is within the conver- 
sion accuracy, but it cannot be represented in BCD for- 
mat. This is why there is a post-scaling test on the 
magnitude of the result. The result can be multiplied or 
divided by 10, depending on whether the result was too 
small or too large, respectively. 



Output Format 

For maximum flexibility in output formats, the position 
of the decimal point is indicated by a binary integer 
called the power value. If the power value is zero, then 
the decimal point is assumed to be at the right of the 
right-most digit. Power values greater than zero indicate 
how many trailing zeroes are not shown. For each unit 
below zero, move the decimal point to the left in the 
string. 

The last step of the conversion is storing the result in 
BCD and indicating where the decimal point lies. The 
BCD string is then unpacked into ASCII decimal char- 
acters. The ASCII sign is set corresponding to the sign 
of the original value. 



LINE 



SOURCE 



$ti tie (Convert a floating point number to ASCII) 
name f loating_to_asci i 

public f loating~t°Z asc * * 

extrn getjpower 10:near ,tos_status:near 



; This subroutine will convert the floating point 

; top of the 8087 stack to an ASCII string and sepa 

scaling value (in binary). The maximum width of 
formed is controlled by a parameter which must be 
denormal values, and psuedo zeroes will be correc 
A returned value will indicate how many binary bi 
precision were lost in an unnormal or denormal va 
(in terms of binary power) of a psuedo zero will 
Integers less than 10**18 in magnitude are accura 
destination ASCII string field is wide enough to 
digits. Otherwise the value is converted to scie 



number in the 
rate power of 10 
the ASCII string 

> 1. Unnormal values, 
tly converted, 
ts of 

lue. The magnitude 
also be indicated, 
tely converted if the 
hold all the 
ntific notation. 



The status of the conversion is identified by the return value, 
it can be: 

0 conversion complete, string^size is defined 

1 invalid arguments 

2 exact integer conversion, string __size is defined 

3 indefinite 

4 + NAN (Not A Number) 

5 - NAN 

6 + Infinity 

7 - Infinity 

8 psuedo zero found, string jsize is defined 

The PLM/86 calling convention is: 

f loating toasci i : 

procedure (number , denormal ptr, string j?tr ,size_ptr,f ield^size, 

power^ptr) word external; - - - 

declare (denormal_ptr # str ing ptr ,powerj?tr ,sizej?tr ) pointer; 
declare field^size word, string size based sizejatr word; 
declare numbeF real; ~ ~ 

declare denormal integer based denormal^ptr ; 
declare power integer based power jptr; 
end floating_to ascii; 

The floating point value is expected to be on the top of the NPX 
stack. This subroutine expects 3 free entries on the NPX stack and 
will pop the passed value off when done. The generated ASCII string 
will have a leading character either •-• or ■ + ' indicating the sign 
of the value. The ASCII decimal digits will immediately follow. 
The numeric value of the ASCII string is (ASCII STRING. ) *10**POWER. 



3-35 

\ 



AP-113 



49 
50 
51 
52 
53 
54 
55 
56 
57 
b8 
59 
60 
61 
62 
63 
64 
65 
66 
67 
68 
69 
70 
71 
72 
73 
74 
75 
76 
77 
78 
79 
80 
81 
82 
83 
84 
85 
86 
87 
88 
89 
90 
91 
92 
93 
94 
95 
96 
.97 
98 
99 
100 
101 
102 
103 
104 
105 
106 
107 
108 
109 
110 
111 
112 
113 
114 
115 
116 
11/ 
118 



It the given number was zero, the ASCII string will contain a sign 
and a single zero chacter. The value string_size indicates the total 
length of the ASCII string including the sign character. String (0) will 
always hold the sign. It is possible for string size to be less than 
field^size. This occurs for zeroes or integer values. A psuedo zero 
will return a special return code. The denormal count will indicate 
the power of two originally associated with the value. The power of 
ten and ASCII string will be as if the value was an ordinary zero. 

This subroutine is accurate up to a maximum. of 18 decimal digits for 
integers. Integer values will have a decimal power of zero associated 
with them. For non integers, the result will be accurate to within 2 
decimal digits of the 16th decimal place (double precision). The 
exponentiate instruction is also used for scaling the value into the 
Grange acceptable for the BCD data type. The rounding mode in effect 
on entry to the subroutine is used for the conversion. 

The following registers are not transparent: 

ax bx cx dx si di flags 



Define the stack layout. - 

bpjsave equ word ptr [bp] 

es~save equ bp^save + size bp^save 

return jptr equ es~save + size es^save 

power_ptr equ reFurnjptr + si ze~return_ptr 

field~size equ power_ptr + size power ptr 

size_ptr equ field^size + size fielcT^size 

stringjptr equ size_ptr + size size__ptF 

denormal^ptr equ stringjptr + size stringjptr 

parms_size equ size powerjatr + size field^size + size size^ptr + 

& size string ptr + size denormal ptr ~~ 



Define constants used 



BCDJ5IGITS 
WORD SIZE 
BCDjTlZE 
MINUS 
NAN 

INFINITY 

INDEFINITE 

PSUEDO^ZERO 

INVALID 

ZERO 

DENORMAL 
UNNORMAL 
NORMAL 
EXACT 



equ 


18 


equ 


2 


equ 


10 


equ 


1 


equ 


4 


equ 


6 


equ 


3 


equ 


8 


equ 


-2 


equ 


-4 


equ 


-6 


equ 


-8 


equ 


0 


equ 


2 



Number of digits in bcd_value 



Define return values 
The exact values chosen here are 
important. They must correspond to 
the possible return values and be in 
the same numeric order as tested by 
the program. 



; Define layout of temporary storage area. 

; ' 

status equ word ptr [bp-wORD_SIZE] 

power_two equ status - WORD SIZE 

power^ten equ power__ two - w6"RD_alZE 

bcd_value equ tbyte~"ptr power ten - BCDjsIZE 

bcd__byte equ byte ptr bcd_yaTue ~* 

fraction equ bcd_value 

local_size equ size status + size power_two + size power_ten 

& ~ + size bcd^yalue ~* . ~ 

Allocate stack space for the temporaries so the stack will be big enough 

stack segment stack 'stack* 

db (local size+6) dup (?) 



3-36, 



AM 13 



120 
121 
122 
123 
124 
125 
126 
127 
128 
129 
130 
131 
132 
133 
134 



cgroup 
code 



constl0 



group code 

segment public 'code' 

assume cstcgroup 

extrn power_table:qword 

Constants used by this function. 



even 
dw 



10 



; Optimize for 16 bits 

; Adjustment value for too big BCD 



Convert the C3,C2,C1,C0 encoding from tos_status into meaningful bit 
flags and values. ~~ 



status table 



db 



UNNORMAL, NAN , UNNORYA I'. + MIMUS, NAN + VIMU£, 



MORTAL, INFINITY, NORMAL + MINUS , INFINITY 4 MINUS, 



136 & ZERO, INVALID, ZERO + MINUS, INVALID, 



137 



DENORMAL, INVALID, DENORMAL 4 MINUS , INVALID 



138 
139 
140 
141 
142 
143 
144 
145 
146 
147 
148 
149 
150 
151 
152 
153 
154 
155 
156 
157 
158 
159 
160 
161 
162 
163 
164 
165 
166 
167 
168 
169 
170 
171 
172 
173 
174 
175 
176 
177 
178 
179 
180 



f loating__to_asci i proc 



call tos_status 

mov bx,ax 

mov al, status tablefbx] 

cmp al, INVALID 

jne not_empty 



; Look at status of ST(0) 
; Get descriptor from table 

; Look for empty ST(0) 



ST(0) is empty! Return the status value, 
ret parms^size 

Remove infinity from stack and exit. 
found_inf ini ty : 



f stp 
jmp 



st (0) 

short exit_proc 



String space is too small! 
smal ljstr ing : 

mov al, INVALID 

exit proc: 



; OK to leave fstp runninq 
Return invalid code. 



mov 
pop 
pop 
ret 



sp,bp 

bp 

es 

parms size 



; Free stack space 
; Restore registers 



ST(0) is NAN or indefinite. Store the value in memory and look 
at the fraction field to separate indefinite from an ordinary NAN. 



NAN or indefinite: 



fstp 
test 
fwait 



fraction 
al, MINUS 

exi t_proc 



; Remove value from stack for examination 

; Look at sign bit 

; Insure store is done 

; Can't be indefinite if positive 



3-37 



AP-113 



181 mov bx,0C000H ; Match against upper 16 bits of fractior 

182 sub bx,word ptr fraction+6 j Compare bits 63-48 

183 or bx,word ptr fraction+4 . ; Bits 32-47 must be zero 

184 \ or bx,word ptr fraction+2 ; Bits 31-16 must be zero 

185 or bx,word ptr fraction ; Bits 15-0 must be zero 

186 jnz exit proc 
187 

188 mov al , INDEFINITE ; Set return value for indefinite value 

189 jmp exit proc 
190 

191 ; Allocate stack space for local variables and establish parameter 

192 ; addressibility. 
193 

194 not empty: 

195 

196 push es ; Save working register 

197 push bp 

198 mov bp,sp ; Establish stack addressibi 1 i ty 

199 sub sp, local size 
200 

201 mov cx,f ield_size ; Check for enough string space 

202 cmp cx,2 ~ 

203 jl small string 
204 

205 dec cx ; Adjust for sign character 

206 cmp cx,BCD DIGITS , ; See if string is too large for BCD 

207 jbe size_ok~ 
208 

209 mov cx ,BCD_J)IGITS ; Else set maximum string size 

210 

211 size ok: 

212 

213 cmp al, INFINITY ; Look for infinity 

214 jge found infinity ; Return status value for + or - inf. 

215 ~ 

216 cmp a 1 , NAN ; Look for NAN or INDEFINITE 

217 jge NAN or indefinite 

218 ; ~ ~ 

219 ; Set default return values and check that the number is normalized. 
220 

221 fabs ; yse positive value only 

222 ; sign bit in al has true sign of value 

223 mov dx,ax ; Save return value for later 

224 xor ax, ax ; Form 0 constant 

225 mov di ,denormal ptr ; Zero denormal count 

226 mov word ptr [di] ,ax 

227 mov bx,power_ptr ; Zero power of ten value 

228 mov word ptr"~[bx] ,ax 

229 cmp dl,ZERO ; Test for zero 

230 jae real zero ; Skip power code if value is zero 
231 

232 cmp dl, DENORMAL ; Look for a denormal value 

233 jae found denormal ; Handle it specially 

234 ~ 

235 fxtract ; Separate exponent from significand 

236 cmp dl ,UNNORMAL ; Test for unnormal value 

237 jb normal value 
238 

239 sub d 1 , UNNORMAL-NORMAL ; Return normal status with correct sign 

240 

241 ; Normalize the fraction, adjust the power of two in ST(1) and set 

242 ; the denormal count value. 
243 

244 ; Assert: 0 <= ST(0) < 1.0 

245 

246 fldl ; Load constant to normalize fraction 

247 

248 normalize fraction: 
249 

250 fadd st(l),st , ; Set integer bit in fraction 

251 fsub ; Form normalized fraction in ST(0) 

252 fxtract ; Power of two field will be negative 

253 ; of denormal count 

254 fxch ; Put denormal count in ST(0) 



3-38 



AP-113 



255 fist word ptr [di] ; Put negative, of denormal count in memory 

256 faddp st(2),st ; Form correct power of two in st(l) 

257 ; OK to use word ptr [di] now 

258 neg word ptr [di] ; Form positive denormal count 

259 jnz not psuedo zero 
260 

261 ; A psuedo zero will appear as an unnormal number. When attempting 

262 ; to normalize it, the resultant fraction field will be zero. Performing 

263 ; an fxtract on zero will yield a zero exponent value. 
264 

265 fxch ; Put power of two value in st(0) 

266 fistp word ptr [di] ; Set denormal count to power of two value 

267 ; Word ptr [di] is not used by convert 

268 ; integer, OK to leave running 

269 sub dl ,NORMAL-PSUEDO_ZERO ; Set return value saving the sign bit 

270 jmp i convert integer ~~ ; Put zero value into memory 
271 

272 ; The number is a real zero, set the return value and setup for 

273 ; conversion to BCD. 
274 

275 real zero: 
276 

277 sub dl , ZERO-NORMAL ; Convert status to normal value 

278 jmp convert integer ; Treat the zero as an integer 
279 

280 ; The number is a denormal. FXTRACT will not work correctly in this 

281 ; case. To correctly separate the exponent and fraction, add a fixed 

282 ; constant to the exponent to guarantee the result is not a denormal. 
283 

284 found denormal: 
285 

286 fldl ; Prepare to bump exponent 

287 fxch 

288 fprem ; Force denormal to smallest representable 

289 ; extended real format exponent 

290 fxtract ; This will work correctly now 
291 

292 ; The power of the original denormal value has been safely isolated. 

293 ; Check if the fraction value is an unnormial. 
294 

295 fxam ; See if the fraction is an unnormal 

296 fstsw status ; Save status for later 

297 fxch ; Put exponent in ST(0) 

298 fxch st(2) ; Put 1.0 into ST(0), exponent in ST(2) 

299 sub dl , DENORMAL-NORMAL ; Return normal status with correct sign 

300 test status, 4400H ; See if C3«C2=0 impling unnormal or NAN 

301 jz normalize fraction ; Jump if fraction is an unnormal 
302 

303 fstp st(0) ; Remove unnecessary 1.0 from st(0) 

304 

305 ; Calculate the decimal magnitude associated with this number to 

306 ; within one order. This error will always be inevitable due to 

307 ; rounding and lost precision. As a result, we will deliberately fail 

308 ; to consider the LOG10 of the fraction value in calculating the order. 

309 ; Since the fraction will always be 1 <* F < 2, its LOG10 will not change 

310 ; the basic accuracy of the function. To get the decimal order of magnitude 

311 ; simply multiply the power of two by LOG10(2) and truncate, the result to 

312 ; an integer. 
313 

314 normal^value: 

315 not psuedo zero: 
316 

317 fstp fraction ; Save the fraction field for later use 

318 fist power two ; Save power of two 

319 fldlg2 ~ ; Get LOG10(2) 

320 ; Power^two is now safe to use 

321 fmul ; Form LOG10 (of exponent of number) 

322 fistp power ten ; Any rounding mode will work here 
323 

324 ; Check if the magnitude of the number rules out treating it as 

325 ; an integer. 
326 

327 ; CX has the maximum number of decimal digits allowed. 



3-39 



AP-113 



328 ; 

329 fwait ; Wait for power _ten to Jbe valid 

330 mov ax,power_ten ; Get power of ten of value 

331 sub a?c,cx ~ s Form scaling factor necessary in ax 

332 ja adjust result ; Jump if number will not fit 
333 

334 ; The number is between 1 and 10** ( f ield_si ze) . 

335 ; Test if it is an integer. 
336 

337 fild power_two . ; Restore original number 

338 mov si,dx~ , ; Save return value 

339 sub dl , NORMAL-EXACT ; Convert to exact return value 

340 fid fraction 

341 fscale ; Form full value, this is safe here 

342 fst st(l) ; Copy value for compare 

343 frndint ; Test if, its an integer 

344 fcomp ; Compare values 

345 fstsw status ; Save status 

346 test status, 4000H ; C3=l implies it was an integer 

347 jnz convert integer 
348 

349 f st P st(0) ; Remove non integer value 

350 mov , dx,si ; Restore original return value 
351 

352 ; Scale the number to within the range allowed by the BCD format. 

353 ; The scaling operation should produce a number within one decimal order 

354 ; of magnitude of the largest decimal number representable within the 

355 ; given string width. 

356 

357 ; The scaling power of ten value is in ax. 

358 

359 adjust result: 
360 

361 mov word ptr [bx] ,ax ; Set initial power ot ten return value 

362 neg ax ; Subtract one for each order of 

363 ; magnitude the value is scaled by 

364 call getj3ower_J,0 ? Scaling factor is returned as exponent 

365 - — ^ fraction 

366 fid fraction ; Get fraction 

367 fmul ; Combine fractions 

368 mov si,cx ; Form power of ten of the maximum 

369 shl si,l ? BCD value to fit in the string 

370 shl si,l ; Index in si 

371 shl si,l 

372 fild power_two ; Combine powers of two 

373 faddp st(2)7st 

374 fscale ; Form full value, exponent was safe, 

375 fstip st(l) ; Remove exponent 

376 ; 

377 ; Test the adjusted value against a table of exact powers of ten. 

378 ; The combined errors of the magnitude estimate and power function can 

379 ; result in a value one order of magnitude too small or too large to fit 

380 ; correctly in the BCD field. To handle this problem, pretest the 

381 ; adjusted value, if it is too small or large, then adjust it by ten and 

382 ; adjust the power ot ten value. 
383 

384 testjpower: 
385 

386 fcom power^table [si ] +type powertable; Compare against exact power 

387 ~" ; entry. Use the next entry since cx 

388 ; has been decremented by one 

389 fstsw status ; No wait is necessary 

390 test status, 4100H ; If C3 = C0 = 0 then too big 

391 jnz test for small 
392 

393 fidiv constl0 ; Else adjust value 

394 and dl,not EXACT ? Remove exact flag 

395 inc word ptr [bx] ; Adjust power of ten value 

396 jmp short in range ; Convert the value to a BCD integer 

397 - 

398 test for smalls 

399 "~ 

400 fcom powe ratable [si] ; Test relative size 

401 fstsw status" ; No wait is necessary 

3-40 



AM 13 



402 test status, 100H ; If C0 ■ 0 then st(0) >* lower bound 

403 jz in range y ; Convert the value to a BCD integer 
404 

405 fimul constl0 ; Adjust value into range 

406 dec word ptr [bx] ; Adjust power of ten value 
407 

408 in range: 

409 

410 frndint ; Form integer value 

411 

412 ; Asserts 0 <« TOS <= 999,999,999,999,999,999 

413 ; The TOS number will be exactly representable in 18 digit BCD format. 
414 

415 convert integer: 

416 - 

417 fbstp bed value ; Store as BCD format number 
418 

419 ; While the store BCD runs, setup registers for the conversion to 

420 ; ASCII. 
421 

422 mov si,BCDJ3IZE-2 ; Initial BCD index value 

423 mov cx,0f07h ; Set stfift count and mask 

424 mov bx,l ; Set initial size of ASCII field for sig 

425 mov di , string jptr ; Get address of start of ASCII string 

426 mov ax,ds ; Copy ds to es 

427 mov es,ax 

428 eld ; Set autoincrement mode 

429 mov al,'+' ; Clear sign field 

430 test dl, MINUS ; Look for negative value 

431 jz positive result 
432 

433 mov al , • - ■ 

434 

435 positive result: 
4 36 ~ 

437 stosb ; Pump strinq pointer past sign 

438 and dl,not MINUS ; Turn off sign bit 

439 fwait ; Wait for fbstp to finish 
.440 

441 ; Register usage: 

442 ; ah: BCD byte value in use 

443 ; al: ASCII character value 

444 ; dx: Return value 

445 ; ch: BCD mask « 0fh x 

446 ; cl: BCD shift count * 4 

447 ; bx: ASCII string field width 

448 ; si: BCD field index 

449 ; di: ASCII string field pointer 

450 ; ds,es: ASCII string segment base 
4 51 

452 ; Remove leading zeroes from the number. 

453 , , , 

454 skip leading zeroes: 
455 

456 mov ah,bcd Jsyte [si] ; Get BCD byte 

457 mov al,ah ; Copy value 

458 shr al,cl ; Get high order digit 

459 and al,ch ; Set zero flag 

460 jnz enter odd ; Exit loop if leading non zero found 

461 , k 

462 mov al,ah ; Get BCD byte again 

463 and al,ch ; Get low order digit 

464 jnz enter even ; Exit loop if non zero digit found 
465 

466 dec si ; Decrement BCD index 

467 jns skip leading zeroes 

468 ~ 

469 ; The significand was all zeroes. 
470 

471 mov al, f 0' ; Set initial zero 

472 stosb ( , 

473 inc bx ; Bump string length 

474 jmp short exit^wi th_yalue 



3-41 



AP-113 



J" 



475 










476 


; Now expand the BCD string 


into digit per byte values 0-9. 


477 


r 








478 


digi t_Jloop: 








479 










480 


mov 


ah,bed^byte [si] 


? 


Get BCD byte 


481 


mov 


al ,ah * 






482 


shr 


al,cl 




Get high order digit 


483 










484 


enter odds 








485 










HOD 


add 


al,«0* * * 




Convert to ASCII 


487 


stosb 




} 


Put digit into ASCII string 


488 


mov 


al»ah 


f 


Get low order digit 


489 


and 


al f ch 






490 


inc 


bx 




Bump field size counter 


491 










492 


enter^evens, 








H y j 










494 


add 


al,*0' 


} 


Convert to ASCII 


495 


stosb 




r 


Put digit into ASCII area 


496 


inc 


bx 




Bump field size counter 


497 


dec 


si 


t 


Go to next BCD byte 


498 


jns 


digit^loop 






499 










500 


; Conversion complete. Set 


the string size and remainder. 


501 










502 


exit with value: 






503 










504 


mov 


di , size^ptr 






505 


mov 


word ptr~ fdi] ,bx 






506 


mov 


ax,dx 




Set return value 


507 


jmp 


exit jproc 






508 










509 


floating to ascii endp 






510 


code 


ends 






511 




end 







ASSEMBLY COMPLETE, HO ERRORS POUND 



LINE SOURCE 

1 $title(Calculate the value of 10**ax) 



2 

3 ; This subroutine will calculate the value of 10**ax. 

4 ; All 8086 registers are transparent and the value is returned on 

5 ; the TOS as two numbers, exponent in ST(1) and fraction in ST(0). 

6 ; The exponent value can be larger than the maximum representable 

7 ; exponent. Three stack entries are used. 

8 , ; y 

9 name get power_10 

10 public get^power" 10, power table 

11 

12 stack segment stack 'stack* 

13 dw 4 dup (?) ; Allocate space on the stack 



14 
15 
16 
17 
18 
19 
20 
21 
22 
23 



stack 



cgroup 
code 



s 



group code 

segment public 'code' 

assume cs regroup 



Use exact values from 1.0 to lel8. 
i even 

power table dq 1.0, lei, le2, le3 



Optimize 16 bit access 



3-42 



# 

AP-113 



24 



dq Ie4,le5,le6,le7 



25 



dq Ie8 r le9,lel0,lell 



26 



aq 



Iel2,lel3,lel4, le!5 



27 



dq 



Iel6,lel7,lel8 



28 
29 
30 
31 
32 
33 
34 
35 
36 
37 
38 
39 
40 
41 
42 
43 
44 
45 
46 
47 
48 
49 
50 
51 



get jpower_10 

cmp 
ja 

push 

mov 

shl 

shl 

shl 

fid 

pop 

f xtract 
ret 



proc 
ax, 18 

out jDf_range 
bx 

bx,ax 
bx,l 
bx,l 
bx,l 

power t able [bx] 
bx 



Test for 0 <» ax < 19 



; Get working index register 
; Form table index 



; Get exact value 

; Restore register value 

; Separate power and fraction 

; OK to leave fxtract running 



Calculate the value using the exponentiate instruction. 
The following relations are used: 
10**x - 2**(log2(10)*x) 
2**(I+F) ■ 2**1 * 2**F 

if st(l) * I and st(0) - 2**F then fscale produces 2**(I+F) 



out jof — range: 



52 


fldl2t 




» 


TOS ■ LOG2(10) 


53 


push 


bp 


i 


Establish stack addressibility 


54 


mov 


bPrSp 






55 


push 


ax 


s 


Put power (P) in memory 


56 


push 


ax 


} 


Allocate space for status 


57 , 


f imul 


word ptr [bp-2] 


i 


TOS,X m LOG2(10)*P - LOG2(10**P) 


58 


f nstcw 


word ptr [bp-4] 


s 


Get current control word 


59 




; 


Control word is a static value 


60 


mov 


ax, word ptr [bp-4] 


; 


Get control word, no wait necessary 


61 


and 


ax, not 0C00H 




Mask off current rounding field 


62 


or 


ax,0400H 


; 


Set round to negative infinity 


63 


xchg 


ax, word ptr [bp-4] 


; 


Put new control word in memory 


64 






; 


old control word is in ax 


65 


fldl 




i 


Set TOS * -1.0 


66 


f chs 








67 


fid 


st(l) 


7 


Copy power value in base two 


68 


f ldcw 


word ptr [bp-4] 


t 


Set new control word value 


69 


frndint 


! 


TOS - I:.-inf < I <* X, I is an integer 


70 


mov 


word ptr [bp-4] ,ax 


? 


Restore original rounding control 


71 


f ldcw 


word ptr [bp-4] 







3-43 



AP-113 



72 


fxch 


st(2) 


; TOS * X, ST(1) * -1.0, ST(2) 


73 


pop 


ax 


; Remove original control word 


74 


f sub 


st, st (2) 


; TOS,F * X-I: 0 <= TOS < 1.0 


75 


pop 


ax 


; Restore power of ten 


76 


fscale 




; TOS * F/2: 0 <* TOS < 0.5 


77 


f2xml 




; TOS » 2**(F/2) - 1.0 


78 


pop 


bp 


; Restore stack 


79 


f subr 




; Form 2** (F/2) 


80 


fmul 


St, St (0) 


; Form 2**F 


81 


ret 




; OK to leave fmul running 


82 








83 


get j?ower_10 


endp 




84 


code 


ends 




85 




end 





ASSEMBLY COMPLETE, NO ERRQRS FOUND 



LINE SOURCE 

1 $title (Determine TOS register contents) 



2 

3 ; This subroutine will return a value from 0-15 in ax corresponding 

4 ; to the contents of 8087 TOS. All registers are transparent and no 

5 ; errors are possible. The return value corresponds to c3,c2,cl,c0 

6 ; of FXAM instruction. 
7 

8 name tosjstatus 

9 public tos~status 
10 

11 stack segment stack ''stack 1 

12 dw 3 dup (?) ; Allocate space on the, stack 



13 stack ends 
14 

15 cgroup group code 

16 code segment public 'code' 

17 assume cs:cgroup 

18 tos status proc 

19 < 

20 fxam ; Get register contents status 

21 push ax ; Allocate space for status value 

22 push bp ; Establish stack addressibility 

23 mov bp,sp 

24 fstsw word ptr fbp+2] ; Put tos status in memory 

25 pop bp ; Restore registers 

26 pop ax ; Get status value, no wait necessary 

27 mov al,ah ; Put bit 10-8 into bits 2-0 

28 and ax,4007h ; Mask out bits c3,c2,cl,c0 

29 shr ah,l ? Put bit c3 into bit 11 

30 shr ah,l 

31 shr ah,l 

32 or al,ah ; Put c3 into bit 3 

33 mov ah,0 ; Clear return value 

34 ret 
35 

36 tos_status endp 

37 code ends 

38 end 



ASSEMBLY COMPLETE, NO ERRORS FOUND 



3-44 



AP-113 



APPENDIX D 



OVERVIEW 

Appendix D shows a function for converting ASCII 
input strings into floating point values. The returned 
value can be used by PLM/86, PASCAL/86, FOR- 
TRAN/86, or ASM/86. The routine will accept a num- 
ber in ASCII of standard FORTRAN formats. Up to 18 
decimal digits are accepted and the conversion accuracy 
is the same as for converting in the other direction. 
Greater accuracy can also be achieved with similar 
tradeoffs, as mentioned earlier. 

Description of Operation 

Converting from ASCII to floating point is less complex 
numerically than going from floating point to ASCII. It 
consists of four basic steps: determine the size in deci- 
mal digits of the number, build a BCD value corre- 
sponding to the number string if the decimal point were 
at the far right, calculate the exponent value, and scale 
the BCD value. The first three steps are performed by 
the host software. The fourth step is mainly performed 
by numeric operations. 

The complexity in this function arises due to the flexible 
nature of the input values it will recognize. Most of the 



code simply determines the meaning of each character 
encountered. Two separate number inputs must be rec- 
ognized, mantissa and exponent values. Performing the 
numerics operations is very straightforward. 

The length of the number string is determined first to 
allow building a BCD number from low digits to high 
digits. This technique guarantees that an integer will be 
converted to its exact BCD integer equivalent. 

If the number is a floating point value, then the digit 
string can be scaled appropriately. If a decimal point oc- 
curs within the string, the scale factor must be decreased 
by one for each digit the decimal point is moved to the 
right. This factor must be added to any exponent value 
specified in the number. 

ACCURACY CONSIDERATIONS 

All the same considerations for converting floating 
point to ASCII apply to calculating the scaling factor. 
The accuracy of the scale factor determines the accuracy 
of ihe result. 

The exponents and fractions are again kept separate to 
prevent overflows or underflows during the scaling 
operations. 



LINE 

1 
2 
3 
4 
5 
6 
7 
8 

y 

10 
11 
12 
13 
14 
15 
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 
27 
28 
29 
30 
31 
32 
33 



SOURCE 

$title(ASCII to floating point conversion) 

Define the publicly known names. 

name asci i_to_f loating 
public ascii~to_f loating 
extrn get_poweF_10:near 

This function will convert an ASCII character string to a floating 
point representation. Character strings in integer or scientific form 
will be accepted. The allowed format is: 

[+,-] [digit(s)] [.] fdigit(s)] [E,e] [+,-] [digit (s)] 

Where a digit must have been encountered before the exponent 
indicator *E* or'e'. If a •+•, or was encountered, then at 

least one digit must exist before the optional exponent field. A value 
will always be returned in the 8087 stack. In case of invalid numbers, 
values like indefinite or infinity will be returned. 

The first character not fitting within the format will terminate the 
; conversion. The address of the terminating character will be returned 

; by this subroutine. 

The result will be left on the top of the NPX stack. This 
subroutine expects 3 free NPX stack registers. The sign of the result 
will correspond to any sign characters in the ASCII string. The rounding 
mode in effect at the time the subroutine was called will be used for 
the conversion from bose 10 to base 2. Up to 18 significant decimal 
digits may appear in the number. Leadirio zeroes, trailina zeroes, or 
exponent digits do not count towards the 18 digit maximum. Integers 
or exactly representable decimal numbers of 18 digits or less will be 
exactly converted. The technique used constructs a BCD number 



3-45 



AP-113 



representing the significant ASCII digits of the string with the decimal 
point removed. 

An attempt is made to exactly convert relatively small integers or 
small fractions, tor example the values: .06125, 123456789012345678, 
lel7, 1.23456e5, and 125e-3 will be exactly converted to floating point. 

The exponentiate instruction is used to scale the generated BCD vaslue 
to very large or very small numbers. The basic accuracy of this function 
determines the accuracy of this subroutine. For very large or very small 
numbers, the accuracy of this function is 2 units in the 16th decimal 
place or double precision. The range of decimal powers accepted is 
10**-4930 to 10**4930. 

The PLM/86 calling" format is: 

asci i_to_f loating: 

procedure (string^ptr ,endj?tr ,status_ptr) real external; 
declare (stringptr ,end_ptr ,status_ptr) pointer; 
declare end based endptr pointer; 
declare status based status ptr word; 
end; 

The status value has 6 possible states: 

0 A number was found. 

1 No number was found, return indefinite. 

2 Exponent was expected but none found, return indefinite. 

3 Too many digits were found, return indefinite. 

4 Exponent was too big, return a signed infinity. 

The following registers are used by this subroutine: 



bx 



dx 



si 



di 



Define constants. 



LOW EXPONENT 
HIGfi EXPONENT 
WORD~S IZE 
BCD SIZE 



equ 
equ 
equ 
equ 



-4930 

4930 

2 

10 



; Smallest allowed power of 10 
; Largest allowed power of 10 



Define the parameter layouts involved: 



bp_save 
returnjptr 
status jptr 
end j?tr 
string_ptr 

parms_size 



equ word ptr [bp] 

equ bpjsave + size bp_save 

equ returnjptr + size returnjptr 

equ statusjptr + size status~ptr 

equ end_j>t? + size end_ptr 



equ size statusjptr + size end_ptr + size stjringjotr 
Define the local variable data layouts 



power^ten 
bcd_form 

local, si ze 
; ~~ 



equ word ptr [bp- W0RDJ3IZE] ; power of ten value 

equ tbyte ptr power ten" - BCDJ5IZE; BCD representation 

equ size power jten + size bcd_form 



Define common expressions used 



bcdjbyte equ byte ptr bcd_form 

bcd~count equ (type (bed form)-l)*2 

bcd~sign equ byte ptr Bed form + 9 

bed ""sign bit equ 80H 



Define return values. 

NUMBER POUND equ 0 

NOJJUMBER equ 1 

NO_EXPONENT equ 2 

T00J1ANY DIGITS equ 3 

EXPONENTJTOO BIG equ 4 



3-46 



; Current byte in the BCD form 
; Number of digits in BCD form 
; Address of BCD sign byte 



; Number was found 

; No number was found 

; No exponent was found when expected 

; Too many digits were found 

; Exponent was too big 



AP-113 



108 

109 ; Allocate stack space to insure enough exists at run time. 

110 

111 stack segment stack 'stack 1 

112 db (localjsize+4) dup (?) 



113 stack ends 
114 

115 cgroup group code 

116 code segment public •code 1 

117 assume cs:cgroup 
118 

119 ; Define some of the possible return values. 

120 

121 even ; Optimize 16 bit access 

122 indefinite dd 0FFC00000R ; Single precision real for indefinite 

123 infinity dd 07FF80000R ; Single precision real for +infinity 
124 

125 ascii to floating proc 
126 

127 fldz ; Prepare to zero BCD value 

128 push bp ; Save callers stack environment 

129 mov bp,sp ; Establish stack addressibility 

130 sub sp, local size ; Allocate space for local variables 
131 

132 ; Get any leading sign character to form initial BCD template. 

133 

134 mov si , str ingjptr ; Get starting address of the number 

135 xor dx,dx ; Set initial decimal digit count 

136 eld ; Set autoincrement mode 
137 

138 ; Register usage: 

139 

140 ; al: Current character value being examined 

141 ; cx: Digit count before the decimal point 

142 ; dx: Total digit count 

143 ; si: Pointer to character string 
144 

145 ; Look for an initial sign and skip it if found. 

146 

147 lodsb ; Get first character 

148 cmp al,*+' ; Look for a sign 
149^ jz scan leading digits 

150 ~ 

151 cmp al,'- 1 

152 jnz enter leading digits ; If not test current character 

153 "~ 

154 fchs ; Set TOS = -0 
155 

156 ; Count the number of digits appearing before an optional decimal point. 

157 

158 scan leading digits: 

159 

160 lodsb ; Get next character 

161 < 

162 enter leading digits: 

163 - - 

164 call test_digit ; Test for digit and bump counter 

165 jnc scan leading digits 

166 ~ 

167 ; Look for a possible decimal point and start fbstp operation. 

168 ; The fbstp zeroes out the BCD value and sets the correct sign. 
169 

170 fbstp bcd_form ; Set initial sign and value of BCD number 

171 mov cx,dx ; Save count of digits before decimal point 

172 cmp al, 1 .' 

173 jnz test for digits 

174 - - 

175 ; Count the number of digits appearing after the decimal point. 
176 

177 scan trailing digits: 
178 

179 lodsb * ; Look at next character 

3-47 



AP-113 



180 call testjjigit ; Test for digit and bump counter 

181 jnc scan"~trailing digits 
182 

183 ; There must be at least one digit counted at this point. 

184 

185 test for digits: 
186 

187 dec si j Put si back on terminating character 

188 or dx,dx ; Test digit count 

189 jz no> number found ; Jump if no digits were found 

190 ~ ~ 

191 push si ; Save pointer to terminator 

192 dec si * ,,■ ; Backup pointer to last digit 
193 

194 ; Check that the number will fit in the 18 digit BCD format. 

195 ; CX becomes the initial scaling factor to account for the implied 

196 ; decimal point. 

197 ; > 

198 sub cx,dx v ; For each digit to the right of the 

199 ; decimal point, subtract one from the 

200 ; initial scaling power 

201 neg dx ; Use negative digit count so the 

202 ; test digit routine can count dx up 

203 ; to zero 1 

204 crop dx,-bcd^count ; See if too many digits found 

205 jb test for unneeded digits 
•206 ; 

207 ; Setup initial register values for scanning the number right to left 

208 ; while building the BCD value in memory. 
209 

210 form bed value: 

211 # - - 

212 std ; Set autodecrement mode 

213 mov power^ten,cx ; Set initial power of ten 

214 xor di,di~ ; Clear BCD number index 

215 mov cl,4 ; Set digit shift count 

216 fwait ; Ensure BCD store is done 

217 jmp enter digit loop 

218 " ; / 

219 ; No digits were encountered before testing for the exponent. 

220 ; Restore the string pointer and return an indefinite value. 

221 ; 

222 no number found: 

223 ~ 

224 mov ax, NO NUMBER ; Set return status 

225 fid indefinite j Return an indefinite numeric value 

226 jmp exit 
227 

228 ; Test for a number of the form ???00000. 

229 

230 test terminating point: 

231 ~ ~ 

232 lodsb ; Get last character 

233 cmp , al,'.' ; Look for decimal point 

234 jz enter power zeroes ; Skip forward if found 

235 ■ " 

236 inc si ; Else bump pointer back 

237 jmp short enter power zeroes 

238 ; ~ 

239 ; Too many decimal digits encountered. Attempt to remove leading and 

240 ; trailing digits to bring the total into the bounds of the BCD format. 
241 

242 test for unneeded digits: 

243 ~ . 

244 std ; Set autodecrement mode 

245 or cx,cx ; See if any digits appeared to the 

246 ; right of the decimal point 

247 jz test terminating point ; Jump if none exist 

248 , "~ 

249 dec dx ; Adjust digit counter for loop 
250 

251 ; Scan backwards from the right skipping trailing zeroes. 

252 ; If the end of the number is encountered, dx»0, the string consists of 

253 ; all zeroes! An 



AM 13 



254 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 
268 
269 
270 
271 
272 
273 
274 
275 
276 
277 
278 
279 
280 
281 
282 
283 
284 
285 
286 
287 
288 
289 
290 
291 
292 
293 
294 
295 
296 
297 
298 
299 
300 
301 
302 
303 
304 
305 
306 
307 
308 
309 
310 
311 
312 
313 
314 
315 
316 
317 
318 
319 
320 
321 
322 
323 
324 
325 
326 
327 



skip_trailing_zeroes: 



inc dx 

jz look_for_exponent 
lodsb 

inc cx 

cmp al,'0' 

jz skip_trail ing_zeroes 

dec cx 

cmp al , 1 . 1 

jnz scan_leading_zeroes 

dec dx 



The string is of the form: 1111 A 
See if any zeroes exist to the left of the decimal point. 



; Bump digit count 

; Jump if string of zeroes found! 

; Get next character 

; Bump power value for each trailing 

; zero dropped 



; Adjust power counter from loop 

; Look for decimal point 

; Skip forward if none found 

; Adjust counter for the decimal point 



enter_power_zeroes: 
dec dx 
skip power_zeroes: 



inc 
jz 

lodsb 
inc 
cmp 
jz 

dec 



dx 

look_for_exponent 



cx 

al, '0' 

ski p_powe r_ze roes 
cx 



; Adjust digit counter for loop 



Bump digit count 



; Get next character 

; Bump power value for each trailing 

; zero dropped 



; Adjust power counter from loop 



Scan the leading digits from the left to see if they are zeroes, 
scan leading zeroes: 



lea 

eld 

mov 

lodsb 

cmp 

je 

cmp 
jne 



di,byte ptr [si+1] 
si ,str ing_ptr 
al, 

skip_leading_zeroes 
al,'-' 

enter leading zeroes 



; Save new end of number pointer 

; Set autoinc-rement mode 

; Set pointer to the start 

; Look for sign character 



Drop leading zeroes. None of them affect the power value in cx. 
We are guarenteed at least one non zero digit to terminate the loop. 



skip_leading_zeroes: 
lodsb 

enter leading zeroes: 



Get next character 



inc dx 
cmp al,'0' 
jz skip_leading_zeroes 

dec dx 
cmp al,'.* 
jnz test_digi t_count 

Number is of the form 000.???? 
Drop all leading zeroes with no effect on the power value. 



; Bump digit count 
; Look for a zero 



Adjust digit count from loop 
Look tor 000.??? form 



skip middle zeroes: 

T* ~* 

inc dx 
lodsb 



3-49 



; Remove the digit 
; Get next character 



AP-113 



328 




cmp 


al, '0* 

skipjniddle^zeroes 








329 




jz 








330 












331 




dec 


dx 




i 


Adjust digit count from loop 


332 


; 










333 


; 


All s 


uperflous zeroes are 


removed. Check if all is well now. 


334 














335 


test 


digit count: 








336 














337 




cmp 


dx,-bcd count 








338 




jb 


too many digits found 






339 














340 




mov 


si ,di 




; 


Restore string pointer 


341 




jmp 


form Jbcd^yalue 








342 












343 


too_ 


manydigi ts 


found : 








344 














345 




fid 


indefinite 




; 


Set return numeric value 


346 




mov 


ax, TOO MANY DIGITS 






Set return flag 


347 




pop 


si 




* 


Get last address 


348 






exit 








349 


; 












350 


; 


Build 


BCD form of the decimal 


ASCII string from right to left with 


351 


; 


trailing zeroes and decimal 


point 


removed. Note that the only non 


352 


; 


digit possible is a decimal 


point 


which can be safely ignored. 


353 


; 


Test digit will correctly count 


dx back towards zero to terminate 


354 


; 


the BCD 


build function. 








355 


; 












356 


get- 


digi t^loop: 










357 














358 




lodsb 








Get next character 


359 




call 


test j3igit 






Check if digit and bump digit count 


360 




"jc 


getjfigi t_loop 




i 


Skip the decimal point if found 


361 














362 




shl 


al ,cl 




i 


Put digit into high nibble 


363 




or 


ah,al 




i 


Form BCD byte in ah 


364 




mov 


bed byte [di] ,ah 




i 


Put into BCD string 


365 




inc 


di ~ 




i 


Bump BCD pointer 


366 




or 


dx,dx 






Check if digit is available 


367 




jz 


look_for^exponent 






368 












369 


enter diqit loop: 








370 














371 




lodsb 








Get next character 


372 




call 


test digit 




i 


Check if diqit 


373 




jc 


entered igi t^loop 






Skip the decimal point 


374 










375 




mov 


ahval 




i 


Save digit 


376 




or 


dx,dx 




i 


Check if digit is available 


377 




jnz 


getjdigit^loop 






378 














379 




mov 


bcdj>yteldi] ,ah 




! 


Save last odd digit 


380 












381 




Look 


for an exponent indicator. 




382 














383 


look 


for exponent: 








384 














385 




pop 


si 






Restore string pointer 


386 




eld 






t 


Set autoincrement direction 


387 




mov 


di ,power_ten 




t 


Get current power of ten 


388 




lodsb 






i 


Get next character 


389 




cmp 


al, 'e* 




S 


Look for exponent indication 


390, 




je 


exponent^found 






391 














392 




cmp 


al, 'E' 








393 




jne 


convert 








394 












395 




An exponent is expected, 


get 


its numeric value. 


396 














397 


exponent 'found: 










398 














399 




lodsb 






? 


Get next character 


400 




xor 


di,di 






Clear power variable < 


401 




mov 


cx,di 






Clear exponent sign flag and digit 



3-50 



AM 13 



402 




cmp 


al, •+' 


; Test for positive sign 


403 




je 


s k i p_po we r _s i g n 




404 










405 




cmp 


al, 1 -' 


; Test for negative sign 


406 




jne 


enter^powe r_loop 




407 










408 




The 


exponent is negative. 




409 










410 




inc 


ch 


; Set exponent sign flag 


411 










412 


skip power sign: 




413 








414 


; 


Register usage: 




415 


; 








416 


; 




al: exponent character being examined 


417 


; 




bx: return value 




418 


; 




ch: exponent sign flag 0 positive, 1 negative 


419 


; 




cl: digit flag 


0 no digits found, 1 digits found 


420 


; 




dx: not usable since 


test_digit increments it 


421 


; 




si: string pointer 




422 


; 




di: binary value of 


exponent 


423 


; 








424 


; 


Scan off exponent digits until 


a non-digit is encountered. 


425 










426 


power 


_loop: 






427 










428 




lodsb 




; Get next character 


429 










430 


enter 


power loop: 




431 










432 




mov 


ah ,0 


; Clear ah since ax is added to later 


433 




call 


tested ig it 


; Test tor a digit 


434 




jc 


f o rm_powe r _va 1 ue 


; Exit loop if not 


435 










436 




mov 


cl, 1 


; Set power digit flag 


437 




sal 


di ,1 


; old*2 


438 




add 


ax,di 


; old*2+digit 


439 




sal 


di,l 


; old*4 


440 




sal 


di ,1 


; old*8 


441 




add 


di ,ax 


; old*10+digit 


442 




cmp 


di ,HIGH EXPONENT+bcd count; Check if exponent is too big 


443 




jna 


power_loop 




444 










445 




The 


exponent is too large. 




446 








447 


exponent verflow: 




448 










449 




mov 


ax, EXPONENT TOO BIG 


; Set return value 


450 




fid 


infinity 


; Return infinity 


451 




test 


bed sign, bed sign bit 


; Return correctly signed infinity 


452 




jz 


exit ~~ 


; Jump if not 


453 










454 




fens 




; Return -infinity 


455 




jmp 


short exit 


456 










457 




Nq exponent was found. 




458 










459 


no exponent found: 




460 










461 




dec 


si 


; Put si back on terminating character 


462 




mov 


ax,NO_EXPONENT 


; Set return value 


463 




fid 


indefinite 


; Set number to return 


464 




jmp 


short exit 




465 










466 




The 


string examination is complete. Form the correct power of ten. 


467 










468 


form_ 


power value: 




469 










470 




dec 


si 


; Backup string pointer to terminating 


471 








; character 


472 




rcr 


ch,l 


; Test exponent sign flag 


473 




jnc 


posi t ivejexponent 




474 










475 




neg 


di 


; Force exponent negative 



3-51 



476 

477 positive exponent: 
478 

479 rcr cl,l ; Test exponent digit flag 

480 jnc no exponent found ; If zero then no exponent digits were 

481 " ~" . . ; found 

482 add di, power ten ; Form the final power of ten value 

483 cmp di ,LOW ^EXPONENT ; Check if the value is in range 

484 js exponent overflow ; Jump if exponent is too small 
485 

486 cmp di , HIGH ^EXPONENT 

487 jg exponenF overflow 

488 ^ 

4fr9 inc si ; Adjust string pointer 

490 

491 ; Convert the base 10 number to base 2. 

492 ; Note: 10**exp * 2** (exp*log2 (10) ) 
493 

494 ; di has binary power of ten value to scale the BCD value with. 

495 

496 convert: 
497 

498 dec si ; Bump string pointer back to last character 

499 mov ax,di ; Set power of ten to calculate 

500 or ax, ax ; Test for positive or negative value 

501 js get negative power 

502 "~ « - ■ 

503 ; Scale the BCD value by a value >= 1. 
504 

505 call get^power 10 ; Get the adjustment power of ten 

506 fbld bcd~form ~* ; Get the digits to use 

507 fmul ; Form converged result 

508 jmp short done 
509 

510 ; Calculate a power of ten value > 1 then divide the BCD value with 

511 ; it. This technique is more exact than multiplying the BCD value by 

512 ; a fraction since no negative power of ten can be exactly represented 

513 ; in binary floating point. Using this technique will guarentee exact 

514 ; conversion of values like .5 and .0625. 
515 

516 get negative power: 
517 

518 neg ax ; Force positive power 

519 call get_power 10 ; Get the adjustment power of ten 

520 fbld bcd~form ' ; Get the digits to use 

521 fdivr "~" ; Divide fractions 

522 fxch ; Negate scale factor 

523 fphs 

524 fxch 
525 

526 ; All done, set return values. 

527 ; 

528 done: 
529 

530 fscale ; Update exponent of the result 

531 mov ax,NUMBER_FOUND ; Set return value 

532 fstp st(l) "~ ; Remove the scale factor 
533 

534 exit: 
535 

536 mov di, status ptr ; Set status of the conversion 

537 mov word ptr Tdi],ax 

538 mov di,end_ptr ? Set ending string address 

539 mov word ptr [di],si 

540 mov sp,bp ; Deallocate local storage area 

541 pop bp ; Restore caller's environment 

542 fwait ; Insure all loads from memory are done 

543 ret parms size 

544 ; 

545 ; Test if the character in al is an ASCII digit. 

546 ; If so then convert to binary, bump cx, and clear the carry flag. 

547 ; Else leave as is and set the carry flag. 



3-52 



AM 13 



548 


; 






549 


tested ig it: 




550 


~" cmp 


al r '9' 


551 




ja 


notjHgit 


552 








553 




cmp 


al,'0' 


554 




jb 


not_digit 


555 








556 


; 


Character is a digit. 


557 


§ 






558 




inc 


dx 


559 




sub 


al, 'B* 


560 




ret 




561 








562 




Character is not a digit. 


563 








564 


not digit: 




565 




stc 




566 




ret 




567 








568 


asci i 


to floating endp 


569 


code 




ends 


570 






end 



; See if a digit 



; Bump digit count 

; Convert to binary and clear carry flag 



; Leave as is and set the carry flag 



ASSEMBLY COMPLETE, NO ERRORS FOUND 



APPENDIX E 



OVERVIEW 

Appendix E contains three trigonometric functions for 
sine, cosine, and tangent. All accept a valid angle argu- 
ment between - 2 62 and + 2 62 . They may be called from 
PLM/86, PASCAL/86, FORTRAN/86 or ASM/86 
functions. 

They use the partial tangent instruction together with 
trigonometric identities to calculate the result. They are 
accurate to within 16 units of the low 4 bits of an ex- 
tended precision value. The functions are coded for 
speed and small size, with tradeoffs available for greater 
accuracy. 

FPTAN and FPREM 

These trigonometric functions use the FPTAN instruc- 
tion of the NPX. FPTAN requires that the angle argu- 
ment be between 0 and PI/4 radians, 0 to 45 degrees. 
The FPREM instruction is used to reduce the argument 
down to this range. The low three quotient bits set by 
FPREM identify which octant the original angle was in. 

One FPREM instruction iteration can reduce angles of 
10 18 radians or less in magnitude to PI/4! Larger values 
can be reduced, but the meaning of the result is ques- 
tionable since any errors in the least significant bits of 
that value represent changes of 45 degrees or more in the 
reduced angle. 

Cosine Uses Sine Code 

To save code space, the cosine function uses most of the 
sine function code. .The relation sin (|A|+PI/2) = 
cos(A) is used to convert the cosine argument into a sine 



argument. Adding PI/2 to the angle is performed by 
adding 010 2 to the FPREM quotient bits identifying the 
argument's octant. 

It would be very inaccurate to add PI/2 to the cosine 
argument if it was very much different from PI/2. 

Depending on which octant the argument falls in, a dif- 
ferent relation will be used in the sine and tangent func- 
tions. The program listings show which relations are 
used. 

For the tangent function, the ratio produced by FPTAN 
will be directly evaluated. The sine function will use 
either a sine or cosine relation depending on which oc- 
tant the angle fell into. On exit these functions will nor- 
mally leave a divide instruction in progress to maintain 
concurrency. 

If the input angles are of a restricted range, such as from 
0 to 45 degrees, then considerable optimization is pos- 
sible since full angle reduction and octant identification 
is not necessary. 

All three functions begin by looking at the value given 
to them. Not a number (NAN), infinity, or empty regis- 
ters must be specially treated. Unnormals need to be 
converted to normal values before the FPTAN instruc- 
tion will work correctly. Denormals will be converted to 
very small unnormals which do work correctly for the 
FPTAN instruction. The sign of the angle is saved to 
control the sign of the result. 

Within the functions, close attention was paid to main- 
tain concurrent execution of the 8087 and host. The 
concurrent execution will effectively hide the execution 
time of the decision logic used in the program. 



3-53 



AP-113 



LINE 


SOURCE 






1 


$title(8087 Trignometric Functions) 


2 
3 




public 


sine , cosine , tangent 


4 




name 


trig^f unctions 


5 

6 +1 


$include ( : f 1 :8087.anc) 




7 
8 


; Define 8087 word packing in the environment area. 


9 
10 


f 

cw 87 


record 


res871 s 3 r inf ini ty control : 1# rounding control:2 f 


11 


& """" 




precision control : 2, error enable.ly res872:l f 


12 


& 




precision~"mask : 1 , underflow mask :1 , overflow mask:l. 


13 


& 




zero divide mask : 1 ,denormaT mask:l, invalid jmask:l 


14 








15 


sw 87 


record 


busy : 1 , cond 3 : 1 , t op : 3 , cond 2 : 1 , cond 1 : 1 , cond0 : 1 , 


16 


& 




er ror pend i ng : 1 , res873 : 1 , pr eci si on er ror • 1 r 


17 


& 




underflow error : 1 ,overf low error:lTzero divide error: 


18 


$ 




denormal error : 1 , invalid error:l 


19 








20 


t-w ft 7 


c 


w- ort 7 ¥ ikft • 0 r art (\ fan* 7 r on ^ f* an • 9 rpn4 fan • ? . 


21 






reg3~"tag: 2, reg2~~tag: 2, regl tag: 2, reg0~~tag: 2 


22 








23 


lowjLp_87 


record 


low_ip: 16 


24 








25 
26 


high_i pjap^87 


record 


hi_ip:4,res874:l,opcode_87:ll 


27 


low_opjB7 


record 


low^op: 16 


28 








29 


highjap_87 


record 


hi_op:4,res875:12 


30 








31 


environment_87 


struc 


; 8087 environemnt layout 


32 


env87_cw ~" 


dw 


? 


33 


env87_sw 


dw 


? 


34 


env87~tw 


dw 


? 


35 


env87~"low ip 


dw 


? 


36 


env872hip~op 


dw 


? 


37 


env87 low~op 


dw 


? 


38 


env87Hhop 


dw 


? 


39 


environment JJ7 


ends 




40 








41 


; Define 8087 related constants. 


42 








43 


TOP_VALUE_INC 


equ 


sw_87 <0,0,1,0,0,0,0,0,0,0,0,0,0,0> 


44 








45 


VALID TAG 


equ 


0 ; Tag register values 


46 


ZERO TAG 


equ 


1 


47 


SPECFAL TAG 


equ 


2 


48 


EMPTY TAG 


equ 


3 


49 


REGISTERJ1ASK 


equ 


7 


50 






51 








52 


; Define local 


variable areas. 


53 


; 






54 

55 


stack 


segment 


stack 'stack' 


56 


local^area 


struc 




57 


swl ~* 


dw 


? ; 8087 status value 


58 


local^area 


ends 




59 








60 




db 


size local_area+4 ; Allocate stack space 


61 


stack 


ends 




62 








63 


code 


segment 


public 'code' 


64 




assume 


cs: code , ss: stack 


65 


; 






66 


; Define local 


constants. 


67 


s 






68 


status 


equ 


[bp] .swl ; 8087 status value location 


69 






70 




even 




71 








72 


pi^uarter 


dt 


3FFEC90FDAA22168C235R ; PI/4 



3-54 



AP-113 



indefinite 



dd 



0FFC00000R 



; Indefinite special value 



This subroutine calculates the sine or cosine of the angle, given in 
radians. The angle is in ST(0) , the returned value will be in ST(0). 
The result is accurate to within 7 units of the least significant three 
bits of the NPX extended real format. The PLM/86 definition is: 

sine: procedure (angle) real external; 
declare angle real; 
end sine; 

cosine: procedure (angle) real external; 
declare angle real; 
end cosine; 

Three stack registers are required. The result of the function is 
defined as follows for the following arguments: 



angle 



result 



valid or unnormal less than 2**62 in magnitude correct value 



zero 

denormal 

valid or unnormal greater than 2**62 

infinity 

NAN 

empty 



or 1 

correct denormal 

indefinite 

indefinite 

NAN 

empty 



This function is based on the NPX fptan instruction. The fptan 
instruction will only work with an angle of from 0 to RI/4. With this 
instruction, the sine or cosine of angles from 0 to PI/4 can be accurately 
calculated. The technique used by this routine can calculate a general 
sine or cosine by using one of four possible operations: 



Let 



R * jangle mod PI/41 

S « -1 or 1, according to the sign of the angle 



1) sin(R) 



2) cos(R) 



3) sin(Pl/4-R) 4) cos(PI/4-R) 



114 






The choice of the relation and 


the sign of the result follows the 


115 






decision table shown below based 


on the octant the angle falls in: 


116 








117 






octant sine 


cosine 


118 










119 






0 S*l 


2 


120 






1 S*4 


3 


121 






2 S*2 


-1*1 


122 






3 S*3 


-1*4 


123 






4 -S*l 


-1*2 


124 






5 -S*4 


-1*3 


125 






6 -S*2 


1 


126 






7 -S*3 


4 


127 










128 










129 










130 






Angle to sine function is a zero or unnormal. 


131 










132 


sine 


jeero^urinormal : 




133 










134 






fstp st(l) 


; Remove PI/4 


135 






jnz enter jsine_normalize 


; Jump if angle is unnormal 


136 








137 


§ 


Angle is a zero. 





pop 
ret 



bp 



Return the zero as the result 



; Angle is an unnormal. 

enter sine normalize: 



3-55 



AP-113 



.46 call normali ze^value 

147 jmp short enter sine 

148 ~ 

149 cosine proc s Entry point to cosine 
150 

151 fxam ; Look at the value 

152 push bp ; Establish stack addressibil ity 

153 sub sp,size local_area ' ; Allocate stack space for status 

154 mov bp,sp ~ 

155 fstsw status ; Store status value 

156 fid pi_quarter ; Setup for angle reduce 

157 mov cl7l Siqnal cosine function 

158 pop ax ; Get status value 

159 lahf ; ZF ■ C3, PP * C2, CF » C0 

160 jc f unny_parameter ; Jump if parameter is 

161 ; empty, NAN, or infinity 
162 

163 ; Angle is unnormal, normal, zero, denormal. 
164 

165 fxch ; st(0) ■ angle, st(l) » PI/4 

166 jpe enter sine ; Jump if normal or denormal 

167 ; 

168 ; Angle is an unnormal or zero. 
169 

170 fstp st(l) ; Remove PI/4 

171 jnz enter sine normalize 
172 

173 ; Angle is a zero. cos(0) * 1.0 

174 ; 

175 fstp st(0) ; Remove 0 

176 pop bp ; Restore stack 

177 fldl ; Return 1 

178 ret 

179 ; 

180 ; All work is done as a sine function. By adding PI/2 to the angle 

181 ; a cosine is converted to a sine. Of course the angle addition is not 

182 ; done to the argument but rather to the program logic control values. 
183 

184 sine: ; Entry point for sine function 

185 

186 fxam ; Look at the parameter 

187 push bp ; Establish stack addressibil ity 

188 sub sp,size local^area ; Allocate local space 

189 mov bp,sp "~ 

190 fstsw status ; Look at fxam status 

191 fid pijquarter ; Get PI/4 value 

192 pop ax" ; Get fxam status 

193 lahf ; CF ■ C0, PF - C2, ZF ■ C3 

194 jc funny parameter ; Jump if empty, NAN, or infinity 

195 ; 

196 ; Angle is unnormal, normal, zero, or denormal. 
197 

198 fxch ; ST(1) « PI/4, st(0) angle 

199 mov cl,0 ; Signal sine 

200 jpo sine zero unnormal ; Jump if zero or unnormal 
201 

202 ; ST(0) is either a normal or denormal value. Both will work. 

203 ; Use the fprem instruction to accurately reduce the range of the given 

204 ; angle to within 0 and PI/4 in magnitude. If fprem cannot reduce the 

205 ; angle in one shot, the angle is too big to be meaningful, > 2**62 

206 ; radians. Any roundoff error in the calculation of the angle given 

207 ; could completely change the result of this function. It is safest to 

208 ; call this very rare case an error. 
209 

210 enter sine: 
211 

212 * fprem ; Reduce angle 

213 ; Note that fprem will force a 

214 ; denormal to a very small unnormal 

215 ; Fptan of a very small unnormal 

216 ; will be the same very small 

217 ; unnormal, which is correct. 

218 mov sp,bp ; Allocate stack space for status 

219 fstsw status ; Check if reduction was complete 

3-56 



AP-113 



220 ; Quotient in C0,C3,C1 

221 pop bx ; Get fprem status 

222 test bh,high(mask cond2) ; sin (2*N*PI+x) = sin(x) 

223 jnz anqle too big 

224 - - - 

225 ; Set sign flags and test for which eighth of the revolution the 

226 ; angle fell into. 

227 ; 

228 ; Assert: -PI/4 < st(0) < PI/4 
229 

230 fabs ; Force the argument positive 

231 ; condl bit in bx holds the sign 

232 or cl,cl ; Test for sine or cosine function 

233 jz sine select ; Jump if sine function 

234 ~ 

235 ; This is a cosine function. Ignore the original sign of the angle 

236 ; and add a quarter revolution to the octant id from the fprem instruction. 

237 ; cos (A) « sin(A+PI/2) and cos(|A|) « cos (A) 
238 

239 and ah, not high (mask condl) ; Turn off sign of argument 

240 or bh,high(mask busy) ; Prepare to add 010 to C0,C3,C1 

241 ; status value in ax 

242 ; Set busy bit so carry out from 

243 add bh,high(mask cond3) ; C3 will go into the carry flag 

244 mov al,0 ; Extract carry flag 

245 rcl al,l ; Put carry flag in low bit 

246 xor bh,al ; Add carry to C0 not changing 

247 ; CI flag 
248 

249 ; See if the argument should be reversed, depending on the octant in 

250 ; which the argument fell during fprem. 
251 

252 sine select: 
253 

254 test bh, high (mask condl) ; Reverse angle if CI = 1 

255 jz no sine reverse 

256 ; ~ 

257 ; Angle was in octants 1,3,5,7. 
258 

259 fsub ; Invert sense of rotation 

260 jmp short do sine fptan ; 0 < arg <= PI/4 
261 

262 ; Angle was in octants 0,2,4,6. 

263 ; Test for a zero argument since fptan will not work if st(0) ■ 0 
264 

265 no sine reverse: 

266 " 

267 ftst ; Test for zero angle 

268 v mov sp,bp ; Allocate stack space 

269 fstsw status ; cond3 * 1 if st(0) « 0 

270 fstp st(l) ; Remove PI/4 

271 pop cx ; Get ftst status 

272 test ch,high(mask cond3) ; If C3*l, argument is zero 

273 jnz sine argument zero 

274 ; ~ 

275 ; Assert: 0 < st(0) <» PI/4 
276 

277 do sine fptan: 
278 

279 fptan ; TAN ST(0) * ST(1)/ST(0) « Y/X 

280 

281 after sine fptan: 
282 

283 pop bp ; Restore stack 

2?4 test bh,high(mask cond3 + mask condl); Look at octant angle fell into 

285 jpo X numerator ; Calculate cosine for octants 

286 ~ ; 1,2,5,6 
287 

288 ; Calculate the sine of the argument. 

289 ; sin(A) tan (A) /sqrt (1+tan (A) **2) if tan(A) * Y/X then 

290 ; sin (A) ■ Y/sqrt(X*X + Y*Y) 
291 

292 fid st(l) ; Copy Y value 

293 jmp short finish^sine ; Put Y value in numerator 



3-57 



AP-113 

7 



294 










295 




The 


top of the stack is either NAN , infinity, or empty. 


296 










297 


f unny parameter : 




298 










299 




fstp 


st(0) 


Remove PI/4 


300 




jz 


return_empty ; 


Return empty if no parm 


ivx 










302 




jpo 


return_NAN ; 


Jump if st(0) is NAN 


iv5 


i 








304 


} 


st (0 


) is infinity. Return an indefinite value. 


jW j 


; 








JlOD 




f prem 




ST(1) can be anything 


J v I 










308 


return 


NAN: 






309 


returnjsmpty: 






310 








311 




pop 


bp 


Restore stack 


312 




ret 


i 


Ok to leave fprem running 


313 










314 




Simulate fptan with st(0) = 0 




315 










316 


sine argument 


zero: 




in 








318 




fldl 


i 


Simulate tan(0) 


319 




jmp 


after _sine_fptan ; 


Return the zero value 


320 








321 




The 


angle was too large. Remove the modulus and dividend from the 


322 




stack 


and return an indefinite result. 




323 










324 


angle too big: 






325 










326 




fcompp 




Pop two values from the stack 


"J 01 
Oct 




fid 


indefinite ; 


Return indefinite 


J<£0 




pop 


bp ; 


Restore stack 


329 




fwait 




Wait for load to finish 






ret 






331 










332 




Calculate the cosine of the argument. 








cos (A) 


* l/sqrt(l+tan(A)**2) if tan(A) 


* Y/X then 


334 




cos (A) 


* X/sqrt(X*X + Y*Y) 














JJD 


X numerator: 






337 










338 




fid 


st(0) 


Copy X value 


339 




f xch 


st(2) 


Put X in numerator 


340 










341 


finish 


sine: 






342 








343 




fmul 


st,st(0) ; 


Form X*X + Y*Y 


344 




fxch 




345 




fmul 


st, st (0) 




346 




fadd 


! 


st(0) * X*X + Y*Y 


347 




fsqrt 




st(0) » sqrt(X*X + Y*Y) 












349 










350 




Form 


the sign of the result. The two conditions are the CI flag from 


351 




FXAM in bh and the C0 flag from fprem in 


ah. 


352 










353 




and 


bh f high (mask cond0) ; 


Look at the fprem C0 flag 


354 




and 


ah,high(mask condl) ; 


Look at the fxam CI, flag 


355 




or 


bh,ah ; 


Even number of flags cancel 


356 




jpe 


positive^sine ; 


Two negatives make a positive 


357 










358 




fchs 


; 


Force result negative 


359 








360 


positive sine: 






361 










362 




fdiv 


; 


Form final result 


363 




ret 




Ok to leave fdiv running 


364 








365 


cosine 


endp 






366 











3-58 



AM 13 



367 
368 
369 
370 
371 
372 
373 
374 
375 
376 
377 
378 
379 
380 
381 
382 
383 
384 
385 
386 
387 
388 
389 
390 
391 
392 
393 
394 
395 
396 
397 
398 
399 
400 
401 
402 
403 
404 
405 
406 
407 
408 
409 
410 
411 
412 
413 
414 
415 
416 
417 
418 
419 
420 
421 
422 
423 
424 
425 
426 
427 
428 
429 
430 
431 
432 
433 
434 
435 
436 
437 
438 
439 
440 



This function will calculate the tangent of an angle. 
The angle, in radians is passed in ST(0), the tangent is returned 
in ST(0). The tangent is calculated to an accuracy of 4 units in the 
least three significant bits of an extended real format number. The 
PLM/86 calling format is: 

tangent: procedure (angle) real external; 
declare angle real; 
end tangent; 

Two stack registers are used. The result of the tangent function is 
defined for the following cases: 



angle 

valid or unnormal < 2**62 in magnitude 
0 

denormal 

valid or unnormal > 2**62 in magnitude 
NAN 

infinity 
empty 



result 

correct value 
0 

correct denormal 

indefinite 

NAN 

indefinite 
empty 



The tangent instruction uses the fptan instruction. Four possible 
relations are used: 

Let R « I angle MOD PI/4 1 

S ■ -1 or 1 depending on the sign of the angle > 



1) tan(R) 



2) tan(PI/4-R) 3) l/tan(R) 



4) l/tan(PI/4-R) 



The following table is used to decide which relation to use depending 
on in which octant the angle fell. 



octant 



tangent proc 

f xam 
push 
sub 
mov 
f stsw 
fid 
Pop 
lahf 
jc 



relation 

S*l 

S*4 
-S*3 
-S*2 

S*l 

S*4 
-S*3 
-S*2 



bp 

sp,size local area 

bp,sp 

status 

pi^quarter 

ax~ 



Look at the parameter 
Establish stack addressibility 
Allocate local variable space 

Get fxam status 
Get PI/4 



CF 



C0, PF ■ C2, 2F = C3 



funnyj?arameter 
Angle is unnormal, normal, zero, or denormal. 



fxch 
jpe 



tan zero unnormal 



st(0) * angle, st(l) ■ PI/4 



Angle is either an normal or denormal. 
Reduce the angle to the range -PI/4 < result < PI/4. 

If fprem cannot perform this operation in one try, the magnitude of the 
angle must be > 2**62. Such an angle is so large that any rounding 
errors could make a very large difference in the reduced angle. 
It is safest to call this very rare case an error. 



tan__normal : 

fprem 



; Quotient in C0,C3,C1 

; Convert denormals into unnormals 



3-59 



AP«113 



441 




mov 


sp,bp 


Allocate stack spce 


442 




* fstsw 


status ; 


Quotient identifies octant 


443 








original angle fell into 


444 




pop 


bx 


tan(PI*N+x) * tan(x) 


445 




test 


bh,high(mask cond2) ; 


Test for complete reduction 


446 




jnz 


angle jtoo big ; 


Exit if angle was too big 


447 


; 








448 


; 


See if the anqle must be reversed. 




449 


; 








450 


; 


Assert: 


-PI/4 < st(0) < PI/4 


• 


451 


; 








452 




fabs 




0 <* st(0) < PI/4 


453 








CI in bx has the sign flag 


454 




test 


bh, high (mask condl) ; 


must be reversed 


455 




jz 


no _t an ^reverse 




456 


; 






457 


; 


Angle 


fell in octants 1,3,5,7. Reverse 


it, subtract it from PI/4. 


458 


; 






459 




f sub 




Reverse angle 


460 




jmp 


short do^tangent 




461 


; 






462 


! 


Angle 


is either zero or an unnormal. 




463 


$ 






464 


tan 


zero unnormal: 




465 










466 




fstp 


st(l) 


Remove PI/4 


467 




jz 


tan_angle__zero 




468 


; 








469 


i 


Angle 


is an unnormal. 




470 


i 






471 




call 


normalize value 




472 




jmp 


tanjiormar 




473 








474 


tan 


_angle_zero: 






475 










476 




pop 


bp 


Restore stack 


477 




ret 






478 


i 








479 


i 


Angle 


fell in octants 0,2,4,6. Test for st(0) * 0, fptan won't work 


480 


; 








481 




tanreverse: 






482 










483 




ftst 


? 


Test for zero angle 


484 




mov 


sp,bp 


Allocate stack space 


485 




fstsw 


status ; 


C3 * 1 if st(0) ■ 0 


486 




fstp 


st(l) 


Remove PI/4 


487 




pop 


cx 


Get ftst status 


488 




test 


ch,high(mask cond3) 




489 




jnz 


tan _ zero 




490 








491 




tangent : 






492 










493 




fptan 




tan ST(0) ■ < ST(1)/ST(0) 


494 








495 


after tangent: 






496 










497 




Decide on the order of the operands and 


their sign for the divide 


498 




operation while the fptan instruction is 


wo rk i ng • 


499 


; 






500 




Pop 


bp 


Restore stack 


501 




mov 


al,bh ; 


Get a copy of fprem C3 flag 


502 




and 


ax, mask condl + high (mask cond3); 


Examine fprem C3 flag and 


503 






# 


fxtract CI flag 


504 




test 


bh,high(mask condl + mask cond3); 


Use reverse divide if in 


505 








octants 1,2,5,6 


506 




jpo 


reverse^_di vide ; 


Note! parity works on low 


507 








8 bits only! 


508 


f 






509 


; 


Angle 


was in octants 0,3,4,7. 




510 


; 


Test for the sign of the result. Two negatives cancel. 


511 


; 








512 




or , 


al,ah 




513 




jpe 


posi tiye_divide 





3-60 



AM13 



514 
515 
516 
517 
518 
519 
520 
521 
522 
523 
524 
525 
526 
527 
528 
529 
530 
531 
532 
533 
534 
535 
536 
537 
538 
539 
540 
541 
542 
543 
544 
545 
546 
547 
548 
549 
550 
551 
552 
553 
554 
555 
556 
557 
558 
559 
560 
561 



fchs 

positivejdivide: 

fdiv 
ret 



tan zero: 



fldl 



after tangent 



; Force result negative 



; Form result 

; Ok to leave fdiv running 



; Force 1/0 « tan (PI/2) 



Angle was in octants 1,2,5,6. 
Set the correct sign of the result. 



reverse divide: 



or 
jpe 



al ,ah 

posit ive^r jdivide 



fchs 

positive_r_divide: 

fdivr 
ret 



; Force result negative 



; Form reciprocal of result 
j Ok to leave fdiv running 



tangent endp 
; 

; This function will normalize the value in st(0). 

; Then PI/4 is placed into st(l). 



no rma 1 i ze^ya 1 ue s 

f abs 
f xtract 
fldl 
fadd 
f sub 
f scale 
fstp 
fid 
fxch 
ret 



st (1) ,st 



st(l) 

pi quarter 



; Force value positive 

; 0 <= st(0) < 1 

; Get normalize bit 

; Normalize fraction 

; Restore original value 

; Form original normalized value 

; Remove scale factor 

; Get PI/4 



code 



ends 
end 



ASSEMBLY COMPLETE, NO ERRORS FOUND 



3-61 



intol APPLICATION AP-122 

NOTE 



September 1981 




©INTEL CORPORATION, 1981 3-62 



A P- 122 



I. INTRODUCTION 

This application note describes the design of a disk con- 
troller for a Shugart SA4008 Winchester disk drive. An 
8089 I/O processor is used to offload many of the disk 
control overhead tasks from the host processor. The in- 
telligent controller maximizes system throughput by 
performing the disk control tasks concurrently with 
data processing by the host processor. The features of 
the 8089 I/O processor which make it ideal for disk con- 
trol applications are also described. 

As newer microprocessors provide more throughput 
and address more memory, larger and more complex 
microprocessor based applications are designed. Many 
of these applications require high performance and high 
capacity mass storage devices such as hard disk drives. 
Winchester-technology (filtered air system and non- 
removable platters) disk drives are cost and perfor- 
mance compatible with high performance micro- 
processors. These drives provide more performance and 
reliability than floppy disk drives yet are less expensive 
than removable platter disk drives of comparable per- 
formance. 

For applications requiring high performance disk 
drives, a major task of the system designer is the design 
of the disk controller— the interface between the high 
performance processor and disk drive. The conven- 
tional approach (Fig. 1) is to develop specialized control 



circuitry which interfaces the disk drive to the host 
processor's system bus. The host has complete control 
over the disk drive and executes a separate command se- 
quence for each function— such as seek, format or read 
data. The host is assisted by a DMA (direct memory 
access) controller which performs the high speed trans- 
fers of read or write data between the drive interface 
and the system memory. Any error processing, such as 
CRC (cyclic redundancy check) error checking and in- 
itiating retries, is also performed by the host processor. 
A major disadvantage of this approach is that a large 
portion of the host's time and bus bandwidth is con- 
sumed by disk control overhead (command execution, 
interrupt servicing, and error processing) leaving little 
time for data processing. 

A better approach is to partition the system functions 
and implement an intelligent disk controller which 
would perform the overhead tasks and free more host 
processor time for data processing. This intelligent con- 
troller would be able to accept a single high level com- 
mand and perform multiple functions such as seek, read 
data, and process errors. Here the host has more time 
for data processing since it generates one high level com- 
mand rather than several simple commands. It also ser- 
vices only one interrupt at the completion of the high 
level command rather than several. 

The system configuration of an intelligent disk con- 
troller based on the Intel 8089 I/O processor is shown in 



HOST 
PROCESSOR 



C=4 



SYSTEM 
MEMORY 



£3 



DISK CONTROLLER 

I 1 



PARALLEL 
I/O 



V 



i i 



DMA 
CONTROLLER 



CONTROL 





1 ■ 


SERIAL/ 




PARALLEL 


1 


CONVERTER 






-I— 



Figure 1. Conventional Disk Controller System Configuration 

3-63 



AFN02057A 



A P. 122 



Figure 2 where it is used in conjunction with an 8086 
CPU as the host processor. This type of system con- 
figuration is called the iAPX 86/11 since it contains an 
8086 and an 8089. The 8089 I/O processor is ideal for 
implementing an intelligent controller since it provides 
processing capabilities well suited for controlling a disk 
drive and high speed DMA transfers for moving data to 
and from the disk drive. The 8089 also supports a 
private local bus which provides access to the drive con- 
trol circuitry, program memory, and local data buffers. 
This minimizes access to the shared system bus and 
hence increases overall system throughput. It will be 
seen later that local data buffering allows: 

— high speed burst transfers without overrun and 
underrun errors 

— disk controller operation at lower system bus priority 
than the host to maximize host processing 

— error detection and retries directly by the disk con- 
troller without host intervention 

The 8089-based disk controller maximizes system 
throughput. The disk control overhead tasks are off- 
loaded from the host and performed by the 8089. This 
frees host processor time for data processing and other 
control processing. Host processor performance is 
reduced when both the host and 8089 try to access the 
system bus at the same time. These system bus conflicts 
can only occur when the 8089 accesses the system 
bus — during the accessing of memory-based com- 
munication blocks (used for transferring command and 



status information) and during sector data transfers be- 
tween the system memory buffer and the 8089* s local 
data buffer. For a single drive, this can mean host proc- 
essor performance degradation of no more than 3%. 
With the conventional approach of Figure 1, the degra- 
dation can approach 10% due to CPU overhead time to 
control the disk operation and system bus time used by 
the DMA controller. Thus the 8089-based controller 
allows significantly more processing by the host, espe- 
cially when multiple drives are supported. 

This application note describes how basic disk control 
functions are implemented with an 8089. Therefore, the 
design described here does not exhibit all features pos- 
sible in an intelligent controller. However, the hardware 
design allows the software to be easily enhanced to pro- 
vide extra features. A later section addresses software 
enhancements. 

The application note begins with an overview of the 
8089 I/O processor followed by a brief description of 
the SA4008 drive. Next a discussion of the implemented 
functions is provided. A detailed description of the 
hardware and software design is then presented. Finally, 
a discussion of possible enhancements concludes the 
note. 

Additional information related to topics discussed in 
this application note can be found in the following Intel 
documents: 

The 8086 Family User's Manual 



8086 

HOST 
PROCESSOR 



A K 



SYSTEM 
BUS 
INTERFACE 



A-K 



LOCAL 
MEMORY 



SYSTEM 
MEMORY 



0 



DISK CONTROLLER 



I/O 

PROCESSOR 



J-N 
tV 



SYSTEM 
BUS 
INTERFACE 



— V 



LOCAL 
BUS 
INTERFACE 



L 



LOCAL 
MEMORY 



vrv 



L \rV 



PARALLEL 
I/O 



A- 

Jvt 



SERIAL/ 
PARALLEL 
CONVERTER 



„ WRITE 
DATA 



READ 
" DATA 



I 



Figure 2. Intelligent Disk Controller System Configuration (iAPX 86/11) 

3-64 



AFN02057A 



AP-122 



Intel Multibus Specification 

iSBC 86/12A Hardware Reference Manual 

iSBC 604/614 Cardcage Hardware Reference Manual 

ICE-86 In-Circuit Emulator Operating Instructions for 
ISIS-II Users 

RBF-89 Real-Time Breakpoint Facility Operating In- 
structions for ICE-86 In-Circuit Emulator Users 

8089 Macro Assembler User's Guide 

In addition, the following documents from Shugart 
Associates provides detailed information on the disk 
drive: 

SA4000 Fixed Disk Drive OEM Manual 
SA4000 Fixed Disk Drive Service Manual 



II. INTEL® 8089 I/O PROCESSOR 

This section briefly describes the 8089 I/O processor's 
features and modes of operation. A more detailed dis- 
cussion can be found in The 8086 Family User's Manual 
(October 1979). 

A block diagram of the 8089 I/O processor is shown in 
Figure 3. The 8089 provides two independent channels. 
Both channels can execute task program instructions 
and perform high speed DMA transfers. Each channel 
has its own register set to support these operations. 

A channel starts operation by executing task program 
instructions. These instructions are conceptually similar 



to instructions of other microprocessors but are typi- 
cally executed to prepare the channel and I/O device for 
DMA transfers. Execution of the XFER (transfer) in- 
struction switches the channel from instruction execu- 
tion mode to DMA mode and high speed data transfer 
cycles are performed. When the DMA transfer termi- 
nates, task program instruction execution resumes for 
any post-DMA processing (e.g., status analysis, error 
processing, etc.). One channel or two channels may be 
operating at any given time. When two channels are ac- 
tive, they operate in a time-multiplexed manner sharing 
a common multiplexed address/data bus. A flexible pri- 
ority structure allows both channels to operate with 
equal priorities or either channel to operate at a higher 
priority. 

The 8089' s bus structure and timing are identical with 
other members of the iAPX 86 and iAPX 88 families, 
such as the 8086 CPU and 8087 numeric processor ex- 
tension. This allows the bipolar support circuits of the 
iAPX 86 and 88 families (8284A clock generator, 8288 
bus controller, 8289 bus arbiter, etc.) to be used with the 
8089. The 8089 generates 20 address signals and, 
depending on how it is initialized, supports an 8- or 
16-bit data bus. This provides compatibility with the 
16-bit 8086 CPU or the 8-bit 8088 CPU. 

Both channels can access a 1 megabyte system address 
space and a 64 kilobyte local address space. Each ad- 
dress space accommodates both memory and I/O 
devices. This allows task program execution, memory 
data access, and I/O device access in both system and 
local address spaces. Task program and DMA access of 
the two address spaces is discussed later. 



CA SEL RESET 

111 



COMMON 
CONTROL 
UNIT 



I 




TASK POINTER 



I/O CONTROL 



TASK POINTER 



I/O CONTROL 



TTT Ml 

DRQ1 EXT 1 SINTR-1 DRQ 2 EXT 2 SINTR-2 



ASSEMBLY/ 
DISASSEMBLY 
REGISTERS 



INSTRUCTION 
FETCH 



MULTIPLEXED 
ADDRESS/DATA BUS 



I 2oL 

1 AD15-AD0 
I A19/S6-A16/S3 
BUS A I 

INTERFACE 4mJ 
UNIT 1 



READY 
CLK 
RQ/GT 



Figure 3. 8089 I/O Processor Block Diagram 

3-65 



AFN02057A 



A P- 122 



The 8288 bus controller used with the 8089 provides 
separate command signals for each address space. The 
bus controller's memory read and write commands pro- 
vide access to the system address space and the I/O read 
and write commands are used to access the local address 
space. Separate commands for each address space allow 
two external buses to be implemented which promotes 
concurrent processing between the 8089 and the host 
processor and increases system throughput. 

In addition, the 8089 allows these physical buses to be 
either 8 or 16 bits wide. During the 8089's initialization 
sequence, the widths of the system and local buses are 
defined. Although the 8089 supports two buses, a single 
bus may be used which is shared with a CPU. This will 
be described later when local and remote mode con- 
figurations are discussed. 

The interface signals used to communicate with a host 
processor are also shown in Figure 3. The channel atten- 
tion (CA) and select (SEQ input signals are used to start 
channel operation. Both signals are activated simul- 
taneously by the host. SEL selects channel 1 or channel 
2 (0 or 1, respectively). The SINTR1 and SINTR2 out- 
put signals are used to interrupt the host processor. One 
of these signals is activated whenever the set interrupt 
instruction, SINTR, is executed. SINTR1 is activated by 
channel 1 and SINTR2 by channel 2. The memory- 
based communication structure used to transfer com- 
mand and status information between the 8089 and the 
host processor is discussed in a later section. 



System Configurations 

Systems using the 8089 may be configured in one of two 
different ways— local mode or remote mode. In the 
local configuration, the 8089 provides capabilities of an 
intelligent DMA controller for a single CPU. In the 
remote configuration, the 8089 provides capabilities of 
a control processor and a DMA controller and can 
operate concurrently with one or more host processors. 

Local Mode Configuration 

In the local mode configuration, the 8089 resides on the 
same local bus as an 8086 or 8088 CPU and shares the 
clock generator, address latches, data transceivers, and 
bus controller with the CPU. An example of a local 
mode iAPX 88/11 (8088 CPU and 8089 I/O processor) 
configuration is shown in Figure 4. 

The 8089 is a slave to the CPU in local mode configura- 
tions and access to the shared bus is controlled by the 1 
bidirectional request/grant (RQ/GT) line. The CPU has 
possession of the bus when system operation begins. 
Whenever the 8089 needs access to the bus, it signals the 
CPU of this need by pulsing the RCj/GT line. The CPU 
may be presently accessing the bus. As soon as the CPU 
is finished with the bus, it pulses the RQ/GT line. The 
8089 receives this grant pulse and accesses the bus. 
When the 8089 is finished using the bus, the 8089 pulses 
the RQ/GT line to notify the CPU that it has released 
the bus. 

Once the 8089 acquires the bus, it retains bus possession 
until finished. The request/grant protocol provides no 



8088 

CPU 



SQ/ST 



RQ/GT 

8089 

IOP 

DRQ2 DRQ1 
EXT2 EXT1 



8288 

BUS 
CONTROLLER 



LATCHES & 
TRANSCEIVERS 



SYSTEM MEMORY 



I/O DEVICE 1 I/O DEVICE 2 



Figure 4. Typical Local Mode Configuration (iAPX 88/11) 

3-66 



AFN02057A 



AP-122 



mechanism for the CPU to regain the bus from the 
8089. Care should be used when selecting this configura- 
tion since frequent or lengthy periods of 8089 activity 
can limit the CPU's use of the bus. However, the local 
mode configuration is an economical technique for add- 
ing intelligent, high speed DMA transfer capabilities to 
the system. 

In local mode configurations, the 8089' s 1 megabyte 
system address space coincides with the CPU's memory 
address space and the 64 kilobyte local address space 
coincides with the CPU's I/O address space. This means 
that when the 8089 accesses its system space or when the 
CPU accesses its memory space, the 8288 bus control- 
ler's memory read or write command is activated. When 
the 8089 accesses its local space or when the CPU ac- 
cesses its I/O space, the bus controller's I/O read or 
write command is activated. 

The 8089's physical data bus widths must be defined the 
same as the CPU's during the initialization sequence (to 
be discussed later) in local mode configurations. With 
an 8088 CPU the 8089' s system and local physical bus 
widths must be initialized as 8 bits. When used with an 
8086 CPU, both buses must be initialized as 16 bits. 

Although the 8089 can execute programs and access 
memory and I/O devices from its two address spaces, 
several rules should be followed to ensure compatibility 
with the CPU. Data memory that is shared with the 
CPU must be accessed in the 8089' s system address 
space. I/O devices which are accessed by the CPU in its 
I/O address space must be accessed in the 8089' s local 
address space. Other memory and I/O devices accessed 
by the 8089 only may reside in either the 8089's system 
or local address space. 

Remote Mode Configuration 

In the remote mode configuration, a shared system bus 
with memory provides communications between the 
host processor and the 8089 I/O processor (Fig. 5). The 



HOST 
PROCESSOR 
MODULE 



8089 

I/O 

PROCESSOR 
MODULE 



SHARED 
MEMORY 



8089 supports two independent externally-implemented 
physical buses (Fig. 6). One bus is the shared system bus 
and the other is a private local bus. The system bus 
interface contains address latches, data transceivers, a 
bus controller, and a bus arbiter. The host processor 
uses an identical interface to access the system bus. The 
8289 bus arbiter controls access to the system bus and is 
responsible for acquiring and surrendering the bus 
based on system priorities. The local bus interface con- 
tains address latches and data transceivers (if required 
by loading conditions). 

The 8089's 1 megabyte system address space is used to 
access the shared system bus and the 64 kilobyte local 
address space is used to access the private local bus. A 
single 8288 bus controller provides command signals for 
both the system and local buses, The memory read and 
write commands are used to access both memory and 
I/O devices on the system bus. The I/O read and write 
commands are used when accessing memory or I/O 
devices on the local bus. 

The physical widths of the system and local buses may 
be 8 or 16 bits. The widths are defined during the in- 
itialization sequence (to be discussed later). All four bus 
width combinations are available: 

8-bit system bus and 8-bit local bus 

8-bit system bus and 16-bit local bus 

16-bit system bus and 8-bit local bus 

16-bit system bus and 16-bit local bus 



IE 



LOCAL 
MEMORY 



II 



8089 A 

iop A- 



LATCHES 
TRANSCEIVERS 



8288 

BUS 
CONTROLLER 



S2l 



8289 

BUS ARBITER 



LATCHES 
TRANSCEIVERS 



ED 



\7 



SHARED SYSTEM BUS 



Figure 5. Remote Mode Configuration 



Figure 6. Typical 8089 I/O Processor Module 
(Remote Mote) 



3-67 



AP122 



The system bus width is typically established by the host 
processor. A 16-bit system bus is usually used with a 
16-bit host while an 8-bit bus with an 8-bit host. The 
local bus width is typically selected based on the peri- 
pheral devices supported— 8-bit bus with 8-bit peri- 
pherals and 16-bit bus with 16-bit peripherals. A 16-bit 
local bus is selected when both 8- and 16-bit peripherals 
are supported since it allows task program and DMA ac- 
cessing of both 8- and 16-bit I/O devices. DMA capa- 
bilities are discussed later. Memory devices are con- 
figured so that the width of the memory's data path is 
the same as the physical bus. 

Communications With Host Processor 

Communications between the host processor and the 
8089 I/O processor are primarily through shared 
memory. The hardwired signals (CA and SEL to the 
8089 and SINTR1 and SINTR2 from the 8089) are used 
as startup and interrupt signals. Memory-based commu- 
nication is implemented through a series of five linked 
control blocks (Fig. 7). This feature provides a very flex- 
ible communication structure and allows the 8089 to 
handle a wide variety of I/O functions. 

The first three linked blocks in the' communication 
structure are used during the 8089's initialization se- 
quence (Fig. 8). The system configuration pointer (SCP) 
and system configuration block (SCB) are used only 
during initialization. Initialization is required after a 
RESET signal is received by the 8089. When the first 
channel attention after reset is received, the initializa- 
tion sequence begins and the 8089 reads the data in the 
system configuration pointer. The parameter SYSBUS 
defines the physical width of the system bus (8 or 16 
bits). The SCB offset and segment base point to the se- 
cond block, the system configuration block (SCB). The 
8089 next reads the data in the SCB. The SOC param- 
eter defines the local bus's physical width and re- 
quest/grant mode (refer to The 8086 Family User's 
Manual). The CB offset and segment base point to the 
channel control block (CB). The 8089 clears (zeros) 
channel l's BUSY byte in the CB which completes the 
initialization sequence. With subsequent channel atten- 
^ tions, the 8089 directly accesses the CB as described 
below. 

The SCP, SCB and CB must reside in shared memory 
since both the host and the 8089 access them. The SCP 
must begin at 0FFFF6H while SCB and CB locations are 
user-defined. The SCP is typically located in ROM 
while the SCB and CB are in RAM. With the SCP in 
ROM, the SCB's location remains fixed once defined. 
Since each 8089 must have a unique CB, the SCB (which 
points to the 8089's CB) must be placed in RAM if mul- 
tiple 8089's exist in the system. This allows each 8089 to 
be initialized and directed to its own CB. The CB must 



be in RAM since certain parameters are updated during 
8089 operation (e.g., BUSY byte). 

The channel control, parameter and task blocks are 
used whenever the host starts channel operation. The 
host initializes certain parameters in the channel control 
and parameter blocks before generating the channel 
attention signal. When the 8089 receives a channel 
attention signal, the proper half of the CB is accessed 
depending on the value of SEL (0 for channel 1 and 1 
for channel 2). The CCW (channel control word) in- 
structs the selected channel what action to perform, 



SYSTEM 
CONFIGURATION 
POINTER 
(SCP) 



SYSTEM 
CONFIGURATION 
BLOCK 
(SCB) 



CHANNEL 
CONTROL 
BLOCK 
(CB) 



PARAMETER 
BLOCK 
(PB1) 



TASK 
BLOCK 
(TB1) 



HIGH MEMORY 



SCB SEGMENT BASE 



SCB OFFSET 



CB SEGMENT BASE 



CB OFFSET 



SOC 



PB2 SEGMENT BASE 



CCW 



PB1 SEGMENT BASE 



BUSY 



TB1 SEGMENT BASE 



CHANNEL 1 
TASK PROGRAM 



LOW MEMORY 



Figure 7. Memory Based Communication Blocks 



3-68 



AFN02057A 



AP-122 



HIGH SYSTEM MEMORY 





(RESERVED) 






SCB SEGMENT BASE 




SYSTEM 


SCB OFFSET 




CONFIGURATION 
POINTER 


(RESERVED) 


SYSBUS 




(FIXED LOCATION) 


8086/8088 
RESET LOCATION 




\ 






SYSTEM 


CB SEGMENT BASE 


!- 


CONFIGURATION 
BLOCK 


CB OFFSET 




(USER-DEFINED LOCATION) 


(RESERVED) 


SOC 













CHANNEL 
CONTROL 
BLOCK 
(USER-DEFINED LOCATION) 



(RESERVED) 



PB2 SEGMENT BASE 



PB2 OFFSET 



(RESERVED) 



PB1 SEGMENT BASE 



FFFFEH 
FFFFCH 
FFFFAH 
FFFF8H 
FFFF6H 
FFFF4H 
FFFF2H 
FFFFOH 



CHANNEL 2 
* PARAMETER BLOCK 



CHANNEL 1 
* PARAMETER BLOCK 



LOW SYSTEM MEMORY - . 



Figure 8. Initialization Control Blocks 



such as start, suspend, resume, or halt task program 
execution. The BUSY byte is set to OFFH by the 8089 if 
task program execution is started or resumed. The 8089 
clears it to OH if task program execution is suspended or 
halted. Within the channel control block, PB1 offset 
and segment base point to the parameter block for chan- 
nel 1 and PB2 offset and segment base point to the 
parameter block for channel 2. From the proper param- 
eter block, the 8089 reads the task block (TBI or TB2) 
offset and segment base which point to the task pro- 
gram. The task block address must be the first two 



words of the parameter block. All other parameters in 
the PB are user-defined allowing parameters to be tail- 
ored to a specific I/O task. 

Of all the five linked blocks, only the task block may 
reside either in system or local memory. For remote 
mode configurations, the task block typically resides in 
local memory to obtain maximum system performance. 
However, executing task programs from system 
memory is advantageous for initial debugging or for ex- 
ecuting a task program that downloads another task 
program from system memory to local RAM. 

AFN02057A 



3-69 



/ 



AP-122 



DMA Capabilities 

The 8089's high speed DMA capability is ideal for disk 
controller applications. The maximum DMA transfer 
rate with a 5 MHz clock is 1 .25 megabytes/sec. Conven- 
tional DMA controllers use a single bus cycle and gate 
data from the source device (memory or I/O) to the 
destination device. However, the 8089*8 DMA transfer 
uses two bus cycles. The first bus cycle reads the data 
from the source device and the second bus cycle writes 
the data to the destination device. The advantages of 
two cycle DMA are discussed in a later section. 

All possible combinations of source and destination 
device specifications are available. Both source and 
destination may be memory or an I/O device. This 
means that memory to memory, I/O to I/O, and 
memory to or from I/O DMA transfers are available. In 
addition, DMA transfers between system and local ad- 
dress spaces or within the same address space can be 
specified. 

Both memory and I/O devices (source and destination) 
are specified as addresses either in the system or local 
address space. These address values are loaded into 
source and destination pointer registers. After each 
word or byte is transferred, a register used as a memory 
pointer is incremented by one for byte transfers or by 
two for word transfers. A register used as an I/O device 
pointer is not modified. Registers used as DMA memory 
pointers are incremented only. No provisions exist for 
decrementing memory pointer registers during DMA. 

DMA Synchronization 

To accommodate a wide range of I/O device transfer 
rates, the 8089 allows DMA transfers to be synchro- 
nized. Each byte or word is transferred between the I/O 
device and the 8089 upon receiving a DMA request 
synchronizing signal from the I/O device. Each channel 
has a DMA request input: DRQ1 for channel 1 and 
DRQ2 for channel 2. Three options exist when specify- 
ing DMA transfer synchronization. DMA transfers may 
be source synchronized, destination synchronized, or 
unsynchronized. 

During source synchronized DMA transfers, the chan- 
nel waits until the DMA request input is activated by the 
source device before reading the data. External circuitry 
decodes the source device's address and provides a 
DMA acknowledge signal to the source device allowing 
it to deactivate the DMA request signal. Immediately 
after reading the data, the 8089 writes it to the destina- 
tion device. The next read and write cycles begin when 
the source device activates DMA request again. Source 
synchronized DMA transfers are typically used when 
transferring data from an I/O device to memory. 



During destination synchronized DMA transfers, the 
channel reads the data from the source device and waits 
for the DMA request signal before writing the data to 
the destination device. Similar to source synchroniza- 
tion, the DMA acknowledge signal is generated by 
decoding the destination device's address. This type of 
synchronization is commonly used when transferring 
data from memory to an I/O device. 

The final synchronization option is to specify no synch- 
ronization. Here the DMA request input is not exam- 
ined and the channel transfers data without waiting for 
a request. This specification is usually reserved for 
memory to memory transfers. The channel runs at full 
memory speed. Wait states may be used when accessing 
slow memory devices or when waiting to access the 
shared system bus. 

DMA latency is the time required for the 8089 to re- 
spond to a DMA request; i.e., the time from DMA re- 
quest signal activation until the synchronized bus cycle 
begins. DMA latency is due to DMA request propaga- 
tion through internal pipelined control circuitry. The 
maximum DMA latency time when one channel is active 
and waiting for DMA request is 6 clocks. When both 
channels are active, the latency time may be up to 12 
clocks. 

Due to DMA latency, the DMA request signal cannot be 
used to synchronize transfers when the transfer rate of 
the I/O device is close (greater than 0.7 megabytes/sec 
when one channel is active) to the maximum transfer 
rate of the 8089, 1.25 megabytes/sec. For this case, wait 
states may be used to synchronize transfers. Since hard 
disk drives are in this category, the disk controller 
described in this application note uses wait states to 
synchronize disk transfers. 

Advantages of Two Cycle DMA 

The two bus cycle implementation of DMA transfers 
allows enhanced DMA capabilities. Data transfers be- 
tween source and destination devices with different data 
widths may be specified. For example (Fig. 9), a DMA 
transfer cycle from an 8-bit I/O device to 16-bit memory 
is accomplished by reading two bytes from the I/O de- 
vice (two bus cycles), assembling the bytes into a word, 
and then writing a single word into memory (one bus cy- 
cle). Here buses are accessed efficiently since three bus 
cycles are required as compared to four bus cycles if a 
single byte at a time were read and written. In the same 
example, since the 16-bit memory resides on the shared 
system bus, 50% fewer system bus accesses are required 
and overall system throughput may be increased. 

Use of this bus matching DMA feature involves specify- 
ing logical DMA source and destination bus widths with 



3-70 



AFN02057A 



AP-122 



BYTE 



8089 

ADDR/DATA 



8-BIT LOCAL BUS 



8-BIT 
MEMORY 



K LOCAL A | I K SYSTEM A K 

) BUS [ ) BUS ( 16-BIT SYSTEM BUS > 

y INTERFACE \j ]/ INTERFACE \| J 



8-BIT 
I/O 
DEVICE 



16-BIT 
MEMORY 



Figure 9. 8-Bit I/O to 16-Bit Memory DMA 



the WID instruction. This allows DMA transfers to or 
from 8-bit I/O devices which reside on a 16-bit bus. The 
only restriction is that the logical bus width may not ex- 
ceed the physical width. Thus 8- or 16-bit transfers may 
be performed with a 16-bit bus while only 8-bit transfers 
are permitted with an 8-bit bus (Fig. 10). Synchronized 



DMA transfers between dissimilar width logical buses 
may have more than one synchronized bus cycle. For ex- 
ample, destination synchronized transfers from 16-bit 
memory to an 8-bit I/O device perform two synchro- 
nized 8-bit write bus cycles for each 16-bit fetch from 
memory. 




8-BIT 
MEMORY 



8 AND 16-BIT _, . ^ 8- BIT LOGICAL_ 

"LOGICAL WIDTHS te WIDTH ONLY 



Figure 10. Logical Bus Widths for DMA Transfers 

3-71 



AFN02057A 



AP-122 



Another feature derived from the two bus cycle DMA 
approach is character translation during DMA mode. 
Byte data may be translated via a 256-byte translation or 
lookup table. During each DMA transfer cycle, a byte 
of data is read from the source device, the data byte is 
translated, and then the translated byte is written to the 
destination device. Three bus cycles are required here 
since the translation requires a fetch cycle from 
memory. 

Two bus cycle DMA also allows DMA transfers to be 
terminated based on masked comparison of the trans- 
ferred data. This is discussed in the next section. 

DMA Termination 

The 8089 allows several conditions to terminate DMA 
transfers. One condition or several conditions may be 
specified. When several conditions are specified, DMA 
transfers are terminated when any one condition is 
detected. In addition, different task program re-entry 
points may be specified for each condition. This permits 
special post-DMA processing based on the terminate 
condition. Task program re-entry points are specified as 
offsets which are added to the task pointer. Three off- 
sets are available: 0, 4, or 8. These offsets permit long or 
short jumps to termination routines. When more than 
one terminate condition occurs simultaneously, task 
program execution is resumed at the largest offset of the 
simultaneously occurring terminate conditions. An ex- 
ception to this rule exists. The byte count terminate con- 
dition has highest priority and its offset is used if this 
terminate condition occurred. 

DMA transfers can be terminated when the byte count 
(BC) register, which is decremented after each byte or 
word is transferred, reaches zero. The 16-bit BC register 
is initialized by task program instructions before the 
DMA transfer is started and permits data transfers of 
up to 64 kilobytes to be terminated. Each channel has an 
external terminate (EXT) input which can be activated 
by external circuitry to terminate the DMA transfer. 
Another condition allows termination based on masked 
comparison of transferred data. As byte data is trans- 
ferred, an 8-bit mask value selects which bits of the data 
are compared with corresponding bits of an 8-bit com- 
pare value. Termination can be specified to occur either 
when a match occurs or does not occur. Examples using 
this terminate condition are transferring data until an 
EOF character is detected (match) and transferring data 
while bit 7=1 (mismatch). A final terminate condition 
called single transfer allows a single byte or word to be 
transferred. 

Register Set 

The register set of the 8089 is presented in Figure 11. 
Each channel has its own set of registers, except for the 



TAG 





CP. ADDRESS A (OA) 




G.P. ADDRESS B (GB) 




G.P. ADDRESS C (GC) 




TASK POINTER (TP) 



15 p 



I 



INDEX 


(IX) 


BYTE COUNT 


(BC) 


MASK J CMPR 


CHAN CNTL 


<CC) 



19 



PARAMETER PNTR (PP) 




CHAN CNTL PNTR (CP) 



Figure 11. 8089 Register Set 



channel control pointer register (CP) which is shared by 
both channels. This register is 20 bits in size and is used 
to access the channel control block whenever a channel 
receives a channel attention signal. Each channel has a 
20-bit parameter pointer register (PP) which provides 
access to the parameter block. The common CP register 
is initialized during the 8089's initialization sequence 
while the PP registers are initialized whenever a channel 
attention signal is received. Therefore, the CP and PP 
may be read during task program execution, but cannot 
be changed. 

Each channel has four 20-bit registers, each with an 
associated tag bit. The tag bit is used whenever the regis- 
ter is used as a pointer and indicates which address space 
(system or local) is accessed. If the tag bit is equal to 0, 
the 1 megabyte system address space is accessed using all 
20 bits of the register. However, if the tag bit is equal to 
1 , the 64 kilobyte local address space is accessed using 
the lower* 16 bits of the register. Instructions that initial- . 
ize these registers either set or clear the tag bit. The load 
pointer instruction clears the tag bit, the move instruc- 
tion sets the tag bit, and the move pointer instruction 
which moves data from memory into the register's 20 
bits and tag bit either sets or clears the tag bit based on 
the contents of the referenced memory location. 

The task pointer register (TP) is used as a tdsk program 
counter. The remaining three 20-bit registers (GA, GB, 
and GC) are general-purpose registers. During task pro- 
gram execution, they may be used for data manipula- 
tion or as pointers. During DMA mode, the GA and GB 
registers point to source and destination devices and if 



3-72 



AFN02057A 



AP-122 



the translation option is specified, the GC register 
points to a 256-byte translation table. Two source/ 
destination register specifications are possible: (1) GA 
points to the source and GB to the destination and (2) 
GB points to the source and GA to the destination. 

Four 16-bit registers are also included in each channel's 
register set. The index register (IX) may be used by task 
program instructions to access memory and I/O 
devices. The address of the memory or I/O device is 
computed by adding the contents of IX with the con- 
tents of the specified pointer register. The byte count 
register (BC) can terminate DMA transfers. The mask/ 
compare register (MC) may be used to perform masked 
compare operations during task program execution or 
masked compare DMA terminations. The channel con- 
trol register (CC) specifies the details of DMA transfers 
(refer to The 8086 Family User's Manual). Although 
these four 16-bit registers have special functions at 
times, they may also be used as general-purpose regis- 
ters for data manipulation. Use of the CC register for 
general-purpose functions is not recommended when 
both channels are simultaneously used since the chain 
bit specifies channel priority. 

Instruction Set 

In addition to intelligent, high speed DMA transfers 
which make the 8089 well-suited for I/O processing, the 
set of 53 instructions is tailored for I/O operations 
rather than data processing. Task programs are pri- 
marily used to prepare for and initiate DMA transfers 
and to perform post-DMA status checking. Included in 
the instruction set are data transfer, arithmetic, logical 
and bit manipulation, program transfer, and processor 
control instructions. 

Data transfer instructions move information between 
registers and memory or I/O devices. Movement of data 
between any two devices in either address space is easily 
accomplished with the MOV instruction. This includes 
memory to memory and I/O to I/O transfers. Arith- 
metic instructions such as add, increment, and decre- 
ment are provided for simple computations (e.g., 
pointer manipulation) required in I/O processing. The 
logical and bit manipulation instructions are especially 
useful in the I/O environment to mask data and set or 
clear bits. 

Procedure calls and conditional and unconditional 
jumps are provided with the program transfer instruc- 
tions. Jump if masked compare equal or not equal and 
jump if bit true or false instructions are also included in 
this group. Finally, the processor control instructions 
perform test and set while locked operations (sema- 
phore access), define logical DMA bus widths, initiate 
DMA transfers, activate the SINTR interrupt output 
lines, and halt task program execution. 



Special Design Considerations 

Most interrupt signals received by the 8089 are used to 
synchronize DMA transfers and the 8089' s DMA re- 
quest (DRQ) inputs support these interrupts. The 8089 
also supports non-DMA related interrupt signals. 

Most non-DMA interrupts are used to synchronize 
channel program execution with some external event. 
Here channel program execution is suspended and the 
channel waits until the synchronizing signal is received 
before resuming task program execution. A disk control 
example is waiting for the INDEX signal before for- < 
matting the track. 

A dummy DMA transfer can be used to implement this 
function. This is a synchronized, externally terminated 
DMA transfer where no data is actually transferred. 
The DMA request (DRQ) signal is held inactive and the 
channel executes idle cycles while waiting for either 
DRQ or EXT (external terminate) signals. 

No bus cycles are executed by the channel during idle 
cycles. The channel's EXT input is used to receive the 
synchronizing signal. When received, the dummy DMA 
transfer is terminated and channel program execution 
resumes. The dummy DMA transfer can also be viewed 
as the iAPX 86/10's WAIT instruction. 

This concept can also be applied when two channels are 
operating. For example, one channel may be waiting for 
a synchronizing signal while the other channel is oper- 
ating. Here the second channel can execute at full speed 
since the first channel is executing idle cycles. 

One application of this two channel approach is to per- 
form two independent DMA transfers in rapid succes- 
sion. After the first DMA transfer, conditions are tested 
to determine if the second DMA transfer is performed. 
One channel (e.g., channel 1) initializes its registers for 
the second DMA transfer and executes a dummy DMA 
transfer. Next, the other channel (e.g., channel 2) ini- 
tializes its registers for the first DMA transfer. Channel 
2 performs the first DMA transfer, activates channel l's 
EXT input, and halts. Channel 1 resumes task program 
execution and determines whether conditions permit the 
second DMA transfer. If the proper conditions are pre- 
sent, the DMA transfer is performed. The two DMA 
transfers are performed in rapid succession because 
both channels initialized their registers before either 
DMA transfer was performed. A single channel im- 
plementation must re-initialize its registers after the first 
DMA transfer before performing the second DMA 
transfer. Therefore, the time between successive DMA 
transfers is increased. 

In the example above, channel 1 performs two DMA 
transfers— a dummy DMA transfer and then the second 
DMA transfer. Registers are initialized for the second 
DMA transfer before the dummy DMA transfer is per- 



3-73 



AFN92057A 



A P. 122 



formed. Therefore, aH DMA register changes resulting 
from the dummy DMA transfer must be accounted for 
when initializing the registers. Synchronized DMA 
transfers between I/O and memory update the byte 
count register (BC) and the memory pointer register 
(GA or GB), During each two cycle transfer, BC is 
decremented during the data fetch bus cycle and GA or 
GB is incremented during the data store bus cycle. Since 
the dummy DMA transfer never stores the data (DRQ 
remains inactive), the memory pointer is never incre- 
mented. However, BC may or may not be decremented 
depending on whether source or destination synchro- 
nization is selected. If source synchronization is 
selected, BC is not decremented because the data is not 
fetched. However, since the data is prefetched during 
destination synchronized DMA transfers, BC is 
decremented. This means that BC must be adjusted only 
when a destination synchronized DMA transfer follows 
the dummy DMA transfer. Here BC must be loaded 
with the actual number of data bytes to be transferred 
plus one for byte transfers or plus two for word trans- 
fers. A byte transfer is defined as the fetching and stor- 
ing of a single byte. All other cases are considered word 
transfers since the net result is that 16 bits of data are 
transferred during the two or more bus pycles. 



III. SHUGART SA4008 DRIVE 

The Shugart Associates SA4008 disk drive is typical of 
Winchester drives now being , used in microcomputer 
systems. The unformatted drive capacity is 29 mega- 
bytes. Typical of high performance drives, the transfer 
rate is 889 kilobytes/second and the average seek time is 
65 milliseconds. A summary of the drivel performance 
and functional specifications is included in Appendix A. 

Drive Organization 

The Shugart SA4008 drive has two 14-inch disk platters. 
The top and bottom surfaces of these two platters pro- 
vide four recording surfaces. Each recording surface 
contains 404 concentric circular data paths called 
tracks. The tracks on each surface are accessed by two 
read/write heads which move along the radial distance 
of the circular platter (Fig. 12). The two heads are rigid- 
ly connected and move in unison. One read/write head 
travels from the outermost track of the surface to the 
midway point between the outermost and innermost 
tracks. The other head travels from the midway point to 
the innermost track. Each of the four surfaces has two 
read/ write heads (eight total heads). The drive's head 
positioning mechanism moves all eight heads |n unison 
onto 202 discrete positions called cylinders (numbered 0 
through 201). The head mechanism is positioned at 




Figure 12. SA4008 Drive with Two Heads Per Surface 



cylinder 0 when the outermost track is accessed and at 
cylinder 201 when the innermost track is accessed. At 
each cylinder position, eight unique data tracks are 
accessible, one by each head. By activating the elec- 
tronics of one read/ write head, a single data track is ac- 
cessed. With 8 heads and 202 cylinders, the SA4008 has 
a total of 1,616 tracks. 

Sector Format 

Data is recorded on sections of the track called sectors. 
The number of sectors per track is a function of the con- 
troller design. The SA4008 allows any number of sectors 
per track. This design organizes each track into 30 sec- 
tors (Fig. 13). The 600 bytes of each sector is divided 
into an ID field, data field and gaps. The ID field is a 
unique identifier or address used to locate a particular 
data record. The data field contains the 512 byte data 
record that is read or written by the host processor. 
Gaps containing no usable information are inserted 
before and after the ID and data fields to allow the drive 
and controller electronics time for synchronization and 
switching between read and write modes. 

Assignment of sequential records to sectors is inter- 
leaved using an interleave code of 3 such that logical sec- 
tors are three physical sectors apart (Fig. 14). Since a 
data record is buffered in local memory, this interleave 
scheme allows two sector times to transfer the data 
record to or from system memory. This allows the disk 
controller to operate at lower system bus priority and 
provides enough time to transfer the data record be- 
tween the local buffer and system buffer. When the 
8089 has complete use of the system bus, a 512 byte data 
record can be transferred in 564 ^sec which is 84% of 



3-74 



AFN02057A 



AP-122 



INDEX 



JL 

JL 



PHYSICAL SECTOR 0 



LOGICAL SECTOR 0 




S hytp H C nPB" HEA D SECTOR CRC 




PHYSICAL SECTOR 1 



PHYSICAL SECTOR 29 



JL 
JL 



LOGICAL SECTOR 10 




LOGICAL SECTOR 29 



7 41 515 
-600 BYTES/SECTOR - 



Figure 13. Track Format 



INDEX ^Jl . , 

PHYSICAL SECTOR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 

LOGICAL SECTOR S \ 0 | 10 j 20 | 1 | 11 | 21 | 2 | 12 | 22 \ 3 | 13 | 23 I 4 | 14 | 24 | \ - 



INDEX 

PHYSICAL SECTOR 
LOGICAL SECTOR 



15 16 17 18 19 20 21 22' 23 24 25 26 27 28 29 
\ 5 | 15 | 25 | 6 | 16 | 26 | 7 | 17 | 27 | 8 | 18 [ 28 | 9 | 19 | 29 | \ 



Figure 14. Interleaved Sector Ordering 



the 672 /*sec sector time. The selected interleave scheme 
permits up to 10 sequential logical sectors to be accessed 
per 20.2 millisecond disk revolution. 

To access up to 15 sequential logical sectors per revolu- 
tion, an interleave code of 2 could be used. For this 
case, logical sectors are two physical sectors apart and 
the buffered data record must be transferred to or from 
system memory in one sector time (672 jisec). Thi& re- 



quires that the 8089 retain possession of the system bus 
for the entire data record transfer after acquir ing the 
system bus. The 8089 can accomplish this with a LOCK 
output signal which is discussed later. The 564 jtsec 
data record transfer time allows 108 jtsec to set up the 
DMA transfer to or from the system bus, obtain posses- 
sion of the system bus, and prepare for a subsequent 
disk sector access. 



3-75 



AFN02057A 



AP-122 



Disk Drive Interface Signals 

The interface signals (Fig. 15) between the SA4008 drive 
and the controller are now described. The input control 
signals are first described, followed by the output con- 
trol signals, and finally the data transfer signals. 

The input control signals to the drive are DRIVE 
SELECT, DIRECTION SELECT, STfeP, HEAD 
SELECT, FAULT CLEAR, WRITE GATE, and 
READ GATE. Four drive select signals, DRIVE 
SELECT 1 to 4, allow selection of one drive in a multi- 
ple drive configuration of up to four drives. A jumper is 
used to select one of the DRIVE SELECT signals and 
allows the drive to respond to only one DRIVE 
SELECT signal. The DRIVE SELECT 4/SEEK COM- 
PLETE line can be jumper selected as the DRIVE 
SELECT 4 signal or SEEK COMPLETE signal (see 



Figure 15. SA4008 Interface Signals 



description below). The DIRECTION SELECT and 
STEP signals are used to position the read/write heads. 
DIRECTION SELECT defines an inward or outward 
movement while the STEP line is pulsed. Each pulse 
moves the heads one cylinder position. Four head select 
signals, HEAD SELECT 1 , 2, 4 and 8, are used to select 
one of the SA4008 , s eight read/ write heads. Four 
signals are provided to allow eight optional fixed heads 
to be selected. The FAULT CLEAR signal is used to 
reset a write fault condition. The WRITE GATE signal 
enables data to be written on the selected data track, 
while the READ GATE enables reading from the track. 

The output control signals from the drive are TRACK 
00, INDEX, READY, WRITE FAULT, SEEK COM- 
PLETE, and BYTE CLOCK/SECTOR. The TRACK 
00 signal is activated when the read/write heads are 
positioned at track 0 (cylinder 0). The INDEX signal is 
pulsed once each revolution (20.2 msec) indicating the 
beginning of the data track. The READY signal in- 
dicates that the drivers ready to position the read/write 
heads, read data, or write data. The WRITE FAULT 
signal indicates that a condition which caused improper 
writing on the disk occurred. The SEEK COMPLETE 
signal is available in a single drive configuration and in- 
dicates when the read/write heads have arrived at the 
desired cylinder during a seek operation. The DRIVE 
SELECT 4/SEEK COMPLETE line can be jumper 
selected as the DRIVE SELECT 4 signal (multiple drive 
configuration) or SEEK COMPLETE (signal drive con- 
figuration). The SEEK COMPLETE signal is selected 
with the controller described in this application note. 
The BYTE CLOCK/SECTOR line is another jumper 
selectable signal. It can be configured as the BYTE 
CLOCK signal (1.12 /*sec period) or as the SECTOR 
signal. The number of SECTOR pulses per revolution is 
jumper programmable. The controller described here 
requires selection of the SECTOR signal and 30 sector 
pulses per revolution. 

The SA4008 provides four data transfer signals: 
WRITE DATA, WRITE CLOCK, READ DATA and 
PLO (Phase Locked Oscillator) CLOCK. All of these 
are differential signals. The WRITE DATA and 
WRITE CLOCK signals are received by the drive and 
used to write data on the track. The WRITE DATA 
signal provides the data while the WRITE CLOCK 
signal is used to sample the data. The READ DATA and 
PLO CLOCK signals are transmitted by the drive and 
used to read data from the track. The READ DATA 
signal provides the data while the PLO CLOCK signal is 
used to sample the data. Both the WRITE DATA and 
READ DATA signals are in the non-return to zero 
(NRZ) format. 

A detailed description and timing of the interface 
signals can be obtained from the Shugart Associates 
manuals referenced in the introduction. 



DRIVE SELECT 1 
DRIVE SELECT 2 



DRIVE SELECT 3 

DRIVE SELECT 4/SEEK COMPLETE 



DIRECTION SELECT 



HEAD SELECT 1 
HEAD SELECT 2 



HEAD SELECT 4 
HEAD SELECT 8 



FAULT CLEAR 



CONTROLLER 



SA4008 
DRIVE 



WRITE FAULT 
BYTE CLOCK/SECTOR 



+ WRITE DATA 
- WRITE DATA 



+ WRITE CLOCK 
- WRITE CLOCK 



+ PLO CLOCK 



3-76 



AFN02057A 



AM 22 



Functional Operations 

The SA4O08 provides three functional operations: track 
accessing, write data, and read data. These operations 
are initiated and controlled by certain interface signals. 

Track accessing (seeking from one track to another) is 
accomplished by activating the DRIVE SELECT line 
and deactivating the WRITE GATE line. Inward or out- 
ward movement is selected by activating or deactivating, 
respectively, the DIRECTION SELECT line. The STEP 
line is pulsed once for each track that the read/write 
heads are moved. 

Writing data to the SA4008 is initiated by activating the 
DRIVE SELECT line, selecting the desired read/write 
head by activating the HEAD SELECT lines, and pro- 
viding a clock signal on the WRITE CLOCK line. The 
WRITE GATE line is then activated and the data to be 
written is transmitted on the WRITE DATA line. The 
WRITE GATE line is deactivated to terminate writing. 

Reading data from the SA4008 is initiated by activating 
the DRIVE SELECT line and selecting the desired 
read/write head by activating the HEAD SELECT 
lines. The READ GATE line is then activated and the 
data is read on the READ DATA line using the PLO 
CLOCK signal to sample the data. The READ GATE 
line is deactivated to terminate reading. 



IV. DISK CONTROLLER OPERATIONS 

By using an 8089, the disk controller becomes an intelli- 
gent interface between the host processor and the disk 
drive. The host issues a single high level command for 
the desired operation and the 8089 implements the 
operation through task program control. 

The 8089-based disk controller described in this applica- 
tion note implements four basic disk control operations: 
seek track, format track, write data record, and read 
data record. The previous section described the three 
functional operations of the SA4008 drive: track access- 
ing, write data, and read data. The controller uses these 
three drive operations to implement the four high level 
operations. An overview of the four operations is now 
presented. This serves as an introduction to the disk 
controller before hardware and software details are 
described. 

Seek Track 

The seek track operation is implemented primarily 
through task program control with minimal use of 
special hardware. Based on the cylinder which is pres- 
ently accessed by the read/ write head mechanism, the 
task program determines which direction (inward or 
outward) the head mechanism must be moved. The 
number of cylinder positions that the heads must be 



moved is also determined. The task program writes data 
to an octal latch which transmits the DIRECTION 
SELECT and STEP signals to the SA4008 drive. By 
writing the proper data sequence to the octal latch, 
DIRECTION SELECT is asserted and STEP is pulsed 
the required number of times. Finally the task program 
asserts the drive's head select (HEAD SELECT 1, 2, 4 
and 8) signals to access the desired track. 

Format Track 

The format track, write data record, and read data 
record operations are implemented by a task program 
which controls special hardware. Details of the special 
hardware are described in the next section. 

The timing overview of the format track operation is 
presented in Figure 16. The INDEX, SECTOR and 
READ DATA signals from the drive and the WRITE 
GATE, WRITE DATA, and READ GATE signals to 
the drive are shown. 8089 channel activity is also shown. 
The READ GATE and READ DATA signals remain in- 
active during the format track operation. 

Channel 1 begins the format track operation by initializ- 
ing the registers for the DMA transfer which writes sec- 
tor O's ID data on the track. Serial/parallel conversion 
hardware is used to convert the 8089's parallel data to 
serial so that it can be received by the drive. The hard- 
ware is initialized with zeros so that when the WRITE 
GATE is activated, zeros are written on the track. Next 
a dummy DMA transfer is used to wait for the INDEX 
pulse which indicates the beginning of the track. 

When the INDEX pulse is received, channel 1 resumes 
execution. The INDEX pulse also activates the WRITE 
GATE signal to the drive and zeros are written on the 
track. Timing hardware which was started by the SEC- 
TOR pulse determines when to stop writing zeros and 
begin the write ID field DMA transfer. A synch 
character is written on the track before the ID field and 
CRC word after the ID field. After the ID data for sec- 
tor 0 has been written on the track, the hardware 
resumes writing zeros. 

Channel 1 next initializes the DMA registers for writing 
ID data to the next sector. A dummy DMA transfer is 
started to wait for the SECTOR pulse. Channel 1 now 
idles while it waits for the SECTOR pulse. Note that 
zeros continue to be written on the track between ID 
data. 

ID data for the remaining 29 sectors is written on the 
track identically to the first sector. After ID data is writ- 
ten for the last sector, channel 1 deactivates the WRITE 
GATE signal. WRITE GATE deactivation is delayed so 
that zeros are written into the data field. This ensures 
that after a data record has been written (in the last sec- 
tor), the required zeros are present before and after the 
data field. 



3-77 



AFN02057A 



AP-122 



INDEX 



.JL 



WRITE GATE 



WRITE DATA 



READ GATE 



READ DATA 



JL 



JL 



JL 
JL 



) ACTIVITY | CHANNEL 1 | | CHANNEL 1 | ^ [ " 



Figure 16. Format Track Timing Overview 



Write Data Record 

The data transfer operations (write data record and read 
data record) are implemented with both 8089 channels 
(Fig. 17). Channel 2 searches for the desired sector by 
comparing the ID field information read from the track 
with the desired ID field information. The comparison 
is performed by a hardware comparator. One input of 
the comparator accepts ID information read from the 
track while the other input accepts the desired ID infor- 
mation transferred from channel 2 using DMA 
transfers. Upon locating the desired sector, channel 1 
transfers the data record to or from the track using 
DMA transfers. Both channels perform DMA transfers 
using the technique described earlier which allows two 
DMA transfers in rapid succession. 

Higher data capacity is achieved with this two channel 
approach than with a single channel approach. With 
two channels, all DMA registers are initialized before 
either DMA transfer is started. No register re- 
initialization is required betwen the DMA transfers for 
the two channel approach. To allow for register re- 
initialization between DMA transfers in the single chan- 
nel approach, a larger gap between the ID and data 
fields is required. This results in lower data capacity per 
track and therefore lower data capacity per drive. 



INITIALIZE 
REGISTERS FOR 
DATA TRANSFER 



COMPARE ID > CHANNEL 2 




TRANSFER DATA 
RECORD TO/FROM 
DISK DRIVE 



Figure 17. Sector Search and Data Transfer 



3-78 



AFN02057A 



AP-122 



The write data record operation begins with channel 1 
initializing DMA registers used to transfer the data 
record to the track (Fig. 17) and starting a dummy DMA 
transfer. Next channel 2 initializes its DMA registers 
used to transfer the desired ID information to the hard- 
ware comparator. Channel 2 waits for a SECTOR pulse 
with a dummy DMA transfer. When the SECTOR pulse 
is detected, channel 2 performs the "compare' ' DMA 
transfer, activates channel l's EXT input and halts. 

Activation of EXT terminates channel 1 's dummy DMA 
transfer and resumes task program execution. The hard- 
ware comparator is tested to determine if the desired 
sector is found (i.e., the compare is successful). If not 
found, the ID field comparison is repeated for the sub- 
sequent sector. If the desired sector is found, the data 
record is written in the data field which follows the ID 
field. 

The timing overview of Figure 18 shows the sector ac- 
tivity when the desired sector is found. Channel 2's 
dummy DMA transfer is terminated by the SECTOR 
pulse and the READ GATE signal is activated. This 



allows the serial/parallel conversion hardware to read 
the serial data from the track and convert it to a parallel 
format. The beginning of the ID field is found by hard- 
ware that searches for a synch character. When 
detected, channel 2's DMA transfer moves the desired 
ID information to the hardware comparator synchro- 
nously with the ID information from the track arriving 
at the comparator. Finally, channel 2 activates channel 
l's EXT input and halts. Channel 2's sector search 
activity is the same for all sectors. 

Channel 1 resumes execution, tests the hardware com- 
parator, and deactivates the READ GATE signal. 
Figure 18 shows that channel 1 then activates the 
WRITE GATE signal and zeros are written on the 
track. Timing hardware which was started by the detec- 
tion of the ID field's synch character determines when 
to stop writing zeros and begin the write data record 
DMA transfer. A synch character precedes the data 
record and an CRC word follows the data record. 
Finally channel 1 deactivates the WRITE GATE signal 
and halts. 



JL 



JL 



WRITE GATE 



WRITE DATA 



J SYNCH [WORD WORD | CRC |^ 



READ DATA j synch | Z | crc [_ 



8089 ACTIVITY _J~ 



CHANNEL 2 



IT 



Figure 18. Write Data Record Timing Overview 



3-79 



AFN02057A 



AP-122 



Read Data Record 

The read data record operation is similar to the write 
data record operation. The sector search activity is iden- 
tical. Only channel l's activity after locating the desired 
sector is different. 

The timing overview of Figure 19 shows that when chan- 
nel 1 resumes execution the hardware comparator is 
tested and the READ GATE signal is deactivated. Next 
the READ GATE is again activated and the hardware 



searches for the synch character. The READ GATE 
signal is momentarily deactivated so that the disk drive 
does not read where the WRITE GATE has been ac- 
tivated (during a previous write data record operation). 
This ensures that the drive's data separator decodes data 
properly. When the synch character is detected, channel 
l's DMA transfer reads the data record from the track. 
Finally, channel 1 checks for a CRC error, deactivates 
the READ GATE signal, and halts. 



sector J"L 



JL 



WRITE GATE 



WRITE DATA 



I SYNCH I ID I CRC 



— — | SYNCH |wORPl|—il-.| WORD | CRC | 



8089 ACTIVITY 



IT 



CHANNEL 1 



Figure 19. Read Data Record Timing Overview 



3-80 



AFN02057A 



AM 22 



V. HARDWARE DESIGN 

The controller was designed to be compatible with 
Multibus, an industry-standard multiprocessor system 
bus. It was constructed on an iSBC 905 Universal Pro- 
totype board using wirewrap interconnections. Seventy- 
five IC packages reside on this 6-3/4 by 12 inch board. 
The development environment consisted of the con- 
troller board, an iSBC 86/12A single board computer 
(based on the iAPX 86/10) which served as the host pro- 
cessor, and an iSBC 604 cardcage which provided a 
Multibus interconnect between the two boards. Other 
development tools used were an ICE-86 in-circuit emu- 
lator and the RBF-89 real-time breakpoint facility. 

A block diagram of the disk controller is shown in 
Figure 20. The hardware is divided into four major sec- 
tions — I/O processor, Multibus interface, timing and 
control, and data transfer. The 8089 I/O processor 
along with the timing and control circuitry supervise all 
disk control operations. The 8089* s interface to the tim- 
ing and control circuitry is through control and status 
registers which are part of the timing and control 
section. 

I/O Processor 

The I/O processor section (Figure 21) consists of the 
8089, support circuitry, local bus interface, and local 
memory. Support circuitry includes the 8284 A clock 
generator and the 8288 bus controller. The clock 
generator is configured in asynchronous mode since 
ready signals are generated asynchronously with respect 
to the 8089's clock signal. The 8089's local bus read 
signal, IO RD, is generated from t he bus controller's 
IORC and INTA commands since INTA is activated 
whenever the 8089 fetches instructions from its local 
bus . Both bu s controller I/ O write commands, advanc- 
ed (AIOWC) and normal (IOWC), are used. The ad- 
vanced command is used to write to all local devices ex- 
cept the two 8282 control ports. The normal command 
is used when writing to these control ports to prevent 
glitching of the 8282' s output signals. This command 
prevents glitches since its timing guarantees that the 
write data is valid before the command's leading edge. 

The channel attention (CA) signal is . generated by 
decoding Multibus I/O writes to ports 0 and 1 allowing 
the host processor to start channel 1 and 2, respectively. 
A CA signal for channel 2 is also generated when the 
8089 accesses local bus port 4070H allowing channel 1 
to start channel 2. 

The local bus interface is implemented with two 8282 
octal latches and two 8286 octal transceivers. Two 8205 
one-of-eight decoders provide the local bus address 
decoding for memory and I/O devices. Two 2716-1 
EPROM components provide 4K bytes of program 



storage addressable from 2000H to 2FFFH. If more 
program storage is required, the 27 16- Is can be replaced 
with 2732As or 2764s to provide 8K or 16K bytes, 
respectively, of program memory. 4K bytes of 
read/write memory for storing program variables and 
buffering disk sector data are provided with four 2142-3 
static RAM components addressable from 0 to 7FFH. 

Multibus™ Interface 

The Multibus interface (Fig. 21) is implemented with 
three 8283 octal latches, three 8287 octal transceivers, 
8289 bus arbiter, and byte swap circuitry. The 8089 has 
access to the full 1 megabyte Multibus memory address 
space since all 20 address signals are latched with the 
three a ddress l atch es. Mem ory read and write com- 
mands (MRDC and AMWC) from the 8288 bus control- 
ler are used to access shared system memory. The 8289 
bus arbiter provides the system bus access functions for 
the 8089. The iSBC 604 cardcage is configured for serial 
priority resolution with the iSBC 86/12A having pri- 
ority over the disk controller board. The priorities can 
be changed by simply swapping the cardcage slot loca- 
tions of the two boards. 

The 8 089 's L OCK output is conn ected to the bus ar- 
biter's LOCK input. While LOCK is active, the bus ar- 
biter will not relinquish the shared system bus to 
another proc essor re gardless of its priority. A channel 
activates the LOCK output when a test and set while 
locked instruction, TSL, is exec uted ( semaphore 
access). A channel may also activate LOCK for the en- 
tire duration of a DMA transfer by setting the LOCK bit 
in its channel control register (CC). This ensures that 
once the system bus is acquired, the DMA transfer is 
completed as quickly as possible. 

Three data transceivers and associated byte swap cir- 
cuitry provide 8- and 16-bit Multibus compatibility. 
Since Multibus convention states that all 8-bit transfers 
must o ccur on the lower half of the 16-bit data bus 
(DAT0 to DAT7), all 8089 designs which access 
Multibus must provide byte swap circuitry . Even though 
the system bus is defined as 16 bits wide during the ini- 
tialization of the 8089, the 8089 may perform byte 
references to odd-addressed memory locations. This 
results in the high byte of a 16-bit word being trans- 
ferred over the lower half of the data bus. 

Timing and Control 

The timing and control section (Fig. 22) receives signals 
from the 8089 and disk drive to control all disk opera- 
tions. The interface with the 8089 is via two 8-bit control 
ports and one 8-bit status port. Control ports 1 and 2 
are implemented with 8282 latches and have addresses 
4010H and 4021H, respectively. The two control ports 
are the primary interface from the software to the hard- 



3-81 



AFN02057A 



r 



M 

U 
L 
T 

I A 

B 

U 

S™ 



I 

/-LA 

VrV 

I 
I 

1 



STATUS CLK 



1 



CLK 

8089 




STATUS 


DRQ 




EXT 



LOCAL 

CONTROL 

BUS 




> 

IO 
IO 



> 



Figure 20. Disk Controller Block Diagram (Sheet 1 off 2) 



CONTROL/STATUS 



LOCAL 
CONTROL 
BUS 



4jV 



DISK DRIVE 



T 



TIMING 
LOGIC 



CONTROL 
LOGIC 



SYNCH DETECT 



CONTROL/STATUS 
REGISTERS 



i ~TF 



8254 
COUNTER 



LOCAL 
DATA 
BUS 



TIMING AND CONTROL 



16-BIT 
SHIFT 
REGISTER 



INPUT 
BUFFER 
(16-BIT) 



4 



TRANSCEIVER 
(16-BIT) 



__L__ 



WRITE CLOCK 



CRC 
LOGIC 



OUTPUT 
BUFFER 
(16-BIT) 



t 



2k 



16-BIT 
COMPARATOR 



WRITE DATA 
GATING 



DATA TRANSF ER j 



Figure 20. Disk Controller Block Diagram (Sheet 2 of 2) 



AM22 



A0R13 



INT1 
iRTS 

XACK 



Kr r v «« 



oJT 3 

bo*,. 



r 



» Wv- 

I S10 

1— «!U 



A" 



APRl 
KOTE 
a"Er£ 



ADR7 
APH8 
ADR5 
A5fi4 



12*—*^ 



—3^ 

7412S 



PATF 
DATE 
DATD 

daTc 

DATB 
DATA 
5ATg 
OAT* 



5AT7 
DAT6 
5TT6 
DAt7 
TSKTS 
57ff2 



5 ONP-OE *• 



BCLK 

bpW5 



T9 It4 ?20 fir^~° 



v cc 


IOB CEN 


DEN 


MCE/PDEN 


ALE 


mfk 


AEN 


8288 ioS5 


So 


58 AIOWC 


Si 


Towc 


S2 


AMWC 


DT/ft c 


K QND"S0S 



I I 



AFN02057A 



Figure 21. I/O Processor and Multibus Interface 

3-84 



AP-122 



6B atm 
RESET 
READY 



?40 [jTlK ^S 



CLK 
READY 



EXT2 



A1B/S6 

A18/S5 r Vs1t 
A17/S4 oRQt 
A16/S3 DR02 
SINTR-1 EXT1 
SINTR-2 
A15/D15 
A14/D14 
A13/D13 
A12/D12 
A11/D11 
A10/D10 
A9/D8 
A8/DS 

CA 7 
A7/D7 
A6/06 
AS/D5 
A4/D4 
A3/D3 
A2/02 
A1/D1 
AO/DO 



26 §5 

27 Sj 

K3L 




+ 5 

T» F 



As B S 
A 6 B, 
*' OE GNO B ' 

JT 



18 


09 


17 


D10 


16 


D11 ' 


IS 


012 


14 013 


13 


,.P1< 


12 


015' 



Ao v ce 

A, 
8 1ft 



GNO °E 

T 



A 3 


2 \ % t s 

Oj 


A 4 


°< 


A$ 
A. 


0$ 

o e 


Ax 

A 8 


o? 

CE 


A, 


GNO 


X 2 



+ 5 

-4-J" 

Aj V ce Ej -il 



~F 



A 2 v ec 



0, 
0 S 

OND °* 



~F 



A1A2 



P"Q1 

_2£2S 
—151! 

EXT2 



Figure 21. I/O Processor and Multibus Interface 

3-85 



AP-122 




WRITE-CLOCK 



Figure 22. Timing and Control 

3-86 



AP-122 



3|S~4_BB3 




Figure 22. Timing and Control 

3-87 



AM22 



ware and allow the 8089' s task program to control all 
disk drive activity. The status port is implemented with 
an 8286 transceiver, has 4030H as an address and allows, 
the task program to monitor drive activity. The 8288 
bus controller's normal I/O write command is used to 
write to the control ports. This prevents the outputs 
from glitching, which can occur if the advanced I/O 
write command is used. 

Output signals from control port 1 are used to control 
the special hardware. The FORMAT signal is active 
when formatting a track. The READ signal is active 
when reading an ID or data field. The WRITE signal is 
active w hen wri ting an ID or data field. The 
CHAN1/CHAN2 signal enables generation of the pro- 
per DMA request (DRQ) signal. The ENB___XCVR 
signal enables transceivers when reading or writing sec- 
tor data or disables them when comparing an ID field. 
The SEL__INDEX signal selects the drive's INDEX or 
SECTOR pulse for terminating dummy DMA transfers. 

Output signals from control port 2 are transmitted 
to the disk drive. The head select (HEAD1, HEAD2, 
HE AIM, and HEAD8), drive select (DRIVE1), seek 
track (DIRECTION and STEP), and 

FAULT CLEAR signals are generated by control port 

2. 

The status port receives signals from the special hard- 
ware and the disk drive. From the special hardware 
are COMPARE_STATUS and CRC__ERROR which 
indicate the status* of the ID field compare and data 

read, respectively. The SEEK COMPLETE, 

DISK READY, TRACK00, and WRITE FAULT 

signals are from the SA4008. 

The interface with the disk drive involves both digi- 
tal and analog signals. All control signals are digital 

while the READ__DATA, WRITE DATA, 

PLO__CLOCK, and WRITE_CLOCK are differential 
signals. Control signals from the drive are resistor ter- 
minated and conditioned with 7414 schmitt-trigger in- 
verters. The control signals to the drive are driven with 
7406 open-collector inverting drivers. The 

READ DATA and PLO__CLOCK inputs are received 

with a 75115 dual differential receiver while the 

WRITE DATA and WRITE__CLOCK outputs are 

driven with a 75114 dual differential driver. 

A 16-bit ring counter is used to provide bit resolution 
timing. Only one of the sixteen outputs is active at any 
time. As 16-bit words are being serially received from or 
transmitted to the drive, the active ring counter output 
corresponds to a bit received or transmitted. When data 
is received from the drive, output 0 (BRO) corresponds 
to bit 0 of the received word, BR7 to bit 7, and BR15 to 
bit 15. When data is transmitted to the drive, BR8 cor- 
responds to bit 0 of the transmitted word, BR15 to bit 7, 



and BR7 to bit 15. The different relationships between 
received and transmitted words are a result of simplified 
ready circuitry (to be discussed later). 

The ring counter is implemented with a 74193 binary 
up/down counter and a 74154 four-to-sixteen decoder. 
The drive's PLO clock is used as the count input signal. 
The ring counter is reset whenever a SECTOR pulse or a 
synch character is detected allowing BRO to be activated 
on the next count. A ring counter provides a great deal 
of design flexibility. Disk control actions can be fine 
tuned with the availability of 16 outputs. Some of these 
key actions are reading from and writing to the serial/ 
parallel conversion circuitry, generating ready and 
DMA request signals, and transmitting and checking 
CRC words. 

An 8254 programmable interval timer provides timing 
delays. The 8254 must be used, rather than an 8253, due 
to the short output pulse widths (approximately 140 
n,sec) of the ring counter. The 8254 has three inde- 
pendent 16-bit counters which are initialized by the soft- 
ware to operate in the hardware triggered strobe mode 
(mode 5). Each counter accepts CLK and GATE inputs 
and provides a single OUJ output. Each counter's 
count register is initialized with a count value and when 
the GATE input is activated, the count register is decre- 
mented with each CLK pulse received. When the count 
register is decremented to zero, a pulse is generated on 
the OUT output. 

The three 8254 output signals are designated CNTRO, 
CNTR1, and CNTR2 and are associated with their 
respective counter. Details of the time delays are dis- 
cussed later. In general, CNTRO signals the start of an 
ID field during the format track operation or the start 
of a data field during the write data record operation. 
CNTR1 signals the end of the DMA transfer when the 
format track operation writes the ID field, when the 
write data record operation writes the data field, or 
when the read data record operation reads the data 
field. During both the read or write data record opera- 
tions, CNTR2 signals the end of the DMA transfer used 
to compare the ID field (sector search). 

When the 8254's counter 0 times out, the 

CNTRO DETECT flip-flop is set. The 

CNTR0___DETECT signal enables the 8089's DMA 
transfer (write ID field or data field) and is reset by 
channel l's task t program at the completion of the 
transfer. 

A synch character (OFH for ID field and ODH for data 
field) must be detected to begin comparing an ID field 
or reading a data field. Only a single AND gate is re- 
quired to detect the synch character since the 
DRIVE_JIEAD__GATE signal is activated when the 
read/ write heads are over a gap written with zeros. 



3-88 



AFN02057A 



AP-122 



Upon detection, the SYNCH DETECT flip-flop is set. 

The SYNCH DETECT signal enables the 8089's DMA 

transfer (write desired ID information or read data 
field) and is reset by channel l's task program at the 
completion of the transfer. 

When an I/O device's transfer rate approaches the 
8089' s maximum transfer rate (1 .25 megabytes/sec), the 
DMA request (DRQ) input cannot be used to synchro- 
nize each byte or Word transferred due to the 1 .2 /tsec 
maximum (at 5 MHz) latency of this input. The disk 
controller uses the 8089's ready signal (and wait states) 
to synchronize the SA4008's 889 kilobyte/sec transfer 
rate with the 8089's transfer rate. The DRQ inputs are 
used to enable DMA transfers while the ready signal is 
used to synchronize individual word transfers. Channel 
l's DMA request signal, DRQ1, is activated when 
CNTR0_JDETECT becomes valid (write ID field or 

data field) or 8 bit times after SYNCH DETECT 

becomes valid (read data field). The 8-bit delay time 
allows the first word to be converted from serial to 
parallel before the 8089's DMA transfer begin. Channel 
2's DMA request signal,' DRQ2, is also activated 8 bit 
times after SYNCH__DETECT becomes valid (write 
desired ID information). DRQ1 and DRQ2 are deacti- 
vated by the task program upon completion of the 
DMA transfer. 

The 8284A clock generator synchronizes ready signals 
from two buses. RDY1 is the ready signal from the 
Multibus and RDY2 is the ready signal from the local 
bus. Both ready inputs are normally inactive. When ac- 
cessing memory or I/O devices, one ready input is acti- 
vated to complete the bus transfer cycle. Depending on 
when the ready input is activated, wait states may or 
may not be inserted. In the disk controller, the 8089 may 
require wait states only when accessing the 16-bit disk 
data port. Wait states are not required when accessing 
other I/O devices or memory devices on the local bus. 
For these devices requiring no wait states, RDY2 is gen- 
erated by the I/O read or write command. 

Accessing the disk data port may require wait states to 
synchronize 8089 transfers with the drive. For this case, 
BRO is used to set a flip-flop. The flip-flop's output 
enables RDY2 generation by the I/O read or write com- 
mand. This ensures that previous data has been trans- 
ferred to or from the serial/parallel converter before 
writing to the output buffer or reading the input buffer, 
respectively. Using only BRO involved changing the rela- 
tionships between ring counter outputs and actual data 
bits transmitted to the drive. A transmitted bit 0 cor- 
responds to BR8 while a received bit 0 corresponds to 
BRO. This is required since a transmitted word must be 
preloaded into the output buffer (at data bit 8 time) 
before being transferred to the serial/parallel converter 
(to prevent underrun errors). On the other hand, a 



received word must be transferred from the serial/ 
parallel converter to the input buffer before being read 
(at data bit 0 time). The input and output buffers are 
described later. 

The external DMA termination signals, EXT1 and 
EXT2, are used to terminate dummy DMA transfers. 
EXT1 is generated whenever the 8254' s counter 2 times 
out (signifying the end of ID field comparison) or when- 
ever the drive's SECTOR or INDEX pulse is detected. 
The SEL__INDEX signal which is controlled by the task 
program selects which pulse generates EXT1 (0 for 
SECTOR and 1 for INDEX). This allows the SECTOR 
or INDEX pulse to terminate the dummy DMA 
transfer. EXT2 is also generated by either the SECTOR 
or INDEX pulse, qualified with SEL INDEX. 



Data Transfer 

The data transfer section (Fig. 23) provides serial/ 
parallel conversion, ID field comparison, and CRC 
generation and checking functions. Serial/parallel con- 
version is performed with a 16-bit shift register imple- 
mented with two 74S299 8-bit shift registers. Data read 
from the drive is converted from serial to parallel while 
data written to the drive is converted from parallel to 
serial. 

A double buffered technique is used here. A 16-bit input 
buffer receives read data from the shift register and a 
16-bit output buffer transmits write data to the shift 
register. Each buffer is implemented with a pair of 8282 
octal latches. Two 8286 octal transceivers provide the 
interface between the local data bus and the input and 
output buffers. These transceivers are enabled when 
writing an ID field or a data field or when reading a data 
field. They are disabled during the ID field comparison. 

The 16-bit comparator is implemented with four 74LS85 
4-bit comparators and one 4-input NAND gate. During 
the ID field comparison, the transceivers are disabled 
allowing the input buffer which contains the ID infor- 
mation read from the disk to drive one. input of the 
16-bit comparator while the ID information written by 
the 8089 drives the other input. The comparator output 
is sampled during each 16-bit comparison. The first mis- 
match is latched (until reset) for channel l's task pro- 
gram to examine later. This permits the length of the ID 
field to be any multiple of words. 

The input buffer, output buffer, and comparator are 
all accessed via port 4000H. The CRC circuitry uses a 
9401 CRC generator/checker strapped to use the CRC- 
CCITT polynomial, X 16 + X 12 + X 5 + 1. Immediately 
after reading the CRC word, the 9401 's error output is 
latched allowing channel l's task program to examine 
the CRC error status later. 



3-89 



AP-122 



READ 




WRITE 



PLO 

READ + WRITE 
WRITE_GATE 
CNTR2 
BR15 
iORD 
ADDRO 
iOWR 



READ + WRITE 
CNTRO-OETECT 




ENB_XCVR 



D0-D15 



AFN02057A 



Figure 23. Data Transfer 

3-90 



AP-122 



]=E>H 



PR Si S2 

EP 

19D 
9401 

9 C 
CP CWE MR 



■ ft 



j|- — W v— -O-t-5 



- CRC_ERROR 



- WRITE_OATA 



- WRITE_CLOCK 




. GNO A = B Vcc. 



--VwV-y -O 



l QND A = B Vcc. 



GND A = B Vcc 



'IN IN i 



C3_ 



4 GN0 A ( =B Vcc B( 
74LS85 8 



_k 



00, 
D0 2 
O0 3 



GND OE 



OUTPUT BUFFER 



In lo 



D0 2 
00 3 



TTTI 



- COW)PARE_STATUS 



Figure 23. Data Transfer 

3-91 



AFN02057A 



AP-122 



VI. HARDWARE OPERATION 

Now that an overview of the four disk control opera- 
tions and the details of the hardware components have 
been presented, the detailed disk control operations will 
be discussed. The interaction of hardware components, 
the relative timing of signals, and the data flow are 
described for the format track, write data record, and 
read data record operations. The seek track operation is 
primarily implemented with software. The channel 1 
and 2 task programs are discussed in the section on soft- 
ware operation. This discussion is focused on how the 
hardware operates. While reading the detailed descrip- 
tion, it may be helpful to refer to the hardware 
schematics (Figs. 21, 22, and 23). 

Format Track 

The format track operation is preceded by a seek track 
operation where the proper cylinder is accessed and the 
proper head is selected. Upon detecting the INDEX 
pulse, the format track operation writes the ID data for 
30 sectors and writes zeros everywhere else including the 
data field areas. Channel 1 controls the entire operation 
without assistance from channel 2. 

The overall timing of the format operation is shown in 
Figure 24. The INDEX and SECTOR signals from the 

drive and the WRITE GATE signal to the drive are 

shown. Also presented are the signals controlled by 
channel l's tas k program— FORMAT, WRITE, 
CHAN1/CHAN2, and ENB__XCVR. In addition, the 
activity of the 8254* s counters is shown. 

Channel 1 begins the format track operation by initial- 
izing the 8254 counters and its DMA registers used to 
transfer the ID data to the drive. The FORMAT signal 
is activated and a dummy DMA transfer is started to 
wait for the INDEX pulse. When the INDEX pulse is 
detected (Fig. 24), the hardware activates the 

WRITE GATE signal and zeros are written on the 

track. A SECTOR pulse which coincides with the IN- 
DEX pulse starts counter 0. Counter 0 provides the time 
delay from the SECTOR pulse to the start of the ID 
field and indicates when to start writing the ID data. 
This provides the proper-sized gap between the SEC- 
TOR pulse and ID field. 

Detection of the INDEX pulse also resumes c hannel l's 
program execution and the WRITE, CHAN1/CHAN2, 



and ENB__XCVR signals are activated (Figs. 24 and 
25). Next the destination synchronized DMA transfer is 
started, the synch character word is prefetched from 
memory, and channel 1 waits for DMA request. 

When counter 0 times out, the CNTR0_DETECT flip- 
flop is set (Fig. 25). CNTRO DETECT is transmitted 

to the 8089's DMA request input, DRQ1. This starts the 
8089 bus cycle which writes the synch character to the 
output buffer. CNTR0_DETECT is also transmitted 
to counter l's gate input, GATE1 , which allows counter 
1 to start counting BR3 ring counter pulses. Counter 1 
provides the time delay from the start to the end of the 
ID field and indicates when to append a CRC word. 

The WRO signal is activated when the 8089 writes to the 
output buffer or the hardware comparator and is used 
by the ready circuitr y to g enerate RDY2A. RDY2A is 
activated by BRO or WRO, whichever occurs last. This 
ensures that previous data has been transferred from the 
output buffer to the shift register before writing new 
data to the output buffer. When RDY2A is activated, 
the write bus cycle completes and the synch character is 
latche d in the output buffer with the rising edge of 
WRO. The synch character is next loaded into the shift 
register with BR7 and written to the drive. 

The DMA activity repeats until four words haye been 
transferred— synch character, first ID word, second ID 
word, and zero word. As the zero word is being written, 
counter 1 times out after counting four BR3 pulses. The 

TRANSMIT CRC flip-flop latches CNTR1 with BR8 

and remains active for one word time. The active 

TRANSMIT CRC signal allows a CRC word to be 

serially transmitted to the drive from the 9401 CRC 
generator/checker. When TRANSMIT CRC goes in- 
active, zeros are shifted out of the shift register to the 
drive. Zeros are written on the track until the next ID 
field since WRITE_GATE is held active until all 30 ID 
fields have been written. 

After the four word DMA transfer, channel 1 initializes 
DMA registers in preparation for writing the next sec- 
tor's ID data and starts a dummy DMA transfer to wait 
for the next SECTOR pulse. The same procedure is re- 
peated until ID data has been written for all 30 sectors. 
The format track operation concludes with channel 1 
deactivating FORMAT, WRITE, CHAN1/CHAN2, 
and ENB__XCVR. The FORMAT signal deactivates 
WRITE^GATE which stops writing zeros to the drive. 



3-92 



AFN02057A 



A P- 122 



TRACK DATA OH | IPO | OH 

INDEX 



SECTOR 
WRITE_GATE 
FORMAT 
WRITE 



CHAN1/CHAN2 
ENB_XCVR 
CNTRO ACTIVE JjJ" 



CNTR1 ACTIVE 



CNTR2 ACTIVE 



7=L 



| IP 10 | OH {\ OH | ID 29 | 



J L 



1=L 



tfl 



JL 



Figure 24. Format Track Operation 



TRACK DATA OH 
WRITE J 



SYNCH | IP1 | tP2 | CRC | OH 



CHAN1/CHAN2 _J" 



ENB_XCVR _J 

CNTRO DETECT 

DRQ1 
RDY2A 



CNTRO_ 
PETECT 



LOAD OUTPUT BUFFER WRO 

LOAD SHIFT_REGISTER 

. CNTRO_ 



— ris — n* — r\ 

SYNCH / IP 1 ) IP 2 J ZEROS / 



SYNCH ID1 IP 2 ZEROS ZEROS ZEROS 

* l . fl *1 • f\ A A 



..... CNTRO r— 

GATE1 DETECT^ <T 



CUC1PM.J 1 n n n 

CNTR1 _ 

TRANSMIT CRC 



_n tl 



J L 



Figure 25. Write ID Field 



3-93 



AFN02057A 



AM 22 



Write Data Record 

The write data record operation consists of two 
phases— sector search and write data field. Channel l's 
task program supervises this operation with assistance 
from channel 2. The sector search phase begins with the 
first complete sector that passes under the read/write 
heads and ends either when the desired sector is located 
or when all 30 sectors on the track have been compared 
without a match. If no match occurs, channel 1 aborts 
the operation and reports the error to the host pro- 
cessor. Upon locating the desired sector, the write data 
field phase begins. Two types of DMA transfers are per- 
formed during the write data record operation— channel 
2 transfers the desired ID field information to the 16-bit 
comparator and channel 1 transfers the data record to 
the drive. 

The overall timing of the write record operation is 
shown in Figure 26. The drive signals (SECTOR, 
RE AD_G ATE , and WRITE__GATE), signals con- 
trolled b y 8089 task programs (READ, WRITE, 
CHAN1/CHAN2, and ENB_XCVR), and activity of 
the 8254 counters are displayed. 

Channel 1 begins the write data record operation by ini- 
tializing the 8254 counters and its DMA registers used to 
transfer the data record to the drive. Next channel 1 
starts channel 2, initiates a dummy DMA transfer, and 
executes idle cycles. Channel 2 begins execution and ini- 
tializes its DMA registers used to transfer the desired ID 
data to the 16-bit comparator. Next channel 2 starts a 
dummy DMA transfer to wait for a SECTOR pulse. 

When the SECTOR pulse is detected (Fig. 26), channel 2 
activates the READ signal. The destination synchro- 
nized DMA transfer is started, ID word 1 is prefetched 
from memory, and channel 2 waits for DMA request. 
The READ signal activates the drive's READ__GATE 
signal and the synch character detection circuitry reads 
data from the track. When the synch character is 

detected, the SYNCH DETECT flip-flop is set (Fig. 

27). The SYNCH__DETECT signal is used to start 
counters 0 and 2 (Figs. 26 and 27). Counter 2 provides 
the time delay from the start to the end of the ID field 
and indicates when to check for CRC errors. Counter 0 
provides the time delay from the start of the ID field to 
the start of the data field and indicates when to start 
writing the data field. This provides the proper-sized 
gap between the ID and data fields. 

SYNCH DETECT also allows the DMA request 



signal, DRQ2, to be activated with BR7. This starts the 
8089 bus cycle which writes ID word 1 to one input of 
the 16-bit comparator. BR14 is used to generate the 

LOAD INPUT BUFFER signal which latches the 

drive's ID word 1 in the input buffer (from the shift 
register). The input buffer drives the other comparator 

input. Note that the ENB XCVR signal is inactive and 

the transceivers between the local data bus and the 
double-buffered serial/parallel converter are off. 
CNTR0__DETECT is also inactive which deactivates 
the output buffer. 

The ready circuitry operates in an identical way as dur- 
ing the format operation. When RDY2A is activated, 
the write bus cycle completes and the COM- 
PARE —STATUS is latched with the rising edge of 
WRO. The COMPARE_STATUS flip-flop keeps the 
first mismatch latched until reset. 

Counter 2 was set up to count three BR7 pulses. After 
both ID words have been compared, counter 2 times 
out. The CNTR2 signal allows the 9401 CRC generator/ 
checker's error output to be latched in the CRC ER- 
ROR flip-flop with BR7. Channel 2 halts after the DMA 
transfer. The CNTR2 signal is also used to activate 
channel l's external terminate input, EXT1. Channel 1 
resumes execution, examines the COM- 

PARE STATUS and CRC__ERROR flip-flops, and 

deactivates the READ signal. 

Upon detecting a match without CRC error, channel 1 
begins th e write da ta field phase by activating WRITE, 
CHAN1/CHAN2, and ENB^XCVR (Fig. 26). The 
destination synchronized DMA transfer is started, the 
synch character word is prefetched from memory, and 
channel 1 waits for DMA request. When counter 0 times 
out, CNTR0__DETECT is activated and counter 1 is 
started. Counter 1 provides the time delay from the start 
to the end of the data field and indicates when to ap- 
pend a CRC word. CNTR0__J)ETECT is also transmit- 
ted to the 8089's DMA request input, DRQ1, which 
starts the data record transfer to the drive (Fig. 28). The 
data record is written on the track almost identically to 
the way that the ID data is written on the track during 
the format track operation. The only hardware opera- 
tional difference is that more words are written on the 
track for the data record than for the ID field. The 
earlier discussion explains the operation of Figure 28 
and therefore will not be repeated here. The write data 
record operation c oncludes with channel 1 deactivating 
WRITE, CHAN1/CHAN2, and ENB__XCVR. 



3-94 



AFN02057A 



AP-122 



^CK DATA OH | SYNCH j I0 1 | ID 2 | crc I 
SECTOR _J"| 



| SYNCH |wORD l| | w O RD | CRC | 



READ_GATE READ 



WRITE_GATE WRITE 

READ 

WRITE 



CHAN1/CHAN2 
ENB_XCVR 
CNTRO ACTIVE 
CNTR1 ACTIVE 
CNTR2 ACTIVE 



5 



J QOUNT = 3 |_ 



COUNT=N+2 



JL 



Figure 26. Write Data Record Operation 



TRACK DATA OH | SYNC | ID 1 | ID 2 | CRC \ 
READ 



CHAN1/CHAN2 
ENB_XCVR 
SYNCH DETECT 



ID1 ID 2 CRC ZEROS 
LOAD_INPUT_BUFFER <R $| || fl 



DRQ2 
RDY2A 



LATCH COMPARE_STATUS WRO 

GATE2 SYNCH DETECT f 

CLK2 BR7 



J~b. Tbv 

ID1 J ID2 / 

1_T l_f 



CNTR2 

LATCH CRC_ERR0R 



Figure 27. Compare ID Field 

3-95 



AFN02057A 



AP-122 



TRACK DATA 



| SYNCH | WORD 1 | (\ \ WORD N | 



WRITE J" 



CHAN1/CHAN2 J~ 
ENB_XCVR J" 
CNTRO DETECT 



1 
1 

1 



DRQ1 DETECT I 
RDY2A 



LOAD OUTPUT BUFFER WRO 
LOAD SHIFT_REGISTER 



Th, Fh. rbv_,J~k Tby 

SYNCH J WORD 1 J WORD 2 / , WORD N / ZEROS J 



SYNCH WORD 1 WORD 2 WORD N ZEROS ZEROS ZEROS 

_il fl fL^_Jl fl fl fl_ 



CNTR0_ r — — 

GATE1 DETECT \ 

1 2 3 

clki br3 n n n n 

CNTR1 __ 

TRANSMIT_CRC 



N + 1 

JL 



Figure 28/ Write Data Field 



Read Data Record 

The read data record operation (Fig. 29) is similar to the 
write data record operation. Although counter 0 is acti- 
vated, it is not used during this operation. The sector 
search activity by channel 1 and 2 is identical to that of 
the write record operation. Only channel l's activity 
after locating the desired sector is different. Channel 1 
reads the data record instead of writing it. 

After the desired sector is located without a CRC error, 
channel 1 begins t he read d ata field phase by activating 
READ, CHAN1/CHAN2, and ENB__XCVR. The 
source synchronized DMA transfer is started and chan- 
nel 1 waits for DMA request. The READ signal acti- 
vates the drive's READ GATE signal and the synch 

character detection circuitry reads data from the track. 
When the synch character is detected, the 

SYNCH DETECT flip-flop is set (Fig. 30). The 

SYNCH DETECT signal is used to start counter 1. 

Counter 1 provides the time delay from the start to the 
end of the data field and indicates when to check for 
CRC errors. 

BR14 is used to generate the LOAD_JNPUT___ 



BUFFER signal which latches the first data word in the 
input buffer (from the shift register). SYNCH__ 
DETECT also allows the DMA request signal, DRQ1, 
to be activated with BR7. This starts the 8089 bus cycle 
which reads the first data word from the input buffer. 

The RDO signal is activated when the 8089 reads the in- 
put buffer and is used by the ready circuitry to ge nerate 
RDY2A. RDY2A is activated by BRO or RDO, 
whichever occurs last. This ensures that data has been 
loaded into the input buffer before reading it. Recall 
that during the format and w rite record o perati ons, the 
ready circuitry used WRO instead of RDO. When 
RDY2A is activated, the read bus cycle completes and 
the 8089 stores the data word in memory. 

The DMA activity repeats until all data words have been 
read. Counter 1 times out and CNTR1 allows the 9401 
CRC generator/checker' s error output to be latched in 
the CRC„_J}RROR flip-flop with BR7. The DMA 
transfer terminates and channel 1 examines the 
CRC__ERROR flip-flop. The read data record opera- 
tion concludes w ith channel 1 deactivating READ, 
CHAN1/CHAN2, and ENB__XCVR. 



3-96 



AFN02057A 



AP-122 



TRACK DATA oh | synch j id 1 | id 2 | crc | oh J synch |worp i| ({*"*| w< y p | crc I 

SECT0R JT : 1. 



READ_GATE READ 
WRITE_GATE WRITE 

READ 

WRITE 

CHAN1/CHAN2 

ENB_*CVR 

CNTRO ACTIVE 

CNTR1 ACTIVE 

CNTR2 ACTIVE 



J s 1 

— I COUNT = 21 1— 



COUNT = N +1 

sv— 



JL 



Figure 29. Read Data Record Operation 



TRACK DATA OH | SYNCH | WORD 1 | (ft | WORD N 



CRC I OH 



READ J" 

CHAN1/CHAN2 f ~ 



ENB_XCVR P 

SYNCH DETECT 

LOAD_INP0T_BUFFER 

DRQt 

^RDY2A m __ 
RDO 



WORD 1/ t WOR I 




WORD 1/.. WORDN-V WORD N 



GATE1 SYNCH DETECT <fr " 



1 2 N N+1 

clki si 3 n ru n_ 



CNTR1 ^ 



LATCH CRC ERROR 



WORD 1 WORDN-1 WORD N CRC ZEROS 

_JL_4wJl fl_ fl fl_ 



Figure 30. Read Data Field 



3-97 



AFN02057A 



AP-122 



VII. SOFTWARE DESIGN 

The host processor communicates with and starts only 
channel 1 and subsequently channel 1 starts channel 2. 
Although the 8089's architecture and the controller 
hardware permit the host processor to control and start 
both channels, this design restricts the host's interac- 
tions with channel 1 . 

In a previous section, the linked blocks of the memory- 
based communication structure are described. The 
system configuration pointer and the system configura- 
tion block are used only during 8089 initialization after 
reset. The channel control block (CB) is used for 8089 
initialization and to control channel operation. Before 
starting channel operation, the host processor initializes 
the channel control word and the parameter block offset 
and segment base in the proper half of the channel con- 
trol block (Fig. 8). This section describes the parameter 
and task blocks used in the disk controller design. 

Parameter Blocks 

The parameter block for channel 1 is shown in Figure 
31. The TBI offset points to channel l's task program 
which resides in local memory. If the task program 
resides in system memory, such as during initial debugg- 
ing, TBI segment base is also used to generate the 
pointer. Note that the 8089's architecture requires that 
the first parameter in the PB be the task program's ad- 
dress. All other parameters are user-defined allowing 
parameters to be tailored for a specific I/O task. Other 
PB1 parameters that are passed to the 8089 in this appli- 
cation are the data buffer's address, function, cylinder, 



head, sector and pointers to the CB and PB2. The only 
parameter passed back to the host is status. 

Normally the host processor starts channel 2 and is 
responsible for initializing parameters in the CB and 
PB2. In this design channel 1 starts channel 2. The CB 
and PB2 pointers received from the host in PB1 allow 
channel 1 to initialize the proper parameters before 
starting channel 2. 

In this disk controller design, channel 2 is essentially a 
slave of channel 1. Prior to starting channel 2, channel 1 
initializes channel 2's CCW and PB2 offset and segment 
base in the second half of the channel control block. 
Next channel 1 initializes three parameters in channel 
2's parameter block (Fig. 32). The first parameter is the 
address of channel 2's task program. The function code 
and the data buffer's address are the other two param- 
eters. Although parameter block 2's structure allows the 
task program and data buffer to reside in system or 
local memory, this design places them both in local 
memory. Therefore, only TB2 offset and data buffer of- 
fset are initialized by channel 1 and the segment bases 
are not used. Channel 2 provides no status information 
back to channel 1 via parameter block 2. 



HIGH MEMORY 






MEMORY BUFFER SEGMENT BASE 






MEMORY BUFFER OFFSET 






FUNCTION CODE 






TB2 SEGMENT BASE 


1 CHANNEL 2 




TB2 OFFSET 


J™ TASK BLOCK 


LOW MEMORY 





Figure 32. Channel 2 Parameter Block 



Software Organization 

The disk controller software is organized as several 
modules with a three-level hierarchy (Fig. 33). When the 
8089 receives a channel attention from the host pro- 
cessor, module TBLK1 begins execution (level 1). Con- 
trol is next transferred to one of the level 2 modules (IN- 
IT, SEEK, FMAT, WDATA, or RDATA) based on 
which function was specified in the parameter block. 
For read or write data record functions, TBLK2, which 
is the lone level 3 module, is also executed. 

The details of each software module are now described. 
While reading the detailed description, it may be helpful 
to refer to the ASM89 assembly language source code in 
Appendix B. 



HIGH MEMORY 






PB2 SEGMENT BASE 


) CHANNEL 2 

} PARAMETER 

I BLOCK 




PB2 OFFSET 




CB SEGMENT BASE 


\ CHANNEL 

} ► CONTROL 

j BLOCK 




CB OFFSET 




HEAD 


SECTOR 






0 


CYLINDER 






STATUS 






FUNCTION CODE 






MEMORY BUFFER SEGMENT BASE 






MEMORY BUFFER OFFSET 






TB1 SEGMENT BASE 


I ^ CHANNEL 1 




TB1 OFFSET 


| TASK BLOCK 


LOW MEMORY 





Figure 31. Channel 1 Parameter Block 



3-98 



AFN02057A 



AP-122 



TBLK1 
(CONTROL) 



INIT 

(INITIALIZATION) 



SEEK 
(SEEK TRACK) 



FMAT 
(FORMAT TRACK) 



WOATA 
(WRITE DATA 
RECORD) 

1 



RDATA 
(READ DATA 
RECORD) 



CA2 



TBLK2 
(COMPARE/ 
READ ID) 



Figure 33. Disk Controller Software Organization 



Control Program (TBLK1) 

After the host processor initializes parameters in the 
channel control and parameter blocks, a channel atten- 
tion is generated which starts module TBLK1. Registers 
GA and GC are first initialized. GA is used as a pointer 
to the start of local RAM and GC is used as a pointer to 
COntro1 Port 1. The FORMAT, READ, WRITE, 

CHAN1/CHAN2, ENB___XCVR, and SEL INDEX 

control signals are generated by writing to control port 
1. In general, the controller software uses GA as a base 
pointer when accessing variables in local memory and 
GC as a base pointer when accessing I/O ports. 

Next TBLK1 examines the function code in the param- 
eter block to determine which function has been speci- 
fied. A unique bit in the function code is used to specify 
each of the five functions. This allows the 8089's bit test 
and branch instructions to be used. If a valid function is 
specified, control is transferred to the proper level 2 

module. If not, the BAD CODE error bit in the 

parameter block's status word is set, the host is inter- 
rupted, and channel 1 halts. 

Initialization (INIT) 

The initialization module, INIT, is used to place the 
controller in a known state after applying power to the 
system. It is also used to reset the drive's write fault 



signal. Control ports 1 and 2 are first cleared and then 
the drive select line is activated. Any pending write 
faults are reset. The heads are next positioned over 
cylinder 0 and the three 8254 counters are initialized in 
preparation for other disk drive operations. Counter 0 is 
initialized to count 8 pulses, counter 1 to count 4 pulses, 
and counter 2 to count 3 pulses. Finally, the host is in- 
terrupted and the channel halts. 

Seek Track (SEEK) 

The seek track module, SEEK, is used to position the 
heads over a specified cylinder and to select one of the 
eight read/ write heads. This module first checks if the 
controller is initialized. Since INIT selects the drive, an 
^active ready signal from the drive indicates that the con- 
troller has been initialized. If not initialized, the 

NOT READY error bit in the status word is set, the 

host is interrupted, and the channel halts. In order to 
minimize unnecessary accesses to Multibus, a status 
word in local memory is updated as errors are encoun- 
. tered. Prior to halting, a module will copy this local 
status word to the parameter block in Multibus's shared 
memory. 

If the drive is initialized, execution of the SEEK module 
continues. The cylinder and head values are copied from 
the parameter block to local memory. These variables 



3-99 



AFN02057A 



AP-122 



are stored in local memory to minimize Multibus access. 
The cylinder and head values are checked to determine 
whether they exceed the maximum values of the drive. If 

one or both does, the BAD CYLINDER and/or 

BAD HEAD error bits are set and the channel halts. 

With valid input parameters, head movement is next 

determined using a local variable, PRESENT CYL, 

which specifies which cylinder is presently being ac- 
cessed. By subtracting the present cylinder value from 
the new cylinder value, the head movement is deter- 
mined. A zero result means no movement, a positive 
resul,t means inward movement, and a negative result 
means outward movement. A non-zero result also speci- 
fies how many cylinders inward or outward the set of 
heads must be moved. Although the 8089 does not have 
a subtract instruction, the subtract operation is easily 
implemented by complementing the subtrahend before 
adding it to the minuend. If head movement is 
necessary, the drivel direction line is activated (1 for in- 
ward and 0 for outward) and a string of pulses equal to 
the number of cylinders to be moved is transmitted to 
the drive. 

Next the PRESENT__CYL variable is updated and a 20 
msec delay loop is executed. This delay is required by 
the drive to allow the head positions to stabilize. 
Finally, the host is interrupted and channel 1 halts. 

Format Track (FMAT) 

Before information can be stored on a track, the ID 
fields must be written. This is the function of the format 
track module, FMAT. Similar to the SEEK module, 
controller initialization is first checked. Next the count 
registers for the 8254 counters 0 and 1 are initialized to 8 
and 4, respectively. A format table is generated which 
contains fpur words of information that are written on 
the track for each of the 30 sectors. The four words con- 
tain the ID synch character, cylinder number, head and 
sector numbers, and a word of zeros. The zero word is 
used to write zeros on the track between ID fields. This 
area contains the gap between ID and data fields, the 
data field, the gap after the data field, and the gap after 
the subsequent SECTOR pulse. Only one zero word is 
needed since the 16-bit shift register continues to shift 
out zeros until it is reloaded. 

The format table is generated in three steps: an array 
containing the 30 interleaved sector numbers is con- 
structed, the head number is loaded into the upper half 
of the MC register, and then four words for each sector 
are assembled in the table. Loading the head number in- 



to MC's upper half is effectively done by shifting the 
data from MC's lower half to its upper half. Although 
the 8089 has no shift instruction, the shift left operation 
can be implemented by adding a number to itself. Shift- 
ing the head number left 8 bits is easily accomplished 
with a loop containing just a few lines of code. 

After the format table has been constructed, the infor- 
mation is written to the drive using high speed DMA 
transfers. Channel 1 performs the entire format opera- 
tion without assistance from channel 2. Dummy DMA 
transfers are used to synchronize the format operation 
with INDEX or SECTOR pulses received from the 
drive. The byte count (BC) register is initialized with the 
actual byte count plus two since the dummy DMA trans- 
fer decrements BC (refer to the section on Special 
Design Considerations). After the synchronization 
signal is received, four words from the format table are 
written on the track with DMA transfers. The first sec- 
tor's ID field is written after the INDEX pulse is 
detected and the ID fields of the remaining 29 sectors 
are written after SECTOR pulses are detected. 

After each of the 30 ID fields has been written on the 
track, the drive's write fault signal is examined. If a 

fault is detected, the BAD WRITE error bit is set and 

the channel halts. If no faults are detected, the channel 
halts after all 30 ID fields have been written. 

Write Data Record (WDATA) 

The WDATA module begins execution whenever a data 
record is written to the drive. Channel 1 begins by 
transferring the desired sector's ID information from 
the parameter block to a local memory buffer. This 
local buffer will be used by channel 2 during the ID field 
compare. The sector number is checked to determine 
whether it exceeds the maximum value. If so, the 

BAD SECTOR error bit is set and channel 1 halts. If 

no error is detected, the 8254's count registers for 
counters 0 and 1 are initialized to 21 and 258, 
respectively. 

Channel 1 next enters the DMA mode and transfers the 
data record from the system memory buffer to a local 
memory buffer. The data synch character is inserted in- 
to this local buffer before the data record and a zero 
word is inserted after the data record. The zero word 
causes zeros to be written after the data record and CRC 
word. 

Preparation for starting channel 2 is next performed. 
Channel 2's half of the channel control block is loaded 
with the channel control word to start task program exe- 



3-100 



AFN02057A 



AP-122 



cution in local memory and with the offset and segment 
base values of parameter block 2' s address. Channel 2's 
task program address, the function code for compare 
ID field, and the address of the buffer containing the 
desired sector's ID information are then loaded into 
channel 2's parameter block. Next channel l's registers 
for the write data record DMA transfer are initialized, a 
channel attention signal to start channel 2 is generated, 
and channel 1 starts a dummy DMA transfer. Note that 
two must be added to BC since it is decremented during 
the dummy DMA transfer. 

Channel 1 now idles while channel 2 detects a SECTOR 
pulse and transfers the desired sector's ID information 
to the 16-bit comparator. As channel 2 completes its 
DMA transfer and halts, counter 2 times out which ter- 
minates channel l's dummy DMA transfer. Channel 1 
resumes execution and examines the compare status and 
CRC error flip-flops simultaneously. This is accom- 
plished using the 8089*8 jump if masked compare not 
equal (JMCNE) instruction which uses the MC register 
to test both flip-flop outputs and jumps if a mismatch 
and/or CRC error is detected. If a match without CRC 
error is detected, channel 1 enters the DMA mode and 
writes the data record on the disk. 

If a mismatch and/or CRC error is detected, the CRC 
error flip-flop is checked individually. The detection of 
a CRC error causes the BAD_JD_CRC error bit to be 
set and the channel to halt. Detecting no CRC error 
means that only a mismatch occurred. In this case, the 
next sector's ID field is compared by starting channel 2 
again. 

Assuming that no CRC errors are detected, the sector 
search is repeated until a match is found or all 30 ID 
fields have been compared, whichever comes first. This 
technique allows the sector search to begin with the first 
complete sector encountered rather than starting at the 
beginning of the track when the INDEX pulse is 
detected. 

After detecting a match and writing the data record on 
the track, the drive's write fault signal is examined. The 

BAD WRITE error bit is set if a fault is detected. 

Otherwise, channel 1 halts. For the case where all 30 sec- 
tors have been searched and the desired sector is not 

found, the BAD SEARCH error bit is set and channel 

1 halts. 

Read Data Record (RDATA) 

Whenever a data record is to be read from the drive the 
RDATA module is executed. Much of the actions per- 
formed by this module are identical to that of the 



WDATA module. Channel 1 also begins by transferring 
the desired sector's ID information from the parameter 
block to a local memory buffer, checking the sector 
number, and initializing the 8254 count registers. Iden- 
tical action continues by updating channel 2's com- 
munication blocks, initializing channel l's registers for 
the DMA transfer, generating a channel attention signal 
to start channel 2, and starting a dummy DMA transfer. 
Since the read data record DMA transfer is source 
synchronized, the BC register is not modified during the 
dummy DMA transfer and therefore no adjustment is 
needed when initializing BC. 

Channel 2 next performs the ID field compare and 
halts. Channel 1 resumes execution when counter 2 
times out. Identically with WDATA, channel 1 exam- 
ines the compare status and CRC error flip-flop simul- 
taneously. Detecting a match without CRC error causes 
channel 1 to enter the DMA mode and read the data 
record. The CRC error flip-flop is again examined and 
if no error is detected, the data record just read into a 
local memory buffer is transferred to the system 
memory buffer with DMA transfers and channel 1 
halts. If a CRC error was detected during the reading of 

the data record, the BAD DATA CRC error bit is set 

and channel 1 halts. 

Detection of a mismatch and/or CRC error after the ID 
field compare causes the CRC error flip-flop to be 
checked individually. Encountering a CRC error will set 
the BAD__JD_CRC error bit and halt channel 1. 
Otherwise channel 1 will repeat the sector search until a 
match is found, all 30 ID fields are compared, or a CRC 
error is detected. Any one of these conditions will cause 
channel 1 to read the data record and halt or set an error 
bit and halt. 

Compare or Read ID (TBLK2) 

Channel 2's task program, TBLK2, is executed when- 
ever the ID field is compared or read. Note that the code 
to read the ID field is included in TBLK2 but is not used 
in this version of the software. Channel 2 begins by 
reading the function code to determine whether to com- 
pare the ID field or to read it. In either case, the major 
actions are similar. Channel 2's DMA registers are ini- 
tialized, a dummy DMA transfer is started to wait for 
the SECTOR pulse, the data transfer DMA mode is 
entered, and finally channel 2 halts. During an ID field 
compare, the data transfer DMA mode writes informa- 
tion to the 16-bit comparator while during an ID field 
reaU, information is read from the serial/parallel con- 
version circuitry. The BC register must be adjusted dur- 
ing the ID compare but not during the ID read. 



3-101 



AFN02057A 



AP-122 



VIII. POSSIBLE ENHANCEMENTS 

As discussed earlier, the main purpose of this applica- 
tion note is to present basic design information on im- 
plementing a disk controller with the 8089 I/O pro- 
cessor. Although the design described here does not ex- 
hibit many intelligent features, the controller does allow 
software enhancements to provide the desired features. 

The present design requires a separate track seek opera- 
tion before a read or write data record operation. Ad- 
ding the capability to perform the seek operation prior 
to reading or writing the data record is simple. Separate 
bits in the function code word are used to specify each 
function. This allows the host to select multiple func- 
tions. Recall that the function code is included in the 
parameter block and is initialized by the host processor. 

The SEEK software module can be modified to examine 
the read and write function code bits after completing 
the seek operation. If only one function (read or write, 
but not both) is specified, control is transferred to the 
proper module, either RDATA or WD ATA. Otherwise, 
an error bit is set and the channel halts. Note that this 
same technique can be used to perform a seek operation 
prior to the format track operation. 

Another possible enhancement is the ability to retry an 
operation when a CRC error is detected. This feature 
applies whenever the ID field (during sector search) or 
data field (during read data record) is read. The soft- 
ware can be modified to reposition the heads at the fail- 
ing sector (by counting SECTOR pulses) and retry the 
search or read operation. If several more CRC errors 
are detected, the operation is terminated, an error bit is 
set, and the channel halts. The number of retries can be 
preset in the task program or received as a variable from 
the host processor via the parameter block. 

The ability to transfer multiple sectors of data is another 
desirable feature. A new variable called record count 
must be added to the parameter block. Sequential logi- 
cal sectors are transferred from the starting logical sec- 
tor specified in the parameter block. As many sectors as 
specified by the record count are transferred. This could 
also include head switching from one track to another 
(without a seek operation) to access data across track 
boundaries. 

The transferred data is buffered in local memory and 
the interleaved scheme allows two physical sector times 
for the 8089 to transfer the data from system memory to 
local memory (write operation) or from local memory to 
system memory (read operation). Data is transferred to 
or from the multiple sector system memory buffer start- 
ing at the location specified by the parameter block 
variables. Another parameter block variable may be 



created which returns the last sector number transferred 
to the host. This information can be used by the host 
during an error to determine how many sectors were 
successfully transferred. 

The ability to perform linked operations might be 
useful. For example, a track seek and the reading of five 
data records can be followed by another track seek and 
the writing of two data records. To include this feature, 
the parameter block could be modified to pass a set of 
parameters for each operation or multiple parameter 
blocks could be linked together. Variables such as func- 
tion code, data buffer's address, cylinder, head, sector, 
record count, status, and last sector transferred are pro- 
vided for each operation. As many sets of parameters as 
desired can be specified. The controller software would 
sequence through these sets of parameters, perform the 
required operations, and halt when a special function 
code, such as one with no functions selected, is detected. 

It was pointec| out earlier that the controller hardware 
includes provisions for reading the ID field. In addition, 
the software module TBLK2, channel 2's task program, 
can either compare the ID field or read it, depending on 
the function code that channel 1 provides. Therefore, 
the software can be modified to read the ID field infor- 
mation and verify track position. The 30 ID fields can 
also be read to verify a format track operation. In addi- 
tion, sophisticated access methods which require read- 
ing the ID field may be implemented. 

Another enhancement is to verify a data record just 
written to the drive. Here the same circuitry used to 
compare ID fields is used to compare data fields. The 
good data is written to one input of the hardware com- 
parator while data read from the drive is applied to the 
other input. The first mismatch is latched in the com- 
pare status flip-flop for examination later. 

The software can also be enhanced to manage a file 
structure. The host processor would refer to data rec- 
ords by logical file names rather than physical disk loca- 
tions (cylinder, head, and sector). By maintaining a disk 
directory, the software would determine where the 
record is located or will be located and perform the data 
record access. The 8089's general instruction set, 
although oriented towards I/O processing, supports 
data processing of this complexity. 

The 8089's flexible memory-based communication 
structure allows enhancements to be easily imple- 
mented. Modifying the parameter block to accommo- 
date any additional parameters is a simple task. All 
variables in the parameter block except for the task pro- 
gram address are defined by the user based on the I/O 
processing task to be performed. 



3-102 



AFN02057A 



AP-122 



IX. CONCLUSIONS 

This application note has provided a detailed descrip- 
tion of a hard disk controller design based on the Intel 
8089 I/O processor. The features provided by the 8089 
make it well suited for disk control applications. The 
1 .25 megabyte/sec DMA transfer rate allows interfacing 
with high speed Winchester disk drives. The two chan- 
nels provided in a single 40-pin package permit back-to- 
back DMA transfers in rapid succession to minimize 
gaps between the ID and data fields and provide a 
higher formatted drive capacity. The bit manipulation 
instructions simplify the implementation of the disk 
controller software, typical of I/O processing software. 
All of these features allow the design of a versatile, in- 
telligent and high performance disk controller compati- 
ble with high performance microprocessors and disk 
drives available today. 

An 8089-based disk controller maximizes overall system 
throughput. The host processor and 8089 operate con- 
currently due to the 8089's local bus which is used to ac- 
cess the controller circuitry, task programs, and local 
data variables and buffers. Shared system bus accesses 
are kept to a minimum which minimizes system bus con- 
tention. System throughput is also maximized by off- 
loading disk control overhead tasks from the host and 
having the 8089 perform these tasks in parallel with the 
host. This frees host processor time for data processing. 

A versatile disk controller with many intelligent features 
is easily implemented with an 8089. The host initiates a 
single high level command to perform track seek, data 
record transfers, error checking, and any retries. Other 
controller features such as multiple sector transfers, 
linked operations, and data record verification can also 
be provided. The 8089 provides flexible system bus in- 



terfacing. The controller described here has a Multibus 
interface with byte swap circuitry that permits inter- 
facing with 8- or 16-bit system memory. Since the 
system bus width is defined during 8089 initialization, 
no controller hardware or software changes are neces- 
sary. Memory based communications allow both 8- and 
16-bit host processors to use this controller. 

Use of the 8089 promotes modular subsystem develop- 
ment. Memory based communication blocks provide a 
simple software interface with the host processor. Once 
the parameter block structure is defined, host and 8089 
software development proceeds in parallel. Future 
enhancements are also easily incorporated with possible 
additions to the parameter block. The hardware inter- 
face is also straightforward. A system bus interface, 
such as Multibus, allows the use of address signals to 
generate the CA and SEL signals received by the 8089 
and the use of the interrupt lines to route interrupts 
back to the host processor. Such a simple interface per- 
mits the disk controller hardware to be developed con- 
currently with other hardware subsystems. Also, note 
that the entire 8089 subsystem may be changed with 
minimal impact, if any, to the host processor software. 
For example, the subsystem could be upgraded to sup- 
port higher capacity disk drives or a bubble memory 
subsystem could be implemented using a similar soft- 
ware interface. 

Finally, the 8089 allows a compact disk controller to be 
implemented. The design here is constructed on a 6-3/4 
by 12 inch board with 75 IC packages. By combining at- 
tributes of a CPU and an intelligent DMA controller in 
a single 40-pin package, the 8089 I/O processor allows 
versatile, high performance, and compact I/O subsys- 
tems to be implemented. 



3-103 



AFN02057A 



AP-122 



APPENDIX A 



SHUQART SA4000 PERFORMANCE AND FUNCTIONAL SPECIFICATIONS 







Af)f\Q. 


No. of Disk Surfaces 


2 


4 


No. of Heads 


4 


8 


No. of Cylinders 


202 


202 


No. of Tracks 


808 


1616 


Gross Capacity (M bytes) 


14.54 


29.08 


Access Time including seek settle 






of 20 ms (Milliseconds) 






One Track 


20 


20 


Average (67 Track Seek) 


65 


65 


Maximum (201 Track Seek) 


140 


140 


Disk Speed 


2964 RPM 




Recording Mode 


MFM 




Recording Density 


5534 BPI 




Flux Density 


5534 FCI 




Track Capacity 


18000 Bytes 




Track Density 


172 TPI 




Transfer Rate 


7,11 xlO 6 bits/sec. 
889 x 10 3 bytes/sec. 




Sectors 


Programmable 




Start Time « 


1.5 minutes 





3-104 



AFN02057A 



AP-122 



APPENDIX B 



8089 MACRO ASSEMBLER *** 8089-BASED piSK CNTLR *** 



ISIS-II 8089 MACRO ASSEMBLER X202 ASSEMBLY OF MODULE HDC89 
OBJECT MODULE PLACED IN : Fl : HDC89. OBJ 

ASSEMBLER INVOKED BY: : Fl : ASM89 : Fl : HDC89. A89 DATE ( 7-20-81 ) 



line Source 



i 

2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 



*TITLE<**« 8089-BASED DISK CNTLR ***) 

i 

8089-BASED HARD DISK CONTROLLER 



HDC89 



SEGMENT 



26 
27 
28 
29 
30 
31 
32 
33 
34 
35 
36 
37 
38 
39 
40 
41 
42 



* INCLUDE < : Fl: EQU89. A89) 



CHANNEL 1 PARAMETER BLOCK OFFSETS 



14 


PB1 TBI OFF 


EQU 


OOH 


15 


PB1JTB1 SEG 


EQU 


02H 


16 


PB1 BUFR OFF 


EQU 


04H 


17 


PB1J3UFR_SEG 


EQU 


06H 


18 


PB1 FUNCTION 


EQU 


08H 


19 


PBl^STATUS 


EQU 


OAH 


20 


PB1_CYLINDER 


EQU 


OCH 


21 


PB1 HEAD SECTOR 


EQU 


OEH 


22 


PBIJXBJDFF 


EQU 


10H 


23 


PB1 CCB SEO 


EQU 


12H 


24 


PB1 PB2 OFF 


EQU 


14H 


25 


PB1 PB2^SE0 


EQU 


16H 



CHANNEL 2 PARAMETER BLOCK OFFSETS 



PB2JTB2J3FF 
PB2JTB2 SEG 
PB2_FUNCTI0N 
PB2JBUFRJ3FF 
PB2 BUFR SEG 



EQU 
EQU 
EQU 
EQU 
EQU 



OOH 
02H 
04H 
06H 
08H 



CHANNEL 2 FUNCTION CODES 

i 

CMP_ID EQU OOH 

READ ID EQU 01H 



*EJECT 



3-105 



AFN02057A 



AP-122 



43 


i 






44 


i 






45 


i 8089 CHANNEL CONTROL 


REGISTER BIT MASKS 


46 








47 


PORTJTO PORT 


EQU 


OOOOOOOOOOOOOOOOB 


48 


BLOCKJTOJ'ORT 


EQU 


0 1 OOOOOOOOOOOOOOB 


49 


PORTjrOJBLQCK 


EQU 


1 OOOOOOOOOOOOOOOB 


50 
51 


BLOCK_TO_BLOCK 


EQU 


1 1 OOOOOOOOOOOOOOB 


52 


TRANSLATE 


EQU 


00 1 OOOOOOOOOOOOOB 


53 








54 


S0URCEJ3YNCH 


EQU 


OOOO 1 OOOOOOOOOOOB 

WW WW * W WW W WW WWWW W*J 


55 


DEST SYNCH 


EQU 


000 1 000000000000B 

WW * wvvwvwwvvwwvw 


56 








57 


GA.J30URCE 


EQU 


OOOOOOOOOOOOOOOOB 


58 


GB_SOURCE 


EQU 


00000 1 0000000000B 


59 








60 
61 


LOC KED_C ONTR t)L 


EQU 


000000 1 000000000B 


62 


CHA I NED J10DE 


EQU 


0000000 1 00000000B 


63 








64 


SINGLE_XFER 


EQU 


00000000 1 0000000B 


65 








66 


EXTJTERMJ} 


EQU 


0000000000 1 00000B 


67 


EXT_TERM_4 


EQU 


000000000 1 000000B 


68 


EXT_TERM_8 


EQU 


OOOOOOOdOl 100000B 


69 








70 


BC_TERM_0 


EQU 


000000000000 1 000B 


71 


BC_TERM_4 


EQU 


00000000000 1 0000B 


72 


BC_TERM_8 


EQU 


000000000001 1000B 


73 


i 






74 


UNTIL JiC_TERM 0 


EQU 


000000000000000 1 B 


75 


UNT I LJ1C _TERMl4 


EQU 


00000000000000 1 OB 


76 


UNT I L J1C_TERM_8 


EQU 


000000000000001 IB 


77 


i 






78 


WH I LEJ1C JTER M_0 


EQU 


0000000000000 1 0 1 B 


79 


WHILE J1CjrERM.j4 


EQU 


00000000000001 1 OB 


80 
81 


WH I LE JiC„jrERM~8 


EQU 


00000000000001 1 IB 


82 REJECT 


# 






83 








84 


i 






85 


i CONTROLLER 


ADDRESSES 




86 


# 






87 


RAM BASE 


EQU 


0000H 


88 


RQMJ3ASE 


EQU 


2000H 


89 


DAT ALPORT 


EQU 


4000H 


90 


CNTL PORT 1 


EQU 


401 OH 


91 


CNTL_P0RTJ2 


EQU 


402 1H 


92 


STATUSJ=>ORT 


EQU 


4030H 


93 


CHAN2_CA_P0RT 


EQU 


4070H 


94 


i 






95 


LD CNTRO 54 


EQU 


405 1H 


96 


LD CNTR1 54 


EQU 


4053H 


97 


LD CNTR2 54 


EQU 


4055H 


98 


MODE.. 54 


EQU 


4057H 



3-106 



AFN02057A 



AP-122 



99 


RD CNTRO 54 




EQU 


4051H 


100 


RD CNTR1 54 




EQU 


4053H 


101 


RD CNTR2 54 




EQU 


4055H 


102 












103 












104 




OFFSET VALUES FROM CNTL PORT 1 « 


105 












106 


CNTL2 




EQU 


01 1H 


107 


STATUS 




EQU 


020H 


108 


CA2 




EQU 


06QH 


109 












1 10 












111 




8254 CONTROL 


WORD BIT 


MASKS 


1 12 












1 13 


SEL^CNTRO 54 




EQU 


OOOOOOOOB 


114 


SELJSNTRl 54 




EQU 


01000000B 


115 


SEL_CNTR2 54 




EQU 


10000000B 


116 












117 


RD LD LATCH 54 




EQU 


OOOOOOOOB 


118 


RD LD MSB 54 




EQU 


00100000B 


119 


RD LD LSB 54 




EQU 


00010000B 


120 


RD LD WORD 54 




EQU 


001 10000B 


121 


, 










122 


MODEO 54 




EQU 


oooooooob 


123 


M0DE1 54 




EQU 


OOOOOOIOB 


124 


M0DE2J54 








125 


M0DE3_54 




EQU 


OOOOOl 10B 

Uvwww X X w£# 


126 


M0DE4 54 




CvlW 


VwwU X V/V/V/D 


127 


MODE 5 54 




E.VXVS 


wvwv X \J X \JO 


128 


. 










129 


BCD_C0UNT_54 




EQU 


OOOOOOO 1 B 


130 


i 




















132 












133 












134 




CNTL_PORT„ 


J 


BIT MASKS 
















136 


CLEAR 




EQU 


OOOOOOOOB 


137 


FORMAT 




EQU 


0000000 IB 


138 


READ 




EQU 


OOOOOOIOB 


139 


WRITE 




EQU 


00000 100B 


140 


CHAN1 




EQU 


00001000B 


141 


CHAN2 . 




EQU 


OOOOOOOOB 


142 


ENB_XCVR 




EQU 


00010000B 


143 


SEL INDEX 




EQU 


00100000B 


144 












145 












146 




CNTLJ^ORT^ 


2 


BIT MASKS 




147 












148 


HEAD1 




EQU 


0000000 IB 


149 


HEAD2 




EQU 


OOOOOOIOB 


150 


HEAD4 




EQU 


00000 100B 


151 


HEAD8 




EQU 


00001000B 


152 


DRIVE1 




EQU 


00010000B 


153 


INWARD 




EQU 


00100000B 


154 


OUTWARD 




EQU 


OOOOOOOOB 



3-107 



AFN02057A 



AP-122 



155 
156 
157 
158 
159 
160 
161 
162 
163 
164 
165 
166 
167 
168 
169 
170 
171 
172 

173 *EJECT 

174 

175 

176 

177 

178 

179 

180 

181 

182 

183 

184 

185 

186 

187 

188 

189 

190 

191 

192 

193 

194 

195 

196 

197 

198 

199 

200 

201 

202 

203 

204 

205 

206 

207 

208 

209 

210 



STEP 

FAULT CLEAR 



EQU 
EQU 



01000000B 
10000000B 



i 



STATUS_PORT BIT POSITIONS 



COMPARE_STATUS 

CRCJERROR 

SEEK_COMPLETE 

DRIVE_READY 

TRACKOO 

WRITE FAULT 



EQU 
EQU 
EQU 
EQU 
EQU 
EQU 



0 

1 
4 
5 
6 

7 



MASK-COMPARE < MO PATTERNS 



TEST_SEC TOR _F OUND 

i 



EQU 



030 1H 



FUNCTION CODE BIT POSITIONS 



INIT_CQDE 


EQU 


0 


SEEK CODE 


EQU 


1 


FMAT CODE 


EQU 


2 


WRITE^CODE 


EQU 


3 


READ_CODE 


EQU 


4 


i 

LOOPJSODE 


EQU 


7 i 


; ERROR 


CODE BIT POSITIONS 


BAD^CODE 


EQU 


0 


NOT_READY 


EQU 


1 


B AD_C YL I NDER 


EQU 


2 


BAD HEAD 


EQU 


3 


BAD SECTOR 


EQU 


4 


BAD^WRITE 


EQU 


5 


BAD_SEARCH 


EQU 


6 


BAD_ID_CRC 


EQU 


7 


BAD_DATA_CRC 


EQU 


0 


i OTHER 


CONSTANTS 




MAX_CYLINDER 


EQU 


202 


MAX_HEAD 


EQU 


8 


MAX_SECTOR 


EQU 


30 


ID^SYNCH 


EQU 


OFH 


DATA_SYNCH 


EQU 


ODH 


i 

ID_SIZE 


EQU 


4 


WORD_COUNT 


EQU 


256 



3-108 



AFN02057A 



AP-122 



211 
212 
213 
214 
215 

216 REJECT 

217 

218 

219 

220 



BYTE_C0UNT 

J * 

START_SYS_CCW 
STARTJLOCJSCW 



EQU WORD_COUNT + WORD_COUNT 

EQU 083H 
EQU 08 1H 



DATA VARIABLE DEFINITIONS 



221 












222 












223 


i 










224 


ORG RAM.J3ASE 






















226 


CYLINDER: 


DW 


0 ; IN 


LOW 


BYTE 


227 


HEAD: 


DW 


0 * IN 


LOW 


BYTE 


228 


SECTOR: 


DW 


0 > IN 


LOW 


BYTE 


229 












230 


FUMCTION: 


DW 


0 






231 












232 


PRESENT^ YL: 


DW 


0 i IN 


LOW 


BYTE 


233 


i 










234 


FIND_SECTOR: 


DW 


0, 0, 0, 0 






235 


i 










236 


TEMPEST ATUS: 


DW 


0 






237 


i 










238 


TEMP: 


DW 


0 






239 


* 










240 


i 










241 


i 










242 


ORG RAMJ8ASE + 


05F0H 








243 


i 










244 


SECTOR JBUFFER: 


DS 


512 







245 

246 ; 

247 REJECT 
248 

249 
250 
251 
252 
253 
254 
255 
256 
257 
258 

259 TBLK1: 

260 

261 

262 

263 

264 

265 

266 



CHANNEL 



CONTROL PROGRAM 
RAMJBASE + 040H 

GA, RAMJ8ASE * GA = RAM BASE PTR 

CGA3. TEMP ^STATUS* OH ; STATUS * NO ERROR 

GCCNTL PORT 1 -i GC » I/O BASE PTR 

CGA3. FUNCTION, CPP3. PB l^FUNCTION i GET FUNCTION 

i CODE 

CGA3. FUNCTION, INITJSODE, INIT \ JUMP IF INIT 

i 

C GA 3. FUNCTION, SEEK^CODE, SEEK ; JUMP IF SEEK 

V 

3-109 An 



ORG 

MOV I 
MOV I 
MOV I 
MOV 

LJBT 

LJBT 



AP-122 



267 








268 




LJBT 


269 








270 




LJBT 


271 








272 




LJBT 


273 








274 




SETB 


275 




MOV 


276 




SINTR 


277 




HLT 


278 




j 




279 


REJECT 






280 




i 


281 




t 




282 








283 








284 








285 




. 




286 


INIT: 


MOVBI 


287 




MOVBI 


288 




MOVBI 


289 








290 


1 10: 


JNBT 


291 








292 








293 








294 








295 








296 




JNBT 


297 




MOVBI 


298 




MOVBI 


299 








300 








301 








302 








303 


115: 


JBT 


304 


120: 


MOVBI 


305 




MOVBI 


306 


130: 


JNBT 


307 




JNBT 


308 








309 


140: 


MOV I 


310 




MOV I 


31 1 




MOVI 


312 




MOV I 


313 








314 








315 








316 








317 




MOVI 


318 


j 


MOVBI 


319 




MOVBI 


320 




MOVBI 


321 




MOVI 


322 




MOVBI 



CGA3. FUNCTION* FMAT_CODE, FMAT 
CGA 3. FUNCTION, WRITEJSODE, WDATA 
CGA3. FUNCTION, READ CODE, RDATA 



JUMP IF FMAT 
JUMP IF WRITE 
JUMP IF READ 



CGA 3. TEMP_STATUS, BAD CODE i ERROR, INVALID 
C PP 3. PB1_STATUS, CGA 3. TEMP„ STATUS i FUNCTION 

i SET INTERRUPT 



INITIALIZATION 



CGC 3, CLEAR 

CGC 3. CNTL2, CLEAR 

CGC 3. CNTL2, DRIVE1 



ZERO CONTROL PORTS 
SELECT DRIVE 



CGC 3. STATUS, DRIVE READY, 110 > WAIT FOR DRIVE 

i READY 



RESET WRITE FAULT (IF ANY) 



CGC 3. STATUS, WRITE FAULT, 115 
CGC 3. CNTL2, DR I VE 1 +FAULT_ CLEAR 
CGC 3. CNTL2, DRIVE1 



POSITION HEADS OVER TRACKOO 

CGC 3. STATUS, TRACKOO, 140 
CGC 3. CNTL2, DR IVE1+0UTWARD+STEP 
CGC 3. CNTL2, DRIVE1+0UTWARD 
CGC 3. STATUS, SEEK^COMPLETE, 130 
CGC 3. STATUS, TRACKOO, 120 



CGA3. PRESENT J? YL, OH 
CGA3. CYLINDER, OH 
CGA3 . HEAD, OH 
CGA3. SECTOR, OH 



INIT PRESENT. CYL 
ZERO VARIABLES 



INITIALIZE 8254 CNTRO, CNTR1, AND CNTR2 
GA, M0DEJ54 

CGA3, SELJSNTR0.54 + RDJLD W0RD_54 + M0DE5_54 
CGA3, SEL_CNTR1 54 4- RD^, LD_W0RD <-m 54 + MODES _54 
CGA3, SELJ?NTR2 54 + RD_LD_W0RD_54 f MODES J54 
GA, LD_CNTR0_54 

CGA3/07 { ; CNTRO. COUNT • 8 PULSUS 



3^110 



AFN02057A 



A P- 122 



323 MOVBI CGA3,0 

324 MOVI GA, LD_CNTR1_54 

325 MOVBI CGA 3, 03 ; CNTR1 COUNT PULSES 

326 MOVBI C G A 3,0 

327 MOVI GA, LD_CNTR2_54 

328 MOVBI C GAT, 02 * CNTR2 COUNT « 3 PULSES 

329 MOVBI CGA 3,0 

330 i 

331 MOVI GA, RAMJBASE i GA ■ RAM BASE PTR 

332 MOV CPP3. PB1_STATUS, CGA 3. TEMPEST ATUS 

333 SINTR ; SET INTERRUPT 

334 HLT 

335 i 

336 REJECT 

337 i 

338 i 

339 i SEEK TRACK 

340 ; 

341 ; r 

342 i 

343 i CHECK IF DRIVE IS INITIALIZED 

344 i 

345 SEEK: JBT CGC3. STATUS, DRIVEJREADY, S10 > JMP IF DRIVE RDY 

346 SETB EGA 3. TEMPjSTATUS, NOT READY i SET ERROR BIT 

347 LJMP S80 

348 i 

349 i 

350 i INITIALIZE VARIABLES: CYLINDER AND HEAD 

351 i 

352 S10: MOV CGA3. CYLINDER, CPP3. PB1 CYLINDER 

353 MOVB GB, CPP3. PB1 JHEAD SECTOR+1 

354 MOV CGA 3. HEAD, GB 

355 i 

356 i CHECK CYLINDER PARAM 

357 MOVI CGA 3. TEMP, MAX CYLINDER-1 ; SUBTRACT FROM MAX 

358 MOV IX, CGA 3. CYLINDER > VALUE 

359 NOT IX 

360 INC IX 

361 ADD CGA 3. TEMP, IX 

362 JNBT CGA 3. TEMP+1, 7, SI 3 > JUMP IF POSITIVE 

363 SETB C GA 3. TEMPEST ATUS, BAD CYLINDER ; SET ERROR BIT 

364 i 

365 i CHECK HEAD PARAM 

366 S13: MOVI CGA3 . TEMP, MAX HEAD-1 > SUBTRACT FROM MAX 

367 MOV IX, CGA 3. HEAD i VALUE 

368 NOT IX 

369 INC IX 

370 ADD CGA 3. TEMP, IX 

371 JNBT CGA3. TEMP+1, 7, S16 i JUMP IF POSITIVE 

372 SETB C GA 3. TEMPEST ATUS, BAD HEAD * SET ERROR BIT 

373 S16: JNZ C GA 3. TEMPEST ATUS, S80 i JUMP IF ERROR 

374 i 

375 i 

376 i DETERMINE HEAD MOVEMENT: INWARD, OUTWARD, 

377 i OR NONE 

378 i 



3-111 



AFN02057A 



AP-122 



379 


MOV 


380 


MOV 


381 


NOT 


382 


INC 


383 


ADD 


384 


JZ 


385 


JBT 


386 


* 


387 


REJECT 




388 






389 






390 






391 






392 


MOV 


393 


S20: MOVBI 


394 


MOVBI 


395 


DEC 


396 


JNZ 


397 


JMP 


398 






399 






400 






401 






402 


S30: MOV 


403 


NOT 


404 


INC 


405 


S40: MOVBI 


406 


MOVBI 


407 


DEC 


408 


JNZ 


409 






410 


S50: JNBT 


41 1 






412 






413 






414 






415 






416 


MOV 


417 






418 






419 






420 






421 


S60: MOV 


422 


OR I 


423 


MOVB 


424 






425 






426 






427 






428 


MOV I 


429 


S70: DEC 


430 


JNZ 


431 




i 


432 




i 


433 


S80: MOV 


434 


SINTR 



CGA3. TEMP, CGA3. CYLINDER ; SUBTRACT PRESENT CYL 
IX, C0A3. PRESENT_CYL i FROM NEW CYLINDER 

IX 
IX 

CGA3. TEMP, IX 
CGA3. TEMP, S60 
CGA3. TEMP+1, 7, S30 



JUMP IF DELTA ZERO 
JUMP IF DELTA NEGATIVE 



MOVE HEADS INWARD (POSITIVE DELTA) 

BC, CGA3. TEMP > GET CYLINDER COUNT 

CGC3. CNTL2, DRIVE1 + INWARD+STEP ; PULSE 
CGC 3. CNTL2, DR I VE1+ INWARD 

BC i DECREMENT COUNT AND 

BCS20 ; REPEAT IF O 0 

S50 



MOVE HEADS OUTWARD (NEGATIVE DELTA) 



i GET AND COMPLEMENT 
; CYLINDER COUNT 



BC, CGA3. TEMP 
BC 
BC 

CGC3. CNTL2, DRIVE1+0UTWARD+STEP ; PULSE 
CGC3. CNTL2, DRIVE1+0UTWARD 

BC i DECREMENT COUNT AND 

BCS40 i REPEAT IF <> 0 

CGC 3. STATUS, SEEK COMPLETE, S50 ; WAIT FOR SEEK 

; COMPLETE SIG 



UPDATE PRESENT^ CYL VARIABLE 
CGA3 . PRESENT_CYL, CGA3. CYLINDER 

SELECT HEAD: ACTIVATE HEAD SIGNALS TO DRIVE 



IX, CGA3. HEAD 
IX, DRIVE1 
CGC 3. CNTL2, IX 



20 MSEC TIME DELAY 



IX, 3448 
IX 

IX, S70 



CPP3. PB1_STATUS, CGA3. TEMP^ STATUS 

i SET INTERRUPT 



3-112 



AFN02057A 



AP-122 



435 
436 

437 REJECT 

438 

439 

440 

441 

442 

443 

444 

445 

446 FMAT: 

447 

448 

449 

450 

451 

452 

453 F05: 

454 

455 

456 

457 

458 

459 

460 

461 

462 

463 

464 



HLT 



FORMAT TRACK 



485 
486 
487 

488 F15: 

489 

490 



JBT 

SETB 

LJMP 



MOV I 

MOVBI 

MOVBI 

MOV I 

MOVBI 

MOVBI 



CHECK IF DRIVE IS INITIALIZED 

CGC3. STATUS* DRIVEJREADY* F05 
CGA3. TEMP^STATUS* NOTJtEADY 
F50 



INITIALIZE 8254 FOR FORMAT 



JMP IF DRIVE RDY 
SET ERROR BIT 



OA i LD_CNTR0_54 
CGA3* 07 
CGA3, 0 

GA* LD_CNTR1_54 
CGA3* 03 
CGA3* 0 



i CNTRO COUNT 



CNTR1 COUNT ~ 4 



GENERATE BYTE ARRAY* SECTOR (30), WHICH CONTAINS 
THE INTERLEAVED SECTOR NUMBERS STARTING AT 
ADDRESS = SECTOR BUFFER + 100H 



465 


MOV I 


GA, RAM BASE 


* GA * RAM BASE PTR 


466 


MOV I 


GB* SECTOR JBUFFER 


+ 100H 


467 


MOV I 


CGA3. TEMP* OH 


* J - 0 


468 F10: 


MOV 


BC* CGA3. TEMP 


* SECTOR < I ) = J 


469 


MOV 


CGB3. OH* BC 




470 


ADD I 


BC* 10 


* SECT0R(I+1) » J+10 


471 


MOV 


CGB3. 1H* BC 




472 


ADD I 


BC* 10 


* SECTOR (1+2) « J+20 


473 


MOV 


CGB3. 2H* BC 




474 


ADD I 


GB* 3 


* I = 1+3 


475 


INC 


CGA3. TEMP 


* J « J+l 


476 


MOV 


BC* CGA3. TEMP 


* REPEAT IF J O 10 


477 


NOT 


BC 




478 


INC 


BC 




479 


ADD I 


BC* 10 




480 


JNZ 


BC* F10 




481 








482 








483 




LOAD MC REGISTER 


WITH HEAD DATA IN UPPER 


484 




BYTE (BITS 8-15) 





MOVI BC* 8H 

MOV CGA3. TEMP* CGA3. HEAD 

MOV MC* C GAIL TEMP 

ADD CGA3. TEMP* MC 

DEC BC 



SHIFT COUNT = 8 

GET HEAD DATA 

SHIFT LEFT BY ADDING 

TO ITSELF 
DECREMENT SHIFT COUNT 



3-113 



AFN02057A 



AP-122 



491 




JNZ 


BC, F15 i 




& REPEAT IF O 0 


492 




MOV 


MC, CGA3. TEMP 






493 












494 


REJECT 










495 




j 








496 




i 








497 






GENERATE SECTOR FORMAT TABLE STARTING 


498 






AT ADDRESS « SECTOR„ BUFFER 


499 












500 




MOV I 


GBi SECTOR BUFFER + 100H 






501 




MOV I 


CGA3.TEMP,0H ; 


SECTOR COUNT * 0 


502 




MOV I 


IX, SEC TOR J3 UFFER 






503 


F20: 


MOV I 


CGA+IX+3, ID_SYNCH 




SYNCH CHARACTER 


504 




MOV 


CGA+IX+3, CGA3. CYLINDER ; 


CYLINDER 


505 




MOV 


CGA+IX3,MC 




HEAD /SECTOR 


506 




MOVB 


BC, CGB3 






507 




OR 


EGA+IX+3, BC 






508 




MOV I 


CGA+IX+3, OH 




ZEROS 


509 




INC 


GB 




INCREMENT SECTOR NO. 


510 










POINTER 


511 




INC 


EGA 3. TEMP 




INCREMENT SECTOR COUNT 


512 




MOV 


BCCGA3.TEMP 




& REPEAT IF O MAX 


513 




NOT 


BC 






514 




INC 


BC 






515 




ADD I 


BC, MAX SECTOR 






516 




JNZ 


BCF20 






517 












518 












519 






FORMAT FIRST SECTOR AFTER 


INDEX PULSE 


520 












521 


F30: 


MOV I 


GB, SECTORJBUFFER 




SOURCE POINTER 


522 




MOV I 


GA, DAT ALPORT 




DESTINATION POINTER 


523 




MOV I 


BC, ID SIZE + 6 




BYTE COUNT 


524 




MOV I 


CC,BLOCK_TO_PORT 






525 


& 




+ DEST„ SYNCH 






526 


?/ 




+ GB SOURCE 






527 


& 




+ EXTJTERMJ) 






528 


& 




+ BC_TERM_0 




DMA CONTROL 


529 




WID 


16, 16 




16-BIT TO 16-BIT DMA 


530 




XFER 






INIT DUMMY DMA TO 


531 










DETECT INDEX PULSE 


532 




MOVB I 


CGC3, FORMAT+SEL_ I NDEX 




EXT1 - INDEX PULSE 


533 












534 










WAIT FOR INDEX PULSE 


535 












536 




XFER 






START ID DATA TO DRIVE 


537 










DMA 


538 




MOVB I 


CGC3, FORMAT 






539 


& 




+ WRITE 






540 


& 




+ CHAN1 






541 






+ ENB XCVR i 


OUTPUT FORMAT COMMAND 


542 












543 










DMA OCCURS HERE 


544 












545 




MOVB I 


CGC3, FORMAT 




RESET ALL BUT FORMAT 


546 










LINE 



3-114 ' AFN02057A 

/ 



AP-122 



547 






> 








548 


HMEJECT 












549 














550 




MOV I 


OA, RAMJBASE 




GA « RAM BASE PTR 


551 




JNBT 


CGC 3. STATUS, WRITE FAULT, F35 ; JUMP IF NO FAULT 


552 




SETB 


CGA3 . TEMP^STATUS, BAD„ 


WRITE i SET ERROR BIT 


553 




JMP 


F50 






554 














555 












* 


556 








FORMAT REMAINING SECTORS 




557 














558 


F35: 


MOV I 


MC.MA* SECTHR—I 




, SECTOR COUNT = MAX-1 


559 


F40: 


MOV I 


GA, DATA PORT 




i DESTINATION POINTER 


560 




MOV I 


BC, ID SIZE + 6 




i BYTE COUNT 


561 




MOV I 


CC, BLOCK TO PORT 






562 


& 






+ DEST SYNCH 






563 


& 






+ GB SOURCE 






564 


& 






+ EXT TERM 0 






565 


& 






+ bcJFermj) 




• DMA CONTROL 

i JL/i in vui<i i y\ ul 


566 




XFER 






• INIT DUMMY DMA TO 


567 












DETECT SECTOR PULSE 


568 




WID 


16, 16 




16-BIT TO 16-BIT DMA 


569 














570 












WAIT FOR SECTOR PULSE 


571 














572 




XFER 






START ID DATA TO DRIVE 


573 












DMA 


574 




MOVBI 


CGC 3, FORMAT 






575 


& 






+ WRITE- 






576 


& 






+ CHAN1 






577 


& 






+ ENB_XCVR 




OUTPUT FORMAT COMMAND 


578 














579 












DMA OCCURS HERE 


580 














581 




MOVBI 


CGC 3, FORMAT 




RESET ALL BUT FORMAT 


582 












LINE 


583 




MOV I 


GA, RAMJBASE 




GA - RAM BASE PTR 


584 




JNBT 


CGC 3. STATUS, WRITE_FAULT, F45 ; JUMP IF NO FAULT 


585 




SETB 


EGA 3. TEMP STATUS, BAD. 


WRITE i SET ERROR BIT 


586 




JMP 


F50 






587 














588 














589 








DECREMENT SECTOR COUNT AND JUMP IF O 0 


590 














591 


F45: 


DEC 


MC 






592 




JNZ 


MCF40 






593 














594 


F50: 


MOV I 


IX, 26 




150 MSEC DELAY 


595 


F55: 


DEC 


IX 




(FOR WRITE GATE 


596 




JNZ 


IX,F55 ' 




TURN OFF) 


597 




MOVBI 


CGC 3, CLEAR 




CLEAR FORMAT LINE 


598 














599 




MOV 


CPP3 . PB1_STATUS, CGA3. 


TEMP^STATUS 


600 




SINTR 




j 


SET INTERRUPT 


601 




HLT 








602 















3-115 



AFN02057A 



AP-122 



603 


$EJECT 






604 








609 








606 








607 








608 






609 








610 








61 1 








612 


WDAT A : 


JBT 


613 




SETB 


A1 4 




LJMP 


A1 S 








A1 A 








ox / 








A1 R 
O X o 








A1 Q 




MOV 






MOV 


ASM 
oe x 




MOV 


622 




AND I 


623 




MOV 


624 








APS 




MOV I 


626 




MOV 


627 




NOT 


628 




INC 


62? 




ADD 


630 




JNBT 


631 




SETB 


632 




LJMP 


633 








634 








635 








636 








637 


W10: 


MOV I 


AIR 




MOVBI 






MOVBI 


640 




MOV I 


641 




MOVBI 


A4P 




MOVBI 


643 








644 








A4S 








A4A 








647 








648 




LPD 


649 




MOV I 


650 




MOV I 


651 




ADD I 


652 




MOV I 


653 




MOV I 


654 


& 






655 








656 




XFER 


657 




WID 


658 




MOV I 



WRITE SECTOR DATA 



CHECK IF DRIVE IS INITIALIZED 

CGC3. STATUS, DRIVEJREADY, W05 
CGA3. TEMP^STATUS, NOT READY 
W50 



JMP IF DRIVE RDY 
SET ERROR BIT 



INITIALIZE SECTOR VARIABLES 



CGA3. FIND_SECTOR, CPP3. PB1 
GB, CPP3. PB1JHEAD SECTOR ; 
CGA3. FIND_SECT0R+2, GB 
GB, OFFH i 
C GA 3. SECTOR, GB 



CYLINDER i FIND_SECTOR 
FIND_SECTOR + 2 

SECTOR 



CGA3. TEMP, MAX^ SECTOR- 1 
IX, CGA3. SECTOR 
IX 
IX 

CGA3. TEMP, IX 
CGA3. TEMP+1, 7, W10 
CGA3. TEMP_STATUS, BAD SECTOR 
W50 



CHECK SECTOR PARAM 
SUBTRACT FROM MAX 
VALUE 



JUMP IF POSITIVE 
SET ERROR BIT 



INITIALIZE 8254 FOR WRITE DATA 



GA, LD_CNTR0_54 
CGA3, 20 
CGA3 , 0 

GA, LD_CNTR1_54 
CGA3, 1 
CGA3, 1 



CNTRO COUNT « 21 



i CNTR1 COUNT - 258 



TRANSFER DATA FROM SYSTEM BUFFER TO 
LOCAL BUFFER 



GA, CPP3. PB1JBUFR OFF 

GB, SECTOR JBUFFER"* 
CGB3, DATA_SYNCH 
GB, 2 

BC, BYTE_COUNT 

CC, BLOCKjrOJBLCJCK 

+ GA_SOURCE 
+ BCJTFRMJ) 

16, 16 
CGB3, OH 



SOURCE POINTER 
DESTINATION POINTER 
INSERT SYNCH CHAR 

IN LOCAL BUFFER 
BYTE COUNT 



DMA CONTROL 
INIT DMA 

16-BIT TO 16-BIT DMA 
INSERT ZEROS 



3-116 



AFN02057A 



AP-122 



A CIO 






AAA 






661 




* 


66d 




i 


66J 




i 


664 




i 


665 






666 




I nn 

Lru 


66/ 




Mm IB T 


66a 




nuv 


66V 




nuv 


6/U 






6/1 






6/el 




LrD 


6/0 




Mm j t 

nuvi 


6/4 




Mm i t 

nuvi 


/■7 c 
6/D 




Mm j y 


6/6 






6/7 




i 


6/0 




j 


6/Y 




i 


680 




i 


60 1 


W_0: 


MOV I 


682 




i 


683 


W30: 


MOV I 


684 




MOV I 


/OK 
60D 




Mm j t 

nuvi 


606 




MOV I 


6a/ 






/ 00 
oaa 






6fcl*7 






/.OA 

67U 


ft. 




AO 1 
67 1 




11 t r\ 
vilu 


6*7 cC 




Mm j t 

nuvi 


67J 




Ar C.K 


6V4 






073 






AQA 




riuvo 


O / / 






Ago 






AOQ 
077 






7nn 






70 1 






TOD 




IMfKIP 
v/rlV/ INC. 






i 


7AA 

/U4 






705 






706 




i 


707 




i 


708 






709 




M0VBI 


710 




XFER 


711 




M0VBI 


712 






713 






714 







PREPARE CHANNEL 2'S CCB AND PB 



GA, CPP3. PB1 _CCBJ3FF i 
CGA3. 08H* START^LOC _CCW * 
CGA3. 0AH, CPP3. PB1_PB2 OFF 
CGA3, 0CH# CPP3, PB1 PB2 SEG 



INITIALIZE CCB 
GET CCB ADDRESS 
INIT CCW 

i INIT PB2 OFFSET 
i INIT PB2 SEGMENT 



INITIALIZE PB2 
GA» CPP3. PB1_PB2„QFF i GET PB2 ADDRESS 

CGA3. PB2_TB2_0FF, TBLK2 ; INIT TB2 ADDRESS 
CGA3. PB2_FUNCTI0N# CMP ID > INIT COMPARE CMD 
CGA3. PB2JUFRJ3FF, FIND_SECT0R i INIT BUFFER 

ADDR 



SEARCH FOR SECTOR SPECIFIED IN FIND SECTOR 



IX, MAX_SECT0R 

GA, SECTOR JBUFFER 

GB, DATAJP0RT 

BCi BYTE_C0UNT + 6 
CC, BL0CKJT0JP0RT 

+ DEST^ SYNCH 
+ GA_S0URCE 

EXT_TERM_0 
+ BCJTERM.J, 

I61 16 

MC, TEST SECTOR FOUND 



CGC3. CA2, BC 



CGC3. STATUS, W40 



SECT0R_C0UNT « MAX 

SOURCE POINTER 
DESTINATION POINTER 
BYTE COUNT 



DMA CONTROL 

16-BIT TO 16-BIT DMA 

INIT MC 

INIT DUMMY DMA TO 
DETECT END OF ID 
COMPARE 

GENERATE CHANNEL 2 
CA SIGNAL 

WAIT FOR CHANNEL 2 
TO COMPARE ID 

JUMP IF NOT FOUND 



WRITE SECTOR DATA ON DISK 



CGC3,CLEAR 

CGC3, WRITE + CHAN1 
+ ENB XCVR 



i CLEAR READ LINE 

i START DMA WRITE 

i OUTPUT WRITE COMMAND 

• _ _______________ _____ 

; DMA OCCURS HERE 



AFN02057A 



A P- 122 



715 , • 

716 NOP i TIME DELAY 

717 NOP 

718 NOP 

719 NOP 

720 NOP 

721 MOVBI HOC 3 1 CLEAR ; CLEAR WRITE LIJME 

722 ; 

723 MOVI GA, RAMJBASE ; OA « RAM BASE PTR 

724 JNBT CGC 3. STATUS/ WRITE FAULT, W50 i JUMP IF NO FAULT 

725 SETB CGA3. TEMP_STATUS, BAD WRITE ; SET ERROR BIT 

726 JMP W50 

727 ) 

728 i 

729 i NO MATCH ON PRESENT SECTOR 

730 i 

731 W40: MOVI OA, RAMJBASE i OA * RAM BASE PTR 

732 JNBT CGC J. STATUS, CRC ERROR, W45 ; JUMP IF NO ERROR 

733 SETB CGA3. TEMP_STATOS, BAD ID. CRC ; SET ERROR BIT 

734 W45. MOVBI CGC 3 , ENB_XCVR ; RESET COMPARE STATUS 

735 MOVBI CGC 3, CLEAR ; FLIP FLOP 

736 JNZ CGA3. TEMP STATUS, W50 ; JUMP IF ERROR 

737 i 

738 DEC IX i DEC SECTOR^COUNT & 

739 JNZ IX,W30 ; LOOP IF O O 

740 SETB CGA3. TEMP_STATUS, BAD SEARCH j SET ERROR BIT 

741 i 

742 W50: MOV CPP 3 . PB 1 ^STATUS, C0A3. TEMP STATUS 

743 LJBT CGA3 . FUNCTION+1, LOOP_CODE, W20 

744 SINTR ; SET INTERRUPT 

745 HLT 

746 i * 

747 REJECT 
748 

749 i 

750 i READ SECTOR DA f A 

751 } ' ■ 

752 1 i 1 

753 ; 

754 i CHECK IF DRIVE IS INITIALIZED 

755 i 

756 RDATA: JBT CGC3. STATUS, DRIVE^READY, R05 * JMP IF DRIVE RDY 

757 SETB , CGA3. TEMP_STATUS, NOT READY i SET ERROR BIT 

758 LJMP R50 

759 i 

760 i 

761 ; INITIALIZE SECTOR VARIABLES 

762 i 

763 R05: MOV CGA3. FIND_SECTOR, CPP 3. PB1 CYLINDER ; FIND_SECTOR 

764 MOV GB, CPP3.PB1 HEAD SECTOR > FINDJ3ECT0R + 2 

765 MOV CGA3. FIND SEC TOR +2, GB 

766 AND I GB, OFFH > SECTOR 

767 MOV C OA 3. SECTOR, GB 

768 ; CHECK SECTOR PARAM 

769 MOVI CGA3. TEMP, MAX SECTOR-l i SUBTRACT FROM MAX 

770 MOV IX, CGA 1. SECTOR > VALUE 



3-118 



AFN02057A 



A P- 122 



771 
772 
773 
774 
775 
776 
777 
778 
779 
780 

781 R07: 

782 

783 

784 

785 

786 

787 

788 

789 

790 

791 RIO: 
792 
793 
794 

795 REJECT 

796 

797 

798 

799 

800 

801 

802 

803 

804 

805 

806 

807 

808 

809 

810 

811 

812 

813 

814 

815 

816 R20: 
817 
818 
819 
820 
821 

822 & 

823 & 

824 & 

825 & 
826 



R30: 



NOT 

INC 

ADD 

JNBT 

SETB 

LUMP 

> 

i 

MOV I 

MOVBI 

MOVBI 



MOV I 
MOV I 
MOV I 
MOV I 
DEC 
JNZ 



LPD 
MOVBI 
MOV 
MOV 



LPD 
MOV I 
MOV I 
MOV I 



MOV I 

i 

MOV I 
MOV I 
MOV I 
MOV I 



WID 



IX 
IX 

EGA 3. TEMP, IX 

CGA3. TEMP+1, 7* R07 ; JUMP IF POSITIVE 

CGA3. TEMP_STATUS> BAD_SECTOR ; SET ERROR BIT 
R50 



INITIALIZE 8254 FOR READ DATA 



GA, LD_CNTR1J34 
CGA3 » 0 
CGA3 * 1 



ZERO SECTOR BUFFER 

GA, SECTOR J3UFFER 
IXi 0 

BC, W0RDJ30UNT 
CGA+IX+3, 0 
BC 

BC, RIO 



PREPARE CHANNEL 2'S CCB AND PB 



CNTR1 COUNT 



257 



GA> ZPP1. PB1_CCB OFF 
CGA3. 08H, START JjX„„CCW 
CGA3 . OAH, CPP 1 . PB1_PB2„„0FF 
CGA3. OCH, CPP3. PB1 PB2 SEG 



INITIALIZE CCB 
GET CCB ADDRESS 
INIT CCW 

i INIT PB2 OFFSET 
i INIT PB2 SEGMENT 



INITIALIZE PB2 
GA, CPP3. PB1 JPB2 OFF * GET PB2 ADDRESS 

CGA3. PB2 TB2J3FF, TBLK2 i INIT TB2 ADDRESS 
CGA3. PB2JFUNCTI0N* CMP ID > INIT COMPARE CMD 
CGAJ. PB2JBUFR OFF, FIND „SECTOR i INIT BUFFER 

; ADDR 



SEARCH FOR SECTOR SPECIFIED IN FIND SECTOR 



IX, MAX_SECTOR 

GA, SECTOR JBUFFER 

GBi DAT ALPORT 

BC, BYTE_COUNT 

CC, P0RT_JTOJBL0CK 

+ SOURCE^SYNCH 
+ GBJ30URCE 
+ EXT„ TFRM. 0 
+ BC Jt Eft M 0 

16^ 16 



SECTOR_COUNT « MAX 

SOURCE POINTER 
DESTINATION POINTER 
BYTE COUNT 



DMA CONTROL 

16-BIT TO 16-BIT DMA 



3-119 



AP-122 



827 




MOV I 


828 




XFER 


829 








830 








831 




MOVB 


832 








833 








834 








835 








836 








837 




JMCNE 


838 








839 


REJECT 






840 








841 




> 




842 








843 




i 


844 




MOVB I 


845 




NOP 


846 




NOP 


847 




NOP 


848 




XFER 


849 




MOVB I 


850 


& 






851 








852 








853 








854 




MOV I 


855 




JNBT 


856 




MOVB I 


857 




SETB 


858 




JMP 


859 








860 








861 








862 








863 








864 


R35: 


MOVB I 


865 




MOV I 


866 




LPD 


867 




MOV I 


868 




MOV I 


869 


& 






870 


& 






871 




XFER 


872 




WID 


873 




MOV I 


874 




JMP 


875 








876 








877 








878 








879 


R40: 


MOV I 


880 




JNBT 


881 




SETB 


882 


R45: 


MOVB I 



MC, TEST SECTOR FOUND 



CGC3. CA2, BC 



CGC3. STATUS, R40 



INIT MC 

INIT DUMMY DMA TO 
DETECT END OF ID 
COMPARE 

GENERATE CHANNEL 2 
CA SIGNAL 

WAIT FOR CHANNEL 2 
TO COMPARE ID 

JUMP IF NOT FOUND 



READ SECTOR DATA FROM DISK 



CGCJ, CLEAR 



CGC3, READ + CHAN1 
+ ENB XCVR 



CLEAR READ LINE 
TIME DELAY 



START DMA READ 
OUTPUT READ COMMAND 
DMA OCCURS HERE 



GA, RAMJ3ASE ; GA « RAM BASE PTR 

CGC3. STATUS, CRC^. ERROR, R35 > JUMP IF NO ERROR 
CGC3,CLEAR ; CLEAR READ LINE 

tGAH. TEMP.J3TATUS+1 , BAD_JDATA_CRC ; SET ERROR BIT 
R50 



TRANSFER DATA FROM LOCAL BUFFER TO 
SYSTEM BUFFER 



CGCZhCLEAR 

GA, SECTOR J8UFFER 

GB, CPP3. PB1J3UFRJ3FF 
BC, BYTE_COUNT 

CC, BL0CK_T0J3L0CK 

+ GA_SOURCE 
+ BC_TERM_0 

16, 16 

GA, RAMJBASE 
R50 



} CLEAR READ LINE 
SOURCE POINTER 
DESTINATION POINTER 
BYTE COUNT 



DMA CONTROL 
INIT DMA 

16-BIT TO 16-BIT DMA 
GA » RAM BASE PTR 



NO MATCH ON PRESENT SECTOR 

GA, RAMJBASE ; GA » RAM BASE PTR 

CGC 3. STATUS, CRC. ERROR, R45 i JUMP IF NO ERROR 
CGA3. TEMP_STATUSi BAD ID CRC i SET ERROR BIT 
CGC}, ENB XCVR i RESET COMPARE STATUS 



3-120 



AP-122 



883 
884 
885 
886 
887 
888 
889 
890 
891 
892 
893 
894 
895 
896 
897 
898 
899 
900 
901 
902 
903 
904 
905 
906 
907 
908 
909 
910 
911 
912 
913 
914 
915 
916 
917 
918 
919 
920 
921 
922 
923 
924 
925 
926 
927 
928 
929 
930 
931 
932 
933 
934 
935 
936 
937 
938 



R50: 



MOVBI 
JNZ 

DEC 
JNZ 
SETS 

MOV 
LJBT 
SINTR 
HLT 



CGC3, CLEAR 

CGA3. TEMPEST ATUS, R50 
IX 

IXi R30 



FLIP FLOP 
JUMP IF ERROR 

DEC SECTOR^COUNT & 
LOOP IF O 0 



CGA3. TEMPEST ATUS* BAD_ SEARCH > SET ERROR BIT 

CPP3. PB1_STATUS, CGA3. TEMPEST ATUS 
CGA3. FUNCTION+1, LOOP_CODE, R20 

i SET INTERRUPT 



REJECT 

*INCLUDE<: Fl: CHAN2. A89) 



ORG 

TBLK2: MOV 
JNZ 



CP ID: 



MOV 
MOV I 
MOV I 
MOV I 



MOV I 
XFER 



W I D 

XFER 
MOVBI 



CHANNEL 



DETERMINE OPERATION TO BE PERFORMED 

0 - Compare id field 

1 « read id FlfLD 
RAMJ3ASE + 0580H 

i GET OPERATION CODE 



IX, CPP3 . PB2JFUNCTIQN 
IX, RD ID 



COMPARE ID FIELD OPERATION 



GA, CPP3. PB2 JBUFR OFF 

GB, DAT ALPORT 
BC, ID_SIZE + 2 
CC, BLOCK_TO_PORT 

+ DEST„ SYNCH 
+ GA_SOURCE 
+ EXT TERMJ> 
+ BC TERM 0 
+ CHAINEDJ10DE 
GCCNTL port 1 



16, 16 



CGC 3 , READ + CHAN2 



SOURCE POINTER 
DESTINATION POINTER 
BYTE COUNT 



DMA CONTROL 

CONTROL PORT POINTER 

INIT DUMMY DMA TO 

DETECT SECTOR 

PULSE 

16-BIT TO 16-BIT DMA 

WAIT FOR SECTOR PULSE 

START COMPARE ID FIELD 
DMA 

OUTPUT COMMAND 



3-121 



AFN02057A 



.AP122 



939 
940 
941 
942 
943 

944 *EJECT 

945 

946 

947 

948 

949 RDJtD: 

950 

951 

952 

953 

954 & 

955 & 

956 & 

957 & 
958 
959 
960 
961 
962 
963 
964 
965 
966 
967 
968 & 
969 
970 
971 
972 
973 
974 

975 HDC89 

976 

977 

978 

979 



DMA OCCURS HERE 



HLT 



MOV I 
MOV 
MOV I 
MOV I 



MOV I 
XFER 



WID 



XFER 
MOVBI 



HLT 
ENDS 

END 



READ ID FIELD OPERATION 

OAi DAT ALPORT 

OB* CPP3. PB2JBUFR. OFF 

BC* ID_SIZE 

CC* P0RTJ"0J3L0CK 

+ SOURCE.. SYNCH 
+ GAJ3DURCE 
+ EXT 1 ERM_ O 

+ bc Jterm 6 

+ CHAINED^ MODE 
GC, CNTL PORT 1 



16; 16 



CGC3* READ + CHAN2 
+ ENB XCVR 



SOURCE POINTER 
DESTINATION POINTER 
BYTE COUNT 



DMA CONTROL 

CONTROL PORT POINTER 

IN IT DUMMY DMA TO 

DETECT SECTOR 

PULSE 

16-BIT TO 16-BIT DMA 
WAIT FOR SECTOR PULSE 
START READ ID FIELD DMA 
OUTPUT COMMAND 
DMA OCCURS HERE 



3-122 



AFN02057A 



inteT 



APPLICATION AP-123 
NOTE 



March 1982 




©INTEL CORPORATION, 1982 MARCH 1982 

ORDER NUMBER: 210355-001 



3-123 



AP-123 



INTRODUCTION 

The purpose of this application note is to provide the 
reader with the conceptual tools and factual informa- 
tion needed to apply the iAPX 86/11 to graphic CRT 
design. Particular attention will be paid to the require- 
ments of high-resolution, color graphic applications, 
since these tend to require higher performance than 
those which do not use color. 

The iAPX 86/11 is a microprocessor system which con- 
tains an 8086 CPU and an 8089 Input/Output Processor. 
In the graphic CRT application, the 8089 performs 
DMA transfers from the display memory to the CRT 
controller, and also serves as a CPU for functions such 
as keyboard polling and initialization of the CRT con- 
troller chips. The DMA transfers are done in such a 
manner that they do not tie up the system bus. 

The system is organized so that the 8086 and the 8089 
can perform concurrent processing on separate buses. 
Using the inherent ability of the 8089 to execute pro- 
grams in its own I/O space, the 8086 can successfully 
delegate many of the chores that have specifically to do 
with the CRT display and keyboard, thus reducing the 
8086's processing overhead. For these reasons, the ca- 
pabilities of the 8086,as a CPU can be more fully utilized 
to perform calculations dealing with the material to be 
displayed. Thus, more complex types of displays can be 
undertaken, and the terminal will also be more 
interactive. 



This application note is presented in five sections: 

1. Introduction 

2. Overview of Graphic CRT Systems 

3. Overview of the 8089 

4. Graphic CRT System Design 

5. Conclusions 

Section 2 discusses typical CRT designs, shows how 
performance requirements increase when the capabil- 
ity for color graphics is included, and explains some of 
the system bottlenecks that can arise. Section 3 de- 
scribes the capabilities of the 8089, which can be 
brought to bear to resolve these bottlenecks. Section 4 
gives detailed information for a color graphic CRT sys- 
tem using the iAPX 86/11 (8086 and 8089). 

The reader may obtain useful background information 
on the 8086 and 8089 from iAPX 86,88 User's Manual. 
It would also be helpful to read the data sheets on the 
8086, 8089, 2118 Dynamic RAM, 8202 Dynamic Ram 
Controller, 8275 CRT Controller, 8279 
Keyboard/Display Interface, and 2732A EPROM. 

OVERVIEW OF CRT GRAPHIC SYSTEMS 
Typical Design Technique 

A typical microprocessor-based CRT terminal is shown 
in block diagram form in Figure 1 . The terminal consists 



CENTRAL 
PROCESSOR 



3 



CRT 
CONTROLLER 



CHARACTER 
GENERATOR ROM 



CRT MONITOR 

A MONITOR 
ELECTRONICS 



SYSTEM BUS 









SERIAL 
COMMUNICATIONS 
DEVICE (US ART) 




PARALLEL 
INTERFACE 




KEYBOARD 
INTERFACE 




DISPLAY 
MEMORY 
(RAM) 




PROGRAM 
MEMORY 
(PROM) 




k 1 <> ^ 







CRT TERMINAL 
SERIAL INPUT LINE 



CRT TERMINAL J I 

SERIAL OUTPUT LINE 

CRT TERMINAL 
PARALLEL INPUT/OUTPUT 



o 




KEYBOARD 




POWER 
SUPPLY 



Figure 1. Typical CRT Terminal Block Diagram 

3-124 



AFN-02172A 



AP-123 



of a CRT monitor, monitor electronics, a CRT control- 
ler and character generator ROM, display memory, a 
DMA device, a central processor and associated pro- 
gram memory, a keyboard and keyboard interface, and 
serial and/or parallel communication devices. 

The primary function of the non-graphic CRT controller 
is to refresh the display. It does this by controlling the 
periodic transfer of information from display memory 
to the CRT screen, with the help of the DMA device. 
The central processing unit (CPU) coordinates the 
transfer of information to and from the external 
devices. When information from an external device is 
received by the terminal, the CPU performs character 
recognition and handling functions, display memory 
management functions, and cursor control functions. 
The CPU also interrogates the keyboard interface 
device. If a key depression is detected, the ASCII char- 
acter representing that key is sent to the display 
memory and/or an external device. 

The design shown in Figure 1 could be implemented 
using Intel LSI products. The CPU could be an 8085, 
the DMA device an 8237 A DMA controller, the CRT 
controller an 8275, the character generator ROM a 
2708, program memory ROM a 2716, display memory 
2114s (2K x 8), and the keyboard interface an 8279 
keyboard controller. These choices would result in a 



CRT terminal capable of displaying 25 lines of text 
containing 80 characters each. 

As the design is upgraded to add color and graphics 
capability, performance requirements increase accord- 
ingly. The components most likely to require changing 
are the CPU, the DMA device, the CRT controller, and 
the display memory. Thus, it is desirable at this point to 
examine the operation of these components in more 
detail to provide a foundation for graphic system opera- 
tion. Later we shall give a specific example of a more 
complex display, and examine the performance re- 
quirements imposed. Figure 2 is a block diagram show- 
ing only those components involved with the 
non-graphic CRT refresh function, with more detail 
provided regarding the connecting signal lines. 

The refresh function proceeds as follows. The 8275, 
having been programmed to the specific screen format, 
generates a series of DMA request signals to the 8237A. 
This results in the transfer of a row of characters from 
display memory to one of two row buffers within the 
8275. From this row buffer, the characters are sent, via 
lines CC0-CC6, to the character generator ROM. The 
dot timing and interface circuitry is then utilized to 
convert the parallel output data from the character 
generator ROM into serial signals for the video input of 
the CRT. 



DISPLAY 
MEMORY 



MEMR 



IOR 



ar* 

RD 

C8 



•237A 
DMA 

CONTROLLER 



PACK 



8275 
CRT 
CONTROLLER 



CCO-6 



VIDEO CONTROLS 



3 



VIDEO SIGNAL 



HORIZONTAL SYNC 



VERTICAL SYNC 



Figure 2. Components Involved In the CRT Refresh Function 

3-125 



AFN-02172A 



AP-123 



1st 2nd 3rd 4th 5th 6th 7th 

Character Character Character Character Character Character Character 



First Line of a Character Row 

1st 2nd 3rd 4th 5th 6th 7th 

Character Character Character Character Character Character Character 



□□■■■■□□□■□□□□■□□■■■■■□□□□□□□□□■■■■□□□□■■■□□□■□□□■a 

□■□□□□■□□■■□□PBQ DP 

Second Line of a Character Row 

1st 2nd 3rd 4th 5th 6th 7th 

Character Character Character Character Character Character Character 



□□■■■■□□□■□□□□■□□■■■■■□□□□□□□□□■■■■□□□□■■■□□□■□□□■a 

□■□□□□■□□■■□□□■□□■□□□□□□□□□□□□□■□□□■□□■□□□■□□■□□□■a 

Third Line of a Character Row 



1st 2nd 3rd 4th 5th 6th 7th 

Character Character Character Character Character Character Character 



□□■■■■□□□■□□□□I 

□•□□□□■□□■■□□□I 
□■□□□□■□□■□■□□I 
□■□□□□■□□■□□□□I 
□■□□□□■□□■□□■□I 
□■□□□□■□□■□□□■I 



icn» □□■£)■□■□ 
Seventh Line of a Character Row 



Figure 3. Character Row Display 



The character rows are displayed on the CRT one line at 
a time. Line count signals LC0-LC3 are applied to the 
character generator ROM by the 8275, to specify the 
specific line count within the row of characters. This 
display process is shown in Figure 3, using a seven-line 
character for purposes of illustration. The entire pro- 
cess is repeated for each row of characters in the 
display. 

At the beginning of the last display row, the 8275 issues 
an interrupt request via the IRQ output line. This inter- 
rupt output is normally connected to the interrupt input 
of the system CPU. The interrupt causes the CPU to 
execute an interrupt service subroutine. This sub- 
routine typically reinitializes the DMA controller 
parameters for the next display refresh cycle, polls the 
system keyboard controller, and executes other appro- 
priate functions. 



Performance Requirements 

In the example we have discussed thus far, a display 
consisting of 25 rows, each containing 80 text charac- 



ters, with no color or graphic capability, has been as- 
sumed. Such a screen can be represented by 80 x 25 = 
2000 bytes of data. If the screen is refreshed 60 times 
per second, then a total of 120,000 bytes will need to be 
transferred each second from display memory to the 
8275 CRT controller. This figure is well within the capa- 
bility of the 8237A DMA controller, even allowing for 
vertical retrace time and other overhead. In this appli- 
cation then, both the display memory and the system 
bus remain available to the system CPU most of the 
time, and no bottleneck occurs because of the DMA 
transfer process. 



The situation is quite different when a high-resolution, 
color graphics capability is desired. The performance 
requirements are obviously much greater. To derive a 
quantitative requirement it is necessary to choose, even 
if somewhat arbitrarily, a specific display method and 
screen format. The display method chosen for the sys- 
tem described in this application note is called the 
virtual-bit mapping technique. When this technique is 
used, the graphic material to be displayed is handled on 
a character basis. Figure 4 shows the structure of the 
text and graphic characters used. The text character is a 



3-126 



APN-Q2172A 



AP-123 



7x5 character in an 8 x 5 matrix. The graphic character 
is a 4 x 5 matrix. 

The size of a graphic character is the same as the size of 
a text character. In addition, the text characters may be 
in color. The resolution (horizontal) for a graphic char- 
acter is twice as coarse as the dot spacing for a text 
character. One of eight colors may be selected for fore- 
ground and for background within a particular 
character. 

Figure 5 shows how the display character can be speci- 
fied using four bytes. The first byte determines whether 
the character is a text character or a graphic character, 
and specifies the colors for foreground and back- 
ground. If it is a text character, the second byte 
specifies the character with a seven-bit ASCII code, and 



the remaining two bytes are not used. If it is a graphics 
character, the second, third, and fourth bytes contain 
the color specification for each of the twenty distinct 
picture elements (pixels) within the character. Use of 
the foreground color is indicated by a one in the respec- 
tive bit position, while a zero specifies use of the back- 
ground color. 

The screen format chosen has 80 characters per row 
and 48 rows. Thus the resolution (in terms of picture 
elements) is 640 x 480 for text characters and 320 x 240 
for graphic characters. A full screen contains 80 x 48 = 
3840 characters. Thus, a single frame of the display can 
be represented by 3840 x 4 = 15,360 bytes. If the screen 
were updated 60 times per second, the CRT refresh 
function would require a DMA transfer rate of 15,360 x 
60 = 921,600 bytes per second. 

















LINE COUNT (LC0-LC2) 


COL3 


COL2 


COL1 


COLO 














000 


1 
1 


1 
1 






ROW A 






i 






001 


1 


1 

I 






ROWS 






m 


mi 


■ 


010 


t 

1, . 


1 
1 






ROWC 


















011 


! 


1 
1 






ROWD 














m 




100 


i 
i 


1 
1 


I 




ROWE 


(A) TEXT CHARACTER 

REPRESENTING THE LETTER A. 




(B) GRAPHIC CHARACTER 





Figure 4. Character Structure 



0 


M 


FC2 


FC1 


FC0 


BC2 


BC1 


BC0 



BACKGROUND COLOR (1 of 8) 



FOREGROUND COLOR (1 of 8) 



MODE— 0 = ALPHANUMERICS 
1 = GRAPHICS 



COLOR CODE 
000 
001 
010 
011 
100 
101 
110 
111 



COLOR 

BLACK 

RED 

GREEN 

YELLOW 

BLUE 

MAGENTA 

CYAN 

WHITE 



Figure 5. Display Character Specification 

3-127 



AFN-02172A 



AP-123 



0 


06 


D5 


04 


03 


02 


01 


DO 










/ 









V ^ / 

7 BIT ASCII 



0 


RB2 


X 


RBO 


RA3 


RA2 


RA1 


RAO 




V 


— -Ny* 


J V 






J 



ROW B GRAPHICS ROW A GRAPHICS 

1 = FOREGROUND COLOR 
0 - BACKGROUND COLOR 

(b) Bytel 



NOTE: RB1 IS INTENTIONALLY MOVED TO BYTE 3 SUCH THAT REPRESENTATION OF A BLANK 
CHARACTER FOR EITHER TEXT OR GRAPHIC IS THE SAME. 



0 


RD1 


RDO 


RC3 


. RC2 


RC1 


RCO 


RB3 




| ROW B GRAPHICS 

I 

I 

ROW C GRAPHICS 



ROW D GRAPHICS 



(c) Byte 2 



0 


RB1 


RE3 


RE2 


RE1 


REO 


RD3 


RD2 



ROW D GRAPHICS 



ROW B GRAPHICS 



ROW E GRAPHICS 



(d) Byte 3 



Figures. Display Character Specification (Cont.) 

3-128 



AP-123 



System Bottlenecks 

It can be seen from the above calculation that nearly 
one megabyte of data must be transferred per second to 
effect the CRT refresh function alone. Even with the 
fastest available DMA controllers, this represents the 
major part of the bandwidth for such devices. When the 
design shown in Figure 1 is used, the system bus must 
also be used by the CRT terminal processor for such 
functions as keyboard polling and communication with 
external devices. In addition, any changes made to the 
material being displayed would require use of the sys- 
tem bus for the purpose of storing the new material in 
the display memory, and possibly also for access to 
system memory during the calculation process. It is 
easy to see, therefore, that severe bottlenecks can oc- 
cur in terms of system bus utilization. Problems involv- 
ing bus contention could also be difficult to resolve. 
Display underruns could become difficult or impossible 
to avoid in some cases, such as when graphics com- 
putations require excessive use of the system bus. 

The situation can be improved substantially if provision 
is made for concurrent processing. One CPU can be 
doing calculations on the material to be displayed, 
while another CPU can be managing the CRT terminal 
functions and the I/O devices simultaneously. Local 
buses can be used for access to the respective program 
memories, with the system bus used only for transfer of 
new display data and for communication between the 
two processors. 

The iAPX 86/11 offers a convenient and economical 
way of implementing this multiprocessing approach. In 
particular, the 8089 has unique capabilities that simplify 
the design process. 



OVERVIEW OF THE 8089 
Architectural Overview 

The 8089 Input/Output Processor is a complete I/O 
management system on a single chip. It contains two 
independent I/O channels, each of which has the capa- 
bilities of a CPU combined with a programmable DMA 
controller. 

The DMA functions are somewhat more flexible than 
those of most DMA controllers. For example, a con- 
ventional DMA controller transfers data between an 
I/O device and a memory. The 8089 DMA function can 
operate between one memory and another, between a 
memory and an I/O device, or between one I/O device 
and another. Any device (I/O or memory) can physi- 
cally reside on the system bus or on the I/O bus. The bus 



width for the source and destination need not be the 
same. If the source, for example, is a 16-bit device, 
while the destination is an 8-bit device, the 8089 will 
disassemble the 16-bit word automatically as part of the 
DMA transfer process. The transfer can be synchro- 
nized by the source, by the destination, or it can be free 
running. The 8089 can effect data transfers at rates up to 
1.25 megabytes when a 5 MHz clock is used. 

Unlike most DMA controllers, the 8089 uses a two- 
cycle approach to DMA transfer. A fetch cycle reads 
the data from the source into the 8089, and a store cycle 
writes the data from the 8089 to the destination. This 
two-cycle approach enables the 8089 to perform opera- 
tions on the data being transferred. Typical of such 
operations are translating bytes from one code to an- 
other (for example, EBCDIC to ASCII) or comparing 
data bytes to a search value. 

A variety of conditions can be specified for terminating 
DMA transfers, including single cycle, byte count (up 
to 64K), external event, and data-dependent condi- 
tions, such as the outcome of a masked compare 
operation. 

The CPU in each channel can execute programs in the 
system space (from a memory on the system bus) or in 
the I/O space (from a memory on a separate I/O bus). 
Thus, complete channel programs can be run by the 
8089 without tying up the system bus or interfering with 
the operation of the system CPU. Figure 6 is a simpli- 
fied block diagram of the 8089, showing how the 8089 
interfaces with these two buses. 

The programs that the 8089 executes may be preexisting 
programs stored in ROM or EPROM, or they may be 
programs prepared for the 8089 by the system CPU. In 
the latter case, the programs are typically in modular 
form, contained in "task blocks" that the system CPU 
places in a memory location accessible to the 8089. 
During normal operation, the system CPU then directs 
the 8089 to the various task blocks, according to which 
programs are to be executed. The details of how this is 
done are given below under Software Interface. 

The 8089 has an addressing capability of 64K bytes in 
the I/O space, and thus can support multiple per- 
ipherals, as illustrated in Figure 7. In the system space, 
the 8089 supports 1 -megabyte addressing, and is di- 
rectly compatible with the 8086 or 8088, and with Intel's 
Multibus. The 8089 operates from a single +5V power 
source, and is housed in a standard 40-pin, dual in-line' 
package. The instruction set for the 8089 IOP is specifi- 
cally designed and optimized for I/O processing and 
control, In addition to being able to execute DMA 



3-129 



AFN-02172A 



AP-123 




CPU 
"CHANNEL 1" 




- EXT1 

- 0RQ1 

. SINTR1 



- SINTR2 
EXT2 

- DRQ2 



CHANNEL 2 PROGRAM 



PERIPHERALS 



Figure 6. Simplified Block Diagram of the 8089 



transfers under a wide variety of operating conditions, 
the 8089 can perform logic operations, bit manipula- 
tions, and elementary arithmetic operations on the data 
being transferred, A variety of addressing modes may 
be used, including register indirect, index autQ incre- 
ment, immediate offset, immediate literal, and indexed. 

The register set for the 8089 is shown in Figure 8. Each 
channel has an independent set of these registers, not 



accessible to the other channel. Table 1 gives a brief 
summary of how these registers are used during a pro- 
gram execution or during a DMA transfer. Four of the 
registers can contain memory addresses which refer to 
either the system space or the I/O space. These regis- 
ters each have an associated tag bit. Tag = 0 refers to the 
system space and tag = 1 refers to the I/O space. More 
details on how the registers are used are given below as 
part of the Software Interface section. 



3-130 



AFN-02172A 



AP-123 



MULTIBUS 
INTERFACE 



DRQ2, EXT2 



0 



MULTIBUS 
INTERFACE 



A-JL-N 
N ✓ 



LOCAL 
BUS 
INTERFACE 



b.d 



SYSTEM 
MEMORY 



LOCAL 
MEMORY 



8275 
CRT 
CONTROLLER 



0 



8271 
FLOPPY 
DISK 
CONTROLLER 



8279 
KEYBOARD 
CONTROLLER 



Figure 7. I/O System with Multiple Peripherals 



USER PROGRAMMABLE 





G P ADDRESS A (GA) 




G.P ADDRESS B (GB) 




G P ADDRESS C (GC) 




TASK POINTER (TP) 


v 1-BIT POINTER TO EITHER I/O OR SYSTEM MEMORY SPACE 


15 1 0 




INDEX (IX) 




BYTE COUNT (BC) 




MASK | COMPARE <MC) 




CHANNEL CONTROL (CC) 



NON USER PROGRAMMABLE 
(ALWAYS POINTS TO SYSTEM MEMORY) 



1£E 



PARAMETER POINTER (PP) 



CHANNEL CONTROL POINTER (CP) 



Figure 8. 8089 Register Set 
System Configurations 

The hardware relationship between the host CPU and 
the 8089 can take one of two basic forms — local con- 
figuration or remote configuration. In local configura- 
tion (Figure 9) the IOP shares the system bus interface 



logic with the host CPU. They reside on the same bus, 
sharing the same system address buffers, data buffers, 
and bus timing and control logic. The 8089 requests the 
use of the bus by activating the request/grant line to the 
host CPU. When the host relinquishes the bus, the IOP 
uses all the same hardware, and the host CPU is re- 
stricted from accessing the bus until the 8089 returns 
control of the bus to the host CPU. 

The local configuration is a very economical configura- 
tion in terms of hardware cost, but it does not allow 
concurrent processing, and thus it is not able to really 
take advantage of the 8089's capabilities for indepen- 
dent operation. In the local configuration, the 8089 acts 
as a local DMA controller for the CPU, providing en- 
hanced DMA capabilities and 1 -megabyte addressing. 

For applications such as the color graphics terminal, 
where system bus utilization (and other overhead) due 
to I/O processing would clearly be excessive in the local 
configuration, it is far more desirable to use the remote 
configuration, illustrated in Figure 10. The two proces- 
sors both access the system bus, but each may have its 
own local bus in addition. Each of the processors may 
execute programs from memory on its own local bus, or 



3-131 



AFN-02172A 



AP-123 



Table 1. Channel Register Summary 



Register 


Size 


Program 
Access 


System 
or I/O 
Pointer 


Use by Channel Programs 


Use in DMA Transfers 

< 


GA 


20 


Update 


Either 


General, base 


Source/destination pointer 


GB 


20 


Update 


Either 


General, base 


Source/destination pointer 


GC 


20 


Update 


Either 


General, base 


^Translate table pointer 


TP 


2Q 


Update 


Either 


Procedure return, instruction pointer 


Adjusted to reflect cause of termination 


PP 


20 


Reference 


System 


Base 


N/A 


IX 


16 


Update 


N/A 


General, auto-increment 


N/A 


BC 


16 


Update 


N/A 


General 


Byte counter 


MC 


16 


Update 


N/A 


General, masked compare 


Masked compare 


CC 


16 


Update 


- N/A 


Restricted use recommended 


Defines transfer options 



OR 
8088 
CPU 



RQ/GT 



V 



RQ/GT 

8089 
(OP 




ORQ2 


DRQ1 


EXT2 


EXT1 



BUS 
CONTROLLER 



LATCHES/ 
TRANSCEIVERS 



SYSTEM MEMORY 



PERIPHERAL 




' PERIPHERAL 


P1 




P2 



Figure 9. CPU and IOP in Local Configuration 

3-132 



AP-123 



LOCAL 
ROM, RAM 



XCEIVER 
LATCH 



Ink 



A 
V 



8289 
BUS ARB 



XCEIVER 
LATCH 



1 1^=11 

I XCEIVER 
1 LATCH I— 1 



MULTIBUS™ SYSTEM BUS 



MULTIBUS CONTROL 



IE 



MULTIBUS CONTROL 



SYSTEM ROM, 
RAM 



Figure 10. CPU and IOP in Remote Configuration 



on the shared system bus. This creates a much more 
flexible arrangement. Concurrent processing may be 
used, and it is not necessary to synchronize the proces- 
sors. An 8086, for example, may run at 8 or 10 MHz 
while the 8089 operates at 5 MHz. The specific terminal 
design described later in this application note makes 
use of one additional technique to further decouple the 
operation of the two processors. This is a dual-port 
RAM, which is located between the system bus and the 
8089, and serves as display memory and as storage for 
the task blocks created by the 8086 CPU. Details on 
how this dual-port RAM operates are given below in the 
sections describing the terminal design itself. 



Software Interface 

Although the 8089 is an intelligent device which has a 
great deal of ability to function independently when 
managing the course of I/O operations, it typically 
operates under the overall supervision of the host CPU. 



Figure 1 1 illustrates the method of communication be- 
tween the CPU and the IOP. The CPU communicates 
to the IOP by placing messages in memory and activat- 
ing the IOP's channel attention (CA) input. The IOP 
communicates to the CPU by placing messages in sys- 
tem memory and making an interrupt request on one of 
its system interrupt request (SINTR-1 or SINTR-2) 
outputs. 

The messages in memory take the form of linked 
blocks. These blocks are of the following five types: 

1. System Configuration Pointer (SCP) 

2. System Configuration Block (SCB) 

3. Channel Control Block (CCB) 

4. Parameter Block (PB) 

5. Task Block (TB) 

The SCP and SCB blocks are used by the CPU (only 
after reset) to initialize the 8089. The CCB, PB andTB 
blocks are used when the CPU wishes to instruct the 



3-133 



AFN-02172A 



AP-123 



CHANNEL ATTENTION 









MESSAGES 






IN 

MEMORY 









Figure 11. CPU/LOP Communication 



IOP to perform a particular sequence of operations. 
Figure 12 shows these five blocks and how they are 
linked. The SCP, SCB, CB, and PB must be in memory 
which is accessible from both the CPU and 8089 (either 
system memory or for this application note, dual-port 
memory). The TB may be in either system or 8089 local 
memory. 

The system configuration pointer is always found at the 
same location (FFFF6) in the system memory. The first 
time channel attention is activated (after an IOP reset) 
the 8089 reads the system configuration pointer from 
this location. The SYSBUS field contains only one sig- 
nificant bit (Bit 0), designated by the letter W. If W = 0, 
the system bus is an 8-bit bus. W = 1 denotes a 16-bit 
system bus. The IOP first assumes an 8-bit bus and 
reads the SYSBUS field. It stores the information as to 
the physical width of the system bus, then immediately 
uses this information in the process of fetching the next 
four bytes, which contain the address of the system 
configuration block. 

The addresses used to link blocks are standard iAPX 86, 
88 pointer variables, each occupying two word loca- 
tions in system memory. The lower-addressed word 
contains an offset, which is added to the segment base 
value (left- shifted four places) found in the upper- 
addressed word to derive the complete 20-bit physical 
address in system memory. If the block is in an I/O 
memory (as a task block might be), only the offset value 
is used. 

After thus deriving the address of the system configura- 
tion block, the IOP reads this block, starting with the 
system operation command (SOC) field. Bit 1 of the 
SOC field specifies the request/grant mode (used in 



local configuration or in multiple-IOP systems). Bit 0 
specifies the I/O bus width (designated I). When 1=0, 
the I/O bus is an 8-bit bus. 1 = 1 denotes a 16-bit I/O bus. 
The IOP then proceeds to read the double- word pointer 
to the channel control block, converts it to the 20-bit 
physical address, and stores it in an internal register 
(the channel control pointer register). This register is 
loaded only during initialization and is not available to 
channel programs. For this reason the channel control 
block cannot be moved unless the IOP is reset and 
reinitialized. 

The initialization is complete when the channel control 
pointer has been stored. The IOP indicates this by clear- 
ing the busy flag in the channel 1 control block (which 
must be set by the host CPU before the initialization 
sequence began). The host CPU can monitor this flag to 
determine when initialization is complete, and then to 
initialize any other 8089s in the system. 

It is the responsibility of the host CPU to make sure that 
the SCP and SCB have the proper contents before 
issuing the channel attention (CA) that begins the in- 
itialization sequence. After initialization, the host CPU 
must also assure that the channel control block (CCB), 
parameter block (PB), and task block (TB) all have the 
proper contents, before issuing a subsequent CA. 

The CA may be issued in the form of an I/O write 
command to the address of the IOP on the Multibus. 
Figure 13 shows a typical decoding circuit for this write 
command. The IOP actually occupies two consecutive 
address locations on this bus, because the AO line is tied 
to the select (SEL) input of the 8089. A zero on the SEL 
line specifies IOP channel 1 for the impending opera- 
tion, while a one specifies IOP channel 2. 



3-134 



AFN-02172A 



AP-123 

V 



INITIALIZATION 





| SYS BUS 


SCB ADDRESS 


I — c 


SCB RELOCATION 




1 soc 




CB ADDRESS 


I — c 


CB RELOCATION 




Busy | ccw 




PB ADDRESS 


— c 


PB RELOCATION 




BUSY | CCW 


PB ADDRESS 


PB RELOCATION 





SYSTEM 
FFFF8 CONFIGURATION 
POINTER 



SYSTEM 

CONFIGURATION 
BLOCK 



I CHANNEL CONTROL BLOCK 
CHANNEL 1 



TB 


Address 




TB 


RELOCATION 

















T 



PARAMETER BLOCK 



IOP TASK 
PROGRAM 



J 



Figure 12. Linked Block Communication Structure 



a 7 - 

A6- 
A 5 - 
A 4 - 
A 3 - 
A 2 - 



_ js02) C 



Figure 13. Channel Attention Decoding Circuit 



The channel control block has a section for each chan- 
nel. When the CA is received, the IOP goes to the 
section corresponding to the selected channel, and 



reads the channel command word (CCW). It then sets 
or clears the busy flag (FFH = set, 00H = clear). The 
encoding of the channel command word is shown in 
Figure 14. The CCW provides the IOP with a functional 
command (START in I/O space, HALT, etc.) and 
specifies some of the operating conditions, such as 
interrupt handling, bus load limit, or priority relative to 
the other channel. If the CPU is instructing the IOP to 
execute a program, it is at this point that the CPU 
specifies, via the CCW, whether the instructions are to 
be fetched from the system space or from the 8089's I/O 
space. Refer to iAPX 86,88 User's Manual for specific 
details on the setting and clearing of the busy flag and on 
CCW specifications. 

After the CCW has been read, the IOP reads (if appro- 
priate to the command) the address of the parameter 
block associated with the impending operation, and 
stores the translated address (from the two-word seg- 
ment and offset pair to the 20-bit physical address) in 



3-135 



AFN-02172A 



AP-123 



ICF 
—1— 



CF 
I I 



CF COMMAND FIELD 

000 UPDATE PSW 

001 START CHANNEL PROGRAM LOCATED IN I/O SPACE. 

010 (RESERVED) 

011 START CHANNEL PROGRAM LOCATED IN SYSTEM SPACE. 

100 (RESERVED) 

101 RESUME SUSPENDED CHANNEL OPERATION 

110 SUSPEND CHANNEL OPERATION 

111 HALT CHANNEL OPERATION 

ICF INTERRUPT CONTROL FIELD 

00 IGNORE, NO EFFECT ON INTERRUPTS. 

01 REMOVE INTERRUPT REQUEST; INTERRUPT IS ACKNOWLEDGED. 

10 ENABLE INTERRUPTS. 

11 DISABLE INTERRUPTS. 

B BUS LOAD LIMIT 

0 NO BUS LOAD LIMIT 

1 BUS LOAD LIMIT 

P PRIORITY BIT 



Figure 14. Channel Command Word Encoding 



the parameter pointer (PP) register. PP is another regis- 
ter which is not programmable by the channel program. 
The IOP then goes to this location in system memory, 
and fetches the address of the task block itself. The task 
block contains the actual program to be executed, while 
the parameter block contains parameters to be used by 
that program. 

Except for the first two words, which contain the task 
block address, the parameter block format is up to the 
discretion of the user. Similarly, the task block may 
have any format whatsoever, as long as the IOP can 
execute the program. The parameter block is always in 
system memory, but the task block may be either in 
system memory or in I/O (local) memory. 

The host CPU may prepare as many parameter- 
block/task-block sets as it wishes. An individual set is 
then activated for execution by placing its parameter 
block pointer in the desired channel's control block, 
loading the appropriate channel control word, and issu- 
ing a CA to that channel. 

The registers shown in Figure 8 store (in addition to 
pointer variables) various flags and parameters associ- 
ated with the IOP's operation. Some of these registers 
are loaded automatically with information fetched dur- 
ing the initialization sequence or during channel atten- 
tion processing. Others must be set by executing a 
program using instructions from the IOP's instruction 
set that are specifically designed for loading these 
registers. 



Channel programs (task blocks) are written in ASM-89, 
the 8089 assembly language. About 50 basic instruc- 
tions are available. The IOP instruction set contains 
some instructions similar to those found in CPUs, and 
also other instructions specifically tailored to I/O oper- 
ations. Data transfer, simple arithmetic, logical, and 
address manipulation operations are available. Uncon- 
ditional jump and call instructions are provided so that 
channel programs can link to each other. An individual 
register or even a single bit may be set or cleared with a 
single instruction. Other instructions specify condi- 
tional jumps, initiate DMA transfers, perform sema- 
phore operations, and issue interrupt requests, to the 
CPU. 

A channel program typically ends by posting the result 
of an operation to a field supplied in the parameter 
block, then interrupting the CPU (if interrupts are en- 
abled) and halting. When the channel halts, its associ- 
ated BUSY flag is cleared in the channel control block. 
The CPU can poll this flag (as an alternative to being 
interrupted) to determine when the operation has been 
completed. 



Timing Details 

The basic bus timing relationships for the 8089 are 
identical to those of the 8086 or #088, in that all cycles 
consist of four states (assuming no wait states), and use 
the same time-multiplexing technique for the ad- 
dress/data lines. The address (and ALE signal from the 



3-136 



AFN-02172A 



AP-123 



j-LJ-Ly 



- ONE BUS CYCLE - 



ADDRESS/STATUS 



S2-S0 ACTIVE / S2-S0 INACTIVE 



BHE LOW FOR DATA TRANSFER ON HIGH-ORDER 

i£or 



BYTE (pi^Dfl 



ADDRESS/DATA I A « A0 \ I DATA IN 

(AD15-AD0) \ A1S -» U / 1 D1S-D0 

- / \ 



*MDRC or MORC 



*DT/R 



*DEN 

'8288 BUS CONTROLLER OUTPUTS 



Figure 15. Read Bus Cycle 



8288 bus controller) is output during state Tl for either a 
read or write cycle. During state T2 for a read cycle 
(Figure 15) the address/data lines are floated. During 
state T2 for a write cycle (Figure 16) data is output on 
these lines. During state T3, the write data is main- 
tained or the read data is sampled. The bus cycle is 
concluded in state T4. 

Figure 17 shows some details on the wait state timing 
and Figure 18 shows the RESET-CA initialization 
timing. 

During DMA transfers, the transfer cycle may be 
synchronized by either the source or the destination. 
Figure 19 (source-synchronized transfers) and Figure 
20 (destination-synchronized transfers) show the 
relationships among the basic clock cycles, the DRQ 
signals, and the DACK signals. 

The 8089 does not have a DACK output signal. Rather, 
it uses the more general process of issuing a command 
(for example, I/O read or write) to an address on the I/O 
bus. This command is then hardware decoded to obtain 



a chip select signal for the addressed device. This 
method enables the 8089 to relate to a variety of I/O 
devices in a very flexible manner. 

Figures 19 and 20 also show how the 8089 inserts idle 
clocks to accommodate various DRQ latency condi- 
tions. If maximum efficiency (transfer rate) is desired, it 
is usually possible to remove this latency by techniques 
such as generating an early DRQ. Another possibility is 
to use the unsynchronized DMA transfer mode (DRQ is 
not examined) and to use the READY signal for 
synchronizing transfers. The early DRQ technique will 
be discussed later. 

GRAPHIC CRT SYSTEM DESIGN 

Having examined the requirements for graphic CRT 
systems in general, and having also discussed the capa- 
bilities of the 8089, we can now proceed to describe a 
specific graphic CRT design using the 8089. 

In this design, the system CPU is an 8086. Thus, the 
entire system is called an iAPX 86/11. 



3-137 



AFN-02172A 



APr123 



T 



J 



S2-S0 INACTIVE 



ADDRESS/STATUS 



ADDRESS/DATA 
(AD15-AD0) 



*AMWC OR *AIOWC 



*MWTC OR *IOWC 



} ( A19-A16 ~]( S6-S3 



BHE LOW FOR DATA TRANSFER ON HIGH-ORDER 
BYTE (D15-D8) 



DATA OUT D15-D0 



i r 



*DEN 

*8288 BUS CONTROLLER OUTPUTS 



Figure 16. Write Bus Cycle 





. ONE BUS CYCLE . 


CLK _J 


4>ijk>i>ijHj4 




TR1VCL*-HMI<«-*R1VCLt*»jL«~H |^-TCLR1X* 


ROY INPUT 


V/A VA 


OUTPUT 


READY \ NOT READY j READY 


*REF 


ER TO THE 8284A CLOCK GENERATOR/DRIVER 




SHEET FOR TIMING INFORMATION 


Figure 17. Wait-State Timing 




(Synchronous RDY Input) 



RESET MUST BE ACTIVE \ 
FOR FIVE CLOCK 



FOR FIVE CLOCK 
CYCLES I 1CLKMIN 



/RECOGNIZED 



Figure 18. Reset and Channel Attention Timing 



System Partitioning 

The 8086 and 8089 are arranged in the remote configura- 
tion. This assures that concurrent processing can occur. 
As mentioned earlier, an additional step is taken to 
further decrease system bus utilization for I/O-related 
processes. This step is the inclusion in the system of a 
dual-port RAM, located between the system bus and 
the 8089. This dual-port RAM contains the display 
memory and also contains the linked message blocks 
used for communication between the 8086 and the 8089. 

The system configuration then becomes that shown in 
Figure 21. The dual-port RAM becomes the only data 
path between the 8086 and the 8089. Access to this 
memory is time-shared between the 8086 and the 8089, 
with the 8089 taking less than 50% of the total time 
available. Since the 8089 does not access the system 
bus, the host system can enjoy complete freedom to 
allocate its resources between its own local bus and the 
system bus. The CPU and the IOP can operate 
asynchronously, with the 8086 running on an 8 MHz 
clock and the 8089 on a 5 MHz clock. 

The division of responsibility between the 8086 and the 
8089 is then very clearly defined. The 8086 initializes the 
8089 and specifies the task parameters, storing them in 



3-138 



AP-123 



FETCH BUS CYCLE 



«1 '2 '3 



j DRQ HOLD 
FROM READ 



I c 



TRANSFER CYCLE 



0 IDLE 
CLOCKS 1 



DRQ 2 

(FROM I/O DEVICE) 



2 IDLE _ 
CLOCKS 1 



STORE BUS CYCLE 



T3 ^ T4 

LTLTl 



4 IDLE _ 
CLOCKS l"* 




DRQ FOR NEXT TRANSFER CYCLE 



DACK 
(DECODED 
I/O ADDRESS) 



I VALID I/O ADDRESS \ 

/ PRESENT \ 



NOTES 

1) INDICATES THE NUMBER OF IDLE CLOCKS INSERTED AFTER T 4 OF THE STORE CYCLE BEFORE THE NEXT TRANSFER CYCLE 
BEGINS IF DRQ IS RECEIVED BEFORE THE RISING EDGE OF CLK IN THE CURRENT FETCH CYCLE, THE NEXT FETCH BEGINS 
IMMEDIATELY AFTER THE CURRENT STORE 

2) IF THE 8089 IS IDLE WHEN DRQ IS RECOGNIZED, FOUR OR FIVE MORE IDLE CLOCK CYCLES OCCUR BEFORE THE 
ASSOCIATED TRANSFER CYCLE BEGINS (DRQ IS LATCHED ON THE RISING EDGE OF CLK ) 

3) TO PREVENT THE START OF THE NEXT TRANSFER CYCLE, DRQ MUST BE BROUGHT LOW BY THE RISING EDGE OF CLK IN T 4 
OF THE CURRENT FETCH (FOR B/B-+W SOURCE SYNCHRONIZED AND W-»B/B DESTINATION SYNCHRONIZED IT MUST BE 
LOW BY THE RISING EDGE OF CLK IN THE FOURTH CLOCK OF THE CURRENT BUS CYCLE INCLUDING WAIT STATES ) 



Figure 19. Source-Synchronized Transfer Cycle 



^ TRANSFER CYCLE 1 ^ 


TRANSFER CYCLE 2 
IDLE 




^ FETCH BUS CYCLE 1 

Tl | T 2 I T 3 | T 4 

uuinji 

DRQ HOLD 
ADVANCED 


STORE BUS CYCLE 1 
Tl | T 2 I T 3 I T 4 

FROM | ^ * I * k I * 
WRITE I I 1 • 


FETCH BUS CYCLE 2 
Tl | T 2 | T 3 | T 4 

Lnnrui 

2 IDLE - 4 IDLE , 
CLOCKS 3 ^ m CLOCKS ^ ^ 


CLOCKS 

L/Ul 

4 OR S IDLE CI 


STORE BUS CYCLE 2 
T 1 I T 2 | T 3 | T 4 

LfUl/Ul 

.OCKS 4 ^_ 



(FROM I/O DEVICE) 



DACK 

(DECODED I/O AQDRESS) 



' DRQ FOR NEXT TRANSFER 



IDLE 

CLOCKS 3 

VALID I/O 
ADDRESS PRESENT 



NOTES 

1) FIRST DMA FETCH CYCLE OCCURS IMMEDIATELY AFTER THE LAST TASK PROGRAM INSTRUCTION IS EXECUTED 

2) FETCH CYCLE 2 BEGINS IMMEDIATELY AFTER STORE CYCLE 1 

. 3) INDICATES THE NUMBER OF IDLE CLOCKS INSERTED AFTER T 4 OF THE FETCH BEFORE STORE CYCLE 2 BEGINS IF DRQ IS 
RECEIVED BEFORE THE RISING EDGE OF CLK IN THE CURRENT STORE CYCLE, THE NEXT STORE BEGINS IMMEDIATELY 
AFTER THE NEXT FETCH 

4) IF THE 8089 IS IDLE WHEN DRQ IS RECOGNIZED, FOUR OR FIVE MORE IDLE CLOCK CYCLES OCCUR BEFORE THE 
ASSOCIATED STORE CYCLE BEGINS (DRQ IS LATCHED ON THE RISING EDGE OF CLK ) 

5) TO PREVENT THE NEXT STORE CYCLE FROM OCCURRING, DRQ MUST BE BROUGHT LOW BY THE RISING EDGE OF CLK IN T 4 
OF THE CURRENT STORE (FOR B/B-+W SOURCE SYNCHRONIZED AND W-^B/B DESTINATION SYNCHRONIZED, IT MUST BE 
LOW BY THE RISING EDGE OF CLK IN THE FOURTH CLOCK OF THE CURRENT STORE CYCLE INCLUDING WAIT STATES ) 



Figure 20. Destination-Synchronized Transfer Cycle 

3-139 



AFN-02172A 



AP-123 



32K BYTE 
2732A-2 
EPROM 



BUS 
ARBITER 



8K BYTE 
2141-4 
SRAM 



RESIDENT 
BUS INTER- 
FACE 



MULTIBUS* 
INTERFACE 



8259 
INTERRUPT 
CONTROLLER 



8K BYTE 




2732A 




EPROM 





2K BYTE 
2114AL-3 
SRAM 



8279 
KYBD/DISPLAY 
CONTROLLER 



4-8275 
CRT 
CONTROLLERS 



LOCAL 
I/O BUS 
INTERFACE 



32K BYTE 
2118-12 
DRAM 



DUAL-PORT 
MEMORY 
CONTROL 



8089 
IOP 



PERIPHERAL CONTROLLER 



Figure 21. Remote Configuration with Dual-Port RAM 

3-140 



AFN-02172A 



AP-123 



the dual-port RAM. In many cases, the 8086 also pre- 
pares the task programs and stores them in the dual- 
port RAM, from which they may be downloaded to a 
memory on the 8089's I/O bus. The 8089 executes the 
task programs (from the dual-port RAM or from a local 
memory on the I/O bus), while the 8086 simultaneously 
executes other control or application programs. The 
application programs may encompass a wide variety of 
operations, but they will always generate the display 
characters and store them in the dual-port RAM. The 
8089 returns status to the 8086 when task program 
execution has been completed. 



Figures 22 and 23 show the manner in which the 
memories are organized. Figure 22, which shows the 
memory configuration for the 8086, should be taken as 
an example, since many different configurations are 
possible, according to the user's application. Figure 23 
shows the memory configuration for the 8089, given the 
particular choices made for the application discussed in 
this note. Of the memories shown in Figure 22, the 2141 
static RAMs and the 2732A EPROMs are located on the 
8086's local bus, while the 2816 EEPROM and the 21 18 
dual-port RAM are interfaced to the Multibus. The 2816 
is a non-volatile read/write memory equivalent in its 
storage capacity to the 2716 EPROM. 



BOOTSTRAP LOADER 
OPERATING SYSTEM 
APPLICATION PROGRAMS 



DISPLAY BUFFER 
PROGRAM STORAGE 
(DOWNLINE LOADED) 



NON-VOLATILE DATA 
STORAGE 



INTERRUPT VECTOR TABLE 
STACK 
SCRATCH PAD 



2732A-2 
EPROM 



2118-12 
DUAL-PORT 
DYNAMIC RAM 



2816 
EEPROM 



2141-4 
CPU LOCAL 
MEMORY 



Figure 22. CPU Memory Organization 



SYSTEM SPACE 



2 PAGES 
DISPLAY 
BUFFER 



2118-12 
DYNAMIC M 



CRT CONTROLLER 1 



CRT CONTROLLER 2 



CHANNEL 
PROGRAM 



2732A 
EPROM 



SCRATCH 
PAD 



2114AL-3 
RAM 



Figure 23. IOP Memory Organization 

3-141 



AFN-02172A 



AP-123 



8086/8089 Software Interface 

Comparing Figures 22 and 23, it can be seen that the 
2118 dynamic RAM appears in the memory con- 
figurations for both the 8086 and the $089. In the 8086's 
system space, this memory occupies addresses F0000 
through F7FFF, while in the 8089's system space, its 
address range is F8000 through FFFFF. 

Figure 24 shows the organization of the dual-port 
RAM. The addresses given are those seen by the 8089. 
The display data (for the CRT refresh function) is con- 
tained in the two largest blocks—Display Page 0 and 
Display Page 1. Each page contains 15K bytes, enough 
to refresh a color graphic screen containing 48 rows of 
80 characters each. In typical operation, the 8086 and 
the 8089 both access the same page of display data. In 
special cases, such as animated displays, the 8089 per- 
forms repetitive DMA transfers from one of these 
pages, while the 8086 is generating new display material 
and storing it in the other page. The display page pointer 
(DSPLY_PG_PTR) in the parameter block specifies 
which of these pages is to be displayed at any given 
time. This pointer may be changed by the 8086, or by a 
command from the terminal keyboard. 

The Command Buffer is a 256-byte area set aside for 
transferring ASCII characters from the 8086 to the 
8089. It is like a second keyboard, scanned by the 8089. 
It takes precedence over any real keyboard activity. 
The COM—8086 flag in the parameter block is used to 
indicate when there are entries in the command block 
area. 

The EEPROM Buffer is a 256-byte area used in connec- 
tion with the non-volatile EEPROM memory, an op- 
tional memory which may be located on the Multibus. 
One use of such a memory would be to store ASCII 
strings, which could then be recalled by the 8086 upon 
recognition of special keyboard control code 
sequences. 

The Keyboard Buffer is a 256-byte area which serves as 
a storage area for ASCII characters entered from the 
terminal keyboard. When this buffer becomes full, or 
when a return is entered at the keyboard, an end-of-file 
byte is placed after the last entered character, and the 
keyboard buffer full (KBD_BUF_FULL) flag is set in 
the parameter block. This prevents the 8089 from pro- 
cessing any more inputs from the keyboard, until the 
8086 resets KBD__BUF_FULL. 

The Spare blocks total IK (1024) bytes, and may be 
used for any purpose, according to the user's 
application. 



LINKED IOP CONTROL BLOCKS 



DISPLAY PAGE 1 



KEYBOARD BUFFER 



EEPROM BUFFER 



COMMAND BUFFER 



DISPLAY PAGE 0 



FFCOO 
FFBFF v 



} 



Figure 24. Organization of the Dual-Port RAM 



The Linked IOP Control Blocks are those which have 
been discussed above, as part of the 8089 overview. The 
specific memory locations are as shown in Figure 25. 
Note that there is only one parameter block, and no task 
blocks present. Only one task block is used in this 
application, and it is stored in the 2732A EPROMs on 
the 8089's I/O bus. 



3-142 



AP-123 



SYSTEM CONFIGURATION 
POINTER 



SYSTEM CONFIGURATION 
BLOCK 



CHANNEL CONTROL BLOCK 



PARAMETER BLOCK 



FFFFO 
FFFEF 



FFFEO 
FFFDF \ 



Figure 25. Organization of the Linked 
IOP Control Blocks Area 

As mentioned earlier, the structure of the parameter 
block is very flexible. Only the first four bytes are fixed 
(because of the 8089's requirements). These four bytes 
contain the address of the task block. The remaining 
space in the parameter block may be defined by the 
user. The following list shows the parameter block 
structure that is used in support of the channel program 
contained in the 2732A EPROMs on the 8089's I/O bus. 



TP_LSW 


DW 


TP_MSD- 


DW 


EEP—INH 


DB 


EEP_BUF_FULL 


DB 


EEP—RECALL 


DB 


COL_CH_INH 


DB 


KBD—INH 


DB 


KBD_ BUF—FULL 


DB 


COM_8086 


DB 


COLOR 


DB 


STR^PTR_8086 


DW 


BACK-COL-SW 


DB 


MON—INH 


DB 


DSPLY_PG_PTR 


DB 


SCROLL—REQ 


DB 


MON-HOM 


DW 


MON-END 


DW 


MON_ LMARG 


DW 


MON^_RMARG 


DW 


KBD_BUF_PTR 


DW 



In the above table, DB represents a one-byte quantity, 
and DW represents a two-byte quantity. 

TP-LSW and TP_MSD are the two words making up 
the task pointer. However, since in this application the 
task program is in the I/O space, only the least- 
significant word (LSW) is fetched. 

EEP—INH, when not equal to zero, indicates that the 
EEPROM buffer is closed to keystrokes or 8086 ASCII 
commands. 

EEP_BUF_FULL, when not equal to zero, indicates 
that the EEPROM buffer is full. 

EEP—RECALL, when not equal to zero, indicates that 
the 8089 is recalling the contents of an EEPROM buffer 
area. 

COL-CH— INH, when not equal to zero, inhibits the 
color control keys on the keyboard. 

KBD—INH, when not equal to zero, inhibits the pro- 
cessing of keystrokes (entered at the keyboard) by the 
8089. Up to 6 keystrokes may be saved in the keyboard 
controller and may be processed later. 

KBD— BUF—FULL, when not equal to zero, indicates 
that a new line of keyboard data needs to be processed 
by the 8086. The 8089 sets KBD_ BUF_ FULL equal to 
-1 when the return key is pressed. The 8086 resets 
KBD—BUF—FULL to zero after it has read this data. 

COM— 8086, when not equal to zero, indicates that 
there are ASCII commands in the command buffer 
areas of dual-port RAM that need to be processed by 
the 8089. 

COLOR determines the foreground and background 
colors to be used in connection with ASCII characters 
entered at the keyboard, or sent by the 808$ via the 
command buffer area. In the COLOR byte, bits B0-B2 
determine the background color, while B3-B5 deter- 
mine the foreground color. The following code is used: 



000 


Black 


001 


Red 


010 


Green 


011 


Yellow 


100 


Blue 


101 


Magenta 


110 


Cyan 


111 


White 



STR-PTR-8086 is a two-byte quantity that serves as 
an offset address for the ASCII characters in the com- 
mand buffer. , 



3-143 



AP-123 



BACK-XOL^SW determines whether the 8089 color 
control keys will alter the foreground or the back- 
ground portions of the COLOR byte. If BACK- 
—COL—SW equals zero, the foreground color is 
altered. If BACK_COL_SW is not equal to zero, the 
background color is altered. 

MON-INH, when not equal to zero, suspends DMA 
transfers by the 8089 from display memory to the 8275s. 
When MON-JNH is cleared, DMA will resume. 

DSPLY_PG_JPTR determines which of the two display 
pages will be used to refresh the CRT. If DSPLY-- 
PG—PTR equals zero, page 0 will be displayed./ If 
DSPLY__PG_PTR does not equal zero, page 1 will be 
displayed. 

SCROLL_REQ is set by the 8089 to indicate to the 8086 
that the cursor is at the bottom of the page, and that key 
entry/command processing has been halted, pending a 
display memory scroll operation. When the 8086 has 
performed this operation, it clears SCROLL-REQ. 

MON-HOM, MON_END, MON—LMARG, and 
MON— RMARG specify, respectively, the upper, lower, 
left, and right boundaries of the region on the screen in 
which keyboard entries will be displayed. 

KBD_BUF_PTR is a two-byte quantity that serves as 
an address for the ASCII characters in the keyboard 
buffer. 

Note that a number of these parameters support op- 
tions (e.g., EEPROM buffer) and are not critical to the 
graphic operation described in this application note. 

8089 Display Hardware Interface 

This section describes the hardware of the peripheral 
processing module (PPM), which includes everything 
between the system bus and the CRT display/keyboard 
unit. The overall organization of the PPM is as shown in 
Figure 21. The dual-port RAM can be accessed from 
either the system bus or the 8089's local bus; The 8089 is 
said to be operating in the system space when it is 
accessing the dual-port RAM, and in the I/O space 
when it is accessing devices on the I/O bus. Included on 
the I/O bus are four 8275 CRT controllers, an 8279-5 
keyboard controller, two 2732 A EPROMs, which are 
used to hold channel programs, and four 2114 static 
RAMs, which are used as scratch-pad RAM for the 
8089. 

As explained above (under OVERVIEW OF CRT 
GRAPHIC SYSTEMS, Performance Requirements), 
four bytes are used to specify each character in the 



display. The first byte determines whether the character 
is a text character or a graphic character, and specifies 
the colors for foreground and background. If it is a text 
character, the second byte specifies the character with 
a seven-bit ASCII code, and the remaining two bytes 
are not used. If it is a graphics character, the second, 
third, and fourth bytes contain the color specification 
for each of the twenty distinct picture elements (pixels) 
within the character. Use of the foreground color is 
indicated by a one in the respective bit position, while a 
. zero specifies use of the background color. 

The structure of the display characters and the formats 
of the individual bytes are shown in Figures 4 and 5. 

The four 8275 CRT controllers on the 8089's I/O bus are 
used to process the four bytes comprising each charac- 
ter. Since the 8089 can transfer two bytes at a time in 
DMA mode, the four bytes are transferred in two 
stages. In the first stage, the 8089 fetches the first two 
bytes from the dual-port RAM, and transfers these two 
bytes into the first pair of CRT controllers. In the 
second stage, the 8089 fetches the second two bytes 
from the dual-port RAM, and transfers these two bytes 
into the second pair of CRT controllers. This process is 
repeated 80 times to transfer the 80 characters making 
up each row in the display. 

The distinction between text and graphic characters is 
entirely transparent to the 8089. Four bytes are trans- 
ferred in every case, even though the text information 
only requires two bytes per character. 

We shall now examine the hardware schematics in 
detail, to see how the various functions of the PPM are 
implemented. Figure 26 shows the 8089 IOP and its 
associated bus controller. At the top left are the inputs 
through which the 8089 is controlled. The DRQF signal 
(detailed later) is the DMA request that initiates the 
transfer of two bytes from the IOP to two of the four 
CRT controllers. DRQF comes from the 8275s via a 
one-shot, and is connected to the DRQ 1 input of the 
8089. 

IRQ is an interrupt request that comes from the 8275s. 
It is activated after an entire screen's video information 
has been transferred from the dual-port RAM to the 
8275s. IRQ is connected to the EXT 1 input of the 8089. 
It is necessary to program the 8089 to terminate the 
DMA transfer on an external event, in order for this 
signal to be effective. 

CA is the Channel attention signal. Upon receipt of CA, 
the 8089 reads the channel control word (CCW) from 
the dual-pbrt RAM. From the CCW, the 8089 deter- 
/ mines the nature of the operation assigned to it by the 



3-144 



AFN-02172A 



AP-123 




AO/DO 
A1/D1 
A2/D2 
A3/D3 
A4/D4 
AS/05 
A6/DS 
A7/D7 
A8/D8 
A9/D9 
A10/D10 
A11/D11 
A12/D12 
A13/D13 
A14/D14 
A15/D15 
A16/S3 
A17/S4 
A18/S5 
A19/S6 
BRE 
SO 
Si 
52 

SINTR-1 
SINTR-2 



-A0/DO-A1S/D15 

A16/S3-A19/S6, §H1 
-§2 



v C c*- 




-Ai3we 

- AMW C 

-BWTC 
-SiR5C 
-JoTiC 

-INTA (READ I/O) 
-DT/ff 



- PEN 

-F6ER 



Figure 26. 8089 I/O Processor and 8288 Bus Controller 



8086. CA is derived by hardware decoding of an I/O 
write command made by the 8086 to address 00H or 
address 01H on the Multibus. The lowest-order bit of 
this address is used to specify whether channel 1 or 
channel 2 of the IOP is to be selected, and is connected 
to the 8089's SEL input. In this application, the DMA 
transfers are always performed by channel 1 . 



RDY is the ready signal that comes from the 8202 
dynamic RAM controller, and is synchronized by the 
8284A clock generator. RDY is low whenever the 8086 
is accessing the dual-port RAM. The RDY signal is used 
to establish a master/slave relationship between the 
8086 and the 8089, with the 8086 as the master. As 
mentioned earlier, the 8089 accesses the dual-port 
RAM about 50% of the time during DMA transfers. It , 
can be seen, referring to Figure 20, that if no idle clocks 
occur, the IOP will access the dual-port RAM during 
the four clock times of the DMA-fetch bus cycle, and 
will access the I/O bus during the four clock times of the 
DMA-store bus cycle. While the 8089 is doing the store 
operation, the 8086 can access the dual-port RAM. 
Once the 8086 has gained this access, the RDY signal 
will remain low until the 8086 is finished. The 8089 waits 
for RDY to go high before making a subsequent fetch. 



At 5 MHz, the 8089 requires 3.2 microseconds (16 clock 
cycles) to transfer the four bytes representing a graphic 
character from the display memory to the four 8275s, 
assuming that no wait states have been inserted be- 
cause of the 8086's access to the dual-port RAM, or 
because of dynamic RAM refresh functions. A com- 
plete row, consisting of 80 characters, requires 80 x 3.2 
= 256 microseconds. The time allowed to complete the 
transfer of one row must be less than the time it takes to 
display that row on the screen. This latter time is equal 
to 1/50 of the total screen update time, or 1/3000 of a 
second (333 microseconds). Comparing the two figures 
(256 vs 333), it can be seen that there are 77 microsec- 
onds available for such wait states. It is the responsibil- 
ity of the software designer to control the 8086's access 
to dual-port RAM in such a mannner that the added 
wait states do not total more than 77 microseconds in 
any span of 333 microseconds. Otherwise, underruns 
may occur and the CRT screen will be blanked. See 
System Performance (below) for further discussion on 
this effect. 

RST is the IOP reset signal, which comes from the 
8284A clock generator. The first CA after RST causes 
the IOP to access address FFFF6 in the dual-port 
RAM, in order to read the system configuration pointer. 



3-145 



AFN-02172A 



AP-123 



Outputs from the IOP are the time-multiplexed address 
and data lines, BHE/ (bus high enable), status lines SO, 
SI, and S2, and the system interrupt request lines, 
SINTR-1 and SINTR-2. The interrupt lines go directly 
to the Multibus, and from there they become inputs to 
the 8086's 8259A interrupt controller. 

Figure 27 shows the I/O address latches and decoder, 
and the circuitry used to generate the DACK/ signals 
for the CRT controllers. The IOP status bit S2 indicates 
whether the IOP is accessing the I/O space or the sys- 
tem space. Latched by ALE (address latch enable), S2/ 
generates IO and 10/. 10 and 10/ are used to indicate 
that the 8089 is not accessing dual-port RAM. 10/ goes 
to the dual-port RAM controller. 



The DACK/ signals are generated in the following 
manner: 

1. Both 8275 pairs are accessed by the 8089 (DMA 
mode) via port AOOOH. 

2. Hardware is used to select one pair of CRT con- 
trollers (bytes 0 and 1 or bytes 2 and 3). 

3 . As the £089 reads (DMA) the word from the dual- 
port memory, address bit 1 (SA1) is latched with 
the memory read command (MRDC/). 

4. When SA1 = 0, DACK 1/ is activated. 

5. When SA1 = 1, DACK 21 is activated. 

6. In this manner the 8089 performs alternating 
writes (DMA) to the 8275 pairs. 



ALE - 

A0/D0-A15/D15 - 



. A2/D2 3 


. A3/D3 


4 


. A4/D4 


5 


. A5/D5 


6 


. A6/D6 


7 


> A7/D7 


8 



AO/ttfl 1 



. A9/D9 


2 


L A10/D10 


3 


lA11/D11 


4 


, A1?/D12 


5 


k A13/D13 


6 


s AJ4/D14 


7 


, A15/D15 


8 



STB 




DIO 


DOO 


DI1 


DI2 


D01 


DI3 


D02 


DI4 


D03 


DI5 


D04 


DI6 


D05 


DI7 


D06 


OE 


D07 



n 



rt>r 



v C c* 

A20 
D 0 - 
74LS74 



A25 




AO 

A1_ 
A2 


I 




E3 
E2 
E1 


i 

07 


820S 





>-l 



A20 0 



74LS74_ 
Q 



" 10 EPR OM 

• eat? 

- •ggfT 

- CLK ENA 

- CRT DACK 

- KEYBOARD 



10 
10 



Figure 27. Address Latches, Decoders, and DACK Generator 

3-146 



AFN-02172A 



AP-123 



Figure 28 shows the bus transceivers used between the 
8089 and the I/O bus, and also shows the 2732 
EPROMs. 

Figure 29 shows the 2K bytes of 2114 static RAM on 
the I/O bus, which are used as scratch-pad RAM for 
the 8089. 

Figure 30 shows the 8279-5 keyboard controller, and 
also shows the 8284A clock generator that produces the 
CLK, RDY, and RST signals for the 8089. For more 
information on interfacing the 8279-5 to the keyboard 
(Cherry Electrical Products B70-05AB), refer to the 
8279/8279-5 data sheet and application note AP-32, CRT 
Terminal Design Using the Intel 8275 and 8279. 



IOA0-IOA15 



Figure 31 shows the clock generator for the character 
timing and dot timing. The character clock frequency (C 
CLK) is 1/8 of the dot clock frequency (D CLK), 10.8 
MHz. Also shown in Figure 31 is a 9602 one-shot used 
to generate the video sync pulses. 

Figure 32 shows the CRT Controllers #0 and # 1 . Bit 6 
of Byte 0 determines whether the display character is 
text or graphic. If Bit 6 is low, the character is a text 
character, and Byte 1 is used to address the 2732A 
character generator ROM. Bytes 2 and 3 are ignored. 
The line count outputs LC0-LC3 of an 8275 (any 8275 
can be used, since they are all synchronized) are also 
applied to the character generator to perform the line 
select function. 



dt/r ■ 

A0/DQ-A15/D15 - 



INTA . 
IORC - 



s 


2_ 




4 


5 




6 




7 


8 



17 




ts 




15 




14 




13 


12 





19 




18 




17 




16 




15 




14 




13 




12 







4> 



. IOA2 


7 


. IOA3 


6 


. IOA4 


5 


. IOA5 


4 


L IOA6 


3 


. IOA7 


2 


. IOA8 


1 


. IOA9 


23 


. IOA10 


22 


. IOA11 


19 


L IOA12 


21 



AO 


Oo 


A1 


©1 


A2 


Oz 


A3 


O3 


A4 


0 4 


A5 


0 5 


A6 


Oe 


A7 


07 


A8 




A9 




A10 




A11 





2732A 
OE 



10 


I0D1 „ 


11 


I0D2 . 


13 


IOD3 . 


14 


1004^ 


15 


I0D5 


16 


I0D6 A 


17 


I0D7 d 



^ IOA2 


7 


. IOA3 


6 


^ IOA4 


5 


k IOA5 


4 


. IOA6 3 


L IOA7 


2 


. IOA8 1 


^ IOA9 


23 


, IOA10 


22 


, IOA11 


19 


t IOA12 


21 



9 


IOD8 . 


10 


IOD9 ^ 


11 


IOD10 u 


13 


I0D11 u 


14 


I0D12 ^ 


15 


I0D13 u 


16 


IOD14 a 


17 


IOD15J 



2732A 
OE 



- IOD0-IOD15 



Figure 28. Bus Transceivers and EPROMs on I/O Bus 

3-147 



AFN-02172A 



AP-123 





6 


7 


4 




3 




2 




1 


17 




16 




IS 



AO 


1/01 


A1 


I/02 


A2 


I/03 


A3 


I/04 


A4 




AS 




A6 




A7 




A8 




A9 




wi 


ci* 





5 




14 


I0D8 




6 




13 


I0D9 








12 


IOD10 


s 


4 




11 


I0D11 




3 








2 








s 


1 










17 










.16 


A56 








15 










2144AL-3 







A38 
2114AL-3 



s, , 


S 




14 


I0D12 




6 




13 


10013 


s 


7 




12 


10014^ 




4 




11 


I0D15" 




3 








2 










1 








17 










16 


A74 








15 










2144AL-3 







Figure 29. Static RAMs on I/O Bus 



3-148 



AFN-02172A 



AP-123 



L lODt 13 


DBO 
DB1 
0B2 


L 1002 14 


L 1003 15 




1004 16 


DB3 
DB4 


L 1005 17 


L 1006 18 


0B5 



tORC 
AIOWC 
KEYBOARD 
I0A1 




RLO 
RL1 
RL2 
RL3 
RL4 
RL5 
RL6 

RL7 



39 RL1 


' " ""^ 




1 RL2 A 




2 RL3 . 




5 RL4 u 




6 RL5 . 




7 RL6 . 




8 RL7 , 




36 

37 STRB 




A3 

SACK "T/""" 

in *r._ 



10 
MBRW 



15 MHz 510 



RST 



AEN1 
F/C 

CSYNC 



CLK 
ROY 



Figure 30. Keyboard Controller and Clock Generator 



3-149 



AFN-02172A 



AP-123 



21.6 MHz 510 

1DI-r^ — n 



F/5 

CSYNC 



1^^2 9 



V C C* 

_A1 



D Q h 
A23 
0 



T" 

v C c* 



I" |13 



12 | 11 



A27 P_ 
765763 T 



HI 



. v cc* 



DCLK 
P2 



0.02/xF 
Hh 9602 
39K | 2 jl 



v C c*i 



=t>— -Or 

4 5 ^ 6 



Figure 31. Character Clock Generator and Video Sync Pulse 



3-150 



AFN-02172A 



, I0P2 14 
„ IOD3 15 



„ IOD4 



s 



DCLK 
VSP 



ceo 

CC1 
CC2 
CCS 
CC4 
CCS 
CC6 



2« 3 


25 


4 


26 


6 


27 


11 


28 


13 



cs 

Back orq 



A13 
8275 



CRT CONTROLLER #0 



5 


FOG 


5 


7 


FOB 


11 


10 


BGR 


3 


12 


BOG 


6 


15 


BGB 


10 





IOD9 


13 




IOD10 


14 




IOD11 


15 




IOD12 


16 


s 


IOD13 


17 




10014 


18 




IOD15 


19 



ceo 

CC1 
CC2 
CC3 
CC4 
CC5 
CC6 
LCO 
LC1 
LC2 
LC3 



A14 
8275 











1A 


1Y 


4 ■» 


54 


1B 




2A 


2Y 


7 GREEN 


55 






3A 








3B 


3Y 


9 BLUE 


56 


4A 




4B 

S 


4Y 


12 




G 


A39 
74157 







DRQ1 

CB0-CB6 

IRQ 



CRT 
CONTROLLER 



r LC1 



A5 
A6 
A7 
A8 
A9 
A10 

A1 
A2 
A3 



2732A 
A28 



F2T Ail 



16 


FB1 


r 1 ■■ 


12 


15 FB2 




11 


14 


FB3 


r— 


10 


13 


FB4 


r 1 1 


5 


11 


FB5 


4 


10 FB6 


3 


9 


FB7 




2 



LD CHAR 
RVV 



v C c*- 



CLR~" 
CLK INH 

SR IN 
74LS166 
LP 



Figure 32. CRT Controllers, Color Multiplexer, and Character Generator 



AP-123 



For each character, the foreground and background 
color bits are output from Byte 6 and latched into the 
74LS 174, from which they are applied to the input of the 
74LS157 multiplexer. Selection between foreground 
and background is done by the output of the 74LS166 
parallel-to-serial converter, which operates from either 
the text or graphic character generator, as appropriate. 
The roles of foreground and background color may be 
reversed by the RVV (reverse video) signal from the 
8275, which is exclusive-ORed with this color select 
output. 

Since the RBG (red-blue-green) inputs of the color 
monitor (Aydin Controls 8039D) are AC coupled, 
return-to-zero type outputs are needed to pass these 
signals through the input stages. This is provided by 
strobing the gate input of the 74LS157 multiplexer with 
the D CLK (dot clock) signal. By varying the duty cycle 
of the D CLK, the user can produce many different 



shades of color. The D CLK signal is ORed with the VSP 
(video suppress) signal from the 8275, to produce com- 
plete video blanking when desired. 

Figure 33 shows the CRT Controllers #2 and #3, the 
decoder for the line select function, and latches for the 
video control signals. CRT controllers #2 and #3 are 
operational in graphics mode only. Synchronization of 
the two pairs of CRT controllers is discussed in the 8089 
Display Functions Software section. 

Figure 34 shows the tri-state buffers used to handle the 
color information within a graphic character. The 
decoded line count outputs (ROW 0/-ROW 4/) are used 
to select which buffer is enabled onto the bus. The 
buffer A36, enabled by the GRAPH MODE signal, is 
used to "double up" the four graphic cells to produce 
eight (horizontal) dot inputs to the shift register (Figure 
32). 



IQRC 

aiowc 

IOA1 

cmT 

0ACK2 
GC CLK 



DRQ1 
LC0-LC3 



r 



DB1 
DB2 
DB3 
DB4 
DBS 



CCO 
CC1 
CC2 
CC3 
CC4 
CCS 
CCS 



25 


CB9 


26 


CB10 . 


27 


CB11 . 


28 


CB12 u 


29 


CB13 . 



DB7 
RD 



CS 

DACK 

CCLK 



LPEN 
A15 
8275 



CRT 
CONTROLLER 



JOD9 


13 


J0P1Q 


14 


JOD11 


15 


. IOD12 


16 


IOD13 


17 


JOD14 


18 


flOD15 


19 



r 



24 


CB15 . 


25 


CB16 „ 


26 


CB17 j 


27 


CB18 A 


28 


CB19 . 


29 


CB20 



8275 
A16 



DRQ 



ft 



ROW 3 
ROW4 



CRT CONTROLLER #3 



40 40 



T 

v CC * 



HTRC 
INT VTRC 



Figure 33. CRT Controllers, Line Decoder, and Video Control Signal Latch 



3-152 



AP-123 



CBO 
\ CB1 



ROWO 
ROW? 
GRAPH MODE 



ROW 2 
ROW 3 



CB18 



AMWC 
MWTC 
MRDC 



1A1 
1A2 
1A3 
1A4 
2A1 
2A2 
2A3 



1Y1 
1Y2 
1V3 
1Y4 



2Y3 
A4 2Y4 
74L8244 

1Q 20 



SB2 . 



.CM 


2 


, CB9 


4 


. CB10 


6 


t CB11 


8 




11 


. CB13 


13 


. CB14 


15 


, CB15 


17 





74LS244 
~P 7 



16 


SB1 . 


14 


SB2 A 


12 


SB3 A 


9 SBO A 


7 


SB1 J 


5 


SB2 A 


3 


SB3 A 



16 SB1 . 


14 


SB2 . 


12 


SB3 



74LS244 



A36 
74LS244 



14 


FB2 1 


12 




9 


M4 J 


7 FB5 J 


5 FB6 1 


3 FB7 J 



SWTC 
SRDC 



Figure 34. Tri-State Buffers for Graphic Color Information 



3-153 



AFN-02172A 



I 

AP-123 



The block diagram in Figure 35 shows how the text 
characters are processed. The following statements ap- 
ply to Figure 35: 

1. Byte 0, Bit 6 = 0 indicates text mode. 

2. The six color signals from CRT Controller #0 
(three foreground and three background) are 
latched and transmitted to the multiplexer. 

3. The seven character output signals and the three 
line count signals from CRT Controller #1 are 
transmitted to the text character generator. 



4. The eight output signals from the text character 
generator are transmitted to the parallel-to-serial 
converter. 

5. The serial, horizontal dot data is transmitted to 
the multiplexer and selects foreground (dot data 
bit = 0) or background (dot data bit = 1) color 
signals. 

6. The red, blue, and green color signals are trans- v 
mitted to the color monitor. 

7. CRT Controllers #2 and #3 are not operational in 
text mode. 



CRT 
CONTROLLER 



CRT 
CONTROLLER 



FOREGROUND & BACKGROUND 6 



COLOR SELECT 



TEXT 
CHARACTER 
GENERATOR 



MULTIPLEXER 



RED 

BLUE 

GREEN 



SERIAL HORIZONTAL 
DOT DATA 



PARALLELTO 

SERIAL 
CONVERTER 



Figure 35. Processing of Text Characters 



3-154 



AFN-02172A 



AP-123 



The block diagram in Figure 36 shows how graphic 
characters are processed. The following statements ap- 
ply to Figure 36: 

1. Byte 0, Bit 6 = 1 indicates graphic mode. 

2. The six color signals from CRT Controller #0 
(three foreground and three background) are 
latched and transmitted to the multiplexer. 

3. The three line count signals from CRT Controller 
#1 are transmitted to a one-of-eight decoder 
which generates five row select signals (ROW 0- 
ROW 4). 

4. The twenty pixel signals from CRT Controllers 
#1, #2, and #3 are transmitted to three octal 
buffers. 



5. The four pixel signals of the selected row (based 
on the row select signals) are transmitted to an- 
other octal buffer. 

6. The octal buffer converts these four bits to eight 
bits by duplicating each signal. Thus, output bits 0 
and 1 are equal, 2 and 3 are equal, etc. 

7. The eight output signals of the octal buffer are 
transmitted to the parallel-to-serial converter. 

8. The serial, horizontal dot data is transmitted to 
the multiplexer and selects foreground (dot data 
bit = 0) or background (dot data bit = 1) color 
signals. 

9. The red, blue, and green color signals are trans- 
mitted to the color monitor. 



CRT 
CONTROLLER 



CRT 
CONTROLLER 



CRT 
CONTROLLER 



CRT 
CONTROLLER 



DECODER 
(1 OF 8) 



FOREGROUND & BACKGROUND 



COLOR SELECT 



RED 
BLUE 
GREEN 



SERIAL HORIZONTAL 
DOT DATA 



BUFFER 




PARALLELTO 






SERIAL 




8 


CONVERTER 


74LS244 




74LS166 



Figure 36. Processing of Graphic Characters 

3-155 



AFN-02172A 



/ 

/ 

AP-123 



Figure 37 shows the circuit used to synchronize the 
8275s, and also the circuit used to generate the DRQF 
signal. As mentioned earlier (see Figure 20), if the 8089 
were to wait for a subsequent DRQ signal from the 
8275s, some clock cycles would be allocated to idle 
clocks, and the DMA transfer would become less effi- 



cient. To preclude this, the circuit shown in Figure 37 
generates a surrogate (early) DRQ signal, DRQF, using 
a one-shot triggered by the trailing edge of DRQ (DRQ 1 
AND DRQ 2). The one-shot times out prior to the rising 
edge of CLK in T4 of the DMAs store bus cycle. 



H5T 




8.2K 50 pF 



v CC * 



DRQ1 
DRQ2 



Vcc* 



0 Q 



Q 

i "Y""ai 

v CC * 



v CC * 



v CC * 



12 



QL» i-d \ 3 

?13 A24 



Figure 37. Circuits to Synchronize CRT Controllers and Generate DRQF 



3-156 



AFN-Q2172A 



AP-123 



Figure 38 shows the relationship between the individual 
DRQ signals from the 8275s and the DRQF signal that is 
sent to the 8089. DRQ 1 is the data request representing 
the 8275s #0 and #1, while DRQ 2 similarly represents 
the 8275s #2 and #3. The DACK 1/ and DACK 21 
signals (along with AIOWC/) are used to deactivate 
DRQ 1 and DRQ 2, respectively. 



Figure 39 shows the multiplexer used to control writing 
of data to the dual-port RAM. When 10 and S WTC/ are 
both low, the 8089 data is gated to the dual-port RAM. 
When BDSEL/ and SWTC/ are both low, the 8086 data 
is gated to the dual-port RAM. BDSEL/ may be active 
only when the 8089 is in the I/O space. Note that the 
address range for the dual-port RAM is F8000-FFFFF 
as seen by the 8089, and F0000-F7FFF as seen by the 
8086. 



BYTES 0 AND 1 

FETCH STORE 
T1 | T2 | T3 | T4 J T1 | T2 | T3 | T4 



BYTES 2 AND 3 

FETCH STORE 
T1 | T2 | T3 j T4 T1 | T2 j T3 | T4 



DRQ1 

(FROM 8275 #0 and #1) 



DRQ2 

(FROM 8275 #2 AND #3) 



DRQ = DRQ1>DRQ2 



DRQF 

(TO 8089 DRQ1 INPUT) 



DACK1 

(TO 8275 #0 AND #1) 



DACK2 

(TO 8275 #2 AND #3) 



AIOWC 
(FROM 8288) 




= LAST TRANSFER 



Figure 38. Derivation of DRQF Signal 



3-157 



A0R15 
A0/D0-A15/D15 



IOWC 
MRDC 
MWTC 

IORC 



°6 ^ 



on 



D12 
D13 



"PT5 



v C c*- 




A70 
STB 



DOO 
001 
0O2 



D04 
D05 



SRDC 
SWTC 
SIOR 



Uw ^ 



T 


A72 


AO 


BO 


A1 


IT 


A2 


B2 


A3 


§3 


A4 


B4 


A5 


B5 


A6 


15 


A7 


B7 


61 


8287 



18 


WSD1 




17 


WSD2 




16 


WSD3 




15 


WSD4 




14 


WSD5 




13 


WSD6 




12 


WSD7 


> 



18 


WSD9 „ 


17 


WSDIO^ 


16 


WSD11 J 


15 


WSD12^ 


14 


WSD13^ 


13 


WSD14 A 


12 


WSD15 J 



v C c* 



s 


AU/UU 

A1/D1 


2 


s 


A2/D2 


3 


< 


A3/D3 


4 




A4/D4 


5 




A5/D5 


6 




A6/D6 


7 




A7/D7 


8 



T 


A35 


AO 


BO 


A1 


B1 


A2 


B2 


A3 


B3 


A4 


B4 


A5 


B5 


A6 


B6 


A7 


B7 


OE 


8286 



18 


WSD1 




17 


WSD2 




16 


WSD3 




15 


WSD4 




14 


WSD5 




13 


WSD6 




12 


WSD7 







A9/D9 


2 




A10/D10 


3 




A11/D11 


4 




A12/D12 


5 




A13/013 


6 




A14/014 


7 




A15/015 


8 



18 WSD9 ^ 


17 WSD10 




16 WSD11 




15 WSD12 


j 


14 WSD13 




13 WSD14 


> 


12 WSD15 


> 



Figure 39. Multiplexer for Writing to Dual-Port RAM 



WSD0-WSD15 



> 

CO 



AP-123 



j 

Figure 40 shows the demultiplexer used to control read- 
ing of data from the dual-port RAM. The internal trans- 
fer acknowledge (SACK/) signal from the dynamic 
RAM controller latches this data. If MRDC/ is active, 
the data is then gated to the 8089. If BD EN AI is active, 
the data is gated to the Multibus for transmission to the 
8086. 



Figure 41 shows the multiplexer for the address inputs 
to the dual-port RAM. If the 10 signal is high, the 
address on the Multibus is gated into the dual-port 
RAM. If 10 is low, the address from the 8089 is gated 
into the dual-port RAM. 



A0/D0-A15/D15 
8089 BUS 




BD ENA 



Figure 40. 



Demultiplexer for Reading from Dual-Port RAM 

3-159 

j 



AFN-02172A 



AP-123 



A0-A19, BHE 
ALE 



aorT 


2 


ADR2 


3 


ADR3 4 


ADR4 5 


IMS 


6 


ADR6 


7 


ADR? 


8 



APR8 



APR9 



ADR11 



ADR12 



-A0R11 



T 


A51 


AO 


"bo 


A1 


B1 


A2 


B2 


A3 


B3 


A4 


B4 


A5 


B5 


A6 


B6 


A7 


B7 


OE 





SA2 A 



SA3 A 



SA6 A 



18 


SA9 . 




17 


SA10 


/ 


16 


SA11 


4 


15 


SA12 




14 


SA13 




13 


SA14 


* 


12 


SA15 


4 



AOR16 


ii 


ADR17 


2 




3 




4 


(dsn 


5 



18 


SA17 




17 


SA18 




16 


SA19 




15 


BHEN 





t, 


A1 


2 




A2 


3 




A3 


4 




A4 


5 




A5 


6 


s. 


A6 


7 




A7 


8 




. A9 


2 . 


k A10 


3 




4 


. A12 


5 


k A13 


6 


A14 


7 


L A15 


8 



8282 



18 


SA9 A 


17 


SA10, 


16 


SA11 u 


15 


SA12 A 


14 


SA13 j 


13 


SA14 A 


12 


8A15^ 



k A17 


2 


k A18 


3 


. A19 


4 



BHF *r 



18 


SA17^ 


17 


SA18 A 


16 


SA19^ 


15 


BHEN J 



Figure 41. Multiplexer for Address Inputs to Dual-Port RAM 



3-160 



AFN-02172A 



AP-123 



Figure 42 shows the 8202 dynamic RAM controller. The 
inputs SA0-SA19 come from the multiplexer shown in 
Figure 41. The dynamic RAM controller generates the 
control signals (shown at the right of the page) for 
operating the dynamic RAM. 

Figures 43 and 44 show the dynamic RAM itself. 



8089 Display Functions Software 

The 8089 display functions software consists of a single 
program which is executed by the 8089 on a continuous 
basis. This program performs the following functions: 

Initialization for the 8089 itself and for the CRT con- 
trollers and the keyboard controller; 



.SA2 


8 


,SA3 


10 


.SA4 


12 


^SA5 


14 


.SA6 


16 


JSA7 


18 


.SA8 


5 


SA9 


4 


. SA10 3 


^8A11 


2 


. SA12 


1 


SA13 39 


SA14 


38 



SRDC 
SWTC 



A9 A19 



SA19 
SA15 



3> 



24 MHz 680 

HDh — 



AL0 OUT0 

AL1 OUT1 

AL2 OUT2 

AL3 OUT3 

AL4 OUT4 

ALS OUT5 

AL6 OUT6 



9 


OUT1 




PUT? „ 


13 




15 


OUT4 u 


17 


OUT5 u 


19 


ODte J 



CAS 



AH1 
AH2 

AH3 RAS0 
AH4 
AH5 



RD 



PCS 
B0 



WE 
XACK 



REFRQ/ 
ALE 



CAS 
RAS 
WE 



INT XACK 
SACK 



XACK 



Figure 42. Dynamic RAM Controller 



3-161. 



AFN-02172A 



WSD0-WSD7 
RSD0-RSD7 



RAS 
CAS 



WE 
SAO 



A2 
A3 
A4 
A5 
A6 
RAS 
CAS 
Wl 
2118-12 



°bUT 



Figure 43. Dynamic RAM (Low Data Byte) 



RAS 
CAS 



BHEN — -C I J 



WS08-WSD15 
RSO8-RS015 



Figure 44. Dynamic RAM (High Data Byte) 



AP-123 



The transfer instruction which causes the DMA 
transfer of the CRT refresh data to begin. 

Polling routines for the keyboard and the command 
buffer. 

Figure 45 is a simplified flowchart showing the relation- 
ships among these three main functions. The program 
begins upon receipt of the second CA (channel atten- 
tion) following an IOP reset. After the initialization 
processes have been completed, the program loops 
continuously, alternating between DMA transfer and 
polling processes. There are 48 rows of characters on 
the screen. The polling processes are carried out during 
the vertical retrace time, which is the equivalent of 2 
rows. Thus, it is easy to see that the DMA process uses 
up 96% of the 8089's time, leaving 4% for the polling 
processes. 



CA 



INITIALIZATION 








CRT 
REFRESH 
(DMA) 






POLl 


-ING 



Figure 45. Channel Program Simplified Flowchart 

As mentioned earlier, the channel program is stored in 
the 2732A EPROMs on the I/O bus. Figure 23 (above) 
shows the address assignments for devices on the I/O 
bus. The 2732As occupy addresses 200O-3FFF. The 
8089 also uses a scratch-pad static RAM (2K bytes at 



addresses 0000-07FF). The CRT controllers are ac- 
cessed by using addresses 4000 and 6000 on the I/O 
bus. Address 6000 is "CRT Controller 1" and actually 
refers to the first pair of 8275s. Address 4000 is "CRT 
Controller 2," the second pair of 8275s. Address 8000 is 
a clock enable address. Write commands to this address 
enable or disable the GC clock, which is the character 
clock for the 8275s. Address A000 is decoded to pro- 
duce the DACK signal for the 8275s. Address C000 is 
the address of the keyboard controller. 

The exact manner in which the channel program ex- 
ecutes depends on the flag settings and parameter 
values in the parameter block. 

Appendix A is a flowchart for the complete channel 
program-. Appendix B is the corresponding ASM-89 
assembly language listing. In the paragraphs to follow, a 
general overview of the channel program is given. The 
reader may refer to the flowchart and listing if a more 
detailed description is desired. 

The first CA after IOP reset causes the 8089 to fetch the 
system configuration pointer (SCP) and system configu- 
ration block (SCB) from dual-port memory. These 
blocks contain certain very basic system-level informa- 
tion for the 8089, as explained above under Overview of 
the 8089. 

The next CA causes the channel program to begin ex- 
ecution (at the point marked START on the flowchart). 
The initialization portion of the channel program con- 
sists of the following operations: 

Start and initialize the 8275 CRT controllers. 

Initialize the 8279 keyboard controller. 

Initialize the dual-port variables (parameter block). 

Synchronize the 8275 CRT controllers. 

To initialize and synchronize the 8275s, the channel 
program performs the following operations: 

Enable the GC CLK to the 8275s by writing 01H to 
I/O port address 8000H. 

Send the Reset command to the 8275s, followed by 
the four screen format parameters (all commands 
sent to the 8275s are sent first to the pair of 8275s at 
address 6000H and then repeated for the second pair 
of 8275s at address 4000H). 

Send the Preset Counters command to the 8275s. 

Disable the GC CLK by Writing 0QH to address 
8000H. 

Send the Start Display command to the 8275s. 

Enable the GC CLK again by writing 01H to address 
8000H. The 8275s are now initialized and 
synchronized. 



3-164 



AFN-02172A 



AP-123 



After the initializations have been completed, the chan- 
nel program enters its main loop. The 8089 channel 
control register is loaded to specify the following DMA 
conditions: 

Data transfer from memory to I/O port. 

Destination-synchronized transfer. 

GA register pointing to data source. 

Termination on external event. 

Termination offset = 0. 

The source for the DMA transfer (display page 0 or 1) is 
then selected according to the value of DSPLY_- 
PG—PTR (the display page pointer initialized by the 
host CPU) in the parameter block. The CRT character 
clock is then started and the DMA transfer begins. 
When the entire screen has been refreshed, the 8275s 
activate the 8089's EXT input. 

The 8089 then executes the SINTR instruction, which 
causes an interrupt to be sent to the 8086 (SINTR- 1 line 
on the Multibus), to notify the 8086 that the page trans- 
fer has been completed. The 8089 then reads the CRT 
controller status registers which causes the IRQ signal 
(from the 8275s to the 8089) to be reset. 

The channel program then begins the polling process 
which checks for ASCII commands from the 8086 (in 
the command buffer) and also for key depressions at the 
keyboard. In addition to the alphanumeric characters, 
the channel program recognizes the following control 
characters: 



Character 


Code 


Description 


CNTRL-A 


01 


Monitor Inhibit 


CNTRl^B 


02 


Monitor Uninhibit 


CNTRL-C 


03 


EEPROM Inhibit 


CNTRI^D 


04 


EEPROM Uninhibit 


CNTRL-E 


05 


Turn on EEPROM Buffer 


CNTRL-F 


06 


Display Page 0 


CNTRI^G 


07 


Display Page 1 


CNTRL-H 


08 


Backspace 


CNTRI^I 


09 


TAB (Every 8 Characters) 


CNTRLJ 


OA 


Linefeed 


CNTRL-K 


0B 


EEPROM Buffer Off 


CNTRL-L 


OC 


Erase Page 


CNTRL-M 


0D 


Carriage Return 


CNTRL-N 


0E 


Set Background Color 


CNTRL-O 


OF 


Set Foreground Color 


CNTRI^P 


10 


Set Color to Black 


CNTRI^Q 


11 


Set Color to Red 


CNTRI^R 


12 


Set Color to Green 


CNTRL-S 


13 


Set Color to Yellow 


CNTRI^T 


14 


Set Color to Blue 


CNTRI^U 


15 


Set Color to Magenta 


CNTRL-V 


16 


Set Color to Cyan 



CNTRL-W 


17 


Set Color to White 


CNTRI^X 


18 


Abort Line 


CNTRLrY 


19 


Cursor Right 


CNTRL-Z 


1A 


Cursor Down and Left 


CNTRI/ 


IE 


Cursor Up 


CNTRI^/ 


1C 


Cursor Home 


CNTRL-DEL 


IF* 


Recall EEPROM Buffer 



The first four commands listed above are not recog- 
nized if they originate from the physical keyboard, but 
are recognized if they appear as ASCII commands in 
the command buffer (that is, if they come from the 
8086). Refer to the flowchart (Appendix A) for more 
details on how the channel program responds to the 
control characters. 

System Performance 

The 8089 performs DMA transfers on 921,600 bytes of 
display data per second. In addition, the 8089 executes 
a polling routine (described above) during the vertical 
retrace time (the equivalent of two display rows). The 
DMA transfer (for a single frame) takes 16.000 millisec- 
onds. This leaves .667 milliseconds for the polling 
routine to execute, out of a total of 1/60-second CRT 
refresh period. The program listed in Appendix B takes 
about 300 microseconds to execute, approximately half 
the available time. When the polling process is finished, 
the channel program goes back to DMA mode, and 
waits for the first DRQ signal from the 8275s. 

While the polling routine is executing, the 8089 makes 
most of its memory accesses in the I/O space, and the 
dual-port RAM is available to the 8086. When the 8089 
returns to the DMA routine, however, it hangs the 
dual-port RAM while waiting for DRQ. This occurs 
because the fetch from the dual-port RAM deactivates 
the IO signal which locks out the 8086 from the dual- 
port RAM. The IO signal is then not activated until 
DRQ is received and the data is written to the CRT 
controllers. This can adversely affect system through- 
put. Therefore, if it is desired to increase the 8086's 
access to the dual-port RAM during this period, the 
user should insert NOPs into the channel program so 
that it spends more time in the I/O space before return- 
ing to DMA. 

The 8086 may also access dual-port RAM during the 
DMA transfer. The dual-port RAM is available to the 
8086 on approximately a 50% duty cycle (during the 
store portion of the DMA transfer cycle). The 8089's 
store cycle is 800 nanoseconds long (assuming a 5 MHz 
clock). The 8086's access to dual-port RAM (assuming 
an 8 MHz clock) takes 500 nanoseconds. However, 
since the two processors operate asynchronously, the 
8086 may begin its access at any point during the 8089's 



3-165 



AFN-02172A 



AP-123 



DMA store cycle. Since the 8086 is the master relative 
to the dual-port RAM, the ready signal for the 8089's 
next fetch operation will not be generated until the 8086 
is through. Thus, on occasion, the 8089 will have to 
wait. 

Each row of characters requires 256 microseconds of 
DMA transfer time if no such wait states occur. The 
repetition rate for rows of characters is 333 microsec- 
onds (1/3000 second). Thus, the accumulated wait 
states due to the 8086's access to dual-port RAM may 
total 77 microseconds before any underrun occurs. The 
8086 programs should be written in such a manner that 
the added wait states do not total 77 microseconds 
during any one period of 333 microseconds. The most 
important single factor in assuring this is to avoid mak- 
ing long burst transfers to or from the dual-port RAM. 
If an underrun does occur, the entire screen will be 
blanked until the beginning of the next frame. 

Aside from the shared access to dual-port RAM, the 
two processors may operate concurrently with no coor- 
dination necessary. Operations performed by the 8086 
(such as numeric processing of display data) may be 
programmed without regard to the overhead associated 
with IOP operations. 

Conclusions 

This application note has demonstrated that a high- 
performance, color-graphic CRT terminal can be con- 
veniently built using the Intel iAPX 86/11 
microprocessor system. This system utilizes a high- 
performance 8086 CPU operating at 8 MHz and an 8089 
I/O processor operating at 5 MHz. 

In particular, the unique abilities of the 8089 lend them- 
selves to the graphic CRT application by enabling a true 
multiprocessing approach to be used. The following list 
summarizes the capabilities used in this specific design: 



.High-speed DMA transfers (up to 1.25 mega- 
bytes/second) without wait states. 

Capabilities of a CPU and a DMA controller in a 
single 40-pin package. 

Support of concurrent operation for the system CPU 
and the I/O processor. Ability to access memory and 
address devices on both a system bus and a separate 
I/O bus. 

Flexible, memory-based communications between 
the I/O processor and the system CPU. 

Capability for 1-megabyte addressing in the system 
space. 

Capability for 16-bit DMA transfer, with external 
event termination. 

Support of modular, subsystem development effort 
due to the simple software interface (memory-based 
communications, plus channel attention and inter- 
rupt signals) and the simple hardware interface (CA, 
SEL, and SINTR lines). 

The following 8089 capabilities were not used in the 
design described in this note, but may be useful in other 
graphic CRT systems or I/O processing systems: 

Two channels, each of which may execute instruc- 
tions and perform DMA transfers. 

Bit manipulation instructions. 

Support of both 8-bit and 16-bit bus width in the 
system space and in the I/O space. 

Enhanced DMA capabilities, including: 

Translation (e.g., ASCII to EBCDIC code). 

Termination on masked compare. 

Word assembly/disassembly (8-bit word to/from 16- 
bit word). 

Memory-to-memory or I/O-to-I/O transfer. 
Synchronization on source, destination, or neither. 



3-166 



AFN-0?172A 



APPENDIX A/AP-123 



INITIALIZATION 



C START ) 



START 
AND INITIALIZE 8275 
CRT CONTROLLERS 



INITIALIZE 8279 

KEYBOARD 
CONTROLLER 



INITIALIZE STATIC 
RAM AND DUAL-PORT 
VARIABLES 



STOP CLOCK 
TO 8275s AND 
SYNCHRONIZE 



USE DISPLAY 
PAGE OAS SOURCE 
POINTER AND CRT AS 
DESTINATION 
POINTER 




CHANGE DMA 
SOURCE POINTER 
TO DISPLAY PAGE 1 




READ 8275 
STATUS REGISTERS 



AND MAIN LOOP 

DMA-BYPASS 




NO 

COM-STR-BYPASS 



SET UP CURSOR 
POSITION IN 8275* 



INCREMENT 8086 
COMMAND STRING 
POINTER 




CLEAR 8086 
COMMAND STRING 
POINTER 



SAVE 8086 
COMMAND IN 
KEYSTROKE REG 




CLEAR 6086 
COMMAND STRING 
POINTER 



I CURSOR-UPDATE 



al I DMA-BYPASS 



3-167 



AFN-02172A 



APPENDIX A/AP-123 



KEY AND COMMAND DECODE 




CURSOR-UPDATE 



GET KEY FROM 3279 
AND SAVE IT 



SAVE ASCII 
CHARACTER FOR 
EEPROM BUFFER 
RECALL 



CURSOR-UPDATE 




SAVE FIRST 
CHARACTER AFTER 
CNTL — E IN BUFFER 
FOR USE AS 
8086 INDEX 



a6 1 CHAR— OUT 



INCREMENT EEPROM 
BUFFER PTR 



CURSOR-UPDATE 



NOT-CNTRLD 



01 H 
02H 
03H 



MONITOR INHIBIT 
MONITOR UNINHIBIT 
EEPROM INHIBIT 
EEPROM UNINHIBIT 




V. CNTRL-2? ^S* 
1 NO 



( a4 J CURSOR-UPDATE 



CNTRL-F 


06H 




CNTRL-G 


07H 




CNTRL-M 


ODH 


CHAR-CR 


CNTRL-H 


08H 


BACK-SPACE 


CNTRL-P to CNTRL 






W 


10H-17H 


COLOR-KEY 


CNTRL-N 


OEH 


CNTRL-N 


CNTRL-0 


OFH 


CNTRL-0 


CNTRL-E 


05H 


CNTRL-E 


CNTRL-K 


OBH 


CNTRL-K 


CNTRL-DEL 


1FH 


EEP-DUMP 


CNTRL-2 


09H 


CURSOR-TAB 


CNTRL-L 


OCH 


ERASE-PAQE 


CNTRL-X 


18H 


CNTRL-X 


CNTLA 


ipH 


CURSOR-HOME 


CNTL-A 


1EH 


UP-CURSOR 


CNTRL-J 
CNTRL-V 


OAH 


DWN-CURSOR 


19H 


RIGHT-CURSOR 


CNTRL-Z 


1AH 


BACK-DOWN 



3468 



AFN-02172A 



APPENDIX A/AP-1 23 



CONTROL KEY OPERATIONS 




3-169 



AFN-02172A 



APPENDIX A/AP-123 




SIGNAL 8086 
THAT THE KEYBOARD 
BUFFER IS FULL 



0 



EEP-UP-EXIT 



3-170 



AFN-02172A 



APPENDIX A/AP-123 



CONTROL KEY OPERATIONS 




APPENDIX A/AP-123 



CONTROL KEY OPERATIONS 




3-172 



AFN-02172A 



APPENDIX A/AP-123 



SUPPORT SUBROUTINES 



C 



c 



CHAR-TO- MON 



3 



POINT AT DUAL-PORT 
PAGE 0 OR PAGE 1 



D8PLY— PO-PTR 



CALCULATE DISPLAY 

PAGE ADDRESS 
USING CHARACTER 
AND UNE COUNT 



SAVE ASCII CODE AND 
COLOR IN THE 
DISPLAY PAGE 




INCREMENT LINE 
COUNTER AND SET 
CHARACTER COUNT 

TO LEFT MARGIN 





SAVE CHARACTER IN 
KEY BUFFER AND 
INCREMENT KEY 
BUFFER POINTER 




DECREMENT BUFFER 

POINTER, SET 
KEYBOARD FULL FLAG, 

AND INSERT EOF 
CHARACTER IN BUFFER 



C 



KBU— RETURN 



J 



3-173 



AFN-02172A 



APPENDIX A/AP-1 23 



SUPPORT SUBROUTINES 



0 



EEP—BUF—UPDATE 



V. INHIBITED? ^ 






NO 




EEPROM ^\Y ES _ 


BUFFER FULLT^ 






NO 




SAVE ASCII 




CHARACTER IN 




EEPROM BUFFER 




AND INCREMENT 




EEPROM BUFFER 




POIN 


TER 




BUFFER 


NO _ 


^POINTER >255?/ 






r YES 




DECREMENT EEPROM 




BUFFER POINTER 




AND SET BUFFER 




FULL FLAG 










r EBU-RETURN 



c 



3-174 



AFN-02172A 



APPENDIX B/AP-123 



8089 MACRO ASSEMBLER 



IS IS- 1 I 8089 MACRO ASSEMBLER X202 ASSEMBLY OF MODULE N89 
OBJECT MODULE PLACED IN : Fl : N89. OBJ 
ASSEMBLER INVOKED BY: : F2: ASM89 : Fl : N89. SRC 



1 



2 
3 




8089 


DUMB TERMINAL PROGRAM 




4 
5 




B. K. 


MELSON 








A 
o 




STARTED: 4/30/80 






7 
8 




LAST 


CHANGE: 


8/12/80 






9 




THIS 


PROGRAM 


INITIALIZES FOUR 8275 CRT CONTROLLERS AND A 


10 




8279 


KEYBOARD CONTROLLER. 


ASCII INFORMATION FLOW MAY FOLLOW 


1 1 




THESE PATHS: 








1 2 








KEYBOARD 


TO 


0086 COMMAND INTERPRETER 


13 








KEYBOARD 


TO 


8086 EEPROM ROUTINE 


14 








KEYBOARD 


TO 


MONITOR 


1 5 








8086 


TO 


MONITOR 


16 








EEPROM 


TO 


8086 COMMAND INTERPRETER 


1 7 








EEPROM 


TO 


8086 EEPROM ROUTINE 


18 
19 








EEPROM 


TO 


MONITOR 


20 




COMMAND CODES ARE: 






21 


; K 


E 










22 








CNTRL-A 




MONITOR INHIBIT 


23 








CNTRL-B 




MONITOR UNINHIBIT 


24 








CNTRL-C 




EEPROM INHIBIT 


2*5 

c v/ 








CNTRL-D 




EEPROM UNINHIBIT 


26 








CNTRL-E 




TURN ON EEPROM BUFFER 


c / 








CNTRL-F 




n t nni aw n AAr /*% fn~"i r~y-% t"it\ 

DISPLAY PAGE 0 SELECTED 


PR 

CO 








CNTRL-G 




DISPLAY PAGE 1 SELECTED 


no 

c / 


n 


X 




CNTRL-H 




BACKSPACE (CURSOR LEFT) 


on 


v 

A 


X 




CNTRL-I 




TAB (EVERY 8 CHARACTERS) 


1 


v 
A 


X 




CNTRL-J 




LINEFEED (CURSOR DOWN) 


on 
oe 


Y 

A 






CNTRL-K 




TURN EEPROM BUFFER OFF 




V 
A 


X 




CNTRL-L 




ERASE PAGE 


d*r 


Y 

A 


X 




CNTRL-M 




CARRIAGE RETURN 


35 


x 


X 




CNTRL-N 




TURN OFF BACKGROUND/FOREGROUND* 


36 


X 


X 




CNTRL-0 




TURN ON BACKGROUND/FOREGROUND* 


37 


X 


X 




CNTRL-P 




SET COLOR TO BLACK 


38 


X 


X 




CNTRL-Q 




SET COLOR TO RED 


39 


X 


X 




CNTRL-R 




GREEN 


40 


X 


X 




CNTRL-S 




YELLOW 


41 


X 


X 




CNTRL-T 




BLUE 


42 


X 


X 




CNTRL-U 




MAGENTA 


43 ; 


X 


X 




CNTRL-V 




CYAN 


44 i 


X 


X 




CNTRL—W 




WHITE 


45 , 


0 


X 




CNTRL-X 




ABORT LINE 


46 i 


X 


X 




CNTRL-Y 




MOVE CURSOR RIGHT 


47 , 


X 


X 




CNTRL-Z 




MOVE CURSOR DOWN AND LEFT 


48 , 


X 


X 




CNTRL— 




MOVE CURSOR UP 


49 j 


X 


X 




CNTRL-\ 




HOME CURSOR 


50 i 








CNTRL-DEL 




RECALL EEPROM BUFFER 



51 



3-175 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

52 ; 

53 i THE TWO COLUMNS ASSOCIATED WITH EACH CONTROL KEY REPRESENT TH/ 

~E 

54 ; APPROPRIATE KEYBOARD AND EEPROM BUFFER ACTION CONNECTED WITH / 

-THAT 

55 ; KEY. 

56 ; ~ KEYSTROKE NOT STORED IN BUFFER 

57 } X KEYSTROKE STORED IN BUFFER 

58 ; 0 OPERATION PERFORMED ON BUFFER 

59 ; 

60 ; A CHARACTER IS STORED IN THE EEPROM BUFFER ONLY IF THE OPERAT/ 

-ION 



A i 


i WAS PERFORMED ON THE 


M 


Oc 


DUMBTERM 


SEGMENT 




AT 








64 


i 8275 REGISTERS 












AA 


CRTJREGS 


STRUC 




A7 


CRT_PARAM: 


DW 


1 


68 


CRT_COM_STAT: 


DW 


1 


69 


CRT_REOS 


ENDS 




70 








71 


; 8279 REGISTERS 




72 








73 


KYBDJREGS 


STRUC 




74 


KBDJDATA: 


DW 


1 


75 


KBD_COM_STAT: 


DW 


1 


76 


KYBDJREGS 


ENDS 




77 








78 


; 8086/808? COMMON FLAGS 


79 








80 


DP__RAM_FLAGS 


STRUC 




81 


TP LSW: 


DW * 


1 


82 


TPJ1SD: 


DW 


1 


83 


EEP INH: 


DB 


1 


84 


EEPJBUF^FULL: 


DB 


1 


85 


EEP_RECALL: 


DB 


1 


86 


COL_CH_INH: 


DB 


1 


87 


KBDJCNH: 


DB 


1 


88 


KBD BUF FULL: 


DB 


1 



89 
90 
91 
92 
93 
94 
95 
96 
97 
98 
99 
100 
101 
102 
103 
104 
105 



C0M_8086: 
COLOR: 

STRJ 3 TRJ3086: 

BACK_CQL__SW: 

M0N_INH: 

DSPLY_PG_PTR: 

&CROLL.REG: 

NEW^CHAR^FL AG : 

NEW CHAR: 



MONJ-IOM : 
MONJEND: 
MONJLMARG: 
M0N_RMARG: 



DB 
DB 
DW 
DB 
DB 
DB 
DB 



DW 
DW 
DW 
DW 



1 
1 
1 
1 
1 
1 
1 

DB 
DB 



1 
1 
1 
1 



1 
1 



3-176 



AFN-02172A 



APPENDIX B/AP-123 



LINE 


SOURCE 






1 AA 


KBDJ3UFJPTR: 


DW 


i 

X 


1 OT 


E2_M0N_INH: 


DB 




108 








1 no 

1 Ut 


DP_RAMJFLAGS 


ENDS 












11-1 
ill 


; DISPLAY CHARACTER 




1 in 
lie. 


i 






i n 
i i j 


CHAR.JDEF 


STRUC 




114 


COLOR^nuDc. 


r\r) 

ua 


1 


1 1 V? 


a /-n /"* T T AD ADLH 

ASC I I_GRAPH1 . 


Da 




11 A 
1 1 O 


GR APH_2AND3 . 


DB 




117 


GRAPH__4ANDt?. 


r\ rj 

DB 


I 


1 1 P 


CHAR^DEF 


tNUb 




1 1 Q 
117 








1 20 


; PRIVATE SOav 


FLAGS 




121 








122 


STAT_RAM_FLAGS 


STRUC 




1 PI 

1 C.J 


STACK: 


DW 


I 


1 OA 


STACK_MSD: 


DW 


1 

X 


125 




DW 


\ 


126 




DW 


I 


1 c / 


EEP_BUF_PTR : 


DW 




1 on 

1 CO 








1 39 
1 c V 


; 






1 


LINE_CNT: 


DW 




lb) Jb 


CHAR _C NT: 


DW 




1 ^p 

1 Jc 


i ' 






1 n 

1 Ju 


i 






1 


ASC 1 1 : 


DB 






ASCII_TEMP: 


DB 


I 




CURSDR_X1: 


DB 


1 

X 


1 wf / 


CURS0R_X2: 


DB 


1 


1 JO 


CURS0R_Y1: 


DB 


I 


1 O v 


CURS0R_Y2: 


DB 


1 


1 AO 
1 tu 


i 






141 


* 






1 A3 

1 tea. 


LINE.JTEMP: 


DW 


I 


1 A*3 


CHAR_TEMP: 


DW 




1 AA 


PAGE_INtfEX: 


DW 


I 


1 AS 
1 *r u7 


STAT RAM FLAGS 


ENDS 




1 to 








147 


; ADDRESS EQUATES 




1 API 
1 to 








1 AQ 

1 TV 


STAT RAM 


EQU 


OOOOOH 
uuuuwrl 


1 so 

1 v/W 


CRT1 


EQU 


OAOOOH 


1 S1 

1 v/ X 


CRT2 


EQU 


OAOOOH 


1 sc> 


CLKJEN 


EQU 


OOOOOH 


1 ST 


CRTJDATA 


EQU 


OAOOOH 


1 SA 


KYBD 


EQU 


orooow 


155 


i 






156 


i 






157 


DSPLYJ=>AGE0 


EQU 


0F8000H 


158 


DSPLY_PAGE1 


EQU 


0FC000H 


159 


C0MJ3UF 


EQU 


0FBD00H 


160 


EEPJBUF 


EQU 


0FBE00H 


161 


KEYJ3UF 


EQU 


0FBF00H 


162 


DP J=>B 


EQU 


0FFF00H 



3-177 



AFN-02172A 



APPENDIX B/AP-123 



LINE 


SOURCE 




163 






164 


i DATA /COMMAND EQUATES 


165 






166 


EOF 


EQU OFFH 


1 67 


CRT_RS7 


EQU OOOH 


168 


CRT_PARAM1 


EQU 04F4FH 


X O T 


CRTJ=>ARAM2 


EQU 06F6FH 


J, / v/ 


CRTJ=»ARAM3 


EQU 04444H 


171 


CRT_PARAM4 


EQU 00606H 


172 


CRT CURSOR 


EQU 08080H 


1 73 


CRT CNTR 


EQU OEOEOH 




STARTED ISP 


EQU 02020H 




END JD ISP PG 


EQU 15360 


1 7 A 


KBD_STR SET 


EQU 006H 


17 y 


KBDJ=»RG CLK 


EQU 034H 


1 78 


KBD_FIF0 RD 


EQU 050H 


1 79 


; ################################## 


180 


; ■*#•«• # 


I N I T I AL I Z AT I ON 


181 




182 






183 


; TURN ON THE 


CRT CHARACTER CLOCK AND RESET THE 


184 


; CRT CONTROLLERS 


185 


i 




186 


START: 




187 


MOV I , 


GB, CLK JEN 


188 


MOV I 


CGB3, 001H 


18? 


MOV I 


GB, CRT1 


190 


MOV I 


GC, CRT2 


191 


MOV I 


CGC 3 . CRT_COM_STAT, CRT _RST 


192 


MOV I 


CGB3. CRT j:OM_STAT, CRT.RST 


1 

A ~ vJ 






194 


SUPPLY THE 


FOUR PARAMETER BYTES THAT SPECIFY 


195 


; 80X48 CHARACTERS, TRANSPARENT ATTRIBUTES, AND 


196 


i A BLINKING 


UNDERLINE CURSOR 


197 






1 QR 

X 7Q 


MOV I 


CGB 3 , CRT^PARAMl 




MOV I 


CGB 3, CRT_PARAM2 




MOV I 


CGB 3, CRT _PARAM3 


201 


MOV I 


CGB 3, CRTJPARAM4 


202 


MOV I 


CGC 3, CRT_PARAM1 


203 


MOV I 


CGC 3, CRT_PARAM2 


204 


MOV I 


CGC 3, CRT_PARAM3 


205 


MOV I 


CGC 3, CRTJ>ARAM4 


206 






207 


; SET CURSOR 


TO UPPER LEFT CORNER OF MONITOR 


208 






209 


MOV I 


CGC3. CRT_COM_STAT, CRT_CURSOR 


210 


MOV I 


CGC3,0G0H 


21 1 


MOV I 


CGC 3, OOOH 


212 


MOV I 


CGB 3. CRT COM STAT, CRT CURSOR 


213 


MOV I 


CGB 3, OOOH 


214 


MOV I 


CGB 3, OOOH 


215 






216 


; SYNCHRONIZE 


8275 CLUSTER BY RESETTING COUNTERS 


217 






218 


MOV I 


CGC3 . CRT COM^STAT, CRT J2NTR 


219 


MOV I 


CGB 3. CRT_COM STAT, CRT_CNTR 



3-178 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 



220 


MOV I 


GC, STATER AM 


221 


MOVBI 


CGC 3. CURSOR XI, OOOH 


222 


MOVBI 


CGC 3. CURS0R_X2, OOOH 


223 


MOVBI 


CGC 3. CURSOR.JrM, OOOH 


224 


MOVBI 


CGC ]. CURSORJ/2, OOOH 


225 






226 


; INITIALIZE 


3279 KEYBOARD CONTROLLER 


227 






228 


MOV I 


GB, KYBD 


229 


MOV I 


CGB 3 . KBD_COM_STAT, KBD_STR J3ET 


230 


MOV I 


CGB 3 . KBD_COM_STAT, KBD_PRG_CLK 


231 


MOV I 


CGB 3. KBD_COM_STAT, KBD_FIFO_RD 


232 






233 


; INITIALIZE 


8089 FLAGS 


234 






235 


MOV I 


GC, STAT JR AM 


236 


LPDI 


GA, DP_PB 


237 


MOV I 


CGC 3. LINE__CNT, OOOH 


238 


MOV I 


CGC 3. CHAR_CNT, OOOH 


239 


i 




240 






241 


MOVBI 


CGA3 . EEP_INH, OFFH 


242 


MOVBI 


CGA3 . EEP_BUF_FULLi OOH 


243 


MOVBI 


CGA3. EEP_RECALL* OOH 


244 


MOVBI 


CGA3 . KBD_INH# OOH 


245 


MOVBI 


CGA3 . KBDJUF^FULL, OOH 


246 


MOVBI 


CGA3 . C0M_8086, OOH 


247 


MOVBI 


CGA3 . COLOR, 038H 


248 


MOVBI 


£GA3 . BACK COL SW> OOH 


249 


MOVBI 


CGA3. COL_CH_INH, OOH 


250 


MOVBI 


CGA3 . SCROLL JREQ, OOH 


251 


MOVBI 


CGA3 . DSPLYJ=>GJPTR, OOH 


252 


MOVBI 


CGA3 . MON_INH, OOH 


253 


MOVBI 


CGA3 . E2_M0N_INH, 0 


254 


MOV I 


CGA3. MON_HOM, OOH 


255 


MOV I 


CGA3. MON_ENDi 048 


256 


MOV I 


CGA3 . MON_RMARG* 080 


257 


MOV I 


CGA3 . MON_LMARG» OOH 


258 






259 


INITIALIZE 


8089 POINTER 


260 






261 


MOV I 


CGC 3. EEPJBUFJ=>TR, OOH 


262 


MOV I 


CGA3 . STR__PTR_S086, OOH 


263 


MOV I 


CGA3. KBDJ3UFJ=»TR, OOOH 


264 




265 




EXECUTIVE 


266 




267 






268 


DMA SET-UP 




269 






270 


LOAD CHANNEL CONTROL REGISTER TO SPECIFY: 


271 




MEMORY TO PORT 


272 




SYNCHRO ON DEST 


273 




GA POINTS TO SOURCE 


274 




TERMINATE ON EXT 


275 




TERMINATION OFFSET«0 


276 







3-179 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

277 MOVI GCCLKJEN 

278 MOVI CGC3,OOH i INHIBIT CHAR CLOCK 

279 ;ON 8275 TO SYNCHRONIZE 

280 MOVI GCCRT1 

281 MOVI CGC3 CRT COM STAT, START ..D ISP 

282 MOV I GC, CRT2 

283 MOVJ CGC3. CRT_COM_STAT, START.. D ISP 

284 DMA_LP: 

285 MOVI CC05120H 

286 i 

287 ; SETUP DESTINATION AND THEN 

288 i SOURCE ACCORDING TO DISPLAY PAGE 

289 i POINTER 

290 ; 

291 MOVI GB, CRTJDATA 

292 LPDI GA, DSPLY_PAGEO 

293 LPDI GC, DP_PB 

294 JZB CGC3. DSPLY_PG„. PTR, SOURCE_OK 

295 LPDI GA, DSpLY_PAGEl 

296 SOURCE JDK: 

297 JNZB CGC3. MON^INH, DMAJBYPASS > IF THE MONITOR IS INHIB/ 
-I TED 

298 i BYPASS THE DMA 

299 JNZB CGC3. E2J10N_INH, DMA_BYPASS_1 

300 MOVI GC, CLK JEN 

301 ; 

302 ; START CRT CHARACTER CLOCK AND BEGIN DMA 

303 i 

304 XFER 

305 MOVI CGC3,01H 

306 SINTR 

307 i 

308 ; SIGNAL THE 8086 THAT END OF FRAME HAS OCCURED AND THE UPDATIN/ 

~G OF THE 

309 ; INTERRUPT DRIVEN SECONDS COUNTER MAY BEGIN 

310 i 

311 i 

312 ; READ CRT STATUS REGISTERS IN ORDER TO RESET IRQ 

313 } 

314 MOVI GCCRT1 

315 MOV GA, CGC3. CRT_COM_STAT 

316 MOVI GCCRT2 

317 " MOV GB, CGC3. CRT^COM. STAT 

318 JMP DMAJBYPASS 

319 DMAJ3YPASS_1: 

320 MOVI GC, 120 

321 E2_WAITJL00P: 

322 MOVI GB, 300 

323 E2_INNER_L0QP: 

324 DEC GB 

325 JNZ GB, E2^INNER_L00P 

326 DEC GC 

327 JNZ GC, E2J4AITJL00P 

328 DMAJBYPASS: 

329 i 

330 i CHECK FOR STRING FROM 8086 

331 ; IT HAS PRIORITY OVER KEYBOARD 



3-i80 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

332 ; 

333 LPDI GC,DP_PB 

334 JNZB CGC3. C0M._8086, STRIN&_86 

335 i 

336 ; CHECK 8279 KYBD STATUS 

337 i 

338 MOV I GB, KYBD 

339 MOVB GA, CGB3. KBD_COM_STAT 

340 AND I GA, OFH 

341 LJN2 GA, READJ4YBD i KEY DOWN 

342 ; 

343 ; UPDATE THE CURSOR POSITION 

344 ; 

345 CURSORJJPDATE: 

346 LPDI GCDPJPB 

347 i 

348 ; CHECK FOR 86 COMMAND CHARACTER MODE AND PROCESS 

349 i THE NEXT BYTE 

350 JZB CGC3. C0M._8086, COM_STR„ BYPASS 

351 INC CGC3. STR_PTR_J3086 

352 JMP GET_COM 

353 COM_STRJBYPASS: 

354 MOVI GB, CRT1 

355 MOVI GC> STATJRAM 

356 MOVI CGB3. CRT COM^STAT, CRT CURSOR 

357 MOVB GA, CGC3. CHAR_CNT i SET UP FOR X POSITION 

358 MOVB CGC3. CURS0R_X1, GA ; CURSOR OUTPUT 

359 MOVB CGC3. CURS0R_X2, GA ; BY DOUBLING UP 

360 MOVB GA, CGC3. LINE_CNT 

361 MOVB CGC3. CURS0R_Y1, GA ; SAME FOR Y POSITION 

362 MOVB CGC3. CURS0R_Y2, GA 

363 MOV CGB3, £GC3. CURSOR__X 1 

364 MOV CGB3, CGC3. CURS0R_Y1 

365 MOVI GB, CRT2 ; DO IT FOR ALL 

366 MOVI CGB3. CRT_COM_STAT, CRT_CURSOR 

367 MOV CGB3, CGC3. CURS0R_X1 ; CONTROLLERS 

368 MOV CGB3, EGC3. CURS0R_Y1 

369 INTR_86: 

370 JMP DMA_LP 

371 STRING_86: 

372 MOVI CGC3. STR J=>TR_8086V OOH 

373 GET_.COM: 

374 MOV IXi CGC3. STR_PTR. 8086 

375 LPDI GB,COMJBUF 

376 ; 

377 i GET NEXT COMMAND CHARACTER FROM THE 8086 

378 i AND SAVE IT AS A KEYSTROKE 

379 i 

380 MOVB GA, CGB+IX3 

381 LPDI GC, COMJBUF s ; ***TEST CODE**** 

382 MOVB GA, £GB + 1X3 ; *** 

383 LPDI GC,DPJ=>B > *** 

384 MOVI GB, STATJRAM 

385 MOVB CGB 3. ASCII, GA 

386 i 

387 ; CHECK FOR END OF COMMAND STRING 

388 ; v 



3-131 



AFN-02172A 



APPENDIX B/AP-1 23 



LINE SOURCE 

389 MO VI MC, OFFFFH 

390 JMCNE C0B3. ASCII.. COM_CNT 

391 ; 

392 i END OF COMMAND STRING-RESET COMMAND FLAG 

393 i 

394 MOVBI CGC 3 . C0M_S086, OOH 

395 ' JMP CURSQRJJPDATE 

396 READJ4YBD: 

397 ; 

398 ; TEMPORARY GET CHAR ROUTINE 

399 i 

400 JNZB CGC 3 . KBD_INH, CURSOR. UPDATE 

401 JNZB CGC 3 . KBD.JBUF J^ULL, CURSORJJPDATE 

402 ; 

403 i IF THE KEYBOARD IS INHIBITED OR THE BUFFER FULL, 

404 i DONT READ THE 8279 

405 i 

406 MOVB GA, CGB3. KBD_DATA % 

407 NOT GA 

408 AND I GA, 007FH 

409 MOVB CGC 3. NEW_CHAR, GA 

410 MOVBI CGC 3. NEW_CHAR_FLAG, 1 

411 MOVI GB, STAT_RAM 

412 MOVB CGB3. ASCII, GA ,* SAVE KEYSTROKE 

413 COM_CNT: 

414 LPDI GB;DP_PB 

415 MOVI OC* STAT RAM 



416 i 

417 ; CHECK FOR FIRST CHARACTER AFTER CNTRL~DEL, THIS CHARACTER WILL 

418 i BE PLACED IN EEPJRECALL AND USED FOR SELECTING WHICH EEP BUFF/ 

HER 

419 i IS TO BE RECALLED 

420 i 



421 MOVB GA, CGB3. EEP_RECALL * IF MSB OF EEPJSECALL IS/ 
- SET 

422 AND I GA, 007FH ; USE PRESENT ASCII CHAR A/ 
-CTER 

423 JZ GA, NO_RECALL ; AS INDEX FOR EEPROM REC/ 
-ALL 

424 MOVB GA, CGC3. ASCII 

425 MOVB CGB 3 . EEP _R EC ALL, GA 

426 JMP CURSORJJPDATE 

427 NO_RECALL: 

428 * 

429 i CHECK FOR FIRST CHARACTER AFTER CNTRL.JE 

430 i THIS CHARACTER WILL BE PLACED IN THE 

431 ; EEPROM BUFFER AND NOT PROCESSED 

432 i 

433 ' JNZB CGB 3. EEP_INH, EEPJ3YPASS 

434 JNZ CGC 3. EEPJBUF_PTR, EEP_J3YPASS 

435 i 

436 ; INSERT ASCII CHARACTER 

437 i 

438 MOV IX, CGC3. EEP J3UF_PTR 

439 MOVB GA, CGC3. ASCII 

440 LPDI GB, EEPJBUF 

441 MOVB CGB+IX3,GA 



3-182 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 



442 
443 
444 
445 
446 
447 
448 
449 
450 
451 
452 
453 
454 
455 
456 
457 
458 
459 
460 
461 
462 
463 
464 
465 
466 
467 
468 
469 
470 
471 
472 
473 
474 
475 
476 
477 
478 
479 
480 
481 
482 
483 
484 
485 
486 
487 
488 
489 
490 
491 
492 
493 
494 
495 
496 
497 
498 



INC 
JMP 

EEP BYPASS: 



C0C3. EEP JBUF_PTR 
CURSOR UPDATE 



CHECK FOR NON CONTROL CHARACTER 

MOV I MC06000H 

LJMCNE CGC3. ASCI I , CHAR.J3UT 

#*####♦#■*•«•#**•»••* CONTROL KEY DECODE 

LOOK FOR 8086 COMMAND STRING SO CERTAIN 
COMMANDS WILL NOT BE AVAILABLE FROM 
KEYBOARD 



JZB 



CGB1.COM 8086, NOT CNtRLG 



CHECK FOR MONITOR INHIBIT 
( CNTRL-A ) 



MOV I 
JMCNE 
MOVBI 
JMP 

NOT CNTRLA: 



MC> 07F01H 

C GC 1 . ASC 1 1 , NOT_ CNTRLA 
CGB3. MON_INH, OFFH 
CURSOR UPDATE 



CHECK FOR MONITOR UN INHIBIT 
< CNTRL-B ) 



MC07F02H 

CGC3. ASCII, NOT CNTRLB 
CGB3. MON_INH, OOH 
CURSOR UPDATE 



MOV I 
JMCNE 
MOVBI 
JMP 

NOT_CNTRLB: 
NQT_CNTRLC: 
NOT CNTRLD: 



CHECK FOR SET DISPLAY PAGE 0 
< CNTRL-F) 



MOV I 
JMCNE 
MOVBI 
JMP 

NOT CNTRLF: 



MC07F06H 

C GC 3 . ASC 1 1 * NOT CNTRLF 
CGB3. DSPLY_PG_PTR, OOH 
CURSOR UPDATE 



CHECK FOR SET DISPLAY PAGE 1 
(CNTRL-G) 



MOV I 
JMCNE 
MOVBI 
JMP 

NOT CNTRLG: 



MC, 07F07H 

CGC3. ASCI I* NOT CNTRLG 
CGB3. DSPLY_PG_PTR, OFFH 
CURSOR UPDATE 



3-183 



AFN-02172A 



APPENDIX B/AP-123 



line source: 



499 i THE FOLLOWING CONTROL, COMMANDS ARE 

500 i AVAILABLE THROUGH THE 8089 KEYBOARD 

501 i 

502 i 

503 i LOOK FOR CARRIAGE RETURN 

504 i J 

505 MOV I MC, 07F0DH 

506 LJMCE C GC 3. ASCII, CHAR CR 

507 ; 

508 ; LOOK FOR BACKSPACE 

509 ; 

510 MOV I MC, 07F08H 

511 LJMCE I GC 3. ASCI I, BACK SPACE 

512 ; 

513 ; LOOK FOR COLOR CONTROL KEYS 

514 i CNTRL-P THRU CNTRL-W 

515 ; 

516 MOVI MC, 07810H 

517 LJMCE EGC 3. ASCII, COLOR KEY 

518 ; 

519 ; CHECK FOR SET BACKGROUND COLOR FLAG 

520 ; (CNTRL-N) 

521 ; 

522 MOVI MC07F0EH 

523 LJMCE CGC3. ASCII, CNTRLJM 

524 ; 

525 ; CHECK FOR SET FOREGROUND COLOR 

526 i ( CNTRL-0 ) 

527 MOVI MC, 07F0FH 

528 LJMCE CGC3. ASCII, CNTRLJ3 

529 ; 

530 i 

531 i 

532 > CHECK FOR EEPROM BUFFER RECALL 

533 > < CNTRL-DEL ) 

534 MOVI MC, 07F1FH 

535 LJMCE CGC3. ASC 1 1 , EEPJDUMP 

536 i 

537 i LOOK FOR TAB 

538 i (CNTRL-I ) 

539 i 

540 MOVI MC, 07F09H 

54 1 LJMCE C GC 3 . ASC 1 1 , CURSOR.. JAB 

542 i 

543 i LOOK FOR ERASE PAGE 

544 i (CNTRL-L) 

545 J 

546 MOVI MC, 07F0CH 

547 LJMCE CGC3. ASC 1 1 , ER ASE_P AGE 

548 i 

549 i LOOK FOR CANCEL LINE 

550 i (CNTRL-X ) 

551 i 

552 MOVI MC, 07F18H 

553 LJMCE CGC3. ASCII, CNTRLJC 



554 i 

555 > LOOK FOR HOME THE CURSOR 



3-184 



AFN-02172A 



APPENDIX B/AP-123 



LINE 
556 
557 
558 
559 
560 
561 
562 
563 
564 
565 
566 
567 
568 
569 
570 
571 
572 
573 
574 
575 
576 
577 
578 
579 
580 
581 
582 
583 
584 
585 
586 
587 
588 
589 
590 
591 
592 
593 
594 
595 
596 
597 
598 
599 
600 
601 
602 
603 
604 
605 
606 
607 
608 
609 
610 
611 
612 



SOURCE 



< CNTRL \> 

MOV I MC07F1CH 

LJMCE CGC 3. ASCII, CURSOR JHOME 

LOOK FOR UP CURSOR 

(CNTRL •'-) 

MOV I MC07F1EH 

LJMCE CGC 3. ASCII, UP_CURSOR 

LOOK FOR DOWN CURSOR 

(CNTRL J) 



MOV I 
LJMCE 



MC, 07F0AH 

CGC 1. ASCII, OWN CURSOR 



LOOK FOR RIGHT CURSOR 
( CNTRL-- Y ) 



MOV I 
LJMCE 



MC* 07F19H 

CGC 1. ASCII, RIGHT CURSOR 



LOOK FOR DOWN AND LEFT CURSOR 
(CNTRL-Z) 



MOV I 
LJMCE 



MC, 07F1AH 

CGC 3. ASCII, BACK DOWN 



i ALL OTHER KEY INPUTS ARE IGNORED 
; 

JMP CURSORJJPDATE 
i ******«**************************^ 
CONTROL SEGMENTS 



SET THE COLOR BACKGROUND/FOREGROUND* FLAG TO 
BACKGROUND (O) 



CNTRL N: 



MdVI 
LPDI 



GB, STAT_RAM 

GC, DP PB 



CHECK FOR MONITOR OR COLOR CHANGE INHIBITED 



KEEP BF: 



JNZB CGC 3. COL_CH_INH, KEEP JBF 
MOVBI CGC 1. BACK_CQL„J3W, OOH 

LJMP KEY EEP EXIT 



SET THE COLOR BACKGROUND/FOREGROUND* FLAG 
TO FOREGROUND 



CNTRL 0: 



MOV I 
LPDI 



GS, STAT_RAM 
GC, DP PB 



.3-185 



AFN-02172A 



APPENDIX B/AP-123 



LINE 


SOURCE 






613 


i CHECK . FOR MONITOR OR COLOR CHANGE INHIBITED 


614 


i 






615 


JNZB 


CGC3. COL_CH_I NH, KEEPJSF2 




616 


MOVBI 


CGC3. BACK . COL, SW, OFFH 




617 KEEPJ3F2: 




618 


LJMP 


KEY JEEP __EX I T 




619 








620 


; TURN ON THE 


EEPROM BUFFER 




621 


(CNTRL 






622 








623 


i THIS ROUTINE INITIALIZES THE EEPROM BUFFER 


624 


; POINTER 






625 








626 CNTRL E: 






627 


MOV I 


GB,STAT_RAM 




628 


LPDI 


GC, DPJPB 




629 


LJNZB 


CGC3. EEP.JBUF_FULL, CURSOR. 


.UPDATE 


630 


MOVBI 


CGC3. EEPJBUF^FULL, OOH ; 




631 


MOV I 


CGB 3 . EEP BUF PTR, OOH 




632 


MOVBI 


CGC3. EEP I NH, OOH 




633 


JMP 


CURSORJJPDATE 




634 








635 


TURN THE EEPRbM BUFFER OFF 




636 








637 CNTRLJ4: 






638 


MOV I 


GB, STAT RAM 




639 


LPDI 


GC, DP_PB 




640 


LCALL 


CGB3, KEYJBUF. UPDATE 




641 


MOVBI 


CGC3. EEPJ3UF~FULL, OFFH 




642 


MOVBI 


CGC3. EEP_INH, OFFH 




643 


MOV 


IX, CGB3. EEP JBUF^PTR 




644 


LPDI 


GA, EEPJBUF 




645 








646 


INSERT END OF FILE MARKER 




647 








648 


MOVBI 


CGA+IX3, OFFH 




649 


INC 


CGB3. EEP_BUF_PTR 




650 


JMP 


CURSOR_UPDATE 




651 i 








652 , 


DUMP EEPROM 


BUFFER 0-9 




653 i 








654 EEPJDUMP: 






655 


MOV I 


GB, STAT_RAM 




656 


LPDI 


GC, DP PB 




657 


LPDI 


GC, DP_PB 




658 


MOVBI 


CGC3 . EEP_RECALL, OFFH ; 


SET FLAG 



659 

660 
661 
662 
663 
664 
665 
666 
667 



~~UT IT 
- NEXT 
ED XIT: 



WILL BE REPLACED BY THE/ 



; ASCI I CHARACTER 



CHAR OUT: 



JMP 

r.- 

MOV I 
LCALL 



INTR_86 

GB, STAT_RAM 
CGB3, CHAR TO MON 



PASS KEYSTROKES TO 8086 



3-186 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

668 ; 

669 KEY__.EEP_.EX IT; 

670 MOV I GB,STATJRAM 

671 LCALL CGB 3, KEY JBUF_UPDATE 

672 EEP_UP_EXIT 

673 MOVI GB, STATJRAM 

674 LCALL LOB It EEP J3UF_UPDATE 

675 JMP CURSOR_UPDATE 

676 CHAR_CR: 

677 MOV I GB, STAT_RAM 

678 LCALL CGB 3 , CRJJPDATE 

679 i 

680 ; SET KEYBOARD AND EEPROM BUFFER FULL 

681 ; FLAGS IF NOT INHIBITED 

682 i 

683 MOVI GB,STAT_RAM 

684 LPDI GC,DP_PB 

685 JNZB CGC3. C0M__8086* CURSOR__UPDATE i IF IN 8086 COMM/ 
-AND 

686 i MODE, DONT ALTER 

687 i KEYBOARD STATUS 

688 MOVI GB, STATJRAM 

689 LCALL CGB 3 , KEY J3 UFJJP DATE 

690 MOVB I CGC 3 . KBD JBUF J^ULL, OFFH > ****** 

691 EEP_CHK: 

692 JMP EEPJJPJSXIT 

693 i 

694 ; ALTER BACKGROUND OR FOREGROUND COLOR ACCORDING 

695 i TO THE 3 LEAST SIGNIFICANT BITS OF THE INPUT 

696 i KEY AND THE STATUS OF THE BACKGROUND/FOREGROUND* 

697 i FLAG. 

698 i 

699 C0L0RJ4EY: 

700 MOVI GB * STATJRAM 

701 LPDI GC, DP_PB 

702 LCALL CGB 3, EEPJ3 UFJJP DATE 

703 LCALL C GB 3 , KEY J3UF JJPDATE 

704 LJNZB CGC 3 . C OL_C H„_ I NH, CURSOR JJPDATE 

705 MOVB GA, CGC 3 . BACK_COL_SW 

706 i 

707 ; CHECK B/F* FLAG 

708 ; 

709 JNZ GA, BACKGROUND 

710 MOVB GA, CGB 3. ASCI I • 

711 AND I GA, 07H 

712 MOV CGB 3. ASCII, GA 

713 MOVB GA, CGC3. COLOR 

714 AND I GA, 038H 

715 i 

716 ; OR INPUT COLOR INTO FOREGROUND SECTION OF COLOR BYTE 

717 i 

718 ORB GA, CGB3. ASCII 

719 MOVB CGC 3 . COLOR, GA 

720 JMP CURSORJJPDATE 

721 BACKGROUND: 

722 MOVB GA, CGB 3. ASCII 

723 ADD GA, CGB3. ASCII 



3-187 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

724 ADD GA, CGB 3. ASCII 

725 ADD GA, CGBIL ASCII 

726 MOVB C GB 1 . ASC 1 1 _TEMP , Q A 

727 ADD OA, CGB3. ASCII TEMP 

728 i 

729 i SHIFT INPUT COLOR OVER AND OR IT INTO THE BACKGROUND 

730 ; SECTION OF THE COLOR BYTE 

731 i 

732 AND I GA, 038H 

733 MOV COB 1. ASCII, GA 

734 MOVB GA, CGC3. COLOR 

735 AND I GA, 047H 

736 ORB GA, CGB 3. ASCII 

737 MOVB CGC3. COLOR, GA 

738 JMP CURSORJJPDATE 

739 ; 

740 ) TAB ROUTINE 

741 ; 

742 i THIS ROUTINE MOVES THE CURSOR TO THE NEXT 

743 ; COLUMN WHOSE NUMBER IS A MULTIPLE OF 8. 

744 i 

745 CURSOR_TAB: 

746 MOV I GB, STATJRAM 

747 LCALL CGB 3 , EEP J3UF JJPDATE 

748 LCALL CGB 3, KEY_BUF JJPDATE 

749 LPDI GC, DP PB 

750 ; 

751 i CHECK FOR CHARACTER COUNT BEING A 

752 i MULTIPLE OF EIGHT <3 LSB =0) 

753 ; 

754 TAB CNT: 

755 ; 

756 ; PLACE BLANK ON THE SCREEN 

757 i 

758 MOVB I CGB 3. ASCII, 020H 

759 LCALL CGB 3 , CHARJT0J10N 

760 MOV GA, CGB 3. CHAR_CNT 

761 AND I , GA, 07H 

762 LJZ GA, CURSORJJPDATE 

763 JZB CGC 3 . SCROLL _REQ, TAB . CNT 

764 JMP CURSORJJPDATE 

765 i I 

766 i ERASE PAGE ROUTINE 

767 i 

768 i THIS ROUTINE ERASES THE PAGE FROM THE CURRENT 

769 ; CURSOR POSITION. IT ENDS WITH THE CURSOR AT 

770 ; THE HOME POSITION. 

771 i 

772 i 

773 ; UP CURSOR ROUTINE 

774 i 

775 UP_CURSOR: 

776 MOVI GB, STATJRAM 

777 LPDI GC, DPJPB 

778 MOV IX, CGC 3. MON_HOM 

779 NOT IX i CHECK FOR UPPER BOUNDARY 

780 AND IX, CGB 3. LINE CNT 



3-188 



AFN-02172A 



APPENDIX B/AP-123 



LINE 
781 
782 
783 
784 
785 
786 
787 
788 
789 
790 
791 
792 
793 

794 
795 
796 
797 
798 
799 
800 
801 
802 
803 

804 
805 
806 
807 
808 
809 
810 
811 
812 
813 
814 
815 
816 

817 
818 

819 
820 
821 
822 
823 
824 
825 
826 
827 
828 
829 
830 
831 
832 
833 



SOURCE 



LJZ IX, CURSOR JJP DATE 

DEC CGB3. LINE..CNT 

JMP KEY_EEP.JEXIT 

LINE FEED (DOWN CURSOR) 



DWN_CURSOR: 
MOV I 
LPDI 
MOV 
INC 
NOT 
AND 

-OVE 

LJZ . 

INC 

JMP 



GB, STAT RAM 

GC, DP_PB 

IX, CGB3. LINE CNT 

IX 

IX 

IX, CGC3. MON_END 

IX, CURSOR. JJPDATE 
COB!. LINE_CNT 
KEY EEP EXIT 



MOVE CURSOR RIGHT 



RIOHT_CURSOR: 
MOV I 
LPDI 
MOV 

~ER 

INC 
NOT 
AND 
LJZ 
INC 
JMP 
BACKJDQWN: 

MOV I 

LPDI 

MOV 

INC 

NOT 

AND 

-OVE 

LJZ 
MOV 
-RGIN 

NOT 
AND 
LJZ 
INC 
DEC 
JMP 



GB, STAT_RAM 

GC, DP_PB 

IX, CGB3. CHAR_CNT 

IX 
IX 

IX, CGC3. MON_RMARG 
IX* CURSOR_UPDATE 
CGB3. CHAR_CNT 
KEYJEEPJEXIT 

GB, STATJRAM 

GC, DP_PB 

IX, CGB3. LINE_CNT 

IX 

IX 

IX, CGC3. MONJEND 

IX, CURSOR_UPDATE 
IX, CGC3. MONJ-MARG 

IX 

IX, CGB3. CHAR_CNT 
IX, CURSORJJPDATE 
CGB3. LINE_CNT 
CGB3. CHAR__CNT 
KEY EEP EXIT 



COMPARE PRESENT LINE 
COUNT + 1 TO BOTTOM 
MARGIN 

IF EQUAL ABORT CURSOR M/ 



MOVE OK 



i COMPARE PRESENT CHARACT/ 

; COUNT + 1 TO RIGHT 
i MARGIN 

i IF EQUAL ABORT 
i CURSOR MOVE 
i MOV OK 



COMPARE PRESENT LINE 
COUNT + 1 TO BOTTOM 
MARGIN 

IF EQUAL ABORT CURSOR M/ 



i IF CURSOR IS AT LEFT MA/ 
; ABORT CURSOR MOVE 



CANCEL THE PRESENT LINE 
CNTRLJC: 

MOV I GB, STAT JR AM 

LPDI GC, DP_PB 

MOV CGB3. CHARJDNT, CGC 3. MON .LMARG 

i ' 

; RESET THE KEYBOARP BUFFER POINTED 



3-189 



AFN-02172A 



APPENDIX B/AP-1 23 



LINE SOURCE 

834 , 

835 MOVBI CGC 3 . RBD. JBUF_FULL, OOH 

836 MOVI CGC3. KBDJBUF^PTR, OOH 

837 JMP KEY. EEP _EXIT~ 

838 ERASEJPAGE: 

839 MOV I QB> STATER AM 

840 LCALL COB 3 , EEP.JBUF..JJPDATE 

841 LCALL CGB3, KEYJBUF_ UPDATE . 

842 LPDI GC,DP_PB 

843 J 

844 ; STORE BLANKS ON THE SCREEN 

845 i 

846 MOVBI ■ CGB3. ASCII, 020H 

847 ERASE_CNT: 

848 LCALL CGB 3 , CHARJT0J10N 

849 JZB CGC3. SCROLL J*EQ, ERASE _CNT 

850 JMP CHJMTR 

851 i 

852 ; HOME THE CURSOR 

853 ; 

854 CURSORJHOME: 

855 MOVI GB,STATJRAM 

856 LCALL C GB 3 , EEP J3UFJJPDATE 

857 LCALL CGB 3 , KEY J3UF.JJPDATE 

858 CHJMTR: 

859 LPDI GC,DP__PB 

860 MOVBI CGC3. KBDJMH, OOH 

861 MOVBI CGC 3. SCROLL_REQ, OOH 

862 MOV C GB 3 . CHAR _CNT, C GC 3 . MON„ LMARG 

863 MOV ^ CGB 3 . LINE__CNT, CGC3. MON ...HOM 

864 JMP CURSORJJPDATE 

865 i 

866 i PERFORM BACK-SPACE BY DECREMENTING THE DISPLAY 

867 ; PAGE POINTER, KEYBOARD POINTER, EEPROM POINTER, 

868 ; AND CURSOR POSITION 

869 ; 

870 BACK-SPACE: 

871 MOVI GB,STAT_RAM 

872 LPDI GC,DPJ=>B 

873 MOV IX, CGC3. M0N_JJ1ARG ; IF CURSOR IS AT LEFT 

874 NOT IX ; MARGIN ABORT BACKSPACE 

875 AND IX, CGB 3. CHAR_CNT 

876 LJZ IX, CURSORJJPDATE 

877 DEC CGB 3. CHAR_CNT 

878 i 

879 > DO BACKSPACE IF MONITOR NOT INHIBITED AND CURSOR IS 

880 i NOT AT THE BEGINNING OF A LINE 

881 i 

882 KYBDJJPDATE: 

883 LJNZB CGC3. KBD_BUF_FULL, EEP_EXIT 

884 ; 

885 i IF KEY BUFFER POINTER IS ZERO, DONT BACKSPACE IT 
, 886 ; 

887 JZ CGC 3. KBDJBUFJ=>TR, EEPJEXJT 

888 DEC CGC3. KBD BUFJ=»TR 

889 EEP_EXIT: 

890 MOVI GB, STAT RAM 



3-190 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

891 JMP EEP_UP__EXIT 

892 i 

893 i SUBROUTINES 

894 ; 

895 CHAR_TO_MON. 

896 i 

897 ; SET UP DISPLAY PAGE POINTER AND INDEX 

898 ; 



899 


LPDI 


GB, DSPLYJPAGEO 




900 


LPDI 


GC, DP PB 




901 


JZ 


CGC 3 . DSPLYJ=>G„_PTR, PTRJ3K 




902 


LPDI 


GBi DSPLYJ=»AGE1 




903 








904 


COMPUTE 80XLINE_CNT 




905 








906 PTRJ3K: 






907 


MOV I 


GC> STAT_RAM 




908 


MOV 


GA, CGC 3 . LINE_CNT 




909 


ADD 


GA, CGC 3 . LINE_CNT 




910 


ADD 


GA, CGC 3 . LINE_CNT 




911 


ADD 


GA, CGC 3 . LINE_CNT 




912 


ADD 


GA, CGC 3. LINE^CNT 




913 


MOV 


CGC 3. L I NE_TEMP * GA 




914 


ADD 


GA, CGC 3. LfNE_TEMP ; 2 X 


5 


915 


MOV 


CGC 3. L I NE_TEMP , GA 




916 


ADD 


GAi CGC 3. LINE_TEMP ; 4 X 


5 


917 


MOV 


CGC 3. LINE_TEMP, GA 




918 


ADD 


£A, CGC 3. LINEJTEMP i 8 X 


5 


919 


MOV 


CGC 3. LINEJTEMP, GA 




920 


ADD 


GA, CGC 3. LINEJTEMP ; 16 X 


5 


921 








922 


MEMORY POINTER = DISPLAY PAGE POINTER + 




923 




4X(80XLINE_CNT + CHAR _C NT ) 




924 








925 


ADD 


GA, CGC 3. CHAR_CNT 




926 


MOV 


CGC 3. LINEJTEMP, GA 




927 


ADD 


GA, CGC 3. LINEJTEMP 




928 


ADD 


GA, CGC 3 . LINEJTEMP 




929 


ADD 


GA, CGC 3. LINEJTEMP 




930 


MOV 


CGC 3. PAGE_INDEX, GA 




931 


ADD 


GB, CGC 3. PAGE_INDEX 




932 








933 


SAVE ASCII 


CODE IN DISPLAY PAGE 




934 








935 


MOVB 


CGB 3 . ASCIIJ3RAPH1, CGC 3. ASCII 




936 








937 


SAVE BACKGROUND AND FOREGROUND COLOR IN 




938 


DISPLAY PAGE 




939 








940 


LPDI 


GC,DPJ=»B 




941 


MOVB 


CGB 3. C0L0RJ10DE, CGC 3. COLOR 




942 








943 


CLEAR OTHER 


2 DISPLAY PAGE BYTES 




944 








945 


MOVB I 


CGB 3. GRAPH_2AND3, OOH 




946 


MOVB I 


CGB 3. GRAPH_4AND5> OOH 




947 




( x 





3-191 



AFN-02172A 



APPENDIX B/AP-123 



LINE SOURCE 

948 i INCREMENT X CURSOR POSITION AND CHARACTER POINTER. 

949 i CHECK FOR RIGHT MARGIN OVERRUN 

950 ; 

951 MOVI GB, STAT_RAM 

952 INC CGB3. CHAR^CNT 

953 MOV CGB 3. CHAR_TEMP, CGB 3. CHAR, CNT 

954 NOT CGB 3. CHAR^TEMP 

955 MOV GA, CGC3. MON_RMARG 

956 AND GA, C GB 3 . CHARJTEMP 

957 JNZ GA, M0N_UPDATE FIN 

958 CRJJPDATE: 

959 i IF RIGHT MARGIN WAS EXCEEDED, MOVE CHARACTER COUNT 

960 i TO LEFT MARGIN AND INCREMENT LINE COUNT AND Y CURSOR 

961 ) POSITION 

962 LPDI GC, DP J=»B 

963 MOVI GB, STAT_RAM 

964 I NC CGB3. LI NE_CNT 

965 MOV CGB3. CHAR_CNT, CGC3. MON LMARG 

966 ; 

967 * CHECK IF LINE COUNT WENT PAST BOTTOM OF SCREEN 

968 ; 

969 MOV CGB 3. LINEJTEMP, CGB 3. LINE^ CNT 

970 NOT CGB 3. LINE_TEMP 

971 MOV GA, CGB 3 . LINEJTEMP 

972 AND GA, CGC3. MONJEND 

973 JNZ GA, MON_UPDATE_ FIN 

974 > 

975 ; LINE COUNT EXCEEDED BOTTOM MARGIN- 

976 i SET SCROLL FLAG 

977 ; AND KEYBOARD INHIBIT AND DECREMENT LINE COUNT 

978 ; 

979 MOVBI CGC3. SCROLL_REQ, OFFH 

980 MOVBI CGC3. KBD J.UH, OFFH ; **** 

981 DEC CGB 3. LINE^CNT 

982 MON_UPDATE_F I N : 

983 s 

984 i RETURN TO CALLING ROUTINE 

985 ; 

986 MOVI GB,STAT_RAM 

987 LPDI GC, DP_PB 

988 MOVP TP, CGB 3 

989 * 

990 ; KEYBOARD BUFFER SUBROUTINE 

991 ; 

992 i TRANSFER THE ASCII CHARACTERS OBTAINED FROM THg 

993 i 8279 CONTROLLER INTO A BUFFER FOR LATER 

994 i PROCESSING BY THE 8086. 

995 i 

996 KEYJBUFJJPDATE: 

997 LPDI GC, DP_PB * 

998 MOVI GB, STATJRAM 

999 ; 

1000 ; BYPASS IF BUFFER FULL 

1001 i 

1002 JNZB CGC 3 . KBD J3UF_FULL, KBU RETURN 

1003 i 

1004 i BYPASS IF 8086 COMMAND MODE 



3-192 



AFN-02172A 



APPENDIX B/AP-123 



LINE 

1005 

1006 

1007 

1008. 

1009 

1010 

1011 

1012 

1013 

1014 

1015 

1016 

1017 

1018 

1019 

1020 

1021 

1022 

1023 

1024 

1025 

1026 

1027 

1028 

1029 

1030 

1031 

1032 

1033 

1034 

1035 

1036 

1037 

1038 

1039 

1040 

1041 

1042 

1043 

1044 

1045 

1046 

1047 

1048 

1049 

1050 

1051 

1052 

1053 

1054 

1055 

1056 

1057 



SOURCE 

JNZB IGC1 C0li._8086; KBU ^RETURN 
XFER THE CHARACTER 

i 

MOV IX* CGC 3. KBD ,BUF. PTR 

LPDI GA# KEY J3UF 

MOVB CGA+I X 3 > CGB3. ASCII 

INC t GC 3 . KBD J3UF_PTR 

MOV GA, CGC 3. KBDjBUF PTR 

AND I GA, OFFOOH 

JZ GA, KBUJ3ETURN 

POINTER OVERRUN-SET BUFFER FULL FLAG 



DEC 
MOVB I 
MOVB I 
KBU_RETURN: 

MOVP 



CGC 3. KBDJ3UF.J=»TR 

CGC 3. KBDJBUF^FULL, OFFH 

CGA+I X 3 , OFFH 



SET END OF BUFFER MARKER 



TP, CGB 3 
EEPROM BUFFER SUBROUTINE 

THIS ROUTINE TRANSFERS THE ASCII CHARACTERS OBTAINED 
FROM THE 8279 CONTROLLER INTO THE DUAL PORT EEPROM BUFFER 



EEP JB UF_UP DATE : 
MOV I 
LPDI 



GB, STATJRAM 

GC, DP PB 



CHECK FOR BUFFER FULL FLAG OR EEPROM INHIBITED 

JNZB CGC 3. EEP_INH, EBU_RETURN 
JNZB CGC 3. EEP „JB UFJFULL , EBU. RETURN 

XFER THE CHARACTER 

MOV IX, CGB 3. EEPJBUF PTR 

LPDI GA, EEP_J3UF 

MOVB CGA+I X 3 , CGB 3. ASCII 

INC CGB 3. EEP_J3UFJPTR 

MOV GA, CGB3. EEPJBUF PTR 

AND I GA, OFFOOH 

JZ GAi EBU_RETURN 

POINTER OVERRUN-SET BUFFER FULL FLAG 



DEC 
MOVB I 
EBUJRETURN; 

MOVP 

DUMBTERM 



CGB 3. EEPJBUFJPTR 

CGC 3. EEP JBUF__FULL, OFFH 

TP, CGB 3 

ENDS 

END 



3-193 



AFN-02172A 



intrJ APPLICATION AP-143 

^ NOTE 



March 1982 



44/ 



©INTEL CORPORATION, 1982 



3-194 



Order Number. 210383 : 001 



AP-143 



INTRODUCTION 

As the performance of microcomputers has improved, 
the types of functions performed by these microcom- 
puters have grown. One application filled by these 
machines has been to perform typical "adding 
machine* ' type calculations, balancing ledgers, etc. This 
type of machine has come to be called a "small business 
computer.' * To be a true business computer, however, 
the types of operations performed by these machines 
need to be expanded beyond simple "balance the 
books" types of operations. There are many algorithms 
that have been impractical for these small business com- 
puters because the number of calculations required by 
the algorithms and the performance available from 
these machines did not make them feasible. Such opera- 
tions were available only on large mainframe or mini- 
computers. With the introduction of the iAPX 86/20, a 
microcomputer can finally perform these types of 
calculations at a cost level appropriate to small business 
computers. 

The iAPX 86/20 features the Intel 8086 with the 8087 
numerics co-processor. This combination allows for 
high-performance, high-precision numeric calculations. 
Many types of operations require this performance to 
provide accurate results in a reasonable amount of time. 
This increased performance will also be particularly 
welcome in the interactive user environment, typically 
found in small business computers. It is very frustrating 
to wait many seconds or even minutes after hitting 
"return" for the computer to generate results. 

In general, if there are many methods to solving a 
business computer problem, the method requiring the 
largest number or calculations will provide the best 
results. In many applications, approximate methods 
have been used because the speed of the hardware (or 
the cost of the computer time) did not allow a more ex- 
act method to be used. Because of the high performance 
of the iAPX 86/20, these numeric intensive methods 
may now be used in small business computer software. 

The types of calculations demonstrated in this note are: 

• Interest and Annuities. These calculations require 
the use of floating point multiplication, division, 
exponentiation and logarithms. These calculations 
are used to determine the present or future value 
of certain types of funds. 

• Restocking. These iterative calculations require 
extensive use of floating point multiplication and 
division. They are used to determine the optimum 
restocking times for a given item when the set-up 
charges, holding costs and demand for the item 
are known or can be estimated. 



• Linear Programming. These calculations require 
extensive use of floating point multiplication and 
division. One of many applications for linear pro- 
gramming is the determination of optimum pro- 
duction quantities of diverse products when the 
quantities of their various constituents are both 
overlapping and limited. 

iAPX 86/20 HARDWARE OVERVIEW 

The iAPX 86/20 is a 16-bit microprocessor based on the 
Intel 8086 CPU. The 8086 CPU features eight internal 
general-purpose 16-bit registers, memory segmentation, 
and many other features allowing for efficient code 
generation from high-level language compilers. When 
augmented with the 8087, it becomes a vehicle for high- 
speed numerics processing. The 8087 adds eight 80-bit 
internal floating point registers, and a floating point 
arithmetic logic unit (ALU) which can speed floating 
point operations up to 100 times over other software 
floating point simulators or emulators. 

The 8086 and 8087 execute a single instruction stream. 
The 8087 monitors this stream for numeric instructions. 
When a numeric instruction is decoded, the 8086 
generates any needed memory addresses for the 8087. 
The 8087 then begins instruction execution automat- 
ically. No other software interface is required, unlike 
other floating point processors currently available 
where, for example, the main processor must explicitly 
write the floating point numbers and commands into the 
floating point unit. The 8086 then continues to execute 
non-numeric instructions until another 8087 instruction 
is encountered, whereupon it must wait for the 8087 to 
complete the previous numeric instruction. The over- 
lapped 8086 and 8087 processing is known as concur- 
rency. Under ideal conditions, it effectively doubles the 
throughput of the processor. However, even when a 
steady stream of numeric instructions is being executed 
(meaning there is no concurrency), the numeric per- 
formance of the 8087 ALU is much greater than that of 
the 8086 alone. 

The hardware interface between the 8086 and the 8087 is 
equally simple. Hardware handshaking is performed 
through two sets of pins. The RQ/GT pin is used when 
the 8087 needs to transfer operands, status, or control 
information to or from memory. Because the 8087 can 
transfer information to and from memory independent 
of the 8086, it must be able to become the "bus 
master," that is, the processor with read and write con- 
trol of all the address, data and status lines. Only one 
unit is permitted to have control of these lines at a time; 
chaos would exist otherwise, like four people talking at 
once with each trying to understand the others. 



3-195 



AFN-02184A 



AP-143 



The TEST/ BUSY pin is used to manage the concur- 
rency mentioned above. Whenever the 8087 is executing 
an instruction, it sets the BUSY pin on high. A single 
8086 instruction (the WAIT instruction) tests the state 
of this pin. If this pin is high, the WAIT instruction will 
cause the 8086 to wait until the pin is returned to low. 
Therefore, to insure that the 8086 does not attempt to 
fetch a numeric instruction while the 8087 is still work- 
ing on a previous numeric instruction, the WAIT in- 
struction needs to be executed. The 8086/87/88 
assembler, in addition to all Intel compilers, auto- 
matically inserts this WAIT instruction before most 
numeric instructions. Software polling can be used to 
determine the state of the BUSY pin if hardware hand- 
shaking is not desired. 

Most other lines (address, status, etc.) are connected 
directly in parallel between the 8086 and the 8087. An 
exception to this is the 8087 interrupt pin which must be 
routed to an external interrupt controller. An example 
iAPX 86/20 system is shown in Figure 1 . A more com- 
plete discussion of both the handshaking protocol be- 
tween the 8086 and the 8087 and the internal operation 
of the 8087 can be found in the application note Getting 
Started With the Numeric Data Processor, AP-113 by 
Bill Rash, or by consulting the numerics section of the 
July 1981 iAPX 86,88 Users Manual. 



In addition to the 8087 hardware, the 8086 is also sup- 
ported by Intel compilers for both Pascal and FOR- 
TRAN, Code generated by these compilers can easily be 
combined with code generated from the other compiler, 
from the Intel 8086/87/88 macro assembler or the Intel 
PL/M compiler. In addition, these compilers produce 
in line code for the 8087 when numeric operations are 
required. By producing in line code rather than calls to 
floating point routines, the software overhead of an un- 
necessary procedure call and return is eliminated. The 
combination of both hardware co-processors and soft- 
ware support for the iAPX 86/20 pfovides for greater 
performance of both the end product, and its develop- 
ment effort. 

ROUTINES IMPLEMENTED 

All routines implemented in this application note were 
written entirely in either Pascal 86 or FORTRAN 86. In 
addition, a FORTRAN program available from IMSL 1 
for use in solving linear programs was used. In each 



IMSL, Inc., Sixth Floor-NBC Building, 7500 Bellaire 
Boulevard, Houston, Texas, 77036. (713) 722-1927. 



8259A 
PIC 



L 



CLOCK 
GENERATOR 



J 



8086/8088 
CLK CPU 



RQ/GT1 

QS0 QS1 TEST 



I i ♦ 



QS0 QS1 BUSY 
RQ/GT0 



ri v 8087 
CLK NDP 



7> 



[~ RQ/GT "~l 



CLK 



8089 
IOP 



8086 
FAMILY 
BUS 
INTERFACE 
COMPONENTS 



SYSTEM BUS ^ 



Figure 1. Typical 86/20 System 



3-196 



AFN-02184A 



AP-143 



case, the routine was executed using a 5 MHz iAPX 
86/20 on an iSBC86/12 board contained within an Intel 
Intellec™ Series III development system. The programs 
can be executed on any iAPX 86/20 (or iAPX 88/20) 
with sufficient memory, however. In general, the 
memory requirements for the programs were not 
substantial. Source listings for all routines written for 
this note are located in the appendix. 

All routines were run using both the 8087 and the 8087 
software emulator. The 8087 software emulator is a 
software package exactly emulating the internal opera- 
tion of the 80$7 using 8086 instructions. When the 
emulator is used, an 8087 is not required. The emulator 
is a software product available from Intel as part of the 
8087 support library. The performance of the 8087 
hardware is much better than that of the software 
emulator, as one would expect from a specialized floating 
point unit. 

In some routines, values are quoted for the various data 
formats supported by the 8087. For real numbers, these 
formats are short real, long real, and temporary real. 
The differences among the three are in the number of 
bits allocated to represent a given floating point 
number. 

In all real numbers, the data is split into three fields: the 
sign bit, the exponent field and the mantissa field. The 
sign bit indicates whether the number is positive or 
negative. The exponent and mantissa together provide 
the value of the number: the exponent providing the 
power of two of the number, and the mantissa pro- 
viding the "normalized" value of the number. A * 'nor- 
malized' * number is one which always lies within a cer- 
tain range. By dividing a number by a certain power of 
two, most numbers can be made to lie between the 



numbers 1 and 2. The power of two by which the 
number must be divided to fit within this range is the 
exponent of the number, and the result of this division is 
the mantissa. This type of operation will not work on all 
numbers (for example, no matter what one divides zero 
by, the result is always zero), so the number system must 
allow for these certain "special cases." 

As the size of the exponent grows, the range of numbers 
representable also grows, that is, larger and smaller 
numbers may be represented. As the size of the mantissa 
grows, the resolution of the points within this range 
grows. This means the distance between any two adja- 
cent numbers decreases, or, to put it another way, finer 
detail may be represented. Short real numbers provide 
eight exponent bits and 23 significand or mantissa bits. 
Long real numbers provide 11 exponent bits and 52 
significand bits. Temporary real numbers provide 15 ex- 
ponent bits and 63 significand bits. These data formats 
are shown in Figure 2. Thus, of the three data, formats 
implemented, short real provides the least amount of 
precision, while temporary real provides the greatest 
amount of precision. These levels of precision represent 
only the external mode of storage for the numbers; in- 
side the 8087 all numbers are represented in temporary 
real precision. Numbers are automatically converted 
into the temporary real precision when they are loaded 
into the 8087. In addition to real format numbers, the 
8087 automatically converts to and from external 
variables stored as 16, 32 or 64-bit integers, or 80-bit 
binary coded decimal (BCD) numbers. 

Memory requirements also increase as precision in- 
creases. Whereas a short real number requires only four 
bytes of storage (32 bits), a long real number requires 
eight bytes (64 bits) and a temporary real number 10 



SHORT REAL 



TEMPORARY REAL 



BIASED 
EXPONENT 



3\ 

> — 14 



LONG REAL S 



BIASED 
EXPONENT 



BIASED 
EXPONENT 



LlL 



64 63 4 



NOTES: 

S = SIGN BIT (0 - POSITIVE, 1 « NEGATIVE) 
A = POSITION OF IMPLICIT BINARY POINT 

I = INTEGER BIT OF SIGNIFICAND; STORED IN TEMPORARY REAL, 

IMPLICIT IN SHORT AND LONG REAL 
EXPONENT BIAS (NORMALIZED VALUES): 

SHORT REAL: 127 (7FH) 

LONG REAL: 1023 (3FFH) 

TEMPORARY REAL: 16383 (3FFFH) 



Figure 2. Data Formats 



3-197 



AFN-02184A 



AP-143 



bytes (80 bits)! In many floating point processors, pro- 
cessing time also increases dramatically as precision is 
increased, making this another consideration in the 
choice of precision to be used by a routine. The dif- 
ferences in 8087 processing time among short real, long 
real and temporary real numbers is relatively insignifi- 
cant, however. This makes the choice of which precision 
to use in an iAPX 86/20 system a function only of 
memory limitations and precision requirements. 

Interest 

Routines were written to calculate the final value of a 
fund when given the annual interest and the present 
value. Although the calculations required to generate in- 
dividual interest values are rather short, the additional 
precision of the iAPX 86/20 can be used to generate 
better results. In addition, if a large number of interest 
calculations are to be performed (or if an interest rate 
type of calculation is used as part of an iterative model), 
the speed of the single interest rate calculation is impor- 
tant, as it will be performed very many times. 

It is assumed that the interest will be compounded daily, 
which requires the calculation of the yearly effective 
rate. This value, which is the equivalent annual interest 
rate when interest is compounded daily, is determined 
by the following formula: 

yer = (\+( 1 )) np -l 

np 

Where: 

• yer is the yearly effective rate 

• i is the annual interest rate 

• np is the number of compounding periods per 
annum 

Once the yer is determined, the final value of the fund 
can be determined by: 

/v = (l + yer)*pv 

Where: 

• pv is the present value 

• fv is the future value 

Results were obtained using short real, long real, and 
temporary real precision numbers when 

• iris set to 10% (0.1) 

• np is set to 365 (for daily compounding) 

• pv is set to $2,000,000 

The results are shown in Table 1 . 



Table 1. Interest Rate Calculation Results 





yer 


Final value 


Short real 
Long real 
Temp real 


10.514% 
10.516% 
10.516% 


$2,210,287.50 
$2,210,311.57 
$2,210,311.57 



The times required to calculate these results using FOR- 
TRAN 86 with both the 8087 and the 8087 emulator are 
shown in Table 2. 



Table 2. Interest Rate Calculation Times 





8087 


Emulator 


Short real 
Long real 
Temp real 


1.052 ms 
1.058 ms 
1.041 ms 


100.4 ms 

100.7 ms 

100.8 ms 



The difference in the final value between the short real 
and long real precision in this simple calculation is 
$24.07. Although the difference between short and long 
real precision results shown here is small, this difference 
would be signficant if the principal was larger, or if the 
period over which the interest was calculated was longer 
than a single year. Hence, the long real precision 
capability of the 8087 can provide most accurate results. 
Indeed, since the error calculated between the long real 
precision and temporary real precision results is in the 
thousandths of cents, the long real results are exactly 
correct, to the penny. Note that temporary real format 
allows for approximately 18 decimal digits of precision 
and the full precision of the numbers used in the calcula- 
tion is not printed in the above table. 

Annuities 

Values for a frequently used type of annuity were 
calculated, using routines written in both FORTRAN 
and Pascal. An annuity is a type of fund which gathers 
interest at the same time the principal is changing. A 
mortgage is a^type of annuity in which the principal is 
decreasing, whereas "the sinking fund*' implemented 
hefe is a type of annuity in which the principal is 
increasing. In both cases, the interest is added to the 
principal. 

THE SINKING FUND 

The "sinking fund" could be characterized by an in- 
dividual retirement account (IRA). In this fund, a fixed 
amount is placed in a savings fund each period. This 
fund also earns a certain amount of interest per period. 
The problem, then, is to calculate the final value of the 



3-198 



AFN-02184A 



AP-143 



fund (after a certain number of periods). The example 
given calculates the value after 20 years of a fund in 
which payments of $1000 are made each month. The 
annual interest rate is given at 12% (0.12), but the in- 
terest is compounded daily. 

The first step in solving the problem is to determine the 
interest rate per month. This is done in a similar manner 
to the way the effective annual rate is calculated; 
however, the number of compounding periods is set to 
the number of days in a month, rather than the number 
of days in a year. Once this is done, the final value of 
the annuity is determined by: 



/v = pmt*- 



((l + /rp)^-l) 
irp 



Where: 

• fv is the final value 

• pmt is the amount placed in the fund each period 

• irp is the interest rate per period 

• np is the number of periods 

The short, long and temporary real precision results are 
shown in Table 3. 

Table 3. Annuity Calculation Results 





Tot Contrib 


Final value 


Rate/period 


Short 
Long 
Temp 


$240,000 
$240,000 
$240,000 


$997,103.25 
$997,048.51 
$997,046.51 


1.005% 
1.005% 
1.005% 



The times required to calculate these results using FOR- 
TRAN 86 with both the 8087 and, the 8087 emulator are 
shown in Table 4. Notice that although the most signifi- 
cant four digits of the interest rates per period shown 
are the same, the final value using short real precision 
calculations is inaccurate by $56.74 compared to the 
final value using long or temporary real calculations. 

Table 4. Annuity Calculation Times 





8087 


Emulator 


Short real 
Long real 
Temp real 


2.121 ms 
2.139 ms 
2.106 ms 


222 ms 
229 ms 
232 ms 



Restocking Algorithms 

A restocking algorithm determines when a company 
should replenish its stock of raw goods which make up 
its products. A restocking algorithm can be used to 
determine the restocking pattern if: 



• the demand for the given product can be predicted 

• carrying costs from month to month are known 
and fixed 

• no shortages are allowed 

• lead times are known and fixed 

There are three methods commonly used to determine 
the restocking pattern: 

1) the Fixed Economic Order Quantity (EOQ) 

2) the Silver-Meal heuristic 

3) the Wagner-Whitin method 

Of the three, the Wagner-Whitin method is guaranteed 
to provide the optional restocking pattern, while the 
Silver-Meal heuristic may provide a good approxima- 
tion to this pattern. The fixed Economic Order Quantity 
will not provide good results when the demand pattern 
is highly variable. Both the Wagner-Whitin method and 
the Silver-Meal heuristic are iterative methods in which 
many options are evaluated before the final restocking 
pattern is determined. 

THE FIXED ECONOMIC ORDER QUANTITY 

The simple Economic Order Quantity method may be 
used to select the number of items to be restocked at a 
time if the demand is constant. This number is deter- 
mined by: 



EQU- 



2AD 



Where: 

• A is the set-up cost 

• D is the average demand for the period 

• v is the variable demand cost per item 

• r is the holding cost per item 

As this method does not provide for period to period 
variability in demand, if this demand is variable, the 
performance of the method will obviously suffer. Its 
only advantage is simplicity. 

THE SILVER-MEAL HEURISTIC 

The Silver-Meal heuristic will provide an approximation 
to the optimal restocking pattern determined by the 
Wagner-Whitin method. It has been used rather than 
the Wagner-Whitin in application where better results 
were required than those supplied by the EOQ method, 
but where the available computing resources did not 
allow the use of the Wagner-Whitin method. This 



3-199 



AFN-02184A 



AP-143 



method begins with the first month to be considered, 
then calculates the total replenishment and holding costs 
for this month, and a certain number of following 
months. As the number of months increases, the set-up 
charge per unit will decrease as it is distributed over 
more units. Also, however, as the number of units in- 
creases, the holding costs will increase. At a certain 
point, the holding costs will begin to increase at a 
greater rate than the set-up cost per unit falls. At this 
point, a "local minimum' * of the replenishment cost 
function will have been realized. The heuristic stops 
here, and begins the process again with the following 
month until all the months of the period have been con- 
sidered. This method may not provide the optimal solu- 
tion, since it provides only a local minimum, rather than 
a global minimum. The cost function is not guaranteed 
to continue to rise once it has begun to rise. This means 
that the restocking cost may actually fall to a lower level 
after an initial rise. This method requires much fewer 
cost calculations than the Wagner-Whitin method, 
however. 

THE WAGNER-WHITIN METHOD 

The Wagner-Whitin method is the most computationally 
intensive method to be discussed. It also is guaranteed 
to produce the optimal results. It is an application of 
"dynamic programming." It starts with the last month 
of the period, determining in inverse order the optimal 
replenishment pattern for the given month if the inven- 
tory is assumed zero at the start of the month. It does 
this by calculating the. replenishment cost for the given 
month and a number of subsequent months along with 
the holding costs for the stock replenished in the given 
month but carried over. The replenishment cost is the 
sum of the set-up charges and the per unit cost times the 
number of units acquired. The holding cost is the 
number of units held but not consumed in a given 
month. The total stocking costs for this option can then 
be determined by adding the replenishment cost, the 
holding cost and the optimal restocking cost for the 
month following the last one restocked in this iteration 
(since we have started from the last month of the period, 
the optimal restocking cost has already been determined 
for all months following the month being considered). 
The optimal restocking cost for the last month of the 
period is the restocking cost for that month alone. For 
example, if we are trying to determine the optimal 
restocking pattern from January through December of a 
year, the determination of the optimal restocking pat- 
tern for June might begin like this: 

1) Determining restocking cost (startup cost, per part 
cost, etc.) for June alone. 

2) Determine the holding costs (if June alone is being 
restocked, the holding cost will be zero). 



3) Determine the total cost of this option. This will be 
the restocking cost determined in (1) added to the 
holding costs determined in (2) added to the op- 
timal restocking cost from zero initial inventory 
determined previously (using this algorithm) for 
July. 

4) Loop back to (1). However this time, restock for 
June and July, calculate the holding cost for the 
July stock, and use the optimal restocking cost 
from zero initial inventory for August. 

This will continue until starting with June, requirements 
for the balance of the year are being restocked. As the 
algorithm continues, the cost of each new restocking 
period (that month and the number of months following 
it being restocked) for a particular month is compared 
with a previously determined minimum cost. If it is less, 
a new minimum cost has been determined, and this 
restocking pattern will replace the qld one as the optimal 
restocking pattern for the month. As should be ap- 
parent, a "horizon" in which the stock will be known to 
go to zero must be determined , in order for this 
algorithm to be used. While this may at first seem 
unrealistic, one can see that in any month where the de- 
mand for the product is relatively high, the stock will be 
allowed to go to zero, as the holding cost to that month 
will surpass the benefit, in the restocking cost if the re- 
quirements were restocked in the previous month. 

OVERALL PERFORMANCE CONSIDERATIONS 

Generally, the better an algorithm is in determining an 
objective function, the greater the computer perform- 
ance required to execute the algorithm. This is true here, 
with the most numeric intensive solution guaranteed to 
realize the optimal solution to the problem, whereas the 
simpler solutions will only provide approximations to 
this solution. A more complete explanation of these 
three methods can be found in Peterson and Silver 2 . 

EXAMPLE RESTOCKING PROBLEM 

Routines were written in Pascal to show possible im- 
plementations of the Wagner-Whitin and Silver-Meal 
heuristic. The EOQ method's results were solved by 
hand and programmable calculator. The following 
example was used to demonstrate the results of these 
methods in solving a general stock management 
problem: 

A company manufactures video games in 
which a ROM programmed microcomputer 

2 J ' 

Peterson, Rein, and Edward A. Silver, Decision Systems For 
Inventory Management And Production Planning, John 
Wiley & Sons, New York, 1979, pp 308-321 . 



3-200 



AFN-02184A 



AP-143 



is used. The manufacturer from which the 
company buys this microcomputer has an in- 
itial ROM set-up charge of $3000, with the 
cost per part varying from $20 in quantities 
of less than 500, $17.50 in quantities from 
500 to 5000, and $15 in larger quantities. The 
holding cost is determined to be $0.40 per 
part. The company barely missed the 
Christmas rush with its introduction, but has 
determined that the monthly demand for the 
next two years will be: 



Month 


Demand 


Month Demand 


January 


500 


July 3500 


February 


1500 


August 2500 


March 


2500 


September 5000 


April 


2000 


October 7500 


May 


2000 


November 9500 


June 


1000 


December 10000 



How should the company restock the 
microcomputers? 

The first problem that must be solved (when using the 
Wagner-Whitin method) is the horizon to which the 
stock will be replenished. The criterion to be used is that 
the final month should be a month in which the demand 
in the subsequent month is relatively high. Choosing 
December as the final month would not produce the 
best results, as the requirements for January are low. 
Looking at the demand function, it can be seen that the 
requirements for September are relatively high, so 
August would be a good choice as the horizon month. It 
is assumed that the demand for the second year will be 
similar to the demand predicted for the first year. This 
allows extending the period of calculation beyond the 
first year up to the chosen horizon month. Given the 
total demand function, the part cost, the holding cost, 
and the startup cost, the problem may be plugged into 
the Wagner-Whitin, Silver-Meal and Economic Order 
Quantity methods, and the results calculated. 

Using the EOQ with this demand function yields: 

• D is 3150 

• A is 3000 

• v is $15.00 

• r is 0.0229 



This leads to an EOQ of 7418. 

The results obtained from the Wagner-Whitin method, 
the Silver-Meal heuristic and the EOQ are shown in 
Table 5. The performance difference between the 
methods is apparent. Although using the Silver-Meal^ 
heuristic would save the business $12,949 over using the 
EOQ method, using the Wagner-Whitin method would 
save the business almost $25,000 over using the EOQ 
(surely below the cost of a small business computer!). 
The effect on the performance of the Silver-Meal 
heuristic of choosing a local minimum rather than a 
global minimum can be seen especially in the first few 
months in which it replenishes stock 5 times vs. 3 times 
for the Wagner-Whitin method. It should also be noted 
that the execution time of the Silver-Meal heuristic using 
the emulator is still greater than the execution time of 
the Wagner-Whitin method when the 8087 is used (and 
the execution time of the EOQ on the hand calculator 
was much greater than the execution time of either of 
the two iAPX 86/20 programs!). These results are also 
interesting when one realizes that until now the 
Economic Order Quantity method has been the most 
commonly used method of scheduling stocking intervals. 

Linear Programming 

Linear programming methods are very powerful ways 
of finding the optimal solution to operations problems. 
For example, if a number of different products can be 
made from a combination of limited resources as ex- 
pressed by a set of equations, a linear program can be 
set up to determine the optimal number of each end 
product to make in order that a certain objective func- 
tion is maximized. This objective function can be prac- 
tically anything if it is a linear function— for example, 
insuring that profit is maximized, that the use of a cer- 
tain facility is maximized, that shipping costs are 
minimized, etc. Various software packages are available 
on the market to solve linear programs. The package 
which was used in this example consisted of a set of 
FORTRAN subroutines available from IMSL 3 . To use 
the routines a FORTRAN program is written to set up 
the appropriate input arrays and call the routine. They 
could very easily be integrated into a friendly interactive 
user environment, where the increased performance of 
the 8087 would be especially apparent and welcomed. 



3 IMSL, Inc. 



3-201 



AFN-02184A 



AP-143 



Table 5. Restocking Algorithm Results 



Wagner-Whitln Method 


Silver-Meal Heuristic 


Economic Order Quantity 


momn 


raumDsr 


upiirnai 


iMumoer 


upnmai 


FMurnDBr 


upiimai 




to Restock 


Cost 


to Restock 


Cost 


to Restock 


Cost 


1 


6500 


$985,200 


500 


$996,600 


7418 


$1,009,549 


2 


* 




1500 


$984,850 






3 


* 




7500 


$995,600 


♦ 




4 






* 




* 




5 


6500 


$879,700 


* 
* 




7418 


$888,810 


6 

7 


* 




6000 


$836,500 


♦ 




8 


7500 


$776,000 


* 




7418 


$769,137 


9 






5000 


$742,500 ^ 


* 




10 


7500 


$658,500 


7500 


$664,500 


7418 


$651,464 


11 


9500 


$543,000 


9500 


$549,000 


14836 


$536,525 


12 


12000 


$397,500 


19500 


$403,500 


7418 


$308,182 


13 


* 












14 


* 




* 




* 




15 


7500 


$213,100 






7418 


$189,600 


16 


* 




* 




* 




17 


* 




*, 




* 




18 


* 




* 




* 




19 


6000 


$94,000 


6000 


$94,000 


3656 


$67,980 


20 


* 




* 




* 




Total Hold Costs: 


$16,200 




$19,600 




$31,409 


Replenishment Costs: 


$24,000 




$27,000 




$24,000 


Times Replenished: 


8 




9 




8 


Total Cost: 




$985,200 




$996,600 




$1,009,549 


Time to calculate above values: 










Using 8087: 


310 ms 




20 ms 






Using emulator: 22.98 seconds 




1.91 seconds 







THE SIMPLEX METHOD 

The simplex method is an algorithm which may be used 
to solve linear programs. The problem is specified to the 
routine as an objective function (of a certain number of 
* 'products'') and a set of constraints on the constituents 
of these products. The objective function specifies 
exactly how the products are combined to derive the 
objective function. The constraints specify how each of 
the constituents are combined to make up each of the 
products, and also specify the limits imposed on these 
various constituents. 

The set of constraints is usually set up as a two- 
dimensional matrix, while the objective function is set 
up as a vector. The combination of the objective func- 
tion and the set of constraining equations is known as 
the input tableau. The constraining equations may have 
both inequality relations (we must use less than 1000 
eggs) and equality relations (we must use exactly 1000 
eggs). The method itself requires all inequality relations 
to be converted to equality relations. This is done 
through the addition of "slack" and "surplus" 



variables, so called beacuse they fill up the slack or take 
up the surplus in an inequality relationship. Through 
many iterations, the method automatically reduces the 
inequality constraints in the original problem to equality 
constraints through the addition of these slack and 
surplus variables. "Artificial" variables are then added 
to the equation to form an initial set of basic variables 
or bases. This basis forms a feasible solution to the 
problem, although this solution is non- optimal. The 
object, however, is to find the optimal solution to the 
problem (the solution that optimizes the objective func- 
tion). This initial form is called the canonical form. It 
transforms the original set of constraint equations and 
the objective function by the addition of artificial, slack 
and surplus variables. 

After the problem has been set into canonical form, 
phase I of the problem is ready to begin. In this phase, 
"pivoting" is performed on the constraint variable 
matrix until all the coefficients on the modified objec- 
tive function are less than zero. This pivoting operation 
is very similar to gaussian elimination. A certain 
variable in a certain row and column of the matrix is 



3-202 



AFN-02184A 



AP-143 



divided by itself to become 1 . Subsequently, every other 
variable in that row must be divided by this variable. All 
other variables in the column containing this variable 
are then eliminated by multiplying the variable set to 
one by the negative of the variable to be eliminated and 
then adding the result of this multiplication to the 
number being eliminated. In order for the matrix to re- 
main valid, this operation must be*performed on all 
other columns of the matrix as well, which leads to a 
large number of multiplies and divides. 

Once phase I is complete, phase II must be initiated. 
This phase is required if any of the artificial variables re- 
main in the solution as a basis. Through another round 
of pivoting, the remaining artificial variables are re- 
moved from the solution. What finally comes out is the 
optimal mix of the input variables so the objective func- 
tion is maximized. A more complete description of both 
the simplex method and the revised simplex method can 
be found in Bradley, Hax, and Magnanti 4 . 

ROUTINE IMPLEMENTED 

The linear program used in this example is the IMSL 5 
routine "ZX3LP." This routine is the so-called "easy- 
to-use" linear program solver. It solves the linear pro- 
gram using the revised simplex method. On output, it 
provides not only the solution to the problem, but also 
what is called the dual solution. The dual solution gives 
information about how the solution could be enhanced. 
The objective function is input to the routine as a vec- 
tor, while the constraining equations are input to the 
routine as a matrix. Both inequality and equality con- 
straining equations may be used; the routine will 
automatically insert slack and surplus variables. The 
outputs of the routine are two vectors containing the 
"primal' ' solution and the dual solution. The routine 
also calculates the optimal value of the objective func- 
tion. The version of the routine used was originally 
developed for the IBM 370/3033 mainframe computer. 
It required no modifications to run on the iAPX 86/20 
using FORTRAN 86. 

EXAMPLE PROBLEM 

The following problem was input to the linear program 
routine: 

A small cookie company has four different 
products: chocolate chip cookies without 
walnuts, chocolate chip cookies with 

Stephen P. Bradley, Hax, Arnoldo C, and Magnanti,. 
Thomas L., Applied Mathematical Programming, Addison- 
Wesley, Reading, Massachusetts, 1977. 

5 IMSL, Inc. 



walnuts, brownies without walnuts, and 
brownies with walnuts. The recipes for the 
four are: 



Chocolate Chip Cookies 
2 eggs 

2 /3 cup shortening 

1 cup sugar 

1 cup brown sugar 

1 tsp. vanilla 

2 X A cup flour 

1 tsp. baking soda 

1 tsp. salt 

12 oz. chocolate chips 

(1 Vi cup walnuts) 
0.15 hour oven time 
0.25 hr mix time (w/o nuts) 
0.45 hr mix time (w/nuts) 



Brownies 
4 eggs 

2 A cup shortening 
2 cups sugar 

1 tsp. vanilla 
l!4cup flour 

1 tsp. baking powder 
1 tsp. salt 

4 oz baking chocolate 
( 2 /3 cup walnuts) 
0.5 hour oven time 
0.25 hr mix time (w/o nuts) 
0.45 hr mix time (w/nuts) 



The available amounts of many of the ingre- 
dients have been set previously by contract 
and may not be altered. They are: 



Item 


Quantity 


eggs 


1000 


sugar 


600 cups 


brown sugar 


20 cups 


baking chocolate 


700 oz. 


flour 


600 subs 


baking soda 


150 tsp. 


baking powder 


150 tsp. 


chocolate chips 


1500 oz. 


walnuts 


125 cups 


oven time 


560 hburs 


mixing time 


750 hours 


The amount of profit made for each type 


cookie is: 




Cookie Type 


Profit per Batch 


chocolate chip w/o 


$0.85 


chocolate chip with 


$0.95 


brownies w/o 


$1.10 


brownies with 


$1.25 



It is assumed that the cookie company can 
sell everything that it makes. How many of 
each kind of cookie should the company 
make in order that the profit is maximized? 

The problem was set up into the input tableau. The 
objective function is: 

Y= .85**i + .95*AT 2 + 1.1**3 + 1.25**4 



3-203 



AFN-02184A 



AP-143 



Table 6. Example Problem Input Tableau 



2X1 


+ 


2X2 


+ 


4X 3 


+ 


4X 4 


= 1000 (eggs) 


Xi 


+ 


x 2 


+ 


2X3 


+ 


2X4 


= 600 (sugar) 


Xi 


+ 


x 2 




4X 3 


+ 


4X 4 


= 200 (b. sugar) 
= 700 (b. choc). 


2.25 Xi 


+ 


2.25 X 2 


+ 


1.25 X 3 


+ 


1.25 X 4 


= 600 (flour) 


X! 


+ 






x 3 


+ 


x 4 


= 150 (b. soda) 
= 150 (b. powder) 


12Xl 


+ 


12X2 
.5 X 2 


+ 


.65 X 4 






= 1500 (c. chips) 
= 125 (walnuts) 


.15Xl 


+ 


.15 X 2 


+ 


.5 X 3 


+ 


.5 X 4 


= 560 (oven time) 


.25Xl 


+ 


.45 X 2 


+ 


.25 X 3 


+ 


.45 X 4 


= 750 (mix time) 



Where the variable Xi is the number of batches of 
chocolate chip cookies without nuts, X2 is the number 
of batches of chocolate chip cookies w,ith nuts, X 3 is the 

, number of batches of brownies without nuts, and X4 is 
the number of batches of brownies with nuts. The input 

N tableau is shown in Table 6. These were put into the 
proper input matricies of the ZX3LP program, and the 
following results were generated: 



profit 


$299.25 


, batches of choc chips w/o 


70 


batches of choc «chips with 


55 


batches of brownies w/o 


0 


batches of brownies with 


150 



In addition, the dual solution shows that the single in- 
gredient most limiting the profit of the cookie company 
is the availability of baking powder, and that for every 
additional unit (teaspoon) of baking powder available, 
the profit of the company will increase 1.12 cents. 

The calculation times are: 



with 8087 


1.01 seconds 


with emulator 


46.78 seconds 


with PDP11/45 


0.7 seconds 


with IBM 3033 6 


0.07 seconds 



The results show that the performance of the iAPX 
86/20 is close to the performance of the mini-computer. 
In addition, the performance is only a little more than 
an order of magnitude below the performance of the 
IBM mainframe, a "maxi" computer with an execution 
rate of 5 MIPS, and a CPU/hour cost of around $800! 
A comparison of results between the iAPX 86/20 and 
the emulator verifies the speed of the 8087 is required to 
provide results, in a reasonable period Of time. The 
power and ease of use of this type of sophisticated 
numerical method combined with an "electronic 
worksheet" type of program could be a major advance 
in the "state of the art" of small business machine soft- 
ware. 

CONCLUSIONS 

The types of routines demonstrated in this note show 
that there are many classes of numeric intensive soft- 
ware which are (or should be) commonly used in every- 
day business operations. With the introduction of the 
iAPX 86/20, these types of applications are finally 
within the performance limits of microcomputers selling 
for a fraction of the cost of the previously required 
mini- or maxi- computers. In addition, the availability 
of both Pascal and FORTRAN compilers for the iAPX 
86/20 eases the problem of software generation and 
availability for the processor. Because of the portable 
nature of these high-level languages, a minimum of ef- 
fort is required to generate or to port software to the 
iAPX 86/20 from existing systems. With this kind of 
numeric intensive software support, the 8087 will be an 
essential part of the next generation of small business 
computers. 



'Non-Intel computers used were a PDP 11/45 mini-computer 
with 256K MOS RAM, and a FP1 1-B floating point unit run- 
ning the UNIX operating system during a period of light load. 
The program was compiled using the UNIX F77 FORTRAN 
compiler, and an IBM 370/3033 mainframe computer run- 
ning the VM/CMS operating system during a period of 
medium ioad (the program, however, did not get swapped 
out of memory during execution). The IBlVf FORTRAN G 
compiler was used. 



3-204 



AFN-02184A 



AP-143 



APPENDIX A Contents page 

Interest rate calculation routine 

in FORTRAN A-2 

Annuity calculation routine 

in Pascal . . . , A-3 

Annuity calculation routine 

in FORTRAN A-4 

Silver-Meal heuristic calculation 

routine in Pascal A-6 

Wagner-Whitin method calculation 

routine in Pascal A-9 

Linear programming routine 

in FORTRAN A-12 



/ 



3-205 



AFN-02184A 



AP-143 



FORTRAN- 8 6 COMPILER 

sF6:INTST.FOR ^ 

SERIES-III FORTRAN-86 COMPILER X023 

COMPILER INVOKED BY: FORT86.86 : F6 : INTST . FOR 

c 

c this program provides the yearly effective rate (double and 

c single precision) and final value when the interest rate 

c (ir), the number of compounding periods (np) , 

c the present value (pv) are specified, 
c 

1 real pv,ir,fv,yer 

2 real*8 fvd,yerd 

3 tempreal fvt,yert 

4 integer*2 np,csv 

5 ihteger*4 count , rtimer 
c 

c $2,000,000., at an interest rate of 10% with daily compounding for 1 year 

6 pv=2000000. 

7 ir=.l 

8 np=365 

c . 

c set rounding control to single precision 

c 

9 call stcw87(csv) 

10 csv=csv .and. #fcffh 

11 x call ldcw87(csv) 

v c 

12 yer=(l+(ir/np) )**np - 1 

13 fv=(i + yer)*pv 
c 

c set rounding control to double precision 
c 

14 csv=csv .or. #200h 

15 call ldcw87(csv) 
c 

16 yerd=(l+(ir/np) )**np - 1 

17 fvd=(l + yerd)*pv 
c 

c set rounding control to temp real precision 
c 

18 csv=csv .or. #100h 

19 call ldcw87(csv) 
c 

20 yert=(l+(ir/np) )**np - 1 

21 fvt=(l + yert)*pv 
c 

c print results 
c 

22 print *,' single precision: yer=' ,yer, ' fv=' , fv 

23 "print *,' double precision: yer= 1 ,yerd, 1 fv= ' , fvd 

24 print * , 1 temp real precision: yer= ' , yert , ' fv= ' , fvt 

25 stop 

26 v end 



3-206 



AFN-02184A 



AP-143 



SERIES-III Pascal-86, VI. 1 



Source File: : Fl : ANNP1 . PAS 
Object File: : Fl : ANNP1 .OBJ 
Controls Specified: CODE. 



SOURCE TEXT: : Fl : ANNP1 . PAS 

(* ANNUITIES: type 1, the sinking fund 

* if one were to place $1000 a month into a savings fund which 

* earns 12% per annum, compounded daily, what will be the value 

* of the fund after 20 years??? 
*) 

module annuity; 
public eel; 

function mqery2x(y,x: real):real; (* takes y to the x *) 
program annuity ( input , output ) ; 

var 

ir, (* the annual interest rate *) 

fv, (* the final value *) 

pmt, (* the amount of the payment *) 
irp: (* the interest rate per period *) 
real ; 

np: (* the number of periods •*) 

integer ; 

begin 

(* insert calculation values *) 
ir := 0.12; 
pmt := 1000; 

np := 12 * 20; (* 20 years of months *) 

(* calculate the effective interest rate per period *) 

irp := mqery2x( ( 1+ ( i r/365 . 0 ) ) ,365. 0/12. 0)-l; 
(* effective monthly rate *) 
(* calculate the future value *) 

fv := pmt * (mqery2x( (1+irp) ,np)-l)/irp; 



(* print results *) 

writeln('the effective monthly rate is*,irp:18); 
writeln('the future value of the annuity is ' , fv: 12: 2) ; 
writeln('the total contribution to the annuity is' ,np*pmt : 12: 2) ; 

end . 



3-207 



AFN-02184A 



AP.143 



FORTRAN-86 COMPILER 
: PI: ANNUL FOR 

SERIES-III FORTRAN-86 COMPILER X023 \ 
COMPILER INVOKED BY: FORT86.86 : Fl : ANNU1 . FOR 

c 

c ANNUITIES: type 1, the sinking fund 

c if you place in a savings fund $1000.00 a month, and it 

c earns an interest rate of 12% per annum compounded daily, 

c what will be the value of the fund after 20 years? 
c 

1 real ir ,pv,f v,pmt , i rp 

i real*8 tvd,irpd 

3 tempreal fvt,irpt 

4 integer*2 cwv 
b integer np 

6 ir = .12 

7 pmt « 1000. 
c 

c the number of periods is the number of months in 20 years! (one period 

c is one month 

c 

8 np = 20*12 
c 

c set the 8087 to single precision mode 
c 

9 call stcw87(cwv) 

10 cwv a cwv .and. #fcffh 

11 call ldcw87(cwv) 
c 

c first calculate the effective interest rate per period 
c 

12 irp * (l+(ir/365.) ) ** (365./12. ) - 1 
c 

c then calculate the future value 
c 

13 fv = pmt * ((1 +irp)**np - l)/irp 
c 

14 print *,'single precision values:' 

15 print *,'the effective rate per month is', irp 

16 write (6,800) fv 

17 write (6,801) np*pmt 

18 800 format('the future value of the annuity is',fl8.2) 

19 801 formatCthe total contribution to the annuity is',fl8.2) 
c 

c set the 8087 to double precision mode 
c 

20 cwv=cwv .or. #200h 

21 call ldcw87(cwv) 

c 

c first calculate the effective interest rate per period 
c > - 

22 irpd = (l+(ir/365. ) ) ** (365d0/12d0) - 1 
c 

c then calculate the future value 
c 

23 fvd = pmt * ((1 +irpd) **np - l)/irpd 
c 

24 print *,'double precision values:* 



3-208 



AFN-02184A 



AP-143 



"FORTRAN-86 COMPILER 
:F1:ANNU1.F0R 

25 print *,'the effective rate per month is',irpd 

26 write (6,800) fvd 

27 write (6,801) np*pmt 
c 

c set the 8087 to temp real precision mode 
c 

28 cwv=cwv .or. #100h 

29 call ldcw87(cwv) 
c 

c first calculate the effective interest rate per period 
c 

30 irpt = (l+(ir/365.))**(365t0/12t0) - 1 
c 

c then calculate the future value 
c 

31 fvt = pmt * ((1 +irpt)**np - l)/irpt 
c 

32 print *,'temp real precision values:' 

33 print *,'the effective rate per month is', irpt 

34 write (6,800) fvt 

35 write (6,801) np*pmt 

36 stop 

37 end 



3-209 



AFN-02184A 



AP-143 



SERIES-III Pascal-86, VI . 1 



Source File: :F6:SMCT.PAS 
Object File: :F6:SMCT.OBJ 
Controls Specified: <none> . 



SOURCE TEXT: :F6:SMCT.PAS 

(* This is going to try to find the optimal replacement cost 

* for a rather variable demand product over 20 months, when 

* the demand is known, an example could be a video game, using 

* a single chip ROM programmed microcomputer with an initial set 

* up charge of $3000.00, demand varies a lot with peak in October 

* and november(for Christmas), droops in may (vacations) , etc. 

* The cost per part varies from $20.00 per part up to 500, 

* $17.50 per part from 500 to 5000, and $15.00 above 5,000. 

* The Sliver-Meal heuristic is going to be used. 
*) 

module silver_meal; 
public timers ; 

function rtimer: integer ; 

procedure stimer; 
program si 1 ver_meal ( input, output ) ; 
const / , 

months = 20; 

monthspl = 21; 

setupcost = 3000.0; 

holdcost = 0.4; 

reallarge = l.OelO; 

reallargei = 32000; 



var 



repl: (* first time stock goes to 

arrayCl . .months] of integer; 



0 for a given month *) 



tomake 
require: 

arrayCl 
trcut , 
holdcos'tv: 

array[l 
cost, 
costl , 
cost2 , 
totalcost , 
lastcost , 
totalholdcost : 

real ; 
i, j,k: 

integer 
totcnt , 
holdcnt: 

real ; 
count : 

integer 



the number of boxes to make in a month *) 
(* number of boxes required in a given month *) 
monthspl] of real; 



(* holding costs 
.months] of real; 



calculated cost in a given situation *) 

production cost *) 

holding cost * ) 

the total cost of it all *) 

used in determining the total cost * ) 

the total hold cost *) 



(* counters *) 

(* accumulated number of boxes in a batch 
(* number of boxed holding *) 

(* the 10 ms count *) 



begin 

required ] 
requireC 2] 
require[3] 
require[4] 



:= 500; 

:= 1500 

:= 2500 

:= 2000 



3-210 



AFN-02184A 



AP-143 



SOURCE TEXT: :F6:SMCT.PAS 



requireC 5] 
require[6] 
require[7] 
require[8] 
require[9] 
requireClO] 
require[ll] 
require[12] 
require[13] 
require[14] 
require[15] 
require[16] 
require[17] 
require[18] 
require[19] 
require[20] 



2000 

1000 

3500 

2500 

5000 
■ 7500; 
= 9500; 
= 10000 

* 500; 
= 1500 
= 2500 
= 2000 
= 2000 
= 1000 

* 3500 
= 2500 



(* stop here, because the next month is much 
higher can assume will restock then *) 
requireCmonthspl] r= reallargei; 



s timer ; 



(* start the timer *) 



i := 1; 

while i <= months do begin 
trcut[i] := reallarge; 
totcnt := 0; 



(* i is the month working on *) 



3 := i; 

while j <= monthspl do begin 

totcnt := totcnt + require[j]; 
if totcnt < 500 then costl := 20 
else if totcnt < 5000 then costl 
else costl := 15.0 * totcnt; 
cost2 := 6.0; 
holdcnt := totcnt; 
for k := i to j - 1 do begin 

holdcnt := holdcnt - require[k]; 
cost2 := cost2 + holdcnt * holdcost 

end; 

cost := (setupcost + cost2 + costl) /(j 
if cost < trcutCi] then begin 

trcutCi] := cost; 

tomake[i] j= totcnt; 

holdcostv[i] := cost2; 

end 

else begin 

repl[i] := j; 
i := j; 

j :== monthspl; 

end; 

j := j + 1; 

end; 



totcnt 
17.5 * totcnt 



i + 1); 



end; 



count := r timer; 
j := 1; 



3-211 



AFN-02184A 



AP-143 



SERIES-III Pascal-86, VI . 1 



SOURCE TEXT: :F6:SMCT.PAS 

writeln( 'month restock# optimal cost per period'); 
totalcost := 0; 
for i := 1 to months do begin 
if i - j then begin 

write(i:5, V ' , tomake[i] :6 , ' r , trcutCi] : 10: 2 ) ; 

writeln( ' * restocking now' ) ; 

j := replCj]; 

lastcost := trcutCi]; 

totalcost := totalcost + lastcost; 

end 

else begin 

totalcost := totalcost + lastcost; 
writeln( i : 5 ) ; 

end ; 

end; 
i 1; 
j 0; 

totalholdcost := 0.0; 
while i <= months do begin 

totalholdcost := totalholdcost + holdcostv[i] ; 

j := j + 1; 

i := repl[i]; 

end ; 

writeln('the total hold cost is ', totalholdcost: 12 : 2 ) ; 
writeln( ' stock gets replenished ', j :4 , ' times'); 
writeln( ' replenishment cost is ' , j*setupcost: 12 : 2 ) ; 
writeln('the total cost thingy is ', totalcost ) ; 
writeln('the 10 ms count isocount); 

end . 



Summary Information: 

PROCEDURE OFFSET CODE SIZE DATA SIZE STACK SIZE 

S ILVER_MEAL 0108H 05F7H 1527D 01ACH 428D 000EH 14D 

Total 06FFH 1791D 01ACH 428D 0042H 66D 

135 Lines Read. 

0 Errors Detected. 
41% Utilization of Memory. 



3-212 



AFN-02184A 



AP-143 



SERIES-III Pascal-86, VI. 1 

I 



Source File: : F6 : WAGCT . P AS 
Object File: : F6 : WAGCT . OB J 
Controls Specified: <none> . 

SOURCE TEXT: : F6 : WAGCT . PAS 

(* This is going to try to find the optimal replacement cost 

* for a rather variable demand product over 20 months, when 

* the demand is known, an example could be a video game, using 

* a single chip ROM programmed microcomputer with an initial set 

* up charge of $3000.00, demand varies a lot with peak in October 

* and november(for Christmas), droops in may (vacations) , etc. 

* The cost per part varies from $20.00 per part up to 500, 

* $17.50 per part from 500 to 5000, and $15.00 above 5,000. 
*) 

module wag_with; 
public timers; 

function rtimer : integer ; 

procedure stimer; 
program wag_with ( input , output ) ; 
const 

months = 20; 

month spl = 21; 

setupcost = 3000.00; (* mask set up charge *) 

holdcost =0.4; (* cost per part of maintaining inventory*) 

reallarge = 1.0e9; 

var 

require, (* number of chips required in a given month *) 

tomake: (* the number of chips to make in a month *) 

arrayCl . .months] of real; 
repl: (* first time stock goes to 0 for a given month *) 

arrayCl . .months] of integer; 
optwz: (* optimum cost for a given month with zero stock 

to start with *) 

arrayCl . .monthspl] of real; 
holdcostv: (* holding costs *) 

arrayCl . .months] of real; 
cost, (* calculated cost in a given situation *) 

costl, (* production cost *) 

cost2, (* holding cost *) 

totalcost, (* the total cost of it all *) 

totalholdcost; (* the total hold cost *) 

real; 

i,j,k: (* counters *) 

integer; 

totcnt, (* accumulated number of chips in a batch *) 

holdcnt: (* number of boxed holding *) 

real; 

count: (* 10 ms count *) 

integer; 

begin 

optwz [monthspl] := 0; 
required] := 500; 
require[2] : = 1500; 
require[3] := 2500; 
require[4] : = 2000; 



3-213 



AFN-02184A 



AP-143 



SERIES-III Pascal-86, VI. 1 



SOURCE TEXT: : F6 : WAGCT . PAS 
require[5] := 2000; 
require[6] t- 1000; 
require[7] := 3500; 
require[8] := 2500; 
require[9] := 5000; 
require[10] := 7500; 
requireCll] := 9500; 
require[12] 10000; 
require[13] := 500; 
require[14] := 1500; 
require[15] := 2500; 
require[16] : s 2000; 
require[17] : = 2000; * 
require£l8] := 1000; 
require[19] := 3500; 

require[20] := 2500; (* stop here, because the next month is much 

higher can assume 1 will restock then *) 

stimer; 

for i := months downto 1 do begin (* i is the month working on *) 
optwz[i] := reallarge; 
totcnt := 0; 

for j := i to months do begin (* j is the option working on *) 
totcnt totcnt + requireCj]; 
costl := setupcost+optwzC j+1 ] ; 

if totcnt <== 500 then costl := costl + 20.0*totcnt 

else if totcnt <= 5000 then costl := costl + 17.5*totcnt 

else costl := costl + 15.0*totcnt; 

cost2 := 0.0; 

holdcnt := totcnt; 

for k := i to j - 1 do begi-n 

holdcnt := holdcnt - requireCk]; 

cost2 := cost2 + holdcnt * holdcost; 

end; 

cost := costl + cost2; 

if cost < optwz[i] then begin 

optwz[i] := cost; 

replCi] := j + 1; 

tomakeCi] :-- totcnt; 

holdcostvCi] := cost2; 

end; 

end; 

end ; 

count := rtimer; 
j := 1; 

writeln( 'month restock# optimal cost'); 
for i : = 1 to months do begin 

write(i:5,' ' , tomake[i] :6 , ' 1 ,optwz[i] :10:2) ; 

if i = j then begin 

writeln( ' * restocking now'); 
j := repl[j]; 

end 

else writeln; 

end ; 



3-214 



AFN-02184A 



AP-143 



SERIES-III Pascal-86, VI . 1 



SOURCE TEXT: :F6:WAGCT.PAS 
i := 1; 
j := 0; 

totalholdcost : = 0.0; 
while i <= months do begin 

totalholdcost := totalholdcost + holdcostv[i] ; 

j :- j + 1? 

i := repl[i]; 

end; 

writeln('the total hold cost is ', totalholdcost : 12 : 2 ) ; 
writeln( 1 stock gets replenished * ,j :4, ' times'); 
writeln( ' replenishment cost is ' , j*setupcost: 12 : 2) ; 
writeln('the 10 ms count is count); 

end . 



Summary Information: 

PROCEDURE OFFSET CODE SIZE DATA SIZE STACK SIZE 

WAG__WITH 00E5H 0576H 1398D 01A8H 424D 000EH 14D 

Total 065BH 1627D 01A8H 424D 0042H 66D 

119 Lines Read. 

0 Errors Detected. 
41% Utilization of Memory. 



3-215 



AFN-02184A 



AP-143 



FORTRAN-86 COMPILER 
:F1: COOKIE. FOR 

SERIES-III FORTRAN-86 COMPILER X023 

COMPILER INVOKE^ BY: FORT86.86 :F1 : COOKIE .FOR 



c 

c this routine will solve a linear problem using the IMSL fortran 



c library, the IMSL routine used is M zx31p" which solves the problem 

c using the revised simplex method, 
c 

1 integer ia,n,ml,m2,iw(37) ,ier 

2 real*8 a(13,4) ,b(13) ,c(4) ,rw(206) ,psol(ll) ,dsol(13) , s 

3 integer*4 rtimer, count 

4 data ,a/2 . , 1 . , 1 . ,0 . , 2 , 25 , 1 . , 0 . , 12 . , 0 . , .15, .25,0 . ,0. , 

* . 2. ,1. ,1. ,0. ,2.25,1. ,0. ,12. , .5, .15, .45,0. ,0. , 

* 4.,2.,0.,4.,1.25,0.,1.,0.,0.,.5,.25,0.,0., 

* 4.,2.,0.,4.,1.25,0.,1.,0.,.65,.5,.45,0.,0./ 

5 data b/1000 . , 600 . , 200 . , 700 . , 600 . , 150 . , 150 . , 1500 ., 125 ., 560 ., 750 . ,0. ,0./ 

6 data c/. 85, .95,1.10,1.25/ 

c 

c n is the number of variables, 

c ml is the number of inequality constraints 

c m2 is the number of equality constraints 

c ia is the declared number of columns of a 

c 

7 ml = 11 

8 m2 = 0 

9 n = 4 

10 ia = 13 

11 print *,'the input tableau:' 

12 do 100 i=l,ia-2 

13 write(6,800)a(i,l) ,a(i,2) ,a(i,3) ,a(i,4) ,b(i) 

14 800 format(4fl0.4, ' <= ',fl0.4) 

15 100 continue 

16 call stimer 

17 call zx31p(a,ia,b,c,n,ml,m2,s,psol,dsol,rw,iw,ier) 

18 count = rtimer () ' 

19 priint * , ' ier = ' , ier 

20 print *,'the final value of the objective function(prof it i ) is:',s 

21 print *, 'batches of chocolate chip w/o walnuts: ' ,psol(l) 

22 print *, 'batches of chocolate chip with walnuts :' ,psol ( 2 ) 

23 print *,'batches of brownies without walnuts :' ,psol ( 3 ) 

24 print *, 'batches of brownies with walnuts: ' ,psol( 4) 

25 print *,'the dual solutions follow:' 

26 do 200 i=l,ia-2 

27 print *,'var',i,' = ' ,dsol(i) 

28 200 continue 

29 print *,'the calculation time here (in seconds...) is: ', count/ 100. 

30 stop 

31 end 



3-216 



AFN-02184A 



intpl APPLICATION AP-144 

NOTE 



October 1983 



© INTEL CORPORATION, 1982 Order Number 210384-001 



3-217 



AP-144 



INTRODUCTION 

As the performance of microcomputers has improved, 
these machines have been used in many applications. 
With the introduction of 16-bit microprocessors (along 
with the associated CPU enhancements, especially the 
integer multiply instruction) the operations required to 
manipulate graphic representations of three- 
dimensional objects were made easier. Only integer 
values could be used to define figures, however, because 
only integer multiplies were supported in hardware. 
While software floating point routines existed, the speed 
at which a general purpose microprocessor could ex- 
ecute even the simplest floating point operation preclud- 
ed the use of these routines because of the number of 
floating point operations which must be performed to 
manipulate all but the simplest of objects. 

The lack of high performance floating point math or the 
restriction of using only integer representations severely 
limits the types and sizes of objects that can be defined. 
Imagine limiting everything in the universe to be less 
than 32,000 millimeters long, high, or wide! This limita- 
tion could severely impact any system that is used to 
model real world objects. An example of such an ap- 
plication is a Computer Aided Design (CAD) system. If 
real or floating point numbers are used, however, prac- 
tically any object can be defined (after all, there are only 
9,397,728,000,000,000,000 millimeters in a light year(!), 
well within the range of floating point numbers). With 
the introduction of the iAPX 86/20, the performance 
required to execute the requisite operations on floating 
point representations of three-dimensional figures has 
finally been achieved in a microprocessor solution, at a 
microprocessor price. 

The iAPX 86/20 features the Intel 8086 with the 8087 
numerics co -processor. This combination allows for 
high performance, high precision numeric operations. 
This performance is especially important in the graphics 
routines implemented in this note because of the large 
number of floating point operations performed for each 
line drawn. In addition, the precision is required to 
maintain the image quality of the represented figures. 

This application note shows the fundamental com- 
ponents of a three-dimensional graphics package. As 
, stated before, if the objects are to be described in real 
size, floating point values must be used. Since the opera- 
tions performed require many multiplies and divides, a 
high performance floating point arithmetic unit is a 
must. Note that the operations to be performed by this 
software are not those of a "bit map" controller: single 
chip devices performing this specialized task are or will 
soon be available. Because they are special-purpose 
devices, they can also execute this task quickly, 
offloading the task from the general purpose 



microprocessor allowing the processor to perform other 
work in parallel. In addition, since the size of the 
memory used in a bit-mapped controller is constrained 
(one could hardly have unlimited memory for the 
refresh map), only integer math is required. This 
graphics package is a much higher level type of routine, 
where the inputs are three-dimensional line drawing 
commands (which could be fed into a bit map con- 
troller). 

The three-dimensional graphics package implemented 
in this note allows for the entry of three-dimensional 
figures, the manipulation of these figures, the setting of 
the viewer's location, the size of the picture to be seen, 
and the position of the picture on the graphics output 
device. Along the way, it performs perspective transfor- 
mations, window clipping and projection. All figures 
are defined using floating point numbers. Thus, any 
figure may be defined "real size" without pre-scaling. 
This means that the size of the figure defined within the 
package may be the actual size of the object, i.e. the size 
of the object is not arbitrarily limited by the machine, 
whether the object be a sub-nuclear particle, or a 
cellestial body. 

iAPX 86/20 HARDWARE OVERVIEW 

The iAPX 86/20 is a 16-bit microprocessor based on the 
Intel 8086 CPU. The 8086 CPU features eight internal 
general purpose 16-bit registers, memory segmentation, 
and many other features allowing for compact, efficient 
code generation from high-level language compilers. 
When augmented with the 8087, it becomes a vehicle for 
high-speed numerics processing. The 8087 adds eight 
80-bit internal floating point registers, and a floating 
point arithmetic logic unit (ALU) which can speed 
floating point operations by up to 100 times over other 
software floating point simulators or emulators. 

The 8086 and 8087 execute a single instruction stream. 
The 8087 monitors this stream for numeric instructions. 
When a numeric instruction is decoded, the 8086 
generates any needed memory addresses for the 8087. 
The $087 then begins, instruction execution automatical- 
ly. No other software interface is required, unlike other 
floating point processors currently available where, for 
example, the main processor must explicitly write the 
floating point numbers and commands into the floating 
point unit. The 8086 then continues to execute non- 
numeric instructions until another 8087 instruction is 
encountered, whereupon it must wait for the 8087 to 
complete the previous numeric instruction. The parallel 
8086 and 8087 processing is known as concurrency. 
Under ideal conditions, it effectively doubles the 
throughput of the processor. However, even when a 
steady stream of numeric insructions is being executed 
(meaning there is no concurrency), the numeric perfor- 



3-218 



AFN-02185A 



AP-144 



mance of the 8087 ALJJ is much greater than that of the 
8086 alone. 

The hardware interface between the 8086 and the 8087 is 
equally simple. Hardware handshaking is performed 
through two sets of pins. The RQ/GT pin is used when 
the 8087 needs to transfer operands, status, or control 
information to or from memory. Because the 8087 can 
access memory independently of the 8086, it must be 
able to become the "bus master," that is, the processor 
with read and write control of all the address, data and 
status lines. 

The TEST/BUSY pin is used to manage the concurren- 
cy mentioned above. Whenever the 8087 is executing an 
instruction, it sets the BUSY pin high. A single 8086 in- 
struction (the WAIT instruction) tests the state of this 
pin. If this pin is high, the WAIT instruction will cause 
the 8086 to wait until the pin is returned low. Therefore, 
to insure that the 8086 does not attempt to fetch a 
numeric instruction while the 8087 is still working on a 
previous numeric instruction, the WAIT instruction 
needs to precede most numeric instructions (the only 
class of instructions which do not need to be preceded 
by a WAIT instruction are those which access the con- 
trol registers of the 8087). The 8086/87/88 assembler, 
in addition to all INTEL compilers, automatically in- 
serts this WAIT instruction before most numeric in- 
structions. Software polling can be used to determine 
the state of the BUSY pin if the hardware handshaking 



is not desired. 

Most other lines (address, status, etc.) are connected 
directly in parallel between the 8086 and the 8087. An 
exception to this is the 8087 interrupt pin. This signal 
must be routed to an external interrupt controller. An 
example iAPX 86/20 system is shown in Figure 1. A 
more complete discussion of both the handshaking pro- 
tocol between the 8086 and the 8087 and the internal 
operation of the 8087 can be found in the application 
note Getting Started With the Numeric Data Processor, 
Ap Note #113 by Bill Rash, or by consulting the 
numerics section of the July 1981 iAPX 86, 88 Users 
Manual. 

In addition to the 8087 hardware, the 8086 is also sup- 
ported by Intel compilers for both Pascal and FOR- 
TRAN. Code generated by these compilers can easily be 
combined with code generated from the other compiler, 
from the Intel 8086/87/88 macro assembler, or the In- 
tel PL/M compiler. In addition, these compilers pro- 
duce in-line code for the 8087 when numeric operations 
are required. By producing in-line code rather than calls 
to floating point routines, the software overhead of an 
unnecessary procedure call and return is eliminated. 

The combination of both hardware co -processors and 
software support for the iAPX 86/20 provides for 
greater performance of the end product, and a quicker, 
easier development effort. 



L_j? 



8284A 
CLOCK 
GENERATOR 



1 I 



8086/8088 
CLK CPU 



RQ/GT1 

QS0 QS1 TEST 



QS0 QS1 BUSY 
RQ/GT0 



ri k 8087 
CLK NDP 



RQ/GT1 



r 



3 



GT ~~i 



^ CLK 8089 

-*"| CLK , 0 p 



A. 



8086 

K FAMILY A K 

) INTERFACE ( SYSTEM BUS ) 

)/ COMPONENTS \ ]/ 



Figure 1 . Example 86/20 System 



3-219 . 



AFN-02185A 



AP-144 



THREE-DIMENSIONAL GRAPHICS 
FUNDAMENTALS 

The charter in life of a three-dimensional graphics 
package is to take a three-dimensional rendering of an 
object and to transform it such that it can be accurately 
represented on the two-dimensional surface of a 
graphics output device. To fulfill these requirements, 
the graphics package must: 

• Allow for the entry of three-dimensional data. 

Since all figures inside the package are represented 
as a series of points in three-dimensional space, 
there must be a way of entering these figures into 
the computer. 

• Perform the current transformation. This 
transformation rotates, translates and scales the 
three-dimensional object throughout three- 
dimensional space. Example rotates, translates 
and scales are shown in Figures 2-11. In all 
diagrams, the first coordinate indicated is X, the 
second Y, the third Z. The viewpoint is the loca- 
tion of the viewer in three-dimensional space in 
relationship to an arbitrarily chosen but consistent 
origin. 

Translations are movements of the object in three- 
dimensional space. Example translations are 
shown in Figures 3-5. Figure 3 shows a translation 
of two units in the plus Z direction. Since the view- 
point is ten units up along the Z axis, this moves 
the cube one-fifth the distance toward the viewer, 
or in other words, the cube seems to get larger. 
Figure 4 shows the same cube translated two units 
in the plus X direction. Since the cube is four units 
on a side, this moves the cube such that the viewer 
is looking straight down one side of the cube. The 
viewer is also looking straight down a side in 
Figure 5. 

Rotations are movements of the object in three- 
dimensional space about the three- coordinate 
axis: X, Y, and Z. The rotation of the object must 
specify both the magnitude of the rotation, and 
the axis about which the rotation must take place. 
Example rotates are shown in Figures 6-8. Figure 
6 shows the cube rotated 45 degrees about the Z 
; axis. Since the viewpoint is straight up the Z axis, 
the cube is seen to keep its same face towards the 
viewer. Figure 7 shows the cube rotated 45 degrees 
about the X axis. Here, the cube no longer shows 
the same face it has previously. The face previous- 
ly turned directly toward the viewer has been 
rotated such that the edge between this face and 
another face is immediately before the viewer. The 
same is also shown in the rotation about the Y axis 
in Figure 8. 



Scaling is the multiplication of all coordinates of 
the points defining a figure by a constant number 
such that the object becomes larger or smaller. Ex- 
ample scales are shown in Figures 9-11. This scal- 
ing need not be uniformly performed for all 
dimensions of an object. If, for example, the Z 
coordinates of a cube are all scaled to be twice as 
large as they originally were, the image shown in 
Figure 9 would be produced. Notice here that the 
X and Y coordinates have not been altered; only 
the Z coordinates are twice as large as they 
originally were, or alternatively, the front and 
back of the cube are closer and farther away from 
the viewer than in the original, unaltered cube. 
Figure 10 shows this same operation being per- 
formed on the X coordinates, while Figure 11 
shows this operation being performed on Y co- 
ordinates. 



Figure 2. 2x2x2 Cube Centered at (0,0,0) 
Viewed from (0,0,10) 




Figure 3. Same Cube and Viewpoint, + 2 Z 
Translation 



3-220 



AFN-02185A 



AP-144 




Figure 4. Same Cube, Viewpoint, + 2 X Translate Figure 5. Same Cube, Viewpoint, +2Y Translate 




Figure 6. Same Cube, Viewpoint, 45 Degree 
Rotation About Z 



Figure 7. Same Cube, Viewpoint, 45 Degree 
Rotation About X 



3-221 



AFN-02185A 



AP-144 




Figure 8. Same Cube, Viewpoint, 45 degree 
Rotation About Y 









\ 



Figure 9. Same Cube, Viewpont 2 x Scale of Z 





Figure 10. Same Cube, Viewpoint, 2 x Scale of X Figure 11. Same Cube, Viewpoint, 2 x Scale of Y 



3-222 



AFN-02185A 



AP-144 




Figure 12. 2x2x2 Cube Centered at (0,0,0) Viewed from (0,0,10) Then from (10,10,0) 



Perform the viewing transformation. This 
transformation moves and rotates the three 
dimensional figure according to the viewer's loca- 
tion and orientation (the direction the viewer is 
facing) in space. An example of changing the view 
location is shown in Figure 12. Again, this loca- 
tion, or viewpoint, is the viewer's location with 
relation to an arbitrarily chosen origin. 

Perform Z-clipping on the three-dimensional 
data. This insures that only data in front of the 
viewer are displayed. In addition, it allows that 
objects beyond a certain distance from the viewer 
will not be displayed. 

Project the three-dimensional data onto a two 
dimensional surface. The objects must be pro- 
jected onto a two-dimensional surface according 
to the laws of perspective. By changing the 
"vanishing point,' * interesting effects are also 
possible. An example of this is shown in Figure 13. 
Here, the first figure shows exaggerated perspec- 
tive (that is, the difference in perceived size be- 
tween the front face and the back face of the cube 
is exaggerated), where the second figure shows the 
object with subdued perspective (the difference in 
the perceived sizes of the front and back faces is 
much less than in the first figure). Exaggerated 
perspective is generated for objects close to the 
viewer, while subdued perspective is generated for 
objects distant from the viewer. Note that the 
same figure, with the same dimensions, is shown 
in both figures; only the perspective values have 
been changed. 



• Perform X-Y clipping on the projected data. This 
cuts off lines in the projected data extending 
beyond the specified "window." 

• Perform the window to viewport transformation. 

This takes the two-dimensional projected values 
and scales them according to the relative sizes of 
the "window" and the "viewport." 

The "window" describes the size of the viewer's portal 
into the data, whereas the "viewport" describes the size 
and position of this portal on the graphics output 
device. Whereas the window's size is determined by the 
size of the input data, the viewport size is determined by 
the physical characteristics of the graphics display 
device. For example, the viewport coordinates of a cer- 
tain CRT display may be constrained to be between 0 
and 1023 in both the X and Y dimensions, whereas the 
window limits are determined only by the maximum size 
of numbers the computer can store. Thus, for maximum 
generality and utility, floating point numbers must be 
used to represent the three-dimensional figures. 

A good reference to the techniques used in this three- 
dimensional graphics implementation can be found in 
Newman and Sproull K 



Newman, William M. and Robert F. Sproull, Principles of 
Interactive Computer Graphics, McGraw-Hill Book Com- 
pany, New York, 1979. 



3-223 



AFN-02185A 



AP-144 




Figure 13. Example Cube Shown with Exaggerated Perspective, then with Subdued Perspective 



IMPLEMENTATION 

Three-dimensional graphics systems can be split into 
three functional modules: the input hardware, the pro- 
cessing hardware, and the output hardware. The 
graphics software is executed by the processing hard- 
ware and is used to receive figure definitions from the 
input hardware, store them in one form or another, and 
manipulate them such that they can be displayed on the 
output hardware. 

Input hardware can range from the common typewriter 
keyboard to sophisticated three-dimensional input 
devices. Output hardware can range from a plotter to a 
storage tube terminal to a bit-mapped raster scan 
display or a vector drawing *CRT. 

The processing hardware can range from general pur- 
pose minicomputers to very fast, specialized graphics 
processing hardware. General purpose computers are 
used because they allow applications programs to be 
written in higher level languages. Specialized hardware 
is sometimes employed when very fast manipulations 
are required, such as in the real time graphics applica- 
tions found in flight simulators. This specialized hard- 
ware can be used to perform whole matrix transforma- 
tions. Many applications do not require figures to be 
drawn real time (on the order of one complete picture 
every 1/30 sec), however, and can be satisfied by the 
performance of the general purpose computer alone. A 
typical application which is satisfied by these latter re- 



quirements is a Computer Aided Design (CAD) system. 
However, since these graphics systems often exist in an 
interactive environment, picture processing delays 
greater than a few seconds for simple figures, or greater 
than a few minutes for very complex figures cannot be 
tolerated. Because of these processing requirements, a 
mini-computer with a hardware floating point unit has 
been required to drive these graphics systems. However, 
with the introduction of the 8087, the floating point 
processing performance required by these systems can 
finally be met in a microcomputer solution. 

The microcomputer system used in this three- 
dimensional graphics application is a general purpose 
microcomputer embodied in the iAPX 86/12 board 
found in an Intel Intellec® Series III development 
system. All routines implemented in this application 
note were written entirely in FORTRAN using the Intel 
FORTRAN 86 compiler. Any iAPX 86/20 (or iAPX 
88/20) with enough memory can be used to execute the 
programs, however. The amount of memory required 
depends on the number and complexity of the figures to 
be displayed. The source code for all routines used in 
this note are given in the appendix. 



3<-224 



AFN-02185A 



AP-144 



SERIES III DEVELOPMENT 
SYSTEM WITH iSBC® 86/12 
BOARD & ISBC 337 MULTIMODULE 



HP 7225A PLOTTER 




600 baud serial 
line 



337 

multimodule 




Keyboard 



86/12 board 



Figure 14. Computer System Used in This Graphics Implementation 



The graphics output device used was a HP 7225A flat 
bed plotter. Communications were performed using the 
RS232 serial link on the 86/12 board. The communica- 
tions speed of the line to the plotter was 600 baud. 
Because of the number of lines drawn in the more com- 
plex figures, the physical characteristics of the plotter, 
and the communications line speed, the amount of time 
required to draw a large picture was a function of the 
plotter speed, not the execution speed of the iAPX 
86/20. As a result, all times quoted in this note do not 
reflect the plotting time. Only the time up to placing the 
ASCII character into the buffer of a serial communica- 
tions chip is included for all machines quoted. Higher 
speed graphics display devices (which are not limited by 
the physical characteristics of plotters) can use the speed 
of the iAPX 86/20 to full advantage. 

The graphics input device used was the standard 
alphanumeric keyboard attached to the development 
system. This allows entry of figures, as well as control 
of the graphics system. Input can also be fetched from 
disk storage, however, to allow for greater speed in 
defining large figures. A block diagram of the hardware 
system used in this implementation is shown in Figure 
14. 

All routines were run using both the 8087 and the 8087 
software emulator. The 8087 software emulator is a 
software package exactly emulating the internal opera- 
tion of the 8087 using 8086 instructions. When the 
emulator is used, an 8087 is not required. The emulator 
is a software product available from Intel as part of the 
8087 support library. The performance of the 8087 
hardware is much better than that of the software 
emulator, as one would expect from a specialized hard- 
ware floating point unit. 

The 8087 supports various data formats. For real 
numbers, these formats are short real (or single preci- 
sion), long real (or double precision), and temporary 
real (or extended precision). The differences among the 



three are in the number of bits allocated to represent a 
given floating point number J 

In all real numbers, the data is split into three fields: the 
sign bit, the exponent field and the mantissa field. The 
sign bit shows whether the number is positive or 
negative. The exponent and mantissa together provide 
the value of the number: the exponent providing the 
power of two of the number, and the mantissa pro- 
viding the "normalized" value of the number. 

A ' 'normalized* * number is one that always lies within a 
certain range. By dividing a number by a certain power 
of two, most numbers can be made to lie between the 
numbers 1 and 2. The power of two by which the 
number must be divided to fit within this range is the ex- 
ponent of the number, and the result of this division is 
the mantissa. This type of operation will not work on all 
numbers (for example, no matter what one divides zero 
by, the result is always zero), so the number system must 
allow for these certain "special cases." 

As the size of the exponent grows, the range of numbers 
representable also grows, that is, larger and smaller 
numbers may be represented. As the size of the mantissa 
grows, the resolution of the points within this range 
grows. This means the distance between any two adja- 
cent numbers decreases, or, to put it another way, finer 
detail may be represented. Short real numbers provide 8 
exponent bits and 23 significand or mantissa bits. Long 
real numbers provide 11 exponent bits aad 52 signifi- 
cand bits. Temporary real numbers provide 15 exponent 
bits and 64 significand bits. These data formats are 
shown in Figure 15. Thus, of the three data formats im- 
plemented, short real provides the least amount of 
precision, while temporary real provides the greatest 
amount of precision. These levels of precision represent 
only the external mode of storage for the numbers; in- 
side the 8087 all numbers are represented to temporary 
real precision. Numbers are automatically converted in- 
to the temporary real precision when they are loaded in- 



3-225 



AFN-02185A 



AP-144 



SHORT REAL S fex^fJlT 



A — ia 



LONG REAL S 



BIASED 
EXPONENT 



SIGNIFICAND 



N — I A 



TEMPORARY REAL S 



BIASED 
EXPONENT 



in 



64 63 * 



NOTES: 

S ■ SIQN BIT (0 = POSITIVE, 1 = NEGATIVE) 
A = POSITION OF IMPLICIT BINARY POINT 

I = INTEGER BIT OF SIGNIFICAND; STORED IN TEMPORARY REAL, 

IMPLICIT IN SHORT AND LONG REAL 
EXPONENT BIAS (NORMALIZED VALUES): 

SHORT REAL: 127 (7FH) 

LONG REAL: 1023 (3FFH) 

TEMPORARY REAL: 16383 (3FFFH) 



Figure 15. Floating Point Data Formats 



to the 8087. In addition to real format numbers* the 
8087 automatically converts to and from external 
variables stored as 16, 32 or 64-bit integers, or 80-bit 
binary coded decimal (BCD) numbers. 

Memory requirements also increase as precision in- 
creases. Whereas a short real number requires only four 
bytes of storage (32 bits), a long real number requires 
eight bytes (64 bits) and a temporary real number ten 
bytes (80 bits). In many floating point processors, pro- 
cessing time also increases dramatically as precision is 
increased, making this another consideration in the 
choice of precision to be used by a routine. The dif- 
ferences in 8087 processing time among short real, long 
real and temporary real numbers are insignificant com- 
pared to the processing time, however, since all opera- 
tions are performed to the internal 80-bit precision. This 
makes the choice of which precision to use in an iAPX 
86/20 system a function only of memory limitations 
and precision requirements. 

Double precision numbers were chosen for this graphics 
implementation because they allow a very wide range of 
numbers to be represented with high precision. This is 
important, since the package allows the user to magnify 
small parts of defined figures. Without the precision 
gained by using double precision numbers, the image of 
the object could easily be distorted under such scrutiny. 



Three-Dimensional Figure Description 
and User Interface 

The graphics user interface implemented in this note is 
both functional and simple. It does not require the use 
of specialized three-dimensional input hardware. All in- 
put data is keyed in through the keyboard. 

The package allows for definition of figures for future 
use within the graphics package. This feature could be 
useful in generating multiple views of a certain object. It 
requires that the object be "defined" at the beginning 
of the session, but then allows the user to view the ob- 
ject from any location, with any rotation, scale, or 
translation. 

Commands to the graphics package consist of a set of 
alphanumeric commands followed by the necessary 
numeric constants. To enter commands to the graphics 
package, one enters an alphanumeric command en- 
closed within the single quotes followed by the ap- 
propriate numeric arguments. The maximum number of 
arguments required by any command is six. If less than 
six arguments are entered on a line, the line must be ter- 
minated by the V character, however. These re- 
quirements (having the command enclosed within single 
quotes, explicitly terminating the line) are a result of us- 
ing the list-directed input format of FORTRAN. 



3-226 



AFN-02185A 



AP-144 



The commands recognized by the graphics processor 
are: 

comment argl. This command instructs the 
graphics processor to ignore the next argl lines. 
This can be used to insert comments within the 
graphics commands. 

define argl. This command instructs the graphics 
processor that the next N lines (up to the enddef 
command) are to be entered into an internal buf- 
fer for future reference as figure argl. The 
graphics commands are not interpreted, i.e. they 
do not cause figures to be drawn as they are 
entered. In this way, three-dimensional objects 
may be defined, or to put it another way, placed 
into an internal display list. Up to ten objects may 
be defined using the current version of the pro- 
gram. This may be increased to the limits of 
available memory. Currently there is internal 
storage space for up to 500 total graphics com- 
mands. These may be spread in any combination 
among the ten figures. This number may also be 
modified to reflect memory restrictions. 

enddef. This command terminates a figure defini- 
tion, and returns control back to the main 
graphics processor. 

call argl. This command causes the graphics pro- 
cessor to fetch graphics commands from the inter- 
nal buffer of the previously defined figure number 
argl. 

line argl arg2 argS arg4 argS arg6. This command 
causes a line to be drawn in three-dimensional 
space from the point argl, argl, argS to the point 
arg4, arg5, arg6. The current object rotation, ob- 
ject scale, object translation, viewer location, win- 
dow, and viewport are used. 

plot argl argl argS arg4. This command causes a 
line to be drawn from the endpoint of the last line 
plotted to the point argl, argl, argS using the 
"pencode" arg4. The current pencodes supported 
are *2* (indicating that a solid, line is to be drawn), 
and '3' (indicating that no line is to be drawn; this 
is used only to change the location of the plot 
head). Additional pencodes could be implemented 
allowing for dashed lines, dotted lines, etc. 

ident. This command causes the "current" matrix 
to be set to the identify matrix. This causes all 
rotates to be set to zero, all translates to be set to 
the origin, and all scales to be set to one. 

push. This command causes the current matrix to 
be pushed onto a 10 location matrix stack. The 
current matrix is not altered. 



pop. This command causes the matrix stack to be 
popped into the current matrix. 

rotate argl argl arg3. This command causes the 
viewers perception of the three-dimensional 
figure to be rotated around the X, Y, and Z axis 
by argl, argl and arg3. The angles are in degrees. 
The definition of an object is not altered. 

translate argl argl arg3. This command causes the 
viewer's perception of the three-dimensional 
figure to be translated in the X, Y, and Z direc- 
tions by argl, argl and arg3. Again, the definition 
of an object is not altered. 

scale argl argl arg3. This command causes the 
viewer's perception of the three-dimensional 
figure to be scaled in the X, Y and Z directions by 
argl, argl, and arg3. 

window argl argl. This command sets up the win- 
dow parameters. These parameters determine the 
visible side to side portion of the projected images. 
This amounts to placing an infinitely tall pyramid 
within three-dimensional space with the viewing 
location located at its apex (looking down). All 
objects within this pyramid will be visible; all ob- 
jects outside this pyramid will not be visible. 

viewport argl argl arg3 arg4. This command sets 
up the viewport parameters. These parameters 
determine the size and location of the above win- 
dow on the plotter surface. The center of the area 
on the plotter surface is given by argl, argl with 
the X and Y half sizes given by arg3, arg4. The 
plotter is assumed to have an X dimension be- 
tween 0 and 12, and a Y dimension between 0 and 
10. The translation to the dimensions the plotter 
recognizes is done in a lower level plotter interface 
routine. By performing this task in a lower level of 
software, the package is made more general. 

viewpoint argl argl arg3 arg4 arg5 arg6. This 
command sets up the "viewing", transformation. 
argl, argl, arg3 represent the location of the 
viewer in three-dimensional space, while arg4, 
argS, qrg6 represent the "lookat" location in 
three-dimensional space. Together they form a 
vector pointing to the area to be viewed whose 
length determines the perspective variables (only 
single point perspective is currently implemented). 



3-227 



AFN-02185A 



AP-144 



/ 



zclip argl arg2. This command sets up the 
"Z-clipping" parameters. These determine the 
visible distance in front of the viewer. Argl 
specifies the near boundary of the viewing area 
while arg2 specifies the far boundary of the area. 
Together with the window command, it defines a 
solid delimiting the visible objects from the not- 
visible objects. 

cube argl argl argS arg4 arg5 arg6. This com- 
mand draws a cube centered at argl, arg2, arg3 
with half-widths of arg4, argS and arg6. 

arrow. This command draws an arrow from 
(0,0,0) to (1,0,0). 

pyramid argl arg2 arg3 arg4 argS arg6. This com- 
mand draws a four-sided pyramid whose base is 
centered at argl, arg2, arg3 and whose half-widths 
are arg4, arg5 t arg6. The X half-width arg4 is used 
as the height of the pyramid. 

current. This command prints the current matrix 
on the terminal. 

printdef. This command prints the definition of 
the given figure. 

startt. This command starts the 10 ms timer on the 
iSBC 86/12 board. 

readt. This command stops the 10 ms timer on the 
iSBC 86/12 board and prints the 10 ms count on 
the terminal. 

end. This command stops execution of the 
graphics package, prints the total numbers of 
points plotted and "success!!!" on the terminal, 
and returns control back to ISIS. 

Internal Operation of the Package 

All internal operations are performed using 1 by 4 or 4 
by 4 double precision real matrices. Points are defined 
in 1 by 4 double precision vectors where the first three 
coordinates are used to hold the X, Y and Z location of 
the point. The fourth location is always set to one, and 
is used when the point is projected onto a two- 
dimensional plane. In most cases, the routine perform- 
ing the task outlined is named the same thing as the 
name of the task outlined (within the six-character limit 
imposed by FORTRAN). The order the routines are 
described is roughly the order a line would encounter 
them on its way from existing as a three-dimensional en- 
tity inside the machine to a line drawn on the bed of a 
plotter. All routine names are set in boldface. 



THE CURRENT TRANSFORMATION 

If each object were to be modified whenever a translate, 
rotate, or scale were to be performed, performance of 
the package could be quite slow. In addition, the 
original definition of the figure would be lost (although 
not irreversibly). If there were a method of performing 
these three operations at a single time, allowing the 
original definition of an object to remain unaltered, 
both the performance and ease of use of the graphics 
package would be enhanced. 

One way in which these operations can be combined is 
by using what is called the "current" matrix. The cur- 
rent matrix is a 4 by 4 double precision real matrix. It 
numerically represents any combination of rotates, 
translates and scales in any order. The matrix is 
multiplied by each 1 by 4 point definition vector on its 
way to being plotted. The result of this multiplication is 
a point that has been rotated, scaled, and translated the 
proper amount. If this matrix is the identity matrix, the 
point will pass through unaltered. Thus, the identity 
matrix represents no scaling', translating, and rotating. 
This multiplication is performed in the routine pline 
lines 20 and 21. 

When a rotate, scale, or translate command is inter- 
preted, the current matrix is multiplied by another 4 by 
4 matrix representing only this transformation. Since 
matrix multiplication is not commutative, the order 
these operations are performed in is preserved. This is 
important, because, for example, a rotate before a 
translate is not the same as a rotate after a translate 
because all rotations are performed pivoting around the 
origin (see Figure 16). Initially, the current matrix is set 
to the identity matrix. The first operation is performed 
relative to state of the current matrix immediately 
preceding the operation. 

Parameters are set up into the current matrix through 
the rotate, scale, translate, ident, push, and pop opera- 
tions. Each name describes the function of the opera- 
tion performed. The routines performing these tasks (in 
order) are: rotate, scale, transl, ident, push, and pop. 
Ident is included to allow all rotates and translates to be 
set to zero and all scales to be set to one. The push and 
pop operations are included in order that figures may 
save the state of the current matrix, while subsequently 
performing operations altering it. This is important 
when a large figure is defined as a set of parts, each of 
which may merely be rotations, etc., of a simpler list of 
parts. 



3-228 



AFN-02185A 



AP-144 




THE VIEWING TRANSFORMATION 

Before an object can be plotted, the viewpoint of the 
viewer must be known. This information provides the 
location of the viewer in three-dimensional space, and 
the direction the viewer is pointing. It is incorporated in- 
to the 4 by 4 "view" matrix. It is another rotation per- 
formed on the object in order that it is viewed from the 
proper viewing angle. All points are passed through the 
view matrix after they are passed through the current 
matrix. What comes out of these two transformations is 
a set of points located in the proper relative positions in 
three-dimensional space when the figure is rotated, 
translated, and scaled by the operations performed on 
the current matrix, and is also rotated properly by the 
operations set in the view matrix. 

The view matrix is set up by the viewpoint command. 
This command will place in the view matrix the proper 
rotations in order that the image of the object will be 
correct. The routine performing this task is the viewpn 
routine. 

Z-CLIPPING 

All points passed through the current and view matrices 
are located at their proper locations in three- 
dimensional space. However, only a portion of this 
space is visible to the viewer. Specifically, objects 
behind the viewer will not be visible. Every point of an 
object has been mapped to the viewer's space, however, 
including those behind the viewer. These * 'invisible* ' 
points are removed by an operation called 



"Z-clipping." Simply, it examines the Z parameter of 
every point being considered and determines if it is in 
front of the viewer. In addition, one may not wish to 
display lines a great distance from the viewer. These 
lines may be removed by a similar process. The only 
complication of clipping is the action performed if only 
part of the line is visible. In this instance, the point 
where the line leaves the visible area must be calculated. 
The method used to calculate this point in this im- 
plementation is the method of "like triangles.' ' 

The Z-clipping parameters are set through the com- 
mand zclip in the routine zclip. The arguments to this 
command are used to determine the visible distance in 
front of the viewer. The first argument sets the 
minimum distance in front of the viewer before any line 
will be visible. Legal values for this parameter are 
anything greater than zero. The second argument sets 
the far distance beyond which no lines will be visible. 
Any value larger than the first argument may be used 
for this parameter. The clipping itself is performed in 
the routine zclipp. 



3-229 



AFN-02185A 



AP-144 



PROJECTION 

Projection maps the three-dimensional points previous- 
ly encountered and projects them onto a two- 
dimensional plane. Only single-point perspective is cur- 
rently supported in the package. Here, the projection is 
performed by using the Z parameter to modify the X 
and Y parameters. As the points get more distant, their 
deviation from the center of the picture should get 
smaller, if the X and Y parameters remain constant. 
Most people are aware of this effect. For example, if 
you look down a set of railroad tracks, the rails seem to 
converge, even though the distance between the rails is 
constant (see Figure 17). Two or three-point perspective 
would be easy to implement; all one must do is generate 
the projected X and Y parameters by using the non- 
projected X and Y parameters in addition to using the Z 
parameter. 

This projection is performed in the graphics package by 
multiplying the 1 by 4 point location vector by a 4 by 4 
"projection" matrix. This matrix is simply the identity 
matrix except the perspective value is placed in location 
(3,4) of the matrix. 




Figure 17. Two Rails, Vanishing into the Distance 

This value is calculated from the viewpoint parameters. 
After the matrix multiply, the only element modified in 
the 1 by 4 point definition vector is the last one (the one 
which is supposed to have the value of one). After the 
multiplication, this location will contain the number 
representing the modification which must be performed 
on the X and Y parameters of the vector to exhibit the 
projection. When this vector is "normalized," the point 
will have been projected using the rules of single-point 



perspective. This normalization is performed by 
dividing every element in the vector by the last element 
of the vector. Thus, the Z element of the original vector 
has modified the X and Y elements. If two or three- 
point perspective is desired, one must only place 
perspective values in locations (1 ,4) and (2,4) of the pro- 
jection matrix; all subsequent processing will be iden- 
tical. The routines performing these operations are: 
viewpn (sets up vanishing point for perspective), projct 
(sets up the projection matrix, and performs the 
perspective multiplication), and norm (normalizes the 
vector). 

X-Y CLIPPING 

Once the data is projected onto a two-dimensional 
plane, X-Y clipping must be performed. This operation 
could also be performed on the three-dimensional data, 
but by deferring it until after the data have been pro- 
jected, the calculations required are simpler. This is not 
true for Z-clipping, since once the, data are projected 
onto a plane, the Z parameter is no longer in its original 
form. 

X-Y clipping is performed by comparing X and Y 
parameters with the window values set up by the win- 
dow command. This comparison is a bit more com- 
plicated than the comparison required by Z clipping, 
however, as two clipping parameters are involved. 
There are nine possible regions in which each endpoint 
of a line may reside. For example, some of these regions 
are: within the X and Y window regions, less than the X 
window region but within the Y region, less than the X 
region and less than the Y region, etc. If one or both of 
the endpoints of the line are within the visible region,