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vi Field Engineering 


Theory-Maintenance 


-System/3 Model 6 
5406 Processing Unit and Attachments 


SY34-0022-1 


Second Edition (February 1971) 


This is a revision of, and obsoletes SY34-0022-0. Changes and corrections were made to 
-all chapters and sections. The basic content and format remain the same. 


Within this manual, System/3 machines made for use in the United States are referred 
to as domestic machines, machines made for use in countries other than the United 
States are referred to as World Trade machines. 


Changes to the information in this manual will be reported in subsequent revisions or 
supplements. 


Copies of this and other IBM publications can be obtained through IBM Branch Offices. 


A form for readers’ comments is provided at the back of this publication. If the form 
has been removed, send your comments to IBM Corporation, General System Division, 
Systems Publications, Department 707, Boca Raton, Florida 33432. 


©Copyright International Business Machines Corporation 1970, 1971 


TNL SN34-0043 to SY34-0022-1. 


Preface 


This manual is a combined theory-diagram and maintenance manual for the 


5406 Processing Unit. It is divided into eleven sections, and with the follow- 


ing exceptions it is a self-contained manual: 


1. Sections 2 through 6 are the diagrams for the processing unit, and 
must be used in conjunction with the Field Engineering Theory of 
Operations Manual, JBM System/3 Model 6 5406 Processing Unit, 
Order No. SY34-0023. 

2. Section 8 is the disk file attachment manual which is a separate 
theory-diagram manual. The Field Engineering Theory-Diagrams 
Manual UBM System/3 5444 Disk Storage Drive Attachment, Order 
No. SY34-0021) can be inserted, in sequence, in this manual. 

3. The binary synchronous communications adapter (BSCA) and serial 
input output channel (SIOC) feature attachment manuals are separate 
theory-diagrams manuals which are also required if these features are 
present on the system. 


The eleven sections of the manual are as follows: 


Section Title 

] System Maintenance 

Z Error Conditions 

3 Data Flow 

4 Functional Units CPU Sections 
5 Operations 

6 Power and Cooling 

d Keyboard and Console 

8 Disk File Attachment (separate saaitial) 

9 Printer and Ledger Card Device Attachments 
10 Data Recorder Attachments 


11 CRT Attachment 


Other manuals necessary to understand and service the IBM System/3 
Model 6 are: 


1. Field Engineering Parts Catalog, JBM 5406 Processing Unit, Order 
No. S134-0001 

2. Field Engineering Maintenance Diagrams, JBM System/3 Serial I/O 
Channel Attachment, Order No. SY31-0275 

3. Field Engineering Maintenance Diagrams, JBM System/3 Binary 
Synchronous Communications Adapter, Order No. SY31-0258 

4. Field Engineering Theory-Maintenance Diagrams, JBM 5496 Data 
Recorder Online Feature, Order No. SY31-0279 

5. Field Engineering Theory-Maintenance Manual, Elastic Diaphragm — 
Encoded Keyboards, Order No. SY27-0073 


| 6. Maintenance Library Theory-Maintenance Manual, [BM 2222 Printer 


Models I and 2, Order No. SY24-3585 


5406 FETMM = (6/71) li 


Abbreviations 
AAR A field Address Register 
ALD Automated Logic Diagram 
ALU Arithmetic Logic Unit 
ARR Address Recall Register 
BAR B field Address Register 
BSCA Binary Synchronous Communications Aaunte: 
BSM Basic Storage Module 
CPU Central Processing Unit 
CR Condition Register 
CRR Condition Recall Register 
CRTAR CRT Address Register 
DA Device Address 
DBI Data Bus In 
DBO Data Bus Out 
DFCR Disk File Control Register 
DFDR Disk File Data Register 
DPF Dual Program Feature (not used on the 5406) 
DRAR Data Recorder Address Register 
DRR Data Recall Register | 
EBCDIC Extended Binary Coded Decimal Interchange Code 
IAR Instruction Address Register 
I/O Input—Output 
K Thousand 
LCD Ledger Card Device 
LCR Length Count Register 
LCRR Length Count Recall Register 
LLAR Locate Line Address Register 
LSR Local Storage Register 
MAP Maintenance Analysis Procedure 
MST Monolithic System Technology 
PC Parity Check | 
PCAR Print Command Address Register 
PDAR Print Data Address Register 
PG Parity Generate 
POR Power On Reset 
PSR Program Status Register 
SAR Storage Address Register 
SDR Storage Data Register 
SIOC Serial Input Output Channel 
XR Index Register 


Contents 


Section 1. 


Chapter 1. 
Chapter 2. 
Chapter 3. 
Chapter 4. 
Chapter 5. 
Chapter 6. 


Section 2. 


System Maintenance 


Reference Data Be. dee ok? & 
Console and Maintenance Facilities . 
Preventive Maintenance . 
Checks, Removals, and Adjustment . 
Power and Cooling 

Locations 


Processing Unit 


Error Conditions . 


Section 3. 


Processing Unit 


Data Flow . 


Section 4. 


Functional 


Section 5. 


Operations . 


Section 6. 


Processing Unit 


Units . 


Processing Unit 


Processing Unit 


Power and Cooling .. 


Section 7. 


Chapter 1. 
Chapter 2. 
Chapter 3. 


Section 8. 


Chapter 1. 
Chapter 2. 
Chapter 3. 


| Section 9. 


_ Chapter 1. 
Chapter 2. 
Chapter 3. 
Chapter 4. 
Chapter 5. 
Units 
Chapter 6. 


Keyboard and Console 


Introduction 
Functional Units . 
Operations . 


Disk Storage Drive Attachment (separate manual) 


Introduction 
Functional Units . 
Operations . . 


Printer and Ledger Card Device Attachments 


Printer Attachment Introduction 

Printer Attachment Functional Units 

Printer Attachment Operations 2 £ 
Ledger Card Device Attachment Introduction 
Ledger Card Device Attachment Functional 


Ledger Card Device Attachment Operations . 


. 1-101 


1-201 
1-301 
1-401 
1-501 
1-601 


2-010 
3-010 


4-010 


_ §-005 


6-010 


7-101 
7-201 
7-301 


8-101 
8-201 
8-301 


9-101 
9-201 
9-301 
9-401 


9-501 
9-601 


Section 10. Data Recorder Attachment 


Chapter 1. Introduction 
Chapter 2. Functional Units . 
Chapter 3. Operations . 


Section 11. CRT Attachment 


Chapter 1. Introduction 
Chapter 2. Functional Units . 
Chapter 3. Operations . 


TNL SN34-0043 to SY34-0022-1 


. 10-101 
. 10-201 
. 10-301 


. 11-101 
. 11-201 
. 11-301 


5406 FETMM 


(6/71) 


iti 


PROCESSING UNIT AND ATTACHMENTS-—Legend (Part 1 of 2) 


Legend 
Ready] ,) | (not) Ready Negator inverts logic on 
positive logic diagrams 


"A" and "B" must be 
active for "C" to be 
active 


Minus polarity 





"D" or "E" active 
causes "F" to be active 





Latch Name 


Set On Output 





Flip flops or flip 
latches that are 
shown on another 
diagram 





Ald Location 


Parity Check 


on Bus Line 










Parity Generator 
: (Correct parity is 

generated. ) 

Input to 0 

bit only Indicators 
\ There are 8 latches 
{0 in register (0 through 7) 
Input bus to 
all bits 


All bits transfer out 


Only bit 7 


transfers out 


Register Reset 


Diag x-x Off-Page Connector 


\/O IF Interface Connector 
> No connector shown 


Diag X-X on referenced page 


Amplifier 


ee ea Indicator 
f 


On-Page 
Connector 


On-Page | 
yO Connector 


A note is shown 
this way ona 
diagram 


Joining Lines 


Lines cross over 


but do not join 


8 lines on bus 
bits 0,1,2,3, 
4,5,6 and 7 


ae 6 AR 
(0-7) 


Boolean Algebra Symbols 


® Ina line name means "And" 


+ Ina line name means "Or" 


(xx - - - x) Indicates a line name that 
does not exist as an actual 
ALD name, but used to better 
explain the function of a 
line or block 


Arithmetic Logic Unit 
(located in the CPU) 


2.5 usec Single Shot 


Cr D A positive shift on 
Py Ss "C" causes a 2.5 
usec shift on "D" 


Exclusive OR 
Either "A" or "B" 


A C must be active for 
B OE "C" to be active, 
but if both are active 


or neither active 
"C" will be inactive. 








5-40A6 Read 


Fase line originates 


on Diagram 5-40 at zone coordinates 


Aé. 


Punch 5-41B3 





A 


Indicates line enters Diagram 5-41 
at zone coordinates B3. 


Indicates 8 duplicate circuits. 





Indicates a shift is required after 
the gate pulse is present. 

* Indicates a point that can be 
scoped on back-panel pins. 


5406 FETMM = (6/70) iv 


Decision Block on 
a Flowchart 
(Asks a question) 


Indicates the func- 

oa tion described can 
be found in the ALDs 
on this page 


— Processing block on 


a flowchart 


"Print' 


Single quotes in the 

block indicate a line 
name, flip latch, or 
flip flop name 


Terminal ona 
flowchart 


Keying Operation on 
Flowchart . 


Note ona 
Flowchart 


Or 


Refers to another 
Flowchart 


Legend 
REGISTER (REG) 


e Aregister is a functional logic block consisting of a group of associated triggers (TR) 
with common lines such as reset (R), contro! (C), etc. Common gates may also be 
included. 

@ Common Section. 

Contains lines common to one or more logic elements. 


e Data Section 


The inputs and/or outputs shall be grouped and shall be interconnected with lines 
and connecting symbol. | 


e Name 


The common section shall have the name “REG”. 


Examples: 





C 


B 


A 


E iz CRM 


PROCESSING UNIT AND ATTACHMENTS-—Legend (Part 2 of 2) 














DECODER (DCD) 


A functional logic block in which inputs and outputs are assigned numeric values. 
An output line is active when and only when its value (number) is equal to the 
sum of the values of all active input lines. 


Note: At any given time there is only one sum. If all input lines 
are inactive, the sum Is zero. 


Common Section. 

When gating is used, the gating line and gated line shall be cross-related by labeling 
with a letter, rather than a numeral. These common lines shall be drawn to the 
common section. The common section is not used if there are no common lines. 
Data Section. 

The inputs to a decode block shall be number 1, 2, 4, 8, 16, etc. The outputs 
shall be numbered to reflect the sum of the active inputs required for each 

decode output. 


Name 


The common section (when used) shall have the name *‘DCD”’; when the common 
section is not used, the data section shall have the name ‘’‘DCD”. 


Example 1: Decoder without gating. 





0 
1 
2 
3 
4 
5 
6 
7 


5406 FETMM = (6/70) Vv 








Section 1. System Maintenance 


This section of the combined theory-maintenance manual (FETMM) contains 
the maintenance procedures for the 5406. It is divided into six chapters as 
follows: 


Chapter 1. Reference Data 

Chapter 2. Console and Maintenance Facilities 
Chapter 3. Preventive Maintenance 

Chapter 4. Checks, Adjustments, and Removals 
Chapter 5. Power and Cooling 

Chapter 6. Locations 


2265 Model 2 
Display Station 


5496 Model 1 
Data Recorder 


Contents 


Chapter 1. Reference Data 1-101 


Instructions 1-101 

Instruction Codes and Addressing Schemes 1-102 

Instruction and Machine Cycles 1-103 

Test I/O and Branch Instruction 1-104 

Load I/O Instruction 1-105 

Start I/O Operation 1-106 

Sense Instruction (3 Parts) 1-107 through 1-109 

I/O Control Fields 1-110 

CPU Sense and Condition Code Response 1-111 

Condition Register Settings and Hexadecimal and Decimal 
Conversion Chart 1-112 | 

Hexadecimal Addition and CPU Timing 1-113 

Local Store Registers and Data Flow 1-114 

Cycle Pattern, Data Storage and Sign Control 1-115 

Code Conversion Chart (2 Parts) 1-116, 1-117 

CRT Code Conversion Chart 1-118 

Tie-Down List 1-119 


5213 Model 1 
Printer | 





5444 Disk Storage Drive (2) 


SYSTEM MAINTENANCE—Contents 


5406 Processing Unit and 
Console Keyboard 


BR0435 


Chapter 2. Console and Maintenance Facilities 1-201 


Integrated Maintenance Package 1-201 

System Console (2 Parts) 1-202, 1-203 

Field Engineer Console (4 Parts) 1-204 through 1-207 
Special Tools (2 Parts) 1-208, 1-209 

Alternate Program Load Device (2 Parts) 1-210, 1-211 


Chapter 3. Preventive Maintenance 1-301 


Preventive Maintenance Chart 1-301 


Chapter 4. Checks, Adjustments, and Removals 1-401 


Storage Module (11 Parts) 1-401 through 1-408C 
Keyboard 1-409 

Single Shots 1-410 

5444 Disk 1-411 

5496 Data Recorder 1-412 


Chapter 5. Power and Cooling 1-501 


Power Input, Output, Sequencing, and MST Regulators 1-501 
—4 Volt and +6 Volt Power Supplies 1-502 
Power Supply Test Points 1-503 


Chapter 6. Locations 1-601 


Covers and Panels 1-601 

Logic Gates 1-602 

Power Supplies 1-603 

Power Controls 1-604 

Power and Cable Channel 1-605 


Appendix A. Special Circuits 1-Al 


Appendix B. World Trade 1-Bl 


5406 FETMM 


(2/71) 


1-i 


SYSTEM MAINTENANCE-Safety | _* , 5406 FETMM (6/70) _—i1-ii 


Safety 


PERSONAL SAFETY 


Ensure your own safety by making it an everyday practice to use caution at 
all times and by being aware of potentially dangerous areas of the machine. 
Be sure to read and follow the safety suggestions in Form No. 229-1264, a 
pocket-sized card issued to all 1BM Customer Engineers. 

Remember: 


@ Loose clothing can become entangled in moving parts of the machine. 


@ Drive belts, because of their internal cable construction, can cause serious 
injury. Do not crank a machine by pulling on the drive belts. 


@ Heat sinks are at an electrical potential. Do not short heat sinks to each 
other or to the machine side frame. | 


e Always unplug machine power and wait one full minute before attempt- 
ing repairs or adjustments in the power supply area. 


e Voltages developed in the resonant circuit of regulating power supplies 
are apt to be much greater than the line voltages. 


e Follow the specific safety precautions that accompany many of the 
adjustment procedures in this manual. 


EQUIPMENT SAFETY 


Electrical 


Always replace blown fuses with fuses of the same type and rating. Using 

fuses of a different type or higher rating could result in component damage. 
Remove power from the machine before replacing MST cards, magnets, 

or solenoids. Failure to do this could result in damage to a card being replaced 

or to other cards in the net. 


Mechanical 4 


Do not operate the machine under power with units disassembled, removed, 
or maladjusted. Keep tools clear of the mechanism when the machine is 
operating under power. 


CAUTION 


Do not use IBM cleaning fluid on plastic parts. 


Chapter 1. Reference Data 


This section contains charts, listings, and diagrams giving general information 
for diagnosing system failures. 

The following sections of this manual (sections 2 through 11) contain the 
flowcharts, timing charts, and diagrams for the central processing unit and 
attachments, The reference material found in this chapter is a collection of 
the most frequently used data found in these chapters. For more detailed 
information on any of the data found in this chapter, refer to the chapter 
that fully explains the area that you are working on. 

For diagnostic techniques, refer to the maintenance analysis procedures 
(MAP) chart user’s guide. The MAP charts help to isolate machine troubles 
without the use of an oscilloscope. 


SYSTEM MAINTENANCE~-Reference Data 
Instructions 


SC 






Two Address 
Instruction 


Zero and add zoned 

Add zoned decimal 
Subtract zoned decimal 
Move hex characters 
Edit 

Insert and test characters 
Move characters 
Compare logical characters 
Add logical characters 
Subtract logical characters 























Opi direct, Op2 direct 
Op1 direct, Op2 indexed by XR1 
Opi direct, Op2 indexed by XR2 
Op1 indexed by XR1, Op2 direct 











Op1 indexed by XR1, Op2 indexed by XR1 
Op1 indexed by XR1, Op2 indexed by XR2 
Op1 indexed by XR2, Op2 direct 

Opi indexed by XR2, Op2 indexed by XR1 






Op1 indexed by XR2, Op2 indexed by XR2 


Sense 1/O 
Load 1/O 
Store register 

Load register 

Add to register 

Test bits on 

Test bits off 

Set bits on 

Set bits off 

Move logical immediate 
Compare logical immediate 













One Address 
Instruction 
(Non-Branch) 




















Opi direct 
Op1 indexed by XR1 
Op1 indexed by XR2 
Branch on condition 
Test |/O and branch 
Load address 















One Address 
Instruction 
(Branch) 













TIO 
LA a palin 
Bit 7-XR1 





Op2 direct 
Op2 indexed by XR1 
Op2 indexed by XR2 












Command 
Instruction 


Halt program level 


HPL i 
APL re NU Advance program level 







Number of Jump on condition 
bytes to jump 
Control 









Start 1/O 






BRO610 


5406 FETMM 


(6/70) 


1-101 


SYSTEM MAINTENANCE-—Reference Data 5406 FETMM (6/70) as 
Instruction Codes and Addressing Schemes 





Op Code Q Operands Total Type 
(one byte) Code Instr 
ae Bits 4-7 One First Second een 
Byte 


EE pAjeleciolel er. 
Gp WY, 3 
s - en dene 
= WY he 
ptt tf = 2 Bytes 1 Byte Disp. 
: - ty Index by XR1 
Direct 1 Byte Disp. 
a Es en reve {| zy iret 
YM YY YY Lp WY) Vy 
TT l, Diy | oven amo 
|G yy YY YY YY Ys YY Index by XRI 


YUIMIICZIJ| (IYI. 
) YY a Index by XR2 








NS 
N 
N 


YJ 


reach CoPN 
nearetobatonete 

ecateteces atetetotePeresotetevetarssetes LALA fs rans 
neParateteconascotesee Pot etenstenecateconsvebeonesetessrecasscarescbereteconevetotesetate 





By XR1 


1 oParelelelese_ 0.0.0. 0-0,0-0°000.0,0,0,0, 0.0.0. 


ee ee ete 
tj, Uy YY YWJJUYVJ_ 
GGe 8: <8 =" 5 
Oe oan ee 


2 Bytes Direct 


1 Byte Disp. 
index by XR1 


YY MY: 
7 LL oe LL LLL 


1 Byte Disp. 
Index by XR2 


Indexed 


Yj 


eotatat ete’ 
ontetatatee 


abe Y/j YA 





fj 
lvocoreveseDetehetetetetets 
rece c oreo ouen ea eststeecta ts aes, atatatatetetatere' ee 
0. 0.@. 0.0 0 6.6.6.6 .8 0.0 E68 8 8.2 0.0.0 8.9, 
| es esos tc tatatatat savanenenetatonere Renesas tsta tata Petatetete’ 


By XR2 


2 Bytes Direct 
1 Byte Disp. 
Index by XR1 





1 Byte Disp. 
Index by XR2 


pice 


Legend 
OP BITS 0123 


NN X 2address instruction (can 
\ be indexed by bits O—3) 


Z 1-address instruction (can Command instruction 


be indexed by bits 2 and 3) 


Y 1address instruction (can 
be indexed by bits 0 and 1) 





BRO611 


x 


x xX X X 
x xX KX XK 
x xX KX XK 
x X xX XK 
x xX K XK 


xxxxxxx x x 
xx xxXxxXxXXxX XX 
xxxxxxxxx 
xx xxx xxx 
xxxxxxXxXXxX 
xxxxxxxxx 
xxxXxXxxX*KXK 
xx xxxxxx x 
xxxxxxXxxXxxX.X 
xxxxxXxxXxXXxX®X 
xxxxxxXxxxex 
xxxxxXxxxXxX SX 
xxxxxxxx x 
xxxxxxxxx x 


x KX KX KK KK KK XK 
x KX KX KX KX KK KK XK 
x KK KX KK KX KK XK 
x KX KX K KX KK KK XK 
x KX KX KK KX KX KK XK 
x xX KX KK KX K KK K 


x KX KK KK KK KX XK 
«KK KX K KK KX KK K 
“KK K KK KK KK XK 
x KX KX KK KX KK KX XK 
x KX KX KK KK KK XK 
x XK KKK KX KK XK 
x KX KK KK KK KK RK 
x KX KK KK KX KX KX XK 
x KX KX KX KK KK K XK 
x KK KX KK K KK XK 
x KX KK KK KX KK X 
x KX KX KX KX K KX KX K XK 
x KX KX KX KK KX KK XK 


x KX KX KX KX KK XK 
x X KX KX KX K XK XK 


Xx 
X 
X 
Xx 
x 
Xx 
x 
Xx 


x xxx x x x x 
x xxxx x xX 


Xx 
x 
x 
x 
x 
x 
x 
x 


xX x x x 


x KX KX KX KX KX KK KK 
x KX KX KX KX KR KX K KX XK 
x KX KX KX KK KK KX RK 
x KX KX KK KX KK K RK 
x KX KX K KK KK K XK 
x xX KX KX KX KX KX KK EK 
x ~ KX KK KK KK RK 

x 

x 

x 
x KX KK KKK KX KX KX XK 
xX KK KK KK KX KX KX RK 
x KX KX KK KK KX KK XK 
x KX KX KX KK KX KX KK XK 


x “xx xxx xXxX xX XK 
xxx xxx xxx xX®E 
x xxx xx «KK xX XK SX 
xx x«xxKMKKX KK MK 


x «xx KKK KKK KX 
xx xx xx x xXxK KS 
x xxx xx KKK XK 
xxx xxxKx KKK KX 
<x K KK KK KK KK KM 


x KX KX K XK 
x KX KX KX XK 
x KX KX KK KK KX K XK 


x xxxx xx x xX xX 
xxxxxx x x xX & 
x xxx xxx KX xX 
x xxxXxx x xX x xX x 
xxx KK KK MX & 
xxx xx xX xX xX xX X 





BRO612 


SYSTEM MAINTENANCE -Reference Data 
Instruction and Machine Cycles | | ~ 5406 FETMM -— (6/70) 1-103 


SYSTEM MAINTENANCE-—Reference Data 
Test.1/O and Branch Instruction 













Op Code OQ Code Address Op Code Q Code D1 Indexed 


Tz [oa [uN | Opera 


XX 













C1 2 Bytes Direct Addressing (H1L1) 
D1 1 Byte Indexed by XR1 
E1 1 Byte Indexed by XR2 


Device Address Serial Printer 


Selects Printer 
Unit Check 

~ End of Forms 
Busy 
Busy or End of Forms | 
Element at Left Margin 
End of Forms or Element at Left Margin 
Element at Left Margin or Busy 
End of Forms, Element at Left Margin or Busy 
Selects LCD 
Unit Check 

: Last Printable Line 
LCD Busy 
- LSR Busy 
Read ID Busy 
Card Not Aligned | 
XXXXKIXXXX Branch to address if condition met 


Se Weal cccetlen Nees ot Device Address Data Recorder 
9496 M bit is not used, it should be zero. 
Data X1X Busy 
Recorder XOX 1/O Check or Not Ready 
| XXXXK IXXXX Branch to address if condition met 
2265 M Bit is not used, it should be zero. 
CRT X1X CRT Busy 
XOX CRT Check (D Reg Parity Error or CRT Not Ready) 
XXXX |XXXX Branch to address if condition met 


5406 1. Le Device Address Keyboard 


Keyboard Test 1/O is invalid and will result in 
invalid Q byte processor check. 


: oo 
5444 
File 


5213/ 
2222 
Printer 
















8 | | |_| | bwiee addres rive? (Spiaiet) = 


M bit is not used. 

Not Ready or Error 
Busy-Data Transfer in Process 
-Scan Found. 


M bit is not used. 

Not Ready/Unit Check 
Op End Interrupt 

Busy 


ITB Interrupt 
Interrupt Pending 


M bit is not used. 
SIOC Not Ready 
SIOC Busy 





Note: An X means bit can be a "1" or “0”. 
BRO614A 





5406 FETMM 


(2/71) 


1-104 

















Op Code QO Code Address 


Sd 


11] 12 113 15]16 
2 Bytes 
1 Byte 
1 Byte 


ee orig: Device Address Serial Printer 


Selects Printer 


Op Code OQ Code 


Direct Addressing (H1L1) 
Indexed by XR1 
Indexed by XR2 





















Selects LCD 

LLAR 
9213/ Control LIO 
2222 PDAR 
Printer 





Device Address Data Recorder 


M bit is not used, it should be zero. 
DRAR 
ba. Device Address CRT 


5496 
Data 
Recorder 






a 
CRT M bit is not used, it should be zero. 

ps CRTAR 
Device Address Keyboard 


5406 M bit is not used, a zero is preferred. 
Keyboard Turn Off Command Lights 

Turn On Command Lights _ 

Turn On/Off Field/Operation Lights 


fee te Device Address Drive 1 (Spindle 0) 
er ean Device Address Drive 2 (Spindle 1) 


M bit is not used. 
5444 | ee 
Disk nvalid 
Invalid 
Diagnostic CE 
DFDR 
Invalid 
DFCR 
Invalid 


Os OO 


MI bit is not used. 
SIOC 001 1/O Function Register 
| 010 SIOC Length Count Register 
100 SIAR 
101 Data Transfer Register 


ee ae (eee eee 


M bit is not used. 
BSCA 001 Stop Address Register 
. 010 | Transition Address Register 
| -100 BSCAR 
110 BSCAR (Diagnostic) 


Note: An X means bit can be a “’1” or “‘0”’. 

















BRO615A 


SYSTEM MAINTENANCE-Reference Data | 
Load I/O Instruction : 5406 FETMM (2/71) 1-105 


SYSTEM MAINTENANCE-~Reference Data. 
Start 1/O Operation 









Op Code Q Code Command 


ea 


12 13 15 
oS 


Device Address Serial Printer 


Selects Printer 
N field is not used, zeros are preferred. 
Serial Print Operation 


2222 
Printer Bi-directional Print Operation 
Selects LCD 

Start 1/O (reads first command byte) 


Read all line finder marks (Diagnostic) 





a a a ae Device Address Data Recorder 


M bit is not used, it should be zero. 
( X01 ReadaCard 
Data X10 Punch a Card 
Recorder X11 Diagnostic Data 
X00 Diagnostic Cycle Steal 
XxXXX| XXxXxX]| Data used in diagnostic data 











Pe [emeranins 
| 2265 
CRT 


M bit is not used, it should be zero. 
X1X Display 
XOX Halt 
“a at Data used in halt 


Device Address Keyboard 





M bit is not used, it should be zero. 

N field is not used, it should be zero. 
5406 CE Diagnostic (Set Interrupt Request) 
Keyboard Reset Parity Check 

Drop Bail (Lock Keyboard) 

Pick Up Bail (Unlock Keyboard) 

Enable Interrupt 

Disable Interrupt 

Turn Off Current Interrupt Request 


[ee ek Device Address Drive 1 (Spindle 0) 


Removable Disk 
Fixed Disk 
000 Control Seek 
001 Read 
Read Data 
-| Read Identifier 
Read Diagnostic 
Read Verify 
010 | — Write 
Write Data 
. Write Identifier 
011 Scan 
Scan Equal 
KAL Scan Low or Equal 
Scan High or Equal 


Note. An X means bit can be a ‘’1”’ or “0”. 





Op Code Q Code Command 


Control 
[| eras! 


8 11] 12 [13 15]1 
ee is, 


M bit must be zero. 
3 | | | | [Pevice Address ioc 


Control 
M bit is not used. 
Always Accepted 
Read 1/O Device 
Write |/O Device 
Reset Interrupt Request 
Enable Interrupt 
Disable Interrupt . 
Reset SIOC Adapter Busy 
Set Interrupt Request 
1/O Control Byte 1 
1/0 1 Select 

SlOc 1/O 2 Select 
1/0 3 Select 
1/O 4 Select 
1/O 5 Select 

1/O 6 Select 

1/O 7 Select 
1/O 8 Select 
1/O Control Byte 2 
1/O Unit 1 Select 
1/O Unit 2 Select 
1/O 9 Select 
1/O 10 Select 
1/O 11 Select 
1/O 12 Select 
1/O 13 Select 
1/O 14 Select 


X000 | 0100 | Start 2 Second Timeout 
Note. An X means bit can be a ‘‘1” or 0". 








Receive 

Transmit and Receive 
Receive Initial 

Auto Call 

Loop Test 

Reset Interrupt Request 
Enable Interrupt 
Disable Interrupt 
Cancel 2 Second Timeout 
Enable Reserved Mode 
Disable Reserved Mode 
Enable Step Mode 
Disable Step Mode 
Enable Test Mode 
Disable Test Mode 
Enable BSCA 

Disable BSCA 





BRO616A 


5406 FETMM 


(2/71) 


1-106 


Keyboard Sense Instruction Printer Sense Instruction 


























Byte 1or3= Operand Address 


Op Code OQ Code Address Op Code OQ Code Byte 2 or 4 = Operand Address -1 


D1 


0 71/8 11712413 15416 XX 
30 2 Bytes Direct Addressing (H1L1) 
70 1 Byte Indexed by XR1 
BO {| 1 Byte Indexed by XR2 
e | ||} Device Address Serial Printer 


Select Printer 

Byte 1 Byte 2 

O Horizontal Cycle Check O Count End Latch 

1 Data Check 1 Print Left Command 

2 Margin Check 2 Matrix Counter Trigger 1 
3 Sync Check 3 Matrix Counter Trigger 2 
4 Ros Check 4 Matrix Counter Trigger 4 
5 Vertical Cycle Check 5 Printer Ready 

6 Primary Carriage EOF 6 SS 2 

7 Invalid Command 7 SS 1 or SS 1 Overlap 


Byte 1 = Operand Address 
Byte 2 = Operand Address —1 





Op Code OQ Code Address 


pve [om [mW [onerna 
0 778 11/12/13 15/16 xx 
30 2 Bytes 
70 ~ 1 Byte Indexed by XR1 
BO 1 Byte Indexed by XR2 
4 M bit is not used, zero is preferred. 
xXX N field is not used, zero’s are preferred. 
5406 
Keyboard 
6 Typamatic Key Identifier 
| | 7 Not Used 
| [000K [000K Operand Address (Sense Byte Destination) 


Byte 1 
Note. An X means bit can be a ‘“‘1"' or ‘‘O”’. 


Op Code OQ Code D1 


Direct Addressing (H1L1) 




























O Parity Check 

1 Data Character Identifier 

2 Command Key Identifier 

3 Function Character Identifier 
4 World Trade Identifier 

5 Keyboard Ready 







Contains the coded 
representation of 
the key position 
that was keyed. 







Byte 4 
O High Speed Latch OSSA 
1 Matrix Output Hammer Dr1 1SS3 
2 Matrix Output Hammer Dr2 2 Stepper Trigger A 
3 Matrix Output Hammer Dr3 3 Stepper Trigger B 
4 Matrix Output Hammer Dr4 43S Z 
5 Matrix Output Hammer Dr5 5SSY — 
6 Matrix Output Hammer Dr6 6 SS X 
7 Matrix Output Hammer Dr7 7 SS W 


pex[ [tar ta 
Tox] [| foarte 
rx] [Pears PR 


Select LCD 
Byte 1 
- QO Sense Amp Check 
1 Card Skew Check 
2 Drive Check 
3 Read Mark Check 
4 
5 Line Finder Mark Check 
6 Card In Switch On 
7 Card Out Switch On 





BRO617A 





5213/ 
2222 
Printer 






































Byte 2 
O Sense Amp 1 

1 Sense Amp 2 

2 Sense Amp 3 

3 Sense Amp 4 

4 Timing Pulse 

5 Drive Check SS 

6 Activate LCD Feed Clutch 
7 Hold Busy SS 


Byte 4 
0 5213 Printer Attached 

1 Not Vertical Forms Control 

2 Not Bi-directional Print Feature 

3 Secondary Carriage EOF 

4 Not Rm sw 7 Slow and Not LM sw 2 Stop 























OSS 1—Skip Line 

1 SS 2—Skip Line 

2 Late Mark 

3 Special Tie Up (always off) 
4 Card Alignment SS 














5 Spare 5 Rm sw 2 Stop or LM sw 1 Slow 
6 Spare 6 Primary or Secondary Forms Motion Contact 
7 Stop Ss 7 Primary Forms Emitter Advance 


| | pooxx] 00x Operand Address (Sense Bytes Destination) . 


* If LCD feature is not installed, then this byte will be hex 00. 


Note. An X means bit can be a ‘’1”’ or “‘0”’. 
BRO618A 


SYSTEM MAINTENANCE-—Reference Data 
Sense Instruction (Part 1 of 3) . . 5406 FETMM. (2/71) 1-107 


SYSTEM MAINTENANCE-Reference Data 
Sense Instruction (Part 2 of 3) 


Data Recorder and CRT Sense Instruction 












Byte 1 = Operand Address 
Byte 2 = Operand Address —1 








Op Code O Code Address 


Wann 
Indexed by XR1 


11112 13 15716 XX 
2 Bytes 
1 Byte 
1 Byte Indexed by XR2 
fie ieee Device Address Data Recorder 


M bit is not used, it should be zero. 

Byte 1 

O Off Line 

1 Transport Jam 

2 Stacker Full, Hopper Empty, or Hopper Jam 
3 Not Used 


Op Code O Code 


Direct Addressing (H1L1) 
































yte 2 







5496 









Contents of 5496 
Entry Register 


4 Incorrect Card Code 

5 Compare Error on Read or Punch 10 
Cycles or Failure to Take Read Cycle Steals 

6 Reserved for FE use. 

7 Reserved for FE use. 


B 
0 
1 

2 
3 
4 
5 
6 
7 




















Data 
Recorder 
a 
M bit is not used, it should be zero. 
Byte 1 
2265 1 Start Character Generator (Diagnostic Only) 
CRT 2 Step-Display (Diagnostic Only) 
3 Cycle Steal Request (Diagnostic Only) 
4 Display Reset (Diagnostic Only) 
5 Data Register Parity Check 
6 Display Not Ready 
| 7 Cycle Steal Acknowledged (Diagnostic Only) 
/xox{ =| | CRTAR-Lo CRTAR-Hi 


O Write Op (Diagnostic Only) 
Note. An X means bit can be a “1” or “0”. 








Contents of 
the Data Register 





BRO619A 


5406 FETMM = (2/71) 1-108 


Disk File Sense Instruction 















Byte 1 or 3 = Operand Address 


O 
Op Code Code Address Op Code Q Code my Byte O or 2 = Operand Address -1 


Direct Addressing (H1 L1) 
Indexed by XR1 
Indexed by XR2 
Ae Sh we dl Device Address Drive 1 (Spindle O) 
Peer Device Address Drive 2 (Spindle 1) 
Ort te eal Removable Disk 
put Fixed Disk 
5444 
File 










2 Bytes 
1 Byte 
1 Byte 























Byte O Byte 1 















O No Op O Scan Equal Hit 


1 Intervention Required 1 Cylinder Zero 





2 Missing Address Mark 2 End of Cylinder 








3 Equipment Check 3 Seek Busy 


4 Data Check 4 100 Cylinder 
5 No Record Found 5 Overrun 
6 Track Condition Check 6 Status Address A 


7 Seek Check 7 Status Address B 









Byte 3 
- OCE Bit 










1 Tap Line A 1 CE Bit 









2 Tap Line B 2 CE Bit 








3 Tap Line C 3 Not Bit Ring Inhibit 


4 Index 4 Standard Write Trigger 
5 Head Settling 5 Condition Priority Request 
6 CE Bit 6 Bit Ring O 


7 Model 6 7 Not CC Register Position 17° 


root [fron SC~idCi OR 
Pao | [orcrvi——SSCS~iSCtrc 


Note. An X means bit can be a “1” or “’0”. 


BRO620A 


BSCA Sense Instruction 


Byte 1 = Operand Address 


Op Code Address Op Code Q Code D1 Byte 2= Operand Address —1 


[yo [oA [|W [ovenat] [vo [0a [m]N]Oenecement| 
0 7 

30 

70 

BO 


8 11] 12 113 15116 23 
2 Bytes Direct Addressing (H1L1) 

1 Byte Indexed by XR1 

Indexed by XR2 


Device Address BSCA 


M bit is not used. 

Byte 1 Byte 2 

Diagnostic Diagnostic 

0 Not Assigned O Not Assigned 

1 Not Assigned 1 Bit Time Counter 4 
2 Not Assigned 2 Bit Time Counter 2 
3 Not Assigned 3 Bit Time Counter 1 
4 ITB, BCC or VRC Check 4 Not Assigned 

5 LSR/Shift Register Parity Check 5 Transmit Trigger 

6 1/0 Cycle Steal Overrun 6 Receive Trigger 

7 DBI Parity Check 7 CE Sense Bit 


Byte 2 
Status Status 
O Not Assigned O Timeout 
1 Not Assigned 1 CRC/LRC/VRC Check 
2 Not Assigned 2 Adapter Check on Transmit 
3 Not Assigned 3 Adapter Check on Receive 
4 Not Assigned 4 Invalid USASCII Character 
5 Not Assigned 5 Abortive Disconnect 
6 Data Set Ready 6 Disconnect Timeout 
7 Data Line Occupied 7 Not Assigned 


Operand Address (Sense Byte Destination) 


Stop Address Register — Lo 


Transition Address Reg — Lo 


Note. An X means bit can be a “‘1"’ or “0”. 
BRO622A 


SYSTEM MAINTENANCE-Reference Data 
Sense Instruction (Part 3 of 3). 


SIOC Sense Instruction 
















Op Code OQ Code 


0 718 «11 13 1 
30 2 Bytes Direct Addressing (H141) 
70 Indexed by XR1 
BO Indexed by XR2 


Byte 1 

M bit is not used. 
Function Register 

O Diagnostic Mode 

1 Spare 

2 Latch Transfer Line 4 


[vo [0a [mw] Ww] iiacemene 





Byte 1 = Operand Address 
Byte 2 = Operand Address —1 













Device Address SIOC 


Byte 2 


Function Register 
O Write Mode Set Service Response 
1 Reset Service Response after 6 usec 





2 Transfer Line 2 EOT 
3 Transfer Line 1 EOT 


: ; 4 Even Parity 
5 Transfer Line 3 Reset Disconnect Latch] 5 Decrement DAR 


6 Reset Disconnect Latch after 6 usec 6 Latch I/O 1 Select 
7 Transfer Line 5 Reset Disconnect Latch} 7 Slave 


ist Data Byte 

0 1/O Transfer Line 8 
1 1/O Transfer Line 7 
2 1/O Transfer Line 6 
3 1/O Transfer Line 5 
4 1/O Transfer Line 4 


3 Latch Transfer Line 3 
4 Latch Transfer Line 1 


2nd Data Byte 

01/O ID Bit 8 

11/O ID Bit 4 

21/0 ID Bit 2 

3 1/0 ID Bit 1 

4 1/O Device Attached 
5 1/O Transfer Line 11 
6 1/O Transfer Line 2 6 1/O Transfer Line 10 
7 1/O Transfer Line 1 7 \/O Transfer Line 9 


A *‘1’’ in each bit position represents an active condition. 


Status Byte (Byte 2) 
O Spare 

1 End Request 

2 Interrupt Pending 
3 1/0 Attention 

4 Data Transfer Register Parity Check 
5 No Operation 

6 LCR Overflow 

7 |/O Ready 


Diagnostic Byte (Byte 2) 
0 SIOC Request Latch 
_ 1 Service Request 
2 Service Response 
3 Interrupt Enable 
4 1/O Disconnect 
5 Write Call 
6 Read Call 
7 1/O Selected 


| 100 | IAR-Lo -SIAR-Hi 
| |XXXX XXXX]} Operand Address (Sense Byte Destination) , 


Note. An X means bit can be a “‘1"' or “0”. 


5 1/O Transfer Line 3 












Length Count Register (Byte 1) 











Contents of the 
Length Count Register 










ata Transfer Register (Byte 1) 


Contents of the 
Data Transfer Register 






Ee 
SIOC : 
010 

0 

1 

2 

3 

4 

5 

6 

7 

101 D 
0 

1 
2 , 

3 

4 

5 

6 

7 

| | fs 


BRO621A 


5406 FETMM = (2/71) 1-109 





SYSTEM MAINTENANCE-—Reference Data 


. ]/O Control Fields 


Printer Command Byte 


Command Chain 
*Print Data 
*Horizontal Tab Right 
*Horizontal Tab Left 
*Primary Carriage Skip 

Element Return 


Secondary Carriage Index 





Primary Carriage Index 
*If bit is on a count byte must follow. 


BR0623 


Format of Disk Control Field 


Byte 


N+ 1 


23 24 31 


Number of sectors to be trans- 
ferred on read, write or scan. 

(N = 16 will process 1.7 sectors.) 
Number of cylinders to be moved 
on seek. 

Head bit 16 (0-1) 


Sector bits 17-21 (0-23). Bit 
22-23 both zeros for read, write, 
or scan. Bit 23 for seek is 

O = reverse, 1 = forward. 


Cylinder (0-202) 


Flag byte — 

Bits O thru 5 are not used 

Good track bit 6 = 0, bit 7=0 
Alternate track bit 6 = 0, bit 7 = 1 
Defective track bit 6 = 1, bit 7 =O 
Defective alternate track bit 6, bit 7 = 1 


The seek operation: uses the H/S and N bytes of the disk control field. 


Hexadecimal Values for Head and Sector Selection 


[bectiex|[ Dectox [DecHex || Dectex] DecHex] Darton | 





BRO624A 


5406 FETMM 


(2/71) 


1-110 


Operand 1 Byte 1 = Operand Address 1/O Channel Condition |/O Condition 
Byte 2 = Operand Address -1 GS = Raise CJ} = Lower | Al B 
16 23 a 
Direct Addressing & | 
Indexed by XR1 
DBO 
arity ok _ 
Indexed by XR2 pay. : ay 








Device Address CPU 
M Bit (not used) 


Byte 2 Byte 1 
EB2 EB1 
Address Address 
Switch Switch 
1 3 
Address Address 
Switch Switch 
2 4 


7 
xxxxxxxx | Operand Address (Sense bytes destinations) 


Note. An X means bit can be a “1” or “‘0”’. 
















Device 
address 
recognized 











N 
field valid 


NOOR WN — O 
Ooh WN Oo 


BRO625A 


Condition 
met 







SIO 
or LIO 
instruction 


BRO626 


SYSTEM MAINTENANCE- Reference Data | 
CPU Sense and Condition Code Response | | | | 5406 FETMM (2/71) 1-111 


SYSTEM MAINTENANCE~—Reference Data 


Condition Register Settings and Hexadecimal and Decimal Conversion Chart 


Condition Register Settings 


Bits 


Compare 
Logical 


Sub Logical 


Logical 
and 
Add 
Register 


; 


PK 


Branch 
on 
Condition * 


Condition High 
or 
Positive 


* Q bit O = O absence of condition. 
Q bit O= 1 presence of condition. 





= EMM 
/\/\ 


Negative} Zero 


BR0O627 


To find the decimal number, locate the Hex number and its decimal equivalent for each position. Add these to obtain the decimal 


number. To find the Hex number, locate the next lower decimal number and its Hex equivalent. Each difference is used to obtain 


the next Hex number until the entire number is developed. 
BYTE ; BYTE BYTE 


0123 4567 0123 4567 0123 4567 















































0 | 0 0 0 0 0 0 0 0 0 00 0. 
1 1,048,576 1 65,536 1 4,096 1 256 1 16 1 1 
2 2,097,152 2 131,072 2 8,192 2 2 32 2 2 
3 3,145,728 3 196,608 3 12,288 3 3 48 3 3 
4 4,194,304 4 262,144 4 16,384 4 4 64 4 4 
5 5,242,880 5 327,680 5 20,480 5 5 80 5 5 
6 6,291,456 6 393,216 6 24,576 6 6 96 6 6 
a | 7,340,032 7 458,752 7 28 672 7 7 112 7 7 
8 8,388 ,608 8 — 524,288 8 32,768 8 8 128 8 8 
9 9,437,184 9 589 824 9 36,864 9 9 144 9 9 
A 10,485,760 A 655 ,360 A 40,960 A A 160 A 10 
B 11,534,336 B 720,896 B 45,056 B B 176 | B 11 
C 12,582,912 C 786 ,432 C 49,152 C C 192 C 12 
D 13,631,488 D 851,968 D 53,248 D D 208 D 13 
E 14,680,064 E 917,504 E 57,344 E E 224 E 14 
F 15,728,640 F 983,040 F F F 240 F 15 








BRO628 


5406 FETMM 


(6/70) 


1-112 


fp 1.52 us ———_ $+ 
Machine Cycle \ X 


Clock | 0 1 2 3 4 5 6 7 8 0 


| ADDR | MISC | COMPUTE | ADDR LO mop | ADDR HI MOD | 


Load SAR / \ / \ 
R/W Select / R \ / WwW \ 


Store Pulse / \ 


New Data to Stor... eseses—(iess—(—Cti‘CsC‘<—C‘<~C~;2 CWS A ae 


LSR Select ADDR ADDR ADDR 


r\ rN 
LSR Write fy / \ LO HI 





BRO629 


1/O Device Priorities 


Pp 


File Seek 
Unassigned 
Unassigned 
Unassigned 
Unassigned 
Unassigned | 
oe ALU Output . X X X K 
Data Recorder : BRO631 
Unassigned . 
Unassigned 
Unassigned 
Unassigned 
Unassigned 
BSCA 
Unassigned 
SIOC 
Printer 
Unassigned 
File Read/Write 


Oo 
ot 
N > 
to 
3 


-~ooed0ec0ec/f oe 00 0 ]}0 0co0o0o-00 0 OFW 
& 


CO-0C000O-C0O0OO-cCOOOAo ofun 3 





NYY OOO a Kee wwweoaoa 
WATONWAUTHYUWAUTAHAYUWAUO 
DO00OOHA=2434aHA COOCOOO CO O]OoO 
DODDOOOOOOB BAB aHwAQo0 OO Of]= 
272700 COCOOO OOOO OO OA Aa HH 
O-DCD0O00=CO00=-cCO00O=000 
DOO=CO00=0000OA0C0O0OO=Ao0]o 
SPCCCO-CC00O=c000OA000C0 AN 


0 
0 
0 
6) 
2 
5 
20 
2 
2 
4 
4 
a. 
4 
4 
6 
6 
6 
6 
6 





BRO630 


SYSTEM MAINTENANCE-Reference Data 
Hexadecimal Addition and CPU Timing 5406 FETMM (6/70) 1-113 


SYSTEM MAINTENANCE~-—Reference Data 
Local Store Registers and Data Flow 


Local Store Registers (Base System) 








Length Count Recall Reg 









Length Count Register 





Instruction Address Register 
Condition Recall Reg 


Data Recall Register 


Interrupt Level 1 Instruction Address Register 
Interrupt Level 1 Address Recall Register 






eek 


LSR 
AR 
AR 
LLAR 
R1 
SR 
AR 
R2 







DFCR 


| 

A 

xX 

P 

B 
PDAR 
PCAR 
DRAR 
DFDR 
LCR DRR 
IAR-1 
ARR-1 





*This LSR is used by the CRT (CRTAR) when the LCD feature is not installed. 
When both the CRT and LCD features are installed, the CRTAR is located in 


feature LSR number 10. 


Local Storage Registers (Feature) 









Spare 





Spare 
BSCA Address Register 


P Sere OSS 


LSR 
Acronym 





BRO0632 


System/3 Data Flow 


Read-CLK 
Write-CLK 






















XR1 
LCRR CRR 


Ww 
> 
LSR Select 


DFCR 


x 
B 3) 
NO 


PDAR 
PCAR 
DRAR 
DFDR 


- 
O 
5 


Inter 1-IAR 
Inter 1-ARR 


hi 
O 





5406 FETMM = _ (6/70) 1-114 


DBI 


| Channel 
In 
Control 


Channel 
Out 
Control 


DBO 
Translate” ey 
Out 





| Cycle Control 
foo [oe [om [esa] [re [ve [ove] na] | eof 
Pe 
a ~ 


Y ao Basic Clock ra 
~s 
“ : ™s 
Storage Read Storage Write ™ 


ABCDE | ABCDE | ABCD|ABCD 


Load Compute Address 
SAR Lo 
Modify 






(P) Parity Checked 


Parity Generated 


BRO633 











© 
2 
o 
= 
£ 
x 
® 
z 
° 
- 
oO 

X-Y-Z X-Y-2 Oo 

Op1 Direct Op1 Indirect 

Z Type 
X Type X Type 
Op2 Direct Op2 Indirect 








IH 


ILo 


No 
Y-Type 


2nd EB 


Register 
Blank 









E-A 
Eliminate 











Register 
Right Part 
Blank 





* Can be performed between any of the 11 above cycles. 


SYSTEM MAINTENANCE-—Reference Data 
Cycle Pattern, Data Storage and Sign Control 





Go To Next Instruction 


_sivrostion | of 1]2]3]4]5] 67] of ]2]3/4}s]5]7Jo]+}2]a)¢|s]ol7 Jols | fol7 ofr fas [as [o|y_ 


Digit 






Function Zone Zone Digit Zone 


I 
Digit] Sign* | Digit 
st 


Digit Zone 




















¢ 
S Low-Order Byte 
S 
8 
= 
bv) *Sign Configurations: 
o 
Zz 
fe) 
. Binary Hexadecimal Function 
© 
~ 4011 ASCIHI-8 Minus 

Alternate Plus 

Standard Minus 

Alternate Plus 

Standard Plus 

BRO635 
Yes 
BRO0634 
5406 FETMM _— (6/70) 1-115 


SYSTEM MAINTENANCE-Reference' Data 
Code Conversion Chart (Part 1 of 2) 


Dec} Hex} Card Code | Mnem | EBCDIC | Symbol 
eee a Bee eo Val | DCBA8421 





00000000 
00000001 
00000010 
00000011 


















DCBA8 
DCBA8 1 
CBA8 2 
CBA8 21 












00001000 
00001001 
00001010 
00001011 







CBA84 
CBA84 1 
CBA842 
CBA8421 


00001100 
00001101 
00001110 
00001111 














00010000 
00010001 
00010010 
00010011 


00010100 
00010101 
00010110 
00010111 










00011000 
00011001 
00011010 
00011011 










00011100 
00011101 
00011110 
00011111 










00100000 
00100001 
00100010 
00100011 










00100100 
00100101 
00100110 
00100111 










00101000 
00101001 
00101010 
00101011 










00101100 
00101101 
00101110 
00101111 








Dec 
Val 


oes Card Code | Mnem | EBCDIC {Symbol 
al | DCBA8421 
‘Tsns_ | 00110000 
00110001 
00110010 


00110011 






























00110100 
00110101 
00110110 
00110111 









00111000 
00111001 
00111010 
00111011 












SBF 
MVI 00111100 
00111101 
00111110 
00111111 





gage 





01000000 
01000001 
01000010 
01000011 











OQ 
Je 





33 BB 8888 
NON 
WN 

om ol >< > f 

WN — o in 5 5 o > co = & Gh & ON 5 






ZAZ_ |01000100 

01000101 

me AZ 01000110 
071 SZ 01000111 





01001000 
01001001 
01001010 
01001011 






= 


— mM 
ao 


01001100 
01001101 
01001110 
01001111 


BA84 
BA84 1 
BA842 
BA8421 












on 








b 
n 


SLC 








01010000 
01010001 
01010010 
01010011 





a 
082 
083 


oOo 










01010100 
01010101 
01010110 
01010111 


01011000 
01011001 
01011010 
01011011 

















m 
O 


01011100 
01011101 
01011110 
01011111 








CBA8 

CBA8 1 
DCBA8 2 
DCBA8 21 


DCBA84 

DCBA84 1 
DCBA842 
DCBA8421 


ITC 


MVC 
CLC 
ALC 
SLC 


01100100 
01100101 
01100110 
01100111 


01101000 
01101001 
01101010 
01101011 


01101100 
01101101 
01101110 
01101111 


01110000 
01110001 
01110010 
01110011 


01110100 
01110101 
01110110 


01110111 


01111000 
01111001 
01111010 
01111011 


01111100 
01111101 
071111110 
01111111 


10000000 
10000001 
10000010 
10000011 


10000100 
10000101 
10000110 
10000111 


10001000 
10001001 
10001010 
10001011 


10001100 
10001101 
10001110 
10001111 


5406 FETMM 





BRO636 


(6/70) 


1-116 


Symbol | Dec| Hex] Card Code EBCDIC | Symbol 
Val |] Val | DCBA8421 


192} CO}D 11000000 
193] C1] 11000001 
194} C2 11000010 
195] C3 11000011 
C4 
5 


Dec | Hex] Card Code EBCDIC Dec | Hex} Card Code EBCDIC | Symbol! 
Val | Val | DCBA8421 Val | Val | OCBA8421 












































a 
144] 90 10010000 11100000 
ele ee 11100601 
146| 92 10010010 11100010 
147| 93 10010011 


11100011 



















































148] 94 10010100 196 11000100 11100100 
149| 95 10010101 197} C 11000101 11100101 
150] 96 10010110 198] C6 11000110 11100110 
151] 97 10010111 199] C7 11000111 11100111 
ee 10011000 200 11001000 11101000 
153] 99 10011001 201 11001001 11101001 
154] 9A 10011010 202 11001010 11101010 
155| 9B 10011011 203 11001011 11101011 
156| 9C 10011100 BA84 11001100 11101100 
157| 9D 10011101 205 BA84 1 11001101 11101101 
158] 9E 10011110 206 BA842 11001110 11101110 
159 10011111 207 BA8421 11001111 11101111 








160 













10100000 208 11010000 


11110000 










162 10100010 210 11010010 11110010 
163 10100011 211 11010011 


11110011 








164 










10100100 212 11010100 


11110100 










165 10100101 213 11010101 11110101 
166 10100110 214 11010110 11110110 
167 10100111 215 11010111 


11110111 





168 









10101000 
10101001 
10101010 
10101011 


216 11011000 
217 11011001 
218 11011010 
219 11011011 


11111000 
11111001 
11111010 
11111011 










10101100 
10101101 
10101110 
10101111 









220 11011100 
221 11011101 
222 11011110 
223 1101117111 


11111100 
11111101 
11111110 
11111111 








BRO0O636 


10110010 
10110011 







10110100 
10110101 
10110110 
10110111 












10111000 
10111001 
10111010 
10111011 


10111100 
10111101 
10111110 
10111111 








SYSTEM MAINTENANCE- Reference Data 
Code Conversion Chart (Part 2 of 2) | 5406 FETMM (6/70) 1-117 


SYSTEM MAINTENANCE -Reference Data | 5406 FETMM (6/70) 1-118 
CRT Code Conversion Chart 


H Symbol Symbol 
EBCDIC Symbol | EBCDIC val | and EBCDIC eh Symbol escoic | He} ang 
Cursor. q Val Cc 
ursor 
20 


ex 
al 
00 60 
61 
62 
63 


ISI] ' 


64 
65 
66 
67 


68 
69 
6A 
6B 


laImIM|O 
IXISI<IC 


6C 
6D 
6E 
6F 


IY IVIL les 


70 
71 
72 
73 


ITIAIC Ie 


74 
75 
76 
77 


IVIOIZIE 
IN [jou 


78 
79 
7A 
7B 


t|>(DIO 


mee] vere] owne a“ we a ao | 


A 
B 
Cc 
-D 
E 
F 
G 
H 
| 
g 
< < 
( a 
+ + 
| L 
& 
J 
K 
L 
M 
N 
O 
Pp 
Q 
R 
Tt 
$ 


0011 1100 
0011 1101 
0011 1110 
0011 1111 


~ 


“Hh 





BRO637 


CPU Tie-downs 


The following tie-downs are required when the following memory features 


are installed: 
Feature Pin Location | To 
12K or 16K memory A-B2B2J02  A-B2B2B10 


16K memory A-B2B2B 10 A-B2B2J04 


2265 II Attachment Tie-down 


If the LCD attachment is installed with the 2265 attachment, the tie-down 
required is O1A-B1N2G12 to O1A-B102D12. 


SYSTEM MAINTENANCE~-Reference Data 
Tie-Down List 


5444 Disk Attachment Tie-downs 


Signal Name 


-100 Cylinder 


-Model 6 CPU 


+ Model 3 Ready 


+’Spin 1 data unsafe’ 


TO: (on board A-A1) 
Jumper from 
pin (on board | If Model 1 | If 1 or 2 If Madel 2 
A-A1) Model 2(s) | and 3 Together 
T2613 T2G13 
T2U07 R2U11 


T2511 T2U07 


Remove Remove 





BRO638A 


5406 FETMM 


(2/71) 


1-119 


Chapter 2. Console and Maintenance Facilities 


2.1 INTEGRATED MAINTENANCE PACKAGE (IMP) 


System failures in the 5406 system, its 1/O devices and attachments, are 
diagnosed with the aid of the IMP. 

The IMP ties all maintenance equipment and information together and 
requires a minimum of recall about detail circuit operation. 

The IMP consists of the following: 


Maintenance Analysis Procedure (MAP) charts 
CE aids | 

Diagnostic programs 

FE education and FE publications 


aS 


MAP charts are systematic flowcharts of failure analysis. Failure symptoms 
and/or a coded halt in a diagnostic program indicates the map chart to start 
with. 

CE aids are: the CE probe, CE sense bits, single pin extenders, and MST 
card extenders. The MAP charts refer to these aids and call out when they 
are to be used. 

Diagnostic programs are loaded and controlled by a diagnostic control 
program (DCP). The DCP may be modified by the CE to call specific test: 
programs into use or perform a specific operation. Halts may occur during 
operation of the DCP or a diagnostic program that refers to a MAP chart for 
further diagnostic procedures. 

FE education and FE publications expand on overall system and |/O 
device operation to aid in free-lance troubleshooting in the event that other 
IMP procedures fail to locate a problem. 

For further information about IMP, MAPs, or the DCP, refer to the 
Integrated Maintenance Package User’s Guide, the MAP charts, or the 
Diagnostic Control Program User’s Guide. Each section contains a description 
and specific operating instructions for its use. 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities 
Integrated Maintenance Package ts 5406 FETMM (6/70) 1-201 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities 
System Console (Part 1 of 2) 


2.2 CONSOLE 


The operator console contains the switches and lights necessary for operator 
control of the system. It-is divided into two sections: system indicator lights, 
and system control switches. 


2.2.1 System Indicator Lights 


The system indicator lights section is divided into six parts. They are: system 
check lights, halt code indicator lights, field/operation indicator lights, key- 
board ready light, command key indicator lights, and the system power on 
light. 

Individual attention lights are provided for disk 1, disk 2, CRT, ledger card 
device, data recorder, SIOC, BSCA, and the printer. The processor check 
light is also displayed on the console. 

The nine halt indicator lights, which are under program sana indicate 
to the operator a cause for system halt. The stop light (not under program 
control) indicates a halt when the stop switch is pressed. 

The field/operation group of lights consists of eight lights that may be 
labeled by use of a plastic overlay. The program uses these lights to inform 
the operator at what point in the program he may enter specific data fields 
or take specific action. | 

The command key indicator light group consists of eight (standard) or 
sixteen (feature) lights that are associated with the command keys on the 
operator keyboard. Command key indicator lights are turned on or off by 
program control (LIO instruction). In addition, the program can light a 
specific command key light whenever there is a need to communicate a 
predefined condition to the operator. Plastic overlays are provided for the 
lights so that the significant meaning for a light can be changed by typing 
on the overlay. 


Processor Check Light (PROC CHECK) 


The processor check light turns on whenever an invalid op code, CPU parity 
error or invalid SAR condition is detected. It is also turned on when an 
invalid Q code is detected. If the check stop switch (on the CE console) is 
set to STOP, the processor check light is turned on when an |/O parity error 
is detected. It is turned off by system reset or by pressing the check reset 
key on the CE panel. Any of these errors cause the processing unit to come 
to an immediate stop. The clock is stopped and the input/output data may 
be lost. The specific error that caused the stop is displayed on the CE 
console display section. 


//0 Attention Lights 


Any of the following lights on indicates that the corresponding !/O device 
has been issued a start |/O instruction but is not ready to operate. A not 
ready condition can be caused by power not being on, or by some condition 
involving the paper or cards to be handled by the !/O device. The |/O atten- 
tion indicators are SIOC, BSCA ATTN, LCD, CRT, DATA RCRDR, 
PRINTER, DISK DRIVE 1, and DISK DRIVE 2. The specific conditions 
that cause each I/O light to turn on are discussed under the individual I/O 
devices. 


ON READY 
oa 
PAP IE IE IE IE IE IE 


DATA DISK. 
ro aL SIOC BSCA LCD CRT RCRDR- PRINTR- DRIVE 1 
7 a aa ae Oo oe cae Geet CODE ON 
STOP : 
| O 





‘a KEYBD 


FIELD/OPERATION 








Halt Code Lights 


These lights are turned on by the individual bits (nine) and the halt identifier 
bytes of the halt program level instruction. 


Power On Light 


This light is turned on when system power-on sequencing has been success- 
fully completed and stays on until system power is turned off. 


Keyboard Ready Light (KEYBD READY) 
This light is on when the keyboard has been enabled and unlocked. 


Stop Light 


This light is turned on when the system start switch is moved to the stop 
position and is turned off by moving the system start switch to the start 
position, or by system reset. 


Field/Operation Lights | 


These lights are turned on by a load I/O instruction. The meaning of each 
light is determined by the program being used. A plastic overlay is provided 
for the field/operation lights so that appropriate labels can be applied. These 
labels identify the particular meaning given to the lights by the programmer. 
Once turned on, the field/operation lights remain on until another load |/O 
instruction specifying the field/operation lights is executed. 


Command Key Lights 


These lights are controlled by the load I/O instruction. Separate load I/O 
instructions are used to turn the command lights on or off. Once turned on, 
command lights remain on until a load 1/O instruction turns them off, or 

until a system reset takes place. A plastic overlay is provided for the command 
lights so that appropriate labels can be assigned to each command light in 
order to identify the particular meaning given to the light by the programmer. 


5406 FETMM = (2/71) 1-202 


SYSTEM] DISK DISK DISK PROGRAM] DATA INQUIRY] SYSTEM 


DISK RESET |DRIVE 1 DRIVE 2 SELECT LOAD RCRDR REQUEST] START 
DRIVE 2 


REMOVABLE ON ON LINE 


@ 9/8 


FF OFF FIXED OFF LINE STOP 


ON 
POWER Q | 
OFF 


BRO360 


2.2.2 System Control Switches 


The system control switches section includes those switches required for 
system powering, program loading, system starting, stopping, resetting, and 
1/O selection. 


Lamp Test 


This switch, located behind the hinged command indicator panel, is used to 
check for faulty indicator lamps. 


System Reset Switch 


When this switch is moved to the on position, a system reset occurs. A 
system reset causes the system to idle (become inactive) and resets all |/O 
and machine registers, |1/O controls, and status indicators. The program |AR 
and the program status register LSR’s are reset to zero in a system reset. 

Normally, a complete program restart is required after a system reset has 
been performed. 


Disk Drive 1 and Disk Drive 2 Switches 


These switches apply electrical power to their respective disk drive motors. 


Disk Select Switch 


This switch selects the disk from which the initial program load will be per- 
formed. When the switch is moved to the removable position, sector zero of 
cylinder zero of the removable disk is used for program loading. Similarly, 
when the switch is in the fixed position, sector zero of cylinder zero of the 
fixed disk. on disk drive one is used for program loading. 


Program Load Switch 


This switch initiates loading the program into main storage. The following 
actions occur when this switch is on: 


1. All |/O and machine registers, controls, and status indicators are reset. 

2. The instruction address register is set to zero. 

3. The disk file data address register is reset to zero. The record in cylin- 
der zero, sector zero on one of the disks in disk drive one is read into 
storage starting at location 0000. The disk that provides the first 
record is selected by the setting of the disk select switch on the con- 
sole. 


When the program load switch is released, the processing unit executes 
the instructions read into storage from cylinder zero, sector zero, starting 
at location 0000. 

If disk drive one is not ready, the I/O attention light is turned on. When 
the program load switch is operated, it is necessary only to make disk drive 
one ready to complete the program load function. 


Data Recorder Switch (DATA RCRDR) 


Moving this switch to the on-line position places the data recorder under 
program control when the verify-punch switch on the data recorder is in the 
punch position. The data recorder keyboard is disabled. Data can be entered 
into the system from the data recorder reading station or punched at the data 
recorder punching station. Data and control can be entered from the system 
keyboard under program control. | | 

Moving this switch to the off-line position places the data recorder under 
its own control and allows it to function as a normal (off-line) data recorder. 


Note. Switches on the data recorder must be properly set for the data 
recorder to operate under program control (see page 10-109). 


Inquiry Request Switch 


This switch is mounted on the console, and although this key is not under 
keyboard bail interlock control, it operates as though it were a key on the 
keyboard. Moving this switch to the on position causes the data and status 
bytes to be stored in the keyboard attachment circuitry. Interrupt level one 
must be enabled for the CPU to recognize this switch. The status byte has 
the function key bit (bit 3) on and the data byte contains the unique data 
character code for the inquiry request key (0001 0001). 

With the inquiry request switch on, the interrupt request latch sets if the 
program enabled the interrupt. At interrupt poll time, the interrupt request 
latch output will activate the ‘interrupt polled KB’ line which forces a key- 
board bit 1 to the local storage register through the DBI channel. This 
signals a keyboard interrupt request to the CPU. When the CPU accepts the 
keyboard interrupt request, a sense instruction is issued to the keyboard to 
allow the data and status bytes (generated by the inquiry request switch) 
to enter the CPU on the DBI channel, These bytes point to the main storage 
location containing the keyboard sub routine to unlock the keyboard and 
turn on the keyboard ready indicator. 

Prior to the initiation of the inquiry request signal, the keyboard is locked 
(bail bar forward) and the interrupt is enabled. 


SYSTEM MAINTENANCE-Console and Maintenance Facilities _ 
System Console (Part 2 of 2) 


System Start Switch 


When this switch is moved to the start position the processor resets the halt 
code lights and resumes normal operation. When this switch is moved to the 
stop position the processor halts at the end of the operation in process. This 
halt is indicated by turning on the stop light on the console. |/O data trans- 
fers are completed without loss of information. The system can be restarted 
without loss of information only by setting the switch to the start position. 


Power ON-OFF Switch 


This switch controls the main electrical power to the system. When it is 
moved to the on position a partial system reset is generated and a power up 


‘sequence is started. The partial system reset prevents any |/O operations from 


starting until they are requested. The power up sequence is performed to 
apply the various voltages within the system in a manner to protect infor- 
mation in main storage. The on position of the power switch is interlocked 
with power supply safety circuits (overload protection and thermal circuits) 
and logic gate thermal protection. The system will not power up until the 


interlock circuits are complete. 


In the off position, the system sequences the system power off in a manner 
to protect the information in main storage and opens the main power to the 
system. If an abnormal power off occurs (such as an electrical failure), the 
system will not sequence down properly and information in main storage 
may not be preserved. 


5406 FETMM 


(2/71) 


1-203 


SYSTEM MAINTENANCE -Console and Maintenance Facilities 
Field Engineer Console (Part 1 of 4) 


2.3 FIELD ENGINEER CONSOLE PANEL 


The FE control panel contains those switches and lights necessary for the 
field engineer to maintain the system. These controls and indicators are 
hidden behind a hinged panel and normally not used for customer opera- 
tion. However, some of the switches on the FE console must be positioned 
correctly for the system to process in customer mode. The FE panel is 
located at the end of the CPU and may be removed from its normal 
mounting by lifting it upward. Support feet underneath the panel can be 
turned cross-wise to support the panel in an upright position. The cable 
attached to the panel is long enough to allow the panel to be placed on 
top of the CPU in position to be viewed while servicing the main gate of 
the CPU. 





BRO354A 


7 CSASNMT 


8 PROC CHK 


o 


bh 
0 


pe 


Tl I~ 
= 1 





LSR| SAR | SAR] INV 
LO| HI | LO | ADD 


1. SARHI/SAR LO. Displays the contents of storage address register 


5406 FETMM = (2/71) 1-204 


2.3.1 CE Display Indicators 


CE Rotary Display 


The rotary display unit consists of a row of 18 lights and eight legend strips © 
mounted on an eight position roller. At any one time, only one of the eight 
strips is visible through a cutout in the console above the row of lights. 

A knob in the upper-left corner of the panel is attached to the roller to turn 
it to each of the eight positions. Turning the roller to each legend position 
selects the register or check condition as defined in the legend strip and 
connects each light to indicate the conditions of the signals. The over-all 
view of the eight legend strips and a description of each position is shown 
below. 


SAR LO 
LSR LO 
QREG 
ALU CTL 
ALU OUT 
COND REG 
INT LEV 


PROC CHK 


BRO640 


high and low. 


2. LSR HI/LSR LO. Displays the contents of the LSR selected by the 


LSR display selector. 


3. OP REG. Displays the contents of the op register. 


Q REG. Displays the contents of the O register. 


4. B REG. Displays the contents of the B register. 


ALU CTL. The state of the following ALU controls are displayed: 


DIG CAR (digital carry) 

DEC (decimal instruction) 

RE COMP (recomplement) 
ADD (addition) 

SUB (subtraction) 

TEMP CAR (temporary carry) 
AND 

OR 


5. A REG. Displays the contents of the A register. 


ALU OUT. Displays the contents of the output of the ALU. 


6. COND REG. The contents of the condition register is displayed as 
follows: : 


BIN OVF (binary overflow) 
TF (test false) 

DEC OVE (decimal overflow) 
HI (high) 

LO (low) 

EQ (equal) 


7. CS ASNMT. Cycle steal assignment is displayed as it is presented to 
the 1/O devices on the I/O interface. 
INT LEV. Interrupt level indicates which I/O device is interrupting 
the program. 

8. PROC CHK. The processor checks are displayed as follows: 


1/O LSR. Indicates selection of an LSR by an I/O device was not 
performed correctly. 

LSR F1. Parity is incorrect on the output of the LSR feature 1. 
LSR F2. Parity is incorrect on the output of the LSR feature 2. 
(This feature LSR is not used currently by the Model 6, but this 
position is reserved in the event of future expansion.) 

LSR HI. Parity is incorrect on the output of the basic LSR high. 
LSR LO. Parity is incorrect on the output of the LSR low. 

SAR HI. Parity is incorrect in the storage address register high. 
SAR LO. Parity is incorrect in the storage address register low. 
INV ADDR. The SAR contains an invalid address. 

SDR. Parity in the storage data register is incorrect. 

CAR. Thecarry out of the ALU is incorrect. 

DBI. Parity is incorrect in the data bus in register. 

A/B. Parity is incorrect in the A register or in the B register. 
ALU. Parity is incorrect in the ALU register. 

CPU DBO. Parity is incorrect on the CPU end of the data bus out to 
the I/O devices. 

OP/Q. Parity is incorrect in the op register or the QO register. 

INV OP. Invalid op code in the op register. 

CHAN DBO. Parity is incorrect on the I/O device end of the data 
bus out from the CPU. 

INV Q. An invalid QO byte is present in an I/O instruction. 


Refer to the Field Engineering Handbook System/3 Model 6, order 
number ZY25-5501 for information to determine which check occurred 
first. 


Machine Cycles 


Twelve indicator lamps represent the twelve CPU machine cycles. They 
identify the processor cycle just completed in all modes of operation. 
However, when the CE mode selector switch is in clock step mode, the 
lamps indicate the cycle in progress. Except during an I/O cycle, no machine 
cycle indicator is on if (1) the CE mode switch is in the test position, (2) 

a system reset has occurred, or (3) an address compare stop has occurred, 

or (4) the stop key has been operated. 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities 
Field Engineer Console (Part 2 of 4) 


INT LEV 


The interrupt level lamp indicates if any interrupt level is being serviced. 


Clock 


Ten lamps indicate machine clock cycles 0 through 9. If the CE mode 
selector switch is in one of the test or step modes, the clock is stopped at 
9. In step mode the machine can be stepped through each cycle. Normal 
(process) mode uses only clock cycles 0 through 8. 


Address Compare Lamp 


This lamp comes on when the address set in the address/data switches 
matches the SAR. For this to occur, the rotary display switch must be in 
position 1(SAR). The system will not stop when the data matches unless 
the address compare switch is on. However, a sync point is available to 
indicate when an equal compare is made. See ALD KE 141. 


1/0 Check Lamp 


This lamp is turned on when unit checks are detected by an addressed I/O 
device. The I/O check lamp can be turned off with a system reset, check 
reset or by the I/O attachment de-activating the |/O check interface line. 


2.3.2 CE Controls 


Address/Data Switches 


These switches are used to set up addresses or data. Switches 1 through 4 
can be used to load a 16 bit address into SAR. Switches 3 and 4 enter data 
into main storage: either 4 bits (switch 4) or 8 bits (switches 3 and 4) can 
be entered. 


!/0 Overlap Switch 


This switch modifies control of the system so that I/O operations may be 
executed in either an overlap or a non-overlap mode. With the switch 

turned to the normal position of ON, |/O operations are executed in an 
overlap mode. When the switch is turned off, the |/O operation is completed 
before the next sequential instruction is executed. A mechanical interlock 
on the FE panel cover insures that the 1/O overlap switch is in the on posi- 
tion with the cover closed. 


File Write Switch 


In the off position, this switch prevents writing on all disk surfaces. Its 


primary purpose is to permit analysis of file write problems without destroy- 


ing information written on the file. A mechanical interlock on the FE panel 
cover insures that the file write switch is on, with the cover closed. 


BSCA Switches (Local Test and BSCA Step) 


The BSCA must be in a SIO test mode of operation for these switches to be 
effective. In the test mode, the switches allow the following actions: 


Local Test Switch. Placing the BSCA in test mode removes the BSCA from 
the communications line for diagnostic testing purposes. Data transmitted is 
sent to the receive trigger to allow wrap-around operation. Test mode is 
used in conjunction with the external test switch. With the external test 
switch turned off, data is sent directly from the transmit trigger to the 
receive trigger; with the switch turned on, data is sent from the transmit 
trigger to the modem and then back to the receive trigger. The external test 
switch is located at the modem end of the medium speed cable. For high 
speed modems the switch is located on the CPU CE control panel. 


BSCA Step Switch. Step mode allows stepping through a test operation by 
using the BSCA step key located on the CPU CE panel. The stepping oper- 
ation can also be performed by using the machine cycle step or clock step 
and the CPU start key to step through each data phase and BCC phase 
within the bit time. 


1/O Check Switch 


This switch, when set to stop, forces the processor to an immediate stop on 
an I/O error. The console display is frozen to indicate the processor status 
at the time the error stop occurred. For normal operation, this switch is set 
to RUN. 
To restart after an I/O error, activate CHECK RESET and then the start key. 


Parity Switch 


This switch, normally set to STOP, forces the processor to stop whenever 

a parity error is detected. Normal restart after a parity stop is to press 
CHECK RESET and then the start key. With the parity switch set to RUN, 
all parity errors are detected and displayed, but the processor stops for only 
some of the errors. The parity errors |/O LSR, INV ADR, INV OP, CHAN 
DBO, and INV Q are not affected by the setting of the parity switch and 
the processor will always stop on these errors. For all other errors, the 
processor will continue to run when the switch is in the run position. — 


5406 FETMM (2/71) 1-205 


SYSTEM MAINTENANCE -Console and Maintenance Facilities 7 — | / $406 FETMM (2/71) 1-206 
Field Engineer Console (Part 3 of 4) 


Storage Test Switch LSR Display Selector Tie up chart 
In the step position, a storage location is accessed with each depression of This rotary switch selects the local store register (LSR) to be displayed in 
the start key. In the run position and the start key pressed, main storage is position 2 of the rotary display switch. The LSR’s that can be displayed are 
exercised by accessing either the same location repetitively or all of core the instruction address register (LAR), address recall register (ARR), index SSE SMGE 
sequentially. _ register 1 (XR1), and index register 2 (XR2). The selected LSR is displayed 
‘ ‘ ae : i t i i i is j A1T2G13 
Note: The storage test switch must be in the step position to avoid a pro- eles ue a a es ee or I/O cycles. ven Unis Sireh ene A1S2M13 
cessor check when changing the CE mode selector from alter storage re POSIEION, sid anou) Be wnen eS eee is in operation, the CPU , A1F 2504 
position to display storage position or vice versa. core : the selection and display of LSR a Data Recorder B1R2S09 
The off position is for CE use. In this position LSR’s other than IAR, B1T2G10 
Aan oedneeene Ss Wien oe XR1, XR2, may be displayed by selecting the desired LSR manually CRT sso 
as follows: 
This switch allows address incrementing when in the CE test modes of alter 7 h Keyboard B1M2G11 
or display storage. With the switch on, the contents of SAR are incremented i ae ee LSR display switch 2 OFF. ; Channel B1J2P13 
by 1 after each storage access. When the switch is off, SAR is not incremented. . ee BIE porary display switch to position 2. (LSR Hi-Lo). | 
3: Tie up the desired LSR to —0.75 volts as shown below. Printer A202D04 


A203D04 
A2U2D04 
A2S2J10 


Address Compare Switch 





This switch allows a compare of the address/data switch setting and the BASIC A2R2B04 
register display when the register display is turned to SAR. When the A2M2G12 
address compare switch is in the run position, the address switch setting is 0201 IARINT1 SIOC 
compared to SAR through the register display, but no processor stop is LLAR/cRT |o 3.¢| DECR (B gate) A1S4G08 
initiated when a match occurs. The matched signal is provided as a sync | 
a ee AAR |o 40| ARR/IAR ene 
Poe eee a | BAR |o 5 0| PSR : 
When the switch is in the stop position, a match of the address switches : ‘ . 
; To Display LSR’s 060 CE Mode Selector Switch 
and the register display causes a processor stop at the completion of the Roller SW to Position 2, CPU not running aie . | 
storage read-write cycle. The processor is restarted by pressing the start key. LSR Display Selector to off. Cia This rotary switch selects one of three processor operating modes: process 
I/O data transfer takes place without loss of information. The contents of Tie up to LSR. See Tie Up Chart. 09 0/ PCAR mode and two positions for CE use, test mode and step mode. 


SAR do not necessarily match the setting of the address switches when the 


ARR INT 1 DRR/LCR 
processor stops. 


DRAR PDAR 
IAR/ARR XR1 
XR2 DFDR 


Process Mode. Process mode is the normal position for customer operation 
of the system. The CE mode switch should be left in this position before 
returning the system back to the customer for use. 


Oo Oo 
—_ wa 
= © 
Oo Oo 


System Reset Key 


When this key is pressed, it resets all |/O registers, CPU registers, controls, 
and status registers, including the program status register (PSR) and the | | A-B2C2 ALD Page MA107 
current [AR (P1 or P2 !AR) register to zero. System reset is operable only 
when the CE mode selector is set to the process mode. 


FEATURE 1 


Check Reset Key Example, to Display AAR: 


oe 1. Stop CPU 
This key resets the processor and I/O check conditions. Check reset removes _ Turn roller display to position 2 


2 
the current error conditions and allows the processor to resume its operation 3. Turn LSR display selector to off 
after the start key is pressed. It also resets the system power-check function 4. Tie up B2-C2M08 to B2-C2U04. 
and allows a power-on retry. 


ARR INT 2 


Start/Stop Switch 


oO 000 0 80 O80 
oOo 0 00 0 0 0 


In the start position, this switch takes the processor out of the stop or halt 
state, turns off the program stop lights, and allows the processor to resume 
its normal operation. | 

In the stop position, the processor halts at the end of the operation in 
progress. The halt state of the CPU is indicated by the stop indicator on the 
system keyboard console. |/O data is transferred completely and without loss A-B2D2 ALD page MA212 
of information. The processor can be restarted, without loss of information 
by placing the switch in the start position. 


IAR INT 2 CRTAR 


SIAR BSCAR 
ARR INT 4 IAR INT 4 





BR1747 


Test Mode. \|n the test mode, data in core storage can be displayed by the 
CE panel indicators. Data set up in the address/data switches 3 and 4 can be 
entered into core storage, or the SAR address can be altered. A functional 
description of each test position is as follows: 


te Display Storage. The contents of main storage at the address specified 


by SAR, are transferred to the B register when the start key is operated. 


When the start key is released, the data is rewritten back into storage 
and transferred to the O register. 


Note: \|n the test mode, invalid storage addresses are not checked, 
therefore the following SAR (Hi) bits are ignored: 


SK memory bits 0, 1, and 2, 
12/16K memory bits O and 1. 


A processor check will occur if the CE mode selector is changed from 
the alter storage position to display storage (or the reverse) and the 
storage test switch is not in the step position. 

2. Alter Storage. Data set up in address/data switches 3 and 4, is trans- 
ferred to the A register when the start key is operated. When the start 
key is released, the data is written into core storage at the address: 
specified by SAR, and transferred into the OQ register. Data may also 
be entered into main storage with the system console keyboard. This 
procedure is useful for hand-entering several continuous bytes of data 
into core storage. Data can be entered from the keyboard as follows: 


a. Load SAR with the main storage address where the first data byte 
is to be entered as per the instruction in alter SAR. 

b. Set the address increment switch to ON, and the storage test switch 
to STEP. 

c. Hexadecimal characters can now be entered by typing on the key- 
board. Each byte is entered as two key strokes. After each second 
key stroke the hexadecimal character is entered into main storage 
and the address in SAR is incremented by one. 

Only the keyboard keys 0 through 9, and A through F can be used to 

enter data. The use of any other keyboard key results in a keyboard 

lockup. To unlock the keyboard, note the address in SAR, and per- 
form a system reset to unlock the keyboard. Then reload SAR and 
retype the byte entered in error. 


3. Alter SAR. An address set up in the address/data switches 1 through 
4 is transferred into SAR through the [AR when the start key is 
operated. The IAR address will be the same as the address in SAR 
after an alter SAR operation. | 


Note: When the CE selector switch is rotated through the alter 
storage position, it causes a keyboard bail reset and unlocks the 
keyboard. If this action is undesired, a system reset should be 
performed to relock the keyboard. 


Step Mode. There are three positions in the step mode of operation. Each 
position controls the manner in which the processor performs the stored 
program. 


SYSTEM MAINTENANCE—Console and Maintenance Facilities 
Field Engineer Console (Part 4 of 4) 


1. Instruction Step. This mode causes one complete instruction to be 
performed with each operation of the start switch. The I-phase is 
performed when the switch is activated and the E-phase, if any, when 
the start switch is released. 

2. Machine Cycle Step. This mode advances a program instruction 
through one machine cycle with each operation of the start switch. 
When the start switch is activated, data in storage is accessed, modi- 
fied as required and the result displayed in the FE panel indicators. 
When the start key is released, the original data or the result (depen- 
ding on the instruction operation) is written back into storage. 

3 Clock Step. This mode advances the CPU clock through an odd- 
numbered clock cycle with each operation of the start switch, and an 
even-numbered clock cycle on the release of the start key. 


Note: The clock is allowed to run at the end of the I-phase during 
a start 1/O instruction, until the 1/O data transfer is complete. In the 
step mode, the start key is not functional during the time a I/O device 
is transferring data. | 

Halt identifier lights do not turn on when the CPU is in the clock 
step mode. 


Program Load Switch (Pushbutton) 


This switch is functionally the same as the one on the keyboard console 
and initiates loading a program into main storage. The following actions 
occur when this switch is on: 


1. All |/O and machine registers, controls, and status indicators are reset. 
2. The instruction address register is set to zero. 
2. The disk file data address register is reset to zero. The record in cylin- 


der zero, sector zero on one of the disks in disk drive one is read into 
storage starting at location 0000. The disk that provides the first 
record is selected by the setting of the disk select switch on the con- 
sole. | 


When the program load switch is released, the processing unit executes 
the instructions read into storage from cylinder zero, sector zero, starting 
at location OOOO. 

If disk drive one is not ready, the I/O attention light is turned on. When 
the program load switch is operated, it is necessary only to make disk drive 
one ready to complete the program load function. 


J7 


This jack is for connecting the alternate program load device (APLD) output 
signal to the CPU for diagnostic program loading or updating programs. 


2.4 ERROR LOG AND STATISTICAL DATA RECORDING 
The System/3 Model 6 accumulates two types of error recording. All 1/O 


device errors are recorded in an area called out board recording (OBR). 
Various counts of temporary errors (ones subsequently overcome by retry) 
and other statistical data are recorded in an area called statistical data 
recording (SDR). OBR 1/O errors cause the Q, R, sense bytes and other — 
data to be recorded in the OBR table located on sectors 7 and 8 of the 
fixed disk on drive 1. The most current OBR entry is found by using the 
first two bytes of sector 7 as displacement from the beginning of sector 7. 

Sectors 3 through 6 contain 512 two-byte counters which are used to 
accumulate statistics about temporary and permanent 1/O errors which 
have occurred. This data in these counters is called statistical data recording. 
SDR data is recorded on sectors 3 through 6 of the fixed disk on drive 1. 

The OBR and SDR data are retrieved from the disk and printed on the 
printer by the CE utility program ERAP. The ERAP ID is FF7 and is 
called in via DCP. | 


2.5 VOLTAGE LEVELS 


Acceptable voltage levels for monolithic system technology (MST)-1 and 
solid logic dense (SLD) 700 technology are: 


MST-1 Voltage Levels 


-0.613V Maximum Up 







-0.987V Minimum Up 


-1.567V Minimum Down 
-2.0V Maximum Down 


SLD-700 Voltage Levels 


15.0V Maximum Up 







2.0V Minimum Up 


0.66V Minimum Down 


-1.0V Maximum Down 


BR0644 


2.6 ERROR RECOVERY PROCEDURES 


Refer to the system operating guide for operator recovery procedures indi- 


cated by the I/O attention lights on the console. 


5406 FETMM (2/71) _—«i1-207 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities | 5406 FETMM_ = (6/70) 1-208 
Special Tools (Part 1 of 2) 


2.7 SPECIAL TOOLS 


The following special tools used in troubleshooting System/3 are either 
included in the System/3 shipping group or are available from the branch 
office, See the /ntegrated Maintenance Package User’s Guide for detailed 
descriptions of the tools. 


2./.1 CE Diagnostic Probe 


The CE diagnostic probe (see figure to the right, part 817971) acts as a free- 
running oscilloscope which replaces scope usage for most System/3 service 
calls. The probe can measure SLD 100/700 and MST-1 signal levels. The 
probe also has two MST-1 gates for gated operation. Consult the /ntegrated 
Maintenance Package User’s Guide for specific levels that trigger the probe. 
The lamps (part 454612) and probe tips (part 453163), shown in the dis- 

~ assembled view of the probe (shown to the right), are field replaceable. 


2.7.2 Jumper Wires 


Six jumper wires (see figure below) are included in each 5406 shipping 
group; two 6 inch wires (part 829117), two 12 inch wires (part 2588263) 
and two 18 inch wires (part 829118). These jumpers are for use with the 
MAP charts and diagnostic programs. 


Probes | 
(Part 453163) 





SS 
jm 
Se 


A 


7 


Y 


Bulbs 
(Part 454612) 


, 
6, 


a 


N 
f * 
‘ y 





BROG645 





BRO646 


2.7.3 Single Pin Extenders 


The single pin extender (shown below, part 2594238) is used to extend 
board pins when using the CE meter to measure voltage levels. The use of 
these pins eliminates shorting to adjacent pins when using the meter leads. 


BR0O647 


2.7.4 MST-1 Card Extender 


The MST-1 card extender (shown below, part 2360068) allows the CE to 
extend a card above the tops of adjacent cards on a board, This makes the 
module pins on the back of the card more accessible for probing with a 
scope or the diagnostic probe. These card extenders are stocked at the 
branch office. 





SS SSS es BRO648 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities | 
Special Tools (Part 2 of 2) 5406 FETMM _ = (6/70) 1-209 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities 
Alternate Program Load Device (Part 1 of 2) 


2.8 ALTERNATE PROGRAM LOAD DEVICE 


The alternate program load device (APLD) is a cassette tape recorder that 
serves as an alternate input device to the Model 6. It is used to load file 
diagnostics when they are unavailable from the file due to a malfunction. 
It is also used to put revisions into the disk resident diagnostic program 
libraries. | 


2.9.1 Interface Circuits 


The APLD attachment contains only pulse shaping circuitry. Error detection, 
tape speed synchronization, noise elimination, signal detection, data separa- 
tion, and de-serialization functions are all performed by the tape loader 
program. 

The interface circuits are contained on a single wide two high MST-1 card 
_ which is located on the printer attachment board (location A-A2B4). The 
function of the interface circuits is to convert the tape audio signals to 
machine readable MST-1 levels. They consist of: 


60 Hz noise filter 
Comparator 

Shaper 

Level Converter 
Polarity Hold Latch 


Oe OS 


The read signal is first filtered to eliminate 60 Hz noise. It is then com- 
pared to a reference voltage, and a signal is generated at the comparator 
output when a positive input signal swing is detected. The generated com- 
parator signal is shaped to the write signal pulse width by a single shot 
shaper. Then it is converted in the level converter to the desired logic level. 
The output of the level converter goes to a polarity hold latch which is 
conditioned during clock 2 of each CPU cycle. The output of the polarity 
hold latch is OR’ed with the ‘printer busy’ line. During a read data sample, 
the ‘printer busy’ condition is tested by performing a test 1/O. When ‘printer 
busy’ is present during the sample, a binary 1 is placed in core. When it is 
not present during the sample, a binary 0 is placed in core. 


2.8.2 Tapes | 

There are two types of tapes used with the alternate program load device. 

1. The first type of tape consists of the tape loader and the diagnostic 
control program (DCP). To load this tape, a 38 byte bootstrap program 


must be manually entered into core. Following the loader and DCP, 
there are a number of file section programs. , 


2. Thesecond type of tape takes the place of card input decks used with 
the editor program. This tape allows the editor to function nearly 


5406 FETMM ss (2/71) 





Output Socket Alternating Current Volume Record Level 


Adapter Socket 


unchanged from its normal mode, except that the card read routine 

is overlayed with a tape read routine. The tape consists of card images 
of the editor data deck (one card per tape record). During operation, 
each time the editor program calls for a card input, a tape image of 
the card is read in rather than the card. To use the card image tapes, 
DCP and the editor programs must be fully loaded. 


2.8.3 Programs 


To load programs from tape, refer to the procedures contained in the FE 
Diagnostic User’s Guide. 


Bootstrap Loader 


The bootstrap loader is a thirty-eight (38) byte manually entered program 
used to bring in the normal tape loader when the file is inoperable. This 
program contains no automatic tape speed synchronism, but instructions 
are provided in the tape MAPS for modification of timing constants if retry 
is required. 


Cassette 


Record 


4 Position Switch 


Bootstrap Loader: 


Storage 
Address 


005D 
0061 

0065 
0068 
OO6B 
OO6F 
0073 
0076 
0079 
007C 
0080 


Stop 

Rewind 

Forward 

Play 

BRO649 
Program Program Description 

C202005D ___Load address XR2 (O05D) 
AFD9FFFF _~ SLC (branch from itself 218 times) 
E1E20E TIO (for busy branch to OO6B) 
E08708 BC to 0065 
ACFFFFFF MVC 256 (approximately 772 us) 
AC62FFFF MVC 99 (approximately 303 us) 
BAO1FF SBN (set bit on) at O15C 
E1E21F TIO — (for busy branch to 007C) 
BBO1FF SBF at 01FC (set off) 
AED9SFFFF- ALC (218 position binary counter) 
E02008 BC — binary overflow 


1-210 


The tape loader is a three hundred fifty (350) byte tape read program with | 
the following features: : 
Printer 


Tape Loader (Normal) fe are ee ee ee ee ee ea 1 
| 
| 

| Busy 







1. Tape speed synchronization. 
2. Error detection (record hash total). | | 
3. Specification for length of data record and address where data is to 
be placed in memory. | 
Record number. 
~ FE communication via command and field indicator lights. | 
6. —_ Record identification (any normal input card for diagnostic control | 
program and/or section programs). 
7. Bit count (overflows beyond 8 bits are ignored). | 
8. Provision for restart in case of soft tape errors. a ee es a Ecc as eer ee J 













Level 
Converter 











Shaper 






Comparator 





Filter 


a 





2 


V-Ref | A-A2B4 Printer Busy 


Read MST Card 


BRO650 
Diagnostic Control Program (DCP) 


This is the standard DCP modified for tape use, and can be read in from the 
cassette so that it can be used with the file diagnostics. 


2.8.4 File Diagnostics 


These are the complete set of file diagnostic programs in sequential order. 
They are coupled with the MAPS for fault locating. 


2.8.5 APLD Setup 


1. Connect the 7.5 Vac adapter from the ac adapter socket to the ac 
convenience outlet. 

2. Connect the shielded audio cable from the cassette output socket to 
J1 on the CE panel. 


Note: When the audio cable is plugged into the cassette output 
socket, the cassette speaker is disabled. 


3: The volume control setting should be approximately 6. 
4. The read MST card is plugged into location A-A2B4. 
2.8.6 Maintenance 


For maintenance of the tape cassette, refer to the manufacturers handbook 
issued with the tape cassette. 


SYSTEM MAINTENANCE-—Console and Maintenance Facilities | | 
Alternate Program Load Device (Part 2 of 2) © | 5406 FETMM (2/71) 1-211 


Chapter 3. Preventive Maintenance 


3.1 SCHEDULED MAINTENANCE 


The preventive maintenance philosophy for the System/3 Model 6 is that it 
is done during unscheduled interrupts whenever possible. When an unsched- 
uled interrupt does not occur on a system within the time limits specified 
below, scheduled maintenance is performed.as follows: 


le Blowers—check every six months for proper operation. 
2.  Filters—replace every six months, if necessary. 
3 Memory—no preventive maintenance is performed if the memory is 


operating properly. If adjustments are required, the XYZ drive voltage 
is varied from —30V by +1.2V while exercising the BSM with a worst 
case pattern. This should establish an operating point. Adjustments are 
made using the voltmeter specified in chapter 4. 


SYSTEM MAINTENANCE-—Preventive Maintenance 


Preventive Maintenance Chart 5406 FETMM (6/70) 1-301 


Chapter 4. Checks, Adjustments, and Removals 


4.1 MONOLITHIC SYSTEM TECHNOLOGY (MST) MAINTENANCE 


All normal maintenance procedures for monolithic system technology com- 
ponents are found in the IBM Field Engineering Theory of Operations 
Manual, Monolithic System Technology Packaging, Tools, and Wiring Change 
Procedure. This manual includes information regarding: 


MST packaging 

Tools 

Wiring change procedure 
Emergency card repair 


4.2 MONOLITHIC TECHNOLOGY SYSTEM CARDS 


The lettering within a logical block on a systems diagram page gives the 
location of that block in the card gates. It also indicates other pertinent 
data as described in the MST packaging FETOM (described above). 
Identification of pins, panels, rows, and columns is also described in this 
manual. 

Logic block locations within the system diagrams are shown on system 
diagram card location charts. The system index contains the machine 
features indexing of automated logic diagrams (ALDS) and maintenance 8K Basic Storage Module (Probe Side) 
diagrams. BR1749 





4.3 BRIDGE BASIC STORAGE MODULE (BSM) 


For reliable storage operation, the BSM diagnostics should run 2 minutes 
without errors when the —30 volt XYZ drive voltage is biased 1.2 volts in 
either direction from its initial setting. If BSM operation is unreliable, 
a fault exists, or XYZ drive voltage (-30V) reoptimization is required, or 
strobe setting and —30V reoptimization is required. 

Proper setting for the —-30V power supply and the strobe settings for each 
BSM are recorded on a decal located on the XYZ current limiting resistor 
cover (see the figure to the right). 


Note: The —-30V power supply is self-adjusting for temperature and adjusts 
by —75 mV for each degree Fahrenheit temperature rise. 


If the BSM operation is unreliable, a fault should be the first problem 
suspected. The only repairs possible are card replacement, voltage and strobe 
adjustments, and repair of minor (visible) shorts, open diodes, or open cir- 
cuits. Major array failures (shorted diodes, internal opens, etc.) necessitate 
BSM replacement. | 

Most problems fall into 2 categories of component failures. 





Teg Normal circuit failures (card, loose connector, etc.) 


2. Array failures (shorted lines, open line, diode, etc.) {Gi Bade Storage Modus (Probe Side) 


Intermittent or random failures are treated separately. BR1750 


SYSTEM MAINTENANCE—-Checks, Adjustments, and Removals . : 
Storage Module (Part 1 of 11) | | 5406 FETMM (2/71) 1-401 


SYSTEM MAINTENANCE—Checks, Adjustments, and Removals | | | 5406 FETMM (2/71) 1-402 
Storage Module (Part 2 of 11) 


4.3.1 Fault Location 


Ifa failing pattern is not already evident, try manually storing and display- 
ing or scanning storage to establish a pattern. If this fails, run the storage 
diagnostics. 





8K Basic Storage Module (Card Side) 
BR1751 


te KE 





16K Basic Storage Module (Card Side) 


BR1752 


4.3.1.1 Circuit Failures 


All BSM problems should be approached as if there has been a circuit 
failure. Circuit failures (card, connector, etc.) can be broken into distinct 
patterns. For example: 


® Single bit—all addresses 
e Single bit—one block of addresses 
® Multiple bits—all addresses 


e Multiple bits—one block of addresses 


The ‘all addresses’ failure could be caused by the drive current source card 
or the control driver card. The ‘block of addresses’ failure could be caused 
by a defective gate driver card. For example, if SAR bit 7, 8 or 9 are always 


active in the failing address, the chart in the figure indicates the failure 
could be the Y-Lo gate driver. 


Single-bit or multiple-bit failures may be caused by a sense/inhibit card 


which also contains the SDR latch for that bit. 


Card location 


3,4,5 XXH4 XXH4 












Note: Bits 9-17 are 0-8 
when SAR bit 2 is active. 
Bit 8 and 17 is the P bit 










12, 13, 14 
15,16, 17 


BR1753 


Multiple-bit failures at all addresses may also be caused by the strobe driver 


card. (For card location, see ALD page SR224.) 


Using bridge map charts (trouble analysis flowcharts) allows repair of most 
of the failures by swapping or replacing cards. Use the CE pocket meter and 


diagnostic probe for help in locating and repairing the trouble. 


SYSTEM MAINTENANCE-—Checks, Adjustments, and Removals 
Storage Module (Part 3 of 11) 


Rd/Wr Call A 


Time 


Rd Set © 


8K-16K BSM | BSM Selection 






Drive 
sarsits | 1 | 2 —((3456| 789 | 10 11:12 [131415] 





1 
ALD Page —— ee SRO51 | SRO41 | SRO43} SRO31 SRO21 SRO22 
SRO 


Rd Hi 
Y Hi Decode (SAR 3, 4, 5, 6) 
Y Rd Current Sink 


Control 
Driver 


Rd Ctrl 


Wr Ctrl 





Y Rd Current Source 
Y-Lo Decode (SAR 7, 8, 9) 
























X-Y Gate 
Control 


X-Y Rd/Wr 
Drive Current 
Source 






Byte 

Sone ane XXF2 | XXE2 mee XXD2 XXB2 XXJ2 
(not used XXH2 Used ; 

on 8K) 


BR1754 


5406 FETMM 


(2/71) 


1-403 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals | 5406 FETMM (2/71) 1-404 
Storage Module (Part 4 of 11) . 


4.3.2 Array Failures 


If the array fails, replacement is necessary unless the failure can be traced 
to cabling defects, visual defects, or an open diode. Trouble caused by open 













: (000) B12 X Read Sink 
diodes can be repaired by patching a new diode across the open one. Shorted © en SaRREEAE 
X Read Hi Gate 
diodes require replacing the array. i dasa 
. X Read Lo ees 
bee (001) 2 
4.3.2.1 Single Bit, Multiple Address Failures Dt @ san 
> = 
A sense/inhibit (S/Z) problem usually shows up as an extra or missing bit SAR 13-1 Pea ae 12-0 
throughout an 8K block of storage (each sense/inhibit line passes through SAR 14=1 ns 
8,192 cores). If the sense/inhibit card is not at fault, check the wiring to the SAR 15-0 iat (000) 
inhibit current limiting resistor. (Refer to SRO71-076 and to SR264 for 1 


/\ 








locations.) Check that —30 volts appears on pin 2 of the affected resistor. ee 


Check also for a broken S/Z wire between the array and the back panel “wae be ate ee 
pins on the sense amplifier. A complete S/Z winding resistance should — 
measure approximately 14.0 ohms. If the open or shorted S/Z winding is 
within the core plane, replace the BSM. 





. X Write Hi Gate 
X Write Source 
(001) 


NOTES: 


XXD2 





1. Circted numbers refer to 
columns on chart. 
Refer to chart on SR 184 


. . cts : Diode Diode 2. 
4.3.2.2 Multiple Bits, Multiple Address Failures Pack Pack for Y Drive Selection. 
i sae - shina ae) 3. Refer to SR 204-224 for 
. e . Op boar op Soar i ions. 
If this type of failure cannot be corrected by card swapping or replacement, : epee eae 


an array fault probably exists. If the failure is related to a combination of 


KARA AAZ 


ms 





2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 
more than one address pattern, suspect a short between drive lines. H! ORDER LOW ORDER 
| HI ORDER DRIVE LINE PINS DIODE PACK -| piope pack DRIVE LINE PINS LOW ORDER 
ae \ : ADDRESS READ SINK WRITE SOURCE Hi ORDER LOW ORDER READ SOURCE WRITE SINK ADDRESS 
4,3,2.2.1 Continuity Check of XY Drive Lines. The charts on SR174 and ? ae i TOP BOARD TOP BOARD [>>> eae 
LARGE LARGE LARGE LARGE 

1 1 1 1 1 1 SAR BITS DIODE DIODE DIODE : DIODE SAR BITS 

SR 184 describe all X and Y drive lines and contain all the points (terminals) 10 11 12 BOARD BOARD PACK NO. PACK NO. BOARD BOARD 13 14 15 


for performing a continuity check. Example: See the figure to the right. 

This example is for the failing X-address of 000110. X-read current is 
shown from left to right through the array X-winding. X-write current is 
shown from right to left through the same array X-winding. 

(In the following discussion, column numbers refer to the chart on SR174.) 
Starting from the X-read lo gate, D2G10 (column 13) current flows to 
terminal 56 on the top diode board (column 12), through a diode in diode 

~ pack 25 on the top diode board (column 11), to pin 161 on top diode board 
(column 9), through the X-winding to pin 12 on the top diode board (column 
7), through a diode in diode pack 32 on the top diode board (column 6), to | EROSSe 
terminal 4 on the top diode board (column 3) to the X-read hi gate, E2B12 
(column 2). | 

Likewise, it can be seen that X-write current flows from the X-write hi 
gate, S2D11 (column 4), in the reverse direction through the X-winding, 
to the X-write lo gate, D2JO9 (column 15). 





~<@-——— Diode Locations 


md 
. 


Turn off power. 

Remove X gate cards D2 and E2. 

3. Probe the points shown with the ohmmeter; be sure to observe the 
polarity of the meter as indicated by the + or —. Expected meter 
readings are infinity (°°) or some resistance (R, unpredictable because 
of circuit variations and the meter in use). 


waveform of the Y-read current source with and without an open diode 
(see SR264). This method will identify an open array drive line if both 
YRD and YWR appear open. If either is correct, an open diode is likely. 
Make a continuity check to determine which of the two diodes in the line 


~ 


4.3,2.2,2 Locating an Open Diode. Because of the complex connections 
of the isolation diodes, a continuity check is difficult. To locate an open is open. | 

diode, use the method described next. The cards named are for the same lf an open diode exists, the charts of SR174 and SR184 indicate the 
failing X-address (000110) discussed in Section 4.3.2.2.1. Refer also to the . An open drive line may also be verified by scoping the source driver load polarity of the diode to be replaced. See the bottom of the figure above 
figure on the next page, ‘‘Locating an Open Diode.”’ resistor on the resistor panel. See page 1-408 ‘’Scope Pictures F’’ for the for diode locations with respect to the charts. 


4.3.2.2.2 Replacing an Open Diode. An individual diode cannot be removed 


since it is part of a module containing 16 diodes. Replacement consists of 
soldering an individual GY diode (part 2414891) over the defective one. 
(A shorted diode calls for replacement of the BSM.) 

When replacing a diode, use thermal set compound (part 814007) a as a heat 
sink. Wrap one end of a yellow wire to the wrap terminal on the diode board 
and solder the other end to the diode. Solder the remaining end of the diode 
to the solderable pin on the edge of the diode board. After diode replace- 
ment, check for reliable BSM operation. 


4.3.2.2.4 Exposing Bottom Diode Board. \f an open Y-drive line exists and 
the fault cannot be located on the top diode board, remove the BSM to ex- 
pose the bottom diode board. 


1. Disconnect all cables to the BSM. 

2. Remove all the cards. 

3. Remove the BSM (weight—approximately 18 pounds) and lay the 
unit on a table with the card side down, pin side up. 

4, Loosen the 4 nuts which hold the array onto the board. It is now 
connected by only the drive and sense-inhibit cables. 


Note: \t is now possible to raise the board separately leaving the 
array resting on the table and expose the bottom diode board, or 
you may continue. 


5, Turn the unit over, Support the array since it is connected only by 
wiring. 

6. Pull the array out vertically and turn it over so that the top side is 
down and lying on the card sockets. The bottom diode board is now 
completely exposed. 


4,3.2.2.5 BSM Replacement. Some systems supply —30 volts to the BSM 
with a single ‘mini-bus’ connector to the following points: C5D09, D5DO09Y, 
E5D09, F5D09, G5D09, H5D09, and J5D09 (see SR264). Earlier systems 
supplied —30V with a single wire to CoDO9, The remaining points were 
jumpered on the board, This includes the associated DO8 ground pins. 

When replacing a BSM it may be necessary to save the jumpers for use on 
the new BSM if your system does not use the ‘mini-bus’ connector. 


4.3.2.3 Poor So!der Connections and Welds 


If a problem appears to be an open diode or an internal open within the 
array, a complete resistance check should be made. Any poor solder connec- 
tions or welds should be resoldered. 

_ Also check for an open land pattern in the X-return card (for an X-drive 
line). If there is an open land pattern, use a piece of #30 wire to repair the 
break. 


4.3.2.4 Shorts Between Drive Lines 


Shorts between X- or Y-drive lines usually show up as dropping one or more 
bits of two addresses. In almost all cases, analysis of the failing addresses 
shows that two adjacent X- or Y-drive lines are the problem. Once the two 
lines are located, make a resistance check of the lines, moving from one end 
of the array to the other. Because of the resistance of the windings, less 


SYSTEM MAINTENANCE—Checks, Adjustments, and Removals 
Storage Module (Part 5 of 11) 


Example: Locating an open diode associated with the failing X-address of 


000110 
Read . Do D 1 
Source a | Sa Terminals EEE > RTE SH 
D2G10 56 , on Array 7 

ye B) SI 

161 

Write : Z zo 
; Sa 3 IN. Terminals i ' 20° | 

Sink PRE < | senab PORTE a crmercm 
D2J09 Do Diode Board 3 


IMPORTANT: Remove X-Gate Cards D2 and E2 


Probe: = co co 
Probe: = co or R 


Open winding 
Open land 
Open weld 












Probe: 
Probe: 


Probe: 20 = 


R er co 
Probe: 161 = . | 


resistance is seen as you get closer to the short. 
In almost all cases, the short is either some foreign material between two 


adjacent pins or two pins touching. A visual check with a strong light may 


show the short. However, if foreign material is causing the short, it may not 
be visible. Try passing a piece of paper between the pins at the area of the 
short. 


Read 


sem Sink 


E2B12 


Write 


m= Source 


E2D11 


Note: R = resistance 
6° = infinity (open) 


BRO655 


5406 FETMM 


(2/71) 


1-405 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals 
_ Storage Module (Part 6 of 11) 


4. 3.25 Defective Cores 


A defective core position usually shows up as dropping a single bit j ina 
single address. This type of problem can be caused by the individual core 
losing its magnetic properties because it is cracked, chipped, or broken, 

Vary the —30V drive voltage and the strobe setting to see if the rate of 
failure changes. If you are unable to obtain a reliable operating position, 
BSM replacement is necessary. See 4.3.4 and 4.3.5 for drive voltage and 
strobe reoptimization. | 


4.3.3 Intermittent or Random Failures 


If a failure pattern cannot be determined, check the following for possible 
failure causes. | | 
1. Using an oscilloscope, probe the: 


a. XY drive voltage pulses on the XY read and write current limiting 
resistors and compare them to those shown in BSM waveforms 
B, C, D and E, page 1-407 and 1-408. 


Note: Probe pins 1 and 3 are common. No pulse can be observed 
on resistor pin 2, since it is ground. 


b. Z drive voltage pulses on the Z (inhibit) current limiting resistors 
and compare them to those shown in BSM waveform F, page 
1-408A. 


Note: No pulse can be observed on resistor pin 2 since it is the 
—30V power supply connection. Note also that the magnitude of 
the pulses may vary slightly if the XYZ drive voltage setting is not 
at —30V. (XYZ drive voltage supply is a temperature correcting 
supply.) 

c. Control driver. (BSM waveform G, page 1-408A). 

d. Strobe driver (BSM waveform H, page 1-408B). 


2. Check for improper setting of the —-30V, +6V, —4V, -14V, and/or 
+3V. (Use a Weston 901 meter or equivalent when adjusting these 
voltages.) 


Note: The +3V supply should be adjusted with reference to +6V. 
This results in a negative reading. 


3. Check the voltage connectors to the large circuit board. (See SR264.) 
4, Check to see if the back panel resistor assemblies are misplugged. 
(See SR264.) 
5, Check for loose interface cables or terminator cards. (See SR 201, 224, 
228, 229.) 


6. Check for improper MST-1 levels at the interface. 


4.3.4 XYZ Drive Voltage (-30V) Reoptimization (8-16K) 


Reverify drive voltage marginal limits whenever replacing S/Z, timing, driver 
source, or strobe driver cards, 
To reoptimize the drive voltage: 


1, Loop storage diagnostics no. 96. 


2. Determine the upper drive voltage (—30V) limit by slowly decreasing 
the drive voltage reading until an error occurs. Record the last oper- 


ating voltage as the upper limit. If system reset and start does not 
start the diagnostic, set the drive voltage close to normal and reload 
the diagnostic. Determine the lower limit by slowly increasing the 
voltage reading until an error occurs (do not exceed a more negative 
voltage than —35V). Record the last operating voltage (or —35V) as 
the lower limit. 


Note: The BSM should run error free for a minimum of 30 seconds 
at the last operating point. 


The optimum drive vase is the average of the upper and the lower 
BSM limits. . 

If the difference between the upper and lower limits is less than 2.4 
volts, strobe reoptimization may be necessary. 


Note: When reoptimizing the drive voltage or strobe setting, a 
thermometer (part 5392366 or any standard thermometer) placed 
at the base of the array should read between 68 degrees and 86 
degrees Fahrenheit. The voltage may be reoptimized outside of 
this range, but a check at the current temperature should be made 
as soon as possible. 


4.3.5 Strobe Setting Reoptimization (8-16K) 


To reoptimize the strobe setting: 


ds 
2. 


Loop storage diagnostics no. 96. 


Refer to the decal on the XYZ current limiting resistor cover. Use 

the present strobe setting and determine the upper and lower XYZ 
drive voltage limit, which is explained by 4.3.4 step 2. Record these 
limits as shown by point A and B in scope picture A (on this page). 
Repeat 4.3.4 step 2 for strobe setting 10, 20 and 30 ns before and 
after the present strobe setting. Strobe settings are made on the strobe 
driver card (SR254). Plot the XYZ drive voltage limits as shown in the 
figure. Set final strobe timing between points where the XYZ driver 
voltage limits start to drop off. | 


If the difference between the upper and lower limits is less than 2.4 
volts, a fault probably exists which must be corrected before further 
reoptimization is attempted. 


Set the optimum drive voltage (—30V) which is the average of the 
upper and lower BSM limits at the selected strobe setting. 


BSM access time is measured from when ‘Rd call/Write call’ becomes 
active, until all sense data latches are active. (Measure access time 
while writing all ones into the BSM.) Access time must be 445ns or 
less. If necessary, reset the strobe setting to obtain 445ns or less. 


The minimum 2.4 volt spread for XYZ voltage must still be met at the 
new setting. 


Note. !f the strobe driver card is replaced, strobe jumpers must be put 
in the new strobe driver card. 





5406 FETMM = (2/71) 1-406 


Optimum setting for XYZ 
35V drive voltage and strobe 
setting is recorded on a 
decal, which is located on 
pin side of BSM 


Do not go beyond —35V ee 


This optimum setting 
can change when a 
component is replaced 
ina BSM 


Points where diagnostics 
fail 


Typical strobe timing 


10ns Strobe Increments 


Scope Picture A 


Optimization—Strobe and XYZ Drive Voltage 
| BR1775 


CE Mode Selector 
Data 
Storage Test 








Alter Storage 
‘00’ 














Address Increment 


Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Signal Pin: 
| Signal Name: 


Channel 2 


Signal Pin: 
Signal Name: 





1 Memory Cycle 


Alter Storage 
00’ 


CE Mode Selector 
Data 
Storage Test 


















Address Increment 


Syne: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1° 


Signal Pin: 
Signal Name: 


Channel 2 


Signal Pin: 
Signal Name: 





*Ground 


BSM Waveforms B 


Lower level determined 
by -30Vdc setting 


SYSTEM MAINTENANCE -Checks, Adjustments, and Removals 
Storage Module (Part 7 of 11) 


Vertical Gain: 


Vertical Gain: 


Vertical Gain: 


Vertical Gain: 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4B3G03 (8K-16K BSM) 
Reset 


1 Vicm | 
B4A2B02 (8K-16K BSM) 
Rd Call Wr Call 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1V/em 
B4A2B02 (8K-16K BSM) 
Rd Call Wr Call © 


10 V/cm 
B4J2G05 (8K-16K BSM) 
X Rd Current Source Resistor 


BRO657A 





CE Mode Selector 
Data 













Alter Storage 
‘00’ 








Storage Test 
Address Increment 





Alter Storage 
‘00’ 


CE Mode Selector 
Data 





















Storage Test 
Address Increment 





*Ground 


BSM Waveforms C 


Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Signal Pin: 
Signal Name: 


Channel 2 


Signal Pin: 
Signal Name: 


Lower level determined 
by -30Vdc setting 


Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Signal Pin: 
Signal Name: 


Channel 2 


Signal Pin: 
Signal Name: 


Lower level determined 
by -30Vdc setting 


Vertical Gain: 


Vertical Gain: 


Vertical Gain: 


Vertical Gain: 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4J2J13 (8K-16K BSM) 
Read Time 


10 V/cm 
B4J2G05 (8K-16K BSM) 
X Rd Current Source Resistor 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4J2J13 (8K-16K BSM) 
Read Time 


10 V/cm 
B4J2J10 (8K-16K BSM) 
X Write Current Source Resistor 


BRO658A 


5406 FETMM (2/71) 1-407 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals 
Storage Module (Part 8 of 11) | 


CE Mode Selector 
‘Data | 
Storage Test 


Alter Storage 
‘00° : 





















Address Increment ~On 


a Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Signal Pin: 
Signal Name: 


Channel 2 


Signal Pin: 
Signal Name: 





Lower level determined 
by -30Vdce setting 


CE Mode Selector _ Alter Storage 
Data | 00' 
Storage Test ~ | Run 
"Address Increment | 


% Sync: 
Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Signal Pin: 
Signal Name: 


Channel 2 


Signal Pin: 
Signal Name: 





*Ground 


Lower level determined 


BSM Waveforms D by -30Vdc setting 


Vertical Gain: 


Vertical Gain: 


Vertical Gain: 


Vertical Gain: 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4J2BQ3 (8K-16K BSM) 
Write Time 


10 V/cm 
B4J2J10 (8K-16K BSM) 
X Write Current Source Resistor 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4A2B02 (8K-16K BSM) 
Rd Call Wr Call 


10 V/cm 


B4J2D05 (8K-16K BSM) 
Y Read Current Source Resistor 


BRO659A 





CE Mode Selector 
Data 
Storage Test 


Alter Storage 
‘'00' 

















Address Increment 





CE Mode Selector Alter Storage 
‘Data | ‘00’ - | 
Storage Test 

Address Increment 


*Ground 


BSM Waveforms E 


Lower level determined 
by -30Vdc setting 





Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Channel 2 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Channel 2 


Vertical Gain: 


Signal Pin: 
Signal Name: 


5406 FETMM ss (2/71) 1-408 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4J2B03 (8K-16K BSM) 
Write Time 


10 V/cm 
B4J2D07 (8K-16K BSM) 
Y Write Current Source Resistor 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4A2B02 (8K-16K BSM) 
Rd Call Wr Call 


1 V/cm 
B4J2B03 (8K-16K BSM) 
Write Time 


BRO660A 


CE Mode Selector Alter Storage CE Mode Selector Alter Storage 
Data — ‘00’ 


Storage Test 


Data ‘00’ 
Storage Test 


Address Increment 


Address Increment 





Lower level determined 
by -30Vdc setting 








* Sync: Plus External Sync: Plus External 
Time Base: 200ns/cm Time Base: 200ns/cm 
Sync Pin: B4A1D11 
Sync: Plus External Signal Name: Reset 
Time Base: 200ns/cm | 
Sync Pin: B4A1D11 Channel 1 
Signal Name: Reset Vertical Gain: 1V/cm 
eS Signal Pin: B4B2B03 (8K-16K BSM) 
Channel 1 : Signal Name: Rd Control 
Vertical Gain: 1V/cm 
Signal Pin: B4A2B02 (8K-16K BSM) Channel 2 
Signal Name: Rd Call Wr Call Vertical Gain: 10V/cm 
Signal Pin: B4B2D10 (8K-16K BSM) 
Channel 2 Signal Name: X Rd Lo Gate Ctrl 
Vertical Gain: 10V/cm 
Signal Pin: | B4J4G10 (8K-16K BSM) 
Signal Name: Z Load Bit O 









X Rd or Y Wr Lo Gate Ctrl signal is shown: 
for reference only. This is a current wave- 
form and can be a different level at similar 


test points in a BSM, and can be a different 


CE Mode Selector Alter Storage level at the same test point and different 
Data *00’ BSMs. 


Storage Test 


CE Mode Selector Alter Storage 
Data | "00° 
Storage Test 





Address Increment Address Increment 











Sync: Plus External Sync: Plus External 
Time Base: 200ns/cm Time Base: 200ns/cm 
Sync Pin: B4A1D11 Sync Pin: B4A1D11 
Signal Name: Reset Signal Name: Reset 
Channel 1 Channel 1 
Vertical Gain: 1V/cm Vertical Gain: 1V/cm 
i in: Signal Pin: B4B2B04 (8K-16K BSM 
Signal Pin B4J4J04 BK-I6K BSM ignal Pin | ( ) 
Signal Name: Inhibit Byte 1 Signal Name: Wr Ctrl 
Channel 2 Channel 2 
Vertical Gain: 10V/cm Vertical Gain: 10V/cm 
Signal Pin: B4J4G10 (8K-16K BSM) Signal Pin: B4B2D06 (8K-16K BSM) 
Signal Name: Z Load Bit O Signal Name: . X Wr Lo Gate Ctrl 
ereung Lower level determined oe 
BSM Waveforms F by -30Vdc setting BSM Waveforms 
BRO661A BR1756 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals 
Storage Module (Part 9 of 11) 


5406 FETMM (2/71) 1-408A 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals 
Storage Module (Part 10 of 11) 


CE Mode Selector | Alter Storage 
Data ‘00’ 
Storage Test 


Address Increment On 


a 

ne ae 
eRe 
Tee 
Rae 
BESeRE 


This time is determined by the 
BSM strobe card adjustment 


CE Mode Selector 
Data 
Storage Test 











Alter Storage 
a F F ’ 








Address Increment 





% 





*Ground 


BSM Waveforms H 


Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Channel 2 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Sync: 

Time Base: 
Sync Pin: 
Signal Name: 


Channel 1 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Channel 2 


Vertical Gain: 


Signal Pin: 
Signal Name: 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4A2B02 (8K-16K BSM) 
Rd Call Wr Call 


5 V/cm 
B4B5D10 (8K-16K BSM) 
Strobe Bits 0-8 


Plus External 
200ns/cm 
B4A1D11 
Reset 


1 V/cm 
B4A2B02 (8K-16K BSM) 
Rd Call Wr Call 


1 V/cm 
B4J4B05 (8K-16K BSM) 
Sense Bit O 


BR1757 





Alter Storage 
EE! 
Run 
On 


CE Mode Selector 
‘Data 
Storage Test 


















Address Increment 


This is a ‘three exposure’ picture. ‘Rd Call 
Wr Call’, and ‘Strobe’ are shown only for 
time reference points. 





Cores being changed from ‘1’ to ‘0’ at read 
time. Any one address can be positive or 
negative. 


Note: Core output measured with Tektronix 453 scope as follows: 


Channel 1 and 2 set for 100 Mv/cm 
‘Mode’ switch set to ’Add’ 


Channel 2 ‘Invert’ switch set to ‘Add’ 
Channel 1 signal pin — B4J4B02 (8K-16K BSM) 
Channel 2 signal pin — B4J4D02 (8K-16K BSM) 


*Ground 


BSM Waveforms 


5406 FETMM (2/71) 


Sync: 


Time Base: 


Sync Pin: 


Signal Name: 


Rd Call Wr Cail 


Plus External 
200ns/cm 
B4A1D11 
Reset 


B4A2B02 


1 V/cm (8K-16K BSM) 


- Strobe Bits 0-8 


10 V/cm 


Core output writing ‘1’ in all bit positions. 


Cores being changed from ‘0’ to ‘1’ at write 
time. Any one address can be positive or 


1-408B 


B4J4B07 (8K-16K BSM) 


BR1758 


These are ‘Three’ exposure pictures. ‘Rd Call Wr Call’ 
and ‘Strobe’ are included for horizontal references. 


CE Mode Selector 
Data 
Storage Test 


Alter Storage 
‘00’ 
















Address Increment 





CE Mode Selector 
Data 
Storage Test 









Alter Storage 
‘80’ 









Address Increment 





*Ground 


BSM Waveforms 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals 


Storage Module (Part 11 of 11) 


Sync: Plus External 
Time Base: 200ns/cm 
Sync Pin: B4A1D11 
Signal Name: Reset 


Rd Call Wr Call B4A2B02 
1 V/cm (8K-16K BSM) 


Strobe Bits 0-8 B4J4B07 (8K-16K BSM) 


Core output writing ‘0’ in all bit positions. 


See Note on waveform located on right 
hand side of page 1-408B. 


Sync: Plus External 
Time Base: 200ns/cm 
Sync Pin: B4A1D11 
Signal Name: Reset 


Rd Call Wr Call B4A2B02 (8K-16K BSM) 
1 V/cm 


Strobe Bits 0-8 B4J4B07 (8K-16K BSM) 
10 V/cm 


Core output writing ‘1’ in this bit position 
and ‘0’ in all other bit positions. See Note 
on waveform located on right hand side of 
page 1-408B. 


BR1759 





CE Mode Selector 
Storage Test 


Alter’Storage 














Run 
Off 





Address Increment 


This is a composite picture which | 
shows a good drive line, and an 
open drive line (broken weld in 
array). 





This is a double exposure picture. 
The highest down level shows a 
good drive line. The lowest down 
level shows 2 drive lines shorted 
together. 





*Ground 


BSM Waveforms 


Sync: Plus External 
Time Base: 200ns/cm 
Sync Pin: B4A1D11 
Signal Name: Reset 


Good drive line measured at 

10 V/cm 

B4J2D05 (8K-16K BSM) 

‘Y Read Current Source Resistor’ 


Open drive line measured at 

10 V/cm 

B4J2D05 (8K-16K BSM) 

‘Y Read Current Source Resistor’ 


Note: These points are in series 
with the current source trans- 
former primary therefore in- 
directly shows the failure. 


5 V/cm 
B4J2D05 (8K-16K BSM) 
‘Y Read Current Source Resistor’ 


BR1760 


5406 FETMM = (2/71) 1-408C 


Loosen Screw 


4.4 KEYBOARD 4.4.4 Keyboard Encode Board " TI. — (both sides) 
For maintenance information on the basic keyboard, refer to the Field Troubleshooting procedures for the keyboard encode board can be found 
Engineering Theory-Maintenance Manual, Elastic Diaphragm Encoded Key- in the system automated logics on pages PKO30 and PK031. Information 
boards, Order No. SY27-0073. on these pages includes keyboard voltages, bail magnet voltages, and test 
Refer to the figure at the right for the location of components to be points for weighted codes. 
removed. 


4.4.1 Keyboard Removal 


1. Remove power from the system. 

2. Pull forward the top left hand side of the console panel (over the 
command lights). Remove the switch cover on the right hand side of 
the console by pulling it straight forward. | 

3: Loosen, but do not remove (1) the screw above and to the left of the 
lamp test switch, (2) the screw at the top right corner of the switch 
mounting plate. | 

4. Remove the two screws that mount the keyboard to the console pan. 
These screws are located under the front of the table top of the ao 
machine. | | | oj. Me 

Remove the console cover by pulling it straight up and towards you. | ) i ee y 

Remove the two screws (one on each side) of the console panel. “sf 

Pivot the console panel back out of the way. 

Remove the four nuts (one on each corner) of the keyboard mounting 

bracket. | 

9, Disconnect the signal cable located on the left hand side and under 
the encode board. 

10. Remove the yellow wire from the lower contact of the inquiry request 
switch. 

11. Disconnect the plug connector. It may be necessary to lift the key- 
board up and to the right to gain access to this plug. 

12. Lift the keyboard up and out of the machine. 


Sa 


Table Top 


4.4.2 Keyboard Replacement 





Note: Check that all leaf springs are in their proper position relative 


| ' Remove Nuts 
to their respective key lever. 


| 

(two on each side) | 
Step 8 | | 
| 








1. Perform the above steps in the reverse order. 

2. Check that there are no binds between the console cover and the 
keyboard. If there are, loosen the four nuts that mount the keyboard 
and reposition the keyboard until there are no binds between the 
keys and the console cover. 


Pivot Back 


4.4.3 Console Lamps 


Test the console indicator lamps with the CE lamp test switch. 


4.4.3.1 Lamp Removal 


1, Pull the console panel forward to expose the lamps. 
2. | Remove the faulty lamp by pulling it forward out of the panel. 
3. Insert a new lamp in its place by pushing it backwards into the 
socket. Remove Screw 


(one each side) 


Step 6 | BRO662 


SYSTEM MAINTENANCE—Checks, Adjustments, and Removals 


Keyboard — : 5406 FETMM = (6/70) 1-409 


SYSTEM MAINTENANCE-Checks, Adjustments, and Removals 
Single Shots . 


4.5 SINGLE SHOTS 


All single shot adjustment procedures are covered in the MAP charts, They 
should be adjusted to the time durations called out in the MAP charts or 
the ALDs. The description of single shots on this page should be used to 
locate the single shot on the board and in the ALDs. 


4.5.1 Use Meter Single Shot 


The use meter single shot is located on gate A, board B1, card S4 (A-B1S4). 


Refer to ALD page CR101 for the duration of the pulse. 


5406 FETMM (6/70) ‘1-410 


4.5.2 Printer Attachment Single Shots | 4.5.3 Ledger Card Device Attachment Single Shots 

The illustration below shows the location of the printer attachment single The illustration below shows the location of the ledger card device attach- 
shots. ment single shots. 

End of Card 


End of Card 


SS3 


SSA 


i ssi 


SSZ 





Gate A, Board A2, Card Q2 (A-A2Q2) 


Gate A, Board A2, Card D4 (A- 
ALD Pages PR111 and PR112 (A-A2D4) 


ALD Pages PR711 and PR712 


End of Card End of Card 
SSW 
SSX 


| ss2 


SSY 





Gate A, Board A2, Card 03 (A-A203) ALD Pages PR121 and PR122 Gate A. Board A2, Card D5 (A-A2D5) 
Single shot 1A (pin feed carriage) is located on Gate A, Board A2, Card U2 (A-A2U2), ALD Pages PR721 and PR 722 


~ ALD Page PR123. BRO664 


BRO663 


4.6 DISK DRIVE 


Note: 


If system power is off, the file drawers may be opened by inserting 


a small screwdriver in an opening in the right hand file side cover and lifting 
_ the interposer. The drawer may then be opened in a normal manner. 


4.6.1 


Disk Drive Service Position 


To move the file to its rear service position, follow the steps below: 


tL 


4.6.2 


Open the file drawer and loosen four front cover mounting screws 

and remove front cover. Remove the two lower screws C3 from 
the slide base. 
Remove the cover at the rear of the file enclosure. 


Note: If the lower file drawer is to be moved to the rear service 
position, remove bracket @:¥ : 





The file slide mounting base may now be pushed to its rear service 
position. 


File Drawer Interlock Adjustment 


Move the upper and lower drawer (if installed) to the rear service 
position. 


Note: \f a second 5444 is not installed, remove the lower front cover 
. Two screws hold the lower cover in place and these screws are 
accessible when the top slide base is moved to the rear service position. 


Remove the right hand side cover © . The 8 screws that hold the 
side cover in place are accessible when the drawers are moved to the 
rear service position. 





Note: Adjustments in items 3 and 4 need not be made unless the 
front covers are out of alignment. 





Reinstall the drawer front covers and adjust vertically with screws a 
so that the top edge of the upper cover is 1/4 inch below and parallel 
with the lower surface of the table top. 

a. if a second 5444 is installed, (lower drawer) adjust the lower front 
cover so that the bottom edge is flush with the lower edge of the 
system frame with screws ‘ 

b. If a second file is not installed, adjust the lower front cover eon 
in adjustment 3a. 

Adjust the EMC blades @fg) (top and bottom for each drawer) so the 

blade enters the center of the finger stock C> located in the cover. 











Adjust the drawer latch retaining nut @gJ)so the latch is horizontal in 
its rest position. (This is a preliminary adjustment.) 


The latch stud is adjusted to hold the drawer securely closed and 
still allow the drawer latch to release and latch easily. 


Note. The adjustment made instep 5 should not keep the drawer latch 
from resting on the latch stud when the drawer is closed. Re- 
adjust the drawer latch retaining nut, if necessary, to meet this 
requirement. 


SYSTEM MAINTENANCE-—Checks, Adjustments, and Removals 


5444 Disk 


8. Adjust the solenoid bracket @™ 







Solenoid Coll 





Interposer 











312 to .372 BEE 
(7,92 to 9,45) Bas 








Ue 


— a es ee (yee 


Note 1, step 7 — 







Latch 


040 to .080 
(1,02 to 2,03) 





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oo ee one nen eta te eta tote tacetetot ene tene tater e te ene ere ete era tane te rere ee ene e etre 8ne Teneo ene ee 0 tnt 0 0 a8 01e 0101010100 0.010.010.010.0.8,0.0-0,0.0,8,0,0.0.0,0,0.0.0,0,8.000.00.06,01 0.000105 0 ele leu! 


eee O 
oer e ete 010. 0.8. 0.0.0.8 0 0 0.0 6 0 © 00 6 0.6 00 00080 O OOo tet eto te tone eens one O one ooo ooo ono 0h 6 ooo 108 oOo oo OOo 8 O oe 000008 0 6000220 0.000.006 8 0.000.060.0000 0.0. 6-0.0 0.0 7,99 9.0, 
oreo tate te rene eens 0 0100 01800010 0'0'0 0 0.0.0-0.0.0-0.0-0-0.0.5. 0.0.0.0. 0.0.0 06 0.0.6.0. 0 0 0.0.0 0.0 000 6 0100000 O OOOO e eee eta Motel ete et ete nenetern ete tetera ene an ere ks rete ener ee ee beet e eee ete se ere 8 ae 


one aro 0 0.0.0.0. 0-0-0-0.0.0.0.0-0-0.0.0.0.0.0.8.0. 9.0.0 00.0 6 010000000000. 0.8 Oot etetet an 
eee ec tena ta ta ete eet ere een aten arene eee ene Bo ote see ee 20 ne Oe 8 ee 88 8 ee 8 OO ROO eC RCO SOOO ETO OO SO ORE OOO CCC COCECESORE OE SEDOOTOOETSESHSEOOSEOS ESOL OT E® 


BRO665A 





d. Move the interlock mounting bracket cS vertically so interposer to 
latch (interlock surfaces) clearance is 040 to .080 inches. The drawer 
latch must be holding against the latch stud (in a closed position), and 
the interposer should be butted against the drawer latch as shown in 
note 1 in the figure. | | 





a&)so that the solenoid coil is from .312 
to .3/72 inches above the interposer when the interposer is at rest. The 
bottom surface of the solenoid coil must remain parallel to the top 
edge of the interposer during this adjustment. 


10. 


Volts 





Adjust the switch bracket @ 9 to close the switch contacts when the 
drawer is closed. The switch contacts should not transfer when the 
.060 to .080 inch travel of the latch is moved up toward the inter- 
poser. After this adjustment is made, insure that the switch actuator 
does not raise above the top surface of latch stud EP 
drawer is open. This is to prevent damage to the switch actuator, by 
the drawer latch, when the drawer is closed. 


The solenoid should attract the interposer to its released position when 
the system power is turned on and the disk drive power is off. The 
interposer should freely drop to prevent the drawer from being opened 
when the system power is turned off, . 


Data Separator Adjustment 


Remove card in location A-A1J2 to select ‘read gate spin 0’ and ‘read © 
gate’ for data separator A card. 

Disable ‘+spin O read data’ and ‘tspin 1 read data’ inputs to data sepa- 
rator A, with jumpers to —4 volts (D4G13 to D4B06) and (D4J13 to 
D4G06). | 

Disable ‘ratio circuit 2’ output on data separator A with jumper to 
logic ground (D4B07 to D4D08). 

Jumper ‘3.177 MHz oscillator output’ signal on oscillator card (D3D07) 
into data separator A card (D4G03). 

Observe ‘ramp’ waveform on data separator B output (E4G02). 

Adjust potentiometer on data separator B card (A-A1E4) until ‘ramp’ 
waveform is swinging equally about logic ground with a +100 millivolt 
tolerance (i.e., V1 should equal V2 within +100 mV). 





Vi-— —A—_—_ 
Vv = Time 
V2 as ~ 
Bit Cell 
“2% 630 Nanosec 
BRO666 


5406 FETMM (2/71) 1-411 


SYSTEM MAINTENANCE-—Checks, Adjustments, and Removals 
5496 Data Recorder 


4.7 DATA RECORDER FE LATCH 


A spare latch in the data recorder is used as a FE latch to aid in trouble- 
shooting (with the MAP charts or for general troubleshooting). This latch is 
used when the data recorder is located away from the central processing 
unit and it is impossible to view the CE probe when operating the console. 

The following procedures apply to questions asked by the MAP charts for 
the data recorder. 


4.7.1 “Pulse on Line?” 


1, Check point to be monitored with CE probe. If point is up, jumper it 
to A-A1A2B08. Jumper A-A1A2D09 to ground. If point is down, 
jumper it to A-A1A2D09. 

2. Momentarily apply a minus SLD pulse or ground to A-A1A2B06 to 
reset the FE latch. 

3. Jumper A-A1A2D07 to the CE probe input. Rerun the program. 

4. -\If a pulse occurs, A-A1A2D07 is plus and the probe red light or up 
light is on. 


4.7.2 “‘Level Change Down?” 


1. Jumper A-A1A2D09 to ground to negate the 4-way AND block. 

2. Momentarily apply a minus SLD pulse or ground to A-A1A2B06 to 
reset the FE latch. 

3. Jumper A-A1A2B08 to the point to be monitored. 

4, Jumper A-A1A2D07 to the CE probe input. Rerun the program. 

5. If the level changes down, A-A1A2D07 is plus and the probe red 
light or up light is on. | 


4.7.3 “Level Change Plus?” 


1. Check point to be monitored with CE probe directly to see if already 
minus or down (it should be in this state to check for plus change). 

2. Jumper point to be monitored to A-A1A2D09. 

3. Momentarily apply a minus SLD pulse or ground to A-A1A2B06 to 
reset the FE latch. 

4, Jumper A-A1A2D07 to CE probe input. Rerun the program. 

5, If the level changes plus, A-A1A2D07 is plus and the probe red light 
or up light is on. 


A2D09 


A-A1 Board A-A1 Board 





A2B08 O 
FE Latch 


A2D11 
A2B10 | 
A2B12 


—<O A2D07 


A2B06 


FE Auxiliary Switch 


| PR AIDS 


+6V 





A2D03 


Stacker 
Full Lamp 





BRO667 


5406 FETMM 


(6/70) 


1-412 


Chapter 5. Power and Cooling 


DANGER 


Unless CB1 is turned off, power is available at K1 and K2 input terminals 
and at transformer (T3) terminals. The 24 volt control voltage is also not 
turned off. 

Replacements of power supply components generally follows the replace- 
ment philosophy of the system; that is, replacement is limited to voltage 
regulator cards, fuses, and relays, However, in some cases it will be necessary 
to replace the series regulator and the filter capacitors. 


5.1 INPUT POWER REQUIREMENTS 


The input power requirements for the System/3 Model 6 are: 
1. 60 Hertz—200, 208, and 230 Vac 3 phase at 30 amps 
2. 50 Hertz—200, 220, 235, 380, and 408 Vac 3 phase at 30 amps 


5.2 POWER SUPPLY OUTPUTS 


The power supply outputs and the location of each supply are shown below. 
The primary use of each of the supplies is also given, The using system 
supplies —-30V, +6V, and —4V to the BSM. An internal BSM +3V and V 
sense (—14V) is generated from the +6V and the —30V respectively. The 
—30V is a temperature compensated drive voltage. | 

In power sequencing, the —30V is the last up and the first down, with 
respect to the —4V and +6V. 


SR chee ar tien 


| 424 Vde at 25 amps | Vdc at 25 | 424 Vde at 25 amps | | WOUnits Units 


+24 Vdc Control Voltage hee eel 
Power Sequencing 

-12 Vde BSCA (medium 
speed only) 


--4 Vde at 32 amps 


— 


SYSTEM MAINTENANCE-Power and Cooling 
Power Input, Output, Sequencing, and MST Regulators 






















B gate only (used in 
non-printed circuit 
board sequence panel 
machines only) 












B gate only (used in 
printed circuit board 
sequence panel 
machines only) 


BRO668A 


5.2.1 Checks and Adjustments 


All voltage measurements should be made in a normal environment (temp- 
erature between 68 degrees and 86 degrees Fahrenheit) with a Weston 901 
meter or its equivalent. 


The +3V supply may be adjusted by connecting meter leads to C4J03 
(minus) and C4G11 (plus). Then adjust potentiometer on the upper half of 
card C4 (board B3 for up to 16K storage). The +3V is set by referencing it 
to the +6V (meter reading will be 3V). 

The 14V supply may be adjusted by using the lower potentiometer on the 
same card (C4). Connect meter leads to C4J11 (minus) and C4D08 (plus) 
and adjust for 14 + 0.05 volts. 

See 5.5 and 5.6 for the adjustment of the —4V and +6V supplies. See 4.3.4 
for the adjustment of the —30V supply. 


5.3 POWER SEQUENCING 


Power sequencing is controlled by the 24 Vdc control voltage. The power 
supplies come on in the following order: 


1. —4V logic voltage 3. —30 Vdc storage supply 
2. +6 Vdc logic voltage 4, +24 Vdc supply 


Power On Sequence. 


Power on Switch | 


180-220 ms Le 


| 300-600 ms 
50-100 ms 
+6Volts — 


—4 Volts 











100-300 ms 
~| wa 1400 ms (See note 1) 
—30 Volts 
400-600 ms 
Roane 

+24V to 1/O 
If power on sequencing is not completed, the power on light 100-200 ms 

ee ffeeeeereeneneeeasecemneananes 





Power On Light 





Note: +24 Volt control voltage is on whenever the main line switch is on. 


_ Note 1: For machines with printed circuit board sequence panel, the delay of 


—30V is approximately 500 ms. 
| BRO669A 


Power Off Sequence 


+24 Volts 


me N 


—30 Volts 150-250 ms 


—4 Volts 13-5 sec el 


200-300 ms 


+6 Volts 100-200 me] 
200-300 ms 


Note: +24 volt control voltage is on whenever main line switch is on. 


BRO670A 


5.4 MST REGULATORS 


The monolithic solid technology (MST) regulator trips when the system 
experiences an overcurrent condition (approximately 15% above the set 
current) or an overvoltage condition (4.7 volts). When this regulator trips, 
the system powers down and thus is protected from high currents and vol- 
tages. Refer to the figure below for a graphic representation of the MST 
regulator. Also note the following: 


1. E12 must be tied to the up (most positive) level. 

2. E8 goes to ground when the regulator trips (overcurrent or over- 
voltage condition). 

3. E8 of the —30 Vdc regulator goes to ground when the output o the 
+6 Vdc regulator is lower than 5.28V. 


Gate Input 
‘(Laminar Bus) 





Start Point to Ground (Error Signal) 


BROG7/1 


5406 FETMM ss (2/71) 1-501 


SYSTEM MAINTENANCE-—Power and Cooling | | 5406 FETMM = (2/71) | 1-502. 
—4 Volt and +6 Volt Power Supplies 


5.5 ADJUSTMENT OF THE —4 VOLT POWER SUPPLY 


5.5.1 Overcurrent Adjustment 


1. Connect the meter across the 4 volt load between E2 (—4V) and E4 
(ground) on regulator. - 


2. Adjust the voltage adjustment potentiometer (shown below) to —4.6V. 


Do not go beyond this. Set the overcurrent regulator to trip. If you 
cannot reach —4.6V before the regulator trips, turn the overcurrent 
adjustment clockwise until you can reach —4.6V before it trips. 
3. When the overcurrent adjustment trips, the machine will power down. 
Turn the voltage adjustment back down and power up the machine. 
5, Adjust the voltage adjustment potentiometer as given in 5.5.2, 


- 


5.5.2 Voltage Adjustment 


1. Connect meter between E2 (—4V) and E4 (ground) on regulator. 
2. Adjust voltage for —4.15V. : 
3. Connect meter across A-B1C2B06 (—4V) and A-B1C2D08 (ground). 
| This voltage should fall between —3.85 volts and —4.15 volts. 
4. If voltage measured in step 3 is out of tolerance, readjust the —4 volt 


supply. 


5.5.3 Overvoltage Adjustment 


There is no field adjustment for overvoltage. It is set and sealed at the time 
of manufacture, Replace regulator card if overvoltage condition fails to trip 
regulator (5.4). 


Voltage Adjustment Potentiometer 


4 and 6 Volt Cards 


Component Side 


Overcurrent 
Adjustment 





Overvoltage 
Adjustment 


BRO672 


Voltage Pot (To increase output voltage 
turn clockwise) 


O/C Pot (To increase O/C adjustment 
turn clockwise) 


O/V Pot (Sealed) 





End View of 4 Volt Regulator Card 
BRO673 


Voltage Pot (To increase 
voltage turn clockwise) 


O/V (Sealed) 


U/V (Sealed) 


O/C (Sealed) 





End View of 30 Voit Regulator Card 
BRO674 


Voltage Pot (To increase 
| O| voltage turn clockwise) 


O/C Pot (Sealed) 


O/V Pot (Sealed) 


End View of 6 Volt Regulator Card 
BRO675 


5.6 ADJUSTMENT OF THE +6 VOLT POWER SUPPLY 


5.6.1 Voltage Adjustment 


1. Connect meter between E4 (+6 volt terminal) and E2 (ground term- 
inal) on regulator. : 

2. Adjust voltage adjustment potentiometer (shown above) for +6.00 
volts. 


Note: This adjustment has no plus or minus tolerance. Set as close 
to +6.00 volts as possible. 


5.6.2 Overvoltage—Overcurrent Adjustment 


There are no field adjustments for overcurrent or overvoltage in this power 
supply. They are set and sealed at the time of manufacture. Replace regula- 
tor card if overcurrent or overvoltage conditions fails to trip the regulator. 


5.7 ADJUSTMENT OF THE —30 VOLT POWER SUPPLY 
Refer to 4.3.4 for adjustment of the -30V power supply. 


5.8 POWER SUPPLY TEST POINTS Machines with printed circuit board sequence panel Machines without printed circuit board sequence panel 


Refer to the figure to the right for test points (TPs) for the power system. \ / 





The machine powers down in any of the conditions detected at TP1,2, or 3. 
: ; . : -4V/ TP1 -4V Overcurrent/overvoltage 
Twenty-four volts is readable at TP1,2, or 3 until the system reset switch is 
pressed. Loss of either the -4V or +6V while the machine is running powers 
down the system and 24V is present at TP1 (loss of -4V) or TP2 (loss of +6V). 
Loss of -30V or +24V while the machine is running does not cause power down, 
' Read 24Vdc at TP 1, 2 
but causes a power on reset that stops operation of the machine. Any regulator : ~ - q Zanes when +6V ©) TP2 +6V Overcurrent/overvoltage 
power fault condition (overvoltage/overcurrent) will drop system power. roe, Vee gine ores 
POWER ON/ THERMAL ACTION 
OFF SWITCH INDICATOR -30V ©) TP3 -30V Overcurrent/overvoltage, +6V undervoltage 
detected by failure of -30V supply 
Internal power . Turn power switch to off 
supply malfunction . Correct problem 
. Press System Reset 
. Turn power on -4V ©) TP4 +24V 
Thermal condition : Turn power switch to off 
. Power on indicator is off 
. Thermal light stays on until 
condition is removed 
+6V ©) TPS -20V 
Customer power . Turn power switch to off 
source loss 2. All indicators turn off Read 24Vdc at TP 4, 5, 6, and 7 when 
. Turn power switch to on and indicated voltage is missing 
continue operation 
BRO676A -30V (©) TP6 +6V 
+24V/ (CO) TP7 -4V 
Spare ( ) TP8 Ground 
Ground (©) TP9 Not present 


BRO677A 


SYSTEM MAINTENANCE- Power and Cooling 
Power Supply Test Points | 5406 FETMM = (2/71) 1-503 


SYSTEM MAINTENANCE -— Power and Cooling 
Isolation of AC and DC ground 


5.9 ISOLATION OF AC AND DC GROUND 


1. Disconnect the flexible aluminum power distribution system (FAPDS) 
and the black wire fastened to the top right hand side of the regulator 
stack, 

2. Disconnect the black wire on position 8 of the frame ground lugs 
located on the right inner panel of the primary power box. 

3. If a CRT is on the system, disconnect the dc cable to TB4 position 6 


and 9, and the CRT flat yellow ribbon cable from the I/O disconnect. 
See page 1-605 for disconnect and TB4 locations. 

4. If a data recorder is attached to the system, disconnect the shield wire 
from the interconnecting bulk signal cable. The shield is fastened to — 
the bottom plate of the machine frame in the rear of the machine. 

5. A short is indicated by zero ohms from any dc common point to the 
frame. 


5406 FETMM 


(2/71) 


1-504 


Chapter 6. Locations 


The figure on this page shows the locations of the covers and access panels = 
on the 5406. : Cc. | 










Disk File Meter(s) am ce 






Access Panel 



































Logic Gate A, CPU, Memory and Attachments 
BSCA Panel 
Logic Gate B, BSCA and SIOC 
CE Meter 
Rear access to disk mechanics and 
electrical units. 
ab 
Access to CRT mechanics and 
electrical units. 
Access to printer mechanics. 7 
oe 
Power Supplies 
) 
Primary Power Box wo 
5444 Disk y 
Secondary Power Box 
Keyboard mechanics and Encode @ Hinged Panel 
Board. 
Panel with Fasteners 
Ferro’s 
Vv Panels which are not easily 
accessible, but must be removed for 
BRO678 some service requirements. 
BRO679 


SYSTEM MAINTENANCE-—Locations 
Covers and Panels 5406 FETMM = (6/70) 1-601 


SYSTEM MAINTENANCE -Locations 
Logic Gates 


File Attachment 


Printer and Ledger Card 
Device Attachment 


CRT Attachment 

Data Recorder Attachment 
Keyboard Attachment 

1/O Channel 


Central Processing Unit 


Memory (BSM) 





Gate 01A 


BRO680A 


SIOC Attachment 


BSCA Attachment 





BRO681 


5406 FETMM 


(2/71) 


1-602 


-30V Reg at 8.5A 
P/N 5797450 


+6V Reg at12A 
P/N 2557470 


-4V Reg at 32 A 
P/N 2557500 
(feature) 


-12V 
SUPPLY 
2590900 


-4V Reg at65A 
P/N 5797480 





Regulator Stack 


For machines without cost reduced ferro #1 


-30V Reg at8.5A 
P/N 5797450 


+6V Regat12A 
P/N 2557470 


-12V Supply 
P/N 2590900 


-4V Reg at 65A 
P/N 5797480 


-4V Reg at 30A 
add on 
P/N 2557530 . 





For machines with cost reduced ferro #1 


SYSTEM MAINTENANCE-Locations 


Power Supplies 







| 
[de 








TB3 


Peel 


_ 
OO 
& 


|cooo000L__] 


Funan nan nm Tn 


Pa] 
TB2 


Ferro 2 (T2) 


Ferro 1 (T1) 


Ferro’s 


For machines without cost reduced ferro #1 


Ep] 
TB2 


Ferro 2 (T2) 


Ferro 1 (T1) 


Power Bulk Supplies (cost reduced ferro 1) 


5406 FETMM 


(2/71) 








BRO682A 


1-603 


SYSTEM MAINTENANCE—Locations | | 5406 FETMM = (2/71) 1-604 
Power Controls 


cpa 


7” 
“0 
10 
io 
[1 0 
; Oo 

0 
lL 
w 


Conv Outlet Thermal 


=) = SF1 SF3 


SF2 SF/ 





Primary Power Box - Front View 


For machines with or without printed circuit board sequence panel 


JB1 JB2 























2 
e P1 
EC3 EC2 EC1 1 e 7 
CTT 0 0 
3 - ” 
. e 
2 Oo of 
EC6 EC5 C4 QO 8 © 
Cy 7 0, e 
TD1 K12 0, poll ° 
rar | 465 o-T—TPS 
ot ed CITT TTT TTT 





_ Secondary Power Box - Front View TB/ 


: ° ete i ircul nce Panel - Front View 
For machine without printed circuit board sequence panel Printed Circuit Board Sequence Panel - F 





"2 +24V Control Asm (T3) 
~ For machines with or without printed circuit board sequence panel 


BRO683A 





TS 
ae 
Se 
7 ~~ 
oe 
Pate 
“ A 
~ - | 
a Se 2 ae a | 
7 e ~ 4 os | 
4 NN 
N\ m ! 
be ae N ey 7 | | 
K aa yo ue 
, ™ bes an SV UE File Cable Connectors | 
PN 
Kk : | 
| oN Terminal Strip TB4(DC ! 
™~ | 
| N\ 
| Tay &. 4 Terminal Strip TB6(AC) | 
| > | a 
ts 
wo 
| Console ad Attachment N - a (Rear of 
Cable C ecto ick 
| oe | © Console Cable Connector Disk ENles) 
| | 
. | 
. | 
| | 
; | 
i. eee | 
™N 
\ | 
~ | 
™ 
a | 
Tey | a 
5 | 7 
(BGate)7% dite me 
Power and Cable Channel 


BRO613A 


SYSTEM MAINTENANCE-Locations | 
Power and Cable Channel 5406 FETMM (2/71) 1-605 


Appendix A. Special Circuits 


There are no special circuits on the 5406 processing unit. 


SYSTEM MAINTENANCE-—Appendix A. Special Circuits 5406 FETMM (6/70) 1-Al 


Appendix B. World Trade 


The input power requirements for World Trade machines are as follows: 


50 Hz — 380/408 V ac for Y input 
220/235 V ac for A input 
200 V ac for Japan 


60 Hz — 200 V ac for Japan 


SYSTEM MAINTENANCE-—Appendix B. World Trade 5406 FETMM = (2/71) 1-B1 


Sections 2 through 6. Processing Unit 


These sections of the 5406 FETMM contain the maintenance diagrams for 

the processing unit. These diagrams are to be used with the Field Engineering 

Theory of Operations Manual (JBM System/3 Model 6 5406 Processing Unit, 

Order No. SY34-0023) to fully explain the operation of the processing unit. 
The sections are: 


Section 2. Error Conditions 
Section 3. Data Flow 

Section 4. Functional Units 
Section 5. Operations 
Section 6. Power and Cooling 


PROCESSING UNIT—Contents 


Contents 


Section 2. Error Conditions 2-010 


Processor Check 2-010 

I/O LSR Select Check 2-020 
LSR Parity 2-030 

SAR Parity 2-040 

Invalid Address 2-050 

SDR Parity 2-060 

Carry Check 2-070 

DBI Parity 2-080 

A/B Register Parity 2-090 
ALU Parity 2-100 

DBO Parity 2-110 

Op and Q Register Parity 2-120 
Invalid Op Code 2-130 
Channel P Check 2-140 
Invalid Device Address 2-150 


Section 3. Data Flow 3-010 


Data Flow 3-010 
Storage Data Flow 3-020 


Section 4. Functional Units 4-010 


ALU 4-010 

ALU P Bit Generation 4-012 

ALU Controls (2 Parts) 4-014, 4-016 
Clock 4-020 

Cycle Controls (2 Parts) 4-030, 4-032 
Run Controls (4 Parts) 4-035 through 4-038 
A Register Controls 4-040 

B Register Controls 4-044 

Condition Register 4-050 

Data Bus In and DBI Translator 4-060 
Cycle Steal Request Priority Assignment 4-064 
Data Bus Out and DBO Translator 4-065 
Local Storage Registers (LSR) 4-070 

LSR Select 4-072 

LSR Control 4-073 

LSR Select (Dual Program Feature) 4-074 
LSR Select (I/O) 4-076 

Storage Unit 4-080 

Storage Delay Clock and Timing 4-082 
I/O Interface Lines 4-100 — 

Op Register and Q Register Decode 4-105 


Section 5. Operations 5-005 


Instructional/Functional Signal Reference 5-005 

I-Op and I-Q Cycles (3 Parts) 5-010, 5-012, 5-014 

I-R Cycle (2 Parts) 5-020, 5-022 

I-H or I-L Cycles (3 Parts) 5-030, 5-032, 5-034 

I-X Cycles (3 Parts) 5-040, 5-042, 5-044 . | 

Set Bits On/Off Masked and Test Bits On/Off Masked (2 Parts) 5-050, 5-052 

Store, Load, or Add to Register (3 Parts) 5-060, 5-062, 5-064 

Move Hex Character (2 Parts) 5-070, 5-072 

Move Characters or Compare, Add, or Subtract Logical Characters 
(3 Parts) 5-080, 5-082, 5-084 

Compare Logical Immediate 5-090 

Move Logical Immediate or Compare Logical Immediate 5-092 

Move Logical Immediate 5-094 

Zero and Add Zoned and Add or Subtract Zoned Decimal (4 Parts) 
5-100 through 5-106 

Edit (3 Parts) 5-110, 5-112, 5-114 

Insert and Test Characters (3 Parts) 5-120, 5-122, 5-124 

Branch On Condition 5-130 

Jump On Condition 5-140 

Start I/O 5-150 

Load I/O (2 Parts) 5-160, 5-162 

Sense I/O (2 Parts) 5-170, 5-172 

Test I/O and Branch 5-180 

Load Address 5-190 

Advance Program Level 5-200 

Halt Program Level 5-210 

System Reset (3 Parts) 5-220, 5-222, 5-224 

Initial Program Load (IPL) 5-225 

Alter SAR (3 Parts) 5-230, 5-232, 5-234 

Display Storage (3 Parts) 5-250, 5-252, 5-254 

Interrupt (2 Parts) 5-260, 5-262 


Section 6. Power and Cooling 6-010 
Power Sequencing (2 Parts) 6-010, 6-011 


5406 FETMM = (2/71) 2-1 


5406 CPU—Error Conditions 


Processor Check 


Diag 4-100 


ALU Parity Error 


Odd Not 9 
Carry Chk Even Not 0 
A Reg P Check 
B Reg P Check 


SAR Parity Error Hi (not)Alter SAR Mode 


SAR Parity Error Low Clock 1 to Chan 


Clock 6 Not Wait 
not) Alter SAR Mode 
SDR P Chk 


Op or Q Reg P Chk 


Clock 8 


DBI P Check 
Gate DBI P Check 
Odd Not 9 


DBO P Chk 
(not) Clock 7-8 
Odd Not 9 


Chan I/O Chk 


not) I/O Chk Sw Run 


Note: Rotate drum switch to position 8 to 
determine cause of proc chk 


Clock 8 
I-Op Cycle 
Invalid Op Code 


Clock 1 to Chan 


Invalid Addr Disp (SAR adr error) 


Even Not 0 


/O LSR Sel Chk 


p> 





1/O Check Lamp 


PBI 21 


Channel Chk 


Parity Check SW Stop 


Phase CD 


Clock 0 
Phase DE 


Sys Reset 


Check Reset 


Processor 


a 


Check 
FL 


KBI151 


5406 FETMM 


(6/70) 


PC111 


2-010 


\/O LSR Select 








(two of the possible & 
five lines should be 
active to select 


an LSR) 


Diag 
4-100 
1/O LSR Select Check Displa 


SS 000 
Ma Display P Bit Hi 
Soi | Ba 
hy 
= 





PBI31 


2 Out Of 5 Check (base LSR) 


; LSR bank 3 Seld* | jon 
2 Of 5 Chk Bank 2 I/O LSR Select Check 
2 Of 5 Chk Bank 3 
[or KB121 KBI21 


Switc 


Pos 
8 Processor A 
Clock 0 , Check _ Processor Check 


DE 










Phase CD 


A 
Even Not 0 A 





KB15} *Not used on 5406. 


5406 CPU—Error Conditions 


1/O LSR Select Check 5406 FETMM = (6/70) 2-020 


5406 CPU—Error Conditions 


LSR Parity 
T Vv 2 V 
A Reg 
ALU SAR High 


To < B Reg 








Display Bit 2 Hi 
LSR Hi P Chk Displ 


MA167 KE271 


A [LSR Lo P Chk Displ 
Display Bit 3Hi_ 
MA127 






bits 0-7 + P : 
A ( its | See K E271 PB101 
" r) Gated Feature 1 LSR Hi Par Err 
Feature 
] 
MA272 
LSR Display Bit O Hi 
(bits 0-7 + P) 
EVEN 
Gated Feature | LSR Lo Par Err im 
MA272 PC101 
(bits 0-7 + P) . 
Gated Feature 2 LSR Hi Par Err 
Feature A 
ae MA372 
(bits 0-7 + P) she Display Bit 1 Hi 
b> ) N LSR to A or B Gated Feature 2 LSR Lo Par Err 
MA372 = 
K E27] PB101 
Drum 
Switch 
SW | Proc Chk Displa 
Pos 
A 
A Reg P Chk : ao 
PC101 
KB111 
B Reg P Chk | 
Even Not 0 Phase CD Processor 
(not) Alter SAR Mode BR Check Proc Chk 
SAR Parity Error Hi Parity Check Sw Stop Ee 
SAR Parity Error Lo jon Sys Reset | ej 
-_ , KBI51 PC111 
3 : Clock 1 to Chan | Check Reset jon 


Note: Machine is stopped by either A register, 
B register or SAR parity error. Drum 
switch position 1 displays SAR contents, 
2 displays LSR contents, 4 displays B 
register contents, and 5 displays A 
register contents 


*Not used on 5406. 


PB1O1. 


5406 FETMM = (6/70) 2-030 


Location 


Base LSR High 













Base LSR Low 
Feat 1 LSR High 
Feat 1 LSR Low 
Feat 2 LSR High 


Feat 2 LSR Low 









2 v 3 
= 
LSR High 
a | EVEN | SAR Parity Error Hi 
SAR Hi P Chk Disp 
, MA167 KETO 
Display Bit 4 Hi 
#MA162 
LSR Low 
| K E271 
SAR : . ic 
is EVEN SAR Parity Error Low 
x Ca SAR Lo P Chk Disp 
KB10} Display Bit 5 Hi 
MA122 
. KE271 
rum 
Switch Cc 
oy PB101 
Pos 
8 A 
Phase CD | PC101 
. Parity Check Sw Stop i 
(not) Alter SAR Mode 
A. 
Clock 1 to Chan 
b> Processor 
: Check Proc Chk 
OR FL 
Sys Reset 
Check Reset OR 
KB151 = 
PC111 
Note: Rotate drum switch to position | to 
display SAR contents 
8 


5406 CPU—Error Conditions 


SAR Parity 5406 FETMM = (6/70) 2-040 


5406 CPU—Error Conditions 5406 FETMM (6/70) 2-050 
Invalid Address 













1 2 3 
SAR Bit 0 Hi 
SAR Bit 1 Hi Invalid Address Displa 
KB10] Display Bit 6 Hi 
SAR Bit 0 Hi 
SAR Bit 1 Hi 
12K oe oes 
Maximum SAR Bit 2 Hi KE27] 
Storage A 
Capacity SAR Bit 3 Hi pees 
: Invalid Addr Disp 
SAR Bit 0 Hi 
16K (SAR addr error) 
SAR Bit 1 Hi Nae not) Test Mode ‘ Processor 
Clock 1 to Chan Check Proc Chk 
Phase CD - OR 
RL 
A i 
Sys Reset | KBI51 


PC111 
Check Reset 


Note: Rotate drum switch to position | to 
display SAR contents 








1 
(to B reg) 
Main i Z | 
Storage SDR |p EVEN 
RA151 
A 
Clock 6 Not Wait x 
not) Alter SAR Mode 
> Note: Rotate drum switch to position 4 to 
display B register contents 
B 


5406 CPU—Error Conditions — 
SDR Parity 


SDR P Check 


Parity Check Sw Stop 


Drum 

Switch 
Sw Proc Chk Displa 
Pos 
8 


PC101 


Phase CD 


Processor 


: Check 

a FL 
Sys Reset : 
Check Reset ORF 
KB151 


A 


KBIO] 


SDR_P_Chk Displa 


Proc Chk 





PCI11 


Display Bit 7 Hi 


KE271 


PB101 


5406 FETMM (6/70) 


5406 CPU—Error Conditions 5406 FETMM = (6/70) 2-070 
Carry Check 


Dec Inst 


A 
Arith Carry to Bit 3 pa 


Bin Add or Subt 






= 
Digit 
Carry 

Circuit 














Temp 


ae (clock 3C to 5C) 
Arith Binary Carry 
Carry 


Circuit 


AV211 [ KY131 (clock 5 through 0) 


Dec Inst 
A 
A, Check Carry to Bit 3 pa 


Bin Add or Subt 


(clock 3C to 5C) 


OE Carry Check 
A Carry Chk Displayed 


KY131 











Digit 
Carry 
Check 


Circuit 















. KB131 Display Bit P Lo 
(clock 5 through 0) 


Po 
KE281 a 








Temp 






Check Binary Carry Carr PB101 
Y Drum 
Check Eee 
wa ee = 
AV181 KY131 Proc Chk Display 
AVI191 8 ie 
AV 201 PC101 
> Carry Check 


For | Phase CD Processor 
" Even Not 0 A Parity Check Sw Stop ‘ Check ec peak 
; 


= 


Sys Reset KBISI PCI1] 


Check Reset jor 


KB151 


Note: Rotate drum switch to position 5 to display 
ALU output, position 4 to display ALU 
B controls and carrys 


DBI P Chk Disp 


KB131 Display Bit 0 Lo 
DBI | 
- KE281 
: (bitsOto7+P) | : 
: | | wm EVEN DBI P Chk 4 | ons 
KE101 
KE101 a 
| witc 
7 Sw : 
p Proc Chk Displa 
OS 
PC101 


Gate DB! P Chk A 
Odd Not 9 Phase CD Processor 
me ! Check | Proc Chk 
Note: Rotate drum switch to position 5 to OR FL 
Parity Check Sw Stop . 


display A register contents. 

Rotate drum switch to position | to Sys Reset 

display SAR (contains address of Check Reset OR 
failing column) to determine bit 

structure 


> 7 | PCI 


KBI51 


5406 CPU—Error Conditions | | | 
DBI Parity | 
5406 FETMM (6/70) 2-080 


5406 CPU—Error Conditions : 5406 FETMM (6/70) 2-090 
A/B Register: Parity | | | 





DBI 
Translator 





A (bits Oto 7 =e) : A Reg P Check 

















LSR jon, g EVEN 
Reg 
RAI11 
RAI11 
RAI 21 
Misc or RAI 31 
A CR Bits 
(P bit generate if no 
input is gated to register. ) : A A or B Reg P Chk Displ 
| RAIT1 
SDR Bho Display Bit 1 Lo 
| 
KE28] 
Drum 
ea (bits 0 to 7 + P) Switch 
, 6B URE CUTIE 6\/E NI B Reg P Check Sa 
_ Reg p Proc Chk Displa 
os 
8 1 A 
RAI11 PC101 
RA101 
3 RAI11 
LSR 
Even Not 0 
Phase CD . Processor 
. | Chk Proc Chk 
4 " 
Parity Check Sw Stop al 
] Check Reset 
Sys Reset PC111 
8 Note: Rotate drum switch to position 5 to display A register 


contents, position 4 to display B register contents 


ALU 
P Bit 


FL 





AV132 


_ Bits 0 to 7 | EVEN A @ ALU Parity Error 





AV132 


ALU P Chk Displ 


KB1 31 






Bits Oto 7 + P Comp | Complement Bits Display Bit 2 Lo 
PERE GS SR SOS og EN SD. decode eee ere eee ee ee ee f . 2 


circuits 





el EVEN A Reg Comp P Check 





AV102 AV102 7 PB1O1 


Drum ) KE281 
"RAT Switch 


RAI21 Sw Proc Chk Displa 


| RAI31 el } fe 
Dec Comp A Reg = 7 
> Bin Comp A Reg jon 


ALU Parity Error 


; Phase CD Processor | . 
Odd Not 9 A Parity Check Sw Stop x , | Chk } Proc Chk 


Check Reset 
Sys Reset 








KB151 


Note: Rotate drum switch to position 5 to 
display ALU and A register contents 


5406 CPU—Error Conditions 
ALU Parit : : 
arity | 5406 FETMM — (6/70) 2-100 


5406 CPU—Error Conditions 
DBO Parity 

























1 Vv 2 Vv 
EBCIDIC 
To Card 
Code 
Translator EVEN DBO P Chk Beak fines 
Kea hk Disp 
AV142 KE24] KE261 eal 
Display Bit 3 Lo 
PB101 
KE281 
Clock 7D thru OC 
Drum 
Prior. Switch 
Req Sw : 
KE251 Pos Proc Chk Display 
8 A 
K E201 
KE211 
DBO P Chk Phase CD Processor 
not) Clock 7-8 A Parity Check Sw Stop A Check 
Odd Not 9 op rt 
Sys Reset 
Check Reset OR PCI 


5406 FETMM 


Note: Rotate drum switch to position 7 to 
> display CS priority bits, position 
5 to display ALU output 


1 
im 
bits 0-7 +P ; 
ALU Op. oO EVEN |__Op Reg P Chk 
Reg 
RN141 
RN101 
m= 
A 
(bits 0-7 + P) “ 
ALU Q — EVEN Parity Error Q Reg 
Reg 
| RN141 


RN101 


Clock 8 


Op or Q Reg P Check 


Note: Rotate drum switch to position 3 to display 


5406 CPU—Error Conditions 
Op and Q Register Parity 


Op and Q registers contents 


jor Op or Q Reg P Check 


RN141 


Phase CD 
Parity Check Sw Stop 


Check Reset 


Sys Reset 


Drum 
Switch 


Os 


A 


Be Proc Chk Display 


Processor 


Check 
FL 


KB151 


Op or Q Reg P Chk Displ 


KB131 


Proc Chk 


= 


PC111 


KE281 


Display Bit 4 Lo 


PB101 


5406 FETMM 


(6/70) 


2-120 


5406 CPU—Error Conditions 5406 FETMM (6/70) 2-130 
Invalid Op Code > | 





















2 3 
not) 4 | 
7 t)6 
Op Bits une) : 
(not) 5 A 
t) 4 t) 5 
2 Address Format 
4 
2 
Op Bit: 
(not) 5 
d 
Op Bits 
Op Bit 6 A 
aan Address Non Branch 
Op Bits 
Z 
th t 
5 
1 Address Branch 
5 
Op Bits 
> 4 Invalid Op Code 
Command Format 
RN13] 
Drum Switch 
ia Proc Chk Displa 
OS 
8 A 
PC101 Invalid Op Displa 
Invalid Op Code KBI11 : : 
I-Op Cycle r ‘Phase CD epieple Bit 5 Lo 
Clock 8 | : 
, : Processor 
: Check Proc Chk : KE281 
ORES FL |. , PB101 


Check Reset 


Sys Reset OR : 





Note: Rotate drum switch to position 3 to 
display Op register contents 


Diag 4-100 1/O Condition A 
cs I/O Condition B 
Diag 4-100 Clock 8 


I/O Check Stop Gate 


1/O Not CE Test 








5406 CPU—Error Conditions 
Channel P Check | a 





Channel P Check 













| Process Chk Displa 







Channel Chk pecan 
Invalid Device Addr ‘ 4 =< ec | _ipietestor ae 








PC111 





Channel P Check Displa 


KE281 


Display Bit 6 Lo 


PB101 


5406 FETMM 


(6/70) — 


2-140 


5406 CPU-Error Conditions 
Invalid Device Address 


Diag 4-100 


Diag 4-100 


I-Q Cycle 

1-O Check Stop Gate 
not) |/O Condition A 
(not) 1/O Condition B 
Clock 8 


Invalid Device Address 


Invalid Device Address Display 






Process Chk Disp 






Channel Chk 


Channel P Chk Fon | A 
KB141 Phase CD 


Processor 


Check Processor Chk 
OR FL 
KB151 
PC111 


KE281 


Display Bit 7 Lo 


PB101 


5406 FETMM 


(6/70) 


2-150 





m™ Address / Data Switches 


















Odd CD (I/O Cycle) 


Translate 































































DBI 
3 ICD (I-Op), 3CD (I-Q) 
Channel In 
Conirol 
LSR Hi - 3CD , 
Maepueen LSR Lo - 1CD, 3CD Pe ves 
Storage Unit 
LSR Hi - 1CD, 7CD 
. LSR Lo - SCD. Fo =i = Channel Out 
: = 
: E 16 
sees sale ciiaeeea BOUBEEEGE | 
©) () ia) BA 3CD, SCD eats Se we 
ae re = ee ae 
PLOT] 273/475 [6] 7] Pp oli] 2] 3f 4[5] 677) a | 
e | CL AC to 6C 
ODE, 9D = - . 
x 2D, 4D, 8D 2D, 4D, 6D 
y LSR (Lo) 
Cycle 
Control 
“ “\ 
“” “ 
B 


Address Address 
Lo Hi 





(P) Parity Checked 


Parity Generate 


aaag Display . Phase TE Note: Clock 0 and 1 consists of 5 phase 
. pulses (A, B, C, D, and E) 


— o_o om 
o 


5406 CPU—Data Flow 


CPU Data Flow (5406 FETMM = (6/70) 3-010 








5406 CPU—Data Flow 
Storage Data Flow 











ALU Store Bits 


Estee et athe ES 


Sense Bit 0-8 


eas 


Sense Bit 9-17 


ALU Store Bits 








Diagram 


4-080 


Diagram 
4-080 


bf 


Sees 


rts TTR os. 
erie 











Byte 


Control 


Diagram 
4-080 





B Reg Input (CPU) 


5406 FETMM (6/70) 


3-020 





5406 CPU—Functional Units 


































ALU 
1 Vv 2 
Z Dec Instruction : 
B e 
Reg Edit Instruction jon 
(bits 0 to 3) 
(bits 4 to 7) 
RA101 
A RAII1 
Output is same | ALU Internal Bits 
AV121 No Controls as B Register 0123 -4567 & 
Dec Comp B Reg = 
re Output is same as 
If line is inactive, output is same Both And and OR ; A Register 
: as input. Input. 2 
ey cetaees bal Z 
Need same bit in both | 2 
And ge inputs to get an ZB 
output. | FF: 
1 oe 
| ! B 
eo ee eee ee ee _l ae 
Bit in either | 
Crs a input gives | 
: = an output. 
> Ss Sais 
Bin or Dec Subtract Fe 
ee A ee 
herb Arith Carry to Bit 3 (decimal) 
27 Arith Binary Carry Out 
Output is figured bit by bit in 
descending order, bit 7 through Test False To Condition 
bit 0 for binary; bit 7 through 4 Register KG121 
for decimal. 
Dec Inst Internal bits 
Carry to 3 0 to 3 
Clock 3C - 5C a 
B 
If not decimal operation, or if;no carry, 
output is same as input. 
Pwr On Reset 
Load ALU , 
Even Not 0 CD jon ALU Latches 
KC141 


AV142_ 


Bin Comp A Reg 


5406 FETMM = (6/70) 4-010 


(bits 0 to 3) 








(bits 4 to 7) 


: 
atest 
203 

22508? 


eek? 
iss 


ag | RAI 


RAI 21 
RAI31 













Dec Comp A Reg 













If line is inactive, output 
is same as input. 


Ist E Cycle 


Dec or Bin Comp A Register , 
Dec Instruction 


Note 1: 








ent Dec 
btract 


a 
3 
o> 
33 
oc 
25 ¢ 
oS 
= 
bal 


o 
a 
@ 
wn 
= 










vA 

® 

«a 
= 
=. 
an 


oo7-ooo7oO 


O 


7A 
“OOO O18 HS 
-—$-o0o--Oo°o 
— — od oF 
ata 
om o-m—-o-o/f2o 
nv % 
Co 
reeereeseal y 
+--+ 
a 7 
om-ooo-oo- 8 
ny = 
o 
ws 
+r + 


> 


1 Vv 2 


Register Bit 5 B Register Bit P 


















(not) Register Bit 6 








A Register Bit 5 








Arith Carry to ALU (Bit 7 position only) 
[Ac> 2 A Register Bit 6 


— 


Diag 4-016 a 


—_— 


Carry In * 












A Regisier Input 
Bits Even 


) 

Ld 

Pe EVEN A Register Compl 
5 

see =! 


\ (No P bit) 
\ 
\ 
\ AV102 
\ 
\ | not) B Register Bit 1 
\\ not) B Register Bit 3 jf | 
Test False = 
AV202 
AV212 not) B Register Bit 0 
AV222 . 
AV232 (Bit 0 position only) ca Change ALU Bit 2 
Diag 4-014 AV132 
Internal Bit 


‘\, 


(Bit 4 position only) 


SINGLE Bit Position 


5406 CPU—Functional Units 
ALU P Bit Generation 


B Register Complement P Bit 


AVI42 


Diag 4-016 
Carry In 
Carry Out 
A (To Next Bit) 
aes | (not) ALU Bit 5 
i foe Arith Carry to Bit 3 - 
0 
| t= 4 Check Parity Bit 1 
a ee 
A | AV162 
Pe AV172 ALU Check Odd 
AV182 
AV192 
SINGLE Check Position 
AV132 A Register Bit P 





Vv 3 


Even Not 0 CD 













(bit 0 position only) 


Check Carry Out fe) 


Diag 4-016 


Check Carry to Bit 3 ee 
Diag 4-016 
(bit 4 position only) 


AV132 ALU Parity Check 


eee (Diag 2-100) 


NY} OS [On f 2 70 ho J JO [°O 


oF | A Register Complement P Check 


AV102 


Shows circuitry used only during operation 
noted on input line. When shaded input 
of OE is not used, output changes with 
other input. 





y x Arith Bin Carry Out ES 


Diag 4-016 
Arith Carry to Bit 3 (decimal) E> 





Diag 4-016 


5406 FETMM (2/71) 4-012 


5406 CPU—Functional Units 
ALU Controls (Part 1 of 2) 





B 





2 Edit Inst 
EA Cycle 


Diag 4-105 









Sign Control 
E Cycle 


Dec Instr 


Cl 3C to 5C 
Ist E Cycle 
Dec Instr 


Change ALU Bit 2 


B Reg Bit 2 


Recompl Cycle 


Zero and Add Instr 
EB Cycle 


Cl 3C to 5C 


System Reset lore 


KY101 


A Reg Bit 2 


SDR Sign Minus 


Ist E Cycle 


Clock 3CD 


ae I-R Program Backup 


Diag 4-030 


Bin Add Grou | 


Diag 4-105 


ik Chan Binary Subtract 


Diag 4-100 
I-R Cycle Jump True | 
; Test Mode (sw 
Diag 4-073 I-X Cycle 
IAA» Bin Add or Sub Group | Bin Add or Sub Group 
Diag 4-105, EB Cycle 
OR 
Diag 4-105 


[e>—20-- 777 


Diag 4-105 


Sign Minus 





2 


Recompl Cycle 


of }-—ay 5 


KY121 


Set or Test Off 


EB Cl 3C to 5C 


Any | Cycle 
not) Clock 3 and 4 


Bin Add Group 

FC Instr (fill character 
EB Cycle 

Cl 5 thru 0 

VO not CE Mode ‘ 





I-Q Cycle 


Clock 3C to 5C 


Odd CD 





5406 FETMM 


Decimal Compl B Reg 


Sign Control 
Dec Sub Gate 


Change ALU Bit 2 


Dec Comp A Reg 


Dec or Bin Comp A Reg 


B Reg Sign Minus 


Bin Comp A Reg 


a 


not) Cl 3C to 5C 
Bin Sub Gate 


KY12] 


EB Binary Add or Sub EB Binary Add or Sub 


Branch or Jump Instr 


OR 

A OR Gate 
EB Clock 3C to 5C 

A 
And And Gate 


KY101 


(2/71) 4-014 


Diag 4-050 


Diag 4-012 


~ Diag 4-050 


Diag 5-050 


Temp Car 


s 


Arith Bin Carry Out 









Arith Carry to ALU fac) 


ix Cycle Diag 4-012 


Clock 5 and 6 


I-R Cycle Jump True 


Diag 4-073 


ES Arith Carry to Bit 3 (decimal 


Diag 4-012 
Arith Bin Carry Out 


A Diag 4-012 


OE |Carry Check (Diag 2-070) 
| Dup 


EB Binary Add or Sub KY131 


Diag 4-014 


Check Carry Out (binary) 


Dec Instr 


Diag 4-012 
Check Carry to Bit 3 (decimal) 


Diag 4-012 


INS Op End 


~ Check Carry to ALU 
Diag 4-030 eGo 





Check Carry Out 
Diag 4-012 


(Force Carry) 


>. Dec or Bin Compl A Reg ___Dec or Bin Compl A Reg 


Diag 4-012 not) Cl 7C to 1C A 


Ist E Cycle 


B nORLER:Cyele 
not) Cl 3C to 5C 


5406 CPU—Functional Units | 
ALU Controls (Part 2 of 2) 5406 FETMM =. (2/71) 4-016 


5406 CPU—Functional Units - 
Clock 


es Enable Clock Run 


Diag 4-037 


not) Trigger B 


not) Trigger C 


Phase D 


Clock 0 


Clock 1 


25 MHZ Ose 


A 
(not) Power on Reset pa 


25 MHZ Ose 
Enable Clock Run 
Trigger A 

B 

Cc 


Phase A 


mM™™mOOo 








v 


5406 FETMM (6/70) 


Alt SAR/Alt-Dis Storage Step aut THaeer 


Step 


TS 


40 ns 
200 ns 200 ns 160 ns 160 ng 160 ns 





Mode 


Sys Rst 


LZ 
be. 
aa te). 2a £89 4 


KC142 





or | not) Y Trigger 


Force Clock 9 
Phase F 






Trigger A 


Phase D 


Phase B 


Sample DBO to Channel 








Phase C to Channel . fed 
a fap a Clock 9 
re : Force Clock 9 
Al KC122 


Phase DE 


Phase CD 





cl 8 Cl 9 
Trigger 


Clock 





4-020 





lst Operand Index 2nd Operand Index 









E> Sys Rst 










Diag 4-035 
> EA Eliminate 
A Ist Operand Direct : 
e Program Interlock 
imc > MC Advance 
eee Seen 


Diag 4-035 
@ Program Interlock 


Peek oo oet ee 
ae ) 
Ke.» Command Format = 


Diag 4-105 


B Reg Bit 4 
B Req Bit 5 


> B Reg Bit 6 
B Reg Bit 7 A ER Gucle 
not) B Reg Bit 6 ie Significance K 
A B Reg Bit O 
B Reg Bit | 
B Reg Bit 2 A 
B Reg Bit 3 


2 Address Format 





One Address Non-Branch 









Clock 8 


not) B Reg Bit 5 
(not) B Reg Bit 4 


Diag 4-016 
4-037 







Diag 4-105 


Program Interlock eS 


Diag 4-040 
4-074 


Diag 4-100 I-X lor I-L | 


1/O Condition B 
fe > One Address Branch 
EB Trigger 
Single EB Cycle Instr P= k 
I-R Program Back-up Lay 


| Clock 8 | 
Diay 4-105 
I-RC cle , | i Diag 4-014 
L N 4 
Q Reg Blank | I-R Cycle to I/O 
|/O Not Console Instruction Op End Gate 


One Address Non-Branch 

not) First E Cycle Trigger 4-040 

2 Address Format 

not) Recomple Gate 
Diag 4-105 Diag ae 
Py > ——@ Reaister Blank 4-050 
Diag 4-105 Significant Digit 
[o> Set Program Interlock (halt instruction) YY 

Diag 4-032 

Diag 4-038 | 4-072 





5406 CPU—Functional Units | 
Cycle Controls (Part 1 of 2) 5406 FETMM (2/71) 4-030 


5406 CPU—Functional Units 
Cycle Controls (Part 2 of 2) 


» 


ER Q Num Blank 


Diag 4-105 


rae Edit Instr 


Diag 4-105 


Dec Instr 


(not) B Reg 20 


Op End 
Diag 4-030 


[ Y Significant Digit 
Diag 4-030 


[so Store Data Group 
Diag 4-105 


Chan Store Data 
Diag 4-100 


Vv 


Recompl Cycle 
FC Instruction (fill character 
1 Address Format 





EB Cycle 


t/O not CE Mode 


_ Alter Storage Mode (Sw | 
A 
not) SAR Address Error (invalid address ad 


KY111 


Cl 4CD 
New Data to Storage 


Cl 6 
POR 


5406 FETMM = (6/70) 4-032 


EA Eliminate ie 


Diag 4-030 
4-040 


AY Store New ese» 


poe Diag 4-080 


KC132 





I/O Cycle 7 
Diag 4-036 


a CSP Request 
Diag 4-064 
Test Mode 


a 


[/O 

e FF 

Process Mode (Sw) |/O Not CE Test 
i ror 


Step Mode (Sw) 





Ea 
iu 


ne Process Run ; Process Run 


Diag 4-036 





A M/C Advance imc) 


Diag 4-030 
| 4-074 


| a IPL 
A G » 
A fe. Enable Clock Rus 
: Diag 4-065 








Diag 4-037 IPL Key IPL 
Program Load Ke E p : py 
FL 
ae I/O Working or Burst T1 
Diag 4-036 
KA202 
System Reset T] on | 


Clock 0 


IPL or System Reset Cycle ie 


Diag 4-037 


| Sys Rst 
Diag 4-030 





a 
es 1/O Condition B Reset IPL | ‘ 
Diag 4-100 a FL Clock 6 


/N | Reset IPL Latch Ee. 


Diag 4-036 


$406 CPU—Functional Units 
Run Controls (Part 1 of 4) 5406 FETMM (6/70) 4-035 


5406 CPU—Functional Units 
Run Controls (Part 2 of 4) 


1 
E>—: End Gate 
Diag 4-030 Stop Key 
System Reset 
Start Key stat sey 
FL 
KA212 


| Ff >Reset Halt Remembered Latch 
Diag 4-038 


Clock 6 


I-Q Cycle 


Te pet Any Interrupt Being Serviced 


Process Mode 


Diag 5-262 

Ty Reset IPL Latch 

Diag 4-035 Address Matched 
Display SAR % 
Clock 4 


Address Matched Enable Switch 


System Reset 


> Tz >We cycle 


Diag 4-035 


I/O Overlap Switch Off 


not) Process Mode (sw 


\/O Working T1 


/O IF Chan I/O Working 


Clock 8 






Burst Mode T1 
IAB Fe 


re 


Burst Request | (not used) 


5406 FETMM (6/70) 4-036 


Stop Light 


oR 


Basic Start Tl 


Stop Light 





Op End Gate 


Clock 7 
Phase CD 













Run_ Pulse 1G) 


Diag 4-038 


Process 


Reset IPL Latch Run 


pace EE FL 
A Run Pulse 
Basic Start T2 


Enable Wait Cycle 






Process Run re 


Diag 4-035 









Process Mode (Sw) 


A 
a] Process Run To I/O 


Nait State |W) 
“Pe Diag 4-040 
4-044 
Inhibit Machine Cycle 


Basic Start T2 THY 


Diag 4-038 




















Clock 0 





Address Match 
| 
I/O Cycle 





KA222 


Enable Wait Cycle AS 


Diag 4-037 


1/O Working or Burst T1 o> 







1/O Working Diag 4-035 
or Burst T2 4-037 
/O Working or Burst T2 TES 
Diag 4-037 © 








2 V 3 


Alter SAR/Alter Display Step System Reset/IPL Ke 
Process Mode (CE mode Sw) - 
M/C Step 






Clock 4 
Clock Step ey bes 
not) Even Clock e Phase CD Stop Ee 
Instruction Step FL ee Enable Clock Run 
| Cycle End A : EL ce. 
Clock 6 System Reset Diag 4-020 
Step Mode oR 4-035 
rE \/O Working or Burst T2 | 
Clock 8 A 
Diag 4-036 ~ KA232 


KA232 


ie» I/O Working or Burst T1 
Diag 4-036 
A | 
Start Key Latch i 


a2 
Key Rel St 
Alter SAR/Alter Display Step y REL OTEp im 
N A 

A 
Clock 9 es a 
‘Clock Step 

. 
A 









Diag 4-030 | 
Enable Wait Cycle 


Diag 4-036 


nee IPL or System Reset Gate | . 
: A 
Diag 4-035 Process Check Latch pa Power On Reset jon 
Clock 8 
Phase B A 
not) Any Mode 


5406 CPU—Functional Units 
Run Controls (Part 3 of 4) | 5406 FETMM (6/70) 4-037 


5406 CPU—Functional Units 
Run Controls (Part 4 of 4) 


1-Op Cycle 
Cl 8 
Halt Instr 


ee Any Interrupt Lev Being Serviced 


Diag 5-262 Load Reg Instr 
Q Reg Bit 2 
l-Q Cycle Cl 6 


> Run Pulse 


Diag 4-036 


ae Basic start T2 


Diag 4-036 


5406 FETMM (6/70) 4-038 


I-R Cycle 


Ae Load Unit Halt Id 
A 


Cl5 


A 
not) Any Inter Being SRD Pa 











Halt Basic 


x Load Ten Halt Id 
I-Q Cycle 





Step Mode (Sw) 


Sys Reset ea 


Rst Halt 
Reset Halt Remembered Latch TF) 


A Remembered . 
Start Key Latch EL 
: Diag 4-036 
3 Set Program Interlock 
pa BD 
KA212 jon 


Set Prg Interlock DPF Diag 4-030 





Clock 1 and 2 


A 
Sense 1/6 Alter SAR or Storage (Sw) 


Gate I/O Bus To A 


not) Any I/O LSR Seld 


I/O Not CE Test 
Clock 3 and 4 


KG13]1 
A | EB 3 and 4 " 
EB Cycle Pe | 
Zone Numeric Interchange A Gate LSR Lo Crossed To A 


Force P Bit to A 








N 
irene I-R Cycle Jump True for NI Tp Gate LSR Lo Normal To A 


Diag 4-073 I-X Cycle 


Op Register Bit 4 

EB Cycle 

2 Address Forma ez 
‘oy EA Eliminate | | Clock 3 and 4 


Diag 4-030 Add to Register or Store Instruction eee sacaetateenenianartatetnetetetiasetonr ttcttes 


Ist E Cycle 
: Misc Bit P to A A REGISTER 
: ‘ z oe ~ A Register Bit P 
A Register Bit 0 
bf 
ay 


Load A and B Register (Odd CD) 












4, Gate LSR Lo ToA 











> Program Interlock 


Diag 4-030 


I-Op C cle 
Clock 1 and 2 


Branch Or Jump Instruction 
I-Q Cycle A 
Clock 3 and 4 


Add to Register or Store Instruction 


















Gate CR to A 












Overflow 





not) Ist E Cycle 


Gate LSR Hi toA 
A A 
EB Cycle Clock 3 and 4 
2 Address Format 
Diag 4-105 Clock 1 and 2 IN al 


not) Decimal Instruction 
(not) EA Eliminate 


Q Reg Num Blank 














CR Test False 


Misc Bit 3 to A 
CR Decimal Overflow 













Diag 4-105 


Recomp Cycle 


Ist E Cycle 


EB Clock 3 and 4 
1/O Not CE Test LSR Lo All 1 


CE Test No Increment I-X Cycle , 
Clock 1 and 2 
Iw > Wait State 
Diag 4-036 jon 


System Reset Clock 5 and 6 


Dp Program Backup . : 
Force Bit 6toA | = aoa EERE, 2 
Diag 4-030. Clock 5and6 | Ee 





Force Bit 7 to A A Register Bit 7 


RAI11 
RAI 21 
RAI 31 





USR OM BUS 


5406 CPU—Functional Units 
A Register Controls 5406 FETMM — (6/70) 








4-040 


5406 CPU—Functional Units | 5406 FETMM (6/70) ah 
B Register Controls . 








Clock 5 and 6 


lw) Wait State . 
ine N 
Diag 4-036, aces jon | | | Gate LSR Lo To B 





B REGISTER 

















A 
| a B Register Bit P 
1-X 
Cycle fon Gate [SR Hi'To:8 oa” 
EB Cycle ae 
x Clock 1 and 2 
B Register Bit 0 
bl 
Ay 
be not) Alter SAR or Storage 
z= Inhibit SDR Transfer | 
Recomplement Cycle jor | 
Gate SDR To B 
t) E | 
(not) EB Cycle Clock:saad4 | 
KGI41 | 
1/O Not CE Test | 
Chan Block SDR : 
rv S oo B Register Bit 7 
Diag 4-100 KGI5I ~~ FL 
A 
Diag 4-080 RA111 
LSR Lo Bus 


LSR Hi Bus 


Load A and B Register (odd CD) 


pS Program Interlock 


Clock 1 and 2 


Load CR Instruction 


Ist E Cycle 
rk Bin Add or Sub Not Move 
Diag 4-105 EB C cle 


Dec Instruction 


| Edit Instruction 
, D 


Diag 4-105 


EA Cycle 


— Ist E Cycle 


Diag 4-014 B Register Sign Minus 


Decimal Sub Gate 


; not) ALU Bit 2 
Diag 4-014 “Arith Bin Carr 


rx» Op End Gate 


Diag 4-030 


io > Bin Add Group 


Diag 4-105 


rH) Q Register Blank 
ne | 


is Dec Compl A Reg 


Diag 4-014 


Branch or Skip Instruction 


B I-Q Cycle : 
Clock 5B 


[Vv Test On Off Instruction 


Diag 4-105 


5406 CPU—Functional Units 
Condition Register 


S stem wor 






























Clock 5B 


Clock 5B 


(nto ALU Numeric Blan 





Ist E Cycle 
Clock 1 and 2 


ALU Bit 6 
Clock 5B 


ALU Bit 2 


4 Load CR 


Bin Add Group 










Ist E Cycle 
Clock 1 and 2 


ALU Bit 4 Pa 
= 
= 


not) Recomp! Cycle 


(not) Arith Carry to 3 | A 


Clock 5B 


B Register Bit 4 


ALU Bit 3 






Test False 
Test On Off Instruction 


A 
B Register Bit 3 pas 


5406 FETMM = (6/70) 4-050 


5406 CPU—Functional Units | 5406 FETMM (6/70) 4-060 
Data Bus In and DBI Translator 


r 
| 


Data Bus In To A Register Then ALU 







H(not) 6 Diag 4-040 


(not) 5 
not) 4 

3 
not) 2 











DBI Bit P 






Console Bit P 





DBI Bit O 


DBI Bit 1 


DBI Bit 2 


DBI Bit 3 





Concole Bit 4 


DBI Bit 5 


DBI Bit 6 


Console Bit 6 





DBI Bit 7 


jon DBI Bit 4 


| | 
wary Console Bit 7 


DBI 
poy 


S 


A 
(even clock time) . Clock 2 and 3 to DBI pa 


et» Translate In 


Diag 4-100 





EVEN DBI Parity Check 
KE121 









Clock 7 Prior Bit P 
AT : 


Odd Clock Not 9, | Clock 5 


B Chan CSR3 LL are 
ee ed ne e 
[a > \ Chon Skt 4} 
















Diog 4-100 Chan S5RS 


System Reset 


Clock OD 


Cl 8 a Req LT 
A & 
4 CSP Req ES 
Cl 5 | | Diag 4-035 
KC152 






DBO Lines 


Attach t 
vee P01234567 


Any CSP meqves cS 


Diag 4-076 








Disk read/write 000010000 
K E20] 







Spare 





000000100 


Printer 





SIOC 000000010 













Spare 









Prior Bit 2 


Ag FL 





BSCA 








110010000 






Spare 






101001000 


Data Recorder 







CRT Display 101000100 


Spare z 
Diag 4-065 





Disk Control 100100001 


5406 CPU—Functional Units 
Cycle Steal Request Priority Assignment — | 5406 FETMM = (2/71) 4-064 


5406 CPU—Functional Units 


5406 FETMM (6/70) _—-4-065 
Data Bus Out and DBO Translator 





ALU Out (4-010) 









3 
gota 
rots 


CPU to Card Translate Clock (Cl 4C to 6C) 


A 
re Translate Out 










Diag 4-100 im Data Bus Out 
Cycle Steal Request (highest priority acknowledged) . scare a8 
ae : eae ORE Oana ees s TEE Tea . Diag 4-100 
Diag 4-064 Clock 7D to OC Ss 
IPL 2 ‘ 
eS EVEN DBO Parity 
Diag 4-035 — Check 
















iD» Select DRR and LCR 


Diag 4-072 
[A> Sel AAR 


Diag 4-072 


Sel BAR 








Diag 4-072 





Pl ARR/IAR LCR and DRR Select 


Diag 4-072 AAR Select 


5 P BAR Select 
A ase - 


EB Cycle 


A 
rw > _Halfword Format 


Diag 4-103! (x6) First E Cycle A 
Clock 4 
I-Q Cycle p 
rn aa A LSR Write Hi 
eeeCueie Clock 4 . OR 
Alter SAR A 
GLE jor Clock 2 


Write 
Amp 


Sense | LSR P Bit Hi 








> 
3 
7s 


Sense | LSR O Bit Hi 
mp | 


ae 


EB Cycle Clocks 


Sense | LSR1 Bit Hi 





EB Cycle 

Halfword Format 
Ist E Cycle 

Clock 4 A 





Sense] LSR 2 Bit Hi 




















Amp 
not) I-H Cycle 
not) EB Cycle 
not) Alter or Display Storage A LSR Write Lo 
Clock 4 Pa 
1-Op Cycle 101 | - 
\/O Cycle Not CE Test Amp ARRAY ? 
‘MA147 — 


Sense} LSR 4 Bit Hi 
Amp 


Sense| LSR 5 Bit Hi 
Amp 


e ° A 
Inhibit LSR Load 


Idle Time 


A or B Register Check 
A Data From ALU- 
LSR to A or B a rE Ee 


Sense| LSR 6 Bit Hi 
Amp 


hs ds Sense| LSR 7 Bit Hi 
(second byte of LSRs) : i Amp 


To second byte of LSR 


5406 CPU—Functional Units 
Local Storage Registers (LSR) | 
C 5406 FETMM (6/70) 4-070 


5406 CPU—Functional Units | | 5406 FETMM — (6/70) 4-072 
_LSR Select 





























1 2 ¥v 3 
I-X2 Cycle i-X2 Cycle 
Clock 3 and 7 
Op Bit 7 Clock 4 and 8 
I-X1 Cycie . |-H2 or I-L2 Cycle 
not) Select XR-2 Gate A A 
Clock 3 and 7 . Clock 3 and 4 A Sel AAR [AA 
Gated P1/P2 Reg Instr XR-1 Seld EA Cycle Allow LSR Select 
Q Code 7 A _ Diag 4-070 
Clock Fad 4 Allow Select LSR Clock 5 through 0 KLI21 
KL141 
I~H1 or I-LI Cycle 
A I-X1 Cycle 
Clock 3 and 4 not) LDX A 
\-X1 Cycle Clock 4 and 8 
; I-H1 or I-L1] Cycle 
Clock 4 and 8 (not) LDX A 
Clock 3 and 4 A Sel BAR 
Q Code 7 EB Cycle Allow LSR Select | BY 
aoe not) Recomp Cycle K Diag 4-070 
A . Clock 5 through 0 KLI21 
LDX (load index reg 
not) Recomp Cycle 
EB Cycle 
Q Code 6 EB Cycle Clock 1 and 2 
EA Cycle jon | 
lock 3 and 4 Select DRR and LCR 
A . 
Hal fword Format ee C: cle Allo LSR Select pa 7 LD 
= ie Diag 4-070 
Diag 4-105 Sl lOve dd KL121 
Op Bit 2 : 
Clock 3 and 7 ce XR-2 Seld Q Bit 4 
4 
Clock 3 and Gated P1/P2 Reg Instr 
KL141 I-H1 or I-L1 Cycle 
A 
Decimal Instr 
Clock 3 and 7 sronch of ne Allow LSR Select 
nstruction ARR System Select 
> (fill character) 
A 
ioe 2 Address Format iz pa KLI11 
Clock 3 and 4 
Diag 4-105 Recomplement Cycle aes ae EB Cycle 
Significant Digit not) Significant Digit A 
— Clock 6 or 8 
Clock 1 and 2 sepsis Diag 4-030 ck 
= 
de 5 
ao a aa ; System Reset not) Any Interrupt Level Being Serviced 
ated Pl/P2 Register In Pl Trigger 






FES Interchengel Pulse 


Diag 4-073 


LSR Interchange Pulse 





Register Instruction 


1-R Cycle Jump True 
not) Q Code 0 A 4 
5 EB Cycle 
A 
A gi 
aeenaa pa Gated P1/P2 Register Instr ee 
Clock 5 through 0 


| Cycle not l-X 
eS I-R Cycle Jump True Clock 0+14+24+5+6+9 










Allow LSR Select 
JAR Seld 


A 

KLT01 
ts 
A 


N 


P1 ARR/IAR 






Q Bit 2 


Diag 4-070 
Diag 4-073 I-X Cycle 


A 
is 
2 


System Reset 
Alter or Display Storage (Sw 
Alter SAR (Sw 






Tc > Any Int Lev Being Serviced 
Diag 5-230 , 1AR Seld 





1 2 3 
Condition true or 
‘condition false 
| Output here means jiepcucle 
Branch condition branch condition satisfied ; ; 
; Jump (instruction) I-R Cycle Jump True 
equals tested register A " ie 
Diag 4-016 
4-040 
4-072 
B Reg Bit 0 4-073 


ALU Blank Branch or Jump 
1-Q Cycle 
| nearness ce ee eSTStS:*~<CS~ Cl 5B 
E> Test I/O Instruction jor Br-Jump True 


TIO Instruction 
| I-Q Cycle 

cl 8 A 
DPF Branch Condition 














U 
Qo 
a 
i 
1 
Oo 
os 


> Q Reg Zone Blank 


TIO 


Clock 8 
I-Q Cycle Internal 
Pl Reader (not) Q Zone Blank and Not Q Bit 4 


| (not) Chan I-O Condition B 
° A enon anand 

Q_Bit 5 DPF Branch Condition 

DPF P2 Reader : 


Control 
Switch Sys Read Console I/O 


| ~ 


Q Bit 7 
Sys Read MFCU 


Y 
Q 

a 
NN 
I 
o 
a 














Cancel 
Not used on 5406. 
fee) Set Program Interlock Set Program Intlk 
Diag 4-038 | | Cl 5B Sys Rst 
Op End (C1 8 
B [n> = 


Branch or TIO 


Diag 4-030 A LSR Interchange Pulse ‘> 
Diag 4-072 
KD151 4-074 


5406 CPU—Functional Units 
LSR Control 5406 FETMM (6/70) — 4-073 


5406 CPU—Functional Units | 5406 FETMM = (6/70) 
LSR Select (Dual Program Feature) 


A 








Pl Enable Switch. 


P2 Enable Switch 








ALU Bit 5 Enable 
DPF 


IAR/ARR P2 












FF 


cE 
| [> 
mn 


> 


I-R Cycle Clock 5 
ct 


KT15] 


Ash 


[MC > M/C Advance 


i 
IAR/ARR P2 Select 
| 

reer 

fee ee 




































CH 
Diag 4-035 
| Op End i. A 
ARR Select ARR/IAR P2 Select 
| Diag 4-030 ye elec a 
Program Intlk as) Program Intlk Ll 

Diag 4-030 
re) (not) Any Interrupt Being Serviced IAR Select 
oe 5-262 — Gated P1/P2 Register Instr 
| ic LSR Interchange Pulse Q Register Bit 1 
| Diag 4-073 

XR-1 P2 Select 
| XR-1 Select 
| Len DPF 
| XR-2 P2 Select 
XR-2 Select 
| PSR P2 Select 
| PSR Select 
| Enable 
| ALU Bit 6 nterrupt O 
= 


| 
| ze SIO Instr 


Diag 4-105 


A 
| ee: Q Register Blank 
| Diag 4-105 
| 
| 


ALU Bit 7 


IAR/ARR Interrupt 0 Select 


(not) Any Interrupt from 1 to 4 Req 
| BY not) Any Interrupt from_1 to 4 Reg 
| Diag 5-262 ARR/IAR Interrupt O Select 


Set Interrupt PH 


Int O Req 
Interrupt Key 


Interrupt Level 0 Request 


KTI4I KT141 EB Interrupt Request Instr 


| 
| 
\ 
| 
| 
| 
| 
| 
| 
lw) Select Interrupt 0 Decode Select Interruot 0 Decode Not used on 5406. 
| 


Diag 4-105 
1 


4-074 


Diag 5-262 





2 3 
3 
Sel I/O LSR #1 
A 
V/O IF LSR Select 3 a : TR3 lft 
Diag 4-100 | ; 5 


Printing Punch Data Field (DRAR) 


File Identif Field (DFCR) 


\/O IF LSR Select 4 


Diag 4-100 





“Sel 1/O LSR #4 


File Data Field (DFDR) 


\/O IF LSR Select 5 


; . in 
Diag 4-100 Print Command Field (PCAR) 


Line Locate Field (LLAR) 
or CRT Display Field (CRTAR) Note 1 


Print Data Field (PDAR) 


Diag 4-100 


CRT Display Field (CRTAR) Note 1 













1/O LSR Select 
\/O IF LSR Select 7 TES ES RE TCG PY OSCR TT re. 
Diag 4-100 Diag 2-020 
Clock Trigger A 
Note 1. If a ledger card device is installed 
I/O Not Console Instruction on the system, the select lines for 
rc, the CRT display are 6 and 7; if not, 
Diag 4-105 the select lines are 6 and 3. 
[o> Any CSP Request CSP Request EB Cyl 
Clock 8 FL a 
Diag 4-064 Clock 2 
Clock 8 
Bg Clock 5 ; pa 





A 
KC152 & 
Clock 0 
Clock 2 a 
Clock 4 A 
System Reset 





Power On Reset 


5406 CPU—Functional Units 


LSR Select (I/O) 5406 FETMM = (2/71) 4-076 


5406 CPU—Functional Units 
Storage Unit 


— 


SAR Bits 


| lw > Write Time 


| Diag 4-082 


| TDS 50 ns Dela 


| Diag 4-082 


| RT» Read Time 


| Diag 4-082 oO . 
Store New 
| Diag 4-014 . 


Ist BSM 


not) SAR Bit | 





Core 


X,Y Drive 


> SS 


BSM Select 

Byte Control 
Hi-Y Decode 
Lo-Y Decode 





SAR Decode 


SAR 


Hi-X Decode 


oft }2{3}4]5 [6 [7 8]9 pop if 2h 3h 


SRO31 - SRO64 


Sense 
Amps 


Inhibit 


| 
| 
| 
| 
| 
| 
| 
| 
| 
| 
pee 
: 
| 
| 


Inhibit 
SRO71 
SRO76 


Lo-X Decode 








9-17 


105 


| Reset (CPU 


ALU Output 






\ SAR Bit 2 


oO Store New 


5406 FETMM 










ee ae ee ee ee ee ee —S $s ——- ro > irwvlnrr9l co 7 
| Not used on 5406. 
| SAR Bit 1 | aa 
2nd BSM 


SAR Bit 1 
Eee 
Core 





v 






Data Bit 
0-8 












Data Bit 


Sense Bit 0 
Sense Bit O (2nd BSM) 
Store Bit O (from ALU Data Bit 0 (latch output 







Tews 


reconstruct) & 






Note: When reset line is plus, 
data bit passes thru the 
OR but does not set the 
latch. When reset line 
is minus, data bit is set 
in latch 


+ Reset 


Store Byte | 










es 






SAR Bit 2 


: Write Time , | 

OR} 9 A : me 

SRO74 “9 (Write/ 
reconstruct) 


not) SAR Bit ] 
















Store nye 2 













Write Time 
Reset (CPU) 


“9 Read Time 


pr 2nd BSM Selected (SAR Bit 1) SRO12 







(6/70) 


4-080 


SDR Bus (to B Reg) 


ms+P 


Diag 4-044 





Clock Pulses 


Timing 


Read Call/Write Call 
A ; Control ‘ Ons Dela 
~ (not) 2nd BSM Selected (SAR Bit 1) : I 


FL 


Reset (CPU 


@ 225 ns Dela 
hm 


0 | 


. SROTI 25 ns Dela 


100 ns Dela Diag 4-080 
125 ns Dela 
TD 150 ns Dela 
175 ns Dela 
200 ns Dela 
225 ns Dela 2 
250 ns Dela 


Read Time PRT) 


Diag 4-080 








i Write , | Wr Set 
FL @ FL 
A : Rd Set 
er 





Reset (CPU 


o~ 250 ns Dela 


Write Time Tw) 


Diag 4-080 


5406 CPU—Functional Units 
Storage Delay Clock and Timing 


50 ns Dela 
75 ns Dela [DY 








CPU Clock KC102 
tead Call/Write Call eee Kem 
SAR Bits ' MA122,SR061 
ace [sk teenie am 
Write Tine Sotetek tbe Se ea 
on ns 
eieaiGaen mari S dcchacathaclect’ ies 
seas A 
Y Read Current > SRO22 
eee 
Strobe : Py SRO2} 
le Data ae at On Co Store New 
“es 
Reset SDR 774 (Reset On Store New SRO12 
| Le eee ns p 
X/Y Write Gate SRO21 
X/Y Write Current — SRO22 
Inhibit ee SRO12, SROZ1 
5406 FETMM (6/70) 





ALD Reference 





1 2 3 
Chan 1 Data Bus | DBI 
Diag 4-060 
Data Bus Out | | | = = | Chan 1 Data Bus Out 
Diag 4-100 
\/O IF Chan I/O Check Chan I/O Check he 
Diag 2-010 
iti I/O Condition A 
(/O IF Chan 1 I/O Condition A - . J ondition > 
Diag 2-140 
2-150 
& Chan 1 I/O Condition B | : I/O Condition B . 
1/0 IF ie, 
Diag 2-140 
2-150 
4-030 
4-035 
it 3- I/O LSR Select 3-7 
/O IF Chan LSR Select Bit 3-7 J elec > 
Diag 2-020 
— 4-076 
/O IF Chan Translate In Translate In TS 
Diag 4-100 
/O IF Chan Translate Out | Translate Out > 
Diag 4-065 
(/O IF Chan Binary Subtract 7 Chan Binary Subtract rR 
Diag 4-014 
\/O IF Chan’ Store Data Chan Store Data SD) 
Diag 4-032 
/O IF Chan Block SDR to B | . Chan Block SDR Tv 
Diag 4-044 
/O IF Channel CS Priority Bit | Chan CSR 3-7 ray 
Diag 4-064 
B é 
LIO Instr LIO Instr OIF) 
KD, V/O IF 
Diag 4-105 
TIO Instr | TIO Instr 1/0 IF 
|x) , /O IF 
Diag 4-105 
SNS Instr | SNS Instr [1/0 1F 
ae. /O IF 
Diag 4-105 
SIO Instr SIO Instr 70 IF Y 
[2 , /O IF 
Diag 4-105 Note: Some of these lines may be referred to as 'Chan 2’. 


5406 CPU—Functional Units | 
I/O Interface Lines 5406 FETMM (6/70) 4-100 


5406 CPU—Functional Units 
Op Register and Q Register Decode 


AND 







Note: X can be either 0 or 1 


2 Address Format 


1 Address (Branch 


1 Address (Non-Branch) 


Command Format 


Diag 4-070 
4-072 


Eisele ele lei se)s 
-[oj-feo[-[>]ef-j>|-le]~ 


4 
ae 
0 | 
0 | 
Ne 
0 | 
BE 
| 
i 
| 
ia 


1/O Not Console Instr 





Diag 4-030 
4-076 


jon | 1/O Check Stop Gate 


RN121 





2) 23 6 7 } 0 
; Fol olo fo | Xx Q Reg Zone Blank : i . 
: fo | ofo [o |o JoJo |o| On 4-05 
Ix{x}x{x fo fo fo [o| Q Reg Blank q — 
xfo}ofo fo jojo jo) gee 


RN101 467 
Q Reg Numeric Blank co 






Diag 4-032 
4-040 
Sel Int Lev 0 Decode — 





Diag 4-074 


g 
4 
| 
| 


5406 FETMM 


AND 


OR 
2 Address Format 


Zero and Add Zoned 

Add Zoned Decimal 
Subtract Zoned Decimal 
_Move Hex Character 

Edit 

Insert and Test Character 
Move Characters 

Compare Logical Characters 
Add Logical Characters 


Subtract Logical Characters 


1 Address Branch 


Sense ZO 


Load I/O 

Store Register 

Load Register 

Add to Register 

Test Bits On Masked 
Test Bits Off Masked 
Set Bits On Masked 

Set Bits Off Masked 
Move Logical Immediate 


Compare Logical Immediate 


Branch On Condition 


Load Address 


“oe 


Command Format 


(6/70) 


Diag 4-014 


Diag 4-014 


Diag 4-030 
4-040 
4-072 


Diag 4-014 
4-032 
4-050 


Hee 
Diag 4-030 


Diag 4-100 


Diag 4-100 












Diag 4-073 
4-100 


Diag 4-074 
4-100 


Diag 4-030 


4-105 


A 


DIAGRAM 
5-100 
5-100 
5-100 
5-070 
5-110 
5-120 
5-080 
5-080 
5-080 

» 5-080 
5~170 
5-160 
5-060 
5-060 
5-060 
5-050 
5-050 
5-050 
5-050 

B 5-090 
5-090 
5-130 
5-180 
5-190 
5-210 
5-200 
5-140 


5-150 


a 


INSTRUCTIONS 

Zero and Add Zoned 

Add Zoned Decimal 
Subtract Zoned Decimal 
Move Hex Character 

Edit 

Insert & Test Characters - 
Move Characters 

Compare Logical Character 
Add Logical Charccta 
Subtract Logical Character 
Sense I/O 

Load I/O 


Store Register 


~ Load Register 


Add to Register 

Test Bits On Masked 
Test Bits Off Masked 
Set Bits On Masked 

Set Bits Off Masked 
Move Logical Immediate 
Compare Logic Immediate 
Branch On Condition 
Test 1/O and Branch 
Load Address 

Halt Program Level 
Advance Prog Level 
Jump On Condition 


Start I/O 


5406. CPU—Operations 


Instructional/Functional Signal Reference 


ZAZ 


AZ 


SZ 


MVX 


ED 


ITC 


MVC 


CLC 


ALC 


SLC 


SNS 


LIO 


ST 


TBN 


TBF 


SBN’ 


SBF 
MVI 
CLI 
BC 
TIO 
LA 
HPL 
APL 
JC,” 


slO 


ALD 
REFERENCE 


5 
Z 
< 
6 
a 

OP BITS 
01231456 
xX 0100 
X 0110 
X O11] 
X 1000 
x 1010 
X 1011 
X 1100 
X 1101 
X 1110 
xX 1 
Y 0000 
Y 0001 
Y 0100 
Y O10! 
Y 0110 
Y 1000 
Y 1001 
Y 1010 
Y 1011 
Y 1100 
Y 1101 
Z 0000 
Z 0001 
Z 0010 
F 0000 
F 0001 
F 0010 
F  OOl 


KY101 


a 
ZL 
< 


KY101 


OR 


RN13] 
RN131 
RN13] 
RN131 
RN121 
RN12] 
RN111 
RN12] 


STORE DATA GRP 
BIN ADD OR SUB GRP 

BIN ADD GROUP 

BIN ADD/SUB NOT MOVE 
INH SDR X-FER 
SINGLE EB CY INST 

[/O NOT CONSL INST 
\/O CHK STOP GATE 


(Q REG NOT BLK) 


Se SK (@ REG NOT BLK) 


x X X x 
xX XX 
x 
x 
x Xx 
x x 
xX XX x xX 
X x x 


&) 






SK (Q REG NOT BLNK) 9K (NOT Q ZONE BLNK) 


SK (Q REG NOT BLNK) 


OW WKH ® 
&) 


RN111 


TIO INST (ADV OR TIO) 


RN111 


BR OR SKIP 







ee er CS Ca Cee 

Z, We LL “fe 1 £2 o£ 

~~ fF Sf SC Ff Sf Sf f& 

O 

uw 

wo 

x< 

oe 

Qa 

x Zz 

UO = 

7. a 

n < S 

Z a 

uu Oa ce 

S no = 2 oO 

eee TE Zeo-sré 
as > @ Oo aA e& 

a°-6 | O. 3S =e 

zr LCL He UH ao Ke KF Hv 


RN111 


HALFWORD FORM 


NH oN eS SS VS ce SS. a OR OR: ee ee 
Zo “2 Fy Be NZ. Oe OS eZ. BZ ZZ 
CO Cf Of O&elOMllOlUOCEDlClUl BK lO OE OE OES 

| 

WY 

z 

uu 

w -— 

O 3 © 

be = <= 

os n 5 a O 

LL 
SO: 2 OS Sw = Z 
Se SZ Oe « =< 226 83 2 
a OF # 0 6 O = & o 'S Dp. 
F ZH o> 38264 €N 22 & 
6 8 Be YM Za a SO ee ee 
Bo. ee ke ee St oe a: 
ow oe 2 eS oo SUS Be eS SES Ue eS 





Notes: *K Conditioned by Q Reg Bits 


&) Line developed but not used in this operation 
OP BITS 0123 
X 2 address instruction (can be indexed by bits 0-3) 
Y | address instruction (can be indexed by bits 0 and 1) 
Z 1 address instruction (can be indexed by bits 2 and 3) 


F Command instruction 


5406 FETMM 


(6/70) 


5-005 





5406 CPU—Operations 
I-Op and I-Q Cycles (Part 1 of 3) 


Clock 0 


Clock 1 & 2] Transfer 


Clock 3 & 4 


Clock 5 & 6 


















l-OP CYCLE 


Address 
Storage 


CR to CRR 
or CRR to CR 












Place 
Op code in 
ALU 


Load Op 
register and 


modify low order 
of instruction 
address 





| Reg decode 
to A 













Objectives: 
@ Load Op code into Op Register 


@ Increment Instruction Address Register 


@ Load CR to CRR if program interlock 
is off (I/O not busy) 


@ Load CRR for alternate program level 
into CR and back into same CRR if 
program interlock is on (I/O busy) 









ALU controls: 
| Clock 384 — 


KLI14I | none, all other 






















; times — ‘bin sub 
Activate jgate’ &'bin | KY121 
IAR seld comp A req' KY121 
Activate 
"load SAR' 
Activate Condition 
"sel PSR' recall register 
| (CRR) for 
{ current 
program level 
Activate 'CR 
bit - to A" 
| Condition Activate 


"load ALU' 





Activate 
'LSR write 











Data read 


Activate out to SDR 


"gate SDR 
to B' 


AV211 


| ALU output 
latched 


KL141 


Activate 
"TAR seld! 





KG141 


Activate 
"gate LSR lo 
to B' 





Clock 7 & 8 





KG141 


Activate 
‘mise bit 


7 to A' 


Activate 
"load Op 


Activate 
"LSR write 


low 








Modify high 
order of 

instruction 
address 














Activate 
"TAR seld! 





Activate 
"gate LSR hi 
toB' 





Activate 
'LSR write 
high' 


GO TO (3) 
I-Q CYCLE 





5406 FETMM=s((2/71) 5-010 












2 V 3 
Objectives: 
e@ Load Q code into Q Register and: (1) Length Count Register and «> 
Length Count Recall Register, or (2) Data Recall Register ATKuio1 AV211 
. . ‘ Activate ALU output 
A t 
@ Increment Instruction Address Register eparae | peas 
low' | 
& I-Q CYCLE : 
Clock 7&8 | Modify high 







order of 
instruction 


END 
l-Q CYCLE 


busy 
. parity check 
. attention 
inv D.A, 







ALU controls: 
same as I-Op 
unless noted 

otherwise 









Clock 0 










Address 
storage 


//o 
instr with (not 
‘channel in I/O 
cond B' 





Yes 





Activate 
"TAR seld! 

















| Activate 


instr with (not) 
"load SAR’ ' 


Clock’S 4 Place Q code 


in ALU and 

store in LSR's KL121 
Nl Used as Activate 
l LCRR ‘sel DRR 


and LCR' 







"Prog intlk' 
is deccHiNares 
if it was 
active 


Activate 
‘prog intlk' 


















ALU output 


| was latched 
| at Clock 4-cd 





Activate - Single KLI41_ 


"sel PSR' 


address 
instruction 


or Branch 
instruction 








Activate 
"IAR seld! 





AV211 


ALU output 
latched 





Activate 'CR 
bit to A' and 
‘AND gate' 





KG141 


Activate 
"gate LSR 
hi to B' 











KLIO) AV211 


ALU output 
latched 





Activate 
"gate SDR to 
B! 


Activate 


‘LSR write 
KL101 


Activate 
'LSR write 









high' and 
'LSR write lo' 


and modify TAKE I-R CYCLE} 
low order of 


instruction 


add 





jAnalyze Op 
pcode bits 
Oto 3 


Clock 5&6] Load Q req eos 
5-030 


L14) 5-042 


Activate 


Diag 5-020 






of 4 bits 
present 





AV211 KG141 


ALU output 
latched 






Activate 
"gate LSR lo 








| 
| 









. p 
to B! ee Yes bits (0 and 
KGI4] instruction Y) or and 





Activate 
‘misc bit 7 
to At 





p 
bit O or 
KDI41_ | | 










Activate | ALU output a 
‘load Q | was latched ° 
at clock 4=-cd 


TAKE IH] CYCLE TAKE IX CYCLE 
Oe 5-030 oy Diag 5-042 








Wait State 








System Reset (not) EB Cycle 


not) Alter SAR or Storage A 






Gate SDR to B 
I/O Block SDR 









\/O Not CE Test 


Main Storage 


SAR SDR 


cl 0 
Phase DE 


as Load SAR 
Se > X 


(not) Wait 
KC142 







Cl 5 and 6 
Gate LSR lo to B 


Wait State © ; 

System Reset jon | - < 
Cl 7 and 8 

> EB Cycle 


Cl 1 and 2 


Gate LSR Hi to B 


16 +2P 





16 + 2P 


1/O Not CE Test 


Channel Inhibit LSR Load 
Idle Time 
B A or B Reg Chk 


oF 
C18 
C4 jf ps LSR Write Hi 
IQ Cycle [ 


LSR to Aor B 


Cl 2 


1 Op Cycle 
Cl 6 


= jor 


KG14] 


HCl 3C to 5C_[—)bin Sub gate 
iB IN KYI21 


: A |And Gate 
fy Branch or Jump Instr 












fa Bin Compl A Reg 








IQ Cycle 
Cl 3C to 5C 


KY101 


zw 
@ 
«a 


Dec Bin : 
Lo 
Ovfl Ovfl _  Lo/Hi] EQ | 












paz) Tarte) 
oT T2Ts[4 [set tots [213] 4st ol7 





Test 
False 
















PSR-P1 (LCRR) PSR-P1 (CRR) 


POT iL 2 sf aist[ot7tolif{2t si 4 si6i7| 









Rie 





ae as FS 
a iS Ss 

is 5 

fa Be ge 

aa ity : bg 

ae ears : re 

af 

Beis X Poa 

ome : ee Re ce Oe co Saye idee 






PSR=P2 (CR) » 
OI TAT sar spel 7rerryapseTSTST7| 


~ PSR-P2 Select 






Force bit 7 to A 
A 


FL 


KY121 


Cond § 


Cl 4 
(not) IH Cycle 


(not) EB Cycle 
(not) Alter or Display Storage 


5406 CPU—Operations 





| | A LSR Write Lo 
Phase D a 


KL101 





a a ee ee | 
SITs ote PST 


I-Op and I-Q Cycles (Part 2 of 3) 





KG141 


Gate LSR Lo Normal to A 


Gate CR to A 


A 








LCR and DRR Seld 


CI 5and6 
(not) IR Program Backup 






Odd CD 


f 


LyleLlolfate] x}= fo) 


IAR Seld 


Load Q Reg 


ae | Op Cycle 


\/O Not CE Test 


N 
IN Fon | CE Test No Increm 


Program Interlock 


A | Op Cycle 
Cl 1 and 2 


KG131 
(not) Prog Interlock 


| Q Cycle 


— [CT Sand 4 
A e 
Branch or Jump Instruction 


Any | Cycle 


A not) Cl 3 and 4 
(not) IR Prog Backup 





Cl 5 Thru 0 


A | Cycle not IX Cycle 
Allow LSR Select 


| Q Cycle 













Cl 5 and 6 





Cl 1 and 2 
| Op Cycle 
Allow LSR Select 
Cl 3 and 4 


IQ Cycle 
2 Address Format 














Cl 3 and 4 
IQ Cycle 
Allow LSR Select 







KL121 


5406 FETMM = (6/70) 5-012 








1 2 3 
Cycle ALD Reference 
Clock KC122 
Load SAR KC142 
Read Call/Write Call KC132 
IAR Select KL141 
LSR Select KL121 
LSR Load KL101 
Load A and B Reg RAIO1 
A Reg Input RA111 
A B Reg Input RA101 
Load ALU AV132 
ALU Control (and) KY10] 
ALU Output AV142 
Bin Sub Gate KY121 
Bin Compl A Reg KY121 
Load Op Reg KD141 
Load Q Reg KD14] 
Set/Reset Prog Intlk KD131 
Condition Reg KGI11 
Op End KD131 


5406 CPU—Operations 


I-Op and I-Q Cycles (Part 3 of 3) 5406 FETMM - = (6/70) 5-014 


5406 CPU—Operations 
I-R Cycle (Part 1 of 2) 


Objectives: 


@ Execute command instruction, unless program 
interlocked 


e@ Increment or decrement Instruction 
Address Register 


Diag. 5-010 
a ~ |-R CYCLE 








- clock 0 





Address 
storage 


Rg 
Paeeis 


rr | 





Activate KL141 


"TAR seld! 


Refer to 
Diagram 5-010 
Point | 
to determine | 
| 
| 
| 















which type 
of cycle to 
take after I-Q 
cycle 





KC142 


Activate 
"load SAR' 










clock 3&4]Add to address in IAR 
for Jump instruction 
with condition satis- 





Data read 
out to SDR 





fied 


Activate KG141 


"gate SDR 


to B' Se 












Jump 
instruction with 
condition satisfied 
(Diagram 5-022 
9~A) 





No 


Yes 


Activate KG131 
"gate LSR lo 


normal to A' 








Activate 'bin 






comp A reg' KY121 
and 'bin sub 

gate' K Y1 21 
Activate KL141 


"TAR seld' 


Activate KL101{ ALU output 
'LSR write | latched 
low' | 






AV211 














Increment 
or decrement 
low order of 
instruction 


clock 5&6 













address Activate KL141 
"TAR seld' 
Activate KG14] 





"gate LSR lo 
to B' 











Activate 
"IR program 
backup' 






Activate 
‘mise bit 7 
to A! 










Activate 
‘bin comp 
A reg' 






Activate KG141 
‘misc bit 6 


to A' 















Activate KY121 


‘bin sub 
gate' 


KL10] , ALU output 
| latched 









Activate AV211 
"LSR write 


low' 










Increment 
or decrement 
high order of 
instruction address 


clock 7&8 


Activate KL141 
"IAR seld 





Activate KG14] 
"gate LSR hi 
to B' 





5406 FETMM__ (6/70) 





Activate KY121 
‘bin sub 


gate’ 










Activate 
‘bin comp 
A reg' 








Turn on 
‘Op end! 
trigger 






KL101 





ALU Output 
latched 


Activate AV211 


"LSR write 
high' 


END OF 
OPERATION 


Cycle 

Clock 

Load SAR 

Read Call/Write Call 
IAR Select 

LSR Load 

Load A and B Reg 
A Reg input 

B Reg input 

Load ALU 

ALU Output 

bin Compl A Reg 
bin Sub Gate 


ae | 
Op End eT 





* Jump Instruction only 





ALD Reference 


KC122 
KC142 
KC132 
KL141 
KL101 
RA101 
RAI11 
RAIO1 
AV132 
AV142 


KY121 
KY121 
KD131 


5-020 


/O Block SDR 


/O Not CE Test 


Wait State 


System Reset 


not) Inhibit SDR Transfe 
(not) EB Cycle 


Recompl Cycle 


ey te} DL 
Eze 


Gate SDR to B 


CL 3 and 4 A 
_fnot Alter SAR or Storage 
; KG141 
A, a 
SAR SDR 






CL 7 ana 8 
Gate LSR Hi to B 


Wait State 


X 
System Reset jon 
- Gate LSR Lo to B 
CL 5 and 6 


KG141 







Phase DE 


not) Wait State 





16 + 2P 


16 + 2P 


5406 CPU—Operations 
I-R Cycle (Part 2 of 2) 











CL 3C to 5C Bin Sub Gate Bin Compl A Reg 


KY121 


LSR Write Hi 


LSR Write Lo 









f xX i e * x 








IAR (Lo) 


JAR (Hi 
ol i2t3i4[sfet7to} ij 2}s] 4] 5{6{7| 


Force Bit 7 to A 


Gate LSR 
Lo Normal to A 













3 
CE Test No Increment 
jon I/O Not CE Test 
‘ (not) I-R Program Backup of: 
CL 5 and 6 


KGl4l | i Branch or Jump 


I-Q Cycle 
CL 5B 


B Reg bit 0 


ALU Blank 


System Reset 


A | R Cycle FL 
Jump Instruction ; 
n CL3 and 4 

Set Program Interlock 


CL 5B 


K D151 


Op End 


I-R Jump True 
Any | Cycle 


not) IR Program Backup 


(not) CL 3 and 4 





Channel Inhibit LSR Load 


I/O Not CE Test 
Idle Time 


A or B Reg Chk 
ae iste Aor 
Phase D 
CL 6 
(not) EB Cycle 
A not) I-H Cycle 
not) Alter or Display Storage 
KL101 
e not I-X Cycle 
IAR Seld A CL 5 Thru 0 
Allow LSR Select 
KL141 
5406 FETMM (6/70) 


5-022 


5406 CPU—Operations | 5406 FETMM (6/70) 5-030 
I-H or I-L Cycles (Part 1 of 3) 





Objectives: @ 2) (3) © 


e Load B Address Register except during load 
address instruction 







Modify high 



















































e Load selected Index Register for load address z Clock 
instruction , No 7 8°8.\| ordarot or test I/O and Yes 
. ; branch instruc- 
Instruction 
@ Load A Address Register for second address address KL141 
Yes 
e Load Adress Recall Register for branch or : Activate Load 
decimal instructions Activate Activate KL101 "TAR seld! address 
"LSR write 'LSR write instruction 
low' high! | 
| 


KG141 


Activate 
"gate LSR 
hi to B' 


See Note 1 
for format. 
Branch, test 


/O and branch 





_I-H OR I-L : 
Clock 5 & 6 | Modify low 
EYCLE order of 


































A re instruction Yes 
Diag 5-010 Sareea ee) Giddleées KLI41 or load address 
oe Refer to | Activate operations end KY121 KDI3I 
Diagram 5-010, : 'IAR seld'! after I-L1 Activate Turn on 
point | Address Clock 0 cycle. Other- 'bin comp A ‘op end! 
to determine storage wise proceed reg’ and 'bin trigger 
which type to specific sub gate! 
of cycle to | Saal , KG14) operation flow 
take after I-Q | Activate Activate charts after 








cycle "IAR seld' "gate LSR lo completing | KLIO] 
‘s) to B' cycles Activate 
. "LSR write 
high' 


KG141 
Activate 
‘misc bit 7 
to A! 





Activate 
"load SAR' 





KY121 
Activate 'bin 
comp A reg' 
and 'bin sub 


> Clock 3 & 4] Load register. 
High order 
position in 
























































I-H cycles, gate! 
low order 
ee AV211 KLIOI 
I-L cycles ee ; po. ea 
Vee XR1 - Q bit 7| ALU Activate ae { single 
XR2 - Q bit 6, output "LSR write I address 
and 3) ‘ : 
\ latched instruction 





Load 
address 
- inst 


Activate 
"ARR seld' 


Yes 





Branch 
instruction 












Load 
address 
instruction 


Branch 
condition 
satisfied 










Take I-H2 


cycle cycle 







KL141 
















Activate 
"XR1 Seld' 
or 
'XR2 Seld' 






Activate 
‘sel AAR' 


Activate 


'LSR intchg Yes 





















No Yes 
= Diag 5-042 
Activate END OF 
ol BAR } 
Take I-L2 Take I-LI Tested during I-Q 
cycle cycle cycle. Activates | 
Br-Jump true FL. | 
KG141 (Diagram 4-073) 
sare:ous | OPERATION 
to BY Note 1: Format for single address instruction 
, , is; 1-H] and I-L1 cycles or I-X1 
Ge | | cycle. Second address requires; |-H2 
and |-L2 cycles or I-X2 cycle 












Wait State 
System Reset joe | 
Not EB Cycle A Gate SDR to B 
/O Block SDR (not) Alter SAR or Storage. CL 3 and 4 ‘ 
/O Not CE Test | * KG141 
| 
ee : eee 
SAR SDR 
A CL 5 and 6 
Gate LSR Lo to B 
Phase DE : Wait State 
Cl 0 a Load SAR. N 
(not) Wait State . System Reset | pa 
A 
Cl 7 and 8 
KC142 Gate LSR Hi to B 


EB Cycle jo 
16 + 2P 
; Ciidad a || ee [Rel 


Cl 5 thru 0 


I Cycle not IX Cycle " 
Allow LSR Select 





1H 2 or IL 2 Cycle 
i AAR Sel 
Cl 3 and 4 
| KL121 
l-H1 or I-L1 Cycle 
Cl 3 and 4 i: BAR Sel 
(not) LDX Instruction 
KL121 
B 
IH 1 or ILI Cycle 
Cl 3 and 4 ARR Sel 
Allow LSR Select A 


Decimal Instruction 


Branch or TIO Instr KL141 
FC Instruction 


5406 CPU—Operations 
I-H_ or I-L Cycles (Part 2 of 3) 









I/O Not CE Test 










CE Test No Increment 





| B 
Cl 3C to 5C Bin Sub Gate Bin Compl A Reg FL i= 








ant anal Any | Cycle 
KY121 A Al le i not) Cl 3 and 4 
KY121 (not) IR Program Backup — 
1H IL 
oti 2434 [5 [6 iz folif2;3t4 [5] 6t7 | 
O12; sf4{5 pet 7 Poti {2 [3]4 [5 [6 [7 | 
IH Cycle 
3 | jon Cl 8 
d i LSR Write Hi A | Phase D 


“ARR (Hi) ARR (Lo) 


Channel Inhibit LSR Load 
OTT {273 (4 {5 [6 [7] 0] 1] 2) 3[-4[5] 6] 7] 


V/O Not CE Test 
L Idle Time 
A or B Reg Chk 
Cl 6 
A 


LSR to A or B 





5406 FETMM (6/70) 5-032 


5406 CPU—Operations 


5406 FETMM = (6/70) 5-034 
I-H or I-L Cycles (Part 3 of 3) 
1 v 2 Vv 3 

Cycle ALD Reference 

Clock KC122 

Load SAR KC142 

Read Call/Write Call KC132 

IAR Select KL141 

AAR Select(IH2 and IL2) KL121 

BAR Select (1H1 and IL1) KL121 

ARR Select (*) KL141 

LSR Load KL101 

Load A and B Reg RAI01 

A Reg Input RAI11 

B Reg Input RA101 

Load ALU AV132 

ALU Output AV142 

Bin Sub Gate 


KY121 
higitin [anieiiiebeialiek\....\deliemmuaaanaiieminaiealaadia: 1... mameaeedaiedae sac 


* Load ARR during IH] and IL] if 
BC, TIO or Decimal Instruction 








Cycle 


Clock 










Load SAR 

Read Call/Write Call 
IAR Select 

XR1 Select (see note) 


XR2 Select (see note) 












AAR Select ae: pt 
BAR Select ab yp 


* Force bit 7 if IAR Lo contains all 1's 
(Predicts a carry from IAR-Lo) 


Binary Sub Gate 






Binary Compl A Reg 


Op End 








ARR Select 


NOTE: The contents of Op Register bits 0 thru 3 
determine which Index Register is used. 


Format | OZ {3 | 



















| Op Bits _| B Address Register 
10 111213 | 


2 bytes from 

fo] Tt | Strage Unchonged__| 

Ol] |" [eo Adres rom 
Address to Address from XRI1 

ih eee = 
non-branch) to Address from XR2 

2 bytes from 
[11 [0[0 | sierage Unchanged 

le) Pear ae 
Address . to Address from XRI1 

| byte from Storage Added 

teanch) ||] "|| car rom 882 
= 


2 bytes from 
to Address from XRI 
to Address from XR2 
2 bytes from 
Storage Unchanged 
] byte from Storage Added 
1 byte from Storage Added 
2 bytes from 
to Address from XRI 
| byte from Storage Added 







Format 


] 










2 bytes from 
















Storage Unchanged 







2 















I 






Address I byte from 






Storage Added to 









Address from XRI1 






1 byte from 







Storage Added to 






Address from XR2 


5406 CPU—Operations 
I-X Cycles (Part 1 of 3) 


ALD Reference 
KC122 
KC142 
KC132 
KL141 
KL141 
KL14] 
KL12] 
KL121 
KL101 
RAI11 
RA101 
AV132 
AV142 
KY121 
KY121 
KD131 


KL141 


5406 FETMM 


(6/70) 


5-040 










































5406 CPU—Operations 5406 FETMM (6/70) 5-042 
I-X Cycles (Part 2 of 3) 
1 2 3 
Objectives: 
e Add address to contents of Index Register Se oO 
@ Load B Address Register unless load address 4 aes 
instruction : 
e Load selected index register if load address No Yes Clock 5 & 6| Increment Activate KL101 
instruction HOW SOrGCr Uh pt a Se 'LSR write 
eo Load A Register for second address of instruction If computation high’ 
e Load Address Recall Register for Branch address Activate KL141 resulted ina 
or Decimal operations single x 'IAR seld' carry, 'temp 
address Yes carry' gives 
I-X CYCLE instruction ‘arith carry 
1D» 2 out' for clock No 


; 

















































































































































Diag . aaa Activate - KG141_ | 7 computation 
2010 Clock 0 | Address : gore Lehe 
p <!oc Activate ~ Activate } XRI for Op Activate to B! Opbits (0 | 
| storage "XRI seld’ "XRI seld' | bit 1. XR2 'XR1 seld! and 1)or (2 | 
| ! or or | for Op bit 0 or and 3) 
| Activate KL141 'XR2 seld' 'XR2 seld’ | 'XR2 Seld' Activate KG141 es Single 
L____, "TAR seld' | | ane bit 7 address 
ear J | to A instruction 
diagram 9-010 | XR1 for Op Activate KG131 XR1 for Op | Branch 
point Aétivate KC142 | bit 3. XR2 "gate LSR lo bit 1 (not) bit | : Activate 'bin} KY121 No instruction 
to determine Noad SAR! for op bit 2 | normal to A! O or Op | 2 comp A req' 
which type bit 3 (not) bit | a and ‘bin Load 
of cycle to 2 . XR2 for | 2 sub gate' Yes Gadaks 
tae etter Activate KG141 Ope 7 : ; etuet 25 
I-Q cycle (not) 1 or A 
e 'gate SDR Op bit2 | ctivate KL101 Tale . . 

Clock 1 & 2] Increment to B! Gon 3 LSR write 1-X2 ih ee 
high order of low cycle No condition 
instruction satiation 
acldvacs Activate KL141 

"TAR seld' Activate 'bin | KY121 
comp A req! a 
ond 'bin, Clock 7 & 8 a a a) Toke Activate 
1 
register = cycle Pore 
Activate g 

















"gate LSR hi | 
to BY | Low order of 
p JAR will carry 
MA121_ | to high when 
_ incremented 


KG141 





Activate 
‘misc bit 7 
to A’ 





Activate 
‘bin comp A 
reg' and 'bin 
sub gate' 


KY121 











Activate 
'LSR write 
high’ 


KL101 





Clock 3 & 4] Load low 
order of 


selected 









Clock 4 


Deactivate KL141 
'XRI seld' 


or 


"XR2 seld' 

























Load 
address 
instructio 





Activate 
*XRI seld' 
or 
"XR2 seld' 











Activate 


‘sel BAR' 







XR1- Q bit 7, 
XR2 - Q bit 6 
| 








Activate 


"ARR seld' 


‘Activate 
"LSR write 
low 


or decimal 
instruction 





KL101 





Activate 
"sel AAR! 





See Note 1 for format. 


Branch, test |/O and branch, 
or load address operations 


end after I-X1 cycle. 
Otherwise proceed to 
specific operation flow 
charts after completing 
I-cycles 





KL121 


Clock 8 





Activate 
'XR1 seld' 
or 
*XR2 seld' 

















Activate 
"gate LSR hi 
to BY 





Activate 
‘bin comp A 
reg’ and ‘bin 
sub gate’ 





Deactivate 
'XR1 seld' 
or 


"XR2 seld' 








Activate 
"sel BAR,' 
"ARR seld,' 


‘sel AAR,' 
*XR1 seld,'- 
or 'XR2 seld' 












Branch 
or test |/O 
and branch 
instructio 


Turn on 


"Op end! 


trigger 












Select same 
index regis- 
| ter selected 
at clock 3 






KG141 


KY121 


KL141 





Select same 
| register 
4 selected at 


clock 4 
















Load 
address 
instruction 


No 





Diag 5-030 


END OF 
OPERATION 










Tested during I-Q 
cycle. Activates 
Br-Jump true FL. 
(Diagram 4-073) 
KD151 





Note 1: Format for single address instruction 


END OF 
| CYCLES 


is; I-H1 and I-L1 cycles or I-X1 cycle. Second 


address requires; |-H2 and I-L2 cycles or |-X2 


cycle, 


aan 





Inhibit SDR Transfer 
EB Cycle 


not) Recompl Cycle 





Cl 8 
1 Address Branch 
IX1 or ILI Cycle 


Gate SDR to B 
; jor 


KG141 














(not) Cl 3 or 4 
Alter SAR or Storage 
l/O Block SDR 






Wait State 





System Reset 


Main Storage 


j “| 














Gate LSR Lo 
Normal to A 









CI 5 and 6 





A Wait State Gate LSR Lo to B A | 
N eS go . 
esata IN - 
: em = x14] IX Cycle jon Bin Sub Gate 
not) Wait State Cl lan 
IX Cycle A KY121 
Hi to B 



















































Cl 7 and 8 
LSR Write Hi a | 
A 
KL101 
IX C cle a a! Sere ae See ae ER ee eee nc ate gieeee ote 
ee oO eee IAR Seld : IAR (Hi) IAR (Lo) 
yl, £7 Y an 
POET ].2 13: 
KL141 x 
] 6 + 2P en ee ee 
1x2 C cle : ne Been eee reece ee eee nee eee een a 
open : : XRI (Hi) XRI (Lo 
o Bit 2 Cl 3 or 7 
eek ao Port 21314 5 Let7 POT 2131 41S [eT 7 
Op Bit 0 A Cl 30r7 ts 
PF} on Sel XR2 Gate A XRI Seld : ; LSR Write Lo 
IX1 Cycle | 
. A KL101 
Spe ae Cl 4or 8 
Op Bit 6 
Load Index Register 
1 Address Branch Instruction A J 







Vee carte Car Te hea ee ee aE | Bee een ent Tea ee 


AAR (Hi) AAR (Lo) 


i. XR2 Seld Oli; 2;314 5 ;6t7] of if 2] 3/445 [6] 7| 
A x yo 
BAR (Hi BAR (Lo) : 


AAR Seld 













1X1 Cycle 
Cl 3 or 7 
Op Bit 2 
Cl 3 or 7 


KL121 














1X2 Cycle | =g__ BAR Seld 
aa loli T2T3t4 15 eT 7Ott 213 [415 18 T7 aa 
Branch or TIO IX1 Cycle LE SEES rca 
Decimal Instr jor ae ARR Seld i ARR (Hi) ARR (Lo) 
oF - POT UP 273745767 7f Offi [27374] 5) 6t7) 
KL141 


5406 CPU—Operations 
I-X Cycles (Part 3 of 3) 


Force Bit 7 to A on 


3 


LSR Lo (IAR) All 1 
IX Cycle 
Cl 1 and 2 


Cl 5 and 6 
not) IR Program Backup 


not) 1/O Not CE Test 
not) CE Test No Increment 


IX Cycle 






Cl 3 and 4 


l-X Cycle 
Any | Cycle 


not) Cl 3 and 4 
| (not) IR Program Backup 










Cl 2 
IX Cycle 


cl 8 


A 


1 1/O Not CE Test 


Channel Inhibit LSR Load 
| dle Time 
A or B Reg Chk 


LSR to Aor B 


Phase D 


Cl 6 


(not) IH Cycle 
not) EB Cycle 


A Cl 4 
(not) Alter or Display Storage 
1X2 Cycle 
Cl 4or8 
IX1 Cycle 
Cl 4or8 


not) Load Index Register 


5406 FETMM (6/70) 5-044 


5406 CPU—Operations 


Set Bits On/Off Masked and Test Bits On/Off Masked (Part 1 of 2) 


1 


Objectives: 
bits: 


. 01234 
Set Bits On Masked Op Code XX111 


567 

010 

e If a bit is present in the Q code, turn on the 
corresponding bit in the storage location 


specified by the B Address Register 


@ Do not change bits which correspond with bits 
not present in the Q code 
bit 01234567 
Set Bits Off Masked Op Code XX111011 
e If a bit is present in the Q code, turn off 
the corresponding bit in the storage location 


specified by the B Address Register 


@ Do not change bits which correspond with 
bits not present in the Q code 
& bis 01234567 
Test Bits On Masked Op Code XX111000 
e@ If a bit is present in the Q code, test to see 
if the corresponding bit in the storage 
location specified by the B Address Register is on 


@ Ignore bits which correspond with bits not 
present in the Q code. 


@ Turn on 'test false’ latch if selected bits 
are not all on 


. 01 

Test Bits Off Masked Op Code X X 
@lf abit is present in the Q code, test to see 

if the corresponding bit in the storage location 


specified by the B Address Register is off 


@ Ignore bits which correspond with bits 
not present in the Q code 


@Turn on 'test false’ latch if selected bits 
are not all off 







































































Set bits off: 
Complement 
DRR and 
combine with 
storage. 

Test bits on: 
Compare bit 
positions on 

in DRR with 
same positions 
in storage. _ 
Test bits off: 
Compare the 
complement of 
bit positions 
on in DRR 
with same 


| 
I 
enters data | 
at clock 5 | 


KL121 





Activate 


false! 
‘sel BAR' 





Activate KC142 


"load SAR' Clock 7 & 8 End 


Operation 












decremented 
from 5 to 8 





positions in top end! time but is 
storage trigger insignificant 
for this 


operation 


KL121 





Activate 


END OF Machine Cycle 
and LCR’ : orEAueN Clock 


Read Call/Write Call 












KG131 Load SAR 
Activate Load DRR BAR Select 
1 s 
gate LSR lo | into A reg DRR Select 


normal to At 





B Reg Input from SDR 
KG141 A Reg Input from DRR 
Activate Load A and B Reg 
igate SDR Load ALU 
oe ALU Output to SDR 
Store New (New Data) 
Bin Compl A Reg (Set Bit Off) 
ALU Control. (And/Or) 
Op End 





Activate 
'CR test 


5406 FETMM 































SET BITS ON/OFF MASKED ey @ 
TEST BITS ON/OFF MASKED | | 
a. 7 | Requires Sat 
| single bits on or No 
| B Cycle test bits on 
operation 
Clock 0 Address Activate KY121 
storage ‘bin comp 
: A reg' 
Activate KDI11 pelivets 
"EB cycle’ or gate 
Activate KY101 
‘and gate’ 
Set 
bits on/off 
masked 
operation 
Activate RN131 
store date bits on or test Yes 
t 
group oits off operation 
let Sa Test bits on: 
Clock 3&4 | Set bits on: Activate KY111 KC132 false for No A Reg bit and 
| Combine DRR 'hew data to "Read call/ Activate any bit (not) B Reg bit. 

storage write call' "store new' Test bits off: 


A Reg bit and 
B Reg bit. 


Set Bits On/Off 





(6/70) 5-050 


ALD Reference 


KC122 
KC132 
KC142 
KL121 
KL1 2] 
RA101 
RAI11 
RA101 
AV132 
AV142 
KC132 
KY121 
KY101 
KD131 


Single EB Cycle Instr CL 8 





EB Trigger 


KDISI 


Main Storage 


SAR 


Store New 
CL4CD 
New Data to Storage FL 


e CL6 
A “KCI32 
EB Cycle 
(not) Significant Digit 
(not) Edit Instr 
Store Data Group 
KY111 


Op Bit 6 


(not) Op Bit 7 
not) Test On or Off A 
not) Op Bit 6 


(not) Halfword mat] OF RN131 











1x 


Gate SDR to 


not) Recompl Cycle 
Inhibit SDR Transfer 


(not) 3 and 4 Time 
Wait State 


System Reset 
Alter SAR or Storage 
I/O Block SDR 


(not) Inhibit LSR Sel 


not) Recompl Cycle 


EB Cycle 


CL 5 Thru 0 


5406 CPU—Operations 
Set Bits On/Off Masked and Test Bits On/Off Masked (Part 2 of 2) 


o 












Sel BAR 


KL121 


KG141 


Test False 


Code (IQ Cycle) 


fo [if2}3 }4 [5 [6 {7 | 


otilepapatstel7 ol ital ssl steis 


Set Bits On 


Test Bits On 
Set Bits Off 


Test Bits Off 
Set Bits Off 


Test Bits Off 


Test Bits On or Off 


7 Sel DRR 









Op Bit 4 
EB Cycle 
A Cl 3 and 4 


not) Zone Num Interchange 


Gate LSR Low Normal to A 


KG131 


Machine Cycle 

fm Clock 

f) Read Call/Write Call 
Load SAR 

RR Select 

b BAR Select 

@ B Reg Input (SDR) 

BA Reg Input (DRR) 

BM load A ond B Reg 

B) Load ALU 

= Bin Compl A Reg (Test bit off) 
= ALU Control (And/Or) 
ALU Output (Test False) 
5 CR Control 

Op End 


EB Cycle 


CL 3 and 4 
Halfword Format 


RN111 


LSR Write Lo 


- LSR Write Hi 


Test Bits On/Off 





ALD 


Reference 





not) Op Bit 4 


One Address Non Branch 


Channel Inhibit LSR Load 
I/O Not CE Test 

Idle Time 

A or B Reg Chk 
LSR to A or B 

EB Cycle 


Clock 2 


5406 FETMM (6/70) 5-052 


Pm, 


5406 CPU—Operations 
Store, Load, or Add to Register (Part 1 of 3) 


Objectives: 


oOo 
On 


bit -012345 
Store Register Op Code XX1101 
e Store the registers which are selected by the Q 


code into the location specified by the BAR 


bits - 01234567 
Load Register Op Code XX110101 
@ Load the registers which are selected by the Q 
code with data from the location specified 
by the BAR 
bit -01234567 
Add to Register Op Code XX110110 


@ Add the data from the location specified by the 
BAR to the contents of the registers which are 
selected by the Q code 


e@ Load the results into the selected registers 


LOAD, STORE, OR 
ADD TO REGISTER 


Requires 







Address 
storage 





KDI111 


Activate 
"EB cycle’ 











Activate 
"Ist E cycle’ 





Deactivate 
"Ist E cycle 





Store 
register 
operation 


Yes 


Activate 
‘store data 
group' 








Activate 


storage' 








Activate KL121 


"sel BAR' 





Activate 
"load SAR! 















RN131 




















"new data to 





RN111 


jLoad CR oper- 
jation is Q bit 5 
|(not) Q bit O 






Clock 1 & 2] Set CR to 
equal on Ist 
cycle of add 
to register 
operation or 
load CR oper- 


ation 


















Add 
to register oper- 
ation or load 
operation 














of operation 












Activate 


"CR equal’ No 






Perform 
operation 
objectives 


Clock 3 & 4 












Q 
register 


bit 


Activate 
"EB inter 


KL101 + eal 
reg inst 


Activate 
'gated P1/P2 





reg instrs' 
















Q 
register 
_ bit 

] 


register 


Yes bit KMI111 
] 





KT131 









Activate 'sel 
JAR/ARR inter 
1' or 'sel ARR/ 
IAR inter 1' 





Activate 
"TAR/ARR P2 

seld' or 'ARR/ 
IAR P2 seld' 





















Q 


register 






Q Yes 

























register bit KM111 
bit KL101 2 Activate 'sel 
2 Activate IAR/ARR inter 









'P] [AR/ARR' 
or 'P1 ARR/ 
1AR' 


2' or 'sel ARR/ 
JAR inter 2' 





















Q 


register 





Q Yes 


















register bit KM101 
bit KL141 3 Activate 'sel 
3 Activate Could be IAR/ARR inter 










"TAR seld! | any JAR, 
| whichever 


ts current 


3' or 'sel ARR/ 
IAR inter 3' 






Q 


register 


Yes 




















Q it 
register Yes 4 aa 
bit KL) Activate 'sel 
JAR/ARR int 
4 Activate i es 







4' or 'sel AAR/ 
"ARR seld! im 


R inter 4! 










Q bits 
1-7 


absent 







Q Yes 


register 
bit 
> 






Yes 






KT141 


Sel "IAR/ 
ARR inter 
Q' 


KL121 


Activate 
"sel PSR' 















PSR is used 
as the CRR 
| and the LCRR 









Q 
register 
bit 
6 






Q 

register 
bit 

7 










Load 
register 
operation 


Yes | 






Store 


ation 







Activate 
‘gate SDR to 
B! 


Clock 5 & Of 






Set CR and 


order of BAR 


No 






register oper- 


decrement low 

















Activate 
"Gate LSR 
hi to A' 


Yes 


Yes 














K 


Activate 
'XR2 seld' 





KL141 


Activate 


"*XR1 seld' 





— Activate 


sub gate’ 


req' 


Activate 


transfer' 


Activate 


Activate 


high' 


to register 
operation 


"gate LSR lo 
normal to A' 


"inhibit SDR 


‘store new' 


"LSR write 


L141 


"CR hi' 


KG13] 












Activate 'bin |KY121 








and 


'bin comp A {KY1 








































Yes 


Activate 











Activate 
"LSR write 
low' 


Activate 


CR hi' 


AV222 


a 


AV212 


Activate 
‘CR lo. 





Yes 


Yes 
























KG121 





Deactivate 


‘CR Equal' 





















Activate 
‘CR lo’ 


KG111 Clock 


Activate 
'CR bin 


overflow' 


Decrement 
high order 
of BAR 





5406 FETMM — (6/70) 5-060 
By ven 
Kua | KY13] 


| If add to 

| register oper- 
| ation and com- 
| putation re- 


Activate 
"sel BAR' 





KG141 |sults ina 
Activate | carry, ‘digit 
'gate LSR lo carry’ is 







| activated to 
| give ‘arith 

[carry out! at 

[next clock 


3C - SC 


to B! 






KG141 
Activate 
‘misc bit 7 
to A! 







KY121 
Activate 'bin 
sub gate' 


KL101 


Activate 
"LSR write 


low 








KL121 









Activate 
"sel BAR' 






Activate 
"bin sub 


gate’ 






Turn on ‘op 
end' trigger 









Activate 
"LSR write 
high' 






END 








spewed 


1 Address Nonbranch 
(not) Ist E Cycle 


EB Trigger 


EA 








Op Bit 5 





_1/O Not CE Test 
CE Test No Increment 


N ‘ 
Force Bit 7 i dh C!5 and 6 N Wait State 
System Reset 


(not) IR Prog Backup 





“KDI3I 


(not) Op Bit 6 and Not 7 


KG141 
Inhibit SDR Transfer 


EB Cycle A 
not) Recompl Cycle 






Gate LSR Hi to A 












not) Cl 3 and 4 
Alter SAR or Storage Gate SDR to B 


I/O Block SDR 





Wait State 























System Reset KG141 Gate LSR Lo Normal to A 
spr | 
EB 3C to 5C 
not) Op Bit 7 
A | Bin Add Group A | (oot) Op Bit 4 
1 Addr Non Branch 
Phase DE F 4 . 2 KY121 
clo A [boad SAR ) ei ah 2 . a Bin Compl A Reg 







5 ; 
eee ee (not) Op Bit 4 


(not) Op Bit 7 A (not) 3C to 5C : i 
1 Address Non-branch | 


RNI31 EB Cycle 
Bin Add or Sub Group ea 


New Data to Storage 













KY121 





Q Code (I-Q Cycle) 


es 






Op Bit 6 not) Significant Digit 


not) Edit Instr Bin Sub Gate 





not Test On or Off St D G ny FL 
A ore Data Group A 
(not) Op Bit 6 KYI11 a Channel Inhibit LSR Load 


KCI 32 











LSR Write Hi 


A 

pa I/O Not CE Test 
eee, aa Idle Time 
Lae A or B Reg Chk 


LSR to Aor B 





CI 5 and 6 







Gate LSR Lo to B 





Wait Stat : 
Wait State LSR Hi (Selected 


by Q Code) 


LSR Lo (Selected by 
Q Code 
OUT 2i3} 4p spot 7poyii 23st 4y slet7| 


System Reset 











Cl 7 and 8 







EB Cycle 


gansel | A [Eo pasar 
BAR (Hi) BAR (Lo) a = not) Recompl Cycle 
Ov it 2734 tsi éi7fofi ft 273] 45 16 [7] (not) Inhibit LSR Select 


KL121 





Cl 1 and 2 







Ist E Cycle 


EB Cycle EB Cycle 






= Halfword Format 





5406 CPU—Operations 


Store, Load, or Add to Register (Part 2 of 3) 


5406 FETMM_—_ (6/70) 5-062 


Machine Cycle 








Ist EB 





2nd EB 












ALD Reference 


LSR Selection 
























Clock roe : KC122 - Q Code bits With Q bit 0 With No Q bit 0 
aeciecl Le ceca mmole Nagel ee Se aig enero ponent ce (emt t ae 
oe a nara ved cena cl ane ba mn an spa el et Pas Pe 
ae Interrupt 2 IAR PI-IAR 

oe fo melee, elec, iii 

em | Lr ee — — . 
LSR Select(Determined by Q Code) doo ia KL121 —— Interrupt 4 IAR PARR | 
B Reg Input (SDR) TT (SDR) ee ee i a ae RA101 psp 
A Reg Input =e ey | VILLI | eee RAI11 =| 
Bin Compl A Reg Baa eee KY121 

t tO lAR 

ee ee ee Store. baal [Nother bits | Interupt 01AR | —— | 
Bin Sub Gate CLLLLMA LLL LALA ee Fey / K Y101 
tanh ee ee i ve 
capes Re ee ee ee awe 
seh a angle 1. Ah. te. i. ae “it 

Reset 

iaieipibliaitieediiiik: 'Vicce.2 Ave abidilcasel dannd iced tend. 38 6. ed et a 
EA Eliminate Bie ee en re eee ee ee ee KY11] 
sta ESOS) Slice a oe esl tae he Ae oe ed ae 
Op En fee eee ie ee mec 





Condition Register 


If ALU bit 2 If ALU bit 3 





Decimal Overflow 


ead PSR If ALU bit 7 


Add to Register 











If ALU bit 6, not 7 If ALU not bit 6 or 7 If ALU bit 4 











If Result is not zero 
and no high order carry 


If Result is not zero 
and a high order carry 


If Result is zero If Result is too large 
for Register (no high 


order carry) 





5406 CPU—Operations 


Store, Load, or Add to Register (Part 3 of 3) 5406 FETMM (6/70) 5-064 


5406 CPU—Operations |. os 5406 FETMM (6/70) 5-070 
Move Hex Character (Part 1 of 2) | , 































































































































1 2 3 
01234567 
Objectives: Op Code XXXX1000 
e Move numeric (lower four bits) or zone (upper four bits) nh A 
portion of the byte in the location specified by the Clock 7 &8 End i 
A Address Register, to the numeric or zone portion of Activate KY111 Opziction decremented 
the byte in the location specified by the B Address Register. ‘new data E from 5 to 8 
to storage’ . time but is 
@ Do not change the other half of the B address a nn insignifi- 
location byte. ee cant for this 
| . : trigger operation 
e@ Do not change the A address location byte. Activate KL121 . 
| | "sel BAR' | : 
@ Bits 6 and 7 of Q code specify portion used. END OF 
OPERATION 
Activate KC142 | 
Ce "load SAR' 
A 7 
MOVE HEX Clock Store select 
CHARACTER 3&4 ed portion 
of DRR and 
unchanged 
Clock 0 | Address A portion of B 
address field byte Activate KL121 
storage KD121 in B address 'sel DRR 
location Activate location and LCR’ 
"EA 
cycle! 
LONG. 
to zone No 
or numeric to RN121 
Activate | RN13I Se ee Activate 
‘store data 'Zone num 
group’ interchg' 
Activate 
Activate petivele KL121 "gate LSR lo Activate 
"load SAR' sel AAR normal to A ‘gate LSR lo 
crossed to A' 
Activat 
Clock Store A ‘ ea 
384 field byte a 
in DRR er 
bs RNT21 | 
Activate 
oie ; : | . | z ALD 
‘gate SDR si aia EA EB Reference 
to B' a an ss = _ aera arerer ene ee rrr een 
oc - 
Ae Read Call/Write Call Se ee ||| KC132 
am ee ee ae eal 
B sed ck pumerie to numer ere cme i 
BAR Select eae KL121 
Activate RN121 B Reg Input (SDR) Ce ee ete eerie RA101 
'LSR write Activate Activate DRR Select (A Reg Input) Peron ghee cn ae ede a | aes i nn KLI2] 
i ‘move num' ‘move zone’ eal ce oe ee dee elles ae cae eee RAIOL. 
es en se a = aes A 
ALU Control (And/OR) aE KY101 
ce |__| | _} mg __{__} | fa om | | AVI32 
Clee 0] Are 8 ce ALU Out Sl ae aml avian 
address decremented ALU Output " is 
storage from 5 to 8 | Load LSR ; een 
sca “ime ba torenew' | | write coll ane eee a 
Activate insignificant | or oe ete ar eee a eae al acon 
at cloc 





"EB First E Cycle 


Op End 


for this 
operation 





ee BPH KD131 


cycle 








5406 CPU—Operations 


Move Hex Character (Part 2 of 2) 





EB Cycle 









not) Recompl Cycle 
Inhibit SDR Transfer 
Wait State 








SS 





o © 
E 


Z| 








System Reset 


not) 3 and 4 time 


Alter SAR or Storage 
O Block SDR 





Gate SDR to B 








KG141 


Gate LSR Low 
A 





































= EB Cycle 


Op Bit 4 
A 
Gate LSR Lo pa EB Cycle 
Crossed to A | ig 
KGI31 : CL 3and 4 
= Cl 2 
Store New | | EB Cycle 
< | | | jon Cl 7 
LSR Write Hi 






t) Significant Digit . so 
nel a os A Naw Dateto. Store : Chan Inhibit LSR Load 
n 1 n ET 
Cc Ak 
L 4 CD AG a A | VO pot CE Te 
KYI11 by | Idle Time 
CLO A or B Reg CHK 







er A 


CL 6 
KL101 
CL 4 


not) EBC rele 
A not) Alter or Display Storage 
not) | H Cycle 


Sel DRR 







Store Data Group 
























Op Bit 6 
woes | = — 
not) Test On or Off ‘2 
ae 10 O|ZonetoZone_— 
not) p eit | 0 1 | Numeric toZone _| 
110 | Zone to Numeric 
(not) Halfword Format Move Numeric 11__1_| Numeric to Numeric _| 





ALU Controls: No Controls-Output Same As B Reg 
Both And and Or-Output Same As A Reg 





EB Cycle 
not) Op Bit 4 EA Cycle EA Cycle 
A Halfword Sel AAR rn 
One Address Format CL 5 Thru O 
RN111 KLI21 
(not) Inhibit LSR Sel 
Sel BAR 










= Rs —s 
A EB Cycle 
m 16 +2P CL 5 Thru 0 


5406 FETMM (6/70) 5-072 


5406 CPU—Operations 5406 FETMM = (6/70) 5-080 
Move Characters or Compare, Add, or Subtract Logical Characters (Part 1 of 3) 






















































1 2 3 
Objectives: eg (2) © e) ) @ oe 
bits 01234567 ; KLI21 : 
1. Move Characters Op Code XXXX1100 : Activate KY111 KY121 
‘sel DRR and : ; ; 
e Move the contents of the A field to the B field LCR! Activate Activate Bouvet 
bitt01234567 ‘sel BAR' "new data “bin sub 
2. Compare Logical Chars. OpCode XXXX1101 KLI01 to storage! pea ove 
| Activate : KC142 ae KL101 
@ Compare the A field data with the 'LSR write , - reg 
B field data . low! ee tvate : ; Activate 
| bits 01234567 load SAR sca 'LSR write 
‘ In su i 
3. Add Logical Characters Op Code XxXXX1110 ae low 
e@ Binary add the A field data to the B field data Clock 5 & 6 | Decrement 
and store results in B field location ere re ae KL121 Clock 1 & 2 ao. Clock 3CD | Activate een att Clock 7 & 8 oe 
1 was latche high order 
4. Subtract LogicaleCharacters Op Code XXXX1111 Activate cycle except load Q 3 at Qed EAR and KL121 


reg 





"sel AAR’ check for 


blank Q reg 


Activate 
‘sel BAR' 


| first B cycle 
e Binary subtract the A field data from the B field ; 
data and store results in B field location 


KG141 


Activate 












































‘ i isc bi Compare 
5. All Operations Activate misc bit 7 ee No A and B KG141 
' ' eratio 
oe LSR lo to A operation KC132 becelas a 
e@ Aand B fields are same length fo Mews Activate ACD reapeated until ae 
: Q i g9 
e Length of field is Q code pius | operation mloiepew. lnlane Sues hi to B 
pelviats i Qre Ss blank 
e et Condition Register except during move operation hae bit 7 | at jend pe field KY121 
MOVE, COMPARE, jhas been Activate 
ADD, SUBTRACT (6 ) preached and "bin sub 
LOGICAL : joperation is gate’ 
" Activate | 





Activate 
‘sel DRR 
and LCR' 







"bin sub jended 


gate' Clock 5 & 6| Decrement 
low order = $_-———————- — — — — — — — 
of BAR and 


set CR 


RN131 
Clock 0 (10) | Op code 


. activates 
Address A | ‘store data 
address } 


grou 
storage 
location 


















Q 
register 


blank 




















Activate 
'LSR write 
low! 















Yes resulted in a 
carry, ‘digit 
carry’ is 

activated to 


Move 
operation 





Activate 
"gate LSR 
hi to B' 





Turn on 
‘op end! 
trigger 


Yes 





give ‘arith 
carry out' at 
next clock 
3c-5Sc 





KD121 Clock 7 & 8 


Activate 
"18t E cycle’ 


Decrement 
high order 
of AAR 


Activate 
‘bin sub 


KL121 aie! 





KL101 


Activate 
"LSR write 
high' 





AV142 


Activate 
"sel AAR' 















ALU 
| output 
| latched 


Activate 
"LSR write 
high’ 






register 


blank 





Activate 
"EA cycle’ 





Activate 
"gate LSR 


hi to B' 
oe Clock 3 & 4] Compute A 


and B field 
data and load 


p 
end' trigger 
_ on 


KL121 





Activate Activate 


Activate 























‘sel AAR' tytceuls remaining : 
; sel DRR : 
te! field length Activate 
gate into @ te and LCR! ICR hit Yes 
KC142 Activate 
| KG131 "CR lo! 
Activate Activate Activat 
"load SAR' 'LSR write CHINES DRR Add 
Site gate LSR lo loaical 
high jinn ogica 
normal to characters L121 
(6) eperctl Activate 
Clock 0 Address B tsel BAR! END OF 
Clock 3 & 4 ie ; aide Yes Move No OPERATION 
leld data storage KD111 operation 
in DRR KG141 g KGI141 





Activate 
'CR bin 
overflow' 


location 


Activate : 
oe Activate 


"Gate LSR 
lo to B' 


Activate 
‘gate SDR 





"EB cycle’ 


Activate Activate 
‘inhibit SDR "gate SDR 
transfer' to B' 





to B' 





KG141 







Compare s<.No Activate 
operation 


| "Misc bit 7 
QO © OO CS e C) 7 
Yes 








Cl 5 and 6 
Wait State Gate LSR Lo to B 2 Address Format Cl8 Op End 


A N 
System Reset La ny Q 
EB Cycle | \ 


(not) Recompl Cycle < 

Inhibit SDR Transfer (not) Cl 3 and 4 Time 
1/O Block SDR N Gate SDR to B OR 

Wait State Alter SAR or Storage 
































Gate LSR Low Normal to A 









Recompl Cycle 


System Reset KG141 (not) Q Num Blank 


; EA Eliminate 
Dec Instr 


EB not Ist Cycle 


A A 
Cl 1 and 2 2 Address Format 
: Ey Cl 5 and 6 
- I/O Cycle Not Test 


Ba KGI41 not) IR Prog Backup 
comme CE Test No Incre 
Wait State 
System Reset 


Cl 2 


EB 3C to 5C a | 
fs | EB Cycle Channel Inhibit LSR Load 


Cl 1 and 2 


Gate LSR Hi to B 


Wait State 






System Reset 


(not) 3C to 5C 


: s Bin Sub ‘Gate 
e [ Binary Add or Sub Group 
Main Storage s S 















































KY121 jon 
= Cl 8. I/O Not CE Test 
SAR SDR Oo ion et a en ee ea Idle Time 
Be : A or B Reg Chk 
| s LSR to A or B 
Op Bit 4 ; ee Phase D o Aor 
Op Bit 5 A ie - Sel LCRand DRR 
: EB Cycle = : te 
C10 | Load S x Sing 
(not) Wait State ) | eayehced 
ae | A not) IH Cycle 
(not) Alter or Display Storage 
Odd Not 9 CD 
Store New Load Q Reg Cl 3 and 4 
2 Address Format 
Op Bit 6 EB Cycle 
3 (not) Significant Digit 
16 + 2P : New Data to Store 
; Not Op Bit 7 not) Edit Instr A 
not) Test on or Off A Store Data Group 
(not) Op Bit 6 KY111 
: | RN131 “a 
s (not) Halfword Format jon Cl 4 CD LAE EL @ | oe a | 
Ke Not Recompl AAR (Hi) AAR (Lo) EA Cycle 
EA Cycle EB Cycl clé_§ 3 AAR Sel CI 5 Thru O 
yeis A KCI32 eB Loli] 2} 3/4/sfo6l7folil2[3][4 15] 6[7| st Tahibir [Sk Select 
jon CIT and 2 | aes 
, : 4 Pe 
(not) Op Bit 4 Cl 3 and 4 | G3 Gi 
Hal fword SE a 
One Address Instr Format KL121 BAR (Hi) BAR (Lo) 6 Cl 5 Thro 0 
polit2}3j4istej7fotij2}3}4]5]6q7| not) Recompl Cycle 


5406 CPU—Operations | | ; 
Move Characters or Compare, Add, or Subtract Logical Characters (Part 2 of 3) | | 5406 FETMM (6/70) 5-082 


5406 CPU—Operations 
Move Characters or Compare, Add, or Subtract Logical Characters (Part 3 of 3) 


3, 
oe 


Machine Cycle 
Clock 

Read Call/Write Call 
Load SAR 

AAR Select 

BAR Select 

LCR/DRR Select 

A Reg Input 

B Reg Input 

Load A and B Reg 
Bin Compl A Reg 
Binary Subtract Gate 
Load ALU 

ALU Output. 

Load LSR 

Store New 

Load Q Reg 

CR Control 


Op End 





1 


| | | EA | _ 


SDR = 7 , , , ms arn 1 





e 
> 
7 
— 
Oo 


Condition Register 





Add 


Subtract 


Compare 


If Result is zero 


If A field equals B field 


If A field equals B field 


If Result not zero and 
a high order carry 


If B field is lower than 
A field 


If B field is lower than 
A field 


If Result not zero and 
no high order carry 


If B field is higher than 
A field 


If B field is higher than 
A field 





Result too large for 
field (no high order carry) 


ALD Reference 
KC122 
KC132 
KC142 
KL121 
KL121- 
KL121 
RAI11 
RA101 
RA101 
KY121 
KY121 
AV132 
AV142 
KL101 
KC132 
KD141 
KGI11 


KD131 


5406 FETMM 


(6/70) 


5-084 





(not) Recompl Cycle 


Inhibit SDR Transfer A 

EB Cycle 

Wait State Single EB Instr 
System Reset jor EB Trigger . 


(not)3 and 4 Gate SDR to B 


Alter SAR or Storage 
| 

























O Block SDR 





KD131 
KG141 


Op Bit 4 
EB Cycle 
Cl 3 and 4 


not) Zone ~- Num Interchange 






Gate LSR Lo Normal to A i 















Main Storage 
KG131 





ALU Blank 


Bin Add or Sub No Move EB ‘ Equal 
Cl 5B | a 





CR Equal 


CR : 
um Loft CR Low 
| Op Bit 4&5 ay ow 


io |, [Bin Add or Sub Not Move FL 
Op Bit 7 First E Cycle Reset CR Lo : High 
| Cl 1 and 2 A oR} g re 
; Edit Instr RGl0l | 
EB Cycle Arith Carry Out 


Cl 1 and 2 
Load CR Instr A Reset CR 
First E Cycle 


KIO oT [213 [47s Te T7 : 





Phase DE 




















EB Cycle KG101 





(not) Wait State 






KY121 


Bin Sub a not) 3C to 5C 
| « Op Bit 4 
f _Bin Add or Sub Group i 
: Op Bit 5 








Q Code 


Sel DRR . (IQ Cycle) 





Bits 01234567 
CLI Op CodeX X111101 ALD 


t D| | | . 
poe ee — Sel BAR EE Machine Cycle (EB) ama a emer Keference 
Cl_5 thru 0 A > BAR (Hi) BAR (Lo) Clock 


KC122 
polil2{3}4}5]6{7jofift2}3}4}5[o6 47) Read Call/Write Call 





KC132 
Load SAR KC142 
< BAR Select KL121 
EB Cycle : DRR Select 


KL121 
(not) Op Bit 4 Cl 3 and 4 ( B Reg Input (SDR) 
A Halfword N A . A Reg Input (DRR) 
One Address Non-Branch . 





RAT11 

RA101 

KY121 
AV132 
AV142 
KGI11 
KG111 
KD131 


RA101 
Format KL121 Load A and B Reg 


Load ALU 
ALU Output (fo CR) 
CR Reset 


CR Set , 
Op End 





16 + 2P 





feces 
si 
ead 
a 
heated 
posed 
eae 
ees 
Pace tl 
ee 
sas 


os ed é 


5406 CPU—Operations te O88 
Compare Logical Immediate | 5406 FETMM (6/70) 5-090 


5406 CPU—Operations 
Move Logical Immediate or Compare Logical Immediate 


Objectives 
bits 0 1 
Move Logical Immediate Op Code X X 


— dO 
— WwW 
—h 
— OQ 
oOo 
OoOnN 


e Store the Q code, which is located in the Data: 
Recall Register, in the location specified by 
the B Address Register 


01 
Compare Logical Immediate Op Code XxX 


e Compare the Q code, which is located in 
the Data Recall Register, with the data 
in the location specified by the B Address 
Register 


e@ Record the result of the comparison 
in the Condition Register 








MOVE LOGICAL IMMEDIATE OR 
COMPARE LOGICAL IMMEDIATE 
Requires 


| single 
| Bcycle 










Clock 0 | Address 


Storage 


KD111 





Activate 
"EB cycle’ 
















logical immedi- 


ate operation RNI13I 





Activate 
‘store data 
group' 





Activate 
‘new data 
to storage’ 





Activate 
‘sel BAR' 





Activate 


"load SAR' 





Clock 1 & 2 Set condition 
register to 


equal for 

















Comparé 
ogical immedi- 
ate operation 


Activate 
‘CR equal’ 


KG101 







5406 FETMM = (6/70) 5-092 





Clock 3 & 4 | Move: Move 
DRR to storage 
Compare: 
Compare DRR Activate 


with storage ‘sel DRR 
and LCR' 


































Load DRR 


Activate 
| into A reg 


"gate LSR lo 
normal to A' 


Activate 
"bin sub 


RN121 


Activate 
‘inhibit 


SDR transfer' 





Yes 
KY121 


Activate 
"bin comp 
A reg' 





Activate 
"gate SDR 
to B' 





KC132 KC132 


Activate "Read Cal \/ 


‘store new' | Write Call' 
| enters data 


at clock 5 






Clock 5 & 6 Set 
condition 
register 





BAR is 
decremented 
from 5 to 8 
time but is 
insignificant 
for this 
operation 







carry out' 


KGI11 


Activate 
‘CR lo! 






Activate 


"CR hi! 





Clock 7 & 8 End 


operation 


KD131 





Turn on 






RN131 iopiend! 
Conditioned trigger 
| by 'bin add 
| or sub not 


move' 


END OF 
OPERATION 








Main Storage 











R Lo Normal To A 





Clock 3 and 4 


not) Zone-Num Interchang 





MVI-Hex YC 





Bits 01234567 


SAR SDR 
Op Code XX111100 





Store New 


A EB Cycle 
= Ech (not) Significant Digit CL4CD 
x Not Edit Instr A. |New Date to Storage A f 


by 


Machine Cycle 






FL 


Clock 

Read Call/Write Call 
Load SAR 

BAR Select 

LCR/DRR Select 

A Reg Input 

Load A Reg 

Bin Compl A Reg 

Bin Sub Gate 

Load ALU 

ALU Output (DRR) 
Store New (NEW Data 
Op End 


KY111 CLE 
KC132 






Bin Sub 


Store Data Group 


Op Bit 6 
(not) Op Bit 7 on | - 


not) Test On or Off A 


not) Op Bit 6 
RN] 31 a cal eles Pera RE ME ear Peg oe rae tte ea ee aoe hn Ce eT eRe Nearer Oia ee, Ree iar 
not) Halfword Format [on Ra EES ne eee 


Sel DRR * ee ee 
1a Cree 


Pe Ee ne eae eee ETE CEE See ReneS Sree eae Teno. 
Sr Sn eat ag SRE Det Per Star RAL RL aaa 


Ea 






| A Reg 





Bin Com 











2G Ges eS ee er ee 
SER eer eee ee ie eee AT ois ena 


pen sa : 


% eo 





not) Recomp Cycle 
EB Cycle 

Cl 5 Thru 0 
not) Inhibit LSR Sel 






KL121 


Op Bit 4 


En Cycle Oe . Bin Add-on SobsGrous ‘ 
16+ 2P Op Bit 5 


CL 3 and 4 A ie 
e KY121 


a not) Op Bit 4 = 
Hal fword . 
B e One Address Non-Branch Format e Odd CD 
KL121 2 
RNI11]1 2 Op Bit 4 
Fe Bin Compl A Reg Op Bit 5 
not) Op Bit 7 


EB 3C to 5C 





5406 CPU—Operations 


Move Logical Immediate 5406 FETMM (6/70) 5-094 


5406 CPU—Operations 


Zero and Add Zoned and Add or Subtract Zoned Decimal (Part 1 of 4) 


1 


Objectives: 


bic OT DS a5e7 
XXXX0100 


|. Zero and Add Zoned Op Code 
e@Decimally add A field data to zeros and place 
results in B field location 


bits 01234567 
XXXX0110 
XXXXO111 


2. Add Zoned Decimal 
Subtract Zoned Decimal 
eDecimally add A field data to B field or 

subtract A field data from B field 
_ elnstruction and signs of fields determine 


Op Code 


add or subtract function 


3. All Operations | 
eLength of A field is numeric portion of Q code + 1 
eB field is longer than A field by amount in 
zone portion of @ code 


ZERO AND ADD ZONED, 
ADD OR SUBTRACT 
ZONED DECIMAL 
























Cycle Gi Diag 5-102 
RN131 
Op Code 
Clock activates 
0 Address A ‘store data 
address group' 
storage 
location 
Yes 
KD121 
Activate * 
"Ist ECycle 
Activate 
"EA Cycle' 
Activate 
‘sel AAR' 
Activate 
"load SAR' 
Clock 
1&2 


Set condition 
register to 


equal on 
first cycle 


KG101 


Activate 


"CR equal’ 














Clock 


3&4 


Clock 


5&6 


Clock 


7&8 





Store A 
field data 
in DRR 


Decrement 


low order 
of AAR 


Decrement 
high order 
of AAR 













Activate 
‘gate SDR 
to B' 






















Activate 
‘sel DRR 
and LCR 





Activate 
‘sign contro!" 





Activate 
'LSR write 
low' 












KL121 
















Activate 
‘sel AAR! 





Activate 
"gate LSR 
lo to B' 





Activate | 
‘misc bit 7 
to A! 


Activate 
‘bin sub 


gate' 





Activate 
"LSR write 
low' 





























Activate 
‘sel AAR' 





Activate 
"gate LSR 
hi to B' 


Activate 
"bin sub 


gate' 





Activate 
"LSR write 
high' 


Bits 0 to 3 of 
Ist byte(1st 

E Cycle) con 
tains sign of 
field. Minus 
is entered 


into DRR as 

1101, plusas 
1111. After 
Ist byte, all 
bytes enter 

with 1111 in 
digits 0 to 3 





Clock 
1&2 






























































B Cycle 4 ‘ - 

y : < Diag 5-102 ee 
Address B oe 
address stor KDI 
location from ree 
BAR during aa ; 
regular B EB cycle 
cycles: ARR 
for recomp 
cycles Activate 

‘new data 
to storage' 
re- 
complement 
Activate Activate 
‘sel BAR' "ARR seld' 
Activate 
"load SAR' 
Decrement 
KG141 
field length 
count. LCR Activate 
during regular "gate LSR 
B cycles:LCRR hi to B' 
during recomp 
ie Yes 
complement KL121 
cycle ain 
Activate LCRR 










"sel PSR’ 


Activate 
‘sel DRR 
and LCR’ 












Ist 
recomplerent 
cycle 
Activate 
"Reset 
CR lo' 
























Activate 
‘misc bit 7 
to A’ 


Activate 
‘misc bit 3 
to A! 


Activate 
"bin sub 
gate' 


AV142 


| ALU 
Output 
i 


Activate 
"LSR write 
high' 





latched 





KG101 









Compute A 


and B field 
data and 


load remair- 


ing field 
length into 
Q reg 





oe 
be 


Diag 5-102 


KL121 


Activate 


‘sel DRR 
and LCR! 









Zero 
and add 


instruction 






EA 
eliminate 
active 


Activate 
‘gate LSR 
lo normal 


to A' 





Add» 

Instruction 
with like 
signs 

















~ Subt, 

Instruction 
with unlike 
signs 


KY121 


Activate 
"dec sub 


Activate 
‘load Q 


reg' 


KCl32, 


Activate 


‘store new’ 











5406 FETMM 



























Re- 
complement 
cycle 


Activate 


"Gate SDR 
to B' 





recomplement 


KY121 


Activate 
‘decimal comp 
B reg' 






KY121 





Activate 
'dec comp 
A reg' 


AV142 








ALU Output 
was latched 


"Read Call/ 
Write Call’ 
enters data 

_at clock 5 


(6/70) 





Activate 
‘misc bit 7 
to A’ 
















Bits 0 to 3 of Ist 
byte (Ist EB cycle) 
contains sign of 
field. Minus is 
entered into sto- 
rage as 1101, 

plus as 1111. B 
field sign is 
entered for result: 
Sign is reversed 
during recomp 

A field sign is 
entered for zero 
and Add operation 


5-100 


a Diag 5-100 


Set CR and 
Clock decrement low 
5&6 order of BAR during 
regular B cycles: 
ARR during 


recomp 


5406 CPU—Operations 
Zero and Add Zoned and Add or 








If computation resulted in 
a carry, ‘digit carry’ is 
activated to give ‘arith carry out' 
at next clock 3 and 4 


















ALU 
numeric output 


blank 





KGI101 


Deactivate 
"CR equal’ 











ALU 
| (not) bit 2 


No Yes 











result 
negative 
























Activate 
"CR hi’ 


Activate 
‘CR lo' 















Last regular 
B cycle or last 
recomp cycle 


register 


blank 






Result is 
minus zero 






‘CR 
equal’ and 
‘CR lo/hi' latch 


; KY121 
active 


Yes 





Zero and 
add inst; 
add inst 
with like 
signs, sub 
inst with 
unlike 
signs 










recomp 





eysle arith 


carry to 


bit 3 


— ——— oe 


Activate 
"recompl 
gate' 


oS | At N6te Te Nie output pin latch 


Subtract Zoned Decimal (Part 2 of 4) 





KY13} 


Clock 
7&8 





Decrement 
high order of 
BAR for regular 
B cycles: ARR 


for recomp 
cycles. 












re- 
complement 
cycle 


Activate 
‘sel BAR' 





Activate 
"gate LSR 
lo to B' 





KG141 


Activate 
‘misc bit 7 
to A' 





KY121 


Activate 
'bin sub 


gate’ 

















Q 
register 
numeric portion 


blank 


recomp 
cycle 


Activate 
"LSR write 


low 





recomp 
cycle 


Activate 
"sel BAR' 


KG141 


RN101 


Yes 


KL101 


Yes 






KL141 





Activate 
"ARR seld' 











Activate 'EA 
eliminate' 












Activate 
"ARR seld’ 





KL141 


Note 2: 


Activate KG141 
"gate LSR 
hi to B' 


Activate KY121 
"bin sub 


gate’ 















Q 
register 


blank 


Yes 


KD131] 


trigger 







Activate KL101 
"LSR write 


high' 





‘Op 
end trigger 







~ KGI21 


"recompl 
gate' 
active 







Yes 


End of 
Operation 


KDI111 
Activate 
'recompl 
cycle' 












Clock 0 






No 


KG1 21. 


Deactivate 
'recompl 
gate’ 








‘FA Diag 5-100 


eliminate' 
active 


Diag 5-100 


Operation repeats A and B cycles until end of A field (Q register 
numeric portion blank). ‘EA eliminate’ then allows B cycles 
until end of B field (Q register blank). Operation ends unless 
result is in complement form. To recomplement, the low order 
of the B field is established by the ARR and the length of the 
field is established by the LCRR. 'EA eliminate’ then allows B 
cycles until end of field (Q register blank). Operation ends. 


5406 FETMM (6/70) 5-102 


5406 CPU—Operations : 5406 FETMM = _ (6/70) 5-104 
Zero and Add Zoned and Add or Subtract Zoned Decimal (Part 3 of 4) 


1 





2 Vv 3 


Recompl Cycle 


A Reg Bit 2 
SDR Sign Minus 


















Ist E Cycle 


A C 5 


2 Addr Format 
Dec Instruction 


Ht Op Bit 6 


Op Bit 7 


EA Eliminate 
ol Gate §& 












not) Op Bit 4 


Cl 5 and 6 ; 
7 A |GateLsRlotoB gw 
Op Bit 5 ay 


(not) Op Bit 4 jon x Gate LSR Hi to B 
On. A Inhibit SDR Transfer Cl 7 and 8 . 28 
p Bits (not) 6 and (not) 7 EB Cycle 


Cl 1 and 2 jor 
A 
EB Cycle pA 


a 
9 






not) Recompl Cycle 
Wait State 













m% Q Reg Blank 
2 Address Instr 







System Reset 











(not) Cl 3 and 4 
Alter SAR or Storage 
I/O Block SDR 


A 


Store New 
EB Cycle 
Not Edit Insir 
not) Significant Digit 















Cl 4CD 
A New_ Data to Store 





(not) Q Num Blank 


KYT11 Clé Dec Instr 


EA Eliminate 






Store Data Group 














Pal 
EE 





























Drees Op Bit 6 . Recompl Cycle EB Not Ist Cycle 
pee 7 | ai : | 2 Address Format 
Cl 0 eS not) Op Bit 7 | Mm Cl 3C to SC Bin Sub Gate ee eres A [ICTT and 2 
(not) Wait Stat ; N Recompl Cycle 
no ait State Pulse a hl (not) Test On or Off TCE Cocke 

KC142 - (not) Op Bit 6 ; KY121 acancer Cl 5 and 6 Cl 3 and 4 


Not IR Prog Backup 
not) CE Test No Increment 


(not) I/O Cycle Not Test 


not) Wait State 


KG141} A 





f [Test False} Dec Ovfl|Bin Ovél 


(not) System Reset 





Cl 1 and 2 : = 3 






: steen eres . ass EB Cycle 
: 2 e are 
1642P Recompl Cycle : 7 "PSR x (LCRR) es Dec Instr 
a ‘(Esra . — 
, KL121 : "ES Q Reg Blank 
8 a] oe ; OR KeEcCOmMp cre 
Channel Inhibit LSR Load ae Cl 8 ce ALSR Write Hi , a AAR (Hi) AAR (Lo) KG121 9 Address Format 














Load Q Reg 


Idle Time | ‘ 
A or B Reg Chk 
LSRto Aor B Phase D 


B és eh 


not) EB Cycle 
(not) IH Cycle 
(not) Alter or Display Storage 


EA Cycle (not) Dec Compl A Reg 


A Arith Carry to 3 
7 Clock 5 thru 0 Cl 5B 
AAR Sel & 
2 (not) Inhibit LSR Sel Cl 7 and 8 
‘ A {CR Low 
: CR Equal 
BAR Sel . = 







co 


LSR Write Lo f 


BAR (Hi) BAR (Lo) 
POP ITZ SP 4tsfet 7 opi 2}; 3y4i5 [6 7) 







(not) Recompl Cycle 












Recompl Cycle 


Cl 1 and 2 


KL101 LCR PRR KL121 G EB Cycle 
Ott 2;3} 4f5(6[7[o][i[2[3]4 [5 [6]7] Clock 5 thru 0 
16+2?) =e = | (not) Recompl 






Cl 5 thru 0 Dac gre eecerererencar reer eersereere tillers tumemeen rs 
(not) inhibit LSR Sel__| A | 


Sel DRR and LCR (not) Op Bit 4 
Halfword Format 
rOLiT 2; 3; 4st oet7fotit2i3i4t5 [6] 7] bs Cl 3 and 4 A [One Address Instr 


EA Cycle 
mama | jor EB Cycle 


KL141 





ALD References 


Cycle en ae 


Clock KC122 


KC142 
KC132 
KL121 


Load SAR 

Read Call/Write Call 
AAR Select 

BAR Select 

LCR/DRR Select 

LSR Load 

Load A and B Reg 





i neck 






KL1 21 
KL121 
KL101 
RA101 
AV132 
AV142 
RA111 
RA101 
KY121 


KYI21 [Operation | Equal | Low | High | Decimal Ov 


KY121 Zero and Result | Result | Result 


Add Zoned is is is 
KY101 Zero | Minus Plus 


Add or Sub Result | Result } Result | Result is too 


Load ALU 
ALU Output 


A Reg Input 








B Reg Input Condition Register 
Binary Sub Gate 
Decimal Sub Gate 
-Dec Compl A Reg 
Sign Control 
Store New Bee 


CR Control 
Load Q Reg 


Zoned is is is large for field 
KGI11 Zero | Minus | Plus 


KD141 
KG121 
KY111 
KD131 





Recomp! Gate 


Hs er pet 
shot fae ees 
ee og — Ee 
ead : 
ae ad th 
Pe 
gl 
a 
Sos 


sye 


EA Eliminate 


Op End 


an Be 
Boe, aes 
o we 
ey 2 x 


bi 
a 
a 








Recomplement Ist EB 





Cycle 





KC122 
KC142 
KC132 
KL141 
KL121 


Clock 
Load SAR 


Read Call/Write Call 
ARR Select 

Sel PSR 

LCR/DRR Select 

LSR Load 





y 
om 


KL12] 
KL101 





Pa oad 
eae ea te 
ss Pi he 


3, 
ou 
: g 
: He ce 





RA101 


AV132 
AV142 


RAT11 
RA101 


Load A and B Reg 





Load ALU 
ALU Output 
A Reg Input 


es 
33 
Fie rm 
38 es poe 
Las es Sy 
a hes 4 
a a Bs 
Pe 
we 
cee 





© [owe Bry Forces) TP 
Bs eee a a a a Ts a 
seipeiceae Wh We es oe comers ee ai eth coe es ale eee Se KYI21 
Dec Compl AReg |_| S| pf a fff KY121 
Sign Control pT et ed KIO 
en Gaaes pesergeesec ieee sp sag ind ee nel | : KGI 
Load @ Reg ae, aes ee Lo KDIAI 
ee Nr a 
Ist Cycle a a KDI 
Op End | po oy et tr = 09 KDI3I 


5406 CPU—Operations 
Zero and Add Zoned and Add or Subtract Zoned Decimal (Part 4 of 4) 5406 FETMM — (6/70) 5-106 


B Reg Input 











5406 CPU—Operations 
Edit (Part 1 of 3) 


Objectives: 

bitt01234567 
Edit Op Code XXXX1010 
eReplace hex 2/0 in B field with A field data 
eSkip other characters in B field leaving them 

as they were 

@Length of B field is Q code + 1 
eA field sign stored in condition register 


EXAMPLE: 
: Q code = 9 


. . Caos 
B field before edit X,XXX.XX€ 
A field 09071 5>— blank 


B field after edit 0,907.15”* 
X=Replaceable Character (2/0) 


EDIT 
A cycle @ 











































Clock 0 [Address A 
address 
storage 
location 
Activate RN131 
‘store data 
group' 
Activate 
"Ist E 
cycle’ 
Activate KD121 
"EA cycle' 
Activate KL121 
"sel AAR' 
Activate KC142 
‘load SAR! . 
B 
Clock Set CR to 
182 equal on 
Ist cycle 
Yes 


Activate 
"CR equal! 










KD121 


KG101 


Clock 3 & 4 


Clock 5 & 6 


Clock 7 & 8] Decrement 
high order 


field data in 


Decrement 
low order of 
AAR. Set 'CR 
lo! latch in 
Ist cycle if 
minus field 


of AAR 























Activate KG141 
"gate SDR to 

B' 

Activate KL121 
‘sel DRR 

and LCR' 

Activate KY101 





3 of Ist byte. Sign 
is entered as plus 
regardless of how it 
came out of storage. 


"sign control’ 






Plus is 1111 in bits 
0 to 3 





Activate 
‘LSR write 
low' 
















at clock 3CD 












reg. sign 
minus 







Turn on 'CR 
lo' latch 






Until 'CR 
equal" is 
deactivated 
it takes 
preference 
over 'CR lo’ 
or 'CR hi' 



















Activate KL121 


‘sel AAR' 






KG141 - 





Activate 
"gate LSR 
lo to B' 










Activate KG141 
‘misc bit 


7 to A' 







Activate KY12] 


‘bin sub 
gate’ 








KL101 





Activate 
"LSR write 
low! 












Activate KL121 
‘sel AAR' 




























Z 
Activate KGI 4] Activate 
"gate LSR "gate SDR 
hi to B' to B! 
Activate KY121 Activate 
‘bin sub 'and' and 
gate' 
AV211 

Activate KLI101 ALU output Activate 

B cycle 'LSR write was latched | ‘load Q 
high' at 2-CD l 

Clock 0 io 








Address B 

























‘sel BAR' 







KCl42, Clock 58 6 & 


Decrement 


low order of 
BAR. Set CR 





Activate 
"load SAR' 















Clock 1 & 2 
Decrement 







ALU 


















Activate 
"gate LSR 
hi to B' 


LCR 







Activate 
‘CR lo' 






Activate 
‘misc bit 


7 to A' 


KGI41° 



















Activate KY121 register 

‘hin sub contain 

gate' 2/0 

Yes 
Activate KL101 
"LSR write 
, nian: Acti KLI21 
Clock 3&4 § ae 

Store A field 
data in B field hetivate KL121 
position if B "sel DRR KG141 
field position and LCR" Activate 
contains "gate LSR 
replaceable KGI31_ lo to B' 





character (Hex 
2/0). Load re- 
maining length 
count into Q 


Activate 


‘gate LSR lo DRR KG141 


Activate 
‘misc bit 7 


normal to A' 





to A’ 


reg 


















register 


address Activate KDI11 contain 
storage 'EB 2/0 
location cycle! 

Activate KL121 





LCR each Activate KL121 : MOS aac 
cycle except ‘sel DRR — blank 
Ist c cle and LCR’ 





Activate 
"EA eliminate 


KGI41 _ 


RN121 


KD141 







No 












Activate 
‘new data 
to storage’ 


Activate 
‘store new' 


Deactivate 
"CR equal’ 


lo’ latch 


on 


Activate 
‘CR hi' 


5406 FETMM — (6/70) 5-110 












3 
Activate KY121 
"bin sub 
gate' 
Activate KL101 
ee 'LSR write 
7 low! 
Clock 7 & 8 
Decrement 
high order of Ketiate KLI 21 
BAR and eel BAR" 
check for blank ae 
Q reg 
KY111 


x Activate KG141 
NOTE 2 "gate LSR 
hi to B' 


Activate 
"bin sub gate’ 

















KY121 










RN111 





Q 
register 


blank 


No 


Turn on 
"Op end' 
trigger 


KGI101 







N 1 Activate KL101 
ote 'LSR write 


























eliminate 
active 


KY111 


END OF 
OPERATION 
Note 1: No output pin from latch. 


Note 2: After B cycle, if B field character was 

not a Hex 2/0, 'EA elminate' causes another B cycle. 
When B field Hex 2/0 is found, machine 

takes another A cycle to read out next character 

to be stored. When end of field is reached 

(Q register blank) operation ends 





EA 


Edit Instr 


EB Cycle 


not) Recompl Cycle 
Inhibit SDR Transfer 


Wait State 








System Reset 


See a ees toa ee rae ee Tk Be od Cpt Teo 


oe 


1/O Block SDR 
EB Cycle 


A 
Cl 1 and 2 


Cl 7 and 8 





CI 3 and 4 Time 
Gate SDR to B 
Alter SAR or Storage 


Gate LSR Hi to B 





‘KDI31 









Wait State 


System Reset jon. 


Force Bit 7 to A 
Gate LSR Lo to B 















Cl 5 and 6 
SDR 
Store New 
EB Cycle 

t) Significant Digit oe 

(not) Significant Digi A New Data To St | 
» Cl 4CD Ey a 

Phase DE is Cn | 

" s X < | | Cl 3 C Thru 5C 
not) Wait State ; i 
KC132 


Store Data Group 


RN131 


Op Bit 6 














(not) Op Bit 7 
not) Test On or O 
not) Op Bit 6 


LSR Write 
Sel LCR and DRR 


| 


LCR 


olif2{3}4]s5lei7jolij2i{3}4[sleqt7 





.? 






(not) Halfword Format 





Edit Instr 


: 


A 


Bit 4 
Bit 5 


B Reg 
B Reg 
B Reg Bit 6 
B Reg Bit 7 


(not) B Reg Bit 0 
not) B Reg Bit 1 
B Reg Bit 2 

(not) B Reg Bit 3 






















opr i 243i 4isiot7{olif2}3i4{5]6q7 


® 





(not) Recompl 
EB Cycle 
Cl_1 and 2 


EA Cycle 


Cl 3 and 4 


KL121 


EB Cycle 
(not) Op Bit 4 





Halfword Format BAR (Hi) BAR (Lo) 


One Address Instr 


Ot ry 2t 3s] 4ysp et 7 polit 2st 4 ys [6 [7 














ME 16 + 2P 


5406 CPU—Operations. 
Edit (Part 2 of 3) 












Op Bit 4 


EB Cycle 


Cl 3 and 4 


Gate LSR Low Nermal to A 


(not) Zone - Num Interchange 


EA Eliminate 


Dec Instr 
A 
aS Cl. 1 and 2 


Cl 5 and 6 


(not) IR Prog Back Up 


(not) Recompl Cycle 


A (not) Q Num Blank 


EB Not Ist Cycle 


2 Address Format 





(not) I/O Cycle Not Test 


(not) CE Test No Incre 


A 
(not) Wait State 





(not) System Reset 











(not) Op Bit 0 
(not) Op Bit 1 
(not) Op Bit 2 
(not) Op Bit 3 





EB 3C to 5C A 








RN121 Op Bit 4 (not) 5 





Cl 2 


Channel Inhibit LSR Load 












Cl 8 
jon : 1/O Not CE Test 
A Idle Time 
>—N 
A or B Reg Chk 
A LSRto AorB 
| Phase D 
a Clé 
KL101 Cl 4 
(not) EB Cycle 
: A not) IH Cycle 
(not) Alter or Display Storage 





EB Cycle 
Cl 3 and 4 
2 Address Format 
(not) Single EB Cycle Instr 


















Load Q Reg 
Odd Not 9 CD 


EA Cycle 
A 
0 
AAR Sel SNe 
A (not) Inhibit LSR Sel 
KLi2.— 
BAR Sel ~ 
EB Cycle 
A Cl 5 Thru 0 
Bere (not) Recompl Cycle 
5406 FETMM -s._ (2/71) 5-112 


5406 FETMM 


5406 CPU—Operations (6/70) 5-114 


Edit (Part 3 of 3) 








Ist EA Ist EB 

















ALD Reference 


Cycle Ley | i 
Clock Sarto inh Tad sean pel eee eee Gena “Re 
Read Call/Write Call Ens. 2 eam Rie eee ie es KC132 
BAR Select ho a Soe eee ee KL121 
LCR/DRR Select Pee al oe RE 
Load LSR Ps | | bak tog aa id KLIO 
lood And BReg = |_| emt 
ice ae Sees name a ace 
A Reg Input fe ale ke ae RA111 
B Reg Input a ae a) SOR) ce RA101 
‘ ae eRewae = | 
inary Sub Gate aS ETE KY121 
ALU Control (And/Or) tt dt oll , = KY101 
CR Control Pe ee A es ee ll ee ee ee Pe ele eS hem 
Lood @ Reg tse a lt Se ee gt oe 
EA Eliminate ee i ee ee ee a i 
sareiNiaw Re ce tle ell a wen el ee We ee ee ere 
Op End De eee lee wl le ee ee i i Se 
Footie orl ces crnove ton Laeadtaed pose mec arke wake ore seco 
el ea a Le ae ere a 
Cycle | EB jaa 2 Last EB = | | . Data Recall Register 
Read Call/Write Call ee re age engeetnennnane eke eee ee ge KC132 
canoe tet Si2) Replaceable Cart 
Load A and B Reg ee ee ee RAIOI ie et es 
Load ALU ie i ll AvI32 B Field after edit 0,907.15 § 
ALU Output eT! a. AID blank 
A Reg Input a Se a Fa ee ee ee ee ee a apie hietengrecan oatae Meee oe 
es TL SB hc BAR DS BAR a BART) aA101 odd CD clock time, the figures shown apply anly to clock 
Binary Sub Gate ees | | ee | eae KY121 3 and 4 time when the main storage data is being analyzed. 
ALU Control (And/Or) te | | KIO 
CR Control a Keil 
Load @ Reg a RR | (A ee (a Te | ee ee ee ee ee ee ee ee 
EA Eliminate nnn | tT ||| 
Store New et eet | 82 
Op End po et 0132 
De ee 
alee a le a ce el 





< 
w 






ALD Reference 












Machine Cycle PE ee ee gee PE RTOS 
Clock bea ie oath ape ete ee eee age | | melee 
Read Call/Write Call Rie cos ee ld a KC132 aes | | a 
AAR Select mes S| sd KL121 4; a ee oe 
KLI 
LCR Select Ee a i eases 
ARR Select Re ele sees de at momo | to LCR unchanged, 
Load A and B Reg Re ee lee Ese ar C4 RA101 also to Q Register 
B Reg Input a ee Boos Pee ee a) B ti 
ALU Output Ee oe east ee Avia2 ($*01..98) 
MU Control (Anefoy [|__| | | KYI01 
sinew SubGuré 3 a KY121 ® Increment BAR 
Bin Compl A Reg PT KYI2 
oad LS Pail cee an > oe 
Significant Digit (1-9) Me ee KDI31 LCR and Q Register 
Load @ Reg Ree ee ee KDIAI . 
Store New eee 2 Wee ee ol ee lel cere © B a 
EA Eliminate oe Ue ee oa one ($**1 98) 
Machine Cyel Decrement length 
Pa. 83S Aaa Korn Shae ee 
Load SAR KC142 | 
seed Cauca — eee 
AAR Select ere significant digit 
BAR Select ee ($**1 .98) 
DRR Select KLI21 (0 Increment BAR 
LCR Select 
ARR Select KL121 
Load A and B Reg RA101 
A Reg Input RA111 
B Reg ‘Input RA101 
ALU Output AVI42 
B ALU Control (And/Or) KYI101 
Binary Sub Gate KY121 
Bin Compl A Reg KY121 
Load LSR KL101 
Significant Digit KD131 
Load Q Reg KD141 
Store New KC132 
EA Eliminate KY111 
KD132 


Op End 


% ene 


5406 CPU—Operations 
Insert and Test Characters (Part 1 of 3) | 5406 FETMM (6/70) 5-120 


5406 CPU—Operations 
Insert and Test Characters (Part 2 of 3) 


Objectives: 


Insert and 


@ Replace 
digit in 


bits 0 1 
Op Code XX 


x ND 


Test Character 


all characters to left of first significant 
B field with A field character 


@ Only numeric characters 1 to 9 are considered 
significant digits 


e@ Length of B field is Q code +1 


e A field is only 1 character in length 


EXAMPLE: 


Edited field before operation 0,907.15 < 


A field character * 
Edited field after operation £*907 15 


B field starting dddregs.___—_-- 


INSERT AND TEST 
CHARACTERS 


A cycle 
Clock 0 


Clock 3 & 4 















Address 
A address 


storage 
location 








Activate 
‘store data 
group" 











Activate 
"Ist E cycle' 
trigger 











Activate 
"EA cycle’ 










Activate 
"sel AAR' 





Activate 
"load SAR' 





Store A 
field char- 
acter in DRR 


Activate 
"gate SDR 
to B! 


ae blank 


RN131 


KD121 


KD121 


KL121 


KC142 


KG141 


Clock 1 & 2 





Activate KL121 
‘sel DRR 


and LCR' 


AAR is 


decremented 










KLI101 from 5 to 8 
Activate time but is 
aD 'LSR write insignificant 
low' for this 






B Cycle operation 
Clock 0 Address (7) 
B address 
storage 






location 










Activate KD111 


"EB cycle 






KL121 






Activate 
"sel BAR 





Activate KC142 


"load SAR' 







Decrement 
LCR each 

cycle except 
Ist cycle 











Activate KL121 
‘sel DRR 


and LCR' 











Activate KG141 
"gate LSR 


hi to B' 






KG141 
Activate 
‘misc bit 7 
to A' 





KY121 





Activate 
"bin sub 
gate' 








KLI01 





Activate 
"LSR write 
high' 











Store A field 
character if B 
field charac- 
ter is not sig- 
nificant. 
Load remain- 
ing length 
count into Q 










Clock 3 & 4 


KL121 





Activate 
‘sel DRR 
and LCR' 




















Increment 
low order of 
BAR. Put ad- 
dress in ARR 
unless B field 
character 
was signifi- 
cant digit 














Activate 
"gate LSR lo DRR 
normal to A! 





Activate 
"gate SDR 
to B' 





Activate RN121 


" and'and 
1 




































Acitvate ALU output | AV142 
‘load Q was latched 
at 2 cd 
register 
significant 
Activate KY111 
‘new data 
to storage’ 
Activate 
‘significance’ 
Activate KC132 


‘store new' 






Activate 
"significant 
digit' 


Activate KY111 
"EA 


eliminate’ 





Activate KL121 
‘sel BAR! 





Activate KG141 
"gate LSR 
lo to B' 





Activate KG141 
‘misc bit 
7 to A' 


Activate KY121 
‘bin sub 


gate' 


Activate KY1 21 
"bin comp 
A reg' 





Clock 7&8 


Increment 
high order of 
BAR. Check 
for significant 
digit or blank 
Q reg 













B cycles are 
repeated until 
either a signi- 
ficant digit is 
found or the 
Q register is 
blank(end of 
field). Oper- 


ation ends 















































5406 FETMM =. (2/71) 5-122 
Signi- 
ficant digit No 

active 
Activate KL14] 
"ARR seld' 

Activate KL101 

'LSR write 

low! 

Activate KL121 

"sel BAR' 

Activate KG141 

"gate LSR 

hi to B' 

Activate |  KYI21 

"bin sub 

gate' 

Activate KY121 

‘bin comp 

A reg' 

Signi- 

ficant digit No 

active 
Activate KL141 
"ARR seld! 

RNI111 





Q 
register 
blank 


Turn on 
"Op end' 
trigger 


No 


Activate KL101 
"LSR write 







trigger 
on 


Yes 


END OF 
OPERATION 


1 Vv 2 Vv 3 











































B Reg Bit 4 ; Lr 
B Reg Bit 5 apo. 4 uy Op End 
: Significant Cl 8 i 
Op Bit 6 a BI eae A 
“a } PRs Bit EB Cycle oe | ee 
+) Op Bi not) Edit Instr Significance Cl4_|Ak ae : 
not) Test On or Off [Store Data Group ow ara te AR FL . B Reg Bit | "i 2 Address Format A Op Bit 4 i 
ot) Oo Bit Storage ‘ (not) B Reg Bit 5} A B Rea Bir? (not) Recompl Gate SP. . KD131 
% & ; A a % Q Reg Blank 
@a_ (not) Halfword Format RNI3I KYTH Clé _ (not) B Reg Bit 4 jon pikeg Bit 8 KD131 
er a cee Store New Se: 4, bes 
y Also KOIn 2 Address Format ff Ik EA ie 
y + ope ee a i ; imi vi 
1 (not) Significant Digit n Gate LSR Lo To B peas BTS EC Instr EB Cl 5 and 6 ole Gate LSR Low Normal to B 
oe A Bir 6 A 2 [AF FF (not) Zone Num Interchange 
(not) Wait State Op Bit 7 : KGI131 
(not) System Reset : 
a (not) Recompl Cycle 
A 
A | aidan «| Cl 1 and 2 Jot Q Num Blank 
Main Storage . , Dec Instr 
EB l 
Cycle | EA Eliminate 
a one ee r ree EB Not Ist Cycle 
A 
: 2 Address Format 
SAR it7 toA ag 1 and 2 
SDR Cl 5 and 6 
A {tnot) IR Prog Backup 


not) CE Test No Increment 


(not) I/O Cycle Not Test 


not) Wait State 


A 





KG141 






Bin Compl 











(not) System Reset 

















I/O Block SDR 
: Alter SAR or Storage 
not) Cl 3 and 4 Gate SDR ToB 





not) Single EB Cycle Instr 
2 Address Format 
EB Cycle 

Cl 3 and 4 





Wait State 


System Reset cS KG14] 





Cl 3C Thru 5C_[~ |Bin Sub Gate 





KY121 Odd Not 9 CD 





EF _EB Cycle 
fi (not) Recompl Cycle 
fi Inhibit SDR Transfe 






FC Instr “ Load Q Reg 
a [CLS thw 0 : 
EB Cycle e 


Op Bit 4 not 5 






















16+ 2P Se Fi ~ Q Reg Blank 0 Ba g | Boye iees 
I/O Not CE Test EB Cycle - LSRBaWrite | i at (not) Op Bit 0 
“ z not) Op Bit 
hannel Inhibit LSR ad 8 C18 4 (not) Op Bit 1 
Idle Time i A not) Op Bit 2 
N --< (not) Op Bit 3 
A or B Reg Chk RS SE ONE : : 
A Sel DRR : 
LSR to A or B Phase D 4 ON ee ee eet ee ee ee ne See eet aoe eet eae PE a And LCR : 
Cl 6 AAR (Hi) AAR (Lo) s 6 
7 


POL ip 2y3i 4 ise 7jotit2] 3i4]5 i617) 


not) EB Cycle 


_&€ not) IH Cycle 
B a not) Alter or Display Storage 


















ERENCES EU SRE SEES ole HERES SSRIS SI Re SNF SRN SSS 


BAR ie) BAR ih 


eli tataptelet a oli tats 4} Terr] 












a | not) Op Bit 4 
sf 5 Halfword Format ee 
Cl 3 and 4 One Address Instr 
Le Cl 1 and 2 | EA Cycle 
KL121 
not) Recompl EB Cycle 
EBC cle 
EA I 
(not) Inhibit LSR Sel Cycle 


oie ’ EB C cle aa Bee as eta tee ea ere een ereeae. Pee eae Le ae a ee . 
ec Cl 6 and 8 > Cl 5 Thru 0 


FC Instruction A 
gf Significant Digit aa Obilzlslélelél7ioli lz 1314151617 AAR Sel 


BAR Sel 
EB Cycle 


A Cl 5 Thru 0 
KLI21 | (not) Recompl Cycle 
5406 CPU—Operations 


I t 
nsert and Test Characters (Part 3 of 3) | | | : 5406 FETMM = _ (2/71) 5-124 













not) Inhibit LSR Sel 






5406 CPU—Operations 
Branch On Condition, Jump On Condition, and Start I/O 


1 


Branch on Condition 


Bits 0 
] 


1234567 
Op Code 1XX0000 
@ Condition register is tested for condition 
specified in Q code 


e Branch to address is placed in ARR 
@ Bit 0 of Q code is used to specify if the 
branch is performed on condition true or 
condition false 
@ IAR/ARR interchange if tested condition is satisfied 


@ Take I-H and I-L or I-X cycle 


A SEE DIAGRAM 5-030 (I-H, I=L) 
5-042 (I-X) 


BRANCH ON 
CONDITION 










l-Op 
Cycle 
Diagram 5-010 


I-Q 
Cycle 
Lo Diagram 5-010 











Instruction Indexed 


Format 















I-H, I-L 
Cycles 
Diagram 5-030 


1-X 
Cycle 
Diagram 5-042 









Branch 
condition 
satisfied 












IAR/ARR 
interchange 
Diagram 5-030 






END 


Tested during I-Q cycle. 
Activates Br-Jump true FL 
(Diagram 4-073) 

KD151 





2 
Jump On Condition 
Bits 01234567 
Op Code 1111001 0 


e Condition register is tested for condition 
specified in Q code 


e If tested condition is satisfied, control 
code is added to IAR for next sequential instruction 


e Q code bit 0 is used to specify if jump 
is performed on condition true or 
condition false 


e Take I-R cycle 


SEE DIAGRAM 5-020 


JUMP ON CONDITION 






l-Op 
Cycle 
Diagram 5-010 


I-Q 
Cycle 
Diagram 5-010 










I-R 
Cycle 
Diagram 5-020 











(Diagram 4-073) 
KD151 


Jump Yes | Tested during I-Q cycle. 
condition | Activates Br-Jump true FL 
satisfied | 
| 





Add control 
code to IAR 
Diagram 5-020 






END 





5406 FETMM_— (6/70) 5-130 


5-140 
5-150 
3 
Start I/O 
Bits 01234567 
Op Code 11110011 
Be ee re ie Oe ge Be ee Oe ee eee ee ™ 
| @ Start I/O device or enable/disable Not used ! 
{| dual programming feature on 5406. 


e@ Q code contains device address and 
function to be performed (read, punch, etc ) 


e Control code contains additional instruction 
for device 


e 1/0 device busy causes; (1) program to 
loop on SIO instruction_if dual_programming 
is not installed,] or (2) program level ad- 


Peed 


@ Take I-R Cycle 


SEE DIAGRAM 5-020 


START I/O 


l-Op 
Cycle 
Diagram 5-010 


I-Q 
Cycle 
Diagram 5-010 











Tested during I-Q cycle 
cl 8. Activates 'program 
interlock' (Diagram 


4-030) KD131 


I-R 
Cycle 
Diagram 5-020 














Dual 
program feature 
enabled 


rc 
| 
| 
| 
| 
| Yes 
| 
| 
| 
| 
| 
| 


No 


PROGRAM 
LEVEL ADVANCE 


Not used on 5406. 


END 


cae 70 ea ae Sel 


5406 CPU—Operations 
Load I/O (Part 1 of 2) 


LOAD I/O 


Clock 0 - © 















Address 
Storage 





Activate 
"Sel BAR' 





Activate 
‘Load SAR' 


Clock 3and4 §& 

Load storage 
data into regis- 
ter selected by 
the attachment 






















Clock 5 and 6 


Decrement 


low order 
of BAR 





Activate 
"Sel BAR' 





Activate 
'Gate LSR 





Activate 
"Misc Bit 7 


Activate ‘Bin 




















Clock 7 and 8 


Decrement 
high order 
of BAR 








Activate 
‘Se! BAR' 





Activate 
"Gate LSR, 


Activate ‘Bin 


Sub Gate' 





Activate 
'LSR Write 
Hi! 





5406 FETMM (6/70) 





Sub Gate' 






KG141 







Data available 
Activate 'Gate lio 1/0 
SDR to B' | register 


Activate 'LSR 
lon DBO 


Write Low' 

















LSR 
selected by 
/O 


ALD 
Ist EB EB Reference 





Cycle 


Clock 
Read Call/Write Call 


Load SAR 










Activate 'LSR 
Write Hi' 


Activate 'LSR 
Write Low' 





BAR Select 


CO Be 
“ 
ys 


LSR Select 


a G 


orce bit 7 


A Reg Input 
B Reg Input 


Load A and B Reg 


Bin Sub Gate 
Load ALU 
ALU Output 
Load LSR 
Store New 
First E Cycle 


a EA Eliminate 
Op End 


- es 
: nae cee 
t : 





the nL 
reer eae Renee e 


(not) Op Bit 6 and (not) 7 


A 

Op Bit 5 se 

not) Op Bit 4 or Inhibit SDR Transfer 
EB Cycle A 
not) Recomp! Cycle 


(not) Cl 3 and 4. K D131 | 


Wait State . 
N 
System Rese! jor N Gate SDR to B 


Alter SAR or Storage KGIAl “nm 
: I/O Block SDR 
Main Storage 


Ea 
A 
e SAR SDR . 
Cl 7 and 8 
Gate LSR Hi to B 


















Force Bit 7 to A 


Wait 
System Reset. jor 


Cl 5 and 6 


C10 3 2 — KGI4AI 
Phase DE A Load x 
(not) Wait SAR 


KC142 


Gate LSR Lo to B 









sat Cl 8 — e5 i 
Channel Inhibit LSR Load ; Phase D : :  OLSR Write Hi : iN & 
1/O Not CE Test if é N 


Idle Time LSR or register in 
A_or B Reg Chk 


/O attachment is 
A : 
LSR to A or B f_LSR Write Lo 


selected by that attachment 


KLIOl & a : 
5 BAR (Hi) BAR (Lo) ae 


PONE A TS Les oe Oa NY eos as eee 


EB Cycle 
not) Recompl 


CI 5 through 0 










Sel BAR 


Cycle 


KL121 





5406 CPU—Operations 


Load I/O (Part 2 of 2) 5406 FETMM (6/70) 


5-162 


5406 CPU—Operations 
Sense I/O (Part 1 of 2) 


SENSE 1/O 





























































Enter result in 
SDR and 
into storage 








Activate 
'Store Data 
Group' 





Activate 
'Nlew Data to 
Storage’ 





Activate 
‘Store New' 








































Clock 0 
Clock 5 and 6 
ae Decrement 
torage low order 
of BAR 
KL121 
Activate 
‘Sel BAR' 
Activate 
‘Load SAR" Activate 
"Gate LSR Lo 
to B' 
Clock 3 and 4 ate i 
Ay Add A register \/Odavies 
contents to | 
blanien selects 
. attachment Activate 
registey register or "Misc bit 
| LSR in CPU 7 to A’ 
Yes 
Activate 
"Bin Sub 
KG13]) KG131 
: Activate 
oe ‘Gate LSR 
Hi to A! Lo Normal Activate 'LSR 
to A' Write Low' 
> Activate "Bin 
Sub Gate’ and 
"Bin Comp A 
Reg' 
Cycle 
Clock 4 
Clock 


Read Call/Write Call 
Load SAR 


BAR Select 


LSR Select (I/O attachment) 


A Reg Input 

B Reg Input 
Load A and B Reg 
Bin Comp A Reg 
Bin Sub Gate 
Load ALU 

ALU Output 
Store New 

Load LSR 

First E Cycle 
EA Eliminate 


Op End 


Clock 7 and 8 











Decrement 
high order 


of BAR KL121 



















Activate 
'Sel BAR' 





Activate 
"Gate LSR 
Hi to B' 


Activate "Bin 
Sub Gate' 


Activate 'LSR 
Write Hi' 








Sense I/O 


Bits 0 
Op Code 0 


on 
ON 


6 7 
00 


o~— 
x<rN 
x Ww 


Objective: 


e Move two bytes from register selected by 
|/O attachment to storage 









5406 FETMM (6/70) 5-170 
3 
ALD 
EB Reference 
















KC142 
aoe ieee oe Sead RAI1] 
ae m RAI01 





1 v 2 4 | 3 


Op Bit 6 


E-B Cycle 
not) Op Bit 7 = ston! ean eight New Data to Storage. 
not) Edit Instr A Cl4 CD A | 
not) Test Off or On A Store Data Group ; 
not) Op Bit 6 


KY111 ; 
not) Op Bit 4 jon : 
Hal fword Format KC132 


One Address Non Branch RN131 


FL 





RN111 
Store New 












Cl_7 and 8 
Wait Gate LSR Hi to B 
System Reset jon T 


Main Storage 















Gate LSR Lo to B 





Cl 5 and 6 







KGI4I De 





SAR SDR 


lent Cycle Ras 


}, Add to Reg or Store Instr 
Clock 3 and 4 


(not) Ist E Cycle 


A 
EB Cycle 


not) I/O Not CE Test 
not) I-R Program Back-up 


Cl 5 and 6 


+f 


KG131 


Force Bit 7 to A 


KG141 








clo . 
Phase DE A Load SAR & 
not) Wait | 


b> KC142 









Cl 8 


8 Channel Inhibit LSR Load Phase D__¢ : eine 7 . 
I/O _Not CE Test = | LSR Selected By eS 
| _ 1/0 Attachment 








Idle Time 
m@ A or B Reg Chk 


LSR To Aor B 
A LSR Write Lo 


Cl 6 
EB Cycle 


Sel BAR A not) Recomp! Cycle 
-LCI_5 through 0 


CE ES ER ES EAA ERIE ESCA ~— KLI2I 










BAR (Hi) 





3 ] 6 + 2P ena se poy BP : : “4 a EE ee ere . ee a a eee wa 


5406 CPU—Operations 
Sense I/O (Part 2 of 2) | | 5406 FETMM (6/70) 5-172 


5406 CPU—Operations 
Test I/O and Branch, and Load Address 


Test 1/O and Branch 


@ Test for I/O condition specified in 
Q code N field 


e Branch to address is loaded into ARR 


e IAR/ARR interchange occurs if tested | |-Op Cycle I-Q Cycle I-H I=L 
condition is satisfied | Op Code Q Code ee Cycle Cycle 
we 0123456710123 4 5671012345671012345 6 


@ Take I-H and I-L or I-X cycle 


SEE DIAGRAM 5-030 (I-H, I-L) 
5-042 (I-X) 


t 





TEST I/O 
AND BRANCH 









l-Op 
Cycle 
Diagram 5-010 





I-Q 
Cycle 
Diagram 5-010 


Instruction 
Format 

















l-X 
Cycle 
Diagram 5-042 


I-H, I=L 
Cycles 
Diagram 5-030 

















11xXxX 0001] Device | y] Tested Branch to Address 
address condition 


Primary or 
secondary unit. 








Tested conditions are 
described in the 
individual attachment 
sections of this manual. 





eee 


Correct address, valid N 
code, condition for branching 
--proceed with next 
ial i tio 


'1/O Condition B' only 


Correct address, valid N 
code, condition for branching 


"I/O Condition A' only 
met--branch to new address 


Incorrect parity--causes 
Both lines processor check and DBO 
parity check 


Invalid address or N code 
Neither line --causes processor check 
and invalid device address 





Load Address 
Bits 01 
1] 


2345 6 

Op Code XX00 1 

@ Load one or two bytes from storage into one 
of the two index registers 


@ If instruction format is four bytes, load two 
byte address into index register selected 
by Q code bits 6 and 7 


e If instruction format is three bytes, add last 
instruction byte to index register selected 
by Op Code bits 2 and 3. Then load result 
into index register selected by Q code bits 
6 and 7 


@ Take I-H and I-L cycles (four byte format) 
SEE DIAGRAM 5-030: 
@ Take I-X cycle (three byte format) 


SEE DIAGRAM 5-042 










LOAD ADDRESS 





l-Op 
Cycle 
Diagram 5-010 









I-Q 
Cycle 
Diagram 5-010 





Indexed (3 bytes 





Instruction 
format 





Direct (4 bytes) 


l-H, I-L 
Cycles 
Diagram 5-030 


7 
0 






5406 FETMM (6/70) 







5-180, 5-190 


Advance Program Level 


Bits 0 
Op Code 1 


Basic Machine 
e@ Test for |/O condition specified in Q code N field 


@ Loop on APL instruction until condition tested for 
no longer exists 


@ Q code N field of all zeros causes automatic 
advance to next sequential instruction 


@ Take I-R cycle SEE DIAGRAM 5-020 
Dual Program Feature Enabled 


® Test for I/O condition specified in Q code N field 


@ Program status register (PSR) contains recall 
information for retuming to original program 


® Take I-R cycle SEE DIAGRAM 5-020 


| | 
l | 
| 
| ® Program level advance if condition is satisfied | 

| 
| | 
| | 
| | 
| 


Not used on 5406. —s | | Line Activated by 
| Feet teee eee ey ee ee Jd ADVANCE Any Device 
PROGRAM LEVEL | 


; "I/O Condition B' only 
I/O Condition A‘ only 


Both lines 


Cycle : Neither line 






















Diagram 5-020 





Cycle 
Diagram 5-020 











Tested during I-Q cycle 
cl 8. Activates 'program 
interlock’ (Diagram 

4-030) 
KD131 


No Q | 
Tees code of 
' ma Yes 
condition a 
satisfied ‘ 
NN Ee 





programming 
enabled 






| 
| 
| 
| Not used 
| 
| 
| 


| 
| F 
on 5406. Xe 7 : 
ALTERNATE i NEXT SEQUENTIAL 
PROGRAM LEVEL /| INSTRUCTION 
| 


5406 CPU—Operations 
Advance Program Level, and Halt Program Level 


I-Op Cycl I-Q Cycl I-R 
Cycle 
Op Code 
01234567'0123 4 567 







f. WP Conditions 
Primary or 
secondary unit. 





2 Vv 3 


Halt Program Level 


Bits 0 
Op Code 1 


—n 
— ow 
Of 
oun 
Oo 
On 


Basic Machine 
© Prevents execution of next sequential instruction 
@ Loops on instruction until system start key is pressed 
e Instruction bytes three and four are displayed on console 


Dual Program Feature Enabled 






tested are de- 
‘scribed in the 
individual attach- 
“ment sections of 
this manual. 


e Prevents execution of next sequential instruction 






@ Branches to alternate program level if DPF is enabled 


© Program returns to original level if appropriate halt 
reset key is pressed 


e Take I-R cycle SEE DIAGRAM 5-020 


Not used on 5406. 


Correct address, valid N 
code, device not busy and 


HALT 
Correct address, valid N PROGRAM LEVEL 
_code, device busy or needs Ee 
attention--instruction rejected 












Incorrect parity--causes 
processor check and DBO 
parity check 


l-Op 
Cycle 
Diagram 5-010 


Invalid address or N code 
--causes processor check 
and invalid device address é 
|-Q 
Cycle 
Diagram 5-010 















I-R 
Cycle 
Diagram 5-020 


Dual 
program 
enabled 







Not used 
on 5406. 


B Yes 


NEXT SEQUENTIAL 
INSTRUCTION 


ALTERNATE 
PROGRAM LEVEL 


5406 FETMM 


(6/70) 


5-200, 5-210 


5406 CPU—Operations | | 5406 FETMM (6/70) 5-220 
System Reset (Part 1 of 3) 


1 v 2 V 3 


SYSTEM RESET 


| 
| "Bin Sub Gate' left up 
} 


from last operation 





























































CLOCK 0 Activate 'Force Clock Activate 'IAR Seld! Activate 'Op End' Activate 'Load Op Reg' ‘Activate 'Load SAR' 
9! . 
Activate 'Load A or ° 
; ' CLOCK 7 : Activate 'Load Q Reg' 
A CLOCK 1 Activate 'Load A or Activate 'Load Q Reg! B Reg 
B Reg' 
AV132 
CLOCK 2 Activate 'Load ALU' 
CLOCK 8 Activate 'Load ALU' Activate 'LSR Write Hi' 
KD141 
CLOCK 3 ae ‘Load A or Activate 'Load Q Reg' 
&g CLOCK 9 Activate 'Load SAR' 
CLOCK 4 Activate ‘Load ALU’ Activate 'LSR Write Lo’ 
CLOCK 5 ee ‘Load A or Activate 'Bin Sub Gate' Activate ‘Load Q Reg! 
eg 
5B 
CLOCK 6 Activate 'Load ALU' Activate 'LSR Write Lo' 


Note: System Reset is enabled only 
in process mode (KB141) 





System Reset 


KD131 


Main | Main Storage 





Phase DE (Odd not 9CD) Load A 
oe 9-0 A |boad SAR & RA101 
not) Wait oe 


KC142 











Cl 3C to 5C 





System Reset 





Load ALU 


Bin Sub Gate 


KY121 


Even not 0 CD 


AV132 


Cl 4 
not) EB Cycle 
not) I-H Cycle 


A i 
not) Alter Display or Storage CI 6 jor LSR Write Lo 
















Phase D 
Channel Inhibit LSR - 
I/O Not CE Test 
Idle Time oR, IN 
N 

A or B Reg Chk 
LSR to A or B i) crs PAR Sele IAR (Hi) IAR (Lo) 

POT IT2;3 ;4{(5 677] o[i] 2434] 5] 6{7 | 

Sel IAR CE or Sys Rst jor IAR System Sel 
5B | KLI11 

18 + 2P 





Note: 1. Refer to Diagram 4-020 
for clock circuits 
2. Refer to Diagram 4-030 | 


for cycle controls 


5406 CPU—Operations 
System Reset (Part 2 of 3) 


5406 FETMM = (6/70) 5-222 


5406 CPU—Operations 5406 FETMM (6/70) 5-224 


~ System Reset (Part 3 of 3) 














1 v 2 v 3 
System Reset Cycle ALD Reference 
oc 

ree = PARAS EAA [DERE INSEE Scie i [eae (a (eee eee 
geod calywrirecot = {| ST S| TTT ccs 
Lood SAR ove ee a eae aie 
re i 
Asien pe haa 
sisi Hf =p} =} + — cai 
eee rl sim ga ee sel el 
i cach ee 

A in Sub Gate iz : KY121 
rn ee le ee He gee cl eels CS 
“a — a a 

utput (all zeros) } ie ‘come AV142 

er eee ee tg 2 Gg ge ee 
Seite He eae ale Pee ee ei 
Op End Ns 
aocnes | eae a es ee a ee ee cs 
cave: fd a em a mln ol el a igor 
Note:. Parity checking is disabled during System Reset 

ag 





Initial Program Load (IPL) 
Objectives 


@ Program Load Key initiates system 
reset cycle 


@ Clock starts and continues to run 







@ System reset cycle causes: 


ae : 1. Send DBO 5 (file) 
| Yn ere 2. Select IAR and DFDR (fil 
(1) DBO 5 (File) : . . Selec an ile) 
Diesromn 220 g.. Ladd selected: LSRewith-all 





, ; zeros 
(2) All zeros written into JAR and 


DFDR (File) 
@ '1/O Condition B' resets IPL latch at end of - 4-036 
data transfer and activates process run. First 
I-Op cycle addresses storage position 0000 | Clock continues to run. 
A, (IAR set to all zero) | Activate 'wait state' 





I/O attachment requests 
cycles to transfer data 
beginning in storage 
location 0000 (Data 
Address Register all 
zeros) 






4-035 


'1/O condition B' resets 
IPL at end of data 





transfer 


4-036 


Activate ‘process run' 









Program begins with 


JAR at 0000 


END IPL 


5406 CPU—Operations 
Initial Program Load (IPL) 5406 FETMM (6/70) 5-225 


5406 CPU—Operations 
Alter SAR (Part 1 of 3) 


Alter SAR 
Objectives: 


@ Load contents of four console 
Address/ Data switches into 
the Instruction Address 
Register (IAR) by way of Data 
Bus In, A register and ALU 


@ Load SAR from the JAR at 
clock 9 time 


@ When start key is pressed, 
the clock runs 0 thru 4. 
A When start key is released, 
clock runs from 5 thru 9. 





ALTER SAR 


Clock 0 













Address storage 


Activate 'IAR Seld' 


Activate 'Bin Sub Gate' 


Activate 'Force Clock 9' 


Activate 'Load SAR' 


Clock 1 and 2 





Gate console bits hi 
from DBI to IAR 


Activate 'Read Call/ 
Write Call ' 











Activate 'IAR Seld' 


Activate 'Load A or 
B Reg' 


Activate 'Bin Compl 
A Reg' 


Activate 'Load ALU' 


Activate 'Write LSR Hi' 






Clock 3 and 4 













Gate console bits lo 


from DBI to IAR Activate IAR Seld 


Activate 'Load A or 
B Reg' 


Activate 'Load ALU' 


Activate 'Bin Sub Gate' 


Activate 'Write LSR Lo' 


Clock steps 4A,B,C,D,E 
and stops at phase F. 
Clock re-starts when 
start key is released 







Clock 5 and 6 


Move IAR lo thru B reg, 
ALU, and back to IAR 


(no change) 



















Activate 'Read Call/ 
Write Call! 


Activate 'IAR Seld' 


Activate 'Load A or 
B Reg’ 


Activate 'Load ALU' 


Activate 'Write LSR Lo‘ 


5406 FETMM = (6/70) 


Clock 7 and 8 


Move IAR hi thru B reg, 
ALU and back into 
IAR (no changes) 














KL141 


Activate 'IAR Seld' 


Activate 'Load A or 
B Reg' 


Activate 'Load ALU' 


Activate 'Write LSR Hi' 


Clock 9 





Move contents of [AR 
to SAR 


Activate 'IAR Seld' 


Activate 'Load SAR' 


END 





Load A or B Reg (odd not 9CD 
RA101 





Main Storage 


: a : 


Load SAR 





Phase DE 
Clock 9-0 
not) Wait State 


KC142 


Alter SAR 





Note: Refer to diagram 4-020 
for clock circuits 


Refer to diagram 4-035 
for Run controls 


5406 CPU—Operations 
Alter SAR (Part 2 of 3) 







a DBI From Address/Data Switches (4) 


caCORE Sake 3: Mein, Cate § 
See Lacey ae Pere see 7 





Test Mode 





rp PAD 


KY121 


Bin Compl A Reg 


Bin Sub Gate 








Test Mode 


Cl 2 


Alter SAR 


LSR Write Hi 


Channel Inhibit LSR 


I/O Not CE Test 


Idle Time 
A or B Reg Chk 







Pic ee oe te eg 


LSR to Aor B 





z POTil2T3[4151 6 7lo Til 27314751 417) 


Cl 4 

not) EB Cycle 

not) I-H Cycle 

not) Alter or Display Storage 








8 +P - A 


5406 FETMM = (6/70) 5-232 


ane og age ee 


5406 CPU—Operations | 5406 FETMM (6/70) 5-234 
Alter SAR (Part 3 of 3) 


ALTER SAR 


Start Key Pressed | Start Key Released 


ALD Reference MDM Reference 





Clock F- kc122 4-020 
ee 
Force Clock 9 KA232 4-020 
, Ss taaaai co col Cicsensleccamtaed 
Read Call/Write Call ae. KC132 
a Y 
Enable Clock Run me KA232 4-037 
Lod SAR eR chine en tans Ker4e 
JAR Select ee a ees en KL141 
pices F ceale st | [Conic iL —_ re 
B Reg Input RA101 
Load A or B Reg RA101 
Bin Compl A Reg KY121 
Bin Sub Gate KY121 
Load ALU AV132 
ALU Output AV142 
Load LSR KL101 





Alter Storage 
Objectives: | 


@ Transfer data from right most two 
console Address/Data switches (one 
byte) into Q reg and storage location 
designated by SAR 


@ With storage test switch in STEP; 
pressing start key advances clock 
through 4 time. Releasing start key 
advances clock through 9 time 


@ With storage test switch in RUN; 
clock re-cycles, skipping 9 time, 
until switch is returned to STEP 


e@e Address Increment switch ON 
A causes IAR to be incremented 
each CPU cycle 


@ Address Increment switch OFF 
causes console data to be transfered 
into same storage location each 
cycle 


ALTER STORAGE 





Clock 0 








Address storage 






Activate ‘Enable Clock 
Run' (Diagram 4-037) 


KL141 


Activate 'IAR Seld' 


KC142 


Activate 'Load SAR' 


5406 CPU—Operations 
Alter Storage (Part 1 of 3) 







KA232 


Activate 'Force Clock 9' 





Clock 1 and 2 
Move data from con- 
sole switches (hi) 
(not used) 











Activate 'Read Call/ 
Write Call' 







Activate 'IAR Seld' 


Activate 'Load A or 
B Reg' 


Activate 'Bin Compl 
A Reg' 







Activate 'Bin Sub Gate' 


Step 


Activate ‘Load ALU' 


Clock 3 and 4 
Move data from console 
Address/Data switches 

(lo) (Right most two 














KL141 


Activate 'IAR Seld' 


Activate 'Load A or 
B Reg' 


Activate 'Bin Sub Gate' 


Activate 'Load ALU' 


Activate ‘Store New' 






Storage 


re test switch 


: Step 














Clock 4F 


Start If storage test switch is. 
key released in STEP, ‘Enable Clock 
(Diagram Run' is activated again 


4-037) 


when start key is re- 
leased 


Clock 5 and 6 


Modify low order of 
instruction address 
register 


KC132 


Activate 'Read Call/ 


Write. Call! 





KD141 


Activate 'Load Q Reg' 





KL14) 


Activate 'IAR Seld' 









Address 
increment 
switch 







Off 






Activate 'Misc Bit 
7 to A' 


RA101 


_ Activate ‘Load A or 
B Reg' 


KY1 21 


Activate 'Bin Sub Gate' 





AV132 


Activate 'Load ALU' 





KL101 


Activate 'Write LSR Lo' 





Clock 7 and 8 : 
Modify high order of 


instruction address 
register 













KL1 41 


Activate 'IAR Seld' 


Activate 'Load Aor . 
B Reg' 


Activate 'Load ALU' 









Storage 
test switch 


Step adi Activate 'Write LSR Hi 


Clock 9 es KC142 


Activate 'IAR Seld' 


and ‘Load SAR' 





END 


5406 FETMM = (6/70) 


5-240 


5406 CPU—Operations 
Alter Storage (Part 2 of 3) 








Wait State Gate LSR Hi to B 





System Reset Gate LSR Lo to B 


Load A or B Reg (odd not 9CD 
RA101 


Main Storage . 


- = - 


Phase DE 
Clock 9-0 A Load SAR X X 
not) Wait State 


KC142 | Alter Storage Mode 








Store New 





(not) SAR Address Error 
(Invalid address) 





5406 FETMM = (6/70) 5-242 







Cl_1_and 2 










Cl 3 and 4 





eee B1 (Console switches) KEI 21 





not) IR Program Backup 
Cl 5 and 6 





Bin ompl A Reg 


Odd CD 


not) 3C to 5C 
Test Mode jon 


KY121 





| Cl 5 and 6- 
Load Q Reg A |Odd_Not 9CD 
: Alter/Display Storage 


KD141 


LSR Write Hi 


Channel Inhibit LSR 
Cl 8 ‘i 
/O Not CE Test 


Idle Time 







A or B Reg 





LSR to A or B 


JAR (Hi) 


OT 2; 3i(4islet7yoti f2}3t4t5]6 {7 | 


IAR (Lo) IAR Seld 


Select IAR CE 


ron | Alter/Display Storage 


KL101 











BSCA 
OFF OFF ae dl 
@ @ C) C) Address Increment Switch: 
ADDRESS \/O ae 
ON ON OFF BSCA COMPARE CHECK : ON - IAR incremented by 
co FILE LOCAL STEP io esdaas es one each CPU cycle 
OVERLAP WRITE : TEST ie ane soetiets i 
STOP RUN OFF SN ie HEE {AR addresses same 
RM HE ROCESS | storage position each 
(Q)- Wil xT ir i: : i ssegegess CPU cycle 
IAR | XR-1 SHU Eeetetsisis: EEE EE 
RUN STOP 5 nae die \ / xR-2 EEE 5 mind: 
I/O PARITY STORAGE ‘renee ADDRESS ne yw 
CHECK CHECK # TEST #INCREMENT ae OrF— ah EE 
2 START 
@ ©) LSR DISPLAY 
A : SELECTOR 
SYSTEM CHECK } STOP PROGRAM 
RESET RESET : | LOAD 
Start Key Held In Start Key Released 
ALD 
~ Reference 
> 0 — 2 3 4 5 6 7. 8 9 
jae Se ee I 
Read Call/Write Cal ale a ae KC132 
ne ee eS page 
IAR Select [Thome Va ae nes Te ee KL141 
m= Console Bits Hi Console Bits Lo a ee 
ee oa ee a | nas B eae ae ss ae a pa RAI 1] 
A Reg | t 
a , KL101 
Load Q Reg ise KD141 





5406 CPU—Operations 
Alter Storage (Part 3 of 3) 





Clock 


Force Clock 9 


Read Call/Write Call 


Load SAR 
Enable Clock Run 
IAR Select 

A Reg Input 

B Reg Input 

Load A or B Reg 
Bin Compl A Reg 
Bin Sub Gate 
Load ALU 

Load LSR 

Store New 


Load Q Reg 















i BSCA —4 

ADDRESS 1/0 

OFF BSCA COMPARE CHECK 
STEP 


STOP 


NORM 
a | XR-] 


RUN / 


gE AAR XR-2 
YO PARITY STORAGE ares ADDRESS rig ye 
:. TEST ¢ INCREMENT sia OFF OFF 


START 


@ 6) LSR DISPLAY ae Agee iH 


SELECTOR 
STOP PROGRAM 
LOAD 








eat eset ete 
eset esetece 


0 I 2 3 4 3 6 / 8 0 


is changed to STEP 


cs see 


sipaeidsadeeaih auediadiieinaeia ania igcaienadl dai 
Ee 











5406 FETMM (2/71) 5-244 


5406 CPU—Operations 
Display Storage (Part 1 of 3) 


Display Storage 
Objectives 


@ Transfer data from storage position 
addressed by SAR into Q register and 
display in console lights when drum 
switch is in position 5 


@ With storage test switch in STEP; 
pressing start key advances clock 
through 4 time. Releasing start key 
advances clock through 9 time 


@ With storage test switch in RUN; 
clock re-cycles, skipping 9 time, 
until switch is returned to STEP 


@ Address Increment switch ON 
A causes IAR to be incremented each 
CPU cycle 


@ Address Increment switch OFF 
causes console data to be transfered 
into same storage location each 
cycle - 


DISPLAY STORAGE 


Clock 0 








Address storage 


Activate 'Enable Clock 
Run' (Diagram 4-037) 






Activate 'IAR Seld' 


Activate 'Load SAR' 





Activate 'Force Clock 9' 


Clock 5 and 6 







Clock 3 and 4 











Move data from storage 
to console display 


Activate 'IAR Seld' 


Activate 'Load A or - 
B Reg' 


Activate 'Gate SDR 
to B' 


Activate 'Bin Sub Gate! 


Activate 'Load ALU' 


| Run 








Storage 
test switch 


lis storage test switch is 

| in STEP, ‘Enable Clock 
Run' is activated again 
when start key is 

| released 





key released 


(diag 4-037) 





Modify low order of 


instruction address 
register 





KC132 


Activate 'Read Call/ 
Write Call' 





KD141 


Activate ‘Load Q Reg' 








Clock 7 and 8 


Modify high order of 
instruction address 
register 













Storage 
test switch 


(+ 
step KLI4] 


Clock 9 KC142 


Activate 'IAR Seld' and 


"Load SAR' 





END 


‘5406 FETMM (6/70) 


Activate 'IAR Seld' 















Address 
increment 
switch 


Off 


Activate 'Misc Bit 7 
to A' 


RA101 


Activate ‘Load A or 


B Reg' 





KY121 


Activate 'Bin Sub Gate' 





AV132 


Activate 'Load ALU' 





KL101 


Activate 'Write LSR Lo' 





KL141 


Activate 'IAR Seld' 





RA1 01 


Activate 'Load A or 
B Reg' 





AV132 


Activate 'Load ALU' 





KL101 


Activate 'Write LSR Hi' 





5-250 


Cl 7 and 8 


Wait State 


Gate LSR Hi to B 


System Reset 





Cl 5 and 6 


EB Cycle 
not) Recompl Cycle A 
Inhibit SDR Transfer not) 3 and 4 Time 
Alter SAR or Storage 
Wait State jor | O Block SDR 


System Reset 


KG141 




















Odd not 9CD 
«a @ | RA101 













A 
SAR SDR pene aX 
Phase DE ; Load A or B Reg 
Clock 9-0 mn Load SAR 
not) Wait State | ; 
, eZ Cl 5 and 6 
KC142 e ek Load Q Reg ZA Odd Not 9CD 
Bin Comp £9 Alter/Display Storage 
ae KD141 
N Test Mode 
IAL 
Drum 
(not) 3C to 5C Switch 
Bin Sub Gate , 
> Test Mode ; Switch 
: t 
KVI21 Position (LPyorii2}3}4[s] 6} 7] ALU Output | 
AV152 
Channel Inhibit LSR 
Cl 8 . A 
LSR Write Hi I/O Not CE Test 
| jon Idle Time 
LSR Write Lo J Phase D A or B Reg Chk. 
C6 
KLI01 LSR to Aor B 


IAR (Hi) IAR (Lo) glAR Seld 
LOFT 2t3si4i5poy7potip2y3st4 is fet 7| 


5 Select IAR CE jon 


8+P 


Alter/ Display Storage 





5406 CPU—Operations 
Display Storage (Part 2 of 3) | | 5406 FETMM = _ (6/70) 


5-252 


5406 CPU—Operations . , 5406 FETMM (2/71) 5-254 
Display Storage (Part 3 of 3) 













































[— BSCA 
am BSCA — —- 
OFF OFF ON OFF OFF sh 
@ @ © O Address Increment Switch: @ @ @ @ : ‘ : 
ADDRES /O 
ADDRESS I/O D. ON ON 
ie ON OFF BSCA COMPARE CHECK } ON - JAR incremented by (/O ane oa pe COMPARE CHECK 
FILE LOCAL STEP — one each CPU cycle gessssesees Soe hah PNG USA a ged age ee pages Cah ceeeet ae, wR hoe eteha te eee 
OVERLAP WRITE innit: TEST Y ey He HH ee ae : SE 
STOP RUN OFF po i IAR addresses same : PES 
2 i 1) NORM : oa storage oe each oh s : 
HE Bi : 3 wets : U : see Mere Se sete sisseteti 
Hiaapapis Fy IAR | XR-1 seieideteas : SEES EEE CPU cycle IAR XR-] : segegitis SEHSESEEE 
D STeEp! RUN \ / i sft RUN STOP ON RUN yar NE WZ XR-2 } PHYS 
vo PARITY one Aone sie PON. XR Hee STOR Gia sis /O PARITY DDRESS ADDRESS Sy ERE ani Bei csc eee 
CHECK CHECK : TEST $INCREMENT COMPARE = ope OFF CHECK TEST INCREMENT COMPARE = ogee — ore } BREE: er CLOCK: 
start ON START ON ae <A 
@ : @ (©) LS DISPLAY @ (©) ee 
SELECTOR He SHER nee 
SYSTEM CHECK | STOP PROGRAM ee STOP = PROGRAM 
RESET RESET LOAD LOAD 


Start Key Held In Start Key Released 








ALD 
ge : age . seesses sss soso tes eces ose Peetirsrirteer es Reference RMP IPSS OSES eS SSL SSeS Ste P eee T seers ieee i rire i eerie rite erie Pir P Pre PPP Pe eee Tee e eee Te ere erste tee Teste Tee etry uaa | eee tater etete foceee 
>» 0 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 0 
Clock A{B JC] DIE | F--F--F-- A{BIC]LDIE]| F KC122 Clock 


—> 


Recycles until 


t test switch 
ah ne ee ees ani 
eee ete ee ee ey 


Force Clock 9 a ee: | nee KA232 Force Clock 9 


siciedipaiied .. - hadalalhai 5 casncah coc a eee eS 


KA232 Enable Clock Run 


Enable Clock Run 


IAR Select | , : sei a | KL141] IAR Select Rae , Meas PeeE TAREE at ome 
a ee a ee ee aad pt il 
A Reg Input ss | RAI] A Reg Input Wn en 
ee ee ate LARD | Te arto a 
B Reg Input eer <s ax (sae Shae es ae Seer RA101 B Reg Input i ee ee ; i eee Tiere 


Load A or B Reg 


| geet. ieee? ae ee RAIOI Load A or B Reg 


Bin Compl A Reg KY12] Bin Compl A Reg 


5B cr TTT leit apy Wmtege | cect cee 
in Su ate Eo Sree eeu See Mh Chapels eke eae ; ne ee a Oe 
icant i ae ae a leet els aviae |] teed ALU cet le Si wl diel dl eee. Ie 





Interrupt START 


@ Interrupt enable is turned on in [/O 
attachment by control code of SIO 
instruction 


Objectives: 


CPU executing main 
program instructions 


@|/O attachment sends interrupt request to CPU 


@ Interrupt occurs only after current instruction 
is finished 

® Interrupts main program with separate program Start 1/O enables 

interrupt (device 

@ Highest interrupt device takes precedence specified by Q code) 

over lower level devices 


@ Interrupt program ends with another SIO to 






A disable interrupt eS 
e Interrupt poll (op end 
a clock 5 to 8) 
_ Interrupt 
= request 
fm Yes 
Select JAR for 
> interrupt level 


Execute interrupt 
program 





RETURNTO 
INTERRUPTED 
PROGRAM 


5406 CPU—Operations 
Interrupt (Part 1 of 2) 








Store status of 
registers used in 
interrupted program 


Disable interrupt with | 
SIO (last instruction 
in interrupt program) 








Op Code Q Code 


Byte | Byte 2 Byte 3 


Y 
3 4 7 0 


3.4 5 7 0 7 


0 










Op Code = F3 
SIO Instruction 


Control Code 

















Bit 0 = 
Bit ] = 
Bit 2 = Set Interrupt Request (Diagnostic) 

Bit 3 = Reset Parity Check 

Bit 4 = Drop Bail 

Bit 5 = Unlock Keyboard 

Bit 6 = Enable Interrupts - Off disables interrupts 
Bit 7 = Reset Interrupt 






Device Address Equals 
0001 (1) for keyboard 











M and N field are 
not checked. Any 
combination of bits 
is valid. 


SIO Instruction Format for Keyboard (interrupt level 1) 


5406 FETMM 


(6/70) 


5-260 


5406 CPU—Operations | 5406 FETMM (6/70) 5-262 
Interrupt (Part 2 of 2) 


1 


Op End 


2 
A Load Interrupt , 
M/C Advance 
System Reset 

























ES 


IAR/ARR Int Lv - 4 Seld 


LZ 
Ww 
aie 






ARP/IAR Int Lv - 4 Seld 
> ARR Seld 


IAR Seld 


EB Interrupt Register Instruction 


IAR/ARR Int Lv - 3 Seld 


Fj 
aes 


SIO 


Clock 5 Instruction 


I-R Cycle 


& 


DBO ARR/IAR Int Lv - 3 Seld 





/O ATT 


IAR/ARR Int Lv - 2 Seld 


iL 


Q 


ARR/IAR Int Lv - 2 Seld 


A 
Inter Req 1 


jon IAR/ARR Int Lv - 1 Seld 


KMI111 


fi 
er ee 





Any Int Lev Being Serviced 


> FF 


| Diag 4-036 

| 4-072 

A | 4-074 
Interrupt Poll 


Diag 4-074 Note: Refer to Diagram 4-074 for circuits 
describing interrupt level 0 


IF 









jon ARR/IAR Int Lv - 1 Seld 


Clock 5 to 8 


La Interrupt Level 0 Request 


KT13] 


This power on-off sequence is 
for machines without printed 
circuit board sequence panels. 
For machines with printed 
circuit board sequence panels, 
see page 6-011. 


-YB100 


115V at 
convenience 


outlet 


5406 CPU—Power and Cooling 
Power Sequencing (Part 1 of 2) 








POWER ON 
SEQUENCE 






Close main 
line circuit 
breaker 





YB100 


Activate CPU 
24V control 
power supply 
















Thermal Yes 
Condition 
No 
YB102 YB120 
Open circuit to 
Turn power on K3 and turn on 
thermal light 
YB120 
Energize K1 
YB100 


Start CPU blowers 


Apply power to: 


Ferro #1 
Ferro #4 
(Note 1) 
—12V supply 
(Note 2) 





Note 1. Ferro #4 and K11 are required for B gate only (YB133). 
Note 2. Required only for machines with BSCA medium speed (YB133). 





YB110 
Energize: 
K10 

K11 (Note 1) 
K12 
K30 
TD1 








; (Note 2) 





Energize 
K2 and K9 






Apply ac power to: 






24V supply 






2 1/O gear 
3 Power packs 
(meters) 








Energize K8 


Energize K4 






Activate ’Power 
On Reset’ 











Turn on power 
on light. Apply 
+24V to the 

file. 






END OF SEQUENCE 









POWER OFF 
SEQUENCE 






Turn power 
off 


YB120 


De-energize 
TD1 and K2 


Deactivate ac 

power to: 

1 24V supply 

2 1/O gear 

3 Power packs 
(meters) 





YB110 - 


De-energize 
K4 and K8 





-YB120 


De-energize K1 


Stop CPU blowers 
Remove power to: 


Ferro #1 
Ferro #4 
(Note 1) 
—12V supply 
(Note 2) 


END OF SEQUENCE 












K3 remains 
energized 


24V control power 
and 115V conveni- 
ence outlet remain 
active until the main 
line circuit breaker 
is turned off 





5406 FETMM = (2/71) 6-010 


5406 CPU—Power and Cooling 
Power Sequencing (Part 2 of 2) 


This power on-off sequence is for 
machines with printed circuit board 
sequence panels. For machines 
without the printed circuit board 
sequence panels, see page 6-010. 


YB100 


115V at 
convenience 


outlet 



















POWER ON 
SEQUENCE 


Close main 
line circuit 
breaker 





YB100 


Activate CPU 
24V control 
power supply 













Thermal 
Condition 


No 
YB102 YB120 
Open circuit to 
Turn power on K4 and turn on 


thermal light 





YB120 


Energize K1 


YB100 


Start regulator 
fan 


Apply power to: 


1 Ferro #1 
2 -12V Supply 
(Note 1) 


Note 1. Required only for machine 
with BSCA medium speed (YB133). 








YB110 


Energize: 
K7 
K10 


Start .5 second 
electronic time 
delay 


YB120 


When time delay 
times out, energize 
K2 and K8 





YB100 


Apply ac power to: 


1 24V supply 


2 1/O gear 
3 Power packs 
(meters) 


YB110 


Energize K5 


YB120 


Energize K3 


YB120 


Activate ‘Power 
On Reset’ 


Turn on power 
on light. Apply 
+24V to the 
file. 


END OF SEQUENCE 









POWER OFF 
SEQUENCE 






Turn power 
off 


YB120 


De-activate time 
delay and drop -30V. 
De-energize K2 


Deactivate ac 
power to: 


24V supply 
\/O gear 
Power packs 
(meters) 





YB110 


De-energize 
K3 and K5 





YB120 


De-energize K1 


Stop regulator 
fan 


Remove power 
to: 


1 Ferro #1 
2 -12V supply 
(Note 1) 


END OF SEQUENCE 





5406 FETMM ss ((2/71) 6-011 





K4 remains 
energized 
















24V control power 
and 115V convenience 
outlet remain active 
until the main line 
circuit breaker is 
turned off 


Section 7. Keyboard and Console 


This section of the 5406 FETMM contains the theory and maintenance 
diagrams for the operator console and the keyboard attachment. It consists 
of three chapters as follows: 


Chapter 1. Introduction 
Chapter 2. Functional Units 
Chapter 3. Operations 


KEYBOARD CONSOLE—Contents 


Contents 


Chapter 1. Introduction 7-101 


5406 Keyboard-Console 7-101 

Keyboard 7-102 

Key Identification System and Key Operation 7-103 

Weighted Codes (2 Parts) 7-104, 7-105 

Keys and Lights (2 Parts) 7-106, 7-107 

Console 7-108 

Console Lights 7-109 

Keyboard Attachment 7-115 

Load I/O Instruction Format 7-116 

Test I/O and Advance Program Level Instruction Format 7-117 


- Sense I/O Instruction Format 7-118 


Start I/O Instruction Format 7-119 
Data Flow Operations 7-120 

Data Flow 7-121 

Keyboard Timing 7-122 


Chapter 2. Functional Units 7-201 


Introduction to Functional Units 7-201 
Board Layout 7-202 

Encode Board 7-203 

DBI Assembler 7-204 

Console Lights 7-205 

Initial Selection 7-206 

Control Latches 7-207 


Chapter 3. Operations 7-301 


Introduction to Operations 7-301 

Load I/O Instruction Flowchart (2 Parts) 7-302, 7-303 
Load I/O Instruction Timing Chart 7-305 

Sense I/O Instruction Flowchart 7-306 

Sense I/O Instruction Timing Chart 7-307 

Start I/O Instruction Flowchart 7-308 

Start I/O Instruction Timing Chart 7-309 

Key Operation—Programmed 7-310 

Keyboard Interrupt Request 7-311 

Alter Storage Operation 7-313 

Alter Storage From Keyboard Flowchart (2 Parts) 7-314, 7-315 
Typamatic Operation 7-316 


5406 FETMM = (2/71) 


7T-i 


Chapter 1. Introduction 


5406 KEYBOARD-CONSOLE Encode 


Board 
7-203 


The model 6 can be controlled by an operator with the combination kev- 
board-console. The keyboard provides a means for data entry and the con- 












Console 
sole provides system control and display. 7-108 
This section of the 5406 FETMM contains the following information: through 


1. Keyboard description and key codes. 7-109 


Zi Console description of lights and switches. 
3: Keyboard attachment including the encode board. 


Electrical and mechanical timing for the keyboard appears on page 7-122. 
For further information concerning the basic keyboard, refer to the Field 
Engineering Theory-Maintenance Manual, Elastic Diaphragm Encoded Key- 


Boards, Order No. SY27-0073. a 


through 
7-107 






Attachment 
7-115 
through 
7-316 





Rin 


BRO639A 


KEYBOARD CONSOLE -Introduction 


5406 Keyboard-Console 5406 FETMM = (2/71) 7-101 


7-102 


(2/71) 


5406 FETMM 


KEYBOARD CONSOLE - Introduction 


Keyboard 


KEYBOARD 








Console 
Keyboard 





























































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Numeric Keys* 


Space Bar 


Alpha-Numeric Keys* 





*Function keys are shaded. 


BRO641A 


KEY IDENTIFICATION SYSTEM 
Erase Key: Key positions Re9, Re10, 


The position of each key on the keyboard is defined by the following nota- ee eee Row e and Re11 are located below the erase 

tional system: Gk keyboard Key position 10 keybutton, Re10 is used for the erase 
key function. Key positions Re9 and 

<L_ L designates keys located on the left hand side of the keyboard. | | Hedi iaesduailabletonestentione te 


R= R designates keys located on the right hand side of the keyboard. 
Lower case alphabetic characters (a, b, c, d, and e) designate the 
key rows. 

Numerals represent the key position on the keyboard. 


the keyboard data output; example: 


10 and 11 pence 


or 


: 00 and 000 
When needed, the words upper or lower are used to designate upper or lower 


case. 


Example: e110 is the left most key in the top row of keys. 
Lcb lower is a lower case a, 


Left Hand Side Right Hand Side 


KEY OPERATION—PROCESS MODE 


When the keyboard is ready (keyboard unlocked and interrupts enabled) 
and a key is pressed, an interrupt request is sent to the CPU. Two bytes are 
generated by pressing a key, a data byte and a status byte. These bytes are 
stored in the DBI assembler in the keyboard attachment. They are sent to 


the CPU during a sense instruction. 10 7 3 Nhe 1 
The first byte sent to the CPU is the status byte. This byte indicates the @ | | | § | | 4 
type of key pressed and the parity of the forthcoming data byte. 10 7 4 3 7 1 

The second byte sent to the CPU is the data byte. The data byte is made @ | °| |S 
up of a weighted code (eight bits and parity). It is called a weighted code 5 3 5 a 
because it represents the key position pressed rather than an EBCDIC, card @ | | | | 4 
code, or any other coded character that represents the graphic on the key 7 5 3 ; ; : 
i | 


Keys that generate upper and lower case characters are controlled by the 

shift bar. They generate two bytes (status and data) in upper or lower shift. & : 
The keyboard is assigned interrupt level 1. An interrupt is granted to the 

keyboard when no other device with a higher priority is polling for an inter- 

rupt. When the interrupt is granted, the CPU issues a sense instruction to 

the keyboard. During the sense instruction, the two bytes are sent to the 

CPU. The status byte is sent first followed by the data byte. 
The status byte is stored in main storage in the address specified by the 

first operand address of the sense instruction. The data byte is stored in the 

specified operand address minus one. 










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(+ sd 


BRO642A 


KEYBOARD CONSOLE—Introduction 
Key Identification System and Key Operation . 5406 FETMM (2/71) 7-103 


KEYBOARD CONSOLE-Introduction 5406 FETMM) (2/71) 7-104 
Weighted Codes (Part 1 of 2) 


WEIGHTED CODES Weighted Code USA | WTC Replaces 

Each key position (except the shift key) has a weighted code assigned (8 bits Key Position 0123 4567 Key Symbol Austria/Germany Weighted Code Character USA Character 
plus odd parity). The command lights and field/operation lights are each Rd6 upper 0011 1000 | (logical OR) Key Position 0123 4567 

assigned a weighted code so that the program can turn them on or off. The Rd6 lower 0011 0000 + Le4 upper 7 0001 0010 @ 

key code is sent to the CPU as the data byte of a sense instruction after that Ra2 0011 0001 . (See note) ~ Le3 upper 0001 0011 # 

key has been pressed. The lights are turned on or off with a load !/O instruc- LS 0000 1010 A Le2 upper 0001 0100 $ 

tion. Lcd 0010 0110 S Re3 upper 0001 1000 ? : 

The key position or light number, the weighted code, and the associated C3 0000 1101 D Re7 upper 0011 1111 ds eo 
keybutton symbol (graphic) are shown for domestic and World Trade tc2 0000 1111 F Baz lower 0010 1111 a - 
Corporation (WTC) keyboard-consoles. Lol 0001 1010 G Rd1 0010 0111 Z Y 

Weighted Code USA Rol 0001 1011 4 Rd6 upper 0011 1000 — | 
Key Position 0123 4567 Key Symbol Re? 0001 1101 J Rd6 lower 0011 0000 U +f 
Le5upper —S<0001:«0001 | | Rc3 0001 1110 K Rcd upper 0011 1010 | : 
Le5 lower 0000 0001 1 Rc4 0001 1111 L Rcd lower 0011 0010 O : 
Le4 upper — 0001 0010 @ Ace bee 0011 1010 : Rc6 lower 0011 0011 A : 
Le4 lower © 0000 0010 2 | RS lower 0011 0010 Lb5 0010 1101 . Z 
Le3 upper 0001 0011 # Ro6 upper 0011 1011 # a a porn mee : 
Le3 lower 0000 0011 3 Rc6 lower 0011 0011 . ih Paienss 

| | plac 
nae se spe : Lb5 0010 1101 2 Denmark Weighted Code Character USA Character 
| oo Lb4 0010 1011 5 aie Key Position 0123 4567 
-Le1 upper 0001 0101 % Lb3 0000 1100 C 
Le1 lower 0000 0101 5 Lb2 0010 1001 V Le# upper iaetlamee e@ 
Re1 upper 0001 0110 ¢ Lb1 0000 1011 B pe a : 
Re1 lower 0000 0110 . Rb1 0010 0001 N Re3 upper 0001 1000 ? ; 
Re2 upper 0001 0111 & Rb2 0010 0000 M | 
Re2lower -—S— 000 0111 7 Rb3 upper 0011 1100 < nao UEDet ee ee a | 
Re3 upper 0001 1000 Rb3 lower 0011 0100 ; ise — sey se A ' 
" | = 
Re3 lower 0000 1000 8 Rb4 upper 0011 1101 > | ore aaa tia 7 = 
Re4 upper 0001 1001 ( Rb4 lower 0011 0101 , 
Re4 lower 0000 1001 9 Rb5 upper 0011 0111 ? AG wee ee | 3 
Re5 upper 0001 0000 Rb5 lower 0011 0110 / i sai a ss . : 
c6 lower 

ned ee | oer Oe mech) Note: As an option for World Trade Corporation, the decimal point may Rb5 upper 0011 0111 * ? 
Re6 upper 0011 1110 ___ (underscore) be changed to a decimal comma. 
Re6 lower 0010 1110 = 
Re/ upper — 0011 1111 —_ 
Re7 lower 0010 1111 = 
Ld5 0010 0100 Q 
Ld4 0010 1010 Ww 
Ld3 0000 1110 E 
Ld2 0010 0101 R 
Ldi 0010 0111 T 
Rd1 0010 1100 Y 
Rd2 9010 1000 U 
Rd3 0001 1100 | 
Rd4_ 0010 0010 O 
Rd5 0010 0011 © P 


WTC Replaces WTC Replaces Brazil/Portugal 
Norway Weighted Code Character USA Character Finland/Sweden Weighted Code Character USA Character Le2 upper 0001 0100 ; ¢ 
Key Position 0123 4567 Key Position 0123 4567 Le3 upper 0001 0011 6 4 
Le4 upper 0001 0010 @ Le4 upper 0001 0010 : @ Le4 upper 0001 0010 A @ 
Le3 upper 0001 0011 ; # Le3 upper 0001 0011 : So Re3 upper 0001 1000 ? : 
Le2 upper 0001 0100 : $ Le2 upper 0001 0100 ‘ $ Rcd lower 0011 0010 M : 
Re3 upper 0001 1000 ? : Re3 upper 0001 1000 ? ; Rc6 upper 0011 1011 . 7 
Rd6 upper 0011 1000 - | Rd6 upper 0011 1000 : | Rb2 0010 0000 G M 
Rd6 lower 0011 0000 / + Rd6 lower 0011 0000 / + Rb3 lower 0011 0100 : : 
Re7 upper 0011 1111 = — Re7 upper 0011 1111 = —, Rb4 lower 0011 0101 Z . 
Re7 lower 0001 1111 + = Re7 lower 0001 1111 + = Rb5 upper 0011 0111 # ? 
Rcd upper 0011 1010 — Rcd upper 0011 1010 | 
Rcd lower 0011 0010 A : Rc5 lower 0011 0010 ; : 
Rc6 lower 0011 0011 : : Rc6 upper 0011 1011 — F : 
Rb3 lower 0011 0100 g ' Ree lower 0017 COT ° 
Rb4 lower 0011 0101 & ; Rb3 lower 0011 0100 A ; 
Rb5 upper 0011 0111 | ? Rb4 lower 0011 0101 A : 
Rb5 lower 0011 0110 j Rb5 upper 0011 0111 F ? 

Rb5 lower 0011 0110 0 / 
| WTC Replaces | | 
Belgium/France Weighted Code Character USA Character WTC Replaces 
#1 Key Position 0123 4567 Spanish Speaking Weighted Code Character USA Character 
Le4 upper 0001 0010 ’ @ Key Position 0123 4567 | 
Le2 upper 0001 0100 f $ Le3 upper 0001 0011 ; = 
Le1 upper 0001 0101 ( % Re3 upper 0001 1000 ? ; 
Rei upper 0001 0110 % ¢ Rcd upper 0011 1010 < : 
Re3 upper 0001 1000 __ Rc5 lower 0011 0010 N 
Ld5 0010 0100 A 0 Rc6 upper 0011 1011 > a 
Re4 upper 0001 1001 ¢ ( Rb3 upper 0011 1100 ; < 
Ld4 0010 1010 Z Ww Rb4 upper 0011 1101 : > 
Red upper 0001 0000 a ) Rb5 upper 0011 0111 # ? 
Lcd - 0000 1010 QO. A Le2 upper 0001 0100 Pts $ 
Re6 upper 0011 1110 ) oe 2 (For Spain Only) 
Lb5 0010 1101 W Z 
United Kingdom 

me Replaces Le2 upper 0001 0100 £ $ 
Belgium/France Weighted Code Character USA Character Rel upper 0001 0110 $ é 
#2 Key Position 0123 4567 
Le4 upper 0001 0010 : @ 
Le2 upper 0001 0100 f $ 
Le1 upper 0001 0101 ( % 
Re1 upper 0001 0110 % ¢ 
Re3 upper 0001 1000 Ps : 
Re4 upper 0001 1001 G ( 
Re5 upper 0001 0000 a ) 
Re6 upper 0011 1110 ) woe 


KEYBOARD CONSOLE -Introduction 


Weighted Codes (Part 2 of 2) 5406 FETMM _—_ (6/70) 7-105 


KEYBOARD CONSOLE —Introduction 


Keys and Lights (Part 1 of 2) 


KEYS AND LIGHTS 


Com mand Keys 


Key Position 


Le10 
Le9Q 
Les 
Le7 


Ldi0 
Ld9 
Ld8 
Ld7 


Lc10 
Lc9 
Lc8 

— Le7 
Lb10 
Lb9 
Lb8 
Lb7 


Code | 
0123 4567 


0000 0001 
0000 0010 
0000 0011 
0000 0100 


0000 0101 
0000 0110 
0000 0111 
0000 1000 


0000 1001 
0000 1010 
0000 1011 
0000 1100 


0000 1101 
0000 1110 
0000 1111 
~ 0001 0000 


Field/Operation Lights 


Light 
Number 


COON OOH WN = 


Function Keys 


Key Position 


Le6 
Ld6 
Space 
Rd7 


Re8 

Re10 
Re11 
Re12 


Inquiry request 
(on console) 


Control 
Code 


1XXX KXXXX 
X1XX XXXX 
XX1X XXXX 
XXX1 XXXX 
XXXX 1XXX 
XXXX X1XX 
XXXX XX1X 
XXXX XXX1 


Weighted Code 
0123 4567 


0000 0101 
1000 0001 
0100 0000 
0001 0101 


0001 0110 
0000 0011 
1001 0001 
0000 0010 


0001 0001 


Keytop Number 


01 


02 
03 
04 


05 
06 
07 
08 


09 
10 
11 
12 


13 
14 
15 
16 


Name 


tab 

program start 
space 

return 
backspace 
erase 


enter + 
enter — 


inquiry request 


Numeric Keyboard Keys 


Key Position Weighted Code Basic Keytop Notation 
0123 4567 

Rat 0000 0000 0 

Rb7 0000 0001 1 

Rb8 0000 0010 2 

Rb9 0000 0011 3 

Rc8 0000 0100 4 

Rc9 0000 0101 5 

Rce10 0000 0110 6 

Rd8 0000 0111 7 

Rd9 0000 1000 8 

Rd10 0000 1001 9 

Re9 0000 0001 See note 

Re11 0000 0010 See note 


Note: These keys are located below, but not activated by, the erase key on 
the domestic keyboard. They are available for World Trade Corporation 
extensions (i.e., 10 and 11 pence or double and triple zero). When activated, 
they cause the status byte preceding the data byte to have bit 4 active. For 
the other keys in this table, the status byte will have bit 1 active. 


KEY FUNCTIONS 


Before a key can be operated, a keyboard start I/O instruction must be given 
to the CPU to enable interrupts and unlock the keys. All keys on the key- 
board (except the shift key) cause an interrupt request to the CPU and 
generate two characters (status byte and data byte) from the keyboard into 
the attachment. The status and data bytes are transferred to the CPU when 
a sense instruction is issued to the keyboard. 


Numeric Keyboard Keys 


These keys are grouped on the right side of the keyboard. They are used to 
enter numeric data and a decimal point. 


Status Byte Data Byte 
0100 0000 See ‘‘Weighted Codes” 


Three function keys (Enter + Enter — and Erase) are associated with these 
keys for use in controlling the data entered. 


Alpha-Numeric and Special Character Keys 


These keys occupy the center portion of the keyboard and resemble an 
electric typewriter keyboard. All of the direct entry system graphics are 
entered from this section. 


Status Byte Data Byte 
0100 0000 See ‘’Weighted Codes”’ 


5406 FETMM 


(6/70) 


7-106 


Function Keys 


The ten shaded keys (shown in the illustration on-page 7-102) and the 
inquiry request switch on the console are called function keys. These keys 
are under program control to perform the function stated on the keybutton 
or console. Bit 3 of the status byte identifies the data byte as a function 
character. The programmed function of these keys follows. 


Tab Key © 


This key has two levels of depression. When pressed down to the first level, 
the print element is spaced until the next programmed tab is sensed. When 
the key is pressed down to the second level, the weighted code continues 
to be sent to the CPU until the key is released. This operation is called 
typamatic and is accomplished through a combination of mechanical and 
program controls. | 


Status Byte 
0001 QO000 


Data Byte 
0000 0101 


Backspace Key 


This key has two levels of depression. When pressed down to the first level, 
the print elernent is spaced one position to the left. The program can either 
physically reposition the print element or merely readdress the previous 
address position in storage, whichever is appropriate for the operation in 
progress. When the key is pressed down to the second level, the weighted 
code continues to be sent to the CPU until the key is released. This operation 
is called typamatic and is accomplished through a combination of mechani- 
cal and program controls. 


.Status Byte 
0001 O000 


Data Byte 
0001 0110 


Program Start Key 


‘When pressed, this key indicates to the program that the keyed in field is 
complete and may be acted upon; example: printed if desired. 


Status Byte Data Byte 
0001 OO000 0000 0001 
Enter — Key 


When pressed, this key indicates to the program that the keyed in field is 
complete and is a negative number. 


Status Byte 
0001 OQ000 


Data Byte 
0000 0010 


KEYBOARD CONSOLE -—Introduction 
Keys and Lights (Part 2 of 2) 


Erase Key 


When pressed, this key indicates to the program that the presently keyed 
field is to be deleted from storage. 


Status Byte Data Byte 
0001 O000 0000 0011 
Return Key 


When pressed, this key causes the print element to return to the left margin 
and normally index one line. Indexing may or may not occur, depending on 
the program. 


Status Byte Data Byte 
0001 0000 0001 0101 
Enter + Key 


This key indicates to the program that the keyed in field is complete and is 
a positive number. 


Status Byte 
0001 O000 


Data Byte 
0001 0010 


Inquiry Request Switch 


This switch is located on the console. Interrupt level 1 must be enabled to 
recognize this switch. The switch is not under keyboard bail interlock con- 
trol. When activated, it normally indicates to the program that a keyboard 
operation is desired and requests that the keyboard be unlocked. 


Status Byte Data Byte 
0001 0000 0001 0001 
Space Bar 


The space bar accomplishes the same result as in standard typewriter use. 
When this key is pressed, the print element is programmed to advance one 
position to the right, either by printing a blank, or a tab right command. 


Status Byte Data Byte 
0001 0000 0100 0000 
Shift Keys 


There are two of these keys, one located on either side of the bottom row 
of alpha-numeric keys. These keys have the same function; they do not 
request an interrupt or generate a weighted code, but condition the encode 
logic for upper shift characters (numeric and special characters). 


Command Keys 


The command keys are grouped to the left side of the keyboard. Eight com-. 
mand keys are standard. An optional feature provides an additional eight 
command keys. The standard keys are labeled 01 through 08. The optional 
keys are labeled 09 through 16. 

The program assigns functions to these keys to permit the operator to 
influence the execution of the program routine. Command key lights are 
used to signify that the associated key function is in effect. 

Bit 2 of the status byte identifies the data byte as a command character. 
The code associated with the command keys and lights is shown in 
“Weighted Codes.” 


5406 FETMM (6/70) 7-107 


KEYBOARD CONSOLE —Introduction 
Console 


CONSOLE 


The operator console contains the switches and lights necessary for operator 
control of the system. It is divided into two sections: system indicator 
lights, and system control switches. 


System Indicator Lights 


The system indicator lights section is divided into six parts. They are: 
system check lights, halt code indicator lights, field/operation indicator 
lights, keyboard ready light, command key indicator lights, and the system 
power on light. 

Individual attention lights are provided for disk 1, disk 2, CRT, ledger 
card device, data recorder, SIOC, BSCA, and printer. The processor check 
light is also displayed on the console. 

The halt indicator group of lights are provided for use under program 
control to indicate to the operator a cause for system halt. They are: stop 
light, and nine halt indicator lights. 

The field/operation group of lights consists of eight lights which may be 
labeled by use of a plastic overlay. The program uses these lights to inform 
the operator at what point in the program he may enter specific data fields 
or take specific action. 

The command key indicator light group consists of eight (standard) or 
sixteen (feature) lights that are associated with the command keys on the 
operator keyboard. When the operator presses a command key, the program 
lights the associated command light on the console. When a command key 
is pressed and the associated command light is on, the program will turn off 
that light. In addition, the program can light a specific command key light 
whenever there is a need to communicate a predefined condition to the 
operator. Plastic overlays are provided for the lights so that the significant 
meaning for a light can be changed by typing on the overlay. 


System Control Switches 


The system control switches section includes those switches required for 
system powering, program loading, system starting, stopping, resetting, and 
configuring. | 


SWITCHES 


System Start Switch 


When this switch is moved to the start position the processor turns off the 
halt code lights and resumes normal operation. When this switch is moved 
to the stop position the processor halts at the end of the operation in pro- 
cess. This halt is indicated by turning on the stop light on the console. 

\/O data transfers are completed without loss of information. The system 

can be restarted without loss of information only by setting the switch to 

the start position. 











ON READY 
Pe P| 
FIELD/OPERATION 








Inquiry Request Switch 


This switch is mounted. on the console, and although this key is not under 
keyboard bail interlock control, it operates as though it were a key on the 
keyboard. Moving this switch to the on position causes the data and status 
bytes to be stored in the keyboard encode circuitry. Interrupt level one 
must be enabled for the CPU to recognize this switch. The status byte has 
the function key bit (bit 3) on and the data byte contains the unique data 
character code for the inquiry request key (0001 0001). 


Data Recorder Switch 


Moving this switch to the on line position places the data recorder under 
program control when the verify-punch switch on the data recorder is in 
the punch position. The data recorder keyboard is disabled, data can be 
entered into the system from the data recorder reading station, data can 
be punched at the data recorder punching station, and data and control can 
be entered from the system keyboard-console. 

Moving this switch to the off line position places the data recorder under 
its own control and allows it to function as a normal (off-line) data 
recorder. 


Program Load Switch 


This switch initiates loading the program into main storage. The following 
actions occur when this switch is operated to the on position: 


4 All {/O and machine registers, controls, and status indicators 


are reset. 

2. The instruction address register is set to zero. 

o The disk file data address register is reset to zero. The record in 
cylinder zero, sector zero on one of the disks in disk drive one is 
read into storage starting at location 0000. The disk that provides 
the first record is selected by the setting of the disk select switch 
on the console. 


SYSTEM] DISK 


PROC DATA DISK DISK RESET |DRIVE 1 DRIVE 2] SELECT LOAD RCRDR REQUEST| START 
02 03 04 CHECK SIOC BSCA LCD CRT RCRDR PRINTR DRIVE 1 DRIVE 2 
; HALT CODE ON ON ON |REMOVABLE ON ON LINE ON START 
PWR KEYBD STOP 


POWER ( 


5406 FETMM ss (2/71) - 7-108 





DISK DISK PROGRAM] DATA = INQUIRY] SYSTEM 


OFF FIXED OFF LINE STOP 


BRO360 


When the program load switch is released, the processing unit executes 
the instructions read into storage from cylinder zero, sector zero, starting 
at location 0000. 

If disk drive one is not ready, its 1/O attention light is turned on. When 
the program load switch is operated, it is necessary only to make disk drive 
one ready to complete the program load function. 


Disk Select Switch 


This switch selects the disk from which the initial program load will be 


» 


"performed. When the switch is moved to the removable position, sector 


zero of cylinder zero, of the removable disk is used for program loading. 
Similarly, when the switch is in the fixed position, sector zero of cylinder 
zero, of the fixed disk on disk drive one is used for program loading. 


Disk Drive 1 and Disk Drive 2 Switches 


These switches turn power on or off to the disk drive motors. 


Power Switch 


This switch controls the power to the system. When this switch is turned on, 
a system reset is performed in such a manner that no I/O operations are 
performed until explicitly directed. Unless the stop switch is actuated before 
power off switch is used, the integrity of data in storage is not quaranteed 
after this switch is operated. When the switch is turned off, power is dropped 
in the CPU and all |1/O devices connected to the system. 

When the switch is turned on, the keyboard is locked, all indicator lights 
are turned off, and interrupts are disabled. An initializing start 1/O instruc- 
tion is required to unlock the keyboard and enable interrupts to allow 
keyboard operation (‘KB Ready’). 


CONSOLE LIGHTS 


Processor Check Light 


The processor check light turns on when an invalid op code or parity error 
is detected in the CPU. It is also turned on when an invalid O code is detec- 
ted. It is turned off by system reset or pressing the check reset key on the 
CE panel. Any of these errors causes the processing unit to come to an 
immediate stop, the clock is stopped and the input/output data may be lost. 
The specific error that caused the stop is displayed on the CE console. 


1/O Attention Lights 


When any one of the following lights is on, it indicates that the correspon- 
ding I/O device has been issued a start I/O instruction but it is not ready to 
operate. A not ready condition can be caused by power not being on or by 


some condition involving the paper or cards to be handled by the I/O device. 


The 1/O attention indicators are SIOC, BSCA ATTN, LCD, CRT, DATA 
RCRDR, PRINTER, DISK DRIVE 1, and DISK DRIVE 2. The specific 
conditions that cause each !/O light to turn on are discussed under the 
individual !/O devices. 


Halt Code Lights 


These lights are turned on by the individual bits (nine), and the halt indica- 
tor, halt identifier bytes of the halt program level instruction. 


Power On Light 


_ This light is turned on when system-power-on sequencing has been success- 
fully completed and stays on until system power is turned off. 


Keyboard Ready Light 
This light is on when the keyboard has been enabled and unlocked. 


Stop Light 


This light is turned on when the system start switch is moved to the stop 
position and is turned off by moving the system start switch to the start 
position, or by system reset. 


Field/Operation Lights 


These lights are turned on by a load !/O operation. The meaning of each 
light is determined by the program being used. A plastic overlay is provided 
for the field/operation lights so that appropriate labels can be applied. These 
labels identify the particular meaning given to the lights by the programmer. 
Once turned on, the field/operation lights remain on until another load !/O 
specifying the field/operation lights is executed. 


KEYBOARD CONSOLE-— Introduction 
Console Lights 


SYSTEM] DISK DISK DISK PROGRAM] DATA 


PROC DATA DISK DISK RESET [DRIVE 1 DRIVE 2] SELECT LOAD RCRDR 
02 03 04 CHECK SIOC BSCA LCD CRT RCRDR PRINTR DRIVE 1 DRIVE 2 
HALT CODE ON ON ON |REMOVABLE ON ON LINE 

a Be D1 2 3 4 5 
| | "| | PWR -KEYBD STOP 


OFF OFF FIXED OFF LINE 


"| = 
ON 
FIELD OPERATION power (} 


de eee Hele = 





Command Key Lights 


These lights are controlled by the load I/O instruction. Separate load |/O 
instructions are used for turning on or turning off command lights. Once 
turned on, command lights remain on until a load I/O instruction turns 
them off, or until a system reset takes place. A plastic overlay is provided 
for the command lights so that appropriate labels can be assigned to each 
command light in order to identify the particular meaning given to the 
light by the programmer. 


INQUIRY | SYSTEM 
REQUEST] START 


ON START 


9 | 9 


STOP 


BRO360 


5406 FETMM ss (2/71) 7-109 
(Pages 7-110 through 7-114 deleted.) 


KEYBOARD ATTACHMENT 


The keyboard attachment is the interface between the processing unit and 


the operator keyboard. The attachment consists of five circuit cards. Two 
of these cards are MST circuitry and are two-high, four-wide cards located 
in 01-frame, A-gate, on B1-board, at L2 and M2 (B1L2 and B1M2). The 
other three cards are used to convert the keyboard SLT circuitry outputs 
to MST. These three cards are located at B1G2, B1K2, and B1K3. 


Keyboard/CPU Interface 


The keyboard console and attachment operate under program control. 


The attachment communicates with the CPU during interrupts; information 


is sent to the CPU main storage upon receiving a sense !/O instruction. 


The attachment operates on interrupt level number one, which is interrupt 


number four in interrupt priority (lowest level). 
All instructions are sent to the attachment on data bus out lines and 


control lines. The attachment decodes the instructions to determine whether 


the operation is a load I/O, start |/O, or sense I/O, and turns on a latch to 
set up controls for the forthcoming data information. 

The keyboard keys are disabled until a start 1/O instruction (with the 
appropriate bits active in the control code) restores them. Once the key- 
board is restored, and interrupts are enabled, information can be keyed. 
Pressing one of the keyboard keys causes two actions: 


1. Two bytes are stored in the keyboard attachment circuitry. 
The first of these bytes is a status byte that defines whether: 
(1) the key pressed is a data character key, acommand key, 
a function key, or a World Trade key; (2) the keyboard is ready; 
or (3) the key is a typamatic key. The second byte is the data byte. 
2. An interrupt request on interrupt level 1 is generated. 


If no higher priority interrupt is being serviced, the CPU honors the inter- 


rupt request and branches to the interrupt subroutine. The interrupt sub- 
routine must perform a sense I/O instruction to transfer the two bytes 
stored in the attachment circuitry into storage. The routine must also 
restore the keyboard and reset the interrupt request by issuing another 
start 1/O instruction. 


KEYBOARD ATTACHMENT- Introduction 
Keyboard Attachment 





Console 
Lights 


Field/Operation Lights 
Command Lights 

Halt Lights 

1/O Check Lights 


7-205 , 


Encode Board 






Alter 


Storage — 


CE Mode Selector 


Encode Matrix 


Keys (data/status) 


Alter Storage Mode 


7-203 


Interrupt Request 
Interrupt Enable 
Keyboard Restore 
Keyboard Parity Check 


7-207 





Instruction Decode 
DBO Register 
1/O Condition A and B 
DBO Parity Check 







7-206 


DBO 





Controls 
and 
Timing 


CPU 


‘DBI Controls 
DBI Outputs 






DBI 


\ 


7-204 


Interrupt, Status, Data 


BR0684 


5406 FETMM (2/71) 


7-115 


(Pages 7-110 through 7-114 deleted.) 


KEYBOARD ATTACHMENT -— Introduction ~ 5406 FETMM - (6/70) 7-116 
Load I/O Instruction Format 


LOAD 1/0 INSTRUCTION | | LOAD 1/0 (LIO) INSTRUCTION FORMAT 





@ Three or four bytes make up the load I/O instruction, 





The command code (two-byte field located at the operand one 
address and operand one address minus one) is sent from the 
CPU to the attachment on DBO lines. The rightmost byte 
(operand one address) of the operand is bit significant in 
turning on or off specific lights in the group defined in the 

N field. The leftmost byte (operand one address minus one) 

is not used. 


Op Code{ QCode | Command Code 
Byte 1 Byte 2 Byte 3 and/or 4 


@ The M field of the load I/O instruction is not used by the keyboard 


and may be any value. | 0 70 34570 70 7 


Pe NOY eee Ee 











e The load I/O instruction selects the keyboard when the device address 
equals 1 (hexadecimal). 










e The N field of the load I/O instruction is bit significant in the two 
low order bits and the high order bit (bit 5 of the O byte) may be 


either O or 1. : | Y 
Op Code = Y1 (hexadecimal) . N =010 LIO Field/Operation Lights 


e Thecontrol byte transfers the one byte field located at the operand Y can = 0011 or 





é : C d Code 

address and the one byte field at the operand address minus one sae a oe 01234 567 
(which is not used) to the attachment circuitry. 1 1XXX XXXX 

2 X1XX XXXX 

® This instruction is used to turn on or off field/operation indicators 3 XX1X XXXKX 
are 4 XXX1 XXXX 

or to turn on or off command indicators. 5 xXXX 1XXX 
This instruction causes two bytes of information to be sent to the key- | Bavicd Aaa 6 Cae ee 

; ; a he 7 XXXK XXK1X 

board attachment for the purpose of controlling lights on the console. This is DBO 3 bit on 8 XXXX XXX 





N field - Defines the group 
of lights to be turned on or 
off. Only bits 6 and 7 are 


The instruction is composed of three or four bytes. The first byte is the during 1Q cycle for 
op code, a Y1 (hexadecimal) for a load I/O instruction. The second byte pees, 
contains the device address (hexadecimal 1 for the keyboard), an M bit 
that may be either 0 or 1, and the N code that selects either the command 
lights or the field/operation lights. The byte field located at the operand 
address is transferred to the attachment for turning on or off individual 
lights within the group selected by the N code. 


The active bit (1) as shown will turn on the 
light in the light number column. The 
selection of a light or lights will automatically 
turn off the non-selected lights. All bits being 
zero will turn off all the lights. 






bit significant (bit 5 can 
be any value). 








M field is not used for 
the keyboard attachment. 
It can be either 1 or O. 


LIO Turn On Command Lights 






Load 1/O Turn On Command Lights 
e The N field equals X01. 


LIO Turn Off Command Lights 








Light No. Command Code Light No. Command Code 






















@ Two bytes of information are sent from main storage to the attachment; 01 0000 0001 0000 1001 
the first byte from the main storage address specified by the operand 02 0000 0010 10 0000 1010 

: 03 0000 0011 11 0000 1011 

one acres, and the second byte from the address of the first operand Pi sone 0106 io aggor 4400 
address minus one. 05 0000 0101 13 0000 1101 
06 0000 0110 14 0000 1110 

e The first byte is the active byte and selects the desired command key 07 0000 0111 15 OOOO 1111 
08 0000 1000 0001 0000 





lights to be turned on for one of the two following reasons: 


le The corresponding command key was pressed on the keyboard. Command codes other than those shown here will be accepted by 
9 The program desired to turn on the light as a communication the attachment, but no command light will be turned on or off as 
me oo g a a result. 
to the operator. : BRO685 


e@ The second byte of information sent to the attachment is not used. 


e The command light whose decimal label corresponds to the decimal 
value of the binary number in the rightmost byte of the operand ts 
turned on. 


e If only the eight basic command keys are installed, binary values more — 
than 8 in the operand byte are ignored. 


_Load 1/0 Turn Off Command Lights 


The N field equals X00. 


Two bytes of information are sent from main storage to the attachment; 
the first byte from the main storage address specified by the operand 
One address, and the second byte from the address of the first operand 
address minus one. 


The first byte is the active byte and selects the desired command key 
lights to be turned off for one of the two following reasons: 


1, The corresponding key was pressed on the keyboard when 
the light was on. | 
2. The program desired to turn the light off as a communication 


to the operator. 
The second byte of information sent to the attachment is not used. 


The selected command key function is no longer active after the 
program turns the light off as a communication to the operator 
(see 2, above). 


The command light whose decimal label corresponds to the decimal 
value of the binary number in the rightmost byte of the operand | 
is turned off. 


If only the eight basic command keys are installed, binary values more 


than 8 in the operand byte are ignored. 


Load 1/O Field/Operation Lights 


o 


The N field equals X1X. 


Two bytes of information are sent from main storage to the attachment; 
the first byte from the main storage address specified by the operand 
one address, and the second byte from the address of the first operand 
address minus one. 


The first byte is the active byte and selects the desired field/operation 
lights to be turned on. 


The selection of specific lights to be turned on automatically resets 
all the non-selected lights (hexadecimal 00 turns off all the lights). 


The second byte of information sent to the attachment from main 
storage is not used. | 


KEYBOARD ATTACHMENT - Introduction 
Test I/O and Advance Program Level Instruction Format 


TEST 1/0 AND ADVANCE PROGRAM LEVEL INSTRUCTION 


Test 1/0 (TIO) Instruction 
@ The keyboard attachment does not respond to this instruction. 
@ Issuing this instruction to the keyboard console results in a processor 


check with invalid O indication issued with the keyboard console 
device address. 


Advance Program Level (APL) Instruction 
@ The keyboard attachment does not respond to this instruction. 
@ Issuing this instruction to the keyboard console results in a processor 


check with invalid Q indication issued with the keyboard console 
device address. 


5406 FETMM 


(2/71) 


7-117 


KEYBOARD ATTACHMENT- Introduction 
Sense I/O Instruction Format 


SENSE I/O INSTRUCTION 


e Four bytes make up the sense instruction. 


@ The sense instruction selects the keyboard when the device address 
equals 1 (hexadecimal). 


@ The M and N fields of the sense instruction are not used by the keyboard 
and may be any value. 


@ This instruction places the data available in the keyboard attachment 
into the field in storage specified by the first operand address, 


The sense instruction is composed of four bytes. The first byte is the op 
code, a YO (hexadecimal) for a sense instruction. The second byte contains 
the device address (DA), and an M and N field that are not used. The third 
and fourth bytes contain the address of the low order byte of the two byte 
field where the sense bytes will be stored. 


Response to Sense Keyboard Instruction 


@ The code for the key position pressed is transferred from the attachment 
circuitry to the CPU. 


In response to a sense keyboard instruction, two bytes (representing the 
key position pressed) are gated on ‘data bus in’ (DBI) for storage in the 
two-byte field specified by the first operand address minus one, and the 
first operand address. 


The high-order byte stored in storage is a status byte and is bit significant. 


This byte defines the low-order byte that is to be transferred to the CPU on 
the next cycle. 

The second byte (low-order) in storage contains the unique bit configu- 
ration for the particular key position pressed. 

If asense keyboard instruction is issued by the program before a key is 
pressed (no interrupt request generated), the status byte will be: 


parity check 
1000 0000 
the second byte (data or function character keyed) will be: 
0000 0000 


SENSE 1/0 (SNS) INSTRUCTION FORMAT 


Op Code Q Code 
Byte 2 


Byte 1 


Operand 1 Address 
Bytes 3 and/or 4 


0 7 0 3 4 


5 7 O 70 7 


Op Code = YO (hexadecimal) 
Y can = 0011 or 

0111 or 

1011 


Device Address = 1 (hexadecimal). 
This is DBO 3 bit on during 10 
cycle for keyboard. 


M field is not used for the 
keyboard attachment. 


N field is not used for the 
keyboard attachment. 











Storage Address 






In response to a sense instruction to the 
keyboard, the bit structure shown below, 
will be sent to the CPU on the DBI lines 
for storage in the field specified by the 
first operand address portion of the 
instruction. The second byte is stored 
at the first operand address minus one. 









Parity Check Contains the coded 
Data Character Identifier representation of 
Command Key Identifier the key position 
Function Character Identifier that was keyed. 
See Key Codes. 


World Trade Identifier 
Keyboard Ready 
Typamatic Key Identifier 
Not Used 





BRO686 


5406 FETMM 


(6/70) 


7-118 


START 1/0 INSTRUCTION 


@ Three bytes make up the start I/O instruction. 


_@ The start I/O instruction selects the keyboard when the device address 
equals 1 (hexadecimal). 


@ The M and N fields of the start |/O instruction are not used by the 
keyboard and may be any value. 


@ The control code of the start |/O instruction causes the keyboard and 
attachment circuitry to perform the operations specified by the control 
code, 


This instruction is composed of three bytes. The first byte is the op code, 
a F3 (hexadecimal) for a start 1/O instruction; the second byte contains the 
device address (a hexadecimal 1 assigned to the keyboard) and the M and N 
fields (not used in the attachment circuitry); and the third byte contains 


the control code to provide control information for the keyboard operation. 


The control code of the start 1/O instruction is used by the programmer 


to: 

1. Reset previously sensed parity checks. 

2. Lock or unlock the keyboard. 

3. Enable or disable interrupts. 

4, Turn off current interrupt requests. 

5. Restore (unlock) the keyboard (required to prepare the keyboard 


for a succeeding key depression). 
6. Cause an interrupt request (see bit 2 in ‘‘Control Code”’ chart). 


The restore keyboard function, necessary to unlock the keyboard for a 
succeeding key operation, is accomplished by issuing a start I/O instruction 
with both bits 4 and 5 present. All bit combinations of the control field are 
valid and all operations will be performed if the appropriate bits are on, 
except that bits 2 and 7 on will not result in interrupt request being set. 


KEYBOARD ATTACHMENT-Introduction 
Start I/O Instruction Format : 





START 1/0 (SIO) INSTRUCTION FORMAT 


Byte 2 


Op Code O Byte 
Byte 1 






0 70 34 5 70 


Op Code = F3 (hexadecimal) 


Device Address = 1 (hexadecimal). 
This is DBO 3 bit on during !0 


cycle for keyboard. 





M field is not used for 
the keyboard attachment. 


__N field is not used for 
the keyboard attachment. 


I-R Byte 
Byte 


3 
Code 


7 


Control Code 


Not used (don’t care) 
Not used (don't care) 












Not used (don’t care) 
Not used (don’t care) 


Set interrupt request if enabled. 
CE diagnostic use: to check 

interrupt level for correct function. 
Do not set interrupt request. 










Reset parity check (if set when key was pressed). 
Do not reset parity check. 





Drop bail (lock keyboard). 
Do not drop bail. 


Pick up bail (unlock keyboard). 
Do not pick up bail. 






Enable interrupt request. 
Disable interrupt request. 


7=1 Turn off current interrupt request (used to exit 
from interrupt routine back to main program). 
7=0 Do not turn off current interrupt request (used 


to remain in interrupt routine for servicing 
further key depressions). 


BRO0687 


5406 FETMM 


(6/70) 


7-119 


KEYBOARD ATTACHMENT- Introduction 


5406 FETMM (6/70) 7-120 
Data Flow Operations 





WW 

































Start 1/O Instruction 











Key Depression 


1. Locks keyboard. 

2. Generates interrupt level 1 to 
CPU (keyboard interrupt request). 
CPU effectively branches from 


Power On or System Reset 






Load 1/O Instruction 
(can be executed any time) 
A separate load 1/O can: 


Purpose: 1. Sense I/O Instruction 


Transfers 2 bytes from the attachment to CPU: 


1. Lock keyboard. 
2. Disable interrupts. 


1. Unlock (restore) keyboard. 
2. Enable one keyboard interrupt. 










a) 1st byte is a status byte that is stored in the 
location specified by the sense instruction 


Example: SNS 0301 
result in storage: 


1. Turn command lights 
on or off, or 


current program to keyboard service 0300 0301 (SNS operand one address). “Tuk field operated 
: program routine. Data Status b) 2nd byte is a data byte that is stored in the 
Alpha-Numeric (data) | Data [Status _| lights on or off. 
















3. Two bytes are generated in 
the encode board logic and 
stored in the attachment. 


lower adjacent location to the status byte 
(operand one address minus one). 


0 7 0 7 





Special Character (data) 
and 
6 Function Keys 





2. Examine Status Byte, Process Data Byte: 
Command Keys 











e Tab a) Function key-program accomplishes 
8 keys (option- e Shift (2 keys) function requested. 
ally 16) for pro- @ Backspace b) Command key-program takes action pre- 
gram control e Program Start designated for this command (command 
e Return 10 Numeric (data) keys permit choice of program alternates). 
e Space and 


c) Data key-program converts data byte from 


4 Function Keys encode board into an EBCDIC character. 





e Enter + . Start 1/O Instruction 
@ Enter - Purpose: To ready keyboard for next key 
@ Erase 


depression and to exit from keyboard 
interrupt routine: 






@ Decimal Point (.) 





a) Unlock (restore) keyboard. 
b) Enable or disable interrupts. 
c) Turn off current interrupt request. 


cS 


ncode 








Key Status and Data 








CPU 











Keyboard Data Latches 












Data and Sense Bytes (DBI) 
Instructions (DBO) 


<f Control Lines | 


1/O Attachment 
Interface 








0-9 or A-F 
Keys 


Keyboard 
Attachment 
Logic 





Ist Key Depression 





0-9 or A-F 


a 2nd Key Depression ey: 





Controls and Storage 












Alter Storage 
Operation 


m 


(not under program control) 


CE Panel 


1. CE mode selector to PROCESS. 
a) Press SYSTEM RESET. 
2. CE mode selector to ALTER SAR. 


First Key Depression 


CPU Start (result of second key depression) 


Loads 1st hexadecimal character 
into encode board data latches 
and causes keyboard restore. 


cond Key Depression ; 
Second Key Depression Causes the CPU to run for one machine cycle, 


during which: 








Loads 2nd hexadecimal character 
into encode board data latches, 
causes a keyboard restore anda 
CPU start. 


b) Set data/address switches to 
starting address. 
c) Press START (once only). 
. CE mode selector to ALTER STORAGE 
(system clock is stopped at clock 9). 


1. The byte in the keyboard data latches is 
transferred to the storage location specified 
by the CE Panel. 

. The keyboard data latches are reset. 


Note: In alter storage mode, only 
keys O through 9 and 
A through F are valid. 








Po 


cbt 


CPU ATTACHMENT CONSOLE 


B A 6 DBI 7 
Reg =F a 6G rman ae 










Channel 
Controls 
























Channel Control In 









Channel|] pt 
Out er 


& Mat n 
e Storage SDR 


Channel Control Out 


Interrupt 
Request 


4) Controls 





LSR Select 


—mmmmaeetii) Command 
: ~ BP] indicators 





Command 


SAR SAR 
and Field 
Indicator 


Hi Lo LSR LSR 
Buffer 
Controls 


KEYBOARD | ff : 








Field 
Indicators 





DBI 
Parity 


K 
(33 Lemmmmmmmmmmaty) ENcode 


Board 


Contacts) 





ontrols 


|| Bail 








DBI 
Assembler 





Bail 
Restore 


Magnet 








Instruction 
Buffer 
Key- 
board 
Ready 
Indicator 


PKOO7 


KEYBOARD ATTACHMENT -— Introduction 
Data Flow 5406 FETMM (6/70) 7-121 


KEYBOARD CONSOLE-Introduction 
Keyboard Timing 


KEYBOARD TIMING 


The figure at the right shows the basic keyboard timing. The variable 
electrical and mechanical timings are shown in relation to the maximum 
time between key cycles. Their duration is determined as follows: 


Elastic Diaphragm Switch (EDS) Closure—Closes as soon as the interposer 
clears the latch spring. It remains closed until the restore is nearly com- 
plete. Time of restore is determined by the system and is, therefore, 
variable. 


Bit Lines—Coincident with the EDS closure. 


Character Ready—Brought up by the bit lines and reset by ‘bail contact.’ 
Restore is controlled by the system; thus the rise of ‘bail contact’ is 
variable. 


Restore Magnet—De-energized when the system accepts data and picked 
when the bail closes the bail contacts. Mechanical travel time of the bail 
determines the time the contacts close. 


Bail Contact Signal—Begins when the restore bail closes the contacts and 
is held up by a circuit delay after the contacts open. The duration is 
variable depending on the time the contacts are held closed by the restore 
bail. | 


Ball Interlock—The duration is determined by the operator releasing the 
keylever. 


Bail Interlock—The duration is directly related to the mechanical travel 
of the bail. 


5406 FETMM = (6/70) 7-122 


Ce Functions 
Key Pressed Next Key 
| Cycle May 
| | Start Here 
40ms Max. 
EDS Closure | Saeee 














Bit Lines 





Character Ready 


| | 
7 SS | , 
| 





Restore Magnet 








Bail Contact Signal 


| 
| 

Mechanical Functions | 
| | 

| 

(Key Released) 7 

| 





Ball Interlock 





Ky Oa LOCK eC en | 





Bail Interlock 


* EDS closure must be 18ms to 28ms 


BR1391 


Chapter 2. Functional Units 


INTRODUCTION TO FUNCTIONAL UNITS 


Chapter 2 contains the functional units of the keyboard attachment. The 
first page of the chapter is a board layout of the keyboard attachment. 
It is broken down into cards and contains the following information: 


1. Card locations. 

2. Circuits found on that card. 

3: ALD page reference numbers that describe the circuits found on the 
card. 


4, Card type number. The part number of the card will change each 
time that the card has an engineering change to it. The card type 
number however, will always stay the same. 


The card location number appears on each page, or section of a page, that 
describes the circuitry on that card. For example, M2 on a page refers to 
the DBI assembler. 


Symbols 


There are two symbols that must be understood in order to read this chap- 
ter. They are: 


1. a Numbers in squares. 
2. © Letters in circles. 


If only one of these symbols appears on a page, it will be numbers in 
squares. They are placed next to a functional unit, and correspond to the 
same number in a square on the facing page. Next to the symbol on the 
facing page, an explanation of that functional unit can be found. 

If both numbers in squares and letters in circles are found on a page, 
the numbers refer to a reading order of the basic operation of a group of 
functional units. These numbers refer to corresponding numbers on the 
same or facing page, that when read consecutively explain the data flow 
between functional units. The letters in circles refer to operation of just 
the functional unit, the same as numbers in squares do when they are 
the only symbol on the page. This is the only application for letters in 
circles. 


KEYBOARD ATTACHMENT—Functional Units 
Introduction to Functional Units . 5406 FETMM (6/70) 7-201 


KEYBOARD ATTACHM 


Board Layout 





ENT—Functional Units 


KB SLD To MST Convert 


1. 
2. 


Keyboard bits 3-7 


Drop bail pulse 


ALD page PK023 
Card Type 5026 











1. Keyboard bits 0-2 


2. Alpha-numeric and typamatic 





KB SLD To MST Convert 





Keyboard Adapter No 1 


. Keyboard bit P 






. DBO register 





. Bail contacts 
ALD page PKO21 
Card Type 5026 







: DBO decode 








. Command latches 








. Instruction latches 


. DBO parity check 








SLD To MST Converters 





6. Condition A 





ALD page PKO22 
Card Type 5026 









ALD Pages 
PKOO1 
Through 
PKOO7 






Card Type 5018 






Keyboard Attachment Board B1* on Gate A (A-B1) 


(card side) 


3. Condition B 














Keyboard Adapter No 2 





. DBI assembler 







. Interrupt polling 






. Field indicators 





. Bail latch 


6. Bail magnet control 





1/O check 


8. Parity check latch 





. Gate command 
indicator 


ALD Pages 
PKO11 
Through 
PKO15 


Card Type 5019 





































5406 FETMM = (6/70) 7-202 


V2 


*Board B1 also contains: 


1. 
2. 
3. 


Channel banks. 
Data recorder attachment. . 
CRT attachment. 








Note 1 — Key position Re9 is shown. Re9 and Re11 | 
are located below the erase keybutton and = 
are available for WTC extensions (See 7-106). 
Note 2 — Tab and backspace keys have typamatic © 
function (See 7-316). “ A 
Inquiry 
Request 
Switch 
(on console) a 
* 
Function Keys 
Command Key Bit 


Latches 





Alpha-Numeric and 


Special Character ie | | 


27@ 81* Al 07 TTAB See 
Shift Note 1 
Key (2) 





@— Lower Case X-|-X-|-|-{-|-|- -|- _— 


PS Not : 
@— Lower Case |~X-|-X-|- J-]-|J- -J|]--7— 








0 
1 
2 
3 
Encode 4 
Board 5 
Diode 
Matrix 6 
7 
lel 
Group H (hex character) f= 
Inquiry Request is 
Group A (command) i 6 
Group B (function) TTT] | 
cadeeste oe EE Te aie 
Typamatic 
Group T (typamatic) DP 14 
sy tT TTL ll 
i> See =~ 
=a © Fit! tNote2! EY 
Bail Contacts (N/O) _- Lt = 
Make when bail | : 
magnet is dropped. PS R_ Bail Bar 


Bail Magnet 
Picked = keyboard unlocked 
B Dropped = keyboard locked — 






Bail 
7-207 Magnet 


Control — (5) 7 


Bail Contact No. 2 A Bail Contacts ss 
Bail Contacts (closed) 


19 


iB L 
Fs F 
& 
a 2 
7 
FF 
cd 
iA 
5 
4 
Cd 
i aL 


Trailing Edge 
of Bail Contacts. 45 


Sys Reset Sw. 


16 
Alter Mode Sw | 17 
Duration extended 
to 80 MS. 
EXT SS 
7-207 Inq Req Reset is 


KEYBOARD ATTACHMENT—Functional Units 
Encode Board 


KB Bits P, 0-7 


Fay eccaiate ne elec te eh ce i ee a 


eng awa chien ins mead 


ee 











15 


17 


4-7 


17 
4-7 


11 


10 


18 
16 


14 





cad 


KB BitP 7-204 


KB Bits P, 0-7 7-204 
Bail Contacts Modified 7-204 


Drop Bail Pulse 
7-204 


A 


(2nd % Byte) Alter Char 


; Ready % @ 
Fi FL 7. 
for} a 


Char Ready 7-204 





erg ee World Trade 7-204 


Alpha Numeric. 


| 7-204 
(1st % Byte) | : 
[jor|} Ft 
) CK008 






Function 7-204 


~~) 


Command 7-204 


Typamatic 7-204 


5406 FETMM __ (6/70) 7-203 


KEYBOARD ATTACHMENT~—Functional Units 


DBI Assembler 
7-207 Interrupt Polled KB 
7-207 Interrupt Poll 
7-206 €B Not 1st Cycle pt 
A oo 
7-206 SNS Data Latch | emp! 
ay FL 
KC122 Clock 2 7 
KC122 Clock 6 a eel 
1208 POR or Ss eset or 
A | DBO KB Bit 7 


PKO14 






SIO, Sample DBO C15, IR Cycle 
(Not) Typamatic Latch 


Clock 3 To Chan 


KD121 EB 1st Cycle 


7-207 Alter Storage Mode 

7-207 KB Ready 

7-207 Parity Check Latch 
Alpha Numeric 


Alter Char Ready 
Drop Bail Pulse 


) . Char Ready 





CV 


PKOQ22 


ce 









. OE 
| World Trade Char en 
‘i ) FunctionChar od 7-207 
B . Command Char | 
PKO12 
Even 
ein 7-203 
to MST ; PKO1 1 
Convert Loo KB Bits, ak a rem Bit (only) PKO11 
fra f PKO21, 22, 23 A §6KB 0-7 Bits 


Gate Data to Bl 


Inquiry Req Reset 


EB 1st Cycle 


Any Char 


7-207 





25 


(gate data to BI) 24 


7-203 


7-207 
Gate Status to Bl 


7-205 


7-206, 7-207 


7-207 


7-207 


7-207 


1st EB Cycle Even: 


KB Bits Even 
KB P Bit Correct 
KB 7 Bit 
KB6Bit 
KB 5 Bit 
KB 4 Bit 
KB 3 Bit 
KB 2 Bit 
KB1Bit 
KB O Bit 


23 


22 
21 
20 
19 


17 


14 
13 
12 
11 


=_ 
© 


OrF~NWHKHOAON WO 


Co Oo 


24 
10 
23 
20 
23 
24 


22 


24 
19 
23 


25 
11 


23 
24 


22 


24 
12 
23 
13 
23 
24 


22 


24 
21 
23 
14 
23 
24 


22 


24 


5406 FETMM = (2/71) 7-204 


tad 







DBI Assembler 





P Bit 
(generate) 





M2 


(Interrupt Request) 


Le Le ee te Te aE 


DBI 0-7, P 


eet P Ee Peer ae 


Be 





sweet 


| 
| 
| 
| 
| 
| 
= 


First byte from the 

storage address 
specified by the Control Lines 

operand 1 address 


active 









O13 a Input Lines} x inactive 
7-206 DBO KB Bits 0-7 = reset 
7-204 EB Ist Cycle oN | PERE Ee [es hoppapapapes Halt Code 
Spe DEO CaS —— 8 efofofofofofor-| FT] T | Pile ies 
10 Field Ind Latch 7 | oyofolojololo| =} 11 1#l_t lol 16 Hal - 
40 efofofofefof ter Tr ye 6 
Tio command Off Latch | fofofojojoj*jo| | | fat [ jols| : c 
Bae ee en Oo OOO pe Ty ee O) i 
‘ . | fefefofofofol= Tt TT Tat [fol i 
A,B,C, D,1,2,3,4,5 yes jofofojojol*fojo} | | | | | |sfol 16 
. Field | | fofefofofol-fofol TT fat T foley ip 
7——| | Operation | ofefolol=fol*( | 1 | I [fol 16 5 
en ac oa, EAR Ea | fotolelofotfe- CCL Ct re em 
[ Field Ind 0 = | : =" * 
_ SS Ns | , ) fefofotetet=tafel Ty tat fet} Si 
| ! 8 ; | | | eel 7 | Lights 
. 9 , | | | | lofo}olo;ol= (sie) Ale) | to) a 17 
| MR ee | ofofof=fofofoy TTY [Ti fo}—f t= Ko; 
: PKOTS : eos j 1 ofofol=fofojol | | i#| | fol= \— 17 
| 3 os | Field Ind 2 | | | Ec ee ee is ee , : 
| en PH | | | ofojojo{*fofoj*| | {| {#] | fol 17 bight 120 Attention 
| : — | FereT | | fefefofoltof-fot TT TT fo oe) Rene Gee 
> | — ' ~for| iy | a a \— 17 Fon 
: : : ere eet fete] ¢ tet te | : 17 [DISK DRIVE 2 | 
Ko eee ep] BREET 
: * * * 
—a pi | eee ree rte 
| *% * * ¥* ‘ . 
11 
aa ofofofol=[*fol={ TT fet T [ols , SB Reedy 
| 7 | fofofotol tt fol TT fo} 4 =f : 
Gate Command Ind On ofotofol=|=t*jol | t fw] | jolts 
Seppe) | Bee erEt ECCT ERE 
j | a oe ee K | 
| 1 7 | fetter Tr 
| 9 a |Gate Command Ind Off 4, fo} 0 [0 | - fofojofo} | | f#t | | fe] : 
Bf ifs PK3, 5, 6 3 | PK003-006 L2 : | PB131-161 


KC152 Gate Console Bits Hi 
Gate Console Bits Hi KE131 
Alter Start Pulse sh? 








(KBD) Alter Char Ready 


Gate Console Bits Lo KF131 





Gate Console Bits Lo 





KEYBOARD ATTACHMENT-—Functional Units 
Console Lights | 5406 FETMM _—_ (6/70) 7-205 


- KEYBOARD ATTACHMENT-—Functional Units | 5406 FETMM = (2/71) 7-206 
Initial Selection 











DBO Reg 
| p Even Parity Even Parity 
| o| 10 | | ) ) RN111 Chan 1110 Instr i 
| ; ‘ KC102 Chan 1 Early PhaseC 4, : 7-204 
DBO BitsP-7 FX 3 P-7 KD121 Chan 1 EB 1 Cycle : PO or Sys Reset 7-205 
4 DBO KR Bits 2-7. 7-207 KD121 Chan 1 EB Not 1 Cycle 5, 7-207 
5 5 . KD121 Chan 1 1R Cycle 
6 | Must be active to turn on nnn DD | 
7 DBO KB Bits 0-7 7-205 Status of Input Lines : Must be inactive to turn on KB151 Chan 1 Check Reset__ 493 16 PO or Sys Reset or Bail 
Resets active status 










| S10 Latch 


O thru 16 | J PKOO7 
= 11}12]13}14] 15} 16 comm () thru 16 sat | 7-206 
7 : 7-207 
Chr TEE E 7-204 
SNS Data Latch I oe | 
DBO KB Bits 0-7 ° . =a : 7-205 
Chan 1 S10 Instr 2 | : 
Chan 1 Clock 5 3 e L1IO Field Ind Latch ; * 6 
Chan 1 Sample DBO 16 3 . | | | 7-205 
se TE 1OIN S SE ee 11 : LtQ Command On Latch J | 
7-204 Bail Contacts 12 z 27 
Wiis (aRichs US 5 7-205 
Chan 1 L10 Instr 13 | | , 
15 ; 
10 


Chan 1 I-O Cycle PKOO7 Sample DBO Clock 5 7-205 














Clock 2 





PKOO7 a EB Not First Cycle 7-204 


| = mn oi. : PKOO2 : 
8 | 








13 for| L2 
18 i mae : | |-O Condition B 
PKOO6 oe 
a 10 Cycle x | 
| PKO15 
9 
A N ! (DBO) Even Parity 
; PKOO2 | 
19 10 Cycle 
PKOO2 | enol IR Bae | = 
ue IR Cycl : 
B 22 aa eal A Time EB 1st Cycle — 27 
24 EB 2nd Cycle | 23 == 
== Za 24— 
DBO Parity Ch | , 
a EB Cycle ra moe | 25 
A FL ; PKO15 
" Eo) A , | ’ 
PKOO2 PO or Sys Reset : | 15 
PKOO2 
Chan 1 Check Reset oR] 
26 
27 | 
28 | 
PKO02 (PO or system reset) This is a high level representation M2 
= Ghan 1 CGhack Reset of the DBO parity check latch. | 


7-206 


7-206 


7-204 
7-204 
PKO22 
A PKO12 
7-204 
KD141 
7-204 
7-204 
7-204 
7-204 


KEYBOARD ATTACHMENT-—Functional Units 


Control Latches 


DBO KB Bit 2 
DBO KB Bit 3 
DBO KB Bit 4 
DBO KB Bit 5 
DBO KB Bit 6 
DBO KB Bit 7 
Alter Storage Mode 
Chan 1 Clock 4 
Sample DBO Clock 5 
SIO Latch 

IR Cycle’ 

PO or Sys Reset 
Typamatic 

Any Char 

Alter Char Ready 
Clock 2 

Drop Bail Pulse 
Interrupt Poll 

Bail Contacts 

Gate Data To Bl 
Gate Status To BI 
KB Bits Even 
Channel Check Reset 
Clock 3 to Chan 


On OOF WN 


© 


11 
12 
13 
14 
15 
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 


11 
12 


10 


21 
13 
19 


13 


20 


17 


18 
22 
23 
24 













Vv 2 3 
Alter Storage Mode 
7-204 
| Pre Bail CKOO9 
i | 
A ‘ aes 
M2 
PiK007 
Inquiry Req Reset 7-203 
Interrupt Polled KB 7-204 
A 
Inter Enable 
A : FL 
Inter Req 
. 7 KB Ready /-204 
qo atch . * 7-205 





° } FL I 
Bail Magnet Control CKO09 
| CV 
N i 
PKO14 
SIO, Sample DBO Clk 5, 1-R Cycle 7-204 


ee c 7 
Reset Bail 
PKO14 : (DBI) 


Parity Check Latch 7-204 


KB 10 Check 








A ~PKO14 


5406 FETMM (6/70) 7-207 


Chapter 3. Operations 


INTRODUCTION TO OPERATIONS 


Chapter 3 contains the detailed flowcharts and timing charts of the operations 
performed by the keyboard attachment. 


Flowcharts 


The flowcharts contain three levels of information. By reading down the 
heavy dark lines, the reader can learn the major objectives of the operation. 
The second level of information is obtained by reading the information in 
the boxes that branch off the heavy dark line. The information that is con- 
tained in each block in a heavy dark line is explained in the blocks that 
branch off from it. The third level of information is contained in the note 
blocks (open ended blocks) that branch off the second level blocks. 
Information in these blocks is intended to explain why an action has been 
performed. 


Timing Charts 


The timing charts in this chapter are to be used to supplement the informa- 
tion found in the flowcharts. 


KEYBOARD ATTACHMENT~— Operations 
Introduction to Operations | | 5406 FETMM = (6/70) 7-301 


KEYBOARD ATTACHMENT-— Operations 
Load I/O Instruction Flowchart (Part 1 of 2) 








Load !/O 
Instruction 
















31, 71, or B1 
decoded during 


oak a CPU I-op cycle 
indicates a 
load 1/O. 
A . Sample O 
code for 
1-0 device address. 
Cycle 


. Check DBO 
register 
parity. 


. Determine 
condition code 
and send it to 
the CPU. 


. Decode the 
N field of the 
OQ byte and 
set a LIO 
latch. 


eRe 
Ree 








PKOO7 







‘Chan LIO instr’ 
is activated 
in the attachment. 


PKOQO7 


At clock 5, with 
‘ch channel DBO’ 
decode the 
device address 

of the keyboard. 


PKO06 


Activate 
‘1-O instruction’. 


PKOO2 


At clock 5C the 
parity of the 
DBO register is 
checked, and the 
condition code is 


determined. 










If the parity is 
even, the DBO 
register is 

latched up. 


fe) 1/O 


Load 1/O I-O Byte Condition Condition Condition 


Incorrect DBO Parity 


Device address not recognized 
or N field invalid. 


Ccrrect Device 
DBO address Rejected 


Parity recognized 
Ana Load I/O 


N field Accepted 
valid. 


Incorrect DBO Parity 


Load 1/0 , E-B Cycles 


-Correct DBO Parity 








5406 FETMM = (6/70) 7-302 


fad 


N Code Yes 
X01 










Set the 
‘LIO command 
.on latch’. 





N Code 
X00 





Set the 
‘LI1O command 
off latch’. 


~ 





Set the 
’LIO field 
ind latch’. 


No 


Any other N code 
is invalid. A 
processor check 


stop would occur 
. with the processor 
- check light on. 





Page 7-303 


X = bit not checked. 





[A Page 7-302 


Before taking the B cycles: 


1. A condition code of B must be 
sent to the CPU. If not, an 
I-R backup is performed. That 
is, the l-op and I-OQ cycles will 
be repeated until a condition 
code of B is decoded and 
sent back to the CPU. 


2. The CPU will (depending upon 
the op code) take either: 
an |-X1 cycle, or an |-H1 
cycle and an I-L1 cycle. 





st 















Po, 
Take EB 1 cycle to : 
select desired field ! PKOO1 
indicator(s) to be ; - 
turned on or off. ‘Chan EB 1° line » 
is activated. 
N code | Yes 
EB 1 X01 
Cycle 
> 





Select the 
desired command 
key indicator to 

be lighted. 


N code 
X00 





Turn off the 
selected command 
indicator. 


Select the desired 
field indicator(s) 
to be lighted. 






KEYBOARD ATTACHMENT-— Operations 
Load I/O Instruction Flowchart (Part 2 of 2) 








EB 2 
Cycle 








X = Bit not checked. 


Take EB not 1 
cycle to select the 
desired field 
indicators to 
be turned off. 














End of 
Operation 









‘Chan EB not 1’ is 
activated. 


If the N code was 
X01 or XOO, this 
EB cycle is taken 
but no information 
is transferred. 








Select the desired 
field indicator(s) to 


be lighted. 





5406 FETMM = (6/70) 


7-303 










LOAD 1/0 INSTRUCTION TIMING CHART 
CPU cycles for 


addressing: 
I-X1, or |-H1 
and I-L1. 


Load 1/O Operation 
EB 1 Cycle EB Not 1 Cycle 


0123 45 67 8,0 12345 67 8 


1-Q Cyc! 
e The CPU decodes the op code of the instruction and activates the = 


control line ‘chan LIO instr’ in the attachment. ALD Page |0 123 45 6 7 810 123 45 6 7 8j0 
@ The attachment takes an I-O cycle to: 1. Chan LIO Instr PKOO7 eae te 


1. Decode the O byte for the device address. 

2. Determine the condition code and send it back to the CPU. 

Si Decode the N code of the O byte to set a load I/O latch in the 
attachment. 






: eae aces pe Oke eee Bae Ek Par RE AE eS Ea a NR EE 


| 
f 
* 
4 


ee SS TERESI TT ee eRe TREATS 
Fey Ome ae yn eee t Coy Gish So Ree Pia ee eee ey 
treo CT nee MEE hoe mene rn D 


SRSERL aek Pet ee Reece ORC 


7 eT err ees 
Den SARA AE ET MOR ACT Be BO 
Poe rrem rey erent TNT CET EP a 

Perr pte ae Oe ke 


Ee 


@ Take EB cycles to: 


1. Turn on a command indicator. 
2. Turn off a command indicator. 
3. Turn on field indicator(s). 


EB Cycles 


The CPU gates the first byte from the main storage location specified by 
the operand one address through the DBO register to turn on or off the 
desired command indicator or field indicator(s) latches. The output of the 
latches control the on or off status of the lights. 

If a load I/O instruction is issued to turn on or off command lights with 
codes other than those shown in ‘‘Weighted Codes,’”’ the instruction is 
accepted, but no command lights are turned on or off. 

A load !/O instruction issued to turn on field indicator(s) resets the non- 
selected field indicator latches. All bit combinations are valid for turning 


on the individual field indicators (all eight indicators can be turned on with 9. Chan EBNort 
one load I/O instruction). When all bits are zero, all of the field indicators 10. Gate Command Ind One PKO15 
are turned off. 11. (command indicators) PK0O04 


The second byte transferred from the main storage location specified by 
the operand one address minus one is also gated to the DBO register, but 12. Gate Command Ind Off =| PKO15 


it is not used. 13. (Field Indicators) PKO15 


Note 1. Reset at clock 2 of the next I-O cycle. 
Note 2. Will be reset by next ‘gate command ind off’ pulse. 


Note 3. Will be reset by the next ‘LIO field ind latch’ pulse. 


BRO688 


KEYBOARD ATTACHMENT-—Operations 
Load I/O Instruction Timing Chart 5406 FETMM (6/70) 7-305 


KEYBOARD ATTACHMENT-— Operations 
Sense I/O Instruction Flowchart 


Sense 
Instruction 









30, 70, or BO 
PKO07 



































1-Op decoded by CPU 
Cycle during an |-op Activate 
cycle indicates ‘chan SNS 
a sense instruction. instr’ in the 
attachment. 
A 
. Sample O code 
for device address. ssl 
- Check DBO At clock 5 with 
1-0 register for fel pb ae eo 
; tive, decode 
Cycle parity. ees: 








the device address 


3. Send a condition of the printer. 


code of B to 
the CPU. 






PK0OQO7 


Set the 
‘SNS latch’. 


PKOO6 


Activate 
'1-O instruction’. 


PKOO1 


At clock 5C, the 
parity of the 
DBO register 
is checked. 












A condition 
code of B is 
sent to the 

CPU. ‘KB 1-O 
condition B’ is 
activated. 

















lf the parity 
is even, the 

DBO register 
is latched up. 






EB-1 
Cycle 


EB-2 


Cycle 


End of 
Operation 




























1 
Before taking the.B cycles, the CPU will (depending 
——- == upon the op code) take either: an |-X1 cycle, or an 
I-H1 cycle and an |-L1 cycle. 
Take EB 1 
cycle to gate At clock 5C, the 
the status PKOO' parity of the DBO 
byte (in the Activate register is checked. 
DBI assembler) ‘chan EB 1’. if the parity is even, 
to the CPU. the DBO register 
PKO14 will latch up. 





Activate 
‘gate status 
to BI’. 







‘SNS latch’ on 
and ‘chan EB 1’ 
AND to activate 
this line. 














The status 
byte is gated out 
of the DBI 

assembler, 
















At clock 5C, the 






Take EB Not 1 











cycle to gate PKOO2 parity of the DBO 
hed b os register is checked. 

3 : soe Activate If the parity is even, 
: ‘EB not 1’, the DBO register 

assembler to Sa 

the CPU. PKO15 will fatcn up. 










‘SNS latch’ on 
and ‘EB not 1st 
cycle’ active AND 
to activate this 
line. 


Activate 
‘gate data 
to BI’. 










The data byte 
is gated out of 
the DBI assembler. 





5406 FETMM 


(6/70) 


7-306 


SENSE 1/0 INSTRUCTION TIMING CHART 









CPU cycles for 
addressing: 
I-X1 or I-H1 

and |-L1. 


Sense Operation 


The CPU decodes the op code of the instruction and activates the 
control line ‘chan SNS instr’. 


|-Op Cycle 1-CQ Cycle 


ALD Page ]O 123 45 6 7 8/0 123 4 5 6 7 8/0 


PKOO7 


@ The attachment takes an I-O cycle to: EB 1 Cycle EB Not 1 Cycle 


1. Decode the QO byte for the device address. Line Title 012345678]/012345 67 8 


2, Send a condition code of B back to the CPU. 4: han CNG AAE 
3. Set the ‘SNS latch’. , 


2. |I-O Instruction 





PKOO6 
@ The attachment takes an EB 1 cycle to gate the status byte out of the 


DBI assembler to send it to the CPU. 3. (decode DA) 


PK0O07 


4. KB 1-0 Condition B PKO15 


e@ The attachment takes an EB not 1 cycle to gate the data byte out of 
the DBI assembler to send it to the CPU. | 5. SNS Latch 


6. Chan EB 1 


PKOO7 


EB Cycles oe 3 
y 7. Gate Status to BI 


Prior to the EB cycles, the data and status bytes (generated by a previous:y 
pressed key) are stored in the encode board. The status byte is the first see 
byte to be gated to the CPU. This byte identifies the type of key that was | 9. Gate Data to BI po pKOIS fo 
pressed. The CPU stores this byte in the field specified by the operand | | | 
portion of the sense instruction. The bit significance of this byte makes the Note 1. Reset at clock 2 of the next I-O cycle. 
program aware of the type of data that is contained in the data byte. 

The data byte is gated to the CPU during the EB not 1 cycle. This byte 
is stored at the operand address minus one (as indicated by the operand 
portion of the sense instruction). The program in the CPU uses this data 
byte as a displacement, and adds it to a base address. The resulting address 
points to the core location that contains the EBCDIC code for that key. 


I et 
ee . Pet 
Sei a ee 
ee we at eS ; 
BS nae cs Be i 
ie Be et ; By 
Ban pr Reg 2 a 
ey Be B ag a 
he oT + Ee ma 
“het a es a Bi 
be oe, cas ae pad 
ae ea ca. Be oe 
cd Ay a z 
a ae s Fi 
ae ad an ay a 
a Re 23 Gy 
a Se te fa 
ai oe re ry 
A : we ; em 
Bag Bo 2 in ec 
cone oo ee > A 
ee on a ae es 
x pee ees ve ~ 
b: So ie s ~ 
ai ea x Ae : 
_ oN a i : 
we oe os if: 4 
ES oa a i BS 
Me ea Pa ot 3 
ae Eis es <7 nf 
Bae re ra 4 3 
Bo a Fea ae th 
2 ca aa : 
3 Se & a a 
Bed S = ; 2 
se oe Be a 4 
. ie ee fe Be : 
a 2h “3 ie fs 
a: i me a 
roa ue Med : ral 
we 3 "Be es 
a Roos A i a 
a es a) Pg fa 
ct pe * i a 
sae a a oe i 
a free ed ‘ The 
ee ae be eae 5 
tot ce ced . rt 
Ree Reon a4 aR eae 
7 ord pre an 
he ey Ex 3 
4 ie po Pe : 
eae a He, a F 
Bat Pe < st 
vs oe y a ; 
ae Pe ed au Be 
ron ag na Pr te 
a i es ‘i fe 
3 Er ube is 
Ee ae a a) S 
Be ae eo s ne 
BE pra aa ve is 
as ae oa res gr 
ae oe pos oe oes 
py 
ca 
at 


fo 


BRO689 


KEYBOARD ATTACHMENT- Operations | 
Sense I/O Instruction Timing Chart 5406 FETMM (6/70) 7-307 


KEYBOARD ATTACHMENT~— Operations 
Start I/O Instruction Flowchart 


l-Op 
Cycle 


|-O 
Cycle 









Start 1/O 
Instruction 






F3 is decoded 













during a CPU 

l-op cycle 
indicating a ‘chan SIO instr’ 
start 1/O is activated in 
















instruction. the attachment. 


. Sample O code 
for device 
address. 


. Check DBO 
register parity. 






PKQOQ7 


At clock 5 with 
‘ch sample DBO’ 
active, decode 
the device 
address of the 
keyboard. 





















3. Determine 
the condition 
code and send 

it to the CPU. 





PKOO7 
Set the 
‘SIO latch’. 

PKOO6 


Activate 
‘!-O instruction’, 


At clock 5C the 
parity of the DBO 
register is checked, 
and the condition 

code is determined. 













if the parity is 
even, the DBO 

register is latched 
up. 


SIO |-OQ Byte Condition 


Incorrect DBO Parity 


Device address not recognized or N 
field invalid. 


Correct 
DBO 
Parity 


Device 
address 
recognized 
and 
N field 
valid 


Incorrect DBO Parity 


Start 1/O 


Start 1/O |-R Byte, 
and 1-O Cycle 
Condition 

Correct DBO Parity 


I-R 
Cycle 


1/0 
Condition 





5406 FETMM (6/70) 7-308 











Before taking the I-R cycle a condition code of 
B must be decoded during the |-Q cycle and sent 
back to the CPU. If condition code B is not 
decoded, !-R backup will occur; that is, l-op 
and |-O cycles will be taken until a condition 
code of B is decoded and sent back to the CPU. 








1.’ The I-R byte of 
the start I/O instruction 

is sent to the 

attachment. 










At clock 5C the 
parity of the 
DBO register is 
checked. If even 
parity is found, the 
DBO register will 
latch up. 









PK0O07 
| Activate 
‘chan IR cycle’. 


At Clock 5 the 
IR byte enters 
the DBO register. 

The byte is decoded 


. The attachment 
decodes the 
byte and sets 
or resets the 
appropriate 
latches in the 
attachment. 
















Bits 0, 1 - Not used (can be on or off). 





to check for the Bit2 - If on, set interrupt request- 
active bits. if enabled. 
This flow chart Bit3 - on - Reset parity check. 
illustrates the use Bit3 - off - Do not reset parity check. 
of bits 5 and 6 to Bit4 - on - Drop bail (lock keyboard). 
activate ‘Kb ready’. Bit4 - off - Do not drop bail. 
Bit5 - on - Pick up bail (unlock keyboard). 
. Bit5 - off - Do not pick up bail. 
Ss Bit6 - on - Enable interrupt request. 
Bit6 - off - Disable interrupt request. 
Bit7 - on - Turn off current interrupt request. 
Bit7 - off - Do not turn off current interrupt 


At ‘sample DBO clock 5’, 
set the ‘pre-bail’ and 
‘inter enable’ latches. 














request. 


End of 


Operation 





The ‘pre-bail’ latch 
set, sets the 


‘pail’ latch. 
1/0 


Condition 


The ‘bail’ and 
‘inter enable’ 
latches AND 
together to 
activate 
‘Kb ready’. 


START 1/0 INSTRUCTION TIMING CHART 


Start 1/O Operation 


@ The CPU decodes the op code of the instruction and activates the 
control line ‘chan SIO instr’. 


e The attachment takes an |-O cycle to: 


1. Decode the O byte for the device address. 
2. Determine the condition code and send it back to the CPU. 
3% Set the ‘SIO latch’. 


@ The attachment takes an I-R cycle to decode the I-R byte. 


@ The bits in the I-R byte set or reset latches in the attachment in prepara- 
tion for a keyboard operation. 


l-R Byte 


The bits present in the I-R byte are determined by the main program in the 
CPU. Bits 4 and 5 must both be present to restore the keyboard. All bit 
combinations of the I-R byte are valid. All functions associated with each 
bit are performed except for the following, !f bits 2 and 7 are both present, 
interrupt request is not set. 


KEYBOARD ATTACHMENT- Operations 
Start I/O Instruction Timing Chart 


!-Op Cycle 1-O Cycle I-R Cycle 


rae 
ee 


Note 1. Reset at clock 2 of next |-O cycle. 




















Note 2. Reset at clock 4 of next I-R cycle if DBO bits 4 or 5 are present. 
Note 3. Reset at sample DBO clock 5 of next I-R cycle if ‘DB Kb bit 6 ckt 2’ is inactive. 
BRO690 


5406 FETMM 


(6/70) 


7-309 


KEYBOARD ATTACHMENT- Operations 5406 FETMM = (6/70) 7-310 


Key Operation—Programmed 


KEY OPERATION—PROGRAMMED 


@ Astart I/O instruction is given to enable interrupts. 


Key Operation 
Programmed 


Take start I/O 
Operation. 


Page 7-308 


@ Interrupt request is generated by pressing any key (except the shift key). 


e Asense instruction from the CPU gates two encoded bytes from the 
DBI assembler in the attachment to the CPU. These two bytes represent 
the key position (the key that was pressed). 






@ A second start I/O instruction is issued to restore the keyboard. 


Before the keys on the keyboard can be operative, a start I/O instruction 
must be issued to enable interrupts, restore the keyboard, and unlock the 
keys. 

When a key is pressed, its EDS latch spring is released and the elastic 
diaphragm is pressed through a hole in the separator by the actuator 
spring projection. The diaphragm common conductor contacts the 
normally open contact on the substrate, which completes the circuit to 
the encode circuit board. 

Pressing a key generates ‘character ready’ in the encode board which is 
sent to the attachment circuitry. ‘Char ready’ (and all other lines from the 
encode board) is converted from an SLD logic level to an MST logic level 
in the attachment. After the logic conversion, the line is called ‘any char’. 

The diode logic circuits of the encode board, decodes the output of the 
key that was pressed (EDS switch) into two bytes of information. The 
data byte is stored in the encode board bit latches, and the function 
latches that represent the bits to make up the status byte are also located in 
the encode board. | | 

An interrupt request is generated by raising the ‘interrupt polled KB’ 
line. This line is activated by channel interrupt poll ANDed with the 
interrupt request latch which is set on by the ‘any char’ line and the 
‘intlk int’ and ‘inter enable’ latches that were set earlier by the start I/O 
instruction. ‘Interrupt polled KB’ is sent to the DBI assembler to gate 
‘KB DBI 1 bit’ to the CPU to request an interrupt. 

When the interrupt is granted by the CPU (interrupt level 1 for the 
keyboard), the CPU branches to the keyboard interrupt routine. A sense 
instruction is issued to the attachment to transfer the two bytes from 
the bit latches through the DBI assembler onto DBI. 

The interrupt routine can now issue a second start |/O instruction with 
bits 4 and 5 active in the I-R byte of the control code to restore the key- 
board in order that another key can be pressed. Depending on the main 
program in process, the start I/O instruction can turn off the ‘int req’ 
latch with bit 7 active in the control code. This turn off interrupt request 
instruction causes the CPU to exit from the keyboard interrupt routine 
and return to the main program. 


Press any key except 
the shift key. 


Generate an interrupt 
request in the attach- 
ment to ask the CPU 
for an interrupt. 


If no device with a higher 
priority is requesting an 
interrupt, the CPU will 
grant the interrupt to 

the keyboard. 


The ‘inter req 1’ latch is 
set in the CPU, and the 


keyboard |!AR and ARR 
LSR’s are selected. 


See page 5-262. 























Start !/O instruction 
will: enable 
interrupts, restore 
the keyboard, and 
unlock the keys. 


PKO22 


‘Character ready’ from the 


encode board activates 
‘any char’, 











Set by ‘any char’ and 
the ‘intlk int’ and ‘inter 
enable’ latches that 

were set by the start |/O. 





Set the 
‘inter req’ latch. 


Activate 
‘interrupt polled KB’. 







PKO13 


This line activates ‘KB DBI 
1 bit’ in the DBI assembler. 






This bit is sent to 
the CPU to poll for 
an interrupt. 












The CPU issues a sense 
instruction to the keyboard 
to transfer the status and 
data bytes (generated by 
pressing a key) from the 
DBi assembler to the CPU. 













See Sense 
Operation. 


Page 7-306. 


Issue a start |/O to restore 
keyboard so that another 
key can be pressed, or to 
turn off ‘int req’ so that 
the CPU can exit to the 
main program. 






















See Start 1/O 
Operation. 


Page 7-308. 


End of 
Operation 


BRO691 


KEYBOARD INTERRUPT REQUEST 


e Astart I/O instruction is issued to the keyboard attachment to: unlock 
the keyboard, restore the keys, and enable interrupts. 


@ Pressing a key on the keyboard, or the inquiry request key on the con- 
sole, turns on the ‘inter req’ (interrupt request) latch in the attachment. 


@ With ‘interrupt poll’ active in the attachment at clock 5-7 time and the 
‘int req’ latch on in the attachment, the ‘interrupt polled KB’ line in the 
attachment gates ‘KB DBI 1 bit’ out of the DBI assembler to request an 
interrupt. 


e If no interrupts with a higher priority are pending and the program in 
progress is at the end of an instruction, the main program is interrupted 
by a branch to the keyboard interrupt routine. 


e The keyboard interrupt routine issues a sense instruction to the key- 
board attachment and allows the two bytes (generated as the result of 
pressing a key) onto DBI. 


e After sensing the two bytes of information generated by pressing the 
key, the keyboard is restored (enabled) when the keyboard interrupt 
routine issues a start |/O instruction. The keyboard keys can now be 
operated again. 


The keyboard interrupt level has a separate [AR and ARR in the CPU 
local storage registers so that the [AR and ARR for the main program are 
not disturbed. Local storage register 15 contains the interrupt level 1 
instruction address register (IAR-1), and local storage register 16 contains 
the interrupt level 1 address recall register (ARR-1) for the keyboard. 

The interrupt routine performed is established by the interrupt priority 
latches. As in the case of cycle steal, the highest interrupt level device takes 
precedence over lower level devices. The keyboard is assigned interrupt 
level 1 which is the lowest level in priority. Therefore, it is possible for any 
other interrupt routine to interrupt the keyboard. However, each device 
maintains its interrupt request until it is satisfied. The lower level priority 
device finishes its routine upon completion of the higher level routine. 

The stored program controls the ability of the keyboard to interrupt by 


enabling and disabling the keyboard through the use of start I/O instructions. 


Once an interrupt has occurred, it is also ended by a start I/O instruction. 

During the !-O cycle, keyboard selection occurs in the same manner as any 
start 1/O instruction. At clock 5 of the I-R cycle, the control code (I-R byte) 
is sent to the attachment on DBO. The control code is decoded by the 
‘attachment to turn on the ‘inter enable’ latch. This latch remains on until 
another start I/O instruction is sent to the attachment to reset (disable) the 
latch. 

When a key is pressed on the keyboard, the ‘inter req’ latch is turned on. 
At the end of the operation being performed in the CPU, ‘interrupt poll’ is 
sent to the keyboard attachment. This activates ‘interrupt polled KB’ in the 
attachment. This line gates ‘KB DBI! 1 bit’ out of the DBI assembler to turn 
on the interrupt latch for the keyboard in the CPU. If more than one device 
is requesting an interrupt, only the highest level priority latch is turned on. 


KEYBOARD ATTACHMENT-—Operations 
Keyboard Interrupt Request 


With any interrupt latch on, the selection of the normal [AR/ARR (P1 or 
P2) is blocked and the !AR/ARR for the active interrupt level latch is 
selected. The interrupt request latch in the attachment stays on until it is 
reset by a start I/O instruction. 

Upon recognizing the keyboard interrupt, the CPU issues a sense instruct- 
ion to the keyboard attachment. The instruction decodes the contents of 


the DBI assembler, which is the coded character of the key that was pressed. 


The output of the DBI assembler is sent to the CPU on DBI. 


[tT 
























With this information, the stored program in the CPU determines the 
cause of the interrupt, branches to that routine, and performs the required 
operation. When the operation is complete, the CPU can issue another 
start 1/O instruction to the attachment. 

Refer to the flowchart on page 7-310 for the operation. The only 
difference is that a keyboard interrupt can be generated by pressing either 
the inquiry request key or a data key. 
















Interrupt 
SIO Inst Op End Gate Latches 
I-R Cycle x | A Interrupt Poll : ay 
Clock 5 Clock 5to 8 CPU 
_ Interrupt 
[~ Enable : M/C Advance ke 
| Enable Pe EL | EL 
| Disable Taj | 
| Page 7-207 | 
| Interrupt | 
Polled 
Keyboard | 
KB DBI Bit 1 
| A B 
Interrupt | MEE, 
| Request me oe 
Char Ready A | | 
| : rE DBI bit and interrupt latch 
| | 
A ft 
| oe | 
| Page 7-207 | *By order of priority. 
a Decode | 
ee Control 
Code 
| | ATTACHMENT | 
Page 7-206 | 
Keyboard | | Character Read | 
y 
ee Any Int Level Being Serviced 
os Interrupt N 
i P1 IAR/ARR 
Page 7-203 Latch 


| f OFL 
Interrupt Control ; 





Sel IAR/ARR Inter 


[AR Seld 


interrupt L[AR/ARR Selection 


BRO692 


5406 FETMM = (6/70) 7-311 


ALTER STORAGE OPERATION 


The alter mode of the keyboard is used to key in test programs and sub- 
routines. The operation of the keyboard in this mode is intended for 
field engineering use as an aid in locating machine troubles by checking and 
testing machine functions. | 

When the CE mode selector switch is at the alter storage position, the 
system stops at clock 9, and the bail contact modified signal (generated by 
the bail contacts being closed) turns on the bail latch. The bail latch output 
signal turns on the bail magnet driver which provides current through the 
bail magnet coils. This causes the bail bar to move back and unlock the 
keyboard. The ‘alter up’ latch (page 7-203) sets and the keyboard unlocks. 

Keys A through F, and O through 9 are the only keys that can be used in 
alter storage mode. Depression of any other key causes the bail bar to go 
forward and lock the keyboard. If this occurs, position the CE mode 


selector switch to the process position and press SYSTEM RESET. The key- 


board unlocks and allows the return to alter storage mode. Before continu- 
ing, an alter SAR must be performed. 

Data entered form the keyboard begins at storage address OOOO, unless an 
alter SAR is made to a specific starting address. 

For this description of the encode board refer to page 7-201. 


First Key Depression (Odd Key Count) 
@ Depress key. 


e EDS switch closes, allowing current through its contacts and associated 
diodes in the encode board. 


e@ The output of the diode gives the proper inputs to the bit latches to 
obtain the hexadecimal value for the key pressed (first half byte). 


e These lines also provide inputs to the ‘group H’ latch. This latch deter- 
mines that the key pressed is a valid hexadecimal character. 


e Bits 0, 1, 2, and 3 are gated by the ‘alter up’ latch output to turn on the 
‘Ist 1/2 byte’ latch. If either zero (0) key is depressed, the P bit turns on 
the first half byte latch. 


@ With ‘1st 1/2 byte’ latch on, one input to the ‘alter up’ latch is removed. 


@ At this time data is gated through the DBI assembler onto DBI, but it is 
not accepted by the CPU because it is idling at clock 9 time. However, 
the keyboard is restored (unlocked) to allow entering the second half 
byte from the keyboard. 


Keyboard Restore 
@ ‘Alter up’ latch ANDed with ‘group H’ latch, ‘Ist 1/2 byte’ latch and 
(not) ‘bail contacts’ generate a ‘drop bail pulse’ line. 


@ This line turns off the bail latch, causing the bail magnet current to drop 
and the bail bar moves forward under spring tension. 


KEYBOARD ATTACHMENT-— Operations 
Alter Storage Operation 


\ 


@ The bail contacts close generating a ‘bail contact’ signal, which: 


1. Turns off the ‘group H’ latch. 
2. Turns off the ’P bit’ latch. 
3 Turns on the ‘bail latch’. 


@ The ‘bail latch’ causes the bail magnets to receive current to draw the 
bail bar back and unlock the keyboard. 


@ When the bail contacts open, the ‘bail reset’ line is activated to turn off 
the ‘alter up’ latch. 


@ The active bits, representing the hexadecimal key that was pressed, now 
make up the first half byte of data. The keyboard is unlocked and ready 
for the second half byte of data (even key count) to be entered. 


Second Key Depression (Even Key Count) 
@ Depress key. 


© EDS switch closes, allowing current through its contacts and associated 
diodes in the encode board. 


© The output of the diode gives the proper inputs to the bit latches to 
obtain the hexadecimal value for the key pressed (second half byte). 


@ With the ‘alter up’ latch off, the lower group of bit latches (4, 5, 6, and 
7) are gated to form the second half: byte (hexadecimal). 


@ The ‘2nd 1/2 byte’ latch is turned on by bit 4, 5, 6, 7, or P with ‘alter 
up’ latch off. 


e ‘Alt char ready’ is now activated. 


e ‘Alt char ready’ turns on the ‘system start’ latch in the CPU to start the 
system. 


@ ‘Clock 2’ ANDed with ‘alt char ready’ turns off the ‘bail latch’ and locks 
the keyboard. 


@ The CE mode selector switch in the alter storage position gates the key- 
board bit latch outputs out of the DBI assembler. 


@ With the ‘bail latch’ off, the bail contacts: 


1. Turn off the ‘P bit’, ‘group H’, and ‘alter up’ latches. 
ney Turn on the ‘bail latch’. 
3. The ‘bail contact’ line ANDed with ‘alter char ready’, and (not) 
‘ing req’ latch turns on the ‘reset’ latch. 
4. The ‘reset’ latch resets the bit latches (O through 3 and 4 through 
7). 


@ The ‘alter up’ latch remains off until the ‘reset’ latch is turned off. When 


it Comes on again, the keyboard is ready for the next odd-key depression. 


Zero Key Depression 


When the zero key is pressed, no hexadecimal character is generated, but the 

‘P bit’ latch is set. This latch being set turns on the ‘1st 1/2 byte’ latch. The 

‘P bit’ latch ANDed with the ‘alter up’ latch off, turns on the ‘2nd 1/2 byte’ 

latch. This generates an ‘alter char ready’ signal but no DBI bits when the 

O through 7 bit latches are not activated by the encode board circuit diodes. 
The ‘P bit’ latch turns on both half byte latches, but only: 


ie The ‘1st 1/2 byte’ latch when a key is pressed on an odd key count. 
2. The ‘2nd 1/2 byte’ latch when a key is pressed on an even key count. 


This is done by ANDing (not) ‘alter up’ and ‘P bit’ to turn on the ‘2nd 1/2 
byte’ latch a zero key is pressed on an even key count. 

The ‘P bit’ line is active when any key giving an even number of bits is 
pressed (the P bit to the attachment is blocked by ‘alter char ready’). 
Since ‘P bit’ does not enter the system DBI from the encode board in alter 
storage mode, the ‘P bit’ is generated in the attachment circuits and ANDed 
with the ‘alter char ready’ line. This allows correct parity to enter the CPU. 


5406 FETMM = (6/70) 7-313 





KEYBOARD ATTACHMENT- Operations 
Alter Storage From Keyboard Flowchart (Part 1 of 2) 


Alter Storage } 
Operation 











Note 1 | | s 
\ Second Key 


7-203 Depression 


On the CE panel 
set the following 
switches: 









‘Alter up’ latch 
is set by the CE 
mode selector 
switch in the 
alter storage 
position. 






. CE mode selector 
to PROCESS. 


2. Actuate SYSTEM 
RESET. 


3. CE Mode Selector 
to ALTER SAR. 


. Data - address 
switches to 
starting address. 


. Actuate START 
(once only). 


character 
into encode 
board data 
latches. 


































6. CE mode selector 
to ALTER 
STORAGE. 


The CPU clock 
will stop at 
clock 9. 






First Key Depression 






Only keys A-F, 
and Q-9 can 















1. Loads first 


| a 










hexadecimal 
character 7-203 be used in alter 
into encode storage mode. 
board data Output of key 


goes to diodes 
in the encode 
board. 


latches. 






The hexadecimal value 
of the key pressed 

is stored in the 

bit latches. 





Encode board 
output sets the 
bit latches. 











Latch set determines 
that a valid hexadecimal 
character key was 

pressed. 


7-203 co 
Set ‘Ist 1/2 Page 7-315 
byte’ latch. ate 


The same output 
sets the ‘group 
H’ latch. 









Set by the bit latches 
and the ‘alter up’ latch. 
Activates the drop bail 
pulse line. Does not 
activate ‘KB reset’ 

line. 


Page 7-315 


(8 | Page 7-315 


1. Loads second 
hexadecimal 




















7-203 


Output of 
key goes to 


diodes in the 
encode board. 


7-203 






The hexadecimal value 
of the key pressed 

is stored in the 

bit latches. 


Encode board 
output sets 
the bit latches. 






7-203 






Set the 
‘2nd 1/2 byte’ Tl 
latch. 


Set by the bit latches 
and the ‘alter up’ 
latch off. 





7-203 


. Activate 
‘alt char ready’. 


Turn on the 
‘system start’ 
latch in the 
CPU to start 
the system. 






Set by ‘alt 
char ready’. 


7-203 


At ‘clock 2' 
turn off the 
‘pail latch’ 
and lock the 
keyboard. 







‘Clock 2’ is ANDed 
with ‘alt char ready’. 


. Note 1. Circuitry is on encode board, instead 
of attachment board. Therefore, 
the references are made to Page 7-203 


P. bn 
age 7-315 of this manual. 


tad 


5406 FETMM 


(6/70) 


7-314 


A Page 7-314 


Keyboard Restore 









The keyboard 
is restored 

to allow the 
second half 
byte of data 
to be 
entered. 


Ge 
oe 





ae 


Bone 


Page 7-314 











Lc | Page 7-314 













7-203 


Generate a 
‘drop bail’ pulse. 


Generated by 
AN Ding: ‘alter up’, 
‘group H’, ‘1st 
1/2 byte’, and, 
‘bail contacts’. 


‘Drop bail’ turns 
off the bail 
latch. The bail 


magnet current 
drops and the 
bail bar moves 
forward. 





7-203 
‘Bail contacts’ 
is activated. 


‘Bail contacts’ 
turns off: 
‘group H’ latch, 
‘P bit’ latch, and 
‘bail latch’. 






Activated by 
the bail contacts 
closing. 









The absence of 
‘alter char ready’ 

prevents generating 
the KB reset signal. 


The bail magnets 
draw the bail 

bar back and 

the keyboard 

is unlocked. 
















7-203 
Activate ea Nas by 
‘bail reset’. the bail contacts 
open. 
7-203 


Reset the 







Reset by 
‘bail reset’. 


‘alter up’ 
latch. 


End of 


Operation 





KEYBOARD ATTACHMENT-—Operations | 
Alter Storage From Keyboard Flowchart (Part 2 of 2) 


ho 


oD Page 7-314 


The two hexadecimal 
characters 
stored in the 
bit latches 
are gated 


through the 
DBI assembler 
in the attach- 
ment to the 
CPU. 


The ‘bail latch’ 
off: 

Turns off the 

‘P bit’, ‘group H’, 
and ‘alter up’ 
latches, and 
turns on the 

‘bail latch’. 


Set the ‘KB 
reset’ latch. 


The ‘reset’ latch 
resets the bit 
latches, 


When the ‘reset’ 


latch turns 
off, the ‘alter 
up’ latch sets 
and the key- 
board is ready 
for the next 


entry. 





7-203 





7-203 





7-203 









sas 


‘Alter up’ latch off 
drops the bail. 


The bail contacts 
turns on the 
bail latch. 








Set by ANDing 
‘pail contact’, 
‘alter char ready’, 
and the ‘ing req’ 
latch off. 


Cad 


5406 FETMM 


(6/70) 


7-315 


KEYBOARD ATTACHMENT- Operations 
Typamatic Operation 


TYPAMATIC OPERATION 


Typamatic keys (tab and backspace) have two operational levels or stops. 
The first level permits a single operation and is indicated by a spring loaded 
stop when a light key stroke is used. The second level allows a repeat action 
without repeated key strokes. A heavy key stroke will push the key lever 
through the spring loaded first stop into the typamatic level. This repeats 
the key function as long as the key is held in the lower level. 

The typamatic function is indicated by the lower level of the key lever. 
However, the typamatic function is performed by the control program. 

Refer to the timing chart on this page for the following description of 
the typamatic operation. 


Area 1 (In Timing Chart) 


dis Assume that the keyboard is ready (enabled and unlocked). 

2. The operator presses the tab or backspace key. 

oS: Data bits are stored in the bit latches in the keyboard encode board. 

4 These bits are recognized as typamatic bits (bit 3 and bit 6 are pre- 
pared to be sensed on the first EB cycle of a sense instruction). 

5. The next time the ‘interrupt poll’ line is activated, a system level 1 
interrupt will occur (unless a higher level interrupt or cycle steal has 
been requested). 

6. During.the subroutine of the program, a sense instruction Is given to 
the keyboard. 


a. First EB cycle—bit 3 (function) and bit 6 are sensed to indicate 
a typamatic operation. 
b. Second EB cycle—data is sensed (tab or backspace). 


7. A start I/O instruction is given to the keyboard with bit 4 on in the 
control code to drop the bail and lock the keyboard. The start I/O 
instruction must occur within 15 ms of the sense instruction. 

3. A time out of approximately 100 ms for the software begins. This 
time is required to maintain a 10 cycle per second rate for the CRT 
cursor. See ‘‘Note 2.” | 

9. During the time out, the CRT cursor or print element can be moved 
one increment in the appropriate direction. 


Area 2 (In Timing Chart) 


1. The typamatic operation is still in process. 
2. Asense instruction is issued to the keyboard at the end of the 100 ms 
time out. 


a. First EB cycle—bit 3 and bit 6 are again sensed indicating a typa- 
matic operation. 
b. Second EB cycle—data is again sensed (tab or backspace). 


3. The 100 ms time out occurs again. 
4, The CRT cursor or the print element can again be moved. 


5406 FETMM = (6/70) 7-316 














eee 
2 


DBI bits 3 and 6 identify typamatic character to the program. Note 7. 





When tab or backspace keys are depressed, bits 3 and 6 of the 
first sense byte are on. This is true even if the keys are not fully depressed. 


Start !/O instruction must have bit 4 on in the control code to drop 


the bail and unlock the keyboard. 
Note 2. Parity checks or additional incrementing may occur if 


Program time out required for 10 cycle per second maximum cursor approximate time intervals are not maintained. 


or print element rate. 

Data byte is transferred (identifies tab or backspace key). 

No typamatic bit (6) is sensed in the status byte (the key was released). 
No data bits are sensed in the data byte (only the P bit). 


BBDS 8 6 


Start 1/O instruction has bits 3 (to reset parity check), 5 (to pick the 
bail and unlock the keyboard), 6 (to enable interrupts), and 7 (to 
reset the current interrupt request) on. 
BRO693 


Area 3 (In Timing Chart) 


1. The operator has released the key and therefore the typamatic opera- 
tion is no longer in process. 
2. A sense instruction is issued to the keyboard. 


a. First EB cycle—the typamatic bits (3 and 6) are no longer present. 
Bit O is sensed. 
b. Second EB cycle—data is sensed, only bit P is present. 


3 A start I/O instruction is issued to the keyboard. The control code 
must have bit 3 on (to reset bit 0), bit 5 on (to pick the bail and 
unlock the keyboard), bit 6 on (to enable interrupts), and bit 7 on 
(to reset the current interrupt request). 


Section 9. Printer and Ledger Card Device Attachments 


This section of the 5406 FETMM contains the theory and maintenance 
diagrams for the 5213 and 2222 Printer attachment and ledger card device 
attachment. It consists of six chapters as follows: 


Chapter 1. Introduction to the Printer Attachment 

Chapter 2. Functional Units of the Printer Attachment 

Chapter 3. Operations of the Printer Attachment 

Chapter 4. Introduction to the Ledger Card Device Attachment 
Chapter 5. Functional Units of the Ledger Card Device Attachment 
Chapter 6. Operations of the Ledger Card Device Attachment 


PRINTER ATTACHMENT —Contents 


Contents 


Chapter 1. Printer Attachment Introduction 9-101 


Introduction to Printer and Attachment (2 Parts) 9-101, 9-102 
Printer Operations (2 Parts) 9-103, 9-104 

Load I/O Instruction Format 9-105 

Test I/O Instruction Format (2 Parts) 9-106, 9-106A 

Advance Program Level Instruction Format (2 Parts) 9-106B, 9-107 
Sense I/O Instruction Format 9-108 ... 

Start 1/O Instruction Format 9-109 

Errors (3 Parts) 9-110, 9-111, 9-111A 

Data Flow 9-112 


Chapter 2. Printer Attachment Functional Units 9-201 


Introduction to Functional Units 9-201 
Board Layout 9-202 

Printer Single Shots 9-203 

Initial Selection (2 Parts) 9-204, 9-205 
Printer Commands 9-206 

Data Bus In Assembler 9-207 

Stepper Motor Controls 9-208 

Print Controls 9-209 

Print Hammer Selection 9-210 

Cycle Steal Controls 9-211 

Error Checking (2 Parts) 9-212, 9-213 


Chapter 3. Printer Attachment Operations 9-301 


_ Introduction to Operations 9-301 


Load I/O Instruction Flowchart 9-302 
Load I/O Instruction Timing Chart 9-303 
Test 1/O and Advance Program Level Instruction Flowchart 9-304 


"Test 1/O and Advance Program Level Instruction Timing Chart 9-305 


Sense I/O Instruction Flowchart 9-306 

Sense I/O Instruction Timing Chart 9-307 

Start 1/O Instruction Flowchart 9-308 

Start 1/O Instruction Timing Chart 9-309 

Stepper Motor Start—Move Right (2 Parts) 9-310, 9-311 
Stepper Motor Start Timing Chart 9-313 

Element Return (3 Parts) 9-314, 9-315, 9-317 

Element Return Timing Chart (2 Parts) 9-318, 9-319 


TNL SN34-0043 to SY34-0022-1 


‘ Stepper Motor Stopping (2 Parts) 9-320, 9-321 


Stepper Motor Stopping Timing Chart (2 Parts) 9-322, 9-323 
Tab Right (3 Parts) 9-324, 9-325, 9-327 ? 

Tab Left (3 Parts) 9-328, 9-329, 9-331 

Primary Skip (2 Parts) 9-332, 9-333 

Primary Index 9-334 | 

Secondary Index 9-335 

Print Operation (3 Parts) 9-336, 9-337, 9-339 

Print Operation Timing Chart (2 Parts) 9-340, 9-341 
Bi-directional Print Operation (3 Parts) 9-342, 9-343, 9-344 
Bi-directional Print Operation Timing Chart 9-345 


Chapter 4. Ledger Card Device Attachment Introduction 


| Ledger Card Format 9-401 


Indicators and Controls 9-402 
Program Instructions 9-402 

ledger Card Device Operations 9-402 
Commands 9-402 

Command Field Formats 9-403 
General Operation of the LCD 9-404 


Chapter 5. Ledger Card Device Attachment Functional Units 


Introduction to Functional Units 9-501 

Data Flow Diagram 9-502 

LCD Pulse Generate and Sense Cell Latches (4 Parts) 9-503 through 9-507 

Command Controls, Diagnostic LIO Controls, and LCD Attachment Resets 
(2 Parts) 9-508, 9-509 | 

DBI Assembler and Channel In Controls (2 Parts) 9-510, 9-511 

Cycle Steal and LSR Selection (5 Parts) 9-513 through 9-517 

Read 1D and Data Assembler (2 Parts) 9-518, 9-519 

LCD Controls (2 Parts) 9-520, 9-521 

LCD Attachment Error Conditions (2 Parts) 9-522, 9-523 


Chapter 6. Ledger Card Device Attachment Operations 


Introduction to Operations 9-601 
Feed, Read ID, and Locate-Eject (10 Parts) 9-603 through 9-611 
Index (3 Parts) 9-615 through 9-617 


| Read Mark and Eject (3 Parts) 9-619 through 9-621 


Eject (3 Parts) 9-623 through 9-625 
Read All Line Finder Marks 9-626 


5406 FETMM (6/71) 9-1 


Chapter 1. Introduction 


PRINTER ATTACHMENT 


The IBM 5213/2222 Printer attachment provides a means for the attached 
5213 or 2222 Printer to use the facilities of the IBM 5406 Processing Unit 
to communicate with main storage. The attachment provides the communi- 
cation lines between the printer and the processing unit and controls the 
transfer of all information between the two. 

A ledger card device attachment is a part of the printer attachment if a 
2222 Printer is installed. The ledger card device attachment is described 
separately in chapters 4, 5, and 6 of this section (section 9). 

The attachment circuitry is MST-1 logic, physically located on gate A, 
board A2 in the 5406 Processing Unit. The control interface lines between 
the attachment board and the electronics board are SLD-100 levels. Con- 
version to MST occurs at the attachment board. 

The communications path between the processing unit and the printer 
attachment is through the I/O channel. Using this channel, data and control 
information is transferred from the processing unit, and status is sent to the 
processing unit under control of stored program instructions. 

During the process of exchanging information, the printer and the pro- 
cessing unit operate together in multiplexer mode. This means the informa- 
tion transfer takes place between processing unit cycles on a priority basis 
with other devices. | 

By the means of a fixed-cycle steal priority, |/O cycles may be interleaved 
between any two processing unit cycles. 


/ 


Controls the transmission of data to and from the 5213 
and 2222 to the CPU and channel and main CPU storage. 


5213 or 
2222 
Printer 


5213/2222 
Attachment 


CPU 


Printed 
Output 


Other 
Attachments 





Performs arithmetic and 
logical functions. 


BRO713 


5406 PRINTER ATTACHMENT - Introduction 
Introduction to Printer and Attachment (Part 1 of 2) 


PRINTER 


The 5406 Printer attachment has the capability of controlling five different 
models of printers (one printer per system), each of which is available in a 
variety of optional features. The basic printer is a 13 inch carriage serial 
printer which prints at a rate of 85 characters per second. 


The five models of printers available are: 


The IBM 5213 Printer Model 1 can print 132 characters per line at 
85 characters per second. Forms are moved by a pin feed platen with 
single or double spacing selectable by the operator. 


2. The IBM 5213 Printer Model 2 has the same characteristics of the 
Model 1, except the carriage is controlled by a pin feed tractor with 
tapeless vertical forms control. 

3. The IBM 5213 Printer Model 3 can print 132 characters per line at 


85 characters per second or functions as a bi-directional printer that 
can print approximately fifty 96-character lines per minute. Forms 
movement is controlled by a pin feed tractor with tapeless vertical 
forms control. 


The following illustration shows the combinations of printers and features 


available. 


5213 Model 1 


Carriage 


13 inch, 
pin feed. 


Type Printing 


Serial. 


(Basic Printer) 





5213 Model 2 


Carriage 


13 inch, 
vertical forms 
control. 


Type Printing 


Serial. 


Printer 
Attachment 


5213 Model 3 


Carriage 


13 inch, 
vertical forms 
control. 


Type Printing 


Bi-directional. 


Tab right at 
high speed. 


2222 Model 1 


Carriage 


22 inch, 
vertical forms 
control. 


Type Printing 


Serial. 


Tab right at 
high speed. 





TNL §N34-0043 to SY34-0022-1 





2222 Model 2 


Carriage 


22 inch, 
vertical forms 
control. 


Type Printing 


Bi-directional. 


Tab right at 
high speed. 


BRO714A 


4. The IBM 2222 Printer Model 1 can print 220 characters at 85 charac- 
ters per second. Forms are handled with a dual pin feed tractor with 
tapeless vertical forms control (on the primary carriage only). 

The 2222 Printer also has as a standard feature a ledger card device. 
The ledger card device allows feeding, printing, and identification of 
ledger cards. | 

5. The IBM 2222 Printer Model 2 has the same characteristics as the 
Model 1 Printer, except that it is a bi-directional printer. It can print 
approximately fifty 96-character lines per minute. 


Vertical forms control allows skipping a number of lines from 2 to 256. 
The pin feed carriage on the 5213 Model 1 can space one or two lines by 
setting the manual control on the printer to the proper position. 


Printing Principle 


Printing is done by a print head capable of making seven dots in a vertical 
arrangement. The print head is moved across the paper from left to right 

or from right to left at a constant velocity. As the print head moves through 
one character space, the head can produce dots in any of seven horizontal 
positions. A restriction is applied, however, that none of the vertical dot 
positions can produce a dot in two consecutive horizontal dot positions. 
Therefore, the maximum number of horizontal dots that can be produced 
by any dot position on the print head is four. 


Printer Functions 


The serial printer (printing without the line printing feature) prints with the 
print head moving from left to right. The bi-directional printing feature 
allows printing with the print head moving either from left to right or right 
to left. The characters that can be printed and the bit patterns (EBCDIC 
code) in storage that caused each character to be printed are shown on 
page 9-102. 

In addition to printing data, the following functions can be performed: 


Tab right 

Tab left 

Element return 

Primary carriage index 

Primary carriage skip (vertical forms control tractor only) 
Secondary carriage single index (dual feed carriage) 


GO GQ 


5406 FETMM = (6/71) 9-101 


5406 PRINTER ATTACHMENT~— Introduction 
Introduction to Printer and Attachment (Part 2 of 2) 


Dual Feed Carriage | 


Dual feed carriage is a standard feature of the 2222 Printer. Vertical forms 
control is utilized on the primary feed carriage with the ability to vertically 
space or skip. The secondary feed carriage is a single vertical space carriage. 
Vertical motion on the secondary carriage can overlap all other printer func- 
tions except printing. 


Ledger Card Device 


The ledger card device on the 2222 Printer allows the feeding, checking, and 
printing of data on ledger cards. The ledger card device is designed to inter- 
fere as little as possible with paper handling and readability of data printed 
on forms. Printing and forms motion of the ledger card are under control of 
the program. | 

For identification purposes and checking that the proper document is be- 
ing printed on, space is provided for printing coded numeric identification 
in the upper right edge of the card and for reading such coded notation. 

The ledger card device also has a function that allows feeding the cards 
and locating the first available print line. Provision is also made for auto- 
matically signalling to the program when no print lines are available. 


The right edge of the ledger card is always positioned in the farthest right | 


printing positions of the 22 inch printer. The last 6 print positions on the 
ledger card (positions 215—220) are reserved for the line finder marks and 


two identification number (1D) code marks. These marks are printed in posi- 


tions 216, 218, and 220. Except for the print mark code, no printing should 
be done beyond position 214. . 

The line finder marks are used for locating the next available print line. A 
line finder must be printed for each line printed to prevent over-printing the 
next time line posting of the same ledger card takes place. 


PRINTER FEATURES 


Bi-directional Printing 


Bi-directional printing (line printing) is a standard feature of the 5213 
Printer Model 3, and the 2222 Printer Model 2. This allows printing with 


the print head moving either left to right or right to left. Printing can be per- 


formed at a rate of approximately fifty 96-character lines per minute. Print- 
ing more characters results in a slower throughput; printing fewer characters 
results in a higher throughput. 


LOCAL STORAGE REGISTERS (LSR) 


There are three local storage registers (located in the CPU) that are assigned 
to the printer attachment. Two of these are used in print operations, and 
the third is used with the ledger card device (LCD). 


Print Data Address Register (PDAR) 


The PDAR contains the leftmost or starting address of the data field when 
issuing a print command. This address has no core boundary restrictions. 


TNL SN34-0043 to SY34-0022-1 


This LSR must be reinitialized after each print command when not printing 
consecutive core fields. The LSR content points to the last printed character 
location plus one at the completion of a print command. 


Print Command Address Register (PCAR) 


The PCAR contains the leftmost storage address of the command field. The 
byte at this address contains the first command to be executed. | 


Locate Line Address Register (LLAR) 


The LLAR is used only with the ledger ‘card device to locate the next print- 
able line and to detect the last printable line. 


BITS 2,3 


BITS O, 1 


BITS 





3406 FETMM (6/71) 9-102 


Shared LSR’s 


The ledger card device uses the PCAR and the PDAR along with the printer. 
The PCAR is used in the same manner by both devices. In LCD operations, 
the PDAR contains the leftmost or starting address of the identification (ID) 
number that will be read from the ledger card. The address has no core boun- 
dary restrictions. The LSR content points to the last position of the 1D num- 
ber plus one at the completion of the feed, read ID, and locate next print 
line command; or feed, read ID, and eject command. 


CHARACTER SET 


The basic printer attachment provides 62 print characters plus blank. This 
does not include the special dash used by the ledger card device. 

The chart below shows the normal EBCDIC code used to print the basic 
character set (a wedge in the corner of the block denotes a character in the 
basic set). All other blocks show the fold (bits 0 and 1), or what will print 
if presented to the attachment. 


Note 1. Code XX101010 will print a special 
dash used by the ledger card device 
for 1D marks and line finder marks. 

BRO715A 


_ 


LOAD 1/0 INSTRUCTION 


e@ The load I/O instruction consists of three or four bytes (three if indexing 
is used). 


@ The load I/O instruction selects the matrix printer or the LCD if the de- 
vice address equals E (hexadecimal). 


e Two bytes in storage, addressed by the operand address, are loaded into 
the destination specified by the N code of the O byte. 


The load I/O instruction is composed of three or four bytes. The first byte 
is the op code, a Y1 (hexadecimal) which indicates a load !/O operation. 
The second byte is the OQ byte which contains the device address, an M code, 
and an N code. The third and/or fourth bytes indicate the address of the 
information to be loaded into the local storage register (LSR), or in the 

case of a control load I/O indicate the address of a byte in main storage 
which is bit significant as a diagnostic aid. 


Q Byte Description 


The upper four bits (bits 0-3) specify the device address of the matrix print- 
er E (hexadecimal). Bit 4 is the M code which is used to determine if the 
instruction is for the printer (bit 4 = QO), or if it is for the ledger card device 
(bit 4 = 1). The lower three bits are the N code or the function code. 


Operand Address 


The operand address of the load I/O instruction can serve one of two pur- 
poses. It can contain the address of storage bytes to be stored in the LSR 
selected for loading, or it can contain the address of the storage byte which 
is bit significant for diagnostic testing. 


Parity and Error Conditions 


The load I/O instruction is accepted only if the printer is not busy (except 
for a control load I/O which is always accepted). A parity error detected 

by the attachment results in a processor check stop and the processor check 
light comes on. 


5406 PRINTER ATTACHMENT ~— Introduction 
Load I/O Instruction Format 


LOAD 1/0 (LIO) INSTRUCTION FORMAT 


OP Code OQ Code Operand Address 
Byte 1 Byte 2 Bytes 3 and/or 4 





Op Code for load !/O 
instruction, 


Y = 0011 (3) or 


0111 (7) or 
1011 (B) 






Address of one 





or two storage 
bytes to be stored 
in the destination 
specified by the 
N code of the 

Q byte. 












Device address 
1110 (E) for matrix 
printer or LCD. 








M Code 


M = QO Selects printer. 
M = 1 Selects LCD. 







Destination 


Control L!O—bit significant 

Bit 
Diagnostic block high speed or LCD diagnostic reset (on = set, off = reset). 
Force DBO check. (Printer only) 
Force diagnostic stepper emitter advance pulse or LCD emitter pulse. 
Force diagnostic print gate emitter, vertical advance pulse, or LCD 
sense cells off (on = set, off = reset), 
Diagnostic mode (on = set, off = reset). 
Integrated emitter or LCD card in switch (on = set, off = reset). 
Use 2nd EOF latch or LCD card out switch (on = set, off = reset). 
End of forms indicator latch (on = set, off = reset). (Printer only) 


Print data address register (PDAR) 
Print command address register (PCAR) 
Locate line address register (LLAR)—(LCD only) 


X means bit can be a “1” or “0”, 


BRO717B 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-105 


5406 PRINTER ATTACHMENT-—Introduction 
Test I/O Instruction Format (Part 1 of 2) 


TEST 1/O INSTRUCTION 


@ The test I/O instruction consists of three or four bytes (three bytes if 
indexing is used). 


e@ The test I/O instruction selects the matrix printer or the LCD when the 
device address equals E (hexadecimal). 


@ The test !/O instruction tests for: 


Printer Ledger card device 
Ty Unit check 1. Unit check 
2. End of forms 2. Last printable line 
3: Busy 3. .LCD busy 
4 Element at left margin 4. LSR busy 
5, Read 1D busy 
6. Card not aligned 


The test 1/O instruction is composed of either three or four bytes. The first 


byte is the op code, a Z1 (hexadecimal) which indicates a test |/O opera- 
tion. The second byte is the OQ byte which contains the device address, an 
M code, and an N code. The third and fourth bytes contain the branch to 
address if the condition tested for is met. 


O Byte Description 


The upper four bits (bits 0-3) specify the device address for the matrix 
printer, E (hexadecimal). Bit 4 is the M code which is used to determine 
if the instruction is for the printer (bit 4 = 0), or if it is for the ledger card 
' device (bit 4 = 1). The lower three bits (bits 5-7) are the N code which 
determines the test to be performed. 


Branch To Address 


The branch to address contains the address to be branched to if the condi- 
tions tested for as specified by the N code are met. It is either one or two 
bytes long depending upon the op code. 


Parity and Error Conditions 


Odd parity must be maintained in the test !/O instruction. A parity error 
detected by the attachment results in a processor check stop, and the pro- 
cessor check light comes on. 


TNL SN34-0043 to SY34-0022-1 


Op Code Q Code 


Byte 1 Byte 2 


TEST 1/0 (TIO) INSTRUCTION FORMAT 


Branch to Address 
Byte 3 and/or 4 


Branch to Address 














Op code for test I/O 
instruction. 


Z = 1100 (C) or 
1101 (D) 
1110 (E) 





Device address 
1110 (E) for matrix 
printer or LCD. 


M Code 


M = 0 Selects printer. 
_M = 1 Selects LCD. 


Branch Address 


Branch to address 
if N code condition 
is met. 





N Codes for Printer 


Unit Check 
Indicates: 


. Cycle check (horizontal or vertical) 
. Data check or ROS check 

. Margin check 

. Sync check 


Invalid command check 
Cover interlock switch open 


End of forms 

Busy 

Busy or end of forms 
Element at left margin 


End of forms or element at left margin 


Element at left margin or busy 


End of forms or busy or element at left margin. 





X means bit can be a ‘1’ or “‘O”’. 


5406 FETMM = (6/71) 


N Codes for Ledger Card Device 


Unit Check 
Indicates: 


. Sense cell check 

. Card skew check 
Drive check 

. Read mark check 
Line finder mark check 
Invalid command 


Last printable line 
LCD busy 

LSR busy 

Read |D busy 


Card not aligned 





Note. In the case of combined tests, any one of the tested conditions will cause the branch to occur. 


BRO718B 


9-106 


LCD TIO Test Condition Description 


Unit Check indicates any one of the LCD check conditions as shown in the 
TIO format diagram. 


Last Printable Line indicates (1) that the last allowable print line is posi- 
tioned at the platen or, (2) all the print lines have been used and the ledger 
card was ejected from the LCD. A sense !/O instruction must be issued to 
determine which of the two conditions exist. If the SNS instruction deter- 
mines that either the card in switch or card out switch is made, condition 1 
exists, if neither switch is made, condition 2 exists. 


LCD Busy indicates that the LCD is executing an SIO instruction. 
LSR Busy indicates: 


1. A printer chained command is in progress. 

2 A printer count command is in progress. 

3. An LCD feed, read ID, and locate next line operation is in progress. 

4 An LCD feed, read ID, and eject command is in progress and the ID 
number has not been transferred into main storage. 


5. An LCD read all line finder marks command is in progress and all the 
line finder marks have not been read. 

6. An LCD read back and eject command is in progress and the line 
finder mark has not been read. 

Te An LCD index command is in progress. 


Note. |f the LCD LSR busy condition is true (active), printer and LCD 
operations cannot be overlapped. 


Read ID Busy indicates that the ledger card |D number is being read from 
the ledger card and transferred into main storage. This condition is present 
during feed, read ID, and locate; or feed, read ID, and eject operations only. 
During a read all line finder marks command, read ID busy is active until 43 
bytes (the complete card) have been read. 


Card Not Aligned indicates that the ledger card is not aligned at the first 
feed rolls in the LCD. This condition must be present before issuing the 
following commands: feed, read ID, and locate; feed, read !D, and eject; 
and read all line finder marks. This test will also cause the LCD I/O attention 
light to turn on, and raise the LCD card gate if a card is not in the LCD. 


5406 PRINTER ATTACHMENT-— Introduction 
Test I/O Format (Part 2 of 2) 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-106A 


5406 PRINTER ATTACHMENT -— Introduction 
Advance Program Level Instruction Format (Part 1 of 2) 


ADVANCE PROGRAM LEVEL INSTRUCTION 
@ The advance program level instruction consists of three bytes. 


@ The advance program level instruction selects the matrix printer or the 
LCD when the device address equals E (hexadecimal). | 


e@ The advance program level instruction tests for: 


Printer Ledger Card Device 
1. Unit check 1. Unit check 
2. End of forms 2. Last printable line 
3. Busy 3. LCD busy 
4 Element at left margin 4. LSR busy 
5. Read ID busy 


6. Card not aligned 


The advance program level instruction is composed of three bytes. The first 
byte is the op code, an F1 (hexadecimal) which indicates an advance pro- 

| gram level operation. The second byte is the OQ code which contains the 
device address, an M code, and an N code. The third byte is not used. 


O Byte Description 


The upper four bits (bits 0-3) specify the device address for the matrix 
printer, E (hexadecimal). Bit 4 is the M code which is used to determine 
if the instruction is for the printer (bit 4 = 0), or if it is for the ledger card 
device (bit 4 = 1). The lower three bits (bits 5-7) are the N code which 
determines the test to be performed. 


_ Application 


If the specified conditions tested for do not exist, the operation becomes 
equivalent to a no-op, and proceeds to the next sequential instruction. 

If the specified condition is present, the operation causes the CPU to loop 
(IR backup) on the APL instruction until the specified condition is no 


longer present, and then proceeds to execute the next sequential instruction. 


_ Parity and Error Conditions 


Odd parity must be maintained in the advance program level instruction. 
A parity error detected by the attachment results in a processor check stop, 
and the processor check light comes on. 


TNL SN34-0043 to SY34-0022-1 


ADVANCE PROGRAM LEVEL (APL) INSTRUCTION FORMAT 


Op Code OQ Code 
Byte 1 Byte 2 
F 1 DA Not Used 
0 3 4 7 0 345 7 


ee ee ye ye ee 









Op code for advance 
program level 
instruction. 





Device address 
1110 (E) for matrix 
printer or LCD. 


M Code 





M = 0 Selects printer. 
M =.1 Selects LCD. 


N Codes for Printer 


Bits 
567 


000 Unit Check 
Indicates: 


. Cycle check (horizontal or vertical) 
. Data check or ROS check 
. Margin check 
. Sync check 
Invalid command check 
Cover interlock switch open 


End of forms 

Busy 

Busy or end of forms 
Element at left margin 


End of forms or element at left margin 


Element at left margin or busy 


End of forms or busy or element at left margin. 





X means bit can be a “1” or “0”. 





5406 FETMM 





'N Codes for Ledger Card Device 


Unit Check 
Indicates: 


. Sense cell check 

. Card skew check 

. Drive check 

. Read mark check 
Line finder mark check 
Invalid command 


Last printable line 
LCD busy 

LSR busy 

Read ID busy 


Card not aligned 


Note. In the case of combined tests, any one of the tested conditions will cause an IR backup to occur. BRO719B 


(6/71) 


9-106B 


LCD TIO Test Condition Description 


Unit Check indicates any one of the LCD check conditions as shown in the 
TIO format diagram. 


Last Printable Line indicates (1) that the last allowable print line is posi- 
tioned at the platen or, (2) all the print lines have been used and the ledger 
card was ejected from the LCD. A sense 1/O instruction must be issued to 
determine which of the two conditions exist. If the SNS instruction deter- 
mines that either the card in switch or card out switch is made, condition 1 
exists, if neither switch is made, condition 2 exists. 


LCD Busy indicates that the LCD is executing an SIO instruction. 
LSR Busy indicates: 


1. A printer chained command is in progress. 

2 A printer count command is in progress. 

2. An LCD feed, read ID, and locate next line operation is in progress. 

4 An LCD feed, read ID, and eject command is in progress and the ID 
number has not been transferred into main storage. 

5. An LCD read all line finder marks command is in progress and all the 

~ line finder marks have not been read. | 

6. An LCD read back and eject command is in progress and the line 
finder mark has not been read. 

7. An LCD index command is in progress. 


Note. \f the LCD LSR busy condition is true (active), printer and LCD 
operations cannot be overlapped. 


Read I/D Busy indicates that the ledger card 1D number is being read from 
the ledger card and transferred into main storage. This condition is present 
during feed, read ID, and locate; or feed, read [D, and eject operations only. 
During a read all line finder marks command, read ID busy is active until 43 
bytes (the complete card) have been read. 


Card Not Aligned indicates that the ledger card is not aligned at the first 
feed rolls in the LCD. This condition must be present before issuing the 
following commands: feed, read ID, and locate; feed, read 1D, and eject; 
and read all line finder marks. This test will also cause the LCD I/O atten- 
tion light to turn on, and raise the LCD card gate if a card is not in the LCD. 


5406 PRINTER ATTACHMENT -~— Introduction 
_ Advance Program Level Instruction Format (Part 2 of 2) TNL SN34-0043 to SY34-0022-1 5406 FETMM _— (6/71) 9-107 


5406 PRINTER ATTACHMENT-— Introduction 
Sense I/O Instruction Format 


SENSE 1/0 INSTRUCTION 


e The sense instruction consists of three or four bytes (three if indexing 
is used). 


@ The sense instruction selects the matrix printer or the LCD when the 
device address equals E (hexadecimal). 


e Data from the area specified by the N code is placed in main storage in ° 
the location specified by the operand address. | 


e The sense instruction can be used at any time, whether the printer is 
busy or not. 


The sense instruction is composed of three or four bytes. The first byte is 
the op code, a YO (hexadecimal) which indicates a sense operation. The 
second byte is the O bye which contains the device address, an M code, 
and an N code. The third and fourth bytes specify the area in main storage 
to store the sense information. 


O Byte Description 


The upper four bits (bits 0-3) specify the device address for the matrix 
printer, E (hexadecimal). Bit 4 is the M code which is used to determine 
if the instruction is for.the printer (bit 4 = 0), or if it is for the ledger card 
device (bit 4 = 1). The lower three bits (bits 5-7) are the N code. 


Operand Address 


The operand address of the sense instruction specifies the location in main 
storage in which to store the sense information. 


Parity and Error Conditions 


The sense instruction is accepted at any time by the printer, A parity error 
detected by the attachment results in a processor check stop and the proces- 
sor check light comes on. 


TNL SN34-0043 to SY34-0022-1 5406 FETMM (6/71) 9-108 


SENSE 1/0 (SNS) INSTRUCTION FORMAT 


Op Code OQ Code Operand Address 
Byte 1 Byte 2 Bytes 3 and 4 


Storage Address 








Op code for sense 
instruction. 





Storage Address 













The two sense bytes are 
stored in the specified address 
and the specified address 

minus one. 


Y = 0011(3) or 
0111(7) or 
1011(B) 















Device address 
1110 (E) for matrix 
printer or LCD. 






Source 










Locate line address register (LLAR). 

010 With M bit = 0, Printer status bytes 1 and 2 (Note 1) 
With M bit = 1, LCD status bytes 1 and 2 (Note 4) 

011 With M bit = 0, Printer status bytes 3 and 4 (Note 2) 
With M bit = 1, diagnostic interface signals (Note 3). 

10X Print data address register (PDAR). 

11X Print command address register (PCAR). 








M Code 
M = O Selects printer. 
M = 1 Selects LCD. 











X = Bit not checked, can be either 1 or O. 


Note 1. Status bytes 1 and 2 Note 3. Diagnostic device interface signals 
j Status Byte 2 (oper addr -1) Status Byte 1 (oper addr) bat LCD Signals* (oper addr) Printer Device Signals (oper addr -1) | 


Skip line SS1 5213 printer attached 
Skip line SS2 Not vertical forms control 
Late mark Not bi-directional print feature 


Count end latch Horizontal cycle check 
Print left command Data check 
Matrix counter trigger 1 Margin check 


Special tie-off Secondary carriage EOF 

Card alignment SS -1 Not Rm sw 1 slow and not Lm sw 2 stop 
Spare Rm sw 2 stop or Lm sw 1 slow 

Spare Primary or secondary forms motion contact 
Stop SS Primary forms emitter advance 


Matrix counter trigger 2 Sync check 

Matrix counter trigger 4 ROS check 

Printer ready Vertical cycle check 
$S2 Primary carriage EOF 
$S1 Invalid command 





*If the LCD is not installed, this byte will be hex O00 with proper parity. 


Note 2. Status bytes 3 and 4 Note 4. Ledger card device status bytes 1 and 2 
i ope Byte 4 (oper addr -1) Status Byte 3 (oper addr) Status Byte 2: (oper addr ye Status Byte 1 (oper addr) 


Secondary carriage EOF Sense amp 1 Sense amp check 
ee Matrix output hammer dr 1 Sense amp 2 Card skew check 
Stepper trigger A Matrix output hammer dr 2 Sense amp 3 Drive check 


Stepper trigger B Matrix output hammer dr 3 Sense amp 4 Read mark check 

SSZ Matrix output hammer dr 4 Timing pulse Line finder mark check 
SSY ' Matrix output hammer dr 5 Drive check SS Invalid command check: 
SSX Matrix output hammer dr 6 Activate LCD feed clutch Card in switch on 

SSW Matrix output hammer dr 7 Hold busy SS 7 | Card out switch on 





BRO720B 


START 1/O INSTRUCTION 
e The start I/O instruction consists of three bytes. 


e The start I/O instruction selects the matrix printer or the LCD when the 
device address equals E (hexadecimal). 


@ The start 1/O instruction initiates cycle steals to obtain printer or LCD 
commands. 


The start 1/O instruction is composed of three bytes. The first byte is the op 
code, an F3 (hexadecimal) which indicates a start |/O operation. The second 
byte is the O byte which contains the device address, an M code, and an N 
code. The third byte is the I-R byte which contains the control code. The 
start I/O instruction has only one function, to initiate cycle stealing to ob- 
tain commands for the printer or LCD. 


O Byte Description 


The upper four bits (bits O—3) specify the device address of the matrix 
printer, E (hexadecimal). Bit 4 is the M code which is used to determine 

if the instruction is for the printer (bit 4 = QO), or if it is for the ledger card 
device (bit 4 = 1). The last three bits are the N code and are not used for a 
printer start I/O instruction. 


I-R Byte (Control Code) 


The I-R byte contains the control code. For the printer, it specifies if the 
operation to be performed is a serial or a bi-directional print operation. For 
the LCD, it specifies if a diagnostic read all line finder marks operation, or 
a normal LCD operation is to be performed. 

A control code of XXXXXXX0O specifies a serial print operation or a nor- 
mal LCD operation. 

A control code of XXXXXXX1 specifies a bi-directional print operation 
or a diagnostic read all line finder marks operation for the LCD. 


Parity and Error Conditions 


Odd parity must be maintained in the start I|/O instruction. If a parity error 
is detected in the attachment, a processor check stop occurs and the pro- 
cessor check light comes on. Program interlock is effective if a printer busy 
condition is detected, or if operator intervention is required as indicated by 
the 1/O attention light. 


$406 PRINTER ATTACHMENT- Introduction 
Start I/O Instruction Format 


START I/O (SIO) INSTRUCTION FORMAT 


Op Code OQ Code 
Byte 1 Byte 2 


Op code for start 1/O 
instruction. 


Device address M Code 


1110 (E) for 
matrix printer. 


M = O Selects printer. 
M = 1 Selects LCD. 





X = Bit not checked, can be either 1 or O. 


TNL SN34-0043 to SY34-0022-1 


BASIC SIO OPERATION FOR THE PRINTER OR LCD 


Control Code 
Byte 3 


SIO instruction issued - 
to the printer or LCD. 


Control Code 


Printer or LCD attach- 
ment selects LSR PCAR 
and requests a command 


XXXXXXXO cycle steal. 


or 
XXXXXXKX1 
(see text) 


The CPU addresses main 
storage as specified by 
the PCAR. This will be 
the printer command 
byte or the first byte of 
the LCD command field. 


N Code = XXX 


Not used In 
start 1/O. 





BRO721B 






Printer Printer 
Command Byte 
Structure 





Device 
selected 





Command Chain 


LCD 


Print Data* 
Horizontal Tab Right* 


| LCD commands and 
command field formats 


Horizontal Tab Left* 


are shown on page 
9-403. 


Primary Carriage Skip* 





Element Return 
Secondary Carriage Index 


Primary Carriage Index 





*Requires a count byte if bit is on. 
BR2500 


5406 FETMM = (6/71) 9-109 


5406 PRINTER ATTACHMENT -Introduction 


Errors (Part 1 of 3) 


Horizontal Cycle Check 


Data Check 


Description 


A horizontal cycle check will occur if there is no response from the 
motion contact within 35ms after a horizontal action command 
was initiated by the attachment (print, tab, or element return 
commands). 


A data check is a parity check detected by the attachment data 
register during a cycle steal to obtain a data character. The char- 
acter in error will not be printed. 


lf the character in error was not the last character to be printed, 


the next sequential character will also have been spaced over by 


the time the print element comes to rest. 


Recovery 


The PCAR is pointing one position beyond the position that failed. If 
the attachment indicates no other problems, the program may sub- 
tract 1 from the PCAR and give a start I/O to retry the same command. 


To resume operation at the point where the data check occurred 
use the following procedure. 


lf machine has bi-directional print feature, issue a sense 1/O 
to determine the status of the print left command. If this 
bit is off, continue with this recovery procedure. If this 

bit is on, skip to paragraph 3. 


The PCAR will be pointing at the byte directly to the right (+1) 
of the count byte of the command that failed. Issue a sense !/O 
to the PCAR and retain the address. Subtract 2 from it, and issue 
a load 1/O to load the PCAR with the results. The PCAR is now 
pointing to the command in which the error occurred. 


Subtract 1 from the originally stored PCAR address to obtain the 
count address. Issue a sense !/O status to check the status of the 
‘count end’ bit. If it is off, use a value of (X = 2) in the following 
procedure. If it is on, use a value of (X = 1). 


Add (X) to the content of the count byte just determined. 
Issue a sense I/O to the PDAR. Subtract (X) to determine the 
address of the character in error. Issue a load I/O to load the 
PDAR with this address. 


Reposition the print element to the left (X) print positions. 


The attachment will attempt to print the same character in the 
correct position, if a start I/O instruction is issued with bit 7 of 
the IR byte off. 


lf a complete retry of the print operation is desired, use the 
following procedure. 


Enter a programmed halt state. Upon depression of START, the 
element should be positioned at (software) left margin on the next 
line and the entire print operation retried. This can be a retry of the 
entire last chained operation called for by the program, rather than 
a retry of the last physical print function. 


Issue a Sense |/O PCAR and retain the address. Subtract two from 
the address and store the result in the PCAR via a load 1/O instruc- 
tion. This will have repositioned the PCAR to the command in 
which the error occurred. 





5406 FETMM (2/71) 9-110 


Notes 


If a horizontal cycle check occurs during a command which had a 
vertical command included in the same command byte, the vertical 
command will have been attempted and properly completed, if possi- 
ble. In this case the recovery routine should involve only the re-issuance 
of the horizontal command. 


Then subtract one from the originally stored PCAR address to 
obtain the count address, Sense I/O status, and check the status 
of the ‘‘count-end” bit. If it is off, use (X=2) in the following 

procedure and (X=1) if it is on. 















Add (X) to the content of the count byte just determined. 






Sense 1/O PDAR. Add (X) to determine the address of the char- 
acter in error. Load 1/O PDAR this address. 







Reposition the print elements to the right (X) print positions. 


At this time, if a Start !/O instruction with IR bit 7 ‘‘on’’ is given, 
the attachment will attempt to print the same character in the 
correct position. 









if desired, the complete retry procedure given in paragraph 2 may 
be used. 




















The element should be re-oriented to the (software) left margin. If the left 
margin status bit is not on, an element return command must be given. 





Margin Check The ‘margin check’ latch is set, and motion is terminated under 
the following conditions. If the count byte is not zero when the 
left margin switch is encountered during a horizontal left count 
command, or if the count byte is not zero when the right margin 


switch is encountered during a horizontal right command. 


A margin check will not occur on element return commands. 







2. At error detection, the PCAR may be pointing at the next 
command or at the count byte (see Data Check error 
recovery). 























Sync Check When a sync check is detected, it is stored in a hardware latch. 
The attachment corrects itself, and the operation continues 
until normal count end. A print command which resulted in a 
sync check would have been properly completed, but possibly _ 
One character may not have been properly printed. Sync checks 


may occur on all horizontal commands except element return. 


A programmed halt state must be entered and the operator may be given 
the following options: visually check the print out and continue, use a 
program check point to restart and reprint only the form in error, or 
restart the complete job. 


A sync check can be caused by either of the following conditions. 










1. Either less than seven or more than seven horizontal print 
gate emitter pulses were received from the printer during 
movement through any character position. 












The recovery procedure may also automatically reposition the print 
element at (software) left margin on the next line and retry the entire 
last print operation as per Data Check error recovery procedure 1. 






2. The counter keeping track of the stepper motor is not in 
synchronization with the counter keeping track of the 
print gate emitter pulses. 






2. If a sync check occurs on a tab command, the operator should 
be encouraged to continue as the recorrect function should be 
successful almost 100% of the time. 





| 5406 PRINTER ATTACHMENT- Introduction 
Errors (Part 2 of 3) | | | 5406 FETMM (2/71) 9-111 


5406 PRINTER ATTACHMENT ~— Introduction 


Errors (Part 3 of 3) 


Error 


ROS Check 


Vertical Cycle Check 


Invalid Command 


Data Bus Out Check 


Description 


A ROS check is a parity check on one of the seven bytes which 
make up one print character as it is being read out of the ROS 
module to be printed. Printing is immediately suppressed and 
the operation is terminated. 


lf the character in error was not the last character to be printed, 
the next sequential character will also have been spaced over by 
the time the print element comes to rest. 


A vertical cycle check occurs when no feedback response is 
received from the printer within 35ms (120ms on pin feed 
printers) after a vertical action command was initiated by the 
printer attachment. This includes primary index, primary skip, 
and secondary index commands. 


An invalid command was issued to the printer attachment. 
The invalid command will not be executed, the command 
chain will be broken, and the attachment immediately drops 
busy. 


A data bus out check is a parity check on data bus out during 
the compute portion of a CPU cycle which is directly affect- 


ing the printer attachment. This includes I-OQ, |-R, B cycles, 
and during printer attachment cycle steals. 





Recovery 


Same as data check. 


Same as Horizontal Cycle Check. 


The contents of the PCAR must be decremented by 1 to point to the 
command issued. This address shou!d be checked to insure that it is 


the expected commanded address. If it is, issue another start 1/O 
instruction to retry. 


None. 





5406 FETMM ss (2/71) 


Notes 









It is possible that the first portion of the character was printed and 
error recovery will continue to overprint this portion. Normally this 
should not cause any harm, and successful retry will complete the 
character. 








lf a vertical cycle check occurs during a command which had 
a horizontal command included in the same command byte, 
the horizontal command will have been attempted and com- 
pleted properly if possible. In this case the recovery routine 
should involve only the reissuance of the vertical command. 












Because either a primary or secondary response will imply 
carriage motion, it is suggested to issue primary and secondary 
commands separately. 







The CPU will be forced to a hard halt at the end of the cycle in which 
the DBO check was detected. The CPU processor check indicator will 


be turned on. 





(9-111A) 


5406 PRINTER ATTACHMENT — Introduction 





























Data Flow 
wv 2 
| PDR Matrix Reg | 
0 1 
| | 
| | sete PY eg | | 
PC 
7 7 ~ PR154 7 
P P 
| PR274 PR271 | 
D Line Printer or 
B |e LCD Mode Only 
A | S| | 
Mi 
Main SDR B A tL DBI B 7 ae 
Storage Reg Reg L nstruction Reg | 
E t 
Channel R 
Controls [PR251 thru PR254 
Channel Channel Control In . LSR | 
Cee epee Select 
; Ch 1C 10 
SAR|SAR ae anne! Contro =. 
' Hi Lo - 
ALU eg Cycle Steal 
| fool! Controls 
: PR231 
thru 
PR234 


Carriage 
Control 





~LSR Select 


LSR{LSR t@ 
Hi | Lo 





Advance Stepper 
Motor 






5406 FETMM _ = (6/70) 9-112 


Pint 


- 
ee 





= | Hammers 


Print Emitter 


PRINTER 


Print Emitter 
Disk 


—7 | Stepper — = 
\ Motor Be A 


Phase A 
Phase Not A 










> Stepper >, 
|) Motor pactseas ae 
Controls 
CPU PR241 | Phase Not B is 
Emitter 
Disk 
Stepper Emitter Feedback 
ATTACHMENT 
re Stepper 
Ps . Emitter 
| Carriage : 
Drive . Carri : 
Shaft << arriage Emitter Disk 





Carriage Emitter 





Carriage Emitter 
ga << (for skipping) 


ee + Carriage Clutch 


Motion Contact (for Indexing) 


Chapter 2. Functional Units 


INTRODUCTION TO FUNCTIONAL UNITS 


Chapter 2 contains the functional units of the printer attachment and the 
error checking circuits. 

The first page of the chapter is a board layout of the printer attachment. 
It is broken down into cards and contains the following information: 


1. Card locations. 
2. Circuits found on that card. 
cP ALD page reference numbers that describe the circuits found on the 
card. 


4, Card type number. The part number of the card changes each time 
that the card has an engineering change to it. The card type number, 
however, always stays the same. 


The card location number appears on each page, or section of a page, that 
describes the circuitry on that card. For example, N2 on a page refers to 
the DBI assembler. 


Symbols 





Figures within this chapter contain the symbols: a numbers in squares, 
and ® letters in circles. These symbols refer to text marked with an 
identical symbol, that describes the function of the unit marked in the 
figure. 


5406 PRINTER ATTACHMENT—Functional Units 


Introduction to Functional Units 5406 FETMM = (2/71) 9-201 


5406 PRINTER ATTACHMENT—Functional Units 
Board Layout 














5406 FETMM 


(2/71) 9-202 





























































































































A2 B2 C2 D2 pegs —Er2** +: G2** 4+H2** i J2 K2 L2 M2 N2 P2 R2 S2 T2 U2 V2 
Printer Sense = LCD DBI # Cycle 4; Commands 21 ast Line Hori- Line Matrix DBI Stepper Cycle Com- Initial Pin Feed 
Sense Amplifier : 1.LCD S : Steal 5 : 1. Com- Bl 1. Docu- zontal Printing Controls 1. DBI as- Motor Steal mands Selection Carriage Miscel- 
enter a :  DBlas- 1. Cycle = mand t ment end : High 1. BIOIre: 1. ROS sembler | 1. Stepper 1. Cycle 1. Com- 1. Chan- ssi enous 
Cable = sembler 4 _ steal controls :| condition | a none matrix motor steal mand nel 
: # controls ‘}2. LSR and 1. High feature ere eontrols ean pegisiee See nciee Channel 
p 2.Read if 2. Busy af Eccles ay 2. ROS drivers ! ‘ #14 
ae ge Count 3. Drive steal latch a. Print . Printer 2.LSR 2. Error Be 
;  dataas- 3 end i ‘ ee output ham- controls | ALD Pages controls check- neg etee 
,  Sembier #3. LSR #4 Manual =f end steal 3. Parity Stepper | PR111 3. Counter Ing oe) 
2 3.Pulse H select 3 gio | REE Rs . Double aie: b. Stepper eee and advance | 2 S¥nC register | ALD Page 
Bo acca Ue 8 shift ie motor ie PR112 | check ade PR123 
eivcilits of a ey : 5. Invalid controls i Card Type | 4 FireSS1]  b. Margin “deeds Card Type 
Bo nein com. sae uabae: aoe 3368 5.Firess2| check 3376 
Ee oe = 4, Diag- »  controls# wang ter set oe c. Margin . LSR 
no Ee B3 C3 D3 2 nostic Ss Test i check J3 quar- anes ereoeS halt selec- V3 
hie =  LIO : : terin tion 
Eee LCD. Sense Bee eerie 0 +: 6. Error : : 7. FireSSA} d. 1/0 DBI 
a Sense =z) Amplifier : 3B * — checks 5. Print 8 Clock eneck . DBI 
= Amplifiers] #2 z 0. Pulse a. Sense data pulses = ep gating Channel 
ee oo : ener- : registe check 
E pape setts : : 2 cell air 9. Count . Diag- #2 
= ator % f. Data ; 
Rs % oS 2 b. Align- 6. Print end nostic 
Be = Circuits = check 
i : ment matrix controls | g ROS LIO 
is = 6. Sense : c. 1-O Bi soe ALD Pages | ALD Pages ALD Pages cheer controls 
i = cells = check # ALD Pages PR821 PR411 PR121 Bey 
: 2 d.Unit 3 PR841 and 2 and and Sng: . 3. Cycle . Condi- 
: 'e. Drive 32PR842 = & PR822 PR412 PR192 eens tion 
me ALD Page® = f. Print 32Card Type # Card Type | Card Type Card Type ing Regiekes 
ssPRO25 : mark =—- BE 6883 3 3381 3379 3367 a. Hori- 
ae oe OI : g. R ea d a aia 
Aa B4 c4 ss |D4 oo A Ja L4 04 b. Vertical ua vo 
Meter and Diag- Sense ‘LCD SS : ROS Busy ise Seer 
Tape nostic Amplifier £1. Skip line m7. Switch Matrix ‘ 4. Magnet oc 
= latches : . Busy Bick 
Cable Tape #3 - $81 si Module i g 
Input '2. Skip fine : a. Card aie a. Primary Channel Channel 
Card  g§s2 = gate; 2. Reset motion #3 ; #3 
3. Hold busy = b. Cardin : lines contact (Termi- 
4. Card = switch ee b. Second- nator) 
alignment : nee counter oo 
‘ALD Pages | - out | motion 
PR711 and 2 switch ALD Page 4. veal! contact 
PR712 2 d.Card PR151 option c. Print 
ALD Page ALD Page Card Type = aligned & Card Type drivers 
PRO41 PR141 3366 : e. Card : 7737 
ST tS sedae. 3 
AS BS CoE D5** switch § Jb K5 L5 U5 V5 
ae ea oe — veer DBO DBO 
ies ftp 2 card : | Channel 
1. Motion g2. Drive : g. Last #4 Channel 
COT SS i ae ete aad : line : (Termi- #4 
2. LCD Eas Mex nator) 
ies % to last 
Face E : ALD Pages : ALD Pages | ALD Pages ALD Pages} ALD Pages | ALD Pages | ALD Pages | ALD Pages 
E ALD Pages = i: PR811 PR271 PR251 PR241 PR261 PR231 PR221 PR211 
ALD Page —:PR721 and ae thru thru thru thru and thru thru thru 
PR641 - FPR722 ; PREIS PR275 PR256 PR245 PR262 PR234 PR224 PR216 
ALD Page Card Type [Card Type st tye Card Type 3: Card Type 3 Card Type | Card Type | Card Type | Card Type | Card Type | Card Type | Card Type 
PRO22 3382 23377 Se Ek 3384 Hf 3383 3375 3370 3374 3369 3373 3372 3371 





**Card locations for ledger card device. 
Printer Attachment Board A2 on Gate A (A-A2) (Card Side) 


PRINTER SINGLE SHOTS 


Single Shot One (SS1) 


@ SS1 is active for a duration of 35 ms. 


@ It is used to check for mechanical motion (both horizontal and 
vertical), 


SS1 is fired during each command cycle steal. Within 35 ms after it has 
fired, an electrical pulse must be received from the printer. If no pulse is 
received from the printer, a horizontal or vertical (depending upon the 
command) check occurs. 


Horizontal Cycle Check 


The ‘horiz cy inlk’ latch is set during the command cycle steal for every 
horizontal command. At the same time, SS1 is fired. Before SS1 times out 
(35 ms), the printer must activate the line ‘+6V right integrated emitter’ to 
reset the ‘horiz cy inlk’ latch. If this latch is not reset before SS1 times out, 
a horizontal cycle check occurs, 


Vertical Cycle Check 


The ‘vert cy inlk’ latch is set during the command cycle steal for every 
vertical command. At the same time, SS1 is fired. Before SS1 times out 

(35 ms), the printer must activate either ‘SP prim motion contact’ (for a 
vertical index command to the primary carriage) or ‘SP sec motion contact’ 
(for a vertical index command to the secondary carriage) to reset the ‘vert 
cy inlk’ latch. If a skip command is issued, a primary vertical emitter signal 
must be received before SS1 times out. If the ‘vert cy inlk’ latch is not re- 
set before SS1 times out, a vertical cycle check occurs. 

If commands are given simultaneously to both the primary and secondary 
carriages, only one of them can reset the ‘vert cy inlk’ latch. Both carriages 
have motion contacts, but there is only one interlock latch. Therefore, if 
both carriages receive vertical commands simultaneously, only one of them 
is checked for motion. 


SS1 


Spare 5 35 ms Q2 
_ SPSS1 
SP Fire SS1 A SS 


/ PR112 
Active at clock 6 of acommand cycle steal. 
BRO722 


Single Shot One—Overlap (SS1 Overlap) 


@ SS1 overlap is active for a duration of 120 ms. 
-@ It is used on printers with pin feed platens. 


e It is fired at the same time as SS1, and has the same function as SS1. 


The SS1 overlap single shot is used only on printers with pin feed platens. 
The mechanical action in these printers is slower and therefore more time 

is required to respond to electrical signals. SS1 overlap is fired at the same 
time as SS1. The result is a 120 ms duration pulse (instead of a 35 ms pulse) 
to give the printer more time to respond. 


5406 PRINTER ATTACHMENT—Functional Units 
Printer Single Shots 


SS1 overlap checks for horizontal and vertical cycle checks the same way 
as SS1 does. Refer to ‘Single Shot One (SS1)’’ for a description of how it 
checks for cycle checks. 


SS1 Overlap 


120 ms U2 


SP Prim Index Cmmd 
SP Fire SS1 





SP SS1 Overlap 











PR123 


Active at clock 6 of acommand cycle steal. 
BRO723 


Single Shot Two (SS2) 

@ S92 is active for a duration of 30 ms. 

@ Itis fired at the end of each command to allow for mechanical settling 
down of the printer. 


SS2 is fired at the end of every horizontal and vertical command to allow 
for mechanical settling down of the mechanics in the printer. It cannot be 
fired until SS1 has timed out. 


SS2 Q3 
Spare 5 oo 
SP SS2 
SP Fire SS2 
PR122 
BRO724 


Single Shot Three (SS3) 
@ SS3 is active for a duration of 600 us. 


e SS3 is used to gate the print drivers that fire the print hammers. 


SS3 is print time. It gates the print drivers to fire the print hammers. It is 
fired seven times per character. 





SS3 
Spare 0 eb us Sp ss3 Q2 
PR111 


Active on the rise of the print emitter pulse during a print command. 
BRO725 


Single Shot A (SSA). 


@ SSA is active for a duration of 1.3 to 2.0 ms. 
@ It starts mechanical motion of the stepper motor by providing the first 
advance pulse to it. | 


SSA is used to start the stepper motor. It provides the first advance pulse 
to It. 


SSA 
1.3-2.0 ms . O2 


pated SP SSA 


SP Fire SSA 






Active with ‘stepper go’. 
BRO726 


Single Shot W (SSW), Single Shot X (SSX), Single Shot Y (SSY), and 
Single Shot Z (SSZ) 


e Settings dependent on the type of printer installed. 
@ These single shots are used to stop the stepper motor. 


5213 Printer 2222 Printer — 


@ SSW is active for a duration of 1.3 ms 1.45 ms 
@ SSX is active for a duration of 1.6 ms 1.45 ms 
@ SSY is active for a duration of | 2.2 ms 2.1 ms 
® SSZ is active for a duration of 4.0 ms 2.8 ms 


These four single shots are the stop single shots. They supply the last four 
advance pulses to the stepper motor. They are fired in sequence (SSW, SSX, 
SSY, and SSZ). Each one has a longer duration time than the one previously 
fired. As a result the stepper motor slows down and stops. 


OQ3 


SSW 
eae Pee SP SSW 
~SP Turn On SSW 


. PR121 
Active at clock 7 with the ‘stepper stop’ latch set, 


and both stepper triggers off (electrical detent). 


Q3 


SSX 


SP SSW Inik L . 
SP Gated SSW or Y Time Out 









PR122 
- Active at clock 5 with the ‘stepper stop’ latch set. 


O03 


SSY 


Spare 1 | 
SP Gated SSX Time Out 





SP SSY 







PR121 


Active at clock 5 with the ‘stepper stop’ latch set. 


O2 
. | SSZ 
(Not) SP SSW Inik L | SP Ss7 
PR111 
Note. Single shot timing depends on the 
type of printer installed. 
BRO727 


5406 FETMM = (2/71) 9-203 


5406 PRINTER ATTACHMENT—Functional Units 5406 FETMM =. (2/71) 9-204 
Initial Selection (Part 1 of 2) | 


























































2 3 
Instruction 
Register SP Clock 5 
Chan !Q Cycle ; PH ( e ; | | 
Chan SNS Instr Select Decode . 
P 
Chan LIO Instr | | io SP EB Cycle ea 1 3 SP LSR Select LLAR 
Chan SIO Instr Cc 2 | 
Chan T!O Instr ese 4 45 
Chan EB Not 1 | | 8 
Chan EB 1 
P 
Chan IR Cycle Sr select) 
SP Select 6 
SP Select 7 
ene SP Select LCD _ 
SP Select SP 
Instruction pitta 
rinter 
A SP |-O Address Enet4 . . 
. SP LSR Select 4 and 6 
A : 
DBO ~ SP Clock 2 
p PR215 
: 0123 
PL 
DBO 3 Bir oh Se nevaend Ot. SP Chan 1 LSR Select 5 
SP Clock 5 PR215 
SP Power On Reset 7 
SP LSR Select 6 
OR 
Select 
SP PR215 
(Not) Block Serial Select 
te a A (Not) SP Manual Busy 7 
; SP LCD or Prt Busy ir SP Chan 1 I-O Working 
SP Clock 5 C DBOR Chk SP Chan 1 1-O Meter Run 


7 FL 
SP Control LIO E-B1 Cycle "| Pc “y BRAN 
: Condition A and B 
PR212 SP LIO N 


SP Attach Check Reset R 
C 


| : | PR214 
| 3 ot SP Diag Prt Emitter Adv T2 
SP Control L PDI 

, SS 10 E-B 1 Cycle C SP Diag Stepper Adv | 
SP DBOR Not 467 3 (4) | 
SP DBOR Not 567 aa 
SP DBOR Not 01234 N 
SP DBOR Not 24567 | Select | 

: | 
SP DBOR Not 1234567 SP Clock 5 C qi or Contel ROE SL pycle: | 
SP LIO. SP System Reset C 


DBO Decode | SP E-B1 Cycle : 
0 = bit inactive . PR215 SP Diagnostic Mode 
Instruction !-OQ Byte Condition 
; +34 . Incorrect DBO Parity Sy 


SP End of Forms 
(6 } SP Diag Integ Emitter 

SP Use 2nd EOF 
Correct Device address not recognized or N field invalid fF 30: | 
DBO Device address not rec- Instruction 

Ognized and N 

field invalid. Accepted OF 
I-R Byte, and !-O | Incorrect DBO Parity 
Correct DBO Parity 


























O00 0 


PR211° 


Parity 1 






Note 1. The ‘DBOR ck’ latch can be set during one of the following times: 
. 1. at clock 5 of the I-O cycle during and I-O instruction, or 
2. during cycle stealing with ‘SP steal cycle’ active. 


Cycle Condition 





INSTRUCTION REGISTER 


@ The instruction register consists of eight polarity hold latches. 





© Latches set determine the instruction and the cycle to be taken by the 
attachment. 


@ Latches have active outputs when their inputs are inactive. 


The four instruction lines (SIO, L1O, TIO, and SNS) indicate the presence 
of an instruction in the CPU register. If the printer attachment decodes its 
device address and a condition code acceptable to the instruction latch set, 
the instruction will be performed in the cycle that is called for by the 
instruction register. 


DATA BUS OUT (DBO) REGISTER 


@ The data bus out register consists of nine polarity hold latches, eight for 
data and one for parity. , 





e All data from the CPU enters the attachment through the DBO register 
and sets the appropriate latches. 


@ Latches have active outputs if their inputs are inactive (except for the 
5 bit latch which is also used for cycle steal priority. 


Eight data bits and one parity bit are transferred to the printer attachment 
from the CPU by the data bus out (DBO) lines. These data bits are sent to 
the DBO parity check circuits and to the DBO latches. 

The parity check circuits check each data byte sent to the attachment 
for odd parity. 

Data sent over to the DBO lines is set into the DBO register at CPU clock 
5 time. At the next CPU clock 5 time, new data is set into the registers or 
the registers are reset. 





LOCAL STORAGE REGISTER (LSR) SELECT 


@ Local storage register select selects printer attachment LSR’s (located 
in the CPU) to obtain print and carriage information, and to modify 
the LSR’s. 


e LSR select lines 4 and 6 select the print command address register 
(PCAR). 


e LSR select lines 5 and 6 select the print data address register (PDAR). 


@ LSR select lines 3 and 6 select the locate line address register. 


The LSR select circuitry is used to select the appropriate LSR to obtain 
print data, a command or a count. After obtaining this data, the LSR is 
reselected for updating. 


5406 PRINTER ATTACHMENT—Functional Units 
Initial Selection (Part 2 of 2): | 5406 FETMM (6/70) 9-205 


5406 PRINTER ATTACHMENT—Functional Units 


Printer Commands 





SP System Reset 


SP Cmmd Steal 
SP Clock 5C 


SP Lm Sw 2 Stop 

(Not) SP Sec Index Cmmd 
(3) SP System Reset 
. SP Clock 7 


(Not) SP Diagnostic Mode 
SP Reset Horiz Cy Chk Inlk 






SP Horiz 
Right Cmmd 


SP Go Right 1 Space "_] 
: OR 
oe 


SP Cmmd Steal 
SP Clock 5C A 


SP DBOR 6 


SP Sec Carr Motion Contact 
SP Attach Reset 
(Not) SP Attach Busv 


SP Line Prt 
or Elem at Lm 


LP Line Prt Mode 


SP DBOR 5 

SP DBOR Not 467 

SP DBOR Not 1234567 
SP Invalid Cmmd 


spe 


Aa SP Sec Index Cmmd 
or 3 


Command 
Register 


C 
SP Reset to Lhm L 


(Not) LP Line Prt Mode 


SP DBOR 5 
SP DBOR 4 


SP Elem Return Cmmd 
SP Prim Skip Cmmd 







SP DBOR 5 






SP Tab Left Cmmd 


SP DBOR 3 
SP DBOR 2 


QaaNaQ0N00 


PR221 


Prt Right 


SP Horiz Right Cmmd 


Cmmd Chained 


5 
SP DBOR 0 PH 


SP Cmmd Chained 


Sec Index : 
SP Attach Reset § 


PR222 


Prim Index 
DBOR 7 A | FL 


SP Prim Motion Contact. 
SP Attach Reset 
(Not) SP Attach Busy 


PR222 SP Prim Index Cmmd 


SP Prim Vert’ 


RF SBo00. Magnet Pick 


SP Count Busy 
(Not) SP Count Stop 
SP Prim Skip Cmmd 


| — 18 
p f PR222 
“No Cmmd 


SP Prim Vert Magnet Pick. 


SP No Cmmd 


SP Clock 2 
SP Attach Reset 


PR222 








SP Prt Left Cmmd 
SP Prt Right Cmmd 


Coe 
[SP Tab Right Gmmde |_| 





(Not) SP Go Right 1 Space 


SP Elem Return Cmmd 


$2 










5406 FETMM (2/71) 9-206 
2 
SP Horiz Left Cmmd 
on SP Horiz Left Cmmd 
| PRODI SP Print Cmmd 

§ SP Print Cmmd 

PR221 sp Horiz Left 

as Count Cmmd 
a SP Horiz Left Count Cmmd 

ot tease 
he none 
) ab Cmm 
PR221 SP Horiz Tab Cmmd 
LD LCD Installed 
PR221 
6 
SP Sec Index Cmmd 2 SP Vert Cmmd 
SP Prim Index Cmmd | | 
PR222 
or SP Vert Non Count Cmmd Busy 
SP Man Rgtor 
SP Prt Left Cmma “oriz Cnt Cmmd 
Ree cognac ol SP Tab Left Cmmd SP Man Rgt or Horiz Cnt Cmmd 
PY SP Horiz Right Cmmd 
SP Horiz 


Count Cmmd 


SP Horiz Count Cmmd 


SP Horiz Cmmd 


PR221 


Data Bus In (DBI) Assembler 


o The DBI assembler consists of nine 
latches and a decode circuit. 


© It separates all data to be sent to the 
CPU on DBI into data bits. 


All data from the attachment that is to 
be sent to the CPU is assembled in the 
DBI assembler and gated out during 
E-B cycles (with the exception of the 
force P bits). 


N2 


E-B1 Cycle 
E-B Not 71 Cycle 
M Code 4 


N Code 5 


N Code 7 


5406 PRINTER ATTACHMENT-—Functional Units 
Data Bus In Assembler 


ose 
o,e = 
ofes %. ogee se : 338 
esese oje ose . ote 
of . ote «fe ces: 
rer, 
Pete tet a ee te ee ee OOO OOO OOOH OOOO ett tata t ag? Oot tet ete te ee Oe ae oe oOo Oe. © 6. Oo 6 Oe eee eee e 
eet el et et asec esos esac at ec esecec ees ene sec eee este tate te teen teeta eae e eta O ete teeta tetera l etal leet eho l et el atet ata et at etet elect eter et elect et eceteresens Ocoee ee et tet et et eet el etal et etal sfetete cee t eee c eet eee OTe te ee eee et et eel tele ele a ele Lee OTe OLR e NOL F SRO O Tee TORE Cele et ele ete RE eNO T eNO ON ROC OREM OC ee COE eee eee e ee elapse tte eee enter et et ere ete e nee eT orev er ererereyey 
: age 
° soe 
: ote 
e = e e,° 
e * e eed 
. Pe ove 
e * e ote 
32 e e Sa eae a te eee ese tec eto te ee ee ate Fea a a eee Eee ete ocelot ete ole se 
‘° 
° 
e: 
° 





















LD Status 2 
PR831 


_D Status 3 
PR831 


LD Status 1 
PR831 













PRO21 





SP Gate 2 





SP Gate 1 







SP Gate 3 SP Gate 4 SP Gate 5 


SP SSA 5213 Printer 
attached 
SP Stepper Tr A 


SP Stepper Tr B 


























SP Horiz Cycle SP Count End LD Skip Line SS1 LD Sense Amp 1 SP Force DBI Bit O 


Check 


LD Sense Amp 
Check L 


Secondary 
Carriage EOF 










Ch Data Bus In O 
PR252 





























LD Card Skew 
Check L 


SP Force DBI Bit 1 





Not Vertical Forms LD Skip Line SS2° LD Sense Amp 2 


Control 


SP Data Check 





SP Prt Left Cmmd SP Matrix Output 1 






Ch Data Bus In 1 
PR252 





















LD Late Mark L' 





SP Matrix Counter LD Drive Check L LD Sense Amp 3 SP Force DBI Bit 2 


Trigger 1 


SP Matrix Output 2 Not Bi-directional 


Printer Feature 








SP Margin Check 






Ch Data Bus In 2 
PR252 

























LD Special Tip-off 





LD Read Mark SP Force DBI Bit 3 


Check L 






SP Secondary EOF LD Sense Amp 4 





SP Matrix Counter 
Trigger 2 


SP Sync Check SP Matrix Output 3 


Ch Data Bus In 3 
PR253 
































SP ROS Check SP Matrix Counter SP Matrix Output 4 Not SP Lm Sw 2 LD Card Alignment | LD Line Finder LD Timing Pulse SP Force DBI Bit 4 























Trigger 4 Stop and Not Rm SS Mark Check L Ch Data Bus In 4 
Sw 1 Slow Se 
PR253 
SP Vert Cycle Printer Ready SP Matrix Output 5 SP SSY SP Rm Sw 2 Stop or | Spare LD Invalid Cmmd LD Drive Check SS SP Force DBI Bit 5 
Check SP LmSw1Slow Check Ch Data Bus tn 5 
PR253 
SP Primary EOF SP SS2 SP Matrix Output 6 SP SSX SP Primary or Spare LD Card In Switch On| LD Activate LCD SP Force DBI Bit 6 
Secondary Motion Feed Clutch Ch Data Bus In6 
Contact | 


| . PR254 





SP SSW SP Vert Emit Adv LD Stop SS 











SP Invalid Command | SP SS1 SP Matrix Output 7 LD Hold Busy SS SP Force DBI Bit 7 





Ch Data Bus In 7 
PR254 





SP Force DBI Bit P 


gece 
ose 
ese 
Ses 
Sess 







Ch DBI Bit P 
PR251 


ote <Te 
efetetesesece : ote tetesesscesece 
crete lesecasesececetesesecsceses teeta hte est state tenet etetetetetesesesesesecore 


5406 FETMM = (2/71) 9-207 


5406 PRINTER ATTACHMENT-—Functional Units 
Stepper Motor Controls 









Stepper 
Advance 
Latch 

















Stepper 
Inlk 
Latch 


STEPPER MOTOR OPERATION 


The stepper motor controls the horizontal movement of the print element 
during printing, tab operations, and element return. 


Advance pulse to motor causes rotor to move. 


Emitter wheel mounted on rotor shaft rotates past the feedback 
emitter. 


Emitter pulse generated by feedback emitter returns to the 
attachment. 


Attachment circuitry converts the emitter pulse to MST. 


This pulse is decoded by the attachment circuitry to generate an 
advance pulse to the stepper triggers. 


The stepper triggers generate another advance pulse to the stepper 
motor. 


a 


Another feedback emitter pulse is generated and the cycle is 
repeated. 


Shift Controls 
(Hi-Lo Speed) 


PR281 


Allow Shift 


5406 FETMM (2/71) 9-208 


ATTACHMENT PRINTER 


N2 


Feedback emitter disk 







Stepper 
Trigger 
Advance 














Stepper advance 
pulse controls 


PR241 








Emitter rise- 
fall decode 


PR242 


Select 









Stepper go and SSA 
(initial advance pulse) 





P2 | Stepper trigger ~| 
A and B pulses. 










Motor Advance Pulse Motor Advance Pulse 
Sequence (Forward) Sequence (Reverse) 
Phase Phase Phase ‘Phase Phase Phase Phase Phase 
A Not A B Not B A Not A B Not B 


ON ON ON 
OFF . ON OFF 
OFF OFF OFF 
ON OFF ON 
ON ON ON 


Stepper Trigger A sgh) Sil ide ae ian nee ee 


— ~~ Electrical detent 


——p- Electrical detent 





First advance pulse is 
generated by SSA. 


Feedback Emitter 





Stepper Advance Pulse 


Stepper Trigger B 
Stepper Trigger Not A 
Stepper Trigger Not B 


cn i ee 


BRO/728A 













Character to f{ 
DBO be printed 





































To print hammers 










Print Hammer 





= ROS Module (4) > 7+P om ROS Control Xm7  solect =] 
! | PR151 L4@ | PR271 PR255 
alee | = SP Print Driver ar 
ae a Se et ee ee ge es | ee Checks 7 bits and parity 
(clock 5C and data steal) i | | : for odd parity. 
DBI | | —_ 22182 _ _ 4 443 
Assembler First vertical row (printing 
; 04 left to right), or last 
Bi-directional print or , PRoG2 | eae pene 
LCD operation only _ | (print emitter) ? 
oa | ae 7 sige aaonsies 
| Hammer 1 
PR252 
N2 | Hammer 2 
BASIC PRINT OPERATION Hammer 3 
ey During a data cycle steal, the character to be printed is brought over The matrix counter advances to two and gates the ROS module. esa 
from main storage and placed in the DBO register. At clock 5C time This operation continues until all seven print emitter pulses have 
the character is gated into the print data register (PDR). been received and the print hammers have fired seven times to eel 
7 L | complete the character. | 
The contents of bit positions 2 through 7 of the PDR are converted 
Hammer 6 


to ROS inputs. These inputs remain active at the ROS module until 
the character is printed (for 7 print emitter pulses). 


The ROS module converts the active input lines into the character 
to be printed. 





4 | The matrix counter advances to a count of one upon receiving the 
first print emitter pulse. 





The matrix trigger one being on, gates the first of seven outputs per 
character from the ROS module to the ROS control. Since the 
character is printed on a seven by seven matrix, the ROS module is 
gated seven times by the matrix counter (advanced by the seven print 
emitter pulses). 


Gi The output of the ROS control is checked for the correct ROS 
parity (odd). | 


The print hammer select determines which hammers are to be fired 
in print position one (for the first vertical row of the character) and 
sends pulses to the printer to energize the selected print magnets. 





EB The selected hammers are fired and another print emitter pulse ts 
sent to the matrix counter. 


5406 PRINTER ATTACHMENT-—Functional Units 
Print Controls : 


PRINT DATA REGISTER (PDR) 


@ Consists of nine flip latches, eight for the data character and one for 
parity. 





@ Retains the data character during printing. 


During the data cycle steal the character to be printed is stored in the PDR. 


The two through seven positions are used to determine the ROS character 
to be printed. The data character is held in the PDR until the character ts 
printed and is replaced with the next character to be printed during the 
next data cycle steal. 


READ ONLY STORAGE (ROS) MODULE 





e Consists of four modules. 


@ Translates the output of the PDR into the character to be printed. 


The ROS module translates the output of the PDR into a printable charac- 
ter. The ROS module has an active output seven times per character (gated 
by the matrix counter), once for each vertical row of the seven by seven 
matrix that forms the character. 





Print Character 
Matrix (7x7) 


Print position one (printing left to right), or 
print position seven (printing right to left). 


BRO729A 





€ MATRIX COUNTER 
@ Consists of three flip-flop triggers. 


@ Is advanced by the print emitter. 
@ Binarily counts to seven to gate the ROS module. 


@ Resets to zero after counting to seven. 


The matrix counter counts the print emitter pulses (seven per character) 
and gates the ROS module seven times per character. The seven matrix 
counter pulses must fall within the time that the integrated emitter is active. 
If not, a syne check occurs. 


5406 FETMM = (2/71) 9-209 


~ 


5406 PRINTER ATTACHMENT—Functional Units 
Print Hammer Selection 


2 

3 

4 
From DBO Xx 5 
register ee 


(clock 5 and data steal) 





SP ROS Input 7 





SP ROS Input 5 





M2 SP ROS Input 4 





DECODING AND PRINTING THE CHARACTER ‘H’ 
ae The character ‘H’ is stored in the print data register to be printed. 











The output of the 2, 5, 6, and 7 latches of the print data register is 
converted to ROS inputs 7, 6, 5, and 4 respectively. These lines are 
held active for the entire character. 


The first print emitter pulse causes SS3 to fire which advances the 
matrix counter to one. With matrix counter one active, ‘SP ROS 
input 1’ is activated. 


The decode for an ‘H’ is stored in the third ROS module. Therefore, 
print data register latch 4 is active and decodes to select the third 
ROS module by activating ‘SP ROS mod 3 select’. This ROS module 
stays selected for the entire character. 


The ROS module decodes the first vertical row of the character ’H’ 
to be printed, and selects all of the print hammers. 


All of the hammers fire at SS3 for 600 us, and the first vertical row 
of the character is printed. SS3 was actually fired prior to the time 

that the matrix counter was stepped to one, but the hammers could 
not respond at this time. 


The second print emitter pulse causes SS3 to fire again. The matrix 
counter advances to two, and the second vertical row of the character 
is decoded in the ROS module. This time no hammers are selected. 


SP ROS Input 6 


| | “"H"’ decoded here. | 


onl 







ROS Modules (4) 
DCD SP ROS Mod 1 Select 









{ 
0 
_P48 Char Set 1 9 SP ROS Mod 2 Select 1 
| SP PDR3 2 4 SP ROS Mod 3 Select 
SP PDR4 i 6 SP ROS Mod 4 Select | 
7 
For an ‘‘H” to be A p 
printed, this line PR275 
is active. | | SPSS3 
1 | 
(matrix 
(2) (ROS out) out) 
7 
P | PR271 














Matrix. | 
Counter [. | (3) ee 
2 ; SP ROS | | 
SP Matrix Counter Trigger 1 Input 1 7 
Conv | P | 
SP ROS 
SP Mairix Counier Trigger 2 i t 2 
| ; | 
SP Matrix Counter Trigger 
PR275 f | 
a PR151 P 


This procedure is repeated until the matrix counter has advanced 


to a count of seven, and all vertical rows of the character have been 
printed. After the seventh print emitter pulse, the integrated emitter 
falls and a count cycle is requested unless the attachment has reached 
‘count end’. 





5406 FETMM (6/70) 9-210 


-B Print Hammer 1 
-B Print Hammer 2 
-B Print Hammer 3 
-B Print Hammer 4 
-B Print Hammer 5 
-B Print Hammer 6 
-B Print Hammer 7 


BRO730 








| Cmmd 
fs a 
Set Cmmd Req (SIO Clk 7B) , 










FL 
Priority Request Bit 5 
| Cmmd fe 
4 | Steal [ama 
Cycle Steal Honored PR231 EL Cmmd Steal 
Cnt Cmd ae A 7 





Initial Left Data Steal (prt left cmd) PR231 


~ (Not) SP Count Stop © 












SP Set Req or Reset Cnt Busy Poo A PR231 
Count Steal 
This AND block will be made to request Ro 
count cycle steals (followed by data 
cycle steals) until a count of FF 
is reached in the count byte. It is 
activated at the fall of the 
integrated emitter. Prt Cmd 
Data 
Steal 
Data Steal 
[Ay FL 
PR231 
Note 1: Take cycle steal 
to get command 
I-R Cycle Request Cycle Steal Request Cycle Steal Request Cycle Steal from PCAR. 
012345678]01 234567810123 4567 8101234567 810123456781/01234567 8)/012345678 Note 2: If required, take a 
| | cycle steal to get 
Set Cmmd Req count from PCAR. 
A 2| Cmmd Req FL Note 3: Take cycle steal 
3 to get print data 
Priority Request Bit 5 from PDAR. 
za Cycle Steal Honored Note 4: Commands with 
count bytes require 
Cmmd Steal FL only one command 
; cycle steal. After 
ee Count Req FL the first command, 
| count, and data 
Count Steal cycle steals; the 
| sequence is 
8 Data Req FL count and data 
cycle steals — 
Data Steal until count end 
is reached. 
5406 PRINTER ATTACHMENT-—Functional Units 
Cycle Steal Controls 5406 FETMM (2/71) 9-211 


5406 PRINTER ATTACHMENT-—Functional Units 
Error Checking (Part 1 of 2) 


Horizontal Cycle Check 


A horizontal cycle check occurs when a horizontal command (print, tab, 
or element return) is given to the printer and no feedback response is re- 
ceived from the printer within 35 ms (SS1 time out). The check for this 
condition is as follows: 


e A horizontal command is given. 
e@ SS1 is fired (it is active for 35 ms). 
e The ‘horiz cy inlk’ latch is set. 


® The printer should activate ‘matrix counter tr1’ indicating 
that mechanical motion has taken place. 


e ‘Matrix counter tr1’ activates ‘SP reset horiz cy chk inlk’ to 
reset the ‘horiz cy inlk’ latch. 


e If the response (‘matrix counter tr1’) is not received within 
35 ms, SS1 times out and the ‘horiz cy inlk’ latch remains set 
causing a horizontal cycle check. 


Vertical Cycle Check 


A vertical cycle check occurs when a vertical command (primary index, 
secondary index, or skip) is given to the printer and no feedback response 

is received from the printer within 35 ms (SS1 time out). For printers with 
pin feed platens, a response time of 120 ms is allowed for primary index 
commands. This is because these printers have a slower mechanical response 
time. The procedure for checking for vertical cycle checks is as follows: 


e Avertical command is given. 


@ SS1 is fired (it is active for 35 ms). If the command is a primary index 
command for a pin feed platen printer, SS1 overlap also is fired (it is 
active for 120 ms). 


@ The ‘vert cy inlk’ latch is set. 


@ The printer should respond with a motion contact pulse. The response 
to a command to a primary carriage activates ‘SP prim motion contact’. 
The response to a command to a secondary carriage activates ‘SP sec 
motion contact’. These lines active indicate that mechanical motion has 
taken place. 


e Either of these lines active resets the ‘vert cy inlk’ latch. On a skip 
command, the carriage emitter pulse resets the ‘vert cy inlk’ latch. 


@ If these responses are not received within 35 ms (120 ms for pin feed 
platen printers), the ‘vert cy inlk’ latch does not reset and a vertical 
cycle check occurs. 


Horiz Cy 
SP Horiz Cmmd Inlk 


(Not) SP Invalid Cmmd pF 
SP Cmmd Steal SP Clock 6 A | 
SP Attach Reset : 
Integrated Emitter | OF] 

A 


Matrix Counter Tr1 PR224 
Allow Shift 
Vert Cy 
Inlk 


SP Vert Cmmd 


SP Cmmd Steal ¢ SP Clock 6 A FL 
SP Attach Reset 
SP Vert Rise Pulse on 


PR224 


(Not) SP Prim Skip Cmmd 


SP Prim Motion Contact —— . 









SP Sec Motion Contact 


From motion contact on secondary carriage. 


From motion contact on primary carriage. 


SP SS1 TimeOut © SP Clock 6 a —=L 
or] “| 


SP Attach Reset ~ 
SP Attach Check Reset 


PR224 


$2 


5406 FETMM)s(2/71) 9-212 


SP (Horiz or Vert) Cycle Check 


BRO731A 


SP Data Steal 
SP Clock 6 B 
SP PDR Even Parity 


SP SS3 Time Out 
SP ROS Even Parity 


SP Man Rgt or Horiz Cnt Cmmd 
SP Set Sync Check 


SP Clock 5 


, _ (Not) SP Hi Speed Inlk 


SP Elem Return Cmmd 
SP Elem at Lm 


SP Rm Sw 
SP Horiz Right Cmmd 


SP Horiz Left Count Cmmd 


(Not) SP Count Stop 

SP Matrix Count 3 

SP Man Rgt or Horiz Cnt Cmmd 
SP Set Syne Chk 

(Not) SP Hi Speed InIk 


(Not) SP Stepper Go L 
SP Clock 5 


SP Integ Emitter Fall 

(Not) SP Matrix Count 7 

(Not) SP Stepper Count 0 

SP SS2 Time Out 

SP SSA Time Out 

(Not) SP Rt A No B Lft BNoA 
(Not) SP Matrix Count 0 


Matrix ctr out of step 





Motor not electrically 
detented after settle 
down time 








No motor advance in A 
either direction after 
initial start pulse 


5406 PRINTER ATTACHMENT-—Functional Units 
Error Checking (Part 2 of 2) 






SP Attach 


ea" 


Reset 


SP Cmmd Steal 


PR244 





wy 


Margin Halt 


i Cs 
HOOUWFLL 

i 

L 

8 

i 

bi 

3 


SP Attach Check Reset. 





PR223 







SP Count Busy 


(not vert cy Inlk latch) 


SP Set Sync Chk 


SP Prim Skip Cmmd 





S2 


P2 


SP Margin Halt 


nm 





SP Data or 
ROS Check 


PR223 


SP Data or ROS Check 





SP Data Check: 


SP ROSCheck 


SP Sync Check 


SP Margin Check: | r 


PR223 


SP Cover Intk Sw or Carr N/C Sw 


(Not) SP Attach Check Reset 
SP Invalid Cmmd 
SP Sync Check 





PR223 


SP Horiz Cycle Check 
SP Vertical Cycle Check 


He 


SP Stepper Go L 
(not horiz cy In!k latch) 


uo 


SP Unit Check or Cover Inlk 


PR223 


SP Ch 1-O Check 
SP Gated Unit Check 


SP Cycle or Margin Check 


5406 FETMM ss (2/71) 9-213 


Chapter 3. Operations 


INTRODUCTION TO OPERATIONS 


Chapter 3 contains detailed flowcharts and timing charts of the operations 
performed by the printer attachment. 


Flowcharts 


The flowcharts contain three levels of information. By reading down the 
heavy dark lines, the reader can learn the major objectives of the operation. 
The second level of information is obtained by reading the information in 
the boxes that branch off the heavy dark line. The information that is con- 
tained in each block in a heavy dark line is explained in the blocks that 
branch off from it. 

The third level of information is contained in the note blocks (open ended 
blocks) that branch off the second level blocks. Information in these blocks 
is intended to explain why an action has been performed. 


Timing Charts 


The timing charts in this chapter are to be used to supplement the informa- 
tion found in the flowcharts. 


5406 PRINTER ATTACHMENT-— Operations | 
Introduction to Operations | 5406 FETMM (6/70) 9-301 














5406 PRINTER ATTACHMENT-— Operations 5406 FETMM ss (2/71) 9-302 
Load I/O Instruction Flowchart 
1 2. 3 
Op Code Q Code Storage Address 1 
Before taking the B cycle(s): 
Operand address 1. Condition code B (except for a control load |/O) 
Yn ese Pee, must be sent to the CPU. If not, an I-R back-up Aaa 
0 70 345 70 15 is performed. That is, the |-Op and 1-Q cycles ae 7 Yes 
will be repeated until a condition code of B is (load PCAR 
* M bit is O unless decoded and sent back to the CPU. aa PR211 












- the LCD device is 
















NO 














. The CPU will (depending upon the Op code) 
















LIO) 


Activate ‘SP E-B cycle’ 

































installed and the load Take B cycle (s) to: No 
\/O is for the LCD. 4. Bartormnca take either: an I-X1 cycle, or an I-H1 cycle for two B cycles. First 
éantrol lasd and an !-L1 cycle. by activating ‘Ch E-B 
** = Bits tested for by the function, or 1 cycle’ then ‘Ch E-B 
attachment. not 1 cycle’. 
. Select the 
| PCAR, or N code PR215 
A a ta chee 01X Yes During the B cycles, the 
Load 1/O BAR . (control code ‘Ch LSR select 4’ and ‘Ch 
Instruction , LIO) LSR select 6’ are activated. 
At ‘SP clock 5C : : 
. Select the sista SP Cano) During the first B cycle 
LLAR. aye i s : the PCAR lo order byte is 
LIO E-B1 cycle’. : 
addressed; during the sec- 
E-B . 
31, 71, or B1 ond B cycle the hi order 
ye : _ Cycles . 
decoded during byte is addressed. 
a CPU |!-Op cycle ‘Ch LIO instruction’ 
indicates a load is activated in the N code } 2 
1/0. attachment. 10X Yes 4g 
(load PDAR PR211 N code 
|-Op | LIO) Activate ‘SP E-B cycle’ for 00x Yes 
Cycle 5 No two B cycles. Once by (load LLAR PR211 


LIO) 


activating ‘Ch E-B 1 cycle’ 











si di Ch E-B not No Activate ‘SP E-B cycle’ for 
1. Sample Q code vee two B cycles. First by ac- 
for device address. PR211 PR215 tivating ‘Ch E-B 1 cycle’ 


Any other N code is inval- 
id. A processor check stop 
would occur and the pro- 


then ‘Ch E-B not 1 cycle’. 


During the B cycles, the 
‘Ch LSR select 5’ and 
‘Ch LSR select 6’ lines 
are active. During the 
first B cycle, the PDAR 


Activate ‘SP 1-O 
instruction’. 


















. Determine and 
notify CPU of 
condition code. 





cessor check light would 
come on. 


PR215 


During the B cycles the ‘SP 
LSR select LLAR’ line is 
activated. During the first 
B cycle the LLAR lo 


PR213 


If DA is E (1110), 
activate ‘SP DBOR 
012 not 3’. 





lo order byte is addressed; 
during the second B 
cycle, the hi order byte 

is addressed. 





Cycle 


order byte is addressed. 
During the second B 


PR214 cycle the Hi order byte 
At ‘SP clock 5’ set If M bit is O, set i / is addressed. 
8B the ‘select SP’ latch. ‘select SP’ latch. Load 1/O 1-0 hee ON Condition 
- If M bit is 1, set 



















PR216 ‘select LCD’ latch. 


Device address not oo, «| 
or N ere ae invalid. 





Determine the 
condition code and 
activate ‘Ch 1 |-O 
























Correct ; 
Sencar ASDC OR, tne aepcee a ieee eee eee) oan |p lacie =< End of 
Ch 1 1-O condition B’. Parity ee Operation 
N field Accepted 
valid. 


Load |1/O E-B 
Cycles 


Incorrect DBO Parity fw 





sana 





CPU cycles for addressing: 
1-X1 or |-H1 
and |-L1. 









1-Op Cycle 1-Q Cycle 


Line Title ALD Page 01 23456781012345678)01 2 
1 | Ch LIO Instruction 
SP 1-O Instruction . 
SP DBOR 012Not3 
pa Select SP Latch 
Ch !-O Conditions (A-B) 


EB-1 Cycle EB Not 1 Cycle 




















a '(i*dh te ee ww ew nee eee nc eacecacanncscncncncncecesscnssecsencssenceseceresesaspanrseseccsccsesecscsensebecsesssccnncccsevessucscosseesesosets 
Si [rete e e's ee resecereseseseses eset esesresseseseseeeeesueesesetsseseseesese spe seesesesereseresesesedessesersscesereresesesssesene rete 


bea, 


soe 
eee 


POPC C a mH ome seh eee sO Het ere ees EEE Hen a EEE ROEH EHR ERE E RESORT HEH ELE E ET ETE EeeseeereEersneeeeeapsoesere 
eee sooo emer sere eee rere ree sere eee ERNE EOE E HEHE EES OD eee Heese mbes eee sneee es eeesee sass descsscs 


I\f N Code is O1X: 


el SP Control LIO E-B1 Cycle PR215 
















If N Code is 10X: 


ee 
[efeneanoene | rear 
[[ercece | rear 












If N Code ts 11X: 


a 
fefenisnswers | reais 











PR211 


fe fareecee | era | ener 
a 
eek 





Note 1. If a condition code of B is not decoded during the |-Q cycle and 
the load 1/O is not a control load 1/0, I-R back up takes place. 


5406 PRINTER ATTACHMENT-— Operations 
Load I/O Instruction Timing Chart 





5406 FETMM 


(2/71) 


9-303 


5406 PRINTER ATTACHMENT- Operations 


Test I/O and Advance Program Level Instruction Flowchart 


TIO/APL 


Instruction 





Ci, D1, or E1 is 
decoded during 
a CPU 1!-Op cycle 
indicating a test 
\/O (F1 for APL). 





1-Op 
Cycle 


1. Sample OQ code 
i for device address. 


. Determine and 
notify CPU of 
condition code. 





1-O 
Cycle 








Test 1/O Instruction 


Op Code O Code Branch to Address 


Branch to Address 





0 } 70 345 70 


* M bit is O unless 
the LCD device is 
installed and 
the test |/O is for 
the LCD. 


** = Bits tested for by the 
attachment. 


PRO11 ~ . PR211 
‘Ch TIO instr’ is 






Activates ‘SP TIO 
or APL’ in the 
attachment. 






activated in the —— 
attachment. 






PR211 


Activate ‘SP |-O 


instruction’. 





PR 213 


If DA is E (1110), 
activate ‘SP DBOR 
012 not 3’. 











PR216 








{if M bit is O, set 
‘select SP’ latch. 


If M bit is 1, set 
‘select LCD’ latch. 


At ‘SP clock 5’ 
set the ‘select SP’ a ume ee 
latch. 


15 





Check for condition 
as specified in the N 
code, and send 


condition (A or B) 
back to CPU. 





End of 


Operation 





5406 FETMM = (6/70) 9-304 


APL Instruction 
Op Code OQ Code 


Not Used 


© 


70 3.45 70 


* M bit is O unless 
the LCD device is 
installed and the 
APL is for the LCD. 


** = Bits tested for by the 
attachment. 


~ 







These are the condi- 

Yes tions that can be 

tested for by the 
test |/O and APL 
instructions. They 
will activate: 

— "Chan 1 10 condi- 
tion A’ and/or 
‘Chan 1 10 condi- 
tion B’. 

1. Condition A for 


XX1 
(end of forms) 


No 
correct DA and 
conditions tested 
N code Yes for met. 
WAN S. 0 eee en ie 


an Um 


. Condition B for 
(busy) correct DA and 
conditions tested 
for not met. 
3. Condition A and 
N code 1XX B for wrong parity. 


(element at 4. Not condition A 
left margin) and B for wrong DA. 


NO 


1. If it was a test |/O instruction: 
When the condition tested for is met, the instruction branches 
to the CPU |- cycles as determined by the Op code: 
1-X1 or, 
I-H1 and I-L1. 


2. If it was an APL instruction: 
When the condition tested for is met, an I-R cycle is 
taken (nothing is done during this cycle). 





X = Bit not checked, can be 1 or O. 


a 1/O 
TIO-APL !-Q Byte Condition Condition B 
Incorrect DBO Parity 
Device address not recognized or N 
field Invalid 


Device 
address TIO Condition Not Met 
recognized ae 
7 po foe 














Correct 
DBO 
Parity 






















and 
N field 
valid. 





Condition Met © 


ced Pte “apiece oe 
Ree e % see & 
% a se 










For Test I/O Instruction: 
CPU cycles for addressing 
I-X1 or, 
I-H1 and I-L1 








For APL 


Instruction — IR Cycle 
ern, 


l-Op Cycle 1-O Cycle 


| Line Title, [ALD Page]0123456781012345678 ,07 781012345678 
PR211 i ee a 
ne Ch Condition (A-B) Soa a 

















f 














5406 PRINTER ATTACHMENT- Operations 
Test I/O and Advance Program Level Instruction Timing Chart : | 5406 FETMM (2/71) 9.305 


5406 PRINTER ATTACHMENT-— Operations 5406 FETMM __ (6/70) 9-306 
_ Sense I/O Instruction Flowchart 





3 


Op Code O Code Storage Address N 1st B Cycle (Lo Order Byte) 2nd B Cycle (Hi Order Byte) 


Store Status 1 
FE Diagnostic Aid Status 3 
Store PDAR LO 

Store PCAR LO 

Store LLAR LO 

Store Status 

LCD Signals 









Before taking the B cycle(s): 












Store Status 2 
FE Diagnostic Aid Status 4 
Store PDAR Hi 

Store PCAR Hi 

Store LLAR Hi 

Store Diagnostic Byte 
Printer Device Signals 









Storage Address The CPU will (depending 


upon the Op code) take 
either: an |-X1 cycle or 
an |-H1 cycle and an I-L1 
cycle. 









*M bit is O unless 
the LCD device is 
installed and the 
sense instruction is 
for the LCD. 





---x x xoo/] = 







Take E-B1 cycle. 
Decode M and N 
codes to determine 
what the sense in- 

struction is for, and 
send sense informa- 
tion back to CPU 


X = Bit not checked. 










PR211 
** = Bits tested for by the 


attachment. Activate ‘SP E-B1 


cycle’. 





Activate ‘SP gate 


































on DBI. : 
" PR215 status 2 or 4’. 
E-B1 , 
Cycle : Activate ‘SP gate 
; status 1 or 3’. 
30, 70, or BO PROI1 isp 
decoded by CPU select 7’ 
during an !-Op ‘Ch SNS instr’ is ative 
cycle indicates activated in the ‘SP select Ves 
asense instruction. attachment. 7 
active PR251 
1-Op : 
Cycle : | No pR251 PR251 


Activate ‘SP gate 2’. Activate ‘SP gate 4’. 





, Activate ‘SP gate 1’. Activate ‘SP gate 3’. 
. Sample QO code 


for device 
address. 

2. Raise ‘Ch |-O 
condition B’. 






PR211 






These lines will gate 
the sense information 
(as specified by the 






Activate ‘SP I-O 
instruction’. 





These lines will gate 
the sense information 
(as specified by the 
M and N codes - see 
above) in the DBI 
assembler. 


End of 
If Mbit isO,set Take E-B not 1 cycle. 
‘select SP’ latch. Decode M and N 
If M bit is 1, set codes to determine 
‘select LCD’ latch. what the sense in- 
struction is for, and 
send sense informa- 


tion back to CPU 
on DBI. 


1-0 
Cycle 







M and N codes - see 
above) in the DBI 
assembler. 





If DA is E (1110), 
activate ‘SP DBOR 
012 not 3’. 







a 









Be 
the 






At ‘SP clock 5’ set 
the ‘select SP’ 
latch. 







PR211 


Activate ‘SP E-B 
Activate ‘Ch |1-O 


condition B’. 






not 1 cycle’. 





E-B Not 1 
Cycle 


(2 ) | (3) 


er 9 





Lad 


Bovose 


CPU cycles for addressing: 
I-X1, or I-H1 and I-L1. 


|-Op Cycle 1-O Cycle EB-1 Cycle EB Not 1 Cycle 


| Line Title = fALD Pagel0123456 7801234567801 781012345678/012345678 


Ch SNS Instruction | 


SEER MESS SS ORME ES 









SP I-O Instruction PR211 


Fe a eR eek ge Sa ae eae See Ee ee) 


PR213 | 





SRR ee i CE 
3 Baa RES co ae ck 


SP DBOR 012Not3 


Select SP Latch 





PR214 | 


PX 





ed 
FS 
4 
& 
4 
a 
i 
Ed 


~ 








m3 


5406 PRINTER ATTACHMENT-— Operations 
Sense I/O Instruction Timing Chart | 5406 FETMM (2/71) 9-307 


5406 PRINTER ATTACHMENT-— Operations 


Start I/O Instruction Flowchart 


oe 
#s, 
Ps 





sss 


Op Code OQ Code Control Code 


a a | *& 
1110 0 XXX!IxXxxxXXXO 


(DA) (M) (N) 





1 
0 _ 70 345 70 7 


*M Bit is O unless 
the LCD device 
is installed and the 
start |/0 is for the LCD 


** QO for Serial Print 
1 for Bi-directional! 
print 
x=Bit not checked, can 
be either 1 or O. 












Start 1/O 
Instruction 


F3 is decoded 

















during a CPU 

1-Op cycle indi- : ——— 

cating a start 1/O. ‘Ch slo instr 
is activated 


in the attachment. 
Cycle 





. Sample OQ code 
for device address. 





. Determine PR211 
and notify 
CPU of condition 


code. 










Activate 
‘SP 1-O instruction’. 











Cycle If DA isE 


(1110), activate 
‘SP DBOR 
012 not 3’. 





At ‘SP clock 5’ 
set the 
‘select SP’ latch. 














‘Determine 
condition code 

and activate 

‘Ch 1-0 condition A’ 
and/or ‘Ch 1-0 
condition B’. 





5406 FETMM 












Before taking the I-R cycle 
a condition code of B must 
be decoded during the |-Q 
cycle and sent to the CPU. 

If condition code B is not 
decoded, I-R back up will 
occur; that is |-Op 1-0, and 
I-R cycles will be taken until 
a condition code of B is de- 
coded and sent to the CPU. 















1. Examine control 
code. If Bit 7 

is O, it will be 

a serial print 


operation. If 







Bit 7 isa 1, it 
will be a 
bi-directional PR214 If a 1 is detected 
Operation. : : ' 

p heats in Bit 7, at ‘SP 

2. Request a cycle ‘SP selected ent A cei clock 5C’ the 
steal. SIO I-R cycle’. ‘line prt mode’ 
latch is set. 





PR261 
Activate 
‘SP set 
command 
requ est’. 
PR231 


Set the 
‘Cmd req’ 


jatch at 
‘SP clock 7B’. 


PR231 














This line active 
activates ‘SP chan 
1 cyc steal req 5’ 
to request a cycle 
steal from the CPU. 


At ‘SP clock 6’, 
activate ‘Ch — 
priority request bit 5’. 


End of Operation 
lf M bit is O, 


set ‘select SP’ 





— latch. If M bit 
a as 1/O 1/0 
is 1, set ‘select Start 1/O 1—OQ ee ee eames Condition [Condition A | A|Condition B 
LCD’ latch. 








Device address not recognized or N 
field invalid. 
Device 
address Rejected 
recognized 
and Start 1/O 
| Accwet foo fo 







Correct 
DBO 
Parity 






















N field 
valid. 







and |-O Cycle 
Condition 





(2/71) 


9-308 





me 
mek, 





!-Op Cycle 1-O Cycle I-R Cycle 











: 


Line Title ALD PagejO12345678012345678012345678 


Te [ersioime [enon | 
[a | se o50n ones | ena | rani eee 
[a seeasrine [emer 
NS 
Ts [srsenmasiorncnie [rae |} 
Te | sese cma Ran | aa oa 
fe [corners ewrtoee [emar[ | Ya 














5406 PRINTER ATTACHMENT-— Operations 
Start 1/O Instruction Timing Chart 





5406 FETMM 


(2/71) 


9-309 


5406 PRINTER ATTACHMENT-— Operations 
Stepper Motor Start-Move Right (Part 1 of 2) 


Start 
Stepper Motor 


PR233 


The stepper motor is 


started during the At ‘SP clock 6’ 


A command cycle steal activate ‘SP fire SS 1° 
as follows: and ‘SP set stepper 
go and SS A’. 

1. Fire SS 1. 
2. Set ‘stepper go’ 

latch. PR112 
3. FireSSAt 

a : Activate ‘SP SS 1’. 
develop an 


a SS 1 is fired (35 ms). 
advance pulse 


for the stepper 


eee mere : 
L 


riggers. 


Set the ‘stepper 
go’ latch. 





Activate ‘SP SS A’. 
Active for 2.0 ms. 


At ‘SP clock 3’ 
activate ‘SS 1 scout’ 
and ‘SS A scout’. 


Activate 
‘SP SS A rise’. 


At ‘SP clock 0’, 
activate ‘SS 1 
intk’ and ‘SS A 
inlk’. 















With ‘SP cmmd 
steal’ active. 









An emitter pulse 
in the printer must 
respond prior to 
SS 1 time out. 
Otherwise a 
horizontal cycle 
check will occur. 





Activate ‘SP fire 
SS A’ and ‘SP 
stepper go L’. 


— woe ~ SS A fired. 






3 


Sorcas 


9-311 


End of 
Operation 


tad 









Activate ‘B stepper 
phase B’. 








Receive ‘stepper 
forward emitter’ 
from the printer. 









This procedure of 
turning the stepper 
triggers on and off 
continues as long 
as the motor is 
running. See chart 
On next page for 
trigger sequence. 








This emitter pulse 


5406 FETMM = (2/71) 9-310 


This pulse is taken 
to stepper motor in 
the printer to 
produce further 
movement of the 
rotor. : 








will turn off ‘stepper 
trigger A’ and cause 
further movement 
of the motor. 





5406 PRINTER ATTACHMENT- Operations 
Stepper Motor Start-Move Right (Part 2 of 2) 


Start the motor 
moving by gen- 
erating stepper 

pulses. 


qT 


Turn on ‘stepper 
trigger A’ to 

send first pulse 
to stepper motor. 


. This pulse causes 


the motor to move 
and generate an 
emitter pulse. 


. The emitter pulse 


generates a pulse 
to turn on 
‘stepper trigger 
B’. 


. ‘Stepper trigger 


B’ sends a 
pulse to the 
motor. 


. Another emitter 


pulse is sent 
back to the 
attachment. 


. This procedure 


continues until 
the motor is 
to be stopped. 





Fe ae tee aera et na ee 





wy 


8 9-310 


PR241 


At ‘SP clock 5’ 
activate ‘SP 


stepper adv pulse 





PR241 


Turn on ‘stepper 
trigger A’ and activate 
"SP stepper tr A’. 





PR256 


Activate 
‘B stepper phase 
A’. 





PR131 


Receive 
‘stepper forward 
emitter’ from printer. 





PR245 


Activate 
‘SLT & MST convtO’. 





PR242 


At ‘SP clock 4’ 
set the 
‘step scout’ latch. 





PR242 


At ‘SP clock 3’ and 
‘SP phase B’ set 
‘step adv’ latch. 





PR242 
At ‘SP clockO' set 
the ‘step adv inlk’ 
latch, and activate 
‘SP stepper rise’. 








PR241 


‘SP stepper rise’ 
activates ‘SP 
stepper adv pulse’ 


to turn on 
‘stepper trigger B’. 









With 
‘stepper go’ 
latch set. 











This pulse is taken 
to the stepper 
motor in the 
printer. It causes 
the rotor to move. 












Emitter pulse caused 
by rotor moving 
emitter wheel on shaft. 











Stepper Trigger 
Sequence 


Forward Reverse 
(right) (left) 


ra [wav] 
off off | off 


t Detent (electronic) 


t Detent (electronic) 


5406 FETMM 


(6/70) 


9-311 


Line Title 


7 ape 


Command Steal Latch PR231 


PSS1 PR233| | 


nY 


P Set Stepper Go and SSA PR224 


Stepper Go Latch PR241 


w” 


P SSA PR112 


SS1 Scout PR243 


SSA Scout PR243 


wn 


P SSA Rise PR243 | | 


SS1 Inlk PR243 | 


SSA InIk PR243 | 
11 | SP Stepper Advance Pulse PR241 | 


12} Stepper A Trigger PR241 


1 B Stepper Phase A PR256 | 


3 


Stepper B Trigger PR241 | 








B Stepper Phase B PR256 { 


B Stepper Phase Not A PR256 | 
B Stepper Phase Not B PR256 |_| 


Note 1. Stepper rise is generated by the leading edge of the stepper emitter feedback pulse. 
Stepper fall is generated by the trailing end of the stepper emitter feedback pulse. 





5406 PRINTER ATTACHMENT- Operations 
Stepper Motor Start Timing Chart 


ca 


Clock 6 


ALD Page]7 8] 0 1 23456781012345678, 
Clock 8 


Clock O! 
1k 


Clock 5 | 


Clock 5 
4,11 





Clock O | 
COule 





tad 







ee ee ee ee 
Be ea a tek eee ener 















Clock 5 


12 






TR eet 
pobre ant) 


ie 


Clock 4 Clock 3 








5,14 ,16 . , | 
Clock 3 Clock 3 
15 Bees cog 15, 17 oa ee oe 
Clock O Clock 0 . 
16 Bee a 





3S i oy a ce bd 


Clock 3 to Clock O 1" 


Clock 3 to Clock O “4 
Clock O Clock 3 












16, 17 16 or 17 = Tae as BE = 
Clock 5 
4,11» 
21 





5406 FETMM (6/70) 9-313 


5406 PRINTER ATTACHMENT-— Operations 
Element Return (Part 1 of 3) 







Element Return 


Element return is 
initiated by 
setting the ‘elem 
rtrn’ command 
latch during a 
command cycle 
steal. There are 
two ways an 
element return 
can be initiated: 


PR221 








Set the ‘elem 

~ rtrn’ command 
latch at ‘SP clock 
5C’ of an ‘SP 
cmmd steal’. 











PR221 






Activate 
‘SP horiz cmmd’. 






1. The command 
byte that the PCAR 

is pointing to in stor- 
age, has a 5 bit on, or 









PR221 










Activate 
‘SP horiz left 
cmmd’. 






2. Check reset then 
system reset to 
position the element 
in the left home posi- 
tion prior to starting 
a print operation. 









PR233, PR224 


At ‘SP clock 6’, 
activate 
‘SP fire SS1’ 


The stepper motor 

will run in reverse 
during element return. 
Its movement is initiated 
as follows: 


and ‘SP set 
stepper go and 
SSA’. 





1. Fire SS1. PR112 


2. Set ‘stepper go’ 
latch. 


Activate 
‘SP SS1’. 





. Fire SSA to 
develop an 
advance pulse 
for the stepper 
triggers. 


PR241 
Set the 
‘stepper go’ 
latch. 





PR112 





Activate 


‘SP SSA’. 





a) 9-315 (8 9-315 





ee 









The command 
latch is set as the 
result of either 

‘SP DBOR 5' 
during a command 
steal, or ‘SP reset to 
LHML’ active. 










To gate the 
stepper triggers. 










With ‘SP cmmd 
steal’ active. 







SS1 fired. 







Active 
‘SP fire SSA’ and 
‘SP stepper go L’: 






SSA fired. 


Cj} 9-315 


. Another emitter 


pulse is sent 
back to the 
attachment. 


. This procedure 
continues as 

long as the 
motor is running. 








At ‘SP clock 4’ set 
the ‘step scout’ 
latch. 





PR242 
At ‘SP clock 3’ 
and ‘SP phase B’ 
set the ‘step adv’ 
latch. 





PR242 
At ‘SP clock O’ set the 
‘step adv inlk’ latch, 
and activate 
‘SP stepper rise’. 






PR241 


‘SP stepper rise’ 
activates ‘SP 
stepper adv pulse’ 
to turn on 
‘stepper trigger A’. 





PR256 
Activate 


‘B stepper phase 
A’. 





PR131 


Receive ‘+6V 





stepper return 
emitter’. 





This procedure 
of turning the 
Stepper triggers 
on and off to 
produce motor 
advance pulses 


continues as 
long as the 
motor is run- 
ning. See 

chart on this 
page for trigger 
sequence. 




















At ‘SP clock 0’ set 
the ‘stp adv inlk L’ 
to bring up ‘SP 

allow shift’. 





This pulse is taken 
to the stepper motor 
in the printer 

to produce further 
movement of the 
rotor. 







This emitter pulse 
will turn off ‘stepper 
trigger B’ and 
produce another 
motor advance 
pulse. 





5406 FETMM 


Stepper Trigger 
Sequence 


Reverse 
(left) 





(6/70) 


t Detent 


(electronic) 


Detent 
(electronic) 


9-314 








Ge Ee Te ee ee 
Sees RRA aes SES ix AEs Gee EET eae A ae es ees 


Sepa oTEY 


Start the motor 
moving by generating 
stepper pulses. 


1. Turn on ‘stepper 
trigger B’ to send 
first pulse to 
stepper motor. 


. This pulse causes 
the motor to move 
and generate an 
emitter pulse. 


. This emitter pulse 
generates a pulse 
to turn on 
‘stepper trigger 
A’. 


. ‘Stepper trigger A’ 
sends a pulse 
to the motor. 


pe 


od 


Co: ee 
© 
Ww 
_ 
SS 


5406 PRINTER ATTACHMENT-— Operations 


Element Return (Part 2 of 3) 





At ‘SP clock 3’ 
activate ‘SS1 
scout’ and ‘SSA 
scout’. 


Activate 
‘SP SSA rise’. 


At ‘SP clock 0’ 
activate ‘SS1 
inlk’ and ‘SSA inlk’. 





PR241 


At ‘SP clock 5’ 
activate ‘SP 
stepper adv pulse’. 


PR241 


Turn on ‘stepper 
trigger B’ and activate 
‘SP stepper tr B’. 





PR256 


Activate ‘B 
stepper phase 
B’. 


Receive 

‘stepper reverse 
emitter’ from the 
printer. 


Activate 
‘SLT & MST convt 1’. 











with ‘stepper 
go’ latch set. 






This pulse is 

taken to the 
stepper motor in 
the printer. It 
causes the rotor to 
move. 














Emitter pulse caused 
by rotor moving 
emitter wheel on shaft. 





Shift the stepper 
motor to high 
speed to return 
the element to 
the left home 
position. 


Receive integ- 
rated emitter 
pulse from 
printer. 


Receive 7 print 
emitter pulses 
from printer. 


. At the 7th pulse 
take an extra 
motor advance 
pulse and 
shift to high 
speed. 


. The element 
returns to 
left home at 
high speed 
(20 inches 
per second). 


. See page 9-320 
for stepping 
sequence. 





STS 


eS eee eee 


eee is a ES 








PR131 


Receive ‘print 


right emitter’ from 
the printer. 





PR243 


Activate 
‘SP integ rise’. 





PR242 
At ‘SP clock 4’ 


set the ‘print scout’ 
latch. 





PR242 





At ‘SP clock 3’ 
set the 
‘print adv L’. 






PR233 


At ‘SP clock 5’ 
activate ‘SP advance 
matrix counter’. 





PR262 
Activate 
‘SP matrix 
counter trigger 1’. 





PR262 


The remaining 
six print emitter 
pulses are rec- 
eived and the 
matrix counter 
is advanced to 
activate ‘SP 
matrix count 7’. 





PR244 
At ‘SP clock 1’ 
set the ‘HS’ latch 


and activate ‘SP 
stepper high 
speed L’. 





S) 9-317 









Activate 
‘+6V right integrated 
emitter’ and ‘t+t6V 

print right emitter’. 









The integrator emitter 
checks that all seven 
print emitter pulses 
are received during the 
time that it is active. 





PR242 






This latch 
activates ‘SP 
print emitter rise’. 














The first print 
emitter pulse has 
been counted. 






With ‘SP allow 
shift’ active. 


5406 FETMM (2/71) 


9-315 


[FJ ois 


‘ee 
ie 


End of 


Operation 





5406 PRINTER ATTACHMENT-— Operations 
Element Return (Part 3 of 3) 





(s 9.315 


PR282 


Activate ‘SP stepper 


high speed’. 





PR 281 


Activate ‘SP shift 
allow emit fall’. 





PR242 


Activate ‘SP stepper 
fall’. 





PR241 


At ‘SP clock 5’ 
activate ‘SP stepper 
adv pulse’. 


The extra advance 
pulse causes the 
stepper motor to 
speed up go into 
high speed. 


Refer to page 9-320 
for shifting to low 
speed and stopping. 








~ latch. 







Set ‘hi speed inlk’ 





This line active 
will allow an extra 
advance pulse at 
the fall of ‘SP allow 
shift. 






This line is active 
with the ‘step 
adv L’ reset off. 


This provides an 
extra advance 

pulse to the stepper 
triggers. The extra 
advance pulse occurs 
at the fall of ‘SP 
allow shift’. 


The stepper motor 
is normally run by 
stepper rise pulses. 
During shifting up, 
an extra pulse is 
added by using a 
stepper fall pulse. 
This results in two 
pulses close 
together. 
















5406 FETMM 


(6/70) 


9-317 


Element Return Timing Chart (Part 1 of 2) 


seen 





1 | Command Steal Latch PR231 | ! Clock 7D |q,. 3 PSE e Ones | 
eon | ViCroseconds 
Elem Rtrn Latch PR221 
SP Horiz Cmmd PR221 


SP Horiz Left Cmmd PR221 






5 PSS1 | PR233 


” 


P Set Stepper Go and SSA PR224 


” 


~~ 


= = ass — = 
© ~S Oo NO = Oo 


tepper Go Latch PR241 


PSSA PR112 


> 
” 


S1 Scout PR243 


SA Scout PR243 


—_ 


Clock_3 


SA Rise PR243 


3, 10, 13 gee 
S1 Inlk PR243 | ee 
13 | SSA Inlk PR243 | | | ee Ne a Spock © 
14 | SP Stepper Advance Pulse PrR24i] | ce : Rise (R) at sak tea? R R R R R R Fall R R R R R R R R 







Clock 5 


— 
oO 


Stepper B Trigger PR241 





PR256 





B Stepper Phase B 





Dp 1 Stepper Reverse Emitter PR132 | | | } | Oo = ae — . : . oar | = . a er : —— ea | | oe ae 
Step Scout Latch PR242 | | a a | | | : | ) | a | Tre | 
i eee ne atc pier Se se eae se sa 
20 | Step Adv Inlk Latch PR242 | | | ee ___ Clock o | = | 
21 | SP Allow Shift PR242 | | a oe ao , : } 
22 | Stepper Emitter Rise Note 1 PR242| | | cee 3 to Clock 0) | a 
23 | Stepper Emitter Fall Note 1 | PR242| | | Clock 3 to Clock 0 
24 | Stepper A Trigger PR241 | Clock anon en 
25 | B Stepper Phase A PR256 | | | | 


26 | B Stepper Phase Not B PR256 


27 | B Stepper Phase Not A PR256 


2 


00 


SP Integ Emitter PR243 





5406 FETMM = (2/71) 9-318 


A 


a 


‘e 





Breet i %,. 


ALD Page|78| 012345678 | 012345678 | 
29 | +6V Print Right Emitter PR131 


30 | +6V Print Right Emitter PR131 
1 







3 Print Scout Latch PR242 


Print Adv Latch 


32 PR242 





33 | Print Adv Inlk Latch PR242 


34 | SP Print Emitter Rise PR242 


35 | SP Advance Matrix Counter | PR233 


36 | SP Print Emitter Fall PR242 


37 | SP Matrix Counter TR1 PR262 


sa Clock 7 


38 | SP Matrix Counter TR2 PR262 __ Clock 7 





39 | SP Matrix Counter TR4 PR262 _ vleek 7 


SP Stepper Hi Speed Latch | PR244 | | | DA a AG ce 
41] SP Integ Fall PR243 : | | | | Clock 3 to Clock 0 


Note 1: Stepper rise is generated by the leading edge of the stepper emitter feedback pulse. 
Stepper fall is generated by the trailing edge of the stepper emitter feedback pulse. 








—— 


5406 PRINTER ATTACHMENT- Operations . 
Element Return Timing Chart (Part 2 of 2) | 5406 FETMM) §((2/71) 9-319 


5406 PRINTER ATTACHMENT-— Operations 


Stepper Motor Stopping (Part 1 of 2) 


Stepper Motor 
Stopping 


During an element 

return operation, 

the stepper motor 

shifted into high speed 

to return the element 

to the left home posi- 

tion. Prior to stopping 

the element, it must be 

slowed down to 85 cps or 
A 8.5 inches per second. 


The element 
must be shifted 
into low speed 
and stopped. 


It is shifted 
into low speed 
as follows. 


1. The element 
activates the 
first left hand 
limit switch 
(slow down 
limit switch). 





2. One stepper 
motor rise 
pulse is missed. 


3. One stepper 
motor pulse is 
generated at the 
fall of stepper 
emitter pulse 
(feed back 
pulse). 


4. A second 
stepper motor 
= rise pulse is 
missed. 


5. The stepper 


motor shifts 
to low speed. 


s 9-321 


PRO21 


Traveling at high 
speed toward the 
left hand limit 

the element makes 
the first limit 


switch (limit 
switch 1) to slow 
down the element. 
Activate ‘SP Im 1 
slow’. 





PR244 


At ‘SP clock 1’ 
reset ‘HS latch’. 





PR281 


At ‘SP clock 4’, 
set the ‘DBL 
shift down latch’ 





PR281 


This latch set 
deactivates 
‘SP shift allow emitt rise’ 





PR281 


At ‘SP clock 1’ the 
‘DBL shift intk’ 
. latch is reset. 





PR281 


Activate 
‘SP shift allow 
emitt fall’. 





PR242 


Activate 


‘SP stepper fall’. 





io 9.321 

























Limit switch 1 
is positioned 8 
print positions 
from the extreme 
left hand limit. 







With ‘SP allow 
shift’ active. 


Without this line 

active, the ‘SP stepper 
rise’ line cannot be 
activated to gate the 
stepper A and B triggers. 
Therefore an advance 
pulse is inhibited, and 
the motor will start to 
slow down. 





This line active will 
allow an extra advance 
pulse at the fall of 

‘SP allow shift’. 





This line active 
provides a gate 
to the stepper A and 
B triggers to provide 
an advance pulse to 

the stepper motor. 


Io 





9-321 


9-321 





[o} 9321 


PR121 


Activate ‘SP SSW’. 





PR243 


At ‘SP clock 3’ 
activate ‘SSW & 
Y scout’. 

At ‘SP clock 0’ 
activate ‘SSW or 
Y inlk’. With 
these two lines 
active, at ‘SP 
clock 5’ activate 
‘SP gated SSW 
or Y timeout’. 





PR122 


Activate 
‘SP SSX’. 





PR243 


At ‘SP clock 3’ 
activate ‘SSX 
scout’. At ‘SP 
clock 0’ activate 
‘SSX: inlk’. At 
‘SP clock 5’ 
activate ‘SP 
gated SSX time- 


’ 


out. 





PR121 


Activate 
“SP SSY’. 





PR243 
At ‘SP clock 3’ 
activate ‘SSW & 
Y scout’. At 
‘SP clock 0’ 
activate ‘SSW 


or Y inlk’. With 
these two lines 
active, at ‘SP 
clock 5’ activate 
‘SP gated SSW 
or Y timeout’. 





oS 9-321 












SSW fired 





SSX fired with ‘SP 
SSW inlk L’ active. 
This latch was set 
by SSA when the 
element initially 
started to move. 






‘SSX inlk’ resets 
the ‘SSW inlk 
latch. 


SSY fired. 


5406 FETMM 


(2/71) 


9-320 


A } 9-320 


2 


The element 
traveling at low 
speed comes 
to a stop as 
follows: 





1. The element 
activates the 
second left 
hand limit 
switch (stop 
limit switch). 


. Fire four 
single shots 
(WX Y and 
Z) to slow 
down the 
stepper motor 
by slowing 
down the 
advance pulses. 


Seed 


. No more advance 
pulses are 
generated, 
Therefore the 
motor stops. 


Lc J 9-820 


5406 PRINTER ATTACHMENT- Operations 
Stepper Motor Stopping (Part 2 of 2) 





2 9.320 


A second advance 
pulse to the stepper 


motor is inhibited. 





The stepper motor 
shifts to low speed. 


PR 281 





At ‘SP clock 7’: 
1. Reset the ‘DBL 


shift down’ latch. 


2. Deactivate ‘SP 


shift allow emit 
fall’. 

. Activate ‘SP shift 
allow emit rise’. 





PRO21 


The element 
makes the second 
limit switch to 
initiate the stop 
sequence. 
Activate ‘SP Lm 
sw 2 stop’. 


PR221 


Set the 
‘SP elem at Lm’ 
latch. 





PR223 


At ‘SP clock 5’ | 
set the ‘margin 
halt’ latch. 





PR241 


Set the 


‘stepper stop’ 
latch. 





PR241 


At ‘SP clock 7’ 






activate 
‘SP turn on SS W’. 


0} 9-320 


wy 










‘SP shift allow emit 
rise’ is still inactive. 
Therefore an advance 
pulse that normally 
goes to the stepper 
motor as the result 
of the emitter feed 
back pulse is missed. 








The stepper motor 
will now step {in 
low speed) on the 
rise of the feed 
back emitter pulse. 






With ‘SP horiz 
left cmmd’ 
active. 









At matrix 
count 3. 







With the stepper 
A and B triggers off. 
Reset the ‘stepper 

go’ latch. 











End of 
Operation 




















ey oy 


SS Z fired. 


# 
"eat 


Activate 
‘SP SS 2’. 


PR243 


At ‘SP clock 3’ 
activate ‘SS Z 
scout’. At ‘SP 
clock 0’ activate 
‘SS Z inlk’. With 
these two lines 
active, activate 
‘SP gated SS Z 
timeout’. 


PR241 


At ‘SP clock 5C’ 
reset the 
‘stepper stop’ latch. 










PR233 







With the stepper 
go and stop latches 
reset off. 


Activate 
‘SP fire SS 2’. 


PR122 













SS 2 fired for 
30 ms to aliow for 
mechanical settling 
down of printer. 


Activate 
‘SP SS 2’, 


PR243 


At ‘SP clock 3’ 
activate ‘SS 2 
scout’. At ‘SP 
clock 0’ activate 
‘SS 2 inlk’. With 
these two lines 
active, activate 
‘SP SS 2 timeout’. 


PR261 


The stepper motor 
is not receiving . 
any advance pulses, 
so it comes to 

a stop. 


At ‘Ch clock 7’ 
reset ‘attach busy’. 
If ‘SP cmmd 
chained’ is 


active, the ‘SP 
set cmmd re- 
quest’ line is 
activated. 


5406 FETMM 


(2/71) 


9-321 


5406 PRINTER ATTACHMENT- Operations | 5406 FETMM = (2/71) 9-322 
Stepper Motor Stopping Timing Chart (Part 1 of 2) 7 





Line Title 


Stepper Go Latch PR241 | [ HOEK 


> 
rr 
O 
wo a" 
a 
© 


2 (stepper emitter) -feedback 


eae 


PR242 Clock 4 to Clock 3 | | 


PR242 |Clock 3 to Clock 3 | | 


PR242 |Clock 0 to Clock 0 ee teil 


3 Step Scout Latch 





Stepper Adv Latch 


Stepper Adv Inlik Latch 
Stepper Emitter Rise Note 1] PR242 {Clock 3 to Clock 0 | | 


Stepper Emitter Fall Note 1 


~ 


PR242 |Clock 3 to Clock 0 | 
SP Allow Shift PR242 |4.5 aS ie ee ge A 


SP Stepper Advance Pulse 


PR241 Rise (R) R Fall RRI I R R R R R. R R R R R. W 4 Y Z 


Stepper A Trigger PR241 se | | = 


Stepper B Trigger PR241 | eee | Seen 


12 SP Integ Emitter PR243 a 


13 SP Integ Fall 


PR243 | | 


SP Advance Matrix Counter| PR233 L 


15 SP Matrix Counter Tr1 PR262 [LL 


16 SP Matrix Counter Tr2 PR262 


17 SP Matrix Counter Tr4 PR262 





Clock 1 (| 
wees Shift to slow speed 
Clock 4 Clock 7 
6, 18 geupeeees 6,20 


Pm 
Clock 1 


Stepper High Speed Latch PR244 [| 


DBL Shift Down PR281 


20 DBL Shift Inlk PR281 {Or CCQ {| 

21 Left Margin Sw 1 (Slow) | | 

22 Left Margin Sw 2 (Stop) | 

23 | SP Elemat Lm Latch PR221 | 2 

24 | Margin Halt Latch PR223 re | Se 
25 _| Stepper Stop Latch PRAT | FO 


B 26 SP SSW PR121 


ee 
| | Clock 3 , Clock 0 
| 


27 (SSW time out) 


28 SP SSX PR122 


29 (SSX time out) 


| | Clock 3 , Clock O 
eee 7 characters from the end. 


| 
| 
| 
= 
| 
| 
| 
| 
| 
| 
| 
| 


30 | spssy 


PR121- 








(SSY time out) a II Clock 3 , Clock 0 
te : 
1 | 
oF See cn | | REESE RAS BRU SRN AS CNTs HE 
| | 
(SSZ time out) md [| Clock 3 , Clock 0 
(ss2 time out) a. 1H approximately 7 characters from the end. Clock 3 , Clock 0 


Note 1. Stepper rise is generated by the leading edge of the stepper emitter feedback pulse. 
Stepper fall is generated by the trailing edge of the stepper emitter feedback pulse. 


oy 





v 
Fins 


5406 PRINTER ATTACHMENT- Operations 
Stepper Motor Stopping Timing Chart (Part 2 of 2) 5406 FETMM = (2/71) 9.323 


5406 PRINTER ATTACHMENT-— Operations 
Tab Right (Part 1 of 3) 


TAB RIGHT OPERATION 


The tab right operation moves the print element to the right a number of 
character positions specified by the count byte. On printers with 22 inch 
carriages or bi-directional printing, tabs of more than eight character posi- 
tions begin at high speed. Tabbing at high speed continues until a count of 
eight is detected in the count byte. At this time the print element is shifted 
down into low speed to complete the operation. 


Printers with 13 inch carriages without bi-directional printing always tab 


right at low speed. 


During a command cycle steal the ‘tab right’ latch is set. 
SS1 is fired to check for a horizontal cycle check. 

SSA is fired to start the stepper motor. 

A count cycle steal is requested. 

A count cycle steal is granted and the PCAR is selected. 


The PCAR addresses the count byte and it is modified —1 in the ALU 
and placed back in main storage. 


The stepper motor moves the print element one character position 


Count cycles are taken until the count byte equals FF and ‘SP count 
end’ is raised in the attachment. 


Tab Right 


Operation 





. Decode tab oper- 


ation and set 
command latch. 


. Fire SS 1 to 


check for hori- 


zontal movement. 


. Fire SS A to 


provide an ad- 
vance pulse to 
the stepper 
triggers and 
start the stepper 
motor. 


eS 9.325 


PR222 


At ‘SP clock 5C’ 
set the ‘tab right’ 


command latch. 





PR221 


Activate ‘SP horiz 
tab cmmd’, ‘SP 
horiz right cmmd’ 
and ‘SP horiz 
cmmd’. 





PR224 


At ‘SP clock 6’ set 
the ‘horiz cy inlk’ 


latch and ‘SP fire 


SS 1’. 


PR112 


Fire SS 1. Active 
for 35 ms. 

Fire SS A. 

2.0 ms. 


PR112 — 


Activate ‘SP SS A’. 





PR241 


Set the ‘stepper go’ 
latch. 





PR241 


Turn on ‘stepper 


A’ trigger. 





















With ‘SP DBO reg 2’ 
active during a 

command cycle 
steal. 










With ‘SP cmmd 
steal’ active. 


An emitter pulse from 
the printer must 

respond in the printer 
prior to SS 1 time out. 
Otherwise a horizontal 
cycle check will occur. 





With ‘SP SS A rise’ 
active, provide an 
advance pulse for 
stepper trigger A. 






To generate a pulse 
to start the stepper 
motor. 












5406 FETMM 


(2/71) 


9-324 


a, 9-325 
a 
eee: 
a 
4 








1. Take count 


cycle steal. 











2. Select PCAR 
to address 
the count byte. 





. Update the 
count date by 
decrementing it 
-1 each cycle steal. 


. Inhibit the PCAR 
from advancing 
to the next 
command until 


the count byte 
is decremented 
to FF. 


. If more than 
8 positions are 
to be spaced, 
- shift the stepper 
motor into 
high speed. 


By 
oa q 
og 











c, 9-327 







Set the 
‘count req’ 
latch. 






PR231 
At ‘SP clock 6’ 
activate ‘ch 

priority request 
bit 5’. 















When cycle steal is 
granted, at ‘SP clock 
8’ activate ‘SP cycle 
steal honored’ and set 
the ‘count steal’ 
latch. 














Activate 
‘SP format steal’. 







Activate ‘SP LSR 
select 4 and 6’. 






PR232 


‘Activate 


‘ch store data’. 





PR232 


At ‘SP clock 1’ 
activate ‘SP force 
DBI bit 7’. 


At ‘SP clock 2’ 
activate 
‘SP count busy’. 





5406 PRINTER ATTACHMENT-— Operations 


Tab Right (Part 2 of 3) 


















To request a 
count cycle 
steal. 











The request bit 
is sent to the CPU. 










At ‘SP phase C’ 
the ‘count req’ 
latch is reset. 










Select the PCAR in the 
CPU to address the 
count byte. 






The 7 bit decodes as — 
a binary 1, to be 
subtracted from 
the count byte to 
decrement it by -1. 








4. Move the 


5. 


print element 
to the right 
one character 
position for 
each count 
(one count 
cycle steal 
per count) 
specified by 
the count 
byte. 


When (if) the 
count is less 
than 8, shift 
to low speed. 


. The stepper 


motor comes 
to a stop. See 
page 9-316. 





End of 


Operation 














PR232 


At ‘SP clock 3' 
activate ‘ch 





This line active 
causes the 7 bit to 
be subtracted from 
the count byte. 







binary subtract’. 


Count No 
byte = FF oa 


Yes pR234 


At ‘SP clock 5C’ RS 9-327 
activate ‘SP count 


end’. 





PR232 


Do not activate 
‘ch inhibit LSR 
load’. 






The PCAR will 

increment to the 

next sequential 

command. 
PR231 

Reset the 

‘count req’ 

latch. 


Start stepper 
motor stop 
sequence. See 
page 9-320. 


5406 FETMM 


(6/70) 


9-325 


8 9-325 







5213 Model 3 
or 2222 Printer 











More than 8 


to be spaced. 


DBO reg >8 


Yes 


PR244 


At ‘SP clock 5C’ 
set the’prog Foor ey 
shift up’ latch. 





At ‘SP clock 6’ 
activate ‘ch 
inhibit LSR 
load.’ 





PR244_ 


At ‘SP clock 1’ 

during ‘SP allow ee 
shift’ set the ‘HS 

latch’. 





The stepper motor 
. moves the element 


one character posi- 
tion at high speed. 





Ss 9-325 


5406 PRINTER ATTACHMENT- Operations 
Tab Right (Part 3 of 3) 






















character positions 












Set only once for 
each horizontal tab 
command. 


This will prevent 
the PCAR from 
advancing to the 
next command. 
The PCAR must not 
be advanced until 
the count byte 

is FF. 








Set only once for 
each horizontal tab 
command. At ‘SP 
matrix count 7’, an 
advance pulse to 

the stepper motor 

is given at the fall 

of the stepper emitter. 







The stepper motor 
receives 12 advance 
pulses to move 
the element one 
character position. 


Ph 











PR244 


At ‘SP clock 5C’ of 
the count cycle 
steal, set the 

‘prog shift down’ 
latch. 





PR232 


At ‘SP clock 6’ 
activate ‘ch 
inhibit LSR load’. 





PR244 


At ‘SP clock 1° 
reset the 
‘HS latch’. 


The stepper motor 
moves the element 
one character posi- 
tion at low speed. 


GB 9-325 


It would have been 
set if more than 8 
character positions 
were detected to be 
skipped on a previous 
count cycle steal. 







The last 8 character 
positions will be 
spaced at low speed. 












This will prevent 
the PCAR from 

advancing to the 
next command. The 
PCAR must not 

advance until the 
count byte is FF. 






The stepper motor 
receives 12 advance 
pulses to move the 
element one 
character position. 


5406 FETMM 


5406 PRINTER ATTACHMENT~— Operations 
Tab Left (Part 1 of 3) 


TAB LEFT OPE RATION 


The tab left operation moves the print element to the left a number of 
character positions specified by the count byte. Tabs of more than 
eight character positions begin at high speed and continue until a 
count of eight is detected in the count byte. At this time the print 
element is shifted down into low speed to complete the operation. 


@ During a command cycle steal the ‘tab left’ latch is set. 
e SS1 is fired to check for a horizontal cycle check. 
e SSA is fired to start the stepper motor. 


e Acount cycle steal is requested. 


A 
e Account cycle steal is granted and the PCAR is selected. 
@ The PCAR addresses the count byte and it is modified —1 in the ALU 
and placed back in main storage. 
e The stepper motor moves the print element one print position. 
e Count cycle steals are taken until the count byte equals FF and 
‘SP count end’ is raised in the attachment. 
pe 


; 





Tab Left 
Operation 


. Decode tab oper- 


ation and set 
command latch. 


. Fire SS 1 to 


check for 
horizontal move- 


ment of print 
element. 


. Fire SS A to 


provide an ad- 
vance pulse to 
the stepper 
triggers and 
start the stepper 
motor. 





es 9-329 


PR222 


At ‘SP clock 5C’ set 
the ‘tab left’ command 


latch. 





PR221 


Activate ‘SP horiz 
tab cmmd’, ‘SP 
horiz left cmmd’, 
‘SP horiz cmmd’, 
and ‘SP horiz left 
count cmmd’. 





PR224 


At ‘SP clock 6’ set 
the ‘horiz cyc inlk’ 
latch and ‘SP fire 
SS 1’. 





PR112 
Fire SS 1. Active for 
35 ms. 
Fire SS A. 


PR112 


Activate ‘SP SS A’. 





PR241 


Set the ‘stepper go’ 
latch. 





PR241 


Turn on ‘stepper B’ 


trigger. 












With ‘SP DBOR 3’ 
active during a 
command cycle steal. 










With ‘SP cmmd 
Steal’ active. 









An emitter pulse from 
the printer must 
respond prior to SS 1 
time out. Otherwise 

a horizontal cycle 
check will occur. 







With ‘SP SS A rise’ 
active, provide an 
advance pulse for 
stepper trigger B. 








To generate a pulse 
to start the stepper 
motor. 






5406 FETMM 


(2/71) 


9-328 


A) 9-328 S 9-331 






1. Take count 


cycle steal. 













Set the 
‘count req’ 
latch. 










2. Select PCAR 
to address the 


count byte. 









To request a 
count cycle 
steal. 






NO 


. Move the 


print element 
to the right 












At ‘SP clock 3’ 
activate ‘ch 
binary subtract’. 


This line active 
causes the 7 bit to 
be subtracted from 
the count byte. 
















one character 
position for 
each count 
(one count 
cycle steal 
PR231 per count) 
specified by 
the count byte. 





At ‘SP clock 6’ 
activate ‘ch priority 
request bit 5’. 






The request bit 
is sent to the 
CPU. 











At ‘SP clock 5C’ . 9-331 
activate ‘SP count 


end’, 











When cycle steal 
is granted, at 
‘SP clock 8’ 
activate ‘SP cycle 
steal honored’ 

and set the ‘count 
steal’ latch. 





At ‘SP phase C’ 
the ‘count req’ 
latch is reset. 






PR232 






. When (if) the 
count is less 
than 8, shift 
to low speed. 






Do not activate 


The PCAR will 
increment to the 
next sequential 

command. 






‘ch inhibit LSR 
load’. 










PR231 


. The stepper 
motor comes 
to a stop. See 
page 9-316. 





Activate 
‘SP format steal’. 


Reset the 
‘count req’ 
latch. 










Activate ‘SP LSR Select the PCAR 









select 4 and 6’. in the CPU to Start stepper 
; address the count motor stop 
byte. sequence. 


See page 9-320. 





1. Update the 
count byte by 
decrementing it 
-1 each cycle steal. 


PR232 


Activate 


‘ch store data’. 






. Inhibit the PCAR 
from advancing 
to the next 
command until 

- the count byte 
B is decremented 
to FF. 





The 7 bit decodes as 
a binary 1, to be 
subtracted from 
the count byte to 
decrement it by -1. 







PR232 


At ‘SP clock 1’ 
activate ‘SP force 
DBI bit 7’. 





. If more than At ‘SP clock 2’ 


activate 
‘SP count busy’. 


8 positions are 
to be spaced, 
shift the stepper 
motor into 

high speed. 


5406 PRINTER ATTACHMENT-— Operations 
Tab Left (Part 2 of 3) : 5406 FETMM — (6/70) 9-329 





End of 
Operation 








, % 


More than 8 
character positions 
to be spaced. 











It would have been 
set if more than 8 
character positions. 
were detected to be 
skipped on a previous 
count cycle steal. 





No : 
DBO r eg ? 8 , sea 3 | A 7 NO IRE RR EET A TCO 








Yes No 


PR244 







At ‘SP clock 5C’ 
set the ‘prog _—— 
shift up’ latch. 


Set only once for 
each horizontal tab 
command. 






At ‘SP clock 5C’ of 
the count cycle 
steal, set the 
‘prog shift down’ 
latch. 









The last 8 character 
positions will be 
spaced at low speed. 









This will prevent 
the PCAR from 
advancing to the 
next command. 
The PCAR must not 
be advanced until 
the count byte 

is FF. 














PR232 


Seige 
se 


At ‘SP clock 6’ 
activate ‘ch 
inhibit LSR 
load’. 








This will prevent 
the PCAR from 

advancing to the 
next command. The 
PCAR must not 

advance until the 
count byte is FF. 














At ‘SP clock 6’ 
activate ‘ch 
inhibit LSR load’. 











PR244 









Set only once for 
each horizontal tab 
command. At ‘SP 
matrix count 7’, an 
advance pulse to 

the stepper motor 

is given at the fall 

of the stepper emitter. 


At ‘SP clock 1’ 
during ‘SP allow 
shift’ set the ‘HS 
latch’. 


At ‘SP clock 1’ 
reset the 
‘HS latch’. 















The stepper motor 
receives 12 advance 
pulses to move the 
element one 
character position. 


The stepper motor The stepper motor 
moves the element 


receives 12 advance | h a ‘catia 
plillses tOvmiove One character position 


the element one at low speed. 
character position. 


co 9-329 G 9.329 
5406 PRINTER ATTACHMENT-— Operations | 
Epa oe 5406 FETMM (2/71) 9-331 


The stepper motor 
moves the element 







One character pos- 
ition at high speed. 





5406 PRINTER ATTACHMENT-— Operations 
Primary Skip (Part 1 of 2) 


PRIMARY SKIP OPERATION 


A skip operation can take place only on a primary carriage. Any number of 
lines from 2 to 256 may be skipped. The number of lines to be skipped is 
contained in the count byte in main storage (addressed by the PCAR). 

One count cycle steal must be taken for each line to be skipped. Count 
cycle steals are taken until the count byte is FF. 


Primary Skip 
Operation 


e During acommand cycle steal the ‘prim skip’ latch is set. 


@ SS1 is fired to check for a vertical cycle check. 


The skip operation 
proceeds as follows: 


e Acount cycle steal is requested. 


e Thecount cycle steal is granted and the PCAR is selected. , 
1. A skip command 


is decoded. 


e The PCAR addresses the count byte and it is modified —1 in the ALU 


. in 
and placed back in main storage _ SS 1 is fired to 


check for car- 


@ The attachment generates a pulse to pick the forms magnet in the 
riage movement. 


printer. 


. Account cycle 
steal is taken. 


@ The printer advances the forms one print line. 


@ The motion emitter in the printer sends a response to the attachment 
to reset attachment vertical cycle check circuitry. 


. The PCAR is 
selected to ad- 
dress the count 

e@ Count cycle steals are taken until the count byte equals FF and byte. 


‘SP count end’ is raised in the attachment. 


a 9-333 








At ‘SP clock 5C’ set 
the ‘prim skip’ 
command latch. 


At ‘SP clock 6’ set 
the ‘vert cyc inlk’ 

latch and ‘SP fire 

SS 1’. 





PR112 


Fire SS 1. Active 
for 35 ms. 





PR231 


Set the ‘count req’ 
latch. 





PR231 


At ‘SP clock 6’ ac- 
tivate ‘Ch priority 
request bit 5’. 





PR231 


When cycle steal is 
granted, at ‘SP 
clock 8’ activate 
‘SP cycle steal 
honored’ and set 
the ‘count steal’ 
latch. 


PR231 


~ Activate ‘SP format 


Steal’. 





PR232 


Activate ‘SP LSR 


select 4 and 6’. 





With ‘SP DBOR 4’ 
active during a 
command cycle 
steal. 


With ‘SP cmmd 
— steal’ active. 


A motion emitter in 
the printer must respond 
prior to SS 71 time out. 
Otherwise a vertical 

cycle check will occur. 




















To request a count 
cycle steal. 


The request bit is 
sent to the CPU. 






At ‘SP phase C’ the 
‘count req’ latch is 
reset. 









Select the PCAR in 
the CPU to address 
the count byte. 






5406 FETMM 


(6/70) 


(a) ecas 


9-332 


a 9.332 


. Update the count 
byte by modifying 
it -1. . 


. Inhibit the 
PCAR from 
advancing to 
the next com- 
mand until the 


count byte is 
-FF. 


. Initiate car- 
riage movement. 


. Check for car- 
riage movement. 





End of 
Operation 





5406 PRINTER ATTACHMENT—Operations 


Primary Skip (Part 2 of 2) 








PR232 


Activate 


‘ch store data’. 





PR232 


At ‘SP clock 1’ 
activate ‘SP force 
DBI bit 7’. 





PR234 


At ‘SP clock 2’ 
activate 
‘SP count busy’. 





PR232 


At ‘SP clock 3’ 
activate ‘ch 
binary subtract’. 





Yes PR234 


At ‘SP clock 5C’ 
activate 
‘SP count end’. 





PR232 


Do not activate 
‘ch inhibit LSR 
load’. 





PR231 
Reset the 


‘count req’ 
latch. 










s 
. 


se 


“gn 
& 


% 








The 7 bit decodes 
as a binary 1, and 
will be subtracted from 
the count byte 
to decrement it 
-1. 






LSR UPDATE 








This will cause 
the 7 bit to be 
subtracted from the 
count byte. 





The PCAR will 
increment 

to the next se- 
quential command. 






PR232 


At ‘SP clock 6’ 


activate ‘ch 
inhibit LSR load’. 





pe) 9.332 








This will prevent 
the PCAR from ad- 
vancing to the next 
command. The 
PCAR must not 
advance until 

the count byte 

is FF. 
























CARRIAGE MOTION 


PR222 


Activate 






‘SP prim vert 
magnet pick’. 








This line goes to the 
printer to pick the 
forms magnet 
which advances 

the forms to the 
next print line. 


PR256 


Activate 
‘B prim forms 
mag’. 






PRO21 


Receiver ‘+ 6V, 
prim vert emitter’ 
from printer. 





Activated only 
once per skip 
operation to 
indicate that 
the carriage 
has moved. 








PR261 
Activate 
‘SP vert rise 
pulse’. 








PR224 








Since carriage 
motion took place, 
we do not have a 
vertical cycle check. 


Reset the 


‘vert cy inik’ latch. 





5406 FETMM 


(6/70) 


9-333 


5406 PRINTER ATTACHMENT- Operations 
Primary Index 


Primary Index 
Operation 


The primary index 
operation ad- 
vances the forms 
in the primary 
carriage to the 
next row of 

print as follows: 


1. Set the ‘prim 
index’ latch. 


. Fire SS 1. 


. Generate a 
pulse to pick 
the motion 
magnet in the 
printer. 


. The magnet picks, 
and advances 
the forms to 
the next row 
to be printed. 


oe 
ee 
y 


. A response 
pulse from 
the motion 
contact resets 
the attachment 
Circuitry. 


bond 





















At ‘SP clock 5C’ 
set the ‘prim Saeed 
index’ latch. 


PR222 
This latch set 
activates ‘SP prim 
vert magnet pick’, | 
‘SP vert cmmd’‘ and 
‘SP vert non count 
cmmd busy’. 





PR233 


At ‘SP clock 6’ 
activate ‘SP —_— — 
fire SS 1’. 






Printer have 
pin feed 
platen 













Fire SS 1 for 35 ms. 
Activate ‘SP SS 1’. 


PR224 


At ‘SP clock 6’ 

(still during ‘SP cmmd 
steal’) ‘SP vert 

cmmd' sets the 

‘vert cy inlk’ 

latch. 






PR256 
* “SP prim vert 
magnet pick’ 
activates ‘B prim 
forms mag’. 


PRO21 


Receive ‘SP prim 
carr motion cont _——- 
N-O' from printer. 


With ‘SP DBOR 7’ 
active during a 
command cycle steal. 


















With ‘SP cmmd 
steal’ active. 







PR123 


Fire ‘SS 1 overlap’. 
Active for 120 ms. 









A motion contact in 
the printer must 
respond prior to 

SS 1 time out. Other- 
wise a vertical 
cycle check will 
occur. Pin feed 
platens require a 
longer response 
time, therefore the 
120 ms is OR’ed to 
the 35 ms of SS 1. 














This line goes to 
the printer to pick 
the forms magnet. 






If carriage 
motion took place. 






PRO21 


‘SP prim motion’ 


cont’ was activated 
by the motion contact. 





PR224 


Reset the ‘vert 
cy inlk’ latch. 





PR222 


Reset ‘prim 


index’ latch. 





End of 
Operation 


Command Cycle Steal 
SS 1 


SS 1 Overlap 


5406 FETMM 








Since carriage 
motion took place, 
we do not have a 
vertical cycle check. 

















(6/70) 9-334 


eer 


Secondary Index 
Operation 


The secondary 
index operation 
advances the 
forms in the 
secondary carriage 
to the next row of 


A, print as follows: 


1. Set the ‘sec 
index’ command 
latch. 


. Fire SS 1. 


. Generate a 
pulse to pick 
the motion magnet 
in the printer. 


. The magnet picks, 
and advances 
the forms to 
the next row 
to be printed. 


. A response 
pulse from 
the motion 
contact resets 
the attachment 
circuitry. 





5406 PRINTER ATTACHMENT-— Operations 
Secondary Index 


PR222 


At ‘SP clock 5C’ 
set the ‘sec index’ 
latch. 


PR222 


This latch set 
activates ‘SP sec 
index cmmd’, ‘SP 


vert cmmd’, and 
‘SP vert non count 
cmmd busy’. 





PR233 


At ‘SP clock 6’ 
activate ‘SP 
fire SS 1’. 





PR112 


Fire SS 1. Active 
for 35 ms. 
Activate ‘SP SS 1’. 





PR224 


At ‘SP clock 6’ 

(still during ‘SP cmmd 
cycle steal’), ‘SP 

vert cmmd’ sets 

the ‘vert cy inlk’ 
latch. 





‘SP sec index cmmd’ 
activates ‘SLT 
2nd forms magnet’. 





PRO21 


Receive ‘SP sec 
carr motion cont 
N-O’ from the 
printer and 
activate ‘SP sec 
carr motion cont’. 





PR224 
Reset the 


‘vert cy inlk’ 
latch. 








Bones 






With ‘SP DBOR 6’ 
active during a 
command cycle steal. 









With ‘SP cmmd 
Steal’ active. 







A motion contact 

in the printer must 
respond prior to 

SS 1 time out. Other- 
wise a vertical cycle 
check will occur. 













This line goes to 
the printer to pick 
the forms magnet. 










If carriage 
motion took 
place. 








Since carriage 
motion took place 

- we do not have a 
vertical cycle check. 


9 “ 


oF fed 








Reset ‘sec 
index’ latch. 









End of 
Operation 


5406 FETMM = (6/70) 


9-335 


5406 PRINTER ATTACHMENT-— Operations 


Print Operation (Part 1 of 3) 


Print 
Operation 


Take two load 
1/O's to preload 
the printer 
LSRs. 

Page 9-302 
















Take a start 
I/O to request 
a cycle steal. 

Page 9-308 









Select the 
PCAR to get a 
command. 












Set the 
command latches 
. in the attach- 
* ment. 


Assume the 
command byte 


is CO fora 
chained print, 
and the count 
byte is 00 to 
print one char- 
acter. 


S 9-337 
















One load |/O loads the 
address of the first 
character to be 

printed into PDAR. 
The second load 1/O 
loads the address 

of the first 

command into 

PCAR. 


s 


PR212 





‘Ch data bus out 
5’ active, and 
‘ch data bus out P’ 
inactive grants 

a cycle steal 
to the printer. 






Activate ‘SP 
decode priority 
assignment’. 





PR231 
Set the 


‘cmmd steal’ 
latch. 


At ‘SP clock 8 
or 4’ activate 
"LSR select 4 and 6’. 


PR221 


At ‘SP clock 5C’ 
activate ‘SP set 


cmmd latches’. 





PR221 


Set the ‘prt right’ 
latch with 


‘SP DBOR 1’. 


LB, 9-337 











PR231 











| At ‘SP clock 8’ this 
line active, activates 
‘SP cycle steal honored’. 






This latch set 

activates 

‘SP format steal’ 
and » 

‘SP cmmd steal’. 





This line activates 
the select lines 
"ch LSR select 4’ 
and ‘ch LSR select 6’ 
to select the PCAR 
in the CPU to get 
the command 

byte. 










This latch activates 
‘SP prt right cmmd’ 
and ‘SP count cmmd’. 


co) 9-337 


5. Store the new 
count byte in 
main storage 
(the count 
byte is FF). 


. Load a new 
address into 
the PCAR. If 
the count byte 
had not been 
FF, loading of 
a new address 
would have 
been inhibited. 
Count cycle 
Steals would 
have been 
taken until 
the count 
was FF. 


. ‘Count stop’ 
is activated 
and no more 
count cycle 
steals are 
requested. 


E 9-337 








At ‘SP clock 8 or 
4' activate ‘LSR 
select 4 and 6’. 










The PCAR in the 
CPU is selected and 
the count byte is 
put in the B register. 


PR232 


At ‘SP clock 1’ 
activate ‘SP 
force DBI bit 7’. 








PR232 


At ‘SP clock 3’ 
activate ‘ch 
binary subtract’. 





PRO11 


‘Ch ALU carry’ is 
activated in the 
attachment. 





PR234 


At ‘SP clock 5C’ 
set the ‘count 
stop’ and ‘cnt 


end status’ 
latches to 

activate ‘SP 
count end’. 




















5406 FETMM (2/71) 


This line activates 
the select lines 

‘ch LSR select 4’ 
and ‘ch LSR select 
6’ to select the 
PCAR in the CPU 
to get the count 
byte. 





This line active 
places a 17 in the 
A register in the 
CPU. 






Subtract the A register 
from the B register to 
reduce the count byte 
by 1 ( from 00 to FF). 







Because the 
count byte has 

been reduced to 
EP. 








No more count cycle 
steals are requested. 
The PCAR is allowed 
to advance to the 
next sequential 
command. 





LB, 9-336 


Start stepper 
motor as ina 
tab right 


operation. 
Page 9-324 


PR221 


gga % 


The stepper motor 
moves the print 
element during 
printing as it does 
during a tab right 
operation (slow 
speed only). SS1 
is fired to check 
for a horizontal 
cycle check and 
the stepper motor 
is stopped by 
firing SSW, SSX, 
SSY, and SSZ. 





Take a data cycle 
steal to bring 

a data character 
from main storage 
to the attachment 
for printing. 


1. Request a data 
cycle steal. 


. Address the 
PDAR and 
bring a data 
character 











PR231 
Set the ‘data 







Set by 


req’ latch at a3 ‘SP print cmmd’. 


‘SP clock 7B’. 


PR231 


At ‘SP clock 6’ 
activate ‘ch 
priority request 
bit 5’. 









This line active, activates 
‘SP chan 1 cyc steal 

req 5’ to request 

a cycle steal from 


PR212 the CPU. 






Set the ‘cmmd 
chained’ latch — 
with ‘SP DBOR 0’. 


over to the 


Eos ‘Ch data bus out 5’ 
print data 


active, and ‘ch data 






Activates 
‘SP cmmd chained’, 





Take count 

cycle steal to 
decrement the 
count byte in 
main storage by 1. 


1. Request count 
cycle steal. 


. Address the 
PCAR and 
place the 
count byte 
in the B reg- 
ister (in the 
CPU). 


. Forcea 7 bit 
in the attach- 
ment and 
place it in the 
A register 
(in the CPU). 


. Subtract the 
A register 
from the B 
register to 
reduce the 
count byte 
by 1. 


c) 9-336 


5406 PRINTER ATTACHMENT- Operations 
Print Operation (Part 2 of 3) 








PR231 


Set the ‘count 
req’ latch at 
‘SP clock 7B’. 






PR231 
At ‘SP clock 6’ 
activate ‘ch 


priority request 
bit 5’. 





PR212 


‘Ch data bus 
out 5’ active 
and ‘ch data 
bus out P’ in- 
active grants a 
cycle steal. 





PR212 


Activate ‘SP 


decode priority 
assignment’. 





PR231 
Set the 


‘count steal’ 
latch. 





D} 9-336 








Set by ‘SP cmmd 
steal’ and 
‘SP count cmmd’. 









PRO12 





This line active, 
activates ‘SP 
chan 1 cyc steal 
req 5’ to request 
a cycle steal 
from the CPU. 










At ‘SP clock 8’ 
this line active 
will activate 
‘SP cycle steal 
honored’. 










When set, this latch 
activates ‘SP 
format steal’. 










register in the 
attachment. 


. Forcea 7 bit on 
DBI to modify 
the PDAR in 
the CPU. 





LF) 9.339 














bus out P’ inactive 
grants a cycle 
steal to the 
printer. 


PR231 







PR212 





At ‘SP clock 8’, 
this line active will 
activate ‘SP cycle 

steal honored’. 


Activate ‘SP 
decode priority —. 
assignment’. 


PR231 


Set the 
‘data steal’ 
latch. 









This line activates 
the select lines 
‘ch LSR select 5’ and 
‘ch LSR select 6’ to 
select the PDAR in 
the CPU to get the 
data character. 





At ‘SP clock 8 or 
4’ activate ‘LSR — 
select 5 and 6’. 






At ‘SP clock 3’ 


activate ‘SP This line will modify 


the PDAR address 
to the next 
character to be 
printed. 








force DBI bit 7’. 


At ‘SP clock 5C’ 
set the char- 


acter to be 
printed into 
the PDAR. 


5406 FETMM 


(2/71) 


9-337 


ww 
eS) 
~N 


rf 
Es 


Print the 
character that 
is in the print 
data register. 


1. Decode the 
character in 
the print data 
register to a 
printable char- 

A acter in the 

ROS module. 


. Convert the 
ROS module 
output to MST 
and set the 
character 
into the ROS 
matrix register. 


. Move the ROS 
character to 
the B print 
hammer 
register. 





. Print the 
character 
by firing 
SS3 seven 
times (once 
for each 
print emitter). 


A print opera- 
tion of printing 
One character 
is complete. 


A second start 
1/O can now be 
taken by the 
printer to do 
another 
operation. 





End of 
Operation 





5406 PRINTER ATTACHMENT-— Operations 
Print Operation (Part 3 of 3) 


PR151 


Decode the 
print data register 


character in the 
ROS module. 





PR271 


Set the ROS 
character in 

the ROS matrix 
register. 





PR255 


Set the ROS 
character in 

the B print 
hammer register. 


At ‘SP SS3’ 
activate ‘SP 


print driver 
gate’ and fire 
the hammers. 












The ROS character 
is now in MST 
logic level. 











The ROS 
character is 
checked for 
parity. 








The hammers 

are fired seven 
times per character 
to complete the 

7 X 7 matrix that 
forms the char- 
acter. Any hammer 
can be fired four 
times (maximum) 
per character. 

SS3 is fired 

seven times. 

See Page 9-209. 





5406 FETMM 


(6/70) 


9-339 


5406 PRINTER ATTACHMENT- Operations 
Print Operation Timing Chart (Part 1 of 2) 


1 


Ch SIO Instr PR211 
Ch |—Q Cycle PR211 


bd Ch !I—O Condition B PR216 


A 


Ch I—R Cycle PR211 


(DBO) 


SP Select SP PR214 


pea ae 
2 [seacaa cor | eer 
Te [comma ean | Prat 
Tener Ramen | rat 


22 
23 


[evatvewy | ero 








2 
1—OP I—O I—R I—O I—O iI—O 
012345678!012345678!012345678!012345678'012345678| 012345678! 012345678! 012345678'012345678! | 
a: a Command , Count Data 
| | Steal | | Steal | | Steal | 
| | | | | | | | 
| | | 
| | | 
1 1’ ' i I I 1 1 
P Q P C P co P P 00 P P * =P 
| | | PPBP | PBBP | 'pBpp | 
| | i =n 
| “il | | [ | | | | 
| | | | | | 
l | Clock 7B | [Clock 8 l | | | | 
ast] 2 
l l ~ | Clock 6 l Clock 6 l l ‘Clock 6 l 
10 18% 28 
lock 7C 
| | | _ mie | | | | 
| ae ls 
| | | ee - a | es ms | 
| | | | | | 
| | | Clock os | | | | | 
| | | | | | | | | 
| | | | Mo |. | | | 
Clock 7B | Clock8 a 
| | | 12, 17 ques | 19 | | | 
Clock 7C 
| | | | | pea | | | 
| | | | T | 
19 | 119 
| | | | Clock 3 | | | 
19 pues 
| | | | | | | | | 
| | | | | fo | | 
Clock 5C 
| | | | | | Eee aalveon 
| | | | | Clock 2 | | | 
| | | | | | Clock 6 | Clock 1 | 


19 24 WA, 


10 ms 


10 ms | 


10 ms 

C — Control Code 

P — Priority Assignment 
Q — Q Byte 

B — DBI Bit 7 


CO — Command Byte 
00 — Count Byte 
* — Character To Print 


5406 FETMM 


20 ms 


(6/70) 


9-340 





i 





see re I-OP I-O IR I-O I-O I-O 
Sees “" 1012345678! | | : | | | | 
[01 2345678] 0123456 78) 012345678) 01 2345678 01 2345678) 01 2345678] 012345678 012345678 10 ms 10 ms 10 ms 20 ms 


| 27. | cnt End Status L PR234 | | | | | Ges Oe a 
Data Req Latch PR231 | | | | | | Clock 7B | | Clock 8 | 
19 peeeeeneees | 29 
29 | Data Steal Latch PR231 | | | | | | | jg t= >. COCK IC 


30 | SP FireSS1 PR233 | | | re sw | | | | ( 
31 | SPSS1 (35 ms) 


32 Stepper Go Latch PR241 | 33 43 
33 | SPSSA PR112 | eee | ‘ —_— = =o aaa a cores 


34 | SP SSA Rise PR243 | — | | | | FNAME ck soca indecent tierce sera aneeaenenl 
(set print data latches) "oct ae a SS genet ee ee 


37 (gated emitter) 





12 










— 
— 

—— 

—— 





SP Stepper TrB | PR241 | | l l l 39 momen 


Stepper Stop Latch | 


| | | a aa "Glock 5C 
PR241 | | | (Matrix Count Three) eats fa ee ore ees | 46 





& 
NO 





| | | a 
PR121 | | | | | | 32 ” 


43 | uh 
44 | SPSSX | PR122 [ | | | — | | | is 
SP SSY | PR121 | | | | | | | 


47 SP Integ Emitter PR243 | l | 
+6V Print Right Emitter PR131 | | | 


+6V Print Right Emitter 


é5 





PR131 


Print Scout Latch PR242 33, 49. 51 (¢ Clock ——— ( 


. Clock 3 Clock 3 
Print Adv Latch PR242 50 pee menue 50, 52 ( 
52 | Print Adv Inlk Latch. PR242 pa Chock 0 
53 SP Print Emitter Rise PR242 | a 
54 | SP Print Emitter Fall PR242 | 
SP SS3 (0.6 ms) 5 ao 
Clock 5 


SP Advance Matrix Counter | PR262 | | Sm te 





we 
Y 


5406 PRINTER ATTACHMENT- Operations | 
Print Operation Timing Chart (Part 2 of 2) } . 5406 FETMM = (2/71) 9-341 


5406 PRINTER ATTACHMENT- Operations | 5406 FETMM = (2/71) 9-342 
Bi-directional Print Operation (Part 1 of 3) 


BI-DIRECTIONAL PRINT OPERATION Line Prt Mode 


Printing in bi-directional print mode is accomplished in the same DBOR 7 
manner as it is in serial print mode. There are two basic require- Sp Sel $10 IR Cyc Ai Prt A : Prt Left 
ments that must be met in bi-directional printing. These are: ee Not LM Mat Tr 1_ A a Cvt Tr 2 
1. All lines to be printed should be of the same length (it is possible 
with some programs to vary line length). 
2. When printing from right to left, the count byte must be added 
(by the attachment) to the PDAR so that the last character in the 
data field is printed first. | 
In order to print the last character first (printing right to left only), an wr2 . 
initial count cycle steal and data cycle steal are taken. The procedure is ; Cvt Tr 4 
: Tr 
as follows: | Tr 
@ Take an initial count cycle steal and place the count byte in the print 


data register in the printer attachment. This count cycle steal is the Tr 1 Cvt Tr 1 
same as any other count cycle steal except that the count byte is not [A | 

decremented in the CPU, and that the count byte is brought over to 

the printer attachment. 


e Take an initial data cycle steal and send the count byte from the print | | | | | | | | 


data register to the CPU. In the CPU it is added to the PDAR address | ae fae Sa 


through the ALU. During this data cycle steal, nothing is brought over Tr? | | | | | | | | Se ose 
to the attachment. The PDAR is not decremented —1, but instead the | oo | [OT 
count byte is added to the contents of PDAR. Tr4 ! | | eee eee erent Se 
e The PDAR is now pointing at the last data character in the Prne Tele: ans | | | | | | | | 
When printing begins on a normal count and data cycle steal basis, l | l l l l 
the last character in the field is printed. The data field is decremented Cvt2 | | | | | | | 
until the count byte goes to FF (data is taken out of storage from right | | | | | | | | 
to left, instead of from left to right). Cvt 4 gr | | | 
It is important to remember that the above procedure (initialize left | | | | | | | | 
operation) takes place only when the print element is at the right hand | 7 | 6 | 5 | 4 | 3. | 2 | 1 | 


limit. Also, the right hand limit is variable according to the program. 
Printing from left to right requires no initial cycle steals. 

The following flowchart of the bi-directional print operation shows 
only the initialize left operation. The actual printing and stepper motor 
operations are the same as shown in the serial print flowchart, except 
that the matrix counters must be decoded so that line seven prints 
first in a bi-directional print operation. 


Bi-directional 
Print Operation 


Take two load 1!/O’s 
to preload 

the printer 

LSRS. 

Page 9-302 





One load 1/0 loads 
the address of 

the first character 

to be printed into PDAR. 
The other load !/O loads 
the address of 

the first command 

to be executed 

into PCAR. 









Take a start 1/O 
to request a 

cycle steal. 
Page 9-308 






‘Ch data bus out 5’ 
active and ‘ch 

data bus out P’ 
inactive, grants 

a cycle steal 

to the printer 
attachment. 










Activate ‘SP decode 
priority assignment’. 





Select the 
PCAR to get 
a command. Set the ‘cmmd steal’ 


latch. 





Start stepper 
motor as in 

a tab oper- 
ation. 

Page 9-324 












At ‘SP clock 8 
_or 4’ activate 
‘LSR select 

4 and 6’. 







A) 9.344 


5406 PRINTER ATTACHMENT- Operations 
Bi-directional Print Operation (Part 2 of 3) 





















PR212 































This line activates the 












The I-R byte of the 
SIO instruction 
will have the 7 bit on. 


PR231 










At ‘SP clock 8’ this 
line active, activates 
‘SP cycle steal honored’. 





This latch set 

activates 

‘SP format steal’ 
and 

‘SP cmmd steal’. 


The stepper motor 
moves the print 
element during a 
print operation as it 
does during a tab 
operation (slow speed 
only). $S1 is fired to 
check for a horizontal 
cycle check; and SSW, 
SSX, SSY and SSZ 
are fired to stop the 


element when printing 
is complete. 








select lines ‘ch LSR 

select 4’ and ‘ch LSR 
select 6’ to select 

the PCAR in the CPU 

to get the command byte. 


Mo 


(8) 9-344 


3. Store the 
count byte 


back in main 
storage. 





Take an initial 
data steal to 
add the count 
byte to the 
PDAR. 


1. 


Request a 
data cycle 
steal. 


. Sendthe — 
count byte 
to the CPU 
and add it 
to the PDAR 
in the ALU. 





S 9-344 



























Set the ‘count 
steal’ latch. 







When set, this 
latch activates 

‘SP format steal’ and 

‘LP initial left count steal’. 










This line activates 
the select lines 
‘ch LSR select 4’ 
and ‘ch LSR select 6’ 
to select the 

PCAR in the CPU 

to get the count 
byte. 









PR232 


At ‘SP clock 8 or 
4’ activate ‘LSR 
select 4 and 6’. 







PR274 


At ‘SP clock 5C’ 
gate the count 






With ‘LP initial 
left count steal’. 






byte into the PDR. 


PR231 
Set the ‘data 





Set by ‘SP print 
command’. 






req’ latch at 
‘SP clock 7B’. 





PR231 









At ’SP clock 6’ 


This line active, 
activates ‘SP chan 1 
cyc steal req 5’ 

to request a 

cycle steal from 
the CPU. 


activate ‘Ch priority 
request bit 5’. 


PR212 
‘Ch data bus out 
5’ active and 
‘ch data bus out P’ 
inactive grants a 


cycle steal PR231 
to the printer. 








At ‘SP clock 8’ 
this line active 
will activate 
‘SP cycle steal 
honored’. 


PR212 
Activate ‘SP 


decode priority 
assignment’. 





PR231 


Set the ‘data 
steal’ latch. 
CS 9-344 


5406 FETMM 


(2/71) 


9-343 


5406 PRINTER ATTACHMENT- Operations 
Bi-directional Print Operation (Part 3 of 3) 


Si, 





A) 9.343 







Set the command 
latches in the 
attachment. 










At ‘SP clock 5C’ 
| activate ‘SP set 
cmmd latches’. 











The commands for 
bi-directional mode 
are the same as for 
serial printing. 












Assume ‘SP DBOR1’ 
for a print com- 
mand is active, 

and the ‘SP elem 

at Lm’ latch is 

not set. 



















In bi-directional 
printing however, 
if the attachment 
decodes a DBO 
reg 1 fora print 
















command, and Set the ‘prt 
the print element left’ command 
is away from the latch. 


left margin, the 
‘prt left’ command 
latch will set 












Set the ‘cmmd 
chained’ latch 
with ‘SP DBORO’. 


Set the ‘initialize 
left’ and ‘init Ift 
inlk’ latches. 


PR231 
Set the ‘count req’ 


Take initial 
count cycle 
steal to bring 
the count byte 
over to the 
attachment and 
place it in 

the print data 
register. 


latch at ‘SP 
clock 7B’. 





PR231 
At ‘SP clock 6’ 
activate ‘ch 
priority request 
bit 5’. 
1. Request a PR212 


‘Ch data bus out 
5’ active and ‘ch 
data bus out P’ 
inactive grants a 
cycle steal to the 
printer. 





count cycle 
steal. 


. Address the 
PCAR and 
bring the 
count byte 
to the at- PR212 
tachment and 
gate it into 
the PDR. 





Activate ‘SP 


decode priority 
assignment’. 


G 9.343 cc) 9-343 















The element is 
away from the 
left hand margin. 
Therefore, in line 

print mode, we will 
print from right to left. 





This latch activates 
‘SP prt left cmmd’ 
and ‘SP count cmmd’. 













Activates 
‘SP cmmd 
chained’. 






At ‘SP clock 7’ 
with ‘SP prt 
left cmmd’. 









Set by ‘SP Cmmd 
steal’ and 
‘SP count cmmd’. 





PRO12 







This line active, 
activates ‘SP 
chan 1 cyc steal 
req 5’ to request 
a cycle steal from 
the CPU. 












At ‘SP clock 8’ 
this line active 
will activate 
‘SP cycle steal 
honored’. 


ety 





\) 9-343 


At ‘SP clock 3’ 
activate ‘LP init 
left gate PDR to 
DBI’. 


The count byte 
is added to the 
PDAR. 


The PDAR is 
now initialized 
and pointing 

at the last 
character in the 
line to be 
printed. 


A normal se- 
quence of count 
and data steals 
will now take 
place until 

the line is 
printed. 


The printing 
takes place 

as shown 

on page 9-336. 


The difference 
is that the 
PDAR is dec- 
remented, while 
the count byte 
goes to FF. 





End of 


Operation 









5406 FETMM (2/71) 9-344 


“a 
Bod? 


PR412 






This line active 
gates the count 
byte out of the 
PDR and back 

to the CPU. 





The PDAR is now 
pointing at the last 
print position 

for the line. It 

will be printed 
first and the 
PDAR will be 
decremented down 
by 1 instead of 
incremented 

by 1 each time 

a character is 
printed. When 

the count byte 

is FF the line 

is complete. 


1 


|—OP 1-—Q I—R I—O I—O I—O I—O I—O 
Line Title ALD Page | 1 i \ I \ l { | 
012345678,/012345678/012345678);012345678/01 2345678/012345678/|01 2345678/012345678)01 2345678 ;|01 2345678)01 2345678,01 2345678);012345678),012345678 


‘i | eCere ! eae. | | cee | | eee ae : | 
| 8 | spcycleSteal Honored | PRI31 | | | Clock 8 | Clock 8 | Clock 8 | Clock 8 | | Clock 8 | | | 
E pra | | ! ee ! 1 1 | | ! 
PR231 | | | | | | eer J Clock 7C | | | | | 
prot | ! | | | 5 oe email a 4 | ! | 
| | | | l Clock 2. al l To Add Count To PDAR | | | 
| li | | | | | Clock 3 7 | [ | To Decrement PDAR 
foe PRO2A To Increment PCAR | | l l Decrements Count Byte —{ | clocks WE PORT 
24 PRO24 | | | Clock 3 | Clock 3 | | | Clock 1 F_ CIO°K § Clock 3 7 ee ae 
B 25 PR232 | | | | | | oe | Clock 1 | | | Clock 6 _Clock 1 | | | 


18 ae 


. | Clock 8 | Clock 7C Clock 8 Clock 7C 
26 Ch Store Data PR232 | | | 14 pele 14 | | 18 a sme 18 ! 7 












i 



























5406 PRINTER ATTACHMENT-— Operations 
Bi-directional Print Operation Timing Chart : 5406 FETMM = (2/71) 9-345 


Chapter 4. Introduction 


LEDGER CARD DEVICE ATTACHMENT 

The ledger card device (LCD) attachment contains the logic circuits to con- 
trol all LCD operations. The LCD attachment responds to LCD program in- 
structions, requests cycle steals from the CPU, controls the resulting I/O 
cycle, error checks, and provides status information about the LCD attach- 
ment to the program. 

The LCD attachment is a standard feature for the 2222 Printer. It is 
located in the printer attachment board (A-A2) and shares considerable 
circuitry with the printer attachment. 7 

Program instruction format and device codes (E hexadecimal) are the 
same for both the printer and ledger card device. The M code of an in- 
struction determines the device selection. An M code of 0 selects the printer, 
and an M code of 1 selects the LCD. 

There are three local storage registers used by the LCD attachment, two 
of the three are shared with the printer. 


Ledger Card Format 

The ledger card format is shown in the illustration to the right. Print posi- 
tions 215 through 220 are reserved for line finder and ID number marks. 

No printing other than these marks should occur beyond print position 214. 
Marks are printed on the card by the printer under program control. Refer 
to page 9-102 for further information on print marks. Each printed line 
must have a line finder mark or the line will be overprinted when the card is 
reinserted into the LCD. 


1D Number 

Each digit of the 1D number is encoded on the ledger card as a 8-4-2-1 bit 
code. Bit values are determined by the way they are arranged and printed 
on the card as shown. 








Odd Vine: sciatic 8 | 


, One digit 
E Ver Vite ccemeecenneinoms 
Code track 2. 
Code track 1 : | 
BR2502 


Each digit of the |D number requires two lines to encode it. 


LCD ATTACHMENT -Introduction 
Ledger Card Format 


Ledger card dimensions 


Maximum Minimum 


Length 11 inches 8 inches 
Width 14 inches 6 inches 


Margins 


Top 1 inch 
Bottom  .833 inches 


Ledger card shown printing 
side up 


TNL SN34-0043 to SY34-0022-1 


LINE 1 ID NUMBER 9876543210 







Print position 215, must be blank 


Print position 217, must be blank 


Print position 218, 2nd code track (8 or 2 bit) 


Print position 219, must be blank 


Print position 220, 1st code track (4 or 1 bit) 





Print position 214, no printing Begane this point (except line finder marks) 


Print position 216, line finder mark track 


=, 20 Srint lines a 
= 10 digit ID number = 


: (Note. Marks within 2 
this area are to show : : 
: fine spaces and are = 
: for reference only.) 


5406 FETMM 












eit UU 


ant 


BR2501 


(6/71) 


iT 








9-401 


LCD ATTACHMENT -— Introduction 
Indicators, Instructions, Operations and Commands 


Indicators and Controls 


There is one indicator and one manual control for the LCD. The indicator is 
the LCD I/O attention light on the keyboard console. It lights when a ledger 
card can be inserted into the LCD and turns off when the LCD operation 
starts. 

The card eject switch, located on the printer cover (to the right of the 
LCD input chute), is the only manual control. When the card eject switch 
is Operated, it causes a ledger card in the LCD to be ejected. This switch is 
interlocked to prevent a manual eject operation if a program initiated opera- 
tion is in progress at the printer or LCD. 


Local Storage Registers 


There are three local storage registers assigned to the LCD attachment. They 
are the print data address register (PDAR), print command address register 
(PCAR), and the locate line address register (LLAR). 

The PCAR and PDAR local storage registers are shared with the printer. If 
printer and LCD operations are overlapped, care must be exercised to pre- 
vent changing an LSR address before an operation is complete. The PDAR 
contains the address of the main storage location where LCD data (ID num- 
ber) is stored. The PCAR contains the address of the main storage location 
where the command field (a control field) for the LCD is located. 

The locate line address register (LLAR) is not shared with the printer. 
This register is used for two LCD operations: feed, read ID, and locate; 
~ and index. This register contains the main storage address of a two byte 
field that is used as two separate decrementing counters. This field is initial- 
ized to 110E (hexadecimal) at the start of an LCD operation. 


Program Instructions 


There are four program instructions for the LCD: load I/O (LIO), test 1/O 
(TIO), sense I/O (SNS), and start I/O (SIO). 

Load I/O instructions load the LSRs with an address in main storage 
where data and contro! fields for the LCD are located. A control LIO in- 
struction is available for diagnostic testing of the LCD attachment under 
program control. 


Test I/O instructions test the LCD attachment for operation status. It also | 
prepares the LCD to accept a ledger card before an LCD operation is started. 


Sense I/O instructions can store the address in an LSR at a main storage 
location, or sense the error and status conditions in the LCD and transfer 
the results into main storage. 

Start I/O instructions perform only one function, to start an LCD opera- 
tion. An LCD start I/O instruction does not have any control information 
to determine what operation the LCD is to perform (except for diagnostic 
operations). The start |/O causes the LCD attachment to request a cycle 
steal to obtain the necessary control information from a control field 
located in main storage. | 

The format of these instructions is the same as for the printer. Refer to 
pages: 9-105 through 9-109 for further description and format illustrations. 


TNL SN34-0043 to SY34-0022-1 


Ledger Card Device Operations 

The LCD can perform the following six operations. 
e@ Feed, read ID, and locate next print line 

e@ Feed, read ID, and eject 

e Read all line finder marks 

e@ Read back and eject 

e@ Index 


e Eject 


Feed, Read 1D, and Locate Next Print Line 
This operation causes the LCD to: 
1. Feed the ledger card into the LCD. 


2. Read the ID number from the ledger card and transfer it into main 
storage. 
3. Feed the ledger card until the next available print line is positioned 


at the printer platen and stop the card feed. 


Feed, Read [D, and Eject 
This operation causes the LCD to: 
t Feed the ledger card into the LCD. 


2. Read the 1D number from the ledger card and transfer it into main 
storage. 

3: Feed the ledger card through the LCD and eject it into the LCD 
stacker. 


Read All Line Finder Marks 
This operation causes the LCD to: 


1. Feed a ledger card into the LCD. 

2. Read the line finder marks (if any) printed on the ledger card. Each 
mark is read twice, once as it passes the lower sense station (sense cell 
3) and again when it passes the upper sense station (sense cell 4). 

3. Generate a data byte for each two lines read from the card. By bit 
assignments within each byte, indicate if a line finder mark was read 
and what sense station it was read from. Transfer the data byte to 
main storage. 


Read Back and Eject 
This operation causes the LCD to: 


1. Start ejecting the card from the LCD. (Note, the card was stopped 
with the last printed line positioned at the platen when this operation 
started.) 


5406 FETMM = (6/71) 9-402 


2. Read the line finder mark that was located at the platen when this 
operation started as it passes sense cell 4. 
3. Indicate if the line finder mark was read by (1) ejecting the card from 


the LCD, or (2) if the line finder mark was not read, stop the LCD 
feed and indicate a read mark check. 


Index 


This operation causes the LCD to move the ledger card to the next sequen- 
tial print line. 


Eject 


This operation causes the ledger card to eject from the LCD into the LCD 
stacker. 

A programmed eject is started when an LCD start I/O instruction is issued 
and the command field in core is an eject. 

A manual eject is started when the card eject switch is operated. This oper- 
ation can not be started if a program initiated operation is in progress at the 
printer or LCD. 

The card eject switch must be held in its operated position to eject the 
card. The manual eject operation will stop as soon as the switch is released. 


Commands 


LCD operations are not performed directly by issuing program instructions 
to the LCD attachment. All LCD operations are divided into one or four 
smaller instructions referred to as commands. Commands are one byte in 
length and are located in main storage. The command or group of commands 
required to perform one operation is referred to as a command field. The 
address where the first byte of the command field is located in main storage 
is loaded into the PCAR LSR, before the beginning of an LCD operation. 

Some commands require an additional control byte, called a count byte. 
Count bytes are used as a decrementing counter and determine how long a 
command instruction is to be executed. If a count byte is required, it must 
immediately follow the command byte it is associated with. 

Commands are accessed by the LCD attachment by requesting cycle 
steals from the CPU and addressing the LSR (PCAR) that contains the com- 
mand field address. As each command enters the LCD attachment, it sets a 
register that gates the attachment to control the LCD and perform the com- 
mand. If the command has a count byte, the LCD attachment executes the 
command until the count byte decrements to FF (hexadecimal). Each byte 
in the command field is executed, in sequence, by the LCD attachment until 
the end of the command field is reached. 

There are eight LCD commands. Their bit codes, the function they per- 
form, and if they require a count byte, is shown in the following illustra- 
tion. 


Command Bit Count byte 
name code | required 
. and if so, 
its value. 


Read mark Yes—08 
eject (count of 9) 


Sense amp Yes—05 


check (count of 6) 


Card skew Yes—00 
check (count of 1) 


Locate Yes—04 


ID (count of 5) 


Read 1D Yes—13 
and locate (count of 20) 


Read !D Yes—13 
and eject (count of 20) 


LCD ATTACHMENT-Introduction 
Command Field Formats 


Function 


Eject the ledger card from the LCD. 


Move the ledger card to the next se- 
quential print line. If the bottom edge of 
the ledger card is above the lower sense 
station, decrement the OE byte of the 
110E field 1 for each index command 
issued. 


Start the LCD card feed. When the line 
that was positioned at the printer platen 
when this command was issued passes 
sense cell 4, see if a line finder mark was 
read. If a line finder mark was read, eject 
the card. If no mark was read, set a read 
mark check. 


Instructs the LCD attachment to check 
the lower sense cells in the LCD for an 
operational status. If they are not func- 
tioning correctly, a sense amp check is set. 


Instructs the LCD attachment to check 
sense cells 1, 2, and 3 for an inactive con- 
dition. If any of the cells are active after 
the 7th line feed, set a card skew check. 


Instructs the LCD attachment to feed the 
top edge of the ledger card 6 line spaces 
above the lower sense station. This moves | 
the top margin of the ledger card above 

the cells and in a position to start reading 
the first printed line where the 1D number 
begins. | 


Instructs the LCD attachment to read the 
20 line ID number (10 digits) and at the 
same time, search for missing line finder 
marks. When 2 missing line finder marks 
are found in succession, start decrement- 
ing the 11 byte of the 110E field at the 
LLAR address. 


This operation is the same as read locate 
except the LCD attachment does not 
check for line finder marks. The ledger 
card is ejected after reading the 1D num- 
ber. 





BR2503 


Command Field Formats 


The commands required for each LCD operation, their sequence and count 
byte relationship is shown in the following illustrations. The LCD com- 


mands for each operation are fixed and must be issued as shown. 


Feed, read ID and eject 


Byte 
Sense amp Card skew 
check check 
Feed, read 1D, and locate next print line 
Byte 
Sense amp Card skew 
check check 
Byte 


Sense amp Card skew 
check check 


TNL SN34-0043 to SY34-0022-1 


Read ID 
and eject 





Read 1D and 
locate next 
print line 





Read ID 
and eject 





Read mark and eject 





Read back 
and eject 


index 


Byte 1 


Cmmd 


Index 


Eject 


Byte 1 


Cmmd 


Eject 


BR2504 


5406 FETMM = (6/71) 9-403 


LCD ATTACHMENT-Introduction 
General Operation 


General Operation of the LCD 


The program is responsible for: 


1. Generating the command field for the operation to be performed. 
2. Loading the LSRs. 
3, Loading the next printable line and the last printable line counters 


with the 110E value if the operation is a feed, read ID, and locate. 


The last program instruction, before starting a feed, read ID, and locate; 
feed, read ID, and eject; or a read all line finder marks operation, is a TIO 
for card not aligned. This instruction causes the LCD to raise the card gate 
and light the LCD 1/O attention light on the keyboard console, indicating 
that a ledger card can be inserted into the LCD. The program will /oop on 
the TIO instruction until a ledger card is inserted into the LCD and is 
aligned at the pinch point of the first feed rolls. When the card is properly 
aligned within the LCD, the TIO instruction for card not aligned is un- 
conditioned and the program performs an LCD SIO instruction. 

One of three operations can be issued to feed the ledger card into the 
LCD: feed, read ID, and locate next print line; feed, read ID, and eject; or 
read all line finder marks. Each of these operations synchronizes the LCD 
attachment, the ledger card, and the LCD with each other when the ledger 
card is aligned at the first feed rolls in the LCD. From this point on, the 
LCD attachment is kept in step with the LCD timing pulses received from 
the LCD. Each timing pulse is generated on a line for line basis. The LCD 
attachment uses this signal to request cycle steals from the CPU, to access 
the command field, and to decrement the count bytes. As each count byte 
is decremented to FF (hexadecimal) the next command byte is accessed. 
This action continues until the command field has been executed. It is im- 
portant to recall the mechanical layout of the LCD and the ledger card for- 
mat to understand the command field function. 


Next Printable Line and Last Printable Line Detection 


A two byte field, addressed by the LLAR, is used as two separate decrement- 
ing counters to detect the next printable line and the last printable line on 
the ledger card. The format of the field is shown below. 


First byte | 


Locate line counter 
equals FF (hexa- 
decimal) when next 
printable line is 
positioned at. the 
platen. 


Second byte 


Last printable line 

| counter equals FF 

| (hexadecimal) when 
| last line is located 

| and FE at the end 
of an operation. 





BR2505: 


TNL SN34-0043 to SY34-0022-1 


The first byte is the locate line counter and contains the value of 11 (hexa- 
decimal) at the start of an operation. Its purpose is to cause a feed of 18 
line spaces after the LCD attachment detects the next available print line. 

The reason for this delay is because the lower read station, where the line 
finder marks are sensed, is 20 line spaces from where the next line should 
stop at the printer platen. In addition, the LCD attachment must sense 2 
missing line finder marks in succession before the attachment recognizes the 
next printable line. Therefore the locate line counter equals 17 (decimal) to 
cause a 20 line lapse. (Two lines for missing line finder marks plus one 
timing pulse to decrement the 11 byte (hexadecimal) to FF.) 

The 11 (hexadecimal) value is decremented with each LCD timing pulse, 
after the two missing line finder marks are detected, until the count be- 
comes FF (hexadecimal). This value generates a control signal to stop the 
LCD feed. The actual value in byte one will be FE (hexadecimal) when the 
operation is complete. 

The second byte contains the value of OE (hexadecimal), and is the last 
printable line counter. When the OE byte decrements to FF (hexadecimal), 
it generates a signal that may be sensed with a TIO instruction. When the 
bottom edge of the ledger card passes the lower read station, the OE byte 
is decremented with each timing pulse. In this manner, when 14 line spaces 
have passed after the bottom of the ledger card was sensed, the last print- 
able line is positioned at the printer platen. (The actual distance between 
the lower sense station and the platen is 20 linespaces, but allowance must 
be made for the 5 linespace margin at the bottom of the card plus 1 for 
decrementing the count to FF.) 

Note, the 110E value must not be reinitialized for an index operation 
because the last printable line count would be invalid. 


Line Finder Mark Detection 


A line finder mark is printed at the end of each printed line. The LCD at- 
tachment uses the absence of line finder marks to detect the next printable 
line on the ledger card. Two conditions are checked for by the LCD attach- 
ment during line finder mark detection. 


i; The line finder mark printed at the last printed line on the ledger 
card should not be late in relation to the LCD emitter pulse. If this 
condition is detected, an extra line space must be skipped before the 
ledger card is stopped at the printer platen to prevent overprinting of 
lines on the ledger card. 

2. If an extra line space is skipped because a line finder mark is detected 
late, the attachment checks that the last printable line has not been 
detected. This is to prevent the skipped line from being stopped be- 
yond the last available print line on the ledger card. If this condition 
exists, the ledger card is ejected from the LCD. 


5406 FETMM = (6/71) 9-404 


Error Detection 


The LCD attachment checks for six error conditions during LCD operations. 
if any of the LCD errors are detected, the LCD card feed is stopped and a 
status condition is generated to indicate which error occurred. For LCD 
error conditions and their description, refer to page 9-523. 


Chapter 5. LCD Functional Units 


This chapter divides the LCD attachment circuits into seven major units. 
e ‘CD pulse generate and sense cell latches 

@e Command control, diagnostic LIO control, and LCD attachment resets 
DBI assembler and channel in controls | 


Cycle steal and LSR selection 


Read ID data assembler 


e LCD controls 
e LCD attachment error conditions 


Each unit contains second level diagrams showing the interconnection 
with other units and ALD references. Some units contain simplified dia- 
grams and timing charts. 

Signal lines on the second level diagrams are labeled to indicate where the 
signal originates. 9-XXX numbers refer to pages within this manual where 
the source of the signal is located. PRX XX references are to printer attach- 
ment ALDs where the signal is generated but is not shown in this manual. 
Clock signals are not referenced. | 

The timing charts are for instructional use only, to show overall signal re- 
lationship. For exact timing references, refer to the ALDs. 

The complex units are explained in detail. Objectives only are given for 
units that are basically self-explanatory. 

A data flow diagram is included at the beginning of this chapter. It shows 
the relationship of the functional units and serves as an index to locate the 
page where the functional unit is described. © 

Printer circuits that are shared with the LCD attachment are shown in the 
printer chapters 2 and 3. Refer to pages 9-202, 9-204 and 9-211 for the 
major units. 

Refer to page 9-202 for the LCD and printer attachments board layout. 


LCD ATTACHMENT -—Functional Units 
Introduction to Functional Units 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-501 


LCD ATTACHMENT—Functional Units 


Dataflow 


an 


O ,Or,~R «OO ~N 


A Register 


DBI 


Channel In 


Controls 


Channel Out 
Controls 


CPU Logic 





DBO 


TNL SN34-0043 to SY34-0022-1 | 5406 FETMM = (6/71) 9-502 












Clock 1 


NO ,Or pP pW AN ym ,O 


DBI Data Stacker Rolls 
Assembler 
Assembler |. 9-510 


9-518 





9-510 
Stacker 


Upper Feed Rolls 


Card Eject CS 
Switch 
\ 
oS 


DBI Assembler 


: LSR ' 
Select 
9-204 


J 










LSR 
Select 






| 
| 
Read ID Seta | 
| 
| 
| 
| 















Cycle steal 
eo honored or 9-515 | | Sense 
LCD Controls 9-520 : Cell 4 
request | ae / 
Pulse Shaping and Card Out Switch | / 





Single Shots 
9-504 9-507 


cS Clutch Motion Contact L_] S 






| Sense Amp 1, 2, 3 and 4 rs) ow, 






reset steal | 


Select 
LLAR 





Printer 
Initial 
Selection 












Feed Clutch Magnet 












| 
| 
9-204 Gate Status | 
| | Timing Pulse 
(2) | Card In Switch 
| | Card Gate Magnet 
0 | 0 
| : | 
2 2 | 
3 3 | 
|4 | . 4 | 
5 | 5 | | 
: - | Skew Rolls r \ 
| ower Feed Rolls 
DBO Register | Command | i 
Register _| 
| Diagbotic 9-510 | Sense Cells 1, 2, and 3 
Printer Attachment | an LCD Attachment | Ledger Card Device 


LCD PULSE GENERATE AND SENSE CELL LATCHES 
This functional unit: 

e@ Receives signals from the LCD. 

@ Synchronizes and shapes signals for the LCD attachment. 
e Detects missing or late line finder marks. 

e Generates timing gates. 


e Contains the sense cell latches. 


Pulse Shaping 


Signals from the LCD to the LCD attachment, and LCD single shot output 
signals are passed through pulse shaping logic. Pulse shaping: 


1. Insures an input signal is at least clock 3 through clock 0 time in 
length to distinguish between a desired signal and electrical noise on 
the signal line. 

2: Synchronizes the input signal to the LCD attachment clock times. 
This results in the input signal starting and ending at definite clock 
times. 

3. Breaks input signals, that are long in duration, into pulses that indi- 
cate a change in signal status. 


Each signal line that requires pulse shaping, is fed into a circuit containing 
two polarity holds. The manner in which the polarity holds operate to shape 
a signal is shown by the timing chart on this page. 


LCD Emitter Pulse 


This signal is generated midway between clutch ratchet teeth whenever the 
LCD feed clutch is energized. The first emitter pulse occurs approximately 
30 ms after the feed clutch is energized and approximately 14 ms thereafter. 
Timing pulses are shaped by the pulse shaping circuits, and result in a signal 
that is clock 3 through clock 0 in duration. LCD timing pulses control the 
LCD attachment on a line for line basis. 


Sense Cell Latches 


There are four sense cell latches, one for each of the LCD sense cells. These 
latches are set when a sense cell detects a mark on the ledger card and are 
reset at the end of each LCD timing pulse. 


Single Shots 


Six single shots develop timing gates in the LCD attachment. The purpose 
of each single shot is as follows: 


1. LD stop single shot produces a pulse 2 ms after each LCD timing 
pulse. Its output is the LD stop pulse and is the final condition to 
reset the LCD drive latch and stop the LCD feed clutch. 

2. LD skip line single shot 1 and LD skip line single shot 2 are used to- 
gether to generate a gate 10.5 ms after each LCD emitter pulse. This 
gate conditions the LCD attachment to define any line finder mark 
sensed after this gate is active, as /ate. LD skip SS1 is fired by each 
LCD emitter pulse; its only function is to fire LD skip SS2. Two single 


LCD ATTACHMENT—Functional Units 
LCD Pulse Generate and Sense Cell Latches (Part 1 of 4) 


Clock joj: |2|3|4|5/6]7]s8/o]1| 2] 3] 4]5]6]7]s]of1 [2|3]4]5]6]7/s}+- s—3]4[5]6{7|sfof1 [2|3]4|5]6|7]8]o| 
t 


For Single Shot Pulse Shaping 
Single Shot Input 
Clock 3 Controlled Parity Hold 
Clock O Controlled Parity Hold 


Time Out Logic Output 


For LCD Timing Pulse and Sense Amp Shaping 
Signal Input 
Clock 3 Controlled Parity Hold 
Clock 0 Controlled Parity Hold 
LD Timing Pulse Clock 3 to O 
LD Sense Amp Pulse 
LD Sense Amp Latch 


shots are needed because of single shot recovery requirements. 


3: LD drive check single shot generates a 45 ms gate to set the drive 
check latch if an LCD timing pulse is not sensed at the LCD attach- 
ment within 45 ms after a feed instruction is issued to the LCD. This 
is to insure mechanical motion was started after a feed instruction was 
issued. The LD drive check single shot is fired at the start of each SIO 
instruction. | 

4. LD hold busy single shot is fired whenever the LCD drive latch is 
reset. This prevents the LCD attachment busy signal from becoming 
inactive until 55 ms after an LCD feed operation has ended. This de- 
lay is to allow mechanical motion to stop before another operation is 
issued to the LCD. | 

5, LD card alignment single shot is fired when a ledger card is aligned at 
the pinch point of the first feed rolls and transfers the card in switch. 
The card alignment single shot generates a gate to prevent an LCD 
feed operation from starting until 250 ms after the card in switch has 
transferred. This is to insure that the ledger card is fully aligned at the 
pinch point of the first feed rolls before card feed begins. 


Line Finder Mark Detection 


The latches: late gate, late mark, 1st miss, 2nd miss, and skip line function 
together to provide line finder mark control to the LCD attachment. 

Refer to the timing chart on page 9-505 for the timing relationship of 
these latches. | 

Late gate latch conditions the late mark latch 10.5 ms after each LCD 
timing pulse. If a line finder mark is sensed before the late gate latch is 


TNL SN34-0043 to SY34-0022-1 


! 
Input signal active 





BR2506 


reset, the late mark latch is set to indicate that a line finder mark was de- 
tected late. 

First and second miss latches indicate the number of line spaces on the - 
ledger card that were read and no line finder marks were found. Two miss- 
ing line finder marks in succession is a signal to the LCD attachment to stop 
the LCD feed after feeding 18 more line spaces. (Unless the last line finder 
mark was late, feed 19 line spaces before stopping the card feed.) This 
positions the next printable line on the ledger card at the printer platen. The 
skip line latch is set, if the last line finder mark read was sensed late to cause 
the extra line feed. 


LCD Card Position Detection 


The card-in and card-out switches in the LCD, set latches in the LCD attach- 
ment. After pulse shaping, these signals control the LCD attachment in re- 
gard to card position within the LCD. 250 ms after the card in switch latch 
is set, the card alignment latch is set to indicate that a ledger card is posi- 
tioned at the pinch point of the feed rolls and a card feed operation can be- 
gin. 

The card gate latch activates the LCD card gate, and controls when a 
ledger card can be inserted into the LCD. This latch is set by an LCD TIO 
instruction for card not aligned. 


5406 FETMM = (6/71) 9-503 


LCD ATTACHMENT—Functional Units | 
Pulse Generate and Sense Cell Latches (Part 2 of 4). 





















TNL SN34-0043 to SY¥34-0022-1 





5406 FETMM = (6/71) 9-504 














T 2 3 
| — _LD Clock 6 ! 
‘ 7 | - —— LD Sense Amp 1 Pulse , 
; LCD Sense Amp 1 __ | | cee aS p | See Keaoaitaten 
9-508 _LCD Diag Sense Cells Off “I LD Sense Amp 1] RH | —_—— LD Sense Amp 1 Latch 
9-5 8 'ag. ense ells —a = ~éPE erent ml ) : | 
— : , LD Sense Amp 3 Pulse 
seb einceAnee il Eee LD Glock 3 | ate Clock Ot —_—— —_— — — LD Sense Amp 2 Latch 
*LCD Sense Amp 3 | ¢ | _ LD Sense Amp 3 Latch 
_*LCD Sense Amp 4_ tt eee PRESS 9-508 LD Attach Rst Pwd 1 |  PR836 LD Sense Amp 4 Latch. 
| Note. The logic for sense amps 2 through 4 LD Clock 8 mas JOR I 
| is identical to sense amp 1. A o 


*LED Timing Pulse 
fon SP Clock 3 


9-204 LD Diag Emitter Pulse wee ee PH “I PH 
oo : Bs dc JO Clack 0 
: PR641 , | 


PR833 PR833 


[OO Ticmeca a 
| 
| LD Stop SS 
| LD Clock’3 
— PR721 
a b-< | 
. | 5 ms 


PR835 
fs LD Skip Line SS1 LD Clock 0 | 
PR711 | | 


PR835 


LD Clock 6 


5.5 ms | 


' 
_ dD Skip SS2 Note. All single shot outputs 
| are shaped by logic 


identical to the ‘LD 
| stop SS’. 


I 
LD Drive Check SS 
) . 


9-204 LD I-R Cycle and Clock 5 





LD Hold Busy SS ¢ 





9-520 LD Drive Latch Reset Pulse 


“Refers to a signal line to or from the LCD. 


t LD Stop Pulse 
, Sat. Y 





















es Late Gate a Mark 
At 9-507 _LD Card In Switch LD Deena Latch 
| ‘.) LD Skip Line SS2 Time Out wal 
| oe 
Mark 
LD Timing Pulse Clock 3 ta 0 PR836 ti OR] - page | 
9-508 {LD Attach Rst Pwd 3 
9-508 LD Read and Locate Cmmd A 
Skip Line 
| LD Skip 2 Line 1 
A 
| LD Clack 6 Tod 
7 Skip Line SS1 Time Out ry. PRS2e: 
| LD Clock 5 
| LD Skip Line SS2 Time Out 
| | 2nd Miss 
LD 2nd Miss 1 
| 9-520 LD Attach Busy Clock 7B a" 
( | LD Drive Check SS Time Out 
PR822 


LD Hold Busy SS Time Out 


) | 






9-508 LD Attach Rst Pwd 2 





i 





Clutch ratchet 
Chart 1 : ee ms 


pf times re oT rr er fey il iti tak 
| | 0 | 0 0 Q O} . O | OL tt tt 0 
: | I | | i | | I | ~ if 


_ Timing Pulse Ciock 3 to O 


Lee LD Skip Line SS1 | | | | | | | | 
3 | LD Skip Line SS2 ) I | ) bo | | i i 


Approximate Position of | | | | | | | | | | 
Line Finder Mark sccaieiaiaia | 


Sense Cell Latch 3 
(shown fora nominal mark) 





Approx 1.72 us A 















Chart 2 


Line Finder Mark Pattern on Ledger Card ! No Mark 


7 | 1st Miss 


ors 


| 2nd Miss 


t No Mark ! _ : No Mark 
‘ A 


re 19 
53> | 
o | 
Tl Iu 
' > 
QO 
om 
™ 
= 
a 
= 
= 
“OU 
oO 
= 
- | « 
: 4) 
= 
p> | 
oO 
pe) 

{ r 
om 
2. 
ae 
4°) 
= F 
oO 
a 
~~ 
o. 





| 1st Miss 


2nd Miss 


o 
— 


Chart 4 
Line Finder Mark Pattern on Ledger Card 





12. Late Mark Latch | | | | | | | | | 


Stop card motion on the 19th ratchet tooth from this point —_. $f} >} | | ; |. << | 


18 Skip Line Latch - Skip line latch set will cause one extra line space before stopping ledger card at platen | | | | : | [ } j 


Chart 5 


Sense Cell 3 Latch 


Late Mark (no mark due to previous late mark skip) | Mark | - |p | NoMark ! | —_— ae 1 No Mark 3 ie 


Line Finder Mark Pattern on Ledger Card] | : ' | | ' 
18 Late Mark Latch | | | | | |. | | | 


Chart 1 shows the normal sequence for line finder mark detection, and is the time base for the 
other 4 charts. Charts 2, 3, 4, and 5 are ending sequences for 4 different line finder mark patterns. 


LCD ATTACHMENT—Functional Units 
LCD Pulse Generate and Sense Cell Latches (Part 3 of 4) TNL SN34-0043 to SY34-0022-1 5406 FETMM = (6/71) 9-505 





1 2 3 
LD Clock 6 
LD Card Alignment SS 7 LD Card Alignment SS Time Out 
PH 
Card In Switch Break Pulse LD Clock 3. 
LD Clock 3 A 
PR835 
LD Clock 0 250 ms | 
Card In Switch Make Pulse PH 
LD Clock O 
PR711 
PR835 
A 





Card Aligned L 
LD Card Aligned L 
FL 


9-508 LD Attachment Reset 
*+LD Card In Sw Card In Sw L | —o—r ee 
A ; oR 


P FL | | 
*—LD Card In§$ 
-D Card In Wee! 9-508 LD Diag Card In Sw o) | 


: | 9-510 LD LCD I/O Attention | Card Gate L 
PR815 Card In Transport FL LD Pick Up Card Gate 


LD Card In Switch 







PR815 
* + LD Card Out Sw Card Out swt | 
A 
aa : FL | LD Card Out Sw 
— LD Card Out Sw, ie 9-508 LD Diag Card Out Sw i 
PR815 
LD Clock 6 
| A LD Card Out Sw Break Pulse 


LD Clock 3 


PR835 


LD Clock 0 


PR835 


*Refers to a signal line to or from the LCD. 


LCD ATTACHMENT—Functional Units 
LCD Pulse Generate and Sense Cell Latches (Part 4 of 4) TNL SN34-0043 to SY34-0022-1 5406 FETMM ss (6/71) 9-507 


LCD ATTACHMENT—Functional Units 
Command Controls, Diagnostic LIO Controls, and LCD Attachment Reset (Part 1 of 2) 





1 


LD DBOR7___ 
LD DBOR 6 
LDDBOR5 __ 
(from printer PR212)} | | 
| (07) 
X = line active EEE ; in — PH 


O = line inactive 


- Read Eject — 





| Read-Locate 





Locate-!D 


PH 


Card Skew Check 
PH —<— 


PH 


Read Mark Check 
PH 


Eject 


index 
PH : 


= . F a F 


9-515 LD Last Printable Line | | 
PR811 
LD Clock 5C | 


9-515 LD Command Steal Latch — 


9-508 LD System Reset 


*Refers to a signal line to or from the LCD. 


_ Sense Amp Check © 


From Printer 
PR211, PR212, 
PR214 


TNL SN34-0043 to SY34-0022-1 


2 


kh WH OO 


SP DBOR O — 
SP Select LCD 
SP Ctri L1IO EB1 Set-Reset 


SP DBOR 3. 


SP DBOR 5 


SP DBO 6 





5406 FETMM = (6/71) 9-508 










3 
LD Read-Locate or Read-Eject 
on | _Read-Mark or Read Locate or Read-E ject 
on Any Count Command 
Command 
Chained LD Command Chained Latch 
A Fay. : 
LD Clock 7 : 
] 9-508 LD System Reset J 
9-515 LD Cmmd Steal L AT i orf 
| | PR811 
PR261 SP Check Reset . LD Check Reset 
on or Attach Reset 
SP Clock 2 | PR814 
9-204 SP LCD Selected I-R Cycle pectin 


PR812 


PR216 SP System Reset 


“~~ 


“U0 


k Je teh ds 


PR834 


or LD System Reset: 


LD Diag System Reset 


LD Diag Sense Cells Off 


, h Pwd 1 

AR . LD Attach Rst Pwd | 
. | ee PR812 

LD Diag Card In Switch 


| | LD Attach Rst Pwd 2 
LD Diag Card Out Switch AR , . 


PR821 


AR LD Attach Rst Pwd 3 


PR832 


COMMAND CONTROL, DIAGNOSTIC LIO CONTROL, AND LCD 
ATTACHMENT RESETS 


This functional unit: 
@ Contains the command register and its controls. 
e Contains the control LIO (diagnostic) register. 


e Shows the LCD attachment reset. 


Command Register | 
e@ Sets during a command cycle steal when a command byte is on the DBO. 


e Output is fed into a decode network to group similar commands, and 
set the command chained latch if there are additional commands in the 
command field for the specific operation. 


e Gates the LCD attachment to perform one of eight commands. 


Diagnostic Control! Register and Reset Wetwork 
e@ Sets during the EB1. cycle of a control LIO instruction. 


e Simulates LCD attachment signals with polarity holds set from the DBO 
lines during a control LIO instruction. 


The LCD attachment reset network prepares the LCD attachment for an 
operation by conditioning the latches in the attachment to specific set or 
reset states, | 


LCD ATTACHMENT—Functional Units 
Command Control, Diagnostic LIO Controls, and LCD Attachment Reset (Part 2 of 2) TNL SN34-0043 to SY34-0022-1 5406 FETMM = (6/71) 9-509 


LCD ATTACHMENT-—Functional Units 
DBI Assembler and Channel In Controls (Part 1 of 2) 


TNL SN34-0043 to SY34-0022-1 5406 FETMM = (6/71) 9-510 

















1 2 Vv 3 
LD Data BitO —— 0 SP Clock. 
it 1 —_—— 9-515 LD Cmmd Steal Latch 
9-204 SP TIO or APL Seats Bir ; : LD Force DBI P Bit 
LD Data Bit2 —= 2 9-514 LSR Plus Steal 
9-204 SP Select LCD LD Data Bit 3 3 LD Clock 1 
LD Clock 7 9-518 
A LD Data Bit4 ——— 4 PR824 
9-204 Chan I-O Cycle LD Data Bit 5 5 , PR842 
PR212 LD DBOR 5and6 ; 
LD LCD 1/0 Attention LD Data Bit 6 —— 6 
9-507 Card Aligned Latch Ny, FL LD Data Bit7 —— 7 
9-508 LD Attachment Rst Pwd 2 lor Status 3 9-522 Sense Amp Check 
PR215 SP Gate Status 1 or 3 ilk xt | | 
PR825 9-504 Sense Amp 1 X 
| TXT || LD Force DBI Bit O 
A 9-504 Skip Line SS1 Ty xy | 
PR221 SP Count Cmmd | | | | fol 
a . 9-522 Card Skew Check xt { [ 
PR261 SP Attch Busy od PR215 SP Gate Status 2 or 4 9-504 Sense Amp 2 | Sta 
| | xt f LD Force DBI Bit 1 


9-504 Skip Line SS2 
PR222 SP Cmmd Chained | 


9-204 SP Select LCD 
LD Ptr or LCD Busy 
9-508 LD Read Cmmd L OR 


PR214 SP Select 7 9-522 Drive Check Latch 


9-504 Sense Amp 3 


. 9-504 Late Mark Latch 
‘ Ee 


9-522 Read Mark Check 
PR831 9-504 Sense Amp 4 


} Bias | 7 LCD Installed 7 
PR811 | | [| [3 


9-522 Line Finder Mark Check 
9-504 LD Timing Pulse 
9-507 Card Alignment SS 


A 
TA 
, 
9-520 LD Attch Busy a @) LD Force DBI Bit 2 
9-508 (not) LD Programmed Eject Cmmd ‘ 
9-515 (not) Cmmd Count Stop L | | 
PR825 Note. (N) means (not) 
9-522 LD Unit Check 


PR212 LD DBOR (N)5 (N)6 (N)7 


LD Force DBI Bit 3 
9-204 SP Select LCD 


9-204 SP TIO or APL 
PR212 LD DBOR (N)5 (N)67 


LD Force DBI Bit 4 
9-515 LD Last Printable Line " 


PR211 SP Cover Inik or Carr N6 Sw 


| 
9-520 LD Manual Eject Inlk L 
9-520 LD Attachment Busy 


PR212 LD DBOR (N)5 6 (N)7 9-522 Invalid Command Check 


9-504 Drive Check SS 


(not used) 


LD Force DBI Bit 5 





PR212 LD DBOR (N)56 7. 






LD Block I/O Condition B | 9-507 Card In Switch 


i~t tf je} ty 


9-520 Activate LCD Feed Clutch 


(not used) 


PR515 (not) LD Read ID End LD Force DBI Bit 6 


LD Force DBI Bit 7 





PR212 LD DBOR (not) 6 
PR212 LD DBOR 5 


Loc 


9-507 (not) LD Card Aligned 
PR212 LD DBOR 56 


9-507 Card Out Switch 
9-504 Hold Busy SS 


9-504 Stop SS 
9-204 SP Select LCD 


@ 9-204 Chan SIO Inst 


TTT PTI 
CCRT 
CeETTe 


9-514 LD Any Cycle Steal 
LD Clock 3 A 


LD Force DBI Bit 7 


*Refers to a signal line 
to or from the LCD. 


PR825 


SP Clock 1 
9-514 LD Count or Loc Line Or Doc End Stl 


PR824 


PR831 


DBI ASSEMBLER AND CHANNEL IN CONTROLS 
This functional unit: 
e Gates LCD attachment data and status bytes onto the DBI. 


e Generates constants for LSR address and storage modification. 


e@ Controls the I/O condition B response to SIO and TIO instructions. 


e Controls the LCD I/O attention light on the keyboard console. 


LCD ATTACHMENT~—Functional Units 
DBI Assembler and Channel In Controls (Part 2 of 2) 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-511 


CYCLE STEAL AND LSR SELECTION 

This functional unit: 

e Requests cycle steals from the CPU. 

e Selects one of the three LSRs assigned to the LCD attachment. 
@ Controls the channel ALU binary subtract line. 


e Can prevent a constant, oe on the DBI, from modifying an LSR 
address. 


e Indicates when a count byte, or either ee of the 110E field, has 
decremented to FF. 


@ Indicates when the last printable line on the ledger card has been de-. 
tected. 


e@ Indicates when the last count byte of a command field has been proc- 
essed for the operation in progress. 


@ Detects when the bottom edge of the ledger card is past the lower sense 
cells. | 


Cycle Steal Requests and Cycle Steal Cycles 


Cycle steal requests are made by the LCD attachment to access the LCD 
command field, the LCD data field, and a field that contains two one-byte 
counters. All fields are located in CPU main storage. The need for an I/O 
cycle is indicated when the LCD attachment sets a request latch. When the 
CPU acknowledges the request, a second latch is set in the attachment to 
gate the use of the 1/O cycle. Timing charts showing most of the LCD cycle 
steal functions may be found on pages 9-516 and 9-517. The purpose of 

- each LCD cycle steal is as follows. 


Command Requests and Command Steal Cycles 


Command requests are made by the LCD attachment to access the com- 
mand bytes in the command field and set the LCD attachment command 
register. During this cycle: | 


1. The PCAR LSR is selected. 
2. When the command pale is on the DBO, set the LcD command reg- 


fster.. 
3. Check that the command byte is valid. 
4. If the command byte is not the last one of the command field, set the 


command chained latch. : 
5. Increment the PCAR address by one. 


Count Requests and Count Steal Cycles 2 
Count requests are made to decrement the count byte. During this cycle: 


1. The PCAR LSR is selected. 
2: ALU binary subtract is conditioned to decrement ‘ive count Byte: 


3. Inhibit LSR load is active to prevent the LSR address from increment- 
ing until the count byte decrements to FF. 
4. Count end latch is set when the count byte decrements to FF. 


LCD ATTACHMENT—Functional Units 
Cycle Steal and LSR Selection (Part 1 of 5) 


5. When the ID field has been read into main storage, a signal is gener- 
ated to set the condition latch and activate ‘LD read ID end.’ 


_ (The last two conditions are dependent on the LCD operations being exe- 


cuted.) | 


Data Requests and Data Steal Cycles 


Data requests are made to transfer into main storage (1) an assembled digit 
of the ledger card 1D number or, (2) during a read all line finder marks oper- 
ation, a byte that indicates the presence of line finder marks. During this 
cycle: 


1. The PDAR LSR is selected. 
2. The data byte is gated onto the DBI. 
a PDAR address is incremented by one. 


Locate Line Requests and Locate Line Steal Cycles 


Locate line requests are made to decrement the 11 byte of the 110E field. 
When the 11 byte decrements to FF, stop the LCD feed clutch to position 
the next printable fine on the ledger card at the printer platen. During this 
cycle: 


1. The LLAR LSR is selected. 

2. Decrement the 11 byte of the 110E field by one. 

3. | When the 11 byte decrements to FF, set the LLAR equals FF tatch, 
and if the skip line latch is not set, reset the stop latch. 


LSR Plus Requests and LSR Plus Cycles, Document End Requests, and 
Document End Cycles ; 


These requests are always made in sequence. Their purpose is to decrement 
the OE byte of the 110E field in order that the last printable line on the 
ledger card can be detected. During the LSR plus cycle: 


1. The LLAR LSR is selected. 


2. The LLAR address is incremented by one. 


3. Request a document end steal. 
During the document end steal: 


1. The OE byte is decremented by one. 
Zi: Set the last line latch if the OE byte decrements to FF. 
3: Decrement the LLAR address by one. 


LSR Selection 


Cycle steals select an LAR to address one of the three LCD fields in main 
storage: LSR PCAR address the command field, LSR PDAR addresses the ~ 
data field, LSR LLAR addresses the field that contains 110E. 


TNL SN34-0043 to SY34-0022-1 


Count End Latch 


This latch is set whenever a count field has decremented to FF and, depend- 
ing upon the operation being executed, it may condition the LCD attach- 
ment to: 


iL Set the last line latch. 

2. Set the count stop latch. 

= Decondition the signal ‘inhibit LSR load’ to allow the address in the 
selected LSR to increment. . 

4. Request another command cycle steal. 


Inhibit LSR Load 


When this signal is active, it prevents the CPU from incrementing the address 
in the selected LSR. An example would be when a count byte is being decre- 
mented, the PCAR address must not be changed until the count byte decre- 
ments to FF. 


Count Stop Latch 


This latch is set when the read locate, read eject, or read mark eject com- 
mand count byte (byte 8 of the command field) decrements to FF. This 
signals the end of the command field for feed, read 1D, and locate; feed, 
read ID, and eject; or read all line finder marks operations. The output 
from this latch is a gate to set the condition latch and is one condition to 
activate the read ID end signal. 


Condition Latch 


The condition latch determines when to allow LSR plus and document end 
requests, It is set during a feed, read ID, and locate operation when the 
count stop latch is set. Note that the condition latch is not reset with the 
LCD attachment reset signal. This is necessary to prevent the condition 
latch from resetting when an LCD index operation is issued to the LCD 
after a feed, read ID, and locate operation. 


Read ID End 


The ‘LD read 1D’ end signal is active when the [ID number, read from the 
ledger card, has been transferred into main storage. It can only be condi- 
tioned during two instructions: feed, read ID, and locate; and feed, read 
ID, and eject. The condition of this signal line determines the LCD attach- 
ment response to an LCD TIO read ID busy instruction. 


5406 FETMM = (6/71) 9-513 


LCD ATTACHMENT—Functional Units 
Cycle Steal and LSR Selection (Part 2 of 5) 


1 


9-508 LD Any Count Cmmd 


9-518’LD Odd Data Line 0 


9-508 LD Read-Loc or Read Eject 





9-508 LD Index Cmmd L 


LD Clock 7B 
LD Allow Doc End Steal Req EL 


9-508LD Read and Locate Cmmd L 


A 


9-504 LD Timing Pulse Clock 3 to O 
A é 
LSP ; 


9-518 LD Odd Data Line 
9-515 LD Data Steal L 







TNL SN34-0043 to SY34-0022-1 
Vv a 2 


9-515 LD Count Stop L Nw 


Count Request 
9-520 LD Attachment Busy Clock 7B 


FL 


) 9-520 LD Attachment Busy PR821 


9-211 SP Steal Cycle Honored 


LSR Plus Reg 


9-211 SP Reset Steal Rea 
9-508 LD Attach Rst Pwd 1 OR, : 


9-504:'LD Timing Pulse Clock 3 to O 


LD Sense Amp 1 
LD Sense Amp 2 | 
LD Sense Amp 3 A 


1 


9-504 






9-515'LD Cmmd Count Stop L 


LD Doc End Steal L 


Condition Latch 


1" 


Initial Reset 


9-515 LD Cmmd Count Stop L 
9-508 LD Read and Locate Cmmd L 


9-508 LD System Rest 


9-522 LD Sense Amp Check Cmmd L 
9-515 LD Cmmd Steal L. 
LD Clock 7 


*Refers to a signal line 
to or from the LCD. 


LSR Plus Steal 
PR842 
1 
9-211 SP Steal Cycle Honored 


LD Clock 7C 
Doc End Req 
PR842 
LD Clock 7B: FL 
9-211 SP Reset Steal Request 
9-508 LD Attach Rst Pwd 1 Doc End Steal 
PR842 


9-211 SP Steal Cycle Honored 


a a LD Clock 7C 
A 
. PR842 
ES eal LD Allow Loc Line Req 
LD Count Steal L on Loc Line Req 
9-520 LD Attachment Busy Clock 7B A FEL 
9-504 LD 2nd Miss L 
LD Doc End Cond L Test Point PR822 


9-211 LD Steal Cycle Honored 


9-520 LD Attachment Busy 


9-204 SP Reset Steal Request C1) 


9-508|/LD Attach Rst Pwd 1 


LD Clock 7C 


9-515 9-515 9-515 


A | FL 
A 


5406 FETMM (6/71) 9-514 


9-520 (not) LD Manual Eject Inlk L _ 


Count Steal 








a 


PR821 
LD Any Cycle Steal Request 


LD Any Steal Cycle 






LD Store Data 
10 


© " 


ine Steal 


Loc L 
FL . 


PR822 


9-508 LD Read Mark or Read-Locate or Read Eject 
2 
| 9-520 LD Attach Rst Pwd 1 


*Refers to a signal line 
to or from the LCD. 


LCD ATTACHMENT—Functional Units 
Cycle Steal and LSR Selection (Part 3 of 5) 





Count Stop 
LD Cmmd Count Stop L 
FL 
9-508 1D Read-Loc or Read-Eject 
PR821 


TNL SN34-0043 to SY34-0022-1 








1 2 2 
9-514 
9-504 LD Timing Pulse Clock 3 to 0. 
9-508 LD Read-Loc or Read Eject 9-204 SP Select LCD 
LD Read ID End z Data Req ‘ 
9-518'LD Odd Data Line FL ° 9-204 SP LSR Select LLAR LD LSR Select 3 and 6 LLAR 
9-520 LD Attachment Busy Clock 7B 
3 Data Steal (next available line 
PR832 
oe A | FL 10 8 i. and last printable line) 
o 9-514 PR822. | c | 
© : LD Clock 8 or 4 
9-514 | 
9-211 LD Steal Cycle Honored PR822 
4 A 
9-508 LD Cmmd Chained L Commd Req , 
6: PRE 
. (4) LD Count End L A or FL 11 842 
Commd Steal ‘ 
9-204 SP LCD Selected |-R Cycle . A | 4 
: . AR Fly AS: as n |__LD_LSR Select 4 and 6 PCAR 
PR821 me 
| : command byte 
9-211 SP Steal Cycle Honored | op causative) 
A 2) LD Clock 8 or 4 
9-520 LD Attachment Busy PR821 A LD LSR Select 5 and 6 PDAR 
10 (1D number) 
2 FL LD ALU Binary Subtract 
> LD Clock 7C | PRO24 
~PR842 
2 LD Clock 3 ALU Bin Sub. 
6 | LD Count or Loc Line or Doc End Steal FL 
° SP Clock 5 and SP Phase B 
9-508 LD Attach Rst Pwd 2 oR | 
Count End PR824 Last Line 
LD Clock 5 _ LD Count End L FL LD Last Printable Line 
SP Adder Carry | FL 
LD Clock 8C - | 9-508 = System Reset : 
9-520 LD Attach Rst Pwd 2 oR’ one Wale! | | 
PR823 PR842 
. 4 N 
2 pu a LD Inhibit LSR Load ‘when active, prevents incrementing the address in the selected LSR) 
s Tea, 


LD Read ID End 


(signals the end of the read ID portion of 
the read locate or read eject instructions) 


5406 FETMM = (6/71) 


9-515 


LCD ATTACHMENT -—Functional Units 7 TNL SN34-0043 to SY34-0022-1 5406 FETMM (6/71) 9-516 
‘Cycle Steal and LSR Selection (Part 4 of 5) | 





2 





Signal Name 


















Count Steal 
and Count End 


Count 
Steal 






Approx 
154 ms 


Approx 
25 ms 






















LCD Attachment Cycle Cmmd Req | Cmmd Steal | | Count Req | Count Req | | Cmmd Req 


CPU Clock 


o 
a 
Q 
a 
3 


Start 1/O Instruction 


I~ 


oo 
~ 
NO 
>) 
S 
=p 


CD Selected IR Cycle 9-204 | | : l j [ 


ae 


CD Attachment Reset 9-508 l | | | l . { | 


© 
cn 
N 
° 


LCD Attachment Busy 


7 | 1/0 Condition B | | 
Data Bus Out (see note 1) PA lbp Q Iba C | PA Iba Cmmd lon | | loa loa Cnt Iba 4 lpn Iba Cnt loa PA 


LCD Select Latch 
Command Request 


Priority Request Bit 4 


No 
© 
fs 


2 
NO 
—_ 
— 


Cycle Steal Honored | | | 
| ! ae | ro | | 
. . | | yo TF . i | 
ae ee i [roan 

| | | Increment. PCAR] 1 a oe | | Increment PCAR] [ 

ie ( Decrement count nem \ Decrement count > 
7 | Store Data I | | ot b | | l | | | | | 
)1g| ALU Binary Subtract | 9.515 a 1 mar mia t 
}19| inhibittsR Load =| 9615 I | | | i ro | Allow PCAR increment | i 
[comm ‘loos TCO 
Se 


25 Activate LCD Feed Clutch | 9-520 | | | . bh, | l 1 l l ( | | i I | 
50. ! { | i | i | 1 i l l ) l i | I 


© 
ND 
cud 
= 


3 Reset Steal Request. 


O 


ommand Steal 
LSR Selected 


Data Bus In Bit 7 


2g = Zz 


26 Drive Check SS . 

Bistd Pulse number references are number of clutch ratchet | | i { 1st | i 
| pulse | | | | | 12th pulse E 

Poe 9-504 teeth past pinch point of first LCD feed rolls ( EE 3 | 

28 Command Latches 9-508 i | | I ! | ) j | | | i | | | | i 


Note 1. PA = Priority assignment Q=Qbyte C=Control byte Cnt= Count byte Cmmd = Command byte 





2 
Oo 


Signal Name 
Count 
Steal 


Approx | 


Loc Line Approx | 
266 ms 


| Loc Line Req | Steal 14 ms 


LCD Attachment Cycle Cmmd Steal | Count Req Data Req 


CPU Clock 


Oo 
o 
© 
| a 
3 


LCD Attachment Busy | 9-520 





Data Bus Out (see note 1) 


PA ~Cmmd 


Pe PA, , PA | A Cnt __PA | 
Eg 1 ) | | | ) | | | | | | 
pry | Lo I | ! | | | ! | | 


PCAR | | | lpcarR , ILLAR | | | lopAR | Il pcAR | 


Increment PCAR | | increment PCAR_ | | | Increment PDAR . | Increment PCAR | 


PA Cnt PA PA PA PA PA PA Cnt “PA 
Priority Request Bit 4 


Cycle Steal Honored 


= 
NO 
— 
-_ 


Reset Steal Request 


LSR Selected 






Data Bus In Bit 7 Decrement count , Decrement count 


ee and 


ag ee) | 
Pe ge ee 7 | aa 4 


I | i | Allow PCAR increment | 


Se rn eo HE | | | 4 
a ee to | | | 


10 | Store Data 


> 


LU Binary Subtract 


2] Block SDR to B Register 


—_ 
W 


Inhibit LSR Load 
4 Adder Carry 


ount End 


ount Request 


mh 


= —_ _ 
on 
oO 


7 


© 0 
o1 NO 
a = 
& cond 

wl] | 

oO ; 

QO 

na 

uv 

: a 

> 

wv 

= 

Q 

st 

@ 

3 

@o 

3 

> 

w 

oO 

Q 

= 

7 

a 

> 

a 

a 

Q 

x 

@ 

3 

@ 

S 

oF 


Count Steal | : i 
rT | | TOT r to 
) 2 es aa! Aa TRE MAORI e. 7 3 7 — : 
ee ee oe ere i 32nd pulse | Pulse number references are number of clutch ratchet | 
( EE | _ — | teeth past pinch point of first LCD feed rolls. 

| | | | | | | | | | | 
pry ( | | VS | | | | | | 
] | L | 
Pa a eee ie ~ I Od 
ro i 1 i | ro | a : I 
| { | { i I | | i I 55 ms | | | l 

. a ee ) / i ; | 7 | Attachment oat or new sonnane 


Set new command { 


ns 7 i a ar a ca ©. es 7 | : ! ia " : 3 ) 


byte C= Control byte Cnt=Count byte Cmmd = Command byte 


rs 
on 
N 
© 


Stop Latch 
} 19 | Activate LCD Feed Clutch] 9-520 


20 | LCD Timing Pulse 3to0 | 
21 


LLAR Request 
22 
23 Data Request 


24 Data Steal 


25. top Pulse 


26 | Hold Busy SS 


© © © 
O1 

a g g 

0 oO a 


27 Command Latches 


Command Steal 


“) rm 
a 
> 
J 
nw 
et 
© 
a 


Le [8 
it 
O 


ote 1.PA = Priority assignment OQ 


LCD ATTACHMENT—Functional Units 
Cycle Steal and LSR Selection (Part 5 of 5) | TNL SN34-0043 to SY34-0022-1 5406 FETMM (6/71) 9-517 


LCD ATTACHMENT -—Functional Units 
Read ID Data Assembler (Part 1 of 2) 


9-508| LD Attach Rst Pwd 2 


SP Clock 6 
9-508;LD Read-Loc or Read-Eject 
9-504.LD Timing Pulse Clock 3 to 0 


9-504 LD Timing Pulse Clock 3 to 0 


LD Clock 5C 


9-504 LD Sense Amp 3 Latch | 


9-504 LD Sense Amp 2 Latch 


PR212 SP DBOR 7 Sean oer 


9-204 SP LCD Selected I-R Cycle PH 
LD Clock 5C A 


9-508 LD Attch Rst Pwd 3. 
PR834 


9-504 LD Sense Amp 1 Latch’ 


9-504 LD Sense Amp 4 Latch 


*Refers to a signal line 
to or from the LCD. 


FF 


PR824 


| 


(odd lines) 


(even lines) 


9-508 LD Attach Reset 


LD 8 and 2 Bits 


LD 4 and 1 Bits 





TNL SN34-0043 to SY34-0022-1 


LD Odd Data Line 
9-514. LD Data Steal Latch 


A 
LD Clock 1 
8 Bit 
PR832 
4 Bit 


PR832 


2 Bit 


PR832 


1 Bit 


PH 


PR832 


(not) 8 
(not) 4 
(not) 2 


(not) 1 


(not) 1 
(not) 4 
r 
8 


2 


5406 FETMM = (6/71) 9-518 


3 
a LD Data Bit O 
A 
LD Data Bit 1 
LD Data Bit 2 
A 
LD Data Bit 3 
Gt 
Not8421 
PR832 
at Ny 
PR832 
82 Not 41 
an 
P 
Rese a LD Data Bit 4 
tS 


ys LD Data Bit 5 
| a LD Data Bit 6 


| LD Data Bit 7 
A 


PR832 


READ ID DATA ASSEMBLER 


This functional unit: For feed, read ID, and eject 
and feed, read 1D, and locate 


e Assembles each digit of the [ID number into an 8 bit byte. ea tnetiants 


e Decodes a blank in the [ID number to 40 (hexadecimal). 


to : Odd-E 
e@ Decodes digits 0 through 9 in the ID number to FO through FQ (hexa- a To 
decimal). | | Timing Pulse FF a 
@ Operates in one of two modes, normal or diagnostic. DBI 
assembler 


The illustration at the right shows the basic operation of the data assem- 
bler. The upper part of the illustration shows how the data assembler func- 
tions during feed, read ID, and locate; and feed, read ID, and eject opera- Sense Cell 2 
tions. The lower part of the illustration shows the data assembler operation 
for the read all line finder marks operation. 

In the operation shown by the upper part of the illustration: 


Sense Cell 1 











Line Finder Marks 





. bP he Odd-even Decimal value Data assembler Hexadecimal 
@ Two lines are read from the ledger card for each digit in the ID number. trigger encoded on parity hold(s) al Gexdeended 
(ledger card and condition ledger card set to DBI 


e The 8 and 4 bits are read on odd lines. 
1D number) 


e The 2 and 1 bits are read on even lines. 












e@ Marks are read from LCD sense cells 1 and 2. odd Siank eon 40 
even 
In the operation shown by the lower part of the illustration: odd 
} 1 1 F1 
e The SIO IR cycle set the scan mode latch. even 
Note. A zero is me odd — 
e Line finder marks are read by LCD sense cells 3 and 4. encoded on the even - ‘ ee 
ledger card as an : odd 
8 and 2 bit. This | even 3 zane ec 
is decoded to odd 
FO by the data even _ an i 
assembler. odd 
agen 5 4 and 1 F5 
odd . 
San 6 | 4 and 2 F6 
eee 7 4,2 and 1 F7 
even 
odd 
Gar 8 8 F8 
odd 
Sieh 9. 8 and 1 FO 


ataharatateetetetytatatetatetetstatatets 


r For read all line 


finder marks Read from Parity hold(s) Decode 


cuctOn sense cell set to 
x 
| }Band2—— and 2 FA 
3 [sis 
Sense Cell 4 x . F2 
Odd Not 8 and not 2 40 
J4andi | 
4 F4 
4 i F1 
Sense Cell 3 ices | Not 4 and not 2 40 
ot use 
X Combinations of above 
¢ 3 and 4 EF 


Not 8, 4, 2, and 1 40 


LCD ATTACHMENT -—Functional Units 


















LCD ATTACHMENT—Functional Units TNL SN34-0043 to SY34-0022-1 
LCD Controls (Part 1 of 2) : 
1 2 3 
| | wee fae oe a 9-507 LD Pick Up Card Gate 
—|s 
9-204 SP Sec Index Cmmd 
Busy Latch JL LD Attach Busy . an 
FL Ts or 9-504 (not) SP Diag Mode Yi} — 
| PR261 (not) SP Attach Busy — | | | 
9-504 LD Hold Busy SS Time Out ox era Y - * . 
9.508 LD Attach Rst , *LD Manual Eject Sw_ | Manual Eject PR641 
PR812 os. ac 
9-508. LD Attach Rst 
9-504 LD Stop Pulse | oR! 
| | PR812 
LD Clock 5C 
A 
9-204 SP LCD Selected I-R Cycle is | 
| | Drive Latch ee tn 
A — . _ oR A 
9-507 LD Card In Transport | : , #F : FL Clock Run : 
Stop Latch 
_ LD Attach Rst 
PR812 
9-522 LD Unit Check 
Manual 
9-507 LD Card Out Sw Break Pulse Eject Inik 
9-508 LD Attach Rst Pwd 1 LD Clock 7 FL 
9-504 LD Skip Line Latch 9-508 LD Attach Rst 
9.515 j LD Clock 6 
9-515 LD Last Printable inet PR812 
A 
9-504 LD Timing Pulse Clock 3 to 0 


A 
9-515 LD Count End Latch 
9-504 LD Stop Pulse 
A 


9-514 LD Loc Line Steal Latch PR641 LD Feed Motion Contact 


FL 






LD Index Cmmd L | 


9-508 LD Index Cmmd L LD Drive Chk Time Out 


9-508 LD Attachment Reset 
PR812 9-522 LD Drive Chk Reset Drive L 


9-504 LD Timing Pulse and Clock 8 9-522 LD Invalid Cmmd Clock 6 


*Refers to a signal line 
to or from the LCD. 


5406 FETMM (6/71) —-9-520 


LCD Card Gate Magnet 
2nd Forms Magnet 


LCD Feed Clutch Magnet 


Manual Eject Inik L 


LD Drive Latch Reset Pulse 


LCD CONTROLS 
This functional unit: 
e Indicates when the LCD attachment is busy. 


e Prevents a manual eject operation when the printer or LCD attachment 
is busy. 


e Contains the LCD feed clutch start-stop circuits. 


Busy Latch 
The busy latch is set at the start of an LCD start 1/O instruction and remains 


set until after an LCD operation ends, and the hold busy single shot times 
out. 


Manual Eject Latch 


The manual eject latch prevents the manually operated card eject switch 
from starting a feed operation whenever the printer or LCD attachment is 
busy. 


Manual Eject Interlock Latch 
While performing a manual eject operation, the manual eject interlock latch: 


1. Prevents LCD cycle steal requests from reaching the CPU. 
2. Blocks the 1/O condition B signal to the CPU. 


Drive Latch and Stop Latch 


The stop and drive latches control the LCD feed clutch magnet. The drive 
latch is set to activate the clutch magnet and start the LCD drive. To stop 
a feed operation, two signals are needed. One signal controls when the feed 
operation should end. The second signal is required to drop the armature 
into the clutch ratchet (at the proper time) to engage the next clutch rat- 
chet tooth. If this precaution is not observed, the armature could fall too 
jate in relation to the next clutch ratchet tooth, to stop the clutch at the 
desired line position. 

In operation, the LCD attachment resets the stop latch to signal when a 
feed operation is to end, and allow the next stop pulse (emitter pulse) to 
reset the drive latch to deactivate the clutch magnet. 

For an index operation, the clutch motion contact resets the drive latch, 
allowing only one line space per index instruction. 


LCD ATTACHMENT—Functional Units 
LCD Controls (Part 2 of 2) 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-521 


LCD ATTACHMENT —Functional Units 
LCD Attachment Error Conditions (Part 1 of 2) 


1 





Sense Amp 1 
9-504 '< Sense Amp 2 


Sense Amp 3 


9-508 LD Card Skew Chk Cmmd L 
9-514 LD Count End L 


PR212 SP DBOR Not 01234 Ny 


hae 
PR212 LD DBOR5 A Le 





9-504 LD Timing Pulse Clock 8 
9-508 LD Attach Rst Pwd 1 





LD Clock 5C 1st Cmmd Inlik 9-520 
9-204 LCD Selected 1/R Cycle FL 9-507 
9-507 
9-508 Attachment Rst 
LD Clock 7 , 
PR813 
9-504 
9-515 Cmmd Steal L 9-504 
9-507 
\ A 
LD Clock 6 9-504 
9-504 
9-508 LD Read Mark and Eject Cmmd L 2s 
9-514 LD Count End L FL 
9-504 LD Timing Pulse Clock 8 
*Refers to a signal line to pee. a ecnmens et Ewell : JOR 
and from the LCD. PR814 


2 


LD Invalid Cmmd and Clock 6 


9-504 LD Drive Chk SS Time Out 






9-204 LD 1/R Cycle and Clock 5C 


LD Attachment Busy 
LD Card tn Sw Break Pulse me 
LD Card Out Sw | w 


TNL SN34-0043 to SY34-0022-1 





9-514 LD Count End L 


9-508 LD Sense Amp Chk Cmmd L Sense Amp Check 














Card Skew Check 


Drive Check 
Inlk - 












PR813 


LD Drive Chk Rst Drive L 





on PR814 


Drive Check L 


LD Sense Amp 3 Latch 
LD 2nd Miss L 
LD Card In Sw 


Line Finder Check 


| 


PR814 
Read Mark Check 





(not) Sense Amp 4 Latch 
LD Timing Pulse Clock 3 to 0 
LD Clock 7 


PR813 


a 
mz 
x 


9-508 LD Check Rst or Attach Rst 


5406 FETMM 





(6/71) 


LD Unit Check 


LD !/O Check Indicator 


LCD ATTACHMENT ERROR CONDITIONS 


This functional unit: 


e Detects Error conditions. 


e Conditions unit check if an error is detected. 


@ Stops any operation in progress when any error condition is detected. 


The LCD attachment checks for proper operation of LCD operations and 


commands. If an abnormal condition occurs during an operation, one of six 
error latches is set. Any of the six error conditions will cause a unit check 
and immediately stops the LCD operation in progress. The LCD check con- 
ditions are as follows. 


I 


Sense amp check. This check may be set during the first command 
for: feed, read ID, and locate; feed, read ID, and eject; and read all 
line finder marks operations. It insures that sense cells one, two and 
three are not activated by the leading edge of the ledger card, after 
the 6th timing pulse of a card feed. Normally the leading edge of the 
ledger card should cover the lower sense cells 6-1/2 line spaces beyond 
the pinch point of the first feed rolls. 

Card skew check. This check may be set during the second command 

for: feed, read ID, and locate; feed, read ID, and eject; and read all 

line finder marks operations. It insures that the top edge of the ledger 
card covered the lower sense cells after the 7th line space beyond the 
pinch point of the first feed rolls. If any sense cell (one, two, or three) 
is not active, it indicates (1) that the card has not reached the lower 
read station at the correct time, (2) that the card is skewed in the card 
path, or (3) one of the sense cells is not functioning correctly. 

Invalid command check. This check may be set during each command 

steal. It checks for two conditions. 

a. The first byte of any command field must be 00, 01, 02, or 03. 
The LCD attachment sets the invalid check latch if DBO lines O, 1, 
2,3, 4, and 5 are active during the first command steal of a com- 
mand field. 

b. Command bytes 3, 5, and 7 of a command string must be coded 
04, 05, 06, or 07. The LCD attachment sets the invalid check latch 
if DBO line 5:is not active during the 2nd, 3rd, and 4th command 
steal cycles. 


LCD ATTACHMENT —Functional Units 
LCD Attachment Error Conditions (Part 2 of 2) 


Drive check. This check indicates that mechanical motion was not 
started in the LCD after a feed operation was issued. To prevent this 
check, an LCD timing pulse must be sensed by the LCD attachment 
within 45 ms after a feed operation was issued to the LCD. At the 
start of an operation, the drive check interlock latch-is set and the 
drive check single shot is fired. If an LCD timing pulse does not reset 


the drive check interlock latch before the drive check single shot times 


out, the drive check latch is set. 

Line finder mark check. This check can be set only during a feed, read 
ID, and locate next print line operation. It indicates that after two 
successive line finder marks were found missing (2nd miss latch is set), 
another line finder mark was sensed at the lower sense station. 


Read mark check. This check can be set during a read back and eject 
operation. It indicates that the line positioned at the printer platen 
when the read back and eject operation was issued, did not have a 
readable line finder mark when that line passed sense cell 4. Sense cell 
4 is located 9 line spaces above the printer platen, therefore the check 
for the line finder mark must be delayed until the ledger card has 
moved 9 line spaces from the printer platen. 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-523 


Chapter 6. Ledger Card Device Attachment Operations 


This chapter explains how the LCD operations are performed. LCD instruc- 
tions load I/O, test 1/O, sense !/O, and start |/O are the same as for the 
printer and are explained in Chapter 3. 

Operations are arranged in the following order. 


Feed, read ID, and locate next print line; and feed, read ID, and eject. 
Index 


Read back and eject 


Eject 


Read all line finder marks (diagnostic) 


All of the operations except read all line finder marks, are explained in 
three parts. First the objectives of the operation are given, followed by an 
operational data flowdiagram and one or more timing charts. | 

Operational data flow diagrams are of the two level type. The boxes con- 
nected by a heavy line explain the major functions of the operation. The 
boxes to the right of the heavy lines and connected by a lighter line, ex- 
plain the details. 

The timing charts show the overall relationship of the signals needed to 
perform an operation. They are referenced to the functional units in Chap- 
ter 5 by listing the page where the logic that generates the signal can be 
found. A note is included on each timing chart that states the assumptions 
made about the marks on the card and other pertinent information. 


LCD ATTACHMENT-—Operations 
Introduction to Operations 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-601, 


FEED, READ ID, AND LOCATE NEXT PRINT LINE; FEED, READ ID, 
AND EJECT 


These operations are similar. Both operations feed the ledger card into the 
ledger card device and read the 1D number from the card into main storage. 
The difference in operation occurs after the 1D number is read from the 
ledger card. 


Feed, Read ID, and Locate Next Print Line 


Feed, read ID, and locate next print line checks for line finder marks while 
feeding the card into the LCD. When two consecutive line finder marks are 
found missing, the LCD attachment signals the LCD to stop feeding the 
ledger card when the next available print line is positioned at the platen. If 
a line finder mark is sensed late (in a position to cause overprinting of a 
line), the LCD attachment signals the LCD to feed one additional print line 
beyond the normal stopping point, before stopping the card. 

Information can now be printed on the card by the printer, each line must 
be followed by a line finder mark. An LCD index instruction can be issued 
to move the ledger card to the next sequential print line. However, the pro- 
gram must check for a last printable line condition (a TIO instruction) be- 
fore printing to insure that the card has not moved beyond the last available 
print position on the ledger card. 

To remove the card from the LCD, the program can issue either a read 
mark and eject or an eject instruction to the LCD. For information about 
these operations, see pages 9-619 and 9-623. . 


Feed, Read ID, and Eject 


Feed, read ID, and eject does not check for line finder marks. After the 
LCD has read the ID number from the ledger card, the card continues to 
feed through the LCD and into the stacker. 

Before either of these operations begins, the system program must issue 
LIO instructions to load the local storage registers with the following ad- 
dresses. 


@ PCAR with the storage address of the first byte of a command field. 


e PDAR with the storage address where the first byte of the 1D number is 
to be read into. 


e LLAR with the storage address of a two byte field that contains 110E 
(hexadecimal). This LSR is used only for the feed, read ID, and locate 
instruction. 


LCD ATTACHMENT- Operations 
Feed, Read ID, and Locate-Eject (Part 1 of 10) 


One of the following command fields must be created at the PCAR ad- 
dress. 
For feed, read ID and locate next print line. 


Rae R eS 


For-feed, read ID, and eject. 


Next, a test I/O instruction is performed to check for card not aligned. 
This causes the LCD to: 


1. Block |/O condition B. 
2. Light the LCD I/O attention lamp on the keyboard console. 
3. Raise the card gate in the LCD so that a card can be inserted. 


Note, the TIO instruction should also check for, not unit check, not LCD 
busy, and not LSR busy. 

The LCD I/O attention light on is a signal to the operator to insert a led- 
ger card into the LCD. 

The program does not have to wait until the operations are completely 
finished to examine the [ID number. Even though the LCD is busy, a TIO 
instruction check for not read ID busy will indicate when the 1D number 
has been transferred into main storage. 


TNL SN34-0043 to SY34-0022-1 


After these operations are finished, the program should check for not unit 
check before starting another operation. If the instruction was a feed, read 
ID, and locate; not last printable line condition should also be checked for. 

If a feed, read ID, and locate next print line instruction is issued to the 
LCD and the ledger card does not have an [ID number, (blank card) the ID 
data field at the PDAR address will be filled with 40 (hexadecimal) and the 
ledger card will stop with the first printable line positioned at the printer 
platen. 


5406 FETMM = (6/71) 9-603 





LCD ATTACHMENT-— Operations 
Feed, Read ID, and Locate-Eject (Part 2 of 10) 


1 


Operator inserts a ledger 
card into the LCD. The 

| LCD aligns the card at 
the pinch point of the 
first feed rolls and trans- 
fers the card in switch. 




















Fire: 
‘card alignment SS’, 9-507 





‘Card align 
SS’ timed out 





Set: 


‘card aligned’ latch. 9-507 
Reset: . | 
‘I/O attention’ latch. | 9.549 


Deactivate: 
‘block |/O condition 
b’. 





The absence of ‘block 
1/O condition b’ allows - 
the program to perform 
an SIO instruction. 


Start 1/O instruction. I-R Cycle 


l-op and 1-Q cycles 1 9-204 


select the LCD through 
the printer attachment 
logic. 





TNL SN34-0043 to SY34-0022-1 





2 


Reset: 
‘card gate latch’ 9-508 
‘LCD resets’. 

Set: 
‘stop latch’ 9-520 
‘pusy’ latch 9-520 
‘drive’ latch 9-520 
‘Ist cmmd inlk’ latch | 9-522 
‘cmmd req’ latch 9-515 
‘drive check intk’ 9-522 
latch. 

Fire: 
‘drive check SS’. 9-504 

Activate: 
‘LCD feed clutch’. 9-520 








Command steal for byte 
one of the command 
field. 














CPU acknowledges com- 
mand cycle steal. 
Set: 

‘cmmd steal’ latch. 
Select PCAR LSR. 
Byte one of the com- 
mand field is on the 
DBO. 
Set cmmd register ‘sense 
amp check’. 
Increment PCAR address 
plus 1. 






The first command is a 
sense amp check. 





9-515 


9-508 


Valid 
command 


No 


‘Invalid cmmd’ latch 9-522 


‘Unit check’ 





5406 FETMM = (6/71) 9-604 













Clutch motion contact 
makes approximately 

8 ms after the drive latch 
is set. 










‘LCD timing pulse’ 






Card movement begins 
when the LCD clutch 

armature is clear of the 
clutch ratchet. 






First ‘LCD 
timing pulse’ 


Yes 















‘Drive 
check SS’ time 







First ‘LCD timing pulse’ 
should occur approx- 
imately 30 ms after the 
LCD attachment drive 
latch is set. 












‘Set: 
‘count request’ latch. 







| Reset: 
‘drive check intk’ 
latch. 





9-522 





CPU acknowledges count 
cycle steal request. 
Set: 

‘count steal’ latch. 
Select PCAR LSR. 
Decrement core 1. 
‘Inhibit LSR load’. 


















Count cycle steal to 
decrement sense amp 
check count byte until 
it carries. 







| 9-514 Note. Loop should occur 
for the second 
through sixth 

9-515 timing pulse. 



















Do not increment PCAR 
address until count byte 
equals FF. 












Count No 
field equal 
FF 
Set: 
‘drive check’ latch 9-522 
} ‘unit check’. 
CPU ‘adder carry’ ena eerer sl 
Set: 

‘count end’ latch. | 9-515 | | 
Increment PCAR 
address 1. End operation 

LCD sense No 


amp 1, 2, and 3 
active 


Set: 


‘sense amp check’ 9-522 
‘unit check’, 


End LCD 
operation 





Set: 
‘cmmd req’ latch. 





A 9-605 


A 9-604 










/ Command cycle steal 
| for byte 3 of the com- 
mand field. 









CPU acknowledges 
command cycle steal 
request. 






The second command is 
a card skew check. 














Select PCAR LSR. 





Byte three of the 
| command field is on 
the DBO. 


Set command register 
‘card skew check’. 


| 9-508 










Increment PCAR address 
| plus 1. | 


Valid No 


command 





‘LCD timing pulse’ 
(seventh) 


Set: 
‘count req’ 9-514 


‘Invalid cmmd’ latch 


| Count cycle steal to 

| decrement card skew 
check count byte until 
it carries. This requires 





CPU acknowledges count | 
cycle steal request. 









only one cycle as the 
count byte value is 00. 








Set: | 
| Increment PCAR address. ‘count steal’ latch. 9-514 
Select PCAR LSR. 
Decrement core (count 
byte) 1. 
‘Inhibit LSR load’. | 9-515 


LCD ATTACHMENT— Operations 
Feed, Read ID, and Locate-Eject (Part 3 of 10) 


‘unit check’ 





End LCD 
operation — 





Command cycle steal for 
byte five of the command 
field. 


The third command 
locates the !D field on 
the ledger card. 





9-522 


CPU ‘adder carry’. 


Set: 
‘count end latch’. 


| Increment PCAR address 
plus 1. 


‘Cmmd req’ latch. 












Sense 
amps 1, 2 and 3 
off 


Yes 






CPU acknowledges 
command cycle steal 
request. 


Select PCAR LSR. 






Byte five of the 
command fields is on 
the DBO. 


Set command register 
‘locate ID’. 


Increment PCAR address 
plus 1. 


Valid 
command 


Yes 


‘LCD timing pulse’ 


‘Count req’ latch 


TNL SN34-0043 to SY34-0022-1 


















9-515 


9-515 


No 





‘Card skew check’ 
‘unit check’ 


9-522 


End LCD 
operation ' 


9-508 


No 


‘Invalid cmmd’ latch 


‘unit check’ 





9-514 


( End LCD operation 


9-522 



















CPU acknowledges 
count cycle request. 





Count cycle steal to 
/ decrement locate 1D 











Set: 



























count byte until it ‘count steal’ latch. | 9.514 
carries. 
| Select PCAR LSR. 
Do not increment PCAR 
address until count byte Decrement core (count 
carries. byte) 1. 
Inhibit LSR load’. 9-515 







Note. Loop should 
occur for the ¢ 
eighth through 
twelvth timing 

pulse. 






Count 
field equal 
FF 


6 





Yes 


CPU adder carry. 





Set: 








‘count end latch’ 9-514 
‘cemmd req’ latch. 9-515 
Increment PCAR address 
plus 1. 
Command cycle steal | 
for byte 7 of command 
field. 
The 4th command is CPU acknowledges 
either read locate or command cycle steal 
read eject. request. 
Select PCAR LSR. 
Byte 7 of the command 
field is on the DBO. 
Set command register 9-508 


latch, read locate, or 
read eject. 


‘Increment PCAR address 
plus 1. 


o 9-606 


5406 FETMM = (6/71) 9-605 


8, 9-606 


LCD ATTACHMENT~— Operations | TNL SN34-0043 to SY34-0022-1 5406 FETMM _—_ (6/71) 9-606 
Feed, Read ID, and Locate-Eject (Part 4 of 10) | 


1 





2 | Vv 3 
9-607 
9-605 
[S le 9-605 S se . 


Yes Valid 
command 











‘Odd-even’ 
trigger condition 


Odd | Even 


Nominal mark(s) 

sensed on ledger card | 9-504 
No set corresponding 
sense cell latches. 





‘Invalid cmmd’ latch 9-522 


‘unit check’ 
















Depending on the 
condition of sense cell 
latches 1 and 2, set 


Depending on the 9-518 
condition of sense cell 


latches 1 and 2, set 





‘LCD timing pulse’ 9-504 


















either the ‘8-bit’ latch, either the ‘2-bit’ latch, 
‘4-bit’ latch, or both ‘1-bit’ latch, or both 
(in the data assembler). (in the data assembler). 
The ledger card is twelve 
plus ratchet teeth past 
the pinch point of the Read locate Command Read eject 






in command 
register 


first feed rolls. 








Set odd-even trigger 
to even. 


‘Count 
stop’ latch 
set 


~ A nominal mark on the 
card would be sensed 
between the 12th and Yes 
13th timing pulse. 


‘Sense 
~ cell 3’ latch 
set 













The LCD attachment 
will read the 1D number 
from the ledger card into 
main storage, then 
depending on the 
command, locate the 
next available print line No ‘Line finder mark check’ | 9.522 
or eject the card from latch 

the LCD. 


Set ‘odd-even’ trigger 
to odd condition. 






9-518 










‘2nd 
miss’ latch 
set 


‘2nd 
miss’ latch 
set 





Yes 






f : Set: | 
Count ‘data req’ latch. 9-515 
stop’ latch 


set 







. ‘unit check’ 
No Yes Yes 





‘Odd-even’ trigger to 9-518 
‘odd condition. 





No 


End LCD operation 


Set: 
‘2nd miss’ latch. 





Reset: 
Set: ‘sense cell’ latches. 


‘1st miss’ latch. 


9-504 


















R : 
eset 9-504 


‘Ist miss’ latch. 





CPU acknowledges data 
cycle steal request. 


e 9-607 Set: 
‘data steal’ latch. 9-515 





‘Late 
mark’ latch 
set 


Select PDAR LSR. 


Gate an LCD data 
assembler onto DBI. 





Set: 
‘skip line’ latch. 


2 9-607 ao LE) 9-607 


Increment PDAR 
address 1. 








LD 9-606 G 9.606 @ S 9-608 | a 


Reset: 






This cycle steal 
decrements core 1 (byte 
OE of the 110E field). 


‘sense cell’ latches. 9-504 






Command 
in command 
register 





Read eject 





CPU acknowledges doc 


Decrement the LLAR end cycle steal request. 


Set: 
Read locate - | address 1. 


‘count req’ latch. 9-514 
Refer to the eject Set: 

command flow if the OE byte carries, it ‘doc end steal’ latch. | 9-514 

chart on page Set: indicates that the last 

9-624 for ending ‘condition’ latch. 9-515 printable line on the - Select LLAR LSR. 

operation of the ledger card was detected. 

read eject command. Decrement main storage 


(byte OE) 1. 


Count cycle steal to 
decrement read locate, 
or read eject count 
field until it carries. 





Decrement LLAR 


CPU acknowledges count address 1 


cycle steal request. 










Do not increment Sense amps 
1,2, and 3 


PCAR address until : 
Set: active 


count field carries. Zesmieeieeacehs sta —— 
i Yes 
Select PCAR LSR. eject operation . 


Decrement core (count 
byte) 1. 













Byte 
OE equal 
FF. 


No 


Set: 
‘LSR plus req’ latch. | 9-514 





‘Inhibit LSR load’. 9-515 





CPU ‘adder carry’. 





Set: 
‘count end’ latch 
‘last line’ latch. 
















Count 
field equal 
FF 


No 





This cycle steal 
increments the LLAR 
address 1 to address 
the OE byte of the 
110E field in main 
storage. 















CPU acknowledges LSR 
plus cycle steal request. 













‘2nd 
miss’ latch 
set 


CPU ‘adder carry’. Do not modify main No 


storage contents. 









Set: 
‘LSR plus steal’ latch. 
‘doc end req’ latch. 






Set: 
‘count end’ latch 
‘count stop’ latch 
‘read |D end’. 


9-514 
9-514 








Yes 


Select LLAR LSR. 





Increment LLAR address 
1. 


Set: 
‘loc line req’ latch. | 9-515 





a 2 e S oe02 9-606 a 


LCD ATTACHMENT- Operations 
Feed, Read ID, and Locate-Eject (Part 5 of 10) TNL SN34-0043 to SY34-0022-1 | 3 5406 FETMM = (6/71) 9-607 


FJ 9-608 


Cycle steal to 
decrement the 11 byte 
of the 110E field. 





_ CPU acknowledges 
locate line cycle steal 
request. 


When this byte carries, 





it is a signal to stop the 
LCD card feed unless 
last printable line or a 
late mark was detected. 





Set: 
‘loc line steal’ latch. 





Select LLAR LSR. 


Decrement main storage 
(byte 11) 1. 


‘Inhibit LSR load’. 


"LLAR = FF’ 
latch set 


CPU ‘adder carry’. 


Set: 
‘count end’ latch 
‘LLAR = FF’ latch. 





‘Last line’ 
latch set 


‘Skip line’ 
latch set 


om°o™ a 


LCD ATTACHMENT-— Operations | 
Feed, Read ID, and Locate-Eject (Part 6 of 10) 





















9-515 


9-515 


9-514 
9-520 


Yes 


S 9-607 





Reset: 
‘stop’ latch. 9-520 
‘Stop pulse’ 9-504 
Reset: . 
‘drive’ latch. 9-520 


Deactivate ‘LCD feed | 9.590 
clutch magnet’. 


Fire ‘hold busy SS’. 9-504 


Stop ledger card with 
next printable line 
positioned at the 
printer platen. 





End LCD read 
locate operation 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-609 


Wo 


LCD ATTACHMENT-— Operations TNL SN34-0043 to SY34-0022-1 5406 FETMM = _ (6/71) 9-610 
Feed, Read ID, and Locate-Eject (Part 7 of 10) 


1 





Starting position of clutch ratchet 


Zz 
oO 


Signal Name 


0 
= 
a) 
2 
Pay 
3 


LCD Selected !R Cycle 

CD Attach Reset 9-508 - 
LD Attach Busy 9-520 
Activate LCD Feed Clutch 
Timing Pulse Clock 3 to O 


Command Steal 


Count Steal 


Assume no line finder marks printed on the card (blank card), there- 


Locate Line Steal : : ‘ eos 
- fore locate line steals begin after the 2nd mark is detected missing. 


Data Steal 


Adder Carry 


Count End 





be Comma ne acne : Sense amp check Pae - Locate ID field Read ID and locate 
Card In Switch 9-507 | | | | | | | | | | | | | | | | | 


Card Alignment SS. 9-504 


16 | Card Alignment Latch 9-507 


od 


7 Drive Check SS 


Card Gate 9-507 
LCD 1/O Attention 


Clutch Motion Contact 





21 | Odd-Even Trigger 9-518 | | | | | | | | | | | leven! odd !eEven! oda | 


22 | Nominal mark would produce an output here | 





Sense Amp 1, 2, or 3 Output 


Sense Amp 1, 2, or 3 Latch 


Feed, Read 1D and Locate Operation 


am 
= 





PARA RRR Armature Stop 


Timing Pulse Clock 3 to 0 18 19 20 21 22. 23 24 25 26 27 38628 29 ~=30 31 32 


ee | lah | ol th! Col th I lot | oleh FE oth ! lioth 


No. Signal Name Diagra 


3 


9 
on 
N 
° 


LCD Attach Busy 


Activate LCD Feed Clutch 


Count Steal 


Data Steal 





Locate Line Steal 


O 


_ 
© 
Ol 
NO 
© 


ommand Count Stop 
Read 1D End 
Adder Carry 


Count End 


ol 
i) 
© 


top Latch (assume skip line 
latch was not set) 


Command Latches 9-508 Read ID and locate | 


‘Card In Switch 9-507 


12 


13 


Clutch Motion Contact 9-502 


Odd-Even Trigger 





Sense Amp 1, 2, or 3 Output 


~l 


Sense Amp 1, 2, or 3 Latches 


Document End Condition Latch 


| 


Hold Busy SS 


Feed, Read 1D and Locate Operation Stop ledger card with first print line positioned at the printer platen. A late mark 
was not detected so that the card stops in a normal manner (no extra line space). 


LCD ATTACHMENT- Operations 
Feed, Read ID, and Locate-Eject (Part 8 of 10) TNL SN34-0043 to SY34-0022-1 








5406 FETMM 


(6/71) 


9-611 


w 


O 


~ LCD ATTACHMENT-— Operations o TNL SN34-0043 to SY34-0022-1 5406 FETMM = (6/71) 9-612 


Feed, Read ID, and Locate-Eject (Part 9 of 10) 
1 





Starting position of clutch ratchet and armature 


2 
° 


Signal Name 


U0 
=. 
a 
o 
3 


LCD Selected 1R Cycle 9-204 


LCD Attach Reset 9-508 


9-520 
- a rs ‘ Reed ee} + ia x G Pare ce. eee 4 ey i Fs od a y eA a a oF 3" a rn . a : a C a * a PUR 
9-520 | | l | i | | i | | | | { l | | i 
Fi ee ee Leos “ i Se E ae ae Pr: ee an fl Hi 5 rar : Poa a = 5 y) errs s i z 


LD Attach Busy 









Activate LCD Feed Clutch 


Timing Pulse Clock 3 to 0 


QO 


ommand Steal 
Count Steal 9-514 


Data Steal 


> 


dder Carry 


ount End 


9-520 


| to to FUlUt!™CUWC(‘<‘<éi ;é‘iQSTOUSTS!UCOUEOUCOCSPCté< DW’ MUUTUDTCUPUCUCU | 
| Sense amp check | Locate ID field Read !D and eject | 


9-507 


~ Stop Latch 
2 Command Latches 
Card In Switch 
9-507 


14 Card Alignment SS 


9-507 


ard Alignment Latch 
Drive Check SS 


ard Gate 


9-507 lL od@edtoteopepeoeoteodotoot ould 


Gate down 


Ss err are t ' a 
9-502 >| 8 ms after line 4 | | | | | | | | | | | l 


cee me 


~ 
r 


CD 1/0 Attention 


I~ 


lutch Motion Contact 


20 


dd-Even Trigger ijt Nese NL th, | Even | Odd | Even | Odd | 


ie a ae " ae: eae 


NO 


1 


Sense Amp 1, 2, or 3 Output Nominal mark would produce an output here 


Sense Amp 1, 2, or 3 Latch 


Feed, read 1D and eject operation 


a 
~= 


> 


¥v 


2 
° 


Signal Name 
Timing Pulse Clock 3 to 0 


LCD Attach Busy -520 


O 
(Q 
3 


Activate LCD Feed Clutch 


- 
cn 
N 
° 


ount Steal 


QO 


| 


Data Steal 


ommand Count Stop 


O 


7 Read |D End 
Adder Carry 
ount End 


Document End Condition Latch 


top Latch 


wm 


-508 


Oo 


ommand Latches 


aah 


3 ard In Switch -507 


© 


-502 


© 


lutch Motion Contact 


Odd-Even Trigger 


Sense Amp 1, 2, or 3 Output 


ond 


7 Sense Amp 1, 2, or 3 Latches 


Feed, read ID, and eject operation 


LCD ATTACHMENT-— Operations 
Feed, Read ID, and Locate-Eject (Part 10 of 10) 





TNL SN34-0043 to SY34-0022-1 


Refer to eject operation for ending se- 
quence of this operation (page 9-623). 


5406 FETMM 


(6/71) 





9-613 


INDEX 


The index instruction moves the ledger card to the next sequential print 
line. If the bottom edge of the ledger card is above the lower sense station, 
LSR plus and document end cycle steal requests are made to decrement the 
OE byte of the 110E field. 

Before starting an index operation, the program should issue T!O instruc- 
tions to check for: not unit check, not LCD busy, not LSR busy, and not 
last printable line. | 

An LIO instruction is issued to: 


1. Load the LSR PCAR with the command field address. LSR PDAR is 
not used. 

2. LLAR must contain the address of the 110E field; the 110E field 
must not be reinitialized. 


Generate the command field 01 at the PCAR address. 


LCD ATTACHMENT — Operations 
Index (Part 1 of 3) 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-615 


> 


v 


= = = 


LCD ATTACHMENT-— Operations TNL SN34-0043 to SY34-0022-1 
Index (Part 2 of 3) 





2 





Armature Starting Position Stop position 


Signal Name 


LCD Selected I-R Cycle 


LCD Attachment Reset 9-508 


ol 
NS 
Oo 


CD Attachment Busy 9 


on 
N 
o 





Activate Feed Clutch 


Timing Pulse Clock 3 to 0 


Command Steal 






These cycle steal requests are made only if the bottom edge of the ledger card is past the 
lower read station. They decrement the last printable line byte (Byte OE of the 110E field). 






| LSR Plus and Doc End Cycle Steals 
Command Count Stop 


| Read ID End 





top Latch 9-520 


Card In Switch 






9 
a 
° 
SI 







Card Out Switch @9 This signal depends on the position of the ledger card in the LCD. Active 41 ratchet teeth past pinch point of first feed rolls. 


on 
© 
I 


Drive Check SS 


Hold Busy SS 


Assume ledger card stopped at the 1st print line positioned at the platen before 
index operation began. This index operation moved the ledger card to print line 2. 


16 


0 
o 
a 
3 


5406 FETMM 


(6/71) 


9-616 


eo 






I-R cycle . 









Start 1/O instruction. 
l-op and |-O cycles 

select the LCD through 
the printer logic. 

















‘LCD resets’. 9-508 
Set: 
‘pusy’ latch 9-520 
‘drive’ latch 9-520. 


‘Ist cmmd inlk’ latch. | 9-522 


Fire ‘drive check SS’. 9-504 
‘Activate LCD feed 9-520 
clutch’. 


‘cmimd req’. 9-515 





Command cycle steal 
for byte one of the 
command field. 


















CPU acknowledges 
command request. 





Set: 
‘cmmd steal’ latch. 9-515 
Select LSR PCAR. 


| Command byte on the 
DBO. 


Set command register 
‘index’. 


9-508 


Increment PCAR address. 





Valid 
command 


‘No 


‘Invalid cmmd check’ 


‘unit check’ 


< End LCD operation | 


LCD ATTACHMENT-— Operations 
Index (Part 3 of 3) 








Card motion begins. 


2 

















Clutch motion contact 
‘closes. 


| 9-502 





Reset: 


‘drive’ latch. 9-520 


Fire ‘hold busy SS’. 9-504 


‘LCD timing pulse’ 





Drive 
check SS time 
out 


~ Yes 










9-522 
Set: 


‘drive check’ 
‘unit check’. 


Reset: 
‘drive check intk’. 











Is sense | 
amp 1, 2, and 3 
active 


Tyes 9-514 


Set: 


‘LSR plus req’ latch. 








| CPU acknowledges LSR > 
plus cycle steal request. 












| Set: 


"LSR plus steal’ 9-514 
“doc end req’. 9-514 
Select PCAR LSR. 
Increment PCAR 19-510 





address 1. 


TNL SN34-0043 to SY34-0022-1 


CPU acknowledges doc 
end steal request. 


Set: 
‘doc end steal’ latch. | 9-514 | 


Select PCAR. 


; Decrement main storage 
si 1 (byte OE). 


Decrement PCAR 
address 1. 





No 


Byte OE 
carry 








CPU ‘adder carry’. 





Set: 
‘count end’ 
‘last line’ latch. 


9-514 
9-515 


: 


st 


End LCD operation End index operation 


5406 FETMM = (6/71) 9-617 


READ BACK AND EJECT 


- This operation is issued to eject the ledger card from the LCD and check 
that the last line finder mark (the one that is positioned at the printer platen 
when this instruction was issued) can be read by sense cell 4'as the ledger 
card is ejected from the LCD. 

After the ledger card feed starts, the command count byte is decremented 
with each LCD timing pulse. When the count field decrements to FF, the 
attachment samples sense cell 4 to see if a line finder mark was read at the 
9th line after LCD card feed started. If sense cell 4 did not sense a line 
finder mark, the read mark check latch is set, and the card feed is stopped. 
If sense cell 4 did read a mark, the card continues to eject from the LCD 
and into the stacker. 

Before starting a read back and eject operation, the program should issue 
TIO instructions to check for, not unit check, not LCD busy, and not LSR 
busy. 

An LIO instruction is issued to load the LSR PCAR with the address of 
the command field. LSRs PDAR and LLAR are not used for this instruc- 
tion. 

Generate the command field 02 08 at the PCAR address. 


LCD ATTACHMENT- Operations 
Read Mark and Eject (Part 1 of 3) 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-619 


LCD ATTACHMENT-—Operations TNL SN34-0043 to SY34-0022-1 5406 FETMM = (6/71) 9-620 
Read Mark and Eject (Part 2 of 3) 





2 


Signal Name Diagram ee 


No. 
TT eeesnceesteve [ose 









~ Command Steal 


1 | | 1 | = | j | i | j j Refer to eject operation for 


Count Steal _ending sequence (page 9-623). 






Command Count Stop 
Read !D End 


Stop Latch 


nd 
on 
° 
00 


Command Latches 


ard In Switch 


QO 


| 


13 


O 


ard Out Switch 


Drive Check SS 


© 
on. 
o 
nO 


Clutch Motion Contact 
dder Carry 


7 


QO 


ount End 


ense Amp 4.Output : : ; . g bas, e & : : 
Leading edge of card covers sense cell 4 sn.g— First line finder mark on the card and the one positioned at the platen when this instruction was issued. 


Sense Amp 4 Latch 


> 


Assume ledger card positioned with print line 1 positioned at the printer platen when this operation 
was started. A line finder mark printed at line 1 is read at sense cell 4, 9 line spaces later. 









































1 2 3 
7 Z QO © 
I-R cycl : Valid No Q No Count 

Start 1/O instruction. eee | a command ' . | ee 
!-op and |I-O cycles see tte | ees | | | ‘ 
select the LCD through LCD resets 9-508 z Yes 4 | eat -— | Yes 
the printer attachment | a eteoaeel Invalid cmmd’ latch 9-522 o , 
logic. Set: : : ‘unit check’ | i 





‘drive’ latch 9-520 CPU ‘adder carry’. 


‘stop’ latch 9-520 Card movement begins. | 
‘busy’ latch 9-520 

















Set: 

























‘Ist cmmd intk’ latch | 9-522 i a ‘count end’ latch. 9-515 
‘drive check intk’ 9-522 5 ‘LCD timing pulse’ 9-504 es 5 
latch. : Ee Increment PCAR 
| End LCD operation a address 1. 
| Fire ‘drive check SS’. —s_ |. 9-504 | : : 
| Activate ‘LCD feed’ clutch.| 9-520 tee Yes > 
: LCD timing | i 
‘Cmmd req’ latch. 9-514 ‘ pulse 
fo | Ves ‘Sense 
‘Drive “Yes amp 4’ latch 
: check SS’ timed set 
ie out 
a No 
| Command steal for byte , ; | 
J one of the command field. | i Reset ‘drive check f Set: 
E inik’ latch. 9-522 | i | ‘read mark check’ 
: “ ‘ latch 
CPU acknowledges : : ‘anit eheale: 
command cycle steal J : sees 
request. % 3 a 
Select PCAR LSR. ‘ Set: | Set: 4 
| | 7 ‘count req’. 9-514 | ‘drive check’ latch =| - 9-522 : 
/ Byte one of the com- A , : ‘unit check’. + 
mand field is on the DBO. 7 : 
| Set command register 9-508 ‘ 
‘read mark-eject’. 3 


Count cycle steal 
Increment PCAR 9-510 request to decrement 
address 1. count byte until it 
carries. 


See eject operation 


CPU acknowledges count flow chart for eject 


cycle steal request. 












portion of this 
instruction 


Set: 
‘count steal’. 





E Do not increment 
a PCAR address until 
count byte carries. 


19-514 


Select PCAR LSR. 









‘Decrement core 1. 


| ‘Inhibit LSR load’. | 9-515 


1 | (2 \ | (2) *) End LCD operation ( Bnd read ppe End LCD operation | 
| | ; eject operation — : | 


LCD ATTACHMENT -—Operations 
Read Mark and Eject (Part 3 of 3) TNL SN34-0043 to SY34-0022-1 5406 FETMM = (6/71) 9-621 


EJECT 


This operation is issued to eject the ledger card out of the LCD and into the 
stacker. This operation should only be used after an I/O check is detected. 

Before starting an eject operation, the program should issue TIO instruc- 
tions to check for not LCD busy and not LSR busy. 

An LIO instruction is issued to load the PCAR with a command field ad- 
dress. LSRs LLAR and PDAR are not used during this operation. 

Generate the command field 00 at the PCAR address. 


LCD ATTACHMENT- Operations 
Eject (Part 1 of 3) 


TNL SN34-0043 to SY34-0022-1 


5406 FETMM 


(6/71) 


9-623 


LCD ATTACHMENT-— Operations TNL SN34-0043 to SY34-0022-1 5406 FETMM (6/71) 9-624 
Eject (Part 2 of 3) : | 






















1 2 2 
Starting position of clutch ratchet and armature Armature stop Armature stop 
“ie for 8 inch card for 11 inch card 
a LCD Selected I-R eels | 9- 204 | 
LCD Attachment Reset | 9-508 | | | These signals are 
. . ) ' for the SIO eject Note. Crosshatched signals are for 11 inch ledger card. 
eornend Steal a command only. 
4 | Drive Check SS Q- 504 | | 45 ms F 
. (8 LCD Attachment Busy i 
TTT LLL ALLA LLL 
“EL Activate LCD Feed Clutch 9- 520 | \ 
Timing Pulse Clock 3 to O | t 
2 Clutch Motion Contact aan al ~< 8s i 
mI ; | Reset next LCD attachment 


—— Command Count Stop 9-515 | 
re 
b> ats Command Latches 


Read 1D End -- 


eis Latch 









eee Pulse 






| 14 | . Card. In Switch | 2 507 | ! | 
— CEE en Le ee ee eee ee uP 772) pero. _| ( 4 
Card Out Switch | 9- 507 | | On for any cara feat ~ | | | i | ( 
| Hold Busy SS | 9- 504 | | : r ee oe : t 155 ms 
LLILTTTLLT® 


For read 1D and eject, read back and eject, or 
lead all line finder marks operation, start here. 


b> 


Start 
issue SIO instruction to 
the LCD. SIO I-op and 
1-O cycles select the 
LCD through the printer 
attachment logic. 


a 
eae: 


See eae Oe 


emo GSES ome 


Command steal for 
command byte. 


rm, PEE an eater. 4 
oe pean esd Cae ee 


BSS. S ete v4 a 2 


oe 


"| 


a 
Bs 
ase 
: 
vo 
ae 
‘ 
G 
: 
, 
i 


LCD ATTACHMENT — Operations 
Eject (Part 3 of 3) 


| 


i-R cycle 


‘stop’ latch 9-520 
‘busy’ latch 9-520 
‘drive’ latch 9-520 
‘drive check inik’ latch} 9-522 
‘Ist cmmd inlk’ latch 9-522 
‘emmd req’ latch. 9-515 


| Fire ‘drive check SS’. 9-504 


‘Activate LCD feed 9-520 
| clutch’. 


‘LCD resets. 9-508 


















CPU acknowledges 
command cycle steal 
request. 


Select PCAR LSR. 









Command byte is on 
the DBO. 


Set command register 
‘eject’. 


9-508 





Increment PCAR 
adaress 1. 








2 
Enter at this : Valid No 
point for eject e command 
ending operation | 9-522 
for other com- : : 
mands. ; Yes 


‘Invalid cmmd’ latch 


‘unit check’ 


















Start card feeding in 
the LCD. 





drive latch was set. 


9-504 
A timing pulse should ‘LCD timing pulse’ | End LCD operation 
occur 30 ms after the 





‘Drive 
check SS’ timed 
out 


‘Drive check’ latch 
‘unit check’ 





Reset: 
‘drive check intk’. 
latch. 


Continue to feed the 
ledger card through the 
LCD until the bottom 


edge of the ledger card 
breaks the card out 
switch. 


Top edge of ledger card 
makes the card out switch | 
when it is between 41 

and 42 ratchet teeth 
beyond the pinch point 





| of the first feed rolls. 
This occurs for both 8 
1 inch and 11 inch card 
| lengths. 





Ca} & , End LCD operation 


TNL SN34-0043 to SY34-0022-1 





End eject operation 


Bottom edge of ledger 
card leaves the pinch 
point of the first feed 
rolls and causes the card 
in switch to transfer 
(break). 


This occurs at different 
| times for the 8 inch and 
11 inch card lengths. 


| For the 8 inch card, the 
top edge of the ledger 

| card is 48 to 49 ratchet 
teeth beyond the pinch 
point of the first feed 
rolls; for an 11 inch card, 
66 to 67 teeth. 


Continue to feed the 
ledger card until the 
card out switch breaks. 








Reset: 
‘stop’ latch. 





‘LCD timing pulse’ . 


‘Stop pulse’. 








Reset: 
‘drive’ latch. 





Fire ‘hold busy SS’. 





Deactivate ‘LCD feed 
clutch magnet’. 


5406 FETMM = (6/71) 





9-504 


9-504 


9-520 
9-504 


9-520 


9-625 


LCD ATTACHMENT-— Operations 
Read All Line Finder Marks 


READ ALL LINE FINDER MARKS 


This is a diagnostic operation to read each line finder mark on the ledger 
card at two different sense stations. Each sense cell indicates if a line finder 
mark was read and at what line from the ledger card by setting bits in main 
storage. Each sense cell has specific bit assignments in order that the data 
read from the first sense station may later be compared to the data read by 
the second sense station. The system program performs the compare opera- 
tion. | 

Line finder marks are first read by sense cell 3, located in the lower read 
station of the LCD. Twenty-nine line spaces later, the same mark is read at 
sense cell 4, located in the upper read station. Sense cell 4 does not respond 
to line finder marks that produce a weak output. Therefore, after the data 
is in main storage and the program has compared the data (bits) read by 
both stations, weak output producing line finder marks can be detected. 


Data Field 


The illustration on this page shows how line finder marks, read from the 
ledger card during a read all line finder marks instruction, are indicated in 
main storage. | 

Bit positions zero through 3 will be either an F (hexadecimal) or a 4 
(hexadecimal). Bit positions 4 through 7, when set to a one bit, indicate 
the presence of line finder marks on the ledger card. 

The numbers shown in bit positions 4 through 7 correspond to line num- 


bers on the ledger card. Line 1 is at the top of the card, line 56 Is at the bot- 


tom. Numbers within parentheses represent lines read at sense cell 3, num- 
bers not in parentheses are lines read at sense cell 4. 

Each byte can represent from one to 4 lines read from the ledger card 
depending on the position of the ledger card within the LCD at the time 
the byte was read. Example, PDAR address 0200 represents lines 1 and 2 
read from the ledger card by sense cell 3. PDAR address 020E shows lines 
29 and 30 read by sense cell 3 and line 1 read by sense cell 4. PDAR ad- 
dress O20F shows lines 31 and 32 read by sense cell 3 and lines 2 and 3 


read by sense cell 4. PDAR address 022A shows line 56 read by sense cell 4. 


TNL SN34-0043 to SY34-0022-1 


Bit positions zero through 3 will be an F (hexadecimal) for each byte that 
has at least one line finder mark in the lines indicated in bits 4 through 7, if 
no line finder marks are read, bits zero through 3 will be a 4 (hexadecimal). 
For those lines that represent lines read by sense cells 3 and 4, any line 
finder mark sensed by either sense cell, will cause bits 0 through 3 to be an 
F (hexadecimal). 

The maximum length card is always read (56 lines). This requires 43 bytes 
of storage to contain the data from both sense cells. (Two lines per byte = 
28 bytes, plus 29 lines separation between sense stations = 15 bytes for a 
total of 43 bytes.) 


Read All Line Finder Marks Operation 


This instruction is similar in operation to a feed, read ID, and eject com- 
mand and therefore data flow diagrams and timing charts are not shown. 
Only the exceptions will be explained. 

The SIO control code for this instruction must be XXXXXXX1 to set 
the scan latch, shown on page 9-515. The scan latch degates sense cell 1 
and 2 into the data assembler and gates sense cell 3 and 4 instead. 

The read ID, and eject command count byte equals 55 (hexadecimal). 
This is to prevent setting the count end latch after reading the 20 line ID 
number as in the feed, read ID, and eject operation. By not setting the 
count end latch, the condition latch is not set to allow LSR plus and docu- 
ment end cycle steal requests. 


PDAR (start) 


[e200 


ols {213} 4|5| 6] 7 
8 }4{2ji{ela{2} 1 


0200 
01 
02 
03 
04 
05 
06 
07 
08 
09 
OA 
OB 
Oc 
OD 
OE 
OF 
10 
1 
12 

13 
14 
0215 


Each 
byte 
can be 
either 
an F 
(hexa- 
decimal) 
or 4 
(hexa- 
decimal) 


BE (30) 1 





Bit 
position 


Bit 
value 


0216 
17 
18 
19 
1A 
1B 
iC 
1D 
1E 
1F 
20 
21 
22 
23 
24 
25 
26 


27 


28 
29 
022A 





5406 FETMM = (6/71) 9-626 


(51)22 (52)23 
(53)24 (54)25 


byte 
can be 
either 
an F 
(hexa- 
decimal) 
or 4 
(hexa- 
decimal) 





PDAR address when the 
operation is complete 


BR2507 


Section 10. Data Recorder Attachment 


This section of the 5406 FETMM contains the theory and maintenance dia- 
grams for the 5496 Data Recorder attachment. It consists of three chapters 
as follows: 


Chapter 1. Introduction 
Chapter 2. Functional Units 
Chapter 3. Operations 


DATA RECORDER ATTACHMENT-—Contents 


Contents 


Chapter 1. Introduction 10-101 


Introduction to Data Recorder and Attachment 10-101 
96 Column Card and Character Set 10-102 

Offline Operation and Memory Organization 10-103 
Flag Bits 10-104 | 

Program Control and Data Recording 10-105 

Online Operation 10-107 

5496 Read Operation (2 Parts) 10-108, 10-109 
5496 Punch Operation (2 Parts) 10-110, 10-111 
Load I/O Instruction Format 10-113 

Test I/O Instruction Format 10-114 

Advance Program Level Instruction Format 10-115 
Sense I/O Instruction Format 10-116 

Start I/O Instruction Format 10-117 

Data Flow 10-118 


Chapter 2. Functional Units 10-201 


Introduction to Functional Units 10-201 

Board Layout 10-202 

Interface Lines 10-203 

Initial Selection (2 Parts) 10-204, 10-205 

Registers (2 Parts) 10-206, 10-207 

Cycle Steal and LSR Select Controls (2 Parts) 10-208, 10-209 — 
Error Conditions 10-210 


Chapter 3. Operations 10-301 


Introduction to Operations 10-301 
Load I/O Instruction Flowchart 10-302 
Load I/O Instruction Timing Chart 10-303 


Test I/O or Advance Program Level Instruction Flowchart 10-304 


Test I/O or Advance Program Level Instruction Timing Chart 10-305 
Sense I/O Instruction Flowchart 10-306 

Sense I/O Instruction Timing Chart 10-307 

Read Operation Flowchart (2 Parts) 10-308, 10-309 

Read Operation Timing Chart 10-311 | 

Punch Operation Flowchart (2 Parts) 10-312, 10-313 

Punch Operation Timing Chart 10-315 

Diagnostic Data Operation 10-316 

Diagnostic Cycle Steal Operation 10-317 


5406 FETMM 


(6/70) 


10-1 


Chapter 1. Introduction 


DATA RECORDER ATTACHMENT 


The IBM 5496 Data Recorder attachment provides a means for the Model 6 
to use the 5496 Data Recorder as an input-output device for reading and 
punching the System/3 card. The attachment provides the interface between 
the delay line memory in the data recorder and main storage in the 5406 
Processing Unit. Information transferred between these two storage devices 
is controlled by the attachment. 

The attachment circuitry is MST-1 logic, physically located on gate A, 
board B1 in the 5406 Processing Unit. The interface between the system 
and the data recorder is a cable consisting of data and control lines. 

The communications path between the central processing unit and the 
data recorder attachment is through the I/O channel. Using this channel, 
data and control information is transferred from the central processing unit 
to the attachment and data (from the delay line storage in the data recor- 
der) is transferred from the attachment to the central processing unit. Also 
through the I/O channel, status is sent to the central processing unit under 
control of stored programmed instructions. 

During the process of exchanging information, the attachment and 
central processing unit operate together in multiplexer mode. This means 
that the information transfer takes place between central processing unit 
cycles on a priority basis with other devices. 

By means of a fixed cycle steal priority, |/O cycles may be interleaved 
between any two central processing unit cycles to fetch or store data to 
and from the attachment. 

















Control Out 












rs : Data 5496 
Attachment Recorder 


Control In 


e@eeece i 
oees 
eeeeos 
eoeee 
e@oeee 
eecee 
eeoee 
eoeee 
eoeee 
eeee 






eeeveoeoe cove ece ees 
eseeetevesecesvee 


SE Other 
seeeees Attachments 






eoeve 

@eees 
oove 

eeeee 
eeee 

eeeee 
e 


BRO791 


DATA RECORDER ATTACHMENT-~-Introduction 
Introduction to Data Recorder and Attachment 


Local Storage Register 


The local storage register in the central processing unit assigned to the data 
recorder attachment is the data recorder address register (DRAR). It must 
contain the leftmost or starting address of the data field in main storage 
when issuing a read or punch command. 


Priority Request 


The data recorder attachment uses the cycle steal method of communicating 
with main storage in the central processing unit. It is assigned priority clock 
two, request bit line four. This is twelfth in the order of priorities from 
highest to lowest. The select lines used by the attachment to request a cycle 
steal are lines five and seven. 


DATA RECORDER 


The IBM 5496 Model 1 Data Recorder with the online read/punch feature 
is used for the System/3 Model 6. With this feature installed, the model 6 
can use the data recorder to read and punch the System/3 card. The data 
recorder can also be operated offline as a normal data recorder. 





BRO792 


5406 FETMM (2/71) 10-101 


DATA RECORDER ATTACHMENT -—Introduction 
96 Column Card and Character Set 


96 COLUMN CARD 


The 96 column card is divided into two sections. The upper section of the 
card is the print area and the lower section is the punch area. The lower 
section (punch area) is divided into three horizontal sections called tiers. 
Each tier contains 32 vertical groups of six punch positions. Each group of 
six punch positions is a card column. The punch positions are B, A, 8, 4, 
2, and 1 from the top of the tier to the bottom. 

The 96 card columns are arranged 32 columns in each tier as follows: 


Tier 1 Columns 1-32 
Tier 2 Columns 33-64 
Tier 3. Columns 65-96 


punched in it. 


Print Line 1 


123 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 


N 7 
= 7 
NX Pa 


/ 
\ 


“ zs 7 | . Print Line 1 
aN 


NX 4 12 3 4 § 6 7 68 8 10 Wt 12 13 14 15 16 17 1B 19 2 21 22 23 24 25 26 27 26 29 30 3! 32 


Print Line 2 


Print Area 33 34 35 36 37 38 39 40 4) 42 43 44 45 46 47 48 49 50 51 52 53 54.55 56 57 SB 59 GO 61 62 63 64 


i 


Print Line 3 


65 66 67 68 69 70 7I 72 73 74 75 76 77 78 79 BO 8! 82 83 84 85 86 B7 S&B B9 90 9! 92 93 94 95 96 


B BO 
A A 
8 8 Tier 1 
4 + 
2 2 
= 12 3 5 6 7 8 9 $0 f] t2 13 14 15 16 17 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
A A 
8 8 Tier 2: 
Punch Area : . ier 
° 2 
- 33 24 35 36 37 3X 39 40 41 42 43 44 45 46 47 48 49 50 5! 52 53 54 55 56 57 58 59 6O Gi 62 63 64 
4 i \. 
2 we 4 Tier 3 
2 2 
\ 


“ 65 66 GY 68 69 70 TI 72 73 74 75 76 77 76 79 BO BI B62 83 84 85 BE B7 8B G9 90 91 92 93 94 95 96 





BRO793 


5406 FETMM = (6/70) 10-102 


All of the information contained on one card (from column 1 through CHARACTER SET 
column 96) is called a record, regardless of how many characters are 


Any one of 64 different combinations of the six punch positions (six-bit 
card code) may be punched in a card column. The print area has 128 print 
positions numbered from 1 to 128; 96 of these correspond with the num- 
bers in the punch area. Print positions 97 to 128 are available for use by 
other System/3 devices. 









Alphabetic Characters 


als|ojojelelalu]i [sy] ke m|njolrfaals|rjulviw]x|y|z 







Punch 
Positions 





Positions 


BRO795 


Special Characters 


3 tel dtd dst Py doh tap ee PP deel Le | 
. errr rss rss; 111111 lllttit 
PaAfalalajafayal | | | tT tT fafafatalatajay | ott Lt 


Punch 
Positions 





eee Ree eRe 


Note: A blank character is represented by a column containing no 
punches. There is no printed graphic representation of the blank 

character. . 
BRO796 


OFFLINE OPERATION 


The two offline operations of the 5496 are data recording and verifying. 
The data recording operation consists of data entry by the operator, punch- 
ing, and optional printing. The verifying operation consists of reading a 
previously punched card and comparing the data with corresponding (but 
identical if no errors have occurred) data being reentered by the operator. 
The 5496 has a delay line buffer (memory) that is used in both data 
recording and verifying operations. For data recording, the buffer: 


1. Allows the operator to store up to four programs for selection and 
use during data entry. 

2. Allows the operator to enter a complete record (96 columns), 
correcting any detected errors as they are made before the card 
is punched. | 

3. Allows complete overlap of: 


a. Operator entry for card 3 
b. Punching of card 2 
c. Printing of card 1 


For verifying, the delay line allows the characters from a previously 
punched card to be compared with corresponding characters as they are 
being reentered by the operator. First, the previously punched card is 
completely read into the delay line. Then, as characters are reentered they 
are compared to the corresponding characters on the delay line. If a non- 


compare occurs, the keyboard is locked and the error indicator is turned on. 


DATA RECORDER ATTACHMENT-Introduction 
Offline Operation and Memory Organization 





MEMORY ORGANIZATION 


As shown below, the delay line is divided into 96 words (corresponding to 
the 96 card columns) numbered 1 through 96. Each word is made up of 
seven Characters: P1, P2, P4, and P3, corresponding to the four levels of 
stored program; KBD, the area into which input data from the keyboard 
is entered; and PU and PR, the respective areas from which punching and 
printing occur. 


Each character on the delay line is made up of eight bits: bit 1, 2, 4, 8, A, 
B, C, and D. The character is sent to the delay line bit-by-bit and is continu- 
ously regenerated through the line, through an 8-bit register (the A register) 
and back onto the delay line until the data is replaced with new data or until 
machine power ts interrupted. Bits are shifted through the line at one micro- 
second intervals. Each interval is called a bit time. The character times are 
eight microseconds and the words are 56 microseconds long. The memory 
cycle for a 96 word record is 5376 data bits. The eight bits in the A register 
are a part of the 53/76-bit storage capacity. 


A Register 


Delay Line 





96 words 


>> 5376 usec 
Sato ee 





Word 
56 usec 


WORD 
pee | eu | cop} ro | re] ra] pt | ora/card Column (96 Tota) 





Character 
8 usec 


CHARACTER 
olctelalsfaf2]a Sai 
es: BIT 
8 Bits/Character 


1 usec 


BRO797 


5406 FETMM 


(2/71) 


10-103 


DATA RECORDER ATTACHMENT-Introduction 5406 FETMM ss ((2/71) 10-104 
Flag Bits 


FLAG BITS , Previous Word 


The figure to the right shows all the 56 bits contained in a word in memory. 





1 
The four basic functions of read, data entry, punch, and print are controlled 2 
by reserved bit locations, called flag bits, written in the delay line memory. 4 | pian’ 
A flag bit is a bit in memory defined by a particular bit time in a particu- P47 8 
lar character of a word. (P3 bit time ‘D’ is the flag bit for the KBD area.) 2 | 
Before performing one of the functions, a flag bit for that function is —— | 
. P ts di | Wh ts eealvaniest sce C Read and Right Adjust Flag _~ Tier-1; Transport Counter Control (Col 1 - Col 23) 
written into each word in memory. en the con ro ogic ‘or a particular D Delay and Feed Check Flag Tier-2: Read Counter Control (Col 33 - Col 42) 
function calls for that function, a search for the first flag is initiated, 1 Tier-3; 100 Ms Delay Control! (Col 65 - Col 83), and Motor Stop 
starting in word 1 (column 1). When the first flag is found, that column is 2 Feed Start Control (Col 84 - Col 96) 
Operated on and its flag bit is erased so that when the search for the next 4 Program 2 
available column is started, the next word will contain the first flag bit. P2 = pROGAn 
When all flags for the function are erased, the operation is complete. B | See ees 
Due to the physical layout of the 96 column card, reading, punching, and C Print Flag (see note) FUNCTION CHAR. WHERE IN ELD 
printing require that one column from each of the three punch tiers (three D Punch Flag 
card columns: 1, 33, 65; 2, 34, 66; etc.) must be operated on during each 1 | END OF FIELD | - (Hyphen) LAST COL 
search cycle. Therefore, two additional first flag scans of the delay line are : 5 r ee oe 0 (Zero) eee a. 
a ee : : : rogram 4 or 
started beginning in words 33 and oS respectively, to permit operating on o4 _8 6-bit Auxiliary Duplicating | LOWER SHIFT ANY COL 
all three tiers at the time the card is in a position to be read, punched, or A Data NUMERIC SHIFT ANY COL 
printed. B { SELF CHECK FLD 
C VER RIGHT ADJUST FIRST COL 
D 
1 
mote ; Note. For on-line operation, this 
3 Program 3 will be the read flag. 
P3 A 
B 
C Verify Error Flag 
D Keyboard Flag 
1 
2 
. Data 
Kbd A | 
B 
GC Print Suppress Flag 
D 
1 
2 
2 Data 
Pu 8 
A 
B 
CG Print Suppress Flag 
D 
1 
2 
4 -Data 
Pr 8 
A 
B 
C Print Suppress Flag 
D Not Used 
Next Word 


BRO798A 


PROGRAM CONTROL 


The 5496 Data Recorder can operate with or without program control. 
To operate with program control, the program coding is first punched into 
a card to define areas of data fields in the card. The program card is then 
read into one of the four program areas on the delay line. Program level 1 
(area P1) is the home program (machine operation is returned to this pro- 
gram level when the program switch on the operator panel is first turned 
on). Only one program level is effective at a time, but program levels can 
be changed at any time during the entry of a record. During data entry, 
the active program level defines the length and type of data fields to be 
entered for the record. Data fields are defined as manual, auto skip, and 
auto duplicate. Consecutive columns that must be keyed by the operator 
constitute a manual field. Consecutive columns in the card that are to be 
skipped are auto skip fields. Consecutive columns that are to receive the 
Same data in every card are auto duplicate fields. 


DATA RECORDING 


Data can be either key-entered into the KBD area of memory or duplicated 
from the preceding record by transferring the appropriate data from the PU 
area in memory. This entry of data is not synchronous to card movement 
and punching. Data entry is controlled only by the rate of keying and pro- 
gram controls. A column indicator shows the next column in memory which 
will receive data. This indicator has no timing relationship to punching or 
printing. When 96 columns of data have been entered, a blank card (skip or 
release causes entry of blanks) is fed from the hopper, registered, and the 
entered data is transferred from the KBD area in memory to the PU area in 
memory. The card is incremented through the punch station at a rate of 
20 increments/second (effective rate of 60 columns per second), punching 
as required while the card is stopped after each increment. After the card 
has moved 32 increments during punching, a printing operation begins if the 
- print switch was on when keying occurred for the record. If the print switch 
was on, print flags are written into memory and the record is transferred 
from the PU area to the PR area in storage. 

The printer consists of a continuously running wheel that has three sets 
of 63 characters engraved on the periphery; the 64th character is a space 
and is blank on the print wheel. The figure shows how the print wheel is 
mounted above the card and the three print hammers are mounted below 
the card path. The print station is 33 columns from the punch station. 
When column 32 is being punched in the card, column 0 is at the print 
station. After the card clears the punch station, another card can be fed 
from the hopper and punching can start on this card. This means that print- 
ing of record 1, punching of record 2, and data entry for record 3 can occur 
simultaneously. | 

A card is read into memory by pressing the read key. This action moves 
the top card in the hopper into the transport to be read. Data is read from 
the card into the PU area in storage enabling that card to be remade. All or 
portions of the card can be duplicated in the next record. 

To synchronize the card movement with the circuit operations, certain 
controls are used. A card sensor control detects that a card has moved from 


DATA RECORDER ATTACHMENT-—Introduction 
Program Control and Data Recording 


Print Line 1 
Print Line 2 


Print Line 3—_,. 


Print Wheel 


Print Ribbon 





Print Hammers 


BRO799 


the hopper to the transport rolls. A magnetic emitter driven with the trans- 
port mechanics provides three transport control pulses. ‘Transport dwell’ 
designates the start of dwell time, ‘punch on’ turns the punches on, and 
‘punch off’ turns the punches off. These pulses also synchronize the control 
logic with card location for reading, punching, and printing. 

There are circuits to check for misfeed, hopper jam, or transport jam con- 
ditions which are indicated by a feed check light on the operator panel. 
The operator panel also contains the column indicator which: 


1. Indicates to the operator the next card data column to be acted 
upon, and 
2. ls used in conjunction with the CE panel to display the bits of any 


storage position. The CE panel is located on the end of the electronics 
gate in the 5496. 


Details of the 5496 Data Recorder Model 1 are contained in the following 
manuals: 


/BM 5496 Data Recorder Operator’s Guide, Order No. GA21-9086 

IBM 5496 Data Recorder Field Engineering Theory of Operations Manual, 
Order No. SY31-0220 

IBM 5496 Data Recorder Field Engineering Maintenance Diagrams Manual, 
Order No. SY31-0221 

IBM 5496 Data Recorder Field Engineering Maintenance Manual, 
Order No. SY31-0219 


5406 FETMM 


(6/70) 


10-105 


ONLINE OPERATION be read or punched with each operation initiated by the CPU. Any pro- 
grams previously entered into the 5496 delay line as a result of an offline 


Online and offline control of the data recorder is determined by the setting 
operation are not effective when the 5496 is operated as an online device. 


of the ‘DATA RCRDR’ switch on the CPU operator console. Setting the 
DATA RCRDR switch to ON LINE places the data recorder under control 
of the CPU program if the 5496 is otherwise ready. Conditions of the 5496 


that prevent program operation are: EBCDIC 5496 Card Code Character EBCDIC 5496 Card Code Character 
Stacker full Binary Bit Position Punch Positions Graphic Binary Bit Position Punch Positions Graphic 
Hopper empty 8 42 1 
Hopper jam 


Transport jam 
Punch/verify switch on VERIFY 
Auto record release switch set to OFF 


(period) 


ee ee 
>PD>>D> YY yD 


co 0 CO © © W/O 0 © © WO 0 


While under program control, all the keyboard keys on the 5496 are held | 
restored to prevent accidental operator intervention. (The release key is 
unlocked in the event of a feed error or a card jam to permit the operator 
to clear the trouble from the machine.) The online/offline switch can be 
set to OFF LINE at any time. However, an operation in progress at the time 
of setting the switch is completed and the 5496 becomes an offline device 
after the successful completion of this operation. 

The 5496, when used as an online printing punch and card reader, is 
attached to the model 6 through a cable of 25 feet maximum length. This 
cable contains the signal lines necessary for connecting the 5496 to the 
data recorder attachment in the processing unit. The data recorder attach- 
ment controls operations of the 5496 which are initiated by the processor 
program. Information is transferred to and from processor storage by using 
the cycle steal capabilities of the CPU. The delay line buffer in the 5496 
allows the CPU to overlap data recorder operations with operations of other 
1/O devices controlled by the system. 

The two online functions of the 5496 are card reading and card punching. 
Both functions, however, cannot be performed on the same card in one 
operation. (A card punched by the data recorder on command from the 
CPU program must be reinserted in the card hopper to be read under pro- 
gram control.) In a card read operation, the CPU program issues a start 
|/O instruction which causes the 5496 to read data from a card into the 
delay line storage. The data is transferred from the delay line in the 5496 
to CPU storage with 96 cycle steal cycles. This data in 6-bit card code is 
translated into 8-bit EBCDIC by a translator on the data bus in (DBI) with 
each transfer of a data character to the CPU. The character codes figure on 
this page shows both the card code and EBCDIC for the 64 character set 
used by the 5496. 

In a card punch operation, the data is transferred from CPU storage to 
the 5496 delay line via cycle steal cycles until an entire record has been | 
transferred (96 cycle steals). This data from the CPU is translated from 
8-bit EBCDIC to 6-bit card code by a translator on data bus out (DBO) 
with each transfer of a data character to the data recorder. When the 96 
data characters have been transferred, the data recorder circuits feed the 
top card from the hopper into the punch station and punch the data into 
the card. Printing of punched data is under control of the print switch loca- 
ted on the operator panel of the 5496 Data Recorder. An entire card must 


(logical OR) 


DDPPP PLY dy>D 


Jeceveenen fe Se nf temtene> 


(logical NOT) 
(dash) 


nnonnmnnnwavnanwwoawowawo wo 


B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 
B 


(underscore) 


rPrrSrTrrryYr 
Co 00 & CO 0} © 0 © 0 





00 


0 
1 

0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 
0 


Oaeeeea aloe an nnn onl coerced cl0o CC OOO OlN 
Om ma aeenlODdooo-olonmas-- a a3]/00 COCO Ow 
Sakae Gla Gat aoa G Ole aa as lao a I 
Om a2 320 0/22 220 00/0 2H a2 aso ol] -a---00 0lH 
O-2002 3/2 20 0-0 0lOo=--002 3/200 o0lo 
OC-O0O-0=0;2 020-0 32/02- 02 0-c0;7-0-0-00N 
BYNUM DHHBDGTOOHOT HGH HG HGTAAAAAAO 

ommuawrinmuounowon0T7tTM TCNQ WypimamMoawypo 


no punches blank 
(space) 





Note: A blank character is represented by a column 
containing no punches. There is no printed graphic 
representation of the blank character. 


BRO800 


0 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 


- 2 eo ee owner mf[nomrnrannrnnlCQOOOOdodoaoood0o0o0nddcaoaooo0on°94enaotn 


le risagh fogs thie sake alg SEs Bt Ne) tae, ae ee Se ee os ee he tlie SEs pe ek RR a ora oe hake Soe fod 2 
Berean annaslOoODDDOOOO Of2 a2 a2 35a aaa nrlodDCCCOOO O|w 
OC=-=2COCDC0O0OOl]3=0DOC0OO|=2 = cD0OC0OO0OOj==cCOdOCCOOO|A 
C0OO=23245200 0]l00222450 0lOo0-33=-c0o|J00s==a=s=sa co Ola 
COO]==00-=0])002-=00=slo0 A= a= 0 OA 20J00-sa=00-=0ln 
O=-0=0-003/2- 020202 0/2 0202 020 42/2 0203200 4] 
“AmMmamMATAMMAAMmMMMmMMmMmMmMmMooooOoODUDUmWMNANAAAAOAOAOA 


COAMAN DAA WN Hf(OWONAOTAWNHIOAN A A PWN AOWMONDORWHND = 





BRO800 


DATA RECORDER ATTACHMENT- Introduction | 
Online Operation 5406 FETMM (2/71) 10-107 


DATA RECORDER ATTACHMENT~—Introduction 
5496 Read Operation (Part 1 of 2) 


(from attachment) 


1/O Read Command die OP 
1/O Switch A FL 
Transport Jam 
Read complete jor fl 

KHO31 


Colm 96 


PU BTC 
|/O Read Cycle Flag 







A Register 
By-pass 





x—x—xX—X— XK 


A Register 


Entry Register 





(Causes a card to feed from hopper, read card and store on delay line) 


1/O Read Sync 


PR FL 

BT 1 A | 

Colm 96 

(not) 1/O read data : 
KLO31 

BTC 

PR 


1/O read data 


PU BTC 
Colm 96 


To DBI In Attachment 


(1/0 Compare Command) 


Bus Out from Attachment DBO 


Read Complete 






Read Transfer 
1/O Switch FL 


PR Time 








P2 1/O Read Flag 
BT4 A FL 
A Reg A Bit 
PR Time 
(flag bit) “KLO41 
Read Cycle Latch 
(from attachment) 
5. | P2 BTC 
BT1 
KBD 


Entry 
Register 












!/O Command Reset 


5406 FETMM ss (2/71) 10-108 


PU To KBD Xfer 
(transfer takes one pass of delay line 
and writes flag bits in P2 BTC) 


1/O operation complete 


(1/O read 
|/O Read Dat d 
KBD Time |, 2 aaa 
BT? FL | 
|1/O Reset 
or KLO41 
A Flag Erase 
A 
A Register 
Compare 
A 1/O Read Not Compare 





lf card stacks with no jam detection error, 


data recorder sends ‘!/O command reset.’ 


5496 READ OPERATION When the ‘read data ready’ line (refer to a ) is active, the user also 
has the responsibility to bring up the ‘read cycle’ line (refer to ei ) to 
reset the ‘I/O read data’ latch. If the ‘read cycle’ line is active before the 
next PR BTC time, the ‘I/O read sync’ latch is not reset and therefore the 


To use the 5496 Data Recorder as an input-output device for the model 6 
system, perform the following steps: 


@ Set the following switches on the data recorder (see figure on this page): next data transfer occurs 56 psec after the first data transfer. If the ‘read 
1. Program switch to OFF. _ cycle’ line is active after PR BTC, a minimum delay of approximately 5.4 
2. Verify switch to PUNCH. msec occurs. There is no restriction on the attachment relevant to the mini- 
3. Auto record release switch to AUTO. . mum data transfer rate. The data transfer continues until the ‘I/O read flag’ 
| latch is set at Col 96 time by the flag in Col 96 P2 BTC. With the ‘I/O read 
—@ On the central processing unit console, position the data recorder online flag’ latch set, Col 96 PU will reset the ‘I/O read cycle’ latch and the ‘I/O 


switch to ON LINE. This activates the line ‘I/O switch’ in the data recor- 
der attachment which is the major control line in the attachment. In 

the data recorder, this line performs a record erase and holds this line 
active which locks out all of the keys and most of the switches on the 
operator console (of the data recorder). The record erase is inhibited 
during a feed check condition to allow operator recovery. If no error 
condition exists in the 5496, the ‘I/O ready’ line is activated. 


read sync’ latch. This signal is also sent to the attachment as ‘operation 
complete’ (refer to a ). After the last column is read, the card con- 
tinues to pass through the transport and a check is made to insure that the 
card cleared the read station. If the card clears the read station, a signal, 
‘command reset’, is sent to the attachment (refer to ). 

The attachment can issue another I/O read command after receiving 
‘command reset’ from the 5496. 

To read prepunched data cards, the operator loads the cards in the 5496 
hopper and sets up the machine as stated above. The data recorder attach- 


ment issues the I/O read command signal. This sets the ‘read op’ latch and SOISTON ACICa TOF 





a normal read operation is initiated. (Refer to cE .) PROG ea Jee Sadie SEG Se euen wERIES 

The data from the cards is read into the PU section of delay line memory. ' 2 SK/DUP REC REL PROG -.LOAD CORRECT ERASE PRINT VERIFY REPCH 
Read flags P1, BT-C are used for this transfer. At the completion of the 3 . ON 
read operation the signal ‘read complete’ sets the ‘I/O read transfer’ latch. ERROR f POWER 
This latch is on for one memory cycle, and transfers the data in the PU STKR FL | OFF 
section to the KBD section (the KBD section is used for data transfer and EDCHK OFF OFF OFF OFF OFF OFF OFF PUNCH OFF 





the punch section is used with the compare command) of memory without 
erasing the PU section. It also writes a flag bit in P2 BTC of every section 

of memory. At the end of the read transfer cycle (5.4 ms), the ‘I/O read 
transfer’ latch is reset. With the ‘I/O read cycle’ latch set, the ‘I/O read sync’ 
latch can be set at Col 96, PR, BT1 and CLB time. This allows the ‘I/O read 
flag’ latch to start searching for flags in P2 BTC starting in Col 1. When a 
flag bit is found, the ‘I/O read flag’ latch is set at P2 BT4 and CLB time and 
the following sequence of events occurs: 


These switches must be set as shown to 
operate the data recorder under control 
of the CPU. 





Data Recorder Operators Panel 


BROSO1 


1. The column indicator is updated to indicate the column that is 
being transferred to the user. 

2. The flag (P2 BTC) is erased. 

3. The entry register is reset at P2 time. 


At KBD BT1 and CLB time the A register is transferred to the entry register, 
and this data appears on the !/O bus out to the user; and at KBD BT2 the 
‘I/O read data’ latch is set which brings up the ‘read data ready’ line (refer 
to 2 ) to the attachment. At this time the I/O data is valid and the 
attachment can sample the I/O bus out. The attachment puts the data on 
the |/O bus out (refer to 3 | ). The entry register is reset and the I/O bus 
out data is loaded into the entry register at KBD BTC. The data in the 
entry register is then compared to the A register at PU time (via the data 
recorder verify circuits) and if a non compare is present, the ‘read non 
compare’ line (refer to ) is active to the user at PU BT2. The I/O 
compare command is active when the data recorder is online to the Sys- 
tem/3 Model 6. 


DATA RECORDER ATTACHMENT - Introduction 
5496 Read Operation (Part 2 of 2) 5406 FETMM ss (2/71) 10-109 


DATA RECORDER ATTACHMENT~-Introduction 
5496 Punch Operation (Part 1 of 2) 









1 2 

PU Op 
Priority Granted (CLB) 
Pch Data Rdy For 5496 wane : — 

nter Data 
1/0 Ready s-14A ‘ 1/O Sample I/O Busy 
(not) 1/O Busy gS FL ! 
; (not) 1/O Bsy . 

PUBT8 : | : : 1/O Sample 


=< 






BT 4CLB 
P2 On-line 


A Reg BT B 
P3 A 
BT 4CLB 


PS 


PR A 
X-P Xfer Req 


Entry Register 
(not) 1/O Busy eee 


BT 1 CLB 






Data Bus Out 





A 
BT C 6 Reset 


‘+ xX —-— UCUTo ceelay line) 












|/O Pch Busy 


a (request cycle steal) 
A 


Ce 
FL | kbd Service 
Erase Flag 
K-P Xfer 
Req 
Col 96 amy FL 


5406 FETMM 





(I/O op 
complete) 


5496 PUNCH OPERATION 


To use the 5496 Data Recorder as an input-output device for the model 6, 
perform the following steps: 


@ Set the following switches on the data recorder: 


1. Program switch to OFF. 
Z: Verify switch to PUNCH. 
3. Auto record release switch to AUTO. 


@ On the central processing unit console, position the data recorder online 
switch to ON LINE. This activates the line ‘I/O switch’ in the data recor- 
der attachment and is the major control line in the attachment. In the 
data recorder, this line performs a record erase and holds this line active 
which locks out all of the keys and most of the switches on the operator 
console (of the data recorder). The record erase is inhibited during a 
feed check condition to allow operator recovery. If no error condition 
exists in the 5496, the ‘I/O ready’ line is activated. 


To punch data cards, the operator sets up the 5496 as in the read opera- 
tion, and loads the hopper with cards to be punched. The cards can be 
prepunched and data added, or they can be blank cards. If printing is de- 
sired, the operator must turn on the print switch on the 5496 console. 

Any number of data columns can be punched in a card up to a maximum 
of 96 columns. All 96 columns must be entered. The columns to be skipped 
are loaded with blanks. 

The I/O punch operation simulates a keyboard entry operation. The attach- 
ment puts the data to be entered on the I/O bus in lines (refer to ) 
and then brings up the ‘I/O enter data’ line (refer to 2 | ). This sets the 
‘1/O enter data’ latch. The following BT8, the ‘I/O sample’ latch is set. 

The following BTC resets the entry register, and the next BT1 and CLB 
loads the 1/O data bus into the entry register. The following BT2 sets the 
‘1/O busy’ latch which brings up the ‘I/O busy’ line (refer to Fey ) to 
signal the attachment to drop the ‘I/O enter data’ line. The 1/O bus in data 
is now available to the attachment on the I/O bus out and the attachment 
can do a compare to test for valid data transfer (refer to ). 

The following Col 1 P2 BT4 and CLB, the ‘I/O any key’ latch is set. This 
allows a normal keyboard service cycle which starts a search for KBD flags. 
When a KBD flag is found, the ‘KBD’ latch is set and the data is entered 
into delay line memory at KBD time. The following PU BT6 resets the 
‘I/O enter data’ latch, ‘1/O sample’ latch, ‘I/O busy’ latch, and the ‘I/O any 
key’ latch. Resetting of the ‘I/O busy latch drops the ‘I/O busy’ line to the 
attachment and tells it that the 5496 is ready for the next data input. If the 
attachment brings up the ‘I/O enter data’ line before the end of the next 
P2 time, the next data transfer is entered into memory 56 usec after the 
first data transfer, which is the maximum data transfer rate. If the attach- 
ment fails to enter new data before the end of P2 time, a minimum delay 
of approximately 5.4 ms occurs before the next data transfer into memory. 
There is no minimum data transfer rate. 


DATA RECORDER ATTACHMENT-~— Introduction 
5496 Punch Operation (Part 2 of 2) 


When the data for column 96 is entered, the signal ‘set K-P transfer req 
fl’ is generated, and this is sent to the attachment as ‘operation complete’ 
(refer to 5 ). Because the auto record release switch is set to AUTO, the 
5496 now feeds a card from the hopper, and a normal punch and print 
operation is performed. 

If a feed check occurs and a card fails to feed from the hopper, the signal, 
‘1/O hopper jam’ is sent to the attachment. The signal ‘I/O feed check’ is 
sent to the attachment if a card jam occurs in the transport. If a feed check 
occurs, the keyboard function release key is unlocked and the operator uses 
normal feed check recovery procedures to clear the condition. A feed check 
also drops the signal ‘I/O ready’ until the feed check condition is cleared. 

The I/O bus lines can be tested by bringing up the diagnostic command 
to the 5496. This allows the data on the I/O bus in lines to be gated to the 
|/O bus out lines and allows the user to exercise the data lines for diagnos- 
tic purposes. 


5406 FETMM 


(6/70) 


10-111 


LOAD 1/0 INSTRUCTION LOAD I/O (LIO) INSTRUCTION FORMAT 


e The load I/O instruction consists of three or four bytes. 


e The load I/O instruction selects the data recorder when the device 
. | Op Code | OQ Byte Storage Address 
address equals F (hexadecimal). Byte 1 Byte 2 Byte 3 and/or 4 


@ Two bytes in storage addressed by the operand address, are loaded into Operand Address 
the data recorder address register (DRAR). | | 





The load !/O instruction is used to load the DRAR, which is located in the 
CPU local store register (LSR), with the starting address used for a start 
1/O read, or punch operation. The load I/O instruction must be executed 
prior to each start !/O read, or punch instruction issued. 















The contents of the core 
address specified will be 
loaded into the DRAR. 


Q Byte Description 


The upper four bits (bits 0-3) specify the device address of the data recor- 
der. Bit 4 is the M bit. This bit is not presently used, and should be zero to 
allow for future use. Bits 5, 6, and 7 are the N field. In this instruction the 
N field is not used and should always be zero. 

The load I/O instruction is accepted only if the data recorder is not busy. 
If the device addressed by the load I/O instruction is busy, the load !/O 
instruction shall be equivalent to a wait until the condition is no longer 
present. When the condition is no longer present, the load !/O instruction 
shall be executed. 





N field is 
not used. 





M bit is 
not used. 


Device address 
1111 (F) for 
data recorder. 











Op Code 
31 - Direct address. 
71 - Indexed by R1. 
B 1 - Indexed by R2. 


Parity and Error Conditions 





A parity error detected by the attachment results in a processor check stop, 


and the processor check light comes on. 
| BRO802 


DATA RECORDER ATTACHMENT- Introduction 
Load I/O Instruction Format 5406 FETMM (6/70) 10-113 


DATA RECORDER ATTACHMENT — Introduction 
Test I/O Instruction Format 


TEST I/O AND BRANCH INSTRUCTION 

@ The test I/O instruction consists of three or four bytes. 

e@ The test I/O instruction selects the data recorder when the device address 
equals F (hexadecimal). 

e The test !/O instruction tests for the following conditions: 


1. Busy 
2. |/O check or not ready 


The test |/O instruction tests for a specific condition designated by its O 
byte. If the condition tested for exists, the test 1/O causes a branch to the 
operand address. 


Q Byte Description 


The upper four bits (0-3) specify the device address of the data recorder. 
Bit 4 is the M bit. This bit is not presently used and should be zero to allow 
for future use. Bits 5, 6, and 7 are the N field. The N field is used to specify 
the condition to be tested for. 

The data recorder always accepts a test I/O instruction. 


Parity and Error Conditions 


A parity error detected by the attachment results in a processor check stop, 
and the processor check light comes on. 


TEST 1/0 (TIO) INSTRUCTION FORMAT 


| Op Code | O Byte Storage Address 
Byte 1 Byte 2 Byte 3 and/or 4 


Branch Address 













The core address specified will 
be branched to if the condition 
tested for is met. 










N Field 
X1X - Busy. 

XOX - I/O check 

or not ready. 












M bit is 
not used. 









Device address 
1111 (F) for 
data recorder. 





Op Code 
C1 - Direct address. 

D1 - Indexed by R1. 
E1 - Indexed by R2. 






BRO803 


5406 FETMM 


(6/70) 


10-114 


ADVANCE PROGRAM LEVEL INSTRUCTION 


e The advance program level instruction consists of three bytes. 


e The advance program level instruction selects the data recorder when 
the device address equals F (hexadecimal). 


@ The advance program level instruction tests the data recorder for 
conditions of busy, and I/O check or not ready. 


The advance program level operation causes the program to loop until the 

condition tested for is no longer present, and then proceeds to execute the 
next sequential instruction. The unconditional advance becomes equivalent 
to ano op. 


OQ Byte Description 


The upper four bits (0-3) specify the device address of the data recorder. 
Bit 4 is the M bit. This bit is not presently used and should be zero to allow 
for future use. Bits 5, 6, and 7 are the N field. The N field is used to specify 
the condition to be tested for. 


Parity and Error Conditions 


A parity error detected by the attachment results in a processor check stop, 
and the processor check light comes on. 


DATA RECORDER ATTACHMENT — Introduction 
Advance Program Level Instruction Format 


ADVANCE PROGRAM LEVEL (APL) INSTRUCTION FORMAT 


Storage 
Op Code O Byte Address 
Byte 1 Byte 2 Byte 3 
F 1 F M N Not used 
0 3 4 7 0 345 70 7 








The storage address byte 
is not used with an APL. 










N Field 
X1X - Busy. 

XOX - |O check or 
not ready. 


X = Bit not checked 











M bit ts 
not used. 







Device address 
1111 (F) for 
data recorder. 














Op Code for APL 
instruction. 






BRO804 


5406 FETMM 


(6/70) 


10-115 


DATA RECORDER ATTACHMENT - Introduction 
Sense 1/O Instruction Format — | | 


SENSE I/O INSTRUCTION 


e@ The sense instruction consists of three or four bytes. 


e@ The sense instruction selects the data recorder when the device address 
equals F (hexadecimal). 


e When bit 6 of the N field equals 0, the DRAR is stored in the storage 
address specified. 


@ When bit 6 of the N field equals 1, two status bytes are loaded into the 
storage address specified. 


The purpose of this instruction is to store data from an I/O attachment or 
an LSR assigned to the attachment into the main storage location of the 
effective address. 


Q Byte Description 


The upper four bits (0-3) specify the device address of the data recorder. 

Bit 4 is the M bit. This bit is not presently used and should be zero to allow 

for future use. Bits 5, 6, and 7 are the N field. Bits 5 and 7 of the N field 

are not used and should be Zero. Bit 6 of the N field is used to determine 

if the LSR, or two status bytes are to be stored in the specified address. 
The data recorder always accepts a sense instruction. 


Parity and Error Conditions 


A parity error detected by the attachment results in a processor check stop, 
and the processor check light comes on. 


SENSE (SNS) INSTRUCTION FORMAT 


| Op Code | O Byte Storage Address 
Byte 1 Byte 2 Byte 3 and/or 4 


Operand Address 


















Address where the two sense 
bytes are stored: one in the 
specified address, and the 
second in operand address 
minus one. 





N Field 
X1X - Store status. 
XOX - Store DRAR. 





M bit is 
not used. 


Device address 
1111 (F) for 
data recorder. 














Op Code 
3 0- Direct address. 
7 O- Indexed by R1. 
B O - Indexed by R2. 





First Byte 


QO Off line. 

1 Transport jam. 

2 Stacker full, hopper empty, or hopper jam. 

3 Not used. 

4 Incorrect card code. 

5 Compare error on read or punch I/O cycle 
or failure to take 96 cycle steals. 

6 Reserved for FE use. 

7 Reserved for FE use. 


Second Byte 
This byte is a diagnostic data byte located in the multi-purpose register. 
The diagnostic data byte was originally sent to the data recorder by a 
diagnostic start 1/O. 
BRO805A 


5406 FETMM 


Start I/O Instruction Format — 


START 1/0 INSTRUCTION 


e The start 1/O instruction consists of three bytes. 


@ Thestart |/O instruction selects the data recorder when the device 
address equals F (hexadecimal). 


@ The start I/O instruction is issued to the data recorder to read a card 
or punch and print a card. 


@ Printing is performed only if the print switch on the data recorder is on. 


The purpose of the start 1/O instruction is to command the I/O attachment 
to initiate a data transfer operation between the data recorder and the CPU 
main storage. 


O Byte Description 


The upper four bits (0-3) specify the device address of the data recorder. 
Bit 4 is the M bit. The M bit is not presently used and should be zero to 
allow for future use. Bits 5, 6, and 7 are the N field. Bit 5 of the N field 
is not used and should be zero. Bits 6 and 7 of the N field are used to 
specify a read or punch and print operation. 

Any start |1/O command issued to the data recorder when offline lights 
the I/O attention lamp. It may be turned off by system reset or by switch- 
ing the online/offline switch to ON LINE. Any start I/O instruction issued 
to the data recorder when online and busy, is looped until busy drops. 


Parity and Error Conditions 


A parity error detected by the attachment results in a processor check stop, 
and the processor check light comes on. 


DIAGNOSTIC INSTRUCTIONS 
Diagnostic Start 1/O 


Device Address: 1111 (F) 
M Bit: Not presently used, but should be zero to allow for future use. 
N Field: 


Bit 5 6 7 
X 1  1—Diagnostic (data) 


This command is issued to test the punch and read logic circuitry used in 
communicating between the CPU and the data recorder. A byte of data is 
issued to the data recorder attachment during the control code cycle of 
the diagnostic start 1/O instruction. : 

This byte is translated from EBCDIC to card code by the channel. It is 
sent to the data recorder attachment, where it is stored in the DBO and 
presented to the data recorder. It then returns to the attachment for 
comparison. 


DATA RECORDER ATTACHMENT-Introductio 


Following this instruction with a sense instruction provides the following 
information: | 


1, First byte—bit 5: This bit is on if the byte sent to the data recorder 
did not match the byte returned by the data recorder. The bit being 
on would indicate a problem in the data recorder or the interface 
between the data recorder and the attachment. 

2. Second byte: This byte contains the data given to the attachment 
on the previous diagnostic start |/O (in case of a compare error, this 
is not the same as the byte returned by the data recorder). If this byte 
does not agree with the byte sent on the diagnostic start |/O, it would 
indicate a problem in either the attachment or the channel translator(s). 


Note: The sense instruction must be issued before the next start |/O instruc- 
tion to make the comparison valid, since the byte of data issued during the 
diagnostic start 1/O instruction is reset by the next start I/O instruction. 

The data recorder is in a diagnostic mode of operation until system reset is 
depressed, or any other start !/O instruction is issued. The data byte is also 
latched up until the diagnostic mode is terminated. No card motion takes 
place, 


Bit 5 6 7 
X 0 O-—Diagnostic read (cycle steal) 


This command causes the attachment to take one cycle steal and insert a 
blank (hexadecimal 40) into the core location specified by the current con- 
tents of the data recorder local store register. No mechanical motion takes 
place, As with all other start 1/O instructions for the data recorder, the 
instruction is executed only if the data recorder is ready and not busy. 


START 1/0 (SIO) INSTRUCTION FORMAT 


Op Code O Byte IR Byte 
Byte 1 Byte 2 Byte 3 


Control 
Code 








Control code is not used with 
astart 1/O Instruction. 










N Field 
X00 Diagnostic read 

(cycle steal) 
X01 Read a card 
X10 Punch and print a card 
X11 Diagnostic start I/O 
(data) 













M bit is 
not used. 












Device address 
°1111 (F) for 
data recorder. 







Op code for 
start 1/O 
instruction. 






BRO806A 


5406 FETMM ss (2/71) 10-117 


DATA RECORDER ATTACHMENT-Introduction 
Data Flow 


Main 
Storage 


DOM 


SAR 
Hi 


CPU 








vp 


=a) 


| Translate Out 





Translate In 


DBI 
Reg 
Store Diag or Gate Data . 


Sense Status Info 














Select 
Controls 








Cycle 
Steal 
Controls 






- 


ATTACHMENT 


DBO : 
|) ° 
i Diag Load DBO | 
or Punch 
X Timed Read Data Available 
LSR 


5406 FETMM = (6/70) 10-118 


5496 A 
Entry Reg 
Reg O 


Delay 
Line 


Card Read, 
5496 Punch,Print, 


Controls 





DATA RECORDER 


Chapter 2. Functional Units 


INTRODUCTION TO FUNCTIONAL UNITS 


Chapter 2 contains the functional units of the data recorder attachment. 
The first page of the chapter is a board layout of the data recorder attach- 
ment, It is broken down into cards and contains the following information: 


1. Card locations. 

2. Circuits found on that card. 

3 ALD page reference numbers that describe the circuits found on the 
card, 


4. Card type number. The part number of the card changes each time 
that card has an engineering change to it. The card type number, 
however, always stays the same. 


The card location number appears on each page, or section of a page, that 
describes the circuitry on that card. For example, S2 on a page refers to the 
DBI assembler. | 


Symbols 


Figures within this chapter contain the symbols: Pa | numbers in squares, 
and © letters in circles. These symbols refer to text, marked with an 
identical symbol, that describes or explains the function of the unit marked 
in the figure. 


DATA RECORDER ATTACHMENT—Functional Units 
Introduction to Functional Units , 5406 FETMM (2/71) 10-201 


DATA:RECORDER ATTACHMENT- Functional Units 5406 FETMM = (6/70) 10-202 
Board:Layout : ou W235 SoU Oits, -eetenet 


—_ 


. Multi-purpose register 1. DBI gates . OP decode 


DBO register | 2. DBI register . OP control signals 


5496 Cards 
Condition latches 3. DBI parity generator . Cycle steal controls 


Card Location U2 


DBO parity latch . LSR select 










DBO gates . Modify +1 Card Location T2 2 Wide Card 
On line read 
transfer and 


entry control. 





Busy latch 






2 Wide Card 





KPCH address latch 






On line control 
and data entry. 












o 89 ON DO aA FF WB DN 





Bit 6 latch On line 
4 punch control. 
- 1/O check decode 
Card Type 
1/O attention decode 5943 








Ald Pages RP411 
RP421 
Card Type 5025 


Card Type 
5942 





Receivers Receivers 


Ald Pages - RP101 Ald Pages  RP121 Ald Pages  RP201 Ald Pages  RP301 
RP111 RP131 Thru RP241 Thru RP331 
Card Type 5026 Card Type 5026 Card Type 5024 Card Type 5023 





Data Recorder Attachment Board B1 on Gate A (A-B1) 
(Card side) 


*Board B1 also contains: 

1. Channel Banks. 

2. Keyboard Attachment. 
3. CRT Attachment. 





4% . “S 
; ; é Bad! 


CPU ATTACHMENT | | 5496 


00 0 eee eve eters? © 0 0 00 ee ee%e%e" 
eeeeereeeerseeoeecoeeeeeoese o.e.e eee 
eese eeoeove © ote ones “ ee OC eeeceeevee - 


4 


0 © © 0-0-0" 0-070" e7".",” @ 0 00 08 6” 
ese ovate: ota e fete te te? @eeoee ore! 









ee 





















Clock (1, 2, 3, 4, 5, 7, 8) to Chan 7 Lines , 









|/O Compare CMD 


Chan (SIO, LIO, TIO, SNS) Instr 4Lines , : 













neoeeeeeeoeesn 
e@eceeveevesv ee 
» eeeveoeeesce 
@eeeoeoeoeoeeevee ee ee 
e@eeeesece 


Chan (10, IR) Cycle 2Lines | s 











































: Req RD Cycle to 5496 * 
Chan System Reset : I/O Lock Keyboard | : 
: Chan Check Reset : Diag Command to 5496 3 
= Key Punch On Line | : RD Comm to 5496 : 
: Chan (EB1, EB Not 1) 2 Lines PU Data Ready for 5496 : 








Chan Sample DBO |/O Switch 













we ee 6 e © “er 
oe 0 00 0 0 0's'e'e* 


1/O Power on Reset 




























Translate (In, Out to CPU) 2 Lines 


wee 
Seeevevevvee 


Chan Data Bus In Bits O---P 9 Lines 





Chan DBO Bits (0----P) : “ss 
: ST = : SOS ES 
: Condition B : : |/O Read Data Ready : 
Sa Light 1/O Unit. Check . | 1/O Caamana Reset : 
tight Vottention : Punch Complete : 
eo orking : 1/O On Line and Ready : 
| Req I/O Cycle to Chan a |/O Hopper Jam : 
: Block SDR to CPU : ee aebeue 3 
ee Rec Chant Store Date 1/O Read Non Compare 
: LSR Line (5, 7) 2 Lines |/O Transport Jam : 





e 
. 
° 
° 
°. 
® . 
°° s 
e Meter e ee 0 0 00 Oe tO ek Ok Ol Oe ee ee 0 6 0 ee nie nn 8.8, 
nt. 9.8 0 0 0 oe wan %.%, 


aE 
2 


fi 


nats 
ee? 


: 


DATA RECORDER ATTACHMENT-—Functional Units 
Interface Lines 5406 FETMM ss (2/71) 10-203 


DATA RECORDER ATTACHMENT-—Functional Units 5406 FETMM (6/70) 10-204 
Initial Selection (Part 1 of 2) : 





Condition A 


KPCH Busy or UC or NR 


SIO , | 
a Reject LIO or SIO, Set Condition A , | Condition B 
KPCH Busy Timed 


RP211 





RP211 Accept LIO or SIO, Set Condition B 


| Diag Read 


CI5 





: | 14 i = Read Op 
KPCH CIl7 15 
Check DBO Parity Check, set Condition A and B 
Parity 3 
| RP321 Gi 
3 iti 
neces Ei Set Condition B | A 


SNS Store Status e Punch Op 
Field SNS Decode} LSR Select . ve 


RP30O1 RP301 


o 


EEN, 





Diag Read 
Read Decode 
fel slo Punch Decode 


slO Decode |" Diag Decode (data) 


Diag Op (data) 


—_ 
oOo © ON 


av 
v—v 
wo 
oO 
= 
8) 
U 
OO 
_ 
= 


T2 









Test Busy | 
TIO Test oy (test condition met, set condition A) ee 
TIO est NR or UC Decode fe Rd Comm to 5496 
RP211 RP221 (not met, set condition B) " 


R2 7 | 


(not) Condition A 
Condition B LIO © 








~ 


= LSR Select 
KPCH Cl 7 Decode IR Cycle 13 Clock Run 
LiO ‘CI7 14 

See 


RP301 


INITIAL SELECTION 


a | Data Bus Out (DBO) Register 


a. At clock 5 of the 1!O cycle, the IQ byte is set in the DBO register. 

b. Parity is checked and if invalid, condition A and B are set, and 
the inverse of DBO is set in the DBO register. 

c. If parity is valid, the data recorder attachment uses the IO byte to 
decode the device address and the N field. 


ea Decode Device Address 


a. DBO register bits (0-3) equal to F (hexadecimal 1111), selects the 
data recorder, 

b. Decoding the device address allows the data recorder attachment 
to decode the |/O instruction. 


ee Decode N Field 


a. DBO register bit 6 sets the bit 6 latch. 
b. DBO register bit 7 and the bit 6 latch are used to decode the N field 
according to the following table: 


O LSR select 
Sense 1/O 
1 






not used 










not used Store status 













Test I/O or not used Test not ready, or 
Advance 1/O check 
Program 

Level not used Test busy 






Diag read (Cycle Steal) 


Read decode 







Start 1/O 





Punch decode 


Diag decode (data) 


BRO807A 


DATA RECORDER ATTACHMENT-—Functional Units 
Initial Selection (Part 2 of 2) 


Accept or Reject Load !/O or Start I/O 


a. A load I/O is rejected by setting condition A if busy is up, and 
accepted by setting condition B if not busy. 

b. A start I/O is rejected by setting condition A if the attachment is 
busy, or if the data recorder is not ready, and accepted by setting 
condition B when these conditions are not present. 

c. Start I/O resets unit check (if set) and if the attachment accepts 
the command, raises |/O condition B. 


Ei Condition A and B Latches 


These latches are set according to the following table: 






1/O Condition 
1/O Attachment Condition 


PA | 8 
sIO Reject Instruction 

Correct oF i0 

Instruction |Accept Instruction 

















Instruction! DBO 
Parity 










O 


Byte : 7 
TIO Condition Not Met 
or APL 
= 





Incorrect DBO Parity 


Correct DBO Parity 





BRO808 


Gi During a Start 1/O 


a. The ‘diag op’ (data) latch is set at clock 5 of the 1Q cycle, or 
b. The ‘diag read’, ‘read op’, or ‘punch op’ latch is set at clock 7 
of the IR cycle. | 


5406 FETMM 


(2/71) 


10-205 


DATA RECORDER ATTACHMENT—Functional Units | 5406 FETMM (2/71) 10-206 
Registers (Part 1 of 2) | 








| RP411 


Store Diag or Gate Data 
DBI 


X 
Xx 


| Sense Status Info 


T ranslate 


cA 
i 





Modify + 1 


Parity 
Generator 





ie, 
le 
aa 


Diag Load or Punch 


eee 
X 


CPU DBO 





To A register. 






Translate 


Timed Read Data Available 
Out 


Parity XX 
Check 






RP201 


Translate Out 


Command 
Generator 


CPU ATTACHMENT DATA RECORDER 





GR bBo REGISTER 


a. During each I/O instruction |O cycle, the 1O byte is available to 
the DBO register at clock 5. 

b. During start |/O IR cycle, the start |/O control code is translated, 
and made available to the DBO register at clock 5. 

c. During a punch cycle, a translated byte of data Is available to the 
DBO register at clock 5. 


[MULTI-PURPOSE REGISTER 


a. During a diagnostic start |/O (data) IR cycle, or a punch cycle, the 
multi-purpose register is loaded with the contents of the DBO 
register at clock 5, 

b. During a read operation, the multi-purpose register is loaded with 
the contents of the 5496 entry register at clock 8 of the CPU cycle, 
during which a cycle steal is requested, 

c. Bits 0, and 1 of the multi-purpose register are used to check for 
incorrect card code during a punch cycle, or a diagnostic start 
|/O (data). 


FEB! ASSEMBLER 


a. During a ‘SNS EB 1’ cycle, the DBI assembler is loaded with sense 
status information at clock 2. This status byte is placed in CPU 
main storage without being translated. 

b. During a ‘SNS EB Not 1’ cycle, the DBI assembler is loaded with 
the contents of the multi-purpose register at clock 2. This byte of 
data (diagnostic byte) is translated prior to being placed in CPU 
main storage. 

c. During a read operation the DBI assembler is loaded with the 
contents of the multi-purpose register at clock 1 of a read |/O 
cycle, This byte of data is translated prior to placing in CPU main 
storage. 


pa | PARITY GENERATOR 


The parity generator is used during a sense instruction, punch cycle, 
or read cycle to maintain correct parity in the DBI register. 





MODIFY +1 


Modify +1 sets bit 7 of the DBI register at clock 3 of an I/O cycle. | 
The DBI register is then used to modify the data recorder LSR. 


DATA RECORDER ATTACHMENT—Functional Units 
Registers (Part 2 of 2) : 


5406 FETMM 


(6/70) 


10-207 


DATA RECORDER ATTACHMENT~—Functional Units 
Cycle Steal and LSR Select Controls ( Part 1 of 2) 


CYCLE STEALS. 











(diagnostic read cycle operation) Clock 2 
Req Read 
1 
Rd Data Available Cycle | | cl 
Clock 1 
Read |/O Cycle 
DBO Bit 1 
RPAD DBO Bit 4 
Clock 8 
Phase B. 
Pu Req 
Punch Op ory 
— EL 
DR Punch Busy or 
RP321 


Se 


e 


Punch Cy 
Clock 1 


. -—for ~ 


(Not) Punch Op 


1/O Operation Complete 
(after 96 
cycle steals) 


(from 5496 at 
end of operation) 


3 


ee 
Sahat 






Punch Op 
Transport Jam 
=e Command Reset 







(inhibit punch cycle steals) 


—— 2 eee eee eee ee 


Req Bit 4 


A 


Read Gate 


(diagnostic read 
cycle operation or 


read operation) 


Punch Op 


Req I/O Cy To CPU 


Early Priority Req (bit 4) 








L 


Priority Granted 


(to LSR select) 


Read Cycle 












5406 FETMM ss (2/71) 10-208 
2 
LSR SELECT 
DR Sense 1/O 
DR Load I/O loR| LSR Select 
Clock 5 A FEL 
(not) Cond A Clock 2 A 
Cond B 
Clock 7 
EB Not Ist Cy A 
EB 1st Cycle or 
| Read cycle or ( !/O Cycle LSR Line. 5 
| punch cycle § Clock 4 A LSR Line 7 
—_eo oT (to CPU) 


(to translate in) 
Read I/O Cycle 


Block SDR to CPU 
Store Data to CPU 
Req Rd Cycle to 5496 


(to translate out to CPU) 


1/O Cycle 
Punch Cycle 
Punch Data Ready for 5496 ee 4 
ock 8. 


| 
| DBO Bit 1 
| 


CYCLE STEALS 


me = he data recorder attachment requests cycle steals during the follow- 
ing operations: 





a. Diagnostic read 
b. Read 
c. Punch 





To request a cycle steal, the request bit 4 AND is activated which 
generates ‘req |O cycle’ to CPU. This line is activated at clock 2 of 
each machine cycle until the request is granted. 


The CPU grants a cycle steal to the data recorder attachment by 
setting DBO bits 1 and 4. | 





LSR SELECT 
le) The data recorder LSR (DRAR) is selected during the following: 


Load !/O, clock 2 of EB cycles 

. Sense LSR, clock 2 of EB cycles 
|/O cycle clock 4 

. Cycle steal priority granted, clock 8 





ao 707m 


To select the DRAR, activate LSR select lines 5 and 7. 


DATA RECORDER ATTACHMENT-—Functional Units 


Cycle Steal and LSR Select Controls (Part 2 of 2) 5406 FETMM (6/70) 10-209 


DATA RECORDER ATTACHMENT—Furctional Units 
Error Conditions 





Vv 
Set DBO C+D Bits 
Card Code Bit D A 
DRBusy DR Bité Lt Card Code Bit C OR 
DR Busy , DR Busy Timed [| #£JA 
FL fo) DR Busy e Not Rdy e |O Chk 
A | Status 4 
A 
FL 
DR Cl3 
RP221 


DR Sys Rst 


Unit Check Rst T.P. 

ay ——_ oR RP221 
DR Punch Busy 
PU Error A 


DR Command Reset : i 
(Not) DR PU or RD Cycles Complete} | A 


DR IO Read Non Compare | 
Read Op ) | A 


Status 5 
Diag Op FL 
DR CI1 A 
EB First Cycle ; 
DR Sys Rst 3 


Unit Check Rst TP. RP221 
DR HJ or HE Stacker Full DE NO LOUSY 


DR Transport Jam 







(Not) DR On Line Ready 





lor! DR Busy or U.C. or N.R. 


Light 10 Attention Punch 
(Not) DR On Line Ready 


DR Address 
DR Start I/O 


‘-DR On Line Ready 
DR Sys Rst 


Data Rec On Line 


iy, 


On Line Lt 


DR Busy Timed 


5406 FETMM = (6/70) 10-210 


Incorrect Card Code 


lon Light 1/O Unit Check LOE» 


Compare Error (or failure to take 96 cycle steals) 


Chapter 3. Operations 


INTRODUCTION TO OPERATIONS 


Chapter 3 contains the detailed flowcharts and timing charts of the opera- 
tions performed by the data recorder attachment. 


Flowcharts 


The flowcharts contain three levels of information. By reading down the 
heavy dark lines, the reader can learn the major objectives of the operation. 
The second level of information is obtained by reading the information in 
the boxes that branch off the heavy dark line. The information that is con- 
tained in each block in a heavy dark line is explained in the blocks that 
branch off from it. | 

The third level of information is contained in the note blocks (open ended 
blocks) that branch off the second level blocks. Information in these blocks 
is intended to explain why an action has been performed. 


Timing Charts 


The timing charts in this chapter are to be used to supplement the informa- 
tion found in the flowcharts. 


DATA RECORDER ATTACHMENT- Operations 
Introduction to Operations 5406 FETMM = (6/70) 10-301 


DATA RECORDER ATTACHMENT-—Operations 
Load I/O Instruction Flowchart 


LOAD 1/0 INSTRUCTION 


l-Op Cycle. The load I/O instruction tag is available to the data recorder 
attachment, but no action takes place until the 1O cycle. 


/Q Cycle, The data recorder attachment checks DBO parity, decodes the 
instruction address, and sets the condition latches. 


EB7 Cycle. The DRAR is selected and the first data byte is transferred into 
LSR Lo. 


EB Not 71 Cycle. The DRAR is selected and the second data byte is trans- 
ferred into LSR Hi. 


A 








Enter |-Q cycle 









Decode !O byte 
for data recorder 
address and set 

the condition 
latches. 













Gate 10 byte 
to attachment at 
clock 5 phase B. 










Valid 
parity on 
DBO 






Decode bits 0-3 
and set ‘KPCH 

address’ latch at 
clock 5 phase B. 







Yes 


Set condition B and 
select LSR at clock 7. 


Take B cycles. 








Set condition 
A and B latches. 


Turn on processor 
check light. 


Processor 
Check Stop 








Set condition A 
at clock 7. 


Exit to CPU and Repeat 


|-Op and I|-O cycles. 


: Before taking B 


cycles, the CPU 
will (depending 
on the cp code) 
take an I-X1 cy- 
cle, or an |-H1 

and |I-L1 cycles. 





End of Operation 


5406 FETMM = (6/70) 10-302 





EB1 Cycle. 












Bring up LSR 
lines 5 and 7 at 
clock 2. 





Transfer data 
byte into low 
half of LSR. 


EB not 1 cycle. 












Bring up LSR 
lines 5 and 7 at 
clock 2. 





Transfer data 
byte into high 
half of LSR. 








ra 
g 

ee 
Be 


Seed 





i : # 
t Bren Baud 


|-Op 


| 1-0 
0123 4 5 6 7 8}0 12 3 4 5 6 7 8 


I-H1* I-L1** |-Op 


EB EB 
0123 4 5 6 7 810 12 3 4 5 6 7 81/0 1 2 3 4 5 6 7 810 12 3 4 5 6 7 8/0 12 3 4 5 67 8 


N Line Title 


Oo 


ALD Page 


LIO Instr RP311 








10 Cycle RP311 





Condition B RP211 


RP211 


QO 


ondition A 
PCH Address Lt RP211 
DBO Register RP201 


RP301 


~ 


LSR Lines 5 and 7 


m 


B 1 Cycle RP311 


EB Not 1 Cycle RP311 


LSR Select Lt RP301 


* For index format I-H1 is I-X1. 
** For index format |-L1 does not exist. 
A- Signal up if DBO parity in error. 


DATA RECORDER ATTACHMENT- Operations 


Load I/O Instruction Timing Chart 5406 FETMM = (6/70) 10-303 


DATA RECORDER ATTACHMENT- Operations 
Test I/O or Advance Program Level Instruction Flowchart 








TEST I/O OR APL INSTRUCTIONS 


!-Op Cycle. The test |/O instruction tag is available to the data recorder 
attachment, but no action takes place until the 10 cycle. 


!Q Cycle. The data recorder attachment checks DBO parity, decodes the 
instruction address, and sets the condition latches. Setting condition A 
causes a program branch. Setting condition B causes the CPU to proceed to 
the next sequential instruction. 


Enter |O 
Cycle 


Decode 10 byte 
for data recorder 


address and set 
condition 
latches. 








Gate !Q byte to 
attachment at 


clock 5 phase B. 














Valid 
parity on 
DBO 


Yes 


Decode bits 0-3 
and set ‘KPCH 

address’ latch at 
clock 5 phase B. 








Bit 6 
latch set at 
clock 5 phase 
B 


Test for busy. 

















Test for I/O 
check or not 
ready. 









Test 
condition 
met 










Set condition 
B latch at clock 7. 


Set condition 
A latch at clock 7. 


Set condition 
A and B latches. 


Turn on processor 
check light. 


Processor 
Check Stop 


5406 FETMM (6/70) 














Perform an I-X1, 
or |-H1 and I-L1 
cycles to develop 
effective address. 
If an APL instruc- 
tion, perform I-R 
cycle. 


End of Operation 


—10-304 


sexes 





_ CONDITION MET CONDITION NOT MET 


l-Op I-X1*(I-R) l-Op I-X1*(I-R) |-Op 


ee 
-Q 
| Line Title J ALDPage]O. 12.345 678/012345678/012345678]/012345678/012345678/012345678/01234567 8 
TIO Instr RPS rs ne ian 


DBO Register RP201 


* For direct address format !-X1 is I-H1 followed by I-L1 
IR cycle follows !Q during an APL. 


2 
Ta “ 
. Pa 
ce _— 
5 t 






NO 


oP ae ie ACR CAS ine ier 











DATA RECORDER ATTACHMENT - Operations | 
Test I/O or Advance Program Level Instruction Timing Chart 5406 FETMM = (6/70) 10-305 


DATA RECORDER ATTACHMENT-— Operation 
Sense I/O Instruction Flowchart ; 





SENSE INSTRUCTION 
Enter 10 Cycle 


!-Op Cycle. The sense instruction tag is available to the data recorder attach- 
ment, but no action takes place until the |O cycle. 


1Q Cycle. The data recorder attachment checks DBO parity, decodes the 


instruction address, and sets the condition latches. Decode IO byte 
for data recorder 

EB?1 Cycle. Either the first data byte, or the DRAR LSR Lo, is stored in address and set 

the CPU main storage address specified. the condition 


latches. 


EB Not 7. Either the second data byte, or the DRAR LSR Hi, is stored in 
the CPU main storage address specified minus one. 


Spool 





Gate 10 byte 


to attachment at 
clock 5 phase B. 













Valid 
parity on 
DBO. 


Yes Set condition 


A and B latches. 


Decode bits 0-3 
and set ‘KPCH 


address’ latch at 
clock 5 phase B. 


Set condition B at _ Processor 
clock 5 phase B. Check Stop 





Bit 6 
latch set at 
clock 5 phase B 


Yes 






Set LSR select at 
° clock 7. 


s SS) ae a ee ee or NOLS. IB SOre taking B 


Take B Cycles. 


cycles, the CPU 
will (depending 
on the ap code) 
take an I-X1 cy- 
cle, or an |-H1 

and !-L.1 cycles. 


EB 1 Cycle. 


Turn on processor 
~ check light. 





EB not 1 Cycle. 


Set store status at 
clock 7. 


5406 FETMM = (2/71) 10-306 


cad 


Note: See decision block 
at co-ordinates 2B. 






LSR select. 
Generate P bit at 
clock. 2. 


‘Store status. 
Set DBI register at 
clock 2. 









Parity even 


Note: See decision block 
at co-ordinates 2B. 


LSR select. 
Generate P bit at 
clock 2. 


Store data. 


Set ‘Diag translate 
in’. 

Set DBI register at 
clock 2. 










Parity even 


I No 


End of Operation 





5 3 


|-Op 1-O 1-H1* I-L1** EB EB 1-Op 
Line Title ALDPage}]012°>3 45 6728/0123 45 678]/012345678]0123 456780123 45678]/012345678]012345678 





SNS Instruction RP311 


10 Cycle RP311 
Condition B RP211 


Condition A RP211 


A 


PCH Address Lt RP211 


KPCH Bit 6 Lt RP201 


tore Status Lt RP301 


LSR Select Lt RP3O1 
EB 1 Cycle RP311 


EB Not 1 Cycle RP311 


Generate P Bit RP3O1 


Diag Translate In RP301 


ow) 


e > 
wn 


3 BI Register RP421 


14| LSR Lines5and7 | RP301 


DBO Register RP201 





* For index format |-H1 is I-L1. 

** For index format I-L1 does not exist. 
A- Signal up if DBO parity in error. 

B - Signal up for store status. 


DATA RECORDER ATTACHMENT-— Operations _ 
Sense I/O Instruction Timing Chart 5406 FETMM (6/70) 10-307 


DATA RECORDER ATTACHMENT~— Operations | 5406 FETMM (6/70) 10-308 
Read Operation Flowchart (Part 1 of 2) 


READ OPERATION | CPU | ATTACHMENT 


A read operation is started on the 5496 if bits 6 and 7 equal O and 1 respec- 
tively in the Q byte. During the CPU I-R cycle, the ‘read op’ latch is set for | 
the operation and a read command is issued to the 5496. The read command | 
causes the 5496 to read a punched card onto the delay line. This read oper- 
ation, which is under control of the 5496 circuits once it has been initiated 
by the attachment, is identical to an operator pressing the read key on the 
5496 in an offline operation. 

The 5496 read cycle feeds a card from the hopper, reads the data from 












| 

the card (placing the data in the proper word on the delay line), and stacks / | Clock 8 prior to 
the card in the stacker. After the entire card has been read onto the delay 0 cycle steel cycle 
, C 7 
line, the 5496 signals the attachment that the first column of data is ready 5 | Modify + 1 (LSR) 
to be sent to CPU storage. 3 

To transfer the data from the delay line to the CPU storage, the data re- | 
corder attachment steals a machine cycle from the CPU and signals the 5496 R 
to make the next column of data available for transfer to the CPU. When O | Cycle Steal Granted 
the data is available, another cycle is stolen to transfer the data to storage. L 

| | | | S Attachment 

This sequence of data-available/stolen cycle continues until 96 data bytes ery pe! 
(an entire card) have been transferred. se Contole | 

At the end of the data transfer, the ‘read op’ latch is reset and the oper- | 2 Flag 
ation ends. Error conditions other than parity checks must be detected by Op Decode Read Gate | oa 
a sense instruction. 

The flowchart of the operation gives a more detailed description of the | : 
read operation for the data recorder attachment. 





5496 


Cycle Steal Request 
ul e Controls Circuits 






Cycle Steal 
and LSR 
Controls 






and . 





\ Mechanics 


Read Data 
| Available 





LEGEND: 1> Op Code 3> Modify LSR 


2> Data 4» Address 
BRO809 


Enter |-O Cycle 


Decode !-Q 
byte for data 
recorder address 





and set condition 
latches. 


, 


Set condition 
A and B latches. 
Lock up DBO 


input latches 
to attachment. 





Exit to CPU 


RP211 


Set condition A latch. 


Exit to CPU 


Enter I-R cycle. 


Start read operation. 


Set condition 
A and B latches. 


Lock up DBO 
input latches 
to attachment. 





Exit to CPU 


DATA RECORDER ATTACHMENT-—Operations 
Read Operation Flowchart (Part 2 of 2) 





Reset condition A Clock 3 
and/or B latches. 



























Attachment 
waits until 
5496 reads all 
96 columns of 
data from card 
onto delay line. 


RP201 i 
Clock 5, ; 
Gate I-OQ byte to Phase B "- 
attachments. CPU mainline 
7 


Valid 
parity 
Read 
data 


on 
DBO 

available from 
5496 


Enter cycle 
steal 1-O cycle. 


Put data 
byte into 

















CPU storage. 





Yes RP321 


Decode bits 
0-3 and set 











data recorder 
address latches. 


Prepare for 








1/O cycle register and is 
RP301 (any CPU RP421 f then gated to 
Set bit 6 and 7 latches cycle). Set ‘rd cycle’ | DBI Assembler. 
for operation. latch 





RP321 


Activate ‘early 
priority request’. 







Data 
recorder busy 
or not 


RP331, RP301 
cee Activate ‘req meee 4 
No RP211 lO cycle to CPU’. (any CPU 
cycle) 
Set condition B latch. RP231 


Reset DBO. Clock 5 
Set DBO. Clock 8 


RP211 


Valid 
parity on 
DBO 







Higher 
priority cycle 
steal request to 
CPU existing 


Yes RP321 


No 
CPU cycle prior RP331 
to stolen cycle. : ae 
granted’. 


Set ‘read op’ 

and ‘read Clock 7 
command to 

5496’ latches. 










96 


RP321 RP331 data No 
‘Read op’ latch transfer 
activates: Set ‘rd cycle’ latch. cycles 


. ‘read gate’. 
. ‘darec busy’. 
. ‘lO busy’. : eae a 
| ei cycle’. 
RP321 RP301 2. ‘10 cycle’. 
3. ‘translate in’. 
4 


Activate: 


Reset: 

1. ‘read command 
to 5496’ latch. 
‘dr addr I-O, 


. ‘store data 
to CPU’. 

. ‘block SDR to 
CPU’. 

. ‘req rd cy to 


I-R cy’ latch. 
. Bits 6 and 7 FL’s. 


. Data recorder | 5496’. | End 
address latch. Operation 








Data byte from 
5496 sets DBI 
multi-purpose 








RP3O1 
RP411 


Gate data byte Clock 1 
to DBI. (10 Cycle) 


RP421, RP301 


Reset: 
1. ‘reqrdcy’ FL. 


2. ‘DBO reset’ FL. 





RP311 
‘Modify + 1’ 
to DBI 
Assembler Clock 3 
(set bit 7 on) 
Update LSR. 
RP311 
‘Sel LSR in 1-O'. Clock 4 
RP421 
Force P bit. Clock 5 
RP331 


: ; Clock 8 
Reset ‘rd cycle’ latch. Phase B 






Command reset from 5496. 


5406 FETMM = (6/70) 10-309 





ssascendh 


I-R Cycle of 


5496 Reads Data From Card to Delay Line 
SIO Insr 


5496 Attachment 


he Soto 
Read Op, Read Gate RP321 


Read Command to 5496 RP321 


Clock J 


NO 


Clock 5 


Request Read Cycle, Early Priority Request RP421 


on 


Read Cycle Latch, Request Read Cycle to 5496 RP331 


Translate In, Block SDR, Store Data RP331 


eset DBO In Read Op Latch RP30O1 


imed Read Data Available (set DBO) RP301 


_ Sense Diagnostic or Gate Data (to DBI) RP301 


Reset DBI Assembler _ RP311 


LSR Select RPSON Re eae ee ee 
Modify +1 (to Update LSR) RP311 





Block DBI Bit P Latch : RP421 


Phase B of Clocks 1, 3, 5, and 8 


Command Reset (from 5496) 


RP111 


4 RP321 


—_ 


. _, eb 
WO N ~ Ww 


Data Recorder Busy (attachment) 


on 
rs 
© 
a 
© 
= 
© 
c 
ot 
n 


Approx. 1700 ms SA 5.4 ms 





Read Op FL KHO31 


Read Transfer Latch PU to KBD Transfer 


KLO31 


~ 


Oo 
fs 
oO! o 


1/O Read Cycle Latch KLO31 


Read Sync Latch | KLO31 Colm 96, 1 


—_> 


1/O Read Flag Latch KLO41, 


20 1/O Read Data Latch, |/O Read Data Ready 


KLO41 


DATA RECORDER ATTACHMENT- Operations 
Read Operation Timing Chart © 





96 Cols Read From Card 









Request Cycle Steal and 
Wait For Priority 


CPU Cycles Continue 
Until Priority Granted 


Request I/O Cycle to CPU ( 


One Pass of Delay Line (5.4 ms) 


16, Col 96 






7 20, PR, BTC 
17, Read Flag PR 


19,KBD 


Clock 3 Clock 4 | 


1/O Cycle — Column 1 
1/O 


CPU CLOCK emnncenim 6|7|s of1|2]sfa[s\— Approx. 1.5 see. ——»\\ ofr f2|sfa{sje\v|e o|1|2|s]4|slel7|s 


RP331) 


Clock 1 





Clock 3 





Wait For Col 
2 Data on 
Delay Line 


Request Cycle 
Steal and |/O 
Cycle For Col 2 


Columns 3 - 96 


\ 





Word Counter 9, ' 


( Sample 2 ( 


1/O Ready 


1/O Read Flag Col 96 


A 











20 





not 20, Col 96, 17 
17, Read Flag 


19, KBD 


5406 FETMM 10-311 


(2/71) 


DATA RECORDER ATTACHMENT -— Operations 5406 FETMM (6/70) 10-312 
Punch Operation Flowchart (Part 1 of 2) 


PUNCH OPERATION CPU | 5496 


A punch operation is started on the 5496 if bits 6 and 7 equal 1 and 0 re- 
spectively in the Q byte. During the CPU I-R cycle, the ‘punch op’ latch is 
set for the operation and a cycle steal is requested from the CPU. When the 
cycle steal is granted by the CPU, the attachment transfers the first data 
byte from storage to the delay line in the 5496 (during the stolen cycle). 
The data recorder attachment continues transferring data bytes to the delay 
line with cycle steal operations until 96 bytes have been transferred. The 
transfer of data bytes 2 through 96 are requested by the 5496. The ‘da rec 
punch busy’ line is active during the time the 5496 is placing the data byte 
on the delay line. After the byte is placed in the proper delay line word, 
the 5496 drops the busy line to request another data byte from the CPU. 

After 96 data bytes are transferred, the 5496 feeds a card from the hopper, 
punches the data into the card, prints the graphic characters represented by 
the data if desired, and stacks the card in the stacker. This operation of card 
feeding, punching, printing, and stacking is under complete control of the 
5496 circuits once the 96 data bytes have been transferred from storage to 

_ the 5496 delay line. The data recorder circuits also signal the attachment 

that the operation is complete when the card is stacked in the 5496. This 
operation complete signal (command reset) resets the ‘punch op’ latch and 
the operation ends, | | | 

Error conditions other than parity checks must be detected by a sense 
instruction. If at any time the EBCDIC data from CPU storage is translated 
into a card code containing C or D bits (an invalid card code), the error is 
indicated by setting the ‘status 4’ latch and by lighting the !/O unit check 
light on the FE console in the CPU. The 5496 punches the translated bit 
code into the card (without the C and D bits) and prints the closest graphic 
that the 5496 can decipher from that bit configuration. 

The flowchart of the operation gives a more detailed description of the 
punch operation for the data recorder attachment. 


Delay # Line 


‘'S 
A 
R 






DBI 





2 


-m-onvnijAZzoo o~- 


Cycle Steal 
Granted 


| Translate Out 





Peet al Attachment 
Punch. 


Controls 










| 
| 
| 
2 
| 
| 






5496 


Cycle Steal Request 
Controls 





Cycle Steal 
and LSR 
Controls 





Hi 5496/LSR Lo 





Legend: 12 OpCode 3) Modify LSR 
2» Data 4» Address 


BRO810 


1 


Enter !-Q Cycle RP201 


Gate I-O byte to Clock 5 
attachment. Phase B 


Decode |-O 
byte for data 
recorder address 
and set condi- 
tion latches. 






Valid 
parity on 
DBO 






No 







Set condition RP211 
A and B latches. Yes RP321 


oe a re Decode bits 0-3 
nput tatcnes and set data 


to-attachment. recorder address latches. 
RP301 






Set bit 6 and 7 
latches for operation.* 


A Exit to CPU 


* 










Data bit 6 = 1 
Yes recorder bit 7 = O 
RP211 busy or not 





ready 
No RP211 


Set condition 

B latch. 
Reset condition Clock 3 
A and/or B latches. 


Valid 





Set condition A latch. 


Exit to CPU 










Enter I-R cycle. 







Start punch operation. No parity on Clock 5— 
DBO Phase B 
Set condition Mee RPS21 
A and B latches. 
Lock up DBO . ‘punch op’ 
input latches latch. Clock 7 


to attachment. 


. ‘pu req |l-O 
cycle latch’. 





RP321 


Exit to CPU ; 
‘punch op latch 


activates: 
1. ‘punch op’. 


2. Data recorder 
busy. 
3. ‘I-O working’. 





RP321 RP301 








Reset: 

1. ‘dr addr |1-O 
I-R cy’ latch. 

2. Bit 6 and 7 
latches. | 

3. Data recorder 

address latch. 






Clock 8» 








DATA RECORDER ATTACHMENT-—Operations 
Punch Operation Flowchart (Part 2 of 2) 





For Punch Operation 


\ 


CPU mainline 
program cycles. 






Cycle steal 


request to CPU. RP331 


‘Req !-O cycle Clock 2 
to CPU’. 


Higher 
priority request 
waiting 











Yes 







No RP331 


Clock 8 
Set ‘pu cycle’ latch. 


Enter |-O Cycle. 








Send data byte 
to multi-purpose 
register, then to 
entry reg of 
5496. Update 
LSR contents. 







RP231 
RP321 







Reset DBO and 


‘pu req I-O cy’ Clock 1 
latch. 





RP421 


to DBI. 


RP311 


‘modify + 1’ 
to DBI 
assembler 
(set bit 7 on). 


RP301 RP421 


‘sel LSR in 1-O’. Clock 4 
Force P-bit on Clock 5 
DBI. 








RP231 
Set data byte 
into multi- 
Purpose register. 


Clock 5 
Phase B 













CorD 
bits present 
on DBO 


Yes 







RP331 
Reset ‘pu cycle’ latch. Clock 8 
Phase B 


Data 
recorder busy 


Yes 







No 


‘1/0 
No , operation 
complete’ from 
5496 ** 


Yes ** After 96 data 
transfer cycles. 
Set ‘inhibit cy 
steal’ latch. 


RP321 


CPU mainline 
program cycles. 
Wait for command 

reset from 5496. 


RP221 


Set ‘da rec busy 
timed’ latch. 








RP321 


Reset ‘punch op’ 
latch. 


RP321 


Reset ‘inhibit 
cy steal’ latch. 
RP221 


Reset ‘da rec Clock 3 
busy timed’ 


latch. 







End Operation 


5406 FETMM = (2/71) 10-313 





2 3 
% x x 
¥ tow hal 


I-R Cycle of | Request Cycle Steal Column 1 Column 1 Data to Columns 2-96 | Punch and 
SIO Instruction | and Wait for Priority 1/0 Cycle 5496 Entry Reg and Stack Card 
. Delay Line 


V 


<q 


5496 Attachment 


3/4 8 














V V 
CPU Clock —————=>- 6|7|8 o|1|2 56 |? [2 o|1]2|3|4] 5]6|7/8 \ \ |1|2|3]4[5]6|7|2 \ 
No.] Signal Name | Logie Request 1 Request 2. Request 96 


Punch Op Latch RP321 


2 Punch Req I/O Cycle Latch RP321 


















AES «RTE See AGS aa ie BEE RIAN, RE WE Ra FN A RA Rg 9 SS Sep a RS eres Wren rrr a een 
BRP eel re east ce para PTE eae OSE Fema eS eee Ree ee PERRET STARR, Boye mone REE NES Er Ear nen Aa ae a OS re ca ROT meer i ee | 





(not) 16 3, Clock 1 


| ees 


Clock g Cycle Steal - Col 96 Goo, gp 


ES OS eer ae anny are eee 
Le ae . ae Prac 3 


Rea Pa ES EN 




















Taare 





> 
o>) 


—_ 


Punch Cycle Latch (cycle steal) RP331 


Peteste 


Clock 8 | Cycle Steal - Col 1 Clock 8B 
ty Berit Seay se Nee Sot ag oan dae WISE Sis. eee? Sho 


Clock 8 Clock 4 (update) 
EN ee 


4 LSR Line 5 and 7 (select LSR) RP301 





Force P Bit on DBI RP421 









Bterracets — 
hier ee 
te BEN ae egy Rate 






Clock 3 


a scene! 
Clock 1 
cet 
Clock 5B 
La 


Modify +1 RP311 


(multipurpose register reset) RP231 


(multipurpose register set) RP231 





(data in multipurpose register) RP231 


Translate Out to CPU RP331 







os 
bs 
Ge 
Le 
es: 
an 


ET eee 
SOS ener Vinton ess o 





I/O Working | RP321 





Cex 


(inhibit punch cycle steal) FL RP321 


O1 
i 
co 
oS 
© 
= 
© 
S 
+ 
7 





® 


1/0 Enter Data Latch KLO51 





1/O Sample Latch 


KLO51 13, (not) 16, BT8 t) 13 


Me REA pe ENO UE ETA ook aL Rg Mae ELT ke 





Load |1/O Data (entry regset) KLO41 13, (not) 16, BT1, Clock 










(not)13 


1/O Busy Latch | KLO51 






I/O Any Key Latch KLO51 





Kybd Serv Fl, PU, BT8 Pe 
‘Set K-P Xfer Req (KDO61) . ea es 
Wd Ctr 9, Counter Sample 2 | i ee, ie 


(reset for 1/O enter data latch) KLO51 


1/O Operation Complete KLO41 


20 1/0 Command Reset KLO11 


—_ -— ~— —_ —_ as 
co © NS ©) Be 


DATA RECORDER ATTACHMENT-—Operations | : 
Punch Operation Timing Chart | 5406 FETMM (2/71) 10-315 


DATA RECORDER ATTACHMENT~— Operations 
Diagnostic Data Operation 


DIAGNOSTIC DATA OPERATION 


A diagnostic data operation is started in the data recorder attachment if 

bits 6 and 7 equal 11 in the OQ byte. During the I-R cycle of the CPU instruc- 
tion, the data byte is sent to the 5496 attachment multi-purpose register. 
The data byte is then sent to the entry register of the 5496, which returns 
the data to the multi-purpose register for checking. At the end of the I-R 
cycle, the data byte remains latched-up on the data bus lines so that the 
field engineer can check voltage levels when searching for the cause of a 
trouble. The data bus circuits in the attachment can also be checked through 
programming by issuing a sense instruction following a start |/O diagnostic 
data instruction. The sense instruction provides the following information. 


First Byte—Bit 5: This bit is on if the byte sent to the 5496 did not match 
the byte returned by the 5496. Otherwise this bit is off. The bit being on 
would indicate a problem either in the 5496 or the interface between the 
5496 and the attachment. 


Second Byte: This byte contains the data given to the attachment on the 
previous diagnostic start 1/O. (In case of a compare error, this is not the 
same as the byte returned by the 5496.) If this byte does not agree with the 
byte sent on the diagnostic start |/O, it would indicate a problem in either 
the attachment or the CPU translator(s). 


The block diagram shows the data flow for the start !/O diagnostic data 
operation. 


e Astart 1/0 loads data byte onto data lines at ‘I-R cycle’, ‘clock 5’, 
‘phase B’. Data is static up to, but not including, data bus in assembler. 


e A sense instruction puts a data byte in the core location following the 
status byte. 
e Translate signal: 


Active during ‘I-R cycle’ for data byte. 
Forced for ‘SNS EB not 1st’ byte. 


LEGEND: 


» 
> 


Op Code 


Data 


CPU 





Hi 5496 


» 
» 


LSR Lo 








Status Information 


Address 


Oo = 


-~owwdi2Zzadona 





ATTACHMENT | 5496 
| Entry 
Li 
2 
| 
2 


Data 
Bus in 
Assembler 





Noort WN — OO 





SIO I-R Cycle | 
| 9 aie MA Ed ise 
} | 
| Op Decode 
1> 2) miami and | 
Controls 
Translate ~ Instructions: 
LSR Select 
| Start 1/O Data 
Sense Not used 





BRO811 


5406 FETMM 


(6/70) 


10-316 


DIAGNOSTIC CYCLE STEAL OPERATION 


A diagnostic cycle steal operation is initiated in the data recorder attachment CPU 
if bits 6 and 7 equal 00 in the O byte. At the time the diagnostic cycle steal 
instruction is decoded, an ‘early priority request’ is made in the attachment 
and the read line is activated. At clock 2 time of the following cycle (I-R 
cycle), a cycle steal request is made to the CPU. When the request is granted, 
bit 7 of the data bus in assembler is set on so that the contents of the data 
recorder attachment LSR are incremented by +1. Following the cycle steal 
operation, the programmer can compare the contents of the LSR with its 
contents prior to the stolen cycle. (The programmer should load a known 
value into the LSR before the start !/O diagnostic cycle steal is issued.) 

This diagnostic operation checks the cycle steal and LSR control circuits 
in the data recorder attachment. The block diagram shows the data flow 
for the diagnostic cycle steal operation. 


ATTACHMENT 


a 
Oo~ 





Modify +1 


rowadat2zono 


@ Start I/O diagnostic cycle steal decodes at clock 5 of I-O cycle. 


e Diagnostic cycle steal decode latch (RP311): 


Set at ‘l-Q cycle sample’ (decode time). 
Reset at ‘rd 1/O cycle’, ‘clock 1’. 


Note: ‘rd 1/O cy’ latch operates as in a normal read cycle steal due to Cycle Steal Acknowledge 


read gate being forced on. 


Read 


| Read Controls 
Gate 


1 mali 1 we ~Op Decode 








Cycle Steal 
and LSR 
Controls 










Cycle Steal Request 





Hi 5496 | LSR Lo 


LEGEND: » Op Code BRO812 


DATA RECORDER ATTACHMENT-—Operations 
Diagnostic Cycle Steal Operation 5406 FETMM (6/70) 10-317 


Section 11. CRT Attachment 


This section of the 5406 FETMM contains the theory and maintenance 
diagrams for the 2265 Display Station Model 2 attachment. It consists of 
three chapters as follows: | 


Chapter 1. Introduction 
Chapter 2. Functional Units 
Chapter 3. Operations 


CRT ATTACHMENT—Contents 


Contents 


Chapter 1. Introduction 11-101 


CRT Attachment (2 Parts) 11-101, 11-102 
2265 Display Station Model 2 11-103 
Load I/O Instruction Format 11-104 
Test I/O Instruction Format 11-105 
Sense I/O Instruction Format 11-106 
Start I/O Instruction Format 11-107 


Chapter 2. Functional Units 11-201 


Introduction to Functional Units 11-201 
Board Layout 11-202 

Card 1 (2 Parts) 11-204, 11-205 

Card 2 (2 Parts) 11-206, 11-207 

Card 3 (2 Parts) 11-208, 11-209 


Chapter 3. Operations 11-301 


Introduction to Operations 11-301 

Load I/O Instruction Flowchart 11-302 

Load I/O Instruction Timing Chart 11-303 

Test I/O Instruction Flowchart 11-304 

Test I/O Instruction Timing Chart 11-305 

Sense I/O Instruction Flowchart 11-306 

Sense I/O Instruction Timing Chart 11-307 | 

Start I/O Instruction Flowchart (2 Parts) 11-308, 11-309 

Start I/O Instruction Timing Chart (3 Parts) 11-310, 11-311, 11-313 
CRT Display Flowchart 11-314 | 
CRT Display Timing Chart 11-315 


5406 FETMM 


(2/71) 


11-i 


Chapter 1. Introduction 


CRT ATTACHMENT 


The IBM 2265 Display Station attachment is the interface between the dis- 
play station and the CPU, It provides a means for the display station to use 
the facilities of the CPU to communicate with main storage. The attachment 
is located in the main gate of the CPU in position A-B1 and uses three, four 
wide cards. 

Instructions and data from the CPU are sent to the attachment via the 
data bus out (DBO) lines. Attachment information is returned to the CPU 
via the data bus in (DBI) lines. Control and timing signals not under pro- 
gram control are sent and received via control lines between the attachment 
and CPU. 
















2265 
Display 
Station 






1 CRT 
Attachment 





Other 
Device 
Attachments 


BRO815 


The CRT attachment contains logic to: 


Decode program instructions 

Detect error conditions 

Generate cycle steal requests (CSR) 

Address the LSR assigned to the CRT (CRTAR) 

Modify the LSR address (generate constants) 

Check the LSR address to detect when 960 characters have been 

displayed 

7, Generate timing signals required by the display station for a 
display operation 

8. Indicate attachment and display station status (operating and 

error conditions) 


OO! = OSs 


CRT ATTACHMENT-Introduction 
CRT Attachment (Part 1 of 2) 


Program Instructions 


The CRT uses four program instructions. Each instruction is decoded by 
the CRT attachment to develop gate signals to initiate and control the 
specific operation as defined in the instruction O and R bytes. Only instruc- 
tions with the CRT address in the device address are accepted by the CRT 
attachment. The CRT address is 1001 (9). 


The program instructions are as follows: 


Load I/O (LIO) 
Test 1/O (TIO) 
Sense I/O (SNS) 
Start I/O (SIO) 


Load I/O addresses the LSR assigned to the CRT to (1) load a core storage 
address of the CRT data field into the LSR, (2) gate the CRT attachment 
to retain the address where the data field began, and (3) reset the display 
station CRT beam to the upper left corner of the screen. 

Test 1/O is used by the program to test operating or error conditions of 
the CRT attachment and display station. Program branching may result 
from the indications returned from the test I/O instruction. 

Sense I/O transfers CRT status information or the address in the CRT 
LSR into main storage to be used by the program. 

Start I/O initiates or halts a CRT display operation. The start I/O halt 
may be used in diagnostic programs to check the operational status of the 
CRT attachment. 


OS 


Error Detection 
The CRT attachment checks for the following error conditions: 


1. Data parity 
2. Display station not ready 


Data parity is checked at the DBO at all times. On each cycle steal granted 
to the CRT, parity is checked within the CRT attachment at the data regis- 
ter. (The data register stores the data byte received from the CPU.) Any 
parity error condition forces the CPU to a hard halt at the end of the cycle 
in which the parity check was detected. All parity checks are latched 
(retained) in the attachment in order to be checked by program instruc- 
tions (test 1/O or sense I/O). Parity check conditions are reset by: 


1. System reset 
2. Check reset 
3. The CRT attachment accepting a SIO instruction 


‘A CRT not ready condition occurs when a start 1/O instruction is issued 
to the CRT device and the display station power is not on. Not ready con- 
dition is indicated at the operator’s console by lighting the CRT |/O atten- 
tion lamp. The lamp remains lit until the CRT is made ready (power is 
restored to the display unit). 


Cycle Steal Requests 


Cycle steal requests are generated by the CRT attachment to signal the CPU 
to transfer data to the CRT or to modify the CRTAR (LSR) address. The 
CRTAR is selected during a cycle steal request to locate the main storage 
address of the data field (it may be a byte within the data field) or to modi- 
fy the CRTAR address. CRT attachment cycle steal requests are thirteenth 
in priority of the cycle steal |/O devices. The CRT cycle steal request may 
be overridden by a higher priority I/O device and requires the CRT to keep 
issuing its cycle steal request until the CPU acknowledges the request by 
returning DBO bits 1 and 5. This signals the CRT attachment that the next 
machine cycle is granted to the CRT and is referred to as an I/O cycle. 


Local Storage Addressing 


Local storage register CRTAR is addressed by the CRT attachment by 
selecting LSR select lines 3 and 6, without ledger card device (with ledger 
card device installed on the printer, CRTAR is addressed with LSR select | 
lines 6 and 7). The CRTAR is addressed during: 


1. Cycle steal requests (CSR) 
2. A load I/O instruction cycle 
3. A sense I/O instruction 


Cycle steal cycles address the CRTAR to locate the data field address and 
to modify the LSR address. | 

Load I/O instruction addresses CRTAR to load the LSR with the main 
storage address of the first byte of the data field. 

Sense I/O instructions address the CRTAR to sense the address presently 
in the LSR and transfer the information into main storage. 


5406 FETMM (2/71) 11-101 


CRT ATTACHMENT~-Introduction 
CRT Attachment (Part 2 of 2) 


Constants 


Constants are generated by the CRT attachment to increment or decrement 
the CRTAR address. Constants are returned to the CPU during a cycle steal 
request, by activating DBI lines that represent the binary value of the desired 
constant. The constants generated are: 


li. +1 (DBI line 7 during the modify lo cycle) 
2. —192 (DBI lines O and 1 during the modify lo cycle) 
3. —768 (DBI lines 6 and 7 during the modify hi cycle) 


Modify plus one is generated each data transfer cycle steal to increment 
the LSR address to the next data byte in the data field. The LSR address 
is incremented by one until the LSR address is 960 above the starting 
address of the data field which indicates the end of the data field. A cycle 
steal request is then made to subtract 960 from the incremented address in 
the LSR to return it to the starting address of the display field so the CRT 
can display the data again. Subtract 960 must be broken into two times, as 
the LSR address contains two bytes. During the modify lo cycle, 192 is sub- 
tracted from the LSR lo byte, during the modify hi cycle 768 ts subtracted 
from the LSR hi byte. 


Local Storage Register Address Increment Checking 


The LSR address must be checked for each increment of 64 or 960 above 
the starting address of the data field address. 

Each increment of 64 of the LSR address indicates that the display station 
has displayed 64 characters (one line on the CRT screen) and the display 
station needs a retrace signal (to move the CRT beam back to the left side 
of the CRT screen). An increment of 960 indicates that the display station 
has displayed 15 lines and a restore signal is needed (to move the CRT beam 
to the upper left corner of the CRT screen in position to start another dis- 
play cycle). 

Attachment logic detects each increment of 64 and 960 in the LSR address 
and develops the signals to initiate a retrace or restore cycle in the display 
station. 


Note: The data field starts on a XX01 boundary; therefore the 64th or 960th 
character is indicated when the LSR address is 65 or 961 respectively. 


CRT Attachment Timing 


CRT attachment logic provides the following timing signals to the display 
station: 


1. Step display 
2. Start character generator 
3: Reset display 


Step display indexes the CRT beam to the next character position on the 
CRT screen. The 65th step display signal, which indicates the end of a line 
display, causes the display station to move the CRT beam to the left edge 
of the CRT screen, and the CRT attachment to generate a time-out signal 
(approximately 288 us) to allow the display station time to complete the 
retrace. Step display signals are generated at the start of each character 
display cycle and are 4.5 us in duration. : 


Start character generator signals the display station to start displaying a 
character. This signal is active 6 us after the beginning of step display and 
is 1.5 us in duration. 

Reset display initiates a restore cycle in the display station (moves the 
CRT beam to the upper left corner of the CRT screen) and starts a delay 
in the CRT attachment to allow the display station to complete the re- 
store cycle. This signal is also active when the attachment detects that the 
LSR address has incremented 960. 


CRT Attachment Status 


A sense I/O instruction causes the CRT attachment to gate the CRT attach- 
ment error latch and signal line conditions (status) onto the DBI and the 
information transferred to main storage. A test 1/O instruction tests the 
CRT attachment for error or busy conditions and causes the attachment to 
return an indication about the result of the test to the CPU (I/O condition 
A and I/O condition B signals). 


5406 FETMM 


(2/71) 


11-102 


IBM 2265 DISPLAY STATION MODEL 2 


The 2265 Display Station Model 2 provides visual access to data in main 
storage. Data is displayed on a cathode ray tube (CRT) in the display sta- 
tion in 15 lines of 64 characters in each line (960 characters). A character 
position marker (cursor) may be displayed at each character position either 
with or without the character. The cursor and character display are under 
program control. 


System Console 


There are no controls for the display station on the system console, only 
an indicator that lights when a program instruction is issued to the CRT 
_and the CRT is not ready (power is off at the display station). The CRT - 
[/O attention indicator remains lit until the CRT is made ready (power is 
turned on at the display station) or a system or check reset is performed. 
A system reset stops a display operation if one is in progress. 


Data 


The character set for the display station consists of 64 characters, each 
character is encoded in a 6 bit EBCDIC sub-set. The seventh bit is for 
cursor control. Format of the data byte for the CRT is as shown: 


Bit 012 3 4 5 6 7 


t————= Data ——> 
——p| |e Cursor Bit 


| (e———. Not Used 


BRO813A 


Each character may have a cursor displayed with it if bit 1 equals 0. No cur- 
sor is displayed if bit 1 equals 1. 


CRT ATTACHMENT-Introduction 
2265 Display Station Model 2 


The following table shows the characters the CRT can display and the 


6 bit code for each, 






000000 
000001 
000010 
000011 
000100 
000101 
000110 
000111 
001000 
001001 
001010 
001011 
001100 
001101 
001110 
001111 
010000 
010001 
010010 
010011 
010100 
010101 
010110 
010111 
011000 
011001 
011010 
011011 
01.1100 
011101 
011110 
011111 


































Bit O is not used. 





Jo tH A DOVOZSarKACRe—+—-/A' FT TATMMIODD 


w 
o 
5 
x 


Bit 1 is the cursor bit. 


The data to be displayed is located in the display field in main storage. 


01234567 







Bit 
01234567 


Bit 


100000 
100001 
100010 
100011 
100100 
100101 
100110 
100111 
101000 
101001 
101010 
101011 
101100 
101101 
101110 
101111 
110000 
110001 
110010 
110011 
110100 
110101 
110110 
110111 
1171000 
111001 
111010 
111011 
111100 
111101 
111110 
111111 


















N<xS<CAM~! 







W 
© 
S 
= 


se" 

























"“@%* OONOOARWN-OV\Y| 











“He 


BRO814A 


lf bit 1 =O acursor is displayed with the character. 
If bit 1 = 1 the cursor is not displayed. 


If bit 1 =O and bits 2 through 7 = QO, only a cursor is displayed. 


Local Storage Register 


‘A local storage register (LSR), located in the CPU, is assigned to the CRT 


display station. This register (CRT AR) contains the address of the CRT dis- 
play field in main storage. The display field contains the data to be displayed 
on the CRT display station screen, Before the start of a display operation, 

the CRTAR must be loaded with the main storage address of the first data 
byte in the display field. As each data byte is displayed, the LSR (CRTAR) 
address is updated by one so the next data byte is addressed when the LSR 


is addressed again. , 


The display field is a sequential 960 byte area in core that may start at 
any XX0Q1 address. (XX is any hexadecimal address that is 960 bytes less 
than maximum core capacity.) The entire field (960 bytes) is displayed. 


5406 FETMM 


(2/71) 


11-103 


CRT ATTACHMENT~—Introduction | 3 7 | | speeauen “eG ans 
Load I/O Instruction Format | * a | 


LOAD 1/0 (LIO) INSTRUCTION FORMAT 


This instruction Is issued to the CRT attachment to load the LSR (C RTAR) 
assigned to the CRT with the starting address of the display field in core 
storage. The format of the load I/O instruction is: 


Op Code | Q Byte | Storage Address 
1 Byte Byte 2 Bytes 3 and/or 4 
3 
7 1 1001 M N 
: || 
0 34 70 345 70 70 7 




















Storage Address 
Core storage address 
of the first byte of 

the 960 byte display 
field. 





N Field 
XXX for CRT 
X=Oor1. 





M Bit 
Not used for CRT 
should be zero. 





Op Code for load I/O. 
3 1 Direct Addressing 
7 1 Indexed by R1 
B 1 Indexed by R2 


BRO816 


A display station CRT beam reset occurs during a load |/O instruction. 
(CRT beam is moved to the upper left corner of the CRT screen.) The CRT 
attachment starts a 288 ps delay to allow time for the display station to 

complete the reset. This delay interlocks the attachment so that other in- 
structions (except sense and test 1/O) cannot start until the delay times out. 

A ready condition in the display station is not needed for the load I/O 
instruction execution. If the CRT attachment is busy (in a display opera- 
tion), the load I/O instruction is rejected by the CRT attachment and 
causes the CPU to reissue the load I/O instruction. (The CRT attachment 
is always busy when executing a SIO display instruction, therefore the 
CPU will hang in a loop (IR backup) until the system power is turned 
off or a system reset is performed.) 

The CRT attachment must retain where the display field was started in 
main storage in order to check the LSR address for each increment of 64 
and 960. The load 1/O instruction is ANDed with the DBO lines and Not 
EB 1 cycle to set the required latches in the attachment. 


TEST I/O (TIO) INSTRUCTION FORMAT 


The test I/O and branch instruction test the CRT attachment for error or 
busy conditions and branches the CPU to a specific address if the condition 
tested for is met. The format of the test I/O instruction is: 


Op Code Q Byte Storage Address 
Byte 1 Byte 2 Bytes 3 and/or 4. 
C 

D 1 1001 M N 

E 


0 34 70 345 70 70 7 





CPU will branch to 
this address if the 

condition tested for 
is met. 



















N Field equals: 
X1X CRT busy. 

XOX CRT check. 
X=Oor 1. 





M Bit 
Not used for CRT 
should be zero. 

















Op Code for test 1/0. x 

C 1 Direct Addressing aoe one 
D 1 Indexed by R1 (1001) 

E . 


1 Indexed by R2 


BRO817 


Conditions that can be tested in the CRT are: 


1. CRT busy 
2. CRT check 


CRT Busy (N Field Code = X1X) 


A busy condition exists when the attachment is executing a start I/O display 
instruction. | 


CRT Check (N Field Code = X0X) 

The following conditions cause a CRT check: 

ik A parity error in the data register of the CRT attachment. (The data 
register contains the data byte for the CRT display.) 

2. CRT display station not ready. This indicates that power to the 


display station is off. (Power on indicator on the 2265 is not lit.) 
The display station is made ready by restoring power to it. 


The test I/O instruction is always executed. 


CRT ATTACHMENT -—Introduction | 
Test I/O Instruction Format : 5406 FETMM (6/70) 11-105 


CRT ATTACHMENT-— Introduction © 
Sense I/O Instruction Format 


SENSE 1/0 (SNS) INSTRUCTION FORMAT 


A sense instruction is issued to the CRT attachment to transfer the attach- 
ment status or LSR (CRTAR) information into main storage. 
The format of the SNS instruction is: 


Op Code | O Byte | Storage Address 
1 Byte Byte 2 Bytes 3 and/or 4 
3 

7 0 1001 M N 

: | 


0 34 70 345 70 70 7 


















Storage address where 
Ist sense byte is stored. 
2nd sense byte is 
stored at the specified 
address minus one. 





N Field 
X1X - Store status. 
XOX - Store LSR. 

X=Oor 1. 





M Bit 
Not used for CRT 
should be zero. 











Op Code for sense. 

3 0 Direct Addressing 
7 

B 








Device Address 
CRT =9 


O Indexed by R1 (1001) 


O Indexed by R2 





BRO818 


Store Status (N Field Code = X1X) 


Two bytes of attachment status are transferred into main storage at the 
address specified by the storage address of the instruction. Status byte one 
is placed in the address as specified in the sense operand one address, status 
byte two is placed in storage at the operand one address minus one. 

The status bytes are as follows: 


Status Byte One 
First E-B Cycle (Operand 1 Address) 


Bit O Write op (diagnostic only) 

Bit 1 Start char gen (diagnostic only) 

Bit 2 Step-display (diagnostic only) 

Bit 3 Cycle steal request (diagnostic only) 

Bit 4 Display reset (diagnostic only) 

Bit 5 Data register parity check 

Bit 6 Display not ready 

Bit 7 Cycle steal acknowledged (diagnostic only) 


Status Byte Two 

E-B Not First Cycle (Operand 1 Address Minus One) 
Bit 0 

Bit 1 

Bit 2 

Bit 3 Contents of 

Bit 4 the data register 
Bit 5 

Bit 6 

Bit 7 

Bit P (regenerated) 

Status bits O through 4, and bit 7 of status byte one and status byte two 
are used for diagnostic programs only. The diagnostic bits in status byte one 
are CRT attachment signal lines of the same name. The bits of status byte 
two are the data register outputs O through 7. 


Store LSR (N Field Code = XOX) 


The LSR address is stored at the operand one address specified in the 
instruction. 
A sense instruction is always executed. 


5406 FETMM (2/71) 


11-106 


START 1/0 (SIO) INSTRUCTION FORMAT 


A start 1/O instruction is issued to the display station to start or halt a 
display operation. The halt instruction may also be used for diagnostic 
purposes. 

The format of the start 1/O instruction is: 


| Op Code | O Byte | i-R Byte | 
1 Byte Byte 2 Byte 3 


Used only in the start 
1/O halt. A byte of 
data is set into the D 
register during the 

start 1/0 | R cycle and 
may later be sampled 
with a sense instruction. 


N Field 

X1X Display 
XOX Halt 
X=Oort. 


M Bit 
Not used for CRT 
should be zero. 


Device address 


Op Code for start I/O. 


BRO819 


Display (N Field = X1X) 


The CRT attachment decodes the start I/O instruction when the device 
address in the O byte equals nine (hexadecimal 1001). If the N field of the 
OQ byte equals X1X (X may be either a one or zero) the CRT attachment is 
conditioned to start a display of the characters in the display field on the 
CRT screen. After the start 1/O I-O and I-R cycles are complete, the CRT 
attachment generates cycle steal requests. Each |/O cycle addresses the 
CRTAR (LSR) for the location of the display field and increments the LSR 
address by one so that the next selection of the CRTAR addresses the next 
sequential character in the display field. A data character is sent to the CRT 
attachment during the |/O cycle and this character is displayed on the CRT 
screen. As soon as the character is displayed, another cycle steal request is 
made for the next character in the display field. This action is repeated 
until the LSR address has incremented 64 (or a multiple of 64) above the 
starting address of the display field. Each increment of 64 in the LSR 


CRT ATTACHMENT-—Introduction 
Start I/O Instruction Format 





address indicates that 64 characters have been displayed and a retrace is 
needed in the display station. A retrace delay of approximately 273 to 
288 microseconds is started to allow time for the CRT beam to move to 
the left edge of the CRT screen in position for the next line of display. 
No cycle steal requests are made during the delay time-out. Cycle steal 
requests are started again when the retrace delay times out. 


When the LSR address has incremented 960 above the starting address of | 


the display field (actual address in the LSR is 961 because the display field 
starts on a XXO1 boundary), a restore operation is needed in the CRT (end 
of frame) to return the CRT beam to the upper left corner in position to 
start a frame of display again. The same delay described for retrace is started 
for beam repositioning. The LSR address is decremented by —960 during 
the restore cycle, so that the CRT begins its display back at the start of the 
display field. Cycle steal requests are made after each character display to 
refresh the CRT screen at a rate of approximately 54 frames per second. 
If a new load I/O instruction is not issued to a new start I/O display instruc- 
tion, the attachment begins its display with the character located at the 
current address in the CRTAR. The start I/O display instruction is accepted 
by the CRT attachment only when it is not busy and the display station is 
ready. 

The CRT attachment is always busy when executing a SIO instruction. 
If a SIO instruction is issued to a busy CRT attachment, the CPU will 
operate in IR backup mode until the system power is turned off or a 
system reset is performed. 


Halt (N Field = XOX) 
A start !/O halt instruction is issued to the CRT to: 


1. Stop a display operation. 
2; Determine if data flow to the CRT attachment is correct. 


A start !/O halt stops the display on the CRT and ends further cycle steal 
requests. A start I/O display instruction must be reissued to the CRT before 
a display operation starts again. 

For diagnostic purposes, a start I/O halt loads the data register in the CRT 
attachment with a data character during the I-R cycle of the instruction. 
The data register may then be sensed with a sense instruction and compared 
to the data sent to the data register to determine if the data was transferred 
to the CRT attachment correctly. 

The CRT attachment accepts a start |/O halt instruction at any time. 


5406 FETMM 


(2/71) 


11-107 


Chapter 2. Functional Units 


INTRODUCTION TO FUNCTIONAL UNITS 


Chapter 2 contains the functional units of the CRT attachment and the 
errer checking circuits. 

The first page of the chapter is a board layout of the CRT attachment. 
It is broken down into cards and contains the following information: 


I Card locations. 

2. Circuits found on that card. 

3. ALD page reference numbers that describe the circuits found on the 
card. 


4. Card type number. The part number of the card will change each 
time that the card has an engineering change to it. The card type 
number, however, will always stay the same. 


The card location number appears on each page, or section of a page, that 
describes the circuitry on that card. For example, Q2 on a page refers to 
LSR select. 


Symbols 





Figures within this chapter contain the symbols: numbers in squares, 
and (ay) letters in circles. These symbols refer to text, marked with an 
identical symbol, that describes or explains the function of the unit 
marked in the figure. 





CRT ATTACHMENT-—Functional Units | | 
Introduction to Functional Units | 5406 FETMM (2/71) 11-201 


CRT ATTACHMENT—Functional Units 
Board Layout 


et 


bad 


A2 


CRT Timing 


. Character control 
. Step display 
. Retrace timing 
. 65 step - 65 trigger 
. CRT counter 
. Error latches 
a. DBO- data 
b. LSR - parity 
. CRT select 


CRT 
Signal Interface 
Cable 





Ke 
Baud 
Saal 


ALD Pages 
CT101 thru CT121 


Card type 5027 





CRT Attachment Board B1* on Gate A (A-B1) 





DBO Input Receivers 
and Parity Check 


. Channel DBO input 


Restore 


. DBI 

. Unit check latch 

. Condition 6 register 
. D- register 


LSR increment 
checking 


ALD Pages 
CT201 thru CT241 


Card type 5028 





5406 FETMM = (6/70) 


V2 


CRT Control 


. Channel interface 

. |/O attention 

. 1/O condition A and B 
. Write latch 

. Command reject 

. Cycle steal request 

. LSR select 


ALD Pages 
CT301 thru CT311 


Card type 5029 


Board B1 also contains: 


. Channel banks 
. Keyboard attachment 
. Data recorder 


attachment 


11-202 





CRT ATTACHMENT—Functional Units 5406 FETMM (2/71) 11-204 
Card 1 (Part 1 of 2) | 





md 


oO Card Location N2 Counter Run 
ALD Pages CT101 thru CT121 
11-206 


Start CRT 
Timing ! 
* Clock 6 


Trigger Ring Counter 

















FL Index Counter 
A 12 us 
(Not) 1 
f (Not) 2 
p 4 
CT101 (Not) : A 
D Reg Pos 1 Step 
Display 
SNS 
15 us 
(Not) 1 © 
, iw 2} 
(Not) 4 Step Display ( To 
8 1 565 





Cece ecccccccccenesceecnere cai GateStust : 
| Gate Status 1 2H 3 
11-206 Gate SNS Parity PE fe 












te Clock 7 
























LSR Gate tt 
332i : : 192 Count @ : 
11-208 Cond 6 Gate Status 2 gees : EL 
EB Not 1 ot: 64 11-208 Retrace » | 
CTT21 aii 128 A Start Retrace Delay ¢ 
Se eee ee a inieineinineinneiseinineisinersemaestaeraiseeaiseatseserageagy geese = g FL Clock 4 
Sai htee enh atene es toes ee neanneetenne sAneaanr Stasi Seaenr sen Chr aee te orate oanal oma penntseneny ures hntour@enocresprcnansersr Geert ae ues ; CT101 ; 
soees Cc 1 
ies 11-204 LIO Reset ve 
L!IO Retrace ee : Start Char Gen (T 
oo 6 us | oO 
EB Not 1 CRT Ht , . 2265 
LIO CRT LIO Reset sien: (Not) 2 
11-204 CRT Sel CRT tte | oF a A Start CharGen SNS 
| CT101 ne 1\—Not) 8 
ne cTi0} 
ats "Clock 8 
PE: System Reset 
Tora OsoYaTs OM x ce mmmELESESSSSSESEEELLLLTSSSSSEEEEEEELEESEEEEEEEEEEGESEESEEEEEEEEELESSEEEEESEEEEEEEEEEEESEEESEEEEEEEESESESSESEESEEEGEESESSEEEEEEEEEESESEEESEEEEEEEELESEEESESEEEEEEEEEEEEEEEESEEEEEEEEEELEEEESSSEEEEEEEEEEEESESEEEEEEEEEEEEEEEEEEEEEEEEEESEEESEEEEEEEEEEEEREESEESEEEEEEEEEEEESSSS SEES SESEEEEEEEEEEEESSSS 
iisne eat Rade | oe PCS SCS See eee Eee eee Cee See eee SSeS SESS EESEEESTE 
Clock 5 CRT SEL BIH 
10 Cycle A | | oni a Clock 1 | DBO 
Sample DBO | : FL 2388s ies 
f ep rror 
Clock 8 System Reset Clock 5 HE Clock 7 Ackd A latch 
11-206 Cmd Reject OR] IR A HH Sample DBO : 
IR A ' 2 SSiee 11-208 DBO Par Error pT a fl = 
ample Set D Reg tte Clock 5 A System Reset 
| Seen, et 11-206 Gate Par Check Clock O oR] 
10 11-206 Ackd A aH CT121 CT121 
Clock 5 33333 
A soees 
TIO ies 


System Reset acess 


CRT DISPLAY STATION TIMING 


7 CRT display station basic timing is provided with the trigger ring 
counter and its decoding logic. The counter is indexed at the trailing 
edge of each clock 6 time when the ‘counter run’ latch is set. During 
a display operation a cycle steal is requested whenever ‘counter run’ 
is not active. 





© Twelve microsecond decode ANDed with a ’D register’ one bit position 
gates the turn off of the ‘character control’ latch when the counter 
indexes to 8. This is the time required by the CRT to display a charac- 
ter without a cursor. The ‘D register’ input signals the decode block 
if a cursor is not to be displayed with this character. If a cursor is to 
be displayed, the ‘D register’ input prevents the turn off of the ‘charac- 
ter control’ latch until a later time. Fifteen microsecond decode turns 
off the ‘character control’ latch at counter 10 time and provides the 
timing to the CRT when a cursor is displayed with the character. 


eC.) ‘Character control’ latch is set at the start of each character display 
cycle. It remains set for either 12 or 15 microseconds depending on 
which turn off decode block gates its reset at clock 8 time. ‘Character 
control’ is active for the length of time to display one character (with 
or without a cursor) and includes the time to index the CRT beam to 
the next position. ‘Character control’ ANDed with another counter 
decode condition, ‘6 microsecond’, activates the CRT interface line 
‘start character generator’. 


© ‘Step display’ latch is set at the same time that ‘character control’ is 
set. ‘Step display’ remains set until counter four time. The ‘step 
display’ latch generates a CRT interface signal of the same name and 
is used to index the CRT beam to the next character position on the 
CRT screen. ‘Step display’ is active for 4.5 microseconds. 


© The ‘retrace’ latch is active to generate a timing delay in the CRT 
attachment to allow time for a CRT beam retrace or restore operation. 
‘Retrace’ latch active prevents ‘character control’ from generating a 
reset counter run signal and allows the counter to index to a count 
of 192. The time of the delay generated may vary due to the actual 
count in the counter at the time ‘retrace’ is active, but is 273 to 288 
microseconds. ‘Retrace’ latch is reset when the counter reaches 192 
and during load |/O commands. 


@ ‘65 trigger’ and ‘65 step’ latch are set at the end of a line display 
(64th character) to delay the step display signal to the CRT unit. 
The 65th step display signal resets a counter in the display unit 
to move the CRT beam back to the left side of the CRT screen to 
begin another line of display. Without delaying the step display 
signal, the CRT may distort (cut off) the trailing portion of 
character or cursor strokes for the 64th character, due to an early 
retrace signal. | 


CRT ATTACHMENT —Functional Units 
Card 1 (Part 2 of 2) 











CRT ATTACHMENT SELECTION 


‘CRT select’ is set during the |-O cycle of an |/O instruction and is the 
gate to indicate that the information on the DBO is for the CRT. A 
gate to set the condition register is generated at this time. 


RESET FOR LOAD 1/0 INSTRUCTION 


‘LIO reset’ is generated at ‘EB not 1’ cycle to indicate the last machine 
cycle of a load !/O instruction. 


DBO PARITY ERROR 


‘DBO parity latch’ is set whenever an error (parity) is detected on 
DBO at clock 5 time in an I/O instruction, or clock 1, 5, or 7 time 
during a cycle steal cycle. 


STATUS GATES FOR SENSE INSTRUCTION 


Gate status one and gate status two are generated to gate the sense 
bytes onto DBI at ‘EB-1’ and ‘EB not 1’ respectively. The parity of 
the sense bytes may not be odd, therefore a parity generate signal 
‘gate sense parity’ is provided at each sense byte time. 


5406 FETMM 


(2/71) 


11-205 


CRT ATTACHMENT—Functional Units 
Card 2 (Part 1 of 2) 


11-208 Cond 6 


11-208 

(Not) CMD Rej 
SIO Clock 7 
10 
CRT Sel 


POSOOOSHHSHHHEHHEEOHEHHOEHCEHHHOSHE THO HERD MOOHAHEREEHEEEHH EE ROHEOEEHOOEHOEHHHESHSEHEEEEOTHOOOOSHCHOMEHCEHEHEHESESHHEOOHOHSES HOSEA OEOHSEERESOHSCHOHHHOHHOCHEEHEHOHHOHHOEEHOEEEESES 
SOSSHSAHSHESHOSHEHHSHHHEHHHEHHSEOHAOSEHESHEHEHE MACE SESE ESHEEAEARAARHERASSEAEHHHEHHHOHESEE HEHEHE HHHEHEHHEHHEMCEOEHHSSHESEHEEEESHEEESEEOEEESEHESSEPEOHOSEHHHOEHOHOHAESCHHHHSHHHOHESCHEOESECEELEOE 
POSHHSHHSHEHSHEHHHSESHEHHHHSHHOHHHHHEHHHHHRASHHHSEHEHHHSCHSEHHEHHHSHHSESEHOSHEHHSHEHSHESHSHHHOHEHHSHHHHOEHHSHEMOHHSHSHSSHHEHHHOSHHSHEHHSHESHSESSOHOHEEHPSHESHHESHOSHHEHHSHESHSSHEEEHEHHESAEHESHEHEE 
PAHHSHSHSHOHHHHHHHHHHHHHHEEHHEHOHHHHHHHRHMEHEHHSHHEOESEEHETEOHEHHSHHHOTHEHOHOOTHEL HHH TOEHSOEHHECOTOSE MECH SOE HHHSHEHHHOHEHHHOSHHEASEHHESEHHOHHHEOHEETHHOHEEHHSOHEHEEESEHOHELHALEEEOE 
COHSSHSHHSHHSHEHHHHEOCHEEHHHOEHSHSHHAEHHHEHEHEHEEHOHMEHESHEHHHEHEHEHEHSHEHHSHEHSHOHHEHOEHEHHSHHSHHHHSESHEHCHCHSHHOHEHSHHOHSMOHHCHEHSHSHSEHOHHSHESHOHRHEHARTEHSHSHSEHEESESHSEHSHEHSHHHAHSHHHSESHSHELESEOLEEESE 


Clock O 


(from 2265) 


7 CRT Ready 
System Rst 


SOHHHHHHOHHEHEEHHEHSEHHHHHEOHEESESEHSEHHHHSAEHRESHEHHESEHHEHESHEHHEHSHHSEHHEHOEHEHHHEHEHSEHSHOOHEHHOEHEHHESSHSEHHHOHHEEHHHHHHESHLOHETHEHEHEEHESEHEHESHOHHESEMEESEEHELESESESESEEELE 
COOH HOHOHHHHHHHHHHHEOHEEHSHEHEOHELOHHOHHHHOEOEHHESHHSHHEHEEH HORSE HSHHOHEHESH HEHEHE HHSHHHEHSEHEEHSHEHEEHAEHEEESESTHOHHHHHHHOEHSEHHOSHHHEHSHSSEPEHESESHOEHOHEOEALHHEPASHHOHHSSEOHHSHSEESEDS 
POSHSSHHSEHHSSHEHHHHSEEHHHOEHE HEHE HOHOHHHHEOEHEOHOEOOSEEHOTHOHHOHEEHESHEHHEHEOHFEHSES TESTO OHHEHETEEEOCEHTH HEHEHE HSEEEHEOHOHHHOHHHHEEESEEESHEHSHSESEHEHEHSEMDELSEEEEEEEOEEOLEEEOES 
SOOCHHHOHSHHHEHEHHEESEHEHOHHHSHOHHEHHOSHOSEHEHOHEHEHHHSEHHEHHOHECSHOSEOHEOHEHSHEHEHHHSEHEEOHHOEOSHESEHSEHHHEEHOSEEESOESOHHHEHSEEHHHHEESOCESEHOSEEEEOHOSOPESSCLEEESEEEEESEEEEEE 
PROHHHEESHHSHESEEHEEHOHOHEHOHESEEHOHHSEHETEOHOTOEEEHHHEHEOHOEESEEEHEHOHOESSOHSSESEHHSHEHOHEOEHOEHSEEHHOTHHSHEEHOHHSHEEESOHEHEOSESECHOHEHEESEHHECSSESHOCEOH HOPES EHOEHEEEEEEHOEHOESE 


EB Not 1 








Card Location O02 
ALD Pages CT301 thru CT311 


S!IO/RST Unit CK 
EB Not 1 













(Not) Counter Run 





11-206 (Not) Ackd 
Processor Run 





11-208 DBO 1 
11-208 DBO 5 


1/O Meter run © 


POSH HH HAO SESHOEEOHOHEHEOHHOSHSHOOEEOEHEHEOEOEEEEEEESOHSOHOOEOHOSECEEHEESCECOCRROOEOLES 
PROSE SCESEEOEESEEEHESHSOEOEO SOSH EH SHE SEO HESOOEEEHHOEESHOHEHE HS OEEECOOEO OCC EEOCECESE Cees 
COSHH SSSHEHSHSEEHEEOCESET OEE SHH EE SEHSHHEOOSEE SH SEEEHOHEHEESHOO HEHE OEO CHES EE CEECOE ORES REOne 
POSH EHHSEREHOEAEHE OTOH OOH OOHSOOEHEEHRESOOCEHEHOHECHEHHOOEOEOOEEEEOHOEEOOOECECEOEOOES BEE08 
POCOHEH OSE SEES HEHE HOH ES ES ESEOE SOHO OE EEO EHS OE HOEEEESOOOESEE SEES EESEOEOO EEO OCC OEEEDEEES BEes:. 








11-204 CRT Sel 





SHOSHHHHASHHSHHHHHESHEESEEEHEHSEHHSHESESOHSHSOHHEHEEESEEHEHOEHHESEEEESOHCOHHOEESEHEHESEEEOEES 
SPOHHEHOHESHESHHESHEESEEOHESHEOSOHOHEHHESESEHSOHEHSECHEHHEHSSOHHHSEHEOHHHEHEHHHOSSELEEESEOOESEE 
SPCOOHSESEHEHSEHHSSSHOHSEHSHEHEHSEHSHESHESEHHEHOHESOHSHHHSHHEHESHSHETHEMESHHOEEEEOHSEHEESHSSEHESDSEE 
SOOSSHSHHSSHHSHCHEEOHHSOEESHTHHHHSOHHEHOLESHEOCHEOE SHEESH EESEH SESH HESS EEOEESHHSESEESEHEEESECESES 
POTOESSHSEHHSSHHHSHEEHEEOHSHSHHESHH SEH SOOEHHHOEHHESEEHOTOHHESHEEEESEHSSOOSSOSSEHORESEHEOHEOE 





| : | , FL 
11-204 CRT Sel i x | 
ft Sys Reset | 
Clock O orf 


11-206 (Not) Cmd Reject 
11-206 (Not) Write 
11-208 Condition 6 


11-206 Ackd 


5406 FETMM = (2/71) 11-206 





LSR Gate 


Note: Jumper added when 
LCD and CRT on same 
system. 


+tie point _* 


] a [LLSR Select 7 
Clock 2 A | 
11-204 CRT Sel ] - @ 
SNS i 
LSR Select 3 
11-208 Cond 6 La A —<c 
_LSR Select 6 


LIO 





Samp DBO ees. 
A & 
Sys Rst . 
ORE 
CT331 
A 
afeka Pri Req Ackd 
| Clock O al EL 
System Rst : 
Clock 3 A ony 
CT331 
11-204 
LIO Reset 
Clock 6 Start CRT 
> | Timing 
[p+ 


COCO O OEEHHEHEHEOOEEEE HEHEHE SESE E HSE SOHO HOO OEEESHOOEEOOOHOE EEO OESOOSEH HOSE SOTHO OE EEE HOT OT HOES HEELS EHO HOES OO OTH OOOO HOSES EHH OOOO HOO SOT HOEOSEOO HOE OEEEHOEEHEOEHOEO EHH HOE OHHOHEHEHSOOHEOOEEOE 
COSHH AEHEHSESHEHOHSHHHHSSHHSEHOOOEHHHEOEHSESOH OHHH SEHOEEOHOOHEEEOSHHHHEHHHOOEEESEHOESHEEEH HOE SHHEOEHHOEHEHHSHH HOE OHOSOCEHHHEHHHOHEEHEOSHEHEHEEHEEESEHEHEEEHHSEEOHEHOHEHHOOESEH OSE HOHE HEO HEHE EHO OEOD 
SOSSHSHOHEHEHOESHHHESHHHSHHSHHSHHT HE HEHHESHHSHSHH OHHH EHHOSOOTETOEHHHSHEHSEHSHHHEHESEEHEE EHH HEHOHHOHHEHHSOHHHESSOHEHHHHEHHEEHHHHESE SHH OHEHOHEHHOHEHOTEHETEHHHOHEHEHHESEHHOHH HEHE HHEREEOHOEREHOO EOE 
SPOHSSSHOSEHHHHHHHSEHESHESHHHSHHOOHSEHSEHOHHESEHSHHHHHHOHOEEHHOSHEHHOHSEHOSHSHEORESES OHO SEHHEHOHHHHOHSHHHHHER HEHEHE SEHREHHSHOHHHHHHSESHHHHHHSEOEHHOHEHESHEHHSESEHHSOHHHOHESESEHHOHHHE HERERO CERERO EE OOOOE 
COOOO SOSH HHHHEEHHES HH OHSOHROHHHHEHSHHHEHEHESHEOSHHSHEHSHOSHSHHSESSESHEHH HEHEHE HESESHHHOHEHEHHSHOHHHEHHHHOHEEHHHHHHEHEHEOHEHHHOHEHHHHHEHOHOHSHSEHSHEHHEAEHHEEHHEHHHHHHHEHHEHHHSEHSEHTOHOTEHOHEH OOF CHEESES 


11-208 DBO Par Error 


1/O Condition A 


CT311 


1/O Condition B 


FL 


Sys Reset 


Clock O OR 


CYCLE STEAL REQUEST 


The ‘write’ latch is set when a CRT start I/O display instruction is 
decoded. The ‘write’ latch is turned off by a start I/O halt instruction 
or by the CRT display station going to a (not) ready condition (power 
off). 





@ cycle steal requests are made when: (1) the CRT ‘write’ latch is on, 
(2) ‘counter run’ is inactive, (3) the display station is not timing out 
for a restore or retrace delay, and (4) ‘processor run’ is active. 


‘Set LSR address’ gates the ‘not 6’ and ‘not 7’ latches during the 2nd 
cycle of a load |/O instruction. LSR hi address is on the DBO at this 
time. | 


@>))‘1/O meter run’ is on if the ‘write’ latch is on and conditions for 
‘process run’ are met. 





ERROR DETECTION 


@ ‘command reject’ and ‘I/O attention’ indicate conditions of the CRT 
display unit and CRT attachment status. ‘Command reject’ latch is 
set if: 





1. The ‘write’ latch is set and a load 1/O instruction attempted. 

2. The ‘write’ latch is set and a start I/O (display) is attempted. 
Start |/O halt instruction is always executed. 

3. A start I/O display instruction is attempted and the display 
station is not ready (power off). 


f ® ‘1/O attention’ latch is set if a start I/O instruction is attempted and 
the display station is not ready. 





co The ‘CRT ready’ line from the 2265 is sampled with clock zero. 
The ‘display ready’ latch is set if the ready line is active. A single shot 
stabilizes the turn on of the ‘display ready’ latch if the ready line is 
erratic. 





fe 1/O INSTRUCTION 


© This logic is active when the CRT attachment is decoding an I/O 
instruction. 


@ ‘Gate parity check’ is a condition to set the ‘parity error’ latch if the 
DBO parity is even during the following times: 
1. An I/O instruction I-OQ cycle 
2. A start I/O instruction I-R cycle 
3. Anl/Ocycle 
4 A load I/O instruction during EB not 1 cycle 


CRT ATTACHMENT -—Functional Units 
Card 2 (Part 2 of 2) 





LSR SELECT 


> The CRTAR (LSR) is addressed with LSR select lines 3 and 6 if the 
ledger card device is not installed on the system printer. If ledger card 
is installed, CRTAR is selected with LSR select lines 6 and 7. The LSR 
is selected for: 


1. A load I/O instruction to load the starting address of the data 
field into the LSR. 

2. An1/Ocycle to modify the LSR address plus 1 for each I/O 
cycle or to subtract 960 from the updated address. 

J A sense instruction to sense the address in the LSR and transfer 
the information into core storage. 


e ‘Pri select’ latch is set when the CPU acknowledges a CRT !/O cycle re- 
~ quest by returning DBO 1 and 5active at clock 8 time. ‘Ack’‘d’ is set at 
clock 0 time to extend LSR selection into the next adjacent CPU cycle 
for LSR address increment checking and to modify the LSR address. 
‘Ack’d’ ANDed with clock 6 starts the CRT timing cycle. 





1/O CONDITION A AND B CONTROL 


[/O condition A and B are used together to indicate to the CPU 
(1) the status of the CRT attachment when an instruction is issued 


to it, and (2) error conditions during an operation. 
1/O Condition 


1/O Attachment Condition 
| worsens Conston OS® 


Incorrect DBO Parity ea 


O Byte Not Correct ae 
Sense Instruction aoe I 


SIO Reject Instruction 

or LIO 

Instruction | Accept Instruction Eee a 
1 


Condition Not Met | Oo 

a 

Incorrect DBO Parity Pad 
Correct DBO Parity po | 
















CPU Reaction 


Processor Check Stop | 
Continue as Normal 


BRO820 
















1-O. Cycle 
of Any I/O | Correct 
Instruction | DBO 








Correct 





Byte 











Test 1/O 






Condition Met 
ee 











5406 FETMM 


(2/71) 


11-207 


CRT ATTACHMENT—Functional Units 
Card 3 (Part 1 of 2) 


nant 





















5406 FETMM (2/71) —‘11-208 















2 3 
Card Location P2 
ALD Pages CT201 thru CT241 
| HE fie 11206 ys 
DBO i gi HEE Any I/O Inst 
| 0 12 3 4 5 6 7 P iret 
11-204 (Not) DBO Parity Error Latch i HHH ‘ 69 eH : ; CRT Address 
x seise chan: ot 
| CT 201 a (Not) 6 a sith Not 2 
DBO Register site Nets ae 
SIE | (Not) 4 HE C1241 , 
pol fztsyafeyet ze ED ton 3 4 | & ssid 
HE Not) 2 ae 
. aenes a 7 : 7 Beh 11-204 Set Cond 6 Reg 
DBO Parity eH = Clock 3 git 
Error sorts 11-206 Ackd 333 
HH Sample DBO HE Sy Sreriiteeet 
BH rece 11-204 Reset Cond 6 Reg 
A ie see eeeeerreviceccterces te teehee aa CT 2A... socsersscetarser 
iE o A FL Clock 1 =) 
ates 1 | 11-206 A Restore 
. geese - ckd Sample DBO 
11-204 Set D Register 33333 A 
re 35335 A PB FL 
| cT221 a 
Hi : CT 211 | 
Ore Sia eel LP He 7 ora 
11-204 Gate Status 2 2. (Even) Unit — . HHH 
ate Status | Check. 30 18s 7 
Clock 6 Kx 7 Check :::: 
: 11-206 Ackd aan ee 
11-206 Write ‘commence | HE «11-206 
11-204 Gate Char 11-206 SIO/Rst Unit Ck | «Set LSR 
Gen SNS 1 : ass Address 11-206 Ackd 
11-204 Step Disp ss = System Rst SHH Clock 0 
11-206 CSR) 11-208 Clee 3 11-206 (Not) Pri Sel 
11-208 RST Disp 3 coe ‘ : Check Rst HE 11-206 (Not) Cycle Steal 
11-208 Unit Ck, 17-308 a ‘ 11-208 (Not) 193 
11-206 Disp Modify Sots seo3e Sys Rst 
(Not) Ready ae 6 ( wel Gace 3 == Sample DBO 
11-206 Ackd © ff 11-208 y >» —l positt! HEI = Svs Ret 
ey | Modify 1 Beal gett CT201 
7 3 mea | D Bit 2 Pee conics ado et cauundu sud im ecuwisau ewan toua wok basi War iaen nue ane aie dada a ii iain bed ieee eee Co cveecovvesevecsvecesce 
11-204 Gate Status 1 4 —| DBit3 ) Eee aleseeeceeeecasceeesceeateaeree eaetaeatestegetaasteeeesseeasteeeasttacceeeeeeeseaasceeeeegeeausteeeeaqzeustseeniteaaaseeeeseceseacteees enecteeeieeeas uneesdisarstceeeeeeactsreee sett suceeestsgaeeeeraasraueteintt 
| o., ie HEE Clock 5 SHEE 
6 —| DBItS5L__ Et: HH 
DBI Reg Bs 7 —,DBit6 cT22 nee sit 11-204 LIO Rst Sys Rst Reset 
eset DBI Register | Note: Line names | HE 9098 tte: isp (7 
ssizs_ 1 4- oss 5 Reset Dis | O 
(Clock 0,2,4,6) | change to 2265 HE Restore HE 11206 Ackd | E 2265-11 
PPP ree oyu, | Ee onl 
ee 11-204 Hi 11-206 A Binary Subtract i22 11-208 (Not) 193] A | 
Bre cna EE ack fT He a! 


eeocece 
eeece 


= PC| (Even) ee eee 


a 5 

: 11-206 Pri Sel A | PL HH Clock6 oT | Ty 

; Clock 0, 2,4, 6 | HHH Ser 
Specie ce 


eecce 
eoccee 
eocee 
eoeceoe 
eeeceo 


i | 
clock 4 a 


eoeoe 


CT211 


eeeoe 


eocee 
eoooe 
eecoe 
evoos 
eevee 







CT211 


23:3 Clock 2 


eevee 
eooee 
eevee 
eoooe 
eoeee 
eevee 
eevce 
covece 
eevee 
eanee 


(Not) Counter Run 


2 11-208 


Start 
Retrace 
i232, (Not) Restore 


Delay 
eecut A 
Hf 11-208 65 latch A 
Modify 1 ::::: 


eevee 
eevee 
eeeve 
eooce 
evoce 
aaace 
ev0oese 
esese 
eoeos 
eacce 
evocee 
eoveon 


DBO REGISTER 


@ Receives data and control information from DBO. 





@ Output is parity checked. 


© Latches up (retains its status) when a DBO register parity error 
is detected. 


o Output is gated into other CRT attachment logic. 


DATA REGISTER (D REGISTER) 


e lIsset during a start I/O I-R cycle or during an I/O cycle. 





@ Status may be sensed with a sense instruction. 


o Positions 1 through 7 are gated to the display station and contain 
data for the CRT display. Position 1 is the cursor bit, 2 through 7 
are data. 


e Output is parity checked. If an error is detected, unit check latch 
is set. 


DBI REGISTER 


@ Output is parity checked. A parity bit is generated if one Is 
needed. | 





@ Is reset at sample DBO time during clock O, 2, 4, and 6 time. 
The ‘parity bit’ latch is reset at each phase C time. 


@ Input may be from three sources: (1) ‘D register’ output, (2) CRT 
status, and (3) constants generator, modify +1, -192 and —768. 


3 LSR ADDRESS 64 and 960 INCREMENT CHECK 


The data field for the CRT display station may start at any hexa- 
decimal XX01 address. (XX is any core address that is 960 bytes 

less than maximum core capacity.) The CRT attachment must retain 
an indication of where the data field was started in order to check 
for each increment of 960 above the starting address. This indication 
is needed in the attachment to signal the end of the data field and 
perform a restore cycle in the display station. A hexadecimal count 
of 960 requires more bit positions than a hexadecimal byte contains; 
therefore the two least significant bits of the LSR hi address are used 
to extend the count to include 960. 


CRT ATTACHMENT —Functional Units 
Card 3 (Part 2 of 2) 


Format of the bit value assignment of the LSR address: 


/«———— LSR Hi ————>+ «———- LSR_ Lo —____} 


Bit Positions [oO] 11 2/3}4}s5{6{7{ol1|2{3]4[5j6[7| 
oO 
N 


Not used —~I 


ooctrtrna ~ 
™ 
- or checked 


; + AN 
Bit Value oO Ww 


N oO 
“= WH 
Lo ON 








Used to indicate increments of 64 when positions 
2 thru 6 = O and position 7 = 1. Sets 65 latch. 


Part of 961 increment check. Positions O and 1 in combination = 
192 (position 7 must be active for a count of 193). Sets 193 latch. 


Checked when the LSR hi byte is on the DBO. 512 and 256 in combination = 768. 
If 193 latch was set during LSR lo time, bits 6 and 7 are exclusive OR’ed with not 6 
and not 7 latches for 961 indication. 


BRO821A 


Note: The data field starts on a XXO1 boundary, therefore the LSR 
address indicates 65 for an increment of 64 or 961 for an increment 
of 960. 

During a load I/O instruction when the LSR is loaded with the 
address of the display data field, two latches (‘not 6’ and ‘not 7’) are 
set or reset together to retain the binary boundary (256 or 512) at 
which the data field address started. The ‘not 6’, ‘not 7’ latches are 
set during the second cycle of the load 1/O EB cycles when the LSR 
hi portion of the address is on DBO. 

The conditions to set-reset the ‘not 6’, ‘not 7’ latches are as shown: 





O = latch reset or inactive condition 
1 = latch set or active condition. 


BRO822A 


_ The 960 count is spread across two LSR address bytes. Each byte 

is on the DBO at separate times. As a result, the 960 increment check 
must be made at two different times. During the time the LSR lo 
address byte is on DBO, it is checked for an increment of 192. If the 
192 check is positive, the 193 latch is set to gate a check for 768 in 
the LSR hi byte. During the time the LSR hi address byte is on the 
DBO, gated by the ‘193’ latch, the DBO lines are exclusive O Red (OE) 
with the ‘not 6’, and ‘not 7’ latches to check for an increment of 961. 














The conditions needed to set the 961 signal are as shown: 


and ‘193’ latch = 961 


BRO823A 


During the time the LSR Io address is on DBO, DBO lines 2 through 
6 are checked for zero and line 7 is checked for 1. If lines 2 through 6 
are zero and line 7 is 1, this indicates an increment of 64. The ‘65’ 
latch is set to gate the CRT attachment for a retrace operation. 


CRT ADDRESS—CONDITION 6 REGISTER 


These lines are conditioned from the DBO register. The CRT address 
is indicated when DBO bits 0 through 3 equal 1001 (9). 

‘Condition 6’ register is set when bit 6 of the O byte of an I/O in- 
struction equals a 1 (active state). |/O instructions for the CRT have 
only two options (i.e.: start |/O display or halt). ‘Condition 6’ regis- 
ter gates the attachment logic for one option when it is set and the 
other option when it is reset. 


CONSTANTS 
This logic: 


@ Provides constants to increment or decrement the LSR address. 
+1 is generated each I/O cycle to increment the LSR address to 
the next data character in the display field. -192 and —768 decre- 
ment the LSR address when the end of the data field is indicated. 
—192 and —768 modify the LSR Io and hi respectively. 


@ ‘Binary subtract’ is active during the time —192 and —768 are 


generated to cause the ALU (in the CPU) to subtract. 


RESET DISPLAY 
This logic: 
@ ls part of an interface to the 2265 II 


@ Resets the display unit beam to the upper left corner of the CRT 


e Starts a 288 (approximately) microsecond delay within the CRT 
attachment to allow time for the CRT beam to restore or retrace 
e Starts a reset display when: 


1. A load 1/O operation is issued to the CRT. 
2. ‘System reset’ is active. 
3. The LSR address has incremented 960. 


5406 FETMM = (2/71) 11-209 


Chapter 3. Operations 


INTRODUCTION TO OPERATIONS 


Chapter 3 contains detailed flowcharts and timing charts of the operations 
performed by the CRT display station attachment. 


Flowcharts 


The flowcharts contain three levels of information. By reading down the 
heavy dark lines, the reader can learn the major objectives of the operation. 
The second level of information is obtained by reading the information in 
the boxes that branch off the heavy dark line. The information that is con- 
tained in each block in a heavy dark line is explained in the blocks that 
branch off from it. The third level of information is contained in the note 
blocks (open ended blocks) that branch off the second level blocks. Infor- 
mation in these blocks is intended to explain why an action has been 
performed. 


Timing Charts 


The timing charts in this chapter are to be used to supplement the informa- 
tion found in the flowcharts. 


CRT ATTACHMENT- Operations 
Introduction to Operations 5406 FETMM = (6/70) 11-301 


CRT ATTACHMENT- Operations 
Load I/O Instruction Flowchart 


Start 
Load !/O Operation 






‘LIO’ interface line 
active. 










A 1/Q Cycle 
: QO byte of instruction 
on DBO. Decode 
device address. Check cT311 
| CT241 
Decode CRT address 
(bit 0-3 of QO byte = 9). 
DBO parity valid no 
CT201 
> Yes Latch DBO register. 


CPU takes I-H1 (or 
1X1) and I-L1 cycles 
to develop effective CT121 CT311 
address. These cycles 

are ignored by the ‘CRT select’ 


GOT attachment: 1/O condition A and B 


End Operation 


CT321 





N 


O 
1/O Condition B CT121 


Reset ‘CRT select’. 


‘Command reject’ 


ee 
+ 


CT311 


CT311 


1/O condition A 


¢ End Operation 





2 
EB 1 Cycle (LSR Lo) 









CT331 
Select LSR lines 

3 & 6 (without LCD), 

6 & 7 (with LCD). 








A retrace delay is 
started to provide a 
time-out for the CRT 
to restore the CRT 
beam. | 










EB Not 1 Cycle 


LSR (Hi) address on 
DBO. ‘Not 6’ and 
‘not 7’ are exclusive 
OR’ed with DBO 
lines for set conditions. 










DBO parity 
valid | 


Latch DBO register. 


CT101 


‘LIO reset’ 
‘Set LSR address’ CT201 


1/O condition A and B 





Set ‘reset display’, 
‘retrace latch’, and 
‘not 6’ and ‘not 7’. 


End Operation 





Reset: 
‘CRT select’ and 
‘restore’. 


End Operation 


5406 FETMM = (2/71) 11-302 





Pe 
tA) 


i-Q EB Not 1 


Clock}5 6 7 810 12 3 4 5 6 7 8]0 123 4 5 67 810 123 4 5 67 8/0 12 3 4 5 

Signal Name Logic CPU I-H1 or I-L1 Cycles 

ero 
EB Not 1 


CRT Address on DBO CT241 


m 
w 
—_ 


g/g 
— 
Go 
= 


O 
= 
S 


O 
aul 
OO 
S 


— 
= 
NO 
—_ 


Data Parity C 


+ 
—_ 
N 
— 


CRT Select 


O 
a 
- 





1/O Condition A or B 


O 
=| 
= 


LSR Select (DBO Lines 3 & 6 
or 6 & 7 with LCD) C1331 
: (if busy-write 
10 | Command Reject intch’cetl CT321 
11 | LIO Reset 
12 | Start CRT Timing CT33 


13 | Reset Display _ CT21 


Set LSR Addr (See 6, 7 latches 
if corresponding DBI line active) 


> Reset 6, 7 latches CT201 


(Lo) 





O 
= 
S 


288 usec 
delay 


ale 


4 





O 
= 
= 


CRT ATTACHMENT—Operations 
Load I/O Instruction Timing Chart 5406 FETMM (6/70) 11-303 


CRT ATTACHMENT -—Operations 
Test I/O Instruction Flowchart 


Start Test 1/O 
Operation 


‘TIO’ interface line 
active. 


O byte of instruction 
on DBO. 


CRT attachment is 
tested for busy or 
check condition. 


Bit 6 of the QO byte 
‘N’ field determines 
which test is made. 


6 = 1 test for busy. 
6 = O test for check. 


Condition 6 register 

in attachment is set 
with DBO 6 = 1. 
Condition 6 register . 
determines which 
condition is tested 
within the attachment. 


1/O condition A indi- 
cates condition tested 
for was met (CPU 
branches). 


1/O condition B indi- 

— cates condition tested 
for was not met. CPU 
goes to next sequential 
instruction. 





CT311 


‘1/O instruction’ active. 


CT241 


Decode CRT address 
(bit 0-3 of O byte). 





CT121 


‘CRT select’ active. 





Latch DBO register. 


CT331 


1/O condition A and B. 


End Operation 












2 3 
DBO 6=1 Yes 
(N field bit 6) 
CT241 
CT311 


Test for busy condition. 







Unit check 
or 
not ready 


Yes 






‘Write’ latch Yes 


on 





1/O condition A 
1/O condition B 





\/O condition B 





CPU takes | cycles to 
develop branch address. 
These cycles are ignored 
by the CRT attachment. 





End Test 1/O 


Operation 








5406 FETMM = (6/70) 11-304 


CT311 


1/O condition A | 





tA 






Clock 


No. Signal Name 
pi fre_fereny 













2 


Data Valid on DBO CT201 Ce 

fs [omen oral 

oe CRT Select CT311 Lo 
Condition Register 6 

6 (if test for busy) CT241 Lo 

1/O Condition Aor B. |CT311 ae 
Command Reject 

ae (if parity error) CT321 Et 





CRT ATTACHMENT-—Operations 
Test I/O Instruction Timing Chart | 5406 FETMM (2/71) 11-305 


CRT ATTACHMENT-Operations | 
Sense I/O Instruction Flowchart 








Sense Operation 


‘SNS’ interface line 
active. OQ byte of Op 
code on DBO. Two 
bytes of attachment 
status may be sensed, 


or 

the CRT LSR content 
is sensed. Bit 6 of the 
Q byte ‘N’ field deter- 
mines which of the 
above is performed. 
Bit 6 = 1: sense status. 
Bit 6 = 0: sense LSR. 


Condition register 6 
in attachment is set 
when DBO 6 = 1. 

Condition register 6 


_ gates sense status. 


(Not) condition 
register 6 gates sense 
LSR. 





CPU takes I cycles to 
develop effective 
address. CRT attach- 
ment ignores these 
cycles. 


EB 1 Cycle 
First sense byte. 


If condition register 6 


on: sense status. 


(Not) condition register 
6 sense LSR Lo. 





CT311 


‘1/O instruction’ 


CT241 


Decode CRT address 
(bit 0-3 of Q byte = 9). 


CT201 
No 









DBO parity valid 





CT121 


Set ‘CRT select’. 






DBO line 6 = 1 


CT311 


1/O condition B 


CT331 


‘LSR gate’ 





CT201 


Latch DBO register. 


1/O condition A and B 


End Operation 


Set ‘cond reg 6’. . 


© 
4 
NO 
= 










Yes No 


Condition register 6 


set 
‘Gate status 1’ 
Gate 8 status bits onto 
DBI. 





~Second sense byte. 





EB Not 1 Cycle 








If condition register 6, 
set sense status. 





(Not) condition register 
6 sense LSR Hi. 





CT331 


‘LSR gate’ 








No 
Condition register 6 
set 


‘Gate status 2’ 


Gate 8 status bits onto 
DBI plus parity bit. 











Reset 
‘cond reg 6’ and 
‘CRT select’. 


End Operation 


CT331 


| Select LSR. 


CT331 


Select LSR. 


5406 FETMM 


(6/70) 


11-306 


4 weey “> 


{— |-Op EB 1 EB Not 1 


1Q 
Clock |5 6 7 8/0 123 4 5 6 7 80 123 4 5 67 810 123 4 567 810 123 4 5 
Signal Name 





Q 
at 
Oo 
= 


a 
= 
iS 


O 
= 
~ 


CT301 


O 


ata Valid on DBO 


OQ 
- 
i) 
= 


O 
re, 
> 


Data Parity 


CRT Select eee 


Condition Register 
6 (if sense status) 


1/O Condition A or B 


QO 
| 
NO 
= 


OQ 
—| 
[ 


Command Reject 
(if parity error) 


O 
4 
WO 
NO 


Status byte 1 Status byte 2 


- 
O 


LSR Select (if store LSR) |CT331 


N 
G) 


O mj}m 
Oo OO 
NO —_ 

O 

—| 

GO 

— 

—_ 


O 
= 
NO 
—_ 


ate Status Bytes 


Bl Register Reset CT331 
DBI Parity Reset CT201 


oud 








CRT ATTACHMENT—Operations 
Sense I/O Instruction Timing Chart | 5406 FETMM = (6/70) 11-307 


CRT ATTACHMENT—Operations 


Start I/O Instruction Flowchart (Part 1 of 2) 


Start |/O 


Operation 


l-Op Cycle 





A 1-O Cycle 


Q byte of instruction 
on DBO. Check DBO 
parity. Set condition 6 
register if DBO 6 = 1. 
Condition register 6 set 
indicates a CRT write 


“operation. Condition 
register 6 reset indicates 
a halt operation. 1/O 
condition A-B indicate 
CRT attachment 
acceptance or rejection 
of the instruction. 
















‘SIO’ interface 
line active. 


CT311 


‘1/O instruction’ 


CT241 


Decode CRT address. 


Clock 5 






DBO parity 
valid 







QO 
anf 
i) 
2 


Yes Latch DBO register. 


CT121 


‘CRT select’ 


OQ 
— 
= 


1/O condition A and B 


End Operation | 





CRT address 
recognized 






“ i 
—| 
= 


1/O condition (not) A 
and (not) B 


End Operation 






CRT attachment Yes 
busy or not 


ready 








No Set ‘command reject’. 


O 
a 
WO 
> 


| R Cycle 


11-309 







i 7 






DBO line 
6=1 


CT241 
Set ‘condition reg 6’. 


CT321 


Set ‘write latch’. 


CT331 


Set ‘cycle steal req latch’. 


CT311 


1/O condition B 







CT201 






DBO parity 
valid 
CT241 


Latch DBO register. 


CT311 


1/O condition A and B 


End Operation 












Set ‘D register’. 
Reset ‘CRT select’ 
and ‘cond reg 6’. 








and ‘cond 6 reg’. 


5406 FETMM 


CT311 


1/O condition A 


CT121 


Reset ‘CRT select’ 





(6/70) 


11-308 





No Write latch 
set 


Yes 


steal request. 
CRT attachment 











End Instruction 


Cycles 





Set: ‘unit check’ 


(unit check light is 
on in CE panel.) 





CRT ATTACHMENT—Operations 


Start I/O Instruction Flowchart (Part 2 of 2) 







Request a | 
cycle steal. 


CPU honors cycle 


continues to request 
a cycle until the CPU 
honors the request. 





For cycle steal cycles 
set ‘CSR’ latch. 





Request bit 5 
Priority clock 3 
13th I/O priority 












Clock 8 CT331 


CPU acknowledges 
cycle steal request by 
returning DBO line 1 


and 5 active. 


Set ‘pri select’ latch. 





Clock 0 CT331 


Set ‘ackd latch’. 


CT331 
Clock 4 CT221 


Select LSR Lo. Modify 
LSR address +1 - DBI 
7 active. 


Clock 5 CT221 


Data byte on DBO. 
Set ‘D register’, condi- 


tion CRT data and 
cursor lines. 





Clock 6 


Start display on CRT 
screen. 


D register 
parity valid 









Yes 















LCD) 


Select LSR (lines 3 
and 6 without LCD 
lines 6 and 7 with 





a 
Po 





Clock 7 


LSR Lo address on 
DBO. CRT attachment 
checks LSR address for 


each increment of 64 
and 960 (actual LSR 
address equal 65 or 961). 










No _ Yes 
DBO 2 thru 6 
=0, DBO 7=1 







Clock 7 CT211 


Set ‘65 latch’. 


DBO O and 1 
= 1 









Clock 7 


Set ‘193 latch’. 





Clock 8 CT331 


Reset ‘pri select latch’. 


Clock 8 CT331 


Clock 1 
Reset ‘pri select latch’. 
LSR H: address on 


DBO. OE ‘not 6’ and 


Clock 3 CT331 ‘not 7’ latches with 





CRT Display 


Flowchart 
11-314 





DBO 6 and 7. 





Reset ‘ackd’ latch. 









‘961' 
conditioned 


Display character when 


‘counter run’ falls, set 
CSR latch. 






Clock 2 CT211 
a 


Clock 3 
Reset: ‘65 latch’ 


‘193 latch’ 
‘ackd’ 





Display last character 
on CRT screen. 


11-314 


No 





Inhibit further cycle 
steal requests. 





Retrace latch prevents 
‘counter run’ from 
dropping at 12 or 15 
counts. Allow counter 
to step for 192 counts. 








Counter = 192 
(288 usec.) 





Yes 


CT101 


Reset ‘retrace’ latch. 





‘Restore’ set 





11-314 


Yes 






CT331 


When ‘counter run’ falls 
request a cycle steal. 


CPU acknowleges cycle 
steal request with DBO 
line 1 and 5 active. 





Clock 8 CT331 


Set ‘pri request’. 





Clock 0 CT331 
Set ‘ackd’ latch. 

Clock 2 CT101 
Set ‘retrace’ and ‘rst 
display’. 

Clock 4 

Clock 6 CT221 





Modify LSR address 
-192 -768 


‘bin sub’ active at clock 
5 and 7. 










Clock 8 CT331 


Reset ‘pri select’. 


Clock O CT331 


Reset ‘restore latch’ 
Reset ‘ackd’ latch 


5406 FETMM = (2/71) 11-309 


CRT ATTACHMENT- Operations 


. 5406 FETMM (6/70) 11-310 
Start I/O Instruction Timing Chart (Part 1 of 3) 





a 


1/O Cycle(s) 


Clock 6 7 8|o 23 45 67 8 234567 8 2345 67 8 


Signal Name Logic 


S!O CT301 


CT121 


CT301 


Data Valid on DBO 7201 
Sample DBO Parity CT121 


CRT Select C1311 


> 





Condition Reg 6 (if write op) CT241 


1/O Condition A or B CT311 


Check Reset . CT301, 


(if display (Not) ready or 


Command Reject second SIO and ‘write’ active) 


CT321 


Reset Cond Reg 6 CT241 


Set Cond Reg 6 (if write op, 





DBO 6=1) . C1241 


Write Latch (Write Command) CT321 
Cycle Steal Request | | CT331 


> Start 1/O Write Operation and First Cycle Steal Aeduesk 







QQ. 


Drops With Next 
SIO Command. 


» Request cycle steal cycle until CPU honors request. 


-_ _ | wz 
NO | — 


©. 
Bc 


&. She? 
SE 








0123 45 67 8 


Clochk}O 123 45 67 810 123 45 67 830 123 45 67 8 


Pri assign (DBO 1 & 5) 


Signal Name Logic 


CT331 


Cycle steal request 


Data on DBO CT20 LSR Hi 


_ 





Data LSR Lo 


Sample DBO 


a 





Vv 


ri Select CT331 





ri Req Ack’d CT331 


ee Eee 
ad * 
i ae 






SR Select CT331 






N 


Data on DBI CT231 


O 
= 
S 


+1 Lo O Hi 


et D Reg. CT331 





wn 


tart CRT Timing CT331 






O 


ata Reg to CRT CT221 






Test DBO for Retrace CT211 (Clock 7) 
65 latch (if DBO 2 thru6=0 mE 
DBO 7 = 1) CT201 

193 latch (if DBO 0 and 1 CT201 

each = 1 


14 | Test LSR for Restore (961 Count) |CT201 


Restore latch (if Hi plus 


Lo = 961 CT211 


O 
az 
© 
= 


Retrace latch 


aah = 


1/O Cycle - Modify CRTAR Address Plus One 


CRT ATTACHMENT -—Operations 
Start I/O Instruction Timing Chart (Part 2 of 3) 





5406 FETMM 


(2/71) 


11-311 





Clock]2 345678 


Signal Name Logic 


Data Valid on DBO CT20 


0123 45 67 830 123 4 67810123 45 6781012345 67 8 


| 
ete 


Cycle Steal 


Request e=> A cycie steal request is made during this interval to modify LSR -960. 


ou 


Data LSR Lo] LSR Hi Data LSR Lo| LSR Hi 


Set ‘Pri Select’ latch CT33 


= 


Primary Select CRT CT33 


om) 


Pri Req Ack’'d —{CT33 


Dataon DBI CT23 


Set D Reg 


7 | Start CRT Timing CT33 


"~U 
u~ 


+1 Lo +0 Hi P -192 Lo -768 Hi 


A 





Data Reg to CRT CT22 


—_, 


© 
4 
—_ 
NO 
=—_> —_ -_ —_ —_ 


Strobe for 65, 193 latch set CT30 


65 Latch if DBO 7 = 1 and 








DBO 2 thru 6 =0 eee 

193 Latch (if DBO O & 1 active) {CT201 

Strobe for Restore CT211 

3 | Restore Latch CT211 
Retrace Latch CT101 273 usec to 288 usec 

15 | Step Display CT101 


7 | LSR Select Lines 3 & 7 CT33 


a 


Cycle Steal Request — LSR address = 961 — Subtract 960 from LSR address 


CRT ATTACHMENT -—Operations | 
Start I/O Instruction Timing Chart (Part 3 of 3) 5406 FETMM (2/71) 11-313 


CRT ATTACHMENT—Operations = | | 5406 FETMM (2/71) 11-314 
CRT Display Flowchart pate 





Start CRT Display 


Set ‘65 step trigger’. 





CT101 



















Display character on 
CRT screen that is in 
the ‘D register’. 





CT331 


Start CRT timing. 


Set: 
‘Counter run’, 
‘character control’, and 


Reset ‘character control’. 






CT101 


Set ‘65 step’. 





sana 
ee 


A ‘step display’. 
. Condition further cycle 
steal requests. 
Condition CRT index 
gate: Condition ‘CRT step 
display’. 
Index counter each ; : ; 
11-309 11-309 eee 
| Reset ‘65 step’. 
2 | 
: Reset ‘step display’. a 


11-309 









Gate interface line 
‘start Character 
generator’. 


D register pos 1 = 
0 










15 usec 
counter = 10 © 


12 usec 
counter = 8 


Retrace latch 
set 


seas, 





| x One division = 1.5 microseconds (one CPU cycle). 


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Logic Only for restore cycle 
ee ‘ Silas 
[+ [seroma ‘enon 
ry ee ERENT isa SSE a TEESE ee ae : apr 3 a ae = 
eigenen baer ve estar eae ame ra 


S50 
Ps 
“ 





aa TN eeeeeSeeeSFSNNSOOOOFESE 








CRT ATTACHMENT-—Operations | | 
CRT Display Timing Chart | | 5406 FETMM (2/71) 11-315 


Index. 


A Register Controls 4-040 
A/B Register Parity 2-090 
Access Panels 1-601 
Add Characters Timing Chart 5-084 
Add Decimal Diagram 5-104 
Add Logical Characters Diagram 5-082 
Add Logical Characters Flowchart 5-080 
Add to Register Diagram 5-062 
Add to Register Flowchart 5-060 
Add to Register Timing Chart 5-064 
Add Zoned Decimal Diagram 4-104 
Add Zoned Decimal Flowchart 5-100 
Address Marks 8-104, 8-224 
Addressing Scheme Table 1-102 
Advance Program Level—CPU 
Advance Program Level Flowchart 5-200 
Advance Program Level—Data Recorder 
Description 10-115 — 
Error Conditions 10-115 
Flowchart 10-304 
Instruction Format 10-115 
Parity 10-115 
QByte 10-115 
Timing Chart 10-305 
eine Program Level—Disk 8-108 
Advance Program Level—Keyboard-Console 7-117 
Advance Program Level—Printer and LCD 
Application 9-106B 
Error Conditions 9-106B 
Description 9-106B 
Flowchart 9-304 
Instruction Format 9-106B 
Parity 9-106B 
Q Byte 9-106B 
Timing Chart 9-305 
Alter SAR Diagram 5-232 
Alter SAR Flowchart 5-230 
Alter SAR Timing Chart 5-234 
Alter Storage Diagram 5-242 
Alter Storage Flowchart 5-240 
Alter Storage from Keyboard 1-207 
Alter Storage from Keyboard Flowchart 7-314 
Alter Storage Operation—Keyboard-Console 7-313 
Alter Storage Procedure 1-207 
Alter Storage Timing Chart 5-244 


5406—Index 


Alternate Program Load Device 1-210 
Interface Circuits 1-210 
Maintenance 1-211 
Programs 1-210 
Bootstrap Loader 1-210 
Diagnostic Control Program 1-210 
Tape Loader 1-210 
Setup 1-211 
Tapes 1-210 
Alternate Track 8-104 
ALU 4-010 
ALU Controls 4-014, 4-016 
ALU P Bit Generation 4-012 
ALU Parity 2-100 
APL (see Advance Program Level) 
APLD (see Alternate Program Load Device) 
Attachment Status, CRT 11-102 
Attachment Timing, CRT 11-101 


B Register Controls 4-044 

Bi-directional Print Operation 9-342 

Bi-directional Print Operation Flowchart 9-343, 9-344 

Bi-directional Print Operation Timing Chart 9-345 

Bi-directional Printing 9-102 

Bit Count Appendage (BCA) 8-101, 8-104 

Bit Ring, Disk 8-224 

Board Layout, CRT 11-202 

Board Layout, Data Recorder 10-202 

Board Layout, Disk 8-203 | 

Board Layout, Keyboard-Console 7-202 

Board Layout, Printer and Ledger Card Device 
Attachment 9-202 

Branch on Condition Flowchart 5-130 

Bridge Basic Storage Module Maintenance 
(see Storage Module Maintenance) 

BSM Maintenance (see Storage Module Maintenance) 


C Byte 8-104 
Cable Channel 1-605 
Card Extender 1-209 

| Card Skew Check, LCD 9-522 
Card, System/3 10-102 
Carriage, Dual Feed 9-102 


TNL §N34-0043 te SY34-0022-1 


Carry Check 2-070 

Cassette, Tape (see Alternate Program Load d Device) 
CE Diagnostic Probe 1-208 

CE Panel Register Display Unit 1-204 

CE Track, Disk 8-104 

Chaining Print Commands 9-103 

Channel P Check 2-140 

Character Codes, Data Recorder 10-107 
Character Set, Data Recorder 10-102 
Character Set, Printer 9-102 | 

Check Counter Check, Disk 8-236 

Checks, Disk 8-228, 8-232 

Clock,CPU 4-020 

Clock, Disk 8-244 

Code Conversion Chart 1-116, 1-117 
Command Byte Structure, Printer 9-103, 9-109 
Command Chaining, Printer 9-103 

Command Field Format, LCD 9-403 
Command Field, LCD 9-403 

Commands, LCD 9-403 

Compare Logical Characters Diagram 5-082 
Compare Logical Characters Flowchart 5-080 
Compare Logical Characters Timing Chart 5-084 
Compare Logical Immediate Diagram 5-090 
Compare Logical Immediate Flowchart 5-092 
Condition Code,CRT 11-207 

Condition Code Response Flowchart 1-111 
Condition Register 4-050 

Condition Register Settings Chart 1-112 
Condition 6 Register, CRT 11-209 

Console 1-202 | 

Console Lamp Replacement 1-409 

Console Lights Diagram—Keyboard-Console 7-205 
Constants, CRT 11-102 

Constants Diagram, CRT 11-208, 11-209 
Control Counter, Disk 8-222 

Control Latches Diagram—Keyboard-Console 7-207 
Controls, CRT 11-103 

Count Byte, LCD 9-402 

Count Byte, Printer 9-104 

Cover, Locations 1-601 

Cover and Panel Removal 1-601 

CPU Cycle Pattern 1-115 

CPU Data Flow 3-010 

CPU Timing 1-113 


5406 FETMM = (6/71) X-1 


NZ 


5406—Index 


CRT Address Decode 11-209 
CRT Address Register 11-103 
CRT Attachment 11-101 
CRT Attachment Timing 11-101 
CRT Card Diagrams 
Card 1 11-204 
Card 2 11-206 
Card3 11-208 
CRT Character Codes 11-103 
CRT Code Conversion Chart 1-118 
CRT Console Indicator 11-103 
CRT Constants 11-102 
CRT Control Data Flow 11-208 
CRT Cycle Steal Requests 11-101 
CRT Data 11-103 
CRT Display Flowchart 11-314 
CRT Display Station Timing 11-205 
CRT Display Timing Chart 11-315 
CRT Error Detection 11-101 
CRT Local Storage Register 11-103 
CRT Program Instructions 11-101 
CRT Select 11-205 
CRT Timing 11-102 
CRTAR_ 11-103 
CursorCRT 11-103 
Cycle Control Ring, Disk 8-220 
Cycle Controls 4-030, 4-032 
Cycle Pattern, CPU 1-115 
Cycle Steal Controls Diagram, Data Recorder 10-208 
Cycle Steal Controls Diagram, Printer 9-211 
Cycle Steal Request, CRT 11-207 
Cycle Steal Request Priority 4-064 
Cycle Steal Requests, CRT 11-101 
Cycle Steal Requests, Disk 8-210, 8-240 
| Cycle Steal Requests, LCD 9-513 
Cycle Steals, Data Recorder 10-209 
Cyclic Code Characters, Disk 8-101, 8-104 
Cylinder 8-104 
Cylinder Address 8-104 


| Data Assembler, LCD 9-518 
Data BusIn 4-060 
Data Bus In Assembler, CRT 11-209 
| Data Bus In Assembler, LCD 9-510 
Data Bus In Assembler, Printer 9-207 
Data Bus Out 4-065 
Data Bus Out Register, Printer 9-205 
Data Check, Printer 9-110 
Data Field, Disk 8-105 
| Data Field, LCD 9-402, 9-626 


TNL SN34-0043 to SY34-0022-1 


Data Flow 
CPU 3-010 
CRT 11-208 
Data Recorder 10-118 
Disk 8-116, 8-204 
Keyboard Attachment 7-120 
Keyboard Operations 7-120 
Ledger Card Device Attachment 9-502 
Printer 9-201 
Data Recorder 10-101 
Data Recorder Attachment 10-101 
Cycle Steals 10-101 
Description 10-101 
Local Storage Register 10-101 
Priority Request 10-101 
Data Recorder FE Latch 1-412 
Data Recorder Interface Lines 10-203 
Data Recorder Maintenance 1-412 
Data Recorder Punch Operation 10-111 
Data Recorder Punch Operation Diagram 10-110 
Data Recorder Read Operation 10-109 
Data Recorder Read Operation Diagram 10-108 
Data Recorder Registers 10-206 | 
Data Recording, Data Recorder 10-103, 10-105 
Data Register, CRT 11-209 
Data Separator 8-208 
- Adjustment 8-208, 1-411 
Data Storage, Disk 8-103 
DBI Assembler, Data Recorder 10-207 
DBI Assembler—Keyboard-Console 7-204 
DBI Parity 2-080 
DBI Translator 4-060 
DBO Parity 2-110 
DBO Register, CRT 11-209 
DBO Register, Data Recorder 10-205, 10-207 
DBO Translator 4-065 
DCP (see Diagnostic Control Program) 
Decimal Conversion Chart 1-112 
Decimal Data Storage Chart 1-115 
Decode Device Address, Data Recorder 10-205 
Delay Line, Data Recorder 10-103 
Delay Line Flag Bits 10-104 
Device Status, Disk 8-109 
DFCR_ 8-105 
DFDR_ 8-105 
Diagnostic, CE, Disk 8-107 
Diagnostic Control Program 1-201 
Diagnostic Cycle Steal Operation Diagram, Data Recorder 10-317 
Diagnostic Data Operation Diagram, Data Recorder 10-317 
Diagnostic Programs 1-201 
Diagnostic Start I/O, Data Recorder 10-117 


5406 FETMM (6/71) X-2 


Difference Counter, Disk 8-212 
Disk Attachment 
Busy 8-108 
Cycle Steal Requests 8-210, 8-240 
Error Detection 8-228, 8-232 
File Control Unit (FCU) 8-101 
Local Storage Registers 8-105 
Parity Error 8-101 
Program Instructions 8-101, 8-107, 8-108, 8-109, 8-111 
Serializer De-serializer (SER-DES) 8-248 
Timing 8-101 
Disk Control Field 8-105 
Disk File Control Register (DFCR) 8-105 
Disk File Data Register (DFDR) 8-105 
Disk Instructions 
Load I/O (LIO) 8-107 
Diagnostic CE 8-107 
Sense I/O (SNS) 8-109 
Start I/O (SIO) 8-111 
Read Data 8-111 
Read Data Diagnostic 8-111 
Read Identifier 8-111 
Read Verify 8-111 
Scan Equal 8-111 
Scan High or Equal 8-111 
Scan Low or Equal 8-111 
Seek 8-111 
Write Data 8-111 
Write Identifier 8-111. 
Test I/O (TIO) 8-108 
Not Ready or Error 8-108 
Disk Storage Drive Maintenance 1-411 
Display Station, 2265 Model 2 11-103 
Display Storage Diagram 5-252 
Display Storage Flowchart 5-250 
Display Storage Timing Chart 5-254 
Drive Check, LCD 9-522 
Dual Feed Carriage 9-101 
Dual Program Feature 4-073, 4-074 


Edit Diagram 5-112 
Edit Flowchart 5-110 


_ Edit Timing Chart 5-114 
| Eject, LCD 9-623 


Element Return Command, Printer 9-103 

Element Return Flowchart, Printer 9-314, 9-315, 9-317 
Element Return Timing Chart, Printer 9-318, 9-319 
Encode Board 7-203 

Encode Board Maintenance 1-409 

End of Forms, Printer 9-104 


Environmental Recording 1-207 
Error Checking Diagram, Printer 9-212, 9-213 
Error Conditions Diagram, Data Recorder 10-210 
Error Conditions, Disk 8-228, 8-232 
Error Detection, CRT 11-101 
| Error Detection, LCD 9-404 
Error Recovery, Printer 9-110, 9-111 
Error Recovery Procedure 1-207 
Extenders | 
Card 1-209 
Pin 1-209 


F Byte, Disk 8-104 
FCU (File Control Unit) 8-101 
FE Console Panel—System Maintenance 1-204 
FE Control Panel Indicators 1-204 
Address Compare 1-205 | 
Clock 1-205 
Interrupt 1-205 
1/O Check 1-205 
Machine Cycles 1-205 
Register Display 1-204 
Rotary Display 1-204 
FE Control Panel Switches 1-205 
Address Compare 1-206 
Address/Data 1-205 
Address Increment 1-206 
BSCA  {-205 
CE Mode Selector 1-207 
Check Reset 7-111, 1-206 
File Write 1-205 
I/O Check Switch 1-205 
1/O Overlap 1-205 
LSR Display Selector 1-206 
Parity 1-205 
Program Load 1-207 
Start/Stop 1-206 
Storage Test 1-206 
System Reset 1-206 
FE Latch, Data Recorder 1-412 
Feed, Read ID, and Eject (LCD) 9-613 
Feed, Read ID, and Locate (LCD) 9-613 
Field/Operation Lights Code 7-106 
File Drawer Interlock Adjustment 1-411 


5406—Index 


File Drawer Service Position 1-411 
Flag Bits, Data Recorder 10-104 
Flag Bits, Disk 8-104 

Forms Control 9-101 

Forms Recognition, Printer 9-104 
Function Keys 7-106, 7-107 
Functional Units Index, Disk 8-202 
Functional Units, LCD 9-501 


Gaps, Disk 8-104 
Gate Locations, CPU 1-602 
General Operation, LCD 9-404 


Halt Program Level Flowchart 5-210 
Head Register, Disk 8-212 

Head Settle Counter, Disk 8-210 
Hexadecimal Addition Chart 1-113 
Hexadecimal Conversion Chart 1-112 
Horizontal Cycle Check, Printer 9-110 


IBM 5444 Disk Storage Drive 

Alternate Track 8-104 

CE Track 8-104 

Configurations 8-102 

Cylinder 8-104 

Data Storage 8-103 

Double Frequency Recording 8-103 

Models 8-102 

Operator’s Console 8-102, 8-103: 

Sector 8-104 

Track Format 8-104 
Address Marks (AM) 8-104 
Bit Count Appendage (BCA) 8-104 
Cyclic Code Characters 8-104 
Data Field 8-104 
Flag Bits 38-104 
Gaps 8-104 
Identifier Field ID) 8-104 
Index 8-104 
Sector Address 8-104 

| IDNumber, LCD 9-401 
Identifier Field (ID), Disk 8-104 


TNL SN34-0043 to SY34-0022-1 — 


I-H Cycle Diagram 5-032 

I-H Cycle Flowchart 5-030 

J-H Cycle Timing Chart 5-034 

I-L Cycle Diagram 5-032 

I-L Cycle Flowchart 5-030 

I-L Cycle Timing Chart 5-034 

IMP (see Integrated Maintenance Package) 
Increment Checking, CRT LSR_ 11-102 
Index, LCD 9-615 

Indicators (see System Indicator Lights) 


| Indicators and Controls, LCD 9-402 


Initial Program Load 

Disk 8-111 

Flowchart 8-307 
Initial Selection Diagram, Data Recorder 10-204 
Initial Selection Diagram, Keyboard-Console 7-206 
Initial Selection Diagram, Printer and LCD 9-204 
Insert and Test Characters Diagram 5-124 
Insert and Test Characters Flowchart 5-122 
Insert and Test Characters Timing Chart 5-120 
Instruction Code Table 1-102 
Instruction Cycle Table 1-103 
Instruction Decode, CRT 11-207 
Instruction/Functional Signal Reference 5-005 
Instruction Register, Printer 9-205 
Instruction Table 1-101. 


Integrated Maintenance Package 1-201 


Interface, Disk 8-205 
Interface Lines, Data Recorder 10-203 
Interrupt Diagram 5-262 
Interrupt Flowchart 5-260 
Interrupt Level, Keyboard 7-115 
Interrupt Request Diagram, Keyboard 7-311 
Invalid Address Diagram 2-050 
Invalid Command Check, LCD = 9-522 
Invalid Command, Printer 9-111 
Invalid Device Address Diagram 2-150 
Invalid Op Code Diagram 2-130 
I/O Condition A, Disk 8-252 
I/O Condition B, Disk 8-252 
I/O Control Fields 1-110 

Disk Control Dield 1-110 

Ledger Card Device 9-403 

Printer Command Byte 1-110 


5406 FETMM = (6/71) 


X-3 


5406—Index 


I/O Interface Lines Diagram 4-100 
I/O LSR Select Check Diagram 2-020 
I-Op Cycle Diagram 5-012 

I-Op Cycle Flowchart 5-010 

I-Op Cycle Timing Chart 5-014 

IPL (see Initial Program Load) 

I-Q Cycle Diagram 5-012 

I-Q Cycle Flowchart 5-010 

1-Q Cycle Timing Chart 5-014 

I-R Cycle Diagram 5-022 

I-R Cycle Flowchart 5-020 

Isolation of ac and dc Ground 1-504 
I-X Cycle Diagram 5-044 

I-X Cycle Flowchart 5-042 

I-X Cycle Timing Chart 5-040 


Jack Plug, APLD 1-207 © 
Jump on Condition Flowchart 5-140 
Jumper Wires 1-208 


Key Identification System 7-103 
Key Operation, Programmed Flowchart 7-310 
Keyboard 7-102 

Back Space Key 7-107 

Command Keys 7-107 

Enter + Key 7-107 

Enter —Key 7-107 

Erase Key 7-107 

Function Keys 7-106 

Inquiry Request Switch 7-107 

Key Functions 7-106 

Key Identification System . 7-103 

Key Operation 7-103 
- Numeric Keyboard Keys 7-106 

Program Start Key 7-107 

Return Key 7-107 

Shift Key 7-107 

Space Bar 7-107 

Tab Key 7-107 

Weighted Codes 7-104, 7-105, 7-106 
Keyboard Attachment 7-115 
Keyboard to CPU Interface 7-115 
Keyboard Encode Board 7-203 
Keyboard Interrupt Request Diagram 7-311 
Keyboard Maintenance 1-409 
Keyboard Removal 1-409 


Last Printable Line 9-404 
Last Printable Line Counter 9-404 


‘ 


TNL SN34-0043 to SY34-0022-1 


So 


Ledger Card Device 9-102 
Ledger Card Device Attachment (LCD) 9-401 
Ledger Card Device Single Shot Locations 1-410 
Ledger Card Format 9-401 
Lights, Console 1-202 
Line Finder Mark 9-401 
Line Finder Mark Check 9-522 
Line Finder Mark Detection 9-404 
LIO (see Load I/O) | 
LLAR (see Local Storage Registers, Printer) 
Load Address Flowchart 5-190 
Load I/O—CPU 
Diagram 5-162 
Flowchart 5-160 
Load I/O—CRT 
Description 11-104 
Flowchart 11-302 
Instruction Format 11-104 
Timing Chart 11-303 
Load I/O—Data Recorder 
Description 10-113 
Error Conditions 10-113 
Flowchart 10-302 
Instruction Format 10-113 
Parity 10-113 
QByte 10-113 
Timing Chart 10-303 
Load I/O—Disk 
Description 8-107 
Diagnostic 8-107 
Instruction Format 8-107 
Load I/O—Keyboard-Console 
Description 7-116 
Field/Operation Lights 7-117 
Flowchart 7-302, 7-303 
Instruction Format 7-116 
Timing Chart 7-305 
Turn off Command Lights 7-117 
Turn on Command Lights 7-116 


| Load I/O—Printer and LCD 


Control Bits 9-105 
Description 9-105 
Error Conditions 9-105 
Flowchart 9-302 
Instruction Format 9-105 
Operand Address 9-105 
Parity 9-105 
QByte 9-105 
Timing Chart 9-303 

Load I/O Reference Table 1-105 


Load Register Diagram 5-062 


Load Register Flowchart 5-060 


5406 FETMM (6/71) xX-4 


Load Register Timing Chart 5-060 
Local Storage Register Chart 1-114 
Local Storage Register Control Diagram 4-073 
Local Storage Register (Dual Programming Feature) Diagram 4-074 
Local Storage Register Parity Diagram 2-030 
Local Storage Register Select Diagram 4-072. 
Local Storage Register Select (I/O) Diagram 4-076 
Local Storage Registers 4-070 
Local Storage Registers (LSR), Disk 
Disk File Control Register (DFCR) 8-105 
Disk File Data Register(DFDR) 8-105 
Local Storage Registers, LCD 9-402 
Local Storage Registers, Printer 9-102 
Locate Line Address Register 9-102, 9-402 
Print Command Address Register 9-102, 9-402 
Print Data Address Registers 9-102, 9-402 
Shared Registers 9-102 
Locate Line Counter, LCD 9-404 
Locations 1-601 
Logic Gate Locations 1-602 
LSR (see Locate Storage Register) 
LSR Address 65 and 961 Increment Check,CRT 11-209 
LSR Addressing, CRT 11-101 
LSR Select, CRT 11-207 
LSR Select, Data Recorder 10-209 
LSR Select Diagram, Data Recorder 10-208 
LSR Select, LCD 9-515 - 
LSR Select, Printer 9-205 


Machine Cycle Table 1-103 

Maintenance Analysis Procedure Charts 1-201 
Maintenance, Scheduled 1-301 | 

MAP Charts (see Maintenance Analysis Procedure Charts) 
Margin Check, Printer 9-110 

Matrix Counter, Printer 9-209 

Matrix Printing Principle 9-101 

Memory Organization, Data Recorder 10-103 
Monolithic System Technology Maintenance 1-401 


Monolithic Technology Cards 1-401 — 


Move Characters Diagram 5-082 
Move Characters Flowchart 5-080 
Move Characters Timing Chart 5-084 


_ Move Hex Character Diagram 5-072 


Move Hex Character Flowchart 5-070 

Move Logical Immediate Diagram 5-094 

MST Card Maintenance 1-401 

MST Cards 1-401 

MST Regulators 1-501 

MST Voltage Levels 1-207 

Multi-function Register, Data Recorder 10-207 


| Next Printable Line, LCD 9-404 


N Byte, Disk 8-105 


Numeric Keyboard Keys 7-106 


Offline Operation, Data Recorder 10-103 
Online Operation, Data Recorder 10-107 
Op and Q Register Decode Diagram 4-105 
Op and Q Register Parity Diagram 2-120 
Operations, Disk | 

Initial Program Load 8-307 

Read Data 8-335 

Read Identifier 8-348 

Seek 8-313 

Start 1/O 8-310 

Write Data 8-326 

Write Identifier 8-317 
Operations, LCD 9-402, 9-601 
Operator’s Console, Disk 8-102, 8-103 
Operator’s Controls (see Console) 


P Bit Generation Diagram 4-012 

Panel, Locations 1-601 

Parallel Parity Check, Disk 8-228 

PCAR (see Local Storage Registers, Printer) 


~ PDAR (see Local Storage Registers, Printer) 


Phase Generator, Disk 8-244 

Pin Extenders 1-209 

PM Chart. 1-301 

Power Box Locations 1-604 

Power Channel 1-605 

Power Chart 1-503 — 

Power Controls Location 1-604 

Power On/Off Sequence Flowchart 6-010 
Power Requirements 1-501 

Power Sequencing 1-501, 6-010, 6-011 

Power Supply Adjustments 1-501, 1-502 
Power Supply Locations 1-603 

Power Supply Outputs 1-501 

Power Supply Test Points 1-503 

Preventive Maintenance 1-301 

Primary Index Flowchart, Printer 9-334 
Primary Skip Flowchart, Printer 9-332, 9-333 
Primary Vertical Index Command, Printer 9-103 
Primary Vertical Skip Command, Printer 9-103 
Print Controls Diagram 9-209 

Print Data Register 9-209 

Print Element Positioning 9-104 

Print Hammer Selection Diagram 9-210 

Print Marks, Ledger Card Device 9-102 

Print Mechanism, Data Recorder 10-105 


5406—Index 


Print Mechanism, Data Recorder 10-105 
Print Operation Flowchart 9-336, 9-337, 9-339 
Print Operation Timing Chart 9-340, 9-341 
Printer Attachment 9-101 
Printer Character Set 9-102 
Printer Commands 9-103 
Printer Commands Diagram 9-206 
Printer Configurations 9-101 
Printer Data Bus Out Check 9-111 
Printer Error Recovery 9-110, 9-111 
Printer Functions 9-101 
Printer Invalid Command 9-111 
Printer Operations 9-103 
Bit Structure 9-103 
Command Chaining 9-103 
Count Byte 9-104 
Element Positioning 9-104 
Forms Recognition 9-104 
Line Printing 9-104 
Overlapping Commands 9-103 
Performing Operations 9-103 
Printer Commands 9-103 
Requirements 9-104 
Restrictions 9-104 
Printer Single Shot Locations 1-410 
Printer Single Shots 9-203 
Printing Principle 9-100 
Priority, Cycle Steal 4-064 
Probe, Diagnostic 1-208 
Processor Check 2-010 
A/B Register Parity 2-090 
ALU Parity 2-100 
Carry Check 2-070 
Channel P Check 2-140 
DBI Parity 2-080 
DBO Parity 2-110 
Invalid Address 2-050 
Invalid Device Address 2-150 
Invalid Op Code 2-130 
I/O LSR Select Check 2-020 
Op and Q Register Parity 2-120 
SAR Parity 2-040 
SDR Parity 2-060 
Program Control, Data Recorder 10-105 


| Program Instructions, LCD 9-402 


Programmed Key Operation Flowchart 7-310 

Punch Operation, Data Recorder 10-111 

Punch Operation Diagram, (5496) 10-110 

Punch Operation Diagram, Data Recorder 10-312 
Punch Operation Flowchart, Data Recorder 10-313 
Punch Operation Timing Chart, Data Recorder 10-315 


TNL SN34-0043 to SY34-0022-1 


Q Register, Op Register Decode Diagram 4-105 


Read All Line Finder Marks, LCD 9-626 

Read Back and Eject, LCD 9-619 

Read Mark Check, LCD 9-522 

Read Only Storage Module 9-209 

Read Operation, (5496) 10-109 

Read Operation Diagram, (5496) 10-108 

Read Operation Diagram, Data Recorder 10-308 
Read Operation Flowchart, Data Recorder 10-309 


Read Operation Timing Chart, Data Recorder 10-311 


Register Diagram, Data Recorder 10-206 
Regulator Stack Location 1-603 


Regulators, MST 1-501 


Reset Display, CRT 11-209 

Run Controls 4-035, 4-036, 4-037, 4-038 
ROS Check, Printer 9-111 

ROS Module Decoding 9-210 


S Byte, Disk 8-104 
Scheduled Maintenance 1-301 
Secondary Index Flowchart 9-335 | 
Secondary Vertical Index Command, Printer 9-103 
Sector, Disk 8-104 
Seek Time Out Counter 8-210, 8-212 
Sense Amp Check, LCD 9-522 
Sense I/O—CPU 
CPU Sense 1-111 
Diagram 5-172 
Flowchart 5-170 
Sense I/O—CRT 
Description 11-106 
Flowchart 11-306 
Instruction Format 11-106 
Status Bytes 11-106 
Timing Chart 11-307 
Sense I/O—Data Recorder 
Description 10-116 
Error Conditions 10-116 
Flowchart 10-306 
Instruction Format 10-116 
Parity 10-116 
QByte 10-116 
Sense Bytes 10-116 
Timing Chart 10-307 
Sense I/O—Disk 
Description 8-109 
Instruction Format 8-109 
Status Bits 8-109, 8-110 


5406 FETMM = (6/71) 


X-5 


5406—Index 


Sense I/O—Keyboard-Console 
Description 7-118 
Flowchart 7-306 
Instruction Format 7-118 
Response to Instruction 7-118 
Timing Chart 7-307 


Sense I/O—Printer and LCD 
Description 9-108 
Diagnostic Signals 9-108 
Error Conditions 9-108 
Flowchart 9-306 
Instruction Format 9-108 
LCD Sense Bits 9-108 
Operand Address 9-108 
Parity 9-108 
QByte 9-108. 
Status Bytes 9-108 
Timing Chart 9-307 
Sense I/O Reference Table 1-107, 1-108, 1-109 
SER-DES 8-248 | 
SER-DES Check 8-228 
Serializer De-serializer 8-102 
Set Bits On/Off Masked Diagram 5-052 
Set Bits On/Off Masked Flowchart 5-050 
Sign Control Chart 1-115 
Simplified Data Flow, Disk 
Compare/Scan 8-114 
Read Data 8-113 
Sense Operation 8-115 
Write Operation 8-112 
Single Shot Adjustments 1-410 
Single Shot Locations 1-410 
Single Shots, Printer 9-203 
SIO (see Start I/O) 
SLD Voltage Levels 1-207 
SNS (see Sense I/O) 
Special Tools 1-208 
Start I/O—CPU 
Flowchart 5-150 
Start I/O—CRT 
Description 11-107 
Display 11-107 
Flowchart 11-308, 11-309 
Halt 11-107 
Instruction Format 11-107 
Timing Chart 11-310 
Start I/O—Data Recorder 
Description 10-117 
Diagnostic 10-117 
Diagnostic Cycle Steal Operation 10-317 
Diagnostic Data Operation 10-316 


TNL SN34-0043 to SY34-0022-1 


Start I/O—Data Recorder (Continued) 
Error Conditions 10-117 
Instruction Format 10-117 
Parity 10-117 
Punch Operation 10-312, 10-313 
QByte 10-117 
Read Operation 10-308, 10-309 

Start I/O—Disk 
Description 8-111 
Instruction Format 8-111 
Read Data 8-111 
Read Diagnostic 8-111 
Read Identifier 8-111 
Read IPL 8-111 
Read Verify 98-111 

Scan Equal 8-111 

Scan High or Equal 8-111 
Scan Low or Equal 8-111 
Seek 8-111 

Write Data 8-111 

Write Identifier 8-111 

Start I/O—Keyboard-Console 
Description 7-119 
Flowchart 7-308 
Instruction Format 7-119 
Timing Chart 7-309 

| Start I/O—Printer and LCD 
Command Byte 9-109 
Description 9-109 
Error Conditions 9-109 
Flowchart 9-308 
Instruction Format 9-109 
I-R Byte 9-109 
Parity 9-109 
QByte 9-109 
Timing Chart 9-309 


Start I/O Reference Table 1-106 
Stepper Motor Controls Diagram, Printer 9-208 
Stepper Motor Start—Move Right Flowchart, Printer 9-310, 9-311 
Stepper Motor Start Timing Chart, Printer 9-313 
Stepper Motor Stopping Flowchart, Printer 9-320, 9-321 
Stepper Motor Stopping Timing Chart, Printer 9-322, 9-323 
Storage Data Flow 3-020 | 
Storage Delay Clock and Timing Diagram 4-082 
Storage Module Maintenance 1-401 

Array Failures 1-404 

Array Replacement 1-404, 1-405 

Circuit Failure Patterns 1-403 

Continuity Check of XY Drive Lines 1-404 

Defective Cores 1-406 

Drive Line Shorts 1-405 


5406 FETMM 


Storage Module Maintenance (Continued) 
Fault Location 1-402 
Intermittent Failures 1-406 
Locating an Open Diode 1-404 
Replacing an Open Diode 1-405 
Scope Pictures. 1-406 through 1-408C 
Strobe Setting Reoptimization 1-406 
Strobe Settings 1-401 
XYZ Drive Voltage Reoptimization 1-406 
-30V Power Supply 1-401 
Storage Unit Diagram 4-080 
Store Register Diagram 5-062 
Store Register Flowchart 5-060 
Store Register Timing Chart 5-064 
Subtract Logical Characters Diagram 5-082 
Subtract Logical Characters Flowchart 5-080 
Subtract Logical Characters Timing Chart 5-084 
Subtract Zoned Decimal Diagram 5-104 
Subtract Zoned Decimal Flowchart 5-100 
Subtract Zoned Decimal Timing Chart 5-106 
Switches, System (see System Control Switches) 
Sync Check, Printer 9-111 | 
Sync Detection, Disk 8-226 


System Control Switches—Keyboard-Console 7-108 


Data Recorder 7-108 

Disk Drive 1 and Disk Drive 2 7-108 
Disk Select 7-108 

Inquiry Request 7-108 

Power 7-108 

Program Load 7-108 

System Start 7-108 

System Control Switches—System Maintenance 

Data Recorder 1-203 , 
Disk Drive 1-203 
-Disk Select 1-203 

Inquiry Request 1-203 

Lamp Test 1-202 

Power On/Off 1-203 

Program Load 1-203 

System Start 1-203 

System Indicator Lights—Keyboard-Console 7-108 

Command Key 7-109 | 
Field/Operation 7-109 

Halt Code 7-109 

I/O Attention 7-109 

Keyboard ‘Ready 7-109 

Power On 7-109 

Processor Check 7-109 

Stop 7-109 


(6/71). X-6 


System Indicator Lights—System Maintenance 
Command Key 1-202 
Field/Operation 1-202 
Halt Code 1-202 
I/O Attention 1-202 
Keyboard Ready 1-202 
Power On 1-202 
Processor Check 1-202 
Stop 1-202 

System Reset Diagram 5-222 

System Reset Flowchart 5-220 

System Reset Timing Chart 5-224 

System/3 Data Flow 1-114 


Tab Command, Printer 9-103 | 
Tab Left Flowchart, Printer 9-328, 9-329, 9-331 
Tab Right Flowchart, Printer 9-324, 9-325, 9-327 
Tape Cassette (see Alternate Program Load Device) 
Test Bits On/Off Masked Diagram 5-052 
Test Bits On/Off Masked Flowchart 5-050 
Test I/O—CPU 

Flowchart 5-180 
Test I/O—CRT 

CRT Busy 11-105 

CRT Check 11-105 

Description 11-105 

Flowchart 11-304 

Instruction Format 11-105 

Timing Chart 11-305 


5406—Index 


Test I/O—Data Recorder 
Description 10-114 
Error Conditions 10-114 
Flowchart 10-304 
Instruction Format 10-114 
Parity 10-114 | 
QByte 10-114 
Timing Chart 10-305 
Test I/O—Disk 
Busy 8-108 
Description 8-108 
Error Conditions 8-108 
Instruction Format 8-108 
Not Read or Error 8-108 
Test I/O—Keyboard-Console 7-117 
| Test I/O—Printer and LCD 
Branch to Address 9-106 
Description 9-106 
Error Conditions 9-106 
Flowchart 9-304 
Instruction Format 9-106 
Parity 9-106 
QByte 9-106 
Timing Chart 9-305 
Test I/O Reference Table 1-104 
Tie Down List 1-119 
CPU 1-119- 
CRT 1-119 
Disk 1-119 
Timing, CPU 1-113 


TNL SN34-0043 to SY34-0022-1 


Timing Signals, CRT 


11-102 


Reset Display 11-102 


Start Character Generator 


Step Display 11-102 


TIO (see Test I/O) 


Translator, DBI 4-060 


Translator, DBO 4-065 
Typamatic Operation 7-316 


Use Meter Single Shot 1-410 


Vertical Cycle Check, Printer 


Vertical Forms Control 
Voltage Regulator Cards 


9-101 
1-502 


11-102 


9-111 


Weighted Codes, Keyboard 7-104, 7-105, 7-106 


Zero and Add Zoned Diagram 5-104 


Zero and Add Zoned Flowchart 


5-100 


Zero and Add Zoned Timing Chart 5-106 


2222 Model 1 Printer 
2222 Model 2 Printer 
5213 Model 1 Printer 
5213 Model 2 Printer 
5213 Model 3 Printer 


9-101 


9-101 
9-101 


9-101. 


9-101 


5406 FETMM = (6/71) 


X-7 


wai 


5406 FETMM 


(2/71) 


X-8 


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READER’S COMMENT FORM | : READER’S COMMENT FORM 


System/3 Model 6 Order No. SY34-0022-1 : System/3 Model 6 Order No. S Y34-0022-1 . 
5406 Processing Unit and Attachments | 5406 Processing Unit and Attachments | 
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SY34-0022-1 


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SY34-0022-1 


YOUR COMMENTS, PLEASE. .. 


Your answers to the questions on the back of this form, together with your comments, will 
help us produce better publications for your use. Each reply will be carefully reviewed by 
the persons responsible for writing and publishing this material. All comments.and sug- 
gestions become the property of IBM. 


Note: Please direct any requests for copies of publications, or for assistance in using your 
IBM system, to your IBM representative or to the IBM branch office serving your locality. 


BUSINESS REPLY MAIL. 
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POSTAGE WILL BE PAID BY 


IBM Corporation 
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Boca Raton, Florida 33432 


Attention: Systems Publications, Department 707 


International Business Machines Corporation 

Data Processing Division 

1133 Westchester Avenue, White Plains, New York 10604 
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IBM World Trade Corporation 
821 United Ne#¥--- ™-— 
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FIRST CLASS 
PERMIT NO. 110 


BOCA RATON, FLA 


33432 

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International Business Machines Corporation 

Data Processing Division 

1133 Westchester Avenue, White Plains, New York 10604 
{U.S.A. only] 


IBM World Trade Corporation © 
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