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£352 Series/1 


GA34-1561-0 
File No. S$1-14 


IBM Series/1 
Series/1 to Series/1 Attachment 
RPQs DO2241 and DO2242 
Custom Feature 


Preface 


This publication describes the IBM Series/1 to 
Series/1 Attachment, RPQ D02241 and RPQ 
D02242, custom features designed for the IBM 
Series/1. The intended audience for this 
publication is customer executives, programmers, 
and maintenance personnel who will use this 
information to order products, prepare machine 
language code, and supplement other maintenance 
aids. The subject matter is presented in two 
chapters and two appendixes. Chapter 1 
introduces the RPQs and gives configuration and 
planning information. Chapter 2 describes the data 
transfer operations the Series/1 to Series/1 
Attachment uses. Appendix A contains Operate 
I/O and DPC operation reference. material. 
Appendix B contains diagnostic command 
information. 


' First Edition (December 1978) 


Use this publication only for the purposes stated in the Preface. 


Related Publications 


IBM Series/1 4955 Processor and Processor 
Features Description, GA34-0021 

IBM Series/1 4953 Processor and Processor 
Features Description, GA34-0022 

IBM Series/1 System Summary, GA34-0035 
IBM Series/1 Customer Site Preparation Manual, 
SA34-0050 


Additional publications are listed in JBM Series/1 
Graphic Bibliography, GA34-0055. 


Changes are periodically made to the information herein; any such changes will be reported in 


subsequent revisions or Technical Newsletters. 


Publications are not stocked at the address given below. Requests for copies of IBM publications 
should be made to your IBM representative or the IBM branch office serving your locality. 


This publication could contain technical inaccuracies or typographical errors. A form for readers’ 
comments is provided at the back of this publication. If the form has been removed, address your 
comments to IBM Corporation, Systems Publications, Department 27T, P.O. Box 1328, Boca 
Raton, Florida 33432. IBM may use and distribute any of the information you supply in any way 
it believes appropriate without incurring any obligation whatever. You may, of course, continue 


to use the information you supply. 


© Copyright International Business Machines Corporation 1978 


Contents 


Chapter 1. Introduction and Planning 1-1 
Configuration 1-2 

Planning 1-3 

Cable Connections 1-3 


Chapter 2. Programming and Operation 2-1 
Cycle Steal Data Transfers 2-1 
Device Control Block (DCB) 2-2 
DCB Word 0—Control Word 2-2 
DCB Word 1—Reserved 2-2 
DCB Word 2—Checksum/Program Data 2-2 
DCB Word 3—Reserved 2-3 
DCB Word 4—Reserved 2-3 
DCB Word 5—DCB Chain Address 2-3 
DCB Word 6—Byte Count 2-3 
DCB Word 7—Data Address 2-3 
Start Command 2-3 
Read Header 2-6 
Read Data 2-6 
Write Data 2-6 
Write Abort 2-6 
Start Cycle Steal StatusCommand 2-6 
Cycle Steal Status Word 0 2-6 
Cycle Steal Status Word 1 2-6" 
Cycle Steal Status Word 2—Not Used 2-6 
Cycle Steal Status Word 3—Not Used 2-6 
Cycle Steal Status Word 4—Error Status 2-6 
Cycle Steal Status Word 5 2-7 
Cycle Steal Status Word 6 2-7 
Cycle Steal Status Word 7 2-7 
Cycle Steal Status Word 8 2-7 
Cycle Steal Status Word 9 2-7 
Cycle Steal Status Word 10 2-7 
Condition Codes 2-8 
Operate 1/O 2-8 
Interrupt 2-8 


Appendix A. Operate I/O and DPC Operations A-1 
Operate I/O A-1 
Direct Program Control (DPC) A-2 

Read ID Command A-3 

PrepareCommand A-4 

Device Reset Command A-5 


Appendix B. Diagnostic Commands B-1 


Diagnostic Command Structure B-1 
Diagnostic Command Results B-2 


Contents tii 


iv GA34-1561 


Chapter 1. Introduction and Planning 


The IBM Series/1 to Series/1 Attachment RPQs the supplied 8-meter (26-foot) cable. (See Figure 

D02241 and D02242 expand the communication 1-1.) This interface provides programmable error 

capability of the Series/1 processor to meet detection capabilities at a maximum instantaneous 
applications requiring processor-to-processor data rate of 65 kilobytes per second. (Data rate is 
communication. This communication link is dependent upon the block size of data transferred 
accomplished by an attachment card plugged into and cable length.) 


each processor’s I/O channel and connected via 


IBM Series/1 processor 
(or [/O expansion unit) 







1BM Series/1 to Series/1 





7 ba | 
Note: RPO D02246 provides additional IBM Series/1 to Series/1 BM oe West) DEOccss0r 


| : : 
3-meter (10-ft) increments to the 8-meter attachment card (RPO soe O expansion. unit) 
(26-ft) cable included in RPO D02242. D02241) 


Figure 1-1. Series/1 to Series/1 Attachment configuration 


Introduction and Planning 1-1 


Configuration 


RPQ D02241 contains an IBM Series/1 
attachment card that will have priority if a 
contention period for data transfer should occur 
between this attachment and the complementary 
attachment, RPQ D02242. RPQ D02246 provides 
additional 3-meter (10-foot) increments to the 


8-meter (26-foot) cable included in RPQ D02242. 


With a maximum order quantity of four extra 
cable increments, the maximum allowable cable 
length is 20 meters (65 feet). 


If a replacement cable is required for use with 
RPQs D02241 and DO2242, RPQ DO2268 must 
be ordered, along with the appropriate quantity of 
extra cable increments (RPQ D02246). 


The maximum instantaneous data rate that can be 
achieved by the Series/1 to Series/1 Attachment 
is 65 kilobytes per second. Throughput, however, 
can vary and is dependent upon the block size of 
the data which is transferred and cable length. 


IBM Series/1 processor 

















IBM Series/1 processor 


Multiple Series/1 to Series/1 Attachments may be 
employed in any configuration. That is, any 
Series/1 processor could contain only RPQ 
D02241 feature cards, or only RPQ D02242 
feature cards, or any combination of them both. 
Figure 1-2 shows an example of a configuration in 
which four Series/1 processors are linked. In this 
example, processor A has priority over. processors 
B and C. However, processor D has priority over 
processor A. 


Note: Multiple Series/1 to Series/1 Attachments 
cannot utilize a single communications link; that 
is, each attachment must have its own distinct 
cable. 


Referring still to Figure 1-2, note that the RPQ 
ordering information for the illustrated 
configuration is given on the right, broken down 
by the requirements for each Series/1 processor. 


Order 
Quantity RPO # 


2 DO02241 
2 D02246 






—— | D02241 
8 meters 14 meters 
on) (46 ft) 
1 D02242 
17 meters 
(56 ft) 
IBM Series/1 processor 
Processor B is located within the 8-meter 
(26-ft) cable distance from processor A. 
1 D02242 
3 D02246 


Note: 
[P| indicates priority card 





IBM Series/1 processor 


Processor C is located at a distance from processor A 
that will require a cable length of 17 meters (56 ft). 
(Therefore, 3 increments of DO2246 are required.) 


Figure 1-2. Multiple attachments configuration 


1-2 GA34-1561 


Planning Cable Connections 


Internal cable routing in a 1.8 meter rack (i.e., Cable connection information is shown in Figure 
with the processor mounted at the top) would use 1-4. Pin designations are given in the following 
a maximum of 2.5 meters (8.2 feet) of cable. See. table: 

Figure 1-3. 


J1& J2 
connector 
pins Line name 


Checksum Error Detected 
Data Valid (DAV) . 
Not Ready for Data (NRFD) 
Not Data Accepted (NDAC) 


Active RPO D02241 
RPQ DO2242 Request 
Active RPO D02242 
Shield (ground) 


RPO D02241 Enable Operation 
DAV Ground 

NRFD Ground 

NDAC Ground 


Active RPQ D02241 Ground 
RPO DO2242 Request Ground 
Active ROP D02242 Ground 
Logic Ground 





Figure 1-3. Cable routing 


{09 


AN 
m 


at 









vAAVS D> 








AK 


Ay 
VAN 


Diagnostic 
connector 
(for service 
use only) 


Ay 
ay 


wy: 
YA 


Wikis 







Ay 
‘Ad 


A\ 








HH HHHHHHHHHT 
a 





VA 





Cable connector Card connector 


Figure 1-4. Cable connections 


Introduction and Planning 1-3 


1-4 GA34-1561 


This chapter, intended primarily for the 
programmer, describes the Series/1 to Series/1 
direct communications operations. Data transfers 
are byte serial under cycle steal mode via a 16-line 
bidirectional interface cable. For a detailed review 
of basic Operate I/O and DPC operations (Read 
ID, Prepare, and Device Reset), see Appendix A. 


Cycle Steal Data Transfers 


Command execution in cycle steal mode permits 
overlapping of I/O and other processor 
operations. 


The processor transfers the IDCB under direct 
program control (DPC) from processor storage to 
the Series/1 to Series/1 attachment. See Figure 
2-1 BB. 

After the attachment accepts the IDCB: 


1. It returns an Operate I/O condition code to 


Operate 1/O instruction 


Chapter 2. Programming and Operation 


the processor [. The processor is now freed 
to continue with other operations. 


2. The attachment uses the information in the 
IDCB to execute the command. The IDCB 
immediate data field contains the address of 
an 8-word device control block (DCB) 
defining the operation. 


3. The attachment steals the DCB words Kj and 
data [J needed to perform the command. 


4. Each data transfer reduces a preset byte count 
in DCB word 6. 


5. When the data transfer ends (i.e.,byte count 
equals zero), the attachment sends an 
interrupt request to the processor. 


The processor then accepts the interrupt condition 
code and an Interrupt ID word from the 
attachment. | 


R2 Address 
01101 


IDCB 


| Effective address. | 





0 7 8 1516 31 
LSR © 
P| Attachment 
— ae 


DCB 


Control word 


jk} 


Data area 


Count 
Data address | rr | 


Figure 2-1. Cycle steal operation 


Programming and Operation 2-1 


Device Control Block (DCB) 


DCB (device contro! block) 


Word 





0 Control! word 


7 Reserved (must = 0) 


2| Checksum Program data 


3| Reserved (must = 0) 


4 Residual status block address 


DCB chain address 


QO 


ie») 


Byte count 


DCB Word 0—Control Word 


Addr 
CF PCI|IF| XD|SE | key TO|0| Operation 


N 


O 1 23 45 789 1011 15 


Bit 0 Chaining flag (CF). This bit equal to 


one indicates a DCB chaining 
operation. After completing the 
current DCB operation the 


attachment will not interrupt but will 


cycle steal the next DCB pointed to 


by the chaining address contained in 


word 5 of the current DCB. 


Bit 1 This bit is not used and must be zero. 


Bit 2 Input flag (IF). This bit indicates to 
the attachment the direction of the 
data transfer. If this bit equals zero, 


. data transfer is from main storage to 


the attachment (output). If this bit 
equals one, data transfer is from 
attachment to main storage (input). 


Bit 3 XD bit is not used and must be zero. 


Bit 4 Not used. 


2-2 GA34-1561 


Bits 5—7 


Bit 8 


Bit 9 


Bit 10 


Bits 11-15 


Cycle steal address key. A program 
assigned three bit processor storage 
protect access key used by the 
attachment during data transfers for 
storage access authorization. 


This bit is not used and must be 
zero. 


Timer override (TO). An exception 
interrupt will occur if the data 
transfer is not complete in one 
second and bit 9 is equal to a zero. 
With bit 9 equal to a one, the 
attachment will wait indefinately for 
the data transfer to complete. 


This bit is not used and must be | 
zero. 


Operation field. Bits 11-15 specify 
the operation to be performed. 
10101 Read Header 

10110 Read Data 

10111 Write Data 

11000 Write Abort 


DCB Word 1—Reserved 


Bits 0-15 


These bits are not used and must be 
zero. 


DCB Word 2—Checksum/Program Data 


O 2 


Bits 0-1 


Bit 2 


Bit 3 


. Checksum 
IF } CK) length Program data 
7 


34 78 15 


These bits are not used and must be 
zero. 


The value of this bit should equal the 
value of the IF bit (bit 2 of DCB 
word 0). 


Checksum bit specifies if error 
detection will occur during data 
transfer. Bit 11 equal to a one 
specifies error detection via 
checksum will occur during data 
transfer, and that the value in the 
checksum (bits 12—15) will be used 
to control the checksum block length. 
The checksum block length is the 
number of data bytes from which a 
checksum total will be generated and 
transmitted as the final byte. 


These bits will control the number of 
data bytes from which a checksum 
byte will be generated. 

0000 32 bytes 

0001 16 bytes . 

0011 8 bytes 

0111 4 bytes 

1111 2 bytes 


Program dependent data can be used 
by the Series/1 programmer for any 
status or information required. 


Bits 4—7 


Bits 8-15 


DCB Word 3—Reserved 


These bits are not used and must be zero. 


DCB Word 4—Reserved 


These bits are not used and must be zero. 


DCB Word 5—DCB Chain Address 


DCB chain address 


0 15 


The DCB chain address word specifies the main 
storage address of the next DCB in the chain. To 
chain DCBs, set the chaining flag bit in the DCB 
control word (DCB word 0 bit 0) to a one. The 
address must be an even number or a DCB 
specification check will result. 


DCB Word 6—Byte Count 


Byte count 


15 


oS 


The byte count word contains a 16-bit unsigned 
integer representing the number of data bytes to 
be transferred for the current DCB. Count is 
specified in bytes with a range of 0 to 65,534 and 
must be even or a DCB specification check will 
result. 


DCB Word 7—Data Address 


0 15 


The data address word contains the starting main 
storage address for the data transfer and must 
start on a word boundary or a DCB specification 
check will result. 


Start Command 


The Start command initiates I/O operations that 
transfer data to or from processor storage in cycle 
steal mode. The control information and 
parameters required for a particular operation 
must be stored in the DCB associated with each 
Start command. The operations that the Start 
command initiates are contained in DCB word 0 
bits 11-15 and are: 


e Read Header 
e Read Data 

e Write Data 

e Write Abort 


Figure 2-2 gives an overview of a data transfer 
operation. 


Programming and Operation 2-3 


Processor ‘A’ initiates a data transfer operation 

to processor ‘B’. Processor ‘A’ attachment uses 
information in the DCB to configure and transmit 
a two-word header. 


Processor Processor 
‘h ’ ‘B 7 


Word 


Ss 


H 


~ 


2,209 BH 


io) 


Interrupt word 
attention bit on 


| | 
| | 
| | 
| | 
| | 
| | 


Attachment Attachment 
‘B’ 


N OD OG A 





The two-word header made up by the attachment is: 
Word 1 
Bit 0 is zero 
Bit 1 is zero 
Bit 2 is equal to DCB word O, bit 2 (read/write bit) and DCB word 2, bit 2 (read/write bit) 
Bit 3 is equal to DCB word 2, bit 3 (checksum) 
Bits 4—7 are equal to DCB word 2, bits 4—7 (checksum control) 
Bits 8—15 are equal to DCB word 2, bits 8—15 (program parameters) 4 | 
Word 2 is equal to DCB word 6 (byte count) 


Processor ‘B’: attachment receives the two-word header 
and inverts the read/write bit (bit 2 of word 1) and 
causes an interrupt with the attention bit on. 


Figure 2-2. Data transfer operation (part 1 of 2) 


2-4 GA34-1561 


Processor ‘B’ now accepts the interrupt from its attachment and initiates a read header operation. 
A user-written program within processor ‘B’ then interrogates the two word header and uses this 
information to build a new DCB and issue the appropriate Start command. Data is transferred be- 
tween the two processors with each attachment cycle stealing data to/from its main memory. 


Processor Processor 
‘A’ ‘B f 


Attachment Attachment 





Either processor can initiate a data transfer operation, if processor ‘A’ initiates a write operation 
then processor ‘B’ would respond with a read operation, and the opposite is true. 


One of the attachments (D02241) will take priority in data transfer to resolve any contention 
problem if both processors should initiate data transfer simultaneously. 


Figure 2-2. Data transfer operation (part 2 of 2) 


Programming and Operation 2-5 


Read Header 


The Read Header operation is used to transfer the 
two-word (four-byte) header into main memory 
when an Attention interrupt or an Attention and 
Exception interrupt has been received. These two 
interrupts specify that an information transfer has 
- been initiated by the other processor and a 
“matching” Read Data or Write Data operation is 
required to transfer the information. In order for 
the “‘matching”’ Read Data or Write Data 
operation to be performed, a user-written program 
must interrogate the two-word header that is 
stored in main memory to build a new DCB and 
issue the appropriate Start command. 


Word 


Checksum 
IF | CK} length Program data 





Byte count 
0 1234 78 15 


Read Data 


The Read Data operation will cause an input of 
data into main memory. The Read Data operation 
can initiate a data transfer operation, or it can be 
in response to a Write Data operation. Information 
needed for this data transfer operation will be 
contained in the DCB. 


Write Data 


The Write Data operation will cause the output of 
data from main memory. The Write Data 
operation can initiate a data transfer operation, or 
it can be in response to a Read Data operation. 
Information needed for this data transfer operation 
will be contained in the DCB. 


Write Abort 


The Write Abort operation is used by the 
responding processor to end the data transfer 
operation by giving the initiating processor an 
exception interrupt. For example, the responding 
processor may want to terminate a data transfer 
operation after receiving the header if the byte 
count specified is too large. 


2-6 GA34-1561 


Start Cycle Steal Status Command 


The Start Cycle Steal Status Command initiates a 
cycle steal operation to obtain residual parameters 
from the attachment (11 Cycle Steal Status 
Words) if the previous cycle steal operation 
terminated due to an error or exception condition, 
or any time residual status is desired. 


Cycle Steal Status Word 0 


Residual Address. The Residual Address word 
contains the main storage address of the last 
attempted cycle steal transfer associated with a 


Start command. If an error occurs during a 
Start Cycle Status operation this address is not 
altered. The residual address may be a data 
address, a DCB address, or a residual status 
block address and is cleared only by a power 
on reset. 





Cycle Steal Status Word 1 










Residual byte count. The Residual Byte Count 
word is the last cycle steal operation count less 
the number of bytes successfully transferred. 


Cycle Steal Status Word 2—-Not Used 
Cycle Steal Status Word 3—Not Used 


Cycle Steal Status Word 4—Error Status 


Bus timed out on Acceptor Handshake. The 
attachment was attempting to receive data 
from the bus. 


Reserved. 


Bus timed out on Source Handshake. The 
attachment was attempting to send data to the 





Cycle Steal Status Word 5 


pits [rmeton 
Jo | status of DIO tine after power on 
7 










Status of DIO line 4 after power on. 


> Status of DIO line 3 after power on. 


oa 

[6 __| status of DIO ine 2ater power on 
[7 | status of B10 tne 1 after power on, 
fs __| sats of active RPQ DO2241 ater power om 












10 Status of RPQ D02242 request operation after 
power on. 

11 Status of checksum error detected after power 
on. 

12 Status of RPQ D02241 enable slave operation 
after power on. 





Status of NRFD line after power on 
Status of NDAC line after power on 


Status of DAV line after power on. 


Cycle Steal Status Word 6 


This word contains the current status of the 
interface. The structure of this word is the 
same as for Cycle Steal Status Word 5. 





This byte contains abort message condition 


codes generated by the system that issued an 
abort operation. 


= 





Cycle Steal Status Word 8 


0-3 Bits 0-3 indicate the cause of the DCB 
specification check. 




















0000 Not used 
0001 Odd DCB address 

0010 Invalid PCI bit 

0011 Invalid IF bit 

0100 Invalid XD bit 

0101 Invalid SE bit 

0110 Invalid DCB word 0 bit 8 

0111 Invalid timer bit 

1000 Invalid DCB word 0 bit 10 

1001 Non-zero unused word 

1010 Odd RSB address 

1011 Odd chaining address 

1100 Invalid byte count 

1101 Invalid command code for configuration 
1110 Not used 

1111 Not used 


Not used and must be zero 
Indicate the following status: 


0000 Not used 

0001 Invalid header IF bit 
0010 Invalid check bit 

0011 Invalid checksum 
0100 Invalid program word 
0101 Not used 

0110 through 0111 Not used 


12-15 | Not used and must be zero 


Cycle Steal Status Word 9 


jBies | Fumetion 
Ls __[cecksum eror detested | 


Cycle Steal Status Word 10 


ee 


0-15 This word will contain the starting address of 
the last DCB used by the attachment. 

































Programming and Operation 2-7 


Condition Codes 


Operate I/O 


Condition codes (CC) are reported after execution 
of each Operate I/O instruction. See Figure 2-3. 
The appropriate condition code is transferred into 
the even, carry, and overflow bit positions of the 
level status register (LSR) in the processor. 







nasi [x{x]x]| | [x] [x 
St 3 a SE 


Device 
reset 


Start bebe Pe 


Start cycle x x 
steal status 


lel 






NAURWN =O 


CC Value Meaning 
Device not attached 
Busy 
Busy after reset 
Command reject 
Intervention required (not reported) 
Interface data check 
Controller busy (not reported) 
Satisfactory 
Figure 2-3. Condition code responses to Operate I/O 
instructions 
Interrupt 


Interrupt condition codes pertain to operations 
that continue beyond execution of the Operate 
I/O instruction (such as cycle stealing of data). 
The condition codes that are reported are: 


CC Value Meaning 

2 Exception 

3 Device end 

4 Attention 

6 Attention and exception 


Along with the interrupt condition code the 
attachment also transfers an interrupt ID word to 
the processor. Bits 0~7 of the interrupt ID word 
are called the interrupt information byte (IIB) or 
Interrupt Status Byte depending on the condition 
code, and bits 8-15 are the device address. 


Interrupt information 
byte (1B) or (ISB) Device address 


0 7 8 15 


2-8 GA34-1561 


If the condition code is 3 (device end) and bit 0 
of the ITB equals one, a permissive end has 
occurred. If the condition code is 4 (attention) or 
6 (attention and exception) and bit 1 of the IIB 
equals one, the other processor has requested 
service. In addition, if bit 2 equals one, a data 
exchange has been initiated by the other system. 


For condition code 2, the IIB has a special format 
and is called an interrupt status byte (ISB). The 
ISB is coded as follows: 


Bit 0 Device dependent status available. 
When set to one, this bit signifies 
that further status is available. This 
status is obtained using the Start 
Cycle Steal Status command. This bit 
is set to one for incorrect length 
records and when an error was 
encountered during execution of the 
on-line diagnostic test. 


Bit 1 Delayed command reject. This bit is 
_ set to one if the device cannot 
‘execute the command due to one of 
the following conditions: 


1. The IDCB contains an incorrect 
parameter. Examples are (a) an - 
odd-byte DCB address or (b) an 
incorrect function/modifier 
combination. 


2. The present state of the device, 
such as ‘not ready’ condition, 
prevents execution of an I/O 
command specified in the IDCB. 


Delayed command reject is set in the 
ISB only if the device cannot report 
I/O instruction condition codes for 
the condition. The operation is 
terminated. DCB is not fetched. 


Bit 2 Not used. 


Bit 3 DCB specification check. This bit is 
set to one when the device cannot 
execute a command due to an 
incorrect parameter specification in 
the DCB. Examples are (1) an 
odd-byte DCB chaining or status 
address, (2) the byte count is odd for 
a word-only device, (3) an odd-byte 
data address for a word-only device, 


Bit 4 


(4) an invalid command or invalid bit 
settings in the control word, or (5) 
an incorrect count. 


The operation is terminated. 


Storage data check. This error 
condition applies to cycle steal 
output operations only. If the bit is 
set to one, it indicates that the main 
storage location accessed during the 
current output cycle contained bad 
parity. Parity in main storage is not 
corrected. The attachment terminates 
the operation. The bad parity data is 
not transferred to the I/O data bus. 
No machine check condition occurs. 


Bit 5 


Bit 6 


Bit 7 


Invalid storage address. When set to 
one, this bit indicates that during a 
cycle steal operation, the attachment 
has presented a main storage address 
that is outside the storage size of the 
system. The operation immediately 
terminates. 


Protect check. When set to one, this 
bit indicates that the attachment 
attempted to access a main storage 
location and presented an incorrect 
address key. 


Interface data check. When set to 
one, this bit indicates that a parity 
error is detected on the I/O interface 
during a cycle steal data transfer. 
The operation immediately 
terminates. 


Programming and Operation 2-9 


2-10 GA34-1561 


Appendix A. Operate I/O and DPC Operations 


Operate I/O 


The processor initiates I/O operations by issuing 
an Operate I/O instruction, and then uses the 
processor I/O channel to transfer data to and 
from the attachment. The Operate I/O instruction 
is a privileged instruction. Its effective address 
(the combination of the R2 and address fields) 
points to an immediate device control block 
(IDCB) in main storage. The IDCB contains an 
I/O command, a device address, and an 
immediate-data field. See Figure A-1. The 
command defines the type of I/O operation; the 
device address identifies the device on which the 


Operate I/O instruction 


R2 Address 
0110 1 *1 100 
45 7 8 


101712 15 16 


0 






Effective address 


IDCB (immediate device control block) 


operation is to be performed. The use of the 
information in the immediate data field depends 
on the mode of operation. For direct program 
control (DPC) operations, the immediate-data 
field is used as a data word; for cycle-steal 
operations, this field points to a device control 
block (DCB) that contains additional information 
needed to perform the operation. The IDCB must 
be on a fullword boundary. Refer to the IBM 
Series/1 4955 Processor and Processor Features 
Description, GA34-0021 or the JBM Series/1 
4953 Processor and Processor Features Description, 
GA34-0022, for a more detailed description. 


31 






XXXXXXXXIOXXXXXX KIX KXXXKXKKXKXXKXKXXKXK XK X 


ree 


0 34 7 \8 1516 31 
Hex Command Type of operation 

0010 0000 20 Read ID DPC 

0110 0000 60 = Prepare DPC 

0110 1111 6F Device reset DPC 

0111 0090 70 ~~ Start Cycle steal 

0111 1111 7F Start cycle Cycle steal 


steal status 


Figure A-1. Operate I/O instruction and IDCB formats 


Operate I/O and DPC Operations 


A-1 


Direct Program Control (DPO 


A command executed under direct program control 
causes an immediate transfer of data or control 
information to or from the attachment. This 
attachment recognizes only the following 
DPC-type commands: 


Command Hex IDCB Immediate Data 
Field Contents 

Read ID 20 Device ID word 

Prepare 60 Interrupt parameters 

Device Reset 6F Zeros 


An Operate I/O instruction must be executed for 
each of the above commands. Each execution 
consists of the following events (see Figure A-2). 


Operate I/O instruction 


The Operate I/O instruction points to an 
IDCB in main storage. §J 


The attachment uses the IDCB’s 
device-address field Jj to determine its 
address, and the command field ]j to 
determine the operation to perform. 


The processor transfers the contents of the 
immediate-data field to the attachment, or 
transfers information from the attachment to 
the immediate-data field, depending on the 
command being executed. 


The attachment sends a condition code to the 
level status register (LSR) in the processor. 


R2 Address 
0110 1 *i1 100 


Effective address 





IDCB 


Command | Device address Immediate data 


0 7 8 15 16 


37 


A, al 


LSR 


ello] = sR 


Condition code 


LSR_ Bit O even indicator 
Bit 1 carry indicator 
Bit 2 overflow indicator 


~—Figure A-2.---Direct program control I/O operation 


A-2 GA34-1561 





1/O attachment 


Read ID Command 


The Read ID command transfers an identification 
(ID) word from the attachment to the 
immediate-data field of the IDCB. For this 
attachment, the ID word is X’0F06’. 


Operate !/O 
instruction 


Transfer IDCB 
to attachment 
then execute 











IDCB (immediate device contro! block) 


Command Device address 
0010000 0/0 X X X X XK XK X 











Se, oe: re oe 0 7 8 15 
Move 1D word vee ———— —_—_—_—_—_— 
from attachment 20 00—7F 
to immediate 
data field 0 7 0 6 
of the IDCB Immediate data 

16 28 29 30 31 

a | 

Bits 16—28 Unique code 

assigned to 


this attachment 


Bit 29=1 Controller device 
that reports delayed 
command reject 


Bit 30=.1 Cycle steal device 
Bit 31 =0 An IBM device 





LSR bits O—2 


Device not attached 
Device busy 

Not reported 

Not reported 





Device reports operate I/O 
instruction condition 
code to processor 





Not reported 
Interface data check 
Not reported 
Satisfactory 








Figure A-3. Read ID command operation 


Operate I/O and DPC Operations A-3 


Prepare Command 


Before the attachment can request interrupts, the 
processor must supply interrupt parameters. The 
user places these parameters in the IDCB’s 
immediate-data field. The Prepare command 
transfers the parameters to the attachment. The 
parameters include an interrupt-enable bit to 
control whether or not the device is allowed to 
interrupt, and the priority-interrupt level to which 
the attachment requests interrupt service. 


Operate I/O 
instruction 


Transfer 1DCB 
to attachment 
then execute 
IDCB 














IDCB (immediate device control block) 


Command Device address 
01310000 0/0 XK X XK XK K XK X 
O 7 8 15 
ae aE nS 


60 00—7F 









Move interrupt 
parameters to 

a prepare register 
in the attachment 






Immediate data 
Zeros 







~<— |-bit 


30\31 










26 27 


Level O 
Level 1 
Level 2 
Level 3 


Device inhibited 
from interrupting 
Device allowed 
to interrupt 






LSR bits 0-2 


Device reports operate I/O 
instruction condition 
code to processor 


Device not attached 
Not reported 
Not reported 
Not reported 






Not reported 
Interface data check — 
Not reported 
Satisfactory 





Figure A-4. Prepare command operation 


A-4 GA34-1561 


Device Reset Command 


The Device Reset command resets the addressed 
attachment. Any pending interrupt or busy 
condition is cleared. The device interrupt-enable 
bit, the assigned priority level, and the residual 
address (cycle steal status word 0) are not 
affected. 


Operate !/O 
instruction 


Transfer IDCB to 
attachment then 
execute IDCB 








IDCB (immediate device control block) 


Command Device address 
0110313143131 31)0 X X XXX X X 


0 7 8 15 
= nema Cnrmmmeemenatill 
6F 00—7F 


Immediate data 
0o00000 000000000 0 


16 37 








Perform reset 









LSR bits O—2 


Device not attached 
Not reported 

Not reported 

Not reported 

Not reported 

Not reported 

Not reported 
Satisfactory 


Device reports operate |/O 
instruction condition 
code to processor 





0 
1 
2 
3 
4 
5 
6 
7 








Figure A-5. Device reset command operation 


Operate I/O and DPC Operations A-5 


A-6 GA34-1561 


Diagnostic commands are used to verify correct 
operation of the Series/1 to Series/1 Attachment. 
These commands are executed during the 
diagnostic MAP sequence and provide actual 
attachment internal testing results. The following 
commands compose the diagnostic command 
group. 


Diagnostic 1 


This command causes an internal microdiagnostic 
test to be performed on the microprocessor, the 
memory modules, and the Series/1 interface 
modules. 


Diagnostic 2 


This command causes an internal microdiagnostic 
test to be performed on the device-dependent logic 
which is associated with the Series/1 to Series/1 
Attachment operation. 


Diagnostic 3 


This command causes a microdiagnostic test to be 

performed on the Series/1 to Series/1 Attachment 
driver/receiver modules. This test manipulates actual 

bus signal lines and should be used only with the Series/1 
to Series/1 Attachment cable disconnected. 


Diagnostic 4 

This command causes a microdiagnostic test to be 
performed on the Series/1 to Series/1 Attachment 
associated cable. This test requires that the attachment 
cable be disconnected from the secondary Series/1 and 
instead be connected to a cable wrap connector. 


Diagnostic Read Jumpers 


This diagnostic command is used to confirm that 
the jumpers have been installed correctly on the 
attachment card. 


Diagnostic Patch Command 


This command is used to modify attachment 
storage. 


Note: Since this command will modify the 
attachment function, it should be used only under 


Appendix B. Diagnostic Commands 


direct authorization of Series/1 product 
engineering, General Systems Division of the IBM 
Corporation. 


Diagnostic Command Structure 


These commands operate under the cycle steal 
mode and should be generated and executed as 
described in the cycle steal portion of this 
document. The DCB structure should be as 
follows: 


Word 
O| Control word 


_1]| Reserved (must = 0) 
2| Reserved (must = 0) 
3| Reserved (must = 0) 
4| Reserved (must = 0) 
5| Reserved (must = 0) 
6} Byte count 


7 | Data address 





DCB Word 0—Control Word 


Addr Diag. 
key operation 


07123456789 1011 15 

Bit 0 This bit is not used and must be 
zero. 

Bit 1 This bit is not used and must be 
zero. 

Bit 2 Input flag (IF). This bit is used and 
must be one. 

Bit 3 This bit is not used and must be 
7ero. 


Diagnostic Commands __—iB-1 


Bit 4 This bit is not used and must be 
zero. 
Bits 5-7 Cycle steal address key. This is a 


program-assigned 3-bit processor 
storage protect access key used by 
the attachment during data transfers 
for storage access authorization. 


Bit 8 This bit is not used and must be 
zero. 

Bit 9 This bit is not used and must be 
Zero. 

Bit 10 This bit is not used and must be 
zero. 


Bits 11-15 Identify the diagnostic operation to 
be performed: 


11010 Diagnostic Read Jumper 
11011 Diagnostic Patch Command 
11100 Diagnostic 1 

11101 Diagnostic 2 

11110 Diagnostic 3 

11111 Diagnostic 4 


DCB Word 1—Not Used, Must be Zero 
DCB Word 2—Not Used, Must be Zero 
DCB Word 3—Not Used, Must be Zero 
DCB Word 4—Not Used, Must be Zero 
DCB Word 5—Not Used, Must be Zero 


DCB Word 6—Byte Count 


The following hex codes are required for the 
associated command. All other codes will result in 
a DCB specification check. 


Diagnostic 1 X‘000C’ 
Diagnostic 2 X‘0004’ 
Diagnostic 3 X‘0004’ 
Diagnostic 4 X‘0004’ 
Diagnostic Read Jumper X‘0002’ 
Diagnostic Patch X‘XXXX’ 


_ DCB. Word. 7—Data Address 


The data address word contains the starting main 
storage address for the data transfer. This starting 
address must be located on an even word 
boundary in Series/1 main storage. 


B-2 GA34-156] 


Diagnostic Command Results 


After completion of a diagnostic command, the 
microdiagnostic testing results can be interpreted 
to determine correct functional operation. The 
results of each diagnostic command are as follows. 


Diagnostic 1 
Yields six words of status in the following format: 


Word 1—Channel Test Word 1 
Pass—X‘5555’ 
Fail—X‘D555’ 

Word 2—-Channel Test Word 2 

, Pass—X‘AAAA’ 
Fail—X‘2AAA’ 

Word 3—Memory Module 1 Test 
Pass—Part number of memory module 1 
Fail—X‘FXXX’ 

Word 4—Memory Module 2 Test 
Pass—Part number of memory module 2 
Fail—XFXXX’ 

Word 5—Memory Module 3 Test 
Pass—Part number of memory module 3 
Fail—X‘FX XxX’ 

Word 6—Memory Test Results on Module 4 
Pass—X‘0000’ 
Fail—X‘XX XX’ (non-zero) 


Diagnostic 2 


Yields two words of status in the following 
format: 


Word 1—Device Logic Test Word 1 
Pass—X‘0000’ 
Fail—X‘1XXX’ 

Word 2—Device Logic Test Word 2 
Pass—X‘0000’ 
Fail—X‘1XXX’ 


Diagnostic 3 


Yields two words of status in the following 
format: 


‘Word 1—Device Logic Test Word 1 


Pass—xX‘0000’ 
Fail—X‘1XXX’ 

Word 2—Device Logic Test Word 2 
Pass—X‘0000’ 
Fail—X‘XXXX’ 


Diagnostic 4 
Yields two words of status in the following 
format: 
Word 1—Device Logic Test Word 1 
Pass—X ‘0000’ 
Fail—X‘1XXX’ 
Word 2—Device Logic Test Word 2 


Pass—xX‘0000’ 
Fail—X‘X XXX’ 


Diagnostic Read Jumper 
Yields one word of status in the following format: 


15 


01234 : 6 7 8 
a, cee 
00000000 RPO D02242 
00000001 RPO D02241 
00000010 Invalid 
00000011 = Invalid 


Data valid 

Not data accepted 

Not ready for data 

RPO D02242 request 
Checksum error detected 
Enable RPO D02242 request 
Active RPQ D02242 

Active RPO D0O2241 


Diagnostic Commands’ B-3 


B-4 GA34-1561 


READER’S COMMENT FORM 


GA34-1561-0 


IBM Series/1 Series/1 to Series/1 Attachment 
RPQs D02241 and D02242 Custom Feature 


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