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PDP-11/45 maintenance 
reference manual 



DEC-ll-HMRMA-A-D 



digital equipment corporation • maynard. massachusetts 



1st Edition November 1972 



Copyright © 1972 by Digital Equipment Corporation 



The material in this manual is for information- 
al purposes and is subject to change without 
notice. 



The following are trademarks of Digital Equipment 
Corporation, Maynard, Massachusetts: 

DEC PDP 
FLIP CHIP FOCAL 
DIGITAL COMPUTER LAB 



CONTENTS 



Pages 

CP INSTRUCTION SET 1-12 

MEMORY MANAGEMENT 13-15 

SEMICONDUCTOR MEMORY 16-23 

CORE MEMORY 24-25 

FLOATING POINT PROCESSOR 26-48 

OP CODE DETERMINATION 49 

MEMORY MAP AND PROGRAM LOADERS 50-53 

ADDRESS MODES 54-56 

CONSOLE 57 

KB11-A BLOCK DIAGRAM 58-59 

MODULE LOCATIONS 60 

DEVICE REGISTER ADDRESSES 61 

ASCII CODE 62 



iii 



INSTRUCTION CARD LEGEND 
OP Fields Time 



n 


Byte(l)/Word(0) 


Add 150 ns if Destination is an odd 


src 


Source Field - 6 Bits 


byte, except where dst = R7 or where 


dst 


Destination Field - 6 Bits 


dst mode equals and src, where 


R 


Register - 3 Bits 


applicable, is 0. 


FS 


Floating Source — 6 Bits 


Add 90 ns/memory reference if mem- 


FD 


Floating Destination — 6 Bits 


ory management KT1 1 is in operation. 


AC 


Floating Accumulator — 2 Bits 


XXX 


Offset - 8 Bits 




YY 


Offset - 6 Bits 




NN 


Count - 6 Bits 




N 


Count — 3 Bits 




A 


AND 




V 


Inclusive OR 




-V- 


Exclusive OR 




( ) 


Contents of 


Condition Codes 


loc 


Location 






Becomes 


* Conditionally Set 


t 


Is Popped from Stack 


Not affected 




Is Pushed onto Stack 


Cleared 




Boolean Not 


1 Set 



1 



GENERAL ADDRESSING MODES 



Format 



Mode @ 



Rn 



*Direct/deferred bit for source and destination address 
**Speeifies how selected registers are to be used 
***Specifies a general register 



Name 



Symbol 



Function 



Register 

Register Deferred 
Auto-increment 



Auto-increment 
Deferred 



Auto-decrement 



Auto-decrement 
Deferred 



Index 



Index Deferred 



%R 
@%R or (R) 
(R)+ 

@(R)+ 

-(R) 

@-(R) 
±X(R) 



@±X(R) 
or 
@(R) 



Register contains operand. 

Register contains the address of the operand. 

Register contains the address of the operand. Register 
contents incremented after reference. 

Register is first used as a pointer to a word containing 
the address of the operand, then incremented (always 
by 2, even for byte instructions). 

Register contents decremented before reference. 
Register contains the address of the operand. 

Register is decremented (always by 2, even for byte 
instructions), then used as a pointer to a word 
containing the address of the operand. 

Value X (stored in a word following the instruction) 
is added to (R) to produce the address of the 
operand. Neither X nor (R) is modified. 

Value X (stored in a word following the instruction) 
and (R) are added and the sum is used as a pointer to 
a word containing the address of the operand. Neither 
X nor (R) is modified. 



(±X is an Index value) 



2 



SPECIAL (PC) ADDRESSING MODES 



Format 



Mode 



Rn 



*Direct/deferred bit for source and destination address 
** Specifies how selected register is to be used 
***Specifies register 7 (PC) 



Mode 


Name 


Symbol 


Function 


2 


Immediate 


#n 


Operand follows instruction. 


3 


Absolute 


@#A 


A follows instruction is the address of the operand. 
(A = absolute address.) 


6 


Relative 


A 


A is the address of the operand. (A = Index value 
following the instruction plus updated PC.) 


7 


Relative Deferred 


@A 


A is the address of a word containing the address of 
the operand. (A = Index value following the 
instruction plus updated PC.) 



BRANCH ADDRESSING 



OFFSET 



(effective address) — (updated PC) 



EFFECTIVE ADDRESS = (offset x two) + (updated PC) 



Branching from location 500 
PC OFFSET 



470 
472 
474 
476 
500 
502 
504 
506 
510 



Instruction 



373 
374 
375 
376 
377 
000 
001 
002 
003 



OFFSET - Number of words to branch 
from updated PC. 

EFFECTIVE ADDRESS - The location 
to branch too. 

UPDATED PC - Location of instruction 
plus two. 



3 



CONDITION CODES OPERATORS: OPR 





15 


5 


4 


3 


2 


1 





Format 


0000000 

1 1 1 


1 
1 




N 


Z 


V 


C 



Condition code operator set or clear condition code 
bits. Indicated bits of the instruction word (3-0) if = 
to a ONE, affect the indicated condition code bits 
NZVC according to bit 4. 

Bit 4 = Clear condition code bits 
Bit 4 = 1 Set condition code bits 



Mnemonic 


Instruction/Operation 


OP Code 


Condition 
Code 
NZVC 


Time 




No Operation 


000240 


- - ~ - 


600 ns 


CLC 


CLear C 


000241 


... o 


600 ns 




c +- n 

^ U 








CLV 


CLear V 


000242 


--0- 


600 ns 




V<-0 








CLZ 


CLear Z 


000244 


-0-- 


600 ns 




Z+-Q 








CLN 


CLear N 


000250 


0--- 


600 ns 




N^O 








ccc 


Clear all CC's 


000257 


0000 


ouu ns 




N,Z, V,C«~0 










No Operation 


000260 




600 ns 




SEt C 


000261 


... 1 


/£AA n c 

ouu ns 




C*-l 








SEV 


SEt V 


000262 


..1 . 


600 ns 




v<-i 








SEZ 


SEtZ 


000264 


- 1 


600 ns 




Z<-1 








SEN 


SEt N 


000270 


1 --- 


600 ns 




N<-1 








sec 


Set all CC's 


000277 


1111 


600 ns 




N, Z, V, C <- 1 










Combinations of the above Clear instructions can be 






ORed together to form combined Clear instructions. 






Clear V and C 


000243 


--00 


600 ns 




v,c<-o 










Combinations of the above Set instructions can be ORed 






together to form combined Set instructions. 








Set N and V 


000272 


1 -1 - 


600 ns 




N, V <- 1 









4 



CONDITIONAL BRANCHES: OPR loc 

15 8 7 

Format op code offset 

11-1462 

The instruction causes a branch to a location defined 
by the sum of the offset (multiplied by 2) and the 
current contents of the program counter, if 
conditions are met. 



TIME: Branch 600 ns/No Branch 300 ns 



Mnemonic 


Instruction/Operation 


OP Code 


BR 


BRanch (unconditionally) 
PC *- loc 


0004+XXX 


BNE 


Branch if Not Equal (zero) 
PC*- loc if Z=0 


0010+XXX 


BEQ 


Branch if EQual (zero) 

PC*- loc if Z=l 


0014+XXX 


BGE 


Branch if Greater or Equal (zero) 
PC*- loc if N=V 


0020+XXX 


BLT 


Branch if Less Than (zero) 
PC*- loc ifN^V 


0024+XXX 


BGT 


Branch if Greater Than (zero) 

PC*- loc if Z=0 and N=V 


0030+XXX 


BLE 


Branch if Less than or Equal (zero) 
PC*- loc if Z=l or N^V 


0034+XXX 


BPL 


Branch if PLus 

PC*- loc if N=0 


1000+XXX 


BMI 


Branch if Minus 

PC*- loc if N=l 


1004+XXX 


rSiil 


Branch if Higher 

PC*- loc if C=0 and Z=0 


1 m n+YYY 

1 U 1 U i AAA 


BLOS 


Branch if LOwer or Same 

PC*- loc if C=l or Z=l 


1014+XXX 


BVC 


Branch if oVerflow Clear 

PC*- loc if V=0 


1020+XXX 


BVS 


Branch if oVerflow Set 

PC*- loc if V=l 


1024+XXX 


BCC 


Branch if Carry Clear 

PC*- loc if C=0 


1030+XXX 


BHIS 


Branch if Higher or Same 
PC*- loc if C=0 


1030+XXX 


BCS 


Branch if Carry Set 

PC*- loc if C=l 


1034+XXX 


BLO 


Branch if LOwer 

PC*- loc if C=l 


1034+XXX 



5 



SINGLE OPERAND INSTRUCTIONS: OPR dst 



Format 



DESTINATION 



Mnemonic 



Instruction/Operation 



OP Code 



Condition 
Code 
NZVC 



Time 



CLR(B) 

COM(B) 

INC(B) 

DEC(B) 

NEG(B) 

ADC(B) 

SBC(B) 

TST(B) 

ROR(B) 



ROL(B) 



CLeaR (Byte) n050DD 
(dst) <- 

COMplement (Byte) n05 1 DD 

(dst) <- -(dst) 
INCrement (Byte) n052DD 

(dst) <- (dst) +1 
DECrement (Byte) n053DD 

(dst) <- (dst) - 1 
NEGate (Byte) n054DD 

(dst) <- —(dst) +1 
ADd Carry (Byte) n055DD 

(dst) <- (dst) + (c) 
SuBtract Carry (Byte) n056DD 

(dst) <- (dst) - (c) 
TeST (Byte) n057DD 

(dst) <- (dst) 
ROtate Right (Byte) n060DD 

(dst) +- (dst) 1 place 
right with (c) 



I 



ROtate Left (Byte) 

(dst) <- (dst) 1 place 
left with (c) 



n061DD 



0100 
**01 



**** 

**00 

**** 



11- 1465 
**** 



300 ns 
300 ns 
300 ns 
300 ns 
300 ns 
300 ns 
300 ns 
300 ns 
300 ns 



300 ns 



ASR(B) 



Arithmetic Shift Right (Byte) 
(dst) <- (dst) shifted 
1 place right 



n062DD 



11-1466 



300 ns 



i 1 i i 



ASL(B) 



SXT 



SWAB 



Arithmetic Shift Left (Byte) 
(dst) «- (dst) shifted 
1 place left 



J L 



_L 



J L 



n063DD 



i i i i i 



Sign eXTend 

(dst)«-0ifN=0 

(dst)«--l ifN=l 
SWAp Bytes 

(dst byte 0) «- (dst byte 1) 

(dst byte l)<-(dst byte 0) 



0067DD 



0003DD 



300 ns 



11- 1468 

-*0- 300 ns 



^00 



300 ns 



6 



Format 



DOUBLE OPERAND INSTRUCTIONS: OPRsrc,dst 

15 12 11 6 5 



OP CODE 



DESTINATION 









Condition 




Mnemonic 


Instruction/Operation 


OP Code 


Code 


Time 






NZVC 




MOV(B) 


MOVe (Byte) 

fH^t^ <- ( <zrr\ 


nlSSDD 




300 ns 


CMP(B) 


CoMPare (Byte) 

(src) + ~ (dst) + 1 
(src) , (dst) unaffected 


n2SSDD 




300 ns 


BIT(B) 


Bit Test (Byte) 

(dst) A (src) 

(dst) , (src) unaffected 


n3SSDD 




300 ns 


BIC(B) 


Bit Clear (Byte) 

(dst) (src) A (dst) 


n4SSDD 


**o - 


300 ns 


BIS(B) 


Bit Set (Byte) 

(dst) «- (src) A (dst) 


n5SSDD 


**Q _ 


300 ns 


ADD 


ADD 

(dst) <- (src) + (dst) 


06SSDD 


•i* *l* *l* 


300 ns 


SUB 


SUBtract 

(dst) <- (dst) + ~ (src) + 1 


16SSDD 


**** 


300 ns 



REGISTER SRC/DST INSTRUCTIONS: OPR src, R 



Format 



OP CODE 









Condition 




Mnemonic 


Instruction/Operation 


OP Code 


Code 
NZVC 


Time 


MUL 


MULtiply 

R,RV1 <- (R)x(src) 


070RSS 




3.3 /xs 


DIV 


DIVide 

quotent R <r (R) , (RV1) 
remainder RV1 J (src) 


071RSS 


**** 


6.9- 

7.5 ms 


ASH 


Arithmetic SHift 

R <- (R)Arith 

shifted N places 
right or left 


072RSS 


**** 


750 ns+ 


ASHC 


Arithmetic SHift Combined 
R,RV1 <~ (R),(RV1) 
Arith shifted 
(two words) N 
places right or left 


073RSS 


**** 


750 ns+ 



1 i i 1 . i 1 i i 1 i i 1 . . 


R+1 






C 




I 1 1 I I I I I I I I I I I I 





C 






K + 1 








1 i i 1 i i 1 i t ! i i 1 i i 




I I I I I I I I I I I I I I I 





11-1471 



XOR 


Exclusive OR 


074RDD 


**0 - 


300 ns 




(dst) <- RV(dst) 










Note: Syntax format is XOR R, dst 









7 



SUBROUTINE INSTRUCTIONS 



Mnemonic 



Instruction/Operation 



OP Code 



Condition 
Code 
NZVC 



Time 



JSR 



Jump to SubRoutine 

tmp <- (dst) 
|(SP) <- (reg) 
reg <- (PC) 
PC (tmp) 



004RDD 



1.5 ms 



Format 



DESTINATION 



OPR R, DST 



RTS 



ReTurn from Subroutine 
PC <~ (reg) 
reg «- (SP)t 



Format 



00020R 



1.2 /is 



MARK 



MARK 



Format 



SP <- (PC) + (2xN) 
PC <- (R5) 
R5 «- (SP)t 



OP CODE 



0064NN 

Note: NN=number of parameters 

6 5 



900 ns 



PROGRAM CONTROL INSTRUCTIONS 



Mnemonic 



Instruction/Operation 



OP Code 



Condition 
Code 
NZVC 



Time 



SPL 



Set Priority Level 

PSW(7-5) <- N 



Format 



00023N 

Note: Kernal mode only 

3 2 

OPR N 



600 ns 



JMP 



JuMP 



PC <- dst 



0001DD 



600 ns 



Format 



DESTI NATION 



OPR DST 



SOB 



Subtract One and Branch 077RYY 

R <- (R)-l 
PC (PC) - (2xOFFSET) if result ^ 

PC <- (PC) if result = 

Note: Branch back only if R^ 



9 8 6 5 



Format 



OPR R, A 



750 ns 



8 



OPERATE INSTRUCTIONS: OPR 



Mnemonic 


Instruction/Operation 


OP Code 


Condition 
Code 
N7VC 


Time 


HLT 


HaLT 

CP 


<- 


Halt 


000000 




750 ns 


WAIT 


WAIT 

wait for interrupt 


000001 






RTI 


ReTurn from Interrupt 

PC «- (SP)t 
PSW <- (SP)t 


000002 


**** 


1.5 jus 


BPT 


Breakpoint Trap 
l(SP) 
l(SP) 
PC 
PSW 


<- 

<- 
«r- 


(PSW) 
(PC) 
(loc 14) 
(loc 16) 


000003 




2.25 jus 


IOT 


I/O Trap 

i(SP) 
l(SP) 
PC 
PSW 


4- 
<- 

<r- 
<- 


(PSW) 
(PC) 
(loc 20) 
(loc 22) 


000004 


**** 


2.25 fis 


RESET 


RESET 
BUS INIT <- TRUE for 10 ms 


000005 




10 ms 


RTT 


ReTurn from Trap 
PC <- 
PSW «- 


(SP)t 
(SP)t 


000006 


#### 


1.5 ms 


EMT 


EMulator Trap 

l(SP) 

l(SP) 
PC 
PSW 


<- 
<- 
<- 
<- 


(PSW) 
(PC) 
(loc 30) 
(loc 32) 


104000- 
104377 


**** 


2.25 jus 


TRAP 


TRAP 

l(SP) 
l(SP) 
PC 
PSW 


<r- 
<r- 
<- 
<- 


(PSW) 
(PC) 
(loc 34) 
(loc 36) 


104400 - 
104777 


**** 


2.25 ms 



Notes: 1. HALT issued in SUPERVISOR or USER mode will generate a trap to vector 4. 

2. SPL or RESET issued in SUPERVISOR or USER mode will be a NO OP. 

3. BPT, IOT, EMT and TRAP push old PC and old PSW onto stack of mode you 
are going to. 



9 



PROCESSOR REGISTER ADDRESSES 



GENERAL REGISTERS 



DISPLAY REGISTER 
15 



RO 


(000000) 


RIO 


Rl 


(000001) 


Rll 


R2 


(000002) 


R12 


R3 


(000003) 


R13 


R4 


(000004) 


R14 


R5 


(000005) 


R15 


R6 


KERNEL SP 


(000006) 


R16 


SUPER SP 


R7 


PC 


(000007) 


R17 


USER SP 



(addressable only by console) 



(000010) 
(000011) 
(000012) 
(000013) 
(000014) 
(000015) 
(000016) 
(000017) 



SWITCH REGISTER 
15 



PROGRAM BREAK REGISTER (PB) 



(777770) 



PROGRAM INTERRUPT REQUEST REGISTER (PIRQ) 
15 14 13 12 11 10 9 7 6 5 3 2 1 



(777772 ) 



7 6 5 4 3 2 1 

^ M ; ^ 



PIA PIA 
PROGRAM INTERRUPT ACTIVE 



STACK LIMIT REGISTER (SL) 
15 8 



( 777774) 



PROCESSOR STATUS WORD (PSW) 
15 14 13 12 11 7 6 5 4 3 2 10 



(777776) 



NOT USED ^_ 



T N Z V C 



-CARRY OUT 
' — OVERFLOW 
-ZERO 
- NEGATIVE 
TRACE 

PROCESSOR PRIORITY 0-7 



- GPR (0 SELECTS REG 0-5 ) 

(1 SELECTS REG 10-15) 



• PREVIOUS MODE 
- CURRENT MODE 



00= KERNEL 
01 = SUPERVISOR 
11 = USER 
10 = ILLEGAL 



10 



MEMORY PARITY CONTROL REGISTER 



15 11 10 9 8 















i 






— H 


— L 
IGH 


I — PARITY DISABLE 

— HALT ENABLE 

OW 4K "I 

> TYPE OF PARITY 
4K J 



1 PARITY ERROR 



11- 1484 



Addressing 



- 8K 


772100 


8K- 16K 


772102 


16K-24K 


772104 


24K - 32K 


772106 


32K - 40K 


772110 


40K - 48K 


772112 


48K - 56K 


772114 


56K - 64K 


772116 


64K - 72K 


772120 


72K - 80K 


772122 


80K - 88K 


772124 


88K - 96K 


772126 


96K- 104K 


772130 


104K- 112K 


772132 


112K- 120K 


772134 


120K-128K 


772136 



Bits 1 1 and 10 are associated with the high-order 4K and low-order 4K of this memory address bank. When 
set to a 1 , they specify odd parity for their respective half banks; when clear, even parity. 

When bit 9 is set, the machine will execute a halt if a parity error occurs; when clear, the machine will 
perform an effective timeout and interrupt through location 4. 

When bit 8 is clear, a parity error will cause an interrupt (or halt as specified in bit 9); if it is set, no action 
will be taken on a parity error. 

When the machine is powered up, the status registers have bit 15 cleared to 0, and the remaining bits set to 
1 : halt, odd parity enable, parity disable, and no error. 



J 



11 



Format 



INTER-MODE COMMUNICATIONS: OPR dst or OPR src 

15 6 5 



OP CODE 



DST /SRC 









Condition 




Mnemonic 


Instruction/Operation 


OP Code 


Code 
NZVC 


Time 


MFPI 


Move From Previous 
Instruction space 

(temp) <- (src) 
4^br J <- (temp J 


0065SS 




1.2/xs 


MFPD 


Move From Previous 

Data space 

(temp) <~ (src) 
|(SP) <- (temp) 


1065SS 


**o - 


1.2 jus 


MTPI 


Move To Previous 
Instruction space 

(temp) <- (SP)t 
(dst) <- (temp) 


0066DD 


**o - 


900 ns 


MTPD 


Move To Previous 
Data space 

(temp) <- (SP)t 
(dst) <~ (temp) 


1066DD 


**o - 


900 ns 



KT1 1-C MEMORY MANAGEMENT STATUS REGISTER 



Status Register (SRO) 



PAGE THAT SET 
ABORT ERROR FLAGS 



15 


14 


13 


12 


11 


10 


9 


8 


7 


6 5 


4 


3 2 1 















1 








I 
1 




1 "™T" 

...J i 





ABORT: NON-RESIDENT 

ABORT :PAGE LENGTH ERR ■ 

ABORT: READ ONLY VIOLATION • 

TRAP • MEMORY MANAGEMENT 

TRAP: OPERATING^ 
SYSTEM TESTER/ 

ENABLE MEMORY 
MANAGEMENT TRAPS ' 



Status Register 1 (SRI) 



Status Register 2 (SR2) 



Status Register 3 (SR3) 



15 11 


10 8 


7 


3 


2 

















ADDRESS: 
777574 


AMOUNT CHANGED 
(2'S COMPLEMENT) 


REGISTER 
NUMBER 


AMOUNT CHANGED 
(2'S COMPLEMENT) 


REGISTER 
NUMBER 


11-1039 


15 

















16-BIT VIRTUAL ADDRESS 


ADDRESS'. 
777576 
















11 - 1040 


15 




4 


3 


2 


1 





















ADDRESS: 
772516g 



1 ENABLES 



SPARE 
KERNEL MODE - 
SUPER MODE - 
USER MODE - 



ADDRESS: 
777572 

ENABLE KT11-C 
PAGE NUMBER 
ADDRESS SPACE I/D 
MODE OF OPERATION 
INSTRUCTION COMPLETE 
MAINTENANCE MODE 

11-1038 



12 



ACTIVE PAGE REGISTERS 



15 14 



Processor Status Word 



— r 

KERNEL (00) 



ArKU 


/ /2J4U 


//2JUU 


1 


772342 


772302 


2 


772344 


772304 


D 


772346 


772306 


4 


772350 


772310 


5 


772352 


772312 


6 


772354 


772314 


7 


772356 


772316 




PAR 


PDR 




KERNEL (00) 


APRO 


772360 


772320 


1 


772362 


772322 


2 


772364 


772324 


3 


772366 


772326 


4 


772370 


772330 


5 


772372 


772332 


6 


772374 


772334 


7 


772376 


772336 




PAR 


PDR 



I space 



r 

SUPERVISOR (01) 



772240 


772200 


772242 


772202 


772244 


772204 


772246 


772206 


772250 


772210 


772252 


772212 


772254 


772214 


772256 


772216 


PAR 


PDR 



D space 
SUPERVISOR (01) 



772260 


772220 


772262 


772222 


772264 


772224 


772266 


772226 


772270 


772230 


772272 


772232 


772274 


772234 


772276 


772236 



1 

USER (11) 



777640 


777600 


777642 


777602 


777644 


777604 


777646 


777606 


777650 


777610 


777652 


777612 


777654 


777614 


777656 


777616 



PAR 



PDR 



USER (11) 



777660 


777620 


777662 


777622 


777664 


777624 


777666 


777626 


777670 


777630 . 


777672 


777632 


777674 


777634 


777676 


777636 



PAR 



PDR 



PAR 



PDR 



PAGE JPOnCSS REGISTER 




PAGE DFjflflMWE R REGISTER 



15 




11 







■ 


lit 




PAGE ADDRESS FIELD 










(PAF) 





13 



15 13 12 



VA 



APF 



DF 



ACTIVE 
PAGE FIELD 



DISPLACEMENT FIELD 



12 







BN 



DIB 



BLOCK NUMBER 



DISPLACEMENT 
IN BLOCK 



15 



m 



12 11 



PAR 



PAF 



PAGE ADDRESS FIELD 



17 



6 5 



PA 



PBN 



DIB 



PHYSICAL BLOCK NUMBER 



VIRTUAL TO PHYSICAL ADDRESS 



11 - 1486 



Virtual to Physical Address 



KERNEL 




KERNEL 
I APR 






USER 
I APR 



ABORT y ~ 



TRAP UPON 
COMPLETION 



YES 




YES 



PA= PAR* 100s + DF 



PHYSICAL 
ADDRESS 
TO UNIBUS 



Memory Management 



15 



M8110 CONTROL 



ON 



11 



M8110 CONTROL 



WRITE DATA (SMCD MEM DATA <17:00>) 



MOSA A - 

B - 



TJTTTT 

17/1*15 14 13 12 

m i 1 1 



SMCC MAD<14:01> 



11 10 09 08 

mi 



MOSA A — 1 
B 

B 

C — 



— -CJ 



2nd K 



16 07 06 05 

Mil 



MOSA A —J 
B — 
B — 
C — 



— -C 



04 03 02 01 00 

lllll 



MOSA A - 
B - 
B - 
C - 



MAD <12 : 03> 



SL DL 



SL DL 



SL DL 



MOSA A - 
D - 



— - CJ 



MOSJ 



MOSA A - 
D - 
C - 

D - 



3rd K 



— -CJ 



MOSA A — 1 
D — 
C — 
D — 



17115 14 13 12 



11 10 09 08 



ffllll I I I I 



n 

)6 0! 

Mil 



-a 



MOSA A —J 
D — 
C — 
D — 



3rd K 



MAD <14, 13,02, 01> 



ACCESS 
CONTROL 
LEVELS 
MOSA 



A 

B «*- 
C ^~ 

D 

SEL 13 
SEL 14 



RREQ 

IN 
PROG 



16 07 06 05 



04 03 02 01 00 

lllll 



READ DATA (SMCE MEM SENSE AMPS <17:00» 



M8110 CONTROL 



MOS Memory Matrix Block Diagram 



MOS Memory System Configuration 



Memory 
Capacity 
Option 



MS11-BC 



Option Type Number 



MS11-BD 



MS11-BM 



Module Complement 



With 

Parity 


Without 
Parity 


(1)M8110 
(1)H746A 
(1)H744A 


(1)M8110 


(1)G401 


(1) G401YA 


4K 


4K 


j 




t 
i 


1 


8K 


8K 


j 




z 


2 


12K 


12K 


; 




3 


3 


16K 


16K 






4 


4 


20K 


20K 






5 


5 


24K 


24K 






6 


6 


28K 


28K 






7 


7 


32K 


32K 






8 


8 



MOS Matrix Selected Address Configuration (4 of 16K) 



MAD 


REQUIRED JUMPERS 


MOS Matrix Memory 
Address Assignment 


14 


13 


(MAD 14) 


(MAD 13) 








C 


A 


0-4095 





1 


C 


B 


4096-8191 


1 





D 


A 


8192-12,287 


1 


1 


D 


B 


12,288-16,383 



MOS Matrix Control Level Generation and Selected Memory 
Address Block (1 of 4K) 



MAD 


CONTROL LEVELS GENERATED 


Memory Address 
Block Selected 


02 


01 


(MAD 02) 




(MAD 01) 










MOSAB 


• 


MOSAA 


0-1023 







1 


MOSAB 


• 


MOSAC 


1024-2047 


1 







MOSAD 


• 


MOSAA 


2048-3071 


1 




1 


MOSAD 


• 


MOSAC 


3072-4095 



17 



M8110 CONTROL 



M8110 CONTROL 



WRITE DATA (SMCD MEM DATA < 17 00> H) 



SMCC MAD <14-01> 



DATA INVERSION 
MEM DATA <17:00> L 



BIPB 



MAD<12,10:01> 



17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 



ROW 




1 

1st 256 LOCATIONS 




BIPD j 


BIPC 


i 
1 

2nd 256 LOCATIONS 




BIPF l 


BIPE 


1 

1 

3rd 256 LOCATIONS 




BIPJ l 


BIPH 


1 

1 

4th 256 LOCATIONS 




l 

BIPL ' 


BIPK 



• CS1 RO 

• CS2 RO 

- CS3 A 

■ ADS SEL 1-8A 

- CS1 R1 
- CS2 R1 

■ CS3 B 

■ ADS SEL 1-8B 

• CS1 R2 

■ CS2 R2 

- CS3 C 

- ADS SEL 1-8C 

- CS1 R3 

- CS2 R3 

- CS3 D 

• ADS SEL 1-8D 



r 



RO RO 

R1 R1 

R2 R2 

R3 R3 



17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 

1 1 i I i 1 1 i 1 1 i 1 1 1 U 1 i 



CS1 
CS2 

ADDRESS 
EXPANDER 

ROW SELECTION 



ADS SEL 1-8 BIPA 

tjti 

A B C D 



MAD<14,13,11> 



Sz 



BRD ENBL 



READ DATA (SMCE MEM SA <17:00> H) 



.WRITE PULSE 
LOW/HIGH 



••-CS3- 



MODULE 
SELECTION 



BIPB 



M8110 
CONTROL 



"1 



WR EN 

LO/HI 



Bipolar Memory Matrix 



18 



Bipolar Memory System Configuration 



Memory 


Option Type Number 


Capacity 


MS11-CC 


MS11-CM 


MS11-CP 


Option 


Module Complement 


With 


Without 


(1)M8110 


(1)M8111 


(1)M8111YA 


Parity 


Parity 


(2)H744A 






IK 




I 




1 




IK 


I 


1 




2K 




I 




2 




2K 


I 


2 




3K 




1 




3 




3K 




3 




4K 








4 




4K 




4 




5K 




2 




5 




5K 


2 


5 




6K 




2 




6 




6K 


2 


6 




7K 




2 




7 




7K 


2 


7 




8K 




2 




8 




8K 


2 


8 





Bipolar Matrix Selected Address Configuration (1 of 16K) 





MAD 






Required Jumpers 




Memory Address 


14 


13 


11 












Assignment 


10 


(MAD 14) 


(MAD 13) 


(MAD 11) 


(MAD 10) 














D 


F 


H 


B 


Oto 1023 











1 


D 


F 


H 


A 


1024 to 2047 








1 





D 


F 


J 


B 


2048 to 3071 








1 


1 


D 


F 


J 


A 


3072 to 4095 





1 








D 


E 


H 


B 


4096 to 5119 





1 





1 


D 


E 


H 


A 


5120 to 6143 





1 


1 





D 


E 


J 


B 


6144 to 7167 





1 


1 


1 


D 


E 


J 


A 


7168 to 8191 













C 


F 


H 


B 


8192 to 9215 










1 


C 


F 


H 


A 


9216 to 10,239 







1 





C 


F 


J 


B 


10,240 to 11,263 







1 


1 


C 


F 


J 


A 


11,264 to 12,287 




1 








C 


E 


H 


B 


12,288 to 13,311 




1 





1 


C 


E 


H 


A 


13,312 to 14,335 




1 


1 





C 


E 


J 


B 


14,336 to 15,359 




1 


1 


1 


C 


E 


J 


A 


15,360 to 16,383 



1 



19 



FA STB US DATA FROM ' 
KB11 PROCESSOR 



PDRB BR< 15:00 >B L 



SMCA PREQ (B) H - 



SMCH UB DATA < 15:00>H 



3 



3 



DATA IN 
MULTIPLEXER 
AND 
PARITY 
GENERATOR 

SMCD 



SMCD MEM DATA<17:00>H 



or 



SMCB DATA LATCH H 



FASTBUS DATA TO 
KB11 PROCESSOR 



BI-DIRECTIONAL 
UNIBUS DATA LINES 



c 



SMCE MEM D<15:00>H 



UNIBUS ADDRESS LINES BUSB A0700L 



UNI BUS 
CONTROL 
LINES 



BUSB CO L] 

BUSB C1 L 

BUSB DC LO L 
BUSA DC LO L 
BUSB MSYNC Lj 
BUSB SSYNC L-*-i 



^ BUSB D<l5O0> ^ 



RECEIVERS /*" 
N ' "D \f 



DRIVERS 
SMCH 



SMCE HIGH BYTE PARITY L 



SMCE LOW BYTE PARITY L 



DATA OUT 

AND 
PARITY 
CHECKER 



c 



SMCE MEM SA<17 00>H 

SMCA SA LATCH (1) H 
SMCB SELECT EVEN H 
SMCB SELECT ODD H 
SMCA PREQ (1) L 



<" > K! 

\| y/ M< 



EMORY 
MATRIX 
MODULES 



SMCE MEM SA<15:00>H 



UNIBUS ADDRESS 



SMCH UBAD<14:02,00>H 



FASTBUS ADDRESS , 



DAPB BAMX <05:02,00> H ANDSAPJ PA < 1 4 : 06 > \ 



FAST BUS ADDRESS LINES 



DAPB BAMX 01 AND SAPJ PA<17:15> 



PARITY REGISTER A OR B DATA OUT 



SMCF MEM L 
SMCA MEM SYNC (B) L 
UBCA CONTROL OK H 
UBCC MEM BUS CO L 
UBCC MEM BUS C1 L 
TMCE BEND CLR L 
TMCE BUST OUT L 



FAST BUS 
AND 
UNIBUS 
ADDRESS 
DECODERS 



SMCH UBC1 H - 
SMCH UBC1 L - 
SMCH MSYNC (B) L - 

I SMCH POWER CLR H - 
\ SMCH UBCO L - 



SMCF UB MUX MAD 12 H 



SMCF FB MUX MAD 12 H 



ADDRESS 
MULTIPLEXER 
AND 

MAD REGISTERL 



04:01 >(1H ^ 



SMCF PAR REG STB A H 



SMCF PAR REG STB B H 







PARITY REGISTERS A AND B DATA 



UBCA CONTROL OK H 

UBCB PERF ACKN L 

SMCB PERF L 

SMCB PE HALT L 



REFRESH ADDRESS 
SMCB RFAD<04:00>H 



REFRESH 
AND 

PARITY 
LOGIC 



SMCF 
BREQ L 



SMCA ACCESS READY LATCH H 



SMCA MEM CO H 



SMCA MEM C1 H 



SMCB 
REF 
REQ L 



SYNCHRONIZATION AND TIMING 



SMCA CENABLE L 
SMCA PRECHARGE L 
SMCA WRITE PULSE LOW L 
SMCA WRITE PULSE HIGH L 



M81 10 Semiconductor Memory Control Module, Block Diagram 



MOS 



BIPOLAR 



SAPJ PA12 H 
SAPJ PA14 H 

SMCF 
DECODE 14 H * 
SAPJ PA11 H 

SAPJ PA13 H 



SMCF 
DECODE 13 H 



1 




16 


SMCF FB 


2 




15 


MUX 14/12 H 




3 




14 


SMCF FB 




4 




13 


MUX DEC 14 H 


5 




12 


SMCF FB 


6 




11 


MUX 13/11 H 




7 




10 


SMCF FB 




8 




9 


MUX DEC 13 H 




E67 







SAPJ PA12 H 
SAPJ PA14 H ■ 

SMCF 
DECODE 14 H ' 
SAPJ PA11 H 

SAPJ PA13 H 



SMCF 
DECODE 13 H 



1 




16 


SMCF FB 


2 




15 


MUX 14/12 H 




3 




14 


SMCF FB 




4 




13 


MUX DEC 14 H 


5 




12 


SMCF FB 


6 




11 


MUX 13/11 H 




7 




10 


SMCF 




8 




9 


MUX DEC 13 H 




E67 







Fastbus Address Multiplexing (14: 1 1), Required E67 Jumpers 



SMCH UBAD 01 H - 
SMCH UBAD 15 H 
SAPJ PA15 H 
DAPB BAMX 01 H 



1 




16 




2 




15 








3 




14 












4 


13 














5 


12 
















6 




11 














7 


E86 


10 












8 


9 















SMCF UB MUX MAD 12 H 
SMCF UB MUX MAD 15 H 

■ SMCF FB MUX MAD 12 H 

■ SMCF FB MUX MAD 15 H 



MAD Multiplexing, Required E86 Jumpers 



MOS 



Bl POLAR 



SMCH UBAD 12 H 
SMCH UBAD 14 H 

SMCF 
DECODE 14 H 
SMCH UBAD 11 H 

SMCH UBAD 13 H 



SMCF 
DECODE 13 H 



1 




16 


SMCF UB 


2 




15 


MUX 14/12 H 




3 




14 


SMCF UB 




4 




13 


MUX DEC 14 H 


5 




12 


SMCF UB 


6 




11 


MUX 13/11 H 




7 




10 


SMCF UB 




8 


E78 V 


9 


MUX DEC 13 H 









SMCH UBAD 12 H ■ 
SMCH UBAD 14 H ■ 

SMCF 
DECODE 14 H 
SMCH UBAD 11 H • 

SMCH UBAD 13 H 



SMCF 
DECODE 13 H ' 



1 




16 


SMCF UB 


2 




15 


MUX 14/12 H 




3 




14 


SMCF UB 




4 




13 


MUX DEC 14 H 


5 




12 


SMCF UB 


6 




11 


MUX 13/11 H 




7 




10 


SMCF UB 




8 


E78 


9 


MUX DEC 13 H 









Unibus Address Multiplexing (14: 1 1>, Required E78 Jumpers 



21 



Fastbus/Unibus Memory Address (Assign and Decode) 



Fastbus/Unibus 
Address Decoder Bits 



Memory Address 
Assignment 



17 


16 


15 


14 


13 


Bipolar 


MOS 


C 


D 


E 


F 


H 

















0-4K 


0-1 6K 
























1 


4-8K 












X 











1 





8-12K 










X 













1 


1 


12-16K 










X 


X 








1 








16-20K 


16-32K 






X 












1 





1 


20-24K 








X 




X 








1 


1 





24-28K 








X 


X 










1 


1 


1 


28-32K 








X 


X 


X 





1 











32-36K 


32-48K 




X 











1 








1 


36-40K 






X 






X 





1 





1 





40-44K 






X 




X 







1 





1 


1 


44-48K 






X 




X 


X 





1 


1 








48-52K 


48-64K 




X 


X 









1 


1 





1 


52-56K 






X 


X 




X 





1 


1 


1 





56-60K 






X 


X 


X 







1 


1 


1 


1 


60-64K 






X 


X 


X 


X 


1 














64-68K 


64-80K 


X 










1 











1 


68-72K 




X 








X 










1 





72-76K 




X 






X 












1 


1 


76-80K 




X 






X 


X 







1 








80-84K 


80-96K 


X 




X 











1 





1 


84-88K 




X 




X 




X 







1 


1 





88-92K 




X 




X 


X 









1 


1 


1 


92-96K 




X 




X 


X 


X 















96-100K 


96-1 12K 


X 


X 


















1 


100-104K 




X 


X 






X 









1 





104-108K 




X 


X 




X 











1 


1 


108-1 12K 




X 


X 




X 


X 






1 








112-116K 


112-128K 


X 


X 


X 










1 





1 


116-120K 




X 


X 


X 




X 






1 


1 





120-124K 




X 


X 


X 


X 








1 


1 


1 


124-128K 




X 


X 


X 


X 


X 



M81 10 Jumpers (E87) 
(NOTE l,NOTE 2) 



NOTES: 1. "X" denotes jumper to be cut. 

2. Jumpers F and H are left intact for all MOS memory assignments. 



22 



+ 5V 



MUX < 1 5:1 3> H 
MUX 14/12, 13/11 SAPJ PA <17: 16> H 



E77 

V 




C-H 



C-H 



i r 



MUX <15 : I3> H 
SAPJ PA <17. 16> H 



\ J-M 



SMCF DECODE <17:13> 
(TO UNIBUS 
DECODE CKT, 
E67.E78) 




SMCF MEM H 



Simplified Memory Address Decode (SMCF) 



MOS/Bipolar Module Addressing 



Fastbus/Unibus 
Memory Address Bits 


Memory Address 
Assignment 


Remove Jumpers 


FB MUX 
14/12 


FB MUX 
13/11 


MOS 


Bipolar 


Fastbus 
Address 
Select 


Unibus 
Address 
Select 








0-4095 


0-1023 


J 


N 





1 


4096-8191 


1024-2047 


K 


P 


1 





8192-12287 


2048-3071 


L 


R 


1 


1 


12288-16383 


3072-4095 


M 


S 



MOS/Bipolar Memory Addressing 



No. of Memory 


Memory 


Remove Jumpers 


Modules in 


Capacity 


Fastbus 


Unibus 


Memory* 


MOS 


Bipolar 


Address 


Address 








Select 


Select 


1 


4K 


IK 


J 


N 


2 


8K 


2K 


JK 


NP 


3 


12K 


3K 


JKL 


NPR 


4 


16K 


4K 


JKLM 


NPRS 



♦Connected to one M8110 Control. 



23 



1% 



u 

N 
I 

B 
U 
S 



BUS A<13:01>,<14> 



m 

BUS A<17.«l>,<00> 



BUS MSYN 



BUS C<hO> 



BUS DC LO 



BUS INIT 



BUS SSYN 



MEMORY 
SELECTION 
TIMING 

a 

CONTROL 



1 — °r — ^ 

RC R V 

— ^L_y 



BUS D<15:8>PB 



</ XM'T 



BUS D<7=D>PA 



CLK 



LOAD 0,1 H 



RESET 0,1 L 



STROBE 0,1 L 



DATA OUT H 



TINH 0,1 H 



READ H 



TNAR 



TWID 



LOAD H 



LOAD 1 H 



CLK H- 



TNAR H 



TWID H 



READ H 



13 


01 

- (H) 


ADDRESS 


REGISTER 


ADDRESS 

{ 

X-Y SW 

a dr 


DECODER 

ITCHES 
VERS 




STACK 
8K X 18 (16) 



SENSE 
AMPLIFIERS 



Pi 




Pi 


-* 


B|15 


8 


A|7 






STROBE 
1 H 



STROBE 
H 



RESET 1 L- 



P! 




p i 




BJ15 


8 


A!7 






DATA BUFFER 



-o ^xm't| 



• DATA OUT H 



TWID H 



PA 
8 



15 
~PB~ 



-RESET L 



TINH 0,1 H- 



MM- 11 S, Simplified Block Diagram 



Memory Bank 
(words) 


Machine Address 
(words) 


Device Address Jumpers (1) 


W6 

Al4 (?5 A01 


W4 
A1S 


W3 
A16 


W2 
A17L 


0— 8K 


000000—037776 


In 


In 


In 


In 


8-16K 


040000—077776 


Out 


In 


In 


In 


16-24K 


100000-137776 


In 


Out 


In 


In 


24-32K 


140000-177776 


Out 


Out 


In 


In 


32-40K 


200000-237776 


In 


In 


Out 


In 


40-48K 


240000-277776 


Out 


In 


Out 


In 


48 -56K 


300000-337776 


In 


Out 


Out 


In 


56-64K 


340000-377776 


Out 


Out 


Out 


In 


64-72K 


400000-437776 


In 


In 


In 


Out 


72-80K 


440000-477776 


Out 


In 


In 


Out 


80-88K 


500000-537776 


In 


Out 


In 


Out 


88-96K 


540000-577776 


Out 


Out 


In 


Out 


96-104K 


600000-637776 


In 


In 


Out 


Out 


104-1 12K 


640000-677776 


Out 


In 


Out 


Out 


112-120K 


700000-737776 


In 


Out 


Out 


Out 


120-128K 


740000-767776 


Out 


Out 


Out 


Out 



( 1 ) W5 and W 1 must be installed and W9 must be removed. 

(2) The memory can be interleaved as 16K only, using two adjacent contiguously addressed 8K 
banks. When two 8K banks are interleaved, jumpers W7 and W8 must be in the configuration 
shown by the dotted lines. Bit A01 goes to the device selector gate controlled by jumper W6. 
One 8K bank must have W6 installed and the other must have W6 removed. 

When not interleaved, jumpers W7 and W8 must be in the configuration shown by the solid 
lines. Bit A 1 4 goes to the device selector gate controlled by jumper W6. 



W7 




W8 



NON- INTERLEAVED INTERLEAVED 

(TWO 8K BANKS REQUIRED) 




Jumper W1 is for test purposes only. It must be installed for normal operation. 

** Jumper W11 should be removed for normal operation. When installed the memory 
responds to DATI only, regardless of state of control lines COO and C01. 

NOTE; 

Jumpers W5,W7,and W8 must remain in the factory installed positions. 



Device Decoding Guide 



25 




FP11 



INTEGER = 5 



SHORT INTEGER (I) 



H WORD 1- 

15 14 



LONG INTEGER (L) 31 30 



■ WORD 1 - 



H h 


















5 


h 


WORD 2 




15 14 


H 



















5 



INTEGER = - 5 



SHORT INTEGER (I) 



15 14 



- WORD 1 H 



LONG INTEGER (L) 31 30 



N WORD 1 H ^ 



WORD 2 H 

16 15 14 o 



Integer Formats 



31 30 



■ WORD 1 

23 22 



SINGLE - PRECISION 
FLOATING POINT (F) 



EXP 



. , WORD . , WORD 



, WORD 
H- 4 " 



63 62 



55 54 



DOUBLE-PRECISION 
FLOATING POINT (D) 



FRACTION 



11 -0802 



S = Sign 

EXP = Exponent in excess 200g notation 

Fraction = 23 or 55 bit fraction in sign and magnitude format. 
Binary point between bits 22 and 23 for F format or between bits 
54 and 55 for D format. 



Floating-Point Data Formats 



27 



INTERRUPT ENABLES MODE BITS CONDITION CODES 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



FER 
FID 

NOT USED 
NOT USED 
FtUV 
FIU 
FIV 
FIC 
FD 
JL 
FT 
FMM 
FN 
FZ 
FV 
FC 



Status Register Format 



FER — This bit indicates an error condition of the FP1 1 . 

FID (Floating Interrupt Disable) — All interrupts by the 
FP1 1 are disabled when this bit is on. 

FIUV (Floating Interrupt on Undefined Variable) — When 
this bit is set and a minus is obtained from memory, an 
interrupt occurs. If the bit is not set, minus can be 
loaded and stored; however, any arithmetic operation is 
treated as if it were a positive 0. 

FIU (Floating Interrupt on Underflow) - When this bit is 
set, an underflow condition causes a floating underflow 
interrupt. The result of the operation causing the 
interrupt is correct except for the exponent, which is off 
by 400 8 . If the FIU bit is not set and underflow occurs, 
the result is set to zero. 

FIV (Floating Interrupt on Overflow) - When this bit is 
set, floating overflow causes an interrupt. The result of 
the operation causing the interrupt is correct except for 
the exponent, which is off by 400 8 . If the FIV bit is not 
set, the result of the operation is the same; the only 
difference is that the interrupt does not occur. 

FIC (Floating Interrupt on Integer Conversion Error) - 

When this bit is set, and the Store Convert Floating to 
Integer instruction causes FC to be set (indicating a 
conversion error), an interrupt occurs. When a conver- 
sion error occurs, the destination register is cleared and 
the source register is untouched. When FIC is reset, the 



result of the operation is the same; however, no 
interrupt occurs. 

FD (Double-Precision Mode Bit) - This bit, when set, 
specifies double-precision format and, when reset, speci- 
fies single-precision format. 

IL (Long-Precision Integer Mode Bit) - This bit is 
employed during conversion between integer and float- 
ing-point format. If set, double-precision, 2's comple- 
ment integer format of 32 bits is specified; if reset, 
single -precision 2's complement integer of 16 bits is 
specified. 

FT (Truncate Bit) — This bit, when set, causes the result of 
any floating-point operation to be truncated rather than 
rounded. 

FMM (Maintenance Mode Bit) — This bit is used to enable 
special maintenance logic. 

FC, FV, FZ, and FN — These bits are the four floating- 
point condition codes, which can be loaded in the CPU's 
C, V, Z, and N condition codes, respectively. This is 
accomplished by the Copy Floating Condition Codes 
(CFCC) instruction. To determine how each instruction 
affects the condition codes, refer to the instruction 
description in the PDP-11 Handbook. 

For the Store Convert Floating to Integer instruction 
(which converts a floating-point number to an integer), the 
FC bit is set if the resulting integer is too large to be stored 
in the specified register. 



28 



PROCESSING OF FLOATING-POINT EXCEPTIONS 



A total of seven possible interrupts can occur. These seven possible interrupt exceptions are encoded in the 
FPU Exception Code Register (FEC). The interrupt exception codes represent an offset into a dispatch 
table , which routes the program to the right error handling routine. The dispatch table is a function of the 
software. The offset for each exception code is shown below followed by a brief description. 



FPU Exception Code 


Definition 


(Base 8) 




2 


Floating Op Code Error — The FP1 1 causes an 




interrupt for an erroneous op code if the FID 




bit is not set. 


4 


Floating Divide by Zero — Division by zero 




causes an interrupt if the FID bit is not set. 


6 


Floating Integer Conversion Error 


10 


Floating Overflow 


12 


Floating Underflow 


14 


Floating Undefined Variable 


16 


Microbreak Trap 




NOTE 


The traps for exception codes 6, 10, 12, and 14 can be 


enabled in the FPU's Program Status Register. 



In addition to the FEC register, the FPU contains a 16-bit Floating Exception Address register (FEA), 
which stores the address of the last floating-point instruction that caused a floating-point exception. 



DATA 
OUT 



DATA OR EXPONENT 



EXPONENT 
CALCULATION 
LOGIC 

(16 BITS) 



TV 



(16 BITS) 





SCRATCH PAD 




ACCUMULATORS 


ACC 0-5- GENERAL PURPOSE 




REGISTERS ACCES- 




SIBLE TO PRO- 




GRAMMER 


ACC 


6-INTERNAL TEMPO- 




RARY STORAGE - 




NOT ACCESSIBLE 




TO PROGRAMMER 


ACC 


7 -INTERNAL STORAGE 




OF STATUS NOT 




ACCESSIBLE TO 




PROGRAMMER 




EXCEPT VIA STORE 




STATUS INSTRUC- 




TION 



DATA OR EXPONENT 



(16 BITS) 



DATA IN 
(16 BITS) 



(32 BITS ) 



FRACTION 
CALCULATION 
LOGIC 

(60 BITS) 



(32 BITS) 



FPU Simplified Block Diagram 



29 



FPU INSTRUCTION FORMATS 





15 




12 


11 


8 


7 6 


5 







F1 


OC =17 


FOC 


AC 


FSRC/FDST 




15 




12 


11 




6 


5 







F2 


OC = 17 


FOC 


FDST 




15 




12 


11 


8 


7 6 


5 







F3 


OC =17 


FOC 


AC 


SRC/DST 




15 




12 


11 




6 









F4 


OC = 17 


FOC 


SRC/DST 




15 




12 


11 













F5 


OC =17 


FOC 



11 - 800 



The 2-bit AC field (bits 6 and 7) allows selection of scratch pad accumulators through 3 only. If address 
mode is specified with formats Fl or F2, bits 2 through are used to select the floating-point 
accumulator. Only accumulators 5 through can be accessed m this manner. If accumulators 6 or 7 are 
specified, the FP1 1 traps if the interrupt is enabled. 

The fields of the various instruction formats 



Mnemonic 


Description 


OC 


Operation Code — All floating-point instructions are 
designated by a 4-bit op code of 17 8 . 


FOC 


Floating Operation Code — The number of bits in this field 
varies with the format and is used to specify the actual 
floating-point operation. 


SRC 


Source — A 6-bit source field identical to that in a PDP- 1 1 
instruction. 


DST 


Destination — A 6-bit destination field identical to that in a 
PDP-11 instruction. 


FSRC 


Floating Source — A 6-bit field used only in format F 1 . It is 
identical to SRC, except in mode when it references a 
floating-point accumulator rather than a CPU general 
register. 


FDST 


Floating Destination — A 6-bit field used in formats F 1 and 
F2. It is identical to DST, except in mode when it 
references a floating-point accumulator instead of a CPU 
general register. 


AC 


Accumulator — A 2-bit field used only in formats F3 and 
Fl to specify accumulators through 3. 



30 



Instruction Format 


Instruction 

J. 1131.1 Uv llvJll 


lVlllClllUUlC 


F 


1 


Ann 


ADDF FSRP AC 








Annn fsrp ac 






t n An 


TnFFQRT AT 








TnnFQRP AT 






QTTRTR APT 
jUDI ivrYt 1 


QJTRF FSRP AT 








QTTRn FQRP Af 






PDMPARF 


PMPF AT Fn^T 








TMPn AT FnST 






MTTT TTPT Y 


MTTT F FQRP AT 








MTTT n FQPT AT 






iV/fnrvf tt ci 

iVlUJJULyU 


MnnF fqpp at 

iVlvjjJr r N Kt, At 








Mnnn fqpp at 






QTTlI? F 


QTF AT FnQT 
olr AL, r JJk>l 








QTn AP FnQT 
olJJ At, rJJol 






F>T\/TnF 
JJ1 VlUJc/ 


nTVF FQPP AT 








nTvn FQPP AP 
LJl V U roJ\l/, At 






t n An ppiisjvfpt 

JLw Pllj V JJiXv 1 


TnPFnFQPP AP 
LUtr roi\t, /vt 








TnPnFFQPP AP 
LJJtLT roivt, /\t 


Fl 


o i wrvii tt/iN v nrv l 


QTPFn AP FnQT 








QTPnF AP FnQT 


F2 


PT FAR 


PT RF FDST 








PT Rn FnQT 






TFQT 


TSTF FDST 








TQTD FDST 

1 J 1 LJ 1 l^/O 1 






ARQOT TTTF 


ARQF FnQT 








ARQn Fnor 

£\LJ vjLJ L LJvJ l 


F2 


NFPATF 


NFOF FnST 








NFGD FDST 

1 ~ JL^ VJ LJ L LJ lj 1 


F 


3 


T OAn FYPONFNT 


T DFXP SRP AP 






T OAn PONVFRT TNTFOFR TO FT OATTNPr 


T PnTF SRP AP 








t nPTn QRP AP 








T PnT F QRP AP 








T nPT n QRP AP 

L-jLJ^L-jLJ kjIVV/, r\ V. 








QTFYP AP nQT 


F3 


CTHRF POMVFRT FT OATTTxTP TO TNTFCFR 


QTPFT AP nQT 
01 tn /\t, i/oi 








QTPFT AP nQT 

O 1 V/T /\t, LJvj 1 








QTPnT AP nQT 
iJltUl /\t, Uol 








QTPnT AP nQT 


F4 


t n a n pp 1 To pt> or 1 p a \ji qt a tt tq 

LUA1J rr 11 S rKUulvAlVl ol Al Uo 


T nFPQ QPP 




) 


QTHP F FP 1 I'o PP Of DAM QT A TT TQ 
o 1 UJtvC/ rrll S rKUuKAM jIAI Uj 


QTFPQ nQT 


F4 


CTHDti FP1 1 'o CTATTTQ 
olUlvc rrl 1 S olAl Uo 


QTQT nQT 
1 1 Do 1 


F5 


rnpv ft r^ATTXTr" rrixmTTTPnvT rnnFQ 


PFPP 
L,r tt 






cct ct OATTXTP MHnF 
oii 1 r LUA 1 UN Lr 1V1U Ltd 


QFTF 






QFT TlxTTFPFP MPinF 


QFTT 






T OAn TTRPF \Y PFHTQTFR 

Lj\JJ\xJ Ur>l\.J_//\Jv IvJ_/vJltJ 1 J_>Iv 


T nTTR 






LOAD SHIFT COUNTER 


LDSC 






STORE AR REGISTER IN ACO 


STAO 






MAINTENANCE RIGHT SHIFT 


MRS 






STORE QR REGISTER IN ACO 


STOO 






SET DOUBLE MODE 


SET D 


F5 


SET LONG INTEGER MODE 


SETL 



31 



DOUBLE OPERAND INSTRUCTIONS: OPR FSRC, AC 

OPR AC, FDST 



15 12 11 8 7 6 5 



Format n 



OC = 17 


FOC 


AC 


FSRC/FDST 



Mnemonic 


Instruction/Operation 


OP Code 


MULF FSRC, AC 
MULD FSRC, AC 


Floating Multiply 

AC <- (AC) * (FSRC) if [(AC) * (FSRC)] > LOLIM; 

else AC <- 
FC<-0 

FV <- 1 if (AC) > UPLIM; else FV+-0 
FZ<-lif(AC) = 0;else FZ<-0 
FN <- 1 if (AC) < 0; else FN <- 


171000 + AC 


* 100 + FSRC 


MODF FSRC, AC 
MODD FSRC, AC 


Floating Modulo 

AC V 1 <- integer part of [(AC) * (FSRC)] 
AC <- fractional part of (AC) * (FSRC) - (AC V 1) if 
1 ^acj yr oKt ) \ ^ L/Ui^iivi or riu — l , eise /\^ ^ u 
FC *-0 

FV <- 1 if (AC) > UPLIM; else FV <- 
FZ«-lif(AC) = 0;else FZ«-0 
FN <- 1 if (AC) < 0; else FN«-0 

The product of (AC) and (FSRC) is 48 bits in 
single-precision floating-point format or 59 bits in 
double -precision floating-point format. The integer part 
of the product [(AC) * (FSRC)] is found and stored in 
AC V 1 . The fractional part is then obtained and stored 
in AC . Note that multiplication by 1 can be done with 
zero error, allowing decimal digits to be stripped off 
with no loss in precision. 


171400+ AC 


* 100 + FSRC 


ADDF FSRC, AC 
ADDD FSRC, AC 


Floating Add 

AC <- (AC) + (FSRC) if [(AC) + (FSRC)] > UPLIM 

else AC <- 
FC <-0 

FV <- 1 if (AC) > UPLIM; else FV+-0 
FZ <- 1 if (AC) = 0; else FZ «- 
FN «- 1 if (AC) < 0; else FN <- 


172000 + AC 


* 100 + FSRC 


LDF FSRC, AC 
LDD FSRC, AC 


Floating Load 
AC <- (FSRC) 
FC«-0 
FV<-0 

FZ <- 1 if (AC) = 0; else FZ <- 
FN «- 1 if (AC) < 0; else FN <- 


172400 + AC 


* 100 + FSRC 


SUBF FSRC, AC 
SUBD FSRC, AC 


Floating Subtract 

AC <- (AC) - (FSRC) if [(AC) - (FSRC)] > LOLIM 

else AC <- 
FC^-0 

FV <- 1 if (AC) > UPLIM, else FV<-0 
FZ <- 1 if (AC) = 0; else FZ<-0 
FN <- 1 if (AC) <- 0; else FN <- 


173000 + AC 


* 100 + FSRC 



32 



DOUBLE OPERAND INSTRUCTIONS: OPR FSRC, AC (Cont.) 

OPR AC, FDST 



Mnemonic 


Instruction/Operation 


OP Code 


CMPF FSRC, AC 
CMPD FSRC, AC 


Floating Compare 
(FSRC) - (AC) 
FC«-0 
FV^O 

FZ <- 1 if (FSRC) - (AC) = 0; else FZ *- 
FN <- 1 if (FSRC) - (AC) < 0; else FN <- 


173400 + AC * 100 + FDST 


STF AC, FDST 
STD AC, FDST 


Floating Store 
FDST <- (AC) 
FC^FC 
FV«-FV 
FZ <-FZ 
FN <- FN 


174000 + AC * 100 + FDST 


DIVF FSRC, AC 
DIVD FSRC, AC 


Floating Divide 

AC «- (AC)/(FSRC) if [(AC)/(FSRC)] > LOLIM; else 

AC<~0 
FC «-0 

FV<-1 if(AC)>UPLIM 
FZ<-lif (AC) = 0; else FZ«-0 
FN <- 1 if (AC) < 0; else FN <- 


174400 + AC * 100 + FSRC 


STCFD AC, FDST 
STCDF AC, FDST 


Store Convert from Floating to Double or Double to 

Floating 
FDST-C FDVDF (AC) 
FC<-0 r '^ vlJ ' r 
FV <- 1 if (AC) > IJPLIM; else FV <- 
FZ <- 1 if (AC) = 0; else FZ <- 
FN <- 1 if (AC) < 0; else FN <- 


176000 + AC * 100 + FDST 
F,D - single -precision to double -precision 
floating 

D,F - double-precision to single -precision 
floating 


LDCDF FSRC, AC 
LDCFD FSRC, AC 


Load Convert Double to Floating or Floating to Double 

ac " c fdvdf( fsrc ) 

FC+-0 ' ' 

FV ^ 1 if (AC) > UPLIM; else FV <- 
FZ <- 1 if (AC) = 0; else FZ <- 
FN <- 1 if (AC) < 0; else FN «- 

If the current format is single-precision floating-point 
(FD = 0), the source is assumed to be a double-precision 
number and is converted to single precision. If the 
floating truncate bit is set the number is truncated; 
otherwise, it is rounded. If the current format is 
double-precision (FD = 1), the source is assumed to be a 
single -precision number and is loaded left justified in the 
AC. the lower half of the AC is cleared. 


177400 + AC* 100+ FSRC 
F,D — single -precision to double-precision 
floating 

D,F — double-precision to single -precision 
floating 



33 



Format F2 



SINGLE OPERAND INSTRUCTIONS: OPR FDST 

15 12 11 6 5 



OC = 17 



FOC 



FDST 



Mnemonic 


Instruction/Operation 


OP Code 


CLRF FDST 
CLRD FDST 


Clear 

FDST «- 
FC«-0 
FV<-0 
FZ<-1 

FN<-0 


170400+ FDST 


TSTF FDST 
TSTD FDST 


Test 

FDST <- (FDST) 

FC<-0 

FV<-0 

FZ <- 1 if (FDST) = 0; else FZ <- 
FN <- 1 if (FDST) < 0; else FN «- 


170500+ FDST 


ABSF FDST 


Absolute 

rlJi>l ^ — (rUol ) 11 (JrDo 1 ) <^ U, else rJJM (^rlJo 1 J 

FC+-0 

FV<-0 

FZ «- 1 if (FDST) = 0; else FZ <- 
FN^O 


170600+ FDST 


NEGF FDST 
NEGD FDST 


Negate 

FDST <- ~ (FDST) 

FC«-0 

FV<-0 

FZ <- 1 if (FDST) = 0; else FZ <- 
FN <- 1 if (FDST) < 0; else FN <- 


170700 + FDST 



DOUBLE OPERAND INSTRUCTIONS: OPR SRC 

OPR DST 



Format f 3 



15 


12 


11 




8 


7 6 


5 




O 


OC=17 


FOC 


AC 


SRC/DST 



Mnemonic 


Instruction/ Operation 


OP Code 


STEXP AC, DST 


Store Exponent 

DST <- AC EXPONENT- 200 

FC+-0 

FV<-0 

FZ <- 1 if (DST) = 0; else FZ <- 
FN <- 1 if (DST) < 0; else FN <- 
C<-FC 

v<-fv 

N <- FN 


175000+ AC * 100 + DST 



34 



DOUBLE OPERAND INSTRUCTIONS: OPR SRC (Cont.) 

OPR DST 



Mnemonic 



Instruction/Operation 



OP Code 



STCFI AC, DST 
STCFL AC, DST 
STCDI AC, DST 
STCDL AC, DST 



LDEXP SRC, AC 



LDCIF SRC, AC 
LDCID SRC, AC 
LDCLF SRC, AC 
LDCLD SRC, AC 



Store Convert from Floating to Integer 

Destination receives converted AC if the resulting integer 

number can be represented in 16 bits (short integer) or 

32 bits (long integer). Otherwise, destination is zeroed 

and C bit is set. 

FV^O 

FZ <- 1 if (DST) = 0; else FZ *- 

FN «- 1 if (DST) < 0; else FN <- 

C«-FC 

V<-FV 

Z«-FZ 

N+-FN 

When the conversion is to long integer (32 bits) and 
address mode or immediate mode is specified, only the 
most significant 16 bits are stored in the destination 
register. 

Load Exponent 

AC SIGN <- (AC SIGN) 

AC EXP <- (SRC) + 200 

AC FRACTION (AC FRACTION) 

FC^O 

FV^l if(AC)>UPLIM 
FZ«-lif(AC) = 0;elseFZ = 
FN^-lif(AC)<0; else FN = 



FL,FD ( SRC ) 



Load and Convert from Integer to Floating 
AC <-Ct 
FC<-0 
FV^O 

FZ^lif(AC) = 0;elseFZ<-0 
FN <- 1 if (AC) < 0; else FN <- 

CfL,FD specifies conversion from a 2's complement 
integer with precision I or L to a floating-point number 
of precision F or D. If integer flip-flop IL = 0, a 16-bit 
integer (I) is specified; if IL = 1 , a 32 bit integer (L) is 
specified. If floating-point flip-flop FD = 0, a 32-bit 
floating-point number (F) is specified; if FD = 1 , a 64-bit 
floating-point number (D) is specified. If a 32-bit integer 
is specified and addressing mode or immediate mode is 
used, the 16-bits of the source register are left justified, 
and the remaining 16-bits are zeroed before the conver- 
sion. 



175400 + AC * 100 + DST 



STCFI - Single float to single integer 
STCFL — Single float to long integer 
STCDI - Double float to single integer 
STCDL - Double float to long integer 



176400+ AC * 100 + SRC 



177000 + AC * 100 + SRC 
LDCIF — single integer to single float 
LDCID — single integer to double float 
LDCLF — long integer to single float 
LDCLD - long integer to double float 



35 



15 



OPERATE INSTRUCTIONS: OPR 

12 11 



Format fs 



OC =17 



FOC 



Mnemonic 



Instruction/ Operation 



OP Code 



Copy Floating Condition Codes 

C^-FC 

V«-FV 

Z*-FZ 

N <- FN 

Set Floating Mode 
FD*-0 

Set Integer Mode 
FL^O 

Load Microbreak Register 

This instruction is a maintenance instruction in which 
the content of register R3 is gated into the UB register. 
When the control ROM address register matches the 
contents of the UB register, a scope sync is generated. If 
the FPU is in maintenance mode (FMM=1), an interrupt 
is also generated and the FPU traps to the Ready state. 
A UB interrupt cannot be generated by the Ready state 
or by the states that are used to generate the UB 
interrupt. 

Load Step Counter 

This is a maintenance instruction in which the content 
of register R4 is gated into the step counter, if the FP1 1 
is in maintenance mode (FMM=1). Whenever the step 
counter is loaded by an LDSC, normal loading via the 
microprogram is inhibited until the step counter is 
incremented to zero. This allows partial quotients and 
products to be formed for diagnostic purposes. If 
FMM=0, the LDSC acts as a NOP. 

Store AR in ACO 

AC0<54:32>«-AR <57:35> if FD = 
ACO <54:0)^-AR (57: 3> if FD = 1 

Maintenance Right Shift 
AR <- AR/2; QR <- QR/2 

Store QR in ACO 

BR <- QR; AC <54:32> <- BR <57:35> if FD = 
ACO <54:0> *- BR <57: 3> if FD = 1 

Set Floating Double Mode 
FD«-1 

Set Long Integer Mode 
FL <- 1 



170000 



170001 



170002 



170003 



170004 



170005 



170006 



170007 



170011 



170012 



36 



SINGLE OPERAND INSTRUCTIONS: OPR SRC 

OPR DST 



15 



12 11 



6 5 



Format F4 



OC = 17 



FOC 



SRC/DST 



Mnemonic 



Instruction/Operation 



OP Code 



LDFPS SRC 



STFPS DST 



STST DST 



Load FPU's Program Status Word 
FPS^-(SRC) 

Store FPU's Program Status Word 
DST «- (FPS) 

Store FPU's Status 
DST <- (FEC) 

DST + 2 +- (FEA) if not mode or not immediate mode 



170100+ SRC 



170200 + DST 



170300 + DST 



37 



111 Op Code 


No Mem Class 


Load Class 


Store Class 


Convert Special* 


ROM 214 


ROM 234 


ROM 254 


ROM 274 


ROM 270 


1 . All illegal FP instruction 


LJJUD MU 


AL/JJr MU 


tLKr MU 


CTCVP 




JLJJr MU 


ci Tor? ^ x^n 
oUrSr MU 


Mr MU 


olLrl 




OTI7 Aid 

blr MU 


lUMrr ~ MU 


MCrD ~MU 


SICrD 


2. If address mode in format Fl 


/^t t> r? 1VIA 

CLRr MU 


MULr ~ MO 


STFPS ~ MO ~ MO 




or r 2 and AC/ 6 or 7 selected 


LDSC MO 


MODr ~ MO 


OTCT" ^ , A>fA l*A 

STST ~ MO MO 


*Do conversion then use store Fl 




Neg F MO 


T\T\ 7 TV * /"V 

DIV ~ MO 


STCFD ~ MO 






i nor _ \ a f\ 

ABSF ~ MO 


LDCDF ~ MO 








TSTr MO 


LDF ~ MO 








LDFDS MO 


LDCFD ~ MO 








LDClr MO 


LDCIF ~ MO 








bb 1 r MU 


T nt?DC ~ , TV /f A 

LDrrb ~ MO 








bblD MU 


pr?pn *A/fn ^ Tk/fn 
CrCC iMU ~ MO 








Mill MU 


JNbLrr ~ MU 








CETT A/ICS 

OJblL MU 


A T5CT7 A/f A 

ArSor ~ MU 








MKo MU 


loir ~ MU 








JlyU MU 


L-UllAr ~ MU 








LDEXP MO 










ADDF MO 










SUBF MO 










COMP MO 










MULF MO 










DIVF MO 










LDCDF MO 










LDCFD MO 









•00(0) 




QRJ(DBL) 


0R2 (D8L) 


STRG1 


FUNCTION 


QR35(SNG) 


QR34(SNG) 











RIGHT SHIFT OR , AR , INCREMENT SC*" 





1 





AR*— BR+AR, RIGHT SHIFT OR, AR, INCREMENT SC 


1 








RIGHT SHIFT QR, AR, INCREMENT SC 


1 







AR-—AR-BR, RIGHT SHIFT QR , AR, SET STRG 1 , 1 N C R EM ENT SC 










AR*— AR+BR, RIGHT SHIFT QR.AR, RESET STRG 1 , INCREMENT SC 







1 


RIGHT SHIFT OR, AR, INCREMENT SC 


1 





t 


AR*— AR-BR, RIGHT SHIFT OR , AR , 1 NCRE ME NT SC 


1 


1 




RIGHT SHIFT OR, AR INCREMENT SC 



"For double precision format 00 (0) ■ QR3 , QR2 , ( STNG I ) 
For tingle precision format 00 (0)> QR35,QR34,( STNG 1 ) 

**The step counter it tet to the two's complement of the number of bits in the multiplier and is checked 
for zero after each incrementation . 

11-0437 



Multiply State Diagram 




BD<15:0> 

LDBD 



BA<15:0> 



ttt: 



T4 



LDBA 



<50ns> 

_n_ 



<25ns> 



o 



CLOCK 




FXPF- 




16 BIT 
DATA PATH 



BB1Z = 1 


UPPER BYTE <15:8> IS 




A ZERO 


BB1Z= 


UPPER BYTE <15:8> 




TO * ZERO 


BN = 1 


[BIT 15 ON l] 


BZ = 1 


BITS<15:0> ZERO 


BZ = 


BITS<15:0> * ZERO 



B-CONDITION CODE LOGIC 



T4 



I I CLOCKED ON 

TRAILING EDGE 
OF T4 



1 1-1490 



32 BIT 
AC 



64 BIT 
AC 



ACCUMULATORS < 



ACO [3] 


ACO [2] 


ACO [ 1 ] 


ACO [0] 


AC1 [3] 


AC1 [2] 


AC1 [ 1 ] 


AC1 [0] 


AC 2 [3] 


AC 2 [2] 


AC2 [ 1 ] 


AC2 [0] 


AC3 [3] 


AC3 [2] 


AC3 [ 1 ] 


AC3 [0] 


AC4 [3] 


AC4 [2] 


AC4 [ 1 ] 


AC4 [0] 


AC5 [3] 


AC5 [2] 


AC5 [ 1 ] 


AC5 [0] 


AC6 [3] 


AC6 [2] 


AC6 [ 1 ] 


AC6 [0] 


AC7 [3] 


AC7 [2] 


AC7 [ 1 ] 


AC7 [0] 



[3] 
16 BITS 



[2] 
16 BITS 



[1] 
16 BITS 



[0] 
16 BITS 



32 BIT 

" word" 



63 48 


47 32 


3 


2 


31 16 


15 


1 





31 28 


27 24 


23 20 19 16 


15 12 


11 8 


7 4 


3 



8 "4-BIT WORDS" « 
32 BIT WORD 



ALU 
Control 

Field 
(ALUC3- 
ALUCO) 


Function 


ALU Select Lines 


Mode 
ALUM 


Carry 
in 

ALUC1 




ALUS3 


ALUS2 


ALUS1 


ALUSO 





~ A 














1 


X 




1 


~ (A V B) 













1 


X 




2 


A minus B 





1 


1 










Drive ALUS2 low 


3 











1 




1 


X 




4 


~ (A AB) 





1 







1 


X 




5 


~B 





1 







1 


X 




6 


A minus B minus 1 





1 


1 







1 




7 


A A~B 





1 


1 




1 


X 




10 


A plus B plus 1 


















Drive ALUSO low 


11 


A plus B 















1 




12 


B 







1 




1 


X 




13 


A A B 







1 




1 


X 




14 


1 




1 







1 


X 




15 


A minus 1 




1 


1 







1 


Drive ALUS1 low 


16 


A V B 




1 


1 




1 


X 




17 


A 




1 


1 




1 


X 





X = don't care 

= low 

1 = high 



41 



to 




T4| 



(aiJP) 
UAF 



8:1 
MXR 

FRMA 



VAAAAAAAAA/AAA/AAZ 



63 14 13 12 



C ROM BUFFER 
FRME 

FRMF 



T2; 



'63 r _ RnM 8 X 7 

FRMC C R0M FRMB 



7 C-ROM ADDRESS 
7 FRMA FRMB 



7~l 



4 



8:1 
MXR 



FRMA 



VAA/AAAAA 



-+ 3 



FRMB 



I 



VAAAMAAA 



VAAAVAAA 



FRMB 



VAAAAAAAAA 



FRMB 



VAAAAAAAA 



VAAAA/AAA 



-» o 



FRMB 



VAAAAAAAAA, 



CP cp cp V CP V 







^AAAAAAAAAAAA/AA/AAAAAAAAAAAAAAAAAA/AAAAAAAAAAA/AAAA^ 




11-1491 



6-Bit Branch Bits 





UAF 


UAF 


UBR 


UBR 


UBR 


ujp ! 


1 





2 


1 






If branch condition true, 

Trap to Ready CROM 



Selects multiplexers 



<13>_f 
CR0M<12 :11> - 



Selects inputs to multiplexers CROM (10:08) 



The three UBR bits are applied to each of the six multiplexers and uniquely specify one of the inputs to the 
multiplexer. If UBR bits 2, 1, and are all Is, the multiplexer output goes to 0, which indicates no 
modification takes place. For all other combinations, the multiplexer output goes to a 1 if the selected 
branch condition is true. The UAF bits specify the multiplexer(s) as follows: 



UAF1 


UAFO 


Multiplexers Selected 








through 5 if UBR is even (UBRO on a 0) 






2 through 5 if UBR is odd (UBRO on a 1) 





1 


Multiplexer selected 


1 





1 Multiplexer selected 


1 


1 


Both and 1 Multiplexers selected 



Multiplexer Branching Conditions 



Multiplexed 
Inputs 





5 


4 


3 


2 


1 





A 


SUB FRAC 


FIRD4 


FIRD3 


FIRD2 


FIRD1 


FIRD0 


B 


FIR07(1) 


FIR06(1) 


FIR11 (1) 


FIRlO(l) 


AR50 (0) 


SD(1) 


C 


RNG2 


RNG1 


RNGO 





BB1Z(1) 


BN (0) 


D 











FIU(l) 


IL (0), 


Immediate « 


E 











FT(1) 


-(FCAFIC) 


FD (0) 


F 


FIRD6 


FIRD5 





~ CONV SP 


~ (FVA FIV) 


M0 


* G 








FIR08 (0) 


AR58 (0) 


AR59 (0) 


BZ(1) 


H 





















I 

A 
3 

1 



Symbolic name for 
this particular state 



SCF.60 
4 



(165) Current ROM Address 



STR Rounded Result 



ALUS*— A 
ACMX «- FALUH 
ACS [3:2] «- ACMX 
SET FCC(l) 



-(164) 6F2 



ROM Next Address - 



The branching conditions are designated as follows: 



represents the octal decode of the 
microbranch bits (bits 10 through 
8 of control ROM) 



6F2 

L 



Branching conditions (certain 
blocks will have no branch con- 
ditions) 



decode of microaddress field (bits 
""and 1 1 of control ROM) 



43 



FRL 
FRH 
FRM 
FXP 



Fraction Data Path Low Order 
Fraction Data Path High Order 
FP ROM and ROM Control 
Floating-Point Exponent Data Path 



M8 115-0-01 
M8 114-0-01 
M81 12-0-01 
M8 113-0-01 



The FRL group of prints contains the following logic: 

1. lower half of FALU 

2. lower half of AR 

3. lower half of BR 

4. lower half of QR 

5 . floating-point status 

6. ACMX 

7. scratch pad (AC7-0) 

8. BMX 

The FRH group of prints contains the following logic: 

1 . upper half of FALU 

2. upper half of AR 

3. upper half of BR 

4. upper half of QR 

5. clock logic, times states, time pulses 

6. sign of source (SS) and sign of destination (SD) logic 

7. fractional control logic 

The FRM group of prints contains the following logic: 

1. control ROM 

2. control ROM address register 

3. Scratch pad addressing logic 

4. ROM multiplexers 

5. ROM data buffer 

6. interfactdogic 

The FXP group of prints contains the following logic: 



1. 


EALU 


2. 


EMX 


3. 


Step counter 


4. 


FIR 


5. 


BA register 


6. 


BD register 


7. 


U break register 


8. 


DIMX 


9. 


BRanching Logic 


10. 


Range ROM 


11. 


FRHE 


1. 


MRJ and MRO register 


2. 


MUL ARITH flip-flop 


3. 


Pause logic 


4. 


STRG I flip-flop 


5. 


AR control 


6. 


QR control 


7. 


MUL SUB flip-flop 


8. 


AR clock logic 


9. 


QR clock logic 


10. 


Sign bit 



44 



SCRATCHPAD! ; FRACTION CALCULATION LOGIC 
ACCUMULATORS ' 



1 



EXPONENT CALCULATION LOGIC 

C UB<7:Q>^) 

U FXPJ 



C FPS<15:Q> J 





EALU<15:0> 


U) 


(B) 



FALUL | 




FALU<59:0> 
(A) (B) 



DATA PATH DEFINITION 

ACMXO <31> +- ~BN; ACMXO <30> <- BZ; ACMXO <29: 16) <- 37777; ACMXO (15:0) FPS 
ACMX1 <31:16>^EALU(15:00>;ACMX1 <15:00> «-EALU (15:00) 
ACMX2 <31> < — SD; ACMX2 (30:23) <- EALU <07:00); ACMX2 <22:00) <- FALU <57:35) 
ACMX3 <31 :00> <- FALU (34:03) 

BMXO (15:00) <- EALU (15:00) 

BMX1 (15:00) <- AC f [3] (15:00) or AC,- [1] (15:00) 

BMX2 (15:00) «-AC z - [2] (15:00) or AC; [0] (15:00) 

BMX3 (15:08) <- 0; BMX3 (07:00) <- AC^ [3:2] (30:23) orAC,- [01:0] (30:23) 

EMXO (15:00) +-BA (15:00) 

EMX1 (15:00) +-DIMX (15:00) 

EMX2 (15:00) <- CNST (15:00) 

EMX3 (15:06) <- 0; EMX3 (05:00) <- SC (05:00) 

FMXO (02) <- BR (35); FMXO (01) «- BR (1 9); FMXO (00) <- BR (3) 
FMX1 (02) <- AR (34); FMX1 (01) <- 1; FMXO (00) <- AR (02) 



LDQ1 = QR (59) <- 0; QR (58) <- 1 if AC f [3:2] (30:24) ^ else QR (58) <- 

QR (57:35)^ AC- [3:2] (22:0) 
LDQ0 = QR(34:3)^AC Z . [1:0] (31:0); QR (2:0) <- 



45 



r 



BACKUP PC; ENA. FP ATTN 

t, <BA*-PCB> 

t 2 SHFR<-PCB-2 

t 3 BEND 

tg PCA+-PCB - 2 

tg FP ATTN 

PCB*-PCA; SR+-SHFR 



ENTER HERE 
AFTER EXECUTION OF 
■ FETOO 
FET 10 
IRD00 



) 



LOOK FOR 
QUESTS SE 
CODE TO FP 
ATTN 


3REAK RE- 
ND PC & OP 
11 WITH FP 


f^^-PCB 

t 2 <SHFR<-BR> 


>- 

FOP 20 1 


r (174) 



CLK. BREAK. 
OP CODE TO 
LOOK FOR F 


5; SEND PC & 
FP11 AND 
P READY 


t, BA<- 
t 2 <SHF 
t 3 BRQ 


PCB 

R<-BR> 

STROBE 



i 



FP ATTN ALLOWS TIMING 
TO ADVANCE TO T# 



-j » — ^— ». ALU'S- 

(# ' / ^ t 3 FIR- 

m. ^* + CCj-t 



AT T2 OF NEXT ROM STATE 
FROM FP SYNC 
50 ns 

_n_ 



STEP PC AND GET FP11 
STATUS 



t t (BA*-FP EALU); READ FP 
t 2 SHFR+-PCB+2 
t 5 PCA^PCB+2 
tg BR«-BUS 
PCB<-PCA 



LOAD CCS IF TO LP TO; 
FP STATUS IN BR ' 



t, <BA<-EALU> 

t 2 (SHFR^DR) 

t 3 BEND 

t 6 CC<-BR(FPCC) 

IF ENABLED BY FP11 



FROM DECODE OF FIR 
WITH FCLD EN ONLY 
ON [CFCC,STCFI,STEXP] 



PUT DEST F 
ENABLE FP 


EG IN BR & 
ATTN 


t t <BA+-EALU> 
t 2 SHFR^-DR 
tg FP ATTN 
BR+-SHFR '* 


FOP 70 


f (316) 



SEND FP AT 
FOR FP11 


rN & WAIT 


FP ATTN 


t, <BA«- 
t 2 SHFR 


EALU> 
•HBR 





-FP REG WRITE 




FP REG WRITE 



(NEVER TRUE FOR 
THIS INSTRUCTION) 



(376) 



GET FP DATA 



t, <BA<-EALU> 

FP READ 
^ <SHFR<H3R> 
t 6 BRH3US 



MODIFY DEST REG & 
ENABLE FP ATTN 



t, <BA-*-EALU> 
t 2 SHFRf-BR 
t 5 GR[DF]<-SHFR 
t 6 FP ATTN 



WAIT FOR NEXT FP INSTR 
LD FIR & INSTR ADDRESS 



DIMX+-DATA ADDRESS 
EMX+-DIMX 
ALU'S*-B 

<-EALU 
r FOR FP ATTN 
+-DATA IN 
t 3 SS+SD-H) 
REQ<-1 



LD INS. ADDRESS 



DIMX-H3ATA ADDRESS 

EMXH3IMX 

ALU'S«-B 

ACMX+-EALU 

S 4 AC7[1]«-ACMX 

S 3 ENABLE FP SYNC 

IF MIONV SP 



NO MEM CLASS LD 
CONTENTS OF GENERAL 
REG. 



EMX-HDATA IN 

ALU'S<-B 

BMX+-EALU 

WAIT FOR FP ATTN 

t 4 BDH3MX 

S 3 ENABLE FP SYNC 



LD DATA 


INTO FPS 


S1 REQ*-0 

EALIH-A — " — 
t 4 FPS+-EALU 


RDY 00 i 


r (3) 


WRITE FPS IN SCRATCH 


S1 REQ<- 
ACMX 
S4 AC7[0 




f-vFPS 
]*-ACMX 



LD FPS 


IN BD 


SCR OU 
BMX<-A 
t 4 BD-f-B 


r<-AC7[0] 

:l 

MX 



WAIT FOR NEXT FP INSTR 
LD FIR & INSTR ADDRESS 



DIMX-H3ATA ADDRESS 

EMXHDIMX 

ALU'Sf-B 

ACMX«-EALU 

WAIT FOR FP ATTN 

t 3 FIR«-DATA IN 

t 3 SS+SD<-0 

REQ*-1 



CP/FPP Interflow Mode 

46 



11-1443 



FET 00 



(217) 



RDY20 



(72) 



START FETCH NEXT 
INSTR 

CLEAR INSTR REG 

t, BA*-PCB;BC*-DATI 
t 2 SHFR<-SR-SR 
t 3 BUST; CLEAR FLAGS 
tg IR<-SHFR 



FET 10 , 


(260) 


GET INSTR 


& STEP PC 


t, BA<-PCB;BC<-DATI 


t 2 <SHFR<- 


PCB+2> 


t 3 PRQ STROBE 


t 5 BUS LONG PAUSE 


PCA«-PCB+2 


te IR*-BUS;BR*-BUS 


PCB 


*-PCA 



DECODE THIS INSTR & 
STEP PCA BEYOND & 
READ SRC &DST FIELD 
GEN REGS 



t, BA«-PCB;BC+-DATI 

t 2 SHFRf-PCB 

t 3 CONDITIONAL BUST 

tg PCA+-PCB+2 

t 6 -SF7:SR«-GS[SF] 

SF7:SR<-SHFR 
-DF7:DR-K3D[DF] 

DF7:DR«-SHFR 



BACKUP PC TO POINT AT 
INSTR;ENABLE FP ATTN 



t, <BA<-PCB> 

t 2 SHFR<-PCB-2 

t 3 BEND 

t 5 PCA<-PCB-2 

t 6 FP ATTN 
PCB+-PCA 
SR<-SHFR 




LOOK FOR 
QUESTS SEr 
CODE TO FP 
ATTN 


3REAK RE- 
JD PC & OP 
U WITH FP 


t, BA*-P 
t 2 <SHFF 


CB 

*<-BR> 



CLK BREAKS. 
CODE TO FPU 
FP READY 


SEND PC & OP 
& LOOK FOR 


t, BA^ 
t 2 <SHF 
t 3 BRQ 


PCB 

R+-BR> 

STROBE 



STEP PC & GET FPU 
STATUS 



t, <BA<-FP EALU) 

READ FP 
t 2 SHFR<-PCB+2 
tg PCA-f-PCB+2 
te BR<-BUS 

PCB-f-PCA 



5 



WAIT FOR NEXT FP INS. 
LD FIR AND INS. ADRS 

DIMXHDATA ADDRESS 

EMXHDIMX 

ALU'S<-B 

ACMX-EALU 

WAIT FOR FP ATTN 
t 3 FIRf-DATA IN 
t 3 SS+SD<-0 
RECh-1 



LD INS ADRS 



DIMX+-DATA ADDRESS 

EMXHDIMX 

ALU'S*-B 

ACMX+-EALU 
S 4 AC7[1]<-ACMX 
S 3 ENABLE FP SYNC 

IFM30NV SP 



LOAD CLASS INS 



EMXHDATA IN 
ALU'S*-B 
BMX<-EALU 
WAIT FOR FP ATTN 
S 3 ENABLE FP SYNC 



LD 1ST WORD OF SRC 
IN AC6 



INC ADDRESS 

FPC1*-DATI 

EMXHDATA IN 

ALU'S^B 

ACMX^EALU 

WAIT FOR FP ATTN 
S 4 AC6[3]«-ACMX 
t 4 SET FCC'S 

ENBL -0 INTERRUPT 
S 3 ENABLE FP SYNC 



LD 2ND WORD OF SRC 
IN AC6 



INC ADDRESS 

FPC1HDATI 

EMX+-DATA IN 

ALU'S^B 

ACMX+-EALU 

WAIT FOR FP ATTN 
S 4 AC6[2]+-ACMX 
S 3 ENABLE FP SYNC 



READ MOST SIGN. 
HALF OF ACS (AC6) AND 
GOTOLDF MO 



S, REQ+-0 

SCR OUT«-ACS[3:2] 

BMX<-EXP 
t 4 BA*-BMX 
t 3 QR«-LDQ1 
t 4 SS+-SCR OUT<31> 
t 4 BR«-QR 



CP/FPP Interflow Mode 2 (sheet 1 of 2) 



47 



y 

D12.80 | (111) 




DST ADRS INDR;SRC 




OPERAND IN BR & SR 




CHECK STACK LIMIT 




t! BA+-DR;BC*-BSOP1 


FCLD EN , 


t 2 SHFRH3R 
t 3 BUST;GR[DF] 
tg SR*-SHFR 
CC<-BR (FPCC) 


CFCC, 
STCFI. 
STEXP 


IF ENABLE BY FPU 




D12.70 \ (135) 




STEP DST FIELD 




REGISTER 




t, <BA<-DR> 




t 2 SHFR<-DR+DSTCON 


^ AD2.AD1 , 


t 3 BEND 

BRQ STROBE 


1 


tg PCAHDR+DSTCON 




GR[DF)-«-SHFR 




tg DF7:PCB*-PCA 





DST ADRS TO BR 
ENABLE FP ATTN 



t, <BA«-EALU> 
t 2 SHFR+-DR 
t 3 BEND 
tg BR^-SHFR 
FP ATTN 



SEND FP AT 
UNTIL FPU 


TN & WAIT 
READY 


t, <BA<-E 
t 2 <SHFR 
t 3 BRQ S 


ALU) 
*-PCB> 
TROBE 



[F1] TO 
ROM 265 



FP SYNC 
FPREQ 



DO BUS OP FOR FPU; 
FOR DATO BR GETS GOOD 
DATA FROM FPU TO 
OUTPUT 



t, BA*-DR;BC<-FC 

FP READ 

<SHF^-PCB> 
ta BUST;GD[0] 
t 6 BR«-BUS 



FINISH BUS OP & STEP 
DR;FOR DATI BR GETS 
DST OPERAND FOR FPU; 
ENABLE FP ATTN 



t, BA«-DR;BC*-FC 
^ SHFR+-DR+2 
tg BUS LONG PAUSE 
tg FP ATTN 

DR<-SHFR 

BR+-BUS 



FPC1 FOR DATI 



/1 04 I 



READ LEAST SIGN. HALF 
OF SOURCE AC+MOVE SS 
TOSD 

SCR OUT*-ACS[1:0] 
t 4 QR*-LDQ0 
t 4 BR*-QR 
t 4 SD+ S3 



WRITE INTO MOST SIGN. 
HALF OF DEST. AC 



ALU'S<-\,B 

FMX-H3R 

ACMX«-FALUH 

EMXH3A 
S 4 ACD[3:2]*-SCR IN 
t 4 SET FCC (0) 



RDYOO y 


r (3) 


WRITE FPS IN SCRATCH 


S, REQ<-0 

ACMX*-^FPS 
S 4 AC7[0J*-ACMX 


RDY 10 i 


' (6) 


LOAD FPS IN BD 


SCROU 
BMX+-A 
t 4 BD+-BM 


T<-AC7[0] 
CL 

X 



CP/FPP Interflow Mode 2 (sheet 2 of 2) 



48 



IR IR 
15 14-12 



IR 
11-09 



IR 
08 



IR 
07-06 



IR 
05-03 



IR 

02-00 



DOUBLE OPERAND 1 
(1 OF 2) 



1 


MOV 


SRC, DST , 


2 


CMP 


SRC, DST 


3 


BIT 


SRC, DST ' 


4 


BIC 


SRC, DST • 


5 


BIS 


SRC, DST 1 


6 


ADD 


SRC, DST J 



4 JSR REG, DST 



L. 

| SINGLE OPERAND (1 OF 2)' 



I 7 RESERVED 

Pr egTsTefTan d"o per and" 



DOUBLE OPERAND 
(2 OF 2) 

1 MOVB SRC, DST 

2 CMPB SRC, DST 

3 BITB SRC, DST 



4 BICB SRC, DST 



BISB SRC, DST 



SRC, DST 



PC AND PS CHANGE (1 OF 2) 
0- 



1 1 
n o 



BR OFFSET 
BNE OFFSET 
1 BEQ OFFSET 

BGE OFFSET 

1 BLT OFFSET 

BGT OFFSET 

1 BLE OFFSET 





SWAB DST 
CLR DST 



COM 
INC 
DEC 
NEG 
ADC 
SBC 
TST 
ROR 
ROL 
ASR 
ASL 



DST 
DST 
DST 
DST 
DST 
DST 
DST 
DST 
DST 
DST 
DST 
MARK OFFSET 
MFPI SRC 
MTPI DST 
SXT DST 



MUL REG, SRC 
DIV REG, SRC 
ASH REG, SRC 
ASHC REG, SRC 
XOR REG, SRC 
RESERVED 
RESERVED 

SOB REG, OFFSET 



fPC AND PS CHANGE (2 OF 2 




_J 

"~1 






BPL 


OFFSET 




1 


BMI 


OFFSET 







BHI 


OFFSET 




1 


BLOS 


OFFSET 







BVC 


OFFSET 




1 


BVS 


OFFSET 







BHIS 


OFFSET 


(BCC) 


1 


BLO 


OFFSET 


(BCS) 





EMT 


CODE 




1 


TRAP 


CODE 





SINGLE OPERAND ( 2 OF 2) 

5 1 0- 




^ o 


CLRB 


DST 


1 


COMB 


DST 


2 


INCB 


DST 


3 


DECB 


DST 


1 o 


NEGB 


DST 


1 


ADCB 


DST 


2 


SBCB 


DST 


3 


TSTB 


DST 


1 


RORB 


DST 


1 


ROLB 


DST 


2 


ASRB 


DST 


3 


ASLB 


DST 


1 


RESERVED 


1 


MFPD 


SRC 


2 


MTPD 


DST 


3 


RESERVED 



}■ RESERVED 



*TS REG 
RESERVED 
RESERVED 
SPL PRIORITY 



HALT 

1 WAIT 

2 RTI 

3 BPT 

4 IOT 

5 RESET 

6 RTT 

7 RESERVED 



CCOP MICROINSTRUCTION 



J 



J 



| FLOATING POINT AC AND OPERANDI I 




[""floating POINT "1 (""FLOATING POINT OPERATE*" 
1 SINGLE OPERAND r 1 



1 



LDFPS 
STFPS 
STST 
CLR (F/D) 
TST (F/D) 



SRC 

DST 

DST 

FDST 

FDST 



MUL (F/D) AC, FSRC 
MOD (F/D) AC, FSRC I 
ADD (F/D) AC, FSRC 1 
LD (F/D) AC, FSRC I 
SUB (F/D) AC, FSRC I 
CMP(F/D) AC, FSRC i 
ST (F/D) AC, FDST 
DIV(F/D) AC, FSRC 1 

STEXP AC, DST 1 1 

STC(F/D)(I/L) AC, DST 1 
STC(F/D)(D/F) AC, FDST I 
LDEXP AC, SRC | 

LDC(I/L)(F/D) AC, SRC , 
LDC(F/D)(D/F) AC, FSRC 



<L Mob \t/V ) rUb I i 
3 NEG (F/D) FDST | 



L_ 7 . 



1 o 


CFCC 


1 


SETF 


2 


SETI 


3 


LDUB 


4 


LDSC 


5 


STAO 


6 


MRS 


7 


STQO 


1 




1 


SETD 


2 


SETL 


3 




4 




5 




6 




7 





J 



Determination of an Instruction from the Binary Code 



49 



15 



000000 
000002 



000400 
000402 



NOTE 1 



\ 



** 7474 
*«7476 
**7500 



**7744 



**7776 



760000 
760002 



777776 



INTERRUPT 8 
TRAP VECTORS 



USER 8 SYSTEM 
PROGRAM STORAGE 



LOADER STACK 



ABSOLUTE LOADER 
u PROGRAM STORAGE 



BOOTSTRAP 
LOADER 

L. 

I/O DEVICE WORD 



CORE MEMORY 
EXPANSION 



I/O DEVICES AND 
PROCESSOR'S 
INTERNAL 
REGISTERS 



NOTE 1 

* * 

01 
03 
05 
07 

11 

13 

15 



MEM SIZE 

4K 

8K 

12K 

16K 
20K 
24K 
28K 



PDP-1 1 Typical Core Memory Storage Map 



50 



( START ) 



LOAD R1 WITH 
THE ADDRESS 
OF THE INPUT 
DEVICE'S 
CONTROL 
REGISTER 



LOAD R2 WITH 
CONTENTS OF 
LOCATION *752 



ENABLE 


INPUT 


DEVICE 


TO 


READ A FRAME 


(BYTE) 






MOVE FRAME 
READ INTO 
LOCATION 
[R2] + » 400 



INCREMENT 
COMENTS OF 
LOCATION *752 




BRANCH TO 
LOCATION *724 
OF MAINTE- 
NANCE LOADER 



Bootstrap Loader, Flow Chart 



Bootstrap Loader Coding 



Location 



Octal 



Symbolic 



*744 


016701 


746 


26 


750 


012702 


752 


352 


754 


005211 


756 


105711 


760 


100376 


762 


116162 


764 


2 


766 


*400 


770 


005267 


772 


177756 


774 


000765 


*776 


177560 




or, 177550 



MOV *776, %1 

MOV #352, %2 

INC(l) 

TSTB(l) 

BPL.-2 

MOVB 2(1), *400 (2) 

INC *752 
BR. -24 



(TK) 

(PR) 



* = 17 for 4K 

37 8K 

57 12K 

77 16K 

117 20K 

137 24K 

157 for 28K 



51 



17476 




000000 


* 17500 




012706 
17470 








17724 




^ — ^ 

012767 


726 




352 


730 




20 


732 




012767 


734 




765 


736 




34 


740 




000167 


74? 




1 / / JJZi 


* 17744 


016701 


016701 




26 


26 




012702 


012702 




352 


373 




005211 


353 




105711 






100376 






116162 






2 






***400 






005267 






177756 






000765 




17776 


(TK) or (PR) 





MAINTENANCE 
LOADER 



OVERLAY 



BOOTSTRAP 
LOADER 



TK = 1 77560 Low-Speed Reader 
PR = 177550 High-Speed Reader 



*Starting address of the Bootstrap Loader 
*Starting address of the Maintenance Loader 



52 



N-2 



N-1 



LAST DATA BYTE 
IN BLOCK N-2 " 

CKSUM BYTE 
FOR BLOCK N-2" 



LEADER 




• 


/ 


777y 

m 


9 


1 


TRAILER 


, V 


) 

#000000 


3 O/O 

V 




00 

0000000 






Y ( 

ooooooooooooooooooooooooooooof 

1 . ) 



START OF BLOCK N 

CKSUM BYTE FOR BLOCK N-1 

LAST DATA BYTE 
IN BLOCK N-1 

FIRST DATA BYTE 

HI ORDER BYTE 1 L0 AD 

LO ORDER BYTE J ADDRESS 

HI ORDER BYTE "1 BYTE COUNT 
LO ORDER BYTE [FOR BLOCK N-1 



START OF BLOCK N-1 



Absolute Loader Tape Format 



53 



ADDRESSING MODES 



MODE 



OPR %R 



NOTES 



INSTRUCTION 








GPR 




OPERAND 



MODE 1 OPR (R) 



INSTRUCTION 



GPR 

ADDRESS 



OPERAND 



MODE 2 OPR(R) + 



INSTRUCTION 








GPR 1 




ADDRESS 



I 











OPERAND 







WORD BYTE 



MODE 3 OPR ©(R)H 



INSTRUCTION 








GPR j 




ADDRESS 



I 



ADDRESS 

ZD 



OPERAND 



R equals a number between Oand 7. 



Addressing Modes (sheet 1 of 3) 



54 



MODE 4 



OPR-(R) 



INSTRUCTION 








GPR 1 


ADDRESS 



WORD 



BYTE 



OPERAND 



NOTES 



MODE 5 



OPR cD-(R) 



INSTRUCTION 








GPR j 




ADDRESS 



ADDRESS 







OPERAND 





MODE 6 



PC 



INSTRUCTION 



PC 
+ 2 



INDEX:±X 



OPR + X(R) 



GPR 



ADDRESS 







OPERAND 





MODE 7 



PC 



INSTRUCTION 





PC 
+ 2 



INDEX:±X 



OPR o)±X (R) 



GPR 



ADDRESS 







ADDRESS 




1 






OPERAND 





Addressing Modes (sheet 2 of 3) 



55 



MODE 2 



PC REGISTER ADDRESSING 
OPR # n 



PC 



PC 
+2 



INSTRUCTION 



OPERANDS 



NOTES 



OPR #n = OPR (7) + 



MODE 3 



OPR d)#A 



PC 



PC 
+ 2 



INSTRUCTION 



OPR d)#-A = OPR <0(7) + 



ADDRESS: A 














OPERAND 







MODE 6 



OPR A 



PC INSTRUCTION 



OPR A = 0PR±X(7) 



PC 
+ 2 

PC 
+ 4 
L_ 



INDEX 



A minus updated PC = INDEX 



NEXT INSTRUCTION 



OPERAND 



MODE 7 



OPR <D A 



PC INSTRUCTION 



OPR a)A=OPR <0 +X (7) 



PC 
+ 2 

PC 
+ 4 
l_ 



A minus updated PC= INDEX 



NEXT INSTRUCTION 



NOTE: 





ADDRESS 




1 






OPERAND 





The mode specified overrides the fact that the register is the PC (register 7). EXAMPLE: 500/CLR-{7) 

502/777 I Program causes halt at address 500 whose 
504/400 ( content has been offered to = Os 
506/HALT 



Addressing Modes (sheet 3 of 3) 



56 




PDP-1 1/45 Operator's Console 



1 START VECTOR 

1 2 TRAP VECTOR 

2 SOURCE CONST. SOB a MARK OFFSET 

3 BEST. CONST.- BXX OFFSET 




TO/FROM UNIBUS 



TO CONSOLE DATA LIGHTS 



DATA 

TO SEMI-COND 
MEMORY 



DATA TO KT11-C X 
REGISTERS AND DATA FROM KT11-C REGISTERS 

FPP DATA 



KB1 1-A Central Processor Data Paths, Block Diagram 



CCL (T2) [54-52] c 

NO CHANGE 

1 INSTRUCTION DEPENDENT 

2 SET/CUR FROM IR (CCOP) 

3 LOAD FROM FPP IF ENABLED 

4 CCLD4 Z&N ACC SHFRj C B V— 

5 CCL05 Z ft N ACC SHFR;C — AMX15 

v *~ v old + SHFR15VAMX15 

6 CCL06 N,C. 8 V UNAFFECTED; Z— Z* SHFR«0 

7 CCLDT Z.N.a V UNAFFECTED; C— ALU CARRY 



ir decode 
(ircb.c.o: 



AFIR DECODE 
(RACE, F.H) 




CONDIT40N 
COOE 

SUBSIDIARY 
ROM 
(IRCH) 



FEN 14 ENABLE FORK C 
FEN 13 ENABLE FORK 8 
FEN 12 ENABLE FORK A 



ADR [07-00] 
TO ADDRESS GATING 



MSC (T1) {29-271 

NO AFFECT 

1 ENA FP ATTN 

2 NOT USED 

3 SET CONF IF KERNEL MODE 

4 SPL (SET PRIORITY LEVEL) 

5 CONDITIONAL BUST 

6 BRQ STROBE 

7 BUST (BUS START) 



BSD (TO [40-39] 

NO PAUSE 

1 INTR PAUSE 
" BUS PAUSE 

BUS LONG PAUSE 



BEF [11-8] 


UADR5 [+40] 


UADR4 [+20] 



1 


DESTINATION MODE 3.5,7 


SR* 1 


2 


CONDITION CODE Z 


-(PWRF+ INTR) 


3 


SC •> 


SC<0 


4 


-DIV SUB 


CONDITION CODE N 


5 


-OBD (000 BYTE DESTINATIONS 


-DIV OUIT 


6 


BR14(0) 


PS RESTORE 


7 




~[BRQ»-(T + CONF)] 


vo 


RIP+FP SYNC 


— (FP REO * FP SYNC) 




SC#0 


DROd) 


12 


CONF (CONSOLE FLAG) 


- BRQ 


13 


PF(0)»(SF+TF) 


PF(0)»(SF+ -TF) 


14 


T 




15 


- FJ/CLASS t 


-O/CLASS t 


16 


DROd) 


SR15I1) 


17 


RIP + FP SYNC 


FP SYNC«FP REG WR 



( BEF » 5 )* CONDITIONAL FORK B 
( BEF « 14) 'CONSOLE BRANCHES 
(BEF«14)»C0NDITI0NAL FORK C 
( BEF » 15)* FJ/CLASS* CONDITIONAL FORK B) 



FROM CONSOLE^ 



BSC (T1) [26-24] 

DATI 

1 SRC1 OATI 

2 KERNEL OATI 

3 SRC2 DATI 

4 FC (CONTROLLED BY FPP) 

5 DATO 

6 BS0P1 

7 BS0P2 



BCT (T1) [32-30] 

NO AFFECT 

1 RE AO FPP DATA 

2 CONSOLE ACKNOWLEDGE 

3 CLEAR FLAGS 
INIT IF KERNEL MODE 
STACK REFERENCE 
ACKNOWLEDGE 
BEND (BUS END) 



CONTROL 
(UBC) 



FORK A 
(RACE.F.H) 



BRANCH 
(RACK) 




TRAPS AND 
MISCELLANEOUS 
CONTROL 
(PRIORITY ARBITRATOR) 
(TMC) 



TO/ FROM 
UNIBUS 
CONTROL 
SIGNALS 



IF 

ROM 



RAR 
(RACO) 



r* R0M<63:60> (RACA) = 



> ROM <59 56> (RACA) = 
-• ROM <55 52> (RACA) E 



» R0M<31:48> (RACA) : 



• R0M<47:44> (RACB) : 
ROM <43:40> (RACB) : 



-• ROM <39 36> (RACB) 
R0M<35 32> (RACB) 



r-m ROM<3128> (RACC) = 



• ROM <27 24> (RACC) = 



ROM <23-20> (RACC) ; 
-* R0M<1916> (RACC) I 



(RACA. 
RACB, 
RACC) 



= pwe ! 
EpadJ 
Ibsd} 



°h 



GENERAL 
REGISTER 
* CONTROL - 



IBCT 
= MSC - 



• ROM<15:12> (RACO) 



M<11:06> (RACO) 



-* R0M<07.04> (RACO) = 
-• R0M<03 00> (RACO) : 



D 



- TO ALL MODULES 



TO/FROM 
FPP. KT11-C 
FASTBUS 
B UNIBUS (BR. BG) 



FROM 
KT11-C FASTBUS 
a UNIBUS 



KB1 1-A Central Processor Control Section, Block Diagram 



o 
3 



3 



O 



o 

3 



CPU 
MAINT 



FPP 
MAINT 



KW1 1 LINE 
CLOCK 



UNIBUS A 



TERM 



FRH(M8114) 



FRL (M8115) 



FRM(M8112) 



FLOATING POINT 



FXP (M8113) 



DAP (M8100) 



GRA (M8101) 



IRC (M8102) 



RAC (M8103) 



PDR (M8104) 



TMC (M8105) 



CENTRAL 
"PROCESSOR" 



UBC (M8106) 



SSR (M8108) or SJB (M8117) 



SAP (M8107) 



TIG (M8109) 



PHK ( 



MEM CTRL (M8110) 



MTRX (Bipolar =M81 1 1 & MOS=G401) 



MTRX (Bipolar =M81 1 1 & MOS=G401) 



MTRX (Bipolar=M81 1 1 & MOS=G401) 



MTRX (Bipolar=M81 1 1 & MOS=G401) 



MEM CTRL (M8110) 



-SEMICONDUCTOR - 
MEMORY 



MTRX (Bipolar =M81 11 &MOS=G401) 



MTRX (Bipolar=M8111 &MOS=G401) 



MTRX (Bipolar =M81 1 1 & MOS=G401) 



MTRX(Bipolar=M8111 &MOS=G401) 



DEVICE 1 



UNI A CABLE 



DEVICE 2 



UNI B CABLE 



DEVICE 3 



UNIBUS B TERM 



Module Layout 



60 



DEVICE REGISTER ADDRESSES 



Device 


CSR 


DBR 


Vector 


Teletype Keyboard 


777560 


777562 


60 BR4 


Teletype Printer 


777564 


777566 


64 BR4 


Reader (PC11) 


777550 


777552 


70 BR4 


run Cxi yrVsi 1 ) 


1 1 1 jj4 


/ / / jjO 


1 A DD /I 

/4 oK4 


Line Clock (KW1 1-L) 


777546 




100 BR6 


Line Printer fLPl H 

XWJ.J. JL V X iUlkVX 1 jL«/X XXI 


777514 


777516 


200 BR4 


DECtape (TCI 1/TU56) 


777340 


777350 


214 BR5 


Control 


777342 






Word Count 


777344 






Current Address 


777346 






DECdisk (RC11/RS64) 


777444 


777456 


210 BR5 




777446 






Look Ahead 


777440 






Disk Address 


777442 






Word Count 


777450 






Current Address 


777452 






Maintenance 


777454 






DECdisk (RF11/RS 11) 


777460 


777472 


204 BR5 


Word Count 


777462 






Current Address 


777464 






Disk Address 


777466 






Disk Address Extended 


777470 






Maintenance 


777476 






DEC Disk Pack (RP1 1/RS03) 


776714 


- 


254 BR5 


Word Count 


776716 






Current Address 


776720 






Disk Cylinder Address 


776722 






Disk Address 


116124 






Device Status 


Hifil i n 

/ /O/ 1U 






Error Register 


776712 






Maintenance Registers 


776726 








776730 








776732 






Card Reader (CR1 1/CM1 U 


777160 


777162 








777164 




Magnetic Tape (TM1 1/TU10) 


772522 


772530 




Byte Count 


772524 






Current Address 


772526 






Status 


772520 






Device Interface (DR1 1) 


772414 


772416 




Word Count 


772410 






Current Address 


772412 







61 



ASCII 




ASCII 




ASCII 




ASCII 




7-Bit 




7-Bit 




7-Bit 




7-Bit 




Octal 




Octal 




Octal 




Octal 




Code 


Char 


Code 


Char. 


Code 


Char. 


Code 


Char. 


000 


NUL 


040 


SP 


100 


@ 


140 


i 


001 


SOH 


041 


j 


101 


A 


141 


a 


002 


STX 


042 


- 


102 


B 


142 


b 


003 


ETX 


043 


# 


103 


C 


143 


c 


004 


EOT 


044 


$ 


104 


D 


144 


d 


005 


ENQ 


045 


% 


105 


E 


145 


e 


006 


ACK 


046 


& 


106 


F 


146 


f 


007 


BEL 


047 


' 


107 


G 


147 


g 


010 


BS 


050 


( 


110 


H 


150 


h 


Oil 


HT 


051 


) 


111 


I 


151 


i 


012 


LF 


052 


• 


112 


J 


152 


j 


013 


VT 


053 


+ 


113 


K 


153 


k 


014 


FF 


054 




114 


L 


154 


1 


015 


CR 


055 


- 


115 


M 


155 


m 


016 


SO 


056 




116 


N 


156 


n 


017 


SI 


057 


J 


117 


O 


157 





020 


DLE 


060 





120 


P 


160 


P 


021 


DC1 


061 


1 


121 


Q 


161 


q 


022 


DC 2 


062 


2 


122 


R 


162 


r 


023 


DC 3 


063 


3 


123 


S 


163 


s 


024 


DC4 


064 


4 


124 


T 


164 


t 


025 


NAK 


065 


5 


125 


U 


165 


u 


026 


SYN 


066 


6 


126 


V 


166 


V 


027 


ETB 


067 


7 


127 


w 


167 


w 


030 


CAN 


070 


8 


130 


X 


170 


X 


031 


EM 


071 


9 


131 


Y 


171 


y 


032 


SUB 


072 




132 


Z 


172 


z 


033 


ESC 


073 


> 


133 


[ 


173 


( 


034 


FS 


074 


< 


134 


\ 


174 


1 


035 


GS 


075 




135 


] 


175 


) 


036 


RS 


076 


> 


136 


t 


176 




037 


US 


077 




137 


<- 


177 


DEL 



62 



SDIDDSD 



DIGITAL EQUIPMENT CORPORATION 
MAYNARD, MASSACHUSETTS 01754