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303A-002 PIT ADAPTER 



715-0037-002 



SEPT 83 REV B 10-715-0037 

(303A-002) 

Copyright © Data I/O Corporation, 1983. All rights reserved. 



Data I/O has made every attempt to ensure that the information in this document is accurate and complete. However, Data I/O 
assumes no liability for errors, or for any damages that result from use of this document or the equipment that it accompanies. 
Data I/O reserves the right to make changes to this document without notice at any time. 

NOTE 

Before using this adapter, read the LogicPak™ manual. 



I 

1O-71W)037 !303A-00e) 



TABLE OF CONTENTS 

SECTION 1. INTRODUCTION 

1.1 OVERVIEW ^^ 

1.2 APPLICATIONS ^2 

1 .3 DEVICE-SPECIFIC INFORMATION (Logic FingerprintTM Test Umrtations) 1-2 

1.4 SPECIFICATIONS 

1-4 

1.5 FIELD APPLICATIONS SUPPORT ,.5 

1.6 WARRANTY 

1-0 

1.7 SERVICE 

1-5 

1.8 ORDERING 

1-b 

SECTION 2. INSTALLATION 

2.1 INSPECTION 2-1 

2.2 ADAPTER INSTALLATION 2-1 

2.3 ADAPTER REMOVAL 2-1 

2.4 REPACKING FOR SHIPMENT 2-2 

SECTION 3. OPERATION 

3.1 OVERVIEW 3^^ 

3.2 POWER UP 3^3 

3.3 POWER DOWN 3^g 

3.4 BASIC DATA TRANSFER OPERATIONS 3.5 

3.4.1 Family Code and Pinout Code Selection 3.5 

3.4.2 Device Insertion , c 

3.4.3 Device Removal - - 

3.4.4 Load RAM With Master Device Data 3^ 

3.4.5 Program Device With RAM Data 3.7 

3.4.6 Verify and Functionally Test Device 3^ . 

3.5 SYSTEM COMMANDS 3.g 

3.5.1 Enable Terminal Mode "3..I , 

3.5.2 Display Command Menu 3.^1 

3.5.3 Family Code arKl Pinout Code 3.^.1 

3.5.4 Set Reject Count Option 3..|2 

3.5.5 Select Verify Option 3.^2 

3.5.6 Select Security Fuse Option 3.13 

3.5.7 Set Number of Logic Rngerprint™ Test Cycles 3.I4 

3.5.8 Enter Logic Rngerprint™ Test Starting Vector 3-14 

3.5.9 Enter Structured Test Vectors 3.1g 

3.5.10 Display Fuse Pattern ........,..'.......... 3.I6 

3.5.11 Receive Fuse Data 3.« 

3.5.12 Transmit Fuse Data ^-^ 



10-7150037 (303AO0B) 



3.5.13 Display Sum-Check of Fuse Data 3-17 

3.5.14 Enter Fuse Number and State 3-18 

3.5.15 Display Configuration Number 3-21 

3.5.16 Exit Command 3-21 

3.6 MMI REGISTERED PAL® PRESET INFORMATION 3-21 

SECTION 4. CAUBRATiON AND TROUBLESHOOTING 

4.1 OVERVIEW 4-1 

4.2 CALIBRATION 4-1 

4.2.1 DC Calibration (Steps 1-10 and 12) 4-2 

4.2.2 Waveform Observation (Steps 11, 13-17) 4-5 

4.2.3 Explanation of Timing Diagrams 4-5 

SECTION 5. CIRCUIT DESCRIPTION 

5.1 INTRODUCTION 5-1 

5.2 GENERAL ARCHITECTURE 5-1 

5.3 COMPONENT LAYOUT 5-1 

APPENDIX A. FUNCTIONAL DIAGRAMS, FAMILY AND PINOUT CODES A-1 



LIST OF FIGURES 



1-1 303A-002 MMI/National Programming /Testirtg Adapter 1-1 

1-2 Example of Limitation 1 1-2 

1-3 Example of Limitation 2 With Truth Table and Boolean Equations 1-3 

1-4 Example of Limitation 2 1-4 

2-1 Adapter Installation 2-1 

3-1 Function Menu 3-1 

3-2 Automatic Programmir>g Sequence Flowchart 3-2 

3-3 Programmer Power Switch Location 3-4 

3-4 Device Installation 3-6 

3-5 Operational Overview Flowchart ,,,,,.., 3-10 

3-6 Fuse Pattern 3-16 

3-7 Logic Diagram 3-17 

3-8 Sam'^ls Printout of JEDEC Format o_iq 

3-9 Complete Logic Diagram 3-19 

4-1 LogicPak™ Cover Removal 4-1 

4-2 Calibration Equipment Setup 4-1 

4-3 LogicPak™ Test and Adjustment Locations 4-5 

4-4 Sample Timing Diagram 4^ 

5-1 Typical Programming /Testing Adapter Block Diagram 5-2 

A-1 Logic Diagram PAL10H8 A-1 

A-2 Logic Diagram PAL12H6 A-2 

A-3 Logic Diagram PAL14H4 A-3 

A-4 Logic Diagram PAL16H2 A-4 

A-5 Logic Diagram PAL16C1 A-5 

A-6 Logic Diagram PAL20C1 A-6 

A-7 Logic Diagram PAL10L8 A-7 

A-8 Logic Diagram PAL12L6 A-8 

A-9 Logic Diagram PAL14L4 A-9 

A-10 Logic Diagram PAL16L2 A-10 

A-11 Logic Diagram PAL12L10 A-11 

A-12 Logic Diagram PAL14L8 A-12 



n 
10-71&«J37 (308A-OO2J 



A-13 Logic Diagram PAL16L6 A-13 

A-14 Logic Diagram PAL18L4 A-14 

A-15 Logic Diagram PAL20L2 A-15 

A-16 Logic Diagram PAL16L8and PAL16L8/A/-2/4 A-16 

A-17 Logic Diagram PAL20L10 A-17 

A-18 Logic Diagram PAL16R8and PAL16R8/A/-2/-4 A-18 

A-19 Logic Diagram PAL16R6and PAL16R6/A/-2/-4 A-19 

A-20 Logic Diagram PAL16R4and PAL16R4/A/-2/-4 A-20 

A-21 Logic Diagram PAL 20x10 A-21 

A-22 Logic Diagram PAL 20x8 A-22 

A-23 Logic Diagram PAL 20x4 A-23 

A-24 Logic Diagram PAL 16x4 A-24 

A-25 Logic Diagram PAL16A4 A-25 

A-26 Logic Diagram PAL20L8 A-26 

A-27 Logic Diagram PAL20R8 A-27 

A-28 Logic Diagram PAL20R6 A-^ 

A-29 Logic Diagram PAL20R4 A-29 



LIST OF TABLES 



1-1 Using the MMI/National Programming /Testing Adapter IVIanuai 1-1 

1-2 Logic FingerprintTM Test Limitations for MMI/National Programmable Logic Devices 1-2 

3-1 PLDS System Command Summary 3-3 

4-1 Key Sequence to Access the Caiibrstlcn Mods 4-2 

4-2 LogicPak™ Error Codes 4-3 

4-3 Measurement Chart 4-8 

4-4 Error Codes for Calibration 4-37 

A-1 LogicPal<™ Family and Pinout Codes A- 30 



IV 

10-71&aa7 OtBA-OOZ) 



SECTION 1 



INTRODUCTION 



1.1 OVERVIEW 

The 303A-0Q2 Monolithic Memories, Inc. 
(MMD/National programming/testing (P/T) adapter consists 
of two zero-insertion force sockets with interface circuitry 
and EPROM (erasable, programmable read-only memory) 
mounted in a metal frame; see figure 1-1. The P/T adapter 
is used with the Data I/O 303A LogicPak™ to match 
programming electronics to the specific device family you 
are using. Any firmware unique to the MMI/National 
programmable logic devices is resident in the EPROM on 
the P/T adapter; all other necessary firmware is in the 
LogicPak™ or the programmer. 



Table 1-1. Using the MMI/National Programming/ 
Testing Adapter Manual 




Rgure 1-1. 303A-002 MMI/National Programming/ 
Testing Adapter 

This manual describes how to use the MMI/National 
adapter. Subjects addressed in this manual and their 
con-esponding sections are listed in table 1-1. Use this table 
as a quick reference point for the major sections. 

In this manual, we will refer to the operational 
procedures for the 29A Universal Programmer; refer to your 
programmer manual for System 19 and 100A key 
sequences. 

The entries that you are to make from either the 
programmer or terminal are indicated by the entry enclosed 
in a key symbol. For example. 



SUBJECT 


SECTION 


Applications 


1.2 


Installatkin procedures for P/T adapter 


2.2 


Basic operation instructions 


3.0 


System commands 


3.5 


Calibration 


4.2 


Measurement chart for DC calibration 




tests 


4.2 


Error codes 


4.2 


Timing diagrams 


4.2 


Circuit description 


5.0 


Family and pinout codes 


Appendix A 


Functional diagrams 


Appendix A 


Data I/O Service Centers 


Back of 




manual 


Warranty Information 


Back of 




manual 




B 



indicates that the ESCAPE key on the terminal keyboard 
should be pressed. 

1.2 APPLICATIONS 

Software tables resktent within the P/T adapter store 
values for programming variables, including pinouts, voltage 
levds, and timing. When you choose the family and pinout 
codes for a particular device, the programmer uses 
informatbn in these tables to assemble a specialized 
programming routine in scratch RAM (random-access 
memory). This alk>ws high-speed operatk>n with minimum 
firmware. Families with more than one pin numt>er series 
(e.g., PAL* 20 and PAL* 24) have sockets to 
accommodate each pin count. 

The family code and pinout code table (tat)le A-1, 
appendix A) lists all the devices that can be programmed 
and/or tested with this P/T adapter. Table A-1 also lists the 
development aids as wdl as the family code and pin code 
corresponding to each device. Thte table will be updated as 
new devices are added. As Data I/O increases the 
capabilities of the LogfcPak™ to program new device, 
firmware and/or hardware updates will be available for 
existing adapters to add new devices to existing device 
families. New adapters wW also be added to accommodate 
new device families. Contact Data I/O for the latest revision 
and any required firmware updates. 

If a fuse pattem is generated on a host system, it must 
use fuse numbers specified aox>rding to the togic diagrams 
in this manual and tran»nitted to the programmer in the 
JEDEC (Joint Bectron Device Engineering Council) format 
(see appendix A of the LogicPak'rM manual). Data I/O uses 



* r^4. it s nQjMtnd tradsmcrti of Monolithic MamoiitB, Inc. 



1-1 

10-71&aX37 0CQA4XB) 



the JEDEC Logic Device Translation Fonnat (number JC-42, 
1-81-62) for serial data input and output with the 
LogicPal<™. The only exception to this is w^en you are 
using a Signetics H&L design adapter, in which case data 
transfer can also occur in the Signetics H&L logic fomiat. 

NOTE 
Before operating, see the JEDEC format 
specificatiorts limitations in the 
LogicPak™ manual, appendix A, 
section 3.0. 



1.3 DEVICE-SPECIFIC INFORMATION 
(Logic FingerprintTM Test Limitations) 

The pseudorandom nature of the input vectors 
generated during the Logic Fingerprint™ test can cause 
some dewces In some programming circumstances to fail by 
giving nonrepetitive results. THIS DOES NOT 
NECESSARILY INDICATE A FAULTY DEVICE, but may be 
an indication that the device is subject to Logic 
Fingerprint™ test limitations. The device may still function 
in the system for which it was designed. The error flag 
indicating the Logic Fingerprint™ test failed is alerting you 
that this programnrwd pattern may not function for all 
possible input states. 

Table 1-2 lists the devices and their Logic Fingerprint™ 
test limitations. Limitation 1 occurs when devices are 
programmed so that nonregistered outputs are fed back to 
product inputs, wrtiich results in an oscillation. This 
condition is shown in the simplified example in figure 1-2. 
The two nonregistered product outputs (pins 19 and 18) in 
figure 1-2 feed back to the other product's input. If input 
pins 2 and 3 are both true (i.e., TTL "1"), the PAL will 



Table 1-2. Logic Fingerprint™ Test Limitations for 
MMI/National Programmable Logic Devices 



Part Numbers 



PAL-12H6" 

PAL-12H4<' 

PAL-16H2» 

PAL-16C1" 

PAL-20C1'' 

PAL-10L8» 

PAL-12L6« 

PAL-14L4« 

PAL-16L2' 

PAL-12L10' 

PAL-14L8" 

PAL-IBLS' 

PAL-18L4a 

PAL-20L2» 

PAL-20L10' 

PAL-16L8» 

PAL-16R8» 

PAL-16R6» 

PAL-16R4^ 

PAL-20X10» 

PAL-20X8" 

PAL-20X4= 

PAL-16X4 

PAL-16A4 

PAL-20L8 

PAL-20R8 

PAL-20R6 

PAL-20R4 

PAL-16R4/A/-2/-4 

PAL-16R6/A/-2/-4 

PAL-16R8/A/-2/-4 

PAL-16L8/A/-2/-4 



Logic FingerprintTM 
Test Limitations 



[ 'Supported by National 



l,i5 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2 ' 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2,3 

1,2 



X = FUSE INTACT »- = ALL FUSES INTACT FOR TERM + = FUSE BLOWN 

INPUTS (0-31) 



Logic Diagram PAL16R4 



112 1 < » ( I 



■"->=:;-; 



-t^ 



n 



11011 1I13H1S lilMIII I0I1I223 lt2ia}7 J121MJ1 




Figure 1-2. Example of Limitation 1 



1-/ 
10-71&O037 i30aA-002) 



oscillate. This condition could exist for one product output 
feeding back to its own input or numerous outputs feeding 
baclc. 

Limitation 2 occurs when a race condition is 
programmed into the device. Because the inputs are 
controlled, it is possible that the race condition will not be 
critical in the circuit for which the device was designed. Due 
to the random nature of the inputs during the Logic 
Fingerprint™ test, the race condition could appear and 
cause unstable results. An RS latch is an example of this. 
Rgures 1-3 and 1-4 show the schematic, truth table. 
Boolean equations, and fuse map. Suppose that A, B, and 
C are at logic lows, 01 is at a logic high, and 02 is at a logic 
low. Let B and C go to a logic high simultaneously. The 
state of D will depend on how fast B and C can propagate 
through the logic gates. The effect of B will arrive at D first, 
forcing it low. At a time equal to the propagation delay of 
the gates later, the effect of C will be seen at D, forcing it 
back to a logic high. When D was at a logic low, the RS 
latch changes state and is unaffected when D comes back 
high. This causes the Logic FingerprintTw test to read the 
wrong values on the outputs, which in turn causes an 
unstable result. 

If the default starting vector of results in a test-sum 
of FFFF FFFF, select a starting vector other than 0. 

Limitation 3 occurs in registered parts only. When using 
the Logic Fingerprint'''^ test, you must start from the same 
state every time the test is performed. These registered 
PALs, however, will not power up into the same state every 
time the test Is performed. If the Logic Fingerprint'''''' test 
starts at a different point, it will produce unstable results. 



To overcome this limitation, the registered outputs must be 
put into a known state before executing the Logic 
Fingerprint^M test. Two methods of doing this are: 

1 . Dedicate one input line as a preset or reset line for all 
registered output. A starting vector can then be written 
to set or dear all registered outputs. 

2. If no extra inputs are available to dedicate to a 
preset/reset line or a known state of other than all ones 
or all zeros is required, the setup must consist of one or 
more vectors to force the outputs into the desired state. 
If more than one is needed, the structured test must be 
used to input the vectors rather than the starting seed 
for the Logic Fingerprinf^w test. (See LogicPakT"^ 
manual, section 1.4.3 and this manual, sections 3.5.7 and 
3.5.8). 

The V03 version of the 303A-002 P/T adapter added a 
feature which greatly improves Logic Fingerprinf^w 
testing of MMI registered PAL®s. It contains a routine 

whirh Ai itnmaticallv nrocAte the rAnietore in tha PAI nrinr *n 

the Logic Fingerprint''''^ test. (See section 3.6 for more 
information.) 

NOTE 

It is important that you recognize when 
devices are programmed with these 
limitations and realize that the Logic 
Fingerprint^'^ test will r^ect them. These 
devices can still be tested by using 
structured test vectors. 



ch:>-d> 



ch:>-\> 



CM>-^ 



RS TRUTH TABLE 



R 


s 


01 


02 








1 


1 





1 


1 





1 








1 


1 


1 


a 


a 



3 Remains unchanged 




01 



02 



BOOLEAN EQUATIONS 



01 = 02*R 

02 = ors 



R = A_ 
S = B*C 



01 = 02*A 



C5 = 01'IB'Cl 
= 01*IB-hC] 



B = (01*61-1^(01*0 



Rgur0 1-3. Example of Limitation 2 With Trutti Table and Boolean Equations 



1-3 
10-71»n37 Oa3A-002) 



X = FUSE INTACT «-= ALL FUSES INTACT FOR TERM + = FUSE BLOWN 



-t>- 



INPUTS (0-31) 



Logic Diagram PAL 16R4-2 



1 ' ' ] • S ( 1 t 11011 1!13H1S 1(11111! 202U233 !«!S»!1 2I29M31 



--l::^=i.^^ 



^'-^ 



11— (- 



cH>: 



P3 



(0 

S 
til 



;: H:^ 



u 

D 
Q 
O 

oc 
& 



^-tS: 



^*= 



-I- 



^-C5C 



M- 
17. 
H- 
H- 
M- 
i1 - 
«- 
II- 



H:^ 



4—4- 





>- 




t-> 0—1 





01 



.ll 02 



D Q 



I£><^ 



D 



'^> 0—1 



D Q 
> O 



■=^ 



*-> 



h 




>- 




t>o^ 



■^^^ 



• 1!J "517 I lint Hums II111III 2IJ1I22J M2S2I27 2I2IM31 



^ 



Figure 1-4. Exampis of Limitation 2 



1-4 
10-71&ai37 (303A-C02) 



1.4 SPECIFICATIONS 

The P/T adapter receives its power from the 
LogicPak™ and the programmer power supplies. 
Programming waveforms are generated from programmer 
supplies using the digital-to-analog converters (DAC) 
controlled by the programmer's microprocessor. The 
controlling firmware is located both on a circuit board in the 
LogicPak™ and in the P/T adapters. The physical and 
environmental specifications of the P/T adapter are: 

• altitude (operating): sea level to 3 km (10,000 ft) 

• humidity (operating): 90% maximum (noncondensing) 

• humidity (storage): 95% maximum (noncondensing) 

• temperature (operating): -5 to 45°C (41 to 113°F) 

• temperature (storage): -40 to 70°C { --TO to 158°F) 

• weight: .255 kg (9 oz) 

• dimensions: 16.6 x 12.3 x 2.1 cm (6.54 x 4.84 x .81 in.) 

1.5 FIELD APPLICATIONS SUPPORT 

Data I/O has field applications engineers throughout 
the world. They can provide additional information about 
interfacing Data I/O products with other systems and 
answer questions about your equipment. 

These engineers are located within the United States at 
the addresses listed in the back of this manual. For 
international applications support, contact your nearest 
Data I/O representative. 



1.6 WARRANTY 

The 303A-0Q2 P/T adapter is warranted against defects 
in materials and workmanship. The warranty period of 90 
days begins when you receive the equipment; the warranty 
card inside the back cover of this manual explains the length 
and conditions of the warranty. For warranty service, 
contact your nearest Data I/O Service Center. 

1.7 SERVICE 

Data I/O maintains service centers throughout the 
worid, each staffed with factory-trained technicians to 
provide prompt, quality service. A list of all service centers 
is located in the back of this manual. 

1.8 ORDERING 

To place an order for equipment, contact your Data I/O 
sales representative. Orders for shipntent must include: 

• a description of the equipment (see the latest Data I/O 
price list or contact your sales representative for 
equipment and part numbers) 

• purchase order number 

• desired method of shipment 

• quantity of each Item ordered 

• shipping and billing address of the finn, including ZIP 
code 

• name of person ordering the equipment 



1-5 
10-71&O037 O03A-0Q2) 



SECTION 2 



INSTALLATION 



2.1 INSPECTION 

The P/T adapter was thoroughly tested and inspected 
before shipment and was carefully packaged to prevent 
shipping damage. Inspect your adapter to ensure that no 
damage occun-ed during shipment. If you notice any 
damage, file a daim with the earner and notify Data I/O. 

2.2 ADAPTER INSTALLATION 

To insert the P/T adapter into the LogicPakTW; 

1. Check to make sure a device is not in a socket. If a 
device is in a socket, remove it as described in 
section 3.4.3. 

2. Align the guide pins on the underside of the adapter with 
the guide pin holes on the LogicPak™ (see figure 2-1). 

3. Gently set the adapter on the LogicPakTw. 

4. Firmly press down on the front edge of the adapter to 
lock the connector pins into the connector receptacle 
(see figure 2-1). 



2.3 ADAPTER REMOVAL 
CAUTION 
BEFORE REMOVING THE ADAPTER, 
press ESC from the terminal, or, from 
the programmer front panel, press the 
KEYBOARD key (on the System 19) or 
the VERIFY key (on the 100A or 29A). 
Because the processor in the 
programmer executes firmware 
resident in the adapter, these 
precautions must be taken before 
removing the adapter from the 
LogicPak™ to prevent a program 
interrupt or loss of RAM data. 



CONNECTOR 
RECEPTACLE 



LOGICPAKTM 




CONNECTOR 



Figure 2-1. Adapter Installation 



2-1 
10-71WICB7 (3O3A-0Q2) 



To remove the adapter: 

1. Ensure that the programmer has completed the current 
operation. 

2^ Ensure th3t a device is r^t In ** ^^'u^i'^* 

3. While holding down the LogicPak™, grasp the adapter 
handle and gently rerrtove the adapter. 

2.4 REPACKING FOR SHIPMENT 

If the adapter is to be shipped to Data I/O for service 
or repair, attach a tag to it describing the vrork required and 



identifying the owner. In correspondence, identify the unit 
by part number, revision level, and the name of the unit. If 
the original shipping container is to be used, place the 
adapter in the container with the appropriate packing 
materials, and seal the container with strong tape. If 
another container is used, be sure that it is a heavy carton, 
wrapped with heavy paper or plastic; use appropriate 
packing material, and seal well with strong tape. Mark the 
container "DELICATE INSTRUMENT" or "FRAGILE." 



2-2 

10-7150037 i303A-C02) 



SECTION 3 

OPERATION 



3.1 OVERVIEW 

The 303A-OQ2 P/T adapter enables you to program and 
functionally test the devices listed in table A-1 of appendix A. 
These Ic^ic devices are an-ays of gates and flip-flops joined 
by matrices of fusible links. The devices can be programmed 
by blowing selected fuses in the matrices, which leaves the 
remaining intact connections to perform the desired logic 
functions. 

The fuse pattem necessary to program a device should 
have already been developed using a Data I/O LogicPak™ 
and a design adapter or a host computer system; if you 
have not developed your fuse pattern, consult the 
LogicPak™ manual and design adapter manual to develop 
your data before proceeding. However, if you have entered 
your data in Boolean equations or function tables (truth 
tables), they must be translated into a fuse pattern before 
you can begin programming. (Don't turn the power off; if 
you do, you will lose all your data.) If you have not used a 
design adapter, the fuse pattern must be loaded from: 1) a 
master device, 2) the serial port, or 3) manually from a 
programmer or terminal keyboard. 

An alternate method of specifying the fuse pattern is to 
manually enter the fuse number and state for every fuse in 
the device. Each P/T adapter manual contains logic 
diagrams for the devices in its repertoire. These are the 
same as those in the device manufacturers' data books, but 
the fuse numbers have been added. Although tedious, fuse 
numbers and states can be entered manually into the 
programmer's data RAM from the programmer's keyboard 
or from a terminal. This method usually will be used only for 
editing fuse data because it is a long process with room for 
error. 

With a P/T adapter, fuse data can be entered into the 
programmer's RAM by loading from a master device shown 
in figure 3-1. Blank devices can then be programmed using 



the same P/T adapter, or other manufacturers' functionally 
equivalent second-source devices can be programmed by 
installing the appropriate P/T adapter. Remember that a 
device with its security fuse programmed cannot be used as 
a master because its fuses cannot be read. 



BftTfi i^a copPDPBTinn PiPr-ppDGPPnniMp, 


TFJIINC 


ftPSFTFP 





- PlSPbftV flFMH 








1 


- FHTPP FHMiiY PIN cone 


CDPVPIKMT 


198? 


? 


- IDftP BTVIfF 








3 


- VFPIFV PFVICF 








« 


- PPPGPBM PFVICF 








5 


- FHTFP PFJFCT COUNT DPTIPN 








f. 


- FNTFP VFPJFY DPTIPN 








7 


- FHTFP tPST FUJF DPTIDN 








e 


- FNTFP FUNCTIDNflt TFST PRTft 








A 


- BirPtBY FOSF PftTTFPN 








B 


- PFfFIVF FUJF IWTB 








c 


- TPflHSniT FOSF PfiTfi 








r 


- DISPifiV FUJF JynCHFCK 








F 


- FNTFP KFCINBt FUJF BftTB 








^eS-O - PfFBPF PFBOVING ftPSPTFP 








FBHHaNB > 









Figure 3-1. Function Menu 

Programming is controlled either from the programmer 
keyboard or from a terminal. Firmware in the P/T adapter 
automatically tests the device's position in the socket, 
ensures that the device is blank, and looks for illegal bits; 
figure 3-2 defines the overall fuse programming sequence. 
Programming begins when these automatic checks are 
completed and determined acceptable. 

After the device has been programmed, it is 
automatically verified and tested according to options you 
select. 



3-1 
10-71&0037 (SOSA-aaZ) 



ERROR 
21 



NO 



ADDRESS 
NEXT 
FUSE 



I BEGIN \ 






ILLEGAL 
BIT 
TEST 



APPLY PROGRAM 
PULSE SEQUENCE 



BLANK 
CHECK 



READ FUSE 
STATE IN 
DEVICE 





ERROR 
B 



Rgure 3-2. Automatic Programming Sequence Flowchart 



3-2 

10-715^X137 (303A-OKI 



In addition to enabling you to program and test 
devices, the P/T adapter also enables you to view data, 
change them, and/or enter test parameters. These optional 
steps are listed in Table 3-1. The functions of the P/T 
adapter are described in table 3-1 and section 3-5. Sections 
1 and 3 of the LoglcPak™ manual also describe these 
functions. Logic diagrams with decimal fuse numbers are in 
appendix A. 



3.2 POWER UP 

NOTE 
If the LogicPakTM with adapter is not 
installed in the programmer before power 
is turned on, you will hear a beep until 
the LogicPak™ is installed. 
When power is applied, the programmer 
will perform an automatic self-test 
routine. When the self-test routine is 
complete, the programmer will signal its 
readiness; see your programmer manual. 









Table 3-1. PLDS System Command Summary 






MODULE OR 
ADAPTER 


COMMAND 
TYPE 


FROM 
FRONT 
PANEL 


VIA 
TERMINAL 


COMMAND 
DESCRIPTION 


SEE 
SECTION 




LogicPakTM 




.. 


e 


Display menu 


3.5.2 




(with any 




E1 


- 


Enable terminal mode 


3.5.1 
3.5.3 
3.5.4 




adapter) 




E5 


1 

5» 


Enter family and pinout codes 
Set reject count 








E6 


6 


Select verify option 


3.5.5 








E7 


7 


Select security fuse option 


3.5.6 








E8 


8 


Set number of Logic FingerprintTM test cycles 


3.5.7 








E9 


8 


Enter starting vector and test-sum 


3.5.8 








" 


8 


Enter structured test vectors 


3.5.9 








EA 


A 


Display fuse pattem 


3.5.10 








EB 


B 


Receive fuse data 


3.5,11 






EC 


C 


Transmit fuse data 


3.5.12 






ED 


D 


Display sum-check of fuse data 


3.5.13 








EE 


E 


Enter fuse data by fuse number 


3.5.14 








E F 


- 


Display configuration number 


3.5.15 




•Except with f 


1 

'ALASM adapter. 




ESC 


Before removing adapter 


3.5.16 




PALASM 


Development 


_. 





Display menu 


Rpfpr tn 




Design 




- 


1 


Enter family and pinout codes 


PALASM 




Adapter 




E2 


2 


Receive source equations 


Design 








E3 


3 


Transmit source equations 


Adapter 








E4 


4 


Translate source equations 


Manual 








E0 


5 


Simulate source equatk)ns 










E5 


~ 


Set reject count 








Edit 


~ 


9 


Edit mode (ail commands listed below) 

B Display line 1 

C Replace text 

D Delete text 

E Display to end 

1 Insert/enter text 

K Delete current line 

L Display 24 lines 

M Display commands 

U Display previous line 

(space bar) Move cursor/prompt right 

(RUB/DEL) Move cursor/prompt left and delete during insert 

mode 
CTRL H/ 

(back apace) Move cursor/prompt left 
CTRL M/ 
(carriage return) Display next line 




1 








CTRL P Purge all text 

CTRL Z Exit etHtor/exit "C" or "1" modes of editor 

ESC Before removing adapter 




NOTE: ESC iascapel returns control to 


programmer fi 


rem panel. 

3^ 












10-7 


t&aoa? oosA-oB) 





Table 3-1. (Con't.) 







FROM 










MODULE OR 


COMMAND 


FRONT 


VIA 




COMMAND 


SEE 
















«u«ri cn 


1 Trc 


rMWCL 


ItKIVIIIVAL 




DESCRIPTION 


SECTION 


H&L 


Development 


.. 


e 




Display menu 


Refer to 


Design 




-- 


1 




Enter family and pinout codes 


H&L Design 


Adapter 




E2 


2 




Receive data (IFL format)" 


Adapter 






E3 


3 




Transmit data (IFL format) 


Manual 




Edit 


-- 


4 


G 

P 

T 

V 

V 

F 

R 

N 

1 

D 

C 

X 

E 

101 

(11 

(2) 

(3) 

<4) 

(5) 

(6) 

CTRLZ 

ESC 


Edit mode 

Enter gate number 

Enter product term number 

Enter transition term number 

Move cursor forward 

Move cursor backward 

Display next term 

Display last term 

Enter next field 

Insert term 

Delete term 

Clear term 

Deactivate term 

Display edit sub-menu 

Exit edit mode 

Return to edit mode 

Serial input (receive IFL format)" 

Serial output (transmit IFL format) 

List low-order terms 

List high-order terms 

Compress terms 

Exit edit mode 

Before removing adapter 




"Integrated fuse 


logic, Signetics A 


SCI! 










All P/T 


Device 




1 




Enter family and pinout codes 


3.4.1 


Adapters 




LxMd 


2 




Load fuse data from device to RAM 


3.4.3 






Verify 


3 




Verify fuse data and [>erform functional test 


3.4.5 






Program 


4 




Program device with RAM data 


3.4.4 



NOTE: ESC (escape) returns control to programmer front pane 



To turn the programmer on: 

1. Check to make sure a device is not In a socket. If a 
device is in a socket, lift up the lever (on the upper left 
of the socket; see section 3.4.2), then gently lift the 
device out of the socket. 

2. Plug the AC power cord into the power outlet. 

3. Rip the power switch up to the ON position; see 
figure 3-3. 




POWER CORD ' 
CONNECTOR 



ON 

\i:;^OFF 
POWER 
SWITCH 



Figure 3-3. Programmer Power Switch Location 



3-4 
10-71&0037 OKQA-Oai) 



3.3 POWER DOWN 

CAUTION 
Do not turn the power off while the 
programmer is doing an operation or 
when a device is in a socket; voltage 
transients may damage the device. 

To turn the programmer power off: 

1. Check to make sure the programmer is not in an 
operatk>n process. If it is, wait until the operation is 
complete. 

2. Check to make sure a device is not in a socket. If a 
device is in a socket, rentove it as described in 
sectbn 3.4.3. 

3. Rip the power switch down to the OFF position 
(figure 3-3). 

3.4 BASIC DATA TRANSFER OPERATIONS 

The basic operations that can be accomplished with the 
LogicPakTM and 29A Universal Programmer are: 

• develop data 

• bad RAM with master device data (described in 
section 3.4.4) 

• program a device with RAM data (described in 
sectbn 3.4.5) 

• verify RAM data against the device data (described in 
section 3.4.6) 

• functbnally test device (described in sections 3.5.7 
through 3.5.9) 

The following sectbns describe device-related 
operations with the PLDS using a P/T adapter. Most setup 
procedures specify that you enter the family and pinout 
codes. Data I/O recommends that you develop the habit of 
entering these codes when prompted by the equipment. 
However, if you are using a design adapter, you will be able 
to perform nondevice-related operations without entering 
the family and pinout codes. 

If the programmer has been used to program PROMs, 
or for some other reason contains data in RAM, this couM 
adversely affect the fuse pattern developed for bgic devbes 
or could inadvertently set option parameters. Therefore, 
execute the "clear RAM" select function (see programmer 
nrtanual), or switch off the programmer to clear RAM before 
beginning operatbns with the PLDS. 

All data transfer or verificatbn operatbns occur 
between the programmer's internal RAM and the device or 
between the RAM and serial port in your programmer. 
Because the operation procedure to transfer data via a serial 
port varies among programmers, this manual descrtt)es only 
data transfer using the 29A. For other programmers, refer to 
the specific operation manual. 



NOTE 
An adapter must be installed in the 
LogicPak™ before any of these 
operations can be performed (see 
section 2.21. 

During copy and verify operations, ADDR 
and SIZE appear in the 29A prompts. 
These correspond to starting address and 
block size, respective. These block limits 
must remain in the default state for logic 
device programming. An error code (see 
section 4, table 4-2) will be displayed if 
these limits are altered. For more detail on 
these parameters, see your programmer 
manual. 

3.4.1 FAMILY CODE AND PINOUT CODE SELECTION 

Any device that can be programmed with the 
LogicPak™ js specified by a unique combination of a two- 
digit family code and a two-digit pinout code; these codes 
are provided in each adapter manual. Once the codes are 
entered for a particular device, the LogicPakTw remains set 
up for any operatbn with that device until you enter new 
codes. If invalid family and pinout codes are entered, a beep 
will sound. In remote control operation, 

[PROB PRH ERR 30 ] 

will be displayed, and the operatbn will be stopped when a 
device operation is attempted. 

To select the family and pinout codes: 

1. Locate the manufacturer and part number stamped on 
the device. 

2. Go to the family and pinout code table, table A-1 in 
appendix A, and find the manufacturer's name. 

3. Go to the column entitled "Device Part Number" and 
find the number coresponding to the number on the 
device. 

4. Go to the column labeled "Family Code" and "Pinout 
Code" to find the code numbers corresponding to the 
devbe number for the manufacturer of the device. 

5. Enter the family code and pinout code you selected from 
this table when prompted by the programmer or 
terminal. An LED (light emitting diode) wHI light above 
one of the sockets on the adapter. 

3.4.2 DEVICE INSERTION 

Once you have entered the appropriate family and 
pinout codes, the LogicPak™ is ready to accept a device in 
the socket bebw the lighted LED. 



3-5 
10-71&0037 (303A-002) 



A good electrical connection between the device and 
the socket is essential. To ensure a good connection: 

1. Check to make sure the programmer is not doing an 
operation. If it is, wait until the operation is complete. 

2. Lift the lever on the upper-left side of the socket below 
the lighted LED; see figure 3-4. The lever will stay in the 
upright position. 

3. Gently set the device in the socket below the lighted 
LED. Make sure pin 1 of the device is aligned with pin 1 
of the socket (upper-left corner); see figure 3-4. 

4. Push the lever down to lock the device in the socket. 



UNLOCKED 



PIN1 




PIN1 



LOCKED 



Figure 3-4. Device Installation 



2. 



3. 



^ 




to select the source of the data. 



29A Displays 

f Tjcri/ DTJTjp /r T fr rn 



ADDR/SIZE pertains to block limit parameters. These 
are PROM-related and are not to be used with logic 
devices. Leave defaults in effect. 



^ H 



IV -A 

HAM 



to select the destination for 
the data. 



29A Displays 



[CQ JIE'/'Rf\t1nRJ}J}R ] 



^^ ITHJ 



29A Displays 



3.4.3 DEVICE REMOVAL 

To remove a device: 

1. Check to make sure the programmer is not doing an 
operation. If it is, wait until the operation is complete. 

2. Lift the lever on the left side of the socket: see 
figure 3-4. The lever will remain in the upright position. 

3. Lift the device out of the socket; the LED will remain 
illuminated. 

3.4.4 LOAD RAM WITH MASTER DEVICE DATA 

To load the 29A RAM with data from a master device 
with control from programmer front panel, follow the steps 
given below. 

NOTE 
If options are desired (see section 3.5), 
select options and parameters as needed 
before proceeding. 



1. 





B 


— ^ 





to select the nrode. 



29A Displays 



r nn>/ 
t-ur I 



mTf{ FROtl ] 



crc3»'i rsr^ DTK nni 
r ni I /\uiu r J.IM uu 



5. Enter the family code and pinout code (see 
section 3.4.1). 

filOTe 
The appropriate socket LED wiU light. 

6. Insert the master device into the appropriate P/T adapter 
socket. (See section 3.4.2.) 



^^ r^ 



29A Displays 



Lunjjj.fMa lit* J.t_t u 



I nn-n 11011 ir 



»/ »/ »/ 1/ 

l\ A *\ IS 



NOTE 
XXXX is the sum-check of the device 



3€ 
10-7150037 (303A-OCB1 



8. Remove the master device from the LogicPak™ (see 
section 3.4.3). 

To load the 29A with data from a master device from 
the terminal control mode, follow the steps given below. 

1. Place the system in terminal mode; see section 3.5.1. 

2. Enter the family pinout code, if prompted by the 
terminal. 

NOTE 

If options are desired (see section 3.5), 
select options and parameters as needed 
before proceeding. 



3.4.5 PROGRAM DEVICE WITH RAM DATA 

NOTE 
If options are desired (see section 3.5), 
select options and parameters as needed 
before proceeding. 

When programming a device, the system performs 
illegal bit tests and blank checks at nominal Vcc- 

To program a blank device with the data in the 29A 
RAM with control from the programmer front panel, follow 
the steps given below. 




m 



Terminal Displays 



xxxx 



^ 




29A Displays 



lLu>"'V jJMfR hKuM J 



^ 




29A Displays 



3. 



9R^,.mj\9/SlZE TU] 



^ 




29A Displays 





There will be a short delay whBe the load operation i 
occurring. After the k}ad operation is conr^>lete, the 
terminal will display XXXX. 

NOTE 

XXXX is the sunt-check of the device 
fuses. 



[CO ffRn; DEr^vRJ^ffl 



■^^ KT^ 



29A Displays 






pr* 

r x'N 






3-7 
10-71»naf7 OCQA-0Q2) 



5. Enter the family code and pinout code (see 
section 3.4.1) if necessary. 

6. Insert the blank device into the adapter socket 
(section 3.4.2). 



7. 



^^ m^ 



29A Displays 



fCCIT Tiri/rrr 



m 
u 



[PRGBRRn HEi'ICE Si 



i'/ERIF-Y ^Ei'JCE Si 

[PPG JPrjE SI ;?;?;(;0 
-J L 



sequence numbers 



sum-check 



^Increments by 1 for each device programmed. 

8. Remove the device from the adapter socket (see 
section 3.4.3). 

To program a device with 29A RAM data from the 
terminal control mode: 

1. Place the system in the terminal mode; see section 3.5.1. 

2. Enter the family pinout code, if prompted by the 
terminal. 

NOTE 
If options are desired (see section 3.5), 
select options and parameters as needed 
before proceeding. 




B 



4. 



Terminal Displays 








There will be a short delay after pressing RETURN. 
This is when the programmer is pretesting, 
programming, verifying, and functionally testing the 
device. If no errors occur, the terminal displays XXXX. 

NOTE 

XXXX is the sum-check of the device 
fuses. 

3.4.6 VERIFY AND FUNCTIONALLY TEST DEVICE 

To verify and functionally test a device from 29A front 
(>ane! control follow the steps given below: 

NOTE 

If options are desired (see section 3.5), 
select options and parameters as needed 
before proceeding. 

The verify routine compares the device data to RAM 
data and performs functional testing if this option is 
selected. 



VERIFY 

a 



29A Displays 



i'/ERlfr JIRTR FPOfl] 



3kS 

1&-71&0037 (3(33A-OQ2) 



^ 




29A Displays 



NOTE 
If options are desired (see section 3.5), 
select options and parameters as needed 
before proceeding. 



t. 






^ 




29A Displays 



I'E ^El'iRRtl^^RJjJlR 1 



^ Ik "*" J. 



29A Displays 




^ 




Terminal Displays 



xxxx 



fcrnM mm dtTI mm ^ 
[r-nii/xmLJ r Li^ tju J 



5. Enter the family code and pinout code (see 
section 3.4.1) if necessary. 

6. Insert the device to be verified and/or tested into the 
LogicPak™ (see section 3.4.2). 



^^ ITHJ 



29A Displays 



y/ERIF-v BEl'ICE Q] 



'i'fl Tip 1/ T)n»(C «/ «/»/ vl 



/V07F 
XXXX is the sum-check. 

8. Remove the master device from the adapter socket (see 
section 3.4.3). 

To verify and test a device from terminal control, foltow 
the steps given baknv. 

1. Place the system in the terminal mode; see section 3.5.1. 

2. Enter the family and pinout codes, if prompted by the 
terminal. 



There will be a short delay after pressing 3. This is 
when the programmer is verifying and functional testing the 
device. If no errors occur, the terminal displays XXXX. 

NOTE 

XXXX is the sum-check of the device 
fuses. 



3.5 SYSTEM COMMANDS 

In addition to the copy (load or program), verify, edit, 
and select functions described in the Operation Section of 
your programmer manual, the LogicPak™ offers numerous 
system commands that allow you to manipulate data and 
set parameters. System commands are accessed by entering 
a two-character select code from the programmer front 
panel or a one-character menu code from the terminal. 
Some commands will prompt for a data entry. The 
operatk>nal overview (figure 3-5) will help you develop data 
and program a device using the system commands and 
programmer operations. Table 3-1 lists the select codes for 
Data I/O programmers to enter system commands from the 
programmer front panel or from a terminal in terminal 
mode. 



3-9 

10-71&a)37 Oa3A-0Q2) 






J 



INSTALL LOGICPAK™ 

IN PROGRAMMER 

(SECTION 2.21 




INSTALL 

P/T 

ADAPTER 

(SECTION 2.21 



INTER 

FAMILY 6 

PINOUT CODES 

(SECTION a.BI 



ENTER NUMBER OF 

CYCLES. START 

VECTOR. SIGNATURE* 

(IF USED: SECTION 

35 7 AND 9 S 81 



INSTALL 
DESIGN ADAPTER 



LOAD DATA 

VIA PROGRAMMER 

RS2BP0RT 

ISECnOtt 3.S 111 



ENTER SOURCE 
EQUATIONS 

OR 
HilL TABLES 




MANUALLY 

LOAD DATA 

FROM KEYBOARD 

(SECTION 3.5 HI 



LOAD 

MASTER 

DEVICE 

(SECTION 3.« 



I 



:x 



SELECT 

OPTIONS 

(SECTION 3.5 



PROGRAM 
DEVICE 

(SECTION 3.51 



EVALUATE DEVICE. 

THEN LOAD TO 
UARN TEST-SUM 



VER(FY AND 
TEST DEVICE 
(AUTOMATIC) 




L_ 




TRANSLATE 
SOURCE EQUATIONS 
INTO PROGRAMMING 

DATA 



SilMULATE 

SOURCE 

EQUATIONS 

(IF NECESSARYI 



■^" 



ENTER TESTING 
INFORMATION 
Of OESIREDI 



REPLACE 

DESIGN 

ADAPTER 

WITH P/T ADAPTER 



._! 



(a) Logic Rngerprint™ test signature 
may also be derived from the 
master device. 



Operations possible 
with P/T adapter 
installed 



Figure 3-5. Operational Overview Flowchart 



3-10 

10-71&OQ37 !303A^X2) 



NOTE 

The sequence explanations assume no 
operating errors. If these occur, the 
programmer signals audibly (except in 
remote control) and displays a two-digit 
error code. It also beeps once when an 
incorrect key is pressed. Error codes are 
explained in section 4. 1 (table 4-2) and in 
your programmer manual. Some errors 
will return you to the programmer front 
panel control. 

3.5.1 ENABLE TERMINAL MODE 



3.5.2 DISPLAY COMMAND MENU 



F-^ B1E1EI^3 



Select code El transfers control of the PLDS to the 
terminal. After control is transferred, the 29A will display 

w...y .»v Mwbivii 0riiiL,v lo %«ui I II I loi lu aiiOvvS yuU lO SCceSS 

data development and remote operations resident in the 
design adapters and remote operations using the P/T 
adapters. 

The terminal will prompt you to enter a family pinout 
code unless one has been entered. The tenninal will display: 




H 



This command causes the PLDS to display its 
comrriand menu on the terminal, as shown below: 



l•n^H J 3 ZDt-t-ntftTia'i 






'< - MZ-lh: lEri-.i 

1 - zmzf •:imvc, ti-( -3i,c 

i - LOnri iievi:e 

'i - vEtiFv iiEv'i:e 

4 - PtQSfci., tiEvlCE 

r. - ENTEC CEJECT ;aLi-(T 3=TID'( 

t- - EMT^ft VECIcv D=Tl3^j 

r - E><TEt Lm:t =n;E ■y•ti^3^^ 

i - E'lTEt cyN.;TI3'(AL T£:t IimT^ 

t - DECEIVE =ii:e MTh 
: - TtH'ciiT -u:e imth 
:■ - nr'^LM. t-yrf - i»i;me.-i 

E - E'lTER tCTinfiL =^'j:c ,;,^Th 
EI' - KFOfE 'Ein VIT- ■it''=it7E- 



FRHILY Bin rgtiE (iijuC 



3.5.3 FAMILY CODE AND PINOUT CODE 

From the 29A front panel control, family and pinout 
code entry is part of a device-related operation; see sections 
3.4.1 and 3.4.4. 




□ 



Terminal Displays 



-ftniL.- 'IM :ar€ n 



-fmii., f'ln rariE 



If desired, enter the family and pinout codes; see 
sectton 3.4.1. Once the codes have been entered, the 
tenTH'nal will display the command menu; see section 3.5.2. 
Bypass the entry of these codes by pressing RETURN. 



3-11 
10-71&OOQ7 OOQA-OCC) 



Enter the family and pinout codes. See section 3.4.1 for 
more detail. 

3.5.4 SET REJECT COUNT OPTION 

Tbis Gornrnar>d allows ^ou to select the ""m^'^^'r '^f 
programming pulses applied to the device fuses before the 
programmer rejects the device as unprogrammable. The 
default value of 00 selects the manufacturer's specified 
number of programming pulses. Refer to the timing 
diagrams for specific entries to select optional reject values 
for single-pulse, military, etc., programming specifications. 



^ 



^r^ fr^ fr^ 




29A Displays 






3.5.5 SELECT VERIFY OPTION 

Three options are available for selecting verify and 
functional test routines. These routines are described in 
detail in section 3.4.6. 

Options available are: 



OPTIONS DESCRIPTION 

Default option. Perform fuse verify, followed 
by structured t^t (if test vectors are present 
in RAM), and Logic Rngerprint™ test (tf one 
or more Logic Fingerprint™ test cycles are 
selected), in that order. 



H 



□ 




Perform fuse verify only. 



Perform structured test and Logic 
Rngerprint™ test only, in that order. Does 
not perform fuse verify. 



To change the reject count to an optional value, enter 
the code number (X) specified in the timing diagram. 



^ 



[m] 




I - ] 



29A Displays 






MU 




y — ii 

5 




M 



Option (default) is the option used in normal 
operation. Option 1 checks the programming of the device 
fuses without checking its functionality. Use optbn 2 to 
functionally test devices with the security fuse blown. In 
addition, option 2 can be used to learn the Logic 
RngerprinfTM test-sum of a device wnth the security fuses 
blown. Fuse data in RAM will be cleared during this 
operation. Programming cannot occur with optktn 2 
selected. 

Test options must be entered from the programmer's 
keyboard or a terminal. The option will remain in effect urrti! 
it is changed or until the unit is powered down. To reselect 
the default, key in option 0. 



3HH^3 



Terminal Displays 



29A Displays 



uu 



ZamfilV ' 5 EMTEB- eS.rECT COLiHT 3PTIDM 
ENTE^ "eO'JOftl "EJECT CD'.IMT QFTIDNIti 



For example, to select functional test only: 



^ 



m 




r — -i 



29A Displays 



R-3 
UtZ 



IHM 



o-i^ 

10-715<!(B7 {303A-O02) 




HH 



Terminal Displays 



:3>1>I-^'ir. = i ETHTSS ■.■•ECI'^V 3=-TI0" 
E'lTEt THE /ECIF-, 3=T1D'(:2 



3.5.6 SELECT SECURITY FUSE OPTION 

Some logic devices are equipped with protective fuses 
called security fuses. Once the security fuses are 
programmed, the fuse states in the logic an^y cannot be 
copied. Programming the security fuses makes it very 
difficult to pirate a device design. 

The PLDS security fuse programming feature is a fail- 
safe function. You can either enable programming of the 
security fuse at all times, only allow programming when 
security fuse data are downloaded to the PLDS via the serial 
port, or disable programming completely, whether security 
fuse data are downloaded or not. 

When the security fuse has been blown, a Logic 
RngerprintTM test and structured test can stHI be performed, 
but a fuse verify operation Is not possible. See 
section 3.5.5. When programming the security fuse on MMI 
Registered PAL® s, be aware that the device registers will 
auto-preset to a different state after the security fuse is 
Mown. This will result in a different Logic Rngerprint™ test 
sum than the one "learned" from a master device with the 
security fuse intact. (Refer to section 3.6 for more 
information.) 

To enable programming of security fuses two 
conditions must be met: 1) the security fuse state in the 
programmer RAM must be 1 (or true), and 2) security fuse 
programming must be enabled. Once the security fuse 
option Is selected, it will remain in effect until changed or 
until the programmer is turned off. 

When security fuse data are entered Into RAM 
manually or in the JEDEC ASCII-logic fomiat, data in the G 
field indicate the state of the security fuse. The G field does 
not affect the enable state of the security fuse option; the 



enable state must be entered separately. This can be done 
before or after loading JEDEC ASCII-logic format data. 

Security fuse states cannot be loaded from a master 
device. 

CAUTION 
Once the security fuse is 
programmed, you can no longer verify 
the state of any fuse in the device. 
The process cannot be reversed; 
therafore, be certain that you want to 
program the security fuse before you 
activate this function. 

CAUTION 

Do not attempt to program the device 
after the security fuse has been blown 
or the device will be damaged. 



Security fuse select-code options are: 
OPTION DESCRIPTION 

Default option. Disable programming and set 
the security fuse state in RAM to 0. 







□ 



Disable programming, and set security fuse 
state in RAM to 1 (true). 

Enable programming, and set security fuse 
state in RAM to 0. (Data downloaded in the 
JEDEC format can change the security fuse 
state to 1.) 

Enable programming, and set security fuse 
state in RAM to 1. (Data downloaded in the 
JEDEC format can change the security fuse 
bit back to 0.) 



^^ BIB1H^3 



29A Displays 



mm 
tJtJ 



For exantple, to enable security fuse programming and 
set security fuse state in RAM to 1 (option 3): 



^^ H lTHJ 



29A displays 






I^M 



3-13 
10-715«B7 OOaA-OOZ) 




HE 



Terminal Displays 



Terminal DisF>iays 



;<CLt: -D= ^Iri-^EC-c&lNT: 01 



E'fTE' .^:t =^;j;e 3=ti:3m:; 



3.5.7 SET NUMBER OF LOGIC FINGERPRINT^m 
TEST CYCLES 

This command allows you to select the number of test 
cycles that are performed during the Logic FingerprintTw 
test. See section 1.4.3 of the LogicPak™ manual for a full 
description of this test. The default value is S0, which 
disables the Logic Fingerprint"" test. 



^ HHH^ 



29A Displays 



mm 



For example, to enable one cycle of testing. 



^ HO^ 



29A Displays 



r 



m it 



Yi} 



3.5.8 ENTER LOGIC FINGERPRINT™ JEST 
STARTING VECTOR 

This command enables you to view or enter the starting 
test vector and resulting test-sum for the Logic 
Rngerprint™ test. 

For this example we will use an arbitrary starting vector 
for a 20-pin device of: 



Ground Vqc 

(Pini) (Pin 101 (Pin 20) 

10000000000000001 1 1 1 



NOTE 

A "1" represents a high; a "0" represents 
a low to be applied to a particular device 
pin. 

Values entered for ground and Vcc are included and 
affect the test-sum, but have no effect on the device under 
test. Values entered for dedicated clock and output-enable 
pins on registered parts must be entered as either or 1 . 
However, they have no effect on the device under test. 

Terminal mode allows the starting vector to be entered 
bit-by-Wt after entering the number of cycles for the Logic 
Fingerprint^M test. For programmer front panel operation, 
the vector must be represented by hexadecimal numbers as 
shown on the following page. 




H 



and enter the number of 
cycles desired. 



10-71&^XB7 (303A-aa2) 



Terminal Displays 



29A Displays 



^INSEseujIT rTi^eTI'i-S VECTa=-! ItitiOOdCiOOOddtifiOiJl 1 11 






^ 




29A Displays 



UUUU Bll 



10000000000000001111 

TTTTT 

8 F 
8000F«e0 



Starting vector 
(binary) 

(hexadecimal) 



Starting vector 
(hexadecimal) 



The unused portion of the 32-bit vector is assumed to 
be zeroes and must be included in the hexadecimal vector 
entry. 

For example: 



BHH^n 



29A Displays 



UtUtUMJ 



57 



NOTE 

The eight-character starting vector is 
entered into the programmer in tvm fields. 
B1 identifies the first field. 

To enter tfie first four hexadecimal digits. 



^HHHH 



B2 represents the second field. 

Enter the remaining hexadecimal digit by pressing 



^^aHQQ 



29A Displays 



ruutu nil 



The zeroes are ignored, but are needed to correctly 
position the "F." 

Assume that this vector, when applied to a logic 
device, gives the following test-sum in hexadecimal: 

8F66FDAF 

The El field represents the first four characters of the 
test-sum. These can be viewed or entered at this time. 



^ 




Enter the first four 
characters of the 
test-sum. 



29A Displays 



(BFGG E 1 



To view or enter the next four characters (E2 field) 



^^ Ulrill 



Enter the next four 
characters. 



29A Displays 



[fl^fif E2 



3-15 
10-715<ra7 (303A^Me) 





Terminal Displays 



■:3ii'>iii = s EMTE* niN':Ti3N^L te:t d'iT'^ 
:.:le: =3' fiM'iEC'fsiHT! oi 

^rfSESfflfT :TflETI15 VE:TDS: KiliiiirMiifnifi 
FI15E"fIMT: jFiiCMF 



3.5.9 ENTER STRUCTURED TEST VECTORS 

After the Logic FingerprintTw test parameters are 
entered, the terminal entry of structured test vectors can 
begin. Structured test vectors cannot be entered from the 
programmer front panel. (See section 1.4.3 and appendix A 
for a detailed explanation of structured tests.) 

This example shows entry of the following structured 
test vector from a terminal: 



3.5.10 DISPLAY FUSE PATTERN 

This command outputs the fuse pattern in the 
programmer data RAM to the serial port of the programmer. 
The fuse states are a series of Is and 0s representing 
wfhether a fuse is blown (1) or left intact (0). Each fuse can 
be identified by a decimal number (figure 3-6). The fuse 
states are arranged in a matrix that corresponds to the logic 
diagram of the device. This is useful for transferring a fuse 
pattern to a logic diagram for documenting a device fuse 
pattern. See figures 3-6 and 3-7. 









mCREMENT 

/ 








?-"^«T ^ - M :pl 


H./cM-f Cf.TTfBI« 






nf.- A 


1 T M U ! "n 


!!!!!!) ni 


■iln 






>.>.A ■ 




" ' 






LINt ""^ 
NUMBER 


"1 -.- 


"i»'j n n n 

in 1 '-1 1 ] i] 
in n n i> } 
ininn n 


n 1 1 Ml 1 11 

1 ] 1 1 ] 1 n I ; 
m mini 










1 n nn n 1 
1 n n ] n n 


n 1 1 »n »>i 1 
iiiiiMiini 
ininiiii 
iiinnni 
1 1 n 1 1 1 1 ii' 


111'. 






-pwwft 


Al. S 








Fuw NumbCF 


-"•= 










ruw Si«e 

> • inMCt 
1 = Dfwn 

























Figure 3-6. Fuse Pattern 



^ 



(Pin 1) 



Ground 
(Pin 10) 



VCC 
(Pin 20) 



\ 



/ 



/ 








.:ani.=IMIi = 5 EtHTER -UMirTIDNiiL TEIT BST^i 

CVCLE: fDs- FIM5EPPPINTI ni 

F,^,5Et.(>t■I.,T ITilCTIN? VECT3'>: 1 (.(K.Otnifn.KlOijHiinfil 1 1 1 

:T=y:Tvi=Eri te:t /ErTat fuji.n: 



diOKUoi'ircoHLH;.? :-< 



3.5.11 RECEIVE FUSE DATA 

This command prepares the programmer to receive fuse 
data from a peripheral via the programmer serial port in the 
JEDEC standard ASCII-logic format (LogicPakTw manual, 
appendix A). 



BHE 





H 



3-16 
10-715«J37 {3CSA-0C12) 



if— = JINTACT) 



D } 



is: 



-t=^ 



Lin* Number 

00 
24 
48 
72 



^ 



-= 1 (OPEN) £» = ROW INTACT 
INPUTS (0-31) 



:^ 



10 



Fin* Numbar 9B 

Example: Line Number + Increment Number 
Fuse No. 98 = 96 + 2' 



20 



Increment Number 



^ 




=B=E> 



Figure 3-7. Logic Diagram 



Terminal Displays 



zannfi'n' « i s-eceive ci.i:e tfiTfi 



3.S.12 TRANSMIT FUSE DATA 

This command pr^)ares the programmer to output fuse 
data via the serial port in the JEDEC ASCII-logic format 
(appendix A). See figure 3-8. 



^ HHH 




B 



3.5.13 DISPLAY SUM-CHECK OF FUSE DATA 

This command displays the sum-check of the fuse 
states in the programmer data RAM (the C field in the 
JEDEC format). The sum-check should match one from a 
previously programmed device that is known-good. 



3-17 
10-715007 {303A-002) 






1 11 1 1 1 I Hi n I U 1 3 > I n 

I I 1 I HM>.M>.HnM.<.>»lt»IH»lt. 



...tt.Mj in..i 31] 1 1 n 1 1 J 
] uni 1) n 1 1 1 1 1 1"] 11 
1111111111111111111} 
•I ..,;tM. 

II |H]ti] n n ni ii* 

> 1 I I ] I ] I 1 I 1 1 1 1 ('l ] Mil 

I I I nnin n n 1 1 1 n I' 
••in II ] 1 1 11 1 11 1 ] 1 1 1 1 
1 1 1 1 n 1 1 1 »'] 1 1 1 1 1 1 1 1 1 
1 1 11 II I n II 1 1 ii>>n n 

11 ] 1 1 1 1 1 3 M I n I »i n 1 



TS-W.-ilT Ft.i:F Iw^Ti^ 



=-i=*L [if:i'?iN rpfcrFic^TiDH 



*b'MriM^ 




l»i N 


H 


H 


• VHMI ». 




•> H 




"^ 


• .MMM 




'I H 


i 


N 


♦ VIM.J.- 




III N 


H 


■« 


•v..»i] : 




Ml N 


H 


•4 


•VMMM 




UN 


!. 


M 


•Tn]»-f 


»[tlll>l 


Olllt 


IITIIIIK 


lll> 


•t*F4r.; 


fFF 








•?"!- 










-:i-w«Ni 











Figure 3-8. Sample Printout of JEDEC Format 



BHE 



Terminal Displays 



xxxx 




3.5.14 ENTER FUSE NUMBER AND STATE 

Programming information in RAM for the logic device 
fuses may be entered using this command. Refer to 
figure 3-7 for an example of fuse states by fuse numbers. A 
fuse number is obtained by adding the line number and 
increment number corresponding to the intersection where 
the fuse is located. (See figure 3-9.) 



29A Displays 



^ 



29A Displays 



HHH 




</ </ 1/ 1/ 
i\ i\ t\ i\ 






UULiiJ 



NOTE 

XXXX is the fuse array sum-check of the 
device. 



Fuse number 



Enter a decimal fuse number; for example, 96. 








^ HH^3 



^10 

10-71&<XB7 SSOMXm 



*-= (INTACT) 



1 (OPEN) a> = ROW INTACrr 
INPUTS (0-31) 



c 1 



^s: 



O 2 



«9 



(0 

z 

K 

UlM i_ 

U 

O 
O 

oc 
a 



F 7 



is: 



FuM Numbar 



00 
24 

48 
72 



^ 



120 



= fe: 



is: 



192 32- 
21« 33- 



" '- 1^ 



240 <a- 
2C4 11- 



is: 



2H M — 
312 49 

3M U 

3W SI 



a I 



-t^ 



"- — tsp 



r. — i^ 



20 



• ' ' J • S « 7 11 IJIJ Id) Hit naxil 2I»M)I 



Figura 3-9. Comptota Logic Diagram 



Loaic Diaaram PAI 19UA 



^ 




s=0- 



&i> 



stO 



^O 




^ 



3;^ 



■ ■ «■■ a^ 



13 L 



3-19 
10-71&^n87 OOaA-002) 



29A Displays 



Terminal Displays 



uuJa uu 



T 



J 



Fuse state 



This display indicates that RAM data for fuse 98 is set 
for "don't program." To change it to a program state: 



29A Displays 





JJ ukj 



uu. 



(Fuse number increments automatically.) 
To decrement a fuse number: 



^ 




29A Displays 



uuJo U f 



D 





Enter the fuse number; for example, 98. 




HH 




■:D?inSMD = E EfnEP tiECllHL PUIc D-^T^ 



ItECIH**L P'J.'E 
M y ?• ? I 



This display indicates that RAM data for fuse 98 is : 
for "don't program." To change to a program state: 




□ 



Terminal Displays 



CaiWHMti ■ E ENTER DECINAL FylE DdTSi 

tECI»WL Fij;E = -SB 
00?S 1 



3-20 
10-71&«S7 (30SA-OG2) 



This indicates that fuse 98 will program, increments the 
fuse number display, and indicates the state of fuse 99 in 
RAM. To display the next fuse. 





N 



To display the previous fuse. 





3.5.16 EXIT COMMAND 

During terminal mode, use this function to exit specific 
operating modes. 




IcRTLJ + ( Z J simultaneously 



Terminal Displays 



To jump to a new fuse location. 




H 



then the decimal fuse number 




RETURN I 




or 



hi 


+ 


r^ 



simultaneously 
to exit the edit 
mode. 



3.5.15 DISPLAY CONFIGURATION NUMBER 

This command displays the configuration number of the 
adapter firmware. Configuration numbers are used as serial 
numbers for firmware. 



^^ BB1B1 IIIH3 



29A Displays 



1/ 1/ 1/ 1/ 
i\ i\ i\ t\ 



1^^ 



NOTE 

XXXX is the configuration number of the 
firmware in the adapter plugged into the 
PLDS. 




m 



returns control to the 
programmer front panel from 
temiinal control. 



3.6 MMI REGISTERED PAL® PRESET 
INFORMATION 

The V03 version of the 303A-002 P/T adapter added an 
auto-preset feature for MMI {Family 22) Registered PAl®s. 
Since the device registers do not power-on to a known 
state, this auto-preset feature sets the registers to a known 
state so that the Logic Fingerprint™ test can be performed 
without first having to intentionally preset the registers, as 
outlined in section 1.3 under Fingerprint Limitation 3. This 
feature is enabled whenever functional testing is performed 
on MMI Registered PAL^s. 

There is, however, one limitation of this preset feature: 
when the security fuse has been blown in the device, the 
registers will preset to a different state. This will cause a dif- 
ferent Logic Fingerprint™ test-sum to be cateulated for a 
good device. It is therefore necessary to have a second 
master device, one with the security fuse blown, to 
generate this second Logic Fingerprint™ test-sum for newly 
programmed parts to be checked against. This second Logic 
fingerprint™ test-sum can then be recorded for future 
manual entry or stored in a JEDEC format file. 



3-21 
io-7i&a>37 ooaA-oce) 



The operations that require the use of this second 
Logic FingerprinfTM test-sum are: 

1. Using a 3O3A-V01 LogicPak™ to do Logic RngerprintTw 
testing of previously programmed MMI Registered 
PAL® with the security fuse already blown. 

2. Using a 3O3A-V02 LogicPak™ to do programming with 
Logic Fingerprint™ testing of MMI Registered PAL® with 
the security fuse programming enabled. 

If you are presently using one of the methods of presetting 
the registers listed in section 1 .3, this auto-preset feature 
will have no effect on your results. 

To "learn" the Logic Fingerprint™ test-sum of a device 
with the security fuse blowm, and leave the fuse pattern in 
RAM intact, perform the following steps: 



1 . Select the number of Logic Fingerprint™ test cycles 
(section 3.5.7). 

2. Enter the starting vector if desired (section 3.5.8). 

3. Enter the value of 00000000 for the Logic FingerprintTw 
test-sum (section 3.5.8). 

4. Select verify option "2" (functional test only), 
(section 3.5.5). 

5. Insert the second (fingerprint) master device 
(section 3.4.2). 

6. Initiate a verify operation (section 3.4.6). 

Note: This is when the Logic Fingerprint™ test-sum 
is "learned". 

7. Select verify option (verify and test), 
(section 3.5.5). 



1O-71W3037 (303A-0!J2) 



SECTION 4 

CALIBRATION AND 
TROUBLESHOOTING 



4.1 OVERVIEW 

The material in this section is provided to help you keep 
your LogicPak™ and P/T adapter in optimum operating 
condition. For users who prefer to do their own calibration, 
detailed procedures, including measurement charts and timing 
diagrams (section 4.2) for each device, are provided. The 
basic procedures to set up the LogicPak™ in the calibration 
mode are described in section 4.2. 

4.2 CALIBRATION 

The need for calibration varies with the amount of use 
your LogicPak™ receives. Generally, we suggest calibration 
whenever: 1 ) programming yields fall below the 
manufacturer's recommended minimums, 2) when 
troubleshooting has been completed, or 3) if your company 
policy requires perbdic calibration certification. Because the 
LogicPak™ must be calibrated with an adapter installed and 
the values vary with different adapters, the detailed 
calibration procedures, measurement charts, and timing 
diagrams are provided in each adapter manual. The 
calibration setup procedure is described in this section. 

NOTE 
If calibration or repair is required, but you 
lack the facilities to accomplish it. contact 
the nearest Data I/O Sen/ice Center. 
Because of the different programmer 
mainframes and adapters this manual 
does not attempt to cover all areas of 
programmer calibration. Instead, it lists 
the steps necessary to calibrate only the 
LogicPak™. 

To prepare the LogicPak™ for calibratron: 

1. Remove the adapter (if any) from the LogicPak™ (see 
section 2.3). 



2. Remove the four phillips-head screws on the top of the 
LogicPak™ cover (see figure 4-1). 

3. Remove the two alien screws on each side of the 
LogicPak™ cover (see figure 4-1). 

4. Lift the cover off the circuit board cage assembly. 

5. Plug the adapter into the connector on the pin driver 
board as shown in figure 4-2. 

6. Plug the LogicPak™ into the programmer. 



PHILLIPS HEAD 

SCREWS 

(FOUR) 




ALLEN SCREWS 
(FOUR) 



Figure 4-1. LogicPak™ Cover Removal 



PIN-DRIVER 
BOARD 



R31 




R28 




Figure 4-2. Calibration Equipment Setup 



4-1 
10-71&a)a7 (303A-002I 



Because of the different programmer mainframes, this 
manual does not cover all areas of programmer calibration. 
Instead, it lists the steps necessary to calibrate only the 
LogicPak™ and adapter. 

Calibration of the LogicPak''^ and adapter consists of 
three parts: 

1 . Power supply calibration-measures the DC supply 
voltages of the programmer. All other voltage depend 
on these supplies; therefore, this part of the calibration 
procedure must be done first. Refer to your programmer 
manual. 

2. DC calibration-consists of measuring and adjusting 
critical DC voltage levels generated by the LogicPak™. 

3. Waveform observation-enables observation of 
waveforms on an oscilloscope to ensure compliance with 
the device manufacturers' critical voltage and timing 
specifications. 

Because the first part of the calibration procedure 
(power supply calibration) varies with the type of 
programmer you have, this manual refers you to your 
programmer manual for details on power supply calibration. 
DC calibration is discussed in section 4.2.1 and waveform 
observation is detailed in section 4.2.2. For information on 
how to carry out these steps on various programmers, 
consult your programmer manual. 

The following equipment is necessary to calibrate the 
LogicPakTM; 

• Three-and-a-half -digit digital voltmeter (DVM) 

• Dual-trace oscilloscope (Tektronix 465 or equivalent! 

4.2.1 DC CALIBRATION (Steps 1-10 and 12) 

These DC calibration procedures enable you to adjust 
critical DC voltage levels generated by the LogicPak™. To 
follow these procedures use the measurement chart at the 
back of this section (table 4-3), which contains the 
information necessary for all DC calibration tests. This 
information is included on the measurement chart in 
columns with the following headings: 

• Step No.-tells which step to use for each test. Step 
numbers are set at the programmer keyboard and 

roflor^oH in f-ho rllenlaw 

»^« ,,, V..W M-W^lfif. 

• Test No.-identifies individual tests. 

• Test description-ideritifies the functions being tested. 

• Measurement location-tells which socket pins or circuit 
board test points to probe for measuring voltages. 

• Measurement-specifies allowable measurement ranges. If 
a reading falls outside the range and you cannot adjust it 
to writhin the range, do not use the LogicPak'^ until the 
problem is corrected. 

• Adjustment location— tells which potentiometer to adjust 
if a measurement is out of range. 

• Comments-gives special instructions for particular tests. 



The DC calibration procedures follow: 

CAUTION 

Remove afi devices from the sockets 
before entering the calibration mode 
(see section 3.4.3 for details). 
Calibration voltages may damage any 
device In the LogicPak'™ sockets. 

1. Turn the programmer power on. 

2. Put the programmer into the calibration mode by 
following the key sequences in table 4-1 . The table also 
explains how to increment, decrement step 2, and how 
to enter calibration at an advanced step (which is 
required during the waveform calibration part of the 
process). 

3. Perform the general calibration steps (steps 1-10 and 16) 
on the measurement chart. 

Table 4-1. Key Sequence to Access the Calibration Mode 



Programmer 


Key Sequence to 


Increment 


Decrement 


System 


Enter Calibration 
Mode 


Step No. 


Step No. 


19 


Press SELECT 
Press C2 
Press ENTER 
Brter Step Number a 
Press START 


Enter 


Review 


29A 


Press SFI FCT 
Press CI 
Pr^ START 
Enter Stem Number a 
Press START 


Start 


Review 


100A 


Press SELECT 
Press 12 

Enter Step Number a 
Press START 


Start 


Backspace 


aOptk)nal 





CAUTION 
If the LogicPak''^ fails the second 
step on the measurement chart, DO 
NOT proceed to the next step. The 
hardware must pass this step or 
further testing may damage the 
LogicPak™. 



If the LogicPak''^ fails any step on the measurement 
chart, do not continue to the next step. Refer to table 4-2, 
which lists error codes and descriptions. Subsequent tests 
will not give valid results unless all preceding steps are 
passed and adjustments made. 



4-2 
10-71&O(B7 (303A-0CC) 



Table 4-2. LogicPak™ Error Codes 



ERROR 
CODE 



DESCRIPTION 



25 
30 

31 



No Socket Adapter 

No (or Invalid) Device Selected 

Overcurrent 



32 



33 



Backward Device 



Source Buffer Write Error (RAM) 



35 



Source Equation Translation Error 



36 



37 



38 



Begin RAM Pointer Not = 00190 



Invalid Device-Related Operation 



Calibration Step Error 



63 



65 



RAM Write Error 



Firmware Sum-Check Error 



70 
71 



DAC Error Vcc 

DAC Error Bit Switch Number 1 



ACTION 



Insert appropriate socket adapter. 

Enter valid device family and pinout codes 
(refer to Comparison Chart of Programmable 
Logic Device in each adapter manual). 

Hardware error in LogicPak™ or shorted 
device. Substitute a known-good device or 
consult the troubleshooting section. If error 
31 is displayed, caused by Vcc overcurrent, 
code 32 will display because £ is tested 
before 31 . 

(1) Device plugged in backward; turn it 
around. 

(2) Seeen-orSI. 

Source equations exceed the available RAM 
space; therefore, 

(1) Reduce the equation length to fit 
available RAM. 

(2) Add more RAM to system to 
accommodate the equation length (refer to 
programmer manual to expand RAM). 

Check equation buffer by connecting 
terminal to examine the equation buffer. This 
error code lets the operator know that an 
error exists in the source equatkins when the 
programmer is not controlled by a terminal. 

Refer to programmer manual to reset the 
begin RAM pointer to zero. This error usually 
occurs when changing from one 
programming pak to another. 

Verify, program, or other illegal operation 
was attempted, with a design adapter 
installed. 

Indicates that you've selected an incorrect 
calibration step. The error will also occur if a 
program operation is attempted prior to exist 
calibration. 

(1) Exit the calibration mode (refer to the 
programmer manual). 

(2) Reenter the correct calibration step 
number. 

System RAM failure. Refer to programmer 
nunuai or contact Data I/O service 
representative. 

Contact Data I/O service representative. This 
indicates that the EPROM firmware in the 
LogicPak''^ or adapter may have changed 
since the unit was shipped. Do not continue 
operation until the situation is corrected. 

See section 4.4 (troubleshooting). 

See section 4.4. 



4-3 

10-71&OOS7 (303A-(nZ) 



Table 4-2. Continued 



ERROR 






CODE 


DESCRIPTION 


ACTION 


72 


DAC Error Bit Switch Number 2 


See section 4.4. 


73 


DAC Error CE 


See section 4.4. 


74 


Logic Fingerprint™ Test Verify Error 


Indicates a Logic Fingerprint''''^ error. 

(1) Device passed fuse verify but failed Logic 
Rngerprinf^'*'' Test— defective device. 

(2) Operator has entered wrong 
test-sum. 

(3) Device cannot be tested with Logic 
fingerprint''''^ (refer to p/t adapter manual for 
the limitations of the Logic Fingerprint™ 
test). 


75 


Structured Test Verify Error 


(1) The device passed fuse verify but failed 

structured test— defective device. 

(21 Check structured test vectors and make 

sure they are correct. If not, reenter the 

correct vectors. The vector could be invalid, 

or the operator may have miskeyed a valid 

vector. 


76 


Self-Test Error 


Indicates failure In the LogicPak"''" Consult 
section 4.4 (troubleshooting) or contact your 
Data I/O service representative. 


77 


Security Fuse Programming Error 


(1) Indicates that the security fuse option 
cannot be programmed in the installed device. 

(2) There is no security fuse option 
available for this type of device. 


78 


No Fuse Verify Set 


Indicates you've tried to program the device 
with the verify-option mode set for 2. The 
verify option won't allow this. When this 
error code displays, select E6 and enter or 
1, and then you will be allowed 1 program. 


82 


Checksum Error 


Indicates an incorrect transmission data from 
a peripheral to the serial port, including fuse 
data, CHs, STX, etc. 


84 


Sum-Checl( &ror 


(1) indicates an error in the fuse data, or 

(2) Received fuse data does not match fuse 

sum-check (C-fiefd error). 

Indicates an invalid fuse address. Check 


91 


Fuse Address Error 


input and make sure fuse address is four 
decimal numbers or an othenwise valid 
address. 



44 
10-71&<XB7 OOQA-OOZ) 



For each general calibration step on the measurement 
chart: 

• Take measurement readings at the device sockets or test 
points indicated in the measurement chart. 

• Ground the DVM to pin 10 on a 20-pin socket, to pin 12 
on a 24-pin socket, or to pin 14 on a 28-pin socket. 

• The oscilloscope trigger point is called out on the 
measurement chart photographs. 

• The adjustment potentiometers on the waveform 
generator and the T/rise comparator card enable you to 
make adjustments when your measurements do not 
match the measurement chart; figure 4-3 shows the 
location of these adjustment points. 

• Access each new step by pressing START (or ENTER). 
The new step number will appear on the display when 
the LogicPak™ is ready for the next step. To return to a 
previous test, press the REVIEW (or BACKSPACE) key. 

4.2.2 WAVEFORM OBSERVATION 

Programming waveforms of your LogicPak™ can be 
observed with an oscilloscope and compared with the 
timing diagrams at the end of this section. In this way, 
timing and magnitude relationships can be measured against 
known specifications to confirm that the LogicPak™ is 
performing to the device manufacturer's speciflcatk>ns. 
When step 15 is called, the waveforms will reflect the 
programming algorithm for only the fuses to be 
programmed as specified in RAM. To alter the state of the 
individual fuses, refer to section 3.5.14, "Enter Fuse Number 
and State" (select code EE). Because the LogicPakTM 
generates many waveforms, and all calibration adjustments 
are accomplished in DC calibration, it is only necessary to 



observe waveforms for commonly used devices or devices 
that are presenting yield problems. These measurements can 
be performed on any device by entering the appropriate 
family pinout code and fuse number (if appropriate). 
During the waveform observation phase of the 
calibration procedure, your LogicPak™ uses a firmware 
routine that generates programming and verify waveforms 
for the data stored in system RAM. 

4.2.3 EXPLANATION OF TIMING DIAGRAMS 

This manual contains a set of timing diagrams for the 
MMI/National family of logic devices. The timing diagrams 
show critical waveforms for a specific device (e.g., 16L8) 
but may be verified for any of the devices by entering the 
appropriate family and pinout codes before invoking the 
calibration mode. To use these diagrams and photographs, 
read the Information provided below and refer to the sample 
timing diagram (figure 4-4). 

1. Family Pin Code Number-corresponds to the family pin 
code number of the device. 

2. Waveform Variables-lists the minimum and maximum 
parameter values; voltage and timing parameters other 
than those listed in this table are to be considered 
noncritical vwth a +1 - 10% tolerance. 

3. Notes-important information pertaining to a timing 
diagram. 

4. Waveform Names-the manufacturer's reference to the 
pin being observed. 

5. Layout Sequence Number-used as a reference point 
within each diagram. 

6. Delay Time Position-indicates the time from the start of 
the main sweep to the start of the delay time. 



=^ 




Rise Time Comparator 
(701-1941) 




Waveform Generator 
(701-1939) 



Figure 4-3. LogicPak™ Test and Adjustment Locations 



4-5 
lO-TIMOS? (303A-OQ2) 



10. PIN NAME AND 
NUMBER 



9. VOLTAGE 



1. FAMILY PIN 
CODE 
NUMBER • 

2. WAVEFORMi 
VARIABLES 




,G(i.D *CCi 



GMD "H 




«-#i 



i^^VMftVEFOWM VARIABLES 



*»«* M*« UHM COWMtWTS 



L 



\DTIS -^MB 



5 T«r oorfirs mr'o< rtir X p-" ^aite 



DfOhhO 



8. TIME-BASE SETTING 

7. OSCILLOSCOPE 

GROUND REFERENCE 



6. DELAY TIME POSITION 



5. LAYOUT SEQUENCE 

NUMBER 
4. WAVEFORM NAMES 

3. NOTES 



Figure 4-4. Sample Timing Diagram 



4-6 

io-7i&oQa7 ooaA-ooei 



7. Oscilloscope Ground Reference-ground contact on the 
socket with its LED illuminated. 

8. Time-Base Setting-horizontal positioning of the 
wavefomns is not critical and may vary slightly from the 
photographs. The important observation is the timing 
relationship between the waveforms in the photographs. 
You can adjust this timing relationship on your 
oscilloscope to set convenient reference points. By 
considering any time-base variance, you can also make 



time comparisons between photographs. The time base 
is always the same for different waveforms in the same 
photograph. 

9. Voltage-indicates volts per division. The one in the 
upper-left comer is for the top trace and the one in the 
lower-left corner is for the bottom trace. 

10. Pin Name and Number-the device pin name and socket 
pin number where the waveform can be observed. 



4-7 
10-71&OQ37 (3CSA-0Q2) 



5 



t 



STEP 



TeST 
NO. 



REVISIONS 



Table 4-3. Measurement Chart 



DESCRIPTION 



Release 



TEST DESCRIPTION 



Allplns low 



Self-test, sink drivers 



LED test 1 



mJM, 



Measurement Chart for MMI National PAL Adapter 
10-715-1947 (303A-002) 



MEASUKEMCNT LOCATION 

Socket/pins or circuit board test points 



24 pin/all pins 



20 pin/all pins 



MEASUREMENT 



MIN 



-0.4 



Comparator reference 



VCC supply 



CE supply 



Bit supply SW 1 



701-1939/TP5 



0.8 



10.20 



24 pin/pin 24 



20 pin/pjn 20 



24 pin/pin 13 



24 pin/pin 19 



Bit supply SW 2 



DAC reference 



24 pin/pin 14 



11. 9 



10.24 



ADJUSTMENT 
LOCATION 



COMMENTS 

Ground Din 10 or 12^ 



10.28 



12.0 



19.8 



19.8 



19.6 



701-1939/TP6 



4.7 



20.0 



20.0 



12.1 



20.2 



20.2 



R28/701-1939 



CAUTION^' 



See table 4-4 if errors result: 



errors must be corrected to 



continue. Possible errors are 



AO-OF. 



Confirm 24-p1n LED on, 20-pin off 



For test 5-19. see note^. 



R9/701-1939 



R31/701-1939 



R6/701-1939 



20.4 



5.3 



CAUTION: DO NOT POWER DOWN AFTER STEP 1. 



CAUTION^ 



Load with 50n 5W resistor to 



ground.^ 



Load with IQQn 5W resistor to 
ground.** 



Load with lOOn 5W resistor to 
ground.*^ 



Load with lOOn 5W resistor to 
ground. d 



.,» X !■_ ^ , .. _ v-nuiiun; uu wui fUWtK UUWN Ah tR STEP 1 

^Connect the ground of the DVM to ground pin 10 on a 20-Din sorkPt tn nin i? nn :. oVli . : ... 

boo not leave programmer unattendeS in calibration rode Eeyond step 1? ^ °" ' ^^""'^ '°''*^*' "^ "^^ P^" 1" °" ^ 28-p1n socket. 

CVoltage levels are for calibration purposes only and are not the specified levels of the device manufacturer. For manufacturer- 
specific levels refer to step 12. 
''insert load resistor after pressing START; remove immediately after performing test. 



§ 



t 



k 



REVISIONS 

DESCRIPTION 



Table 4-3. Continued 



STEP 



Ti»T 
NO. 



Release 



To- 



ll 



IT 



"IT 



"IT- 



T«8T DESCRIPTION 



Self-test source drivers 



K*l 



DATE 



^^ 



Measurement Chart for MMl National PAL Adapter 
10-715-1947 (303A-O02) 



MEASUREMENT LOCATION 

Socket/pins or circuit board test points 



LEO test 2 



docket pins TTL high 



Socket pins TTL low 



If 



Socket pins TTL low 



Socket pins TTL high 



TT 



17 



18 



Socket pins source 



Socket pins TTL high 



Socket pins TTL high 



MEASUREMENT 



i>4 pin/pins i:, 4, 6, 8, 10. 13, 16, 18, 19. 21, 23 



20 pin/pins 2,4,6,8,11,13.15.17.19 



24 pin/pins 1,3,5,7,9,11,14,15,17,20,22 



20 pin/pins 1,3,5,7,9,12,14,16,18 



at pin/pins 2,4,6,8.10,13,16,18,19 ,21,21 
i:u pin/pins 2,4,6,8,11,13,15,17,19 



24 pin/pins 1.3,5,7,9,11,14,15,17,20,22 



3.0 



3.0 



-0.4 



-0.4 



-0.4 



-0.4 



20 pin/pins 1,3,5,7.9.12,14,16.18 



24 pin/pins 2.4,6,8,10,13.14.16.18,19. 



21.23 



20 pin/pins 2,4.6.8,11,13,15,17,19 



24 pin/pins 1.3.5.7.9,11.15.17.20.22 



20 pin/pins 1.3,5,7,9,12,14.16.18 



24 pin/pins 2,4,6.8.10.13.14.16.18,19. 



21.23 



3.0 



3.0 



9.5 



9.5 



9.5 



3.0 



3.0 



3.0 



3.0 



5.2 



5.2 



0.8 



0.8 



0.8 



0.8 



5.2 



5.2 



10.5 



10.5 



10.5 



5.2 



5.2 



5.2 



5.2 



ADJUSTMENT 
LOCATION 



aconnect the ground of the DVM to ground pin 10 on a 20-p1n socket, to pin 12 on a 24-pin socket, or to pin 14 



COMMENTS 

Ground pin 10 or 12^ 



See table 4-4 If erro rs result. 
Possible errors are EO-FF. 



Confirm that 20-pin socket 



LED is on and 24-pin LEO Is off. 



Iferror 76 occurs during steps 



5-16. perform steps 2 and/or 4 



for diagnostics. 



on a 28-p1n socket. 



1 



o 



STEP 



10 



Tt«T 
NO. 



18" 

"IT 



TT 



IT 



22 



REVISIONS 



Table 4-3. Continued 



DESCRIPTION 



Releasp 



TESTOESCfllPTION 



Socket pins source 



Backwards device test 



6vercurrent test 
Low range V(^(; 



.^mJ&L 



DATE 



Me.isiirement Chart for MMI National PAL Adapter 
10-715-1947(303A-C02) 



Low range CS switch 



Low range bit switch 1 



Low range bit switch 2 



Overcurrent test 



High range 



MEASUREMENT LOCATION 

Socket/pins or circuit board test points 



20 pin/pins 2,4,6,8,11.13,15,17,19 



24 pin/pins 1,3,5,7,9,11,15,17,20,?? 



20 pin/pins 1.3,5,7,9, 1?, 14,16,18 
24 pin/pin 24 20 pin/pin 20 



MEASUREMENT 



3.0 



9.5 



n.5 



24 pin/pin 24 



20 pin/pin 20 



24 pin/pin 13 



24 pin/pin 19 



24 pin/pin 14 



NOM 



24 pin/pin 24 



20 pin/pin ?0 



MAX 



5.? 



10.5 



ADJUSTMENT 
LOCATION 



10.5 



COMMENTS 

Ground pin 10 to 1?^ 



CAnTIOfP.c 



Load with lOo to around, confirm 



error 32. 



CAUTIONC 



Load with 2no 5W Lm oround, 



confirm error 31 , 



..idi with 30o 5W to ground. 



confinii prror 31. 



Load with 30n 5W to ground. 



confirm error 31. 



Load with 30o 5W to ground. 



confirm error 31. 



cautionc 



Same loads as step 9, confirm no 



errors. 



^Connect the ground of the DVM to ground pin 10 on a 20-pin socket, to pin 1? on a ?4-pin socket or to nin la on ;, ?q n,-. e , * 
CTn«^J "'^""""^ .'" ^^il ''"P or beyond; must enter calibration at an advanced step (See fabl, '4-? ' ^^ '"'"''• 

^Insert load resistor after pressing START; remove immediately after performinq test! ' 



§ 



ITR 



STEP 



TEST 
NO. 



w 



REVISIONS 

DESCRIPTION 



Table 4-3. Continued 



Release 



TEST DESCRIPTION 



7T 



High range Vqq 



7T 



TT 



7T 



High range CS switch 



High range BIT switch 1 



High range BIT switch 2 



IT 



Waveform observation 
for security fuse 



programming 



?r 



Static programming" 
■Levels VCCP 



'CE Gen VIHH 
Ull tien VIHH 



mc 



DATE 



mt 



Measurement Chart for MMI National PAL Adapter 
10-715-1947 {303A-002) 



MEASUREMENT LOCATION 

Socket/pins or circuit bo ard test points 
Z4 pin/pin 13 ~ " 



^4 pin/pin 19 
24 pin/pin 14 



A pin/pin 24 



20 pin/pin 20 



24 pin/pin 13 



MEASUREMENT 



24 pin/pin 19 



24 pin/pin 14 



Refer to timing diagram (this step 



number) for test points, family 



pin code, and waveforms. 



Jo pin/pin 20 
20 pin/pin I 



Jo pin/pin 19 



NOM 



11.5 



11.5 



11.5 



ADJUSTMENT 
LOCATION 



12.0 



12.0 



12.0 



COMMENTS 

Ground pin 10 or 12* 



Load with 5o 5W to ground. 



confirm error 31. 



Load with l2o 5W to ground, 



confirm error 31. 



Load with 12o 5W to ground. 



confirm error 31. 



Load with 12o 5W to ground. 



confirm error 31. 



Verify waveforms per timing 
diagrams.'' ' " 



Note ".c 



Voltages are for fuse 32. 



Family code = 95. 



^Connect the ground of the DVM to ground pin 10 on a 20-Dln socket tn nin i? nn , 9/i „• 

bA family pin code must be entered or errSr 30 will be f^aSged See the Umfna dfaaraS^fnTtfllH^'' i° "'" ^^ °" ^ ^S-pin socket. 

CA fuse number must be entered or default to fuse will occur] aiming diagrams for valid code. 



g 






g 



REVISIONS 



Table 4-3. Continued 



DESCniPTION 



-Release 



STEP 



12 



13 



14 



15 



16 



17 



TEST 
NO. 



26 



27 



28 



29 



30 



31 



TEST DESCRIPTION 



Static programming 



Levels VCCP 



VIHH 



VIHH 



Waveform observation 



Verify array 



Waveform observation 



Program array 



Waveform observation 



Program all fuses (opt) 



Rise time adjust(tr2) 



CS switch 



BIT switch 1 



BIT switch 2 



Supply linearity 



Vcc supply 



CE supply 



P.E. 



2*1 



^ 



Measurement Chart for MM! National PAL Adapter 
10-715-1947 (303A-002) 



MEASUREMENT LOCATION 

Socket/pins or circuit board test points 



20 pin/pin 20 



20 pin/pin 1 



20 pin/pin 19 



Refer to timing diagram 



(this step number) for test points, 



family pinout code, and waveforms 



MEASUREMENT 



MAX 



11.5 



11.5 



11.5 



Refer to timing diagram 



(this step number) for test points. 



family pinout code, and waveforms 



No timing diagram supplied; waveforms 



will vary depending on RAM data 



24 pin/pin 2 



24 pin/pin 23 



24 pin/pin 18 



24 pin/pin 24 



24 pin/pin 16 



ADJUSTMENT 
LOCATION 



12.0 



COMMENTS 

Ground pin 10 or 12* 



foltages are for fuse 32. 



12.0 



-araily code = 22. 



12.0 



tote ti.c 



9.0 S 



8.0 S 



8.0 S 



l/erify waveforms per timing 



Jiagram for fuse number Indicated. 



/erify waveforms per timing 



Jiagram for fuse number Indicated. 



-pad RAM for desired pattern. 



"/avefonns are for fuses that have 



data stored In RAM. 



U/701-1941 Mjust Rl for Tr as shown on 



11.0 S 



12.0 S 



12.0 S 



timing diagram (this step 



lumber). 



Verify waveforms per 



timing diagram (this step number). 



BIT supply 24 pin/pin 19 , — — 

^Connect the ground of the OVM to ground pin 10 on a 20-Dln socket tn nin 1? on ;, ?d ni^ cn^uof * ■ ^A Waveforms should be linear as shown. 

bA family pin'code must be enteredV erro'r 30 wni\e f?Ig%'5'''ke'?he' tllinp"dia r'^S % ' id°co e '" '' "" ' '^-''" ""''''■ 
CA fuse number must be entered or default to fuse will occur. ' 

"°^^' refer^to'tte^Sr^ ^'"" "^^^'"^'^^°" """"P"^" »'">' «"d are not the specified levels of the device manufacturer for manufacturer-specific levels; 



Measurement Chart Photographs 



4-13 
10-71 5-0037 (303A-002I 



Measurement 
Chart 



PROGRAM ELECTRONICS 



RISE TIME WAVEFORM 



CHIP SELECT SWITCH PIN 2 



VCALH 



VCALL 




GND 



BIT SWITCH 1 PIN 23 



VCALH 



VcALL 




GND 



4-14 
1^71&«H7 (303A-002) 





DATE 


REV 


REVISION RECORD 


DR 


CK 




r/2?/5'3 


A 


Release 


f</^ 




















































B!T SWITCH 2 PIN 18 




B 




WM 



VcalhI 



VCALL 




GND 





VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


VCALH 


19.8 


_. 


20.2 


V 






VCALL 


4.8 


- 


5.2 


V 






Tri CS SW 


6.75 


.750 


.825 


;us 


Adjust 
ni on 1941 
end 




Tr2 CS SW 


9.0 


10.0 


11.0 


lis 






TrsCSSW 


22.5 


25.0 


27.5 


US 






TriBIT SW 


.600 


.750 


.900 


ps 






TR2BITSW 


8.0 


10.0 


12.0 


ps 






Tr3 BIT SW 


20.0 


25.0 


30.0 


iis 





NOTES 

1. Oscil/oscope trigger: TP1 1939 card. 

2. Step 16 on the measurement chart. 

3. Test points are for the 24-pin socket. 



4-15 
1O-71&O037 (303A-(nZ) 



Measuremenl 
Chart 


' PROGRAM ELECTRONICS 

1 


SUPPLY LINEARITY 
















Vcc SUPPLY 






~15V 
PIN 24 








GND 






CE SUPPLY 






~24V 
PIN 6 


/ — 


/ 


1 




oms 















4-16 
1O-715O0S7 <303A-O02) 



DATE 



V/^7/5 



Cr 



REV 



REVISION RECORD 



DR 



CK 



Release 



£2m. 



BIT SUPPLY 




GND 



NOTES 

1. OsciUoscope trigger: TP1 1939 card. 

2. Step 17 on the measurement chart. 

3. Test points are for the 24-pin socket. 



4-17 
10-71&ai37 I303A-0Q2) 



Timing Diagrams 



4-18 
10-71&0C37 OOiA-OaH 



Vp 
V|H 



Vp 



V|H 
V|L 



i?K 


PIHII 


: 20uS 

1 ■ ■ 




J- ■ 




•»—» 


1 ■ ■ 


7(^ 


PIN J 





GND 



GND 




GND 



GND 




GND 



GND 



FAMILY CHARACTERrSTICS 





VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


Vp 


20.0 


.. 


22.0 


V 






V|H 


3.0 


- 


5.2 


V 






V|L 


-0.4 




0.8 


V 






Tpw 


20 




SO 


ms 





NOTES 

1. Oscilloscope trigger: TP1 1939 card. 

2. Family pin code 9517. 

3. Step 11 on the measurement chart. 

4. Test points are for the 20-pin socket. 



s 



IS 



g 



REVISIONS 



LTR 



DESCRIPTION 



Release 



P.E. 



y/K 



DATE 



SECURITY FUSE PROGRAM 
TIMING DIAGRAM FOR FAMILY CODE 9517 



DMA I/O 



vccv 




V|HH 



GND 



GND 




QNO 



GND 




GND 



GND 



FAMILY CHARACTERISTICS 





VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


vccv 


4.8 


6.2 


.. 


V 






V|HH 


11.5 


12.0 


-- 


V 






V|H 


3.0 


5.2 


-- 


V 






V|L 


-0.4 


0.8 


-■ 


V 






Bt 










Backward 
Device Test 



NOTES 

1. Oscilloscope trigger: TP1 1939 card. 

2. Family pir} code 9517. 

3. Step 13 on the measurement chart. 

4. Fuse 32. 

5. Test points are for the 20-pin socket. 



S 



REVISIONS 



LTR 



DESCRIPTION 



Release 



P.E. 



7F 



DATE 



VERIFICATION WAVEFORM 
TIMING DIAGRAM FOR FAMILY CODE 9517 



DfflAI/0 



0526/ 12«! 



s 




6ND 



QND 



GND 



V|HH 




V|HH 



VCCP 



Vccv 



iv : ^WC'PIhM 



'W^^' 



GND 



GND 



■ GND 



IS 



§ 




GND 



GND 



GND 



V|HH 



V|HH 




V|HH 



GND 



QND 



GND 



FAMILY CHARACTERISTICS 





VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


VCCP 


11.5 


„ 


12.0 


V 






vccv 


4.8 




5.2 


V 






VlHH 


11.5 




12.0 


V 






V|H 


3.0 




5.2 


V 






V|L 


-0.4 




0.8 


V 






Tpw 

BT 


lOiJS 




50 


JJS 


Backward 
Device Test 



NOTES 

7. Oscilloscope trigger: TP1 1939 card. 

2. Family pin code 9517. 

3. Step 14 on the measurement chart. 

4. Fuse 9517. 

5. Test points are for the 20-pin socket. 



z 



u 



REVISIONS 



LTR 



DESCRIPTION 



P.E. 



^M- 



OATE 



yAs/ jy 



PROGRAMMING WAVEFORM 
TIMING DIAGRAM FOR FAMILY CODE 9517 



Sheet 1 of 2 



DfflAI/O 



53 



U 



V|HH 



V|HH 




GND 



V|HH 



GND 



GND 



s 



^ 



I 







REVISIONS 








LTR 


DESCRIPTION 


P.E. 


DATE 




A 


Release 


t:m 


v/7.rfi(i 












TIM 



















































PROGRAMMING WAVEFORM 
TIMING DIAGRAM FOR FAMILY CODE 9517 



Sheet 2 of 2 



DAIAI/0 



9 

■M 



15 



I 



GND 



QND 



GND 



10^ PIN 11 



W PINI 



22M 



jvp 




VCCPIN^ 



gnd! 



gnd! 



■^■'U.^ 



PI^l: ; lOOCfrS 



GND 



GND 



■ 


1 






VCCPP 



FAMILY CHARACTERISTICS 





VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


Vp 


18.0 


1B.5 


19.0 


V 






VCCPP 


5.5 


6.0 


6.5 


V 






V|L 


-0.4 


-- 


0.8 


V 






Tpw 


40 


60 


60 


ms 


(5 Pulses) 



7. 



8. 



NOTES 



Oscilloscope trigger: TP1 1939 card. 
Calibration step 11. 
Family pin code 2217. 
Test points are for the 20-pin socket. 
Test points are identified on left side of photos. 
6. Important pulse widths (Tpwl and/or rise times (T/j) are 
identified on photos. 

Oscilloscope horiz. time base setting Is identified on top of 
photos when delayed sweep is used, the delay time from 
trigger is on bottom. 
Oscilloscope vert, voltage settings are identified on photos. 



5 



S 



REVISIONS 



LTR 



DESCRIPTION 



Release 



P.E. 



icm 



DATE 



MMI NATIONAL ADAPTER 
LOGICPAKTM TIMING DIAGRAMS 
DEVICE CODE 2217 



DfflAI/O 



0526/1282 



<3N0 



QND 




GND 



gnd: 




^ 1/ V'^ 



gnd! 



gnd: 



10 PIN 2 



5k i 'PiN '9\ i pM" 



lOCd 



|V|HH 

|v|L 
|V|HH 

V|H 
V|L 



GND 



GND 



4 



V|HH 






FAMILY CHARACTERISTICS 






VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


V|HH 


11.B 


11.75 


12.0 


V 






V|H 


3.0 


-- 


5.2 


V 






V|L 


-- 


- 


0.8 


V 






vccv 


4.75 


5.00 


5.25 


V 






BT 










Backward 

Device 

Test 



9 



is 



NOTES 

Oscilloscope trigger: TP1 1939 card. 

Calibration step 13. 

Fuse 32. 

Family pm code 2217. 

Test points are for the 20-pin socket. 

Test points are identified on left side of photos. 

Important pulse widths (Tpw) and/or rise times (Tf^) are 

identified on photos. 

Oscilloscope horiz. time base setting is identified on top of 

photos which delayed sweep is used, the delay time from 

trigger is on bottom. 

Oscilloscope vert, voltage settings are identified on photos. 



REVISIONS 



LTR 



DESCRIPTION 



Release 



P.E. 



Twr 



DATE 



MMI NATIONAL ADAPTER 

LOGICPAKTM TIMING DIAGRAMS 

DEVICE CODE 2217 



Sheet 1 of 2 



DfflAI/O 



0526/1282 



5 




QNO 



H 






s 



1^ 



REVISIONS 



LTB 



DESCRIPTION 



P.E. 



TW 



DATE 



Sheet 2 of 2 



DfflAI/0 



0526/1203 



s 







PINI ' 


SOOi^ 


ftMn 


m 








^^^^■pi^novTm^^l 


- 


QND 
QND 


•, >__ 






f 


1 ill i 


: \ ^ „ 



V|HH 

V|L 
V|HH 

V|L 

VccP 
VccV 
V|L 



QND 



OND 



GND 



is 




our PiH i^ 



sod 



QND 



QND 



OND 



:^JK : VCCPlH^ ^SM 



|VJHH 




GND 



GND 



GND 




FAMILY CHARACTERISTICS 





VARIABLE 


MIN 


NOM 


MAX 


UNIT 


COMMENTS 


PROGRAM 


V|HH 


11.B 


11.75 


12.0 


V 






V|H 


3.0 


-- 


6.2 


V 






V|L 


-0.4 


-- 


0.8 


V 






VCCP 


11.5 


11.75 


12.0 


V 






vccv 


4.75 


5.00 


5.25 


V 






BT 






" 


■- 


Backward 

Device 

Test 




TD 


1 


- 


- 


us 






TPW 


10 


15 


50 


na 





NOTES 

f. Oscilloscope trigger: TP1 1939 card. 

2. Calibration step 14. 

3. Fuse 32. 

4. Family pin code 2217. 

5. Test points are for the 20-pin socket. 



§ 



V 



REVISIONS 



LTR 



DESCRIPTION 



Release 



P.E. 



DATE 



MMI NATIONAL ADAPTER 

LOGICPAKTM TIMING DIAGRAMS 

DEVICE CODE 2217 



Sheet 1 of 2 



DfflAI/0 



0526M282 



GNDl 



2 



QNDl 



Is 



our PIN 1^ 


IGuS^ 


' ^ -■— 




-H hHE 




C P& ; 


\^ 







V|HH 

V|H 

VcCP 
VccV 



GND 



QND 



OND 




s 



Is 



REVISIONS 



LTB 



DESCRIPTION 



P.E. 

3S 



DATE 



V^^V^ 



Sheet 2 of 2 



DAlAI/0 



0526/1282 



Table 4-4. Error Codes for Calibration 



ERROR 


I/O PINa 


CONDITION 


ERROR 


I/O PINa 


CONDITION 


AO 


1 


Failure to 


DO 


17 


Failure to 


A1 


2 


read desired 


D1 


18 


read desired 


A2 


3 


level on input 


D2 


19 


TTL level on 


A3 


4 


register 


D3 


20 


output pin 


A4 


5 




D4 


21 




A5 


6 




D5 


22 




A6 


7 




D6 


23 




A7 


8 




D7 


24 




A8 


9 




D8 


25 




A9 


10 




D9 


26 




AA 


11 




DA 


27 




AB 


12 




DB 


28 




AC 


13 




DC 


29 




AD 


14 




DD 


30 




AE 


15 




DE 


31 




AF 


16 




DF 


32 




BO 


17 


Failure to 


EO 


1 


Failure to 


B1 


18 


read desired 


El 


2 


read desired 


B2 


19 


level on input 


E2 


3 


10V level on 


B3 


20 


register 


E3 


4 


desired 


84 


21 




E4 


5 


output pin 


B5 


22 




E5 


6 




86 


23 




E6 


7 




87 


24 




E7 


8 




B8 


25 




E8 


9 




89 


26 




E9 


10 




BA 


27 




EA 


11 




DO 


ffi 




CD 


12 




W>k* 












BC 


29 




EC 


13 




BD 


30 




ED 


14 




BE 


31 




EE 


15 




BF 


32 




EF 


16 




CO 


1 


Failure to read 


FO 


17 


Failure to 


CI 


2 


desired TTL 


F1 


18 


read desired 


C2 


3 


level on 


F2 


19 


10V level on 


C3 


4 


output pin 


F3 


20 


desired 


C4 


5 




F4 


21 


output pin 


C5 


6 




F5 


22 




C6 


7 




F6 


23 




C7 


8 




F7 


24 




C8 


9 




FB 


25 




C9 


10 




F9 


-- 




CA 


11 




FA 


Z7 




C8 


12 




FB 


28 




CC 


13 




FC 


- 




CD 


14 




FD 


- 




CE 


15 




FE 


-- 




CF 


16 




FF 







8 see LogicPak™ manual for locations of I/O pins 



4-37 

1O-71&O037 (303A-002) 



SECTION 5 



CIRCUIT DESCRIPTION 



5.1 INTRODUCTION 

This section defines the functions of the LogicPakTw 
P/T adapters' principal components. The circuit board 
assembly is depicted by a block diagram accompanied by a 
written description. 

5.2 GENERAL ARCHITECTURE 

The adapters interface with the LogicPak™. When they 
are installed, they customize the PLDS to support a specific 
family of logic devices. 

5.3 COMPONENT LAYOUT 

A typical block diagram is shown in figure 5-1, and the 
schematic is at the back of this manual. The adapter board 
routes all the necessary signals required to perfonn fuse 
operations and functional tests of the logic devices. These 
signals are routed to two sockets to support the pin counts 
of the devices. The socket enabled by the family pinout 
code is identified by the lighting of the appropriate socket 
LED. 



Programming voltage levels are routed to a clamping 
R-C network, which is precharged to the programming 
voltage potentials. When the programming pulses are 
presented to the device pins, the network prevents 
overshoot. 

A backward test circuit connects to the Vcc pin of 
each socket. The circuitry tests the orientation of the logic 
device in its socket. If it is incorrect, an error code will be 
flagged and operation will stop. The test method limits 
power to the device, thereby preventing damage to it. 

Firmware specific to the device manufacturer's family of 
logic is resident in an EPROM, which receives its address 
and select inputs from the LogicPak™. The PROM outputs 
are buffered by an octal data gate, whose inputs feedback 
to the data base within the LogicPak™. Fuse programming, 
verification, and functional testing algorithms are stored in 
PROM and are referenced by stored family and device 
pinout codes. 



5-1 
10-71 5«J37 (30aA-Oa2J 



CE. BIT SUPPLV 



2 LINES 



■NPUT /OUTPUT 1» 



s 



n M 



e 
3 
71 



■D 

O 

« 

■u 

S 

a 

5 
3 

3 

a* 
tt 

I 

3 

n 

> 
a 



Vcc Pi»uup 



SELECT A 



SELECT B 



"CC 



Vcc SENSE 



LED 
A 




LED 

a 



CLAMP 



O 

o 

w 

o 

m 

CI 

3 
3 



ADDRESS BUS 




APPENDIX A 



FUNCTIONAL DIAGRAMS 
FAMILY AND PINOUT CODES 



Increment Number «-<»S'« Diagram PAL10H8 


1 2 


3 4 S 


9 1 


M3 1 


S17 t 


071 J 


• lb »2I)0]1 


— o 
















Line 

Number „ 














D — ^~^ " 


' K 














B-iJ> — 


> 
















ao — 

1 hw. 














B-^_> 


— 1>^ W| 
















^ K- 














B-^I> 


\U 
















'■ K_ 














||===r:=8=0 - 


[> 1 
















wo 

fi ^w 


! 












:==B=C> 


1> 
















f K> 
















fF=====B=C> ^ 


> LI 
















(F K. 














F=====B=0 


1> 
















hs 














F=8=0 ^ 


• 11) 


* I • 

NOTE: Fi 


ise nu 


mber = 


1 « 

= Incri 


tment 


Numbe 


<| ^ 

r -f Line Number 


Figure A-1. Logic Diagram PAL10H8 








10 


> 
-715003 


V-1 
7(303A 


002) 





Incren 

t 1 7 ] 

1 t^ 


lent Number ^ 

« S 1 ? ■ ) 


to 11 


on 


WW m? « 1 


Logic Diagram PAL12H6 

1 xrisxi 




D% 








,., ^ 




1? \ 




Line 
Number „ 












^ ^ 




12 

i fSr 












^3 












- — bF 4- 










-— =B=L> 




\^ 






5=D 




i — hs 




1 






E 




u^ — 








fVj 










B-4J> 




U*— 








- — r> 










B-O 




v^ 

)I2 










an — 1 

'- 1> 










_^ 




! Kg^ 










< ^ 




*^ i-i— +4- 
1 NOTE 


• ' 1 ■ W 11 

: Fuse numbt 


1? ij 

>r = In 


creme 


llii 1 

w i; a « K 

nt Number 


Vr <-- 

?' SK » 

+ Line Number 






Figure A- 


2. Log 

10-71^ 


!c Dia{ 

A-2 

0037(30 


(ram PALi: 

8A-0Q2) 


i»B 


— 1 





Increment Number 



Logic Diagram PAL14H4 



->= 



g I 2 3 4 S I ? • I 1011 1213 Mil MIT 



^X==. 



i^ 



•~t!^ 



Line 
Number 



^ 



i*: 



^ 



^Cs 



•—i^ 



« <• aozi a a ataiiz? 



■ II] 4ti> itiati 12 1] 



^ 



^ 



^ 



:^ 



^ 



« II H 11 M ;i Z? 73 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-3. Logic Diagram PAL14H4 



A-3 

10-715«)37 (303A-002t 



Logic Diagram PAL16H2 



Vncrement Number 

I'l •*« imn i:i]iai5 liuiiis mmii Miisji aaxit 




=— ts 



•'»' •*«» »imi 12I9MIS Kiiiiit lijini] M»»:; nnjiji 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-4. Logic Diagram PAL16H2 



A-4 

10-71&a3S7 (303A-002) 



Logic Diagram PAL16C1 



Increment Number. 




I'JJ aiir I mil iiiihii iiii<iii miihi] »»»» niaaii 

NOTE: Fuse number = Increment Number + Line Number 



Rgure AS. Logic Diagram PAL16C1 



A-5 

io-7i&ooa7 ofOMxta 



Logic Diagram PAL20C1 



Line 
Number „ 




• * ? ] a S i J « t II II 17 1] U IS li IF II If n 71 11 n 1* lilt IJ Jl 7t H II 37 31 M I& li 31 31 31 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-6. Logic Diagram PAL20C1 



A-6 
10-7154037 {303A-0Q2) 



Increment Number 


Logic Diagram PAL10L8 


• 1 2 


J < s 


« T 


1 9 


10 11 1 


7 13 


K IS Wi 


7 11 IS 


[> 
















Une 

Number » _ _ 














r-^ 1 ^ tn 


' K 














8=L> 


> 














r— ^ %' "^. .a 

















B^O ^ 


> 
















100 















-W 3=0 - 


— 1> 
















b K-. 














^ — ^B=I> ^ 


— 1> 






■* ' 










rs 










" ■ - 




||=e=C> 


wo 














,r— >■- \ "N. i« 


330 














B-^_y- 


in 














U =B:i> ^ 


300 

- — h* 















y — =s4> ^ 


1 

• 11) 


OTE: Fus< 


■ I 

9 numi 


n 1 

Iter = 


ncrein 


ent Ni 


- 

jmber h 


g^~ l: 

1- Une Number 


Figure A-7. Logic Diagram PAL10 


IB 








10-71 


A-7 
&<XB7( 


30SA-Oa 


2) 





Logic Diagram PAL12L6 



t^ 



Increment Number . 



' ' • 5 6 7 I ) » 11 12 13 M 15 t« n ia IS 20 r S 23 



-^ 



Line 
Number 



^ 



fe 



^>: 



■t^ 



^ 



-tX 



' 1^ 



"T 



3f^ 




=B:iI> 



=e:0- 



=8=0 



3:0 




^ 



^ 



'2 M It u IT M ;3 » ;i £ n 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-8. Logic Diagram PAL12L6 



A-8 
1O-71&O037 OOQA-OOBI 



Logic Diagram PAL14L4 



^ 



Increment Number . 



»''3 «S(I 19 11111 1!1] UH Hlinn 101122= M !S » 27 



^ 



^ 



i:^ 



Line 
Number 



"t^ 



^ 



^ 



^-t^ 



^ 



^ 



^ 



^ 



^ 



'■') «S«7 ItlOll 1113 im !»?1?22) »»»!! nitjtjl 



3K^ 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-9. Logic Diagram PAL14L4 



A-9 
10-71&4037 (303A-CQ2) 



Increment Number^ 



' '' •>» »'•" l!lJm» IIIJUIS »!W!ZJ !12S!6!I ZIJSMJ. 



Logic Diagram PAL16L2 




" 1 ! J 4 St 7 ••■•11 I2l)lais ItWHIl 



a2U22] 2a;s»27 iinjiii 



NOTE: Fuse number = increment Number + Line Number 



Figure A- 10. Logic Diagram PAL16L2 



A-10 
10-71&«>37 (303A-002) 





1 

Line 
Numbe 

2 

3 
t 
6 

6 

7 

a 

9 

10 

11 


Incr 


ement Number . ^ 

J 4 S (7 


• 


II 


2 13 


4 K 


« 17 


Logic Diagram PAL12L10 

B 19 20 31 22 23 




-fe- 


















D — r">v_ ^ 






















-=b=I> 

D— T"N^ 21 




1^ 






96 . , 






130 




- 














-=B=i> 

D— r~N_ JO 




— te 






1M 






•^ 






- 












ii— H-J_^>° 

J~\ I-^ 19 




"~V^ 








IK 
















- 










--=B=1> 

D — r-N-^ '8 




~V^ 




















h^: 










■ 












-D^--- 






















K_ 






















— P^- - 




























-fcr~± 


















-=B=0 




\if. — 
















t>«: 


















-=B^> 

-1 — 0-T"*v. " 




-C^- 






















" — 1 












-tei" 


















3»i 13 


i 


■ 1 J J 


• 1 IT 

NOT 


l:FuM 


numbc 


tr = Inc 


M T 

rement 


NumftH 


n 

ir + Lir 


« jg ]i 1 

le Numb< 


f^ ^ 

I n 

»r 








F 


Igure A 


-11. Lofl 

10-71M 


icDiag 

A-11 

mnatm 


ram PA 
k-0Q2) 


L12L10 







Incrament Number 



Logic Diagram PAL14L8 



1?) < i * ) IS 



-u 



-i^. 



Line 
Number 



^X 



■i^ 



"U 



^ 



-fe 



^-i:^ 



i^ 



-U 



Wt: 



" " "15 « " 11 » » II a 23 » 35 je 27 



■T 



^d- 




e=o 



3:0 



s^>- 



e=I> 



s=o>- 



:B=E> 




^ 



3d- 



I 1 I 1 « 4 I I It 12 I] II w n 21 H n n n 32 u la n x » a >i 

NOTE: Fuse number = Increment Number + Line Number 



Figure A-12. Logic Diagram PAL14L8 

A-12 

10-71&«)37 OCQA-OE) 



Increment Number . 



0113 «S«T tiiai 



Logic Diagram PALI 61. 6 



H>: 



-t^- 



"{^ 



Line l^ 

Number ,a _ 



^ 



^ 



^-t^ 



^-t^ 



^ 



17 t] M 15 



■i^ 



-rs: 



w" «w 102122X1 Mas2az7 a: 



• ^ ' ' < I I 7 I ■ II II 11 tj H IT 



:^ 



:?^ 





St> 



©i> 





i:J- 



130- 



30- 



"" MX nimii a t>» a aitaji 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-13. Logic Diegram PAL16L6 



A-13 
10-71&OQ37 f30aA-002) 



Increment Number. 



Logic Diagram PAL18L4 



B I ' 3 » i t I I ) ID 11 I? 1] U lb <l n 



M5t 



Jh^~' 



M^ 



"-t^ 



Line R^ 



Number 



■^ 



P^ 



'-—t^ 



^ 



Msd 



Its 3Q2M2 13 HKXll SB30 3^ 3333MS 



• f>i 4»(T It-nil nniiw hit «i 



44 



:^ 



^ 







^ 



30- 



3:1 — ^ 



ittaiii MSMn aswr vnna 



NOTE: Fuse numbsr = increment Number + Line Number 



Figure A-14. Logic Diagram PAL18L4 



A-14 
1O-71&O037 (303A-0Q2) 



.ncrementNu^ber,^ ,^,,„ ^^, Lofl^c D'a9ram PAL20L2 

■ ' ' * ' ■ ' " " " " " » " " '• " » " " " i> nin, It n 10 ], „ 1, X n n i> u n 




• ' ' ■ < 1 « I I I II II i> 11 M IS H II II II n II 11 n M » H II n n > II u n n » ^ li 



NOTE: Fuse number = Increment Number + Line Number 



Figure A-15. Logic Diagram PAL20L2 



A-15 
10-71&a]37 (3CBA-002) 



Increment Number 



Logic Diagram PAL16L8 and PAL16L8/A/-2/-4 



Line 
Number 



"'!! «S>I ItltM IJUUll Itlltlll Itlizui J4«!6!I Itnitl 



-t:^ 



-t^ 



~t^ 



-tx 



-P^ 



-r:^ 



-t^ 



1)13 ' 

DM ■ 

tJJ» ■ 



'^tl <Si) I HDD I2I3MIS ICII1III »2I221] MKJII7 »»]01t 








NOTE: Fuse number = Increment Number + Line Number 
Figure A-16. Logic Diagram PAL16L8 and PAL16L8/A/-2/-4 



A-16 
10-71&0037 (303A-002) 



Logic Diagram PAL20L10 



^ Inc 


:rement 


Number .^.^^^^^ 




















Line > < 
Number „ 


; J < 5 


it 11 


IB tl 17 IJ 


la 15 i« *r 


II i» 78 ?i 


71 JJ H 2 


Jfc ?' a ?■ 


JB Jl 17 J 


M is Ik 11 


3i n 


1— ^ 




""Vk. « 






















l3>^i- 




^*- «. - 


































































1 


























<1 


















































S^V^ 






















' 




























3»1 




3 IS5 
















i 


i 






U«-- 










1 








i 






























^^=t-V-hK^ 




T 




















■■ 


21 




















^ 




r1 




* hs: — 
















1 i 

~H — ^ 








-U*-- 
















: i 






Kl 


























3»1 




















' ' 








SID 
















I 1 








b h5-4-- 




— 1 1— ^- 


^ 




4-^ — K 


-t— 1 j 


-1— ( 1— 1- 


— \ — U- 


1 : 
-4—1 — 1—1- 


'. i 

4— i 




t*-- 




1 1 




* 1 




1 

i 




1 1 


"i — H 




^ 


19 








, 










'■ 






S^ 












! 


! 










"* 




1 ! 


i ! 






' 




i ! 


1 




16 


1 

6 K5 1 


1 i 
4-i — h4- 


i ' 
— , »_f. 






'-! 1-- 


1 

"H 


1 




j 
i — 





u^ ^ 


--i — i__i_ 
j 


i i ! 




1 


rrt 






i \ 

if 1 ' 






^ 








1 




! 












<l-v-l^ 


■ 






1 
















■D 
















1 






— *i 


17 


' rs— 






-j 






^ 




1 






1;%--- 






-1 

j 










! 






— ^ 
























?d"v-i^ 


KBO 






1 






















I 
















z^ 


16 


' br- 


__j — 1 . 




I 




'■■ 1 


-,_ 1 1 




1 






l,^ — 

1 


— 1 


i 






i 


I 






-i 1-- 

! j 


1 


$J 


J i 




1 


j 


: 


1 






' 


] 




■<~t~^ Kn 










i 


1 


j 




[ 


1 






1 


1 












1 


I 




a»1 


15 . 

14 
13 


' hs-^- 


.J i 


1 ! 

1 1 ,i 


i 1 i 
i-i — i-i- 


4_J t.i..l,. Ut. 


1 : 




,_- — U- 


i; :; 


1 i 

i i 


\Ay-f-- 


t f 
i 1 


1 


1 


1 
1 


. 1 i 


i .; 




, i ' ^ ■ ' 


I 


f4 












! 


i 






I ; 




ji 














1 
































10 Kj--- 






— L- 








-4 — --i- 


1 , 


j 


■H 


l^ 




1 


1 






-H — h 


H i 1 


i 


1 f— H- 




«J 
























»^ 








































i 






11 f^ 
























J J * i 


% > 1 « 

NOTE 


■ II 1? 1] 
: Fuse 


i 

numbe 


II 11 n 11 

r « Inc 


i 

rement 


i 

K 11 M It 

Numb 


«^ 

It 11 n )i 

er + L 


ine Nun 


N N- 

nber 


^ 










Rt 


iure A- 


17. Log 

io-7i&a 


ic Diag 

A-17 
137(303/ 


ram P^ 

^■002) 


^L^LIO 


1 









L 



Increment Number 

H> ^ 

Line *^ 
Number 



Logic Diagram PAL16R8 and PAL16R8/A/-2/-4 



tsi; I mil !?i3uis 1(171119 ni\uii vnnit !i!!3ii3i 



'-^ 



'-^^ 



MX 



'-^ 



— pg- 



1376 



-^ 



'-Dr: 






J J 




^ 




-^ 




^ 




^ 




^ 




^ 




K 



^ 




^ 



:gC^ 



i^> 5 



'-> o 



{>o-^ 



^-> 5 



h 



^ 



5>-^' 



3>- 



I - > ^ 



■5>—^ 



L 



D O 
f> 5 



b>^^ 



■-^x^' 



•'23 « i f ? e S mi :2:3U1S ItWIttI 262122:3 241&2CI1 2t293fi31 

NOTE: Fuse number = Increment Number + Line Number 



•-«^' 



Figure A-18. Logic Diagram PAL16R8 and PAL16R8/A/-2/-4 



A-18 
1O-71&O037 (303A-002I 



Logic Diagram PAL16R6 and PAL16R6/A/-2/-4 



H>- 



Increment Number 



2v 



LJne 
Number 



'^ 



' ' •»1011 IJOUlb 1(171119 »J1?2!3 «25»JJ »!JMi, 



^-C:r 



'—be 



"->: 



i2ie 



^-fe: 






^-ts 



'-t*: 



H^ 



''' •*«' I mil iiuMii liiimi nnnii Mniiii nnait 




=^ 










D 



{i>c^' 



D Q 



'-> 



■!>- 



'-> 5 



^> o 



->c-^ 



■=^ 



■fl-H 

-p -| 



D Q 



■-> 5 



■] 



{>o-!^ 



■5>-^ 



NOTE: Fuse number = Increment Number + Une Number 



Rgure A-19. Logic Diegram PAL16R6 and PAL16R6/A/-2/-4 



A-19 
10-71&<xa7 (303A-aB) 



Une ^ 
Number 



Increment Number , 



Logic Diagram PAL16R4 and PAL16R4/A/-2/-4 



--te=.ft 



>' •'•" 'Jin«ii liiiiin ni\nn unnn jijsjosi 



H>r 



H:s: 



H>= 



H^ 



H^ 



'-^ 



IMS 



^— ^ 



:.'t 



nn 



T 






w 








D O 
> Q 



f^ 



'-> O -, 



7T1 p>o-!i 



D 
> Q 



-^^^ 



l-> O 



■^^ 



'■'' «»•) I (tilt iiiiuii iiiTiiii ittinn Mnit2) nnii-i\ 

NOTE; Fuse number = Increment Number + Line Number 



"^J 



Figure A-20. Logic Diagram PAL16R4 and PAL16R4/A/-2/-4 



A-20 
10-715-0037 (303A-002) 



Increment Number 



Logic Diagram PAL20X10 




' ' ■ ' « I • 1 I t H 11 It II a » H II H 11 M II n n n » it ii n'n » it u n x h ■nan 



NOTE: FuM number = Increment Number + Line Number 



Figure A-21. Logic Diagram PAL20X10 



A-21 
1O-71&O0S7 GBBMXa) 



Increment Number^ 



Line 
Number 



MJ- 



< < I } « i ( I (inn II 1] la M It I 



'—Csd.^' 



H^ 



Hx 



'-^ 



'~t^ 



"-PS 



*— C3B= 



II If » II 1 



M3S 



^H^ 



H^ 



T 



Logic Diagram PAL20X 8 




^^ 




:^ 



h 



.-> 5 



^ 




fS 





i-h3>-^ 



is^ 




'^^w 



^ 






-5>-^' 



■^^^J 



rff 



■^' 



ZB^ 



■5>-^' 



;3f 



^=^ 



33- 



■-f>o 



■ " » ' • • • I I I It II i> II u 11 It II n n a >i » II m k it » a a ■ ii n n a x a i a a 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-22. Logic Diagram PAL20X8 



A-22 
1&-71&0037 OOSA-Omi 



Logic Diagram PAL20X4 




' ' ' ' ' > ' ' • < n n II 11 » 11 H 11 II n M 11 n 11 M „ M „ n » » n » u >■ » x » a 



NOTE: Fuse number = Increment Number + Line Number 



Figure A-23. Logic Diagram PAL20X4 



A-23 

i(V7i»n37 (3oaA-oa2) 



Line ^^ 
Number 



Increment Number 



H> — T^> 



M>: 



f t£> 



dD- 



f^^ 



:£>- 



11*6- 




17 3 4 sb r I91DII tnitit^ mniis niiiuj ?«2s;ei} »i93(t3i 



-t-r 



4-iH i-i-t- 



'^:i> 



j~>- 



isaB ■ 
IS* ■ 

HOD ■ 



H>= 



1726 ■ 

I7K - 



^-Pr 



t:i 



in 



Logic Diagram PALI 6X4 




IE>^ 



*-> qI— I 





lE^ 



^>4E>-F 



D O 
f— 1> Q 



n 



>— > Q -1 



>-^ 



x>^ 



>^ 



{>>^ 




t12] «Str lllln 12l3t4i& I|tni19 21712213 242SH37 2I2I3I31 



L-<J^ 



NOTE: Fuss number = Increment Number + Line Number 



Figure A-24. Logic Diagram PAL16X4 



A-24 
10-715-0037 (303A-0Q2) 



Increment Number 



» iiiitiiTii iiu uiiHK niTiiia an 



Line 
Number 



Logic Diagram PAL16A4 



nn MBHI7 aa»ii 



M:^ 



M::^ 



Ifl^: 



in'r 



'^a>: 




=1i5f 




X^ 



t^ 



Hx 



H:r 



^Hr 



VA'r 



iSr 




iE>H 



'— > iS— I 





iT-^ 



g=>l 



tM 



-> a 




>E>^ 




»E>H 



{>o^ 



D O 



> B -I 



— 5>-^' 



D Q 



"-> 0-1 



>^ 



1121 «tt> 111(11 niiHii HiTiin Miiaa Mnni? naMii 




L<H 



NOTE: Fuse number = Increment Number + Line Number 



Rgure A-25. Logic Diagram PAL16A4 



A-25 
10-71&a)a7 (303A-0Q2) 



Logic Diagram PAL20L8A 



Increment Number 




• I 7 3 4 5 t I ■ I II II 17 13 14 li le IT It 19 «}i nn rtnnj^ ?b n 30 3i 37 33 ji 3b m 3t 38 3S 



NOTE: Fuse number = increment Number + Line Number 



Figure A-26. Logic Diagram PAI^LS 



A-26 
10-71&a)37 (303A-002) 



Logic Diagram PAL20R8A 



4> 



Increment Number. 



\ 



Line 
Number 






I ' 3 * i * J I 9 10 II 17 13 14 IS l( i; II 19 n 21 t2 n M JS B !J » R 30 3i 



•-^ 



■-w 



'-U 



TT 



-O- 



-fe 



'-Ds 



'-U 



■--t^ 






t-f- 



-I — * 



♦n: 



tr 



3? 3:< i« tt xvna 



^\ 




r^ 



^ 





t^ 



3^ 




3:^ 




30- 




5J 




^ 




S^ 



^ 



• ' ' ^ < 1 I ; ■ 1 10 M t? 13 M li II I- II 13 n ?> 7? ?3 »nn r nnxi^ 3? 33 m 3& 31 3? 3t 3S 



NOTE: Fuse number = Increment Number + Line Number 



Figure A-27. Logic Diagram PAL20R8 



rri — [>o-2 



Q 

6 



D 



D 
> 6 



-^ 




4-> Q 



D O 



D Q T^O-^" 



71 — [>^-i' 



a 



d 



o o 



D [><^^' 




d 



O 

> ci 




Q 



D Q 



D 




kH 



A-27 
10-71M037 WBA-OCC) 



,. Increment Number 

M> . \ 



Logic Diagram PAL20R6A 



Line 
IMumber 



'-m., 



> < z 1 « a ■ r I I 10 



\ 



*-■ 



"i^ 



tt 



^ 



-^ 



^ 



^ ^ \ •-~\—- 



'-U 



'-Ci 






n 7 13 MIS II 17 fill minn rt a jtv nnnn kumu uvmjt 



S f I a * i % 1 • t II II It i] I 



.. 




la Hirnii nnnn Nnn77 annsi S33UX ajijia 









NOTE: Fuse number = Increment Number + Line Number 



Rgure A-28. Logic Diagram PAL20R6 



D o — r^o-2; 



D O 
Q 



D 



D O 
6 






D Q — r^«>-^ 



D O T^O-a 



O 




U 



D a 

Q 



Q 



D Q 



D 




D T^o-^ 



-^JO— i3 



A-28 
10-71&a)37 (303A-002) 



Increment Number 

4> ^ 



Logic Diagram PAL20R4A 



7 iir aiaii n ii m ■ nima ansa xnan aaan 



aaaa asaa 



Una 
Number. 




• Ill till iiaii iriiMit ai?aa anna nnmr aa 



» aaaa avi 



L^ 



NOTE: Fuse number = Increment Number + Line Number 



Figure A-29. Logic Diagram PAL20R4 



A-29 

lO-TI&OB? OOSA-OQS!) 











Table A-1. LogicPak™ Family Codes and Pinout Codes 






DvTlce 




nnout LooicFoklV P/TAdapt*i DMlgn Adoptai 


D«TlC» 


Fssaiiy 


Haeu! LofficPas'*' P/TAaapt©i Dssica Adapter 


AdTonced Micro D«t1c«s 




DATA I/O Pent Numbeis 




Nationcil Semiconductoi 




DATA I/O Pfflt Numbeis 




AmPAL 16L8 


97 


17 


vol 


303A-004 


VOI 


303A-100 


vol 


PAL 10H8 


95 


IS 


VOl 


303A-Oa2 VOl 303A-100 


vol 


AmPAL 16R8 


97 


24 


vol 


303A-aO4 


VOI 


3a3A-100 


VOI 


PAL 12H6 


95 


19 


VOl 


303A-0D2 VOI 303A-100 


voi 


AmPAL 16R6 


97 


24 


V01 


303A-004 


VOI 


303A-100 


voi 


PAL 14H4 


9S 


20 


VOI 


XBA-aa VOI 303A-100 


V01 


AmPAL 16R4 


97 


24 


V01 


303A-004 


VOI 


303A-100 


vol 


PAL 16H2 


95 


22 


VOI 


3CI3A-0OZ VOI 3rnA-ioc 


vol 


AmPAL 16LD8 


97 


17 


vol 


303A-004 


VOI 


• 


• 


PALIOIB 


95 


13 


VOl 


303A-002 VOI 303A-100 


VOI 


AmPAL 16H8 


97 


2S 


vol 


303A-004 


vol 


• 


• 


PAL12L6 


95 


14 


VOl 


303A-002 VOl 303A-100 


vol 


AmPAL 16HD8 


97 


25 


vol 


303A-0O4 


VOI 


* 


« 


PAL 14L4 


95 


IS 


VOl 


303A-002 VOI 303A-100 


vol 


Hauls Semiconductoi 






DATA I/O Ponl Nu3nb«» 




PAL16L2 
PAL16R4 


95 


16 
24 


VOI 

VOI 


303A-002 VOI 303A-100 
303A-002 VOI 303A-100 


vol 
voi 


HPL77163/CS1B3 


SB 


04 


vol 


303A-003 


voi 


30SA-1O1 


V01 


PAL16R6 


95 


24 


vol 


303A-002 VOI 303A-100 


VOI 


HPL//;«J«/16LB 


96 


01 


vol 


303A-003 


VOI 


3O3A-100 


vol 


PAL16L8 


95 


17 


VOl 


303A-O02 VOI *nA-100 


voi 


HPL77210/16R4 


98 


02 


vol 


303A.003 


VOI 


303A-100 


vol 


PAL 16R8 


95 


24 


vol 


3a3A-002 VOI snsA-ioo 


VOl 


HPL77211/16fi6 


98 


02 


vol 


3O3A-O03 


VOI 


303A-100 


vol 


PAL 16C1 


95 


21 


VOI 


303A-002 VOI 303A-100 


VOI 


HPL77212/16R8 


98 


02 


vol 


303A-003 


VOI 


303A-100 


vol 


PAL20L10 


95 


06 


vol 


303A-002 VOI 303A-100 


vol 


HPL77215/16H8 


98 


01 


vol 


303A-003 


VOI 




• 


PAL 20X10 


95 


23 


VOI 


303A-002 VOI 303A100 


VOI 


HPL77216/16P8 


98 


03 


vol 


303A-003 


VOI 


• 


* 


PAL 20X8 
PAL 20X4 


95 
95 


23 

23 


VOI 
VOl 


303A-002 V01 3mA-100 
303A-002 VOI 303A-100 


voi 
vol 


Monolithic Memoiies 






DATA I/O Pent Niiinheis 
































Signetics 








DATA I/O Part Numbers 




PAL)0H8 


22 


18 


V01 


303A-OQ2 


V02 


303A-100 


vol 














PAL 12H6 


22 


19 


vol 


3n3A-002 


V02 


3(aA-100 


VOI 


FPLA82S101/100 


96 


01 


VOI 


303A-001 VOI 303A-101 


VOI 


PAL 14H4 


22 


20 


vol 


3aTA-002 


V02 


303A-100 


VOI 


FPLS82S104/105 


96 


03 


VOI 


3Q3A-001 VOI 303A-101 


vol 


PAL 16H2 


22 


22 


vol 


303A-O02 


V02 


303A-100 


VOI 


FPRP82S106/107 


96 


04 


vol 


303A-001 VOI 303A-101 


vol 


PAL10L8 


22 


13 


vol 


303A-O02 


V02 


303A-lb0 


VOI 


FPGA 825102/103 


96 


02 


VOI 


303A-001 VOI 303A-101 


VOl 


PAL 12L6 


22 


14 


vol 


303A-002 


V02 


303A-100 


vol 


FPLA82S1S2/153 


96 


06 


vol 


303A-001 VOl 303A-101 


voi 


PAL 14L4 


ZZ 


15 


vol 


303A-002 


V02 


303A-100 


VOI 


FPLS82S1SB/159 


• 


• 


* 


• • • 


• 


PAL16L2 
PAL 16A4 


22 
22 


16 
24 


V01 
V01 


303A-002 
303A-002 


V02 
V02 


303A-100 
303A-100 


VOI 
VOI 


Texas Instiumenis 






DATA I/O Part Numbers 




PAL 16X4 


22 


24 


vol 


xfiA-aa 


V02 


303A-100 


VOI 


PAL 16LB 


96 


17 


VOl 


303A-006 VOl 3mA-100 


voi 


PAL16R4/1W4A 


22 


24 


voi 


303A-a02 


V02 


3O3A-1O0 


vol 


PAL 16R4 


99 


24 


VOl 


303A-0a6 vol 303A-1X 


vol 


PAL 16R6/16R6A 


22 


24 


vol 


303A-002 


V02 


303A-100 


VOI 


PAL 16R6 


98 


24 


vol 


303A-006 voi 303A-100 


voi 


PAL16L8/1f)18A 


22 


17 


vol 


303A-0Q2 


V02 


303A-100 


voi 


PAL 16R8 


99 


24 


VOl 


303A-006 voi 303A-100 


voi 


PAL16R8/16R8A 


22 


24 


vol 


303A-002 


V02 


303A-100 


vol 


FPLS74FP33S/333 


• 


• 


« 


• ■ « 




PAL 16C1 


22 


21 


voi 


303A-0Ce 


V02 


303A-100 


VDl 


FPLA74FP840/839 


• 


« 


. 


* • • 


• 


PAL 12H10 


22 


07 


vol 


303A-O02 


V02 


303A-100 


VOI 














PAL14H8 


22 


08 


voi 


303A-002 


V02 


303A-1O0 


VOI 














PAL16H6 


22 


09 


VOI 


303A-0Q2 


V02 


303A-100 


V^l 














PAL18H4 


22 


10 


voi 


303A-002 


V02 


303A-100 


VOI 














PAL20H2 


22 


11 


VOI 


303A-002 


V02 


303A-100 


VOI 














PAL 12L10 


22 


01 


VOI 


3O3A-002 


V02 


303A100 


VOI 














PAL14L8 


22 


02 


VOI 


303A-002 


V02 


303A-100 


VOI 














PAL 16L6 


22 


03 


VOI 


303A-002 


V02 


303A-100 


VOI 














PAL 18L4 


22 


04 


VOI 


303A-002 


V02 


303A-1K 


VOI 














f,'-- -OLi 


■Zi 


0& 


VOl 


303A-OQ2 


V02 


303A-100 


VOI 














PALaOCl 


22 


12 


VOI 


303A-002 


V02 


303A-1M 


VOI 














PAL20L10 


22 


06 


vol 


303A-002 


V02 


303A-ia0 


vol 














PAL 20X10 


22 


23 


VOI 


303A-002 


V02 


303A-100 


VOI 














PAL 20X8 


22 


23 


VOI 


303A-002 


V02 


aosA-ioo 


voi 














PAL 20X4 


22 


23 


vol 


303A-OQ2 


V02 


303A-100 


VOl 














PAL20L8 


22 


26 


vol 


303A-002 


V02 


3a3A-ioa 


vol 














PAL20R8 


22 


27 


vol 


303A-0Q2 


V02 


303A-100 


VOl 














PAL20R6 


22 


27 


voi 


303A-OQ2 


V02 


303A-n» 


vol 














PAL20R4 


22 


27 


VOI 


303A-Oa2 


V02 


X3A-100 


VOl 














• under development 



























A-30 
10-71&O037 {303A-O02) 



APPENDIX B 

SCHEMATICS 

30-702-1947 Programming/Testing Adapter 



B-1 
10-71&ai37 (303A-0Q2) 



vcc 
:nse 



BIT SW 1 



<1H 



Q1 



VCC PULLUP 2.2K 




CR6 



R7 

I /SA/*— I 

300 I 

1/2W ^ 



K 



2N2a0 7A _%_1_ 



26 SINK ^^ 

26 SOURCE ^^^ 

27 <7?)^ 




+5 



( 



JRH 

iqlioo , 

V^l/2W^ 



I/O 



CR13 



B 



^ 



11. 



+ s 



C 



SEL A 



SEL B 



^ 



ff 



-L 24l23l22l2<2cliallBll7ll6lldl^ 



Ts 



li 



5 6 



1/2/ 3/4/* V* 



6/7/8/-' 



91C 11 



^ 



Ik: 



20 19 



18 



T7 



J6 



M 



ja 



XU1 

20 PIN ZIF 



FIRMWARE *' 



1/2/ 



6 



^^s/6. 



8 9 



7/a^v 



10 



a 



Z7 



DATA GATE 



VPP P6M 



4»6 2764 

*7 80O079fEF 



11 


6 


12 


4 


13 


2 


B 


11 


l« 


13 


17 


15 


18 


17 


19 


9 



221 



CRI^ 



CR2' 



12/ 



12/J 



1\ 



t: 



3\ 4^1 sS 6^1 



A 



eS 



^A% (^ ^ % % % % % 




LTR 



B 



DESCRIPTION 



RELEASE 



ECN -^feS* 



ECN 4786 



OR CHK APPRO DATE 



JK 



^ 



BV 



/^ '-^ 



i/ii 11 






A ^ ^N ■*^ ^^ ^^ 'Ii ^^ ^1 ^'^ 

U2 ^" " "1 ~ ~ Tl IfRfi Ml XjI lb -k'"' 

L'> J_Lij * L * -iJ— *J ' 

— • <>14 x/ni TAriF <;PIKF CLAV 



VOLTAGE SPIKE CLAMPS(BIT) 



:ci 






2 3 5 



CS C9 



V ^i 



8 9 11 12 



C14C1S 



I7 



100PF/100W 
(.11 PLACES) 



i I I CR8 CR9 CRIO CRII 

!_.;_ 1 J_if_ j_l__i Jjl 1 1 I 
14' wni TARF «;pikFri AMP5;(rF 



CR4 



CR3 



VOLTAGE SPIKE CLAMPSCCE) 



NOTES: UNLESS OTHERWISE SPECIFIED 

I >■ I orroie-rnDC HOC HAW Akin IN nHMS.&%. 

1. MI_L. r\t.»3»*»iv»i»«# r^iik- ■»-.■« «..^ ••- — -I - - 

2. ALL CAPACITORS ARE IN MICROFARADS, .1.50V. 

3. LAST REFERENCE DESIGNATOR USED^ 

U6.R11 .DS2.CR13.C21.P4,«9S. 

4. ALL DIODES 1N4 146 



S. POWER a eROUHO. 



J4 



REFDES 


+5 


6ND 


XU4 


- 


12 


XU1 


- 


10 


US 


20 


10 


xu« 


26^8 


14 



-© 



<!> 



+5 



C4,19,21 _L 
-01 




CE SUPPLY 
BIT SUPPLY 



+ 5. 



< <» > REFER TO ASSY DWG. AND PARTS LIST FOR 

PARTS MOT INSTALLED FOR -002 CONFIGURATION 




GND 



iV?' 



y^) INTERLOCK 



< < <<<<<<<<< << 



IG 



10 



^ © <^ <g>J4 

o 0000000 

Q QQOQQQQ 



APPROVALS: 



DSN €«IGR 



MFC FNGg 



OUAl ASSUB 



ENGR MGR 






M 



UNLESS OTHEHWISE 
SPECIFIED DIMENSIONS 
ARE IN INCHES 



lANCfS UNIESS 
OIHf*^SF SPECIHtr 



ANGU! &R 



nnAvwN fiv 

.•AEHEE Klk' 



CHECKED e* 



-/,? 



DMA I/O 



TiTiE SCHEMATIC DIAGRAM. 
TEST PROG ADAPTER 
SERIES 20/24 



SCALE XQNE [ 



DRAWING NO 



30-702-1947