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IEEE 696 / S-100 

8 CHANNEL SERIAL I/O BOARD 
RS232 • with full handshake 



J74C ) (orapuPro 

mac ^^^^^■■■^^^^^^■^^^^^^^^^ 



a GODBOUT company 



4/82 
*11743 



TABLE OF CONTENTS 

About Interfacer 3 3 

Technical overview .... 3 

Fort map 4 

Port addressing 4 

User/board selection 5 

Wait state selection 6 

Cables 6 

Slave clear /power-on-clear option 7 

Using interrupts 8 

Channel 6/7 interrupt option 8 

Interrupt control registers 9 

Interrupt status registers 9 

USART initialization 10 

Data registers 11 

Status register 11 

Mode registers 12 

Command register 13 

Serial mode jumpers 13 

RS-232 control lines 14 

Synchronous mode clock driver/receivers 14-15 

Theory of operation 16 

S-100 Bus drivers 16 

I/O port decode logic 16 

Strobe generation logic 17 

Wait state logic 17 

Interrupt control/status logic 17 

USARTs 18 

RS-232 level conversion logic 18 

User notes 19 

Sample test programs 

Asynchronous mode 20-21 

Synchronous mode 22-23 

CP/M console 24-25 

INS2651 Programmable Communications Interface . . 26-31 

Logic diagram 32-33 

USARTs 0-7 (detail) 34-37 

Parts list 38 

Component layout 39 

Customer service/limited warranty information ... 40 

DISCLAIMER 

Godbout Electronics makes no representations or warranties 
with respect to the contents hereof and specifically 
disclaims any implied warranties of merchantability or 
fitness for any particular purpose. Further, Godbout 
Electronics reserves the right to revise this publication 
and to make any changes from time to time in the content 
hereof without obligation of Godbout Electronics to notify 
any person of such revision or changes. 

This document was proofread with the aid of SpellGuard™ 
from ISA, Menlo Park, CA. 



ABOUT INTERFACER 3 

Congratulations on your decision to purchase the INTERFACER 3 multi- 
user serial I/O board. INTERFACER 3 has been designed to be the most 
flexible and highest performance multi-user serial I/O interface available 
that fully complies with the IEEE 696/S-100 bus standard. Due to its 
provision for ready expansion and modification as the state of the compu- 
ting art improves, the S-100 bus is the professional level choice for 
commercial, industrial, and scientific applications. We believe that this 
board along with the rest of the S-100 portion of the CompuPro family, is 
one of the best boards available for that bus. 

The INTERFACER 3 boasts several innovative features not found on 
currently available multi-user I/O boards. These features include 8 fully 
programmable asynchronous serial channels, 2 of which are capable of high 
speed synchronous transmission, five RS-232 handshaking lines per channel 
plus bi-directional clock drivers on both the synchronous channels, expan- 
dability to 32 users with four boards using only 8 port addresses, a 
flexible interrupt structure with full maskability and pending status on 
both transmit and receive interrupts, and conservative design for 
operation with most CPUs operating at up to 10 MHz. Other features 
standard to all CompuPro boards include thorough bypassing of all supply 
lines to suppress transients, on-board regulators, and low power Schottky 
TTL and MOS technology integrated circuits for reliable, cool operation. 
All this and sockets for all IC's go onto a double sided, solder masked 
printed circuit board with a complete component legend. 



TECHNICAL OVERVIEW 

The INTERFACER 3 was designed primarily for operation in interrupt 
driven/ multi-user microcomputer systems. Sixteen distinct interrupts are 
generated on-board by the eight USARTs, and these are brought out for 
jumpering by the user to the eight vectored interrupt lines on the S-100 
bus. Since these interrupt lines are open collector, they may be 
configured to interrupt on any or all of the vectored interrupt lines. In 
addition, a transmit and receive interrupt mask port is provided for 
inhibiting unwanted interrupts. 

The INTERFACER 3 provides multi-user operation with a minimum number 
of I/O ports by incorporating a user select register to activate the 
required serial channel. The five bit register is used to select a parti- 
cular serial channel, which allows up to 32 users (four boards) on the 
same 8 port addresses. When a particular user is selected, the four USART 
registers associated with that specific serial channel are made available 
for examination and alteration by the host processor or other temporary 
bus master. In addition, whenever a particular channel is selected, the 
interrupt registers on that particular board are available for examination 
and alteration. 

The typical sequence of operation would require all channels on the 
INTERFACER 3 to be mode initialized and the interrupt mask registers set 
for operation. All parameters of the USART may be altered by selecting 
that particular channel and writing a new set of mode and command words to 
the proper registers. If running in a non-interrupt environment, the 



interrupt status registers may be polled and checked in roughly the same 
manner as a standard single channel serial board. 

Six of the serial channels on the INTERFACES. 3 are designed for direct 
connection to DATA TERMINAL EQUIPMENT (DTE) in asynchronous mode without 
alteration of the cables. This allows direct connection to CRT terminals 
and printers. The remaining two channels may be connected in either DTE 
mode or DATA COMMUNICATION EQUIPMENT (DCE) mode. This allows direct 
connection to all types of RS-232 equipment including modems. In addi- 
tion, these two channels are capable of high speed synchronous operation 
using internal or external clocks. 



PORT MAP 

The INTERFACER 3 interface uses a block of eight port addresses for 
communication between it and the host processor. The address of the first 
port is switch selectable to any address which is a multiple of eight. The 
ports will be referred to as relative ports 0-7. 



RELATIVE PORT 



FUNCTION 



USART Data Register (R/W) 

USART Status Register (R) 
SYN1/SYN2/DLE Register (W) 

USART Mode Register (R/W) 

USART Command Register (R/W) 

Transmit Interrupt Status Register 
Transmit Interrupt Mask Register 

Receive Interrupt Status Register 
Receive Interrupt Mask Register 



(R) 
(W) 

(R) 
(W) 



Not used 



User Select Register (write only) 



PORT ADDRESSING 

DIP switch SI, positions 1 thru 6 are used to select the base address 
of the eight port block in a binary fashion as shown below: 



SWITCH POSITION 



ADDRESS BIT 



1 . . . . PORT DISABLE WHEN "ON" 

2 A7 

3 A6 "ON" = "0" 

4 A5 "OFF" = "1" 

5 A4 

6 A3 



EXAMPLE: To address this board at addresses 10H thru 17H for the CompuPro- 
/Phase 1 OASIS operating system, position 1 and 5 would be "OFF" and 
positions 2 thru 4 and positions 6 would be "ON". 

EXAMPLE: To address this board at addresses 38H thru 3FH, positions 1, 4, 
5, and 6 would be "OFF" and positions 2 and 3 would be "ON". 



USER/BOARD SELECTION 

To select a particular channel and to select which board that channel 
will be on (when running more that 8 users), requires the use of the User 
Select Port and two board select switches. The five bit User Select 
Register determines which of 32 possible users will be selected at a 
particular time. The two board select switches determine whether a board 
will respond to users thru 7, 8 thru 15, 16 thru 23, and 24 thru 31. A 
particular user (0-31) is selected by outputting the five bit number that 
represents that user. The diagram shown below will describe the relation 
between the board select switches and the User Select Register. 



USER SELECT REGISTER 



'A BIT 


NAME 


FUNCTION 




DO 


USO 


USER SELECT 


(LSB) 


Dl 


US1 


USER SELECT 1 




D2 


US2 


USER SELECT 2 


(MSB) 


D3 


BSO 


BOARD SELECT 


(LSB) 


D4 


BS1 


BOARD SELECT 1 


(MSB) 


D5 




NOT USED 




D6 




NOT USED 




D7 




NOT USED 





Since each INT ERF ACER 3 will support 8 users, we will refer to these 8 
as RELATIVE USER 0-7. These 8 ports are physically configured with rela- 
tive user on the extreme right side of the board and relative user 7 on 
the extreme left side. To determine the exact user number, the RELATIVE 
USER number must be added to the USER OFFSET number. The RELATIVE USER 
number corresponds to the 3 bits above called USER SELECT 0-2, and the 
USER OFFSET number corresponds to the 2 bits above called BOARD SELECT 
and 1. These 5 bits determine the exact user number. 



US2 US1 USO 


















1 





1 








1 


1 


1 








1 





1 


1 


1 





1 


1 


1 



USER NUMBER 


USER 





USER 


1 


USER 


2 


USER 


3 


USER 


4 


USER 


5 


USER 


6 


USER 


7 



BOARD 


BOARD 


USER 


SELECT 


SWITCHES 


SELECT 


BITS 


OFFSET 


Sl-8 


Sl-7 


BS1 


BSO 




ON 


ON 











ON 


OFF 





1 


8 


OFF 


ON 


1 





16 


OFF 


OFF 


1 


1 


24 



EXAMPLE: To address the INTERFACER 3 to respond to users thru 7, 
switches Sl-7 and Sl-8 would be "ON". To select a particular user in the 
group from to 7, BS1 and BSO must be "0" for the board to respond. To 
select user 5, a 05H must be sent to the user select port. 

EXAMPLE: To address the INTERFACER 3 to respond to users 16 thru 23, 
switch Sl-7 would be "ON", and switch Sl-8 would be "OFF". To select a 
particular user in the group from 16 to 23, BS1 must be a "1" and BSO must 
be "0" for the board to respond. To select user 18, a 12H must be sent to 
the user select port. 



WAIT STATE SELECTION 

The INTERFACER 3 was designed to run in very fast microcomputer 
systems by allowing up to two wait states to be added when accessing the 
USART registers. Since the user select and interrupt control registers 
are capable of higher speed operation than the USART registers, no wait 
states are inserted even when they are enabled on the board. 

The 3 vertical pins at J17 control the enabling of one or two wait 
states. With the black pin shunt connecting pins "A" and "C", one wait 
state will be inserted. With the pin shunt connecting pins "B" and "C", 
two wait states will be inserted. If the pin shunt is left removed, no 
wait states will be inserted. 



CABLES 

The INTERFACER 3 is designed to use two each of 2 different cables 
assemblies. Relative users 0-5 use a custom 50 conductor cable and 
relative users 6 and 7 use standard 26 conductor cables identical to those 
used on the INTERFACER 1 and INTERFACER 2. 



Relative users 0-2 (50 pin connector on the far right) and relative 
users 3-5 (50 pin connector in middle of board) use a custom 3 user cable 
(see photo A page 7). This cable consists of a female 50 pin insulation 
displacement connector that splits into thirds and connects to three 
female DB-25 connectors. The actual cable has positions 1-16 (pin 1 on the 
far left side of the connector) on the first DB-25, positions 17-32 on the 
second DB-25, and positions 33-50 on the third DB-25. NOTE: The pin 
numbers on the circuit diagram show the pin numbers on the DB-25 connector 
and not the 50 pin connector. 

Relative user 7 (26 pin connector on the far left) and relative user 6 
(26 pin connector to the right of user 7) use standard RS-232 I/O cables 



(see photo B below). This cable consists of a female 26 pin insulation 
displacement connector that mates to a female DB-25 (the 26th conductor is 
not used). NOTE: The pin numbers on the circuit diagram show the pin 
numbers on the DB-25 connector and not the 26 pin connector. 



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4 *s««w»w«*«S8iA * 



\ 



*********** y 



B 





SLAVE CLEAR/POWER-ON-CLEAR OPTION 



The INTERFACER 3 is designed to be cleared by either pRESET* or 
SLAVECLR*. In some older non-IEEE 696 processor boards, POC* does not 
generate SLAVECLR* and pRESET*. On these systems this board might not be 
cleared upon power-up. By cutting the trace at J18 between "B" and "C", 
and installing a jumper between holes "A" and "C", this board will be 
cleared by POC* instead of SLAVECLR*. 



USING INTERRUPTS 

The INTERFACER 3 has a simple but elegant interrupt structure that 
allows considerable flexibility. Each USART generates both a transmit and 
receive interrupt, for a total of 16 distinct interrupts for the board. A 
transmit interrupt indicates that the USART transmit register is empty and 
it is ready to accept a character. A receive interrupt indicates that 
data is available from the receiver data register. Each of these inter- 
rupts may be masked "OFF" or "ON" by altering the INTERRUPT CONTROL 
REGISTERS as described below. Each of these interrupts are open 
collector, and may be individually tied to any of the 8 vectored interrupt 
lines (VI0-VI7). The status of each interrupt line may be sampled by 
reading the INTERRUPT STATUS REGISTERS as described below. 

Since each of the 16 interrupts generated on the INTERFACER 3 may be 
tied to any of the 8 vectored lines, almost any type of priority scheme 
may implemented. All transmit interrupts are brought out on one side of 
jumper socket J15, and all receive interrupts are brought out on one side 
of jumper socket J16. On the opposite side of each socket, each of the 8 
vectored interrupt lines are brought out. By using the provided headers, 
any USART interrupt may be connected to any VI line. The pin-out of J15 
and J16 are shown below. 



INTERRUPT 



J15 



VI LINE 



J16 



INTERRUPT 



TxINT 
TxINT 1 
TxINT 2 
TxINT 3 
TxINT 4 
TxINT 5 
TxINT 6 
TxINT 7 



19 


8| 


1 10 


7| 


111 


6| 


1 12 


5| 


1 13 


4| 


1 14 


3| 


1 15 


2| 


1 16 


1| 



VI 
VII 
VI 2 
VI 3 
VI 4 
VI 5 
VI 6 
VI 7 



19 


81 


1 10 


7| 


111 


6| 


1 12 


5| 


113 


A| 


|14 


3| 


1 15 


2| 


1 16 


1| 



RxINT 
RxINT 1 
RxINT 2 
RxINT 3 
RxINT 4 
RxINT 5 
RxINT 6 
RxINT 7 



EXAMPLE: If we wish to generate an interrupt on vectored interrupt line 
VI3 when data becomes available from relative user 6, a wire should be 
soldered between pins 2 and 12 of J16. 

EXAMPLE: If we wish to generate an interrupt on vectored interrupt line 
VI6 when data becomes available from relative users 0, 1, 2, and 7, a wire 
should be soldered to connect pins 1, 6, 7, 8 and 15 of J16. 

EXAMPLE: If we wish to generate an interrupt on vectored interrupt line 
VIO when relative user 2 is ready to accept a character, a wire should be 
soldered to connect pins 8 and 11 of J15. 



CHANNEL 6/7 INTERRUPT OPTION 

Relative channels 6 and 7 are capable of generating a third interrupt 
called TxEMT/DSCHG*. This interrupt occurs when the transmitter has 
completed serialization of the last character loaded or a change has 
occured in the state of the DSR or DCD RS-232 status lines. Additional 
information on this line may be found in the 2651 data sheet in this 
manual . 



8 



The TxEMT/DSCHG* output from the 2651 may be jumpered to generate 
either a transmit or receive interrupt. Due to the wire-OR capability of 
the interrupt outputs from the 2651, when jumpered, the transmit interrupt 
will become TxRDY OR TxEMT/DSCHG or the receive interrupt will become 
RxRDY OR TxRDY/DSCHG. Therefore, when jumpered, the user must check the 
status register to determine what condition caused the interrupt. 

The following table will demonstrate where to install the shorting 
plug to generate the appropriate interrupt. 



CHANNEL TO CAUSE A TxEMT/DSCHG INTERRUPT ON THE: 
NUMBER TxRDY LINE RxRDY LINE 

6 INSTALL J14 INSTALL J13 

7 INSTALL J4 INSTALL J3 



INTERRUPT CONTROL REGISTERS 

Two registers are provided for individually masking the transmit and 
receive interrupts from the bus. On power-up or reset, all interrupts are 
disabled on the INTERFACER 3. To gain access to these registers, a user 
channel must be enabled on the particular board to be altered. (You 
cannot alter any interrupt register on the board set for users thru 7 
unless you have selected one of those 8 users) To enable a particular 
Transmit or Receive interrupt, a "1" must be sent to the proper bit of the 
register. The registers are configured so that Data Bit will mask 
relative user 0, Dl will mask relative user 1, and so on with D7 masking 
relative user 7. This is true for both the Transmit Interrupt Control 
Register (relative port 4) and the Receive Interrupt Control Register 
(relative port 5). 

EXAMPLE: To enable all Transmit interrupts on a particular INTERFACER 3, 
you should send a OFFH to relative port 4. 

EXAMPLE: To enable the transmit interrupt on relative users 1, 4 and 6, 
you should send a 52H to relative port 4. 

EXAMPLE: To disable all Receive interrupts on a particular INTERFACER 3, 
you should send a 00H to relative port 5. 

EXAMPLE: To enable the Receive interrupt on relative users 2, 3 and 7, 
you should send a 8CH to relative port 5. 



INTERRUPT STATUS REGISTERS 

Two registers are provided for checking the status of pending transmit 
and receive interrupts. To gain access to these registers, a user channel 
must be enabled on the particular board to be altered. (You cannot read 
any interrupt register on the board set for users thru 7 unless you have 
selected one of those 8 users) If a Transmit or Receive interrupt is 
pending, a "1" will be present in the proper bit of the status register. 



The registers are configured so that Data Bit contains the status of 
relative user 0, Dl contains the status of relative user 1, and so on with 
D7 containing the status of relative user 7. This is true for both the 
Transmit Interrupt Status Register (relative port 4) and the Receive 
Interrupt Status Register (relative port 5). Remember, these status 
registers are read only! Writing into these registers will alter the 
Interrupt Control Mask. In addition, the status of a channel's interrupts 
are available even if those interrupts are masked "OFF". The Interrupt 
Control Register does not affect the reading of the status from a 
register. 

EXAMPLE: If all Transmit interrupts on a particular INTERFACER 3 are 
asserted, you will read a OFFH at relative port 4. 

EXAMPLE: If transmit interrupts are pending on relative users 1, 4 and 6, 
you will read a 52H from relative port 4. 

EXAMPLE: If there are no Receive interrupts pending on a particular INTER- 
FACER 3 (no data available), you will read a 00H from relative port 5. 

EXAMPLE: If Receive interrupts are pending on relative users 2, 3 and 7, 
you will read a 8CH from relative port 5. 



USART INITIALIZATION 

The serial channels on the INTERFACER 3 are implemented with a 2651 
type USART from either National Semiconductor or Signetics. Several of 
the USART parameters and channel control functions are programmed by 
writing into or reading from certain registers in the 2651. They are: 

1. The baud rate. 

2. The word length. 

3. Whether or not a parity bit is generated. 

4. Whether the parity is even or odd (if generated). 

5. The number of stop bits. 

6. Enabling and disabling the transmitter and receiver. 

7. Setting and testing the RS-232 handshake lines. 

8. Synchronous or asynchronous operation. 

In addition, the normal status indication and data transfer functions 
are also handled through the USART's registers. 

A table of the various registers and where they appear in the I/O port 
map is shown in a previous section and in the following tables. 



"READ" or "INPUT" Ports 

Relative Port Address UART Register Function 

00 hex Data Port, read received data. 

01 hex Status Port, read UART status info. 

02 hex Mode Registers, read current UART mode. 

03 hex Command Register, read current command. 



10 



'•WRITE" or "OUTPUT" Ports 

Relative Port Address UART Register Function 

00 hex Data port, write transmit data. 

01 hex SYN1/SYN2/DLE register, write sync bytes. 

02 hex Mode registers, write mode bytes. 

03 hex Command register, write command byte. 

USART INITIALIZATION SEQUENCE 

When bringing up the USART in asynchronous mode, the following 
sequence of events must occur: 

1. Set Mode Register 1 

2. Set Mode Register 2 

3. Set Command Register 

4. Begin normal USART operation 



When bringing up the USART in transparent synchronous mode, all of the 
following sequence of events must occur. If bringing up the USART in non- 
transparent synchronous mode, step 5 may be omitted. 

1. Set Mode Register 1 

2. Set Mode Register 2 

3. Set SYN1 Register 

4. Set SYN2 Register 

5. Set DLE Register 

6. Set Command Register 

7. Begin normal USART operation 



DATA REGISTERS 

The UART data registers are straight-forward in their operation. You 
write a byte to the data register when you want to transmit that byte to 
an external serial device and you read the byte in the data register to 
receive a byte from an external serial device. The UART will automatically 
add the proper start and stop bits when transmitting and will remove them 
when receiving. 



STATUS REGISTER 

The status register is used to determine the current state of the 
UART. Each bit of the status register has a different meaning depending on 
whether it is high or low. (High means a logic one or high level and low 
means a logic zero or low level.) The following table describes the 
meaning of the status bits: 



11 









STATUS REGISTER FORMAT 

BIT NUMBERS 








SR-7 


SR-6 


SR-S 


SR-4 


SR-3 


SR-2 


SR-1 


SR-0 



DATA SET 
READY 

0-D5H INPUT 
IS HIGH 

1-B5B INPUT 
IS LOW 



DATA CARRIER 
DETECT 

0-DCD INPUT 
IS HIGH 

1 = DCO INPUT 
IS LOW 



FE/SYN DETECT OVERRUN 

ASYN: 0-= NORMAL 

0- NORMAL 1= OVERRUN 

1- FRAMING ERROR ERR OR 
SYNC: 
0- NORMAL 
1 - SYN CHARACTER 
OETECTEO 



NOTE 1: BAUD RATE FACTOR IN ASYNCHRONOUS MODE APPLIES ONLY IF 
EXTERNAL CLOCK IS SELECTED. FACTOR IS 16x IF INTERNAL 
CLOCK IS SELECTED. 



PE/DLEOETECT 
ASYNC: 

= NORMAL 

1 = PARITY ERROR 
SYNC: 

D- NORMAL 

1- PARITY ERROR 
OR OLE 
CHARACTER 
RECEIVED 



T«EMT/DSCHG 
0- NORMAL 



1- CHANGE IN 
DSR OR DTD, OR 
TRANSMIT SHIFT 
REGISTER IS 1 - RECEIVE 



RxRDY 

0* RECEIVE 
HOLDING 
REGISTER 
EMPTY 



EMPTY 



HOLOING 
REGISTER 
HAS DATA 



TxROY 

0* TRANSMIT 
HOLOING 
REGISTER 
BUSY 

t * TRANSMIT 
HOLDING 
REGISTER 
EMPTY 



MODE REGISTERS 

When bringing up the UART, its two mode registers must be set with 
various bit patterns that will determine the operating modes. There are 
two registers, however they occupy only one I/O port address. This is 
accomplished with internal sequencing logic that allows you to write the 
first register (Mode Register 1) and then the second register (Mode 
Register 2). It is important to write to Mode Register 1 first. 

The meanings of the various bits in the mode registers are described 
below: 



MODE REGISTER 1 FORMAT 
BIT NUMBERS 



MR1-7 


MR1-6 


MR1-5 


MR 1-4 


MR1-3 


MR1-Z 


MR1-1 


MR1-0 



SYNC: 



SYNC: PARITY TYPE 

TRANSPARENCY 0-ODD 

CONTROL 1-EVEN 

0- DOUBLE SYN 0« NORMAL 

I- SINGLE SYN 1 ■ TRANSPARENT 



NO. OF SYN 
CHARACTERS 



PARITY CONTROL 
0« DISABLED 
1- ENABLED 



CHARACTER LENGTH 
00 -5 BITS 
Ot • 6 BITS 
10 -7 BITS 
11 -8 BITS 



ASYNC: 

STOP BIT LENGTH 
00 'INVALID 
01 * 1 STOP BIT 
10-154 STOP BITS 
11 = 2 STOP BITS 



MODE AND BAUD RATE FACTOR 1 
00- SYNCHRONOUS 1x RATE 
01 - ASYNCHRONOUS 1x RATE 
10- ASYNCHRONOUS 16x RATE 
11 • ASYNCHRONOUS 64x RATE 









MODE REGISTER 2 FORMAT 

BIT NUMBERS 








MR2-7 


MR1-6 


MR2-5 


MR2-4 


MR2-3 


MR2-2 


MR2-1 


MR2-0 



TRANSMITTER 
CLOCK 


RECEIVER 
CLOCK 




BAUD RA1 


0- EXTERNAL 


0= EXTERNAL 


0000 =50 BAUD 


0110- 600 BAUD 


1 = INTERNAL 


1 -INTERNAL 


0001 = 75 BAUD 


0111 = 1200 BAUD 






0010-U0BAUD 


1000-1800 BAUD 






0011 -134.5 BAUD 


1001 -2000 BAUD 






0100 -150 BAUD 


1010- 2400 BAUD 






0101 -300 BAUD 


1011 -3600 BAUD 



1100 -4800 BAUD 
1101 -7200 BAUD 
1110 -9600 BAUD 
1111 -19200 BAUD 



That completes the description of the Mode Registers. Remember that 
you must always write both mode registers, with Mode Register 1 first. 



12 



COMMAND REGISTER 

The Command Register is used to set the operating mode (sync or 
async), enable or disable the receiver and/or transmitter, force a "break" 
condition, reset the error flags and control the state of the RTS and DTR 
outputs. 



OPERATING MODE 
00 -NORMAL OPERATION 
01- ASYNC: AUTOMATIC 
ECHO MODE 
SYNC: SYN AND/OR 
OLE STRIPPING MODE 

10 'LOCAL LOOP BACK 
11 -REMOTE LOOP BACK 



COMMAND REGISTER FORMAT 

BIT NUMBERS 



CR-7 


CR-6 


CR-5 


CR-4 


CR-3 


CR-2 


CR-1 


CR-0 



REQUEST TO 
SEND 

0- FORCES RTS 
OUTPUT HIGH 

1 = FORCES RTS" 
OUTPUT LOW 



RESET ERROR 

0- NORMAL 

1 « RESET ERROR 
FLAG IN STATUS 
REGISTER (FE. 
OE. PE/DLE 
DETECT) 



ASYNC: 


RECEIVE 


DATA TERMINAL 


TRANSMIT 


FORCE BREAK 


CONTROL 
(RxEN) 


READY 


CONTROL 


0- NORMAL 

1 -FORCE BREAK 


0- FORCES DTR 


0- DISABLE 


0- DISABLE 
1 -ENABLE 


OUTPUT HIGH 
1 -FORCES DTR 


1- ENABLE 


SYNC: 




OUTPUT LOW 




SENDDLE 








0= NORMAL 








1-SENODLE 









SERIAL MODE JUMPERS 

The INTERFACER 3 board with its serial programming jumpers allows the 
user to adapt relative channels 6 and 7 to all standard RS-232 pin 
configurations. In RS-232 mode, these jumpers may be set so that this 
board operates in a "master" mode where it behaves as the Data Terminal 
Equipment (DTE), or it may be set so that the board operates in a "slave" 
mode where it behaves as the Data Communication Equipment (DCE). Since 
almost all CRT terminals and serial interface printers operate as the 
"master" or as the Data Terminal Equipment, then the INTERFACER 3 board 
must operate as the "slave" or Data Communication Equipment. (For this 
reason, relative channels 0-5 are set to operate in this mode.) For 
example, to connect the INTERFACER 3 to a terminal like an Televideo or a 
Hazeltine, relative channels 0-5 will connect directly and relative 
channels 6 and 7 require that serial mode jumpers (Jl and J2) should be 
set in "slave" mode as shown on the following table. To connect relative 
channels 6 and 7 to a Modem is a different set-up because Modems are set 
to operate as "slaves". When connected to a Modem, the serial mode 
jumpers (Jl and J2) of the INTERFACER 3 should be set in the "master" mode 
as shown on the following table. 

PROGRAMMING JUMPERS 



SLAVE MODE, J1/J2: for 
connections to CRT term- 
inals, printers, etc. 




















































MASTER MODE, J1/J2: for 
connection to MODEMS. 




13 



RS-232C CONTROL LINES 

The RS-232 control and data lines are defined as shown below. The EIA 
RS-232 standard defines a signal line at greater than +3V (+12V typical) 
to be "SPACING" and a signal line at less than -3V (-12V typical) to be 
"MARKING" . 



TN# 


CIRCUIT 


DIR. 


NAME 


1 


AA 






2 


BA 


TO DCE 


TxD 


3 


BB 


TO DTE 


RxD 


4 


CA 


TO DCE 


RTS 


5 


CB 


TO DTE 


CTS 


6 


CC 


TO DTE 


DSR 


7 


AB 






8 


CF 


TO DTE 


DCD 


15 


DB 


DCE SOURCE 


TSET 


17 


DD 


DCE SOURCE 


RSET 


20 


CD 


TO DCE 


DTR 



DESCRIPTION 

PROTECTIVE GROUND 
TRANSMITTED DATA 
RECEIVED DATA 
REQUEST TO SEND 
CLEAR TO SEND 
DATA SET READY 
SIGNAL GROUND 
REC'D LINE SIGNAL DET. 
TRANS. SIG. ELE. TIMING 
REC'D SIG. ELE. TIMING 
DATA TERMINAL READY 



Five hardwired RS-232 handshaking signals are provided for interfacing 
to equipment needing these lines as shown below. Output lines may be set 
either "MARKING" or "SPACING" and their state may be altered by software 
commands as described in the USART INITIALIZATION Section under Command 
Register. 



OUTPUT LINES 



NAME 


RS-232 


LINE 


DB25 PIN CONNECTION 


DTR 


CD 




20 OR 6 * 


RTS 


CA 




4 OR 5 * 






INPUT 


LINES 


NAME 


RS-232 


LINE 


DB25 PIN CONNECTION 


DSR 


CC 




6 OR 20 * 


CTS 


CB 




5 OR 4 * 


DCD 


CF 




8 



* NOTE: Non-starred pin numbers indicate the DB25 pin number for relative 
channels 0-5 and when the Serial Mode Jumpers of relative channels 6 and 
7 are set for "master" mode. The starred pin numbers indicate the DB25 
pin number on relative channels 6 and 7 when the Serial Mode Jumpers are 
set for "slave" mode. 



SYNCHRONOUS MODE CLOCK DRIVER/RECEIVERS 

Relative channels 6 and 7 can either transmit or receive the 
synchronous signal timing element signals. The typical configuration 
requires that the DATA COMMUNICATION EQUIPMENT (DCE) be the source of the 
of the synchronous transmit and receive clocks. The INTERFACER 3 is 



14 



capable of independently transmitting or receiving either of the clocks in 
either DCE or DTE modes. The following table will describe how the pin 
shunts should be set for transmitting or receiving the clocks. 

| RECEIVE SYNC CLOCK | TRANSMIT SYNC CLOCK | 
| CHANNEL J I I 

j NUMBER | TRANSMIT | RECEIVE | TRANSMIT | RECEIVE | 



1 6 


| INSTALL Jll 


| INSTALL J12 


| INSTALL J9 


| INSTALL J 10 | 


1 7 


| INSTALL J7 


| INSTALL J8 


| INSTALL J5 


| INSTALL J6 | 



EXAMPLE: If you want relative channel 7 to transmit both its transmit and 
receive sync clocks, you would install pin shunts on J7 and J5. 

EXAMPLE: If you want relative channel 6 to receive both its transmit and 
receive sync clocks, you would install pin shunts on J10 and J12. 



15 



THEORY OF OPERATION 

The INTERFACER 3 can be roughly divided into 7 subsections for 
describing its operation. These sections include: The S-100 Bus Drivers, 
the I/O Port Decode Logic, the Strobe Generation Logic, the Wait State 
Logic, the Interrupt Control/Status Logic, the USART, and the RS-232 Level 
Conversion Logic. 



S-100 BUS DRIVERS 

The separate data input and output data buses of the S-100 bus are 
converted to a bi-directional data bus by octal drivers U44 and U58. Data 
from the S-100 bus is driven onto the internal data bus by U58 only when 
sOUT goes high, indicating an output operation. The internal data bus is 
driven onto the S-100 bus when DOEN* goes low, indicating that a valid 
board select (SEL) and pDBIN are high (NAND-U45). 

All S-100 bus signals are buffered onto the board if the line would 
otherwise have more than 1 LSTTL load. Address lines AO, Al, A2, and 
pDBIN are buffered onto the board by 2/3 of hex buffer U48, and the lines 
sOUT, sINP, pWR*, (|), and pSTVAL* are inverted using portions of U29, U43, 
and U50. 



I/O PORT DECODE LOGIC 

The eight port block that the INTERFACER 3 occupies is decoded by 6 
open collector X-OR gates (U46 and U47). 5 of these gates decode address 
lines A3-A7 by comparing against positions 2-6 of switch Si, and the last 
section compares sOUT and sINP* to determine if an I/O operation is occu- 
ring. When all compare conditions are satisfied, ASEL goes high. Closing 
position 1 of SI will ground ASEL and disable the board completely. 

A valid board select (SEL*) is generated (by 1/3 of U32), when ASEL 
goes high along with USEL (indicating that this boards select number is 
active) and Al and A2 are not both high (indicating the USER SELECT PORT 
is not selected). SEL* is disabled by 1/3 of U32 when the USER SELECT 
PORT is enabled so that conflicts between up to four boards does not 
occur. 

A USER SELECT write occurs when ASEL, Al, A2, sOUT, and STROBE go 
high. This generates OUTO* (U32) which clocks the least significant 5 
bits on the bus (D0-D4) into hex latch U34. The 3 low order bits of U34 
are decoded into 8 chip enables (CEO* - CE7*) by U35 when SEL is high and 
A2 and ESTROBE* are low. The 2 high order bits of U34 are compared to 
switch positions 7 and 8 of SI by 1/2 of U47 (X-NOR) to decode a current 
user board select signal USEL. Access to registers on the board requires 
that USEL be high before access is gained. 

The four interrupt read and write strobes are generated by decoder U49 
when A2 is high and SEL* and STROBE* are low. AO, Al, and sINP* determine 
which output becomes active at the proper time. 



16 



STROBE GENERATION LOGIC 

In order to gain additional access time in an I/O cycle for the 2651 
USARTs, the INTERFACER 3 generates early strobes based on valid status. 
S-100 bus strobes pDBIN and pWR* are gated together (U30) and inverted to 
generate STROBE and STROBE*. These signals indicate that a bus strobe is 
occuring. The interrupt registers and user select port have their data 
gated by STROBE because they are TTL and capable of very high speed 
operation. Since the 2651 type USART is a MOS device and has an access 
time of approximately 250 nS, an early strobe is generated so that wait 
states are avoided whenever possible. A status valid signal, ESTATVAL*, 
is generated whenever pSYNC is high and pSTVAL* is low. ESTATVAL* clears 
"D" flop U33a to generate ESTROBE*, which becomes one term of the USART 
chip enable decoder U35. The termination of STROBE* causes a "1" to be 
clocked into U33a and terminate ESTROBE*. 



WAIT STATE LOGIC 

To allow operation with high speed processors, a wait state generator 
allows the addition of 1 or 2 wait cycles. U31 forms a 2 bit shift 
register clocked by (J)*. A wait state is left pending after STROBE goes 
low, and when STALL1* or STALL2* and A2 are low (U30), and SEL is high 
(U45), WAIT* is generated. STALL 1* is clocked out on the next rising edge 
of (J)* after STROBE goes high, and STALL2* is clocked out the following 
cycle. The pRDY* line is pulled low by U48 when WAIT* goes low. When 
neither STALL1* or STALL2* is connected on J17, no wait states will be 
generated. 



INTERRUPT CONTROL/STATUS LOGIC 

The interrupt logic consists of two 8 bit latches for enabling inter- 
rupts onto the bus, two 8 bit buffers for reading current interrupt 
status, and sixteen 2 input open collector NAND buffers for driving the 
interrupts on the bus. 

Two 8 bit latches are formed by four 4 bit latches (U38, U41, U52, and 
U55) for generating the interrupt enable mask. The Q outputs become the 
RxINTENx and TxINTENx interrupt enables for selectively masking "OFF" 
individual interrupts. Upon power-up or reset, these latches are cleared 
by CLR* so that all interrupts are disabled. 

The TxRDY and RxRDY interrupt outputs from the 2651 USARTs are 
inverted to form active high interrupt signals. These interrupt signals 
are fed to one input of the open collector NAND buffer, with the corres- 
ponding interrupt enable fed to the other input. The resulting interrupt 
outputs (TxINTx and RxINTx) are capable of driving the VI0-7 lines 
directly, and are brought out to J15 and J16 for jumpering to the appro- 
priate line. 

Two 8 bit buffers are formed from four quad tri-state buffers (U37, 
U42, U51, and U56) for gating the current USART interrupts (TxRDYx and 
RxRDYx) onto the bus as status information. Since the buffers use Tx and 
Rx RDY instead of Tx and Rx INT lines, the status of disabled interrupts 
are displayed as well as enabled interrupts. 



17 



Relative channels 6 and 7 allow jumpering the TxEMT/DSCHG interrupt 
from the USART to either the TxRDY or RxRDY interrupt outputs. This is 
possible since the outputs from the 2651 are open drain and may be wire- 
ORed. 



USARTS 

The 2651 type USART is quite sophisticated in that it can run in both 
asynchronous as well as synchronous modes. In addition, the part has an 
internal baud rate generator, RS-232 status and control bits, up to 3 
interrupt outputs, and the capability of transmitting as well as receiving 
baud clocks. 

The chip enable (CE) and read/write (R*/W) lines are operated by 
initially determining whether a read or a write will occur (sINP* to R*/W) 
and then strobing the part with CE*. Address lines AO and Al determine 
which of four registers will be selected and CLR resets the USART. 

The baud rate clock BAUDCLK is generated by a 5.0688MHz crystal oscil- 
lator formed from 3 inverters (U29) and crystal XI. 



RS-232 LEVEL CONVERSION LOGIC 

Each USART has a full compliment of RS-232 handshaking lines for 
devices that require them. Industry standard 1488 and 1489 receivers and 
transmitters are used throughout for highest performance. In addition to 
the data lines TxD and RxD, each channel has a RTS and DTR output and a 
CTS, DSR, and DCD input. All three RS-232 status lines have pullup 
resistors to +12V so that floating inputs are pulled high. 

Relative channels 0-5 have the RS-232 lines set for direct connec- 
tion to CRT terminals and printers. Relative channels 6 and 7 may be set 
for both DCE and DTE modes by wiring new jumpers for Jl and J2. 

Relative channels 6 and 7 are capable of sending and receiving both 
the transmit and receive baud clocks for running in synchronous mode. An 
RS-232 driver and a receiver are provided for RxC and TxC, and either one 
may be jumpered in. 



18 



User Notes 



19 



SAMPLE TEST PROGRAM FOR RUNNING IN ASYNCHRONOUS MODE 



INTERFACER 3 TEST PROGRAM 



* 
* 
* 
* 
* 

* This program will initialize all 2651s for asynchronous 

operation at 9600 baud with 8 data bits, one stop bit, no 

parity. This program will echo all characters received on any 

user channel (from to 31) and if any user sends a ~C, the 

program will terminate and return back to CP/M. 

NOTE: This program assumes that the console device is either an 

INTERFACER 1 or 2 addressed at ports and 1. 

* 

* 

base 

udata 

ustat 

mode 

coramr 

txreg 

rxreg 

user 

exit 

tbmt 

dav 
* 
* 
* 



Start 
Loop 



Init 



Echo 



Loopl 



equ 



18h 



equ 


BASE+Oh 


equ 


BASE+lh 


equ 


BASE+2h 


equ 


BASE+3h 


equ 


BASE+4h 


equ 


BASE+5h 


equ 


BASE+7h 


equ 





equ 


Olh 


equ 


02h 



data port in and out 
status register port 
mode register port 
command register port 
tx int register 
rx int register 
port to select user 
CP/M reentry point 
transmitter buffer empty 
data available 



org 


lOOh 


mvi 


a,0ffh 


inr 


a 


cpi 


2 OH 


jz 


echo 


out 


user 


mov 


b,a 


call 


init 


mov 


a,b 


jmp 


loop 


mvi 


a,0CEh 


out 


mode 


mvi 


a,7Eh 


out 


mode 


mvi 


a,27h 


out 


commr 


ret 




mvi 


a,0FFh 


out 


txreg 


out 


rxreg 


inr 


a 


out 


user 


mov 


b,a 


call 


cstat 



init user 

next user 

check for final uart 

start echo routine 

select uart 

save user in b 

init the uart 

restore user 

next 

set up the 2651 

send to mode register 1 

9600 baud, internal clocks 

SEND BYTE TO M.R. 2 

could be 07h (no 1420) 



;mask value 
;set tx int reg 
;set rx int reg 
;next user 
; select uart 
;save user in b 
; check for data 



20 





cpi 


OAAh 


;data if aa 




cz 


ok 


;do echo loop 




mov 


a,b 


;restore user 




jmp 


loopl 


;next 


Ok 


call 


inloop 


;get data 




call 


oloop 


; output data 




ret 






Cstat 


in 


us tat 


;look for key entry 




ani 


dav 


; check status 




jz 


nodat 


;no data 




mvi 


a, OAAh 


;data char 




ret 






Nodat 


mvi 
ret 


a,0 


;no data char 


Inloop 


in 


ustat 


;look for key entry 




ani 


dav 


; check the status 




jz 


inloop 


;wait for key entry 




in 


udata 


;get key entry 




ani 


7Fh 


jmask parity off 




cpi 


03h 


;has a ~c been hit? 




jz 


done 


; return to CP/M 




mov 


e,a 


;save input in E reg. 




ret 






Oloop 


in 


ustat 


; check ready for output 




ani 


tbmt 


; check status 




jz 


oloop 


;wait for ready 




mov 


a,e 


;get data 




out 


udata 


; output character 




ret 






Done 


jmp 


exit 


; return to cp/m 




end 







21 



SAMPLE TEST PROGRAM FOR RUNNING IN SYNCHRONOUS MODE 



INTERFACER 3 SYNCHRONOUS TEST PROGRAM 



* 

* 
* 
* 

* This program will take characters typed on the console and 
transmit them synchronously at 19.2K baud out of relative user 
6 to relative user 7, and then back out of 7 to 6 and back to 
the console. When a control C (~C) is hit on the console, the 
program will terminate and re-enter CP/M. 

NOTE: This program assumes that the console device is an INTER- 
FACER 1 or 2 at ports and 1. It does not use direct BIOS 
entry points. The synchronous clock jumpers should be set as 
described in the example in the SYNCHRONOUS MODE CLOCK DRIVER- 
/RECEIVER section. The SERIAL MODE JUMPERS should be set so 
that channel 7 is in master mode and 6 is in slave mode. 



* 

base 

udata 

ustat 

mode 

commr 

txreg 

rxreg 

user 

exit 

cstat 

cdata 

tbmt 

dav 

* 

START 



INIT6 



equ 


lOh 


equ 


base+Oh 


equ 


base+lh 


equ 


base+2h 


equ 


base+3h 


equ 


base+4h 


equ 


base+5h 


equ 


base+7h 


equ 





equ 


Olh 


equ 


OOh 


equ 


Olh 


equ 


02h 



INIT7 



org 


lOOh 


mvi 


a,0ffh 


out 


txreg 


out 


rxreg 


mvi 


a,6h 


out 


user 


mvi 


a,08cH 


out 


mode 


mvi 


a,0fh 


out 


mode 


mvi 


a,0a5h 


out 


ustat 


mvi 


a,67h 


out 


commr 


mvi 


a,0a5h 


out 


udata 


mvi 


a,7h 


out 


user 



data port in and out 
status register port 
mode register port 
command register port 
tx int register 
rx int register 
port to select user 
CP/M reentry point 
console status port 
console data port 
transmitter buffer empty 
data available 



mask value 

set tx int reg 

set rx int reg 

init user 6 

select uart 

set up the 2651 

send to mode register 1 

19200 baud, external clocks 

send to mode register 2 

synch character 

send to synch reg 

synch strip mode 

send to command register 

dummy synch character 

poke in butt to start 

init user 7 

select uart 



22 



CONIN 



OUT 6 
OUT6L 



IN 7 
IN7L 



OUT 7 



IN 6 
IN6L 



CONOUT 



DONE 



mvi 


a,08cH 


out 


mode 


mvi 


a,3fh 


out 


mode 


mvi 


a,0a5h 


out 


ustat 


mvi 


a,67h 


out 


commr 


mvi 


a,0a5h 


out 


udata 


in 


cstat 


ani 


dav 


jz 


conin 


in 


cdata 


ani 


7fh 


cpi 


03 


jz 


done 


mov 


l,a 


mvi 


a, 6 


out 


user 


in 


ustat 


ani 


tbmt 


jz 


out61 


mov 


a,l 


out 


udata 


mvi 


a, 7 


out 


user 


in 


ustat 


ani 


dav 


jz 


in71 


in 


udata 


mov 


l,a 


in 


ustat 


ani 


tbmt 


jz 


out7 


mov 


a,l 


out 


udata 


mvi 


a, 6 


out 


user 


in 


ustat 


ani 


dav 


jz 


in61 


in 


udata 


mov 


l,a 


in 


cstat 


ani 


tbmt 


jz 


conout 


mov 


a,l 


out 


cdata 


jmp 


conin 


jmp 


exit 


end 





set up the 2651 

send to mode register 1 

19200 baud, internal clocks 

send to mode register 2 

SYN1 character 

send to synch reg 

synch strip mode 

send to command register 

dummy synch character 

poke in butt 

look for key entry 

check status 

no data 

get char 

mask parity off 

has a ~c been hit? 

return to CP/M 

save in 1 

user 6 

select 

look for ready 

check the status 

wait for ready 

restore character 

output char 

user 7 

select 

get status 

check for char 

no char 

get char 

save char 

check ready for output 

check status 

wait for ready 

get data 

output character 

user 6 

select 

get status 

check for char 

no char 

get char 

save char 

check ready for output 

check status 

wait for ready 

get data 

output character 



; return to cp/m 



23 



SAMPLE PROGRAM FOR USING THE INTERFACER 3 AS THE CP/M CONSOLE 



CompuPro INTERFACER 3 equates. 



GBI3: 


EQU 


lOh 


GBUD: 


EQU 


GBI3+0 


GBUS: 


EQU 


GBI3+1 


GBUM: 


EQU 


GBI3+2 


GBUC: 


EQU 


GBI3+3 


GBUSR 


EQU 


GBI3+7 


I3DAV: 


EQU 


02H 


I3TBMT: 


EQU 


01H 



; INTERFACER 3 BASE 
;Uart data port 
;Uart status port 
;Uart mode port 
;Uart command port 
;User select register 
; INTERFACER 3 DAV 
; INTERFACER 3 TBMT 



CONSOLE INITIALIZATION 

This routine performs the initialization 
required by the INTERFACER 3 USART. 



;select user "0" 

;output to select user 

;8 bits, no parity, 2 stops 

;Set up mode register 1 

;9600 baud 

;Set up mode register 2 

;dtr low, no break, 

;no reset, rts low 

;Set up command port 



sTINIT 


MVI 


A,0 




OUT 


GBUSR 




MVI 


A,0EEH 




OUT 


GBUM 




MVI 


A,07EH 




OUT 


GBUM 




MVI 


A,027H 




OUT 


GBUC 




RET 





sCONST 



CONSOLE STATUS 

This routine samples the Console status and returns 
the following values in the A register. 

EXIT A = (zero) , means no character 
currently ready to read. 

A = FFh (255), means character 
currently ready to read. 



; Input from port 
;Mask data available 
;If data not available 



IN 


GBUS 


ANI 


I3DAV 


RZ 




ORI 


OFFH 


RET 





CONSOLE INPUT 

Read the next character into the A register, 
clearing the high order bit. If no character 
currently ready to read then wait for a character 
to arrive before returning. 



EXIT 



A = character read from terminal. 



24 



sCONIN 


IN 


GBUS 




AN I 


I3DAV 




JZ 


sCONIN 




IN 


GBUD 




AN I 


7Fh 




RET 





;Get status from uart 



CONSOLE OUTPUT 

Send a character to the console. If the console 
is not ready to receive a character wait until 
the console is ready. 

ENTRY C = ASCII character to output to console. 

;Get uart status 
;Test if buffer empty 



sCONOUT 


IN 


GBUS 




AN I 


I3TBMT 




JZ 


sCONOUT 




MOV 


A,C 




OUT 


GBUD 




RET 





End GBcbioI3.asm 



25 



hO 




National 
Semiconductor 



INS2651 Programmable Communications Interface 

General Description 



October 1980 



The INS2651 is a programmable Universal Synchronous/ 
Asynchronous Receiver/Transmitter (USART) chip 
contained in a standard 28-pin dual-inline package. The 
chip, which is fabricated using N-channel silicon gate 
MOS technology, functions as a serial data input/output 
interface in a bus structured system. The functional 
configuration of INS2651 is programmed by the system 
software for maximum flexibility, thereby allowing the 
system to receive and transmit virtually any serial data 
communications signal presently in use. 

The INS2651 can be programmed to receive and transmit 
either synchronous or asynchronous serial data. The 
INS2651 performs serial-to-parallel conversion on data 
characters received from an input/output device or a 
MODEM, and parallel-to-serial conversion on data char- 
acters received from the CPU. The CPU can read the 
complete status of the INS2651 at any time during the 
functional operation. Status information reported 
includes the type and the condition of the transfer 
operations being performed by the INS2651, as well as 
error conditions (parity, overrun, or framing). 



Features 

■ Synchronous and Asynchronous Full Duplex or Half 
Duplex Operations 



Synchronous Mode Capabilities 

- Selectable 5- to 8-Bit Characters 

- Selectable 1 or 2 SYNC Characters 

- Transparent or Non-Transparent Mode 

- Automatic SYNC or DLE-SYNC Insertion 

- SYNC or DLE Stripping 
Asynchronous Mode Capabilities 

- Selectable 5- to 8-Bit Characters 

- 3 Selectable Clock Rates (1x, 16x. or 64x the 
Baud Rate) 

- Line Break Detection and Generation 

- 1-, 1V4-, or 2-Stop Bit Detection and Generation 

- False Start Bit Detection 
Baud Rates 

- DC to 0.8 M Baud (Synchronous) 

- DC to 0.8 M Baud (1x, Asynchronous) 

- DC to 50 k Baud (16x, Asynchronous) 

- DC to 12.5 k Baud (64x, Asynchronous) 
Internal or External Baud Rate Clock 

- 16 Internal Rates (50 to 19,200 Baud) 
Double Buffering of Data 

TTL Compatible 

No System Clock Required 

Direct Plug-In Replacement for Signetics 2651 



INS2651 General System Configuration 





A00RESS 
•US 










PERIPHERAL 
INTERFACE 














- 










■ 




















Al 

At 


INS2 


5S1 










SYSTEM 
PROCESSOR 




0ATA 

BUS 

BUFFER 






_ 


SYN/OLE 
CONTROL 






4- 


4 






CONTROL 
IUS 














t 




_ 


TRANSMITTER 
SECTION 












0ATA 
■US 


^ 


OPERATION 
CONTROL 




•> 
















*•»■ 


RECEIVER 
SECTION 














\ 










•AU0 RATE 

GENERATOR 

AN0 

CONTROL 






















MODEM 
CONTROL 


























♦ 










1 


BRCLK 








MEMORY 

































SERIAL 

DATA 

OUT 



MODEM 

CONTROL 

FUNCTIONS 



1980 National Semiconductor Corp. 



Absolute Maximum Ratings 

Operating Ambient Temperature 0°C to +70°C 

Storage Temperature -65°C to +150°C 

All Voltages with Respect to Ground -0.5 V to +6.0 V 

Note: Maximum ratings indicate limits beyond which permanent 
damage may occur. Continuous operation at these limits is not 
intended and should be limited to those conditions specified under 
DC Electrical Characteristics. 



DC Electrical Characteristics 

Ta = 0°C to +70°C; Vqc = +5.0 V ± 5%, GND = V 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Test Conditions 


VlL 


Input Low Voltage 






0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 




0.25 


0.45 


V 


'OL = 1.6mA 


VOH 


Output High Voltage 


2.4 


2.8 




V 


IOH = -100M 


ML 


Input Load Current 






10 


JiA 


V|N = 0Vto5.5V 


"LD 


Data Bus Leakage Current 






10 


AiA 


VoUT = 4.0V 


"LO 


Open Drain Leakage Current 






10 


HA 


VQUT = 4.0V 


ice 


Power Supply Current 




65 


150 


mA 





Capacitance 

Ta • +25°C; Vcc = GND = V 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Test Conditions 


C|N 

CouT 

Cl/O 


Input Capacitance 
Output Capacitance 
I/O Capacitance 






20 
20 
20 


pF 
PF 
PF 


f c = 1 MHz 
Unmeasured pins 
to ground 



AC Electrical Characteristics 

Ta • 0°C to +70°C; Vcc " +50 V ± 5%. GND - V 



Symbol 



Parameter 



Min 



| Typ I Max | Unit | Tert Condition* 



BUS PARAMETERS 



tCE 


Chip Enable Pulse Width 


300 






ns 




tAS 


Address Setup Time 


20 






ns 




tAH 


Address Hold Time 


20 






ns 




tcs 


R/W Control Setup Time 


20 






ns 




tCH 


R/W Control Hold Time 


20 






ns 




tos 


Data Setup Time for Write 


225 






ns 




tDH 


Data Hold Time for Write 


50 






ns 




tDD 


Data Delay Time for Read 






250 


ns 


Cl = lOOpF 


tDF 


Data Bus Floating Time for Read 






150 


ns 


Cl = 100pF 



OTHER TIMINGS 



tRES 


RESET Pulse Width 


1000 






ns 




fBRG 


Baud Rate Generator Input Clock 
Frequency 


1.0 


5.0688 


5.073 


MHz 




tBRH 


Baud Rate Clock High State 


70 






ns 




tBRL 


Baud Rate Clock Low State 


70 






ns 




ffl/T 


TxC or RxC Input Clock Frequency 


DC 




0.769 


MHz 




tR.TH 


TxC or RxC Clock High State 


650 






ns 




tR'TL 


TxC or RxC Clock Low State 


650 






ns 




tTxD 


TxD Delay from Falling Edge of TxC 






650 


ns 


Cl = 100pF 


tTCS 


Skew Between TxD Changing and 
Falling Edge of TxC Output 










ns 


Cl ^ 100pF 


tR»S 


Rx Data Setup Time 


300 






ns 




tR>H 


Rx Data Hold Time 


300 






ns 





Timing Waveforms 



J 



'MS — 



\ 



RESET TIMING 



"•Ia. 



p 



4 



H ,£S h- 



£ 



— *| 'CH U— 



X 



_JtohU— 

IDC 



(REAM IUSHOATIIMsY ■OTVAIIO Y DATA VALID I Y IUSH0ATWC 



|*-«0F-J 



READ AND WRITE TIMING 



rStt 



-'IRH- 
-'H/TH- 



/ 



- <«Rl - 
WTL ' 



-'f«R6- 
-IffR/T- 



/ 



CLOCK TIMING 



•-«TX0-4 



1 



t-- 



y 



TRANSMIT TIMING 



X 



\ 



mx: 



x: 



\. 



/ 



v 



RECEIVE TIMING 






00 



Timing Waveforms (cont'd.) 

^ooinnnfuuuinnjuuuiniuirijuuuinjmj^ 



1,1, 1,4, 1.1,1! 1,4, 5 . 1,1,1,4,8 . 1,1,1,4,1 . 1,1,1,4,1 . 
DATA 1 I DATA1 I DATA] I SHI I 0ATA4 I 




DATA 1 DATA 1 



OATA 1 OATA 4 

SYNCHRONOUS MODE 



-0 , A |1|1|1|4|5|B C A .I|1|3|4|S|« C A i 1 | 1 , 1 | 4 | 8 j » C< » A I 1 | 2 

| | 0ATA1 | [_ | DATA1 | | j OATA 1 | | | DATA 4 




WRITE \t/ 
Of THR U 

OATA I 0ATA1 OATA) OATA 4 

ASYNCHRONOUS MODE 

■* iruinjuuiJinjui^^ 

, 1,1, 3,4,8 . I , 1,1,4,5, I ,1,1,4,8. 1,1,1,4,8.1 ,1,3,4,5 . I ,1,1,4, 8, 1 
RiD I SYN1 I DATA1 I 0ATA1 I OATA) I 0ATA4 I DATA 5 I 



I I |» -- IGNORED •) 




REAO REAO 

STATUS RHR 

(OATA 1) 



READ 


REAO 


REAO 


RHR 


RHR 


RHR 


(OATA 11 


(OATA 11 


(DATA 31 



SYNCHRONOUS MODE 



^0,^.1,1,1,4,5.. C*. 1,1, 1,4, 1.1 C,-D-->> 1 I I »|I I I|1|I C *, 1|1,1, 
RiD f> LI OATAI | | I 0ATA1 | | | 0ATA1 | [_ | 0ATA4 




ASYNCHRONOUS MODE 
TTHDY. Titirr TIMING (SHOWN FOR HIT CHARACTERS. KO PARITY. 1 STOP IITS (IN SYNCHRONOUS MODE). 
If.TniV TIMING (SHOWN FOR HIT CHARACTERS. NO PARITY. 1 STOP IITS (IN ASYNCHRONOUS! 



INS2651 Block Diagram 



DATA I US 
07-00 



'l.'ll.l»l 




OPERATION CONTROL 



MODE REGISTER 1 



MODE REGISTER 1 



COMMAND REGISTER 



STATUS REGISTER 



BAUO RATE 

GENERATOR 

AND 

CLOCK CONTROL 



SYN/OLE CONTROL 



SYN1 REGISTER 



SYN1 REGISTER 



DIE REGISTER 



INS2651 Functional Pin Definitions 

The following describes the function of all the INS2651 
input/output pins. Some of these descriptions reference 
internal circuits. 

INPUT SIGNALS 

Reset (RESET), Pin 21: When high, performs a master 
reset on the INS2651. This signal asynchronously 
terminates any device activity and clears the Mode, 
Command, and Status Regsiters. The device assumes the 
idle state and remains in this mode until initialized with 
the appropriate control words. 

Address Lines (A1-A0), Pins 10, 12: Address lines used 
to select internal Mode and Command registers. 

Read/Write (R/W), Pin 13: Controls the direction of 
data bus transfers. A high input allows data from the 
CPU to be loaded into the addressed register. A low 
input causes the contents of the addressed register to be 
present on the data bus. 

Chip Enable (CE), Pin 11: When low, indicates that 
control and data lines to the device are valid and that the 
specified operation should be performed. When high, 
places the device in the TRISTATE* condition. 



Baud Rate Generator Clock (BRCLK), Pin 20: 5.0688 
MHz clock input to the internal Baud Rate Generator. 
Not requ ired if external receiver and transmitter (TxC 
and RxC) clocks are used. 

Receiver Data (RxD), Pin 3: Serial data input to the 
receiver. 

Data Set Ready (DSR), Pin 22: General-purpose input 
which, when low, indicates either the Data Set Ready or 
Ring condition. Its complement is stored as Status 
Register bit 7. A change in state of this input causes a 
low output on TXEMT/DSCHG. 

Data Carrier Detect (DCD), Pin 16: When low, enables 
the receiver to operate. The complement of this input is 
stored as Status Register bit 6, and an input change in 
state causes a low output on TXEMT/DSCHG. 

Clear to Send (CTS), Pin 17: When low. enables the 
transmitter to operate. When high, holds the TxD 
output in MARK condition. 

Vcc. Pi" 26: +5-volt supply. 
Ground, Pin 4: 0-volt reference. 



OUTPUT SIGNALS 

Transmitter Ready (TxRDY), Pin 15: A low on this 
output, which is open-drain, indicates that Transmit 
Holding Register (THR) is ready to accept a data char- 
acter from the CPU. This output, which is the comple- 
ment of Status Register bit 0, goes high when the data 
character is loaded and is valid only when the transmitter 
is enabled. The TxRDY output can be used as an inter- 
rupt to the system. 



Receiver Ready (RxRDY), Pin 14: A low on this output, 
which is open-drain, indicates that the Receive Holding 
Register (RHR) has a character ready for input to the 
CPU. This output, which is the complement of Status 
Register bit 1, goes high either when the Receiver 
Holding Register is read by the CPU or when the receiver 
is disabled. The RxRDY output can be used as an 
interrupt to the system. 

Transmitter Empty or Data Set Change (TxEMT/DSCHG), 

Pin 18: A low on this output, which is open-drain, 
indicates that either the transmitter has completed 
serialization of the last charact er lo ade d by t he CPU or 
that a change of state of the DSR or DCD inputs has 
occurred. If the TxEMT condition does not exist, this 
output goes high when the Status Register is read by the 
CPU. Otherwise, the Transmit Holding Registe r must be 
loaded b y the CPU for this line to go high. The TxEMT/ 
DSCHG output can be used as an interrupt to the system. 
This output is the complement of Status Register bit 
SR2. 

Transmitter Data (TxD), Pin 19: Composite serial data 
output to a MODEM or input/output device. The TxD 
output is held in the marking state (logic 1) when the 
transmitter is disabled. 



Pin Configuration 



RiD ' 
GNO ' 



fi/W • 
RiRDV • 



Data Terminal Ready (DTR), Pin 24: General-purpose 
outp ut nor mally used to indicate Data Terminal Ready. 
The DTR output is the complement of Command 
Register bit 1. 

Request to Send (RTS), Pin 23: General-purpose ou tput 
normally used to indicate Request to Send. The RTS 
output is the complement of Command Register bit 5. 



INPUT/OUTPUT SIGNALS 

Data (D7-D0) Bus, Pins 28, 27. 8, 7, 6, 5, 2, 1: This bus 
comprises eight TRI-STATE input/output lines. The bus 
provides bidirectional communications between the 
INS2651 and the CPU. Data, control words, and status 
information are transferred via the Data Bus. 

Receiver Clock (RxC), Pin 25: If external receiver clock 
is programmed, this input controls the rate at wh ich a 
data character is received. The frequency of the RxC 
input is a multiple (1x, 16x, or 64x) of the Baud Rate. 
Data is sampled on the rising edge of the clock. If 
internal receiver clock is programmed, this pin becomes 
an output at 1x the programmed Baud Rate. 

Transmitter Clock (TxC), Pin 9: If external transmitter 
clock is programmed, this input controls the rate at 
which a data character is transmitted. The frequency of 
the TxC input is a multiple (1x, 16x, or 64x) of the 
Baud Rate. Transmitter Data is clocked out of the 
INS2651 on the falling edge of the TxC input. If 
internal transmitter clock is programmed, this pin 
becomes an output at 1x the programmed Baud Rate. 





\^f n 




01 




n 




00 




u 




vcc 




25 




Bit 




24 




DTB 




21 




RTS 




IMS265I " 




DSR 
RESET 




20 




BRCIK 


10 

11 


19 
11 




T»D 


TaEMT/DSCHG 


12 


17 




CTS 


13 


It 




DTD 


14 


IS 




TTRDY 






INS2651 Programming 

The system software determines the operative conditions 
(mode selection, clock selection, data format, and so 
forth) of the INS2651 via internal Mode Registers 1 and 
2. and the Command Register. Prior to initiating data 
communications, the INS2651 operational mode must 
be programmed by performing write operations to these 
8 bit registers via the Data Bus. The device can be repro 
grammed at any time during program execution. How- 
ever, the receiver and transmitter should be disabled if 
the change has an effect on the reception or transmission 
of a character. 

The internal registers of the INS2651 are accessed by 
applying signals to the CE. R/W. A1. and A0 inputs as 
specified in table 1. 



Table 1. Guess My Name 



CE 


A1 


A0 


R/W 


Function 


1 


X 


X 


X 


TRI STATE Data Bus 














Read Receive Holding Register 











1 


Write Transmit Holding Register 








1 





Read Status Register 








1 


1 


Write SYN1/SYN2/DLE Registers 





1 








Read Mode Registers 1 and 2 





1 





1 


Write Mode Registers 1 and 2 





1 


1 





Read Command Register 





1 


1 


1 


Write Command Register 



In the case of multiple registers (SYN1/SYN2/DLE 
Registers and Mode Registers 1 and 2), successive read 
or write operations will access the next higher register. 
For example, if A1 equals 0, A2 equals 1, and R/W 
equals 1. the first write operation loads SYN1 Register. 
The next write operation loads SYN2 Register, and the 
third loads the DLE Register. Read and write operations 
are performed on the Mode Registers in a similar manner. 
If more than the required number- of accessses is made, 
the internal register pointer returns to the first register. 
The pointers are reset to the first registers either by a 
RESET input or by performing a "Read Command 
Register" operation, but are unaffected by any other 
read or write operation. 



INITIAL RESET 



■ODE REGISTER I 




STRCHROROUS^ 



ROTE M00E REGISTER I MUST IE WRITTER 
•EE0RE M00E RECISTER I CAR IE 
■HITTER MODE REGISTER 1 REED 
ROT IE rROGRAMMEO IE EXTERNAL 
CLOCKS ARE USED 



ROTE SVRI REGISTER MUST IE MRITTER 
■EF0RE SYR2 REGISTER CAR IE 
■MUTER ARDSTUIEEOREDLE 
CAR IE WRITTER 




s 



SI 




Figure 1. Initialization Flowchart 



CO 

o 



MODE REGISTER 1 FORMAT 

-BIT NUMBERS- 



MR1-7 


MRI-6 


MR1-5 


MR1-4 


MR1-3 


MR1-2 


MRI-I 


MRI 



YNC SYNC PARITY TYPE 

OOF SYN TRANSPARENCY 0-000 

HARACTERS CONTROL 1 . EVEN 

■DOUBLE SYN 0' NORMAL 

' SINGLE SYN I . TRANSPARENT 

ASYNC 

STOP BIT LENGTH 

00-INVALIO 

01 • I STOP BIT 

10- 1'A STOP BITS 

II • 2 STOP BITS 



PARITY CONTROL 
0* DISABLED 
I • ENABLED 



CHARACTER LENGTH 

00 - S BITS 

01 • 6 BITS 
10= J BITS 
11= B BITS 



MODE AND BAUD RATE FACTOR* 

00 'SYNCHRONOUS URATE 

01 • ASYNCHRONOUS 1i RATE 
10 • ASYNCHRONOUS 16i RATE 
11 • ASYNCHRONOUS W. RATE 



MODE REGISTER 2 FORMAT 

-BIT NUMBERS- 



MR2-7 


MR 1-6 


MR2-5 


MR2-4 


MR2-3 


MR2-2 


MR2-1 


MR2-0 



NOT USED 


TRANSMITTER 
CLOCK 


RECEIVER 
CLOCK 








BAUD RATE SELECTION 






0» EXTERNAL 


0' EXTERNAL 


0000 


SO BAUD 


0110 


S00 BAUD 


1100 


4100 BAUO 




!■ INTERNAL 


1 • INTERNAL 


0001 


7SBAU0 


0111 


1200 BAUD 


1101 


7200 BAUO 








0010 


110BAUO 


1000 


1B00BAUO 


1110 


9600 BAUO 








0011 


134.S8AUD 


1001 


2000 BAUD 


mi 


19200 BAUD 








0100 


ISO BAUD 


1010 


2100 BAUO 












0101 


300 BAUD 


1011 


3600 BAUO 







COMMAND REGISTER FORMAT 

-BIT NUMBERS- 



CR-7 


CR-6 


CR-5 


CR-4 


CR-3 


CR-2 


CR-1 


CR-0 



OPERATING MODE 
00 'NORMAL OPERATION 
01 ■ ASYNC: AUTOMATIC 
ECHO MODE 
SYNC: SYN AND/OR 
OLE STRIPPING MODE 
10 •LOCAL LOOP BACK 
II -REMOTE LOOP BACK 



REQUEST TO 

SENO 

0» FORCES RT5 

OUTPUT HIGH 
1- FORCES ATS 

OUTPUT LOW 



RESET ERROR 
0- NORMAL 

1' RESET ERROR 
FLAG IN STATUS 
REGISTER [FE. 
OE. PE/OLE 
OETECTI 



ASYNC 

FORCE BREAK 
0* NORMAL 
I- FORCE BREAK 
SYNC: 
SENO OLE 
0» NORMAL 
1 'SEND OLE 



STATUS REGISTER FORMAT 
-BIT NUMBERS- 



RECEIVE 
CONTROL 


OATA TERMINAL 
REAOV 


TRANSMIT 
CONTROL 


(R.ENI 
O'OISABLE 
1' ENABLE 


O'FORCESOTR 
OUTPUT HIGH 

1- FORCES 675 
OUTPUT LOW 


' DISABLE 
■•ENABLE 



SR-7 


SR-6 


SR-S 


SR-« 


SR-3 


Sfl-2 


SR-1 


SR-0 



OATA SET 


OATA CARRIER 


FE/SYN DETECT 


OVERRUN 


PE/OLE OETECT 


READY 


DETECT 


ASYN: 


- NORMAL 


ASYNC: 


• SSR INPUT 


• DCO INPUT 
IS HIGH 


• NORMAL 


1- OVERRUN 
ERROR 


0" NORMAL 


1 ■ DTK INPUT 


1 • OCO INPUT 


1 - FRAMING ERROR 


1 • PARITY ERROR 


IS LOW 


(SLOW 


SYNC: 

- NORMAL 

1 • SYN CHARACTER 

DETECTED 




SYNC: 

0" NORMAL 

1- PARITY ERROR 

OR OLE 

CHARACTER 

RECEIVEO 



TiEMT/OSCHG RiROY 

0- NORMAL 0* RECEIVE 

"KAcUOR gj*«» 

TRANSMIT SHIFT """ 

REGISTER IS 1 • RECEIVE 

EMPTY HOLDING 

REGISTER 

HAS DATA 



• TRANSMIT 
HOLDING 
REGISTER 
BUSY 

• TRANSMIT 
HOLOING 
REGISTER 
EMPTY 



NOTE 1: BAUO RATE FACTOR IN ASYNCHRONOUS MODE APPLIES ONLY IF 
EXTERNAL CLOCK IS SELECTEO. FACTOR IS III IF INTERNAL 
CLOCK IS SELECTED. 



Table 2. Baud Rate Generator Characteristics (Crystal Frequency = 5.0688 MHz) 



Baud 
Rate 


Theoretical 

Frequency 

16x Clock 

(kHz) 


Actual 
Frequency 
16x Clock 

(kHz) 


Percent 
Error 


Duty 
Cycle 

(%) 


Divisor 


50 


0.8 


0.8 


- 


50/50 


6336 


75 


1.2 


1.2 


- 


50/50 


4224 


110 


1.76 


1.76 


- 


50/50 


2880 


134.5 


2.152 


2.1523 


0.016 


50/50 


2355 


150 


2.4 


2.4 


- 


50/50 


2112 


300 


4.8 


4.8 


- 


50/50 


1056 


600 


9.6 


9.6 


- 


50/50 


528 


1200 


19.2 


19.2 


- 


50/50 


264 


1800 


28.8 


28.8 


- 


50/50 


176 


2000 


32.0 


32.081 


0.253 


50/50 


158 


2400 


38.4 


38.4 


- 


50/50 


132 


3600 


57.6 


57.6 


- 


50/50 


88 


4800 


76.8 


76.8 


- 


50/50 


66 


7200 


115.2 


115.2 


- 


50/50 


44 


9600 


153.6 


153.6 


- 


48/52 


33 


19200 


307.2 


316.8 


3.125 


50/50 


16 



Not*: 16x clock is used in asynchronous mode. In synchronous mode, 
rate. 



clock multiplier is 1x and duty cycle is 50%/50% for any baud 



INS2651 Operation 

GENERAL 

The transmitter section of the INS2651 performs 
parallel-to-serial conversion of data supplied to it from 
the system data bus. 

The receiver section of the INS2651 performs serial-to- 
parallel conversion of data received from the MODEM or 
input/output device. Both the transmitter and receiver 
are double buffered, allowing a full character time in 
which t o service Transmit Ready (TxRDY) and Receive 
Ready (RxRDY) interrupts. 

The character size [5, 6, 7, or 8 bits) is prograt.i select- 
able. Parity check/generation and the baud rate may also 
be defined by the program. Note that the character size 
is exclusive of the start/stop and parity bits. 

SYNCHRONOUS MODE 

The transmitter starts transmitting a continuous bit 
strea m onc e the transmitter is enabled and the Clear to 
Send (CTS) input is low. If the system is late in supplying 
a character to the transmitter, then the transmitter will 
send the SYN character (or SYN1, two characters if in 
double SYNC mode) as an idle fill in the Non-Transparent 
mode, or the DLE-SYN1 character pair as an idle fill in 
the Transparent mode. If this condition occurs, the 
TxEMT/DSCHG output goes low. 

The receiver enters a character synchronization mode as 
soon as the receiver is enabled and the Data Carrier 
Detect (DCD) input goes low. Either one or two con- 
secutive SYN characters must be recognized by the 
receiver. The number of SYN characters is program 
selectable, and data is sent to the processor only after 



synchronization. The SYN character(s) in the Transparent 
mode (or DLE-SYN1 characters in the Non-Transparent 
mode) are stripped off the data stream after synchron- 
ization. This feature is program selectable. 

An overrun error will occur if the processor is late in 
servicing the received character. When this condition 
occurs, the character in the receiver buffer is written 
over by the character causing the overrun, and the 
overrun status bit is set. 

ASYNCHRONOUS MODE 

Once transmission is initiated, the transmitter supplies 
the start bit, odd, even, or no parity bit, and the proper 
number of stop bits as specified by the program. If the 
next character is presented to the transmitter, it is sent 
immediately after transmission of the stop bit of the 
present character. Otherwise the Mark (logic high) 
condition is sent. The transmitter can be programmed to 
send a Space (logic low) condition instead of the Mark 
condition. 

Once the receiver is enabled, reception of a character is 
initiated Dy recognition of the start bit. The Start/Stop 
and Parity bits are stripped off while assembling the 
serial input into a parallel character. If a break condition 
is detected then the receiver sends a character of all zero 
bits and a Framing Error status bit to the processor. 

Succeeding all-zero or break characters are not assembled 
and presented to the system. The Receive Data (RxD) 
input must return to a marking condition before 
character assembly is resumed. The overrun condition is 
checked in the same manner as in the Synchronous 
mode. 



CO 



Physical Dimensions 



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at any one anneal notace. It change saej c*cv*ry 



BAUDCLK 




A5 |T?>- 
A4 f3?>- 
A3 f!P>- 



4 



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A2 [8?>- 

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A0 [77>- 



LS 367 
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STROBE E> ' 



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SEL 



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ESTATVAL E»— 





INTERFACER3 174C ©1981 

COMPUPRO division GODBOUT ELECTRONICS 
Page 1 of 2 



ESTROBE 
U34-5 



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i 1 ^ 



pSTVAL 



ee> HMj^y 



pSYNC [7?^>- 



32 



TxRDYJI 



13 



U42 



TxRDYl t> 
TxRDY2 



9 
U42 

TxRDY3 B»— 
TxRDY4 '^- § - 



TxRDY5 I> 
TxRDY6 



TxROY7 t> 



37l^ i 



IN2 X>- 



^ 



OJ42 



15: 



U37 



■*»■ D2 

■*» D3 



-O 04 



D5 
06 
D7 



RxRDYl C*- 
RxRDY? C«- 5( 
RxRDY3 «*- 
RxRDY4l 
RxRDY5C»- 
RxRDY6l 



c^ <; "U56l 






USl 



RxRDY7 t*- 



INS &»- 



/<$jHl 



121 — ^.1 



nwp> 



-*> D0 
-OD1 
-OD2 
-OD3 
-O 04 



-O D5 
-C» 06 



-O D7 



0UT2 t» 




CLR O 4 ' 



0UT3 t» 




RxINTEN7 



CDJ B* 



TxINT0 C- 

TxINTl t>- 

TXINT2 O- 

TxINT3 O- 

TxINT4 O- 

TxINT5 ta- 

TxINT6 n* 

TxINT7 E>- 



10 



15 



015 



See pages 34 - 37 for pin numbers of each USART Channel 



D0 ES- 
DI O- 
02 O- 



D3 O- 

04 t>- 



D5 n»- 
D6 £3- 
D7 £»■ 



r 



CLRO 



BAUDCLKI 



28 



26 




20, 



vcc 

GND 



2 CHANNELS ONLY 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



RxC 



TxC 



2661 
2651 



A0 

Al 

R/W 

CE 

XR 



BRCLK 



TxEMT 
/DSCH6 



TxRDY 



RxRDY > 



£> 



{E> 



°<F 



^H^f 



.22 



{E> 



4^B 



• +12\ 



+ 12V <«-\A/W 



•-12V 



25 



o — cx^j- 



-t© — ° 



-dz> — • 



r*-6 O-j 




TxRDYx O- 
TxINTENx t>- 



o 



-OTxINTx 






RxINTENx O- 



RxINTx 



-j^O— O TxRDYx 



RxRDYx 



INTERFACER3 174C ©1981 

COMPUPRO division GODBOUT ELECTRONICS 

Page 2 of 2 



^Q> 



VI2_ 



^<Z> 



VI5 



S <E> 



-a RxINT0 
-<3 RxINTl 



-a RxINT4 




16V[5T>- 



7912 
Ul 



in T- 1 -t 



LI> 



-t— | Ulll*' +16V|JJ> f— U2 |"~|- 



7812 
U2 



: 'T 1 V 



D> 



7805 
U60 



7805 
U59 



X 



C8~T T"C7 C6~T T"C5 



T 1 T" 



1 



33 






USART 



■t r 



USART 1 



D4 E»- 
D5 O- 



D6 E>- 
07 Ca- 



r 



A0 E> 




BAUOCLKI 



20. 



vcc 

GND 



U28 
2661 
2651 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCO 



TxEHT 
/DSCH6 



RxRDY > 



.23 



18 



Tf^ 



/ U20 



^^k 



ii?JH _k K X_fc.+12V 



^r*^ 



/u20 *" . 



TxRDY0 C>- 

TxINTEN0 O- 



12 



"wjp- 



RxRDY0 O- 
RxINTEN0 ts- 

U43 



~^y 



TxINT0 



RxINT0 



T SR6 



lft>^ 



U57 



nfr^. 



TxRDY0 



RxROY0 



D0 E— 
Dl &- 



D2 Es~ 
D3 E»- 



D4 &- 

D5 E>- 

D6 O- 

D7 *=»- 



r 



A0 E»- 



CE1 1 
CLRJ 



BAUDCLKO- 



26 



12 



10 



20. 



VCC 
GND 



U27 
2661 
2651 



A0 
Al 

"r/w 

CE 
XR 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



TxEHT 
/DSCH6 



TxRDY 



15 






«^ 



^EX 






^r^> 



TxRDY I O— 
TxINTENl e- 



r U40^ 



RxRDY I O- 
RxINTENI O- 



10 



^ 



TxIHTI 



RxINTI 



U43 



T SR6 



^iT»l£-C» TxRDY I 
5V „ r , 



U57 



4>t-~ 



5V 



k............... .............. .... ............ ...........rf k.............. .................. — ..... ... .............--.--' 



USART 2 



USART 3 



00 ES- 
DI t>- 



D3 E»- 
D4 t>- 



D6 O- 
D7 £»- 



r 



A0 C- 
Al C*- 



CLRO- 



28 



26 



10 



vcc 

GND 



U26 
2661 
2651 



A0 
Al 

■r/w 

CE 
XR 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



TxEMT 
/DSCH6 



TxRDY 



19 



.23 



17 



22 



24 



16 



{B^ 



<>&■ 



SE^ 



^^ 



^r^ 



+ 12V 



^»r** 



+ 12V 



{ny— 



TxR0Y2 B- 
TxINTEN2 E>- 



U40^> 



-O-TxINT? 



RxINTEN' o- 
U43 



^T)>IL 



-e» RxINTZ 



•— ^AA-^-+5V U5 7 

14 3 [\ 4 _ 

—p^ — ^~^ 

' — ^/V<-»- +5V 



TxRDY2 



D3 n>- 



D4 Ea- 
D5 C»- 



D6 O- 

U7 E»- 



r 



A0 Ea- 
Al O- 



SINP E*- 



12 



13 



20. 



VCC 
GND 



U25 
2661 
2651 



A0 

Al 

"R/H 

CE 

XR 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



TxEMT 
/DSCH6 



5 HJUV6 



2o<<LL 

53? 



-fg!s>fc 









TxRDY3 E»- 
TxINTEN3 D>- 



" U40j|>= 



RxINTEN3 o- 



_5_"u54^p 



J SR6 



-4^>>^ O TxRDY3 

U57 
HJ^X>^L^ RxRDY3 



-O RxINI 3 



w 
in 



CO 



USART 4 



■1 r .. 



USART 5 



D0 na- 
Dl o- 
D2 C>- 



D3 Ca- 

D4 E*- 
D5 E»- 



D6 O- 
D7 O- 



r 



27 



26 




20. 



vcc 

GND 



U24 
2661 
2651 



TxO 

RxD 

rts 

CTS 
DSR 
DTR 
DCD 



TxEMT 
/DSCH6 



RxROY * 



17 



22 



24 



16 



4 . . 

nrrr 
50 



ui2 



o<)i 



۩* 






+ 12V 



-5E* 



^■■r^ 



^r*~ 



_igy_ 



TxRDY4 Cs— 
TxINTEN4 O- 



_9_ "391^ 



TxINT4 



U8^»„V 



RxRDY4 O 
RxINTEN4 D> 

U36 
iLTNol2_c> TxR0Y4 



10 



EH 



-O RxINT4 



T SR5 

I— (\A/M^ + 



i!JNo^-C> RxR0Y4 



D0 e>- 

Dl c— 



D2 O- 



D3 ts- 
04 O- 



r 



A0 E>— 
Al &- 



sINP »- 



28 



12 



10 



20. 



VCC 
GNO 



U23 
2661 
2651 



A0 

Al 

"R/W 

CE 

XR 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



TxEMT 
/DSCH6 



RxRDY 3! 



22 






^E>ti 



ffifc 









TxRDY5 ts- 
TxINTEN5 n»- 



12 



3^ 



TxINT5 



RxRDY5 O- 
RxINTEN5 C»- 



13 



GEF- 



L^W^ +5V u50 

" 1 ! 

SR5 



£>o*U» 



.--_------------_-_____>______________>_____________-__-------------^ 



USART 6 



.., r 



USART 7 



D0 Ca- 
Dl E»- 
D2 O- 



03 &- 



D5 &- 
D6 O- 



r 



A0 E>- 



27 



12 



10 



13 



VCC 

GND 



U22 
2661 
2651 



A0 

Al 

"R/W 

CE 

XR 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



^^GfEH 



TxEMT 
/DSCH6 



RxRDY * 



22 



rV\8 
>ip °J°~ 



o<p 



8 S . R I +12 V 

4 



< ^§£i 



.15^ 



{£> 



^■r* 



2|U^ VI 



/^ U8 SRl+12 



S_R1 +J2V 



12, _ + 12V 

13 O 



R3 8 



14 



13 



10 



„ J12 (> _Jlo<£p 



J10 



13, Oil 



TxRDY6 Ca- 
TxINTEN6 Ca- 



3h 



-Ca» TxINT6 



T SR5 

+ 5V 



RxRDY6 Ca- 
RxINTEN6 J5>- 

U36 



]EDH 



RxINT6 



{>^- 



TxRDY6 



T SR5 



i-^-P^O 4 - C* RxRDY6 



00 ES- 
DI C9- 



D2 E>- 
D3 Ca- 



r 



A0 Ea- 



BAUDCLKEa- 



10 



20. 



VCC 

GND 



U21 
2661 
2651 



A0 
Al 

rVw 

CE 
XR 



TxD 
RxD 
RTS 
CTS 
DSR 
DTR 
DCD 



16 11 . 



TxC 



TxEMT 
/DSCH6 



RxRDY * 



19 



-GE> 



U4 
3^^1 1 



.23 






. U4 SRI +12V 
^J J?5 + 12V 



25 



B^ 



^r^ 



u4 5J*il21 v 



o^r*^ 



R4 
+ 12V •♦VW- 



16 



10 



9 Rl 



J 8 , U6 ^, i 

o^>^[-L 



4, v J7 



b UD 



o- J 



■12V 



TxRDY7 ta- 
TxINTEN7 ts- 



:Z5H 



TxINT7 




T SR5 



RxRDY7 ta- 
RxINTEN7 ta- 



:^> 



■i-TNo^ Ea. TxRDY7 



T SR5 

I — i\ft/v». + 



U50 



-----J ».._. --------__--_■__.___.. ._._. 



CO 



PARTS LIST 

INTEGRATED CIRCUITS (note: the following parts may have letters, 
suffixes and prefixes along with the key characters given below.) 



(1) 74LS00 quad 2 input NAND 

(1) 74LS02 quad 2 input NOR 

(5) 74LS04 hex inverter 

(1) 74LS10 triple 3 input NAND 

(4) 74LS38 quad 2 input NAND OC buffer 

(2) 74LS74 dual D flip flop 

(4) 74LS125 quad ® TRI-STATE buffer 

(2) 74LS138 3 to 8 line decoder 

(1) 74LS174 6 bit D type latch 

(4) 74LS175 4 bit D type latch 

(1) 74LS244 octal buffer 

(2) 74LS266 quad X-NOR 
(1) 74LS367 hex buffer . 

(1) 81LS95/97 octal buffer 

(9) 1488 TTL to RS-232 driver 

(9) 1489 RS-232 to TTL converter 

(8) 2651/61 USART 

(2) 7805 +5 volt regulator 
(1) 7812 +12 volt regulator 
(1) 7912 -12 volt regulator 

OTHER ELECTRONIC COMPONENTS 



(2) 1.2K resistor 1/4 watt 5% 

(1) 1.8K resistor 1/4 watt 5% 

(5) 4.7K resistor 1/4 watt 5% 

(6) 5. IK SIP resistor 10 pin 
(4) 2.7uF 20V dipped tant. caps 
(4) 39uF 10V axial tant. caps 
(1) .OluF ceramic disc cap 

(39) .OluF ceramic disc cap 

(1) 5.0688 MHz crystal 

MECHANICAL COMPONENTS 

(60) low profile sockets 

(1) 8 position DIP switch 

(2) small TO-220 heat sink 
(2) large TO-220 heat sink 
(4) set #6 hardware 

(2) 26 pin transition connector 
(2) 50 pin transition connector 
(2) 12 pin post assembly 

(1) 3 pin post assembly 
(10) post shunt 

(2) 16 pin DIP shunt 
(2) 16 pin DIP header 

ADDITIONAL ITEMS 

(1) Circuit board #174B 

(1) User's Manual 



U45 

U30 

U29,36,43,50,57 

U32 

U39,40,53,54 

U31,33 

U37,42,51,56 

U35,49 

U34 

U38,41,52,55 

U44 

U46,47 

U47 

U58 

U3,5, 7,9, 11, 13, 15, 17, 19 

U4, 6, 8, 10, 12, 14, 16, 18, 20 

U21-28 

U59,60 

U2 

Ul 



R7,8 

R6 

Rl-5 

SR1-6 

Cl-4 

C5-8 

C9 



XI 



SI 



JA,JB 
JC,JD 
J3-14 
J17 

Jl,2 
J15,16 



* May be supplied already soldered to the board. 



38 




COMPONENT LAYOUT 






IF YOU NEED ASSISTANCE ALWAYS CONTACT 
YOUR COMPUPRO DEALER FIRST 

CUSTOMER SERVICE INFORMATION 

Our paramount concern is that you be satisfied with any Godbout 
CompuPro product. If this product fails to operate properly, it may be 
returned to us for service; see warranty information below. 

If you need further information feel free to write us at: 

Box 2355, Oakland Airport, CA 94614-0355 

LIMITED WARRANTY INFORMATION 

Godbout Electronics will repair or replace, at our option, any parts 
found to be defective in either materials or workmanship for a period of 1 
year from date of invoice. Defective parts MUST be returned for 
replacement. 

If a defective part causes a Godbout Electronics product to operate 
improperly during the 1 year warranty period, we will service it free 
(original owner only) if delivered and shipped at owner's expense to and 
from Godbout Electronics. If improper operation is due to an error or 
errors on the part of the purchaser, there may be a repair 
charge. Purchaser will be notified if this charge exceeds $50.00. 

We are not responsible for damage caused by the use of solder in- 
tended for purposes other than electronic equipment construction, 
failure to follow printed instructions, misuse or abuse, unauthorized 
modifications, use of our products in applications other than those in- 
tended by Godbout Electronics, theft, fire, or accidents. 

Return to purchaser of a fully functioning unit meeting all advertised 
specifications in effect as of date of purchase is considered to be com- 
plete fulfillment of all warranty obligations assumed by Godbout 
Electronics. This warranty covers only products marketed by Godbout 
Electronics and does not cover other equipment used in conjunction 
with said products. We are not responsible for incidental or conse- 
quential damages. 

Prices and specifications are subject to change without notice, owing 
to the volatile nature and pricing structure of the electronics industry. 



"INTERFACER 3" is a trademark of W.J. Godbout. 

"TRI-STATE" is a trademark of National Semiconductor Corp. 

"IN2651 PROGRAMMABLE COMMUNICATIONS INTERFACE", 1980, 
Copyright 1980, National Semiconductor Corp. Reprinted by 
permission of National Semiconductor Corp. 

Copyright 1981, 1982 by Godbout Electronics. All rights reserved. We 
encourage quotation for the purposes of product review if source is 
credited. Printed in U.S.A. 

COMPUPRO A GODBOUT COMPANY • 3506 BREAKWATER CT, HAYWARD CA 94545