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CDP-8KX16 
MAGNETIC CORE MEMORY 
(P/N C85500000) 

TECHNICAL MANUAL 
C21518001-X3 




California data processors 



2019 south ritchey street • santa ana, caKfornia 92705 • (714) 558-82T1 



CDP-8KX16 
MAGNETIC CORE MEMORY 
(P/N C85500000) 

TECHNICAL MANUAL 
C21518001-X3 



DOCUMENT C2 15 18001 

Revision X3 

September 1974 



Cal Data, MACROBUS and HEXBOARD are trademarks of 
California Data Processors 




© copyright 1974 califomia data processors $7.00 



REVISIONS 



Revision 

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Date 

12-21-73 

2-1-74 

9-12-74 



Approval 




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Description 

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New Repro 



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C21518001-X3 



CONTENTS 



Page 



SECTION 1; INTRODUCTION 

1.1 PURPOSE AND SCOPE 1-1 

1.2 DOCUMENTATION 1-1 

1.2.1 Pxoblications 1-1 

1.2.2 Abbreviations and Conventions 1-2 

SECTION 2; DESCRIPTION 

2.1 GENERAL 2-1 

2.2 FUNCTIONAL DESCRIPTION 2-1 

2.2.1 Operating Modes 2-3 

2.2.1.1 Read/Restore (DATI) 2-3 

2.2.1.2 Half-Cycle Read (DATIP) 2-3 

2.2.1.3 Clear/Write CDATO) and Clear/Write Byte CDATOB) . . . 2-3 

2.2.2 Interleaved Modules 2-4 

2.2.3 7K-Word Option 2-4 

2.2.4 Other Features 2-5 

2.3 PHYSICAL DESCRIPTION 2-5 

2.4 SPECIFICATIONS 2-9 

SECTION 3; INTERFACE 

3.1 GENERAL 3-1 

3.2 INTERFACE DESCRIPTION 3-1 

3.2.1 Interface Signals 3-1 

3.2.2 Control Modes 3-3 

3.3 INTERFACE TIMING 3-3 

3.3.1 Read/Restore (DATI) 3-3 

3.3.2 Clear/Write (DATO) and Clear/Write byte (DATOB) 3-5 

3.3.3 Half-Cycle Read (DATIP) 3-5 

3.4 INTERFACE CITCUITS 3-6 

3.4.1 Line Driver 3-6 

3.4.2 Line Receiver 3-6 

3.4.3 Bus Loading 3-6 

SECTION 4; INSTALLATION 

4.1 GENERAL PROCEDURES 4-1 

4.1.1 Unpacking and Inspection 4-1 

4.1.2 Handling 4-2 

4.1.3 Address Strapping 4-2 

4.2 INSTALLATION IN THE PDP-11/05 OR PDP-11/10 4-4 

4.2.1 24K-Word Configuration lA 4-6 

4.2.2 16K-Word Configuration IB 4-8 

4.2.3 16K-Word Configuration IC 4-10 

4.2.4 16K-Word Configuration 2A 4-12 



C21518001-X3 



^ 



Page 
SECTION 4: CContlmied) 

4.2.5 16K-Word Configuration 2B.. . , 4-14 

4.2.6 8K-Word Configuration 2C 4-16 

4.3 INSTALLATION IN THE PDP-11/35, PDP-11/40 OR PDP-11/45 4-18 

4.3.1 32K-Word Configuration 1 4-24 

4.3.2 32K-Word Configuration 2 . , 4-26 

4.3.3 24K-Word Configuration 1 4-28 

4.3.4 24L-Word Configuration 2 , 4-30 

4.4 INSTALLATION IN THE CAL DATA CHASSIS , 4-32 

SECTION 5; MAINTENANCE 

5.1 GENERAL , , 5-1 

5.2 PREVENTIVE MAINTENANCE 5-1 

5.3 CORRECTIVE MAINTENANCE 5-1 

5.3.1 Test Program 5-1 

5.3.1.1 Program Description 5-2 

5.3.1.2 Loading, Starting and Riinning 5-2 

5.3.1.3 Error Printouts 5-4 



APPENDIX 

Page 
APPENDIX A: INTERFACE PIN ASSIGNMENTS A-1 




^^ ._■■■- C21518001-X3 



TABLES 



Table Title 



Page 



1-1 Abbreviations 1-2 

2-1 CDP-8KX16 Memory General Specifications 2-9 

3-1 MACROBUS Signal Definitions. . . . , 3-2 

3-2 CDP-8KX16 Operating Modes 3-3 

4-1 Jvmipers for CDP-8KX16 Block Starting Addresses 4-3 

5-1 Test Program SWITCH REGISTER Switch Settings 5-3 

A-1 CDP-8KX16 Interface Pin Assignments, Connectors A and B A-1 

A-2 CDP-8KX16 Power and Bus-Grant Pin Assignments, Connectors 

D and F A-2 



ILLUSTRATIONS 



Figure Title 



Page 



2-1 CDP-8KX16 Magnetic Core Memory, Component Side ..,.,,... 2-2 

2-2 CDP-8KX16 Magnetic Core Memory, Mechanical Outline 2-6 

2-3 CDP-8KX16 Magnetic Core Memory, Core-Plane Side 2-7 

2-4 CDP-8KX16 Magnetic Core Memory, Core-Plane Assembly 2-8 

3-1 CDP-8KX16 Memory Interface Timing 3-4 

4-1 DEC PDP-11/05 and PDP-11/10 Standard Module Utilization 

Configuration 1 C16K) 4-5 

4-2 DEC PDP-11/05 and PDP-11/10 Standard Module Utilization 

Configuration 2 C8K) 4-5 

4-3 24K-Word Configuration lA 4-7 

4-4 16K-Word Configuration IB 4-9 

4-5 16K-Word Configuration IC 4-11 

4-6 16K-Word Configuration 2A 4-13 

4-7 16K-Word Configuration 2B 4-15 

4-8 8K-Word Configuration 2C 4-17 

4-9 PDP-11/40 Mounting Box 4-19 

4-10 PDP-11/40 Multiple-Module Installation 4-20 

4-11 PDP-11/40 Backplane Connector Scheme 4-21 

4-12 DEC Assembly Utilization (24K) 4-23 

4-13 32K-Word Configuration 1 4-25 

4-14 32K-Word Configuration 2 4-27 

4-15 24K-Word Configuration 1 4-29 

4-16 24K-Word Configuration 2 4-31 

4-17 Typical Cal Data Chassis Layout 4-33 

A-1 CDP-8KX16 Interface Connector Layout A-3 



C21518001-X3 




111 



SECTION 1 
INTRODUCTION 



1.1 PURPOSE AND SCOPE 



This manual provides the information needed to understand, install and 
maintain the CDP-8KX16 Magnetic Core Memory when used with the drawing 
package provided. The information in this manual is for the use of a 
skilled technician familiar with standard test equipment, solid-state 
logic theory, common maintenance practices and standard troubleshooting 
techniques. A basic knowledge of design principles and circuits used in 
CO incident- current core memories is assumed, hence no tutorial material 
of this kind is included. An understanding of the computers in which the 
CDP-8KX16 may be used is also assumed. Detailed information about these 
computers is available in published manuals. 

As a stand-alone publication, this manual has a good functional eind 
physical description of the CDP-8KX16, providing the information needed 
to understand the capabilities and optional features of the memory and to 
plan a system using it. The maintenance coverage of this manual is com- 
mensurate with the prerequisite skills and knowledge of the defined user, 
characteristics of the product and maintainability requirements estab- 
lished by Cal Data. 

Users holding controlled copies will be provided with revisions and 
additions to this manual. 



1 . 2 DOCUMENTATION 



Cal Data products covered in this manual include: 

85000 Standard CDP-8KX16 

85001 Interleaved CDP-8KX16 

85002 CDP-8KX16 with 7K-word option 

The following paragraphs define publications and conventions that support 
this manual. 



1.2.1 Publications 



The Cal Data MACROBUS is described in publication C21518013, MACROBUS Channel 
Adapter Technical Manual. 

For maintenance purposes, this manual is supported by a drawing package 
that contains theory of operation, schematic diagrams, assembly drawings 
and other required engineering drawings. 




C21518001-X3 Ol^ 1-1 



1.2.2 Abbreviations and Conventions 

Table 1-1 lists the abbreviations found in this manual. 

Conventions used in the text of this manual include: 

a. Equipment panel nomenclature is reproduced in all upper case 
characters . 

b. The proper names of instructions, microcommands and signals are 
capitalized. 

c. ZERO and ONE are used to express binary logic "0" and "1" states, 
respectively . 

d. Octal numbers are preceded by a dollar sign for easy identifi- 
cation. Decimal and binary numbers are not prefixed. 

Table 1-1. Abbreviations 



Abbreviation 


Meaning 


Cal Data or CDP 


California Data Processors 


A 


ampere 


cm 


centimeter 


dc 


direct current 


I/O 


input /output 


K 


1,024 memory locations 


Ifm 


linear feet per minute 


1mm 


linear meters per minute 


mA 


milliampere 


ns 


nanosecond 


MA 


microampere 


V 


volt 


DMA 


direct memory access 


MMU 


memory management unit 



1-2 




C21518001-X3 



SECTION 2 
DESCRIPTION 



2 . 1 GENERAL 



The CDP-8KX16, shown in Figure 2-1, is a plug-compatible storage element 
for the Cal Data and PDP-11 series of computers. The CDP-8KX16 offers 
several outstanding features and advantages. These include: 

High speed . The 2 75- nanosecond access and 675-nanosecond cycle times 
offer a fast core memory system for the PDP-11 series. 

Full compatibility . The CDP-8KX16 can be installed in all Cal Data 
and PDP-11 models, thus eliminating the need for different versions 
or expensive, space- consuming auxiliary mounting boxes, power 
supplies and interface cables. 

Reduced bus loading . The Cal Data memory has a low MACROBUS (and 
UNIBUS) load specification, permitting expansion in large system 
configurations . 

Low power consumption . The dc power consiomption of the CDP-8KX16 is 
lower thcin comparable memory modules available. 

7K-word option . This option permits Cal Data and PDP-11 systems to 
be expanded to 31K words (versus 28K words) without addition of a 
memory management unit. Only IK rather than 4K word locations are 
reserved for I/O device addresses. (The system can be expanded to 
12 7K words of addressable memory with the optional CDP-MMU Memory 
Management Unit. ) 

2.2 FUNCTIONAL DESCRIPTION 

The CDP-8KX16 is a random-access, coincident-current ferrite core memory, 
arranged in a "three-wire, 3-D" configuration. The capacity is 8,192 
words of 16 bits each. The CDP-8KX16 consists of: 

a. A single full-size printed circuit board containing the memory 
electronic circuitry. 

b. A plug-in magnetic core-plane board. 

The CDP-8KX16 can be operated in one of four modes: 

a. Read/restore (equivalent to PDP-11 DATI) . 

b. Half-cycle read (equivalent to PDP-11 DATIP) . 

c. Clear/write (equivalent to PDP-11 DATO) . 

d. Clear/write byte (equivalent to PDP-11 DATOB) . 

The full memory cycle (clear/write or read/restore) time is 675 nano- 
seconds for the worst case, measured at the memory interface connector. 
The worst case read-data access time is 275 nanoseconds. 

Since the CDP-8KX16 is directly compatible with the PDP-11 computer 
series, the memory interface follows all rules of the standard UNIBUS. 



C21518001-X3 ^BP 2-1 






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2-2 




C21518001-X3 



The CDP-8KX16 is a functionally complete module and requires no addi- 
tional supporting electronics (other than dc power) for operation in a 
MACROBUS (or UNIBUS) interface environment. 

The CDP-8KX16 is addressed by a set of 18 address lines. In the standard 
configuration, each CDP-8KX16 module in a system uses the least-signifi- 
cant 14 bits of the address for byte or word selection. The least- 
significcint bit (AOO) selects either the more-significant (even) or less- 
significant (odd) data byte for modification during a clear/write-byte 
operation (DATOB) . The most-significant four address bits select one of 
16 possible module starting addresses, which can be between and 120K 
in 8K increments. A plug- in address header asseinbly provided with each 
CDP-8KX16 patches the desired starting address. 

In addition to the standard configuration described above, two optional 
configurations are available: 

a. Interleaved modules 

b. 7K-word option 

2.2.1 Operating Modes 

2.2.1.1 Read/Restore (DATI) 

In a read/restore operation, the CDP-8KX16 reads information from a 
selected core location, transfers it to the MACROBUS and then writes the 
information back into the core location. Restoring is necessary, since 
the process of reading a core location erases the contents. 

During the read cycle of the operation, the CDP-8KX16 loads the accessed 
information into a register while applying it to the MACROBUS. 

During the restore cycle of the operation, the CDP-8KX16 writes the 
information held in the register back into the selected location. 

2.2.1.2 Half-Cycle Read (DATIP) 

In a half -cycle read operation, the CDP-8KX16 reads information from a 
selected core location, transfers it to the MACROBUS and then pauses. 

Diaring the read cycle, the CDP-8KX16 loads the accessed information into 
a register while applying it to the MACROBUS. Data are provided to a 
master device for modification prior to being restored in the same loca- 
tion. The half-cycle read operation should be followed by a write 
operation (DATO or DATOB) , since any other siibsequent operation leads to 
a memory error and can prevent proper operation of the MACROBUS. 

2.2.1.3 Clear/Write (DATO) and Clear/Write Byte (DATOB) 

In a clear/write operation, the CDP-8KX16 reads infoinnation from a 
selected core location, discards the information and then writes into the 
selected location the information provided on the MACROBUS. The read part 
of the cycle is necessary to clear the specified location prior to 
writing new data. If the clear/write operation is specified after a half- 



C21518001-X3 /Ulfi^ 2-3 



^ 



cycle read operation (DATO following DATIP) , the read cycle of the 
operation is not performed, reducing the operation time by about 50 per- 
cent. Regardless of whether the clear/write operation is commanded 
independently or after a half-cycle read operation, the data to be stored 
are loaded into a register immediately on receipt of the command. Any 
information previously stored in the register is lost. During the write 
cycle of the operation, the CDP-8KX16 writes the information held in the 
register into the selected location. 

A clear/write byte operation is identical to a clear/write operation, 
except that only the byte to be stored is loaded into a register 
immediately on receipt of the command. Any information previously stored 
in that half of the register is lost. The other half of the register 
always contains the retained byte previously read from the selected loca- 
tion. The write cycle of the operation is identical for both clear/write 
operations . 



2.2.2 Interleaved Modules 



A pair of CDP-8KX16 modules can be set for interleaved operation in which 
words at even and odd word addresses are written into or read from alter- 
nate modules. A clear or read operation can begin in one module while a 
write or restore operation is being completed in the alternate module, 
giving a higher effective memory-transfer rate. This configuration is 
prepared by interchanging the least-significant word-address bit (AOl) 
with the least-significant module-address bit (A14) . 

Interleaving is always associated with a pair of CDP-8KX16 modules , and 
the interleaved pair is effectively treated as a contiguous series of 16K 
word (32K byte) locations. Interleaved CDP-8KX16 modules must be ordered 
in this configuration. 



2.2.3 7K-Word Option 



The basic Cal Data and PDP-11 computer systems limit, by convention, the 
number of usable memory locations to 28K. The last 4K locations (out of 
a maximum of 32K) are reserved for I/O device addresses other than core 
memory. Expansion of addressable memory from 28K to 124K requires add- 
ition of a memory management unit. 

In some systems, IK is adequate for nonmemory I/O devices. The Cal Data 
7K-word option permits addressable memory expansion to 31K (versus the 
usual maximum of 28K) without requiring the addition of a memory manage- 
ment unit. With a memory management unit installed, the 7K-word option 
permits addressable memory expansion to 127K. 




2-4 Ol^ C21518001-X3 



2.2.4 Other Features 



The CDP-8KX16 permits retention of previously stored contents during a 
power-up or a power-down sequence. A dc power status signal (DCLO) indi- 
cating availability of properly regulated dc power is supplied to the 
CDP-8KX16 on one of the interface pins. A low signal disables the select 
current drives to all memory locations and prevents erasure of data by 
spurious current pulses during a transient power condition. This dc 
power status signal is generated by the power supply when the CDP-8KX16 
is used in a compatible computer environment. 

Voltages required for memory operation are +5 Vdc and -15 Vdc. No 
special sequencing of these voltages is required by the CDP-8KX16. 



2.3 PHYSICAL DESCRIPTION 



The CDP-8KX16 (Figures 2-1 and 2-2) is contained on a drive electronics 
board having overall outline dimensions of 15.7 inches (39.9 cm) by 8.9 
inches (22.7 cm). The drive board contains AMP Mod. 1 recepticles into 
which the core-plane assembly plugs from the back side of the board 

(Figure 2-3) . The core-plane assembly is shown in Figure 2-4. The over- 
all depth of the CDP-8KX16 assembly with core-plane installed is 0.9 inch 

\ ^ . ^ cm> . 

The drive board contains all electrical circuits of the memory except the 
steering diodes associated with the core-plane X and Y drive lines. The 
core-plane assembly is a planar array of magnetic cores mounted on a sub- 
strate, with a protective cover plate. The core-plane board also con- 
tains the X and Y drive-line steering diodes and current-probe test 
loops. The core-plane assembly is electrically connected by AMP pins to 
the drive board. 

On the top right-hand edge of the board, a 0.2 by 5.3 inch (0.4 by 13.5 
cm) indentation permits a flat I/O cable to exit the rear of the chassis 
over the top of the boeird. 

CDP-8KX16 modules should normally be mounted nearest to the CPU inside 
the chassis, since I/O device cables are most easily routed outside from 
the rear of the chassis. 

The right-hand edge of the board has a 1.0 by 5.5 inch (2.5 by 14.0 cm) 
cut out as clearance for the side-mounted cooling fans in the Cal Data, 
PDP-11/15 and PDP-11/20 computers, as well as the DEC BAll-EC and BAll-ES 
extension mounting boxes. When the CDP-8KX16 is installed in a PDP-11 
model 05, 10, 35, 40 or 45, a board adapter can be inserted into the cut- 
out area to provide a continuous edge for mating with the card guides of 
these computers. 




C21518001-X3 ^i^ 2-5 



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C21518001-X3 



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Figure 2-4. CDP-8KX16 Magnetic Core Memory, Core-Plane Assembly 



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pii: 



C21518001-X3 



2.4 SPECIFICATIONS 



General specifications for the CDP-8KX16 are given in Table 2-1. 
Table 2-1. CDP-8KX16 Memory General Specifications 



Characteristic 



Type 

Organization 
Word length 
Storage capacity 
Operating times: 

Read/restore (DATI) 
Read (DATIP) 
Clear/write (DATO) 
Half-cycle write 

Interface signals: 
High (False) 
Low (True) 
Input current 

Power: 

+5 Vdc 
-15 Vdc 

Ambient teit5)erature 

Ambient humidity 

Dimensions 

Mounting centers 



Specification 



Ferrite magnetic core, random access, coincident 
current. 

3-wire, 3-D planar core array. 

16 bits. 

8,192 words (16,384 bytes) . 



Cycle Time (1) 
Noninterleaved Interleaved (2) 



675 ns 
275 ns 
675 ns 
425 ns 

Input 

+2.5 V min 
+1.4 V max 
+120 yA max 
at 2 . 5 V 

Operating (3) 

Amperes 

2.8 
4.4 



425 ns 
275 ns 
340 ns 
450 ns 

Bidirectional 
+2.5 V min 
+1.4 V max 

+ 120 viA max 

at 2.5 V 

Standby (3) 

Amperes 

1.80 
0.34 



Access Time (1) 

275 ns 
275 ns 



Output 

+0.5 V max at 50 mA 
+120 MA max at 2.5 V 

Voltage 
Tolerance 

±5% 
±5% 



to 50°C with 200 Ifm (56.6 Imra) airflow. 

to 90 percent without condensation. 

8.9 by 13.2 by 0.9 inches (22.7 by 33.6 by 2.2 cm). 

1 inch (2.5 cm) recommended minimum. 



Notes: 
1. 
2. 



Worst case, measured at the CDP-8KX16 module interface connector. 
Effective cycle time for sequential access to contiguous interleaved 
memory locations . 

Maximiim current drain for continuous operation. For noninterleaved 
operation, only one memory module in the system is operating at a time. 
The others are on standby. If two CDP-8KX16 modules are interleaved, 
both should be considered as operating for power calculations . 



C21518001-X3 




2-9 



SECTION 3 
INTERFACE 



3 . 1 GENERAL 



This section describes the functional circuit design of the CDP-8KX16 and 
operation of the memory as an I/O device. The CDP-8KX16 conforms to all 
standard UNIBUS interfacing rules and interfaces equally well with the 
standard Cal Data MACROBUS or UNIBUS. This section assumes an under- 
standing of these I/O structures. Detailed MACROBUS information is avail- 
able in other technical publications. 

3.2 INTERFACE DESCRIPTION 

The CDP-8KX16 connects either to the MACROBUS or UNIBUS as a standard 
peripheral device. It always operates as a slave device (i.e., the 
memory never takes control of the bus as a master device). Thus, all 
transfers are controlled by a bus master, such as the CPU or a direct- 
memory-access controller. 

The memory is designed to plug into a single standard hex-height connector 
row; however, the unit plugs into only connectors A, B, D and F. All 
functional interface signals used by tfie memory terminate on the A and B 
connectors, with standard pin assignments used. Bus Grant signals are not 
used by the memory module; however, these signals are jumpered through the 
D connector via etched lines on the board so that these priority interrupt 
lines are automatically propagated with the memory installed. 

If a memory is removed from a location and no new board is installed, the 
Bus Grant lines must be jumpered on the connector if other I/O devices 
are operating on any of the priority interrupt lines. The D and F con- 
nectors are used for power and ground connection to the memory module. 

The CDP-8KX16 decodes the 18-bit address transmitted on the MACROBUS when 
a Master Synchronization signal (MSYN) is asserted by the device in con- 
trol of the bus (bus master) . If the address corresponds to the 
CDP-8KX16 module address, the CDP-8KX16 responds by executing the opera- 
tion specified by the mode Control lines (CO, Cl) and asserting a Slave 
Synchronization signal (SSYN) on the MACROBUS to indicate acceptance or 
availability of data. 

3.2.1 Interface Signals 

Table 3-1 lists the mnemonic, name and description of each MACROBUS signal 
used by the CDP-8KX16. Signals not required for memory operation are 
ignored (open circuit) ; however, there are certain signals associated with 
chained priority operations on the MACROBUS that require physical line 
continuity through the interface connectors, whether or not the interface 
device uses the signals. The CDP-8KX16 ensures continuity of these sig- 
nals, when installed, by propagating the necessary signal lines via etched 
conductors on the circuit board. If a memory module is removed from the 



C21518001-X3 ^fi^ 3-1 




Table 3-1. MACROBUS Signal Definitions 



Mnemonic 


Name 


Description 


Memory Use 


A17 to AOO 


Address 


Selects slave 


A17 to A14 select mod- 






device . 


ule? A13 to AOl select 
word; AOO selects byte. 


D15 to DOO 


Data 


Word or byte 
transferred. 


Data in or out. 


CO and Cl 


Control 


Selects mode. 


Operation performed. 


MSYN 


Master 


Initiates operation. 


Gates in A, D and C 




Synchroni zation 




signals. 


SSYN 


Slave 


Response to MSYN. 


Signals acceptance or 




Synchronization 




availability of data. 


PA 






Reserved. 


PB 






Reserved. 


NPR 


Nonprocessor 


Highest-priority 


Ignored. 




Request 


bus request. Not 
used for interrupts. 




BR7 to BR4 


Bus Request 


General bus request 
where CPU interrupts 
are involved . 


Ignored. 


NPG 


Nonprocessor 


Grant response to 


Ignored. 




Grant 


NPR. 




BG7 to BG4 


Bus Grant 


Grant response to 
BRn. 


Propagated , ignored . 


SACK 


Selection 


Acknowledges bus 


Ignored. 




Acknowledgement 


grant. 




BBSY 


Bus Busy 


Asserts bus 
mastership. 


Ignored . 


INTR 


Interrupt 


CPU interrupt noti- 
fication sent with 
interrupt vector 
address . 


Ignored. 


INIT 


Initialize 


Clear and reset. 


Initializes memory. 


ACLO 


AC Low 


Impending power 
failure • 


Ignored. 


DCLO 


DC Low 


DC voltages out of 


Protects memory 






tolerance. 


contents . 



3-2 



<^^ 



C21518001-X3 



system, these signal lines must be closed by jumper wiring or other means 
If another board is not physically located in the vacated connector slot. 

Appendix A lists interface pin assignments. 
3.2.2 Control Modes 

The CDP-8KX16 operates in one of four modes (Table 3-2) specified by bus 
Control lines CO and Cl. In modes requiring a byte operation (DATOB) , 
address bit AOO specifies the byte affected. 

Table 3-2. CDP-8KX16 Operating Modes 



AOO 



Cl 






1 

1 



CO 





1 



1 



Command 



DATI 
DATIP 
DATO 
DATOB 0* 

DATOB 1* 



Operation 



read/restore 

half-cycle read 

clear/write 

read/restore byte 1, 
clear/write byte 

read/restore byte 0, 
clear/write byte 1 



*Byte = less-significant; byte 1 = more-significant, 



CDP-8KX16 logic forces the operation immediately following DATIP to be a 
half-cycle write operation. The bus master initiates DATO or DATOB after 
DATIP, and these commands are interpreted by the memory logic as half- 
cycle write operations. 



3 . 3 INTERFACE TIMING 



Figure 3-1 shows interface timing for the basic CDP-8KX16 operations. 
The direction of data transfer is given with respect to the bus master 
rather than to the CDP-8KX16. Thus, data input implies a transfer to the 
master (output from the CDP-8KX16) , and vice versa. 



3.3.1 Read/Restore (DATI) 



The CDP-8KX16 reads a 16-bit word from the location designated by the in- 
put address and places the word on the MACROBUS. The word is also 
restored automatically by the CDP-8KX16. 

As shown in Figure 3-1, the Address and Control lines (A17 to AOO, CO and 
Cl) must be settled at the CDP-8KX16 at least 50 nanoseconds prior to 
receipt of MSYN to permit decoding of these signals. Data (16-bit word) 
read from memory and SSYN are placed on the bus within a maximum of 275 
nanoseconds from receipt of MSYN. The addressed word is restored during 
the next 400 nanoseconds. Address and Control signals received at 625 



C21518001-X3 



^ 



3-3 



NANOSECONDS 



600 



000 



200 



400 



600 



000 



DAT I 



DATO 

or 

DATOB 



DAT IP 



DATO 
after 
DAT IP 



A17 to AOO, 
CO, CI 

MSYN 

SSYN 

D15 to DOO 



^S)C 



A17 to AOO, 
CO, CI 

D15 to DOO 

MSYN 

SSYN 



50 
MIN 



A 



^ssc 



s^s>c 






275 
MAX 



100 
MAX 



"' *° «"• S^( 



CO, CI 
MSYN 



SSYN 



D15 to DOO 



A17 to AOO, 
CO, CI 

D15 to DOO 

MSYN 
SSYN 



A 



A. 



-TT 
X 



y 



/ 



7 



/■ 



»C 



J 



A. 



^®C 



^S)C 



100 
MAX 



275 
MAX 



X^SK 



>^\\\\\ \\VV\VW ^ 



V\\\\\\ \\\\\\\V\ \^ 



\ 



/" 



J 



J 






XSSSSS^S 



\ 



>S^^^^5 



)S^^^SSS 



f 



f 



Figure 3-1. CDP-8KX16 Memory Interface Timing 



3-4 




C21518001-X3 



nemoseconds, followed by a MSYN at 675 nanoseconds, result in a miniimam 
repetitive read/restore cycle of 675 nanoseconds. 

The CDP-8KX16 provides internal storage for the Address and Control sig- 
nals, hence it is not necessary to retain information on these lines 
throughout the cycle. The earliest recommended time for removing the 
Address and Control signals is 100 nanoseconds after MSYN is received. 
Because of the asynchronous nature of the MACROBUS, the bus master has no 
indication that the memory operation has actually started until SSYN is 
received. Early removal of Address and Control signals is not useful in 
this case, but other applications could make use of this feature. 

The operation timing shown represents the guaranteed worst-case and, in 
general, the CDP-8KX16 operates faster than specified. MSYN can be 
reasserted within 150 nanoseconds after it has been removed in response 
to SSYN, provided that the Address and Control signals have been estab- 
lished at least 50 nanoseconds earlier. 

3.3.2 Clear/Write (DATO) and Clear/Write byte (DATOB) 

For DATO, the CDP-8KX16 clears the location designated by the address 
lines and writes into that location the 16-bit word received from the 
MACROBUS . 

As shown in Figure 3-1, the Address, Control and Data signals must be 
settled at the interface connector at least 50 nanoseconds prior to 
receipt of MSYN to permit decoding of the Address and Control signals, 
and storing of the data. SSYN is asserted on the MACROBUS within 100 
nanoseconds after MSYN is recognized. The clear/write operation internal 
to the memory requires 675 nanoseconds, maximum. 

MSYN can be reasserted within 150 nanoseconds after it is removed in 
response to SSYN, provided Address and Control signals are settled at 
least 50 nanoseconds earlier. The CDP-8KX16 generally operates at a 
speed higher than specified. 

Timing for the clear/write-byte operation (DATOB) is identical to that 
for DATO. Functionally, the CDP-8KX16 clears and writes only the desig- 
nated byte (odd or even) . A read/restore operation is performed on the 
other byte. 

3.3.3 Half-Cycle Read (DATIP) 

The CDP-8KX16 reads a 16-bit word from the location designated by the 

input address and places the word on the MACROBUS along with SSYN. The 

word read out is not restored, but is held in the memory data register. 

Access timing at the interface is identical to that for DATI (Figure 3-1) . 

DATIP permits the word read out to be modified by the bus master and the 
modified word restored in the same location. The bus master must retain 
mastership until the modified word is restored. To ensure that proper 
design rules are followed, DATO and DATOB are the only commands permitted 
to follow DATIP. These operations can be initiated within 150 nano- 

C21518001-X3 «||^ "^"^ 



seconds (by reassertion of MSYN) after MSYN has been removed following 
the assertion of SSYN by the CDP-8KX16, provided that Address and Control 
signals are settled at least 50 nanoseconds earlier. Figure 3-1 shows 
the timing. 

The CDP-8KX16 automatically performs a half-cycle write operation in 
response to the next MSYN after a DATIP, regardless of the states of Cl 
and CO. 



3.4 INTERFACE CIRCUITS 



Because memories are attached to the MACROBUS as peripheral devices, 
the bus loading introduced by CDP-8KX16 is an important system consider- 
ation for configurations containing a large amount of memory or numerous 
peripheral devices. The CDP-8KX16 minimizes the loading of receivers and 
the leakage current of drivers in the high state (these being the critical 
bus-loading parameters). This is accomplished in two ways: 

a. The driver leakage load is limited to that of one gate instead 
of two (as is common in other designs) . 

b. A Cal Data proprietary bus receiver circuit improves speed and 
reduces drive requirements. 



3.4.1 Line Driver 



The line drive is a TTL buffer. The critical bus specifications for the 
device are: 

Output-low voltage at 50 mA +0.5 V, max 

sink (V^^) 

Output-high leakage current +60 yA, max 

at 2.5 V (I^^) 



3.4.2 Line Receiver 



The CDP-8KX16 uses a Cal Data line receiver. The critcal bus specifica- 
tions for this device are: 

Input-high threshold (V^.^) +2.5 V min 

Input-low threshold (V ) +1.4 V max 

XL 

Input current at +2.5 V (It„. +60 mA max 

IH) 

Input current at 0.0 V (1^.^ ) ±25 pA max 

XL 



3.4.3 Bus Loading 



The limiting bus load occurs on the bidirectional data lines that have 

one receiver and one driver for each CDP-8KX16 memory module. Worst-case 

module bus load specifications are: 

V +2 . 5 V min 

IH 

V__ +1.4 V max 

III 

I +120 pA max at +2.5 V 

IH 

I ±25 pA max at 0.0 V 

IL 



3-6 UV C21518001-X3 




SECTION 4 
INSTALLATION 



4.1 GENERAL PROCEDURES 



When used as part of a Cal Data system, the CDP-8KX16 will have been 
installed euid tested by Cal Data prior to shipment. Thus, the following 
procedures describe the installation of modules received individually for 
addition to an existing installation. 

The CDP-8KX16 core memory module is designed for direct installation in a 
Cal Data computer, in a CDP-EB Extension Box, a DEC BAll-EC or BAll-ES 
extension box or in any model computer of the PDP-11 series. 

Before installing the CDP-8KX16 in a PDP-11 computer, the user should be 
familiar with physical details of the applicable system, particularly the 
backplane (system-imit signal wiring and power distribution) . The 
CDP-8KX16 interfaces with the standard UNIBUS signals carried in the A 
and B connector columns of all PDP-11 series computers. The specific 
installation procedures vary with each model in the series, since the 
physical signal connector and power distribution schemes differ from 
model to model. 

The signal, power and ground connections to the CDP-8KX16 are made via 
the A, B, D and F connectors as given in Appendix A. For any given 

installation, compare this signal list against that of the backplane of 
system unit for the intended installation. 

The general installation procedure consists of inserting the CDP-8KX16 
into the appropriate connectors so that A and B plugs interface with the 
MACPOBUS (or UNIBUS) connectors. The component side of the CDP-8KX16 
drive board faces the same direction as the component side of the 
standard circuit boards. In a DEC chassis, the CDP-8KX16 core-plane, 
which plugs into the rear of the drive board, blocks the next connector 
slot, since standard PDP-11 connector rows are on half-inch centers and 
the CDP-8KX16 requires 0.9 inch (2.2 cm). This restriction does not 
apply to Cal Data chassis, which have one- inch (2.5 cm) memory slot 
separation. 

4.1.1 Unpacking and Inspection 

Each CDP-8KX16 is shipped in an individual, padded shipping container for 
protection during transportation. This container can be saved for future 
use if the unit is returned for repair or reshipped separately from the 
associated computer system. 

The following steps are recommended for unpacking and initially inspect- 
ing the memory: 

1. Prior to opening, inspect the container for obvious damage. 

2. Cut the packing tape, open the container and remove the module. 
Next remove the plastic wrapper and inspect the module for 
physical damage. 



C21518001-X3 MP>: 4-1 




3. Inspect the board connector pins for any foreign matter and 
clean, if necessary, for reliable contact with the connectors. 

It is important to note immediately any physical damage that might have 
resulted from shipment. The carrier should be notified of such damage 
and given the opportxmity to inspect the unit and container. This helps 
establish the validity of any claims for shipping insurance. 



4.1.2 Handling 



The CDP-8KX16 can withstand all normal shock and vibration encountered in 
shipping and when installed in a computer system. While not a fragile 
device, the unit should be handled with reasonable care to avoid damage 
that might result in operational failure. The following are some general 
pointers on handling the unit during inspection, installation and 
maintenance operations : 

a. The core stack plugs into the rear of the drive board and is held 
in place by safety nuts at several points on the stack assembly. 
These nuts should always be on and tight when the memory is 
installed in a system. 

b. When inserting the CDP-8KX16, be sure that the component 
side faces the correct direction and that the board is 
aligned in the card guides. 

DO NOT EXERT PRESSURE ON THE CORE-PLANE BOARD. 

c. Avoid bending components when handling the drive board. To 
prevent oxides from forming on the gold plating, do not touch the 
connector pins. 

d. Always insert and remove modules with the system power OFF. 

e. When inserting or removing the CDP-8KX16, be sure that the 
component side faces the correct direction and that the board is 
aligned in the card guides. 

f. Insert and remove the memory slowly and carefully so that it does 
not make contact with adjacent boards. 

g. Never use components as finger grips. Use the grip areas at the 
corners of the board. 



4.1.3 Address Strapping 



Each memory module in a system must have a different block starting 
address to prevent more than one unit responding to the same address from 
the CPU or DMA device (except for interleaved pairs, which have a common 
block starting address) . 

The CDP-8KX16 can be set to any starting address from to 120K in 8K 
increments. Interleaved modules can have starting addresses from to 
112K in 16K increments. 

Cal Data provides a memory address header assembly with each CDP-8KX16. 
This assembly can be delivered either prewired to a specified starting 
address, as defined in Table 4-1, or unwired, according to user specifi- 
cation. The assembly plugs into a socket on the board. This should be 
done prior to system installation. 



4-9 OK^ C21518001-X3 




Table 4-1. Jumpers for 


:ajP-8KXl6 Block Starting Addresses 






Block 
Starting 
AcMresses 


Cal Data Part Number 


Standard Module 


Module with 7K-Word Option 


Single 


Interleaved 


Single 


Interleaved 


Even 


Odd 


Even 


Odd 





56148015 


56148015 


56148016 








8K 


56148016 












16K 


56148017 


56148017 


56148018 




56148032 


56148030 


24K 


56148018 






56148030 






32K 


56148019 


56148019 


56148020 








40K 


56148020 












48K 


56148021 


56148021 


56148022 








56K 


56148022 












64K 


56148023 


56148023 


56148024 








72K 


56148024 












80K 


56148025 


56148025 


56148026 








BBK 


56148026 












96K 


56148027 


56148027 


56148028 








104K 


56148028 












112K 


56148029 


56148029 


56148034 




56148033 


56148031 


120K 


56148034 






56148031 







C21518001-X3 




4-3 



If the system contains a 4K-word memory unit, this xinit must be set to 
the highest block starting address in the system (i.e., 8K-word modules 
occupy block starting addresses 0, 8K, 16K, etc.). 

4.2 INSTALLATION IN THE PDP-11/05 OR PDP-11/10 

CDP-8KX16 modules can be installed directly in the PDP-11/05 or PDP-11/10 
chassis with or without an BK MMll-L memory. The information presented 
in this subsection is also applicable to installations in the PDP-11/35 
expansion chassis. 

There are two standard DEC configurations of the models 05 and 10, each 
with a different backplane: 

a. Configuration 1 is wired for 16K of memory with one small- 
peripheral controller slot (Figure 4-1) . 

b. Configuration 2 is wired for 8K of memory with four small- 
peripheral controller slots (Figure 4-2) . 

The following apply to those installations: 

a. The CDP-8KX16 is installed with components toward the top of the 
cabinet and the core-plane toward the bottom of the cabinet. The 
keyed connectors prevent reversing the board. 

b. Check the CDP-8KX16 for proper orientation (components up, core- 
plane down) before attempting to insert the board. Excessive 
force applied to a reversed board can result in damage to the 
backplane connectors. 

c. Always install and remove boards with the system power OFF. 

d. A UNIBUS terminator is placed at the end of the UNIBUS, either 
inside or outside the computer chassis. 

e. The Cal Data board adapter assembly should be installed on the 
CDP-8KX16 to make contact with the card guides of the chassis. 

CDP-8KX16 modules can be installed in various combinations with or with- 
out an MMll-L. No modification of the computer backplane is necessary 
and no electrostatic shield is required. The following siabsections 
describe typical memory configurations. 




, _^, C21518001-X3 

4-4 -^» 



CONNECTOR COLUMNS 
A B C D E F ^!^^ 


1 MAINT. 1 MAINT. | | **PERIPHERAL CONTROLLER | i 


— 


|*UNIBUS TERMINATOR | DEC MEMORY STACK 1 | 2 




1 DEC MEMORY DRIVER 1 I 3 




1 DEC MEMORY CONTROL 1 | 4 




1 UNIBUS TERMINATOR | DEC MEMORY STACK 2 | 5 




1 DEC MEMORY DRIVER 2 | 6 




1 DEC MEMORY CONTROL 2 | 7 




1 DEC CPU 1 8 




1 DEC CPU 1 9 


COMPONENT SIDE 


1 CIRCUIT BOARD | *0R EXTERNAL CABLE 


CIRCUIT SIDE **^^ ^^^^^ LUNIINUIIY CAKU 



Figvire 4-1. DEC PDP-11/05 and PDP-11/10 Standard Module Utilization - 
Configuration 1 (16K) 



CONNECTOR COLUMNS 
1 A B C D E F ^l^""" 


1 UNUSED 1 1 ♦♦ PERIPHERAL CONTROLLER | i 




1 MAINT. 1 1 MAINT. | | ** PERIPHERAL CONTROLLER | 2 




1 *UNIBUS TERMINATOR | ** PERIPHERAL CONTROLLER | 3 




UNUSED 1 ♦♦PERIPHERAL CONTROLLER | 4 




1 UNIBUS TERMINATOR | | DEC MEMORY STACK | 5 




1 DEC MEMORY CONTROL I 6 




1 DEC MEMORY DRIVER I 7 




1 DEC CPU 1 8 




1 DEC CPU 1 9 


*0R EXTERNAL CABLE 
**0R GRANT CONTINUITY CARD 



Figure 4-2. DEC PDP-11/05 and PDP-11/10 Standard Module Utilization 
Configuration 2 (8K) 



C21518001-X3 



^ 



4-5 



4.2.1 24K-Word Configuration lA 

The 24K-word configuration lA (Figure 4-3) uses three CDP-8KX16 modules 
and no MMll-L. 

The CDP-8KX16 modules are installed in slots 2, 4 and 6. Because of the 
core-plane board, the adjacent slots (3, 5 and 7, respectively) are 
blocked, even though no connections to the CDP-8KX16 modules are made in 
these locations. 

For this installation, the UNIBUS terminator normally located in 
connectors 5A/5B is moved to connectors 7A/7B prior to installing any 
memories . 

UNIBUS signals are available at connectors 3A/3B and 5A/5B. A UNIBUS 
terminator or external cable can be inserted in either of these locations , 
although 3A/3B are normally used. 

The rated power limits for this configuration are: 

+5 V -15 V 
Unit Amps Amps Note 

CPU 8.0 - Approximate 

One CDP-8KX16 operating 
Two CDP-8KX16 standby 
Terminator 

LOAD 
Available reserve 

SUPPLY LIMIT 17.0 6.00 

If the UNIBUS terminates in this chassis, an additional 1.2 A (+5 V) must 
be allowed for a second terminator. 



Amps 
8.0 
2.8 
3.6 
1.2 


Amps 

4.40 
0.68 


15.6 
1.4 


5.08 
0.92 




4_6 uii^ C21518U01-X3 



MA I NT. 



MA I NT. 



UNIBUS TERMINATOR 
OR CABLE 



UNIBUS TERMINATOR 



COMPONENT SIDE 



CIRCUIT BOARD 



SOLDER SIDE 



CONNECTOR COLUMNS 
C I D 



GRANT CONTINUITY CARD 



CDP-8KX16 



CDP-8KX16 



DEC CPU 



DEC CPU 



Figure 4-3. 24K-Word Configuration lA 



SLOT 

▼_ 

1 







CDP-8KX16 


UNIBUS 



COMPONENT SIDE 



CDP-8KX16 



CORE-PLANE SIDE 



C21518001-X3 




4-7 



4.2.2 16K-Word Configuration IB 

The 16K-word configuration IB (Figure 4-4) uses two CDP-8KX16 modules 
and no MMll-L. 

The CDP-8KX16 modules are installed in slots 4 and 6. The core-plane 
board blocks the adjacent slots (5 and 7, respectively) even though no 
connections to the CDP-8KX16 modules are made in these locations. 

For this installation, the UNIBUS terminator normally located in con- 
nectors 5A/5B is moved to connectors 7A/7B prior to installation of the 
memories . 

UNIBUS signals are available at connects 5A/5B, 3A/3B and 2A/2B. A 
UNIBUS terminator or external cable can be inserted in any of these 
locations, although 2A/2B are normally used. 

Note that empty slots 2 and 3 are wired to contain the MMll-L core stack 
and memory driver boards. This wiring does not conform to that used by a 
peripheral controller board, hence the slots cannot be used for standard 
DEC quad-height controller assemblies. These slots can, however, be used 
for expansion to a third CDP-8KX16 module (configuration lA) and can also 
contain user-designed controllers on hex-height cards. Such cards obtain 
all UNIBUS communication from the A and B connectors, and power and 
ground inputs from the other connectors. Cal Data offers various hex- 
height controllers, including a general-purpose wire-wrap HEXBOARD, that 
plug into these slots. 

Check that the overall power consumption does not produce an overload 
condition. 

The rated power limits for this configuration are: 

+5 V -15 V 
Unit Amps Amps Note 

8.0 - Approximate 



CPU 

One CDP-8KX16 running 2.8 4.40 
One CDP-8KX16 standby 1.8 0.34 

Terminator 
LOAD 



1.2 - Required 



13.8 4.74 
Available reserve 3.2 1*26 

SUPPLY LIMIT 17.0 6.00 

If the UNIBUS terminates in this chassis, an additional 1.2 A (+5 V) must 
be allowed for a second terminator. 



4-8 




C21518001-X3 



CONNECTOR COLUMNS 
C I D 



MA I NT. 



MA I NT. 



UNI BUS TERMINATOR 
OR CABLE 



UNIBUS 



COMPONENT SIDE 



I CIRCUIT BOARD 
SOLDER SIDE 



PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 



UNUSED 



NOT AVAILABLE 



DEC CPU 



DEC CPU 



SLOT 

_▼ 

1 







CDP-8KX16 


UNIBUS 







CDP-8KX16 


UNIBUS TERMINATOR 



COMPONENT SIDE 



CDP-8KX16 



CORE-PLANE SIDE 



Figure 4-4. 16K-Word Configuration IB 



C21518001-X3 




4-9 



4.2.3 16K-Word Configuration IC 



The 16K-word configuration IC (Figure 4-5) uses one CDP-8KX16 module and 
one MMll-L module. 

The CDP-8KX16 module is installed in slot 3. The core-plane board blocks 
adjacent slot 4 even though no connection is made to the CDP-8KX16 in 
this location. The UNIBUS terminator remains in connectors 5A/5B. 

UNIBUS signals are available at connectors 2A/2B and 4A/4B. A UNIBUS 
terminator or external cable can be inserted in either of these locations, 
although 2A/2B are normally used. 

Note that empty slot 2 is wired to contain the MMll-L core stack. The 
wiring in this location does not conform to that used by a peripheral 
controller, hence the slot cannot be used for standard DEC quad-height 
controller assemblies. This slot can, however, be used for a user- 
designed controller on a HEXBOARD. Such a board obtains all UNIBUS 
communication from connectors 2A/2B, and power and ground inputs from the 
other connectors. Cal Data offers various hex-height controllers that 
interface in this slot. 



The rated power limits for this configuration are 



+5 V 


-15 V 


Amps 


Amps 


8.0 


- 


3.4 


6.00 


1.8 


0.34 


1.2 


- 


14.4 


6.34 


2.6 


-(0.34) 


17.0 


6.00 



Note 
Approximate 



Unit 

CPU 

One MMll-L operating 

One CDP-8KX16 standby 

Terminator 1-2 ^_ Required 

LOAD 
Available reserve 
SUPPLY LIMIT 

Note that the -15 V is over the supply limit in this configuration. The 
standby consumption on -15 V of a second MMll-L would be 0.5 A versus the 
0.34 A of the CDP-8KX16, hence, the latter presents less of an overload than 
using two MMll-L memories (the CDP-8KX16 power rating given is for worst- 
case conditions) . Should difficulties be experienced in running the 
-15 V supply above the rated load, consult the computer manufacturer 
concerning provisions for normal operation of two MMll-L units under the 
same conditions . 

If the UNIBUS terminates in this chassis, an additional 1.2 A (+5 V) must 
be allowed for a second tejrminator . 



4-10 




C21518001-X3 



CONNECTOR COLUMNS 



MA I NT. 



MA I NT. 



UNIBUS TERMINATOR 
OR CABLE 



UNIBUS TERMINATOR 



COMPONENT SIDE 



CIRCUIT board! 
SOLDER SIDE 



c 


D 


E 




F 


PERIPHERAL 


CONTROLLER OR GRANT 


CONTINUITY 


CARD 






NOT 


AVAILABLE 







DEC MEMORY STACK 



DEC MEMORY DRIVER 



DEC MEMORY CONTROL 



DEC CPU 



DEC CPU 



SLOT 

▼_ 

1 







CDP-8KX16 


UNIBUS 



COMPONENT SIDE 



CDP-8KX16 



CORE-PLANE SIDE 



Figure 4-5. 16K-Word Configuration IC 



C21518001-X3 



^ 



4-11 



4.2.4 16K-Word Configuration 2A 

The 16K-word configuration 2A (Figure 4-6) has two CDP-8KX16 modules and 
two peripheral controllers. 

The CDP-8KX16 modules are installed in slots 4 and 6. Because of the 
core-plcine board, the adjacent slots (5 and 7, respectively) are blocked 
even though no connections to the CDP-8KX16 modules are made in these 
locations . 



For this installation, the UNIBUS terminator normally located in con- 
nectors 5A/5B is moved to connectors 7A/7B prior to installing any 
memories . 

UNIBUS signals are available at connectors 3A/3B and 5A/5B. A UNIBUS 
terminator or external cable can be inserted in either of these locations, 
although 3A/3B are normally used. 

Two small-peripheral controller slots are available for use, provided 
that the overall system power consumption does not cause an overload 
condition. 

The rated power limits for this configuration are: 





+5 V 


-15 V 




Unit 


Amps 


Amps 


Note 


CPU 


8.0 


- 


Approximate 


One CDP-8KX16 operating 


2.8 


4.40 




One CDP-8KX16 standby 


1.8 


0.34 




Terminator 


1.2 
13.8 


- 


Required 


LOAD 


4.74 




Available reserve 


3.2 


1.26 




SUPPLY LIMIT 


17.0 


6.00 





If the UNIBUS terminates in this chassis, an additional 1.2 A (+5 V) must 
be allowed for a second terminator. 



4-12 




C21518001-X3 





CONNECTOR COLUMNS 
1 A B C D 1 E F 


SLOT 
T 




UNUSED 


PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 


1 






MAI NT. 


MA I NT. 


PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 


2 






UNIBUS TERMINATOR 
OR CABLE 


GRANT CONTINUITY CARD 


3 




4 






CDP-8IO(16 






UNIBUS 


5 




6 






CDP-8KX16 






UNIBUS TERMINATOR 


7 
8 
9 




DEC CPU 




DEC CPU 


COMPONENT SIDE ' COMPONENT SIDE 




1 CIRCUIT BOARD | I | 












SOLDER SIDE 




CORE-PLANE SIDE 





Figure 4-6. 16K-Word Configuration 2A. 



C21518001-X3 




4-13 



4.2.5 16K-Word Configuration 2B 

The 16K-word configuration 2B (Figure 4-7) has one CDP-8KX16 module, one 
^^M11-L module and one peripheral controller. 

The CDP-8KX16 module is installed in slot 3. Because of the core-plane 
board, the adjacent slot 4 is blocked even though no connections to the 
CDP-8KX16 are made in this location. 

UNIBUS signals are available at connectors 2A/2B and 4A/4B. A UNIBUS 
terminator or external cable can be inserted in either of these locations, 
although 2A/2B are normally used. 

One small-peripheral controller slot is available for use, provided that 
the overall system +5 V power consumption does not cause an overload 
condition. 



The rated power limits for this configuration are: 





+5 V 


-15 V 




Unit 


Amps 


Amps 


Note 


CPU 


8.0 


- 


Approxim. 


One MMll-L operating 


3.4 


6.00 




One CDP-8KX16 standby 


1.8 


0.34 




Terminator 


1.2 
14.4 


- 


Required 


LOAD 


6.34 




Available reseirve 


2.6 


-(0.34) 




SUPPLY LIMIT 


17.0 


6.00 





Note that the -15 V is over the rated load in this configuration. The 
standby consumption on -15 V of a second MMll-L would be 0.5 A versus 
the 0.34 A of the CDP-8KX16, hence the latter presents less of an over- 
load than using two MMll-L memories (the CDP-8KX16 power rating given is 
for worst-case conditions) . Should difficulties be experienced in running 
with the -15 V supply above the rated load, consult the computer manu- 
facturer concerning provisions for normal operation of two MMll-L units 
under the same conditions. 

If the UNIBUS terminates in this chassis, an additional 1.2 A (+5 V) must 
be allowed for a second terminator. 



4-14 




C21518001-X3 



CONNECTOR COLUMNS 



MA I NT. 



MA I NT. 



UNIBUS TERMINATOR 
OR CABLE 



UNIBUS TERMINATOR 



COMPONENT SIDE 



CIRCUIT BOARD 



SOLDER SIDE 



c 


D 


E 


F 


PERIPHERAL 


CONTROLLER OR GRANT CONTINUITY 


CARD 






GRANT CONTINUITY 


CARD 





DEC MEMORY STACK 



DEC MEMORY DRIVER 



DEC MEMORY CONTROL 



DEC CPU 



DEC CPU 



SLOT 

r_ 
1 







CDP-8KX16 


UNIBUS 



COMPONENT SIDE 



,CDP-8KX16 



CORE-PLANE SIDE 



Figure 4-7. 16K-Word Configuration 2B 



C21518001-X3 




4-15 



4.2.6 8K-Word Configuration 2C 

The 8K-word configuration 2C (Figure 4-8) has one CDP-8KX16 module and 
four peripheral controllers. 

The CDP-8KX16 is installed in slot 6. Because of the core-plane board, 
the adjacent slot 7 is blocked even though no connections to the 
CDP-8KX16 are made in this location. 

For this installation, the UNIBUS terminator normally located in con- 
nectors 5A/5B is moved to connectors 7A/7B prior to installing the 
memory . 

UNIBUS signals are available at connectors 3A/3B, 4A/4B and 5A/5B. A 
UNIBUS terminator or external cable can be installed in any of these 
locations, although 3A/3B are normally used. 

Four small-peripheral controller slots are available for use, provided 
that the overall system power consumption does not cause an overload 
condition. 

The rated power limits for this configuration are: 





+5 V 


-15 V 




Unit 


Amps 


Amps 


Note 


CPU 


8.0 


- 


Approximate 


One CDP-8KX16 operating 


2.8 


4.4 




Terminator 


1.2 


- 


Required 


LOAD 


12.0 


4.4 




Available reserve 


5.0 


1.6 




SUPPLY LIMIT 


17.0 


6.0 





If the UNIBUS terminates in this chassis, an additional 1.2 A (+5 V) must 
be allowed for a second terminator. 



4-16 



^ 



C21518001-X3 



UNUSED 



MA I NT. 



MA I NT. 



UN I BUS TERMINATOR 
OR CABLE 



UNIBUS 



UNIBUS 



UNIBUS TERMINATOR 



COMPONENT SIDE 



CIRCUIT BOARD 



SOLDER SIDE 



CONNECTOR COLUMNS 
C I D 



SLOT 



PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 



PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 



PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 



PERIPHERAL CONTROLLER OR GRANT CONTINUITY CARD 



NOT AVAILABLE 



CDP-8KX16 



DEC CPU 



DEC CPU 



COMPONENT SIDE 



iCDP-8KX16 



CORE-PLANE SIDE 



Figure 4-8. 8K-Word Configuration 2C 



C21518001-X3 




4-17 



4.3 INSTALLATION IN THE PDP-11/35, PDP-11/40 OR PDP-11/45 

CDP-8KX16 modules can be installed directly in the PDP-11/40 moiinting box 
(BAll-FC) . Figure 4-9 shows a view of the module side of the chassis. 
Figure 4-10 shows a multiple-module installation and Figure 4-11 shows 
the backplane connectors. 

Although the material in this subsection is a specific description of 
CDP-8KX16 installations in the PDP-11/40, it is also applicable to the 
PDP-11/35 and the PDP-11/45, with minor modifications. 

The basic system contains two double system units for board installation, 
each unit containing nine rows of connectors. The first nine-slot unit 
contains the CPU and associated option boards emd is not used for memory 
installation. 

The second doiable system unit is prewired for one to three MMll-L memory 
modules. Each MMll-L module is a three-board assembly consisting of a 
stack, memory driver and control board. Thus, this doxible system unit 
generally contains 8K to 24K of MMll-L memory. 

The remainder of the BAll-FC box can be used for single or double system 
units for additional memory or peripheral interfaces. Each double system 
\init is equivalent to five single system \anits. 

This section presents typical installation detail for mounting CDP-8KX16 
modules in the assembly with or without MMll-L memories. Memory expan- 
sion beyond the basic double system unit for memory is identical when 
other MMll-L backplanes are installed. The user cam use the information 
provided to determine the installation method required for other types of 
system mounting units. 



4-18 




C21518001-X3 



SIDE VIEW 


A 


D( 
Ul 


)UBLE SYSTE 
^IT, 9 SLOl 


EM 

rs 


^ 


^CONSOLE 




'■II 








B 








\ 




CONNECTOR 
COLUMNS 


C 

D 
E 
F 


















I. t 




ADDITIONAL MEMORY OR 
PERIPHERAL INTERFACES 


CPU 






5 SINGLE SYSTEM DOUBLE SYSTEM 
UNITS OR EQUIVALENT UNIT, 9 SLOTS 





Figure 4-9. PDP-11/40 Mounting Box 



C21518001-X3 




4-19 



m 



v^ 



'" :i* ^ 



■^ >^ .-a. ^•''iliii 



«r» 



*■?» 



12». 



■*»' 
.-*~' 



ST. 



i?- 






ISr/J-J -, ■J.I'!.! flV-. i -..n 









kW^ 









I J- ' 




Figure 4-10. PDP-11/40 Multiple-Module Installation 



4-20 




C21518001-X3 



NINE-SLOT SYSTEM UNIT 



UNIBUS 
JUMPERS 



INSTALLED 
BOARDS 




Figure 4-11. PDP-11/40 Backplane Connector Scheme 



C21518001-X3 



^^ 



4-21 



Figure 4-12 shows slot allocation for a fully- expanded 24K assembly. The 
MMll-L memory driver and control/data boards are hex-height and use all 
six connectors of a slot. The stack board is quad-height and occupies 
columns C to F only. 

The A and B connectors in slots 1 cind 9 are used either to extend or to 
terminate the UNIBUS. A standard UNIBUS jumper is used to extend the bus 
from system unit to system unit. A terminator is placed in the last 
system unit at or near the end of the UNIBUS. These requirements, and 
the number of MMll-L modules installed, determine the number of CDP-8KX16 
modules that can be used. 

The following are general installation rules for the CDP-8KX16 : 

a. The component side of a CDP-8KX16 cannot be adjacent to a board 
that occupies connector colimms C to F, because CDP-8KX16 com- 
ponents in this area can make contact with the adjacent board. 

b. The component side of a CDP-8KX16 can be adjacent to a board that 
occupies connector columns A and B only (e.g., the stemdard 
UNIBUS jumper emd terminator boards) . 

c. The component side of a CDP-8KX16 always faces the same direction 
as the components of all other boards in the system. 

d. Always have power OFF when inserting or removing boards. Check 
the memory board for proper component orientation before inser- 
tion. Excessive force applied to a reversed board can result in 
damage to the backplane connectors. 

e. Memory management is required for configurations that total more 
than 32K of memory. 

f. The core-plane side blocks the adjacent higher-nvimbered slot. 
The second-higher slot can be occupied by another CDP~8KX16 
module, or by any other board whose maximum height does not 
exceed that of the CDP-8KX16 components. 

g. A Cal Data board adapter should be installed on the CDP-8KX16 to 
make contact with the card guides of the computer chassis. 

Installations in PDP-11/35 ejcpansion chassis are analagous to those in 
PDP-11/05 computers (subsection 4.2). 



^ 



. C21518001-X3 

4-22 



SLOT^I 9 









CO 



CO 



CO 



o 



a: 

o 



t_3 



o 



CO 

:»: 

o 

< 

co 

>- 
a: 
o 



m 
o 



J 



CO 

LU 
> 
»— I 

Q 

>- 

a: 
o 

s: 



UJ 
Q 



CO 



o 



o 
o 

>- 
oc 
o 



o 

LiJ 

o 



CVJ 



o 



o 
tj 

>- 
a: 
o 



c_> 

UJ 

o 



C\J 

oc 



oc 
o 

>- 

o 



UJ 

o 



CJ 

I— 

CO 

>- 
oc 
o 



UJ 

o 



o 
cc 

(— 
z 
o 
o 

>- 
oc 
o 

5 



UJ 

o 



a 

>- 
a: 
o 



o 

UJ 
Q 



< 
I— 
00 

>- 

O 



UJ 
Q 



SOLDER 
SIDE 



COMPONENT 
SIDE 



Figure 4-12. DEC Assembly Utilization (24K) 



C21518001-X3 



^ 



4-23 



4.3.1 32K-Word Configuration 1 

The 32K-word configuration 1 (Figure 4-13) has one MMll-L and three 
CDP-8KX16 modules in a nine-slot system unit. 

The CPU ccin address only the first 28K core locations. Addressable 
memory capacity generally cannot be expanded beyond 28K without the 
addition of memory management; however, the Cal Data 7K-word option can 
be installed in a CDP-8KX16 module (or pair of interleaved modules) to 
obtain a 3lK-word addressable capacity without memory management (with 
the last iK-word addresses allocated to I/O devices) . 

CDP-8KX16 modules are installed in slots 5, 7 and 9. A UNIBUS terminator 
is installed in slot 8 if the bus is to be terminated at that point. If 
the bus is to be extended, a UNIBUS extension cable is used rather than 
the jxmiper, since connectors 9A/9B are not available. The CDP-8KX16 
board is notched at the top to provide adequate clearance for the cable. 
Slot 4 is left empty to prevent CDP-8KX16 components from touching the 
board in slot 3. 

The worst-case power consumption for this configuration is: 





+5 V 


-15 V 




Unit 


Amps 


Amps 


Note 


One MMll-L operating 


3.4 


6.00 




Three CDP-8KX16 standby 


5.4 


1.02 




MINIMUM LOAD 


8.8 


7.02 




Terminator 


1.2 
9.7 


- 


If required 


TOTAL LOAD 


7.02 


Noninterleaved 


Interleaved 


0.9 


4.10 


Optional 


INTERLEAVE LOAD 


10.6 


11.12 





Check this requirement against the power available from the power distri- 
bution panel for the particiilar system imit used for the memory modules. 



4-24 




C21518001-X3 



SLOT ► I 9 



o 
o 



o 



o 



o 



F ;;;;:;;:; 



1^ 

X 

00 

I 

Q. 

a 
o 



UNIBUS TERMINATOR 
OR CABLE 








X 

a. 

Q 

o 





Q 

z 
:3 










s 

00 

1 

Q. 
Q 
(_) 





CQ 






O 



o 
o 

>- 

o 



LU 

o 



UJ 

a. 

■-3 
CO 



Q 

>- 

a: 
o 



o 

LU 
Q 



o 

< 



>- 
a: 
o 



o 

LU 
Q 



Note: 



This area indicates the 
space occupied by the 
CDP-8KX16, but does not 
imply the existence of 
another slot. 



SOLDER 
SIDE 



COMPONENT 
SIDE 



CORE- 
PLANE 
SIDE 



X 

00 

a. 

Q 

o 



COMPONENT 
SIDE 



Figure 4-13. 32K-Word Configuration 1 



C21518001-X3 




4-25 



4.3.2 32K-Word Configuration 2 

The 32K-word configuration 2 (Figure 4-14) has four CDP-8KX16 modules in 
a nine-slot system unit with no MMll-L. 

The CPU can address only the first 28K core locations. Addressable 
memory capacity generally cannot be expanded beyond 28K without the 
addition of memory management; however, the Cal Data 7K-word option can 
be installed in a CDP-8KX16 module (or pair of interleaved modules) to 
obtain a 3lK-word addressable capacity without memory management (with 
the last IK-word addresses allocated to I/O devices) . 

CDP-8KX16 modules are installed in slots 2, 4, 6 and 8. Slots 1 and 9 
are empty, except that the UNIBUS is jumpered into slot 1 and is either 
extended or terminated in slot 9. 

The worst-case power consumption for this configuration is : 





+5 V 


-15 V 




Unit 


Amps 


Amps 


Note 


One CDP-8KX16 operating 


2.6 


4.40 




Three CDP-8KX16 standby 


5.4 


1.02 




MINIMUM LOAD 


8.0 


5.42 




Terminator 


1.2 
9.2 


- 


If required 


TOTAL LOAD 


5.42 


Noninter leaved 


Interleaved 


0.9 


4.10 


Optional 


INTERLEAVE LOAD 


10.1 


9.52 





Check this requirement against the power available from the power distri- 
bution panel for the particular system unit used for the memoiry modules. 



4-26 




C21518001-X3 



SLOT ►! 9 



I 1 I 



o 
o 



on 
o 



LU 



o 
o 



UNIBUS TERMINATOR, 
JUMPER OR CABLE 














r— 

X 

00 

1 

Q. 
Q 







Q 
LU 
00 



VO 



00 



a. 
o 



Q 
LU 

00 



X 

:^ 

00 

I 

Q. 
Q 



a 

LU 

oo 

Z 
=3 










CO 

1 

Q. 
Q 





LU 

s: 

=3 

CO 

CO 



< 






SOLDER 
SIDE 



COMPONENT 
SIDE 



CORE- 






PLANE 






SIDE 


^■^ 






>< 

00 




Q 
O 



COMPONENT 
SIDE 



Figvire 4-14. 32K-Word Configuration 2 



C21518001-X3 




4-27 



4.3.3 24K-Word Configuration 1 

The 24K-word configuration 1 (Figure 4-15) has two CDP-8KX16 modules 
with one MMll-L in a nine-slot system unit. 

CDP-8KX16 modules are installed in slots 5 and 7. The UNIBUS is jumpered 
into slot 1 and is either extended or terminated in slot 9. Slot 4 is 
left empty to prevent CDP-8KX16 components from touching the board in 
slot 3. 

The worst-case power consumption for this configuration is: 





+5 V 


-15 V 




Unit 


Amps 


Amps 


Note 


One MMll-L operating 


3.0 


6.00 




Two CDP-8KX16 standby 


3.6 


0.68 




MINIMUM LOAD 


6.6 


6.68 




Terminator 


1.2 
7.8 


- 




TOTAL LOAD 


6.68 


Noninterleaved 


Interleaved 


0.9 


4.10 


Optional 


INTERLEAVE LOAD 


8.7 


10.78 





Check this requirement against the power available from the power distri- 
bution panel for the particular system unit used for the memory modules. 



4-28 




C21518001-X3 



SLOT ►! 9 







en 




o 




t— 


LU 


< 


_1 


2: 


CO 


K- 1 


cr 


5^ 





cn 




LlJ 


a: 


H-O 1 


oo 


^ 


=3 LU 1 


CO 


Q- 


t— « 


s. 


•z. 


■^ 


Z3 '-D 



o 
o 



on 
o 



o 
o 



Q 
UJ 
I/) 



Q 










r— 
X 

00 

1 

Q. 
Q 






Q 
LU 

■z. 










00 

1 

CI. 







OQ 



>• 



o 



o 
o 

>- 

o 



LU 



o: 



a: 

>- 
a: 
o 



o 

UJ 
Q 



LU 
Q. 

CO 

CO 



I — 



o 



o 

LU 
Q 



SOLDER 
SIDE 



COMPONENT 
SIDE 



CORE- 




^^™ 


PLANE 






SIDE 








X 

00 




Q 




COMPONENT 
SIDE 



Figure 4-15. 24K-Word Configuration 1 



C21518001-X3 




4-29 



4.3.4 24K-Word Configuration 2 

The 24K-word configuration 2 (Figure 4-16) has one CDP-8KX16 and two 
MMll-L modules in a nine-slot system unit. 

The MMll-L boards occupy slots 1 to 6. The CDP-8KX16 is installed in 
slot 8. The UNIBUS is jumpered into slot 1 and is either extended or 
terminated in slot 9. Slot 7 is left empty to prevent CDP-8KX16 compo- 
nents from touching the board in slot 6. 

The worst-case power consumption for this configuration is: 



Unit 

One MMll-L operating 
One MMll-L standby 
One CDP-8KX16 standby 

MINIMUM LOAD 
Terminator 

TOTAL LOAD 



+5 V 


-15 V 


Amps 


Amps 


3.4 


6.00 


1.7 


0.50 


1.8 


0.34 


6.9 


6.84 


1.2 


- 



Note 



8.1 



6.84 



If required 
Noninterleaved 



Check this requirement against the power available from the power distri- 
bution panel for the particular system unit used for the memory modules. 



4-30 




C21518001-X3 



SLOT ►! 9 



I 1 I 



«t 




q: 




o 




t— 


LU 


< -J 1 


z 


CQ 


1 — 1 


<r 


s: o 1 


o^ 




LU 


q: 


i-o 1 


lo 


a: 


r3 


LU 


CQ 


a. 


1— « 


s: 


z 


ZD 


=D 


•s 



tn 



o 

C_3 



a: 
o 



o 
o 



X 

00 

I 

a. 
o 
<_> 



CQ 






o 



o 
o 

>- 
a: 
o 



ij I 



L 



CM 
OH 



0£. 
Q 

>- 

oc 
o 



CJ 

LU 



o 

LU 



v: 

•a: 



>- 
a: 
o 



LU 
Q 



O 

ce: 



o 
o 

>- 
Qc: 
o 






q: 



Qi 

>- 
cc 
o 



t_5 

LlJ 
Q 



OH. 
LU 
Q- 

■=> 

■-3 
GO 



L 



C_) 



>- 
OH 
O 



LU 
Q 



SOLDER 
SIDE 



COMPONENT 
SIDE 



CORE- 
PLANE 
SIDE I 



(A 



00 

I 

a. 

Q 
O 



COMPONENT 
SIDE 



Figure 4-16. 24K-Word Configuration 2 



C21518001-X3 




4-31 



4.4 INSTALLATION IN THE CAL DATA CHASSIS 

Up to eight CDP-8KX16 modules can be installed in a typical Cal Data 
chassis, as shown in Figure 4-17. 

Slots 1 to 5 are closely spaced for the CPU and related boards. Slots 6 
and up are on wider centers so that each slot can accomodate either a 
CDP-8KX16 module (including core-plane board) , a controller board or an 
option board (slots 6 and 7 only) . If a memory management unit (MMU) is 
present, it must be installed in slot 6. The MMU is required for memory 
expansion beyond 32K words. 

When a chassis contains both CDP-8KX16 modules and controllers, the 
memory modules are installed to occupy available slots close to the 
CPU, followed by the controllers toward the power supply. 



^ 



4_32 ^ ■»■» C21518001-X3 



14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 



SLOTS 



POWER SUPPLY 



tUh^-OI^Aib ' 1 



CDP-8KX16 
CDP-8KX16 
CDP-8KX16 



CDP-8KX16 
CDP-8KX16 



CDP-8KX16 
CDP-8KX16 



CDP-8KX16 (OR OPTION) 



MMU (OR OPTION) 



EMULATE 



CPU 



CPU 



MACROBUS CHANNEL ADAPTER 



MACROPANEL 



C I D 
CONNECTOR COLUMNS 



~ ~~Z3 






FANS 



Figure 4-17. Typical Cal Data Chassis Layout 



C21518001-X3 



^ 



4-33 



SECTION 5 
MAINTENANCE 



5 . 1 GENERAL 



This section describes preventive and corrective maintenance procedures 
that apply to the CDP-8KX16. In general, corrective maintenance is 
limited to isolation of a fault to a specific CDP-8KX16 module, followed 
by replacement of the module. Troiobleshooting may then be used to verify 
that the suspected module is malfunctioning and to help diagnose the 
specific problem. Repair should be conducted at the factory or by an 
authorized Cal Data representative. 



5.2 PREVENTIVE MAINTENANCE 



The CDP-8KX16 is a reliable solid-state device designed to perform 
continuously for many years without degredation. Preventive maintenance 
consists of performing the following tasks every six months: 

a. Inspect the C3DP-8KX16 for damaged wires, components or other 
obvious defects. 

b. Using a lo^-pressure source of air (75 psi one foot from board, 
or 5 kg/cm 30 cm from board) , blow off accumulated dust and 
foreign matter. 

c. Check the +5 Vdc cind -15 Vdc inputs to the memory. They should 
be within 15 percent. 

5.3 CORRECTIVE MAINTENANCE 

Repair or adjustment of the CDP-8KX16 in the field is not recommended. 
Separation of the core-plane board from the drive board or changing the 
adjustment of any potentiometer breaks factor seals on the module and 
voids the warranty . 

If a malfunction is detected, replace the CDP-8KX16 with a spare module 
known to be operating properly and return the malfunctioning module for 
repair to California Data Prociessors or an authorized representative. 

Malfunctions can be detected with the aid of test programs and by signal 
troubleshooting described in the following paragraphs. 



5.3.1 Test Program 



When the CDP-8KX16 is installed in any PDP-11 computer or Cal Data 1 
equivalent, it can be tested by the DEC program MAINDEC-11-DZQMB 0-124K 
MEMORY EXERCISER. This program tests contiguous memory addresses from 
to 0757776, verifying that each address is unique (address test) and that 
each location can be read from or written into reliably (worst-case noise 
test) . If memoiry management is installed, all testing is performed with 
memory management enabled. 




C21518001-X3 OHN 5-1 



The 11 FAMILY INSTRUCTION EXERCISER DZQKA, and the KTll-C/KTll-D LOGIC 
TEST, if memory management is installed, are considered preliminary to 
the memory exerciser. 

5.3.1.1 Program Description 

The program verifies each location from 020000 to the end of memory by 
writing the value of each address into that location, printing the last 
address plus two on the teleprinter, and verifying each value written. 
The program then writes the complement of the address into each location 
from the end of memory back to 020000, and verifies each value written. 

The next test comprises reading, writing and verifying memory using a 
Cal Data-supplied worst-case noise pattern (8 XOR 13) . The test proceeds 
by exercising one block of memory at a time. If memory management is 
installed, the test is performed with memory management enabled. 

One bit of a program indicator (location 01012) is set by the program 
for each 4K-word memory block between 4K and 28K that tested error free. 
After all locations from 020000 to the end of memory have been tested, 
the program relocates itself to the lowest 4K block that tested error 
free as noted in the program indicator. Locations to 017776 are then 
tested as described above. 

When testing is complete, the program relocates itself to its original 
position of to 017776, increments the pass counter in location 010000 
and restarts, beginning with the worst-case noise test. The teleprinter 
bell rings after 128 passes, after which the program restarts, beginning 
with the address test. 

5.3.1.2 Loading, Starting and Running 

To load and start the memory exerciser: 

1. Load the program into memory using the ABS loader. 

2. Load starting address 0200 into the program counter (0777707). 

3. Set SWITCH REGISTER switches to the desired configuration 
(Table 5-1) . 

4. Press START. 

The program loops and, on completion of 128 passes, rings the teleprinter 
bell. The pass number can be monitored by reading address location 
01000 

The program must be in the lowest 4K of memory when starting or 
restarting. It tests only contiguous areas of memory. 

The program saves both loaders (BOOT and ABS) by relocating them. To 
restore them, restart at 0210 after ensuring that the program has not 
been relocated. The program has been relocated if location 0200 does 
not contain 0137 or if bit 15 of the macropanel data indicators is on. 

In this case, the current 4K memory block number is indicated in program 
counter (PC) bits 15 to 13. Restart the program at 0X17400, where X is 



5-2 



^ 



C21518001-X3 



Table 5-1. Tpr-I- Pr-nrir-atn RWTTrw T3Vi-TCnm-Q cf.,,ij.-t. r<-i._- 

-J.- J •„. *»iJvjj.v^j.ijK owj.i_^n oet.tj.nys 



Switch 



15 



When set (up) 



14 
13 
11 
10 
09 



The program halts on detection of an error. Correct data 
are not loaded into the faulty location. If the switch 
is raised after the error printout begins, the program 
halts when the message is completed, and the correct data 
are loaded into the faulty location. 

Subtest loops. 

Inhibits error printouts. 

Inhibits subtest iterations. 

Rings the teleprinter bell on detection of an error. 

Displays the error count instead of the pass count in the 
display register (01000) . 



the octal value of PC bits 15 to 13. The program relocates itself to the 
lowest 4K of memory and halts at 0176. To res-jme testing, press COlviT. 

When the program is relocated, it verifies that the relocation has been 
made correctly. If the program cannot be relocated upward, the testing 
from the relocated area is bypassed. If there is an error while 
returning the program to the lowest 4K memory block, the program halts 
and types an error message. Continuing the program retries the downward 
relocation until successful or until the program is reloaded. 

Stack-pointer file-register FR6 (location 0777706) starts at 0500 and resets 
to this value at the start of each siibtest. 

The program stores, in CPU file- register FRl (location 0777701), the PC 
value of the last successful test. This can be used to aid in the isolation 
of a hardware failure. 

The program makes 128 passes and then rings the teleprinter bell. The 
pass counter, location OlOOO, is displayed when switch 09 is down, but bit 
15 is not part of the count. Bit 15 set indicates that the program has 
been relocated. 

Each detected error increments the error counter, location 01002, which 
is displayed when switch 09 is up, but bit 15 is not part of the count. 
Bit 15 set indicates that the program has been relocated. The maximum 
error count is 017777, after which no further incrementation occurs. 

If the program halts in trap/interrupt vector area to 01000, examine 
stack-pointer FR6 to find the address of the instruction that caused 
the trap. File- register FRl indicates the last successful test. 



C21518001-X3 



xiP' 



5-3 



5.3.1.3 Error Printouts 

The program prints the PC value where an error occurred, followed by the 
faulty location, the good data and the bad data, in the format: 

PC xxxxxx ADDRESS aaaaaa GOOD DATA gggggg BAD DATA bbbbbb 

The address is the actual 18-bit physical address, and is in FR2 (loca- 
tion 0777702) . The good data are in FRO (location 0777700) and the bad data 
are in FR3 (location 0777703) . 

When memory locations to 017776 are tested, the PC printed is 020000 
greater than that reflected in the program listing. 

To recover from an error, press CONT or restart at location 0200, unless 
the program has been relocated. See paragraph 5.3.1.2. 




5-4 UkW C21518001-X3 



APPENDIX A 
INTERFACE PIN ASSIGNMENTS 



Table A-1 gives interface pin assignments for A and B connectors that provide all 
active signal lines used by the CDP-8KX16. Table A-2 gives ground and power inputs 
and propagated Bus Grant line pins associated with the D and F connectors. Figure 
A-1 is a drawing of the connector layout. 



Table A-1. CDP-8KX16 Interface 


Pin Assignments, 


Connectors A and 


B 


Signal 


Connector 


Signal 


INIT L 


AAl 


AA2 




+5 V 




* INTR L 


ABl 


AB2 




GND 




DOO L 


ACl 


AC2 




GND 




D02 L 


ADl 


AD2 




DOl L 




D04 L 


AEl 


AE2 




DOS L 




D06 L 


AFl 


AF2 




DOS L 




DOS L 


AHl 


AH2 




D07 L 




DIO L 


AJl 


AJ2 




D09 L 




D12 L 


AKl 


AK2 




Dll L 




D14 L 


ALl 


AL2 




D13 L 




* PA 1 


AMI 


AM2 




D15 L 




GND 


ANl 


AN2 


* 


PB 1 




GND 


API 


AP2 


* 


BBSY L 




GND 


ARl 


AR2 


* 


SACK L 




GND 


ASl 


AS 2 


* 


NPR L 




GND 


ATI 


AT2 


* 


BR7 L 




* NPG H 


AUl 


AU2 


* 


BR6 L 




* BG7 H 


AVI 


AV2 




GND 




* BG6 H 


BAl 


BA2 


* 


+5 V 




* BG5 H 


BBl 


BB2 




GND 




* BR5 L 


BCl 


BC2 




GND 




GND 


BDl 


BD2 


* 


BR4 L 




GND 


BEl 


BE2 


* 


BG4 H 




* ACLO L 


BFl 


BF2 




DCLO 1 




AOl L 


BHl 


BH2 




AOO L 




A03 L 


BJl 


BJ2 




A02 L 




A05 L 


BKl 


BK2 




A04 L 




A07 L 


BLl 


BL2 




A06 L 




A09 L 


BMl 


BM2 




A08 L 




All L 


BNl 


BN2 




AlO L 




A13 L 


BPl 


BP2 




A12 L 




A15 L 


BRl 


BR2 




A14 L 




A17 L 


BSl 


BS2 




A16 L 




GND 


BTl 


BT2 




CI L 




SSYN L 


BUI 


BU2 




CO L 




MSYN L 


BVl 


BV2 




GND 




*Pins assigned in 


the MACROBUS, but not used by 


the CDP-8KX16. 





C21518001-X3 




A-1 



Table A-2. CDP-8KX16 Power and Bus-Grant Pin Assignments, Connectors D and F 



Signal 



+5 V 
+5 V 
-15 V 
-15 V 
GND 
GND 
GND 
GND 



Power 



Connector 



DA2 
FA2 
DB2 
FB2 
DC2 
FC2 
DTI 
FTl 



Bus Grant 



Signal 



* BGl IN 

* BGl OUT 

* BG2 IN 

* BG2 OUT 

* BG3 IN 

* BG3 OUT 

* BG4 IN 

* BG4 OUT 



Connector 



DK2 
DL2 
DM2 
DN2 
DP 2 
DR2 
DS2 
DT2 



*Pins assigned in the MACROBUS, but not used by the CDP-8KX16. 

These signals are properly jumpered in the CDP-8KX16 to provide Bus Grant 
continuity. 



A-2 




C21518001-X3 



51Ut tL 







m 

5iUt I — 



Connector 
Designator 



Pin Assignments 



BLANK 



SIDE 

Connector 
Designator 



2© 



SIDE 1 



m 



Pin Assignments 



GND 


V 


MSYN L 


CO L 


U 


SSYN L 


CI L 


T 


GND 


A16 L 


s 


A17 L 


A14 L 


R 


A15 L 


A12 L 


P 


A13 L 


AlO L 


N 


All L 


A08 L 


M 


A09 L 


A06 L 


L 


A07 L 


A04 L 


K 


A05 L 


A02 L 


J 


A03 L 


AGO L 


H 


AOl L 


DCLO L 


F 


ACLO L * 


* BG4 H 


E 


GND 


* BR4 L 


D 


GND 


GND 


C 


BR5 L * 


GND 


6 


BG5 H * 


* +5 V 


A 


BG6 H * 





V 






U 






T 






S 






R 






P 






N 






M 






L 






K 






J 






H 






F 






E 






D 




GND 


C 




-15 V 


B 




+5 V 


A 





GND 


V 


BG7 H * 


* BR6 L 


U 


NPG H * 


* BR7 L 


T 


GND 


* NPR L 


S 


GND 


* SACK L 


R 


GND 


* BBSY L 


P 


GND 


* PB L 


N 


GND 


D15 L 


N 


PA L * 


D13 L 


L 


D14 L 


Dll L 


K 


D12 L 


D09 L 


J 


DIO L 


D07 L 


H 


DOS L 


DOB L 


F 


D06 L 


DOS L 


E 


D04 L 


DO! L 


D 


D02 L 


GND 


C 


DOO L 


GND 


B 


INTR L * 


* +5 V 


A 


INIT L 



► MACROBUS 



BLANK 



Component Side. Stack Side. 

*Pins assigned in the MACROBUS, but not used by the CDP-8KX16. 



Figure A-1. CDP-8KX16 Interface Connector Layout 



C21518001-X3 



^ 





V 






U 




* BG4 OUT 


T 


GND 


* BG4 IN 


S 




* BG3 OUT 


R 




* BG3 IN 


P 




* B62 OUT 


N 




* BG2 IN 


M 




* BGl OUT 


L 




* BGl IN 


K 






J 






ri 






F 






E 






D 




GND 


C 




-15 V 


B 




+5 V 


A 





A- 3 



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