Skip to main content

Full text of "analogDevices :: dsp :: ADSP-2100 Users Manual 3ed Sep95"

See other formats


ADSP-2100 FAMILY 
USER'S MANUAL 


m sewm- 

SER'W- PORT 

PORE 


meniore 


HOSE 

\NEERF£ ce 

PORE 


OSP 

wchieeceure 


M»M.OG 

INTERNE 


t\n\er 


□ ANALOG 
DEVICES 



APSP- 2100 Family 
User's Manual 


Third Edition (9/95) 


ANALOG 

DEVICES 




ADSP-2100 Family User’s Manual 

© 1 995 Analog Devices, Inc. 

ALL RIGHTS RESERVED 

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is 
assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which 
may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices. 


Third Edition September 1995 

Analog Devices, Inc. 

Computer Products Division 
One Technology Way 
P.O. Box 9106 
Norwood, MA 02062-9106 
(617) 329-4700 


If you have comments or suggestions about this manual or find any errors in it, please contact us 
via email at: 

dsp_techpubs@analog . com 


For product marketing information or technical support, contact any Analog Devices sales office or 
authorized distributor. For applications engineering assistance, contact: 

DSP Applications Engineering 
Phone: (61 7) 461 -3672 Massachusetts 
Fax: (617) 461-3010 

email: dsp_applications@analog . com 

Phone: (408) 879-3037 California 
Phone: (404) 263-3722 Georgia 


Analog Devices maintains a DSP BBS supporting V.32bis, V.42 and MNP classes 2,3,4 error correction, 
and V.42bis and MNP class 5 data compression which can be reached at: 

(61 7) 461 -4258 8 data bits, no parity, 1 stop bit, 300/1 200/2400/9600/1 4400 baud 

Ail information on the BBS is also available from Analog Devices’ Internet FTP site. Login as anonymous 
using your email address for your password, and type (from the Unix prompt): 

ftp ftp.analog.com (or ftp 137.71.23.21) 


PRINTED IN CANADA 



Contents B 


CHAPTER 1 INTRODUCTION 


1.1 OVERVIEW 1-1 

1.1.1 Functional Units 1-1 

1.1.2 Memory And System Interface 1-3 

1.1.3 Instruction Set 1-4 

1.1.4 DSP Performance 1-4 

1 .2 CORE ARCHITECTURE 1-5 

1 .2.1 Computational Units 1-6 

1 .2.2 Address Generators & Program Sequencer 1-7 

1.2.3 Buses 1-8 

1 .3 ON-CHIP PERIPHERALS 1-8 

1 .3.1 Serial Ports 1-8 

1.3.2 Timer 1-9 

1 .3.3 Host Interface Port 1-9 

1.3.4 DMA Ports 1-9 

1.3.5 Analog Interface 1-10 

1.4 ADSP-2100 FAMILY DEVELOPMENT TOOLS 1-10 

1.5 ORGANIZATION OF THIS MANUAL 1-11 


CHAPTER 2 COMPUTATIONAL UNITS 


2.1 OVERVIEW 2-1 

2.1.1 Binary String 2-1 

2.1.2 Unsigned 2-1 

2.1.3 Signed Numbers: Twos-Complement 2-1 

2.1.4 Fractional Representation: 1.15 2-2 

2.1.5 ALU Arithmetic 2-2 

2.1.6 MAC Arithmetic 2-3 

2.1.7 Shifter Arithmetic 2-3 

2.1.8 Summary 2-4 

2.2 ARITHMETIC/LOGIC UNIT (ALU) 2-5 

2.2.1 ALU Block Diagram Discussion 2-5 

2.2.2 Standard Functions 2-7 

2.2.3 ALU Input/Output Registers 2-8 

2.2.4 Multiprecision Capability 2-8 

2.2.5 ALU Saturation Mode 2-8 

2.2.6 ALU Overflow Latch Mode 2-9 



2.2.7 Division 2-9 

2.2.8 ALU Status . 2-13 

2.3 MULTIPLIER/ ACCUMULATOR (MAC) 2-13 

2.3.1 MAC Block Diagram Discussion 2-13 

2.3.2 MAC Operations 2-16 

2.3.2.1 Standard Functions 2-16 

2.3.2.2 Input Formats 2-18 

2.3.2.3 MAC Input/Output Registers 2-18 

2.3.2.4 MR Register Operation 2-18 

2.3.2.5 MAC Overflow And Saturation 2-19 

2.3.2.6 Rounding Mode 2-20 

2.32.7 Biased Rounding (ADSP-217x/218x/21msp5x) 2-21 

2.4 BARREL SHIFTER 2-22 

2.4.1 Shifter Block Diagram Discussion 2-22 

2.4.2 Shifter Operations 2-28 

2.4.2.1 Shifter Input/Output Registers 2-28 

2.4.2.2 Derive Block Exponent 2-29 

2.4.2.3 Immediate Shifts 2-30 

2.4.2.4 Denormalize 2-31 

2.4.2.5 Normalize 2-33 

CHAPTER 3 PROGRAM CONTROL 

3.1 OVERVIEW 3-1 

3.2 PROGRAM SEQUENCER 3-1 

3.2.1 Next Address Select Logic 3-3 

3.2.2 Program Counter & PC Stack 3-4 

3.2.3 Loop Counter & Stack 3-4 

3.2.4 Loop Comparator & Stack 3-5 

3.3 PROGRAM CONTROL INSTRUCTIONS 3-8 

3.3.1 JUMP Instruction 3-8 

3.3. 1 . 1 Register Indirect JUMPs 3-8 

3.3.2 CALL Instruction 3-9 

3.3.3 DO UNTIL Loops 3-9 

3.3.4 IDLE Instruction 3-10 

3.3.4.1 Slow IDLE 3-10 

3.4 INTERRUPTS 3-11 

3.4.1 Interrupt Servicing Sequence 3-14 

3.4.2 Configuring Interrupts ....3-14 

3.4.2.1 Interrupt Control Register (ICNTL) 3-15 

3.4.2.2 Interrupt Mask Register (IMASK) 3-16 

3.4.2.3 Global Enable /Disable For Interrupts 3-17 

3.4.2.4 Interrupt Force & Clear Register (IFC) 3-18 

3.4.3 Interrupt Latency 3-18 

3.4.3.1 Timer Interrupt Latency (ADSP-2101/2105/21 11/21 15) ....3-19 



3.5 STATUS REGISTERS & STATUS STACK 3-20 

3.5.1 Arithmetic Status Register (ASTAT) 3-20 

3.5.2 Stack Status Register (SSTAT) 3-21 

3.5.3 Mode Status Register (MSTAT) 3-22 

3.6 CONDITIONAL INSTRUCTIONS 3-24 

3.7 TOPPCSTACK 3-25 

3.7.1 TOPPCSTACK Restrictions 3-27 


CHAPTER 4 DATA TRANSFER 


4.1 OVERVIEW 4-1 

4.2 DATA ADDRESS GENERATORS (DAGS) 4-1 

4.2.1 DAG Registers 4-1 

4.2.2 Indirect Addressing 4-3 

4.2.2.1 Initialize L Registers To 0 For Non-Circular Addressing 4-3 

4.2.3 Modulo Addressing (Circular Buffers) 4-4 

4.2.4 Calculating The Base Address 4-5 

4.2.4. 1 Circular Buffer Base Address Example 1 4-5 

4.2.4.2 Circular Buffer Base Address Example 2 4-5 

4.2.4.3 Circular Buffer Operation Example 1 4-5 

4.24.4 Circular Buffer Operation Example 2 4-6 

4.2.5 Bit-Reverse Addressing 4-6 

4.3 PROGRAMMNG DATA ACCESSES 4-7 

4.3.1 Variables & Arrays 4-7 

4.3.2 Circular Buffers 4-8 

4.4 PMD-DMD BUS EXCHANGE 4-9 

4.4.1 PMD-DMD Block Diagram Discussion 4-9 


CHAPTER 5 SERIAL PORTS 


5.1 OVERVIEW 5-1 

5.2 BASIC SPORT DESCRIPTION 5-1 

5.2.1 Interrupts 5-4 

5.2.2 SPORT Operation 5-4 

5.3 SPORT PROGRAMMING 5-4 

5.3.1 SPORT Configuration 5-5 

5.3.2 Receiving And Transmitting Data 5-6 

5.4 SPORT ENABLE 5-7 

5.5 SERIAL CLOCKS 5-8 

5.6 WORD LENGTH 5-9 

5.7 WORD FRAMING OPTIONS 5-10 

5.7.1 Frame Synchronization 5-10 

5.7.2 Frame Sync Signal Source 5-11 

5.7.3 Normal And Alternate Framing Modes 5-13 

5.7.4 Active High Or Active Low 5-14 



5.8 CONFIGURATION EXAMPLE 5-15 

5.9 TIMING EXAMPLES 5-16 

5.10 COMPANDING AND DATA FORMAT 5-23 

5.10.1 Companding Operation Example 5-24 

5.10.2 Contention For Companding Hardware ..5-25 

5.10.3 Companding Internal Data 5-25 

5.11 AUTOBUFFERING 5-26 

5.11.1 Autobuffering Control Register 5-27 

5.11.2 Autobuffering Example 5-28 

5.12 MULTICHANNEL FUNCTION 5-30 

5.12.1 Multichannel Setup 5-30 

5.12.2 Multichannel Operation 5-32 

5.13 SPORT TIMING CONSIDERATIONS 5-34 

5.13.1 Companding Delay 5-34 

5.13.2 Clock Synchronization Delay 5-34 

5.13.2.1 Startup Timing 5-34 

5.13.3 Internally Generated Frame Sync Timing 5-34 

5.13.4 Transmit Interrupt Timing 5-36 

5.13.5 Receive Interrupt Timing 5-36 

5.13.6 Interrupt And Autobuffer Synchronization 5-38 

5.13.7 Instruction Completion Latencies 5-38 

5.13.8 Interrupt And Autobuffer Service Example 5-39 

5.13.9 Receive Companding Latency 5-40 

5.13.10 Interrupts With Autobuffering Enabled 5-41 

5.13.11 Unusual Complications 5-42 


CHAPTER 6 TIMER 


6.1 OVERVIEW 6-1 

6.2 TIMER ARCHITECTURE 6-1 

6.3 RESOLUTION 6-3 

6.4 TIMER OPERATION 6-3 



CHAPTER 7 


HOST INTERFACE PORT 


7.1 OVERVIEW 7-1 

7.2 HIP PIN SUMMARY 7-2 

7.3 HIP FUNCTIONAL DESCRIPTION 7-4 

7.4 HIP OPERATION 7-6 

7.4.1 Polled Operation 7-7 

7.4.1. 1 HIP Status Synchronization 7-8 

7.4.2 Interrupt-Driven Operation 7-9 

7.4.3 HDR Overwrite Mode 7-9 

7.4.4 Software Reset 7-1 0 

7.5 HIP INTERRUPTS 7-10 

7.6 HOST INTERFACE TIMING 7-11 

7.7 BOOT LOADING THROUGH THE HIP 7-16 


CHAPTER 8 ANALOG INTERFACE 


8.1 OVERVIEW 8-1 

8.2 A/D CONVERSION 8-2 

8.2.1 Analog Input 8-2 

8.2.2 ADC 8-3 

8.2.2.1 Decimation Filter 8-4 

8.2.2.2 High Pass Filter 8-5 

8.3 D/ A CONVERSION 8-6 

8.3.1 DAC 8-6 

8.3.1. 1 High Pass Filter 8-6 

8.3. 1 .2 Interpolation Filter 8-7 

8.3.1. 3 Analog Smoothing Filter & Programmable Gain Amp. ...8-8 

8.3.2 Differential Output Amplifier 8-8 

8.4 OPERATING THE ANALOG INTERFACE 8-9 

8.4.1 Memory-Mapped Control Registers 8-9 

8.4.1. 1 Analog Control Register 8-9 

8.4.1.2 Analog Autobuffer/Powerdown Register 8-10 

8.4.2 Memory-Mapped Data Registers 8-11 

8.4.3 ADC & DAC Interrupts 8-12 

8.4.3.1 Autobuffering Disabled 8-12 

8.4.3.2 Autobuffering Enabled 8-13 

8.5 CIRCUIT DESIGN CONSIDERATIONS 8-16 

8.5.1 Analog Signal Input 8-16 

8.5.2 Analog Signal Output 8-18 

8.5.3 Voltage Reference Filter Capacitance 8-19 



CHAPTER 9 


SYSTEM INTERFACE 


9.1 OVERVIEW 9-1 

9.2 CLOCK SIGNALS 9-3 

9.2.1 Synchronization Delay 9-3 

9.2.2 lx & l/2x Clock Considerations 9-4 

9.3 RESET 9-4 

9.4 SOFTWARE-FORCED REBOOTING 9-4 

9.4.1 ADSP-2181 Register Values For BDMA Booting 9-13 

9.5 EXTERNAL INTERRUPTS 9-14 

9.5.1 Interrupt Sensitivity 9-14 

9.6 FLAG PINS 9-15 

9.7 POWERDOWN 9-17 

9.7.1 Powerdown Control 9-18 

9.7.2 Entering Powerdown 9-19 

9.7.3 Exiting Powerdown 9-20 

9.7.3.1 Ending Powerdown With The PWD Pin 9-20 

9.7.3.2 Ending Powerdown With The RESET Pin 9-21 

9.7.4 Startup Time After Powerdown 9-21 

9.7.4.1 Systems Using An External TTL/ CMOS Clock ... 9-21 

9.7.4.2 Systems Using A Crystal/Internal Oscillator 9-22 

9.7.5 Operation During Powerdown 9-23 

9.7.5.1 Interrupts & Flags 9-23 

9.7.5.2 SPORTS 9-23 

9.7.5.3 HIP During Powerdown 9-24 

9.7.54 IDMA Port During Powerdown (ADSP-2181) 9-25 

9.7.5.5 BDMA Port During Powerdown (ADSP-2181) 9-26 

9.7.5.6 Analog Interface (ADSP-21msp5x) 9-26 

9.7.6 Conditions For Lowest Power Consumption 9-26 

9.7.7 PWDACK Pin 9-29 

9.7.8 Using Powerdown As A Non-Maskable Interrupt 9-30 


CHAPTER 10 MEMORY INTERFACE 


10.1 OVERVIEW 10-1 

10.2 PROGRAM MEMORY INTERFACE 10-3 

10.2.1 External Program Memory Read/Write 10-3 

10.2.2 Program Memory Maps 10-5 

10.2.3 ROM Program Memory Maps 1 0-6 

10.3 DATA MEMORY INTERFACE 10-10 

10.3.1 External Data Memory Read /Write 10-10 

10.3.2 Data Memory Maps 10-11 

10.3.3 Memory-Mapped Peripherals 10-14 



10.4 BOOT MEMORY INTERFACE 10-15 

10.4.1 Boot Pages 10-15 

10.4.2 Powerup Boot & Software Reboot 10-16 

10.4.3 Boot Memory Access 10-17 

10.4.4 Boot Loading Sequence 10-17 

10.5 BUS REQUEST/GRANT 10-21 

10.6 ADSP-2181 MEMORY INTERFACES 10-23 

10.6.1 ADSP-2181 Program Memory Interface 10-25 

10.6.2 ADSP-2181 Data Memory Interface 10-30 

10.6.3 ADSP-2181 Byte Memory Interface 10-32 

10.6.4 ADSP-2181 1/ O Memory Space 10-32 

10.6.5 ADSP-2181 Composite Memory Select 10-35 

10.6.6 External Memory Read - Overlays & I/O Memory 10-36 

10.6.7 External Memory Write - Overlays & I/O Memory 10-37 


10.7 MEMORY INTERFACE SUMMARY (ALL PROCESSORS) .... 10-37 


CHAPTER 11 DMA PORTS 


11.1 OVERVIEW 11-1 

11.2 BDMA PORT 11-2 

1 1 .2. 1 BDMA Port Functional Description 11-4 

1 1 .2.2 BDMA Control Registers 1 1-4 

1 1 .2.3 Byte Memory Word Formats 1 1-9 

1 1 .2.4 BDMA Booting 11-9 

1 1 .2.4.1 Development Software Features for BDMA Booting 1 1-1 1 

11.3 IDMA PORT 11-12 

11.3.1 IDMA Port Pin Summary 11-12 

11.3.2 IDMA Port Functional Description 1 1-14 

11.3.3 Modifying Control Registers for IDMA 11-16 

11.3.4 IDMA Timing 11-17 

11.3.4.1 Address Latch Cycle 11-17 

11.3.4.2 Long Read Cycle 11-18 

1 1 .3.4.3 Short Read Cycle 1 1-20 

1 1 .3.4.4 Long Write Cycle 1 1-21 

1 1 .3.4.5 Short Write Cycle 1 1-23 

1 1 .3.5 Boot Loading Through The IDMA Port 1 1-24 

1 1 .3.6 DMA Cycle Stealing, DMA Hold Offs, and LACK 11-25 



CHAPTER 12 


PROGRAMMING MODEL 


12.1 OVERVIEW 12-1 

12.1 .1 Data Address Generators 12-2 

12.1 .1 .1 Always Initialize L Registers 12-2 

12.1 .2 Program Sequencer 12-4 

12.1.2.1 Interrupts 12-4 

12.1.2.2 Loop Counts 12-4 

12.1.2.3 Status And Mode Bits 12-5 

12.1.2.4 Stacks 12-5 

12.1 .3 Computational Units 12-6 

12.1.4 Bus Exchange 12-6 

12.1.5 Timer 12-6 

12.1 .6 Serial Ports 12-7 

12.1.7 Memory Interface & SPORT Enables 1 2-7 

12.1.8 Host Interface 1 2-8 

12.1.9 Analog Interface 1 2-8 

12.2 PROGRAM EXAMPLE 12-8 

1 2.2. 1 Example Program: Setup Routine Discussion 1 2-1 0 

1 2.2.2 Example Program: Interrupt Routine Discussion 1 2-1 1 


CHAPTER 13 HARDWARE EXAMPLES 


13.1 OVERVIEW 13-1 

13.2 BOOT LOADING FROM HOST USING BUS REQUEST 13-2 

13.3 SERIAL PORT TO CODEC INTERFACE 13-5 

13.4 SERIAL PORT TO DAC INTERFACE 13-8 

13.5 SERIAL PORT TO ADC INTERFACE 13-10 

13.6 SERIAL PORT TO SERIAL PORT INTERFACE 13-12 

13.7 80C51 INTERFACE TO HOST INTERFACE PORT 13-13 


CHAPTER 14 SOFTWARE EXAMPLES 


14.1 OVERVIEW 14-1 

14.2 SYSTEM DEVELOPMENT PROCESS 14-2 

14.3 SINGLE-PRECISION FIR TRANSVERSAL FILTER 14-4 

14.4 CASCADED BIQUAD HR FILTER 14-6 

14.5 SINE APPROXIMATION 14-7 

14.6 SINGLE-PRECISION MATRIX MULTIPLY 14-9 

14.7 RADIX-2 DECIMATION-IN-TIME FFT 14-11 

14.7.1 Main Module 14-11 

14.7.2 DIT FFT Subroutine 14-13 

14.7.3 Bit-Reverse Subroutine 14-18 

14.7.4 Block Floating-Point Scaling Subroutine 14-19 



CHAPTER 15 


INSTRUCTION SET REFERENCE 


15.1 QUICK LIST OF INSTRUCTIONS 15-1 

15.2 OVERVIEW 15-2 

15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS 15-3 

15.4 MULTIFUNCTION INSTRUCTIONS 15-4 

15.4.1 ALU/MAC With Data & Program Memory Read 15-4 

15.4.2 Data & Program Memory Read 15-6 

15.4.3 Computation With Memory Read 15-6 

15.4.4 Computation With Memory Write 15-6 

15.4.5 Computation With Data Register Move 15-7 

15.5 ALU, MAC & SHIFTER INSTRUCTIONS 15-9 

15.5.1 ALU Group 15-9 

15.5.2 MAC Group 15-10 

15.5.3 Shifter Group 15-11 

15.6 MOVE: READ & WRITE 15-12 

15.7 PROGRAM FLOW CONTROL 15-14 

15.8 MISCELLANEOUS INSTRUCTIONS 15-16 

15.9 EXTRA CYCLE CONDITIONS 15-18 

15.9.1 Multiple Off-Chip Memory Accesses 15-18 

15.9.2 Wait States 15-18 

15.9.3 SPORT Autobuffering & DMA 15-18 

15.10 INSTRUCTION SET SYNTAX 15-19 

15.10.1 Punctuation & Multifunction Instructions 15-19 

15.10.2 Syntax Notation Example 15-19 

15.10.3 Status Register Notation 15-20 

ALU Add/ Add with Carry 15-23 

Subtract X-Y/Subtract X-Y with Borrow 15-25 

Subtract Y-X/Subtract Y-X with Borrow 15-27 

AND, OR, XOR 15-29 

Test Bit, Clear Bit, Set Bit, Toggle Bit 15-31 

Pass/ Clear 15-33 

Negate 15-35 

NOT 15-36 

Absolute Value 15-37 

Increment 15-38 

Decrement 15-39 

Divide 15-40 

Generate ALU Status 15-42 



MAC Multiply 15-43 

Multiply/ Accumulate 15-45 

Multiply /Subtract 15-47 

Clear 15—49 

Transfer MR 15-50 

Conditional MR Saturation 15-51 

SHIFTER 

Arithmetic Shift 15-52 

Logical Shift 15-54 

Normalize 15-56 

Derive Exponent 15-58 

Block Exponent Adjust 15-60 

Arithmetic Shift Immediate 15-62 

Logical Shift Immediate 15-64 

MOVE 

Register Move 15-65 

Load Register Immediate 15-67 

Data Memory Read (Direct Address) 15-69 

Data Memory Read (Indirect Address) 15-70 

Program Memory Read (Indirect Address) 15-71 

Data Memory Write (Direct Address) 15-72 

Data Memory Write (Indirect Address) 15-73 

Program Memory Write (Indirect Address) 15-75 

I/O Space Read/ Write 15-76 

PROGRAM FLOW 

JUMP 15-77 

CALL 15-78 

JUMP or CALL on Flag In Pin 15-79 

Modify Flag Out Pin 15-80 

Return From Subroutine (RTS) 15-81 

Return From Interrupt (RTI) 15-82 

Do Until 15-83 

IDLE 15-85 



MISC 


Stack Control 15-86 

Mode Control 15-89 

Modify Address Register 15-91 

NOP 15-92 

Interrupt Enable/Disable 15-93 

MULTIFUNCTION 

ALU/MAC/SHEFT Operation with Memory Read 15-94 

ALU/MAC/ SHUT Operation with Register to Register Move 15-98 

ALU/MAC/ SHIFT Operation with Memory Write 15-101 

Data & Program Memory Read 15-105 

ALU/MAC Operation with Data & Program Memory Read 15-106 


APPENDIX A INSTRUCTION CODING 


A.l OPCODES A-l 

A.2 ABBREVIATION CODING A-7 


APPENDIX B DIVISION EXCEPTIONS 


B.l DIVISION FUNDAMENTALS . B-l 

B.1.1 Signed Division B-l 

B.l. 2 Unsigned Division B-2 

B. 1 .3 Output Formats B-2 

B. 1 .4 Integer Division B-3 

B.2 ERROR CONDITIONS B-3 

B.2.1 Negative Divisor Error B-3 

B.2.2 Unsigned Division Error B-4 

B.3 SOFTWARE SOLUTION B-4 


APPENDIX C NUMERIC FORMATS 


C.l OVERVIEW C-l 

C.2 UNSIGNED OR SIGNED: TWOS-COMPLEMENT FORMAT...C-1 

C.3 INTEGER OR FRACTIONAL C-l 

C.4 BINARY MULTIPLICATION C-3 

C.4.1 Fractional Mode And Integer Mode C^l 

C.5 BLOCK FLOATING-POINT FORMAT C-5 



APPENDIX D INTERRUPT VECTOR ADDRESSES 


D. l INTERRUPT VECTOR ADDRESSES D-l 

APPENDIX E CONTROL/STATUS REGISTERS 

E. l OVERVIEW E-l 


INDEX 



Introduction h 1 


1.1 OVERVIEW 

The ADSP-2100 family is a collection of programmable single-chip 
microprocessors that share a common base architecture optimized for 
digital signal processing (DSP) and other high-speed numeric processing 
applications. The various family processors differ principally in the type 
of on-chip peripherals they add to the base architecture. On-chip memory, 
a timer, serial port(s), and parallel ports are available in different members 
of the family. In addition, the ADSP-21msp58/ 59 processors include an 
on-chip analog interface for voiceband signal conversion. 

This manual provides the information necessary to understand and 
evaluate the processors' architecture, and to determine which device best 
meets your needs for a particular application. Together with the data 
sheets describing the individual devices, this manual provides all the 
information required to design a DSP system. Complete reference material 
for programmers is also included. 

1.1.1 Functional Units 

Table 1.1 on the following page lists the main functional units of the 
ADSP-21xx architecture, and shows which functions are included on each 
of the processors. 

• Computational Units — Every processor in the ADSP-2100 family 
contains three independent, full-function computational units: an 
arithmetic/logic unit (ALU), a multiplier /accumulator (MAC) and a 
barrel shifter. The computational units process 16-bit data directly and 
also provide hardware support for multiprecision computations. 

• Data Address Generators & Program Sequencer — Two dedicated address 
generators and a program sequencer supply addresses for on-chip or 
external memory access. The sequencer supports single-cycle 
conditional branching and executes program loops with zero 
overhead. Dual data address generators allow the processor to 
generate simultaneous addresses for dual operand fetches. 

Together the sequencer and data address generators keep the 
computational units continuously working, maximizing throughput. 


i-i 





Feature 

2101 

2103 

2105 

2115 

2111 

2171 

2173 

2181 

2183 21msp58 

Arithmetic/Logic Unit 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Multiply/ Accumulator 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Shifter 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Data Address Generators 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Program Sequencer 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Data Memory RAM 

IK 

IK 

512 

512 

IK 

2K 

2K 

16K 

16K 

2K 

Program Memory RAM 

2K 

2K 

IK 

IK 

2K 

2K 

2K 

16K 

16K 

2K 

Timer 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Serial Port 0 (Multichannel) 

• 

• 

- 

• 

• 

• 

• 

• 

• 

• 

Serial Port 1 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Host Interface Port 

- 

- 

- 

- 

• 

• 

• 

- 

- 

• 

DMA Ports 

- 

- 

- 

- 

- 

- 

- 

• 

• 

- 

Analog Interface 

- 

- 

- 

- 

- 

- 

- 

- 

- 

• 

Supply Voltage 

5V 

3.3V 

5V 

5V 

5V 

5V 

3.3V 

5V 

3.3V 

5V 

Instruction Rate (MIPS) 

20 

10 

13.8 

20 

20 

33 

20 

33 

33 

26 


. Table 1 .1 ADSP-2100 Family Processor Features & On-Chip Peripherals 


• Memory — The ADSP-2100 family uses a modified Harvard architecture 
in which data memory stores data, and program memory stores both 
instructions and data. All ADSP-2100 family processors contain on- 
chip RAM that comprises a portion of the program memory space and 
data memory space. The speed of the on-chip memory allows the 
processor to fetch two operands (one from data memory and one from 
program memory) and an instruction (from program memory) in a 
single cycle. 

• Serial Ports — The serial ports (SPORTs) provide a complete serial 
interface with hardware companding for data compression and 
expansion. Both p-law and A-law companding are supported. The 
SPORTs interface easily and directly to a wide variety of popular serial 
devices. Each SPORT can generate a programmable internal clock or 
accept an external clock. SPORTO includes a multichannel option. 

• Timer — A programmable timer /counter with 8-bit prescaler provides 
periodic interrupt generation. 

• Host Interface Port — The Host Interface Port (HIP) allows direct 
connection (with no glue logic) to a host processor. The HIP is made up 
of 16 data pins and 11 control pins. The HIP is extremely flexible and 
has provisions to allow simple interface to a variety of host processors. 
For example, the Motorola 68000, the Intel 8051, or another ADSP-2100 
family processor can be easily connected to the HIP. 


1-2 








• DMA Ports — The ADSP-2181's Internal DMA Port (IDMA) and Byte DMA 
Port (BDMA) provide efficient data transfers to and from internal memory. 
The IDMA port has a 16-bit multiplexed address and data bus and supports 
24-bit program memory. The IDMA port is completely asynchronous and 
can be written to while the ADSP-2181 is operating at full speed. The byte 
memory DMA port allows boot loading and storing of program instructions 
and data. 

• Analog Interface — The ADSP-21msp58/59 processors include on-chip 
circuitry for mixed analog and digital signal processing. This circuitry 
includes an analog-to-digital converter (ADC), a digital-to-analog converter 
(DAC), analog and digital filters, and a parallel interface to the processor's 
core. The converters use sigma-delta technology to capture data samples 
from a highly oversampled signal. 

The ADSP-2100 family architecture exhibits a high degree of parallelism, 
tailored to DSP requirements. In a single cycle, any device in the family can: 

• Generate the next program address. 

• Fetch the next instruction. 

• Perform one or two data moves. 

• Update one or two data address pointers. 

• Perform a computation. 

In that same cycle, processors which have the relevant functional units can also: 

• Receive and/or transmit data via the serial port(s). 

• Receive and/or transmit data via the host interface port. 

• Receive and/ or transmit data via the DMA ports. 

• Receive and/ or transmit data via the analog interface. 

1 .1 .2 Memory And System Interface 

In each ADSP-21xx processor, four on-chip buses connect internal memory with 
the other functional units: Data Memory Address bus, Data Memory Data bus. 
Program Memory Address bus, and Program Memory Data bus. A single 
external address bus and and a single external data bus are extended off-chip; 
these buses can be used for either program or data memory access. 

External devices can gain control of the processor's buses with the bus request 
and grant signals (BR, BG). The ADSP-21xx processors can continue running 
while the buses are granted to another device, as long as an external memory 
operation is not required. 


1-3 



The ADSP-21xx processors support memory-mapped peripherals with 
programmable wait state generation. 

Boot circuitry provides for loading on-chip program memory 
automatically after reset. This can be done either through the memory 
interface from a single low-cost EPROM, through the host interface port 
from a host processor, or through the BDMA port of the ADSP-2181. 
Multiple programs can be selected and loaded with no additional 
hardware. 

ADSP-2100 family processors differ in their response to interrupts. In all 
cases, however, the program sequencer allows the processor to respond 
with minimum latency. Interrupts can be nested with no additional 
latency. External interrupts can be configured as edge- or level-sensitive. 
Internal interrupts can be generated from the timer, the host interface port, 
the serial ports, and the BDMA port. 

1.1.3 Instruction Set 

The ADSP-2100 family shares a single unified instruction set designed for 
upward compatibility with higher-integration devices. The ADSP-2171, 
ADSP-2181, and ADSP-21msp58/59 processors have a number of 
additional and enhanced instructions. 

The ADSP-2100 family instruction set provides flexible data moves. 
Multifunction instructions combine one or more data moves with a 
computation. Every instruction can be executed in a single processor cycle. 
The assembly language uses an algebraic syntax for readability and ease of 
coding. A comprehensive set of software and hardware tools supports 
program development. 

1.1.4 DSP Performance 

Signal processing applications make special performance demands which 
distinguish DSP architectures from other microprocessor and 
microcontroller architectures. Not only must instruction execution be fast, 
but DSPs must also perform well in each of the following areas: 

• Fast and Flexible Arithmetic — The ADSP-2100 family base architecture 
provides single-cycle computation for multiplication, multiplication 
with accumulation, arbitrary amounts of shifting, and standard 
arithmetic and logical operations. In addition, the arithmetic units 
allow for any sequence of computations so that a given DSP algorithm 
can be executed without being reformulated. 




• Extended Dynamic Range — Extended sums-of-products, common in DSP 
algorithms, are supported in the multiply/ accumulate units of the 
ADSP-2100 family. A 40-bit accumulator provides eight bits of 
protection against overflow in successive additions to ensure that no 
loss of data or range occurs; 256 overflows would have to occur before 
any data is lost. Special instructions are provided for implementing 
block floating-point scaling of data. 

• Single-Cycle Fetch of Two Operands — In extended sums-of-products 
calculations, two operands are needed on each cycle to feed the 
calculation. All members of the ADSP-2100 family are able to sustain 
two-operand data throughput, whether the data is stored on-chip or 
off. 

• Hardware Circular Buffers — A large class of DSP algorithms, including 
digital filters, requires circular data buffers. The ADSP-2100 family 
base architecture includes hardware to handle address pointer 
wraparound, simplifying the implementation of circular buffers both 
on- and off-chip, and reducing overhead (thereby improving 
performance). 

• Zero-Overhead Looping and Branching — DSP algorithms are repetitive 
and are most logically expressed as loops. The program sequencer in 
the ADSP-2100 family supports looped code with zero overhead, 
combining excellent performance with the clearest program structure. 
Likewise, there are no overhead penalties for conditional branches. 


1.2 CORE ARCHITECTURE 

This section describes the core architecture of the ADSP-2100 family, as 
shown in Figure 1.1. Each component of the core architecture is described 
in detail in different chapters of this manual, as shown below: 


Arithmetic/logic unit (ALU) 
Multiplier/ accumulator (MAC) 

Barrel shifter 

Program sequencer 

Status registers and stacks 

Two data address generators (DAGs) 

PMD-DMD bus exchange (PX registers) 


Chapter 2, Computation Units 
Chapter 2, Computation Units 
Chapter 2, Computation Units 
Chapter 3, Program Control 
Chapter 3, Program Control 
Chapter 4, Data Transfer 
Chapter 4, Data Transfer 


1-5 




1.2.1 Computational Units 

Every processor in the ADSP-2100 family contains three independent, full- 
function computational units: an arithmetic/logic unit (ALU), a 
multiplier/ accumulator (MAC) and a barrel shifter. The computation 
units process 16-bit data directly and provide hardware support for 
multiprecision computation as well. 

The ALU performs a standard set of arithmetic and logic operations in 
addition to division primitives. The MAC performs single-cycle multiply, 
multiply/ add and multiply/ subtract operations. The shifter performs 
logical and arithmetic shifts, normalization, denormalization, and derive- 
exponent operations. The shifter implements numeric format control 
including multiword floating-point representations. The computational 
units are arranged side-by-side instead of serially so that the output of any 
unit may be the input of any unit on the next cycle. The internal result (R) 
bus directly connects the computational units to make this possible. 











All three units contain input and output registers which are accessible 
from the internal data memory data (DMD) bus. Computational 
operations generally take their operands from input registers and load the 
result into an output register. The registers act as a stopover point for data 
between memory and the computational circuitry. This feature introduces 
one level of pipelining on input, and one level on output. The R bus allows 
the result of a previous computation to be used directly as the input to 
another computation. This avoids excessive pipeline delays when a series 
of different operations are performed. 

1 .2.2 Address Generators & Program Sequencer 

Two dedicated data address generators and a powerful program 
sequencer ensure efficient use of the computational units. The data 
address generators (DAGs) provide memory addresses when memory 
data is transferred to or from the input or output registers. Each DAG 
keeps track of up to four address pointers. When a pointer is used for 
indirect addressing, it is post-modified by a value in a specified register. 
With two independent DAGs, the processor can generate two addresses 
simultaneously for dual operand fetches. 

A length value may be associated with each pointer to implement 
automatic modulo addressing for circular buffers. (The circular buffer 
feature is also used by the serial ports for automatic data transfers. Refer 
to the Serial Ports chapter for additional information.) 

DAG1 can supply addresses to data memory only; DAG2 can supply 
addresses to either data memory or program memory. When the 
appropriate mode bit is set in the mode status register (MSTAT), the 
output address of DAG1 is bit-reversed before being driven onto the 
address bus. This feature facilitates addressing in radix-2 Fast Fourier 
Transform (FFT) algorithms. 

The program sequencer supplies instruction addresses to the program 
memory. The sequencer is driven by the instruction register which holds 
the currently executing instruction. The instruction register introduces a 
single level of pipelining into the program flow. Instructions are fetched 
and loaded into the instruction register during one processor cycle, and 
executed during the following cycle while the next instruction is 
prefetched. To minimize overhead cycles, the sequencer supports 
conditional jumps, subroutine calls and returns in a single cycle. With an 
internal loop counter and loop stack, the processor executes looped code 
with zero overhead. No explicit jump instructions are required to loop. 



1.2.3 Buses 

The processors have five internal buses. The program memory address 
(PMA) and data memory address (DMA) buses are used internally for the 
addresses associated with program and data memory. The program 
memory data (PMD) and data memory data (DMD) buses are used for the 
data associated with the memory spaces. The buses are multiplexed into a 
sing le exte rnal address bus and a single external data bus; the BMS, DM5 
and PMS signals select the different address spaces. The R bus transfers 
intermediate results directly between the various computational units. 

The PMA bus is 14 bits wide allowing direct access of up to 16K words of 
mixed instruction code and data. The PMD bus is 24 bits wide to 
accommodate the 24-bit instruction width. 

The DMA bus is 14 bits wide allowing direct access of up to 16 K words of 
data. The data memory data (DMD) bus is 16 bits wide. The DMD bus 
provides a path for the contents of any register in the processor to be 
transferred to any other register or to any data memory location in a single 
cycle. The data memory address comes from two sources: an absolute 
value specified in the instruction code (direct addressing) or the output of 
a data address generator (indirect addressing). Only indirect addressing is 
supported for data fetches from program memory. 

The program memory data (PMD) bus can also be used to transfer data to 
and from the computational units through direct paths or via the PMD- 
DMD bus exchange unit. The PMD-DMD bus exchange unit permits data 
to be passed from one bus to the other. It contains hardware to overcome 
the 8-bit width discrepancy between the two buses, when necessary. 


1.3 ON-CHIP PERIPHERALS 

This section describes the additional functional units which are included 
in various processors of the ADSP-2100 family. 

1.3.1 Serial Ports 

Most ADSP-21xx processors have two bidirectional, double-buffered serial 
ports (SPORTs) for serial communications. The SPORTs are synchronous 
and use framing signals to control data flow. Each SPORT can generate its 
serial clock internally or use an external clock. The framing sync signals 
may be generated internally or by an external device. Word lengths may 
vary from three to sixteen bits. One serial port, SPORTO, has a 
multichannel capability that allows the receiving or transmitting of 
arbitrary data words from a 24-word or 32-word bitstream. The other 



serial port, SPORT1, m ay opt ionally be configured as two additional 
external interrupt pins (IKQT and IRQ0)and the Flag Out (FO) and Flag In 
(FI) pins. 

1.3.2 Timer 

The programmable interval timer provides periodic interrupt generation. 
An 8-bit prescaler register allows the timer to decrement a 16-bit count 
register over a range from each cycle to every 256 cycles. An interrupt is 
generated when this count register reaches zero. The count register is 
automatically reloaded from a 16-bit period register and the count 
resumes immediately. 

1.3.3 Host Interface Port (ADSP-2111, ADSP-2171, ADSP-21msp5x) 

The host interface port (HIP) is a parallel I/O port that allows for an easy 
connection to a host processor. Through the HIP, an ADSP-21xx DSP can 
be used as a memory-mapped peripheral of the host. The HIP operates in 
parallel with and asynchronous to the ADSP-21xx's computational core 
and internal memory. The host interface port consists of registers through 
which the ADSP-21xx and the host processor pass data and status 
information. The HIP can be configured for: an 8-bit data bus or 16-bit 
data bus; a multiplexed address/data bus or separate address and data 
buses; and separate read and write strobes or a read/ write strobe and a 
data strobe. 

1.3.4 DMA Ports (ADSP-2181) 

The ADSP-2181 contains two DMA ports, and Internal DMA Port and a 
Byte DMA Port. The IDMA port provides an efficient means of 
communication between a host system and the DSP. The port is used to 
access the on-chip program memory and data memory of the DSP with 
only one cycle per word of overhead. The IDMA port has a 16-bit 
multiplexed address and data bus and supports 24-bit program memory. 
The IDMA port is completely asynchronous and can be written to while 
the ADSP-2181 is operating at full speed. 

The internal memory address is latched and then automatically 
incremented after each IDMA transaction. An external device can 
therefore access a block of sequentially addressed memory by specifying 
only the starting address of the block. 

The byte memory DMA controller allows loading and storing of program 
instructions and data using the byte memory space. The BDMA circuit is 
able to access the byte memory space while the processor is operating 
normally and steals only one processor cycle per 8-, 16- or 24-bit word 
transferred. 



1.3.5 Analog Interface 

The analog interface of the ADSP-21msp58/59 consists of input amplifiers 
and a 16-bit sigma-delta analog-to-digital converter (ADC) as well as a 
sigma-delta digital-to-analog converter (DAC) and a differential output 
amplifier. 


1.4 ADSP-2100 FAMILY DEVELOPMENT TOOLS 

The ADSP-2100 family is supported with a complete set of software and 
hardware development tools. The ADSP-2100 Family Development 
System includes software utilities for program development and EZ Tools 
for hardware/ software debugging. 

The Development Software includes: 

• System Builder — The System Builder defines the architecture of your 
hardware system. This includes the specification of the amount of 
external memory available and any memory-mapped I/O ports. 

• Assembler — The Assembler assembles the source code and data 
modules as well as supporting the high-level syntax of the instruction 
set. In addition to supporting a full range of system diagnostics, the 
Assembler provides flexible macro processing, include files, and 
modular code development. 

• Linker — The Linker links separately assembled modules. It maps the 
linked code and data output to the target system hardware, as 
specified by the System Builder output. 

• Simulator — The Simulator performs an interactive, instruction-level 
simulation of the hardware configuration described by the System 
Builder. It flags illegal operations and supports full symbolic assembly 
and disassembly. 

• PROM Splitter — This module reads the Linker output and generates 
PROM programmer compatible files. 

• C Compiler — The C Compiler reads ANSI C source and outputs ADSP- 
2100 family source code ready to be assembled. It also supports inline 
assembler code. 

The EZ-ICE® emulators provide hardware-based debugging of ADSP-21xx 
systems. The EZ-ICEs perform stand-alone, in-circuit emulation with little 
or no degradation in processor performance. 



The EZ-LAB® evaluation boards are low-cost, basic hardware platforms 
for running example applications. 

For additional information on the development tools, refer to the 
ADSP-2100 Family Development Tools Data Sheet. 


1 .5 ORGANIZATION OF THIS MANUAL 

This manual is organized as follows. 

Chapters 2, 3, and 4 describe the core architectural features shared by all 
members of the ADSP-2100 family: 

• Chapter 2, "Computational Units," describes the functions and internal 
organization of the arithmetic/logic unit (ALU), the multiplier/ 
accumulator (MAC), and the barrel shifter. 

• Chapter 3, "Program Control," describes the program sequencer, 
interrupt controller and status and condition logic. 

• Chapter 4, "Data Transfer," describes the data address generators 
(DAGs) and the PMD-DMD bus exchange unit. 

Chapters 5, 6, 7, and 8 describe the additional functional units included in 
different members of the ADSP-2100 family. (See Table 1.1 for a list of the 
functions included in each device.) 

• Chapter 5, "Serial Ports," describes the serial ports, SPORTO and 
SPORT1. 

• Chapter 6, "Timer," explains the programmable interval timer. 

• Chapter 7, "Host Interface Port," describes the operation of the host 
interface port, including boot loading and software reset. 

• Chapter 8, "Analog Interface," describes the operation and the internal 
architecture of the ADSP-21msp58/59's analog interface. 

Chapters 9 and 10 describe the behavior of the ADSP-21xx processors 
from the point of view of external memory and control logic: 

• Chapter 9, "System Interface," discusses the issue of system clocking, 
and describes the processors' control interface, the software reboot 
function, and the powerdown mode. 



• Chapter 10, "Memory Interface," describes the data and program 
memory spaces. This chapter describes both internal and external 
memory, including the use of boot memory space. A special section is 
devoted to the ADSP-2181, since its memory interface differs from that 
of the other family processors. 

Chapter 11, "DMA Ports," describes the operation of the ADSP-218rs 
IDMA and BDMA features. 

Chapter 12, "Programming Model," gives a functional description of the 
processor resources — such as registers — as they appear in software. 

Chapter 13, "Hardware Examples," gives examples of system designs 
using the ADSP-21xx processors. Each example illustrates the solution to a 
different system design issue, using block diagrams, explanatory text, and 
programs or timing diagrams as needed. 

Chapter 14, "Software Examples," provides illustrative code for some 
important DSP and numerical algorithms. 

Chapter 15, "Instruction Set Reference," provides a detailed description of 
each ADSP-21xx instruction. 

The Appendices provide reference material and further details on specific 
issues: 

• Appendix A, "Instruction Coding," gives the complete set of opcodes 
and specifies the bit patterns for choices within each field of the 
instruction word. 

• Appendix B, "Division Exceptions," describes signed and unsigned 
division. 

• Appendix C, "Numeric Formats," describes the fixed-point numerical 
formats directly supported by the ADSP-2100 family, discusses block 
floating-point arithmetic, and tells how to handle the results of 
multiplication for operands of various formats. 

• Appendix D, "Interrupt Vector Addresses," lists the interrupt vectors 
of each family processor. 

• Appendix E, "Control/Status Registers," summarizes the processors' 
control and status registers. 


12 



Computational Units 


2.1 OVERVIEW 

This chapter describes the architecture and function of the three 
computational units: the arithmetic /logic unit, the multiplier/ 
accumulator and the barrel shifter. 

Every device in the ADSP-2100 family is a 16-bit, fixed-point machine. 
Most operations assume a twos-complement number representation, 
while others assume unsigned numbers or simple binary strings. Special 
features support multiword arithmetic and block floating-point. Details 
concerning the various number formats supported by the ADSP-2100 
family are given in Appendix C. 

In ADSP-2100 family arithmetic, signed numbers are always in twos- 
complement format. The processors do not use signed-magnitude, ones- 
complement, BCD or excess-n formats. 

2.1.1 Binary String 

This is the simplest binary notation; sixteen bits are treated as a bit pattern. 
Examples of computation using this format are the logical operations: 
NOT, AND, OR, XOR. These ALU operations treat their operands as 
binary strings with no provision for sign bit or binary point placement. 

2.1.2 Unsigned 

Unsigned binary numbers may be thought of as positive, having nearly 
twice the magnitude of a signed number of the same length. The least 
significant words of multiple precision numbers are treated as unsigned 
numbers. 

2.1.3 Signed Numbers: Twos-Complement 

In discussions of ADSP-2100 family arithmetic, "signed" refers to twos- 
complement. Most ADSP-2100 family operations presume or support 
twos-complement arithmetic. The ADSP-2100 family does not use signed- 
magnitude, ones-complement, BCD or excess-n formats. 




2.1 .4 Fractional Representation: 1 .15 

ADSP-2100 family arithmetic is optimized for numerical values in a 
fractional binary format denoted by 1.15 ("one dot fifteen"). In the 1.15 
format, there is one sign bit (the MSB) and fifteen fractional bits 
representing values from -1 up to one LSB less than +1 . 

Figure 2.1 shows the bit weighting for 1.15 numbers. Below are examples 
of 1.15 numbers and their decimal equivalents. 


1.15 Number 

0x0001 

0x7FFF 

OxFFFF 

0x8000 


Decimal Equivalent 

0.000031 

0.999969 

-0.000031 

- 1.000000 


„0 

.-1 

-2 

-3 

„-4 

.-5 

_-6 

-7 

„-8 

-9 

-10 

-11 

-12 

-13 

-14 

-15 

-2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 


Figure 2.1 Bit Weighting For 1 .15 Numbers 


2.1.5 ALU Arithmetic 

All operations on the ALU treat operands and results as simple 16-bit 
binary strings, except the signed division primitive (DIVS). Various status 
bits treat the results as signed: the overflow (AV) condition code, and the 
negative (AN) flag. 

The logic of the overflow bit (AV) is based on twos-complement 
arithmetic. It is set if the MSB changes in a manner not predicted by the 
signs of the operands and the nature of the operation. For example, 
adding two positive numbers must generate a positive result; a change in 
the sign bit signifies an overflow and sets AV. Adding a negative and a 
positive may result in either a negative or positive result, but cannot 
overflow. 

The logic of the carry bit (AC) is based on unsigned-magnitude arithmetic. 
It is set if a carry is generated from bit 16 (the MSB). The (AC) bit is most 
useful for the lower word portions of a multiword operation. 





2.1.6 MAC Arithmetic 

The multiplier produces results that are binary strings. The inputs are 
"interpreted" according to the information given in the instruction itself 
(signed times signed, unsigned times unsigned, a mixture, or a rounding 
operation). The 32-bit result from the multiplier is assumed to be signed, 
in that it is sign-extended across the full 40-bit width of the MR register 
set. 

The ADSP-2100 family supports two modes of format adjustment: the 
fractional mode for fractional operands, 1.15 format (1 signed bit, 15 
fractional bits), and the integer mode for integer operands, 16.0 format. 

When the processor multiplies two 1.15 operands, the result is a 2.30 
(2 sign bits, 30 fractional bits) number. In the fractional mode, the MAC 
automatically shifts the multiplier product (P) left one bit before 
transferring the result to the multiplier result register (MR). This shift 
causes the multiplier result to be in 1.31 format, which can be rounded to 
1.15 format. Figure 2.7, in the MAC section of this chapter, shows this. 

In the integer mode, the left shift does not occur. For example, if the 
operands are in the 16.0 format, the 32-bit multiplier result would be in 
32.0 format. A left shift is not needed; it would change the numerical 
representation. Figure 2.8 in the MAC section of this chapter shows this. 

2.1 .7 Shifter Arithmetic 

Many operations in the shifter are explicitly geared to signed (twos- 
complement) or unsigned values: logical shifts assume unsigned- 
magnitude or binary string values and arithmetic shifts assume twos- 
complement. 

The exponent logic assumes twos-complement numbers. The exponent 
logic supports block floating-point, which is also based on twos- 
complement fractions. 


2-3 




2.1.8 Summary 

Table 2.1 summarizes some of the arithmetic characteristics of ADSP-2100 
family operations. In addition to the numeric types described in this 
section, the ADSP-2100 Family C Compiler supports a form of 32-bit 
floating-point in which one 16-bit word is the exponent and the other 
word is the mantissa. See the ADSP-2100 Family C Tools Manual 


Operation Arithmetic Formats 


ALU 

Operands 

Result 

Addition 

Subtraction 

Logical Operations 
Division 

ALU Overflow 

ALU Carry Bit 

ALU Saturation 

Signed or unsigned 

Signed or unsigned 

Binary string 

Explicitly signed/unsigned 

Signed 

16-bit unsigned 

Signed 

Interpret flags 
Interpret flags 
same as operands 
same as operands 
same as operands 
same as operands 
same as operands 

MAC, Fractional 



Multiplication (P) 
Multiplication (MR) 

Mult / Add 

Mult / Subtract 

MAC Saturation 

1.15 Explicitly signed/unsigned 

1.15 Explicitly signed /unsigned 

1.15 Explicitly signed/unsigned 

1.15 Explicitly signed /unsigned 

Signed 

32 bits (2.30) 

2.30 shifted to 1.31 
2.30 shifted to 1.31 
2.30 shifted to 1.31 
same as operands 

MAC, Integer Mode 



Multiplication (P) 
Multiplication (MR) 

Mult / Add 

Mult / Subtract 

MAC Saturation 

1.15 Explicitly signed /unsigned 

16.0 Explicitly signed /unsigned 

16.0 Explicitly signed /unsigned 

16.0 Explicitly signed /unsigned 

Signed 

32 bits (2.30) 

32.0 no shift 

32.0 no shift 

32.0 no shift 
same as operands 

Shifter 



Logical Shift 

Arithmetic Shift 

Exponent Detection 

Unsigned / binary string 

Signed 

Signed 

same as operands 
same as operands 
same as operands 


Table 2.1 Arithmetic Formats 


2-4 


2.2 ARITHMETIC/LOGIC UNIT (ALU) 

The arithmetic/logic unit (ALU) provides a standard set of arithmetic and 
logical functions. The arithmetic functions are add, subtract, negate, 
increment, decrement and absolute value. These are supplemented by two 
division primitives with which multiple cycle division can be constructed. 
The logic functions are AND, OR, XOR (exclusive OR) and NOT. 

2.2.1 ALU Block Diagram Discussion 

Figure 2.2, on the following page, shows a block diagram of the ALU. 

The ALU is 16 bits wide with two 16-bit input ports, X and Y, and one 
output port, R. The ALU accepts a carry-in signal (Cl) which is the carry 
bit from the processor arithmetic status register (AST AT). The ALU 
generates six status signals: the zero (AZ) status, the negative (AN) status, 
the carry (AC) status, the overflow (AV) status, the X-input sign (AS) 
status, and the quotient (AQ) status. All arithmetic status signals are 
latched into the arithmetic status register (ASTAT) at the end of the cycle. 
Please see the "Instruction Set Reference" chapter of this manual for 
information on how each instruction affects the ALU flags. 

The X input port of the ALU can accept data from two sources: the AX 
register file or the result (R) bus. The R bus connects the output registers of 
all the computational units, permitting them to be used as input operands 
directly. The AX register file is dedicated to the X input port and consists 
of two registers, AXO and AX1. These AX registers are readable and 
writable from the DMD bus. The instruction set also provides for reading 
these registers over the PMD bus, but there is no direct connection; this 
operation uses the DMD-PMD bus exchange unit. The AX register file 
outputs are dual-ported so that one register can provide input to the ALU 
while either one simultaneously drives the DMD bus. 

The Y input port of the ALU can also accept data from two sources: the 
AY register file and the ALU feedback (AF) register. The AY register file is 
dedicated to the Y input port and consists of two registers, AYO and AY1. 
These registers are readable and writable from the DMD bus and writable 
from the PMD bus. The instruction set also provides for reading these 
registers over the PMD bus, but there is no direct connection; this 
operation uses the DMD-PMD bus exchange unit. The AY register file 
outputs are also dual-ported: one AY register can provide input to the 
ALU while either one simultaneously drives the DMD bus. 


2-5 




The output of the ALU is loaded into either the ALU feedback (AF) 
register or the ALU result (AR) register. The AF register is an ALU 
internal register which allows the ALU result to be used directly as the 
ALU Y input. The AR register can drive both the DMD bus and the R bus. 
It is also loadable directly from the DMD bus. The instruction set also 
provides for reading AR over the PMD bus, but there is no direct 
connection; this operation uses the DMD-PMD bus exchange unit. 



Figure 2.2 ALU Block Diagram 


2-6 















Any of the registers associated with the ALU can be both read and written in 
the same cycle. Registers are read at the beginning of the cycle and written at 
the end of the cycle. A register read, therefore, reads the value loaded at the 
end of a previous cycle. A new value written to a register cannot be read out 
until a subsequent cycle. This allows an input register to provide an operand to 
the ALU at the beginning of the cycle and be updated with the next operand 
from memory at the end of the same cycle. It also allows a result register to be 
stored in memory and updated with a new result in the same cycle. See the 
discussion of "Multifunction Instructions" in Chapter 15, "Instruction Set 
Reference" for an illustration of this same-cycle read and write. 

The ALU contains a duplicate bank of registers, shown in Figure 2.2 behind the 
primary registers. There are actually two sets of AR, AF, AX, and AY register 
files. Only one bank is accessible at a time. The additional bank of registers can 
be activated (such as during an interrupt service routine) for extremely fast 
context switching. A new task, like an interrupt service routine, can be 
executed without transferring current states to storage. 

The selection of the primary or alternate bank of registers is controlled by bit 0 
in the processor mode status register (MSTAT). If this bit is a 0, the primary 
bank is selected; if it is a 1, the secondary bank is selected. 

2.2.2 Standard Functions 

The standard ALU functions are listed below. 


R = X + Y 
R = X + Y + Cl 
R = X- Y 
R = X- Y + CI-1 
R = Y-X 
R = Y - X + Cl - 1 
R = -X 
R = - Y 
R = Y + 1 
R = Y- 1 
R = PASS X 
R = PASS Y 
R = 0 (PASSO) 

R = ABS X 
R = X AND Y 
R = X OR Y 
R = X XOR Y 
R = NOT X 
R = NOT Y 


Add X and Y operands 

Add X and Y operands and carry-in bit 

Subtract Y from X operand 

Subtract Y from X operand with "borrow" 

Subtract X from Y operand 

Subtract X from Y operand with "borrow" 

Negate X operand (twos-complement) 

Negate Y operand (twos-complement) 

Increment Y operand 

Decrement Y operand 

Pass X operand to result unchanged 

Pass Y operand to result unchanged 

Clear result to zero 

Absolute value of X operand 

Logical AND of X and Y operands 

Logical OR of X and Y operands 

Logical Exclusive OR of X and Y operands 

Logical NOT of X operand (ones-complement) 

Logical NOT of Y operand (ones-complement) 


2-7 



2.2.3 ALU Input/Output Registers 

The sources of ALU input and output registers are shown below. 


Source for 
X input port 

AXO, AX1 
AR 

MRO, MR1, MR2 
SRO, SRI 


Source for 
Y input port 

AYO, AY1 
AF 


Destination for 
R output port 


AR 

AF 


MRO, MR1 and MR2 are multiplier/ accumulator result registers; SRO and 
SRI are shifter result registers. 

2.2.4 Multiprecision Capability 

Multiprecision operations are supported in the ALU with the carry-in 
signal and ALU carry (AC) status bit. The carry-in signal is the AC status 
bit that was generated by a previous ALU operation. The "add with carry" 
(+ C) operation is intended for adding the upper portions of 
multiprecision numbers. The "subtract with borrow" (C - 1 is effectively a 
"borrow") operation is intended for subtracting the upper portions of 
multiprecision numbers. 

2.2.5 ALU Saturation Mode 

The AR register has a twos-complement saturation mode of operation 
which automatically sets it to the maximum negative or positive value if 
an ALU result overflows or underflows. This feature is enabled by setting 
bit 3 of the mode status register (MSTAT). When enabled, the value loaded 
into AR during an ALU operation depends on the state of the overflow 
and carry status generated by the ALU on that cycle. The following table 
summarizes the loading of AR when saturation mode is enabled. 


Overflow (AV) 
0 
0 
1 
1 


Carry (AC) 
0 
1 
0 
1 


AR Contents 
ALU Output 
ALU Output 
0111111111111111 
1000000000000000 


full-scale positive 
full-scale negative 


Table 2.2 Saturation Mode 


The operation of the ALU saturation mode is different from the 
Multiplier/ Accumulator saturation ability, which is enabled only on an 
instruction by instruction basis. For the ALU, enabling saturation means 
that all subsequent operations are processed this way. 



When the ALU saturation mode is used, only the AR register saturates; if 
the AF register is the destination, wrap-around will occur but the flags 
will reflect the saturated result. 

2.2.6 ALU Overflow Latch Mode 

The ALU overflow latch mode, enabled by setting bit 2 in the mode status 
register (MSTAT), causes the AV bit to "stick" once it is set. In this mode, 
when an ALU overflow occurs, AV will be set and remain set, even if 
subsequent ALU operations do not generate overflows. In this mode, AV 
can only be cleared by writing a zero to it directly from the DMD bus. 

2.2.7 Division 

The ALU supports division. The divide function is achieved with 
additional shift circuitry not shown in Figure 2.2. Division is accomplished 
with two special divide primitives. These are used to implement a non- 
restoring conditional add-subtract division algorithm. The division can be 
either signed or unsigned; however, the dividend and divisor must both 
be of the same type. Appendix B details various exceptions to the normal 
division operation as described in this section. 

A single-precision divide, with a 32-bit dividend (numerator) and a 16-bit 
divisor (denominator), yielding a 16-bit quotient, executes in 16 cycles. 
Higher and lower precision quotients can also be calculated. The divisor 
can be stored in AXO, AX1 or any of the R registers. The upper half of a 
signed dividend can start in either AY1 or AF. The upper half of an 
unsigned dividend must be in AF. The lower half of any dividend must be 
in AYO. At the end of the divide operation, the quotient will be in AYO. 

The first of the two primitive instructions "divide-sign" (DIVS) is executed 
at the beginning of the division when dividing signed numbers. This 
operation computes the sign bit of the quotient by performing an 
exclusive-OR of the sign bits of the divisor and the dividend. The AYO 
register is shifted one place so that the computed sign bit is moved into 
the LSB position. The computed sign bit is also loaded into the AQ bit of 
the arithmetic status register. The MSB of AYO shifts into the LSB position 
of AF, and the upper 15 bits of AF are loaded with the lower 15 R bits 
from the ALU, which simply passes the Y input value straight through to 
the R output. The net effect is to left shift the AF-AYO register pair and 
move the quotient sign bit into the LSB position. The operation of DIVS is 
illustrated in Figure 2.3 (on the next page). 


2-9 



15 



Figure 2.3 DIVS Operation 


When dividing unsigned numbers, the DIVS operation is not used. 
Instead, the AQ bit in the arithmetic status register (ASTAT) should be 
initialized to zero by manually clearing it. The AQ bit indicates to the 
following operations that the quotient should be assumed positive. 

The second division primitive is the "divide-quotient" (DIVQ) instruction 
which generates one bit of quotient at a time and is executed repeatedly to 
compute the remaining quotient bits. For unsigned single precision 
divides, the DIVQ instruction is executed 16 times to produce 16 quotient 
bits. For signed single precision divides, the DIVQ instruction is executed 
15 times after the sign bit is computed by the DIVS operation. DIVQ 
instruction shifts the AYO register left by one bit so that the new quotient 
bit can be moved into the LSB position. The status of the AQ bit generated 
from the previous operation determines the ALU operation to calculate 
the partial remainder. If AQ = 1, the ALU adds the divisor to the partial 
remainder in AF. If AQ = 0, the ALU subtracts the divisor from the partial 
remainder in AF. The ALU output R is offset loaded into AF just as with 
the DIVS operation. The AQ bit is computed as the exclusive-OR of the 


2-10 












divisor MSB and the ALU output MSB, and the quotient bit is this value 
inverted. The quotient bit is loaded into the LSB of the AYO register which is 
also shifted left by one bit. The DIVQ operation is illustrated in Figure 2.4. 


15 



Figure 2.4 DIVQ Operation 

The format of the quotient for any numeric representation can be 
determined by the format of the dividend and divisor. Let NL represent 
the number of bits to the left of the binary point, and NR represent the 
number of bits to the right of the binary point of the dividend; DL 
represent the number of bits to the left of the binary point, and DR 
represent the number of bits to the right of the binary point of the divisor; 
then the quotient has NL-DL+1 bits to the left of the binary point and NR- 
DR-1 bits to the right of the binary point. 


2-11 




Some format manipulation may be necessary to guarantee the validity of 
the quotient. For example, if both operands are signed and fully fractional 
(dividend in 1.31 format and divisor in 1.15 format) the result is fully 
fractional (in 1.15 format) and therefore the dividend must be smaller than 
the divisor for a valid result. 

To divide two integers (dividend in 32.0 format and divisor in 16.0 format) 
and produce an integer quotient (in 16.0 format), you must shift the 
dividend one bit to the left (into 31.1 format) before dividing. Additional 
discussion and code examples can be found in the handbook Digital Signal 
Processing Applications Using the ADSP-2100 Family, Volume 1. 


Dividend BBBBB . BBBBBBBBBBBBBBBBBBBBBBBBBBB 
NL bits NR bits 

Divisor BB . BBBBBBBBBBBBBB 

DL bits DR bits 

Quotient BBBB . BBBBBBBBBBBB 

(NL-DL+1) bits (NR-DR-1) bits 

Figure 2.5 Quotient Format 

The algorithm overflows if the result cannot be represented in the format 
of the quotient as calculated above or when the divisor is zero or less than 
the dividend in magnitude. 


2-12 



2.2.8 ALU Status 

The ALU status bits in the AST AT register are defined below. Complete 
information about the ASTAT register and specific bit mnemonics and 
positions is provided in the Program Control chapter. 


Flag 

Name 

Definition 

AZ 

Zero 

Logical NOR of all the bits in the ALU result register. True 
if ALU output equals zero. 

AN 

Negative 

Sign bit of the ALU result. True if the ALU output is 
negative. 

AV 

Overflow 

Exclusive-OR of the carry outputs of the two most 
significant adder stages. True if the ALU overflows. 

AC 

Carry 

Carry output from the most significant adder stage. 

AS 

Sign 

Sign bit of the ALU X input port. Affected only by the ABS 
instruction. 

AQ 

Quotient 

Quotient bit generated only by the DIVS and DIVQ 
instructions. 

2.3 

MULTIPLIER/ACCUMULATOR (MAC) 


The multiplier/ accumulator (MAC) provides high-speed multiplication, 
multiplication with cumulative addition, multiplication with cumulative 
subtraction, saturation and clear-to-zero functions. A feedback function allows 
part of the accumulator output to be directly used as one of the multiplicands 
on the next cycle. 

2.3.1 MAC Block Diagram Discussion 

Figure 2.6, on the following page, shows a block diagram of the multiplier/ 
accumulator. 

The multiplier has two 16-bit input ports X and Y, and a 32-bit product output 
port P. The 32-bit product is passed to a 40-bit adder/ subtracter which adds 
or subtracts the new product from the content of the multiplier result (MR) 
register, or passes the new product directly to MR. The MR register is 40 bits 
wide. In this manual, we refer to the entire register as MR. The register 
actually consists of three smaller registers: MRO and MR1 which are 16 bits 
wide and MR2 which is 8 bits wide. 

The adder/ subtracter is greater than 32 bits to allow for intermediate overflow 
in a series of multiply /accumulate operations. The multiply overflow (MV) 
status bit is set when the accumulator has overflowed beyond the 32-bit 
boundary, that is, when there are significant (non-sign) bits in the top nine bits 
of the MR register (based on twos-complement arithmetic). 



PMD BUS 


24 



Figure 2.6 MAC Block Diagram 


2-14 























The input/output registers of the MAC are similar to the ALU. 

The X input port can accept data from either the MX register file or from 
any register on the result (R) bus. The R bus connects the output registers 
of all the computational units, permitting them to be used as input 
operands directly. There are two registers in the MX register file, MXO and 
MX1. These registers can be read and written from the DMD bus. The MX 
register file outputs are dual-ported so that one register can provide input 
to the multiplier while either one simultaneously drives the DMD bus. 

The Y input port can accept data from either the MY register file or the MF 
register. The MY register file has two registers, MYO and MY1; these 
registers can be read and written from the DMD bus and written from the 
PMD bus. The instruction set also provides for reading these registers over 
the PMD bus, but there is no direct connection; this operation uses the 
DMD-PMD bus exchange unit. The MY register file outputs are also dual- 
ported so that one register can provide input to the multiplier while either 
one simultaneously drives the DMD bus. 

The output of the adder/ subtracter goes to either the MF register or the 
MR register. The MF register is a feedback register which allows bits 16-31 
of the result to be used directly as the multiplier Y input on a subsequent 
cycle. The 40-bit adder/ subtracter register (MR) is divided into three 
sections: MR2, MR1, and MRO. Each of these registers can be loaded 
directly from the DMD bus and output to either the DMD bus or the R 
bus. 

Any of the registers associated with the MAC can be both read and 
written in the same cycle. Registers are read at the beginning of the cycle 
and written at the end of the cycle. A register read, therefore, reads the 
value loaded at the end of a previous cycle. A new value written to a 
register cannot be read out until a subsequent cycle. This allows an input 
register to provide an operand to the MAC at the beginning of the cycle 
and be updated with the next operand from memory at the end of the 
same cycle. It also allows a result register to be stored in memory and 
updated with a new result in the same cycle. See the discussion of 
"Multifunction Instructions" in Chapter 15 "Instruction Set Reference" for 
an illustration of this same-cycle read and write. 


2-15 



The MAC contains a duplicate bank of registers, shown in Figure 2.6 
behind the primary registers. There are actually two sets of MR, MF, MX, 
and MY register files. Only one bank is accessible at a time. The additional 
bank of registers can be activated for extremely fast context switching. A 
new task, such as an interrupt service routine, can be executed without 
transferring current states to storage. 

The selection of the primary or alternate bank of registers is controlled by 
bit 0 in the processor mode status register (MSTAT). If this bit is a 0, the 
primary bank is selected; if it is a 1, the secondary bank is selected. 

2.3.2 MAC Operations 

This section explains the functions of the MAC, its input formats and its 
handling of overflow and saturation. 

2.3.2. 1 Standard Functions 

The functions performed by the MAC are: 

X*Y Multiply X and Y operands. 

MR+X*Y Multiply X and Y operands and add result to MR register. 

MR-X*Y Multiply X and Y operands and subtract result from MR register. 

0 Clear result (MR) to zero. 

The ADSP-2100 family provides two modes for the standard multiply/ 
accumulate function: fractional mode for fractional numbers (1.15), and 
integer mode for integers (16.0). 

In the fractional mode, the 32-bit P output is format adjusted, that is, sign- 
extended and shifted one bit to the left before being added to MR. For 
example, bit 31 of P lines up with bit 32 of MR (which is bit 0 of MR2) and 
bit 0 of P lines up with bit 1 of MR (which is bit 1 of MRO). The LSB is zero- 
filled. The fractional multiplier result format is shown in Figure 2.7. 

In the integer mode, the 32-bit P register is not shifted before being added 
to MR. Figure 2.8 shows the integer-mode result placement. 

The mode is selected by bit 4 of the mode status register (MSTAT). If this 
bit is a 1, the integer mode is selected. Otherwise, the fractional mode is 
selected. In either mode, the multiplier output P is fed into a 40-bit adder/ 
subtracter which adds or subtracts the new product with the current 
contents of the MR register to form the final 40-bit result R. 





Figure 2.8 Integer Multiplier Result Format 


2-17 






2.3.22 Input Formats 

To facilitate multiprecision multiplications, the multiplier accepts X and Y 
inputs represented in any combination of signed twos-complement format 
and unsigned format. 


X input 

signed x 

unsigned x 

signed x 

unsigned x 


Y input 

signed 

signed 

unsigned 

unsigned 


The input formats are specified as part of the instruction. These are 
dynamically selectable each time the multiplier is used. 

The (signed x signed) mode is used when multiplying two signed single 
precision numbers or the two upper portions of two signed multiprecision 
numbers. 


The (unsigned x signed) and (signed x unsigned) modes are used when 
multiplying the upper portion of a signed multiprecision number with the 
lower portion of another or when multiplying a signed single precision 
number by an unsigned single precision number. 

The (unsigned x unsigned) mode is used when multiplying unsigned 
single precision numbers or the non-upper portions of two signed 
multiprecision numbers. 

2.32.3 MAC Input/Output Registers 

The sources of MAC input and output are: 

Source for Source for 

X input port Y input port 

MXO, MX1 MYO, MY1 

AR MF 

MRO, MR1, MR2 
SRO, SRI 

2.32.4 MR Register Operation 

As described, and shown on the block diagram, the MR register is divided 
into three sections: MRO (bits 0-15), MR1 (bits 16-31), and MR2 (bits 32- 
39). Each of these registers can be loaded from the DMD bus and output to 
the R bus or the DMD bus. 


Destination for 
R output port 

MR (MR2, MR1, MRO) 
MF 



The 8-bit MR2 register is tied to the lower 8 bits of these buses. When MR2 
is output onto the DMD bus or the R bus, it is sign extended to form a 16- 
bit value. MR1 also has an automatic sign-extend capability. When MR1 is 
loaded from the DMD bus, every bit in MR2 will be set to the sign bit 
(MSB) of MR1, so that MR2 appears as an extension of MR1. To load the 
MR2 register with a value other than MRl's sign extension, you must load 
MR2 after MR1 has been loaded. Loading MRO affects neither MR1 nor 
MR2; no sign extension occurs in MRO loads. 

2.3.2.S MAC Overflow And Saturation 

The adder/ subtracter generates an overflow status signal (MV) which is 
loaded into the processor arithmetic status (ASTAT) every time a MAC 
operation is executed. The MV bit is set when the accumulator result, 
interpreted as a twos-complement number, crosses the 32-bit (MR1 /MR2) 
boundary. That is, MV is set if the upper nine bits of MR are not all ones or 
all zeros. 

The MR register has a saturation capability which sets MR to the 
maximum positive or negative value if an overflow or underflow has 
occurred. The saturation operation depends on the overflow status bit 
(MV) in the processor arithmetic status (ASTAT) and the MSB of the MR2 
register. The following table summarizes the MR saturation operation. 

MV MSB of MR2 MR contents after saturation 

0 0 or 1 no change 

1 0 00000000 0111111111111111 1111111111111111 full-scale positive 

1 1 11111111 1000000000000000 0000000000000000 full-scale negative 

Table 2.3 Effect Of MAC Saturation Instruction 

Saturation in the MAC is an instruction rather than a mode as in the ALU. 

The saturation instruction is intended to be used at the completion of a 
string of multiplication/accumulations so that intermediate overflows do 
not cause the accumulator to saturate. 

Overflowing beyond the MSB of MR2 should never be allowed. The true 
sign bit of the result is then irretrievably lost and saturation may not 
produce a correct value. It takes more than 255 overflows (MV type) to 
reach this state, however. 


2-19 




2.3.2.6 Rounding Mode 

The accumulator has the capability for rounding the 40-bit result R at the 
boundary between bit 15 and bit 16. Rounding can be specified as part of 
the instruction code. The rounded output is directed to either MR or MF. 
When rounding is invoked with MF as the output register, register 
contents in MF represent the rounded 16-bit result. Similarly, when MR is 
selected as the output, MR1 contains the rounded 16-bit result; the 
rounding effect in MR1 affects MR2 as well and MR2 and MR1 represent 
the rounded 24-bit result. 

The accumulator uses an unbiased rounding scheme. The conventional 
method of biased rounding is to add a 1 into bit position 15 of the adder 
chain. This method causes a net positive bias since the midway value 
(when MR0=0x8000) is always rounded upward. The accumulator 
eliminates this bias by forcing bit 16 in the result output to zero when it 
detects this midway point. This has the effect of rounding odd MR1 values 
upward and even MR1 values downward, yielding a zero large-sample 
bias assuming uniformly distributed values. 

Using x to represent any bit pattern (not all zeros), here are two examples 
of rounding. The first example is the typical rounding operation. 

Example 1 MR2 MR1 MRO 

Unrounded value: xxxxxxxx xxxxxxxxOOl 00101 lxxxxxxxxxxxxxxx 

Bit 15 = 1 

Add 1 to bit 15 and carry 1 

Rounded value: xxxxxxxx xxxxxxxx 00100110 0 xxxxxxxxxxxxxxx 


The compensation to avoid net bias becomes visible when the lower 15 
bits are all zero and bit 15 is one, i.e. the midpoint value. 


2-20 



MR1 


MRO 


Example 2 MR2 

Unrounded value: xxxxxxxx xxxxxxxxO 1100110 1000000000000000 
Bit 15 = 1 and bits 0-14 = 0 

Add 1 to bit 15 and carry 1 

xxxxxxxx xxxxxxxxOHOOlll 0000000000000000 
Since bit 16 = 1, force it to 0 

Rounded value: xxxxxxxx xxxxxxxxOHOOHO 0000000000000000 

In this last case, bit 16 is forced to zero. This algorithm is employed on every 
rounding operation, but is only evident when the bit patterns shown in the 
lower 16 bits of the last example are present. 

2.32.7 Biased Rounding (ADSP-217x, ADSP-218x, ADSP-21msp5x) 

A mode is available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/ 

59 processors to allow biased rounding in addition to the normal unbiased 
rounding. This mode is selected by the BIASRND bit (bit 12 of the SPORTO 
Autobuffer Control register). When the BIASRND bit is set to 0, the normal 
unbiased rounding operations occur. When the BIASRND bit is set to 1, 
biased rounding occurs instead of the normal unbiased rounding. When 
operating in biased rounding mode all rounding operations with MRO set 
to 0x8000 will round up, rather than only rounding odd MR1 values up. 

For example: 


MR value before RND 
00-0000-8000 
00-0001-8000 
00-0000-8001 
00-0001-8001 
00-0000-7FFF 
00-0001 -7FFF 


biased RND result 
00-0001-8000 
00-0002-8000 
00-0001-8001 
00-0002-8001 
00-0000- 7FFF 
00-0001 -7FFF 


unbiased RND result 
00-0000-8000 
00-0002-8000 
00-0001-8001 
00-0002-8001 
00-0000- 7FFF 
00-0001 -7FFF 


This mode only has an effect when the MRO register contains 0x8000; all 
other rounding operations work normally. This mode allows more efficient 
implementation of bit-specified algorithms that use biased rounding, for 
example the GSM speech compression routines. Unbiased rounding is 
preferred for most algorithms. 


2-21 



2.4 BARREL SHIFTER 

The shifter provides a complete set of shifting functions for 16-bit inputs, 
yielding a 32-bit output. These include arithmetic shift, logical shift and 
normalization. The shifter also performs derivation of exponent and 
derivation of common exponent for an entire block of numbers. These 
basic functions can be combined to efficiently implement any degree of 
numerical format control, including full floating-point representation. 

2.4.1 Shifter Block Diagram Discussion 

Figure 2.9 shows a block diagram of the shifter. The shifter can be divided 
into the following components: the shifter array, the OR/ PASS logic, the 
exponent detector, and the exponent compare logic. 

The shifter array is a 16x32 barrel shifter. It accepts a 16-bit input and can 
place it anywhere in the 32-bit output field, from off-scale right to off-scale 
left, in a single cycle. This gives 49 possible placements within the 32-bit 
field. The placement of the 16 input bits is determined by a control code 
(C) and a HI/LO reference signal. 

The shifter array and its associated logic are surrounded by a set of 
registers. The shifter input (SI) register provides input to the shifter array 
and the exponent detector. The SI register is 16 bits wide and is readable 
and writable from the DMD bus. The shifter array and the exponent 
detector also take as inputs AR, SR or MR via the R bus. The shifter result 
(SR) register is 32 bits wide and is divided into two 16-bit sections, SRO 
and SRI. The SRO and SRI registers can be loaded from the DMD bus and 
output to either the DMD bus or the R bus. The SR register is also fed back 
to the OR/PASS logic to allow double-precision shift operations. 

The SE register ("shifter exponent") is 8 bits wide and holds the exponent 
during the normalize and denormalize operations. The SE register is 
loadable and readable from the lower 8 bits of the DMD bus. It is a twos- 
complement, 8.0 value. 

The SB register ("shifter block") is important in block floating-point 
operations where it holds the block exponent value, that is, the value by 
which the block values must be shifted to normalize the largest value. SB 
is 5 bits wide and holds the most recent block exponent value. The SB 
register is loadable and readable from the lower 5 bits of the DMD bus. It 
is a twos-complement, 5.0 value. 

Whenever the SE or SB registers are output onto the DMD bus, they are 
sign-extended to form a 16-bit value. 




Figure 2.9 Shifter Block Diagram 

Any of the SI, SE or SR registers can be read and written in the same cycle. 
Registers are read at the beginning of the cycle and written at the end of 
the cycle. All register reads, therefore, read values loaded at the end of a 
previous cycle. A new value written to a register cannot be read out until a 
subsequent cycle. This allows an input register to provide an operand to 
the shifter at the beginning of the cycle and be updated with the next 
operand at the end of the same cycle. It also allows a result register to be 
stored in memory and updated with a new result in the same cycle. See 
the discussion of “Multifunction Instructions" in Chapter 15, "Instruction 
Set Reference" for an illustration of this same-cycle read and write. 


2-23 





















The shifter contains a duplicate bank of registers, shown in Figure 2.9 
behind the primary registers. There are actually two sets of SE, SB, SI, SRI, 
and SRO registers. Only one bank is accessible at a time. The additional 
bank of registers can be activated for extremely fast context switching. A 
new task, such as an interrupt service routine, can then be executed 
without transferring current states to storage. 

The selection of the primary or alternate bank of registers is controlled by 
bit 0 in the processor mode status register (MSTAT). If this bit is a 0, the 
primary bank is selected; if it is a 1, the secondary bank is selected. 

The shifting of the input is determined by a control code (C) and a HI/LO 
reference signal. The control code is an 8-bit signed value which indicates 
the direction and number of places the input is to be shifted. Positive 
codes indicate a left shift (upshift) and negative codes indicate a right shift 
(downshift). The control code can come from three sources: the content of 
the shifter exponent (SE) register, the negated content of the SE register or 
an immediate value from the instruction. 

The HI/LO signal determines the reference point for the shifting. In the HI 
state, all shifts are referenced to SRI (the upper half of the output field), 
and in the LO state, all shifts are referenced to SRO (the lower half). The 
HI/LO reference feature is useful when shifting 32-bit values since it 
allows both halves of the number to be shifted with the same control code. 
HI/LO reference signal is selectable each time the shifter is used. 

The shifter fills any bits to the right of the input value in the output field 
with zeros, and bits to the left are filled with the extension bit (X). The 
extension bit can be fed by three possible sources depending on the 
instruction being performed. The three sources are the MSB of the input, 
the AC bit from the arithmetic status register (ASTAT) or a zero. 

Table 2.4 shows the shifter array output as a function of the control code 
and HI/LO signal. 

The OR/ PASS logic allows the shifted sections of a multiprecision number 
to be combined into a single quantity. In some shifter instructions, the 
shifted output may be logically ORed with the contents of the SR register; 
the shifter array is bitwise ORed with the current contents of the SR 
register before being loaded there. When the [SR OR] option is not used in 
the instruction, the shifter array output is passed through and loaded into 
the shifter result (SR) register unmodified. 




Control Code Shifter Array Output 


HI reference 

LO Reference 





+16 

to +127 

+32 to +127 

00000000 

00000000 

00000000 

00000000 

+15 


+31 

R0000000 

00000000 

00000000 

•00000000 

+14 


+30 

PROOOOOO 

00000000 

00000000 

00000000 

+13 


+29 

NPROOOOO 

00000000 

00000000 

00000000 

+12 


+28 

MNPROOOO 

00000000 

00000000 

00000000 

+11 


+27 

LMNPROOO 

00000000 

00000000 

00000000 

+10 


+26 

KLMNPROO 

00000000 

00000000 

00000000 

+9 


+25 

JKLMNPRO 

00000000 

00000000 

00000000 

+8 


+24 

IJKLMNPR 

00000000 

00000000 

00000000 

+7 


+23 

HIJKLMNP 

R0000000 

00000000 

00000000 

+ 6 


+22 

GHIJKLMN 

PROOOOOO 

00000000 

00000000 

+5 


+21 

FGHIJKLM 

NPROOOOO 

00000000 

00000000 

+4 


+20 

EFGHIJKL 

MNPROOOO 

00000000 

00000000 

+3 


+19 

DEFGHIJK 

LMNPROOO 

00000000 

00000000 

+2 


+18 

CDEFGHIJ 

KLMNPROO 

00000000 

00000000 

+1 


+17 

BCDEFGHI 

JKLMNPRO 

00000000 

00000000 

0 


+16 

ABCDEFGH 

IJKLMNPR 

00000000 

00000000 

-1 


+15 

XABCDEFG 

HIJKLMNP 

R0000000 

00000000 

-2 


+ 14 

XXABCDEF 

GHIJKLMN 

PROOOOOO 

00000000 

-3 


+13 

XXXABCDE 

FGHIJKLM 

NPROOOOO 

00000000 

-4 


+ 12 

XXXXABCD 

EFGHIJKL 

MNPROOOO 

00000000 

-5 


+ 11 

XXXXXABC 

DEFGHIJK 

LMNPROOO 

00000000 

-6 


+10 

XXXXXXAB 

CDEFGHIJ 

KLMNPROO 

00000000 

-7 


+ 9 

XXXXXXXA 

BCDEFGHI 

JKLMNPRO 

00000000 

-8 


+ 8 

XXXXXXXX 

ABCDEFGH 

IJKLMNPR 

00000000 

-9 


+7 

xxxxxxxx 

XABCDEFG 

HIJKLMNP 

ROOOOOOO 

-10 


+ 6 

XXXXXXXX 

XXABCDEF 

GHIJKLMN 

PROOOOOO 

-11 


+5 

xxxxxxxx 

XXXABCDE 

FGHIJKLM 

NPROOOOO 

-12 


+4 

xxxxxxxx 

XXXXABCD 

EFGHIJKL 

MNPROOOO 

-13 


+3 

xxxxxxxx 

XXXXXABC 

DEFGHIJK 

LMNPROOO 

-14 


+2 

xxxxxxxx 

XXXXXXAB 

CDEFGHIJ 

KLMNPROO 

-15 


+1 

xxxxxxxx 

XXXXXXXA 

BCDEFGHI 

JKLMNPRO 

-16 


0 

xxxxxxxx 

XXXXXXXX 

ABCDEFGH 

IJKLMNPR 

-17 


-1 

xxxxxxxx 

XXXXXXXX 

XABCDEFG 

HIJKLMNP 

-18 


-2 

xxxxxxxx 

xxxxxxxx 

XXABCDEF 

GHIJKLMN 

-19 


-3 

xxxxxxxx 

xxxxxxxx 

XXXABCDE 

FGHIJKLM 

-20 


-4 

xxxxxxxx 

xxxxxxxx 

XXXXABCD 

EFGHIJKL 

-21 


-5 

xxxxxxxx 

xxxxxxxx 

XXXXXABC 

DEFGHIJK 

-22 


-6 

xxxxxxxx 

xxxxxxxx 

XXXXXXAB 

CDEFGHIJ 

-23 


-7 

xxxxxxxx 

xxxxxxxx 

XXXXXXXA 

BCDEFGHI 

-24 


-8 

xxxxxxxx 

xxxxxxxx 

XXXXXXXX 

ABCDEFGH 

-25 


-9 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XABCDEFG 

-26 


-10 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXABCDEF 

-27 


-11 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXXABCDE 

-28 


-12 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXXXABCD 

-29 


-13 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXXXXABC 

-30 


-14 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXXXXXAB 

-31 


-15 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXXXXXXA 

-32 

to -128 

-16 to -128 

xxxxxxxx 

xxxxxxxx 

xxxxxxxx 

XXXXXXXX 


Table 2.4 Shifter Array Characteristic 


ABCDEFGHIJKLMNPR 
represents the 16-bit 
input pattern 

X stands for the 
extension bit 


2-25 



The exponent detector derives an exponent for the shifter input value. The 
exponent detector operates in one of three ways which determine how the 
input value is interpreted. In the HI state, the input is interpreted as a 
single precision number or the upper half of a double precision number. 
The exponent detector determines the number of leading sign bits and 
produces a code which indicates how many places the input must be up- 
shifted to eliminate all but one of the sign bits. The code is negative so that 
it can become the effective exponent for the mantissa formed by removing 
the redundant sign bits. 

In the Hl-extend state (HIX), the input is interpreted as the result of an 
add or subtract performed in the ALU which may have overflowed. 
Therefore the exponent detector takes the arithmetic overflow (AV) status 
into consideration. If AV is set, then a +1 exponent is output to indicate an 
extra bit is needed in the normalized mantissa (the ALU Carry bit); if AV 
is not set, then Hl-extend functions exactly like the HI state. When 
performing a derive exponent function in HI or Hl-extend modes, the 
exponent detector also outputs a shifter sign (SS) bit which is loaded into 
the arithmetic status register (ASTAT). The sign bit is the same as the MSB 
of the shifter input except when AV is set; when AV is set in Hl-extend 
state, the MSB is inverted to restore the sign bit of the overflowed value. 

In the LO state, the input is interpreted as the lower half of a double 
precision number. In the LO state, the exponent detector interprets the SS 
bit in the arithmetic status register (ASTAT) as the sign bit of the number. 
The SE register is loaded with the output of the exponent detector only if 
SE contains -15. This occurs only when the upper half-which must be 
processed first-contained all sign bits. The exponent detector output is 
also offset by -16 to account for the fact that the input is actually the lower 
half of a 32-bit value. Table 2.5 gives the exponent detector characteristics 
for all three modes. 

The exponent compare logic is used to find the largest exponent value in 
an array of shifter input values. The exponent compare logic in 
conjunction with the exponent detector derives a block exponent. The 
comparator compares the exponent value derived by the exponent 
detector with the value stored in the shifter block exponent (SB) register 
and updates the SB register only when the derived exponent value is 
larger than the value in SB register. See the examples shown in the 
following sections. 




S = Sign bit 
N = Non-sign bit 
D = Don’t care bit 


HI Mode 




HIX Mode 



Shifter Array Input 

Output 

AV 

Shifter Array Input 

Output 




l 

DDDDDDDD 

DDDDDDDD 

+i 

SNDDDDDD 

DDDDDDDD 

0 

0 

SNDDDDDD 

DDDDDDDD 

0 

SSNDDDDD 

DDDDDDDD 

-1 

0 

SSNDDDDD 

DDDDDDDD 

-1 

SSSNDDDD 

DDDDDDDD 

-2 

0 

SSSNDDDD 

DDDDDDDD 

-2 

SSSSNDDD 

DDDDDDDD 

-3 

0 

SSSSNDDD 

DDDDDDDD 

-3 

SSSSSNDD 

DDDDDDDD 

-4 

0 

SSSSSNDD 

DDDDDDDD 

-4 

SSSSSSND 

DDDDDDDD 

-5 

0 

SSSSSSND 

DDDDDDDD 

-5 

SSSSSSSN 

DDDDDDDD 

-6 

0 

SSSSSSSN 

DDDDDDDD 

-6 

ssssssss 

NDDDDDDD 

-7 

0 

SSSSSSSS 

NDDDDDDD 

-7 

ssssssss 

SNDDDDDD 

-8 

0 

SSSSSSSS 

SNDDDDDD 

-8 

ssssssss 

SSNDDDDD 

-9 

0 

SSSSSSSS 

SSNDDDDD 

-9 

ssssssss 

SSSNDDDD 

-10 

0 

ssssssss 

SSSNDDDD 

-10 

ssssssss 

SSSSNDDD 

-11 

0 

ssssssss 

SSSSNDDD 

-11 

ssssssss 

SSSSSNDD 

-12 

0 

ssssssss 

SSSSSNDD 

-12 

ssssssss 

SSSSSSND 

-13 

0 

ssssssss 

SSSSSSND 

-13 

ssssssss 

SSSSSSSN 

-14 

0 

ssssssss 

SSSSSSSN 

-14 

ssssssss 

SSSSSSSS 

-15 

0 

ssssssss 

SSSSSSSS 

-15 


LO Mode 


ss 

Shifter Array Input 

Output 

s 

NDDDDDDD 

DDDDDDDD 

-15 

s 

SNDDDDDD 

DDDDDDDD 

-16 

s 

SSNDDDDD 

DDDDDDDD 

-17 

s 

SSSNDDDD 

DDDDDDDD 

-18 

s 

SSSSNDDD 

DDDDDDDD 

-19 

s 

SSSSSNDD 

DDDDDDDD 

-20 

s 

SSSSSSND 

DDDDDDDD 

-21 

s 

SSSSSSSN 

DDDDDDDD 

-22 

s 

SSSSSSSS 

NDDDDDDD 

-23 

s 

SSSSSSSS 

SNDDDDDD 

-24 

s 

SSSSSSSS 

SSNDDDDD 

-25 

s 

ssssssss 

SSSNDDDD 

-26 

s 

ssssssss 

SSSSNDDD 

-27 

s 

ssssssss 

SSSSSNDD 

-28 

s 

ssssssss 

SSSSSSND 

-29 

s 

ssssssss 

SSSSSSSN 

-30 

s 

ssssssss 

SSSSSSSS 

-31 


Table 2.5 Exponent Detector Characteristics 


2-27 



2.4.2 Shifter Operations 

The shifter performs the following functions (instruction mnemonics 
shown in parentheses): 

• Arithmetic Shift (ASHIFT) 

• Logical Shift (LSHIFT) 

• Normalize (NORM) 

• Derive Exponent (EXP) 

• Block Exponent Adjust (EXPADJ) 

These basic shifter instructions can be used in a variety of ways, 
depending on the underlying arithmetic requirements. The following 
sections present single and multiple precision examples for these 
functions: 

• Derivation of a Block Exponent 

• Immediate Shifts 

• Denormalization 

• Normalization 

The shift functions (arithmetic shift, logical shift, and normalize) can be 
optionally specified with [SR OR] and HI/LO modes to facilitate 
multiprecision operations. [SR OR] logically ORs the shift result with the 
current contents of SR. This option is used to join two 16-bit quantities into 
a 32-bit value in SR. When [SR OR] is not used, the shift value is passed 
through to SR directly. The HI and LO modifiers reference the shift to the 
upper or lower half of the 32-bit SR register. These shift functions take 
inputs from either the SI register or any other result register and load the 
32-bit shifted result into the SR register. 

2.4.2. 1 Shifter Input/Output Registers 

The sources of shifter input and output are: 

Source for Destination for 

Shifter input Shifter output 

SI SR (SRO, SRI) 

AR 

MRO, MR1, MR2 
SRO, SRI 


2-28 



2.42.2 Derive Block Exponent 

This function detects the exponent of the number largest in magnitude in 
an array of numbers. The EXPADJ instruction performs this function. The 
sequence of steps for a typical example is shown below. 

A. Load SB with -16 

The SB register is used to contain the exponent for the entire block. The 
possible values at the conclusion of a series of EXPADJ operations range 
from -15 to 0. The exponent compare logic updates the SB register if the 
new value is greater than the current value. Loading the register with -16 
initializes it to a value certain to be less than any actual exponents 
detected. 

B. Process the first array element: 

Array(l) = 11110101 10110001 
Exponent = -3 

-3 > SB (-16) 

SB gets -3 

C. Process next array element: 

Array(2)= 00000001 01110110 

Exponent = -6 

-6 < -3 

SB remains -3 

D. Continue processing array elements. 

When and if an array element is found whose exponent is greater than SB, 
that value is loaded into SB. When all array elements have been processed, 
the SB register contains the exponent of the largest number in the entire 
block. No normalization is performed. EXPADJ is purely an inspection 
operation. The value in SB could be transferred to SE and used to 
normalize the block on the next pass through the shifter. Or it could be 
simply associated with that data for subsequent interpretation. 


2-29 



2.42.3 Immediate Shifts 

An immediate shift simply shifts the input bit pattern to the right 
(downshift) or left (upshift) by a given number of bits. Immediate shift 
instructions use the data value in the instruction itself to control the 
amount and direction of the shifting operation. (See the chapter 
"Instruction Set Overview" for an example of this instruction.) The data 
value controlling the shift is an 8-bit signed number. The SE register is not 
used or changed by an immediate shift. 


The following example shows the input value downshifted relative to the 
upper half of SR (SRI). This is the (HI) version of the shift: 

SI=0xB6A3; 


SR=LSHIFT 

SI BY -5 

(HI) ; 

Input: 

10110110 

10100011 

Shift value: 

-5 


SR: 

00000101 

10110101 00011000 000000 


Here is the same input value shifted in the other direction, referenced to 
the lower half (LO) of SR: 

SI=0xB6A3; 

SR=LSHIFT SI BY 5 (LO) ; 

Input: 10110110 10100011 

Shift value: +5 

SR: 00000000 00010110 11010100 01100000 




In addition to the direction of the shifting operation, the shift may be 
either arithmetic (ASHIFT) or logical (LSHIFT). For example, the following 
shows a logical shift, relative to the upper half of SR (HI): 

SI=0xB6A3; 

SR=LSHIFT SI BY -5 (HI); 

Input: 10110110 10100011 

Shift value: - 5 

SR: 00000101 10110101 00011000 00000000 


This example shows an arithmetic shift of the same input and shift code: 
SI=0xB6A3; 

SR=ASHIFT SI BY -5 (HI); 

Input: 10110110 10100011 

Shift value: -5 

SR: 11111101 10110101 00011000 00000000 


2.42.4 Denormalize 

Denormalizing refers to shifting a number according to a predefined 
exponent. The operation is effectively a floating-point to fixed-point 
conversion. 

Denormalizing requires a sequence of operations. First, the SE register 
must contain the exponent value. This value may be explicitly loaded or 
may be the result of some previous operation. Next the shift itself is 
performed, taking its shift value from the SE register, not from an 
immediate data value. 


2-31 



Two examples of denormalizing a double-precision number are given 
below. The first shows a denormalization in which the upper half of the 
number is shifted first, followed by the lower half. Since computations 
may produce output in either order, the second example shows the same 
operation in the other order, i.e. lower half first. 

Always select the arithmetic shift for the higher half (HI) of the twos- 
complement input (or logical for unsigned). Likewise, the first half 
processed does not use the [SR ORl option. 

Modifier = HI, No [SR OR], Shift operation = Arithmetic, SE = -3 

First Input: 10110110 10100011 (upper half of desired result) 

SR: 11110110 11010100 01100000 00000000 

Now the lower half is processed. Always select a logical shift for the lower 

half of the input. Likewise, the second half processed must use the 

[SR OR] option to avoid overwriting the previous half of the output value. 

Modifier = LO, [SR OR], Shift operation = Logical, SE = -3 

Second Input: 01110110 01011101 (lower half of desired result) 

SR: 11110110 11010100 01101110 11001011 

Here is the same input processed in the reverse order. The higher half is 
always arithmetically shifted and the lower half is logically shifted. The 
first input is passed straight through to SR, but the second half is ORed to 
create a double-precision value in SR. 

Modifier = LO, No [SR OR], Shift operation = Logical, SE = -3 

First Input: 01110110 01011101 (lower half of desired result) 

SR: 00000000 00000000 00001110 11001011 


Modifier = HI, [SR OR], Shift operation = Arithmetic, SE = -3 
Second Input: 10110110 10100011 (upper half of desired result) 


SR: 


11110110 11010100 01101110 11001011 



2A2.5 Normalize 

Numbers with redundant sign bits require normalizing. Normalizing a 
number is the process of shifting a twos-complement number within a 
field so that the rightmost sign bit lines up with the MSB position of the 
field and recording how many places the number was shifted. The 
operation can be thought of as a fixed-point to floating-point conversion, 
generating an exponent and a mantissa. 

Normalizing is a two-stage process. The first stage derives the exponent. 
The second stage does the actual shifting. The first stage uses the EXP 
instruction which detects the exponent value and loads it into the SE 
register. This instruction (EXP) recognizes a (HI) and (LO) modifier. The 
second stage uses the NORM instruction. NORM recognizes (HI) and (LO) 
and also has the [SR OR] option. NORM uses the negated value of the SE 
register as its shift control code. The negated value is used so that the shift 
is made in the correct direction. 

Here is a normalization example for a single precision input: 

SE=EXP AR (HI) ; 

Detects Exponent With Modifier = HI 
Input: 11110110 11010100 

SE set to: -3 

Normalize, with modifier = HI Shift driven by value in SE 

Input: 11110110,11010100 

SR: 10110110 10100000 00000000 00000000 

For a single precision input, the normalize operation can use either the 
(HI) or (LO) modifier, depending on whether you want the result in SRI 
or SR0, respectively. 

Double precision values follow the same general scheme. The first stage 
detects the exponent and the second stage normalizes the two halves of 
the input. For double precision, however, there are two operations in each 
stage. 


2-33 



For the first stage, the upper half of the input must be operated on first. 
This first exponent derivation loads the exponent value into SE. The 
second exponent derivation, operating on the lower half of the number 
will not alter the SE register unless SE = -15. This happens only when the 
first half contained all sign bits. In this case, the second operation will load 
a value into SE. (See Table 2.5) This value is used to control both parts of 
the normalization that follows. 

For the second stage, now that SE contains the correct exponent value, the 
order of operations is immaterial. The first half (whether HI or LO) is 
normalized without the [SR OR] and the second half is normalized with 
[SR OR] to create one double-precision value in SR. The (HI) and (LO) 
modifiers identify which half is being processed. 

Here is a complete example of a typical double precision normalization. 

1 . Detect Exponent, Modifier = HI 

First Input: 11110110 11010100 (Must be upper half) 

SEsetto: -3 

2. Detect Exponent, Modifier = LO 
Second Input: 01101110 11001011 
SE unchanged, still - 3 

3. Normalize, Modifier=HI, No [SR OR], SE = -3 

First Input: 11110110 11010100 

SR: 10110110 10100000 00000000 00000000 

4. Normalize , Modifier=LO, [SR OR], SE = -3 
Second Input: 01101110 11001011 

SR: 10110110 10100011 01110110 01011000 


2-34 



If the upper half of the input contains all sign bits, the SE register value is 
determined by the second derive exponent operation as shown below. 

1 . Detect Exponent, Modifier = HI 

First Input: 11111111 11111111 (Must be upper half) 

SE set to: - 1 5 

2. Detect Exponent, Modifier = LO 

Second Input: 11110110 11010100 

SE now set to: -19 

3. Normalize, Modifier -HI, No [SR OR], SE = -19 (negated) 

First Input: 11111111 11111111 

SR: 00000000 00000000 00000000 00000000 

All values of SE less than -15 (resulting in a shift of +16 or more) upshift 
the input completely off scale. 

4. Normalize, Modifier=LO, [SR OR], SE = -19 (negated) 

Second Input: 11110110 11010100 

SR: 10110110 10100000 00000000 00000000 


2-35 



There is one additional normalization situation, requiring the Hi-extended 
(HIX) state. This is specifically when normalizing ALU results (AR) that 
may have overflowed. This operation reads the arithmetic status word 
(AST AT) overflow bit (AV) and the carry bit (AC) in conjunction with the 
value in AR. AV is set (1) if an overflow has occurred. AC contains the true 
sign of the twos-complement value. 

For example, given these conditions: 

AR = 11111010 00110010 

AV = 1, indicating overflow 

AC = 0, the true sign bit of this value 

1 . Detect Exponent, Modifier = HIX 
SE gets set to +1 

2. Normalize, Modifier = HI, SE = 1 

AR = 11111010 00110010 
SR = 01111101 00011001 

The AC bit is supplied as the sign bit, shown in bold above. 

The HIX operation executes properly whether or not there has actually been 
an overflow. Consider this example: 

AR = 11100011 01011011 

AV = 0, indicating no overflow 

AC = 0, not meaningful if AV = 0 

1. Detect Exponent, Modifier = HIX 
SE set to -2 

2. Normalize, Modifier = HI, SE = -2 

AR = 11100011 01011011 

SR = 10001101 0110100000000000 00000000 

The AC bit is not used as the sign bit. A brief examination of Table 2.4 
shows that the HIX mode is identical to the HI mode when AV is not set. 
When the NORM, LO operation is done, the extension bit is zero; when the 
NORM, HI operation is done, the extension bit is AC. 



Program Control B 3 


3.1 OVERVIEW 

This chapter describes the program sequencer of the ADSP-2100 family 
processors. The program sequencer circuitry controls the flow of program 
execution. It contains an interrupt controller and status and condition 
logic. 


3.2 PROGRAM SEQUENCER 

The program sequencer generates a stream of instruction addresses and 
provides flexible control of program flow. It allows sequential instruction 
execution, zero-overhead looping, sophisticated interrupt servicing, and 
single-cycle branching with jumps and calls (both conditional and 
unconditional). 

Figure 3.1, on the following page, shows a block diagram of the program 
sequencer. Each functional block of the sequencer is discussed is detail in 
this chapter. 

This chapter discusses both program sequencer logic and the following 
instructions used to control program flow: 

DO UNTIL 

JUMP 

CALL 

RTS (Return From Subroutine) 

RTI (Return From Interrupt) 

IDLE 

For a complete description of each instruction, refer to Chapter 15, 
Instruction Set Reference. 


3-1 



DMD BUS 



PMA BUS 

Figure 3.1 Program Sequencer Block Diagram 


3-2 




















3.2.1 Next Address Select Logic 

While the processor is executing an instruction, the program sequencer 
pre-fetches the next instruction. The sequencer's next address select logic 
generates a program memory address (for the pre-fetch) from one of four 
sources: 

• PC incrementer 

• PC stack 

• instruction register 

• interrupt controller 

The next address circuit (shown in Figure 3.1) selects which of these 
sources is used, based on inputs from the instruction register, condition 
logic, loop comparator and interrupt controller. The next instruction 
address is then output on the PMA bus for the pre-fetch. 

The PC incrementer is selected as the source of the next address if 
program flow is sequential. This is also the case when a conditional jump 
or return is not taken and when a DO UNTIL loop terminates. The output 
of the PC incrementer is driven onto the PMA bus and is loaded back into 
the program counter to begin the next cycle. 

The PC stack is used as the source for the next address when a return from 
subroutine or return from interrupt is executed. The top stack value is also 
used as the next address when returning to the top of a DO UNTIL loop. 

The instruction register provides the next address when a direct jump is 
taken. The 14-bit jump address is embedded in the instruction word. 

The interrupt controller provides the next program memory address when 
servicing an interrupt. Upon recognizing a valid interrupt, the processor 
jumps to the interrupt vector location corresponding to the active 
interrupt request. 

Another possible source for the next address is one of the 14-17 index 
registers of DAG2 (Data Address Generator 2), used when a register 
indirect jump is executed as in the following instruction: 

JUMP (14); 

In this case the program counter (PC) is loaded from DAG2 via the PMA 
bus. (Data address generators are described in Chapter 4.) 



3.2.2 Program Counter & PC Stack 

The program counter (PC) is a 14-bit register which always contains the 
address of the currently executing instruction. The output of the PC is fed 
into a 14-bit incrementer which adds 1 to the current PC value. The output 
of the incrementer can be selected by the next address multiplexer to fetch 
the next sequential instruction. 

Associated with the PC is a 14-bit by 16- word stack that is pushed with the 
output of the incrementer when a CALL instruction is executed. The PC 
stack is also pushed when a DO UNTIL is executed and when an interrupt 
is processed. For interrupts, however, the incrementer is disabled so that 
the current PC value (instead of PC+1) is pushed. This allows the current 
instruction, which is aborted, to be refetched upon returning from the 
interrupt service routine. The pushing and popping of the PC stack occurs 
automatically in all of these cases. The stack can also be manually popped 
with the POP instruction. 

A special instruction is provided for reading (and popping) or writing 
(and pushing) the top value of the PC stack. This instruction uses the 
pseudo register TOPPCSTACK, described at the end of this chapter. 

The output of the next address multiplexer is fed back to the PC, which 
normally reloads it at the end of each processor cycle. In the case of a 
register indirect jump, however, DAG2 drives the PMA bus with the next 
instruction address and the PC is loaded directly from the PMA bus. 

3.2.3 Loop Counter & Stack 

The counter and count stack provide the program sequencer with a 
powerful looping mechanism. The counter is a 14-bit register with 
automatic post-decrement capability that controls the flow of program 
loops which execute a predetermined number of times. Count values are 
14-bit unsigned-magnitude values. 

Before entering the loop, the counter (CNTR register) is loaded with the 
desired loop count from the lower 14 bits of the DMD bus. The actual loop 
count N is loaded, as opposed to N-l. This is due to the operation of the 
counter expired (CE) status logic, which tests CE (and automatically post- 
decrements the counter) at the end of a DO UNTIL loop that uses CE as its 
termination condition. CE is tested at the beginning of each processor 
cycle and the counter is decremented at the end; therefore CE is asserted 
when the counter reaches 1 so that the loop executes N times. 



The counter may also be tested and automatically decremented by a 
conditional jump instruction that tests CE. The counter is not decremented 
when CE is checked as part of a conditional return or conditional 
arithmetic instruction. 

The counter may be read directly over the DMD bus at any time without 
affecting its contents. When reading the counter, the upper two bits of the 
DMD bus are padded with zeroes. 

The count stack is a 14-bit by 4- word stack which allows nesting of loops 
by storing temporarily dormant loop counts. When a new value is loaded 
into the counter from the DMD bus, the current counter value is 
automatically pushed onto the count stack. The count stack is 
automatically popped whenever the CE status is tested and is true, 
thereby resuming execution of the outer loop (if any). The count stack may 
also be popped manually if an early exit from a loop is taken. 

There are two exceptions to the automatic pushing of the count stack. A 
counter load from the DMD bus does not cause a count stack push if there 
is no valid value in the counter, because a stack location would be wasted 
on the invalid counter value. There is no valid value in the counter after a 
system reset and also after the CE condition is tested when the count stack 
is empty. The count stack empty status bit in the SSTAT register indicates 
when the stack is empty. 

The second exception is provided explicitly by the special purpose syntax 
OWRCNTR (overwrite counter). Writing a value to OWRCNTR 
overwrites the counter with the new value, and nothing is pushed onto 
the count stack. OWRCNTR cannot be read (i.e. used as a source register), 
and must not be written in the last instruction of a DO UNTIL loop. 

3.2.4 Loop Comparator & Stack 

The DO UNTIL instruction initiates a zero-overhead loop using the loop 
comparator and loop stack of the program sequencer. 

On every processor cycle, the loop comparator compares the next address 
generated by the program sequencer to the address of the last instruction 
of the loop (which is embedded in the DO UNTIL instruction). The 
address of the first instruction in the loop is maintained on the top of the 
PC stack. When the last instruction in the loop is executed the processor 
conditionally jumps to the beginning of the loop, eliminating the 
branching overhead otherwise incurred in loop execution. 




The loop stack stores the last instruction addresses and termination 
conditions of temporarily dormant loops. Up to four levels can be stored. 
The only extra cycle associated with the nesting of DO UNTIL loops is the 
execution of the DO UNTIL instruction itself, since the pushing and 
popping of all stacks associated with the looping hardware is automatic. 

When using the counter expired (CE) status as the termination condition 
for the loop, an additional cycle is required for the initial loading of the 
counter. Table 3.1 shows the termination conditions that can be used with 
DO UNTIL. 


Syntax 

Status Condition 

EQ 

Equal Zero 

NE 

Not Equal Zero 

LT 

Less Than Zero 

GE 

Greater Than or Equal Zero 

LE 

Less Than or Equal Zero 

GT 

Greater Than Zero 

AC 

ALU Carry 

NOT AC 

Not ALU Carry 

AV 

ALU Overflow 

NOTAV 

Not ALU Overflow 

MV 

MAC Overflow 

NOT MV 

Not MAC Overflow 

NEG 

X Input Sign Negative 

POS 

X Input Sign Positive 

CE 

Counter Expired 

FOREVER 

Always 


True If: 

AZ = 1 
AZ = 0 

AN .XOR. AV = 1 

AN .XOR. AV = 0 

(AN .XOR. AV) .OR. AZ = 1 

(AN .XOR. AV) .OR. AZ = 0 

AC = 1 

AC = 0 

AV = 1 

AV = 0 

MV = 1 

MV = 0 

AS = 1 

AS = 0 


Table 3.1 DO UNTIL Termination Condition Logic 


When a DO UNTIL instruction is executed, the 14-bit address of the last 
instruction and a 4-bit termination condition (both contained in the DO 
UNTIL instruction) are pushed onto the 18-bit by 4-word loop stack. 
Simultaneously, the PC incrementer output is pushed onto the PC stack. 
Since the DO UNTIL instruction is located just before the first instruction 
of the loop, the PC stack then contains the first loop instruction address, 
and the loop stack contains the last loop instruction address and 
termination condition. The non-empty state of the loop stack activates the 
loop comparator which compares the address on top of the loop stack 
with the address of the next instruction. When these two addresses are 
equal, the loop comparator notifies the next address source selector that 
the last instruction in the loop will be executed on the next cycle. 



At this point, there are three possible results depending on the type of 
instruction at the end of the loop. Case 1 illustrates the most typical 
situation. Cases 2 and 3 are also allowed but involve greater program 
complexity for proper execution. 

Case 1 

If the last instruction in the loop is not a jump, call, return, or idle, the 
next address circuit will select the next address based on the 
termination condition stored on the top of the loop stack. If the 
condition is false, the top address on the PC stack is selected, causing 
a fetch of the first instruction of the loop. If the termination condition 
is true, the PC incrementer is chosen, causing execution to fall out of 
the loop. The loop stack, PC stack, and counter stack (if being used) 
are then popped. 

(Note that conditional arithmetic instructions execute based on the 
condition explicitly stated in the instruction, whereas the loop 
sequencing is controlled by the (implicit) termination condition 
contained on top of the stack.) 

Case 2 

If the last instruction in the loop is a jump, call, or return, the 
explicitly stated instruction takes precedence over the implicit 
sequencing of the loop. If the condition in the instruction is false, 
normal loop sequencing takes place as described for Case 1. 

If the condition in the instruction is true, however, program control 
transfers to the jump/call/ return address. Any actions that would 
normally occur upon an end-of-loop detection do not take place: 
fetching the first instruction of the loop, falling out of the loop and 
popping the loop stack, PC stack, and counter stack, or decrementing 
the counter. 

(Note that for a return instruction, control is passed back to the top of 
the loop since the PC stack contains the beginning address of the 
loop.) 

Case 3 

If the last instruction in the loop is an IDLE, program flow is 
controlled by the IDLE instruction rather than the loop. When the 
IDLE instruction is executed, the processor enters a low-power wait- 
for-interrupt state. When the processor is interrupted, loop execution 
terminates and program execution continues with the first instruction 
following the loop. 



Note: Caution is required when ending a loop with a JUMP, CALL, 
RETURN, or IDLE instruction, or when making a premature exit from a 
loop. Since none of the loop sequencing mechanisms are active while the 
jump/ call/return is being performed, the loop, PC, and counter stacks are 
left with the looping information (since they are not popped). In this 
situation, a manual pop of each of the relevant stacks is required to restore 
the correct state of the processor. A subroutine call poses this problem 
only when it is the last instruction in a loop; in such cases, the return 
causes program flow to transfer to the instruction just after the loop. Calls 
within a loop that are not the last instruction operate as in Case 1. 

The only restriction concerning DO UNTIL loops is that nested loops 
cannot terminate on the same instruction. Since the loop comparator can 
only check for one loop termination at a time, falling out of an inner loop 
by incrementing the PC would go beyond the end address of the outer 
loop if they terminated on the same instruction. 


3.3 PROGRAM CONTROL INSTRUCTIONS 

The following sections describe the primary instructions used to control 
program flow. 

3.3.1 JUMP Instruction 

The 14-bit jump address is embedded in the JUMP instruction word. 

When a JUMP instruction is decoded, the jump address is input directly to 
the next address mux of the program sequencer. The address is driven 
onto the PMA bus and fed back to the PC for the next cycle. The following 
instruction, for example, 

JUMP fir_start; 

jumps to the address of the label f ir_start 

3.3. 1. 1 Register Indirect JUMPs 

In this case of register indirect jumps, the jump address is supplied by one 
of the I registers of DAG2 (14, 15, 16, or 17). (Data address generators are 
described in Chapter 4.) The address is driven onto the PMA bus by 
DAG2, and is loaded into the PC on the next cycle. For example, the 
instruction 

JUMP (14) ; 

will jump to the address contained in the 14 register. 



3.3.2 CALL Instruction 

The CALL instruction executes in a similar fashion as the JUMP 
instruction. The address of the subroutine is embedded in the CALL 
instruction word and, once extracted from the instruction register, is fed 
back the PC for the next cycle. In addition, the current value of the 
program counter is incremented and pushed onto the PC stack. Upon 
return from the subroutine, the PC stack is popped into the program 
counter and execution resumes with the instruction following the CALL. 

3.3.3 DO UNTIL Loops 

The most common form of a DO UNTIL loop uses the counter register 
(CNTR) as a loop iteration counter. When the counter is used to control 
loop iteration, CE (counter expired) must be used as the DO UNTIL 
termination condition. A simple example of this type of loop is as follows: 


L0=10; 

IO= / 'data_buf fer; 


M0=1 ; 
CNTR= 10; 


{setup circular buffer length register} 

{load pointer with first address of} 

{circular buffer} 

{setup modify register for pointer increment} 
{load counter with circular buffer length} 


DO loop UNTIL CE; {repeat loop until counter expired} 
DM(I0,M0)=0; {initialize/clear circular buffer} 

. . .any instruction. . . 
loop: . . .any instruction. . . 


When the 
CNTR=10; 

instruction is executed, prior to entering the loop, the counter is loaded via 
the DMD bus. Any previously existing count would be simultaneously 
pushed onto the count stack; this push operation is omitted if the counter 
is empty. The 

DO loop UNTIL CE; 

instruction itself only sets up the conditions for looping; no other 
operation occurs while the instruction is executed. This occurs only once, 
at the beginning of the first time through the loop. 



Execution of the DO UNTIL instruction pushes the address of the 
instruction immediately following the DO UNTIL onto the PC stack (by 
pushing the incremented PC). On the same cycle, the loop stack is pushed 
with the address of the end-of-loop instruction and the termination 
condition. 

As execution continues within the loop, the loop comparator checks each 
instruction's address against the address of the loop's last instruction. 

Until that address is reached, normal execution continues. 

Each time the end of the loop is reached, the loop comparator determines 
that the currently executing instruction is the last in the loop. This affects 
the next address select logic of the program sequencer: instead of using 
the incremented PC for the next address, the loop termination condition is 
evaluated. If the termination condition is false, execution continues with 
the first instruction of the loop (the top of the PC stack is taken as the next 
address). Note that the PC and loop stacks are not popped, only read. 

On the final pass through the loop, the termination condition is true. The 
PC stack is popped and execution continues with the instruction 
immediately following the last instruction of the loop. The loop stack and 
count stack are also popped on this cycle. 

3.3.4 IDLE Instruction 

The IDLE instruction causes the processor to wait indefinitely in a low 
power state until an interrupt occurs. When an unmasked interrupt 
occurs, it is serviced; execution then continues with the instruction 
following the IDLE instruction. 

3.3 A. 1 Slow IDLE 

An enhanced version of the IDLE intruction allows the processor's 
internal clock signal to be slowed, further reducing power consumption. 
The reduced clock frequency, a programmable fraction of the normal clock 
rate, is specified by a selectable divisor given in the IDLE instruction. The 
format of the instruction is 

IDLE (n) ; 

where n = 16, 32, 64, or 128. This instruction keeps the processor fully 
functional, but operating at the slower clock rate. While it is in this state, 
the processor's other internal clock signals, such as SCLK, CLKOUT, and 
timer clock, are reduced by the same ratio. The default form of the 
instruction, when no clock divisor is given, is the standard IDLE 
instruction. 



When the IDLE (n) instruction is used, it effectively slows down the 
processor's internal clock and thus its response time to incoming 
interrupts. The one-cycle interrupt response time of the standard idle state 
is increased by n, the clock divisor. When an enabled interrupt is received, 
the processor will remain in the idle state for up to a maximum of n 
processor cycles before resuming normal operation in = 16, 32, 64, or 128). 

When the IDLE (n) instruction is used in systems that have an externally 
generated serial clock (SCLK), the serial clock rate may be faster than the 
processor's reduced internal clock rate. Under these conditions, interrupts 
must not be generated at a faster rate than can be serviced, due to the 
additional time the processor takes to come out of the idle state (a 
maximum of n processor cycles). 


3.4 INTERRUPTS 

The program sequencer's interrupt controller responds to interrupts by 
shifting control to the instruction located at the appropriate interrupt 
vector address. Tables 3.2-3.7 show the interrupts and associated vector 
addresses for each processor of the ADSP-2100 family. (Note that SPORT1 
can be configured as either a serial port or as a coll ection of control pins 
including two external interrupt inputs, IRQO and IRQ1. See Chapter 5, 
"Serial Ports," for more information about the configuration of SPORT1 .) 

The interrupt vector locations are spaced four program memory locations 
apart — this allows short interrupt service routines to be coded in place, 
with no jump to the service routine required. For interrupt service 
routines with more than four instructions, however, program control must 
be transferred to the service routine by means of a jump instruction placed 
at the interrupt vector location. 

After an interrupt has been serviced, an RTI (Return From Interrupt) 
instruction returns control to the main program by popping the top value 
on the PC stack into the PC; the status stack is also popped to restore the 
previous processor state. 

Interrupts can also be forced under software control; see the discussion of 
the IFC register below. 



Because of the efficient stack and program sequencer, there is no latency 
(beyond synchronization delay) when processing unmasked interrupts, 
even when interrupting DO UNTIL loops. Nesting of interrupts allows 
higher-priority interrupts to interrupt any lower-priority interrupt service 
routines that may currently be executing, also with no additional latency. 

The ADSP-2100 family processors include a secondary register set which 
can be used to provide a fresh set of ALU, MAC, and Shifter registers 
during interrupt servicing. This feature allows single-cycle context 
switching. Use of the secondary registers is described in the "Mode Status 
Register (MSTAT)" section of this chapter. 


Interrup t Source 
RESET startup 
IRQ2 

SPORTO Transmit 

SPORTO Receive 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 
0x0000 

0x0004 (highest priority) 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 (lowest priority) 


Table 3.2 ADSP-21 01/21 15 Interrupts & Interrupt Vector Addresses 


Interrup t Source 
RESET startup 

IRQ2 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 
0x0000 


0x0004 (highest priority) 

0x0010 

0x0014 

0x0018 (lowest priority) 


Table 3.3 ADSP-21 05 Interrupts & Interrupt Vector Addresses 


Interrup t Source 
RESET startup 
IRQ2 

HIP Write (from Host) 
HIP Read (to Host) 
SPORTO Transmit 

SPORTO Receive 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 
0x0000 

0x0004 (highest priority) 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 

OxOOlC 

0x0020 (lowest priority) 


Table 3.4 ADSP-21 11 Interrupts & Interrupt Vector Addresses 



Interrupt Source 

Interrupt Vector Address 


RESET startup (or powerup w/PUCR=l) 

0x0000 (highest priority) 


Powerdown (non-maskable) 

0x002C 


IRQ2 

0x0004 


HIP Write (from Host) 

0x0008 


HIP Read (to Host) 

OxOOOC 


SPORTO Transmit 

0x0010 


SPORTO Receive 

0x0014 


Software Interrupt 1 

0x0018 


Software Interrupt 2 

OxOOlC 


SPORT1 Transmit or IRQ1 

0x0020 


SPORT1 Receive or IRQO 

0x0024 


Timer 

0x0028 (lowest priority) 


Table 3.5 ADSP-2171 Interrupts & Interrupt Vector Addresses 


Interrupt Source 

Interrupt Vector Address 


RESET startup (or powerup w/PUCR=l) 

0x0000 (highest priority) 


Powerdown (non-maskable) 

0x002C 


IRQ2 

0x0004 


IRQL1 (level-sensitive) 

0x0008 


IRQLO (level-sensitive) 

OxOOOC 


SPORTO Transmit 

0x0010 


SPORTO Receive 

0x0014 


IRQE (edge-sensitive) 

0x0018 


Byte DMA Interrupt 

OxOOlC 


SPORT1 Transmit or IRQ1 

0x0020 


SPORT1 Receive or IRQO 

0x0024 


Timer 

0x0028 (lowest priority) 


Table 3.6 ADSP-2181 Interrupts & Interrupt Vector Addresses 


Interrupt Source 

Interrupt Vector Address 


RESET startup (or powerup w/PUCR=l) 

0x0000 (highest priority) 


Powerdown (non-maskable) 

0x002C 


IRQ2 

0x0004 


HIP Write (from Host) 

0x0008 


HIP Read (to Host) 

OxOOOC 


SPORTO Transmit 

0x0010 


SPORTO Receive 

0x0014 


Analog (DAC) Transmit 

0x0018 


Analog (ADC) Receive 

OxOOlC 


SPORT1 Transmit or IRQ1 

0x0020 


SPORT1 Receive or IRQO 

0x0024 


Timer 

0x0028 (lowest priority) 


Table 3.7 ADSP-21msp58/59 Interrupts & Interrupt Vector Addresses 




3-13 



3.4.1 Interrupt Servicing Sequence 

When an interrupt request occurs, it is latched while the processor finishes 
executing the current instruction. The interrupt request is then compared 
with the interrupt mask register, IMASK, by the interrupt controller. 

If the interrupt is not masked, the program sequencer pushes the current 
value of the program counter (which contains the address of the next 
instruction) onto the PC stack — this allows execution to continue, after the 
interrupt is serviced, with the next instruction of the main program. The 
program sequencer also pushes the current values of the AST AT, MSTAT, 
and IMASK registers onto the status stack. AST AT, MSTAT and IMASK 
are stored in this order, with the MSB of ASTAT first, and so on. When 
IMASK is pushed, it is automatically reloaded with a new value that 
determines whether or not interrupt nesting is allowed (based on the 
value of the interrupt nesting enable bit in ICNTL). 

The processor then executes a NOP while simultaneously fetching the 
instruction located at the interrupt vector address. Upon return from the 
interrupt service routine, the PC and status stacks are popped and 
execution resumes with the next instruction of the main program. 

3.4.2 Configuring Interrupts 

The following registers are used to configure interrupts: 

• ICNTL — Determines whether interrupts can be nested and configures 
the external interrupts IRQ2, IRQl, IRQO as edge-sensitive or level- 
sensitive 

• IMASK — Enables or disables (i.e. masks) each individual interrupt (both 
external and internal). 

• IFC — Forces an interrupt or clears a pending edge-sensitive interrupt. 

The IRQ2, IRQl, IRQO interrupts may be either edge-sensitive or level- 
sensitive, as selected in the ICNTL register. The ADSP-2181 has three 
additional interrupt pins: IRQE, IRQLl, and IRQL2. The IRQE input is 
edge-sensitive, while the IRQLl and IRQL2 inputs are level-sensitive. 

For edge-sensitive IRQx interrupts, an interrupt request is latched 
internally whenever a falling edge (high-to-low transition) occurs at the 
input pin. The latch remains set until the interrupt is serviced; it is then 
automatically cleared. A pending edge-sensitive interrupt can also be 
cleared in software by setting the corresponding clear bit in the IFC 
register. 



Edge-sensitive interrupt inputs generally require less external hardware 
than level-sensitive inputs, and allow signals such as sampling-rate clocks 
to be used as interrupts. 

A level-sensitive interrupt must remain asserted until the interrupt is 
serviced. The interrupting device must then deassert the interrupt request 
so that the interrupt is not serviced again. Level-sensitive inputs, however, 
allow many interrupt sources to use the same input by combining them 
logically to produce a single interrupt request. Level-sensitive interrupts 
are not latched. 

Your program can also determine whether or not interrupts can be nested. 
In non-nesting mode, all interrupt requests are automatically masked out 
when an interrupt service routine is entered. In nesting mode, the 
processor allows higher-priority interrupts to be recognized and serviced. 

There are two levels of masking for the Host Interface Port (HIP) 
interrupts of the ADSP-2111, ADSP-2171, and ADSP-21msp58/59. The 
memory-mapped HMASK register configures masking out the generation 
of individual read or write interrupts for each HIP data register. The 
IMASK register can be set to mask or enable the servicing of all HIP read 
interrupts or all HIP write interrupts. Both IMASK and HMASK must be 
set for HDR interrupts. See Chapter 7, "Host Interface Port," for details. 

3.4.2. 1 Interrupt Control Register (ICNTL) 

ICNTL is a 5-bit register that configures the external interrupt requests 
(IRQx ) of each processor. All bits in ICNTL are undefined after a 
processor reset. The bit definitions for each processor's ICNTL register are 
given in Appendix E, "Control /Status Registers." 

ICNTL contains an IRQx sensitivity bit for each external interrupt. The 
sensitivity bits determine whether a given interrupt input is edge- or level- 
sensitive (0 = level-sensitive, 1 = edge-sensitive). There are no sensitivity 
bits for internally generated interrupts. 

The interrupt nesting enable bit (bit 4) in ICNTL determines whether 
nesting of interrupt service routines is allowed. 

When the value of ICNTL is changed, there is a one cycle latency before 
the change in interrupt configuration. 



3.42.2 Interrupt Mask Register (IMASK) 

Each bit of the IMASK register enables or disables the servicing of an 
individual interrupt. Specific bit definitions for each processor's IMASK 
register are given in Appendix E, "Control/Status Registers." The mask 
bits are positive sense: 0=masked, l=enabled. IMASK is set to zero upon a 
processor reset. 

On the ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors, all 
interrupts are automatically disabled for one instruction cycle following 
the execution of an instruction that modifies IMASK. This does not affect 
serial port autobuffering or DMA transfers. 

If an edge-sensitive interrupt request signal occurs when the interrupt is 
masked, the request is latched but not serviced; the interrupt can then be 
recognized in software and serviced later. 

The contents of IMASK are automatically pushed onto the status stack 
when entering an interrupt service routine and popped back when 
returning from the routine. The configuration of IMASK upon entering the 
interrupt service routine is determined by the interrupt nesting enable bit 
(bit 4) of ICNTL; it may be altered, though, as part of the interrupt service 
routine itself. 

When nesting is disabled, all interrupt levels are masked automatically 
(IMASK set to zero) when an interrupt service routine is entered. 

When nesting is enabled, IMASK is set so that only equal and lower 
priority interrupts are masked; higher priority interrupts remain 
configured as they were prior to the interrupt. This is shown graphically, 
for the ADSP-2101, in Table 3.8. 

The interrupt nesting enable bit (in ICNTL) determines the state of IMASK 
upon entering the interrupt, as shown in Table 3.8. 



ICNTL Interrupt Nesting Enable bit = 0 (nesting disabled) 

Interrupt IMASK contents before IMASK contents entering 

level serviced (pushed on stack) interrupt service routine 


0 (low) 

1 
2 

3 

4 

5 (high) 


ijklmn 
i jklmn 
i jklmn 
i jklmn 
i jklmn 
i jklmn 


OOOOOO 

000000 

OOOOOO 

000000 

000000 

000000 


ICNTL Interrupt Nesting Enable bit = 1 (nesting enabled) 

Interrupt IMASK contents before IMASK contents entering 

level serviced (pushed on stack) interrupt service routine 

0 (low) i jklmn ijklmO 

1 ijklmn ijklOO 

2 ijklmn ijkOOO 

3 ijklmn ijOOOO 

4 ijklmn iOOOOO 

5 (high) ijklmn 000000 

("ijklmn" represents any pattern of ones and zeroes) 

Table 3.8 IMASK Entering Interrupt Service Routines (ADSP-2101 example) 

3.42.3 Global Enable/Disable for Interrupts 

Global interrupt enable and disable instructions are available on the 
ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors: 

ENA INTS; 

DIS INTS; 

Interrupts are enabled by default after reset. The DIS INTS instruction 
causes all interrupts (including powerdown) to be masked out regardless 
of the contents of IMASK. The ENA INTS instruction allows all 
unmasked interrupts to be serviced again. 


Disabling interrupts does not affect serial port autobuffering. 



3. 4.2. 4 Interrupt Force & Clear Register (IFC) 

IFC is a write-only register that allows the forcing and clearing of edge- 
sensitive interrupts in software. An interrupt is forced or cleared under 
program control by setting the force or clear bit corresponding to the 
desired interrupt. After the force or clear bit is set, there is one cycle of 
latency before the interrupt is actually forced or cleared (except for the 
timer interrupt on the ADSP-2101/2105/2111/2115 processors). 

Edge-sensitive interrupts can be forced by setting the appropriate force bit 
in IFC. This causes the interrupt to be serviced once, unless masked. An 
external interrupt must be edge-sensitive (as determined by ICNTL) to be 
forced. The timer, SPORT, and analog ADC/DAC interrupts also behave 
like edge-sensitive interrupts and can be masked, cleared and forced. 

Pending edge-sensitive interrupts can be cleared by setting the 
appropriate clear bit in IFC. Edge-triggered interrupts are cleared 
automatically when the corresponding interrupt service routine is called. 

Specific bit definitions for each processor's IFC register are given in 
Appendix E, "Control /Status Registers." The IFC registers of the ADSP- 
2111, ADSP-2171, and ADSP-21msp58 processors do not include force/ 
clear bits for Host Interface Port interrupts; HIP interrupts cannot be 
forced or cleared in software. 

3.4.3 Interrupt Latency 

For the timer, IRQx, SPORT, HIP, and analog interface interrupts, the 
latency from when an interrupt occurs to when the first instruction of the 
service routine is executed is at least three full cycles. This is shown in 
Figure 3.2. Two cycles are required to synchronize t he in terrupt internally, 
assuming that setup and hold times are met (for the IRQx input pins). 

Since interrupts are only serviced on instruction boundaries, the 
instruction(s) executed during these two cycles must be fully completed, 
including any extra cycles inserted due to Bus Request/Bus Grant or 
memory wait states, before execution continues. 

The third cycle of latency is needed to fetch the first instruction stored at 
the interrupt vector location. During this cycle, the processor executes a 
NOP instead of the instruction that would normally have been executed. 
On the next cycle, execution continues at the first instruction of the 
interrupt service routine. The address of the aborted instruction is pushed 
onto the PC stack; it will be fetched when the interrupt service routine is 
completed. 



CLKOUT 


Interrupt 



Instruction 

Executing 


Address for 
Instruction Fetch 


- ) 

1 M ) 


^ NOP 

Vlstinstrof ^ 
/\serv routine j 







L " ) 

( n+1 

V interrupt 

A vector i 

t M ) 


Figure 3.2 Interrupt Latency (Timer, TRQx, SPORT, HIP, & Analog Interrupts) 


(Note that this latency for the timer interrupt only applies for the ADSP-2171, 
ADSP-2181, and ADSP-21msp58/59 processors. See the next section for a 
description of timer interrupt latency on the ADSP-2101, ADSP-2105, 
ADSP-2115, ADSP-2111.) 


For a pending interrupt that is masked, the latency from execution of the 
instruction that unmasks the interrupt (in IMASK) to the first instruction of 
the service routine is one cycle. This one-cycle latency is similar to that shown 
in Figure 3.3 for the timer interrupt of the ADSP-2101 /2105/2111/2115, with 
the "n" instruction executing being the instruction that writes to IMASK (to 
unmask the interrupt). 

3.4.3. 1 Timer Interrupt Latency on ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111 

For the timer interrupt on these processors, the latency from when the 
interrupt occurs to when the first instruction of the service routine is executed 
is only one cycle. This is shown in Figure 3.3. The single cycle of latency is 
needed to fetch the instruction stored at the interrupt vector location. 


CLKIN 


Timer 

Value 


Instruction 

Executing 


Address for 
Instruction Fetch 


J )f^T)( )( l 




V interrupt \ 

x 

A A 

A vector i / 

L_ A 


Figure 3.3 Timer Interrupt Latency for ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111 


3-19 



3.5 STATUS REGISTERS & STATUS STACK 

Processor status and mode bits are maintained in internal registers which 
can be independently read and written over the DMD bus. These registers 
are: 

ASTAT Arithmetic status register 
SSTAT Stack status register (read-only) 

MSTAT Mode status register 

ICNTL Interrupt control register 

IMASK Interrupt mask register 

IFC Interrupt force/clear register(write-only) 

The interrupt-configuring status registers are described in the previous 
section. ASTAT, SSTAT, and MSTAT are discussed in the following 
sections. 

The current ASTAT, MSTAT, and IMASK values are pushed onto the 
status stack when the processor responds to an interrupt; they are popped 
upon return from the interrupt service routine (with the RTI instruction). 
The depth of the stack varies from processor to processor. In each case, 
sufficient stack depth is provided to accommodate nesting of all 
interrupts. 

3.5.1 Arithmetic Status Register (ASTAT) 

ASTAT is eight bits wide and holds the status information generated by 
the computational blocks of the processor. The individual bits of ASTAT 
are defined as shown in Figure 3.4. The bits which express a particular 
condition (AZ, AN, AV, AC, MV) are all positive sense (l=true, 0=false). 


7 6 5 4 3 2 1 0 



SS MV AQ AS AC AV AN AZ 


ALU Result Zero 
ALU Result Negative 
ALU Overflow 
ALU Carry 
ALU X Input Sign 
ALU Quotient 
MAC Overflow 
Shifter Input Sign 



3-20 


Figure 3.4 ASTAT Register 




Each of the bits is automatically updated when a new status is generated 
by an arithmetic instruction. Each bit is affected only by a subset of 
arithmetic operations, as defined by the following table: 

Status Bit Updated by 

AZ, AN, AV, AC Any ALU operation except DIVS, DIVQ 
AS ALU absolute value operation (ABS) 

AQ ALU divide operations (DIVS, DIVQ) 

MV Any MAC operation except saturate MR (SAT MR) 

SS Shifter EXP operation 

Arithmetic status is latched into AST AT at the end of the cycle in which it 
was generated, and cannot be used until the next cycle. 

Loading any ALU, MAC, or Shifter input or output registers directly from 
the DMD bus does not affect any of the arithmetic status bits. Executing 
the ALU instruction PASS sets the AZ and AN bits for a given X or Y 
operand and clears AC. 

3.5.2 Stack Status Register (SSTAT) 

The SSTAT register is eight bits wide and holds information about the four 
processor stacks. The individual bits of SSTAT are defined as shown in 
Figure 3.5. All of the bits are positive sense (l=true, 0=false). 


7 6 5 4 3 2 1 0 



PC Stack Empty 
PC Stack Overflow 
Count Stack Empty 
Count Stack Overflow 
Status Stack Empty 
Status Stack Overflow 
Loop Stack Empty 
Loop Stack Overflow 

Figure 3.5 SSTAT Register (Read-Only) 



3-21 




The empty status bits indicate that the number of pop operations for the 
stack is greater than or equal to the number of push operations that have 
occurred since the last processor reset. The overflow status bits indicate 
that the number of push operations for the stack has exceeded the number 
of pop operations, by an amount that is greater than the total depth of the 
stack. When this occurs, the values most recently pushed will be missing 
from the stack — older stack values are considered more important than 
new. 


Since a stack overflow represents a permanent loss of information, the 
stack overflow status bits "stick" once they are set, and subsequent pop 
operations have no effect on them. In this situation, then, it is possible to 
have both the stack empty and stack overflow bits set for a given stack. 

Assume, for example, that the four-location count stack is overflowed by 
five successive pushes. Five successive pops will restore the stack empty 
condition, but will not clear the overflow condition. The processor must be 
reset to clear the stack overflow status. 


3.5.3 Mode Status Register (MSTAT) 

The MSTAT register determines the operating mode of the processor. The 
individual bits of MSTAT are defined as shown in Figure 3.6. 

6 5 4 3 2 1 0 




Data Register Bank Select 
0 = primary, 1 = secondary 
Bit Reverse Mode Enable (DAG1) 
ALU Overflow Latch Mode Enable 
AR Saturation Mode Enable 
MAC Result Placement 
0 = fractional, 1 = integer 
Timer Enable 
Go Mode Enable 


Figure 3.6 MSTAT Register 




MSTAT can be modified by writing a new value to it with a MOVE 
instruction. Unlike the other status registers, MSTAT can also be altered 
with the Mode Control instruction (ENA, DIS). The Mode Control 
instruction provides a high-level, self-documenting method of configuring 
the processors' operating modes. Refer to the description of the Mode 
Control instruction in Chapter 15, "Instruction Set Reference," for further 
details. 

To enable the bit reverse mode, for example, the following instruction 
could be used: 

ENA BIT_REV; 

The bit-reverse mode, when enabled, bitwise reverses all addresses 
generated by data address generator 1 (DAG1). This is useful for 
reordering the input or output data of an EFT algorithm. 

The ADSP-2100 family processors include a secondary register set which 
can be used to provide a fresh set of ALU, MAC, and Shifter registers at 
any time, for example during execution of a subroutine. The data register 
bank select bit of MSTAT determines which set of data registers is active 
(0=primary, l=secondary). The secondary register set duplicates all of the 
input and result registers of the computation units, ALU, MAC, and 


Shifter: 

AXO 

MXO 

SI 

AX1 

MX1 

SE 

AYO 

MYO 

SB 

AY1 

MY1 

SRI 

AF 

MF 

SRO 

AR 

MRO 



MR1 

MR2 



The following mode control instruction, for example, switches from the 
processor's primary register set to its secondary register set: 

ENA SEC_REG; 

while the following instruction switches back to the primary register set: 
DIS SEC_REG ; 


3-23 



The ALU overflow latch mode causes the AV status bit to "stick" once it is 
set. In this mode, AV will be set by an overflow and will remain set even if 
subsequent ALU operations do not generate overflows. AV can then be 
cleared only by writing a zero into it. 

AR saturation mode, when enabled, causes AR to be saturated to the 
maximum positive (0x7FFF) or negative (0x8000) values whenever an 
ALU overflow occurs. 

The MAC result placement mode determines whether the multiplier 
operates in integer or fractional format. This mode is discussed in Chapter 
2, "Computational Units." 

Setting the timer enable bit causes the timer to begin decrementing. 
Clearing this bit halts the timer. 

Enabling GO mode allows the processor to continue executing instructions 
from internal program memory during a bus grant. The processor will 
halt, waiting for the buses to be released, only when an access of external 
memory is required. When GO mode is disabled, the processor always 
halts during bus grant. 


3.6 CONDITIONAL INSTRUCTIONS 

The condition logic circuit of the program sequencer determines whether a 
conditional instruction is executed, for example a jump, call, or arithmetic 
operation. It also controls implicit loop sequencing operations based upon 
the loop continuation condition on top of the loop stack. The condition 
logic takes raw status information from ASTAT and the down counter and 
derives a set of sixteen composite status conditions. 

The status conditions and corresponding assembly language syntax are 
listed in Table 3.9. These status conditions are used with the IF condition 
clause available on some instructions. In addition, the status of the FI pin 
(Flag In) can also be used as a condition for JUMP and CALL instructions. 


3-24 



Syntax Status Condition 

EQ Equal Zero 

NE Not Equal Zero 

LT Less Than Zero 

GE Greater Than or Equal Zero 

LE Less Than or Equal Zero 

GT Greater Than Zero 

AC ALU Carry 

NOT AC Not ALU Carry 

AV ALU Overflow 

NOT AV Not ALU Overflow 

MV MAC Overflow 

NOT MV Not MAC Overflow 

NEG X Input Sign Negative 

POS X Input Sign Positive 

NOT CE Not Counter Expired 

FLAG_IN* FI pin 

NOT FLAG _IN* Not FI pin 


True If: 

AZ = 1 
AZ = 0 

AN .XOR. AV = 1 

AN .XOR. AV = 0 

(AN .XOR. AV) .OR. AZ = 1 

(AN .XOR. AV) .OR. AZ = 0 

AC = 1 

AC = 0 

AV = 1 

AV = 0 

MV = 1 

MV = 0 

AS = 1 

AS = 0 

Last sample of FI pin = 1 
Last sample of FI pin = 0 


* Only available on JUMP and CALL instructions. 

Table 3.9 IF Condition Logic 


3.7 TOPPCSTACK 

A special version of the Register-to-Register Move instruction. Type 17, is 
provided for reading (and popping) or writing (and pushing) the top 
value of the PC stack. The normal POP PC instruction does not save the 
value popped from the stack, so to save this value into a register you must 
use the following special instruction: 

reg = TOPPCSTACK; (pop PC stack into reg} 

{ " toppcstack" may also be lowercase} 

The PC stack is also popped by this instruction, after a one-cycle delay. 

A NOP should usually be placed after the special instruction, to allow the 
pop to occur properly: 

reg = TOPPCSTACK; 

NOP; (allow pop to occur correctly} 


3-25 



There is no standard PUSH PC stack instruction. To push a specific value 
onto the PC stack, therefore, use the following special instruction: 

TOPPCSTACK= reg; (push reg contents onto PC stack} 

The stack is pushed immediately, in the same cycle. 

Examples: 

AXO = TOPPCSTACK; {pop PC stack into AXO} 

NOP; 

TOPPCSTACK = 17 ; {push contents of 17 onto PC stack} 

Only the following registers may be used in the special TOPPCSTACK 
instructions: 

ALU, MAC, 


& Shifter 
Registers 

DAG 

Registers 

AXO 

10 

14 

AX1 

11 

15 

MXO 

12 

16 

MX1 

13 

17 

AYO 

MO 

M4 

AY1 

Ml 

M5 

MYO 

M2 

M6 

MY1 

M3 

M7 

AR 

L0 

L4 

MRO 

LI 

L5 

MR1 

L2 

L6 

MR 

L3 

L7 


SI 

SE 

SRO 

SRI 

The Type 17 Register Move instruction is described in Chapter 15, 
Instruction Set Reference. Note that TOPPCSTACK may not be used as a 
register in any other instruction type! 



3.7.1 TOPPCSTACK Restrictions 

There are several restrictions on the use of the special TOPPCSTACK 
instructions, as described below. 


1. ) The pop and read TOPPCSTACK instruction may not be placed 

directly before an RTI instruction (return from interrupt). A NOP 
must be inserted in between: 

reg = TOPPCSTACK; 

NOP; (allow pop to occur correctly} 

RTI; (another pop happens automatically} 

2. ) The pop and read TOPPCSTACK instruction may not be the last or 

next-to-last instruction in a Do Until loop. Neither instruction 1 nor 
instruction 2 may be the pop/read TOPPCSTACK instruction in the 
following code: 

DO loop UNTIL CE; 

AX0=DM(I5,M5) ; 

instruction 2; 
loop: instruction 1; 


3. ) There must be an equal number of pushes and pops within any Do 

Until loop, including any normal POP PC instructions as well as the 
special TOPPCSTACK pop/read and push/ write instructions. 

4. ) Several restrictions exist in relation to the RTS (return from 

subroutine), RTI (return from interrupt routine), and POP PC 
instructions. If instruction 3 in the following sequence is an RTS, RTI, 
or POP PC, 


instruction 1; 
instruction 2 ; 
instruction 3; 


(if this is an RTS, RTI, or POP PC 




Data Transfer i 4 


4.1 OVERVIEW 

This chapter describes the processor units that control the movement of 
data to and from the processor, and from one data bus to the other within 
the processor. These are the data address generators (DAGs) and the unit 
for exchanging data between the program memory data bus and the data 
memory data bus — the PMD-DMD bus exchange unit. 


4.2 DATA ADDRESS GENERATORS (DAGS) 

Every device in the ADSP-2100 family contains two independent data 
address generators so that both program and data memories can be 
accessed simultaneously. The DAGs provide indirect addressing 
capabilities. Both perform automatic address modification. For circular 
buffers, the DAGs can perform modulo address modification. The two 
DAGs differ: DAG1 generates only data memory addresses, but provides 
an optional bit-reversal capability, DAG2 can generate both data memory 
and program memory addresses, but has no bit-reversal capability. 

While the following discussion explains the internal workings of the 
DAGs, bear in mind that the ADSP-2100 Family Development Software 
(assembler and linker) provides a direct method for declaring data buffers 
as circular or linear and for managing the placement of the buffer in 
memory. Only the initializing of DAG registers must be explicitly 
programmed: see "Indirect Addressing" and "Modulo Addressing 
(Circular Buffers)" below. 

4.2.1 DAG Registers 

Figure 4.1, on the following page, shows a block diagram of a single data 
address generator. There are three register files: the modify (M) register 
file, the index (I) register file, and the length (L) register file. Each of the 
register files contains four 14-bit registers which can be read from and 
written to via the DMD bus. 


4-1 



DMD BUS 



ADDRESS 

Figure 4.1 Data Address Generator Block Diagram 

The I registers (10-13 in DAG1, 14-17 in DAG2) contain the actual addresses 
used to access memory. When data is accessed in indirect mode, the 
address stored in the selected I register becomes the memory address. 
With DAG1, the output address can be bit-reversed by setting the 
appropriate mode bit in the mode status register (MSTAT) as discussed 
below or by using the ENA BIT_REV instruction. Bit-reversal facilitates 
FFT addressing. 


The data address generators employ a post-modify scheme; after an 
indirect data access, the specified M register (M0-M3 in DAG1, M4-M7 in 
DAG2) is added to the specified I register to generate the updated I value. 
The choice of the I and M registers are independent within each DAG. In 
other words, any register in the 10-3 set may be modified by any register in 
the M0-M3 set in any combination, but not by those in DAG2 (M4-M7). 

The modification values stored in M registers are signed numbers so that 
the next address can be either higher or lower. 


4-2 







The address generators support both linear addressing and circular 
addressing. The value of the L register corresponding to an I register (for 
example, LO would correspond to 10) determines which addressing scheme is used 
for that I register. For circular buffer addressing, the L register is initialized 
with length of the buffer. For linear addressing, the modulus logic is 
disabled by setting the corresponding L register to zero. 

Each time an I register is selected, the corresponding L register provides 
the modulus logic with the length information. If the sum of the M register 
and the I register crosses the buffer boundary, the modified I register 
value is calculated by the modulus logic using the L register value. 

All data address generator registers (I, M, and L registers) are loadable 
and readable from the lower 14 bits of the DMD bus. Since I and L register 
contents are considered to be unsigned, the upper 2 bits of the DMD bus 
are padded with zeros when reading them. M register contents are signed; 
when reading an M register, the upper 2 bits of the DMD bus are sign- 
extended. 

4.2.2 Indirect Addressing 

The ADSP-2100 family processors allow two addressing modes for data 
memory fetches: direct and register indirect. Indirect addressing is 
accomplished by loading an address into an I (index) register and 
specifying one of the available M (modify) registers. 

The L registers are provided to facilitate wraparound addressing of 
circular data buffers. A circular buffer is only implemented when an L 
register is set to a non-zero value. For linear (i.e. non-circular) indirect 
addressing, the L register corresponding to the I register used must be set 
to zero. 

Do not assume that the L registers are automatically initialized or may be 
ignored; the I, M, and L registers contain random values following processor 
reset. Your program must initialize the L registers corresponding to any I 
registers it uses. 

4.2.2. 1 Initialize L Registers To 0 For Non-Circular Addressing 

Setting an L register to a non-zero value activates the processor's circular 
addressing modulus logic. For linear indirect addressing you must set the 
appropriate L register to zero to disable the modulus logic. 



Here is a simple example of linear indirect addressing: 


13=0x3800; 

M2 = 0 ; 

L3 = 0; 

AX0=DM { 13 , M2 ) ; 


Here is an example which uses a memory variable to store an address 
pointer: 


.VAR/DM/RAM addr_ptr; 
l3=DM(addr_ptr) ; 

L3 = 0; 

Ml=0 ; 

AX0=DM ( 13 , Ml ) ; 


{variable holds address to be accessed} 
{13 loaded using direct addressing} 
{disable circular addressing} 

{no post-modify of 13} 

{AXO loaded using indirect addressing} 


4.2.3 Modulo Addressing (Circular Buffers) 

The modulus logic implements automatic modulo addressing for accessing 
circular data buffers. To calculate the next address, the modulus logic uses 
the following information: 

• The current location, found in the I register (unsigned). 

• The modify value, found in the M register (signed). 

• The buffer length, found in the L register (unsigned). 

• The buffer base address. 


From these inputs, the next address is calculated according to the formula: 

Next Address = (I + M-B) Modulo (L) + B 

where: 

I = current address 

M = modify value (signed) 

B = base address 

L = buffer length 

M + I = modified address 

The inputs are subject to the condition: 

I M I < L 

This condition insures that the next address cannot wrap around the buffer 
more than once in one operation. 



4.2.4 Calculating The Base Address 

The base address of a circular buffer of length L is 2 n or a multiple of 2 n , 
where n satisfies the condition: 

2”' 1 < L < 2 n 


In other words, the base address is L "rounded" upwards to the closest 
power of 2 (or its multiple). This rule implies that a certain number of low- 
order bits of the base address must be zeroes. 

In practice, you do not need to calculate n yourself; the linker 
automatically places circular buffers at a proper address. 

4.2.4. 1 Circular Buffer Base Address Example 1 

For example, let us assume that the buffer length is eight. The length of the 
buffer must be less than or equal to some value 2 n ; n therefore, must be 
three or greater. The left side of the inequality rule specifies that the buffer 
length must be greater than the value 2 n l ; n therefore must be three or less. 
The only value of n that satisfies both inequalities is three. Valid base 
addresses are multiples of 2 n , so in this example valid base addresses are 
multiples of eight: 0x0008, 0x0010, 0x0018, and so on. 

4.2. 4. 2 Circular Buffer Base Address Example 2 

As a second example, assume a buffer length of seven. The inequality 
again yields the same value for n, namely, three. With a buffer length of 
seven, therefore, the valid base addresses are multiples of eight: 0x0008, 
0x0010, 0x0018, and so on. 

4.2A.3 Circular Buffer Operation Example 1 

Suppose that 10 = 5, M0 = 1, L0 = 3, and the base address = 4. The next 
address is calculated as: 

(10 + M0 - B) mod L0 +B = (5 + 1-4) mod 3 + 4 = 6 

The successive address calculations using 10 for indirect addressing 
produce the sequence: 5, 6, 4, 5, 6, 4, 5 .... For M0 = -1 (0x3FFF), 10 would 
produce the sequence: 5, 4, 6, 5, 4, 6, 5, 4 .... 



4.2.4.4 Circular Buffer Operation Example 2 

Assume that 10 = 9, MO = 3, LO = 5, and the base address = 8. The 
five-word buffer resides at locations 8 through 12 inclusive. The next 
address is calculated as: 

(10 + MO - B) mod LO + B = (9 + 3-8) mod 5 + 8 = 12 

The successive address calculations using 10 for indirect addressing 
produce the sequence: 9, 12, 10, 8, 11, 9 ... This example highlights the fact 
that the address sequence does not have to result in a "direct hit" of the 
buffer boundary. 

4.2.5 Bit-Reverse Addressing 

The bit-reverse logic is primarily intended for use in FFT computations 
where inputs are supplied or the outputs generated in bit-reversed order. 
Bit-reversing is available only on addresses generated by DAG1. The pivot 
point for the reversal is the midpoint of the 14-bit address, between bits 6 
and 7. This is illustrated in the following chart. 


Individual address lines (ADDR N ) 


Normal Order 

13 

12 

11 

10 

09 

08 

07 

06 

05 

04 

03 

02 

01 

00 

Bit-reversed 

00 

01 

02 

03 

04 

05 

06 

07 

08 

09 

10 

11 

12 

13 


Bit-reversed addressing is a mode, enabled and disabled by setting a 
mode bit in the mode status register (MSTAT). When enabled, all 
addresses generated using index registers 10-3 are bit-reversed upon 
output. (The modified valued stored back after post-update remains in 
normal order.) This mode continues until the status bit is reset. 

It is possible to bit-reverse address values less than 14 bits wide. You must 
determine the first address and also initialize the M register to be used 
with a value calculated to modify the I register bit-reversed output to the 
desired range. This value is: 

2(14- N) 

where N is the number of bits you wish to output reversed. For a 
complete example of this, refer to Section 6.6.5 .2 "Modified Butterfly" in 
Chapter 6, One-Dimensional FFTs, of the applications handbook Digital 
Signal Processing Applications Using the ADSP-2100 Family (Volume 1). 



4.3 PROGRAMMING DATA ACCESSES 

The ADSP-2100 Family Development Software supports the declaration 
and use of a simple data structure: one-dimensional arrays, or buffers. The 
array may contain a single value (a variable) or multiple values (an array). 
In addition, the array may be used as a circular buffer. Here is a brief 
discussion of each instance, with an example of how they are declared and 
used in assembly language. Complete syntax for all assembler directives is 
given in the ADSP-2100 Family Assembler Tools Manual. 

4.3.1 Variables & Arrays 

Arrays are the basic data structure of the ADSP-21xx. In our literature, the 
word "array" and the expression "data buffer" (as well as "variable") are 
used interchangeably. Arrays are declared with assembler directives and 
can be referenced indirectly and by name, can be initialized from 
immediate values in a directive or from external data files, and can be 
linear or circular with automatic wraparound. 

An array is declared with a directive such as 

.VAR/DM coefficients [128] ; 

This declares an array of 128 16-bit values located in data memory (DM). 
The special operators A and % reference the address and length, 
respectively, of the array. It could be referenced as shown below: 

I0= A coef f icients ; (point to address of buffer} 

L0=0; (set L register to zero} 

MX0=DM(I0,M0) ; (load MXO from buffer} 

These instructions load a value into MXO from the beginning of the 
coefficients buffer in data memory. With the automatic post-modify of the 
DAGs, you could execute the second of these instructions in a loop and 
continuously advance through the buffer. 

Alternatively, when you only need to address the first location, you can 
directly use the buffer name as a label in many circumstances such as 

MXO=DM(coefficients) ; 

The linker substitutes the actual address for the label. 


4-7 




It is also possible to initialize a complete array /buffer from a data file, 
using the .INIT directive: 

. INIT coefficients: < filename . dat> ; 

This assembler directive reads the values from the file filename.dat into the 
array at link time. This feature is supported only in the simulator — data 
cannot be loaded directly into on-chip data memory by the hardware 
booting sequence. 

An array or data buffer with a length of one is a simple single- word 
variable, and is declared in this way: 

.VAR/DM coefficient; 

4.3.2 Circular Buffers 

A common requirement in DSP is the circular buffer. This is directly 
implemented by the processors' data address generators (DAGs), using 
the L (length) registers. First, you must declare the buffer as circular: 

.VAR/DM/CIRC coefficients [128] ; 


This identifies it to the linker for placement on the proper address 
boundary. Next, you must initialize the L register, typically using the 
assemblers's % operator (or a constant) and, in the example below, the I 
register and M register: 

L0=%coef f icients ; (length of circular buffer} 

I0= A coef f icients ; (point to first address of buffer} 

M0=1; (increment by 1 location each time} 

Now a statement like 


MX0=DM ( 10 , MO ) ; 


(load MXO from buffer} 


placed in a loop, cycles continuously through coefficients and wraps 
around automatically. 


4-8 



4.4 PMD-DMD BUS EXCHANGE 

The PMD-DMD bus exchange unit couples the program memory data bus 
and the data memory data bus, allowing them to transfer data between 
them in both directions. Since the program memory data (PMD) bus is 24 
bits wide, while the data memory data (DMD) bus is 16 bits wide, only the 
upper 16 bits of PMD can be directly transferred. An internal register (PX) 
is loaded with (or supplies) the additional 8 bits. This register can be 
directly loaded or read when the full 24 bits a,re required. 

Note that when reading data from program memory and data memory 
simultaneously, there is a dedicated path from the upper 16 bits of the 
PMD bus to the Y registers of the computational units. This read-only path 
does not use the bus exchange circuit; it is the path shown on the 
individual computational unit block diagrams. 

4.4.1 PMD-DMD Block Diagram Discussion 

Figure 4.2 shows a block diagram of the PMD-DMD bus exchange. There 
are two types of connections provided by this circuitry. 

PMD BUS 
24 



Figure 4.2 PMD-DMD Bus Exchange 


4-9 




The first type of connection is a one-way path from each bus to the other. 
This is implemented with two tristate buffers connecting the DMD bus 
with the upper 16 bits of the PMD bus. One of these two buffers is 
normally used when data is exchanged between the program memory and 
one of the registers connected to the DMD bus. This is the path used to 
write data to program memory; it is not shown in the individual 
computational unit block diagrams. 

The second connection is through the PX register. The PX register is 8-bits 
wide and can be loaded from either the lower 8 bits of the DMD bus or the 
lower 8 bits of the PMD bus. Its contents can also be read to the lower 8 
bits of either bus. 

PX register access follows the principles described below. 

From the PMD bus, the PX register is: 

1. Loaded automatically whenever data (not an instruction) is read from 
program memory to any register. For example: 

AXO = PM(I4,M4); 

In this example, the upper 16 bits of a 24-bit program memory word are 
loaded into AXO and the lower 8 bits are automatically loaded into PX. 

2. Read out automatically as the lower 8 bits when data is written to 
program memory. For example: 

PM(I4,M4) = AXO; 

In this example, the 16 bits of AXO are stored into the upper 16 bits of a 
24-bit program memory word. The 8 bits of PX are automatically 
stored to the 8 lower bits of the memory word. 



From the DMD bus, the PX register may be: 

1. Loaded with a data move instruction, explicitly specifying the PX 
register as the destination. The lower 8 bits of the data value are used 
and the upper 8 are discarded. 

PX = AXO; 

2. Read with a data move instruction, explicitly specifying the PX register 
as a source. The upper 8 bits of the value read from the register are all 
zeroes. 


AXO = PX; 

Whenever any register is written out to program memory, the source 
register supplies the upper 16 bits. The contents of the PX register are 
automatically added as the lower 8 bits. If these lower 8 bits of data to be 
transferred to program memory (through the PMD bus) are important, 
you should load the PX register from DMD bus before the program 
memory write operation. 




Serial Ports 


5.1 OVERVIEW 

Synchronous serial ports, or SPORTs, support a variety of serial data 
communications protocols and can provide a direct interconnection 
between processors in a multiprocessor system. 

These ADSP-2100 family processors contain serial ports: 

Number of 
Serial Ports 
2 
1 
2 
2 
2 
2 
2 

The serial ports, designated SPORTO and SPORT1, have some differences 
that are described in this chapter. On the ADSP-2105, only SPORT1 is 
provided. 


Processor 

ADSP-2101 

ADSP-2105 

ADSP-2115 

ADSP-2111 

ADSP-2171 

ADSP-2181 

ADSP-21 msp58 / 59 


5.2 BASIC SPORT DESCRIPTION 

Each SPORT has a five-pin interface: 

Pin Name Function 

SCLK Serial clock 

RFS Receive frame synchronization 

TFS Transmit frame synchronization 

DR Serial data receive 

DT Serial data transmit 


Table 5.1 SPORT External Interface 




A SPORT receives serial data on its DR input and transmits serial data on 
its DT output. It can receive and transmit simultaneously, for full duplex 
operation. The data bits are synchronous to the serial clock SCLK, which is 
an output if the processor generates this clock or an input if the clock is 
generated externally. Frame synchronization signals RFS and TFS are used to 
indicate the start of a serial data word or stream of serial words. 

Figure 5.1, shows a simplified block diagram of a single SPORT. Data to be 
transmitted is written from an internal processor register to the SPORT's TX 
register via the DMD bus. This data is optionally compressed in hardware, 
then automatically transferred to the transmit shift register. The bits in the shift 
register are shifted out on the SPORT's DT pin, MSB first, synchronous to the 
serial clock. The receive portion of the SPORT accepts data from the DR pin, 
synchronous to the serial clock. When an entire word is received, the data is 
optionally expanded, then automatically transferred to the SPORT's RX 
register, where it is available to the processor. 

The following is a list of SPORT characteristics. Many of the SPORT 
characteristics are configurable to allow flexibility in serial communication. 

• Bidirectional: each SPORT has independent transmit and receive sections. 



Figure 5.1 Serial Port Block Diagram 







Double-buffered: each SPORT section (both receive and transmit) has a 
data register for transferring data words to and from other parts of the 
processor and a register for shifting data in or out. The double-buffering 
provides additional time to service the SPORT. 

Clocking: each SPORT can use an external serial clock or generate its 
own in a wide range of frequencies down to 0 Hz. See Section 5.5. 

Word length: each SPORT supports serial data word lengths from 
three to sixteen bits. See Section 5.6. 

Framing: each SPORT section (receive and transmit) can operate with 
or without frame synchronization signals for each data word; with 
internally-generated or externally-generated frame signals; with active 
high or active low frame signals; with either of two pulse widths and 
frame signal timing. See Section 5.7. 

Companding in hardware: each SPORT can perform A-law and |i-law 
companding according to CCITT recommendation G.711. See 
Section 5.10. 

Autobuffering with single-cycle overhead: using the DAGs, each 
SPORT can automatically receive and/ or transmit an entire circular 
buffer of data with an overhead of only one cycle per data word. 
Transfers between the SPORT and the circular buffer are automatic in 
this mode and do not require additional programming. See 
Section 5.11. 

Interrupts: each SPORT section (receive and transmit) generates an 
interrupt upon completing a data word transfer, or after transferring 
an entire buffer if autobuffering is used. See Section 5.13. 

Multichannel capability: SPORTO can receive and transmit data 
selectively from channels of a serial bitstream that is time-division 
multiplexed into 24 or 32 channels. This is especially useful for T1 
interfaces or as a network communication scheme for multiple 
processors. See Section 5.12. Note: The ADSP-2105 has only one serial 
port (SPORT1) and does not support multichannel operation. 

Alternate configuration: SPORT1 can be configured as two external 
interrupt inputs, IRQO and IRQ1, and the Flag In and Flag Out signals 
instead of as a serial port. The internally generated serial clock may 
still be used in this configuration. See Section 5.4. 




5.2.1 Interrupts 

Each SPORT has a receive interrupt and a transmit interrupt. The priority 
of these interrupts is shown in Table 5.2. 

Highest SPORTO Transmit (on 2-SPORT processors) 

SPORTO Receive (on 2-SPORT processors) 

SPORT1 Transmit 
Lowest SPORT1 Receive 

Table 5.2 SPORT Interrupt Priorities 

For complete details about how interrupts are handled, see the 
'Interrupts" section in Chapter 3, "Program Control." 

5.2.2 SPORT Operation 

Writing to a SPORT's TX register readies the SPORT for transmission; the 
TFS signal initiates the transmission of serial data. Once transmission has 
begun, each value written to the TX register is transferred to the internal 
transmit shift register and subsequently the bits are sent, MSB first. Each 
bit is shifted out on the rising edge of SCLK. 

After the first bit (MSB) of a word has been transferred, the SPORT 
generates the transmit interrupt. The TX register is now available for the 
next data word, even though the transmission of the first word is ongoing. 

In the receiving section, bits accumulate as they are received in an internal 
receive register. When a complete word has been received, it is written to 
the RX register and the receive interrupt for that SPORT is generated. 

Interrupts are generated differently if autobuffering is enabled; see 
"Autobuffering" later in this chapter. 


5.3 SPORT PROGRAMMING 

To the programmer, the SPORT can be viewed as two functional sections. 
The configuration section is a block of control registers (mapped to data 
memory) that the program must initialize before using the SPORTs. The 
data section is a register file used to transmit and receive values through 
the SPORT. 


5-4 




5.3.1 SPORT Configuration 

SPORT configuration is accomplished by setting bit and field values in 
configuration registers. These registers are memory mapped in data 
memory space. SPORTO configuration registers occupy locations 0x3FF3 
to 0x3FFA; SPORT1 configuration registers occupy locations 0x3FEF to 
0x3FF2. The contents of these registers are summarized in Table 5.3 and in 
the register summary in Appendix E. The effects of the various settings 
are described at length in the sections that follow. 

Address Contents 

0x3FFA SPORTO* multichannel receive word enables (31-16) 

0x3FF9 SPORTO* multichannel receive word enables (15-0) 

0x3FF8 SPORTO* multichannel transmit word enables (31-16) 

0x3FF7 SPORTO* multichannel transmit word enables (15-0) 

0x3FF6 SPORTO* control register 

Multichannel mode controls 
Serial clock source 
Frame synchronization controls 
Companding mode 
Serial word length 

0x3FF5 SPORTO* serial clock divide modulus (determines frequency) 

0x3FF4 SPORTO* receive frame sync divide modulus (determines frequency) 

0x3FF3 SPORTO* autobuffer control register 

0x3FF2 SPORT1 control register 

Flag output value 
Serial clock source 
Frame synchronization controls 
Companding mode 
Serial word length 

0x3FFl SPORT1 serial clock divide modulus (determines frequency) 

0x3FF0 SPORT1 receive frame sync divide modulus (determines frequency) 

0x3FEF SPORT1 autobuffer control register (not on ADSP-21msp58/59) 

*SPORTO configuration registers are defined only on processors that have both SPORTO and SPORT1 

Table 5.3 SPORT Configuration Registers 

There are two ways to initialize or to change values in SPORT 
configuration registers: write a register to an immediate address 
(instruction type 3) or write immediate data to an indirect address 
(instruction type 2). With either method, it is important to configure the 
serial port before enabling it. 


5-5 



The first method of programming configuration registers requires no 
setup of DAG registers but does require two instructions to perform the 
write. For example: 

AXO = 0x6B27; 

DM(0x3FF2) = AXO; {the contents of AXO are written} 

{to the address 0x3FF2} 

AXO = 0; 

DM(0x3FF3) = AXO; {the contents of AXO are written} 

{to address 0x3FF3} 

In the second method, the DAG (I) index register must contain the data 
memory address of the configuration register to be written. The modify 
(M) register, which updates the I register after the write, must also contain 
a valid value. And the length (L) register that has the same number as the 
I register must be initialized to zero so that the circular buffer capability is 
not active. For example: 

10 = 0x3 FF2; 

MO = 1; 

L0 = 0; 

DM (10, M0 ) = 0x6B27; {the constant 0x6B27 is written to } 

{address pointed to by 10; pointer } 
{then modified by M0} 

DM ( 10 , M0 ) = 0; {address 0x3FF3 is set to 0} 

Either method works. The second method requires only one cycle to 
configure the registers once the I, M and L registers are initialized. This 
method is, however, more prone to error because the registers are written 
indirectly. You must make sure that the I register contains the intended 
value before the write. 

5.3.2 Receiving And Transmitting Data 

Each SPORT has a receive register and a transmit register. These registers 
are not memory mapped, but are identified by assembler mnemonics. The 
transmit registers are named TX0 and TX1, for SPORTO and SPORT1 
respectively. Receive registers are named RX0 and RX1 for SPORTO and 
SPORT1 respectively. These registers can be accessed at any time during 
program execution using a data memory access with immediate address, 
load of a non-data register with immediate data or register-to-register 
move (instruction types 3, 7 and 17). For example, the following 
instruction would ready SPORT1 to transmit a serial value, assuming 
SPORT1 is configured and enabled: 

TXl = AXO; {the contents of AXO are transmitted} 

{on SPORT1 } 




The following instruction would access a serial value received on SPORTO: 

AYO = RXO; {the contents of SPORTO receive register} 

{is transferred to AYO} 

Because the SPORTs are interrupt driven, these instructions would 
typically be executed within a interrupt service routine in response to a 
SPORT interrupt. 


5.4 SPORT ENABLE 

SPORTs are enabled through bits in the system control register. This 
register is mapped to data memory address 0x3FFF. Bit 12 enables 
SPORTO if it is a 1, and bit 11 enables SPORT1 if it is a 1. Both of these bits 
are cleared at reset, disabling both SPORTs. 

Bit 10 of the system control register determines the configuration of 
SPORT1, either as a serial port or as interrupts and flags, according to 
Table 5.4 on the next page. If bit 10 is a 1, SPORT1 operates as a serial port; 
if it is a 0, the alternate functions are in effect (and bit 11 is ignored). At 
reset, bit 10 is a 1, so SPORT1 functions as a serial port. 

System Control Register 
0x3FFF 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


L SPORT1 Configure 

1 = serial port, 0 = FI, FO, IRQ0, IRQ1, SCLK 

SPORT1 Enable 

1 = enabled, 0 = disabled 

SPORTO Enable 

1 = enabled, 0 = disabled 

Figure 5.2 SPORT Enables In The System Control Register 


5-7 




Pin Name Alternate Name 


Alternate Function 


RFS1 

IKQU 

TFS1 

IRQ! 

DR1 

FI 

DTI 

FO 

SCLK1 

Same 


External interrupt 0 
External interrupt 1 
Flag input 
Flag output 
Same 


Table 5.4 SP0RT1 Alternate Configuration 


5.5 SERIAL CLOCKS 

Each SPORT operates on its own serial clock signal. The serial clock 
(SCLK) can be internally generated or received from an external source. 

The ISCLK bit, bit 14 in either the SPORTO or SPORT1 control register, 
determines the SCLK source for the SPORT. If this bit is a 1, the processor 
generates the SCLK signal; if it is a 0, the processor expects to receive an 
external clock signal on SCLK. At reset, ISCLK is cleared, so both serial 
ports are in the external clock mode. When ISCLK is set, internal 
generation of the SCLK signal begins on the next instruction cycle, 
whether or not the corresponding SPORT is enabled. 

External serial clock frequencies may be as high as the processor's cycle 
rate, up to a maximum of 13.824 MHz; internal clock frequencies may be 
as high as one-half the processor's clock rate. The frequency of an 
internally generated clock is a function of the processor clock frequency 
(as seen at the CLKOUT pin) and the value of the 16-bit serial clock divide 
modulus register SCLKDIV (0x3FF5 for SPORTO and 0x3FFl for SPORT1). 

SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


ISCLK 0 = External (Default) 

1 = Internal 

Figure 5.3 ISCLK Bit In SPORT Control Register 





CLKOUT frequency 

SCLK frequency = 

2 x (SCLKDIV + 1) 


Table 5.5 shows how some common SCLK frequencies correspond to 
values of SCLKDIV. 


SCLKDIV 

SCLK Frequency 

20479 

300 Hz 

5119 

1200 Hz 

639 

9600 Hz 

95 

64 kHz 

3 

1.536 MHz 

2 

2.048 MHz 

0 

6.144 MHz 


(Assumes CLKOUT frequency of 12.288 MHz) 

Table 5.5 Common Serial Clock Frequencies (Internally Generated) 

If the value of SCLKDIV is changed while the internal serial clock is 
enabled, the change in SCLK frequency takes effect at the start of the next 
rising edge of SCLK. 

Note that the serial clock of SPORT1 (the SCLK pin) still functions when 
the port is being used in its alternate configuration (as FO, FI and two 
interrupts). In this case, SCLK is unresponsive to an external clock, but can 
internally generate a clock signal as described above. 


5.6 WORD LENGTH 

Each SPORT independently handles words of 3 to 16 bits. The data is 
right-justified in the SPORT data registers if it is fewer than 16 bits long. 
The serial word length (SLEN) field in each SPORT control register 
determines the word length according to this formula: 

Serial Word Length = SLEN + 1 

For example, if you are using 8-bit serial words, set SLEN to 7 (0111 
binary). The SLEN field is bits 3-0 in the SPORT control register (0x3FF6 
for SPORTO and 0x3FF2 for SPORT1). See Figure 5.4 on the next page. 

Do not set SLEN to zero or one; these SLEN values are not permitted. 


5-9 





SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 1 

0 

iiii 


~ 

mm 

1111 





m 

jliiililiij; 



i i i 

1 1 1 


SLEN (Serial Word Length - 1) 

Figure 5.4 SLEN Field in SPORT Control Register 

5.7 WORD FRAMING OPTIONS 

Framing signals identify the beginning of each serial word transfer. The 
SPORTs have many ways of handling framing signals. Transmit and 
receive framing are independent of each other. All frame sync signals are 
sampled on the falling edge of the serial clock (SCLK). 

5.7.1 Frame Synchronization 

Word framing signals are optional. If the receive frame sync required 
(RFSR) or transmit frame sync required (TFSR) bit in the SPORT control 
register is a 0, a frame sync signal is necessary to initiate communications 
but is ignored after the first bit is transferred. Words are then transferred 
continuously, unframed. If the RFSR or TFSR bit is a 1, a frame sync signal 
is required at the start of every data word. 

SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

I 





$£$$§ 

Silll : 

111 



Si-Sx-xi 

• 

• •• 

III 

"1 


□ 


TFSR 0= Transmit Frame Sync Required 1st Word 

1= Transmit Frame Sync Required Every Word 

RFSR 0= Receive Frame Sync Required 1st Word 

1= Receive Frame Sync Required Every Word 


Figure 5.5 TFSR And RFSR Bits in SPORT Control Register 




The RFSR bit is bit 13 in the SPORT control register (0x3FF6 for SPORTO 
and 0x3FF2 for SPORT1), and the TFSR bit is bit 11. These bits are both 
cleared at reset, so that communication in both directions on both serial 
ports is unframed. 

See "Configuration Examples" later in this chapter for examples of frame 
sync timing. 

5.7.2 Frame Sync Signal Source 

The processor can generate frame synchronization signals internally or 
receive them from an external source. The sources for transmit frame 
syncs and receive frames syncs can be set independently. If the internal 
receive frame sync (IRFS) bit or internal transmit frame sync (ITFS) bit in 
the SPORT control register is a 0, the processor expects to receive a signal 
on its frame sync pin (RFS or TFS). If the IRFS or ITFS bit is a 1, the 
processor generates its own frame sync signal and drives the RFS or TFS 
pin as an output. 

The IRFS bit is bit 8 in the SPORT control register (0x3FF6 for SPORTO and 
0x3FF2 for SPORT1), and the ITFS bit is bit 9. Both of these bits are cleared 
at reset, that is, both serial ports require externally generated frame sync 
signals for both transmitting and receiving data. 

SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



1= Internal RFS (Output) 

ITFS 0= External TFS (Input) 

Is Internal TFS (Output) 

Figure 5.6 ITFS And IRFS Bits In SPORT Control Register 


5-11 



If frame sync signals are generated externally, then RFS and TFS are 
inputs, and the external source controls data transmission and reception. 
The SPORT will wait for a transmit frame sync before transmitting data 
and for a receive frame sync before receiving data. If frame sync signals 
are generated internally, however, then RFS and TFS are outputs, and the 
processor controls the timing of data operations. 

The SPORT outputs an internally generated transmit framing signal after 
data is loaded into the transmit (TXO or TX1) register, at the time needed 
to ensure continuous data transmission, after the last bit of the current 
word is transmitted (the exact time depends on the framing mode being 
used; see "Normal and Alternate Framing Modes," the next section). The 
occurrence of the transmit frame sync is a result of the availability of data 
in the transmit register. 

With an internally generated receive framing signal, the processor controls 
the timing of the receive data. The external data source must provide data 
to the serial port synchronized to the receive framing signal (the timing 
depends on the framing mode being used; see "Normal and Alternate 
Framing Modes," the next section). The processor generates RFS 
periodically on a multiple of SCLK cycles, based on the value of the 16-bit 
receive frame sync divide modulus register, RFSDIV (0x3FF4 for SPORTO 
and 0x3FF0 for SPORT1): 


Number of SCLK cycles between RFS assertions = RFSDIV + 1 


For example, to allow 256 SCLK cycles between RFS assertions, set 
RFSDIV to 255 (OxFF). 

Values of RFSDIV+1 that are less than the word length are not 
recommended. 

Note that frame sync signals may be generated internally even when 
SCLK is supplied externally. This provides a way to divide external clocks 
for any purpose. 

You can also use one frame sync to generate a single signal for both 
transmit and receive data. For example, an internally generated RFS 
(output) could be connected to an externally generated TFS (input) on the 
same SPORT for simultaneous transmit and receive operations. This 
interconnection is especially useful for combo codec interfaces. 


5-12 




5.7.3 Normal And Alternate Framing Modes 

In the normal framing mode, the framing signal is checked at the falling 
edge of SCLK. If the framing signal is asserted, received data is latched on 
the next falling edge of SCLK and transmitted data is driven on the next 
rising edge of SCLK. The framing signal is not checked again until the 
word has been transmitted or received. If data transmission or reception is 
continuous, i.e., the last bit of one word is followed without a break by the 
first bit of the next word, then the framing signal should occur in the same 
SCLK cycle as the last bit of each word. 

In the alternate framing mode, the framing signal should be asserted in 
the same SCLK cycle as the first bit of a word. Received data bits are 
latched on the falling edge of SCLK and transmitted bits are driven on the 
rising edge of SCLK, but the framing signal is checked only on the first bit. 
Internally generated frame sync signals remain asserted for the length of 
the serial word. Externally generated frame sync signals are only checked 
during the first bit time. 

Framing modes for receiving and transmitting data are independent. If the 
receive frame sync width (RFSW) bit or transmit frame sync width (TFSW) 
bit in the SPORT control register is a 0, normal framing is enabled. If the 
RFSW or TFSW bit is a 1, alternate framing is used. The RFSW bit is bit 12 
in the SPORT control register (0x3FF6 for SPORTO and 0x3FF2 for 
SPORT1), and the TFSW bit is bit 10. These bits are both cleared at reset, so 
that normal framing in both directions is enabled. 

SPORTO Control Register: 0x3FF6 

SPORT1 Control Register: 0x3FF2 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 





ill 

mil 


-: I.;:;:-..':::'-.- 

Plfi 

• 

•Xv:§:$£& 


iilli: 

SI 

> 

... • ’ 

msam 

; 

■Illll 

an 

i 1 


TFSW 0=Normal Transmit Framing 
1=Alternate Transmit Framing 

RFSW 0=Normal Receive Framing 
1=Aiternate Receive Framing 


Figure 5.7 TFSW And RFSW Bits In SPORT Control Register 


5-13 





For examples of normal and alternate framing, see "Configuration 
Examples" later in this chapter. 

5.7.4 Active High Or Active Low 

Framing sync signals for receiving and transmitting data can be either 
active high or active low and are configured independently. If the invert 
RFS (INVRFS) bit or invert TFS (INVTFS) bit in the SPORT control register 
is a 0, the corresponding frame sync signal is active high. If the INVRFS or 
INVTFS bit is a 1, the frame sync signal is active low. These controls apply 
regardless of the source of frame sync signals; they either control the 
polarity of internally generated signals or determine how externally 
generated signals are interpreted. 

The INVRFS bit is bit 6 in the SPORT control register (0x3FF6 for SPORTO 
and 0x3FF2 for SPORT1), and the INVTFS bit is bit 7. These bits are both 
cleared at reset, so that frame sync signals are active high. 

SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



1 — INVRFS 0=Active High RFS 
1=Active Low RFS 

INVTFS 0=Active High TFS 

1=Active Low TFS 

Figure 5.8 INVTFS And INVRFS Bits In SPORT Control Register 


5-14 




5.8 CONFIGURATION EXAMPLE 

The example code that follows illustrates how to configure the SPORTs. 
This example configures both SPORTO and SPORT1. SPORTO is 
configured for an internally generated serial clock (SCLK), internally 
generated frame synchronization, and |i-law companded 8-bit data. This is 
a typical setup for communication with a combo codec. SPORT1 is 
configured for an externally generated serial clock, externally generated 
frame synchronization, non-companded 16-bit data and autobuffering. 
This setup could be used to transfer data between processors in a 
multiprocessor system. 

Only the needed memory mapped registers are initialized. Notice that the 
SPORTs are configured before they are enabled and that any extraneous 
latched interrupts are cleared before interrupts are enabled. 


{ — SPORT INITIALIZATION CODE — } 

{ SPORTl inits } 

AXO = 0x0017; 

DM ( 0x3 FEF ) = AXO; {enable SPORTl autobuffering} 

{TX autobuffer uses 10 and MO} 

{RX autobuffer uses II and Ml} 

AXO = 0x2 8 OF; 

DM(0x3FF2) = AXO; {external serial clock, RFS and TFS} 

{RFS and TFS are required, normal} 
{framing, no companding and 16 bits} 

{SPORTO inits} 

{Assumes a CLKIN of 12.288 MHz. Internally generated} 

{SCLK will be 2.048 MHz, and framing sync of 8 kHz} 

AXO = 255; 

DM ( 0x3 FF4 ) = AXO; {RFSDIV = 256, 256 SCLKs between} 

{frame syncs: 8 kHz framing} 

AXO = 2; 

DM ( 0x3 FF5 ) = AXO; {SCLK = 2.048 MHz} 

(continued on next page) 


5-15 



(continued from previous page) 


AXO = 0x6B27 ; 

DM { 0x3FF6 ) = AXO; 

{internal SCLK, RFS and TFS} 

{normal framing, mu-law companding} 

{8 bit words} 

{SPORT ENABLE} 


IFC = OxlE ; 

ICNTL = 0; 

{clear any extraneous SPORT interrupts} 
{interrupt nesting disabled} 

AXO = OxlClF; 

DM ( 0x3 FFF) = AXO; 

{both SPORTs enabled, BWAIT and} 

{ PWAIT left as default} 

IMASK = OxlE; 

{SPORT interrupts are enabled} 

{ — END SPORT INITIALIZATIONS — } 


Figure 5.9 Example SPORT Configuration Code 


5.9 TIMING EXAMPLES 

This section contains examples of some combinations of the various 
framing options. The timing diagrams show relationships between 
signals, but are not scaled to show the actual timing parameters of the 
processor. Consult the data sheet for actual timing parameters and values. 

The examples assume a word length of four bits, that is, SLEN = 3. 
Framing signals are active high, that is, INVRFS = 0 and INVTFS = 0. 

The value of the SPORT control register (0x3FF6 for SPORTO and 0x3FF2 
for SPORT1) is shown for each example. In these binary values, 1= high, 0 
= low, and X can be either. The underlined bit values are the bits which 
set the modes illustrated in the example. 

Figures 5.10 to 5.15 show framing for receiving data. In Figures 5.10 and 
5.11, the normal framing mode is shown for noncontinuous data (any 
number of SCLK cycles between words) and continuous data (no SCLK 
cycles between words). Figures 5.12 and 5.13 show noncontinuous and 
continuous receiving in the alternate framing mode. In these four figures, 
both the input timing requirement for an externally generated frame sync 
and the output timing characteristic of an internally generated frame sync 
are shown. Note that the output meets the input timing requirement; thus, 
on processors with two SPORTs, one SPORT could provide RFS for the 
other. 






SPORT Control Register: 

Internal Frame Sync 0X10 XXXI XOXX 0011 
External Frame Sync 0X10 XXXO XOXX 001 1 

Both Internal Framing Option and External Framing Option Shown 

Figure 5.10 SPORT Receive, Normal Framing 


SCLK 



RFS 


RFS 


OUTPUT / — V 


J V 


J V 


INPUT 




DR 



SPORT Control Register: 

Internal Frame Sync 0X10 XXXI XOXX 0011 
External Frame Sync 0X10 XXXO XOXX 001 1 

Both Internal Framing Option and External Framing Option Shown 

Figure 5.11 SPORT Continuous Receive, Normal Framing 


5-17 


SCLK 


RFS 


OUTPUT 


\ 


RFS 


INPUT 


r 


mmmmsmm 


r 


mmmmsmm 


DR 



SPORT Control Register: 

Internal Frame Sync 0XH XXXI XOXX 001 1 
External Frame Sync OXU XXXO XOXX 001 1 

Both Internal Framing Option and External Framing Option Shown 

Figure 5.12 SPORT Receive, Alternate Framing 



SPORT Control Register: 

Internal Frame Sync 0X11 XXXI XOXX 001 1 

External Frame Sync OXU XXXO XOXX 001 1 

Both Internal Framing Option and External Framing Option Shown 

Figure 5.13 SPORT Continuous Receive, Alternate Framing 


5-18 



Figures 5.14 and 5.15 show the receive operation with normal framing and 
alternate framing, respectively, in the unframed mode. There is a single 
the frame sync signal that occurs only at the start of the first word, either 
one SCLK before the first bit (normal) or at the same time as the first bit 
(alternate). This mode is appropriate for multiword bursts (continuous 
reception). 


SCLK 

RFS 





DR 



SPORT Control Register: 

Internal Frame Sync 0X00 XXXI XQXX 001 1 
External Frame Sync 0X00 XXXO XOXX 001 1 

Figure 5.14 SPORT Receive, Unframed Mode, Normal Framing 


SCLK 

RFS 



j msmmwmmmsmmmmm 



SPORT Control Register: 

Internal Frame Sync 0X01 XXXI XOXX 001 1 
External Frame Sync 0X01 XXXO XQXX 001 1 

Figure 5.15 SPORT Receive, Unframed Mode, Alternate Framing 


5-19 



Figures 5.16 to 5.21 show framing for transmitting data and are very 
similar to Figures 5.10 to 5.15. In Figures 5.16 and 5.17, the normal framing 
mode is shown for noncontinuous data and continuous data. Figures 5.18 
and 5.19 show noncontinuous and continuous transmission in the 
alternate framing mode. As with receive timing, the TFS output meets the 
TFS input timing requirement. 


SCLK 


TFS 


OUTPUT 


TFS 


INPUT 


7 \ 




j — \ 




DT ( B3 |[~ B2 ]( B1 BO ) ( B3 K B2 ]( B1 ]{ BO 

SPORT Control Register: 

Internal Frame Sync OXXX 101 X OXXX 001 1 
External Frame Sync OXXX 100X OXXX 001 1 

Both Internal Framing Option and External Framing Option Shown 

Figure 5.16 SPORT Transmit, Normal Framing 


SCLK 


TFS 


TFS 


OUTPUT / \ 


7 V 


7 V 


INPUT 




DT 


^ 63 y B2 B1 y BO X 83 X B2 X B1 X 80 )( B3 )( B2 


SPORT Control Register: 

Internal Frame Sync OXXX 101X OXXX 0011 
External Frame Sync OXXX 100 X OXXX 0011 

Both Internal Framing Option and External Framing Option Shown 

Figure 5.17 SPORT Continuous Transmit, Normal Framing 


5-20 



SCLK 



SPORT Control Register: 

Internal Frame Sync OXXX 111X OXXX 0011 
External Frame Sync OXXX 110X OXXX 0011 

Both Internal Framing Option and External Framing Option Shown 

Note: There is an asynchronous delay between TFS input and DT. See the appropriate 

data sheet for specifications. 

Figure 5.18 SPORT Transmit, Alternate Framing 



SPORT Control Register: 

Internal Frame Sync OXXX 111X OXXX 001 1 
External Frame Sync OXXX 110X OXXX 001 1 

Both Internal Framing Option and External Framing Option Shown 

Note: There is an asynchronous delay between TFS input and DT. See the appropriate 

data sheet for specifications. 

Figure 5.19 SPORT Continuous Transmit, Alternate Framing 


5-21 



Figures 5.20 and 5.21 show the transmit operation with normal framing 
and alternate framing, respectively, in the unframed mode. There is a 
single the frame sync signal that occurs only at the start of the first word, 
either one SCLK before the first bit (normal) or at the same time as the first 
bit (alternate). 


SCLK 

TFS 





DT 


■ ( B3 % B2 )( B1 )( BO )( B3 B2 X B1 X" 60 X 63 K B2 


SPORT Control Register: 

Internal Frame Sync OXXX 001X OXXX 001 1 
External Frame Sync OXXX OOOX OXXX 0011 

Figure 5.20 SPORT Transmit, Unframed Mode, Normal Framing 


SCLK 

TFS 

DT 



r~ 

- ( B3 




k 12 x ■» x~=~x ° 3 r 5 x 81 x ■■ x ° 3 r E 


SPORT Control Register: 

Internal Frame Sync OXXX 011 X OXXX 0011 
External Frame Sync OXXX OlOX OXXX 001 1 

Note: There is an asynchronous delay between TFS input and DT. See the appropriate 
data sheet for specifications. 

Figure 5.21 SPORT Transmit, Unframed Mode, Alternate Framing 


5-22 


5.1 0 COMPANDING AND DATA FORMAT 

Companding (a contraction of COMpressing and exPANDing) is the 
process of logarithmically encoding and decoding data to minimize the 
number of bits that must be sent. Both SPORTs share the companding 
hardware; one expansion and one compression operation can occur in 
each processor cycle. In the event of contention, SPORTO has priority. 

The ADSP-2100 family of processors supports both of the widely used 
algorithms for companding: A-law and (i-law. The processor compands 
data according to the CCITT G.711 recommendation. The type of 
companding can be selected independently for each SPORT. 

If companding is not enabled, there are two formats available for received 
data words of fewer than 16 bits: one that fills unused MSBs with zeros, 
and another that sign-extends the MSB into the unused bits. 

The type of companding, as well as the non-companding data format, are 
controlled by the DTYPE field (bits 5-4) in the SPORT control register 
(0x3FF6 for SPORTO and 0x3FF2 for SPORT1) as shown in Figure 5.22. 


SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


DTYPE 00=Right justify, zero fill unused MSBs 

01=Right justify, sign extend into unused MSBs 
10=Compand using u-law 
11=Compand using A-law 

Figure 5.22 DTYPE Field In SPORT Control Register 


5-23 




When companding is enabled, valid data in the RXO or RX1 register is the 
right-justified, sign-extended, expanded value of the eight LSBs received. 
Likewise, a write to TXO or TX1 causes the 16-bit value to be compressed 
to eight LSBs (sign-extended to the width of the transmit word) before 
being written to the internal transmit register. If the magnitude of the 16- 
bit value is greater than the 13-bit A-law or 14-bit p-law maximum, the 
value is automatically compressed to the maximum positive or negative 
value. 

5.10.1 Companding Operation Example 

With hardware companding, interfacing to a codec requires little 
additional programming effort. See the codec hardware interfacing 
example in the last section of this chapter. 

Here is a typical sequence of operations for transmitting companded data: 

• Write data to the TXn register 

• The value in TXn is compressed 

• The compressed value is written back to TXn 

• After the frame sync signal has occurred (if required), TXn is written to 
the internal transmit register and the bits are sent, MSB first. 

As soon as the SPORT has started to send the second bit of the current 
word, TXn can be written with the next word, even though transmission 
of the first is not complete. After the MSB has been transferred, the SPORT 
generates the transmit interrupt to indicate that TXn is ready for the next 
data word. If the framing signal is being provided externally, the next 
word must be written to TXn early enough to allow for compression 
before the next framing signal arrives. 

Here is a typical sequence of operations for receiving companded data: 

• Bits accumulate as received in the internal receive register 

• When a complete word is received, it is written to RXn 

• The value in RXn is expanded 

• The expanded value is written back to RXn 

The receive interrupt for that SPORT is then generated. 


5-24 



5.10.2 Contention For Companding Hardware 

Since both SPORTs share the companding hardware, only one 
compression and one expansion operation can take place during a single 
machine cycle. If contention arises, such as when two expansions need to 
occur in the same cycle, SPORTO has priority, while SPORT1 is forced to 
wait one cycle. 

The effects of contention, however, are usually small. The instruction set 
does not support loading both TXO and TX1 in the same cycle; 
consequently these operations will be naturally out of phase for 
contention in many cases. The overhead cycle for the receive operation 
occurs prior to the receive interrupt and does not increase the time needed 
to service the interrupt, although it does affect the latency prior to 
receiving the interrupt. 

5.10.3 Companding internal Data 

Because the values in the RX and TX registers are actually companded "in 
place" it is possible to use the companding hardware internally, without 
any transmission or reception at all and without enabling the serial port. 
This operation can be used for debugging or data conversion and requires 
a single cycle of overhead. 

To compress data, enable companding and then: 

1. Write data to TXn (compression is calculated). 

2. Wait for one cycle (TXn is written with compressed value) 

3. Read TXn (it returns the 8-bit compressed data) 

The code might look like this: 

TXO = AXO; {linear data written to transmit register} 

NOP; {any instruction} 

AXl = TXO; {compressed data transferred to AX1} 

Use the same procedure to expand data, but use RXn instead of TXn. 

RXO = AXO; {compressed data written to receive register} 

NOP; {any instruction} 

AXl = RXO; {expanded - linear value transferred to AXl} 



5.11 AutoBuffering 

In normal operation, a SPORT generates an interrupt when it has received 
or has started to transmit a data word. Autobuffering provides a 
mechanism for receiving or transmitting an entire block of serial data 
before an interrupt is generated. Service routines can operate on the entire 
block of data, rather than on a single word, reducing overhead 
significantly. Autobuffering is available on both SPORTO and SPORT1, 
except on the ADSP-21msp58/59 which autobuffers only on SPORTO. 

Autobuffering uses the circular buffer addressing capability of the DAGs. 
With autobuffering enabled, each serial data word is transferred (or if 
multichannel operation is enabled, each active word is transferred) to or 
from data memory in a single overhead cycle. (Autobuffering to program 
memory is not supported.) This overhead cycle occurs independently of 
the instructions being executed and effectively suspends execution for one 
cycle (or more, if wait states are required) when it happens. No interrupt 
is generated for these individual data word transfers. 

The autobuffer transfer cannot be duplicated by any instruction. However, 
an equivalent assembly language instruction would be: 

DM ( I , M ) = RXO 

or Equivalent Instructions Only 

TXO = DM ( I , M) 

The I and M registers used in the transfer are selected by fields in the 
SPORT's autobuffer control register. 

The processor waits for the current instruction to finish before inserting 
the overhead cycle. A delay in the autobuffer transfer occurs if the transfer 
is required during an instruction executing in multiple cycles (for wait 
states, for example). If the transfer is required when the processor is 
waiting in an IDLE state, the transfer is executed and the processor returns 
to IDLE. 

When a data word transfer causes the circular buffer pointer to wrap 
around, the SPORT interrupt is generated. The receive interrupt occurs 
after the complete buffer has been received. The transmit interrupt occurs 
when the last word is loaded into TXn, prior to transmission. 

Aside from the completion of an instruction requiring multiple cycles, the 
automatic transfer of individual data words has the highest priority of any 
operation short of RESET, including all interrupts. Thus, it is possible for 



an autobuffer transfer to increase the latency of an interrupt response if 
the interrupt happens to coincide with the transfer. Up to four 
autobuffered transfers can occur; in the case that two or more are needed 
in the same cycle, they have the following priority, which is the same as 
the SPORT interrupt priority: 

Highest SPORTO Transmit 

SPORTO Receive 
SPORT1 Transmit 
Lowest SPORT1 Receive 

In the worst case that all four autobuffer transfers are required at about 
the same time, interrupt latency would increase by the time it takes for all 
the transfers to occur, which is affected by wait states and bus request. 

5.11.1 Autobuffering Control Register 

In autobuffering mode, an interrupt is generated when the modification of 
a specified I register (in the DAG) by the value in the specified M register 
(in the DAG) causes a modulus overflow (pointer wraparound). This 
means that the end of the buffer has been detected. 

The autobuffering mode is enabled separately for receiving and 
transmitting by bits in the SPORT's autobuffer control register (0x3FF3 for 
SPORTO or 0x3FEF for SPORT1), shown in Figure 5.23. 

SPORTO Autobuffer Control Register: 0x3FF3 
SPORT1 Autobuffer Control Register: 0x3FEF 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

\ '• : I- I • •• "I- I ' ' 1 ' 1 ' ' 1 1 1 1 1 


■ ■ i i i ■ ■ 



TIREG TMREG RIREG RMREG 1 

TBUF 

(Transmit Autobuffering Enable) 

RBUF 

(Receive Autobuffering Enable) 


Figure 5.23 SPORT Autobuffer Control Register 




The I and M registers used for autobuffering are identified by fields in the 
autobuffer control register. TIREG and TMREG are binary values that 
indicate the numbers of the I and M registers, respectively, associated with 
the transmit buffer. The rules governing the pairing of I and M registers 
are the same as for other DAG operations: the I and M registers must be in 
the same DAG, numbered either 0-3 for DAG1 or 4-7 for DAG2. 
Consequently, three bits identify the I register, but only two bits are 
necessary to indicate the M register because the third bit (MSB) of the M 
register number must be the same as for the I register. 

Likewise, RIREG and RMREG indicate the numbers of the I and M 
registers, respectively, associated with the receive buffer. 

The TBUF and RBUF bits enable transmit autobuffering and receive 
autobuffering, respectively. These bits are cleared to zeros at reset and 
after a reboot. Consequently, autobuffering in progress cannot continue 
through a reboot operation; you must re-enable autobuffering after a 
reboot. 

5.11.2 Autobuffering Example 

The code shown below is an example that sets up SPORT1 for 
autobuffering operation. The code assumes that the processor is driven 
with a clock frequency of 12.288 MHz. The SPORT will automatically 
transmit values from the circular buffer named txjbuffer. It will receive 
values as they are sent to the SPORT and automatically transfer the data 
into the buffer named rxjbuffer. A transmit interrupt will be generated 
once all of the txjbuffer values have been transferred to TX1, but before the 
last value has been loaded into the transmit shift register. A receive 
interrupt will be generated once the rxjbuffer has been completely filled. 


. MODULE/RAM code_to_init_AB_SPORTl ; 


{ — Initialization code for autobuffer — } 


. VAR/DM/CIRC 
. VAR/DM/CIRC 
. ENTRY 


tx_buf fer [10] ; 
rx_buf fer [10] ; 
sportl_inits; 


(set up I , M, and L registers) 



sportl_inits : 10 = A tx_buffer; {10 contains address of tx_buffer} 

MO = 1; {fill every location} 

L0 = %tx_buffer; {L0 set to length of tx_buffer} 

II = ''rx-buffer; {II points to rx_buffer} 

LI = %rx_buffer; {Ll set to length of rx_buffer} 

{set up SPORT1 for autobuffering} 

AXO = 0x0013; {TX uses 10, MO; RX uses 11, MO} 

DM ( 0x3 FEF) = AXO; {autobuffering enabled} 

{set up SPORT1 for 8 kHz sampling and 2.048 MHz SCLK} 

AXO = 255; {set RFSDIV to 255 for 8 kHz} 

DM ( 0x3 FF0 ) = AXO; 

AXO = 2; {set SCLKDIV to 2 for 2.048 MHz SCLK} 

DM ( 0x3 FF5 ) = AXO; 

{set up SPORT1 for normal required framing, internal SCLK} 
{internal generated framing} 

AXO = 0x6B27; {normal framing, 8 bit mu-law} 

DM(0x3FF2) = AXO; {internal clock, framing} 

{set up interrupts} 

IFC = 6; {clear any extraneous SPORT interrupts} 
ICNTL = 0; {interrupt nesting disabled} 

IMASK = 6; {enable SPORTl interrupts} 

{enable SPORTl} 

AXO = OxOCIF; {enable SPORTl leave PWAIT, } 

DM ( 0x3 FFF) = AXO; {BWAIT as default} 

{Place first transfer value into TXl} 

AXO = DM (10, M0 ) ; 

TXl = AXO; 

RTS; 

.ENDMOD; 

Figure 5.24 Autobuffering Example Configuration Code 


5-29 




5.12 MULTICHANNEL FUNCTION 

SPORTO supports a multichannel function. In the multichannel mode of 
operation, serial data is time-division multiplexed. Each subsequent word 
belongs to the next consecutive channel so that, for example, a 24-word 
block of data contains one word for each of 24 channels. SPORTO supports 
32 or 24 channels and can automatically select words for particular 
channels while ignoring the others. 

In single-channel mode, receive and transmit framing identifies the start 
of a single word or continuous stream, with independent receive and 
transmit operation. In the multichannel mode, the receive frame sync 
signal (RFSO) identifies the start of a 24- or 32-word block of serial data 
with the receiver and transmitter operating in parallel. TFSO has an 
alternate function, described below. Note: The ADSP-2105 has only one 
serial port (SPORT1) and does not support multichannel operation. 

5.12.1 Multichannel Setup 

Multichannel operation is enabled by bit 15 in SPORTO's control register 
(0x3FF6). When this bit is a 1, multichannel mode is enabled, and some 
control bits in the SPORTO control register are redefined. Bits affected by 
multichannel mode are shown in Figure 5.25. At reset, bit 15 is cleared, 
disabling multichannel mode and enabling normal operation. 

SPORTO Control Register (Multichannel Version) 

0x3FF6 


15 14 

13 12 11 10 

9 

8 

7 6 

5 4 

3 

2 

1 

0 

1 

il#; 

1 1 1 

1 1 1 


j 

II 






■ 


INVTDV (Invert Transmit Data Valid) 

MCL (Multichannel Length) 

0 = 24 Words 

1 = 32 Words 


Figure 5.25 SPORTO Control Register With Multichannel Mode Enabled 



MFD 

(Multichannel 
Frame Delay) 


MCE 

(Multichannel Enable) 

1 = Multichannel Operation 


5-30 





The state of the multichannel length bit MCL, bit 9, determines whether 
there are 24 or 32 channels, i.e. whether the block length is 24 or 32 words. 
A 0 selects 24-word blocks; a 1, 32-word blocks. In multichannel mode, the 
word length is still set by the SLEN field in the SPORT control register and 
can be 3 to 16 bits. 


The multichannel frame delay (MFD) is a 4-bit field specifying (in binary) 
the number of serial clock cycles between the frame sync signal and the 
first data bit. This allows the processor to work with different types of T1 
interface devices. Figure 5.26 shows a variety of delays. 


SCLK 
First Bit 


RFS MFD=9 


RFS MFD=8 


RFS MFD=7 


RFS MFD=6 


■<ZZ>- 


r\ 


_r\ 


r\ 


r\ 


RFS MFD=5 


J~\ 


RFS MFD=1 


J—\ 


RFS MFD=0 


r\ 


Figure 5.26 SPORT Multichannel Frame Delay Examples 

The memory-mapped receive enable register and transmit enable register 
are each 32 bits wide and made up of two contiguous sixteen-bit registers, 
as shown in Figure 5.27, which can be found on the next page. Each bit 
corresponds to a channel; setting the bit enables that channel so that the 
processor will select its word from the 24- or 32-word block. For example, 
setting bit 0 selects word 0, bit 12 selects word 12, and so on. 


5-31 



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 










I 









15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
















□ 


0x3FFA 

Receive 

Word 

Enables 

0x3FF9 


1 = Channel Enabled 
0 = Channel Ignored 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 

















□ 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
















□ 


Figure 5.27 SPORTO Multichannel Word Enable Registers 


0x3FF8 


0x3FF7 


Transmit 

Word 

Enables 


5.12.2 Multichannel Operation 

Received words for channels that are not enabled are ignored; that is, no 
interrupts are generated for these words, no autobuffering occurs and no 
data is written to the RXO register. Likewise, there are no interrupts and 
no autobuffering for transmit words that are not enabled. During transmit 
word time slots for channels that are not enabled, the data transmit (DT) 
pin is tristated. 


Most aspects of SPORTO operate normally in the multichannel mode. 
Specifically, word length (SLEN), internal or external framing (IRFS), 
frame signal inversion (INVRFS), companding (DTYPE) and 
autobuffering are unchanged in the multichannel mode. Note: It is 
important that RFS does not occur more than once per frame in 
multichannel mode. 


Instead of providing frame synchronization, the TFSO signal functions as a 
transmit data valid (TDV) signal in multichannel mode. TDV is asserted 
while the transmitter is active. TDV can be active high or low, and its 
polarity is controlled by the INVTFS bit, renamed INVTDV in this context. 
If INVTDV is a 1, TDV is active low; otherwise it is active high. TDV can 
be used to enable additional buffer logic, if required. 

Figure 5.28 shows the start of a multichannel transfer. As in earlier 
examples, word length is four bits (SLEN=3) and frame sync signals are 
active high. Multichannel frame delay (MFD) is one SCLK cycle. For the 
purpose of illustration, words 0 and 2 are selected for receiving and words 
1 and 2 are selected for transmission. 


5-32 




WORDO 


WORD 1 


WORD 2 



Figure 5.28 Start Of Multichannel Transfer 


Figure 5.29 shows a complete 24-word block in the multichannel mode, 
with complete words represented in the waveforms instead of individual 
bits. Receiving is active for all words and transmitting is active for words 
0-3, 8-11 and 16-19 only. 

Note: The ADSP-2105 has only one serial port (SPORT1) and does not 
support multichannel operation. 



5-33 



5.1 3 SPORT TIMING CONSIDERATIONS 

The SPORTs support full duplex operation and are normally interrupt 
driven. That is, whenever a SPORT transaction has completed, the 
processor generates an internal interrupt. Under most operating 
conditions, the actual timing of the SPORT interrupts is not critical. In 
some sophisticated DSP systems, however, it is important to know the 
timing of the interrupt relative to the operation of the serial port. 

5.13.1 Companding Delay 

Use of the companding circuit introduces latency in two ways. First, 
compressing or expanding a data value takes a single processor cycle. 
Second, SPORTO has priority over SPORT1 if both require an expansion or 
compression operation in the same cycle; in this case, SPORT1 must wait 
one processor cycle. See the section on companding earlier in this chapter 
for more details on companding. 

5.13.2 Clock Synchronization Delay 

Some SPORT timings depend on the processor clock. Other timings 
depend on the serial clock (SCLKO or SCLK1). These clocks are 
asynchronous. There is a delay associated with synchronizing the serial 
clock to the processor clock whether the serial clock is internally or 
externally generated. This delay is different for the transmit and receive 
interrupts, as explained in the following sections. 

5.13.2.1 Startup Timing 

When a serial port is enabled by a write to the System Control Register, it 
takes two SCLK cycles before it is actually enabled. On the next (third) 
SCLK cycle, the serial port becomes active, looking for a frame sync. 

5.1 3.3 Internally Generarated Frame Sync Timing 

When internally generated frame syncs are used, all that is necessary to 
transmit data, from the programmer's point of view, is to move the data 
into the appropriate TX register with an instruction such as: 

TXO = AXO; 

Once data is written into the TX register, the processor generates a frame 
sync after a synchronization delay. This delay in turn affects the timing of 
the serial port transmit interrupt. The latency depends on five factors: the 
frequency of the serial clock, whether or not companding is enabled, 
whether or not there is contention for the companding circuit, whether the 
current word has finished transmitting and the logic level of the SCLK 
when the data value was loaded into the transmit register. 



(Note that if the transmit frame sync is generated externally, data starts 
transmitting when a frame sync signal is received.) 

After the TX register is loaded, it takes three complete phases of the serial 
clock, HIGH, LOW and HIGH, in that order, to ensure synchronization 
(see Figure 5.30). Once synchronization has been ensured and a frame 
sync generated, the most significant bit of the transmit word is shifted out 
on the same rising edge as the frame sync if alternate framing is used and 
on the rising edge of the next serial clock if normal framing is used. 
Therefore, the worst-case synchronization delay is two SCLK cycles. 

There is additional delay if the previous data transmission has not 
completed; the TX register cannot be loaded into the transmit shift register 
until the previous transmission is complete. 


TX Written, SCLK High 


Processor Clock 


Serial Clock 


TX Written 


MSB Transmitted MSB Transmitted 
(Alternate Framing) (Normal Framing) 




High 


High 


L 


TFS OUTPUT 
(Normal Framing) 

TFS OUTPUT 
(Alternate Framing) 


TX Written, SCLK Low 

TX Written 

Processor Clock 


MSB Transmitted MSB Transmitted 
(Alternate Framing) (Normal Framing) 



1 



1 

[ t 


Serial Clock 

High 

| Low 

High 






TFS OUTPUT 
(Normal Framing) 

TFS OUTPUT 
(Alternate Framing) 


Figure 5.30 Clock Synchronization 




5.13.4 Transmit Interrupt Timing 

Once the MSB has been transmitted, the subsequent bits are transmitted 
on the rising edges of the SCLK. The transmit interrupt (or autobuffer 
request) is generated internally on the falling edge of SCLK during the 
transmission of the second bit (see Figure 5.31 below). This timing gives 
the program time to load the TX register with the next data for continuous 
data transmission. 

The transmit interrupt, like any other interrupt, must be synchronized to 
the processor clock. Servicing is subject to the same latencies as other 
interrupts. 

The transmit interrupt essentially means that it is all right to write a value 
to the TX register. 



Interrupt or Autobuffer Request ► ij 


Figure 5.31 SPORT Interrupt or Autobuffer Timing, Transmit 4-Bit Words (No Companding) 
5.1 3.5 Receive Interrupt Timing 

The receiver portion of the SPORT latches data on the DR pin on the 
falling edges of SCLK. 

Receive interrupt timing differs from transmit interrupt timing. The 
receive interrupt or autobuffer request occurs only after an entire word is 
received. The interrupt request occurs on the rising edge of SCLK after a 
word is received (see Figure 5.32) and indicates that new data in the RX 
register can be read. 

Companding causes a delay in the same manner as for transmitting. 
However, the latency is transparent, as the receive interrupt is generated 
after the expansion has taken place. 


5-36 



RFS 



Figure 5.32 SPORT Interrupt or Autobuffer Timing, Receive 4-Bit Words (No Companding) 



The LSB is received on the falling edge of SCLK. One processor cycle 
elapses to allow synchronization to the processor clock. One processor 
cycle later, the SPORT attempts to expand the data if companding is 
enabled and the other serial port is not using the companding circuitry. 
Companding latencies as discussed above occur prior to generation of a 
receive interrupt. Servicing the receive interrupt is subject to the same 
latencies as other interrupts. 



Figure 5.33 SPORT Interrupt or Autobuffer Timing, Receive 4-Bit Words (Companding Enabled) 


5-37 



5.1 3.6 Interrupt & Autobuffer Synchronization 

The serial ports are treated as an asynchronous system to the processor, 
even if the processor is providing the serial clock. Internal to the processor 
is a circuit which synchronizes the autobuffer or interrupt requests to the 
processor clock. Figure 5.34 shows the synchronization delay for the serial 
ports, assuming the setup and hold times are met for the current processor 
cycle. The setup and hold times for the serial port requests are the same as 
shown on the data sheet for the IRQ2 signal. If the setup and hold times 
are not met, there is an additional processor cycle of delay added. 


CLKOUT 


_/ 


\ | — 1 

Request ►; 

Setup Time !;◄ ►{ 


J \ 

Processor Can ► 

Service The 
Request Here 



Hold Time 



Figure 5.34 Synchronization of Autobuffer or Interrupt Request to Processor Clock 


As shown in Figure 5.34, there is a two-processor-cycle delay before the 
autobuffer or interrupt request is acted on by the processor. The same 
latencies exist for all external interrupts. The processor can only service 
interrupt or autobuffer requests on instruction cycle boundaries, so there 
may be additional latency cycles added due to the completion of an 
instruction. 

5.13.7 Instruction Completion Latencies 

There are several situations which can cause an instruction to take more 
than one processor cycle. Any of the following can delay the processor's 
ability to service a pending interrupt or autobuffer request: 

• External memory wait states 

• Bus request when an external access is required (in go-mode) 

• Bus request with go-mode disabled 

• Multiple external accesses required for a single instruction 

• A pending higher priority autobuffer or interrupt request 

• Interrupt being masked 


5-38 




On instruction cycle boundaries the processor will service multiple 
pending interrupt or autobuffer requests in the following priority order: 

• SPORTO transmit autobuffer — highest priority (not on ADS P-2105) 

• SPORTO receive autobuffer (not on ADSP-2105) 

• SPORT1 transmit autobuffer 

• SPORT1 receive autobuffer 

• Unmasked pending interrupts in priority order 

5.1 3.8 Interrupt & Autobuffer Service Example 

Figure 5.35 shows the execution of a serial port interrupt based on a 
request that meets the setup and hold time requirements. This example is 
the same for a receive or a transmit interrupt request. 


Request ► j 

CLKOUT -I \ / \ / \ / \ f 

EXEC ( A X B X FETCH INT )( INT f 

Sync Delay ► \ 

NOP Instruction, Fetch Vector ► \ 

Execute First Instruction Of Interrupt Routine j-^ ► j 

Figure 5.35 Interrupt Service Example 

An additional latency cycle is consumed due to the fetching of the first 
instruction of the interrupt routine. The interrupt can only be serviced on an 
instruction cycle boundary. The above example (in Figure 5.35) assumes all 
instructions are completed in one processor cycle. Figure 5.36 shows the 
result of an autobuffer request that meets the setup and hold requirements. 


Request — ► \ 


CLKOUT 

EXEC 


_/ 

— c 


\ 


A 


J v_ 

J 

Sync Delay 


J 

\ AUTOBUFFER 



J 

TL 


Do The Autobuffer Transfer f- 


Continue Main Program i- 


"\ r 

i — r 


Figure 5.36 Autobuffer Service Example 


5-39 




Autobuffering only consumes the cycles necessary to perform the data 
transfer; no additional cycles are lost fetching instructions. The above 
diagram assumes that all instructions and data transfers occur in one 
processor cycle. 

5.13.9 Receive Companding Latency 

In addition to the cycles used for synchronization, there are some 
additional delays possible due to receive companding. The synchronized 
request is used by the processor to decide when to write the receive 
register with the expanded value. This can only occur on instruction cycle 
boundaries and only one receive register can be expanded at a time. On 
the ADSP-2100 family processors that have two serial ports (i.e. all except 
the ADSP-2105), there is also a possibility of a delay due to the availability 
of the companding circuitry. SPORTO has the higher priority. When 
companding is enabled, the autobuffer or interrupt request does not occur 
until the register has been expanded. The next two diagrams show 
examples of autobuffering with companding and the latencies involved. 


Request — ► \ 

CLKOUT _/ \ / \ / \ / \ r 

EXEC ( A X B X c ~X autobuffer f 

COMPAND ( EXPAND RX ) 

Sync Delay ► ; 

Expand The Receive Register j-* ►! 


Do The Autobuffer Transfer 


Figure 5.37 Receive Companding Example 


Continue Main Program i-* 


D 


5-40 



The following diagram shows the latency when there are two pending 
receive autobuffer requests with companding enabled. 


Request 

Request 

CLKOUT 


— ► j SPORTO Receive 
— ► : SPORT1 Receive 




Figure 5.38 Receive Companding Example With Both Serial Ports 


5.1 3.1 0 Interrupts With Autobuffering Enabled 

When autobuffering is enabled, SPORT interrupts occur when the address 
modification done during the autobuffer operation causes a modulus 
wraparound. The synchronization delay applies to this type of interrupt as 
well. An example is shown below in Figure 5.39: 



Figure 5.39 Autobuffering Interrupt Example 


Execute First Instruction Of Interrupt Routine — 


5-41 



5.13.11 Unusual Complications 

In most cases the serial port companding, autobuffer, and interrupt 
latencies are transparent to your application program. When trying to use 
the same I register for more than one autobuffer channel, it becomes 
important to make sure that the latencies do not effect the correct order of 
operations. For example, if the serial port data is continuous, and the 
receiver and transmitter are working with the same frame signal, the order 
of the transmit and receive autobuffer or interrupt operations may be 
affected by the latencies shown below in Figure 5.40. 



SCLK r\ 


DR X B,T3 

X 

BIT2 X 

BIT1 X B,T0 

X B i T L 

X BIT2 

XX 

XX L 

1 


DT -{ BIT3 

X 

BIT2 x 

BIT1 X BIT0 

YBIT3 

JBU2 

X BIT1 

Ybjto 



Transmit Autobuffer Request ► i 

Receive Autobuffer Request ► j 


Figure 5.40 Using One Index Register for Transmit and Receive Autobuffer 

If the processor is free to handle the autobuffer requests in the order they 
are generated, the receive autobuffer happens first and is then followed by 
the transmit autobuffer. The order of these operations may change if the 
processor is not available to handle the requests due to any of the 
previously mentioned latencies. In this case there are VA serial clock cycles 
between the requests. If the processor is subject to bus requests, wait 
states, or other latencies which are longer than VA serial clock cycles, both 
autobuffer operations may be held off. Since the transmit autobuffer has a 
higher priority, it's request will occur first. Because of the priority of the 
autobuffer requests the use of a single I register more difficult or even 
impossible in some cases. As long as there are no possible latency cases 
longer than the difference in the timing of the requests, it is quite possible 
to use a single I register for serial port autobuffering. 


5-42 



Timer 



6.1 OVERVIEW 

The programmable interval timer can generate periodic interrupts based 
on multiples of the processor's cycle time. When enabled, a 16-bit count 
register is decremented every n cycles, where n-1 is a scaling value stored 
in an 8-bit register. When the value of the count register reaches zero, an 
interrupt is generated and the count register is reloaded from a 16-bit 
period register. 

The scaling feature of the timer allows the 16-bit counter to generate 
periodic interrupts over a wide range of periods. Given a processor cycle 
time of 80 ns, the timer can generate interrupts with periods of 80 ns up to 
5.24 ms with a zero scale value. When scaling is used, time periods can 
range up to 1.34 seconds. 

Timer interrupts can be masked, cleared and forced in software if desired. 
For additional information, refer to the section "Interrupts" in Chapter 3, 
"Program Control." 


6.2 TIMER ARCHITECTURE 

The timer includes two 16-bit registers, TCOUNT and TPERIOD and one 
8-bit register, TSCALE. The extended mode control instruction enables 
and disables the timer by setting and clearing bit 5 in the mode status 
register, MSTAT. For a description of the mode control instructions, refer 
to Chapter 15, Instruction Set Reference. The timer registers, which are 
memory-mapped, are shown in Figure 6.1 (on the following page). 

TCOUNT is the count register. When the timer is enabled, it is 
decremented as often as once every instruction cycle. When the counter 
reaches zero, an interrupt is generated. TCOUNT is then reloaded from 
the TPERIOD register and the count begins again. 




0X3FFD 



15 

14 13 

12 

11 

10 

9 

8 

7 6 5 4 3 2 1 0 

C 

r i i 

i i i 

i i 

1 1 1 1 

TPERIOD 

i J i i 

i i i i i i i i i 

Period Register 

i i i i i i i i i 

i i i i i i i i i i i i i i i 

TCOUNT Counter Register 

0 

0 0 

0 

0 

0 

D 

a 

1 1 1 1 1 1 1 

TSCALE Scaling Register 
1 1 1 1 1 1 l 


Figure 6.1 Timer Registers 


0x3FFC 

0x3FFB 


TSCALE stores a scaling value that is one less than the number of cycles 
between decrements of TCOUNT. For example, if the value in TSCALE 
register is 0, the counter register decrements once every cycle. If the value 
in TSCALE is 1, the counter decrements once every 2 cycles. Figure 6.2 
shows the timer block diagram. 


DMD Bus >10 



Timer Enable 


Figure 6.2 Timer Block Diagram 


6-2 







6.3 RESOLUTION 

TSCALE provides the capability to program longer time intervals between 
interrupts, extending the range of the 16-bit TCOUNT register. Table 6.1 
shows the range and the relationship between period length and 
resolution for TPERIOD = maximum. 

Cycle Time - 80 ns 
TSCALE Interrupt Every 

0 5.24 ms 

255 1.34 s 

Table 6.1 Timer Range And Resolution 

6.4 TIMER OPERATION 

Table 6.2 shows the effect of operating the timer with TPERIOD = 5, 
TSCALE = 1 and TCOUNT = 5. After the timer is enabled (cycle n-1) the 
counter begins. Because TSCALE is 1, TCOUNT is decremented on every 
other cycle. The reloading of TCOUNT and continuation of the counting 
occurs, as shown, during the interrupt service routine. 


Cycle 

n-4 

n-3 

n-2 

TCOUNT 

Action 

TPERIOD loaded with 5 

TSCALE loaded with 1 

TCOUNT loaded with 5 

n-1 

5 

ENA TIMER executed 

n 

5 

since TSCALE = 1, no decrement 

n+1 

5 

decrement TCOUNT 

n+2 

4 

no decrement 

n+3 

4 

decrement TCOUNT 

n+4 

3 

no decrement 

n+5 

3 

decrement TCOUNT 

n+6 

2 

no decrement 

n+7 

2 

decrement TCOUNT 

n+8 

1 

no decrement 

n+9 

1 

decrement TCOUNT 

n+10 

0 

no decrement 

n+11 

0 

zero reached, interrupt occurs 
load TCOUNT from TPERIOD 

n+12 

5 

no decrement 

n+13 

5 

decrement TCOUNT 

n+14 

4 

no decrement 

n+15 

4 

decrement TCOUNT, etc.. 

Table 6.2 

Example Of Timer Operation 


Resolution 
80 ns 
20 }is 



One interrupt occurs every (TPERIOD +1) * (TSCALE +1) cycles. To set the 
first interrupt at a different time interval from subsequent interrupts, load 
TCOUNT with a different value from TPERIOD. The formula for the first 
interrupt is (TCOUNT+1) * (TSCALE+1). 

If you write a new value to TSCALE or TCOUNT, the change is effective 
immediately. If you write a new value to TPERIOD, the change does not 
take effect until after TCOUNT is reloaded. 



Host Interface Port D 7 


7.1 OVERVIEW 

The host interface port (HIP) of the ADSP-2111, ADSP-2171, and 
ADSP-21msp58/59 is a parallel I/O port that allows these processors to be 
used as memory-mapped peripherals of a host computer (i.e. slave DSP 
processors). Examples of host computers include the Intel 8051, Motorola 
68000 family, and even other ADSP-21xx processors. 

The host interface port can be thought of as an area of dual-ported 
memory, or mailbox registers, that allow communication between the host 
and the processor core of the ADSP-21xx. The host addresses the HIP as a 
segment of 8- or 16-bit words of memory. To the processor core, the HIP is 
a group of eight data-memory-mapped registers. 

Any number of ADSP-21xx processors can be used in parallel as memory- 
mapped peripherals. Assigning a different address location to each one 
allows the host to control them all. 

The operating speed of the HIP is similar to that of the processor data bus. 
A read or write operation can occur within a single instruction cycle. 
Because the HIP is normally connected with devices that are much slower 
(the 68000, for example, can take four cycles to perform a bus operation), 
the data transfer rate is usually limited by the host computer. 

The host interface port is completely asynchronous to the rest of the 
ADSP-21xx's operations. The host can write data to or read data from the 
HIP while the ADSP-21xx is operating at full speed. The HIP can be 
configured for operation on an 8-bit or 16-bit data bus and for either a 
multiplexed address /data bus or separate address and data buses. 

The ADSP-2111, ADSP-2171, and ADSP-21msp58/59 support two types of 
booting operations. One method boots from external memory (usually 
EPROM) using the boot memory interface described in the "Memory 
Interface" chapter. The other method uses the HIP to boot load a program 
from the host computer. HIP booting is described at the end of this 
chapter. 


7-1 





7.2 HIP PIN SUMMARY 

The HIP consists of 27 pins. As shown in Table 7.1, 16 of these are data 
pins and 11 are control pins. Some of the control pins have dual functions, 
allowing the processor to support different bus protocols. 

Pin Number 


Name 

of Pins 

Direction 

Function 

HSEL 

1 

Input 

HIP Select 

HACK 

1 

Output 

HIP Acknowledge 

HSIZE 

1 

Input 

HIP 8/16 Bit Host 

0=1 6-bit; l=8-bit 

BMODE 

1 

Input 

HIP Boot Mode Select 

0=normal (EPROM); 1=HIP 

HMDO 

1 

Input 

HIP Bus Strobe Select 

0=RD, WR; 1=RW, DS 

HRD/HRW " 

1 

Input 

HIP Read Strobe/ 

Read /Write Select 

HWR/HDS ' 

1 

Input 

HIP Write Strobe/ 

Host Data Strobe 

HMD1 

1 

Input 

HIP Address /Data Mode 
0=separate; l=multiplexed 

HD15-0/HAD15-0 ** 16 

Bidirectional 

HIP Data/ Address & Data 

HA2 /ALE ** 

1 

Input 

HIP Host Address 2/ 

Address Latch Enable 

HAl-O/no function 

** 2 

Input 

Host Addresses 1 & 0 


TOTAL 27 

* HMDO selects function 
** HMD1 selects function 

Table 7.1 Host Interface Port Pins 


7-2 




HSEL is a host select which allows the host to enable or disable the HIP for 
host data transfers. 

HACK is a host acknowledge output for hosts that require an 
acknowledge for handshaking. 

HSIZE configures the bus size; the HIP can function in both 8-bit and 16- 
bit modes. If the HIP is configured for an 8-bit host (HSIZE=1), data is 
read from and written to the lower eight bits of a HIP data register and the 
upper eight bits are zero-filled (on host writes) or tristated (on host reads). 

BMODE determines whether booting occurs through the HIP or through 
the memory interface pins. 

HMDO and HMD1 are mode pins that configure the address, data and 
strobe pins, as shown in Table 7.2. HMDO configures the bus strobes, 
selecting either separate read and write strobes or a single read /write 
select and a host data strobe. HMD1 configures the bus protocol, selecting 
either separate address (3-bit) and data (16-bit) buses or a multiplexed 16- 
bit address/data bus with address latch enable. The timings of each of the 
four bus protocols are described later in this chapter. 


HMD1=0 HMD1=1 


HRD 

HIP Read Strobe 

HIP Write Strobe 

HIP Data 

HIP Address 

HRD 

HIP Read Strobe 

HIP Write Strobe 

HIP Address/Data 

HIP Address Latch Enable 

HWR 

HD15-0 

HA2-0 

HWR 

HAD15-0 

ALE 

HRW 

HIP Read/Write Select 

HRW 

HIP Read /Write Select 

HDS 

HIP Data Strobe 

HDS 

HIP Data Strobe 

HD15-0 

HIP Data 

HAD15-0 

HIP Address/Data 

HA2-0 

HIP Address 

ALE 

HIP Address Latch Enable 


Table 7.2 HIP Configuration Modes 


7-3 





The functions of the following pins are determined by HMDO and HMD1 
as described above: 

HD15-0/HAD15-0 are either a data bus or a multiplexed address /data 
bus. (Only the 3 least significant address bits are used.) 

HRD/HRW is either a read strobe or a read/ write select (l=read, 

0= write). 

HWR/HDS is either a write strobe or a data strobe. 

HA2/ ALE is either the most significant host address bit or an address 
latch enable. 

HA1-0 are either the two least significant host address bits or are unused. 


7.3 HIP FUNCTIONAL DESCRIPTION 

The HIP consists of three functional blocks, shown in Figure 7.1: a host 
control interface block (HCI), a block of six data registers (HDR5-0) and a 
block of two status registers (HSR7-6). The HIP also includes an associated 
HMASK register for masking interrupts generated by the HIP. The HCI 
provides the control for reading and writing the host registers. The two 
status registers provide status information to both the host and the ADSP- 
21 xx core. 

The HIP data registers HDR5-0 are memory-mapped into internal data 
memory at locations 0x3FE0 (HDRO) to 0x3FE5 (HDR5). These registers 
can be thought of as a block of dual-ported memory. None of the HDRs 
are dedicated to either direction; they can be read or written by either the 
host or the ADSP-21xx. When the host reads an HDR register, a maskable 
HIP read interrupt is generated. When the host writes an HDR, a 
maskable HIP write interrupt is generated. 

The read/ write status of the HDRs is also stored in the HSR registers. 
These status registers can be used to poll HDR status. Thus, data transfers 
through the HIP can be managed by using either interrupts or a polling 
scheme, described later in this chapter. 




Figure 7.1 HIP Block Diagram 

The HSR registers are shown in Figure 7.2, which can be found on the 
following page. Status information in HSR6 and HSR7 shows which HDRs 
have been written. The lower byte of HSR6 shows which HDRs have been 
written by the host computer. The upper byte of the HSR6 shows which 
HDRs have been written by the ADSP-21xx. When an HDR register is 
read, the corresponding HSR bit is cleared. 













HSR7 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

|| 

0 

0 

■ 

0 

0 

ill 

0 

0 

0 

0 

0 

0 

0 

0 


0x3FE7 



HSR6 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 


;i; 0 0 0 0 0 0 Hi 0 0 0 0 0 0 


0x3FE6 



Host HDRO Write 
Host HDR1 Write 
Host HDR2 Write 
Host HDR3 Write 
Host HDR4 Write 
Host HDR5 Write 


Figure 7.2 HIP Status Registers 

The lower six bits of HSR7 are copied from the upper byte of HSR6 so that 
8-bit hosts can read both sets of status. Bits 7 and 6 of HSR7 control the 
overwrite mode and software reset, respectively; these functions are 
described later in this chapter. The upper byte of HSR7 is reserved. All 
reserved bits and the software reset bit read as zeros. The overwrite bit is 
the only bit in the HSRs that can be both written and read. At reset, all 
HSR bits are zeros except for the overwrite bit, which is a one. 


7.4 HIP OPERATION 

The ADSP-21xx core can place a data value into one of the HDRs for 
retrieval by the host computer. Similarly, the host computer can place a 
data value into one of the HDRs for retrieval by the ADSP-21xx. To the 
host computer, the HDRs function as a section of memory. To the 
ADSP-21xx, the HDRs are memory-mapped registers, part of the internal 
data memory space. 





Because the HIP typically communicates with a host computer that has 
both a slower instruction rate and a multicycle bus cycle, the host 
computer is usually the limiting factor in the speed of HIP transfers. 
During a transfer, the ADSP-21xx executes instructions normally, 
independent of HIP operation. This is true even during a multicycle 
transfer from the host. 

For host computers that require handshaking, the ADSP-21xx returns 
HACK in the same cycle as the host access, except in overwrite mode. In 
ove rwrite m ode, the ADSP-21xx can extend a host access by not asserting 
the HACK acknowledge until the cycle is complete. The user can enable 
and disable overwrite mode by setting and clearing a bit in HSR7. 
Overwrite mode is described in more detail later in this chapter. 

The HDRs are not initialized during either hardware or software reset. 
The host can write information to the HDRs before a reset, and the ADSP- 
21 xx can read this information after the reset is finished. During reset, 
however, HIP transfers cannot occur; the HACK pin is deasserted and the 
data pins are tristated. 

Because a host computer that requires handshaking must wait for an 
acknowledgement from the ADSP-21xx, it is possible to cause such a host 
to hang. If, when the host has initiated a transfer, but has not yet received 
an acknowledgement, the ADSP-21xx is reset, then the acknowledgement 
can not be generated, thus causing the host to wait indefinitely. 

There is no hardware in the HIP to prevent the host from writing a 
register that the ADSP-21xx core is reading (or vice versa). If the host and 
the ADSP-21xx try to write the same register at the same time, the host 
takes precedence. Simultaneous writes should be avoided, however: since 
the ADSP-21xx and the host operate asynchronously, simultaneous writes 
can cause unpredictable results. 

7.4.1 Polled Operation 

Polling is one method of transferring data between the host and the 
ADSP-21xx. Every time the host writes to an HDR, a bit is automatically 
set in the lower byte of HSR6. This bit remains set until the ADSP-21xx 
reads the HDR. Similarly, when the ADSP-21xx writes to an HDR, a bit in 
the upper byte of HSR6 (and the lower byte of HSR7) is set. This bit is 
cleared automatically when the host reads the HDR. 


7-7 



For example, the ADSP-21xx can wait in a loop reading an HSR bit to see if the 
host has written new data. When the ADSP-21xx sees that the bit is set, it 
conditionally jumps out of the loop, processes the new data, then returns to the 
loop. When transferring data to the host, the ADSP-21xx waits for the host to 
read the last data written so that new data can be transferred. The host polls 
the HSR bits to see when the new data is available. 

7.4. 1. 1 HIP Status Synchronization 

Processes running on the ADSP-21xx are asynchronous to processes running 
on the host. Values in the shared status registers (HSR6, HSR7) can therefore 
change at any time, and reading a changing value could give unpredictable 
results. The ADSP-21xx HIP, however, includes synchronization circuitry 
which guarantees that the HIP status is constant during a read by either the 
ADSP-21xx core or the host. This synchronization is illustrated in Figures 7.3 
and 7.4. The status registers are updated by the ADSP-21xx and thus are 
synchronous with the ADSP-21xx processor clock, but host accesses are 
asynchronous with respect to the ADSP-21xx clock. 

When the host reads HSR6 or HSR7 to obtain status information, there is a 
one-cycle synchronization delay before the current (i.e. updated) status is 
available. To obtain the correct, current status, therefore, the host must perform 
two consecutive reads — the second read will generate the correct status 
information (the first read generates the previous status). 


□pi I# / Host A / Host \ 

I Access \ / Access \ 

dl status d2 status cl host status c2 



Figure 7.3 Host Status Synchronization 


CLKOUT 


/ \ 


dl status 
change 


d2 status 
change 


Cl 21 xx HIP 

status update 


c2 


21 xx HIP 
status update 


Figure 7.4 ADSP-21xx HIP Status Synchronization 


host status 
update 


7-8 



In Figure 7.3, host status synchronization is based on a pseudo-clock HCLK, 
internal to the ADSP-21xx, which is a logical combination of HKD, HWR and 
HSEL. The first event shown in the figure is a status change at dl. The host status 
will then be updated after the HCLK low, HCLK high, HCLK low sequence at 
point cl. A status change at d2 would wait for the HCLK low, HCLK high, 

HCLK low sequence, and then host status would be updated at point c2. 

Status synchronization for the ADSP-21xx requires one full CLKOUT cycle 
(starting at the rising edge) after a status change. As shown in Figure 7.4, a status 
change at point dl would cause a 21 xx HIP status update at cl. A status change 
at d2 would cause a 21xx HIP status update at c2. 

7.4.2 Interrupt-Driven Operation 

Using an interrupt-driven protocol frees the host and the ADSP-21xx from polling 
the HSR(s) to see when data is ready to be read. For interrupt-driven transfers to the 
ADSP-21xx, the host writes data into an HDR, and the HIP automatically generates 
an internal interrupt. The interrupt is serviced like any other interrupt. 

For transfers to the host, the ADSP-21xx writes data to an HDR, then sets a flag 
output, which is connected to a host interrupt input, to signal the host that new data 
is ready to be transferred. Hag outputs are discussed in detail in Chapter 9, "System 
Interface." If the ADSP-21xx passes data to the host through only one HDR, then that 
HDR can be read directly by the host when it receives the interrupt. If more than one 
HDR is used to pass data, then the host must read the appropriate HSR(s) to 
determine which HDR was written by the ADSP-21xx. 

7.4.3 HDR Overwrite Mode 

In most cases, the ADSP-21xx reads host data sent through the HIP faster than the 
host can send them. However, if the host is sufficiently fast, if the ADSP-21xx is busy, 
or if the ADSP-21xx is driven by a slow clock, there may be a delay in servicing a 
host write interrupt. If the host computer uses a handshaking protocol requiring the 
ADSP-21xx to assert HACK to complete a host transfer, the ADSP-21xx can optionally 
hold off the next host write until it has processed the current one. 

If the HDR overwrite bit (bit 7 in HSR7) is cleared, and if the host tries to write to a 
register before it has been read by the ADSP-21xx, HACK is not asserted until the 
ADSP-21xx has read the previously written data. The host processor must wait for 
HACK to be asserted. As described earlier, however, there is a delay from when the 
host writes data to when the status is synchronized to the ADSP-21xx. During this 
interval, it is possible for the host to write an HDR a second time even when the 
overwrite bit is cleared. 


If the HDR overwrite bit is set, the previous value in the HDR is overwritten and 
HACK is returned immediately. If the ADSP-21xx is reading the register that is 
being overwritten, the result is unpredictable. 


7-9 



After reset, the HDR overwrite bit is set. If the host does not require an 
acknowledge (HACK is not used), the HDR overwrite bit should be always be 
set, because there is no way for the ADSP-21xx to prevent overwrite. 

7.4.4 Software Reset 

Writing a 1 to bit 6 of HSR7 causes software reset of the ADSP-21xx. If the 
ADSP-21xx writes the software reset bit, the reset happens immediately. 
Otherwise, the reset happens as soon as the write is synchronized to the 
ADSP-21xx system clock. The internal software reset signal is held for five 
ADSP-21xx clock cycles and then released. 


7.5 HIP INTERRUPTS 

HIP interrupts can be masked using either the IMASK register or the HMASK 
register. Bits in the IMASK register enable or disable all HOOP read interrupts or 
all HIP write interrupts. The HMASK register, on the other hand, has bits for 
masking the generation of read and write interrupts for individual HDRs. In 
order for a read or write of an HDR to cause an interrupt, the HIP read or write 
interrupt must be enabled in IMASK, and the read or write to the particular 
HDR must be enabled in HMASK. HMASK is mapped to memory location 
0x3FE8. IMASK is described in Chapter 3, "Program Control." 

A host write interrupt is generated whenever the host completes a write to an 
HDR. A host read interrupt is generated when an HDR is ready to receive data 
from the ADSP-21xx — this occurs when the host has read the previous data, 
and also after reset, before the ADSP-21xx has written any data to the HDR. 
HMASK, however masks all HIP interrupts at reset. The read interrupt allows 
the ADSP-21xx to transfer data to the host at a high rate without tying up the 
ADSP-21xx with polling overhead. 

HMASK allows reads and writes of some HDRs to not generate interrupts. For 
example, a system might use HDR2 and HDR1 for data values and HDRO for a 
command value. Host write interrupts from HDR2 and HDR1 would be 
masked off, but the write interrupt from HDRO would be unmasked, so that 
when the host wrote a command value, the ADSP-21xx would process the 
command. In this way, the overhead of servicing interrupts when the host 
writes data values is avoided. 

The HMASK register is organized in the same way as HSR6; the mask bit is in 
the same location as the status bit for the corresponding register. The lower 
byte of HMASK masks host write interrupts and the upper byte masks host 
read interrupts. The bits are all positive sense (0=masked, l=enabled). 



HMASK 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


0 1 

1 0 

0 

0 

0 

0 

0 

ill 

i 

0 

0 

0 

0 

0 

0 


0X3FE8 


Host HDR5 Read 
Host HDR4 Read 
Host HDR3 Read 
Host HDR2 Read 
Host HDR1 Read 
Host HDRO Read 




Host HDRO Write 
Host HDR1 Write 
Host HDR2 Write 
Host HDR3 Write 
Host HDR4 Write 
Host HDR5 Write 


Figure 7.5 HMASK Register 


INTERRUPT ENABLES 
1=enable 
0=disable 


HMASK is mapped to the internal data memory space at location 0x3FE8. At reset, 
the HMASK register is all zeros, which means that all HEP interrupts are masked. 


HIP read and write interrupts are not cleared by servicing such an interrupt. Reading 
the HDR clears a write interrupt, and writing the HDR clears a read interrupt. The 
logical combination of all read and write interrupt requests generates a HIP interrupt. 
Pending interrupt requests remain until all HIP interrupts are cleared by either 
reading or writing the appropriate HEP data register. If the ADSP-21xx is reading 
registers that the host might be writing, it is not certain that an interrupt will be 
generated. To ensure that all host writes generate interrupts, you must make sure that 
die ADSP-21xx is not reading the HDRs that the host is writing. While servicing the 
interrupt, the status register can be read to determine which operation generated the 
interrupt and whether multiple interrupt requests need to be serviced. 


HEP interrupts cannot be forced or cleared by software, as other interrupts can. 
The HEP write interrupt vector is location 0x0008. The HEP read interrupt vector is 
location OxOOOC. 


7.6 HOST INTERFACE TIMING 

The following diagrams show the timings of HIP signals in the various modes 
determined by HMD0 and HMD1. HMD0 configures the bus strobes, selecting either 
separate read and write strobes or a single read/ write select and a host data strobe. 
HMD1 configures the bus protocol, selecting either separate address (3-bit) and data 
(16-bit) buses or a multiplexed 16-bit address/data bus with address latch enable. 

The HSIZE pin can be changed on a cycle-by-cycle basis; although not shown in the 
foEowing diagrams, it has the same timing as the HRD/HRW signal. 


7-11 




Figure 7.6 shows the HIP timing when both HMD0=0 and HMD1=0. HMDO 
selects separate read and write strobes, and HMD1 selects separate address 
and data buses. The timing for the read cycle and the write cycle is as follows: 

1. The host asserts the address. 

2. The host asserts (HKD or HWR) and HSEL. 

3. The ADSP-21xx returns HACK (and, for a read cycle, the data). 

4. For a write cycle, the host asserts the data. 

5. The host deasserts (HKD or HWR) and HSEL. 

6. The host deasserts the address (and, for a write cycle, the data). 

7. The ADSP-21xx deasserts HACK (and, for a read cycle, the data). 


HA2-0 


mx 


ADDRESS 




HSEL 


Host Write Cycle hwr 



/ 

/ 


HACK 


\ 


/ 


mm 


c 






HA2-0 


m x mmmm 


Host Read Cycle 


HSEL 


HRD 


\ 

\ 


/ 

I 


HACK 


\ 


/ 


HD15-0 


<x x> 


Figure 7.6 HIP Timing: Separate Strobes, Separate Buses 


7-12 



Figure 7.7 shows the HIP timing when HMD0=1 and HMD1=0. HMDO selects 
a multiplexed read/write select with data strobe, and HMD1 selects separate 
address and data buses. The timing for the read cycle and the write cycle is as 
follows: 

1 . The host asserts HRW and the address. 

2. The host asserts HDS and H5EL. 

3. The ADSP-21xx returns HACK (and, for a read cycle, the data). 

4. For a write cycle, the host asserts the data. 

5. The host deasserts HDS and HSEL. 

6. The host deasserts HRW and the address (and, for a write cycle, the data). 

7. The ADSP-21xx deasserts HACK (and, for a read cycle, the data). 

HA2-0 

HSEL 

HRW 

Host Write Cycle 

HD§ 


HACK 




Figure 7.8 shows the HIP timing when HMD0=0 and HMD1=1. HMDO selects 
separate read and write strobes, and HMD1 selects multiplexed address and 
data buses. HD0-HD2 are used for the address. The timing for the read cycle 
and the write cycle is as follows: 

1 . The host asserts ALE. 

2. The host drives the address. 

3. The host deasserts ALE. 

4. The host stops driving the address. 

5. The host asserts (HKD or HWR) and HSEL. 

6. The ADSP-21xx returns HACK (and, for a read cycle, the data). 

7. For a write cycle, the host asserts the data. 

8. The host deasserts (HKD or HWR) and HSEL. 

9. For a write cycle, the host deasserts the data. 

10. The ADSP-21xx deasserts HACK (and, for a read cycle, the data). 


HSEL 


Host Write Cycle hwr 


HACK 


H ADI 5-0 


ALE 


HSEL 


Host Read Cycle hrd 


HACK 

HAD15-0 

_ . _ Figure 7.8 HIP Timing: Separate Strobes, Multiplexed Buses 

7-14 







Figure 7.9 shows the HIP timing when HMD0=1 and HMD1=1. HMDO selects 
a multiplexed read/write select with data strobe, and HMD1 selects 
multiplexed address and data buses. HD0-HD2 are used for the address. The 
timing for the read cycle and the write cycle is as follows: 

1 . The host asserts ALE. 

2. The host drives the address. 

3. The host deasserts ALE. 

4. The host stops driving the address. 

5. The host asserts HRW. 

6. The host asserts HDS and HSEL. 

7. The ADSP-21xx returns HACK (and, for a read cycle, the data). 

8. For a write cycle, the host asserts the data. 

9. The host deasserts HDS and HSEL. 

10. The host deasserts F1RW (and, for a write cycle, the data). 

1 1 . The ADSP-21xx deasserts HACK (and, for a read cycle, the data). 


HSEL 

HRW 

Host Write Cycle _ 

HDS 


HACK 

H ADI 5-0 





HAD15-0 



7-15 


Figure 7.9 HIP Timing: Multiplexed R/W Strobe, Multiplexed Buses 




7.7 BOOT LOADING THROUGH THE HIP 

The entire internal program RAM of the ADSP-21xx, or any portion of it, 
can be loaded using a boot sequence. Upon hardware or software reset, 
the boot sequence occurs if the MMAP pin is 0. If the MMAP pin is 1, the 
boot sequence does not occur. 

The ADSP-21xx can boot in either of two ways: from external memory 
(usually EPROM), through the boot memory interface, or from a host 
processor, through the HIP. The BMODE pin selects which type of booting 
occurs. 

When BMODE=0, booting occurs through the memory interface. This 
process is described in Chapter 10, "Memory Interface." When the 
BMODE=l, booting occurs through the HIP. 

To generate a file for HIP booting, use the HIP Splitter utility program of the 
ADSP-2100 Family Development Software. (This utility produces HIP boot 
files while the PROM Splitter utility produces files for EPROM booting.) 

The BMS signal is asserted when booting through the HIP just as when 
booting through the memory interface; in this case, it serves as an 
indication that the boot sequence is occurring. Boot memory wait states 
have no effect when booting through the HIP. 

Booting through the HIP occurs in the following sequence: 

1. After reset, the host writes the length of the boot sequence to HDR3. 

2. The host waits at least two ADSP-21xx processor cycles. 

3. Starting with the instruction which is to be loaded into the highest 
address of internal program memory, the host writes an instruction 
into HDRO, HDR2 and HDR1 (in that order), one byte each. The upper 
byte goes into HDRO, the lower byte goes into HDR2 and the middle 
byte goes into HDR1. 

4. The address of the instruction is decremented, and Step 3 is repeated. 
This continues until the last instruction has been loaded into the HIP. 


7-16 


The ADSP-21xx reads the length of the boot load first, then bytes are 
loaded from the highest address downwards. This results in shorter 
booting times for shorter loads. 



The number of instructions booted must be a multiple of eight. The boot 
length value is given as: 

length = (number of 24-bit program memory words 4- 8) - 1 

That is, a length of 0 causes the HIP to load eight 24-bit words. 

In most cases, no handshaking is necessary, and the host can transfer data 
at the maximum rate it is capable of. If the host operates faster than the 
ADSP-21xx, wait states or NOPs must be added to the host cycle to slow it 
down to one write every ADSP-21xx clock cycle. 

The following example shows the data that a host would write to the HIP 
for a 1000-instruction boot: 


Data Location 

Page Length (124 decimal) HDR3 

Upper Byte of Instruction at 999 HDRO 

Lower Byte of Instruction at 999 HDR2 

Middle Byte of Instruction at 999 HDR1 

Upper Byte of Instruction at 998 HDRO 

Lower Byte of Instruction at 998 HDR2 

Middle Byte of Instruction at 998 HDR1 

Upper Byte of Instruction at 997 HDRO 

Lower Byte of Instruction at 997 HDR2 

Middle Byte of Instruction at 997 HDR1 


Upper Byte of Instruction at 0 HDRO 

Lower Byte of Instruction at 0 HDR2 

Middle Byte of Instruction at 0 HDR1 


A 16-bit host boots the ADSP-21xx at the same rate as an 8-bit host. Either 
type of host must write the same data to the same the HDRs in the same 
sequence (HDRO, HDR2, HDR1). If a 16-bit host writes 16-bit data, the 
upper byte of the data must be 0x00. The following example, loading the 
instruction OxABCDEF, illustrates this: 

8-Bit Host 16-Bit Host 

1st Write (to HDRO) OxAB 0x0 0AB 

2nd Write (to HDR2) OxEF 0x0 0EF 

3rd Write (to HDR1) OxCD 0x0 0CD 7-17 




Analog Interface El 8 


8.1 OVERVIEW 

The ADSP-21msp58 and ADSP-21msp59 processors include an analog 
signal interface consisting of a 16-bit sigma-delta A/D converter, a 16- 
bit sigma-delta D/A converter, and a set of memory-mapped control 
and data registers. The analog interface offers the following features: 

• linear-coded 16-bit sigma-delta ADC 

• linear-coded 16-bit sigma-delta DAC 

• on-chip anti-aliasing and anti-imaging filters 

• 8 kHz sampling frequency 

• programmable gain for DAC and ADC 

• on-chip voltage reference 

The analog interface provides a complete analog front end for high 
performance voiceband DSP applications. The ADC and DAC operate 
at a fixed sampling rate of 8 kHz. The inclusion of on-chip anti-aliasing 
and anti-imaging filters, 16-bit sigma-delta converters, and 
programmable gain amplifiers ensures a highly integrated solution to 
voiceband analog processing requirements. Sigma-delta conversion 
technology eliminates the need for complex off-chip anti-aliasing filters 
and sample-and-hold circuitry. 

The ADSP-21msp58 and ADSP-21msp59 contain the same analog 
interface — they differ only in the amount of on-chip memory. Refer to 
the ADSP-21msp58/59 Data Sheet for detailed analog performance 
specifications. 

The analog interface of the ADSP-21msp58/59 is operated by using 
several data-memory-mapped control and data registers. The ADC 
and DAC I/O can be transmitted and received via individual memory- 
mapped registers, or the data can be autobuffered directly into the 
processor's data memory. This autobuffering is similar to serial port 
autobuffering, as described in Chapter 5. 


8-1 




Two ADSP-21msp58/59 interrupts are dedicated to the ADC and DAC 
converters. One interrupt is used for the ADC and the other interrupt 
is used for the DAC. Interrupts occur at the sample rate or when the 
autobuffer transfer is complete. 

A block diagram of the analog interface is shown in Figure 8.1, and pin 
definitions are given in Table 8.1. 



Figure 8.1 Analog Interface Block Diagram (ADSP-21msp58/59) 


8.2 A/D CONVERSION 

The A/D conversion circuitry of the ADSP-21msp58/59's analog 
interface consists of an input multiplexer, a programmable gain 
amplifier (PGA), and a sigma-delta analog-to-digital converter (ADC). 

8.2.1 Analog Input 

The analog input is internally biased by an on-chip voltage reference to 
allow operation of the ADSP-21msp58/59 with a single +5V power 
supply. The analog inputs should be ac-coupled. 


An analog multiplexer selects either the NORM or AUX input. The 
input multiplexer is configured by bit 1 (IMS) of the 
ADSP-21msp58/59's analog control register (which is memory- 
mapped at address 0x3FEE in data memory). The multiplexer setting 
should not be changed while an input signal is being processed. 


8-2 








Pin Name 

vin norm 

I/O 

I 

Function 

Input terminal of the NORM channel of the ADC. 

vin aux 

I 

Input terminal of the AUX channel of the ADC. 

Decouple 

I 

Ground reference of the NORM and AUX channels 
for the ADC. 

VOUTp 

o 

Non-inverting output terminal of the differential 
output amplifier from the DAC. 

VOUT N 

o 

Inverting output terminal of the differential output 
amplifier from the DAC. 

V REF 

o 

Buffered output voltage reference. 

REF_FILTER 

o 

Voltage reference external bypass filter node. 

v cc 


Analog supply voltage. 

GND a 


Analog ground. 


Table 8.1 Analog Interface Pin Definitions 


The ADC PGA may be used to increase the signal level by +6 dB, +20 
dB, or +26 dB. This selection is configured by bits 9 and 0 (IG1, IGO) of 
the analog control register. Input signal level to the sigma-delta 
modulator should not exceed the Vinmax specification listed in the 
ADSP-21msp58/59 Data Sheet. Refer to "Analog Input" in the "Design 
Considerations" section of this chapter for more information. 

An offset may be added to the input of the ADC in order to move the 
ADC's idle tones out of the 4.0 kHz speech band range. This is selected 
by bit 10 of the analog control register. The added offset must be 
removed by the ADC's high pass filter; therefore the high pass filter 
must be inserted (not bypassed) when the offset is added. 

8.2.2 ADC 

The analog interface's ADC consists of a 4th-order analog sigma-delta 
modulator, an anti-aliasing decimation filter, and a digital high pass 
filter. The sigma-delta modulator noise-shapes the signal and produces 
1-bit samples at a 1.0 MHz rate. This bit stream, which represents the 
analog input signal, is fed to the anti-aliasing decimation filter. 



8.2.2. 1 Decimation Filter 

The ADC's anti-aliasing decimation filter contains two stages. The first 
stage is a sine 4 digital filter that increases resolution to 16 bits and 
reduces the sample rate to 40 kHz. The second stage is an HR low pass 
filter. 

The HR low pass filter is a lOth-order elliptic filter with a passband 
edge at 3.7 kHz and a stopband attenuation of 65 dB at 4 kHz. This 
filter has the following specifications: 

Filter type: lOth-order low pass elliptic HR 

Sample frequency: 40.0 kHz 

Passband cutoff*: 3.70 kHz 

Passband ripple: ±0.2 dB 

Stopband cutoff: 4.0 kHz 

Stopband ripple: -65.00 dB 

* The passband cutoff frequency is defined to be the last point in the 
passband that meets the passband ripple specification. 

(Note that these specifications apply only to this filter, and not to the 
entire ADC. The specifications can be used to perform further analysis 
of the exact characteristics of the filter, for example using a digital filter 
design software package.) 

Figure 8.2 shows the frequency response of the HR low pass filter. 



FREQUENCY -Hz 

Figure 8.2 HR Low Pass Filter Frequency Response 


8-4 




8.22.2 High Pass Filter 

The ADC's digital high pass filter removes frequency components at 
the low end of the spectrum; it attenuates signal energy below the 
passband of the converter. The ADC's high pass filter can be bypassed 
by setting bit 7 (ADBY) of the ADSP-21msp58/59's analog control 
register. 

The high pass filter is a 4th-order elliptic filter with a passband cutoff 
at 150 Hz. Stopband attenuation is 25 dB. This filter has the following 
specifications: 

Filter type: 

Sample frequency: 

Passband cutoff: 

Passband ripple: 

Stopband cutoff: 

Stopband ripple: 

(Note that these specifications apply only to this filter, and not to the 
entire ADC. The specifications can be used to perform further analysis 
of the exact characteristics of the filter, for example using a digital filter 
design software package.) 

Figure 8.3 shows the frequency response of the high pass filter. 

Passband ripple is ±0.2 dB for the combined effects of the ADC's 
digital filters (i.e. high pass filter and IIR low pass of the decimation 
filter) in the 300-3400 Hz passband. 


4th-order high pass elliptic IIR 

8.0 kHz 

150.0 Hz 
±0.2 dB 

100.0 Hz 
-25.00 dB 




0 60 120 180 240 300 

FREQUENCY -Hz 


Figure 8.3 High Pass Filter Frequency Response 





8.3 D/A CONVERSION 

The D/ A conversion circuitry of the ADSP-21msp58/59's analog 
interface consists of a sigma-delta digital-to-analog converter (DAC), 
an analog smoothing filter, a programmable gain amplifier, and a 
differential output amplifier. 

8.3.1 DAC 

The analog interface's DAC implements digital filters and a sigma- 
delta modulator with the same characteristics as the filters and 
modulator of the ADC. The DAC consists of a digital high pass filter, 
an anti-imaging interpolation filter, and a digital sigma-delta 
modulator. 

The DAC receives 16-bit data values from the ADSP-21msp58/59's 
DAC Transmit data register (which is memory-mapped at address 
0x3FEC in data memory). The data stream is filtered first by the DAC's 
high pass filter and then by the anti-imaging interpolation filter. These 
filters have the same characteristics as the ADC's anti-aliasing 
decimation filter and digital high pass filter. 

The output of the interpolation filter is fed to the DAC's digital sigma- 
delta modulator, which converts the 16-bit data to 1-bit samples at a 
1.0 MHz rate. The modulator noise-shapes the signal such that errors 
inherent to the process are minimized in the passband of the converter. 

The bit stream output of the sigma-delta modulator is fed to the DAC's 
analog smoothing filter where it is converted to an analog voltage. 

8.3. 1.1 High Pass Filter 

The DAC's digital high pass filter has the same characteristics as the 
high pass filter of the ADC. The high pass filter removes frequency 
components at the low end of the spectrum; it attenuates signal energy 
below the passband of the converter. The DAC's high pass filter can be 
bypassed by setting bit 8 (DABY) of the ADSP~21msp58/59's analog 
control register. 


8-6 



The high pass filter is a 4th-order elliptic filter with a passband cutoff 
at 150 Hz. Stopband attenuation is 25 dB. This filter has the following 
specifications: 


Filter type: 

Sample frequency: 
Passband cutoff: 
Passband ripple: 
Stopband cutoff: 
Stopband ripple: 


4th-order high pass elliptic HR 

8.0 kHz 

150.0 Hz 
±0.2 dB 

100.0 Hz 
-25.00 dB 


(Note that these specifications apply only to this filter, and not to the 
entire DAC. The specifications can be used to perform further analysis 
of the exact characteristics of the filter, for example using a digital filter 
design software package.) 


Figure 8.3 shows the frequency response of the high pass filter. 

8.3.1. 2 Interpolation Filter 

The DAC's anti-imaging interpolation filter contains two stages. The 
first stage is is an HR low pass filter that interpolates the data rate from 
8 kHz to 40 kHz and removes images produced by the interpolation 
process. The output of this stage is then interpolated to 1.0 MHz and 
fed to the second stage, a sine 4 digital filter that attenuates images 
produced by the 40 kHz to 1.0 MHz interpolation process. 

The DR low pass filter is a lOth-order elliptic filter with a passband edge at 
3.70 kHz and a stopband attenuation of 65 dB at 4 kHz. This filter has the 
following specifications: 


Filter type: 

Sample frequency: 
Passband cutoff*: 
Passband ripple: 
Stopband cutoff: 
Stopband ripple: 


lOth-order low pass elliptic IIR 

40.0 kHz 
3.70 kHz 
±0.2 dB 

4.0 kHz 
-65.00 dB 


* The passband cutoff frequency is defined to be the last point in the 
passband that meets the passband ripple specification. (Note that these 
specifications apply only to this filter, and not to the entire DAC. The 
specifications can be used to perform further analysis of the exact 
characteristics of the filter, for example using a digital filter design software 
package.) 



Figure 8.2 shows the frequency response of the IIR low pass filter. 


Passband ripple is ±0.2 dB for the combined effects of the DAC's digital 
filters (i.e. high pass filter and DR low pass of the interpolation filter) in the 
300-3400 Hz passband. 

8.3. 1.3 Analog Smoothing Filter & Programmable Gain Amplifier 

The DAC's programmable gain amplifier (PGA) can be used to adjust the 
output signal level by -15 dB to +6 dB. This gain is selected by bits 2-4 
(OGO, OG1, OG2) of the of the ADSP-21msp58/59's analog control register. 

The DAC's analog smoothing filter consists of a 2nd-order Sallen-Key 
continuous-time filter and a 3rd-order switched capacitor filter. The Sallen- 
Key filter has a 3 dB point at approximately 25 kHz. 

8.3.2 Differential Output Amplifier 

The ADSP-21msp58/59's analog output signal (VOUT p - VOUT N ) is 
produced by a differential amplifier. The differential amplifier meets 
specifications for loads greater than 2 kD (R L > 2 kQ) and has a 
maximum differential output voltage swing of ±3.156 V peak-to-peak 
(3.17 dBmO). The DAC will drive loads smaller than 2 kd, but with 
degraded performance. 

The output signal is dc-biased to the on-chip voltage reference (V REF ) 
and can be ac-coupled directly to a load or dc-coupled to an external 
amplifier. Refer to "Analog Output" in the "Design Considerations" 
section of this chapter for more information. 

The VOUTp - VOUT N outputs must be used as a differential signal, 
otherwise performance will be severely degraded. Do not use either 
pin as a single-ended output. 


8-8 



8.4 OPERATING THE ANALOG INTERFACE 

The analog interface of the ADSP-21msp58/59 is operated with the use 
of several memory-mapped control and data registers. The ADC and 
DAC I/O data can be received and transmitted in two memory- 
mapped data registers. The data can also be autobuffered into (and 
from) on-chip memory where data is automatically transferred to or 
from the data registers. In both cases, the I/O processing is interrupt- 
driven: two ADSP-21msp58/59 interrupts are dedicated to the analog 
interface, one for ADC receive data and one for DAC transmit data. 
(Note: Autobuffering with SPORT1 is not available on the 
ADSP-21msp5x processors because this autobuffering channel is used 
for the analog interface.) 

The ADSP-21msp58/59 must have an input clock frequency of 13 
MHz. At this frequency, analog-to-digital and digital-to-analog 
converted data is transmitted at an 8 kHz rate with a single 16-bit word 
transmitted every 125 ps. 

8.4.1 Memory-Mapped Control Registers 

Two memory-mapped control registers are used to configure the 
ADSP-21msp58/59's analog interface: the analog control register and 
analog autobuffer /powerdown register. 

8.4. 1. 1 Analog Control Register 

The analog control register (located at address 0x3FEE in data 
memory) is shown in Figure 8.4. This register configures the ADC 
input multiplexer, ADC input gain PGA, ADC high pass filter, DAC 
high pass filter, and DAC output gain PGA. 

The analog control register also contains the APWD bits (bits 5, 6) 
which must both be set to ones to enable and start up the analog 
interface — always enable and disable the analog interface using both bits 
5 and 6. The DAC and ADC begin transmitting data after these bits are 
set. Clearing the APWD bits disables the entire analog interface by 
putting it in a powerdown state. The APWD bits must be cleared (to 
zeros) at least three processor cycles before putting the processor in 
powerdown. See "Powerdown" in Chapter 9, System Interface. 

The analog control register is cleared (to 0x0000) by the processor's 
RESET signal. Note that bits 10-15 of this register are reserved and 
must always be set to zero. 



Analog Control Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


ill 

0 

111! 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

3 


ADC Offset 


IGO 

ADC Input Gain (ADC PGA) 



DABY 

DAC High Pass Filter Bypass 
1=bypass, 0=insert 

ADBY 

ADC High Pass Filter Bypass 
1=bypass, 0=insert 


DM(0x3FEE) 


IG1 

ADC Input Gain (ADC PGA) 
IMS 

ADC Input Multiplexer Select 
1=AUX input, 0=NORM input 

OG2, OG1, OGO 

DAC Output Gain (DAC PGA) 

APWD 


All bits are set to 0 at processor reset. 
(Reserved bits 10-15 must always be set to 0.) 


Analog Interface Powerdown 
0=powerdown, 1=enable 
(Set both bits to 1 to 
enable analog interface) 


IG1, IGO 

ADC Input Gain (ADC PGA) 


OG2, OG1, OGO 

DAC Output Gain (DAC PGA) 


Gain 

IG1 

IGO 

OdB 

0 

0 

+6dB 

0 

i 

+20 dB 

1 

0 

+26 dB 

1 

1 


Figure 8.4 Analog Control Register 


Gain 

QQ2 

QG1 

9G0 

+6dB 

0 

0 

0 

+3 dB 

0 

0 

i 

OdB 

0 

1 

0 

-3dB 

0 

1 

1 

-6dB 

1 

0 

0 

-9dB 

1 

0 

1 

-12 dB 

1 

1 

0 

-15 dB 

1 

1 

1 


8.4. 1.2 Analog Autobuffer/Powerdown Register 

The analog autobuffer/ powerdown register (located at address 0x3FEF 
in data memory) is shown in Figure 8.5. This register enables or 
disables autobuffering of ADC receive data and/ or DAC transmit 
data — autobuffering is enabled by writing ones to the ARBUF (bit 0) 
and/ or ATBUF (bit 1) bits. When autobuffering is enabled, I (index) 
and M (modify) registers are selected in bits 2-11 for the receive 
and/or transmit data buffers. See “Autobuffering" in the Serial Ports 
chapter for details on autobuffering. 


8-10 





8 


Analog Autobuffer/Powerdown Control Register 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 


Processor powerdown control bits. 
(See Chapter 9, “System Interface”) 


Figure 8.5 Analog Autobuffer/Powerdown Control Register 


DM(0x3FEF) 


ARBUF 

ADC Receive Autobuffer Enable 


ATBUF 

DAC Transmit Autobuffer Enable 


ARMREG 
Receive M register 

ARIREG 
Receive I register 

ATMREG 

Transmit M register 

ATIREG 
Transmit I register 


Bits 12-15 of the analog autobuffer/powerdown register control the 
ADSP-21msp58/59's processor powerdown function, not powerdown 
of the analog interface — powerdown of the analog interface only is 
controlled by the APWD bits (bits 5, 6) of the analog control register. 
The ADSP-21msp58/59's powerdown function is described in the 
"Powerdown" section of Chapter 9, System Interface. 

8.4.2 Memory-Mapped Data Registers 

There are two memory-mapped data registers dedicated to the analog 
interface. The 16-bit ADC receive data register is located at address 
0x3FED in data memory. The 16-bit DAC transmit data register is 
located at address 0x3FEC in data memory. These registers must be 
individually read and written when autobuffering is not in use 
(autobuffering automatically transfers the data to and from processor 
data memory). 

When autobuffering is disabled, data must be transmitted to the 
sigma-delta DAC by writing a 16-bit word to the DAC transmit 
register (0x3FEC) and data must be received from the sigma-delta ADC 
by reading a 16-bit word from the ADC receive register (0x3FED). 


8-11 




8.4.3 ADC & DAC Interrupts 

The analog interface generates two interrupts that signal either: 

1) that a 16-bit, 8 kHz analog-to-digital or digital-to-analog conversion 
has been completed, or 2) that an autobuffer block transfer has been 
completed (i.e. the entire data buffer contents have been transmitted or 
received). 

When one of the analog interrupts occurs, the processor vectors to the 
appropriate address: 

DAC Transmit interrupt vector address: 0x18 

ADC Receive interrupt vector address: OxlC 

These interrupts can be masked out in the processor's IMASK register 
and can be forced or cleared in the IFC register. 

8 A 3.1 Autobuffering Disabled 

The ADC receive and DAC transmit interrupts occur at an 8 kHz rate, 
indicating when the data registers should be accessed, when 
autobuffering is disabled. On the receive side, the ADC interrupt is 
generated each time an A/D conversion cycle is completed and the 
16-bit data word is available in the ADC receive register. On the 
transmit side, the DAC interrupt is generated each time a D/A 
conversion cycle is completed and the DAC transmit register is ready 
for the next 16-bit data word. 

Both interrupts are generated simultaneously at an 8 kHz rate, 
occurring every 3250 instruction cycles with a 13 MHz internal clock, 
when autobuffering is disabled. The interrupts are generated 
continuously, starting when the analog interface is powered up by 
setting the APWD bits (bits 5, 6) to ones in the analog control register. 
Because both interrupts occur simultaneously, only one should be 
enabled (in IMASK) to vector to a single service routine that handles 
both transmit and receive data. (When autobuffering is enabled, 
though, both interrupts should be enabled.) 

A simple analog loopback program is shown in Listing 8.1. 



8 


{ ADSP-21msp58/59 Analog Interface Loopback Example } 
{ - configures analog interface } 
{ - copies ADC receive data to DAC transmit buffer} 


.MODULE/ABS=0/BOOT=0 talkthru; 

ttdefine codec_tx_data 0x3FEC 
ttdefine codec_rx_data 0x3FED 
ttdefine codec_ctrl_reg 0x3FEE 


resetv : 


JUMP setup; NOP; NOP; NOP; 


irq2v: 

RTI; 

NOP; 

NOP; 

NOP; 

{interrupt vectors 

. . .} 

hipwv: 

RTI ; 

NOP; 

NOP; 

NOP; 



hiprv: 

RTI; 

NOP; 

NOP; 

NOP; 



sptOtv: 

RTI; 

NOP; 

NOP; 

NOP; 



sptOrv: 

RTI; 

NOP; 

NOP; 

NOP; 



an tv: 

RTI; 

NOP; 

NOP; 

NOP; 



anrv: 

SI = 

DM (code c_ 

,rx_data) ; 

{read in data from 

ADC} 


DM (codec_ 

tx_data) = SI; 

{write out data to 

DAC} 


RTI; 

NOP; 





irqlv: 

RTI; 

NOP; 

NOP; 

NOP; 



irqOv: 

RTI; 

NOP; 

NOP; 

NOP; 



timerv: 

RTI; 

NOP; 

NOP; 

NOP; 



pwrdwnv : 

RTI; 

NOP; 

NOP; 

NOP; 




setup : 


wait_loop : 
.ENDMOD; 


AXl = 0x0060; 
DM(codec_ctrl_reg) = AXl; 
IMASK = 0x8; 

IDLE; 

JUMP wait_loop; 


{power up analog interface} 
{enable analog receive interrupt} 
{wait for interrupt} 


Listing 8.1 ADSP-21msp58/59 Analog Loopback Program 


8A.3.2 Autobuffering Enabled 

In some applications it is advantageous to perform block data transfers 
between the analog converters and processor memory. Analog 
interface autobuffering allows you to automatically transfer blocks of 
data from the ADC to on-chip processor data memory or from on-chip 
processor data memory to the DAC. 

An interrupt is generated when an entire block transfer is complete (i.e. 
when the data buffer is full or empty). Analog interface autobuffering 
operates in the same way as SPORT autobuffering, described in 
Chapter 5. Note that data can be autobuffered through the analog 
converters or through SPORTO of the ADSP-21msp58/59. 
Autobuffering is not available on SPORT1 of the ADSP-21msp58/59. 


8-13 




Before autobuffering is enabled, separate circular buffers must be set 
up in data memory for the ADC receive and DAC transmit data. This 
is accomplished by selecting I (index) and M (modify) registers in the 
analog autobuffer /powerdown register; see Figure 8.5. 

Transmit data autobuffered to the DAC is addressed with the I register 
specified in the ATIREG field (bits 9, 10, 11). Receive data autobuffered 
from the ADC is addressed with the I register specified in the ARIREG 
field (bits 4, 5, 6). The modify (M) registers are specified in the 
ARMREG (bits 2, 3) field and ATMREG (bits 7, 8) field. Since the 
transfer of ADC and DAC data occurs simultaneously, it is possible to 
use the same I register for transmit and receive autobuffering. In this 
case, the buffer is shared for both functions and care should be taken 
when specifiying a value for the M register. 

An autobuffering example program is shown in Listing 8.2. 


{ ADSP-21msp58/59 Analog Interface Autobuffer Example } 


{ - configures analog interface } 
{ - enables analog autobuffer } 
{ - receive analog data into a 256 word buffer } 
{ - transmit analog data from a 256 word buffer } 


.MODULE/ RAM/ ABS=0/BOOT=0 auto_example; 
.VAR/DM/CIRC buffi [256] ; 

.VAR/DM/CIRC buff 2 [256] ; 

.VAR/DM flagjbit; 

#define codec_tx_data 0x3 FEC 
#define codec_rx_data 0x3FED 
#define codec_ctrl_reg 0x3FEE 
#define codec_auto_ctrl 0x3FEF 


resetv: 

JUMP 

setup; NOP; NOP; NOP; 

irq2v: 

RTI; 

NOP; 

NOP; 

NOP; 

hipwv: 

RTI; 

NOP; 

NOP; 

NOP; 

hiprv : 

RTI; 

NOP; 

NOP; 

NOP; 

sptOtv: 

RTI; 

NOP; 

NOP; 

NOP; 

sptOrv: 

RTI; 

NOP; 

NOP; 

NOP; 

an tv: 

RTI; 

NOP; 

NOP; 

NOP; 

anrv: 

JUMP 

switch; NOP; NOP; NOP 

irqlv: 

RTI; 

NOP; 

NOP; 

NOP; 

irqOv: 

RTI; 

NOP; 

NOP; 

NOP; 

timerv: 

RTI; 

NOP; 

NOP; 

NOP; 

pwrdwnv : 

RTI; 

NOP; 

NOP; 

NOP; 


(first data buffer} 
(second data buffer} 
(tracks buffers} 


(interrupt vectors . . . } 


(call autobuffer switch} 


8-14 



8 


setup: 10 = ''buffi; 

L0 = %buf f 1 ; 

II = ''buff 2 ; 

LI = %buf f 2 ; 

MO = Oxl; 

SI = 0x0; 

DM ( f lag_bit) = SI; 


AYO = 0x0203; 

DM ( codec_auto_ctrl ) 

AX1 = 0x0060; 

DM ( codec_c tr l_reg ) 

IMASK = 0x8; 

IDLE; {wait for autobuffer interrupt} 

JUMP wait; 

AX0 = DM( flag_bit) ; 

AR = pass AX0; {check buffer status} 

IF NE JUMP f ill_buf f 2 ; 

SI = 0x1; {fill buff2 next time} 

AYO = 0x0013; 

JUMP done; 

SI = 0x0; {fill buffi next time} 

AYO = 0x0203; 

JUMP done; 

DM(codec_auto_ctrl) = AYO; 

DM ( f lag_bi t ) = SI ; 

RTI ; 


Listing 8.2 ADSP-21msp58/59 Analog Autobuffer Program 

Receive and transmit autobuffering may be independently enabled 
and the two interrupts can occur (and be serviced) independently. This 
allows the use of different data buffer lengths when autobuffering both 
receive and transmit data. It also allows autobuffering to be used on 
only one side, receive or transmit, while the other is serviced at the 
8 kHz interrupt rate. 


wait : 
switch: 

f ill_buf f 1 : 

f ill_buf f 2 : 

done : 

.ENDMOD; 


{10 points to first data buffer} 
{II points to second data buffer} 


{initialize flag register} 

{use II and M0 for tranmsit} 
{use 10 and M0 for receive} 
{enable rev and tx autobuffer} 

= AYO; 

= AX1 ; {power up analog interface} 
{enable analog rx interrupt} 


8-15 



8.5 CIRCUIT DESIGN CONSIDERATIONS 

The following sections discuss interfacing analog signals to the 
ADSP-21msp58/59. 

8.5.1 Analog Signal Input 

Figure 8.6 shows the recommended input circuit for the 
ADSP-21msp58/59's analog input pin (either VINnorm or VIN A ux)- 
The circuit of Figure 8.6 implements a first-order low pass filter (R^Ci). 
The 3 dB point of the filter should be less than 40 kHz. This is the only 
filter that must be implemented external to the processor to prevent 
aliasing of the sampled signal. Since the ADSP-21msp58/59's sigma- 
delta ADC uses a highly oversampled approach that transfers most of 
the anti-aliasing filtering into the digital domain, the off-chip anti- 
aliasing filter need only be of low order. Refer to the ADSP-21msp58/59 
Data Sheet for more detailed information. 

The ADSP-21msp58/59's on-chip ADC PGA (programmable gain 
amplifier) can be used when there is not enough gain in the input 
circuit. The ADC PGA is configured by bits 9 and 0 (IG1, IGO) of the 
processor's analog control register. The gain must be selected to ensure 
that a full-scale input signal (at R| in Figure 8.6) produces a signal level 
at the input to the sigma-delta modulator of the ADC that does not 
exceed V INMAX (which is specified in the data sheet). 



Figure 8.6 Recommended Analog Input Circuit 


8-16 



VINnqrm and VINaux are biased at the internal voltage reference 
(nominally 2.5V) of the ADSP-21msp58/59, which allows the analog 
interface to operate from a single supply. The input signal should be 
ac-coupled with an external capacitor (C 2 ). The value of C 2 is determined 
by the input resistance of the analog input (VINnorm / VINaux)/ 200 kQ, 
and the desired cutoff frequency. The cutoff frequency should be less than 
or equal to 30 Hz. The following equations should be used to determine 
the values for R lr C\, and C 2 : R} should be less than or equal to 2.2 kQ, C 2 
should be greater than or equal to 0.027 jliF, C3 should be equal to C2. 


2n fjR IN 

R in = input resistance of ADSP-21msp58/59 (200 kQ) 
f 1 =cutoff frequency < 30 Hz 

1 

Rl = 2k f 2 C 2 

R a < 2.2 kQ 

20 kHz < f 2 < 40 kHz * 


Ci 


1 

2k f 2 R 1 


C 3 =c 2 


* If minimum (< 0.1 dB) rolloff at 4 kHz is desired, f 2 should be set to 40 kHz. 



8.5.2 Analog Signal Output 

The ADSP-21msp58/59's differential analog output (VOUTp - VOUTn) is 
produced by an on-chip differential amplifier. The differential amplifier 
will meet dynamic specifications for loads greater than 2 kQ (Rp > 2 kQ) 
and has a maximum differential output voltage swing of ±3.156 V peak-to- 
peak (3.17 dBmO). The DAC will drive loads smaller than 2 kQ, but with 
degraded dynamic performance. The differential output can can be 
ac-coupled directly to a load or dc-coupled to an external amplifier. 

Figure 8.7 shows a simple circuit providing a differential output with ac 
coupling. The capacitor of this circuit (Cout) is optional; if used, its value 
can be chosen as follows: 


Cout = 


1 

60tcR l 


The VOUTp - VOUT N outputs must be used as differential outputs; do not 
use either as a single-ended output. Figure 8.8 shows an example circuit 
which can be used to convert the differential output to a single-ended 
output. The circuit uses a differential-to-single-ended amplifier, the 
Analog Devices SSM-2141. 



ADSP-21msp5x 

C OUT 


t- Hh- 

VOUTp 

• — II — 

vout n 

C OUT 



Figure 8.7 Example Circuit For Differential Output With AC Coupling 


8-18 



8 



-12 V _L 

-gnd a 

Figure 8.8 Example Circuit For Single-Ended Output 


8.5.3 Voltage Reference Filter Capacitance 

Figure 8.9 shows the recommended reference filter capacitor connections. 
The capacitor grounds should be connected to the same star ground point 
as that of Figure 8.6. 



Figure 8.9 Voltage Reference Filter Capacitor 


8-19 




System Interface 13 9 


9.1 OVERVIEW 

This chapter describes the basic system interface features of the ADSP-2100 
family processors. The system interface includes various hardware and 
software features used to control the DSP processor. 

Processor control pins include a RESET signal, clock signals, flag inputs and 
outputs, and interrupt requests. This chapter describes only the logical 
relationships of control signals; consult individual processor data sheets for 
actual timing specifications. 


9.2 CLOCK SIGNALS 

The ADSP-2100 family processors may be operated with a TTL-compatible 
clock signal input to the CLKIN pin or with a crystal connected between the 
CLKIN and XTAL pins. If an external clock is used, XTAL must be left 
unconnected. The CLKIN signal may not be halted or changed in frequency 
during operation. 

The ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2111 processors operate 
with an input clock frequency equal to the instruction cycle rate. The 
ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors operate with an 
input clock frequency equal to half the instruction rate; for example, a 
16.67 MHz input clock produces a 33 MHz instruction rate (30 ns cycle time). 
Device timing is relative to the internal clock rate which is indicated by the 
CLKOUT signal. 

Because these processors include an on-chip oscillator circuit, an external 
crystal can be used. The crystal should be connected between the CLKIN and 
XTAL pins, with two capacitors connected as shown in Figure 9.1, which can 
be found on the following page. A parallel-resonant, fundamental frequency, 
microprocessor-grade crystal should be used. The frequency value selected 
for the crystal should be equal to the desired instruction rate for the processor 
(for the ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2111) or half the 
desired instruction rate (for the ADSP-2171, ADSP-2181, and 
ADSP-21 msp58 / 59) . 


9-1 





Figure 9.1 External Crystal Connections 

The internal phased lock loop of the processors generates an internal 
clock which is four times the instruction rate. 

The processors also generate a CLKOUT signal which is synchronized to 
the processors' internal cycles and operates at the instruction cycle rate. A 
phase-locked loop is used to generate CLKOUT and to divide each 
instruction cycle into a sequence of internal time periods called processor 
states. The relationship between the phases of CLKIN, CLKOUT, and the 
processor states is shown in Figure 9.2 for the ADSP-2101, ADSP-2105, 
ADSP-2115, and ADSP-2111 processors. Figure 9.3 shows the same 
information for the ADSP-2171, ADSP-2181, and ADSP-21msp58/59 
processors. The phases of the internal processor clock are dependent upon 
the period of the external clock. 

The CLKOUT output can be disabled on the ADSP-2171, ADSP-2181, and 
ADSP-21msp58/59 processors. This is controlled by the CLKODIS bit in 
the SPORTO Autobuffer Control Register. 


CLKIN 


INTERNAL 

PROCESSOR 

STATE 


CLKOUT 



Figure 9.2 Clock Signals & Processor States (ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111] 


9-2 



CLKIN 




Figure 9.3 Clock Signals & Processor States (ADS P-21 71, ADSP-2181, ADSP-21msp58/59) 

9.2.1 Synchronization Delay 

Each processor has several asynchronous inputs (interrupt requests, for 
example), which can be asserted in arbitrary phase to the processor clock. 

The processor synchronizes such signals before recognizing them. The 
delay associated with signal recognition is called synchronization delay. 

Different asynchronous inputs are recognized at different points in the 
processor cycle. Any asynchronous input must be valid prior to the 
recognition point to be recognized in a particular cycle. If an input does 
not meet the setup time on a given cycle, it is recognized either in the 
current cycle or during the next cycle if it remains valid. 

Edge-sensitive interrupt requests are latched internally so that the request 
signal only has to meet the pulse width requirement. To ensure the 
recognition of any asynchronous input, however, the input must be 
asserted for at least one full processor cycle plus setup and hold time. 

Setup and hold times are specified in the data sheet for each individual 
device. 

9.2.2 1 x & 1 /2x Clock Considerations 

Each processor requires only a IX or 1/2X frequency clock signal. They 
use what is effectively an on-chip phase-locked loop to generate the higher 
frequency internal clock signals and CLKOUT. Because these clocks are 
generated based on the rising edge of CLKIN, there is no ambiguity about 
the phase relationship of two processors sharing the same input clock. 

Multiple processor synchronization is simplified as a result. 


9-3 



Using a IX or 1/2X frequency input clock with the phase-locked loop to 
generate the various internal clocks imposes certain restrictions. The CLKIN 
signal must be valid long enough to achieve phase lock before RESET can be 
deasserted. Also, the clock frequency cannot be changed unless the processor 
is in RESET. Refer to the processor data sheets for details. 


9.3 RESET 

RESET halts execution and causes a hardware reset of the processor. The 
RESET signal must be asserted when the processor is powered up to assure 
proper initialization. 

Tables 92-9.7 show the RESET state of various registers, including the 
processors' on-chip memory-mapped status/ control registers. The values of 
any registers not listed are undefined at reset. The contents of on-chip 
memory are unchanged after RESET, except as shown in Tables 92-9.7 for 
the data-memory-mapped control/ status registers. The CLKOUT signal 
continues to be generated by the processor during RESET, except when 
disabled on the ADSP-2171, ADSP-2181, or ADSP-21msp58/59. 

The contents of the computation unit (ALU, MAC, Shifter) and data address 
generator (DAG1, DAG2) registers are undefined following RESET. 

When RESET is released, the processor's booting operation takes place, 
depending on the state of the processor's MMAP pin. Program booting is 
described in Chapter 10, "Memory Interface." 

For the ADSP-2111, ADSP-2171, and ADSP-21msp58/59 processors, which 
include a host interface port, setting the softwa re reset bit in the HSR7 
register has the same affect as asserting RESET. This allows either the host 
processor or the ADSP-21xx to initiate a reset under software control. 

In a multiprocessing system with several processors, a synchronous RESET is 
required. 


9.4 SOFTWARE-FORCED REBOOTING 

Software-forced reboots can be accomplished in several ways. A software- 
forced reboot clears the context of the processor and initializes some 
registers. A context clear clears the processor stacks and restart execution at 
address 0x0000. Table 9.1 shows the different ways each processor can 
perform a software reboot. 



Description 

Setting the BFORCE bit in the System 
Control Register causes a reboot 


Processor Reboot Method 
ADSP-2101 Boot Force 
ADSP-2105 
ADSP-2111 
ADSP-2115 

ADSP-2171 Boot Force Setting the BFORCE bit in the System 

Control Register causes a reboot 

Powerup Context Reset Setting the PUCR bit in the SPORT1 
Autobuffer & Powerdown Control 
Register causes a reboot on recovery 
from powerdown 

ADSP-2181 BDMA Context Reset Setting the BCR bit in the BDMA 

Control Register before writing to the 
BDMA Word Count Register 
(BWCOUNT) causes a reboot. 
Execution starts after the BDMA reboot 
is completed. 

Powerup Context Reset Setting the PUCR bit in the SPORT1 
Autobuffer & Powerdown Control 
Register causes a reboot on recovery 
from powerdown 

Table 9.1 Software-Forced Rebooting 

Tables 92-9.7 show the state of the processor registers after a software- 
forced reboot. The values of any registers not listed are unchanged by a 
reboot. 

During booting (and rebooting), all interrupts including serial port 
interrupts are masked and autobuffering is disabled. The serial port(s) 
remain active; one transfer — from internal shift register to data register — 
can occur for each serial port before there are overrun problems. 

The timer runs during a reboot. If a timer interrupt occurs during the 
reboot, it is masked. Thus, if more than one timer interrupt occurs during 
the reboot, the processor latches only the first. A timer overrun can occur. 


9-5 



Control Field 

Description 

Reset 

Reboot 

Bus Exchange Register 

PX 

PX register 

undefined 

undefined 

Status Registers 

IMASK 

Interrupt service enables 

0 

0 

ASTAT 

Arithmetic status 

0 

0 

MSTAT 

Mode status 

0 

unchanged 

SSTAT 

Stack status 

0x55 

0x55 

ICNTL 

Interrupt control 

undefined 

unchanged 

IFC 

Interrupt force /clear 

0 

0 

Control Registers (memory-mapped) 

BWAIT Boot memory wait states 

3 

unchanged 

BPAGE 

Boot page 

0 

unchanged 

SPORT1 configure 

Configuration 

1 

unchanged 

SPEO 

SPORTO enable 

0 

unchanged 

SPE1 

SPORT1 enable 

0 

unchanged 

DWATT0-4 

Data memory wait states 

7 

unchanged 

PWAIT 

Program memory wait 

7 

unchanged 

TCOUNT 

Timer count register 

undefined 

operates during reboot 

TPERIOD 

Timer period register 

undefined 

unchanged 

TSCALE 

Timer scale register 

undefined 

unchanged 

Serial Port Control Registers (memory-mapped, one set per SPORT) 


ISCLK 

Internal serial clock 

0 

unchanged 

RFSR, TFSR 

Frame sync required 

0 

unchanged 

RFSW, TFSW 

Frame sync width 

0 

unchanged 

IRFS, ITFS 

Internal frame sync 

0 

unchanged 

INVRFS, INVTFS 

Invert frame sense 

0 

unchanged 

DTYPE 

Companding type, format 

0 

unchanged 

SLEN 

Serial word length 

0 

unchanged 

SCLKDIV 

Serial clock divide 

undefined 

unchanged 

RFSDIV 

RFS divide 

undefined 

unchanged 

Multichannel word enable bits 

undefined 

unchanged 

MCE 

Multichannel enable 

0 

unchanged 

MCL 

Multichannel length 

0 

unchanged 

MFD 

Multichannel frame delay 

0 

unchanged 

INVTDV 

Invert transmit data valid 

0 

unchanged 

RBUF, TBUF 

Autobuffering enable 

0 

0 

TIREG, RIREG 

Autobuffer I index 

undefined 

unchanged 

TMREG, RMREG 

Autobuffer M index 

undefined 

unchanged 

FO (SPORT1 only) 

Flag Out value 

undefined 

unchanged 


Table 9.2 ADSP-2101/ADSP-21 15 State After Reset Or Software Reboot 


9-6 




Control Field 

Description 

Reset 

Reboot 

Bus Exchange Register 

PX 

PX register 

undefined 

undefined 

Status Registers 

IMASK 

Interrupt service enables 

0 

0 

ASTAT 

Arithmetic status 

0 

0 

MSTAT 

Mode status 

0 

unchanged 

SSTAT 

Stack status 

0x55 

0x55 

ICNTL 

Interrupt control 

undefined 

unchanged 

IFC 

Interrupt force/clear 

0 

0 

Control Registers (memory-mapped) 

BWAIT Boot memory wait states 

3 

unchanged 

BPAGE 

Boot page 

0 

unchanged 

SPORT1 configure 

Configuration 

1 

unchanged 

SPE1 

SPORT1 enable 

0 

unchanged 

DWAITO-4 

Data memory wait states 

7 

unchanged 

PWAIT 

Program memory wait 

7 

unchanged 

TCOUNT 

Timer count register 

undefined 

operates during reboot 

TPERIOD 

Timer period register 

undefined 

unchanged 

TSCALE 

Timer scale register 

undefined 

unchanged 

Serial Port 1 Control Registers (memory-mapped) 

ISCLK Internal serial clock 

0 

unchanged 

RFSR, TFSR 

Frame sync required 

0 

unchanged 

RFSW, TFSW 

Frame sync width 

0 

unchanged 

IRFS, ITFS 

Internal frame sync 

0 

unchanged 

INVRFS, INVTFS 

Invert frame sense 

0 

unchanged 

DTYPE 

Companding type, format 

0 

unchanged 

SLEN 

Serial word length 

0 

unchanged 

SCLKDIV 

Serial clock divide 

undefined 

unchanged 

RFSDIV 

RFS divide 

undefined 

unchanged 

RBUF, TBUF 

Autobuffering enable 

0 

0 

TIREG, RIREG 

Autobuffer I index 

undefined 

unchanged 

TMREG, RMREG 

Autobuffer M index 

undefined 

unchanged 

FO 

Flag Out value 

undefined 

unchanged 


Table 9.3 ADSP-2105 State After Reset Or Software Reboot 


9-7 



Control Field 

Description 

Reset 

Reboot 

Bus Exchange Register 

PX 

PX register 

undefined 

undefined 

Status Registers 

IMASK 

Interrupt service enables 

0 

0 

ASTAT 

Arithmetic status 

0 

0 

MSTAT 

Mode status 

0 

unchanged 

SSTAT 

Stack status 

0x55 

0x55 

ICNTL 

Interrupt control 

undefined 

unchanged 

IFC 

Interrupt force/clear 

0 

0 

Control Registers (memory-mapped) 

BWAIT Boot memory wait states 

3 

unchanged 

BP AGE 

Boot page 

0 

unchanged 

SPORT1 configure 

Configuration 

1 

unchanged 

SPEO 

SPORTO enable 

0 

unchanged 

SPE1 

SPORT1 enable 

0 

unchanged 

DWAITO-4 

Data memory wait states 

7 

unchanged 

PWAIT 

Program memory wait 

7 

unchanged 

TCOUNT 

Timer count register 

undefined 

operates during reboot 

TPERIOD 

Timer period register 

undefined 

unchanged 

TSCALE 

Timer scale register 

undefined 

unchanged 

Serial Port Control Registers (memory-mapped, one set per SPORT) 


ISCLK 

Internal serial clock 

0 

unchanged 

RFSR, TFSR 

Frame sync required 

0 

unchanged 

RFSW, TFSW 

Frame sync width 

0 

unchanged 

IRFS, ITFS 

Internal frame sync 

0 

unchanged 

INVRFS, INVTFS 

Invert frame sense 

0 

unchanged 

DTYPE 

Companding type, format 

0 

unchanged 

SLEN 

Serial word length 

0 

unchanged 

SCLKDIV 

Serial clock divide 

undefined 

unchanged 

RFSDIV 

RFS divide 

undefined 

unchanged 

Multichannel word enable bits 

undefined 

unchanged 

MCE 

Multichannel enable 

0 

unchanged 

MCL 

Multichannel length 

0 

unchanged 

MFD 

Multichannel frame delay 

0 

unchanged 

INVTDV 

Invert transmit data valid 

0 

unchanged 

RBUF, TBUF 

Autobuffering enable 

0 

0 

TIREG, RIREG 

Autobuffer I index 

undefined 

unchanged 

TMREG, RMREG 

Autobuffer M index 

undefined 

unchanged 

FO (SPORT1 only) 

Flag Out value 

undefined 

unchanged 

Host Interface Port Registers (memory-mapped) 

HDRO-5 HIP data registers 

undefined 

used during HIP reboot 

HSR6 

HIP status register 

0x0000 

used during HIP reboot 

HSR7 

HIP status register 

0x0080 

unchanged 

HMASK 

HIP interrupt enables 

0 

unchanged 


Table 9.4 ADSP-2111 State After Reset Or Software Reboot 


9-8 



Control Field 

Description 

Reset 

Reboot 

Bus Exchange Register 

PX 

PX register 

undefined 

undefined 

Status Registers 

IMASK 

Interrupt service enables 

0 

0 

ASTAT 

Arithmetic status 

0 

0 

MSTAT 

Mode status 

0 

unchanged 

SSTAT 

Stack status 

0x55 

0x55 

ICNTL 

Interrupt control 

undefined 

unchanged 

IFC 

Interrupt force /clear 

0 

0 

Control Registers (memory-mapped) 

BWAIT Boot memory wait states 

3 

unchanged 

BP AGE 

Boot page 

0 

unchanged 

SPORT1 configure 

Configuration 

1 

unchanged 

SPEO 

SPORTO enable 

0 

unchanged 

SPE1 

SPORT1 enable 

0 

unchanged 

DWAITO-4 

Data memory wait states 

7 

unchanged 

PWAIT 

Program memory wait 

7 

unchanged 

TCOUNT 

Timer count register 

undefined 

operates during reboot 

TPERIOD 

Timer period register 

undefined 

unchanged 

TSCALE 

Timer scale register 

undefined 

unchanged 

ROMENABLE 

Program memory ROM enable 

0 

unchanged 

PDFORCE 

Powerdown force 

0 

unchanged 

PUCR 

Powerup context reset 

0 

unchanged 

XTALDIS 

XTAL pindrive disable 

0 

unchanged 

XTALDELAY 

during powerdown 

Delay startup from powerdown 

0 

unchanged 

(4096 cycles) 

Serial Port Control Registers (memory-mapped, one set per SPORT) 


ISCLK 

Internal serial clock 

0 

unchanged 

RFSR, TFSR 

Frame sync required 

0 

unchanged 

RFSW, TFSW 

Frame sync width 

0 

unchanged 

IRFS, ITFS 

Internal frame sync 

0 

unchanged 

INVRFS, INVTFS 

Invert frame sense 

0 

unchanged 

DTYPE 

Companding type, format 

0 

unchanged 

SLEN 

Serial word length 

0 

unchanged 

SCLKDIV 

Serial clock divide 

undefined 

unchanged 

RFSDIV 

RFS divide 

undefined 

unchanged 

Multichannel word enable bits 

undefined 

unchanged 

MCE 

Multichannel enable 

0 

unchanged 

MCL 

Multichannel length 

0 

unchanged 

MFD 

Multichannel frame delay 

0 

unchanged 

INVTDV 

Invert transmit data valid 

0 

unchanged 

RBUF, TBUF 

Autobuffering enable 

0 

0 

TIREG, RIREG 

Autobuffer I index 

undefined 

unchanged 

TMREG, RMREG 

Autobuffer M index 

undefined 

unchanged 


Table 9.5 ADSP-2171 State After Reset Or Software Reboot (cont. on next page) 


9-9 



FO (SPORT1 only) 

Flag Out value 

undefined 

unchanged 

CLKODIS 

CLKOUT disable 

0 

unchanged 

BIASRND 

MAC biased rounding 

0 

unchanged 

Host Interface Port Registers (memory-mapped) 



HDRO-5 

HIP data registers 

undefined 

used during HIP reboot 

HSR6 

HIP status register 

0x0000 

used during HIP reboot 

HSR7 

HIP status register 

0x0080 

unchanged 

HMASK 

HIP interrupt enables 

0 

unchanged 

Table 9.5 ADSP-2171 State After Reset Or Software Reboot 



Control Field 

Description 

Reset 

Reboot 

Bus Exchange Register 

PX 

PX register 

undefined 

undefined 

Status Registers 

IMASK 

Interrupt service enables 

0 

0 

ASTAT 

Arithmetic status 

0 

0 

MSTAT 

Mode status 

0 

unchanged 

SSTAT 

Stack status 

0x55 

0x55 

ICNTL 

Interrupt control 

undefined 

unchanged 

IFC 

Interrupt force/clear 

0 

0 


Control Registers (memory-mapped) 


BWAIT 

Boot memory wait states 

3 

unchanged 

BP AGE 

Boot page 

0 

unchanged 

SPORT1 configure 

Configuration 

1 

unchanged 

SPE0 

SPORTO enable 

0 

unchanged 

SPE1 

SPORT1 enable 

0 

unchanged 

DWAIT0-4 

Data memory wait states 

7 

unchanged 

PWAIT 

Program memory wait 

7 

unchanged 

TCOUNT 

Timer count register 

undefined 

operates during reboot 

TPERIOD 

Timer period register 

undefined 

unchanged 

TSCALE 

Timer scale register 

undefined 

unchanged 

PDFORCE 

Powerdown force 

0 

unchanged 

PUCR 

Powerup context reset 

0 

unchanged 

XTALDIS 

XTAL pindrive disable 
during powerdown 

0 

unchanged 

XTALDELAY 

Delay startup from powerdown 
(4096 cycles) 

0 

unchanged 


Table 9.6 ADSP-2181 State After Reset Or Software Reboot (cont. on next page) 


9-10 




Serial Port Control Registers (memory-mapped, one set per SPORT) 


ISCLK 

Internal serial clock 

0 

unchanged 

RFSR, TFSR 

Frame sync required 

0 

unchanged 

RFSW, TFSW 

Frame sync width 

0 

unchanged 

IRFS, ITFS 

Internal frame sync 

0 

unchanged 

INVRFS, INVTFS 

Invert frame sense 

0 

unchanged 

DTYPE 

Companding type, format 

0 

unchanged 

SLEN 

Serial word length 

0 

unchanged 

SCLKDIV 

Serial clock divide 

undefined 

unchanged 

RFSDIV 

RFS divide 

undefined 

unchanged 

Multichannel word enable bits 

undefined 

unchanged 

MCE 

Multichannel enable 

0 

unchanged 

MCL 

Multichannel length 

0 

unchanged 

MFD 

Multichannel frame delay 

0 

unchanged 

INVTDV 

Invert transmit data valid 

0 

unchanged 

RBUF, TBUF 

Autobuffering enable 

0 

0 

TIREG, RIREG 

Autobuffer I index 

undefined 

unchanged 

TMREG, RMREG 

Autobuffer M index 

undefined 

unchanged 

FO (SPORT1 only) 

Flag Out value 

undefined 

unchanged 

CLKODIS 

CLKOUT disable 

0 

unchanged 

BIASRND 

MAC biased rounding 

0 

unchanged 

External Memory Control Registers (non-memory-mapped) 
DMOVLAY Data memory overlay select 

0 

unchanged 

PMOVLAY 

Program memory overlay select 

0 

unchanged 

(memory-mapped) 

DWAIT 

Data memory overlay wait states 

0x7 

unchanged 

PWAIT 

Program memory overlay wait states 

0x7 

unchanged 

BMW AIT 

Byte memory wait states 

0x7 

unchanged 

IOWAITO-3 

I/O memory wait states 

0x7 

unchanged 

CMSSEL 

Composite memory select 

OxB 

unchanged 


Programmable Flag Data & Control Registers (memory-mapped) 


PFDATA 

Programmable flag data 

undefined 

unchanged 

PFTYPE 

Programmable flag direction 

0 

unchanged 

DMA Control Registers 
IDMAA 

(memory-mapped) 

IDMA Internal Memory Address 

0x00 

unchanged 

IDMAD 

IDMA Destination Memory Type 

0 

unchanged 

BIAD 

BDMA Internal Memory Address 

0 

0x20* 

BEAD 

BDMA External Memory Address 

0 

0x60* 

BTYPE 

BDMA Transfer Word Type 

0 

unchanged 

BDIR 

BDMA Transfer Direction 

0 

unchanged 

BCR 

BDMA Context Reset 

1 

unchanged 

BWCOUNT 

BDMA Word Count 

0x20 

0* 

BMPAGE 

External Byte Memory Page 

0 

0* 


Table 9.6 ADSP-2181 State After Reset Or Software Reboot 

* These values assume that you have just completed an initial BDMA boot load of the 
ADSP-2181 (MMAP=0 & BMODE=0). For more information on BDMA register contents 
during the boot loading process see Table 9.8. These values will vary with a processor 
reboot (other than initial load), since they depend on the previous values. 


9-11 



Control Field 

Description 

Reset 

Reboot 

Bus Exchange Register 

PX 

PX register 

undefined 

undefined 

Status Registers 

IMASK 

Interrupt service enables 

0 

0 

ASTAT 

Arithmetic status 

0 

0 

MSTAT 

Mode status 

0 

unchanged 

SSTAT 

Stack status 

0x55 

0x55 

ICNTL 

Interrupt control 

undefined 

unchanged 

IFC 

Interrupt force /clear 

0 

0 

Control Registers (memory-mapped) 

BWAIT Boot memory wait states 

3 

unchanged 

BP AGE 

Boot page 

0 

unchanged 

SPORT1 configure 

Configuration 

1 

unchanged 

SPEO 

SPORTO enable 

0 

unchanged 

SPE1 

SPORT1 enable 

0 

unchanged 

DWAITO-4 

Data memory wait states 

7 

unchanged 

PWAIT 

Program memory wait 

7 

unchanged 

TCOUNT 

Timer count register 

undefined 

operates during reboot 

TPERIOD 

Timer period register 

undefined 

unchanged 

TSCALE 

Timer scale register 

undefined 

unchanged 

ROMENABLE 

Program memory ROM enable 

0 

unchanged 

PDFORCE 

Powerdown force 

0 

unchanged 

PUCR 

Powerup context reset 

0 

unchanged 

XTALDIS 

XTAL pindrive disable 

0 

unchanged 

XTALDELAY 

during powerdown 

Delay startup from powerdown 

0 

unchanged 

(4096 cycles) 

Serial Port Control Registers (memory-mapped, one set per SPORT) 
ISCLK Internal serial clock 

0 

unchanged 

RFSR, TFSR 

Frame sync required 

0 

unchanged 

RFSW, TFSW 

Frame sync width 

0 

unchanged 

IRFS, ITFS 

Internal frame sync 

0 

unchanged 

INVRFS, INVTFS 

Invert frame sense 

0 

unchanged 

DTYPE 

Companding type, format 

0 

unchanged 

SLEN 

Serial word length 

0 

unchanged 

SCLKDIV 

Serial clock divide 

undefined 

unchanged 

RFSDIV 

RFS divide 

undefined 

unchanged 

Multichannel word enable bits 

undefined 

unchanged 

MCE 

Multichannel enable 

0 

unchanged 

MCL 

Multichannel length 

0 

unchanged 

MFD 

Multichannel frame delay 

0 

unchanged 

INVTDV 

Invert transmit data valid 

0 

unchanged 

RBUF, TBUF 

Autobuffering enable 

0 

0 

TIREG, RIREG 

Autobuffer I index 

undefined 

unchanged 

TMREG, RMREG 

Autobuffer M index 

undefined 

unchanged 


Table 9.7 ADSP-21msp58/59 State After Reset Or Software Reboot (cont. on next page) 

9-12 



FO (SPORT1 only) 

Flag Out value 

undefined 

CLKODIS 

CLKOUT disable 

0 

BIASRND 

MAC biased rounding 

0 

Host Interface Port Registers (memory-mapped) 


HDRO-5 

HIP data registers 

undefined 

HSR6 

HIP status register 

0x0000 

HSR7 

HIP status register 

0x0080 

HMASK 

HIP interrupt enables 

0 

Analog Autobuffer /Powerdown Registers 


ARBUF 

Receive autobuffer enable 

0 

ATBUF 

Transmit autobuffer enable 

0 

control bits 

Analog autobuffer control bits 

0 


Table 9.7 ADSP-21msp58/59 State After Reset Or Software Reboot 


unchanged 

unchanged 

unchanged 


used during HIP reboot 
used during HIP reboot 
unchanged 
unchanged 


0 

0 

unchanged 


9.41 ADSP-2181 Register Values for BDMA Booting 

The state of some ADSP-2181 registers during reset and rebooting is 
influenced by the MMAP and BMODE pins. If these pins are set for a BDMA 
boot, the values in the BDMA registers change as shown in Table 9.8. 


Register 

Process Description* 

BIAD 

BDMA Internal Memory Address. 

Set for internal address 0. 

BEAD 

BDMA External Memory Address. 

Set for external address 0. 

BTYPE 

BDMA Transfer Word Type. 

Set for 24-bit program memory words. 

BDIR 

BDMA Transfer Direction. 

Set to transfer data from byte memory. 

BMPAGE 

BDMA Page Selection. 

Set to byte memory page 0. 

BWCOUNT 

BDMA Word Count. 

Set to transfer 32 words. 

BMW AIT 

BDMA Port Wait States. 

Set to 7 waits per transfer. 

BCR 

BDMA Context Reset. ** 


Value Before Boot 
0 

0 

0 

0 

0 

0x20 

0x7 

1 


Value After Boot 
0x20 

0x60 

0 

0 

0 

0 

0x7 

1 


Table 9.8 BDMA Registers Before And After Initial Boot Loading 

* Assuming MMAP=0 and BMODE=0 for a BDMA boot. 

** Set to 1 to (a) holdoff instruction execution during BDMA transfer, 

(b) start execution at address PM(0x0000) after BDMA transfer, and 

(c) leave a BDMA interrupt pending. This sequence of events occurs if 
BCR is set before BWCOUNT is written, or after the initial boot. 


9-13 



9.5 EXTERNAL INTERRUPTS 

Each ADSP-2100 family processor has a number of prioritized, individually 
maskable external interrupts which can be either level- or edge-triggered. 
These interrupt request pins are named 1RQ0, IRQ1, and IRQ2. The IRQO and 
IRQ1 pins are only available as the (optional) alternate configuration of 
SPORT1. The configuration of SPORT1 as either a serial port or as interrupts 
(and flags) is determined by bit 10 of the processor's system control register. 

The ADSP-2181 processor additionally has two dedicated level-triggered 
interrupt request pins and one dedicated edge-triggered interrupt request pin; 
these are IRQLO , 1RQL1, and IRQE. 

Internal interrupts, including serial port, timer, host interface port, DMA and 
analog interface interrupts, are discussed in other chapters. Additional 
information about interrupt masking, set up, and operation can be found in 
Chapter 3, "Program Control." 

9.5.1 Interrupt Sensitivity 

Individual external interrupts can be configured in the ICNTL register as 
either level-sensitive or edge-sensitive. 

Level- sensitive interrupts operate by asserting the interrupt request line 
(IRQx) until the request is recognized by the processor. Once recognized, the 
request must be deasserted before unmasking the interrupt so that the DSP 
does not continually respond to the interrupt. 

In contrast, edge-triggered interrupt requests are latched when any high-to- 
low transition occurs on the interrupt line. The processor latches the interrupt 
so that the request line may be held at any level for an arbitrarily long period 
between interrupts. This latch is automatically cleared when the interrupt is 
serviced. Edge-triggered interrupts require less external hardware than level- 
sensitive requests since there is never a need to hold or negate the request. 
With level-sensitive interrupts, however, many interrupting devices can share 
a single request input; this allows easy system expansion. 

An interrupt request will be serviced if it is not masked (in the IMASK 
register) and a higher priority request is not pending. Valid requests initiate 
an interrupt servicing sequence that vectors the processor to the appropriate 
interrupt vector address. The interrupt vector addresses for each family 
processor are given in Appendix D. There is a synchronization delay 
associated with both external interrupt request lines and internal interrupts. 



If an interrupt occurs during a waitstated external memory access or during the 
extra cycles required to execute an instruction that accesses external memory 
more than once, it is not recognized between the cycles, only before or after. 
Edge-sensitive interrupts are latched, but not serviced, during bus grant (BG) 
unless the GO mode is enabled. 

In order to service an interrupt, the processor must be running and executing 
instructions. The IDLE instruction can be used to effectively halt processor 
operations while waiting for an interrupt. 

Edge-sensitive and level-sensitive interrupt requests are serviced similarly. 
Edge-sensitive interrupts may remain active (low) indefinitely, while level- 
sensitive interrupts must be deasserted before the RTI instruction is executed; 
otherwise, the same interrupt immediately recurs. 

Care must be taken with the serial port (SPORT1) that can be configured for 
alternate functions (IRQO and IRQ1). If the RFS1 or TFS1 input is he ld low when 
SPORT1 is configured as the serial port and then is reconfigured as IRQO and 
IRQ1, an interrupt request can be generated. This interrupt request can be 
cleared with the use of the IFC register. 


9.6 FLAG PINS 

All ADSP-21xx processors provide flag pins. The alternate configuration of 
SPORT1 includes a Flag In (FI) pin and a Flag Out (FO) pin. The configuration 
of SPORT1 as either a serial port or as flags and interrupts is selected by bit 10 
of the processor's system control register. 

FI can be used to control program branching, using the IF FLAGJOM and IF 
NOT FLAG_IN conditions of the fUMP and CALL instructions. These 
conditions are evaluated based on the last state of the FI pin; FLAG JN is true if 
FI was last sampled as a 1 and false if last sampled as a 0. FO can be used as a 
general purpose external signal. The state of FO is also available as a read-only 
bit of the SPORT1 control register. 

The ADSP-2111, ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors 
have three additional flag output pins: FLO, FL1 and FL2. These flags (and FO) 
can be controlled in software to signal events or conditions to any external 
device such as a host processor. The Modify Flag Out instruction, which is 
conditional, can perform SET, RESET and TOGGLE actions — this instruction 
allows programs executing on the DSP processor to control the state of its flag 
output pins. Note that if the condition in the Modify Flag Out instruction is CE 
(counter expired), the counter is not decremented as in other IF CE instructions. 



Flag outputs FL0JFL1 and FL2 are set to 1 at RESET. The Flag Out (FO) is 
not affected by RESET. 

The ADSP-2181 has eight additional general-purpose flag pins, PF7-0. 
These flags can be programmed as either inputs or outputs; they default to 
inputs following reset. The PFx pins are programmed with the use of two 
memory-mapped registers. The Programmable Flag & Composite Select 
Control Register determines the flag direction: l=output and 0=input. The 
Programmable Flag Data Register is used to read and write the values on 
the pins. Data being read from a pin configured as an input is 
synchronized to the processor's clock. Pins configured as outputs drive 
the appropriate output value. When the PFDATA register is read, any 
pins configured as outputs will read back the value being driven out. 


Programmable Flag & Composite Select Control 


15 14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 


3 

2 

1 

0 

i&si 1 

0 1 

1 

1 

71 

1 1 

i l 

0 

1 1 

1 

1 

0 

1 

0 

1 

0 

1 

0 

T 

0 

1 

0 

1 

0 

71 

11111 l 

| 

_J 

| IQM | 

BMj 

jJJMj 

PM 


I 

l 

1— , 

J. 


1 

1 

L_J 


DM(0x3FE6 


BMWAIT 

CMSSEL 


1 = Enable CMS 


0 = Disable CMS 


PFTYPE 
1 = Output 
0 = Input 


Figure 9.4 Programmable Flag & Composite Select Control Register (ADSP-2181) 


9-16 




Programmable Flag Data 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


D 







1 1 1 1 1 1 1 

1 L_l 1 i L_ 


DM(0x3FE5) 


-PFDATA 


Figure 9.5 Programmable Flag Data Register (ADSP-2181) 


9.7 POWERDOWN 

The ADSP-2171, ADSP-2181, and ADSP-21msp58/59 provide a 
powerdown feature that allows the processor to enter a very low power 
dormant state through hardware or software control. In this CMOS 
standby state, power consumption is less than 1 mW (approximate). (Refer 
to the processor data sheet for exact power consumption specifications.) 

The powerdown feature is useful for applications where power 
conservation is necessary, for example in battery-powered operation. 
Features of powerdown include: 

• Internal clocks are disabled 

• Processor registers and memory contents are maintained 

• Ability to recover from powerdown in less than 100 CLKIN cycles 

• Ability to disable internal oscillator when using crystal 

• No need to shut down clock for lowest power when using external 
oscillator 

• Interrupt support for executing "housekeeping" code before entering 
powerdown and after recovering from powerdown 

• User selectable powerup context 


9-17 




Even though the processor is put into the powerdown mode, the lowest 
level of power consumption still might not be achieved if certain 
guidelines are not followed. Lowest possible power consumption requires 
no additional current flow through processor output pins and no 
switching activity on active input pins. Therefore, a careful analysis of pin 
loading in your circuit is required. The following sections detail the 
proper powerdown procedure as well as provide guidelines for clock and 
output pin connections required for optimum low-power performance. 

9.7.1 Powerdown Control 

You can control several parameters of powerdown operation through 
control bits in the SPORT1 Autobuffer /Powerdown Control Register 
(or Analog Autobuffer /Powerdown Control Register on the 
ADSP-21msp58/59). This control register is memory-mapped at location 
0x3FEF and is shown in Figure 9.6. 


SPORT1 Autobuffer / Powerdown Control Register 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


t — i — — i — — i — i — — r 
i i I i I i i I i 


DM(0x3FEF) 


XTALDIS 1 

XTAL Pin Drive Disable During Powerdown 
1=disabled, 0=enabled 
(XTAL pin should be disabled when 
no external crystal is connected) 

XTALDELAY 

Delay Startup From Powerdown 4096 Cycles 
1=delay, 0=no delay 
(use delay to allow internal phase locked 
loop or external oscillator to stabilize) 

PDFORCE 

Powerdown Force 
1=force processor to vector to 
powerdown interrupt 

PUCR 

Powerup Context Reset 
1=soft reset (clear context)*, 
0=resume execution 


Figure 9.6 SP0RT1 Autobuffer / Powerdown Control Register 

* PUCR=1: Clears the PC, STATUS, LOOP and CNTR stacks. IMASK and ASTAT 
registers are cleared to 0 and SSTAT is set to 0x55. The processor will start executing 
instructions from address 0x0000. 


9-18 




9.7.2 Entering Powerdown 

The powerdown sequencers defined as follows. 

1. ) Initiat e the p owerdown sequence by applying a high-to-low transition 

to the PWD pin or by setting the powerdown force control bit 
(PDFORCE) in the SPORT1 Autobuffer /Powerdown Control Register. 

2. ) The processor vectors to the non-maskable powerdown interrupt 

vector at address 0x002C. (Note: The powerdown interrupt is never 
masked. You must be careful not to cause multiple powerdown 
interrupts to occur or stack overflow may result. Multiple powerdown 
interrupts can occur if the PWD input is pulsed while the processor is 
already servicing the powerdown interrupt.) 

3. ) Any number of housekeeping instructions, starting at location 0x002C, 

can be executed prior to the processor entering the powerdown mode. 
Typically, this section of code is used to configure the powerdown 
state, disable on-chip peripherals and clear pending interrupts. 

4. ) The processor now enters powerdown mode when it executes an IDLE 

instruction (while PWD is asserted). The processor may take either one 
or two cycles to power down depending upon internal clock states 
during the execution of the IDLE instruction. All register and memory 
contents are maintained while in powerdown. Also, all active outputs 
are held in whatever state they are in before going into powerdown. 

If an RTI is executed before the IDLE instruction, then the processor 
returns from the powerdown interrupt and the powerdown sequence is 
aborted. 

While the processor is in the powerdown mode, the processor is in CMOS 
standby. This allows the lowest level of power consumption where most 
input pins are ignored. Active inputs need to be held at CMOS levels to 
achieve lowest power. More information can be found in the section 
"Operation During Powerdown" later in this chapter. 




9.7.3 Exiting Powerdown 

The powerdown mode can be exited with the use of the PWD pin or with 
RESET. There are also several user-selectable modes for start-up from 
powerdown which specify a start-up delay as well as specify the program 
flow after start-up. This allows the program to resume from where it left 
off before powerdown or for the program context to be cleared. 


9. 7.3. 1 Ending Powerdown With The PWD Pin 

Applying a low-to-high transition to the PWD pin will take the processor 
out of powerdown mode. You have the option of selecting the amount of 
time the processor takes to come out of the powerdown mode with the 
"delay start-up from powerdown" control bit (XTALDELAY, bit 14 in the 
Powerdown Control Register.) If this bit is cleared to 0, no additional 
delay over the quick start-up (100 cycles) is introduced. If this bit is set to 
1, a delay of 4096 cycles is introduced. The delay feature is used 
depending upon the state of an external clock oscillator at the time of 
powerup or if the internal clock is disabled. This is further discussed in the 
sections "Systems Using an External TTL/ CMOS Clock" and "Systems 
Using a Crystal and The Internal Oscillator." 

You can also program one of two options directing the processor how to 
resume operation. The context for exiting powerdown is set by bit 12 
(PUCR, powerup context reset) of the Powerdown Control Register. 

If the PUCR control bit is cleared to 0, the processor will continue to 
execute instructions following the IDLE instruction. For example, a high- 
to-low transition is applied to the PWD pin which causes the processor to 
vector to the powerdown interrupt routine. In this routine, a few 
housekeeping tasks are performed and the IDLE instruction is executed. 
The processor powers down. Some time later a low-to-high transition is 
applied to the PWD pin, causing the processor to exit powerdown mode. 
Since the PUCR bit is 0, the processor resumes executing instructions in 
the powerdown interrupt routine, starting at the instruction following the 
IDLE instruction. When an RTI instruction is encountered, control then 
passes back to the main routine. 

If the PUCR bit is set to 1 for a clear context, the processor resumes 
operation from powerdown by clearing the PC, STATUS, LOOP and 
CNTR stacks. The IMASK and ASTAT registers are set to 0 and the SSTAT 
goes to 0x55. The processor will start executing instructions from address 
0x0000. 


9-20 



9. 7.32 Ending Powerdown With The RESET Pin 

If RESET is asserted while the processor is in the powerdown mode, the 
processor is reset and instructions are executed from address 0x0000. A 
boot is performed if the MMAP pin is set to 0. If the RESET pin is used to 
exit powerdown, then it must be held low for the appropriate number of 
cycles. If the clock is stopped at powerup or operating at a different 
frequency at powerup than it was before powerdown, RESET must be 
held long enough for the oscillator to stabilize plus an additional 1000 
CLKIN cycles for the phase locked loop to lock. The time required for the 
oscillator to stabilize depends upon the type of crystal used and 
capacitance of the external crystal circuit. Typically 2000 CLKIN cycles is 
adequate for clock stabilization time. 

If the clock was not stopped at powerup and is at a stab le frequ ency at 
powerup (same as before powerdown), only 5 cycles of RESET are 
required. 

When ending powerdown with RESET, the XTALDELAY (delay start-up 
from powerdown) control bit is ignored. 

9.7.4 Startup Time After Powerdown 

The time required to exit the powerdown state depends on whether an internal 
or external oscillator is used, and the method used to exit powerdown. 

9. 7.4. 1 Systems Using An External TTL/CMOS Clock 

When the processor is in powerdown, the external clock signal is ignored if the 
XTALDIS bit (XTAL pin disable) of the Powerdown Control Register is set to 1. 
It is therefore not necessary to stop the external clock since no power is wasted 
while the external clock is running. If the external clock is to be stopped 
anyway, it must be kept running for (at least) one additional cycle after the 
IDLE instruction is executed. 

The XTALDIS bit should always be set before entering powerdown. This 
specifies that the XTAL pin is not to be driven by the processor. During 
powerdown there is no need to drive the XTAL pin when an external oscillator 
is used. Disabling the XTAL pin drive during powerdown lets the input clock 
run without wasting power. 

After the pr ocessor is taken out of the powerdown mode by either the 
PWD pin or RESET, it will begin executing instructions after a maximum 
start-up time of 100 CLKIN cycles as long as the clock oscillator is stable 
and at the same frequency as before powerdown. 



If the external clock is unstable when the processor exits powerdown, then 
the XTALDELAY control bit can be used. This allows time for the external 
clock to stabilize by inserting an additional 4096-cycle delay before the 
processor starts to execute instructions. The start-up delay can only be used 
when the processor is taken out of powerdown mode with the PWD pin. 

If the processor is taken out of powerdown by RESET and the clock is stable 
and at the same frequency as before powerdown, RESET needs to be held for 
only 5 cycles. 

9. 7.4.2 Systems Using A Crystal And The Internal Oscillator 

A trade-off can be made so that a fast start-up is possible, but power is 
consumed by leaving the oscillator running during powerdown. If a fast 
start-up is desired, then you must clear bits 14 (XTALDELAY) and 15 
(XTALDIS) of the Powerdown Control Register to 0 before entering 
powerdown. This selects no additional delay after start-up from powerdown 
and drives the external crystal during powerdown. In this configuration, the 
oscillator will continue to operate and the processor will start executing 
inst ructio ns in less than 100 cycles after the low to high signal transition at 
the PWD pin. The XTAL pin will also be driven and the powerdown power 
consumption will be higher than the 1 mW specification. The following code 
example shows the powerdown interrupt routine. 

{ Sample Powerdown Code } 

{ Located at interrupt vector address 0x0 02C } 

pwd_int: axO = 0x0000; { enable crystal, no delay } 
dm(0x3FEF) = axO; 
idle; 
rti ; 

If lowest possible power consumption is required, then you must set the 
XTALDELAY and XTALDIS bits to 1 before entering powerdown. This selects 
the additional 4096 cycle delay to allow the oscillator to start and the phase 
locked loop to lock after start-up and disables the drive to the XTAL pin 
during powerdown. The following code example shows the powerdown 
interrupt routine. 

{ Sample Powerdown Code } 

{ Located at interrupt vector address 0x002C } 

pwd_int: axO = OxCOOO; { disable crystal, delay } 
dm(0x3FEF) = axO; 
idle; 
rti ; 



Depending on the particular situation and external system conditions, the 
powerdown modes shown above could be set conditionally. If you want 
to powerdown for a long time you may want to set the mode for lowest 
power consumption. If you want to powerdown for a short time, lowest 
power consumption may not be that important. 

If the RESET pin is us ed to exit powerdown and the clock has been 
stopped, then RESET must be held low for 1000 CLKIN cycles plus the 
time required for the phase locked loop to lock and the crystal oscillator to 
stabilize (typic ally 200 0 CLKIN cycles.) If the clock is running during 
powerdown, a RESET signal of only 5 cycles is required. 

9.7.5 Processor Operation During Powerdown 

Some processor circuitry may still be active during powerdown mode. 
Also, some output pins remain active. A good understanding of these 
states will allow you to determine the best low-power configuration for 
your system. By keeping output loading and input switching to a 
minimum the lowest possible power consumption can be achieved. 

9. 7.5. 1 Interrupts And Flags 

Interrupts are latched and can be serviced if the processor exits 
powerdown without a context reset (PUCR=1). Any activity on the 
interrupt or flag input pins during powerdown will increase the power 
consumption. There should also be no resistive load on the flag output 
pins (as with any active output pin) if lowest power is desired. 

9.7.5.2 SPORTS 

The circuitry of the serial ports is not directly affected by powerdown. The 
SPORTs are indirectly affected if an internally generated SCLK or frame 
sync is required. SPORT circuitry continues to operate during 
powerdown. 

It is possible to clock data into or out of the serial ports during 
powerdown. You must supply an external serial clock to support 
operation during powerdown. No interrupts or autobuffer operations will 
be serviced during powerdown. Instead, the SPORT interrupts are latched 
and can be serviced if the processor exits powerdown without resetting 
the processor. Data clocked into the processor will remain in the receive 
(RX) registers. Autobuffer transfers will occur after t he devi ce exits 
powerdown if the processor is not powered up with RESET. Note that any 
SPORT activity will increase the power consumption above the 1 mW 
specification. 


9-23 




If an external serial clock and an external frame sync signal are supplied, 
data can be clocked into the RX register or out of the TX register during 
powerdown. Since the TX register can not be updated while the processor 
is in powerdown, the same value is repeatedly clocked out the serial port. 
Also, data in the RX register is continually overwritten since the RX 
register can not be read by the processor during powerdown. 

If an external serial clock is used with an internal frame sync, frame sync 
signals continue to be generated during powerdown since they are 
derived from the serial clock. Data bits continue to be received with the 
RX register being overwritten. Since data is only transmitted when the TX 
register is written, data bits are only transferred out of the processor if the 
processor is put in powerdown during a serial port transfer. While the 
processor is being put into powerdown, the serial port transfer in progress 
is allowed to complete. Since an internally generated transmit frame sync 
is used, no subsequent frame syncs are generated while in powerdown. 

If internal serial clock is used, there is no SPORT activity during 
powerdown; the serial clock stops. 

Lowest power dissipation is achieved when active SPORT pins are not 
changing during powerdown and are held at CMOS levels. 

97.5.3 HIP During Powerdown 

The circuitry of the Host Interface Port (HIP) is not directly affected by 
powerdown on the ADSP-2171 and ADSP-21msp58/59. The HIP is 
indirectly affected since the processor, when in powerdown, is unable to 
service interrupts or read and write HIP data registers. HIP circuitry 
continues to operate during powerdown. 

The host can write to the HIP register during powerdown but the 
processor is disabled and cannot service interrupts. Instead, HIP 
interrupts are latched and can be serviced if the processor exits 
powerdown without a context reset (PUCR=1). 

If the HDR overwrite bit (bit 7 in HSR7) is cleared, a host acknowledge 
signal will not be asserted until the processor has read data written by the 
host. During powerdown, the processor is unable to read the data register 
and the host acknowledge signal will not be asserted. Care must be taken 
in a system where the host waits for a host acknowledge. In this case, it is 
possible that the host will "hang" waiting for the acknowledge while the 
DSP processor is in powerdown. 


9-24 




While in powerdown, the processor can be reset by writing the HSR _____ 
software reset bit. This will produce the same results as asserting the RESET 
pin for five cycles (minimum RESET pulse) on the processor. If an external 
crystal is used and the clock has been stopped, this reset duration is too 
short; therefore software reset cannot be used in this mode. Note that any 
HIP activity will increase the power consumption above the 1 mW 
specification. 

Two mode pins, HMDO and HMD1, are used to put the processor's HIP into 
one of four possible modes. When HMDO = 1, the HIP data bus is 
multiplexed for both address and data. In this case, the HIP data bus inputs 
are active during powerdown and any bus activity will result in higher 
power dissipation. Also, inputs must be at CMOS levels. If this host mode is 
used and there is potential for the bus to be floating, pull-up resistors 
should be used on the data lines. If you desire the host to communicate with 
other devices on the bus while the DSP processor is in powerdown, HMDO 
should be held low to avoid extra power to be dissipated. When the HIP is 
put in other modes where data inputs are not active this is not a problem. 

Lowest power dissipation is achieved when the HIP pins are not changing 
during powerdown and are held at CMOS levels. 

9J.5.4 IDMA Port During Powerdown (ADSP-2181) 

The IDMA port can receive data during powerdown, but it can not respond 
with an acknowledge (IACK) signal or increment the IDMA internal 
address. If you are using a short read or short write and are in the middle of 
an IDMA transfer, you can complete a single read or write while the 
processor is in powerdown. If you are using the long read or long write 
method and are in the middle of an IDMA transfer, your host must be able 
to handle a "timeout" condition, as the DSP will not return an acknowledge 
to the transfer in process. 

Note that IDMA activity while the DSP is in powerdown uses power and 
should be avoided to conserve power. For more information on lowest 
power use, see "Conditions For Lowest Power Consumption." 


9-25 



9. 7.5.5 BDMA Port During Powerdown (ADSP-2181) 

Do not powerdown the ADSP-2181 during a BDMA transfer. If you do, the DSP 
will not be able to recover correctly from powerdown and the contents of 
memory accessed by the ADSP-2181's BDMA port will be corrupted. 

If you need to go into powerdown mode, either: 

• Verify that the BWCOUNT register contains a zero. If a BDMA transfer is in 
process, poll the BWCOUNT register to determine when the transfer is done. 

or 

• Abort any BDMA transfer in progress by writing 1 to the BWCOUNT 
register and go into powerdown when the BWCOUNT register contains a 
zero. (Note that the BDMA transfer is not properly completed in this case.) 

9.7. 5.6 Analog Interface (ADSP-21msp5x) 

You must powerdown the ADSP-21msp58/59 , s analog interface separately 
from the processor, as described in the Analog Interface chapter of this manual. 
The analog interface does not work during powerdown and causes additional 
power to be dissipated if it is not disabled. The following code example shows 
a powerdown interrupt routine for the ADSP-21msp58/59: 

{ Sample Powerdown Code } 

{ located at address 0x002C } 

pwd_int : axO = 0x0000; (powerdown analog interface} 

dm (0x3 FEE) = axO; 

axO = 0x0000; (enable crystal, no delay} 

dm(0x3FEF) = axO; 

NOP; 
idle; 
rti ; 

It takes three cycles for the analog interface to powerdown. The IDLE 
instruction should not be executed before these three cycles have elapsed. 

9.7.6 Conditions For Lowest Power Consumption 

The state of all processor pins during powerdown is shown in Table 9.9. 

To assure the lowest power consumption, all active input pins should be held 
at a CMOS level. All active output pins should be free of resistive load since 
load current will increase power dissipation. Some pins will be in one of 



several states depending upon the connection of mode pins. For example, 
the ADSP-2171's HIP data bus pins may be either active or inactive 
depending whether a host write is in progress or how the host mode pins 
are connected. You must perform a careful analysis of each input and 
output pin in order to insure lowest power dissipation. 

Some inputs are active but ignored. The state of these inputs does not 
matter as long as they are at a CMOS level. 


Pin 

Direction 

State During Powerdown 

RESET 

I 

Active 

EWD 

I 

Active 

IKQ2 

I 

Active, latched but not serviced 

IKQE 

I 

( AD SP -2181 ) Active, latched but not serviced 

1RQL0 

I 

( ADSP-2181 ) Active, latched but not serviced 

1RQL1 

I 

( ADSP-2181 ) Active, latched but not serviced 

MMAP 

I 

Active 

ER 

I 

Active, no response until after powerdown 

m 

O 

Driven HIGH unless bus is granted 

CLKIN 

I 

Input buffer inactive, but XTAL oscillator is active unless XTALDIS bit is set 

CLKOUT 

o 

Driven HIGH 

XTAL 

o 

Driven HIGH if XTALDIS set, inversion of CLKIN otherwise 

PWDACK 

o 

Driven HIGH 

FM5 

o 

Driven HIGH, high impedance if bus granted 

DM5 

o 

Driven HIGH, high impedance if bus granted 

BM5 

o 

Driven HIGH, high impedance if bus granted 

IOM5 

o 

( ADSP-2181 ) Driven HIGH, high impedance if bus granted 

CMS 

o 

( ADSP-2181 ) Driven HIGH, high impedance if bus granted 

RD 

o 

Driven HIGH, high impedance if bus granted 

WK 

o 

Driven HIGH, high impedance if bus granted 

ADDR<13:0> 

o 

High impedance 

DATA<23:0> 

I 

Inactive 

DATA<23:0> 

o 

High impedance 

SCLKO 

I 

Active 

SCLKO 

o 

Driven to static level if internal, high impedance otherwise 

TFSO 

I 

Active if SPORT 0 is enabled 

TFSO 

o 

Driven if configured internal or in multichannel mode and SPORT 0 
enabled, high impedance otherwise 

RFSO 

I 

Active if SPORT 0 is enabled 

RFSO 

o 

Driven if configured internal and SPORT 0 enabled, high impedance 
otherwise 

DRO 

I 

Active if SPORT 0 is enabled 

DTO 

o 

Driven if serial port operating. Output may be static or changing depending 
upon serial clock, high impedance otherwise 


Table 9.9 Pin States During Powerdown (cont. on next page) 


9-27 




Pin Direction 

State During Powerdown 

SCLK1 

I 

Active 

SCLK1 

O 

Driven to a static level if internal, high impedance otherwise 

TFS1/IKQT 

I 

Active if SPORT 1 is enabled or configured alternate (IRQl) 

TFS1 

O 

Driven if SPORT 1 is enabled and configured for internal transmit framing, 
high impedance otherwise 

RFS1/IKQU 

I 

Active if SPORT 1 is enabled or configured alternate (IRQO) 

RFS1 

O 

Driven if SPORT 1 is enabled and configured for internal receive framing, 
high impedance otherwise 

DR1/FLAGIN 

I 

Active if SPORT 1 is enabled or configured alternate (FLAGIN) 

DT1/FLAGOUT 

o 

Driven if serial port operating. Output may be static or changing depending 
upon serial clock. Driven if SPORT 1 is enabled or configured alternate 
(FLAGOUT) 

FL<2:0> 

o 

Driven to previous value 

PF<7:0> 

I/O 

( ADSP-2181 ) Active 

BMODE 

I 

Active 

IKD 

I 

( ADSP-2181 ) Active, if 15 asserted 

IWR 

I 

( ADSP-2 181) Active, if 15 asserted 

15 

I 

(. ADSP-2181 ) Active 

IAL 

I 

( ADSP-2181 ) Active, if 15 asserted 

IAD 

I/O 

( ADSP-2181 ) Active, if an operation in progress 

IACK 

o 

C ADSP-2181 ) Active 

HSIZE 

I 

(ADSP-2171, ADSP-21msp5x) Active 

HMDO 

I 

( ADSP-2171 , ADSP-21 msp5x) Active . 

HMD1 

I 

( ADSP-2171 , ADSP-21msp5x) Active 

HSEL 

I 

( ADSP-2171 , ADSP-21msp5x ) Active 

HRD 

I 

( ADSP-2171 , ADSP-21msp5x ) Active 

HWR 

I 

( ADSP-2171 , ADSP-21msp5x ) Active 

HADR<2:0> 

I 

( ADSP-2171 , ADSP-21msp5x) Active 

HDATA<15:0> 

I 

(. ADSP-2171 , ADSP-21msp5x ) Active if host writing or HMD1 and 
HA2/HALE HIGH, inactive otherwise 

HDATA<15:0> 

o 

(ADSP-2171, ADSP-21msp5x ) Driven if host reading, high impedance otherwi 

HACK 

o 

(. ADSP-2171 , ADSP-21msp5x ) Driven 

VIN (NORM) 

I 

(ADSP-21msp5x) Inactive, set analog powerdown bit 

VIN (AUX) 

I 

(ADSP-21msp5x) Inactive, set analog powerdown bit 

VFB (NORM) 

o 

(. ADSP-21msp5x ) Inactive, set analog powerdown bit 

VFB (AUX) 

o 

(ADSP-21msp5x) Inactive, set analog powerdown bit 

VOUTP 

o 

(ADSP-21msp5x) Driven low in powerdown 

VOUTN 

o 

(ADSP-21msp5x) Driven low in powerdown 

VREF 

o 

(ADSP-21msp5x) Reference turned off 


Table 9.9 Pin States During Powerdown 


9-28 




9.7.7 PWDACK Pin 

The powerdown acknowledge pin (PWDACK) is an output that indicates 
when the processor is powered down. This pin is driven high by the 
processor when it has powered down and is driven low when the 
processor has completed its powerup sequence. A low level on the 
PWDACK pin also indicates that there is a valid CLKOUT signal and that 
instruction execution has begun. Figure 9.7 shows an example of timing 
for the powerdown and restart sequence. 

The processor is executing code when the PWD pin is brought low. The 
processor vectors to the powerdown interrupt vector and an IDLE 
instruction is executed causing the processor to go into powerdown. The 
CLKOUT and PWDACK signals are driven high by the processor. At this 
point, the input clock pin is ignored. If the processor is put into the 
powerdown mode via the powerdown force bit in the powerdown control 
register, the result is the same as described above. 

The input clock is started and the PWD pin is brought high. After the 
necessary start-up cycles the processor brings the PWDACK output low, 
begins driving the CLKOUT pin with a clock signal and begins to fetch the 
instruction after the IDLE instruction. The processor then resumes normal 
operation. 


clkin JWMirniwm- - - wimm 1 - -imm 

PWD 

PWDACK 

CLKOUT juimuiimjuYU — ~ --- iTmiLr 

- RUN 

K 
I h- 


RUN 


PWRDWN _►! 


PENDING 
EXECUTE IDLE 


POWERED 

DOWN 


- START CLK 

DOWN 

| FINISH IDLE - 

NOP WHILE FETCHING INSTRUCTION FOLLOWING IDLE 


Figure 9.7 Powerdown Timing Example 



9-29 



When powerdown is terminated with the RESET pin or if a start-up delay 
is selected, a low level on the PWDACK pin only indicates the start of 
oscillations on the CLKOUT pin. It will not necessarily indicate the start of 
instruction execution. 

The state of PWDACK and also the CLKOUT signal is undefined during 
the first 100 cycles of initial reset. 

9.7.8 Using Powerdown As A Non-Maskable Interrupt 

The powerdown interrupt is never masked. It is possible to use this 
interrupt for other purposes if desired. The processor will not go into 
powerdown until an IDLE instruction is executed. If an RTI is executed 
before the IDLE instruction, then the processor returns from the 
powerdown interrupt and the powerdown sequence is aborted. 

It is possible to place a series of instructions at the powerdown interrupt 
vector location 0x002C. This routine should end with an RTI instruction 
and not contain an IDLE instruction if the interrupt is to be used for 
purposes other than powerdown. 



Memory Interface B 10 


10.1 OVERVIEW 

The ADSP-2100 family has a modified Harvard architecture in which data 
memory stores data and program memory stores both instructions and 
data. Each processor contains on-chip RAM and/or ROM, so that a 
portion of the program memory space and a portion of the data memory 
space reside on-chip. Each processor (except the ADSP-2181) also has a 
boot memory space in addition to the data and program spaces. The 
ADSP-2181 has a byte memory space instead of the boot memory space. 
The boot memory space and byte memory space can be used to load on- 
chip program memory with code from an external EPROM at reset. 

In each ADSP-2100 family device, memory is connected with the internal 
functional units by four on-chip buses: the data memory address bus 
(DMA), data memory data bus (DMD), program memory address bus 
(PMA), and program memory data bus (PMD). The internal PM A bus and 
DMA bus are multiplexed into a single address bus which is extended off- 
chip. Likewise, the internal PMD bus and DMD bus are multiplexed into a 
single external data bus. The sixteen MSBs of the external data bus are 
used as the DMD bus: external bus lines D„ . are used for DMD 1C .. 

There are three separate memory spaces: data memory, program memory 
and boot (or byte) memory. The PMS, DM5, and BMS signals indicate 
which memory space is being accessed. Because the program memory and 
data memory buses are multiplexed off-chip, if more than one external 
transfer must be made in the same instruction there will be an overhead 
cycle required. There is no overhead if just one off-chip access (with no 
wait states) occurs in any instruction. Figure 10.1 shows the external 
memory buses and control signals (for all ADSP-21xx processors except 
the ADSP-2181). 

All external memories may have automatic wait state generation 
associated with them. The number of wait states — each equal to one 
instruction cycle — is programmable. 


10-1 




This chapter includes example timing diagrams for the memory interfaces 
of the ADSP-21xx processors. For each bus transaction, only the sequence 
of events is described; you must consult the processor data sheets for 
actual timing parameters. All timing diagrams use CLKOUT as a 
reference, which indicates the instruction execution rate. 

The memory interfaces of the ADSP-2181 are described separately in the 
second half this chapter. 


lx CLOCK 
or 

CRYSTAL 


SERIAL 

DEVICE 

(OPTIONAL) 






SERIAL 

DEVICE 

(OPTIONAL) 




< — ► 


ADSP-21 xx 


CLKIN 

XTAL 

CLKOUT 


RESET 

IRQ2 

BR 

BG 

MMAP 


ADDR 13 _q 

data 2 3_o 

BMS 


K=^ 


SPORT 1 

SCLK1 

RFS1 or IRQO 
TFS1 or IRQ1 
DTI or FO 
DR1 or FI 


RD 

WR 


SPORT 0 

SCLKO 

RFSO 

TFSO 

DTO 

DRO 


PMS 

DMS 


/V /V 




24. 


ft 


*13-0 k 

P 23-22 > Q y 




'15-8 


ADDR 

BOOT 


MEMORY 

DATA 

e.g. EPROM 


2764 

OE 

27128 


27256 

CS 

27512 




*13-0 


5f 






ADDR 

PROGRAM 

DATA 

MEMORY 

OE 

WE 

(OPTIONAL) 

CS 



ADDR 

DATA 

DATA 

MEMORY 


& 

OE 

WE 

PERIPHERALS 

CS 

(OPTIONAL) 


NOTES 

1. Applies to all ADSP-21xx processors except ADSP-2181. 

2. ADSP-21 71 and ADSP-21 msp58/59 use a 1/2x CLKIN signal. 

3. Unused data bus lines may be left floating. 

4. The two MSBs of the data bus (D23-22) are used to supply the two MSBs of the 
boot memory EPROM address. This is only required for the 27256 and 27512. 


Figure 10.1 ADSP-21 xx System With External Memory 


10-2 








10.2 PROGRAM MEMORY INTERFACE 

This section describes the program memory interface of all ADSP-21xx 
processors except the ADSP-2181. 

The processors address 16K of 24-bit wide program memory, up to 2K 
on-chip and the remainder external, using the control lines shown in 
Figure 10.1. The processors supply a 14-bit address on the program 
memory address bus (PMA) which is driven off-chip on the address bus in 
the case of external program memory accesses. Instructions or data are 
transferred across the 24-bit program memory data (PMD) bus which is 
also multiplexed off-chip. For a dual off-chip data fetch, the data from 
program memory is read first, then the data memory data. A program 
memory select pin, PMS, indicates that the address bus is being driven 
with a program memory address and memory can be selected. 

Two control lines indicate the direction of the transfer. Memory read (RD) 
is active low signaling a read and memory write (WR) is active low for a 
write operation. Typically, you wou ld con nect PMS to CE (Chip Enable), 
RD to OE (Output Enable) and WR to WE (Write Enable) of your memory. 

10.2.1 External Program Memory Read / Write 

On-chip mem ory accesses do not drive any external signals. PMS, DM5, 
RD, and WR remain high (deasserted); the address and data buses are 
tristated. Off-chip program memory access happens in this sequence: 

1. The processor places the a ddre ss on the PMA bus, which is 
multiplexed off-chip, and PMS is asserted. 

2. RD or WR is asserted. 

3. Within a specified time, data is placed on the data bus, multiplexed to 
the internal PMD bus. 

4. The data is read or written and RD (or WR ) is deasserted. 

5. PMS is deasserted. 

The basic read and write cycles are illustrated in Figure 10.2 on the next 
page. Figure 10.2 A shows zero wait states and 10.2B shows the effect of 
one wait state. 


10-3 



WR 


Data 

In 




External Program/Data Memory Read/Write 
PWAIT=0, DWAIT=0 (no wait states added) 


Figure 10.2A Memory Read And Write, No Wait States 




External Program/Data Memory Read/Write 
PWAIT=1, DWAIT=1 (one wait state added) 

Figure 10.2B Memory Read And Write, One Wait State 


10-4 






The program memory interface can generate 0 to 7 wait states for external 
memory devices. The program memory wait state field (PWAIT) in the 
system control register is shown in Figure 10.3. PWAIT defaults (after 
RESET) to seven wait states for program memory accesses. 

System Control Register 
0x3FFF 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



PWAIT 

(Program Memory Wait States) 

Default = 7 

Figure 10.3 Program Memory Wait State Field In System Control Register 

10.2.2 Program Memory Maps 

For all RAM-based processors except the ADSP-2181, the program 
memory space is mapped in one of two configurations depending on the 
state of the MMAP pin. Figure 10.4 shows these configurations for the 
processors with 2K internal program memory (ADSP-2101, ADSP-2111, 
ADSP-2171, ADSP-21msp58), and Figure 10.5 shows the same information 
for the processors with IK internal program memory (ADSP-2105, 
ADSP-2115). 

When MMAP=0, internal RAM occupies 2K words beginning at address 
0x0000. In this configu ration, the boot loading sequence is automatically 
initiated when RESET is released (as described in "Boot Memory 
Interface"). 

When MMAP=1, words of external program memory begin at address 
0x0000 and internal RAM is located in the upper 2K words, beginning at 
address 0x3800. In this configuration, program memory is not loaded 
although it can be written to and read from under program control. 

The program memory space can hold instructions and data intermixed in 
any combination. The ADSP-21xx linker determines where to place 
relocatable code and data segments. You may specify absolute address 
placement for any module or data structure, including the code for the 
restart and interrupt vector locations. The restart vector is at program 
memory address 0x0000. The interrupt vector locations are given in 
Chapter 3 and in Appendix D. 




ADSP-2105 

ADSP-2115 


ADSP-2101 
ADSP-21 1 1 
ADSP-2171 
ADSP-21 msp58 


INTERNAL 

RAM 

0x0000 


0x0000 

INTERNAL RAM 

IK 

0x0000 


0x0000 

2K 

Loaded From 




Loaded From 
External 

Boot Memory 

0X03FF 



External 

Boot Memory 

0x07FF 



Reserved 

0x0400 

EXTERNAL 

14K 



0x0800 

EXTERNAL 

14K 


IK 

0x07FF 







0x0800 


0x37FF 


EXTERNAL 

14K 



0x37FF 

EXTERNAL 


INTERNAL RAM 

IK 

0x3800 



0x3800 

14K 



0x3BFF 



INTERNAL 

RAM 

2K 




Reserved 

IK 

0x3000 


0x3FFF 


0X3FFF 


0x3FFF 


0x3FFF 


MMAP=0 MMAP=1 MMAP=0 MMAP=1 

No Booting No Booting 

Figure 10.4 Program Memory Maps (2K internal RAM) Figure 10.5 Program Memory Maps (IK internal RAH 

Internal program memory RAM is fast enough to supply an instruction 
and data in the same cycle, eliminating the need for cache memory. 

Consequently, if the processor is operating entirely from on-chip memory, 
it can fetch two operands and the next instruction on every cycle. It can 
also fetch any one of these three from external memory with no 
performance penalty. 

10.2.3 ROM Program Memory Maps 

The ADSP-21 72 and ADSP-21 msp59 processors contain mask- 
programmable ROM on-chip. The program memory maps for these 
processors are shown in Figures 10.6 and 10.7. The ADSP-2172 contains 8K 
of ROM and the ADSP-21 msp59 contains 4K. 

On the ADSP-2172 and ADSP-21 msp59, the ROM is enabled by setting the 
ROMENABLE bit in the Data Memory Wait State control register (at 
address DM[0x3FFE]). When the ROMENABLE bit is set to 1, addressing 
program memory in the ROM range will access the on-chip ROM. When 
ROMENABLE is set to 0, addressing program memory in this range will 
access external program memory. The ROMENABLE bit is initialized to 0 
after reset unless MMAP and BMODE=l. 


10-6 





0000 



2K Internal RAM 
Booted 

0000 

07FF 

2K External 

0000 

07FF 

2K Internal RAM 
Not Booted 

8K Internal ROM 

(ROMENABLE = 1) 

or 

0800 

8K Internal ROM 

(ROMENABLE = 1) 

or 

0800 

8K Internal ROM 

(ROMENABLE Defaults 
to 1 During RESET) 

8K External 

(ROMENABLE = 0) 

27FF 

8K External 

(ROMENABLE = 0) 

27FF 



2800 


2800 


6K External 


4K External 

37FF 

6K External 



2K Internal RAM 

3800 



3FFF 


3FFF 



07FF 

0800 


27FF 

2800 


3FFF 


MMAP = 0 MMAP = 1 MMAP = 1 

BMODE = 0 or 1 BMODE = 0 BMODE = 1 

Figure 10.6 ADSP-2172 Program Memory Map 



0000 


0000 


0000 


INTERNAL 

RAM 

LOADED FROM 
EXTERNAL 
BOOT 
MEMORY 

07FF 

INTERNAL 

RAM 

LOADED FROM 
EXTERNAL 
BOOT 
MEMORY 

07FF 

EXTERNAL 

07FF 

EXTERNAL 

INTERNAL 

MASK 

PROGRAMMED 

ROM 

0800 


0800 

INTERNAL 

MASK 

PROGRAMMED 

ROM 

0800 


17FQ-17FF 

RESERVED 

17FF 

EXTERNAL 


17FQ-17FF 

RESERVED 

17FF 



1800 


EXTERNAL 

1800 


EXTERNAL 





37FF 

INTERNAL 


3FFF 


3FFF 

INTERNAL 

RAM NOT 
LOADED 

3800 

3FFF 

RAM 

NOT 

LOADED 


ROM ENABLED ROM ENABLE=0 ROM ENABLED ROM ENABLE=0 

MMAP=0 MMAP=0 MMAP=1 MMAP=1 

Figure 10.7 ADSP-21msp59 Program Memory Map 


10-7 






When the MMAP and BMODE pins both are set to 1, the ADSP-2172 (or 
ADSP-21msp59) will operate in standalone ROM execution mode. When 
MMAP=1 and BMODE=l, the ROM is automatically enabled and 
execution begins from program memory location 0x0800 at the start of 
ROM. This lets an embedded design operate without external memory 
components. To operate in this mode, the ROM-coded program must copy 
an interrupt vector table to the appropriate locations in program memory 
RAM. In this mode, the ROMENABLE bit defaults to 1 during reset. 

Table 10.1 summarizes the booting and startup execution modes for the 
ADSP-2172 and ADSP-21msp59. 



BMODE = 0 

BMODE = 1 

MMAP = 0 

Boot from EPROM, 
then execution starts 
at internal RAM 
location 0x0000 

Boot from HIP, then 
execution starts at 
internal RAM location 
0x0000 

MMAP = 1 

No booting, execution 
starts at external memory 
location 0x0000 

Standalone mode, 
execution starts at 
internal ROM location 
0x0800 


Table 10.1 Booting Mode for ADSP-2172, ADSP-21msp59 


The ADSP-216x processors are memory-variant versions of the ADSP-2101 
and ADSP-2103 that contain factory-programmed on-chip ROM program 
memory. The ADSP-2161, ADSP-2163, and ADSP-2165 are 5.0V supply 
processors based on the ADSP-2101. The ADSP-2162, ADSP-2164, and 
ADSP-2166 are 3.3V supply processors based on the ADSP-2103. These 
devices offer different amounts of on-chip memory for program and data 
storage, as shown in Table 10.2. 


Feature 

2161 

2162 

2163 

2164 

2165 

2166 

Data Memory (RAM) 

ViK 

Vac 

vac 

Vac 

4K 

4K 

Program Memory (ROM) 

8K 

8K 

4K 

4K 

12K 

12K 

Program Memory (RAM) 

- 

- 

- 

- 

IK 

IK 


Table 10.2 ADSP-216x ROM-Programmed Processors 


Figures 10.8, 10.9, and 10.10 show the program memory maps for the 
ADSP-2161 /62, ADSP-2163/ 64, and ADSP-2165/66, respectively. 


10-8 






0x0000 

2K 

0x0000 


0x0000 

2K 

0x0000 

8K 

INTERNAL 

ROM 


EXTERNAL 

0x07FF 

4K 

INTERNAL 

ROM 


EXTERNAL 

0x07FF 


6K 

INTERNAL 

0x0800 


2K 

INTERNAL 

0x0800 



ROM 



OxOFFO 

ROM 

OxOFFO 


0x1 FFO 


0x1 FFO 

Reserved 

Reserved 



OxOFFF 

0x1000 

OxOFFF 

0x1000 

Reserved 


Reserved 

0x1 FFF 

0x2000 




0x1 FFF 
0x2000 



10K 



6K 


12K 


EXTERNAL 


8K 

EXTERNAL 


EXTERNAL 

0x37FF 

EXTERNAL 



0x37FF 



2K 

0x3800 



2K 

0x3800 



INTERNAL 




INTERNAL 



0x3FFF 

ROM 

0x3FFF 


0x3FFF 

ROM 

0x3FFF 

MMAP=0 


MMAP=1 


MMAP=0 

MMAP=1 


Figure 10.8 ADSP-21 61/62 Program Memory Maps Figure 10.9 ADSP-21 63/64 Program Memory Maps 


12K x 24 
INTERNAL 
ROM 


IK x 24 RAM 


RESERVED 


2K x 24 
EXTERNAL 


0000 


2FFF 

3000 


33FF 

3400 


37FF 

3800 


3FFF 


2K 

EXTERNAL 


1 0K X 24 
INTERNAL 
ROM 


IK x 24 RAM 


RESERVED 


2K x 24 
INTERNAL 
ROM 


0000 


07FF 

0800 


2FFF 

3000 


33FF 

3400 


37FF 

3800 


3FFF 


MMAP=0 


MMAP=1 


Figure 10.10 ADSP-21 65/66 Program Memory Maps 


10-9 




10.3 DATA MEMORY INTERFACE 

This section describes the data memory interface of all ADSP-21xx 
processors except the ADSP-2181. 

The processors supply a 14-bit address on the data memory address bus 
(DMA) which is multiplexed off-chip. Data is transferred across the upper 
16 bits of the 24-bit memory data bus, which is also multiplexed off-chip. 

A data memory select pin, DMS, indicates that the address bus is being 
driven with a data memory address and memory can be selected. 

Two control lines indicate the direction of the tra nsfer . Memory read (KD) 
is active low signaling a read and memory write (WR) is active low for a 
write operation. Typically, you wou ld con nect DMS to CE (Chip Enable), 
KD to OE (Output Enable) and WR to WE (Write Enable) of your memory. 

10.3.1 External Data Memory Read/Write 

Internal data memory accesses are transparent to the external memory 
interface. Only off-chip accesses drive the memory interface. Off-chip data 
memory accesses follow the same sequence as off-chip program memory 
accesses, namely: 

1. The processor places the address on the DMA bus, which is 
multiplexed off-chip, and DMS is asserted. 

2. KD or WR is asserted. 

3. Within a specified time, data is placed on the data bus, multiplexed to 
the internal DMD bus. 

4. The data is read or written and KD (or WR ) is deasserted. 

5. DMS is deasserted. 

The basic read and write cycles are illustrated in Figure 10.2. 

For a dual off-chip data fetch, the data from program memory is read first, 
then the data memory data. 


10-10 




10.3.2 Data Memory Maps 

The processors can address a total of 16K words of 16-bit data memory. 
On-chip data memory is IK in size and starts at address 0x3800 on the 
ADSP-2101 and ADSP-2111. On-chip data memory is 512 locations in size 
on the ADSP-2105 and ADSP-2115, again starting at address 0x3800. On- 
chip data memory is 2K in size on the ADSP-2171 and ADSP-21msp58/59, 
beginning at address 0x3000. 

The processors' control and status registers are mapped into the top IK of 
data memory, addresses 0x3C00-0x3FFF. The rest of the top IK is 
reserved. External data memory is available for additional data storage. 
Figures 10.11, 10.12, and 10.13 show the data memory maps for each 
ADSP-21xx processor. 


IK for ADSP-2101 
ADSP-2103 
ADSP-2111 



0x0000 

1 K External 


DWAIT0 

0x0400 


IK External 


DWAIT1 

0x0800 


10K External 


DWAIT2 

0x3000 


1 K External 


DWAIT3 

0x3400 


1 K External 


DWAIT4 


512 for ADSP-2105 

0x3800 

ADSP-2115 

ADSP-216X 

0x3A00 

Memory-Mapped 
Control Registers 

0x3C00 

& Reserved 

0X3FFF 


EXTERNAL 

RAM 




T 


INTERNAL 

RAM 


t 


Figure 10.11 Data Memory Map (ADSP-2101, ADSP-2111, ADSP-2105, ADSP-2115, ADSP-2161/62/63/64) 


10-11 



As shown in Figure 10.11, the ADSP-2101, ADSP-2111, ADSP-2105, 
ADSP-2115, and ADSP-2161 / 62/63/64 processors have five external wait 
state zones (DWAIT0-DWAIT4). Each of the five zones of external data 
memory has its own programmable number of wait states. Wait states are 
extra cycles that the processor either waits before latching data (on a read) 
or drives the data (on a write). This means that one zone of memory could 
be used for working with memory-mapped peripherals of one speed 
while another zone was used with faster or slower peripherals. Similarly, 
slower and faster memories can be used for different purposes, as long as 
they are located in different zones of the data memory map. 

As shown in Figures 10.12 and 10.13, the ADSP-2171, ADSP-21msp58/59, 
and ADSP-2165/66 processors each have three wait state zones for 
external data memory. 



0000 


2FFF 

3000 


37FF 

3800 


3BFF 

3C00 


3FFF 



0000 

03FF 

0400 

07FF 

0800 


2FFF 

3000 


3FFF 


Data Memory Wait States 

Figure 10.12 Data Memory Map (ADSP-2171, ADSP-21msp58/59) 


10-12 





0x0000 

0x0400 

0x0800 

0x2000 

0x3000 

0x3FFF 


Figure 10.13 Data Memory Map (ADSP-21 65/66) 


The Data Memory Waitstate control register has a separate field for each zone 
of external memory. Each 3-bit field specifies the number (0-7) of wait states 
for the corresponding zone of memory; all zones default to 7 wait states after 
RESET. Figure 10.14 shows this control register for the ADSP-21 01, ADSP-21 11, 
ADSP-2105, ADSP-2115, and ADSP-21 61/ 62/ 63/ 64 processors. Figure 10.15 
shows the register for the ADSP-2171/72 and ADSP-21 msp58/59 processors; 
on the ADSP-21 72 and ADSP-21msp59, one bit in this register is used to enable 
or disable the on-chip ROM. 


10-13 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



DM(0x3FFE) 


DWAIT4 DWAIT3 DWAIT2 DWAIT1 DWAITO 

Figure 1 0.1 4 Data Memory Waitstate Control Register (ADSP-21 01 , ADSP-21 1 1 , 
ADSP-2105, ADSP-21 15, ADSP-21 61/62/63/64) 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

□ 

0 

0 

E 

0 

□ 

E 

E 

1 1 

3 

E 

1 

1 

1 

□ 

E 

1 

1 

i 

□ 


DWAIT2 DWAIT1 DWAITO 


DM(0x3FFE) 


1 — ROM Enable (ADSP-21 72, ADSP-21 msp59 only) 
1=enable 
0=disable 


Figure 10.15 Data Memory Waitstate Control Register (ADSP-21 71/72, ADSP-21 msp58/59) 


10.3.3 Memory-Mapped Peripherals 

Peripherals requiring parallel communications and other types of devices 
can be mapped into external data memory. Communication takes the form 
of reading and writing the memory locations associated with the device. 
Some A/D and D/ A converters require this type of interface. The .PORT 
directives in the System Builder and Assembler modules of the ADSP-21 00 
Family Development Software support this mapping. 

Communication with a memory-mapped device consists simply of reading 
and writing the appropriate locations. By matching the access times of the 
external devices to the wait states specified for their zone of data memory, 
you can easily interface a variety of devices. 

The 16 MSBs of the external data bus (D 23 . 8 ) are connected to the 16 LSBs of 
the internal DMD bus, so D 23-8 should be used for 16-bit peripherals. 


10-14 




1 0.4 BOOT MEMORY INTERFACE 

This section describes the boot memory interface of all ADSP-21xx 
processors except the ADSP-2181. 

The entire internal program memory, or any portion of it, can be loaded 
from an external source using a boot sequence. To interface with 
inexpensive EPROM, the processor loads instructions one byte at a time. 

Automatic booting at reset depends on the state of the MMAP pin at the 
time of processor reset. The boot sequence occurs if the MMAP pin is 0. 
The boot sequence can also be initiated after reset by software. 

The ADSP-2111, ADSP-2171, and ADSP-21msp5x processors, which 
include a Host Interface Port (HIP), can boot using either the memory 
interface or the HIP (from a host computer). The state of the BMODE pin 
determines which method is used: the memory interface if BMODE=0, or 
the HIP if BMODE=l. Booting through the HIP is described in Chapter 7. 

BR is recognized during the booting sequence. The bus is granted after 
completion of loading the current byte. 

The ADSP-216x contain on-chip program memory ROM; on these devices, 
no booting occurs. 

10.4.1 Boot Pages 

Boot memory is organized into eight pages, each of which can be 8K bytes 
long. Every fourth byte of a page is an "empty" byte, except the first one, 
which contains the page length. Each set of three bytes between successive 
empty bytes contains an instruction. The page length is read first and then 
bytes are loaded from the top of the page downwards. This results in 
shorter booting times for shorter pages. 

The length of the boot page is given as: 

page length = (number of 24-bit PM words / 8) - 1 

That is, a page length of 0 causes the boot address generator to generate 
byte addresses for 8 words which reside in 32 sequential ROM locations. 

The PROM Splitter utility, part of the ADSP-2100 Family Development 
Software tools, calculates the proper page length for your program and 
orders the bytes of your program as shown in Figure 10.16 (on the next 
page). 


10-15 



Address 


0000 

WordO: USB 

0001 

WordO: MSB 

0002 

WordO: LSB 

0003 

Page Length 

0004 

Wordl: USB 


( A 

001 B 

Not Used 

001 C 

Word 7: USB 

001 D 

Word 7: MSB 

001 E 

Word 7: LSB 

001 F 

Not Used 




Figure 10.16 EPROM Contents 

10.4.2 Powerup Boot & Software Reboot 

Upon a hardware or software reset, the boot sequence occurs if the MMAP 
pin is a logical 0. The boot sequence on reset always loads boot page 0. 
After reset, boot loading can occur under program control from any one of 
up to 8 different boot pages. The boot page select field (BPAGE) in the 
memory-mapped System Control Register (see Figure 10.17) specifies 
which boot page is to be loaded. To boot from a specific boot page, set 
BPAGE to the desired page number and, in the same memory-mapped 
register, set the boot force bit (BFORCE). When the boot force bit is set, the 
software-forced booting sequence starts. Except for the page selection and 
(possibly) the number of wait states, there is no difference between a 
software-forced boot sequence and a reset boot sequence. 

Tables 92 - 9.7 in the System Interface chapter show the state of the 
processor control registers after a reset and after a software reboot. 
Essentially, the processor's control state is saved, but stacks are cleared 
and execution starts at the restart vector, at program memory location 
0x0000. 


10-16 



System Control Register 


15 

14 

13 

12 

11 

10 

9 

8 7 6 

5 4 3 

2 

1 

0 

0 

0 

0 

□ 




o 

o 

o 

1 1 

0/1 1 1 

1 1 



II 


DM(0x3FFF) 


BFORCE 
(Boot Force Bit) 




BWAIT (Boot Wait States) 

Defaults for ADSP-21xx 

Default=7 for ADSP-2171, ADSP-21msp58 


BPAGE (Boot Page Select) 
Default = 0 


Figure 10.17 Boot Control Fields In System Control Register 


10.4.3 Boot Memory Access 

The processor can boot its internal memory from a single byte-wide 
CMOS EPROM, such as the 27C64 and 27C512. A low-cost, commodity- 
grade EPROM with an industry-standard access time can be used. The 
number of wait states for the boot memory access is selected in the BWAIT 
field of the System Control Register (see Figure 10.17). This field can be set 
to any value from 0 to 7 in order to generate 0 to 7 wait states. The default 
value at reset is 3 wait states on the ADSP-2101, ADSP-2105, ADSP-2111, 
and ADSP-2115. BWAIT defaults to 7 wait states on the ADSP-2171 and 
ADSP-21msp58. 

Timing of the boot memory access is identical to that of external program 
memory or exter nal d ata mem ory accesses, except that the active strobe is 
BMS rather than PM$ or DM5. To address eight pages of 8K bytes each, 16 
bits are needed. The least significant 14 bits are output on the 14-bit 
address bus, and the most significant 2 bits are output on the 2 MSBs of 
the data bus during a boot memory access. Data is read from the middle 
eight bits of the data bus. 

10.4.4 Boot Loading Sequence 

The order in which the processor loads data into its internal memory 
during a boot operation is unimportant in most applications. The boot 
loading sequence is explained in this section for those instances in which 
the order is relevant, for instance when a latch is providing data rather 
than an EPROM. 


10-17 




To execute the boot operation, the boot address generator generates the 
appropriate byte addresses and loads internal program memory with the 
contents of the EPROM. The internal program memory is loaded 
beginning with the high addresses. For example, assume that eight 24-bit 
words are loaded into the processor during the booting process. The first 
word written into program memory is written to address 0x0007. The last 
word loaded is written to internal program memory address 0x0000. 

The boot address is made up of several values, as shown in Figures 10.18 
and 10.19: the 3-bit page number (from BPAGE in the system control 
register); the 8-bit page length, which is always read first (from the fourth 
byte of the page); a 3-bit word counter value; and a 2-bit code whose value 
determines which byte of the word is being addressed. 

The last 24-bit word (instruction or data value) is loaded into the 
processor first. The byte loading order is: upper byte, lower byte, middle 
byte. The word pointer is then decremented. This addresses the second-to- 
last 24-bit word in the EPROM. 

For example, to boot from page 0 the shortest allowable page (with eight 
24-bit words corresponding to a page length of 0), the following addresses 
would be generated (see Figure 10.20): 

1. The first address generated is 0x0003 which reads the page length. 

2. The next address generated in this example is address OxOOlC. This is 
the upper byte of the last word. 

3. The byte code is then updated to specify the lower byte (the final two 
bits are 10) and the address generated is OxOOlE. 

4. The byte address changes again, this time to address the middle byte 
(the two bit code is 01) and the address generated is 0x001 D. 

5. Once all three bytes are loaded, the word counter is decremented. The 
three succeeding byte addresses generated are 0x0018, OxOOlA, and 
0x0019. 

6. The word counter is decremented again and the next set of byte 
addresses generated is 0x0014, 0x0016, and 0x0015. This process 
continues until word 0 is loaded. 

The contents of the EPROM, the byte addresses, and the order of 
addresses generated is shown in Figure 10.20. 



Byte Address 




Word Pointer 

1 


1 

15 14 13 

12 

11 10 9 8 7 6 5 

4 3 2 

1 0 


■ 



H 


2-bit byte code: USB = 00 
MSB = 01 

Figure 10.18 Boot Memory Address LSB = io 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


Page # 

8-Bit Page Length 

111 

0 0 

Page # 

8-Bit Page Length 

111 

1 0 

Page # 

8-Bit Page Length 

111 

0 1 

: I 

Page # 

: \ 

8-Bit Page Length 

110 

0 0 

Page # 

8-Bit Page Length 

110 

1 0 

Page # 

: s 

8-Bit Page Length 

110 

0 1 

Page # 

8-Bit Page Length 

10 1 

0 0 


\- 1st Word 


\- 2nd Word 


etc. 


Figure 10.19 Boot Memory Addresses 









Address 

EPROM 

Order 



Addressed 

0000 

WordO: USB 

(bytes) 

0001 

WordO: MSB 


0002 

WordO: LSB 


0003 

Page Length 

◄ 1st 

0004 

Wordl: USB 


0005 

Wordl: MSB 


0006 

Wordl: LSB 


0007 

Not Used 


* 

z' / 

* 

0018 

Word 6: USB 

◄ 5th 

0019 

Word 6: MSB 

◄ 7th 

001 A 

Word 6: LSB 

◄ 6th 

001 B 

Not Used 


001 C 

Word 7: USB 

m 2nd 

001 D 

Word 7: MSB 

< 4th 

001 E 

Word 7: LSB 

< 3rd 

001 F 

Not Used 



2nd word loaded 


1st word loaded 


Page#=0, Pagelength=0 

Figure 10.20 Example of Boot Loading Order (with Page#=0, Pagelength=0) 


10-20 





10.5 BUS REQUEST /GRANT 

This section describes the bus request and grant feature of all ADSP-21xx 
processors, including the ADSP-2181. 

The ADSP-21xx can relinquish control of its data and address buses to an 
external device. The external device requests the bus by asserting (low) the 
bus request signal, BE. BE is an asynchronous input. If the ADSP-21xx is not 
performing an external access, it responds to the active BE input in the 
following processor cycle by: 

• tristating the data and address buses and the xMS, ED, WE output drivers, 

• asserting the bus grant (FG) signal, and 

• halting program execution (unless Go Mode is enabled). 

If Go Mode is enabled, the ADSP-21xx continues to execute instructions from 
its internal memory. It will not halt program execution until it encounters an 
instruction that requires an external access. (An "external access" maybe 
either a memory device access or, on the ADSP-2181, a memory overlay 
access, BDMA access, or I/O space access.) 

If Go Mode is not enabled, the ADSP-21xx always halts before granting the 
bus. The processor's internal state is not affected by granting the bus, and the 
serial ports and host interface port (on the ADSP-2111, ADSP-2171, 
ADSP-21msp5x) remain active during a bus grant, whether or not the 
processor core halts. 

If the ADSP-21xx is performing an external access when the BE signal is 
asserted, it will not grant the buses until the cycle after the access completes. 
The sequence of events is illustrated in Figure 10.21. The entire instruction 
does not need to be completed when the bus is granted. If a single instruction 
requires two external accesses, the bus will be granted between the two 
accesses. The second access is performed after BE is removed. 

When the BE input is released, the ADSP-21xx releases the BG signal, 
reenables the output drivers and continues program execution from the point 
where it stopped. BG is always deasserted in the same cycle that the removal 
of BE is recognized. Refer to the data sheet for exact timing relationships. 

The bus request feature operates at all times, including when the processor is 
booting and when RESET is active. During RESET, BG is asserted in the same 
cycle that BE is recognized. During booting, the bus is granted after 
completion of loading of the current byte (including any wait states). Using 
bus request during booting is one way to bring the booting operation under 
control of a host computer. 


10 




The ADSP-2171 a nd AD SP-2181 processors have an additional feature, the 
Bus Grant Hung (BGH) output, which lets them operate in a 
multi processor system with a minimum number of wasted cycles. The 
BGH pin asserts when the ADSP-21xx is ready to execute an instruction 
but is stopped because the external bus is granted to another device. The 
other device can release the bus by deasserting bus request. Once the bus 
is released, the ADSP-21xx deasserts BG and BGH and executes the 
external access. Figure 10.22 shows timing for the BGH signal. 



If a memory access is in progress, BG is asserted in 
the cycle after the access is completed: 



Figure 10.21 Bus Request (with and without external access) 


10-22 



xMS 

RD 

WR 



Figure 10.22 Bus Grant Hung (BGH) Timing (ADSP-21 71, ADSP-2181 only) 

10.6 ADSP-2181 MEMORY INTERFACES 

The ADSP-2181 has the same modified Harvard architecture for internal 
memory as the other processors of the ADSP-2100 family. In this 
architecture. Data Memory stores data values and Program Memory 
stores both instructions and data. The ADSP-2181 has as its full base 
memory on-chip: 16K x 24-bit words of internal program memory RAM 
and 16K x 16-bit words of internal data memory RAM. 

There are four separate memory spaces: data memory, program memory, 
byte memory, and I/O memory. To provide external access to these 
memory spaces, the ADSP-2181 extends the internal address and data 
buses off-chip and provides the PMS, DM5, BMS, and IOMS select lines. 
The PMS, DM5, BMS, and IOMS signals indicate which memory space is 
being accessed. 

The composite memory space (and its CMS select line) lets a single off- 
chip memory be accessed as multiple memory spaces. The Composite 
Memo ry Sel ect register lets you define which memory spaces are selected 
by the CMS signal. 



10-23 




Figure 10.23 shows the external memory buses and control signals in an 
ADSP-2181 system. Two control lines determine the direction of external 
memory transfers: RD is active low signaling a read and WR is active low 
for a write o pera tio n. T ypically, you would connect KD to OE (Output 
Enable) and WR to WE (Write Enable) of your memory. 

Internal mem ory acc esses do not drive any external signals: PMS, DM5, 
BMS, IOMS, RD, and WR remain high (deasserted), and the address and 
data buses are tristated. 


1/2x CLOCK 
or 

CRYSTAL i 


SYSTEM 

INTERFACE 

or 

^CONTROLLER 


SERIAL 

DEVICE 


B=a 


SERIAL 

DEVICE 




ADSP-2181 

CLKIN 


XTAL 

addr 13 . 0 

FLO-2 

PFO-7 

DATA2 3 .q 

IRQ2 


IRQE 

SMS 

IRQLO 


IRQL1 


SPORT 1 

SCLK1 

RFS1 or IRQO 
TFS1 or IR5T 

(CMS 

DTI or FO 

DR1 or FI 




SPORT 0 


SCLK0 

RFS0 

TFS0 


DT0 

PMS 

DR0 

SMS 


CMS 

IDMA PORT 

IRES 

— — 

BR 

BG 

1WR 

IS 

BGH 

IAL 

tSCK 

' 

PWD 

IAD15-0 









3 


*13-0 k 
P 23-16^ jy > 


A0-A21 


BYTE 

MEMORY 


-►cs 


Mo-o 


K 


•'23-8 


ADDR 

I/O SPACE 

DATA 

(PERIPHERALS) 


2048 Locations 

CS 



*13-0 


K 


^ 23-0 


V V 


ADDR 

OVERLAY 

DATA 

MEMORY 


Two 8K 


PM Segments 


Two 8K 


DM Segments 


Figure 10.23 ADSP-2181 System Diagram 


10-24 















Unlike other processors of the ADSP-2100 family, the ADSP-2181 supports 
several additional memory interfacing features. These features include: 

• External Overlay Memory in 8K segments: these segments can be 
swapped for the upper 8K of internal program memory or lower 8K of 
data memory. 

• I/O Memory space: this memory space is for peripheral I/O, has 2K 
(16-bit wide) locations, and has four user-assignable waitstate ranges. 

• Byte Memory & Byte Memory DMA (BDMA): this memory space can 
address up to 4M bytes. The byte memory interface supports booting 
from and runtime access to inexpensive 8-bit memories. The DMA 
feature lets you define the number of memory locations the DSP will 
transfer to /from internal memory in the background while continuing 
foreground processing. 

• Internal Direct Memory Access (IDMA) Port: this port supports booting 
from and runtime access to host systems (for example, PC Bus Interface 
ASICs). The DMA feature of this port lets you define the number of 
memory locations the DSP will transfer to/ from internal memory in the 
background while continuing foreground processing. 

For complete information on the BDMA port, including booting, and IDMA 
port, refer to the DMA Ports chapter of this manual. 

The ADSP-2181 uses a half-instruction-rate clock input from which it 
generates a full-instruction-rate internal clock. For example, from a 
16.67 MHz clock input (CLKIN) the ADSP-2181 generates a 33.33 MHz 
instruction rate clock. All timing diagrams for the processor use the full- 
instruction-rate output clock (CLKOUT) as a reference. 

All external memories may have automatic wait state generation associated 
with them. The number of wait states — each equal to one instruction cycle — 
is programmable. 

10.6.1 ADSP-2181 Program Memory Interface 

The ADSP-2181 processor addresses its 16K of internal program memory as 
well as two 8K external program memory overlays. All program memory is 
24 bits wide. Up to two accesses to internal program memory can be 
completed per instruction cycle; this lets the DSP complete all operations in 
a single cycle. The PWAIT field of the System Control Register (shown in 
Figure 10.24) sets the number of waitstates for each access to program 
memory overlays. PWAIT defaults (after reset) to seven. 



System Control Register 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 1 0 

□ 

±1 

0 

ill 

111 

1 

111 

1 

0 

L 

IB 

O 

loj 

1 1 

1 1 1 

1 1 


DM (0x3FFF) 


SPORTO Enable 

1 = enabled, 0 = disabled 

SPORT1 Enable 

1 = enabled, 0 = disabled 



PWAIT 

Program Memory Overlay Wait Stab 


SPORT1 Configure 1 

1 = serial port 

0 = FI, FO, IRQO, IRQ1, SCLK 

Figure 10.24 PWAIT Field in System Control Register 


The on-chip program memory and overlays can hold instructions and 
data intermixed in any combination. The ADSP-21xx linker determines 
where to place relocatable code and data segments. You may specify 
absolute address placement for any module or data structure, including 
the code for the restart and interrupt vector locations. The restart vector is 
at program memory address 0x0000. 

The ADSP-2181's MMAP pin lets you select from two program memory 
configurations. The MMAP pin also controls whether the ADSP-2181 
boots after RESET is released. Figure 10.25 shows the MMAP options and 
the resulting memory maps for program memory. 

The program memory overlay select register (PMOVLAY) lets you choose 
a memory overlay to map from address PM(0x2000) to address 
PM(0x3FFF). The memory mapped to this space and corresponding 
PMOVLAY register values are shown in Figure 10.25. Table 10.3 shows 
how PMOVLAY relates to the addressing of memory locations (with 
address line A13). 

PMOVLAY Memory A13 A12:0 

0 Internal — — 

1 External overlay 1 0 13 LSBs of address between 

0x2000 and 0x3FFF 

2 External overlay 2 1 -13 LSBs of address between 

0x2000 and 0x3FFF 

Table 10.3 PMOVLAY and Program Memory Overlay Addressing 


10-26 




MMAP = 0 


MMAP = 1 


Program Memory 

Address 

8K Internal 
(PMOVLAY = 0) 

0x3FFF 

or 


External 8K 
(PMOVLAY = 1 or 2) 

0x2000 


OxlFFF 

8K Internal 

0x0000 


Program Memory 

Address 


0x3FFF 

8K Internal 
(PMOVLAY = 0) 

0x2000 


OxlFFF 

8K External 

0x0000 


Figure 10.25 ADSP-2181 Program Memory Map 

The following example instructions demonstrate how to use the 
PMOVLAY register. 

PMOVLAY=DM( 0x1234) ; (type 3 instruction, PMOVLAY is loaded } 

{ with the contents of address DM(0xl234)} 

PMOVLAY=2; (type 7 instruction, PMOVLAY is loaded } 

{ with the value 2. } 

PMOVLAY=AXO; (PMOVLAY is loaded from AXO register.} 

AXO=PMOVLAY; (AXO is loaded from PMOVLAY register. } 

If you are using a system design that sets MMAP=1, note that the first 8K is 
used to support a single segment of external memory. This allows an 
external ROM-based system to operate properly. In this mode, the external 
program memory address always has A13 set to 0 and 8K of internal PM is 
available. Set PMOVLAY=0 and MMAP=1. This mode is available on other 
ADSP-2100 family processors. 


10-27 






Figure 10.26 shows a memory design that provides full external program 

and data memory overlays for an ADSP-2181 processor, assuming that 

MMAP=0. The important points to note about this design are: 

• Three 32K x 8-bit SRAMs are required for full external program and 
data memory overlays; glue logic is not required. 

• Four control lines are required for read (RD), write (WR), chip select 
(CMS), and data /program memory select (PMS or DM5). 

• Composite Memory Select (CMSSEL) is configured to assert the CMS 
control line when Program Memory Select (PMS) or Data Memory 
Select (DM5) are asserted. 

• The order of overlays stored in this design (from lowest address to 
highest) is PM Overlay 1, PM Overlay 2, DM Overlay 1, and DM 
Overlay 2. Address line 13 (A13) of the ADSP-2181 selects between 
overlay 1 or 2. Figure 10.27 shows a memory map of this design. 



CMS RD WR PMS CMS RD WR PMS CMS RD WR PMS 

Figure 10.26 Example Program and Data Memory Overlay Design 


10-28 






There are some restrictions on using program memory overlays: 

• The ADSP-2181's program sequencer does not consider the value in the 
PMOVLAY register. Switching pages during operations that are sensitive to 
the current PMOVLAY register value can result in program execution errors. 
For example, if your program is performing a loop operation on one of the 
external overlays and the program changes to another external or internal 
overlay, an incorrect loop operation could occur. 

• The contents of the PMOVLAY register are not automatically saved and 
restored on the processors status stack when the processor responds to an 
interrupt. If your program uses overlays, you must save and restore the 
contents of PMOVLAY as part of your interrupt service routine. 


10-29 




10.6.2 ADSP-2181 Data Memory Interface 

The ADSP-2181 addresses 16K x 16-bit wide internal data memory and 
two 8K x 16-bit wide external data memory overlays. All accesses to 
internal data memory are completed in a single processor instruction 
cycle. The DWAIT field of the Waitstate Control Register (shown in Figure 
10.28) sets the number of waitstates for each access to data memory 
overlays. Figure 10.29 shows the data memory map of the ADSP-2181. 

The processor's memory-mapped control/ status registers are mapped 
into the top locations of internal data memory, addresses 0x3FE0-0x3FFF. 
Most of the ADSP-2181's control registers correspond to those found on 
other ADSP-21xx processors. Note that the ADSP-2181's System Control 
Register does not have the boot memory control fields found on other 
ADSP-21xx processors. Also note that the Waitstate Control Register 
includes four fields for the ADSP-2181's I/O memory space. 


Wait State Control Register 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAITO 


DM(0x3FFE] 


Figure 10.28 ADSP-2181 Wait State Control Register 


Data Memory 

Address 

32 Memory-Mapped 
Control Registers 

0x3FFF 

0x3FE0 


0x3FDF 

Internal 

8160 words 

0x2000 


OxlFFF 

8K Internal . 
(DMOVLAY=0) 


or 


External 8K 
(DMOYL AY =1,2) 

0x0000 


10-30 Figure 10.29 ADSP-2181 Data Memory Map 







The Data Memory overlay select (DMOVLAY) register lets you choose a 
memory overlay to map from address DM(OxOOOO) to address DM(OxlFFF). 
The DMOVLAY register is unique to the ADSP-2181. The memory mapped 
to this space and corresponding DMOVLAY contents are shown in Figure 
10.29. Table 10.4 shows how DMOVLAY relates to memory addressing 
(address line A13). 

DMOVLAY Memory A13 A12:0 

0 Internal — — 

1 External overlay 10 13 LSBs of address between 

0x0000 and 0x1 FFF 

2 External overlay 2 1 13 LSBs of address between 

0x0000 and OxlFFF 

Table 10.4 DMOVLAY and Data Memory Overlay Addressing 


The following example 
register: 

DMOVLAY =DM (0x1234); 

DMOVLAY=2 ; 

DMOVLAY = AX 0 ; 

AX 0= DMOVLAY; 


instructions demonstrate how to use the DMOVLAY 


(type 3 instruction, DMOVLAY is loaded } 
{ with the contents of address DM(0xl234)} 

{type 7 instruction, DMOVLAY is loaded } 

{ with the value 2. } 

{DMOVLAY is loaded from AX0 register.) 

{AX0 is loaded from DMOVLAY register. } 


For an example memory design that provides full external program and 
data memory overlays for an ADSP-2181 processor, see the previous section 
"Program Memory Interface." 


Two control lines indicate the direction of external tra nsfer s. Memory read 
(ED) is active low signaling a read and memory write (WR) is active low for 
a writ e op eration. Typically, you would connect DM5 to CE (Chip Enable), 
KD to OE (Output Enable) and WR to WE (Write Enable) of your memory. 


10-31 



10.6.3 ADSP-2181 Byte Memory Interface 

The ADSP-2181's byte memory space is 8 bits wide and can address up to 
4M bytes of program code or data. This memory space takes the place of 
the boot memory space found on other ADSP-2100 family processors. 

Unlike boot memory space, byte memory has read /write access through 
the ADSP-2181's BDMA port. 

Byte memory space consists of 256 pages, each containing 16K x 8-bit wide 
locations. This memory can be written and read in four different formats: 

24-bit, 16-bit, 8-bit MSB alignment, and 8-bit LSB alignment. 

Each read/ write to byte memory consists of data (on data bus lines 15:8) 
and address (on address bus lines 13:0 plus data lines 23:16). The 22-bit 
byte memory address lets you access up to 4M bytes of ROM or RAM. 

For complete information on the ADSP-2181's byte memory and BDMA 
port, refer to the DMA Ports chapter of this manual. 

10.6.4 ADSP-2181 I/O Memory Space 

The ADSP-2181 has a dedicated I/O Memory Space instead of the 
memory-mapped I/O used on other ADSP-21xx processors. The I/O 
memory space consists of 2048 locations with four associated 
programmable waitstate regions. Figure 10.30 shows the Wait State 
Control Register and the IOWAITO-3 bit fields that control I/O memory 
waitstate regions. 

Wait State Control Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

DM(0x3FFE 

DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0 

Figure 10.30 ADSP-2181 Waitstate Control Register 



10-32 





The Wait State Control Register is divided into the following fields: 

• IOWAITO. This 3-bit field sets the number of waitstates (0-7) for 
accesses to 1/ O memory addresses 0x000-0x1 FF. 

• IOWAIT1. This 3-bit field sets the number of waitstates (0-7) for 
accesses to I/O memory addresses 0x200-Ox3FF. 

• IOWAIT2. This 3-bit field sets the number of waitstates (0-7) for 
accesses to I/O memory addresses 0x400-0x5FF. 

• IOWAIT3. This 3-bit field sets the number of waitstates (0-7) for 
accesses to 1/ O memory addresses 0x600-0x7FF. 

• DWAIT. This 3-bit field sets the number of waitstates (0-7) for accesses 
to external program and data memory overlays. 

Note: The PWAIT field of the System Control Register sets the number of 
waitstates for access to external program memory overlays. 

When you connect a parallel I/O device to the ADSP-2181 as shown in 
Figure 10.31, the address sent to the device appears on the external 
address bus as shown in Figure 10.32. 

ADDRESS 10:0 
or 

Decoded 

Address Input DATA 23:8 

111 

Codec, A/D, D/A, or 
other peripheral device. 

I l I 


IOMS RD WR 

Figure 10.31 I/O Memory Space Peripheral Connection Example 


10-33 





13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

1 

X 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 



I/O Memory Operation 1 I/O Memory Address 

1 = Write 
0 = Read 


Figure 10.32 I/O Memory Address Word 


Host interfaces can use the additional communications channel provided 
by the ADSP-2181's I/O memory space. If your system bus interface ASIC 
uses a set of data registers for passing control information from the system 
bus and must also pass large amounts of sample data, map the control 
registers as 1/ O memory peripherals and transfer the sample data using 
IDMA. This combination of the I/O memory and IDMA channels reduces 
system bus transfer rate limitations. 


Note: As with other ADSP-2100 Family processors, on the ADSP-2181 you 
can define memory-mapped 1/ O ports with the assembler's .PORT 
directive. On the ADSP-2181, this directive defines memory-mapped I/O 
ports in external program memory overlays or data memory overlays. If 
you want to use this feature, you must make sure at runtime that you are 
on the correct program memory overlay or data memory overlay when 
accessing the port; the assembler and linker will not flag errors in .PORT 
accesses related to overlays because the issue is resolved at runtime. The 
"IO" keyword does not work with the .PORT directive; to assign symbolic 
labels to I/O memory addresses, use a #de fine macro. The best use of 
the .PORT directive is in porting non- ADSP-2181 applications to the 
ADSP-2181; otherwise, use 1/ O memory space for memory-mapped 1/ O. 


10-34 





1 0.6.5 ADSP-21 81 Composite Memory Select 

The ADSP-21 81 has a programmable memory select signal. Composite 
Memory Select (CMS). This signal lets you generate a memory select for 
devices mapped to more than one memory space, with the same timing as 
other individual memory select signals (PMS, DM5, BMS, and IOMS). 

Based on the value of CMSSEL in the Programmable Flag & Com posi te 
Select Control register (see Figure 10.33), the ADSP-21 81 asserts CMS 
whe n the corresponding memory select signal (or signals) are asserted. 
Each xMS signal can be individually enabled. After reset, CMSSEL is 
initialized to enable PMS, DM5, and IOMS (with BMS disabled). 


Programmable Flag & Composite Select Control 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



CMSSEL 
1 = Enable CMS 
0 = Disable CMS 


1 = Output 
0 = Input 


DM(0x3FE6) 


Figure 10.33 CMSSEL Selection for CMS Signal 


Figur e 10.26 (earlier in this cha pter) shows an example of how to use the 
CMS signal. In this system the CMS line drives the chip select for all three 
SRAMs. This lets you use three 32K x 8-bit SRAMs, with no glue logic, for 
complete program and data memory overlays. 


10-35 




10.6.6 External Memory Read - Overlays & I/O Memory 

External memory reads may access either PM overlays, DM overlays, or 
1/ O memory space. These read operations occur in the following 
sequence (see Figure 10.34): 

1) The ADSP-2181 executes a read from an external memory address; the 
address is driven on the address bus and PMS, DM5, BMS, or IOMS, 
and KD is asserted. (CMS may also be asserted, depending how it is 
configured.) 

2) The external peripheral drives the data onto the data bus. 

3) The ADSP-2181 reads the data and deasserts KD. 

WR remains high (deasserted) throughout the external memory read 
operation. 

Note that ADSP-2181 internal memory accesses do not drive any 
external signals: PMS, DM5, IOMS, BMS, CMS, RD, and WR remain high 
(deasserted), and the address and data buses are tristated. 




Figure 10.34 External Memory Read Timing 


10-36 






1 0.6.7 External Memory Write - Overlays & I/O Memory 

External memory writes may access either PM overlays, DM overlays, or I/O 
memory space. These read operations occur in the following sequence (see 
Figure 10.35): 

1) The ADSP-2181 executes a write to an external memory address; the address 
is driven on the address bus, data is driven on the data bus, and PMS, DM5, 
BMS, or IOMS, and WR is asserted. (CMS may also be asserted, depending 
how it is configured.) 

2) The external peripheral stores the data. 

3) The ADSP-2181 stops driving the address and data buses and deasserts WR. 
KD remains high (deasserted) throughout the external memory write operation. 



x> 

Figure 10.35 External Memory Write Timing 
1 0.7 MEMORY INTERFACE SUMMARY (ALL PROCESSORS) 

Table 10.5 summarizes the states of the memory interface pins for various 
combinations of program memory and data memory accesses. Table 10.6 
summarizes the states of the memory interface and control pins during 
reset, booting (ADSP-21xx boot memory booting, not ADSP-2181 byte 
memory booting), and bus grant. 



10-37 




Access 

PMS 

DMS 

BMS 

RD 

WR 

Address 

Data 

Internal program 
memory only 

high 

high 

high 

high 

high 

tristated 

tristated 

Internal data 
memory only 

high 

high 

high 

high 

high 

tristated 

tristated 

Internal program 
memory, external 
data memory 

high 

low 

high 

low 

(for 

read) 

low 

(for 

write) 

DM address 

DM data 

Internal data 
memory, external 
program memory 

low 

high 

high 

low 

(for 

read) 

low 

(for 

write) 

PM address 

PM data 

External boot 
memory 

high 

high 

low 

low 

(for 

read) 

high 

Boot address 

Boot data. 
Boot page 
address 


Table 10.5 Pin States During Memory Accesses 


Operation 

Address 

Data 

PMS 

DMS 

ME 

RD 

WR 

CLKOUT 

SPORTs 

BG 

Reset 

tristated 

tristated 

high 

high 

active 

tristated 

high 

Booting* 
after Reset 

active 

active 

BMS active 
PMS, DMS 
high 

RD active 
WR high 

active 

tristated 

high 

Reboot* 

active 

active 

BMS active 
PMS, DMS 
high 

RD active 
WR high 

active 

active 

high 

BR Asserted 
during Normal 
Operation, Booting*, 
or Go Mode 

tristated 

tristated 

tristated 

tristated 

active 

active 

low 

BR Asserted 
during Reset 

tristated 

tristated 

tristated 

tristated 

active 

tristated 

low 


Table 10.6 Pin States During Reset, Booting*, and Bus Grant 

* ADSP-21xx boot memory booting, not ADSP-2181 byte memory booting. 


10-38 


































































































DMA Ports 


11.1 OVERVIEW 

The ADSP-2181 supports several DMA interfacing features: 

• Byte Memory & Byte Memory DMA (BDMA): this memory space can 
address up to 4M bytes. The byte memory interface supports booting 
from and runtime access to inexpensive 8-bit memories. The BDMA 
feature lets you define the number of memory locations the ADSP-2181 
will transfer to /from internal memory in the background while 
continuing foreground processing. 

• Internal Direct Memory Access (IDMA) Port: this parallel port 
supports booting from and runtime access to host systems (for example, 
PC Bus Interface ASICs). The DMA feature of this port lets you transfer 
data to/from internal memory in the background while continuing 
foreground processing. 

These DMA transfers are accomplished internally by "cycle stealing," in 
the same way as serial port autobuffering. This means that the ADSP-2181 
uses internal bus cycles to transfer the data to and from memory. The 
stolen cycles will only occur at instruction cycle boundaries, i.e. not 
between cycles of a multiple-cycle instruction. See "IACK Acknowledge & 
DMA Cycle Stealing" at the end of this chapter for additional details. 

The ADSP-2181 uses a half-instruction-rate clock input from which it 
generates a full-instruction-rate internal clock. For example, from a 16.67 
MHz clock input (CLKIN) the ADSP-2181 generates a 33.33 MHz 
instruction rate clock. All timing diagrams for the processor use the full- 
instruction-rate output clock (CLKOUT) as a reference. 

Figure 11.1 shows an ADSP-2181 system and the interfaces to byte 
memory space and the IDMA port. 




1/2x CLOCK 
or 

CRYSTAL 


SYSTEM 

INTERFACE 

or 

^CONTROLLER 


SERIAL 

DEVICE 


H— ► 




SERIAL 

DEVICE 


■ 7 ^ 


ADSP-21 81 

CLKIN 


XTAL 

ADDR 13 _o 

FLO-2 


PFO-7 

DATA 23.0 

IRQ2 


IRQE 

BMS 

IRQLO 


IRQL1 


SPORT 1 


SCLK1 


RFS1 or IRQO 


TFS1 or fRQT 


DTI or FO 


DR1 or FI . 




SPORT 0 


SCLKO 


RFSO 


TFSO 



DTO 

PMS 

DRO 

DMS 


CMS 

IDMA PORT 


TO 

BR 

IWR 

BG 

IS 

BCSH 

IAL 

IACK 

PWD 

IAD15-0 

PWDACK 










*13-0 k 
P 23-16^ )v > 


K 


°15-8 


A0-A21 

BYTE 

MEMORY 

DATA 


CS 



Maddr 


C 23 8 Mdata 
cs 


I/O SPACE 
(PERIPHERALS) 

2048 Locations 


3 


R23-0 


V V 


ADDR 

OVERLAY 

DATA 

MEMORY 


Two 8K 


PM Segments 


Two 8K 


DM Segments 


Figure 11.1 ADSP-21 81 System 


11.2 BDMA PORT 

The ADSP-2181's byte memory space is 8 bits wide and can address up to 
4M bytes of program code or data. This memory space takes the place of 
the boot memory space found on other ADSP-21 00 family processors. 
Unlike boot memory space, byte memory has read/write access through 
the ADSP-2181's BDMA port. 

Each read/ write to byte memory consists of data (on data bus lines 15:8) 
and address (on address bus lines 13:0 plus data lines 23:16). The 22-bit 
byte memory address lets you access up to 4M bytes of ROM or RAM. 

11-2 







Byte memory space consists of 256 pages, each containing 16K x 8-bit wide 
locations. This memory can be written and read in four different formats: 
24-bit, 16-bit, 8-bit MSB alignment, and 8-bit LSB alignment. 

To use byte memory for purposes other that boot loading, for example 
runtime access to bulk data storage, you must know the page (BMP AGE) 
that the code/ data is stored on, the number of words (BWCOUNT) to read 
from that page, and the word format (BTYPE) of the data. Use the following 
procedure to prepare a runtime-accessible byte memory EPROM: 

• Develop the data /code to be accessed at runtime 

• Use the ADSP-2100 Family PROM Splitter utility to split the file into 
single page (or smaller) 16K x 8-bit- wide segments 

• Program these pages into your EPROM, noting the offset (page number) 
of each 

• Use these page numbers when doing BDMA accesses 

Note: For more information on the ADSP-2100 Family Development 
Software Tools, see the ADSP-2100 Family Assembler Tools & Simulator Manual 
and current software release note. 

When using BDMA for non-boot-loading transfers , a BDMA transfer begins when 
data is written to the BWCOUNT register and a BDMA interrupt is issued when the 
transfer is complete. 

The following restrictions apply to BDMA transfers: 

• The source or target of BDMA transfer is always internal program or data 
memory. The contents of the PMOVLAY and DMOVLAY registers do not 
influence BDMA source (or target selection). 

• Do not access the BEAD or BIAD registers during BDMA transfers. 

• Other external memory accesses (PM overlay, DM overlay, or I/O space) 
take precedence over BDMA port accesses. These accesses cannot occur at 
the same time because they also use the processor's external bus. 

• Do not enter powerdown mode with the BDMA port active. For 
information on powerdown restrictions on BDMA port access, see the 
System Interface chapter of this manual. 


11-3 




11.2.1 BDMA Port Functional Description 

The BDMA Port lets you load (and store) program instructions and data 
from (and to) byte memory with very low processor overhead. While the 
ADSP-2181 is executing program instructions, the BDMA port reads (or 
writes) code or data from (or to) byte memory — stealing one ADSP-2181 
cycle per word when it needs to write to (or read from) internal memory. 
You can calculate BDMA transfer time from the formula: 


r Number' 



r Number'' 


r Number 

1 "I 


f 1 1 



r 

of PM 



of Bytes 


of Added 

Cycle 


Cycle for 


+ 

Hold 

or DM 



per Word 


Waitstates 

for 


Internal 



Offs 

^ Words j 



S. J 


^ per Byte 

Transfer 


Lrd/wr J 



s. ' j 


If, for example, you wanted to transfer 100 24-bit program memory words 
through the BDMA port, assuming five waitstates and no hold offs, the 
operation would take 1900 cycles. This is shown in the following equation: 


f 100 "1 



r 3 ] 


f 5 1 'I 


f 1 



r o 

PM 



Bytes 


Added Cycle 


Cycle for 


+ 

Hold 

Words 



per 


Waitstates for 


Internal 



Offs 

v. > 



L.Word J 


s. per Byte Transfer^ 


[.RD/WR J 



j 


Hold offs for DMA transfers are defined in the section "DMA Cycle 
Stealing, DMA Hold Offs, and IACK Acknowledge" at the end of this 
chapter. 

11.2.2 BDMA Control Registers 

A set of memory-mapped registers are used to setup and control transfers 
through the BDMA port. Figures 11.2 through 11.6 show these registers. 

The BDMA Internal Address Register (BIAD) lets you set the 14-bit 
internal memory starting address for a BDMA transfer. The BDMA 
External Address Register (BEAD) lets you set the 14-bit external memory 
starting address for a BDMA transfer. 


11-4 



BDMA Internal Address 



Figure 11.2 BDMA Internal Address Register 



Figure 11.3 BDMA External Address Register 


11-5 




BDMA Control 


15 

14 

13 

12 

11 

10 

9 

8 7 

6 

5 

4 

3 

2 

1 0 

E 

0 

0 

0 

E 

0 

0 

0 pit 

0 

0 

0 

E 

0 

1 

0 0 





DM(0x3FE3) 


I BTYPE (see table) 


BMPAGE 


BTYPE 

00 

01 

10 

11 

Internal Memory Space 

PM 

DM 

DM 

DM 

Word Size 

24 

16 

8 

8 

Alignment 

full 

word 

full 

word 

MSB 

LSB 


BDIR 

0 = load from BM 

1 = store to BM 

BCR 

0 = run during BDMA 

1 = halt during BDMA, 
context reset when done 


Figure 11.4 BDMA Control Register 


The BDMA Control Register lets you set: 

• The BDMA Transfer Type (BTYPE) 

• The BDMA Direction (BDIR) 

• The BDMA Context Reset (BCR) 

• The BDMA Page (BMPAGE) 

BTYPE can be: 

00 24-bit Program Memory Words 

01 16-bit Data Memory 

10 8-bit bytes for Data Memory, MSB alignment 
10 8-bit bytes for Data Memory, LSB alignment 


11-6 


BDIR can be: 

0 from Byte Memory 

1 to Byte Memory 





BCR can be set to: 


0 Allow program execution during BDMA 

1 Inhibit program execution during BDMA transfers and cause a 
context reset after transfer is complete 

BMPAGE lets you select the starting page for BDMA transfer. 

Note: Rebooting with BDMA Context Reset (BCR=1) is similar to a 
Powerup Context Reset. For more details on processor states during reset 
and reboot, see the System Interface chapter of this manual. 

The BWCOUNT register lets you start a BDMA transfer by writing the 
number of words for the transfer to this register. The count automatically 
decrements as the transfer proceeds. When the count is zero (i.e. transfer 
complete), the processor issues a BDMA interrupt. When MMAP and 
BMODE are set to zero on boot, a value of 32 (decimal) is written to this 
register directing the ADSP-2181 to load the first 32 locations of its 
internal program memory. 

Two useful control techniques using this register are: 

• Poll the BWCOUNT register to determine when the DMA transfer is 
complete (BWCOUNT=0), instead of waiting for the BDMA interrupt. 

• Abort the DMA operation by writing a 1 to the BWCOUNT register and 
poll to determine when the transfer is complete (BWCOUNT=0), 
instead of waiting for the BDMA interrupt. (Note that the DMA transfer 
is aborted, and cannot be resumed later.) 

BMWAIT consists of bits 12, 13, and 14 of the Programmable Flag & 
Composite Select Control Register. BMWAIT lets you select 0-7 waitstates 
(each equal to a single instruction cycle) to apply to each byte memory 
access. BMWAIT is set to 7 after a reboot. 



BDMA Word Count (MMAP=0 and BMODE=0) 



BDMA Word Count (MMAP=1 or BMODE=1) 



Figure 1 1 .5 BDMA Word Count Register 





1 1 .2.3 Byte Memory Word Formats 

In your byte memory ROM or RAM, data is stored by the ADSP-21xx PROM 
Splitter according to the data format you select: 24-bit program memory 
words, 16-bit data memory words, 8-bit data memory bytes with MSB- 
alignment, or 8-bit data memory bytes with LSB-alignment. The byte order 
for 24-bit program memory words and 16-bit data memory words stored in 
byte memory is most-significant-byte in the lower address. Table 11.1 shows 
an example of byte memory storage of all four code/ data formats. 

Note: When transferring either of the data memory byte formats, the unused 
byte of data memory is zero-filled. 



Internal 

Internal 

Byte Memory 

Byte 


Memory 

Memory 

Address 

Memory 

BTYPE 

Address 

Contents 

(page 0x00) 

Contents 

00 

PM(0x0000) 

OxABCDEF 

BM(0x0000) 

OxAB 




BM(0x0001) 

OxCD 




BM(0x0002) 

OxEF 

00 

PM(OxOOOl) 

0x123456 

BM(0x0003) 

0x12 




BM(0x0004) 

0x34 




BM(0x0005) 

0x56 

01 

DM(0x0000) 

0x9876 

BM(0x0006) 

0x98 




BM(0x0007) 

0x76 

01 

DM(0x0001) 

0x3456 

BM(0x0008) 

0x34 




BM(0x0009) 

0x56 

10 

DM(0x0002) 

0x9800 

BM(0x000A) 

0x98 

10 

DM(0x0003) 

0x7600 

BM(0x000B) 

0x76 

11 

DM(0x0004) 

0x0034 

BM(0x000C) 

0x34 

11 

DM(0x0005) 

0x0056 

BM(0x000D) 

0x56 


Table 1 1 .1 Byte Memory Storage Formats 


11.2.4 BDMA Booting 

The entire on-chip program memory of the ADSP-2181, or any portion of it, 
can be loaded from an external source using a byte memory booting 
sequence. Booting from byte memory is one of two methods available for 
automatic booting after a reset. 


Table 11.2 shows how to select the post-reset booting method using the 
ADSP-2181's MMAP and BMODE pins. 


11-9 



MMAP BMODE Booting 
Pin Pin Method 

0 0 Boot through BDMA Port. Boot sequence loads the 

first 32 program memory words from the byte 
memory space. After all 32 words are loaded, 
program execution begins at internal address 
PM(OxOOOO) with a BDMA interrupt pending. 

0 1 Boot through IDMA Port. Boot sequence holds off 

execution while the host processor loads Program 
Memory using writes through the IDMA Port. 
Program execution begins when internal address 
PM(OxOOOO) is loaded. 

1 - No Booting. Boot sequence does not load memory or 

hold off execution. Program execution starts at 
external address PM(OxOOOO). The PMOVLAY 
register must be cleared (to zero). 

Table 11.2 Selecting The ADSP-2181 Boot Method 

The ADSP-2181 uses a BDMA boot sequence after reset when the BMODE 
and MMAP pins are held low. The BDMA port is initialized for booting as 
follows: 

• BWCOUNT is set to 32 

• BDIR, BMP AGE, BEAD, BIAD, and BTYPE are set to zero 

• BCR is set to 1 

• BMW AIT is set to 7 

These initializations set the BDMA port to load 32 words (BWCOUNT) — 
from (BDIR) — byte memory page zero (BMP AGE) — byte memory address 
zero (BEAD) — to internal Program Memory address zero (BIAD) — using 
24-bit program memory word format (BTYPE). The BDMA context reset bit 
(BCR) set to 1 inhibits program execution during BDMA transfer and 
causes execution to begin at address PM(OxOOOO) after the transfer. The 
number of waitstates (BMW AIT) for BDMA access is set to the maximum 
of 7. After the boot sequence is complete (32 words transferred), program 
execution begins at internal PM address 0x0000. 

The ADSP-2100 Family PROM Splitter utility provides a boot loader 
option for ADSP-2181 based designs; see "Development Software Features 
for BDMA Booting" below. 


11-10 



If you are developing your own boot-loading software for the ADSP-2181, 
however, you should note that the BDMA Context Reset bit (BCR) is set to 
1 (inhibiting program execution during BDMA transfer) and a BDMA 
interrupt is pending (signalling the first 32 word were sent) after the boot 
sequence is complete. Your program will have to process the interrupt (if 
you unmask the BDMA interrupt with the IMASK register) or clear the 
interrupt (with the IFC register). 

In an alternate method, using the BDMA interrupt without context clear, a 
loader program could suspend program execution with the IDLE 
instruction while BDMA boot loading. If the loader sets the PM boot-load 
parameters, enables only the BDMA interrupt in the IMASK register, and 
then executes an IDLE instruction — the IDLE instruction suspends 
program execution until the BDMA interrupt occurs. At that point all of 
program memory is loaded. 

11.2.4. 1 Development Software Features for BDMA Booting 

The ADSP-21xx PROM Splitter utility lets you create BDMA boot- 
loader programs for ADSP-2181-based designs. This provides a 
low overhead method for BDMA boot-loading your program. The 
boot loader program adds memory loader code to your executable 
program. The PROM Splitter generates loader code that initializes 
up to 6 pages of program memory and 4 pages of data memory, 
where each page is 16k bytes in size. Typically, the code generated 
by the PROM Splitter is burned into an EPROM and used as the 
ADSP-2181's Byte Memory space. 

When the MMAP and BMODE pins equal 0, the ADSP-2181 will 
load the first 32 program memory words from the Byte memory 
space and then begin execution. The loader routine is in those first 
32 words; it continues to load from the Byte Port until your whole 
program is loaded. 

Refer to the ADSP-2100 Family Assembler Tools & Simulator Manual 
as well as the software release note for complete information on 
the PROM Splitter features. 




11.3 IDMA PORT 

The IDMA Port of the ADSP-2181 is a parallel I/O port that lets the 
processor's internal memory be read or written by a host system. The IDMA 
Port architecture eases host bus interface design. 

Think of the IDMA port as a gateway to all internal memory locations on the 
DSP (except for the processor's memory-mapped control registers). The 
IDMA Port has a 16-bit multiplexed address and data bus that supports 
access to both 16-bit Data Memory and 24-bit Program Memory. IDMA Port 
read/write access is completely asynchronous and a host can access the 
DSP's internal memory while the ADSP-2181 is operating at full speed. 

Unlike the Host Interface Port (HIP) of the ADSP-2171 and ADSP-2111, the 
IDMA port does not require any ADSP-2181 processor intervention to 
maintain data flow. The host system can access ADSP-2181 internal memory 
directly, without going through a set of mailbox registers. Direct access to 
DSP memory increases throughput for block data transfers. Through the 
IDMA port, internal memory accesses can be performed with an overhead of 
one DSP processor cycle per word. 

The ADSP-2181 supports boot loading through the IDMA port, through the 
BDMA port, or from an external Program Memory Overlay. The BMODE 
and MMAP pins select the DSP's boot mode and memory map. Setting 
BMODE=l and MMAP=0 directs the ADSP-2181 to boot through the IDMA 
Port. For information on IDMA booting, see "Boot Loading Through The 
IDMA Port" at the end of this chapter. 

Note: The IDMA port cannot be used to read or write the ADSP-2181's 
memory-mapped control registers. See "Modifying Control Registers for 
IDMA." 


11 .3.1 IDMA Port Pin Summary 

The IDMA Port pins are shown below in Table 11.3. 


Input / 

Pin Name(s) Output 


IKD I 

IWK I 

15 I 

IAL I 

I ADO-1 5 I/O 

TACK O 


Table 11.3 IDMA Port Pins 


Function 

IDMA Port Read Strobe 

IDMA Port Write Strobe 

IDMA Port Select 

IDMA Port Address Latch Enable 

IDMA Port Address /Data Bus 

IDMA Port Access Ready Acknowledge* 


11-12 


* After reset, IACK is asserted (low) . It stay s low until an IDMA transfer is initiated. After 
each IDMA operation is completed, IACK will again be low. 



Four IDMA port i nputs control when the port is selected (15) for read 
(IRD), write (IWR), or address latch (IAL) operations on its address/data 
bus (IADO-15). The IDMA Port Select (IS) line acts as a chip select for all 
IDMA operations. 

Asserting the IDMA Port Select (IS) and address latch enable (IAL) directs 
the ADSP-2181 to write the address on the IADO-15 bus into the IDMA 
Control Register. This register, shown in Figure 11.7, is memory-mapped 
at address DM(0x3FE0). Note that the latched address (IDMAA) cannot be 
read back by the host. 


IDMA Control Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


DM(0x3FE0) 


IDMAD 1 

Destination memory type: 

0=PM 
1=DM 

Figure 11.7 IDMA Control Register 

Asserting the IDMA Port Select (IS) and Read strobe (IRD) inputs directs the 
ADSP-2181 to output the contents of the memory location pointed to by the 
IDMA Control register onto the IDMA data bus. 

Asserting the IDMA Port Select (IS) and Write strobe (IWR) inputs directs the 
ADSP-2181 to write the input from the IDMA data bus to the address pointed 
to by the IDMA register. 

When reading/writing to Data Memory, the IDMA data bus pins make up a 
16-bit Data Memory word. When reading/writing to Program Memory, the 
upper 16 bits of the 24-bit Program Memory word are sent first on the IDMA 
data bus pins. On the next IDMA Port read /write, the lowest 8 bits of the 
Program Memory word are sent on bits 0-7 of the IDMA data bus. For reads, 
the ADSP-2181 sets data bus lines 8-15 to 0; for writes, the ADSP-2181 ignores 
bits 8-15 from the host. 

The IDMA Port Access Acknowledge (IACK) line identifies completion of 
data reads/write operations. It also acts as a busy signal for the IDMA Port. 
External devices must wait for this signal to go low before modifying IDMA 
Control register or starting the next read/write operation. 


IDMAA 

Starting address 


11-13 




1 1 .3.2 IDM A Port Functional Description 

The IDM A Port lets a host system directly access internal ADSP-2181 
memory locations (but not the memory-mapped control registers). Figure 
11.8 shows a flow chart of the most general case for IDMA transfers. 

In the case shown in Figure 11.8, the host system starts an IDMA transfer 
by checking the state of the IACK line to determine port status (ready/ 
busy). When the IDMA port is ready, the host directs the ADSP-2181 (with 
the 15 and IAL lines) to latch the IDMA internal memory address from the 
IDMA address/data bus to the IDMA Control Register. (Note that the 
latched address cannot be read back by the host.) 

Next, the host (using the 15 and IRD or 15 and IWR lines) begins reading 
(or writing) the DSP's internal memory until done. With each IDMA read 
or write operation, the the ADSP-2181 automatically increments the IDMA 
internal memory address. Note that the ADSP-2181 continues program 
execution throughout the IDMA transfer operation, except during the 
"stolen" cycle used to do the memory access. 

The case shown in Figure 11.8 is not the only way to use the IDMA port. 
Some variations on this scheme include: 

• After completing an IDMA port read/ write operation, the host could 
change the IDMA internal memory address and start a new operation 
from a different starting address. 

• After latching an IDMA internal memory address, the host could stop 
the operation and come back at a later time to proceed with the read/ 
write operation. The IDMA starting memory address remains in the 
IDMA Control Register until the host or DSP changes it. 

• The ADSP-2181 can also read and write the IDMA Control Register as 
part of your program. This means that the host could just control read/ 
write operations and let the ADSP-2181 control the IDMA starting 
memory address. 

• Using the IDMA short read cycle (which does not wait for the data-ready 
assertion of the IACK signal), you could set up a single-location data 
buffer for IDMA read transfers. For information on how this data buffer 
would work, see "IDMA Port Short Read Cycle" below. 

• For ADSP-2181 applications with a host processor or host ASIC that 
does not use a data-ready or write-complete acknowledge, use the 
IDMA short read /write cycles. 





Figure 11.8 General IDMA Transfer Flow Chart 

There are some restrictions on IDMA operations. These hardware/ 
software design restrictions include: 

• If your design has both the host and ADSP-2181 writing to the IDMA 
Control Register, do not let both write to this register at the same time; 
the results of this are indeterminate. 

• Host reads of internal Program Memory take two IDMA reads (for a 24- 
bit word through a 16-bit port). If an IDMA address latch cycle or a 
ADSP-2181 write to the IDMA Control Register occurs after the first 
Program Memory read cycle, the IDMA port "loses" the second half of 
the 24-bit Program Memory word. The next IDMA read or write uses 
the address selected by the new contents of the IDMA Control Register. 

Note that writing to the IDMA Control Register after the first half of a 

Program Memory IDMA read lets you read just 16-bit data from II “10 

Program Memory. 






• Host writes to internal Program Memory take two IDMA writes (for a 
24-bit word through a 16-bit port). If an IDMA address latch cycle or a 
ADSP-2181 write to the IDMA Control Register occurs after a first 
Program Memory write cycle, the IDMA port "loses" the Program 
Memory word without changing the contents of memory. The next 
IDMA read or write accesses the address selected by the new contents 
of the IDMA Control Register. 

• Host memory accesses through the IDMA port that occur while the 
ADSP-2181 is in powerdown have some restrictions. For information on 
powerdown restrictions on IDMA port transfers, see the System Interface 
chapter of this manual. 

11.3.3 Modifying Control Registers for IDMA 

The ADSP-2181's memory-mapped control registers are protected from 
DMA transfers to prevent accidental corruption. You may want the host 
processor to read and write these registers, however, in order to 
determine the ADSP-2181's configuration and then change it. 

To read the memory-mapped control registers, you must first transfer the 
contents of these locations to another area of internal RAM. The following 
code segment shows a loop that performs this task: 

.const NUM_REG=32; 

. var/dm/ram temp_array [NUM_REG] ; 

1 0 = A t emp_ar r ay ; 

10 = 0 ; 

11 = 0x3 feO ; 

11 = 0 ; 

ml=l; 

cntr=NUM_REG ; 

do transfer until ce; 

axO=dm(il,ml) ; 
transfer: dm(i0,ml) =ax0; 

To have the host write to the memory-mapped control registers, you must 
first load the values to a temporary buffer (through the IDMA port) and 
then signal the ADSP-2181 to transfer the contents of the temporary buffer 
to the memory-mapped control registers. This transfer is performed in a 
similar manner as the code shown above. You should set up some form of 
signalling between the host and the ADSP-2181, either interrupts, flag 
1/ O, or a mailbox register. This will provide a mechanism for the host to 
tell the DSP when to perform an operation and vice versa. 



11.3.4 IDMA Timing 

From the host system interface point of view, there are three IDMA port 
operations with critical timing parameters. These operations are: 

• latching the IDMA internal memory address, 

• reading from the IDMA port, and 

• writing to the IDMA port. 

The following sections cover the timing details of each of these operations. 

11.3.4.1 Address Latch Cycle 

The host writes the DMA starting address and destination memory type 
(DM or PM) using the IDMA address latch cycle. The address latch cycle, 
shown in Figure 11.9, consists of the following steps: 

1. Host ensures that LACK line is low. 

2. Host asserts IAL and IS, directing the ADSP-2181 to latch the IDMA 
starting address from the IAD15-0 address/data bus into the IDMA 
Control Register. 

3. Host drives the starting address (bits 0-13) and destination memory 
type (bit 14) onto the IAD15-0 bus. (Bit 15 must be a 0.) 

Note that IRD and IWR remain high (inactive) throughout the latch 
operation. 



Figure 11.9 IDMA Address Latch Cycle Timing 


11-17 



Note: The IDMA starting address and destination memory type is available to 
the host and to the ADSP-2181 in the IDMA Control Register. For Data Memory 
accesses, the ADSP-2181 increments the address automatically after each IDMA 
read or write transfer (16-bit word). For Program Memory accesses, the 
ADSP-2181 increments the address automatically after each pair of IDMA read 
or write transfers (24-bit word). 

Warning: Both the ADSP-2181 and the host can specify the starting address by 
writing to the IDMA Control Register. Do not let the ADSP-2181 access the 
IDMA Control Register while it is being written by the host; this operation will 
have an indeterminate result. 

11.3.4.2 Long Read Cycle 

The host reads the contents of an ADSP-2181 internal memory location using 
the IDMA port long read cycle. The read cycle, shown in Figure 11.10, consists 
of the following steps: 

1 . Host ensure s tha t IACK line is low. 

2. Host asserts IRD and 15 (low), causing the ADSP-2181 to put the contents of 
the location pointed to by the IDMA address on the IAD15-0 address/ data 
bus. 

3. ADSP-2181 deasserts IACK line, indicating the requested data is being 
fetched. When the ADSP-2181 asserts the IACK line, the requested data is 
driven on the IAD address/data bus. 

4. Host detects the IACK line is now low and reads the data (READ DATA) 
from the IAD15-0 address/ data bus. After reading the data, the host 
deasserts IRD and IS. 

Note that IAL is low (inactive) and IWR is high (inactive) throughout the read 
operation. 

IDMA memory accesses "steal" one processor cycle, but may only occur on 
instruction cycle boundaries. The best-case response for a 16-bit Data Memory 
read or the first 16 bits of a Program Memory read is 2.5 processor cycles; worst 
case is 3.5 cycles. One cycle is for synchronization, one is for reading the 
memory internally, and one-half cycle is for IACK setup time. A second cycle of 
synchronization may be required. Thus the best-case and worst-case response 
times are determined as follows: 

Best Case: 1 cycle (sync) + 1 cycle (internal memory read) + 0.5 cycle (IACK setup) = 2.5 cycles 

Worst Case: 1 cycle (sync) + 1 cycle (sync) + 1 cycle (internal memory read) + 0.5 cycle (IACK setup) = 3.5 cycle 


11-18 




Figure 11.10 IDMA Long Read Cycle Timing 


In the case of a Program Memory operation, the second IDMA port read 
cycle for a given internal 24-bit word does not require an internal memory 
access, does not wait for an instruction cycle boundary, and takes 1.5 or 
2.5 cycles. 

The best- and worst-case response times given above assume no system hold offs. 
Hold offs for DMA transfers are defined in the section "DMA Cycle 
Stealing, DMA Hold Offs, and IACK Acknowledge" at the end of this 
chapter. 

Warning: If an IDMA address latch cycle or an ADSP-2181 write to the 
IDMA Control Register occurs after a first Program Memory read cycle (16 
bits), the IDMA port will lose the second half of the Program Memory 
word. The ADSP-2181 treats the next IDMA access as the first operation 
for the new IDMA address and destination. 


11-19 




11.3.4.3 Short Read Cycle 

The host reads the contents of a ADSP-2181 internal memory location using 
the IDMA short read cycle. The read cycle, shown in Figure 11.11, consists 
of the following steps: 

1. Host ensures that LACK line is low. 

2. Host asserts IRD and IS (low), directing the ADSP-2181 to put the 
contents of the location pointed to by the target IDMA address on the 
IAD15-0 address /data bus. 

3. ADSP-2181 deasserts IACK line, indicating the requested data is being 
fetched. 

4. Host detects the IACK line is now high and reads the data (PREVIOUS 
DATA) from the I ADI 5-0 address /data bus, before the requested data 
(READ DATA) is driven on the IAD address/ data bus — not waiting for 
the ADSP-2181 to assert the IACK line. After reading the data, the host 
deasserts IRD and 15. 

The host must do an initial "dummy" read, to make the ADSP-2181 put the 
first data word (PREVIOUS DATA) on the IAD15-0 bus. 

Note that IAL is low (inactive) and IWK is high (inactive) throughout the 
read operation. 

The IDMA Short Read and Long Read cycles provide different alternatives 
for implementing your DMA transfers. Short reads are useful for hosts that 
can handle the faster timing of these accesses, while long reads allow 
slower hosts more time. 

The IDMA short read cycle also serves as a single-location data buffer. If 
you are using the ADSP-2181 in a multiprocessing environment, using this 
buffer is one way to avoid tying up the IAD bus (waiting for IACK signal). 

Warning: If an IDMA address latch cycle or a ADSP-2181 write to the 
IDMA Control register occurs after a first Program Memory read cycle, the 
IDMA port will lose the second half of the Program Memory word. The 
ADSP-2181 treats the next host data on the IAD address/ data bus as the 
new contents of the IDMA Control Register. 


11-20 



IACK 


\ r 


\ 



IRD 


\ 


/ 

/ 


/\/ PREVIOUS \ 

IAD15 " 0 \ A DATA / 

Figure 11.11 IDMA Short Read Cycle Timing 

11.3.4.4 Long Write Cycle 

The host writes the contents of an internal memory location using the 

IDMA long write cycle. The write cycle, shown in Figure 11.12, consists of 

the following steps: 

1. Host ensures that IACK line is low. 

2. Host asserts IWR and IS (low), directing the ADSP-2181 to write the 
data on the IAD15-0 address/ data bus to the location pointed to by the 
target IDMA address . 

3. ADSP-2181 deasserts the IACK line, indicating it recognizes the IDMA 
write operation. 

4. Host drives the data on the IAD address/data bus. 

5. ADSP-2181 asserts IACK line, indicating it latched the data on the 
IAD15-0 address/ data bus. 

6. Host recognizes the IACK line is now low, stops driving the data on 
the IDMA address /data bus and deasserts IWR and IS (ending the 
IDMA Long Write Cycle). 

Note that IAL is low (inactive) and IRD is high (inactive) throughout the 

write operation. 


IACK 



Figure 11.12 IDMA Long Write Cycle Timing 

Note: IDMA port writes to Program Memory require two IDMA port 
write cycles to write a word to ADSP-2181 internal Program Memory. The 
ADSP-2181 acknowledges the IDMA port write of the first 16 bits (MSBs 
of PM word) as they are written to a temporary holding latch, not waiting 
for an instruction cycle boundary. The ADSP-2181 does not assert the 
IACK line after the second Program Memory write (or all Data Memory 
writes) until the internal memory write is complete and the IDMA port is 
ready for another transaction. 

Warning: Host IDMA write accesses to internal Program Memory take 
two IDMA port writes (24-bit word through a 16-bit port). If an IDMA 
address latch cycle or a ADSP-2181 write to the IDMA Control register 
occurs after a first program memory write cycle, the IDMA port "loses" 
the Program Memory word without changing the contents of ADSP-2181 
internal memory. The next IDMA read or write uses the address selected 
by the new contents of the IDMA Control register. 


11-22 



11.3.4.5 Short Write Cycle 

The host writes the contents of a ADSP-2181 internal memory location using the 

IDMA short write cycle. The write cycle, shown in Figure 11.13, consists of the 

following steps: 

1 . Host ensures that IACK line is low. 

2. Host asserts IWK and IS (low), directing the ADSP-2181 to write the data on 
the I ADI 5-0 address/ data bus to the location pointed to by the target IDMA 
address . 

3. ADSP-2181 deasserts IACK line (high), indicating it recognizes the IDMA 
write operation. 

4. Host drives the data on the I AD address /data bus. 

5. Host deasserts IWK and IS after meeting the short write timing requirements 
(ending the short write c ycle). 

6. ADSP-2181 detects IWR and IS have gone high, then latches the data on the 
IAD address/ data bus. 

7. Host stops driving the data on the IAD15-0 address/data bus after meeting 
the short write timing requirements. 

Note that IAL is low (inactive) and IRD is high (inactive) throughout the write 

operation. 


IACK 



/ 


IS 



IWR 


\ 


/ 

/ 


I ADI 5-0 


DATA 


\ 


Figure 11.13 IDMA Short Write Cycle Timing 



Note: IDMA port writes to Program Memory require two IDMA port 
write cycles to write a word to ADSP-2181 internal Program Memory. The 
ADSP-2181 acknowledges the IDMA port write of the first 16 bits (MSBs 
of PM word) as they are written to a temporary holding latch, not waiting 
for an instruction cycle boundary. The ADSP-2181 does not assert the 
IACK line after the second Program Memory write (or all Data Memory 
writes) until the internal memory write is complete and the IDMA port is 
ready for another transaction. 

Warning: If an IDMA address latch cycle or a ADSP-2181 write to the 
IDMA Control register occur after a first Program Memory write cycle, the 
IDMA port will lose the first half of the Program Memory word. The next 
Program Memory write will be considered the first half of a Program 
Memory write pair. 

There are two features that differentiate between the IDMA Port long 
write and short write. The long write supports hosts (processors or ASICs) 
that allow a data- written acknowledge. If your host needs the ADSP-2181 
to signal that it has written the data, use the IDMA long read cycle. 

The short write lets your host hold data on the bus just until it is latched 
and then release the bus. If you are using the ADSP-2181 in a 
multiprocessing environment, using the short write is one way to avoid 
tying up the IAD15-0 data bus (waiting for IACK signal). Short writes are 
also useful for hosts that can handle the short write timing, but can't 
extend the accesses with IACK (when holdoffs occur). 

1 1 .3.5 Boot Loading Through The IDMA Port 

The ADSP-2181 supports boot loading through the IDMA port. To boot 
through the IDMA Port, use the following steps: 

• Reset the processor (assert RESET). 

• Set MMAP=0 and BMODE=l. These pin settings select IDMA booting. 

• Deassert RESET. 

• Load ADSP-2181 internal memory through the IDMA port. Program 
execution is held off until you write to Program Memory address zero, 
PM(OxOOOO). The ADSP-2181 responds to IDMA control signals (IAL, 
IS, IWR, and IRD) and provides acknowledge (IACK) in the same 
manner as during non-booting IDMA transfers. 

• Write to PM(OxOOOO) to begin program execution. 

Warning: Make certain to load all of the necessary memory locations with 
the proper data before writing to PM(OxOOOO). 



1 1 .3.6 DMA Cycle Stealing, DMA Hold Offs, and IACK Acknowledge 

The IACK signal is generated by the ADSP-2181 to signal that it is safe to 
read or write through the IDMA port. After reset, IACK is asserted (low). 

It stays low until an IDMA transfer is initiated. After each IDMA 
operation is completed, IACK will again be low. 

In order for IACK to be asserted (low) during the IDMA operation, the 
IDMA port must have completed the internal memory access by either 
writing data to memory or reading data from memory. The IDMA port 
must "steal" a processor cycle to do this. In order to steal a processor 
cycle, the IDMA port must wait for an instruction completion boundary. 
Thus if IACK is not asserted, it is not safe for the host to access the IDMA port. 

In most cases, there is an instruction boundary on every clock cycle 
(CLKOUT period) and the IDMA port can complete its transfer in a given 
period of time. There are, however, some instances where either the 
ADSP-2181 does not complete an instruction in one clock cycle or the 
IDMA port cannot access memory. These are DMA hold offs : 

• Bus Request - If the ADSP-2181 is being held in Bus Request when it 
attempts an external access (DM overlay, PM overlay, or I/O memory 
space), or if it is not in GO mode, processor execution stops in the 
middle of the cycle and no instruction boundary is encountered. 
Therefore, the IDMA port cannot complete its internal memory access 
and IACK will be held off. 

• External Access with Wait State(s) - If the ADSP-2181 is performing a 
wait-stated external access (DM overlay, PM overlay, or I/O memory 
space), then the instruction cycle will not complete until the access has 
completed; the IDMA port cannot steal a cycle, and IACK will be held 
off. 

• Multiple External Accesses - If the ADSP-2181 is executing a 
multifunction instruction where more than one of the required elements 
(PM instruction fetch, PM data access, or DM data access) resides 
externally, it will reauire more than one cycle to complete the 
instruction and IACK will be held off. Likewise, if the ADSP-2181 is 
executing an instruction from external PM that initiates an I/O memory 
space access, IACK will be held off until the cycle completes. 

• IDLE n (clock-reducing IDLE instruction) - Because this instruction 
slows down the effective cycle time of the ADSP-2181, IACK may be 
delayed. 


11-25 




• SPORT Autobuffering to External Memory with Waitstated Access - 

When one of the processor's serial ports needs to access external 
memory for autobuffering and the external access takes more than one 
cycle, the IDMA transfer will be held off. 

• EZ-ICE Emulation - When the EZ-ICE emulator is controlling your 
ADSP-2181 target system, IDMA transfers may be held off for periods 
of time. 

Using the IACK signal simplifies your system design by allowing you to 
ignore hold-off conditions. If you always wait for IACK to assert before 
accessing the IDMA port, the DMA transfers will always operate properly. 

You can ignore IACK, however, if you are sure that no hold-offs occur in your 
system or if your IDMA accesses are longer than any hold-offs. To be sure of 
this, you must carefully analyze all possible hold-off conditions of your 
system. 


11-26 



Programming Model 13 12 


12.1 OVERVIEW 

From a programming standpoint, the ADSP-21xx processors consist of 
three computational units, two data address generators, and a program 
sequencer, plus on-chip peripherals and memory that vary with each 
processor. Almost all operations using these architectural components 
involve one or more registers — to store data, to keep track of values such 
as pointers, or to specify operating modes, for example. 

Internal registers hold data, addresses, control information or status 
information. For example, AXO stores an ALU operand (data); 14 stores a 
DAG2 pointer (address); ASTAT contains status flags from arithmetic 
operations; and fields in the Wait State register control the number of wait 
states for different zones of external memory. 

There are two types of accesses for registers. Dedicated registers such as 
MXO and IMASK can be read and written explicitly in assembly language. 
For example: 

MX0=1234; 

IMASK=0xF; 

Memory-mapped registers — the System Control Register, Wait State 
Control Register, timer registers, SPORT registers, etc. — are accessed by 
reading and writing the corresponding data memory locations. For 
example, this code clears the Wait State Control Register, which is mapped 
to data memory location 0x3FFE: 

AX0=0; 

DM ( 0x3 FFE ) =AX0 ; 

(AXO is used to hold the constant 0 because there is no instruction to write 
an immediate data value to memory using an immediate address.) 


12-1 




The ADSP-21xx registers are shown in Figure 12.1. Not all of these registers 
are available on every processor. The registers are grouped by function: data 
address generators (DAGs), program sequencer, computational units (ALU, 
MAC and shifter), bus exchange (PX), memory interface, timer, SPORTs, host 
interface and DMA interfaces. 

12.1.1 Data Address Generators 

DAGl and DAG2 each have twelve 14-bit registers: four index (I) registers 
for storing pointers, four modify (M) registers for updating pointers and four 
length (L) registers for implementing circular buffers. DAGl addresses data 
memory only and has the capability of bit-reversing its outputs. DAG2 
addresses both program and data memory and can provide addresses for 
indirect branching (jumps and calls) as well as for accessing data. 

For example: 

AX0=DM ( 10 , MO ) ; 

is an indirect data memory read from the location pointed to by 10. Once the 
read is complete, 10 is updated by MO. 

PM (14, M5 ) =MRl ; 

is an indirect program memory data write to the address pointed to by 14 
with a post modify by M5. The instruction 

JUMP (14); 

is an example of an indirect jump. 

12. 1. 1. 1 Always Initialize L Registers 

The ADSP-21xx processors allow two addressing modes for data memory 
accesses: direct and register indirect. Indirect addressing is accomplished by 
loading an address into an I (index) register and specifying one of the 
available M (modify) registers. 

The L registers are provided to facilitate wraparound addressing of circular 
data buffers. A circular buffer is only implemented when an L register is set 
to a non-zero value. For linear (i.e. non-circular) indirect addressing, the L register 
corresponding to the I register used must be set to zero. Do not assume that the L 
registers are automatically initialized or may be ignored; the I, M, and L 
registers contain random values following processor reset. Your program 
must initialize the L registers corresponding to any I registers it uses. 




Processor Core 


DATA ADDRESS GENERATORS 


| DAG1 

(DM addressing only) 
Bit-reverse capability 


DAG2 

(DM and PM addressing) 
Indirect branch capability 


MEMORY INTERFACE 



HOST INTERFACE PORT 
(ADSP-2171, ADSP-2111, ADSP-21msp5x) 



I DMA PORT 
BDMA PORT 

PROGRAMMABLE FLAGS 
(ADSP-2181) 


IDMA Registers 

IDMA Control 
Register 


Programmable 
Flag Registers 


BDMA Registers 
0x3FE4 I BWCOUNT I 


0x3FE3 BDMA Control 


0x3FE6 PFTYPE 
0x3FE5 PFDATA 


12-3 


Figure 12.1 ADSP-21xx Registers 

Shading denotes secondary (alternate) registers. 
Registers are 16 bits wide (unless otherwise marked). 









































12.1.2 Program Sequencer 

Registers associated with the program sequencer control subroutines, 
loops, and interrupts. They also indicate status and select modes of 
operation. 

12.1.2.1 Interrupts 

The ICNTL register controls interrupt nesting and external interrupt 
sensitivity; the IFC register lets you force and clear interrupts in software; 
the IMASK register masks (disables) individual interrupts. The widths of 
the IFC and IMASK registers depend on the processor, since different 
ADSP-21xx processors support different numbers of interrupts. 

The ADSP-2171, ADSP-2181, and ADSP-21msp58/59 support a global 
interrupt enable instruction (ENA INTS) and interrupt disable instruction 
(DIS INTS). 

Interrupts are enabled by default at reset. Executing the disable interrupt 
instruction causes all interrupts to be masked without changing the 
contents of the IMASK register. Disabling interrupts does not affect serial 
port autobuffering, which will operate normally whether or not interrupts 
are enabled. The disable interrupt instruction masks all user interrupts 
including the powerdown interrupt. 

The interrupt enable instruction allows all unmasked interrupts to be 
serviced again. 

12.1.2.2 Loop Counts 

The CNTR register stores the count value for the currently executing loop. 
The count stack allows the nesting of count-based loops to four levels. A 
write to CNTR pushes the current value onto the count stack before 
writing the new value. For example: 

CNTR= 1 0 ; 

pushes the current value of CNTR on the count stack and then loads 
CNTR with 10. 

OWRCNTR is a special syntax with which you can overwrite the count 
value for the current loop without pushing CNTR on the count stack. 
OWRCNTR cannot be read (i.e. used as a source register), and must not be 
written in the last instruction of a DO UNTIL loop. 


12-4 



12.1.2.3 Status And Mode Bits 

The stack status (SSTAT) register contains full and empty flags for stacks. 
The arithmetic status (ASTAT) register contains status flags for the 
computational units. The mode status (MSTAT) register contains control 
bits for various options. MSTAT contains 4 bits that control alternate 
register selection for the computational units, bit-reverse mode for DAG1, 
and overflow latch and saturation modes for the ALU. MSTAT also has 3 
bits to control the MAC result placement, timer enable, and Go mode 
enable. 

Use the Mode Control instruction (ENA, DIS) to conveniently enable or 
disable processor modes. 

12.1.2.4 Stacks 

The program sequencer contains four stacks that allow loop, subroutine 
and interrupt nesting. 

The PC stack is 14 bits wide and 16 locations deep. It stores return 
addresses for subroutines and interrupt service routines, and top-of-loop 
addresses for loops. PC stack handling is automatic for subroutine calls 
and interrupt handling. In addition, the PC stack can be manually pushed 
or popped using the PC Stack Control instructions TOPPCSTACK=reg 
and reg=TOPPCSTACK 

The loop stack is 18 bits wide, 14 bits for the end-of-loop address and 4 
bits for the termination condition code. The loop stack is four locations 
deep. It is automatically pushed during the execution of a DO UNTIL 
instruction. It is popped automatically during a loop exit if the loop was 
nested. The loop stack may be manually popped with the POP LOOP 
instruction. 

The status stack, which is automatically pushed when the processor 
services an interrupt, accommodates the interrupt mask (IMASK), mode 
status (MSTAT) and arithmetic status (ASTAT) registers. The depth and 
width of the status stack varies with each processor, since different 
processors have different numbers of interrupts. The status stack is 
automatically popped when the return from interrupt (RTI instruction) is 
executed. The status stack can be pushed and popped manually with the 
PUSH STS and POP STS instructions. 

The count stack is 14 bits wide and holds counter (CNTR) values for 
nested counter-based loops. This stack is pushed automatically with the 
current CNTR value when there is a write to CNTR. The counter stack 
may be manually popped with the POP CNTR instruction. 



12.1.3 Computational Units 

The registers in the computational units store data. 

The ALU and MAC require two inputs for most operations. The AXO, 

AX1, MXO and MX1 registers store X inputs, and the AYO, AY1, MYO and 
MY1 registers store Y inputs. 

The AR and AF registers store ALU results; AF can be fed back to the ALU 
Y input, whereas AR can provide the X input of any computational unit. 
Likewise, the MRO, MR1, MR2 and MF register store MAC results and can 
be fed back for other computations. The 16-bit MRO and MR1 registers 
together with the 8-bit MR2 register can store a 40-bit multipy/ accumulate 
result. 

The shifter can receive input from the ALU or MAC, from its own result 
registers, or from a dedicated shifter input (SI) register. It can store a 32-bit 
result in the SRO and SRI registers. The SB register stores the block 
exponent for block floating-point operations. The SE register holds the 
shift value for normalize and denormalize operations. 

Registers in the computational units have secondary registers, shown in 
Figure 12.1 as second set of registers behind the first set. Secondary 
registers are useful for single-cycle context switches. The selection of these 
secondary registers is controlled by a bit in the MSTAT (mode status) 
register; the bit is set and cleared by these instructions: 

ENA SEC_REG; (select secondary registers} 

DIS SEC_REG; (select primary registers} 

12.1.4 Bus Exchange 

The PX register is an 8-bit register that allows data transfers between the 
16-bit DMD bus and the 24-bit PMD bus. In a transfer between program 
memory and a 16-bit register, PX provides or receives the lower eight bits. 

12.1.5 Timer 

The TPERIOD, TCOUNT and TSCALE hold the timer period, count and 
scale factor values, respectively. These registers are memory-mapped at 
locations 0x3FFD, 0x3FFC, and 0x3FFB respectively. 



12.1.6 Serial Ports 

SPORTO and SPORT1 each have receive (RX), transmit (TX) and control 
registers. The control registers are memory-mapped registers at locations 
Ox3FEF-Ox3FFA in data memory. SPORTO also has registers for 
controlling its multichannel functions. Each SPORT control register 
contains bits that control frame synchronization, companding, word 
length and, in SPORTO, multichannel options. The SCLKDIV register for 
each SPORT determines the frequency of the internally generated serial 
clock, and the RFSDIV register determines the frequency of the internally 
generated receive frame sync signal for each SPORT. The autobuffer 
registers control autobuffering in each SPORT. 

Programming a SPORT consists of writing its control register and, 
depending on the modes selected, its SCLKDIV and/or RFSDIV registers 
as well. The following example code programs SPORTO for 8-bit p-law 
companding, normal framing, and an internally generated serial clock. 
RFSDIV is set to 255, for 256 SCLK cycles between RFS assertions. 
SCLKDIV is set to 2, resulting in an SCLK frequency that is 1/6 of the 
CLKOUT frequency. 

SI=0xB27 ; 

DM ( 0X3FF6) =SI ; {SPORTO control register} 

SI=2 ; 

DM ( 0x3FF5 ) =SI ; {SCLKDIV = 2} 

SI=255 ; 

DM ( 0x3 FF4 ) =SI ; {RFSDIV = 255} 

1 2.1 .7 Memory Interface & SPORT Enables 

The System Control Register, memory-mapped at DM(0x3FFF), contains 
SPORT enables as well as the SPORT1 configuration selection. On all 
ADSP-21xx processors except the ADSP-2181, it also contains fields for 
controlling the booting operation: selecting the page, specifying the 
number of wait states and forcing the boot in software. The System 
Control Register also contains the PWAIT field which specifies the 
number of wait states for external program memory accesses. 

The Wait State Control Register, memory-mapped at data memory 
location 0x3FFE, contains fields that specify the number of wait states for 
each bank of data memory. On the ADSP-2181, it also specifies the number 
of wait states for I/O memory space. In processors with optional on-chip 
ROM, it also contains a bit for enabling the ROM. 



^ CQ 


On the ADSP-2181, wait states are applied to external memory overlay 
accesses. Other memory-mapped registers control the IDMA port and 
byte memory DMA port for booting operations — selecting the byte 
memory page, specifying the number of wait states, and forcing the boot 
from software — and runtime access of byte memory. 

12.1.8 Host Interface 

The ADSP-2171, ADSP-2111, ADSP-21msp58/59 processors contain a host 
interface port (HIP). The host interface has six data registers, two status 
registers and an interrupt mask register. These registers are memory- 
mapped at data memory locations 0x3FE7 - 0x3FE0. The status registers 
contains status flags for each of the data registers. The HMASK register 
lets you enable or disable the generation of HIP read or HIP write 
interrupts independently for each HIP data register. HMASK is memory- 
mapped at data memory location 0x3FE8. 

12.1.9 Analog Interface 

The analog interface of the ADSP-21msp58/59 has four memory-mapped 
registers. These registers are memory-mapped in data memory locations 
0x3FEC - 0x3FEF. The transmit register sends data to the DAC for 
transmitting. The receive register receives data from the ADC. The analog 
control register contains bits that select amplifier, gain, analog input and 
filter options. 


12.2 PROGRAM EXAMPLE 

Listing 12.1 presents an example of an FIR filter program written for the 
ADSP-2111 with discussion of each part of the program. The program can 
also be executed on any other ADSP-21xx processor, with minor 
modifications. This FIR filter program demonstrates much of the conceptual 
power of the ADSP-2100 family architecture and instruction set. 


(ADSP-2111 FIR Filter Routine 


-serial port 0 used for I/O 
-internally generated serial clock 

-12.288 MHz processor clock rate is divided to 1.536 MHz serial clock 
-serial clock divided to 8 kHz frame sampling rate} 


.MODULE/RAM/ABS=0 
. INCLUDE 

. VAR/ DM/RAM/ABS= 0x3 800 /CIRC 
.VAR/PM/RAM/CIRC 
. GLOBAL 
. EXTERNAL 
. INIT 


main_routine; (program loaded from } 
(EPROM, with MMAP=0 } 

<const.h>; 

data_buf fer [taps] ; (on-chip data buffer} 
coefficient [taps] ; 
data_buffer, coefficient; 
fir_start; 

coefficient : <coef f . dat> ; 


12-8 



{code starts here} 

{load interrupt vector addresses} 



JUMP restarter; NOP; 
RTI; NOP; NOP; NOP; 
RTI; NOP; NOP; NOP; 
RTI; NOP; NOP; NOP; 
RTI; NOP; NOP; NOP; 

NOP; NOP; 

{restart interrupt} 
{IRQ2 interrupt} 

{HIP write interrupt} 
{HIP read interrupt} 
{SPORTO transmit int} 

JUMP fir_start; NOP; 
RTI; NOP; NOP; NOP; 
RTI ; NOP; NOP; NOP; 
RTI; NOP; NOP; NOP; 

{initializations} 

NOP; NOP; 

{SPORTO receive int} 
{SPORT1 transmit int} 
{ SPORT1 receive int} 
{TIMER interrupt} 

restarter : 

L0=%data_buf fer; 

{setup 

circular buffer length} 


L4=%coeff icient ; 

{setup 

circular buffer length} 


M0=1; 

M4 = 1 ; 

{modify=l for increment through 


lO= / 'data_buf fer; 

{point 

to data start} 


I4= A coef f icient ; 

CNTR=%data_buf fer ; 

{point 

to coeff start} 

clear: 

DO clear UNTIL CE; 

DM (10, MO) =0; 

{clear 

data buffer} 


{set up memory-mapped control registers} 



AX0=191 ; 

DM ( 0x3 FF4 ) =AX0 ; 
AX0=3 ; 

{set up divide value for 8KHz RFS} 


DM ( 0x3 FF5 ) =AX0 ; 
AX0=0x69B7; 

{1.536MHz internal serial clock} 


DM ( 0x3FF6 ) =AX0 ; 

{multichannel disabled} 

{internally generated serial clock} 
{receive frame sync required} 
{receive width 0} 

{transmit frame sync required} 
{transmit width 0} 

{int transmit frame sync disabled} 
{int receive frame sync enabled} 
{u-law companding} 

{8 bit words} 


AX0=0x7000 ; 

DM ( 0x3 FFE) =AX0; 

{DM wait states: } 

{ Ox3400-Ox37FF 7 waits} 

{ all else 0 waits} 


AXO=OxlOOO; 

DM ( 0x3 FFF) =AX0; 

{SPORTO enabled} 

{boot from boot page 0} 

{0 PM waits} 

{0 boot memory waits} 


ICNTL = 0x00; 

IMASK = 0x0018; 

{enable SPORTO interrupt only} 

ma inloop: 

IDLE; 

JUMP mainloop; 

{wait for interrupt} 

.ENDMOD; 



Listing 12.1 Program Example Listing (Setup & Main Loop Routine) -j 2 - 


12-9 



. CONST 


taps=15, taps_less_one=14 ; 


Listing 12.1 (cont.) Include File, Constants Initialization 

12.2.1 Example Program: Setup Routine Discussion 

The setup and main loop routine performs initialization and then loops on 
the IDLE instruction to wait until the receive interrupt from SPORTO 
occurs. The filter is interrupt-driven. When the interrupt occurs control 
shifts to the interrupt service routine (shown in Listing 12.2). 

Line A of the program shows that the constant declarations are contained 
in a separate file. 

Section B of the program includes the assembler directives defining two 
circular buffers in on-chip memory: one in data memory RAM (used to 
hold a delay line of samples) and one in program memory RAM (used to 
store coefficients for the filter). The coefficients are actually loaded from 
an external file by the linker. These values can be changed without 
reassembling; only another linking is required. 

Section C shows the setup of interrupts. Since this code module is located 
at absolute address zero (as indicated by the ABS qualifier in the 
.MODULE directive), the first instruction is placed at the restart vector: 
address 0x0000. The first location is the restart vector instruction, which 
jumps to the routine restarter. Interrupt vectors that are not used are filled 
with a return from interrupt instruction followed by NOPs. (Since only 
one interrupt will be enabled, this is only a thorough programming 
practice rather than a necessity.) The SPORTO receive interrupt vector 
jumps to the interrupt service routine. 

Section D, restarter, sets up the index (I), length (L), and modify (M) 
registers used to address the two circular buffers. A non-zero value for 
length activates the processor's modulus logic. Each time the interrupt 
occurs, the I register pointers advance one position through the buffers. 
The clear loop zeroes all values in the data memory buffer. 

Section E, after clear, sets up the processor's memory-mapped control 
registers used in this system. See Appendix E for control register 
initialization information. 


12-10 



SPORTO is set up to generate the serial clock internally at 1 .536 MHz, 
based on a processor clock rate of 12.288 MHz. The RFS and TFS signals 
are both required and the RFS signal is generated internally at 8 kHz, 
while the TFS signal comes from the external device communicating with 
the processor. 

Finally, SPORTO is enabled and the interrupts are enabled. Now the IDLE 
instruction causes the processor to wait for interrupts. After the return 
from interrupt instruction, execution resumes at the instruction following 
the IDLE instruction. Once these setup instructions have been executed, 
all further activity takes place in the interrupt service routine, shown in 
Listing 12.2. 

.MODULE/ROM fir_routine; {relocatable FIR interrupt module} 

.INCLUDE <const.h>; {include constant declarations} 

.ENTRY fir_start; {make label visible outside module} 

.EXTERNAL data_buffer, coefficient; {make globals accessible in module} 

{interrupt service routine code} 

FIR_START: CNTR = taps_less_one ; 

SI = RXO; 

DM (10, MO) = SI; 

MR=0, MY0=PM(I4,M4) , MX0=DM ( 10 , MO ) ; 

DO convolution UNTIL CE; 

convolution: MR=MR+MX0*MY0 (SS) , MY0=PM(I4,M4) , MX0=DM 

MR=MR+MX0 *MY0 (RND) ; 

TXO = MRl ; 

RTI ; 

•ENDMOD; 

Listing 12.2 Interrupt Routine 

12.2.2 Example Program: Interrupt Routine Discussion 

This subroutine transfers the received data to the next location in the 
circular buffer (overwriting the oldest sample). All samples and 
coefficients are then multiplied and the products are accumulated to 
produce the next output value. The subroutine checks for overflow and 
saturates the output value to the appropriate full scale, then writes the 
result to the transmit section of SPORTO and returns. 

The first four lines of the listing declare the code module (which is 
relocatable rather than placed at an absolute address), include the same 
file of constants, and make the entry point visible to the main routine with 
the ENTRY directive. Likewise, the .EXTERNAL directive makes the 
main routine labels visible in the interrupt routine. 


{N-l passes within DO UNTIL} 
{read from SPORTO} 

{transfer data to buffer} 
{set up multiplier for loop} 
{CE = counter expired} 

(10, MO) ; 

{MAC these, fetch next} 
{Nth pass with rounding} 
{write to sport} 

{return from interrupt} 


12-11 




The subroutine begins by loading the counter register (CNTR). The new 
sample is read from SPORTO's receive data register, RXO, into the SI 
register; the choice of SI is of no particular significance. Then, the data is 
written into the data buffer. Because of the automatic circular buffer 
addressing, the new data overwrites the oldest sample. The N-most recent 
samples are always in the buffer. 

The fourth instruction of the routine, MR= 0 , MYO = PM ( 1 4 , M4 ) , 

MX0=DM ( 10 , MO ), zeroes the multiplier result register (MR) and fetches 
the first two operands. This instruction accesses both program and data 
memory but still executes in a single cycle because of the processor's 
architecture. 

The convolution label identifies the loop itself, consisting of only two 
instructions, one setting up the loop (DO UNTIL) and one "inside" the 
loop. The MAC instruction multiplies and accumulates the previous set of 
operands while fetching the next ones from each memory. This instruction 
also accesses both memories. 

The final value is transferred back to SPORTO, to the transmit data register 
TXO, to be sent to the communicating device. 


12-12 



Hardware Examples H 13 


13.1 OVERVIEW 

This chapter describes some hardware examples of circuits that can be 
interfaced to the ADSP-21xx serial ports, host interface port (HIP), or the 
memory port. As with any hardware design, it is important that timing 
information be carefully analyzed. Therefore, the data sheet for the 
particular ADSP-2100 family processor used should be used in addition to 
the information presented in this chapter. 


13-1 




1 3.2 BOOT LOADING FROM HOST USING BUS REQUEST & GRANT 

All ADSP-2100 family processors that have internal program memory 
RAM support boot loading. With boot loading, the processor reads 
instructions from a byte-wide external memory device (usually an 
EPROM) over the memory interface and stores the instructions in the 24- 
bit wide internal program memory. Once the external memory device is 
set up to provide bytes in the proper order, the boot operation can run 
automatically and transparently at reset or when forced in software. See 
Chapter 10, "Memory Interface." 

In some systems where the ADSP-21xx is controlled by a host processor, it 
is necessary to boot the DSP directly from the host. In this case the host, 
rather than an EPROM, is the source of bytes to be loaded into on-chip 
memory. If the ADSP-21xx has a host interface port (such as the ADSP- 
2111), it can perform automatic boot loading through this port. If the 
processor does not have a host interface port, however, it can still boot 
through the memory interface using the bus request signal, as described 
below. 

This example shows a simple way to download programs from a host 
processor to the internal program memory of an ADSP-21xx. There are 
several techniques for connecting a DSP processor to a host. The choice of 
which technique to use depends upon the I/O structure of the host, 
availability of I/O port lines, and the amount of address decoding logic 
already available in the system. 

Figure 13.1 illustrates a minimal system implementation to allow a 
microcontroller to boot an ADSP-21xx. The only hardware required is a D- 
type flip-flop and a 5 k£2 resistor. The resistor is used to pull the ADSP- 
21xx's BMS pin (Boot Memory Select) high. 

The ADSP-21xx automatically enters its booting sequence after the 
processor is reset (when the MM AP pin is tied low) or when software 
initiates a reboot operation. When the ADSP-21xx begins to fetch a byte 
from external boot memory (in this case, the host processor), it asserts 
BMS. When BMS goes low, the flip-flop is preset and the Q output 
brought low. This low signal asserts BR (bus request) on the ADSP-21xx. 
When bus request is recognized by the ADSP-21xx, the current execution 
cycle is allowed to finish and then processor operation is suspended. The 
ADSP-21xx then asserts BG (bus grant) in the next cycle (after BR is 
recognized). 


13-2 



VDD 



Figure 13.1 ADSP-21xx Booting From Host 


13-3 




When a low-level signal at the D input is clocked into the flip-flop, the Q 
output is brought high, deasserting BK. 

The bus request pin (BK) of the ADSP-21xx is used to stop and 
synchronize the booting process. The host releases bus request, causing 
the ADSP-21xx to read one byte of boot data. During the read operation 
the BMS pin is asserted, which in turn causes the BE pin to be asserted 
and the ADSP-21xx to be put back into a bus request state. The ADSP-21xx 
remains suspended, waiting for the next byte of boot data. 

Three programmable port bits of the microcontroller (PB 8-10) are used to 
provide the handshake mechanism for the transfer of each byte of boot 
data. Alternately, PB9 and PB10 could be implemented as a memory- 
mapped port location. PB8 is used to bring the ADSP-21xx out of reset, 
starting the boot process. Note that if PB8 is not low at power-up, the 
ADSP-21xx will start executing undefined instructions until PB8 is 
brought low. 

The boot data is presented by the microcontroller either through 8 port 
bits (PBO-7) or through a memory-mapped port. The PBO-7 bits should be 
put into a high-impedance state after the boot is complete, to prevent bus 
contention if the ADSP-21xx tries to write to external memories or 
peripherals. 

A typical boot sequence for this system is as follows: 

1. ) Bring PB8 low to reset the ADSP-21xx. 

2. ) Clock a high state into the flip-flop with PB9 and PB10 to bring BK low. 

3. ) Bring PB8 high to bring the ADSP-21xx out of reset. 

4. ) Place a byte of boot data on the data bus (PBO-7.). 

5. ) Clock a low state into the flip-flop with PB9 and PB10 to bring BK high. 

6. ) Wait a minimum of six processor cycles while the ADSP-21xx fetches 

the data byte and the flip-flop asserts BK. 

7. ) Repeat steps 4, 5, and 6 for each byte of boot data. After the last 

iteration, the ADSP-21xx will automatically start execution. 




Note: The proper loading sequence for boot data must be followed (i.e. the 
order in which the host passes bytes to the ADSP-21xx). This sequence is 
described in the Chapter 10, "Memory Interface." To create a file for 
booting, use the PROM Splitter utility of the ADSP-2100 Family 
Development Software. The PROM Splitter automatically organizes the 
bytes in the proper order for booting. 


13.3 SERIAL PORT TO CODEC INTERFACE 

A codec (COder/ DECoder) incorporates analog-to-digital conversion, 
digital-to-analog conversion, and filtering in one device. The codec shown 
in this example also performs pulse-code modulation (PCM) encoding and 
decoding according to the CCITT ji-law standard. PCM compresses digital 
data so that fewer bits are needed to store the same information. The 
ADSP-21xx serial ports have both p-law and A-law companding 
(compressing/ expanding) capability. 

In the example described here, a codec converts its analog input to digital 
data, compresses it and sends it serially to the SPORT on an ADSP-21xx 
processor. At the same time, the processor sends compressed serial data 
via the SPORT to the codec, which expands the data and converts the 
result to an analog signal. 


13-5 



Figure 13.2 shows an industry standard p-law companding codec 
connected to a serial port (in this case, SPORTO) on an ADSP-21xx 
processor. The codec's analog input at VFXI+ is internally amplified by a 
gain which is controlled by the resistor combination at GSX and VFXI-. 
The gain is 

20 x log (R1 + R2)/R2 
in this case, 20 log 2. 

The ADSP-21xx controls codec operation by supplying master and bit 
clock signals. In the configuration shown, the codec transmit and receive 
sections operate synchronously. MCLKR and MCLKX are the master 
clocks for the receive and transmit sections of the codec, respectively. 
BCLKX is the bit clock and in this configuration is used for clocking both 
received and transmitted serial data. MCLKR, MCLKX and BCLKX must 
be synchronous and in this case they are the same signal, namely the 
SCLKO output generated by the ADSP-21xx processor. The BCLKR/ 
CLKSEL input, tied low, selects the frequency of MCLKX to be 2.048 MHz. 
The ADSP-21xx must be programmed for internal SCLKO generation at 
2.048 MHz. 


From Input 
Amplifier 


To Output 
Amplifier 



Figure 13.2 ADSP-21xx Serial Port (SPORTO) To CODEC 


13-6 




The processor uses frame synchronization signals to tell the codec to send 
and receive data. To transmit data to the codec, it sends a TFSO pulse to 
the FSR input of the codec and then outputs the eight bits on DTO on the 
next eight serial clock periods. The codec receives the data on its DR input. 
Likewise, the processor initiates a data receive operation by sending an 
RFSO pulse to the codec's FSX input, which causes the codec to output 
eight bits on its DX output on the next eight serial clock periods. The 
processor receives the data on its DRO input. The ADSP-21xx must be 
programmed to use normal framing, 8-bit data words, and internal, active- 
high frame sync generation. 

The ADSP-21xx code shown in Listing 13.1 configures SPORTO for 
operation as required in this example: 

• Internally generated serial clock 

• 2.048 MHz serial clock frequency 

• Both transmit and receive frame syncs required 

• Use normal framing for both transmit and receive 

• Internally generated transmit and receive frame syncs 

• Both frame syncs active high 

• Word length of eight bits 

• p-law companding 

This code assumes the processor operating at 12.288 MHz. The code also 
sets up the processor to request data from the codec at an 8 kHz rate (this 
register is not initialized at reset and should always be written before the 
SPORT is enabled if RFS is generated internally). The processor transmits 
data as needed by the program it is executing. 


AX0=0x6927; {Int SCLK, RFS/TFS req, norm framing,} 

DM ( 0x3 FF 6 ) =AX0 ; {generate RFS, active HI, Mu-law, word length 8} 


AX0=2; 

DM ( 0x3 FF5 ) =AX0 ; 


{value of SCLKDIV for 2.048 MHz} 
{with a 12.888 MHz CLKOUT} 


AX0=255; 

DM ( 0x3 FF4 ) =AX0 ; 


{RFSDIV=256 , 256 SCLKs between} 
{frame syncs, 8 kHz framing} 


AX0=0xl038; {enable SPORTO only, leave defaults} 

DM ( 0x3FFF) =AX0; 


Listing 13.1 Serial Port Initialization Example 




13.4 SERIAL PORT TO DAC INTERFACE 

Any DSP process must ultimately output analog information. The serial 
port of the ADSP-21xx processors can send data directly to a DAC (digital- 
to-analog converter) for conversion to an analog signal. 

Analog Devices' AD766 is a DAC that requires no extra logic to interface 
to the SPORT. The AD766 receives 16-bit data words serially, MSB first, 
which it then converts to an analog signal. Its digital interface consists of 
three inputs: DATA, the serial data input; CLK, for clocking data into the 
DAC (active low because data is clocked on the falling edge) and LE (latch 
enable), which latches each 16-bit word into the conversion section of the 
DAC. 

The serial port connection to the AD766 is shown in Figure 13.3. In this 
configuration, the processor generates SCLK internally and provides it to 
the DAC. Serial data is output from the DT pin to the DATA input of the 
DAC. The TFS signal provides the DAC's LE input. 


ADSP-21xx 


AD766 

TFS 

► 

LE 

SPORT DT 

► 

DATA VOUT 

SCLK 

► 

CLK 


Figure 13.3 Serial Port Interface To AD766 DAC 


LE should go low on the clock cycle after the LSB (sixteenth bit) of a word 
is transmitted, to latch the 16-bit word into the DAC. To provide this 
timing, TFS is configured for the alternate framing mode, non-inverted; it 
goes high when the first bit is transmitted and low after the last bit is 
transmitted. This low-going edge latches the word into the AD766. The 
only restriction is that the SPORT cannot transmit continuously; there 
must be a break in between the last bit of one word and the first bit of the 
next so that TFS can go low. Figure 13.4 shows the timing. 


13-8 




SCLK 


DT 


-0ccd5 — & 



Latches data into DAC 


Figure 13.4 SPORT To AD766 DAC Timing 

The configuration of the SPORT control registers for this application is 
shown in Figure 13.5. 


SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 


15 14 13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

1 Ifjj 


1 

1 

1 

| 

0 


FI 

0 

1 

1 

1 

n 




. 

. 


1 



i 

— 





SCLK generated internally 
Transmit framing required 
Alternate transmit framing 
Internally generated TFS — 


Word Length = 16 bits 
Data format = right justify, zero fill 


Non-inverted TFS 


Figure 13.5 SPORT To AD766 DAC Control Register Settings 


13-9 



1 3.5 SERIAL PORT TO ADC INTERFACE 

An ADC (analog-to-digital converter) converts an analog signal to digital 
samples that a DSP processor can operate on. The ADSP-21xx processors 
can receive data from an ADC directly through a serial port. 

Analog Devices' AD7872 is an ADC that requires no extra logic to 
interface to the SPORT. The AD7872 converts an analog signal to 14-bit 
samples. Each sample is padded with two zero MSBs to yield 16-bit 
samples. The AD7872 outputs each sample serially, MSB first. Its digital 
interface consists of three pins: SDATA, the serial data output; SCLK, for 
clocking data out; and SSTRB, (serial strobe), which frames each serial 
word. 


The serial port connection to the AD7872 is shown in Figure 13.6. The 
timer regulates sampling via the CONVST input at a constant frequency. 
Instead of the timer, an unused serial clock or flag output from the ADSP- 
21 xx processor can be programmed to generate the CONVST signal. The 
AD7872 generates SCLK internally and provides it to the processor. With 
the CONTROL input held at -5 V, the SCLK signal is continuous, running 
even when no data is being output. 



Figure 13.6 Serial Port Interface To AD7872 ADC 


Serial data is output from the SDATA output of the ADC to the 
processor' s DR pi n. The SSTRB signal provides the RFS input to the 
processor. SSTRB goes low when the first bit is transmitted to the 
processor. Figure 13.7 shows the timing of the serial data transfer. 


13-10 





SCLK 



vy\y~\/\y^^ - YyT_ 


DR 


^ MSB (0) 


zznx 


■# 


■# 




Figure 13.7 SPORT To AD7872 ADC Timing 

RFS is configured for the alternate framing mode, externally generated, 
with inverted (active low) logic. The SPORT must also be programmed for 
external serial clock and a serial word length of 16 bits. The configuration 
of the SPORT control register for this application is shown in Figure 13.8. 


SPORTO Control Register: 0x3FF6 
SPORT1 Control Register: 0x3FF2 


15 14 13 12 11 10 9 8 


6 





fill] o 



Word Length = 16 bits 
Data format = right justify, zero fill 


Inverted RFS 


Figure 13.8 SPORT To AD7872 ADC Control Register Settings 


13-11 



13.6 SERIAL PORT TO SERIAL PORT INTERFACE 

The serial ports provide a convenient way to transfer data between ADSP- 
21 xx processors without using external memory or the memory bus and 
without halting either processor. The serial ports are connected as shown 
in Figure 13.9 — in this example, SPORT1 of processor #1 is connected to 
SPORTO of processor #2. 

The serial clock used by both processors is generated internally by 
processor #1. Processor #2 is configured to receive its serial clock 
externally. The serial port control registers should be set up with the 
following parameters. 


Processor 1, SPORT1 

SCLKDIV = system-dependent 

SLEN = system-dependent 

ISCLK = 1 

TFSR = 1 

RFSR = 1 

IRFS = 0 

ITFS = 1 

RFSDIV = don't care 


Processor 2, SPORTO 

SCLKDIV = system-dependent 

SLEN = system-dependent 

ISCLK = 0 

TFSR = 1 

RFSR = 1 

IRFS = 0 

ITFS = 1 

RFSDIV = don't care 


TFSW1 = RFSW1 = TFSW2 = RFSW2 = system-dependent 
INVRFS1 = INVTFS1 = INVRFS2 = INVTFS2 = system-dependent 


RFS1 



TFSO 

TFS1 

► 

RFSO 

ADSP-21xx SP0RT1 DT1 


p R0 SPORTO ADSP-21XX 

#1 


#2 

DR1 



SCLK1 

► 

SCLKO 


Figure 13.9 Serial Port interface Between Two ADSP-21xx Processors 

Frame synchronization is used to coordinate the transfer of serial data. 
Each processor generates a transmit frame sync (TFS) signal internally and 
expects to receive its receive frame sync (RFS) signal externally, from the 
other processor. The framing mode can be normal or alternate, but must 
be the same for both SPORTs. Likewise, the SPORTs must be configured 
for the same serial word length and companding type, if companding is 
used, or data format if companding is not used. 


13-12 




The autobuffering capability of the serial ports can be used in this 
configuration to transfer an entire buffer of data from the data memory 
space of one processor to the other's, without interrupt overhead. The serial 
ports handshake automatically — when one processor writes its' TXO 
register, the data is automatically transmitted to the other processor's RXO 
register and an autobuffer cycle is generated. 

In fact, autobuffer transfers can occur in both directions at the same time, 
in the background, while each processor is executing some other primary 
function. Each SPORT will generate an interrupt when the autobuffer 
transfer is complete. The description of autobuffering in the Serial Port 
chapter shows an example of the code for setting up autobuffering. 

13.7 80C51 INTERFACE TO HOST INTERFACE PORT 

The host interface port (HIP) on the ADSP-2111, ADSP-2171, and ADSP- 
21msp5x processors facilitates communication with a host microcomputer 
such as the Intel 80C51. An example connection is shown in Figure 13.10. 
In this example, the HIP data registers (HDRs) and HIP status registers 
(HSRs) of the ADSP-2111 occupy eight contiguous locations in the 
memory space of the 80C51. 



+5 v +5 v 

Figure 13.10 Host Port Interface to 80C51 Microcomputer 


13-13 




To access one of the HIP registers, the 80C51 asserts ALE and outputs a 
16-bit address, with the upper half on P2.0-2.7 and the lower half on 
P0.0-0.7. The upper half is decoded to select the HIP via HSEL, and the 
lower half selects the HIP register via HADO-7. The ALE assertion causes 
the HIP to latch the address so that the 8-bit data can then be transferred 
on the HADO-7 lines. The 80C51 asserts WR for a write or RD for a read. 

In this example, the 80C51 reads and writes 8-bit data, so the ADSP-2111's 
HSIZE input is tied high. Only the lower eight bits of each HIP register are 
used. HMDO is tied low because the 80C51 uses separate read and write 
strobes rather than a single Read /Write line. HMD1 is tied high because 
the address and data use the same bus (time-multiplexed using ALE) 
rather than separate buses. 


13-14 



Software Examples 11 14 


14.1 OVERVIEW 

This chapter provides a brief summary of the development process that you 
use to create executable programs for the ADSP-2100 family processors. The 
summary is followed by a number of software examples that can give you an 
idea of how to write your own applications. 

The software examples presented in this chapter are used a variety of DSP 
operations. The FIR filter and cascaded biquad IIR filter are general filter 
algorithms that can be tailored to many applications. Matrix multiplication is 
used in image processing and other areas requiring vector operations. The sine 
function is required for many scientific calculations. The FFT (fast Fourier 
transform) has wide application in signal analysis. Each of these examples is 
described in greater detail in Digital Signal Processing Applications Using The 
ADSP-2100 Family, Volume 1, available from Prentice Hall. They are presented 
here to show some aspects of typical programs. 

The FFT example is a complete program, showing a subroutine that performs 
the FFT and a main calling program that initializes registers and calls the FFT 
subroutine as well as an auxiliary routine. 

Each of the other examples is shown as a subroutine in its own module. The 
module starts with a .MODULE directive that names the module and ends 
with the .ENDMOD directive. The subroutine can be called from a program in 
another module that declares the starting label of the subroutine as an external 
symbol. This is the same label that is declared with the .ENTRY directive in the 
subroutine module. The last instruction in each subroutine is the RTS 
instruction, which returns control to the calling program. 


14-1 



Each module is prefaced by a comment block that provides the following 
information: 


Calling Parameters 


Return Values 
Altered Registers 


Computation Time 


Register values that the calling program must 
set before calling the subroutine 

Registers that hold the results of the subroutine 

Registers used by the subroutine. The calling 
program must save them before calling the 
subroutine and restore them afterward if it 
needs to preserve their values. 

The number of instruction cycles needed to 
perform the subroutine 


14.2 SYSTEM DEVELOPMENT PROCESS 

The ADSP-2100 family of processors is supported by a complete set of 
development tools. Programming aids and processor simulators facilitate 
software design and debug. In-circuit emulators and demonstration 
boards help in hardware prototyping. 

The software development system includes several programs: System 
Builder, Assembler, Linker, PROM Splitter, Simulators and C Compiler 
with Runtime Library. These programs are described in detail in the 
ADSP-2100 Family Assembler Tools & Simulator Manual, ADSP-2100 Family 
C Tools Manual, and ADSP-2100 Family C Runtime Library Manual. 

Figure 14.1 shows a flow chart of the system development process. 

The development process begins with the task of describing the hardware 
environment for the development software. You create a system 
specification file using a text editor. This file contains simple directives 
that describe the locations of memory and I/O ports, the type of 
processor, and the state of the MMAP pin in the target hardware 
configuration. The system builder reads this file and generates an 
architecture description file which passes information to the linker, 
simulator and emulator. 

You begin code generation by creating source code files in C language or 
assembly language. A module is a unit of assembly language comprising a 
main program, subroutine, or data variable declarations. C programmers 





o = USER FILE OR HARDWARE 
□ = SOFTWARE DEVELOPMENT TOOL 
O a HARDWARE DEVELOPMENT TOOL 


Figure 14.1 ADSP-2100 Family System Development Process 

write C language files and use the C compiler to create assembly code modules 
from them. Assembly language programmers write assembly code modules 
directly. Each code module is assembled separately by the assembler. 

The linker links several modules together to form an executable program 
(memory image file). The linker reads the target hardware information from the 
architecture description file to determine appropriate addresses for code and 
data. In the assembly modules you may specify each code/ data fragment as 
completely relocatable, relocatable within a defined memory segment, or non- 
relocatable (placed at an absolute address). 


14-3 














The linker places non-relocatable code or data modules at the specified 
memory addresses, provided the memory area has the correct attributes. 
Relocatable objects are placed at addresses selected by the linker. The 
linker generates a memory image file containing a single executable 
program which may be loaded into a simulator or emulator for testing. 

The simulator provides windows that display different portions of the 
hardware environment. To replicate the target hardware, the simulator 
configures its memory according to the architecture description file 
generated by the system builder, and simulates memory-mapped I/O 
ports. This simulation allows you to debug the system and analyze 
performance before committing to a hardware prototype. 

After fully simulating your system and software, you can use an EZ-ICE 
in-circuit emulator in the prototype hardware to test circuitry, timing, and 
real-time software execution. 

The PROM splitter software tool translates the linker-output program 
(memory image file) into an industry-standard file format for a PROM 
programmer. Once you program the code in PROM devices and install an 
ADSP-21xx processor into your prototype, it is ready to run. 


14.3 SINGLE-PRECISION FIR TRANSVERSAL FILTER 

An FIR transversal filter structure can be obtained directly from the 
equation for discrete-time convolution. 

N-l 

y(n) = X h k (n) x(n-k) 
k=0 

In this equation, x(n) and y(n) represent the input to and output from the 
filter at time n. The output y(n) is formed as a weighted linear 
combination of the current and past input values of x, x(n-k). The weights, 
hk(n), are the transversal filter coefficients at time n. In the equation, 
x(n-k) represents the past value of the input signal "contained" in the 
(k+l)th tap of the transversal filter. For example, x(n), the present value of 
the input signal, would correspond to the first tap, while x(n-42) would 
correspond to the forty-third filter tap. 


14-4 



The subroutine that realizes the sum-of-products operation used in 
computing the transversal filter is shown in Listing 14.1. 

.MODULE f ir_sub; 


FIR Transversal Filter Subroutine 
Calling Parameters 

10 — > Oldest input data value in delay line 
LO = Filter length (N) 

14 — > Beginning of filter coefficient table 
L4 = Filter length (N) 

Ml , M5 = 1 

CNTR = Filter length - 1 (N-l) 

Return Values 

MR1 = Sum of products (rounded and saturated) 
10 — > Oldest input data value in delay line 
14 — > Beginning of filter coefficient table 

Altered Registers 
MXO , MYO , MR 

Computation Time 

N - 1 + 5 + 2 cycles 

All coefficients and data values are assumed to be 
in 1.15 format. 


.ENTRY fir; 

fir: MR=0 , MX0=DM ( 10 , Ml ) , MY0=PM(I4,M5) ; 

DO sop UNTIL CE; 

sop: MR=MR+MX0*MY0 (SS) , MX0=DM ( 10 , Ml ) , MY0=PM ( 14 , M5 ) ; 

MR-MR+MXO *MY0 (RND) ; 

IF MV SAT MR; 

RTS ; 

.ENDMOD; 

Listing 14.1 Single-Precision FIR Transversal Filter 


14-5 




14.4 CASCADED BIQUAD HR FILTER 

A second-order biquad HR filter section is represented by the transfer 
function (in the z-domain): 

H(z) = Y(z)/X(z) = ( B 0 + B^" 1 + B 2 z ~ 2 )/( 1 + AjZ -1 + A 2 z~ 2 ) 

where Ay A 2 , B 0 , Bi and B 2 are coefficients that determine the desired 
impulse response or the system H(z). The corresponding difference 
equation for a biquad section is: 

Y(n) = B 0 X(n) + BjXfn-l) + B 2 X(n-2) - AjYfn-l) - A 2 Y(n-2) 

Higher-order filters can be obtained by cascading several biquad sections 
with appropriate coefficients. The biquad sections can be scaled separately 
and then cascaded in order to minimize the coefficient quantization and 
the recursive accumulation errors. 

A subroutine that implements a high-order filter is shown in Listing 14.2. 
A circular buffer in program memory contains the scaled biquad 
coefficients. These coefficients are stored in the order: B 2 , By B Q/ A 2 and A 1 
for each biquad. The individual biquad coefficient groups must be stored 
in the order that the biquads are cascaded. 


.MODULE biquad_sub; 

{ Nth order cascaded biquad filter subroutine 

Calling Parameters: 

SRl=input X(n) 

10 — > delay line buffer for X(n-2), X(n-l) , 

Y (n-2 ) , Y(n-l) 

L0 = 0 

11 — > scaling factors for each biquad section 
LI = 0 (in the case of a single biquad) 

LI = number of biquad sections 
(for multiple biquads) 

14 — > scaled biquad coefficients 
L4 = 5 x [number of biquads] 

MO, M4 = 1 

Ml = -3 

M2 = 1 (in the case of multiple biquads) 

M2 = 0 (in the case of a single biquad) 

M3 = (1 - length of delay line buffer) 


14-6 



Return Value : 

SRI = output sample Y(n) 

Altered Registers: 

SE, MXO, MX1, MYO, MR, SR ■ 

Computation Time (with N even) : 

ADSP-2101/2102 : (8 x N/2) + 5 cycles 

ADSP-2 100/2 10 OA: (8 x N/2) +5+5 cycles 

All coefficients and data values are assumed to 
be in 1.15 format 

} 

.ENTRY biquad; 

biquad: CNTR = number_of_biquads 

DO sections UNTIL CE; {Loop once for each biquad} 
SE=DM ( II , M2 ) ; {Scale factor for biquad} 

MXO =DM (10, MO ) , MY0=PM ( 14 , M4 ) ; 

MR=MX0*MY0 (SS) , MX1=DM (10 , MO ) , MY0=PM ( 14 , M4 ) ; 
MR=MR+MX1*MY0 (SS) , MY0=PM(I4,M4); 

MR=MR+SR1*MY0 (SS) , MX0=DM ( 10 , M0 ) , MY0=PM ( 14 , M4 ) ; 
MR=MR+MX0*MY0 (SS) , MX0=DM ( 10 , Ml ) , MY0=PM ( 14 , M4 ) ; 
DM ( I 0 , M0 ) =MX1 , MR=MR+MX0 *MY0 ( RND ) ; 
sections: DM (10 ,M0) =SR1, SR=ASHIFT MRl (HI); 

DM(I0,M0) =MX0; 

DM (10, M3) =SR1; 

RTS; 

.ENDMOD; 

Listing 14.2 Cascaded Biquad HR Filter 
14.5 SINE APPROXIMATION 

The following formula approximates the sine of the input variable x: 

sin(x) = 3.140625x + 0.02026367x 2 - 5.325196x 3 + 0.5446778x 4 + 1.800293x 5 

The approximation is accurate for any value of x from 0° to 90° (the first 
quadrant). However, because sin(-x) = -sin(x) and sin(x) = sin(180° - x), 
you can infer the sine of any angle from the sine of an angle in the first 
quadrant. 


14-7 




The routine that implements this sine approximation, accurate to within 
two LSBs, is shown in Listing 14.3. This routine accepts input values in 
1.15 format. The coefficients, which are initialized in data memory in 4.12 
format, have been adjusted to reflect an input value scaled to the 
maximum range allowed by this format. On this scale, 180° equals the 
maximum positive value, 0x7FFF, and -180° equals the maximum 
negative value, 0x8000. 

The routine shown in Listing 14.3 first adjusts the input angle to its 
equivalent in the first quadrant. The sine of the modified angle is 
calculated by multiplying increasing powers of the angle by the 
appropriate coefficients. The result is adjusted if necessary to compensate 
for the modifications made to the original input value. 


.MODULE Sin_Approximation; 
{ 

Sine Approximation 
Y = Sin(x) 


Calling Parameters 

AX0 = x in scaled 1.15 format 
M3 = 1 
L3 = 0 


Return Values 

AR = y in 1.15 format 

Altered Registers 

AY0 , AF , AR , MYl , MX1 , MF , MR , SR, 13 

Computation Time 
25 cycles 

} 


14-8 



.VAR/ DM 


sin_coef f [5] ; 


. INIT sin_coef f : 0x3240, 0x0053, OxAACC, 0x08B7, OxlCCE; 

.ENTRY sin; 


approx : 


. ENDMOD ; 


I3= A sin_coef f ; {Pointer to coeff. buffer} 

AY0=0x4000 ; 

AR=AX0 , AF=AX0 AND AY0 ; {Check 2nd or 4th quad.} 

IF NE AR=-AX0; {If yes, negate input} 

AY0=0x7FFF; 

AR=AR AND AY0; {Remove sign bit} 

MY1=AR; 

MF=AR*MYl (RND) , MXl=DM ( 13 , M3 ) ; {MF = x 2 } 

MR=MXl*MYl (SS), MXl=DM ( 13 , M3 ) ; {MR = C-jX} 

CNTR=3 ; 

DO approx UNTIL CE; 

MR=MR+MXl *MF (SS) ; 

MF=AR*MF (RND), MXl=DM ( 13 , M3 ) ; 

MR=MR+MX1 *MF (SS) ; 

SR=ASHIFT MR1 BY 3 (HI); 

SR=SR OR LSHIFT MR0 BY 3 (LO) ; {Convert to 1.15 format} 
AR=PASS SRI; 

IF LT AR=PASS AY0 ; {Saturate if needed} 

AF=PASS AX0; 

IF LT AR=-AR; {Negate output if needed} 

RTS; 


Listing 14.3 Sine Approximation 


14.6 SINGLE-PRECISION MATRIX MULTIPLY 

The routine presented in this section multiplies two input matrices: X, an 
RxS (R rows, S columns) matrix stored in data memory and Y, an SxT 
(S rows, T columns) matrix stored in program memory. The output Z, an 
RxT (R rows, T columns) matrix, is written to data memory. 

The routine is shown in Listing 14.4. It requires a number of registers to be 
initialized, as listed in the "Calling Parameters" section of the initial 
comment. SE must contain the value necessary to shift the result of each 
multiplication into the desired format. For example, SE would be set to 
zero to obtain a matrix of 1 .31 values from the multiplication of two 
matrices of 1.15 values. 


14-9 



. MODULE 


matmul ; 


{ 


Single-Precision Matrix Multiplication 
S 

Z(i,j) = X [X{i,k) X Y(k,j)] i=0 to R; j=0 to T 

k=0 

X is an RxS matrix 
Y is an SxT matrix 
Z is an RxT matrix 

Calling Parameters 

11 — > Z buffer in data memory 

12 — > X, stored by rows in data memory 

16 — > Y, stored by rows in program memory 
MO = 1 Ml = S 

M4 = 1 M5 = T 

L0,L4,L5 = 0 

SE = Appropriate scale value 
CNTR = R 

Return Values 

Z Buffer filled by rows 

Altered Registers 

10 , II , 12 , 14 , 15 , MR, MXO , MYO , SR 

Computation Time 

((S+8) XT+4) XR+2+2 cycles 


LI s 0 
L2 = 0 
L6 = 0 


14-10 



. ENTRY 


spmm; 


spmin: DO row_loop UNTIL CE; 

15=16; 

CNTR=M5 ; 

DO column_loop UNTIL CE; 

10 = 12 ; 

14=15; 

CNTR=M1 ; 

MR=0 , MXO =DM ( I 0 , MO ) , MY0 = PM ( 14 , M5 ) ; {Get 1st data) 
DO element_loop UNTIL CE; 

MR=MR+MX0 *MY0 (SS) , MX0=DM ( 10 , MO ) , 


{15 = start of Y} 


{Set 10 to current X row} 
{Set 14 to current Y col} 


element_loop 

MY0=PM(I4,M5 


column_loop : 


SR=ASHIFT MR1 (HI), MY0=DM ( 15 , M4 ) ; {Update 15} 
SR=SR OR LSHIFT MRO (LO) ; {Finish shift} 

DM ( II , MO ) =SRl ; {Save output} 


row_loop: MODIFY ( 12 , Ml) ; 

RTS; 

.ENDMOD; 


{Update 12 to next X row} 


Listing 14.4 Single-Precision Matrix Multiply 


14.7 RADIX-2 DECIMATION-IN-TIME FFT 

The FFT program includes three subroutines. The first subroutine 
scrambles the input data (places the data in bit-reversed address order), so 
that the FFT output will be in the normal, sequential order. The next 
subroutine computes the FFT and the third scales the output data to 
maintain the block floating-point data format. 

The program is contained in four modules. The main module declares and 
initializes data buffers and calls subroutines. The other three modules 
contain the FFT, bit reversal, and block floating-point scaling subroutines. 
The main module calls the FFT and bit reversal subroutines. The FFT 
module calls the data scaling subroutine. 

The FFT is performed in place; that is, the outputs are written to the same 
buffer that the inputs are read from. 

14.7.1 Main Module 

The dit_fft_main module is shown in Listing 14.5. N is the number of 
points in the FFT (in this example, N=1024) and N_div_2 is used for 
specifying the lengths of buffers. To change the number of points in the 
FFT, you change the value of these constants and the twiddle factors. 


14-11 




The data buffers twid_real and twid_imag in program memory hold the 
twiddle factor cosine and sine values. The inplacereal, inplaceimag, 
inputreal and inputimag buffers in data memory store real and imaginary 
data values. Sequentially ordered input data is stored in inputreal and 
inputimag. This data is scrambled and written to inplacereal and 
inplaceimag. A four-location buffer called padding is placed at the end of 
inplaceimag to allow data accesses to exceed the buffer length. This buffer 
assists in debugging but is not necessary in a real system. Variables (one- 
location buffers) named groups, bflys_per_group, node_space and 
blk_exponent are declared last. 

The real parts (cosine values) of the twiddle factors are stored in the buffer 
twid_real. This buffer is initialized from the file twid_real.dat. Likewise, 
twid_imag.dat values initialize the twid_imag buffer that stores the sine 
values of the twiddle factors. In an actual system, the hardware would be 
set up to initialize these memory locations. 

The variable called groups is initialized to N_div_2, and bflys_per_group 
and node_space are each initialized to 2 because there are two butterflies 
per group in the second stage of the FFT. The blk exponent variable is 
initialized to zero. This exponent value is updated when the output data is 
scaled. 

After the initializations are complete, two subroutines are called. The first 
subroutine places the input sequence in bit-reversed order. The second 
performs the FFT and calls the block floating-point scaling routine. 


. MODULE /ABS= 4 
. CONST 

. VAR/ PM/RAM/CIRC 
.VAR/ PM/RAM/CIRC 
. VAR/DM/ RAM/ ABS=0 
[4] ; 


dit_f ft_main; 

N=1024, N_div_2=512; {For 1024 points} 
twid_real [N_div_2]; 
twid_imag [N_div_2]; 

inplacereal [N] , inplaceimag [N] , padding 


VAR/DM/RAM/ABS=H#1000 

VAR/DM/RAM 

inputreal [N] , inputimag 
groups, bf lys_per_group, 
blk_exponent ; 

INIT 

twid_real : 

<twid_real . dat>; 

INIT 

twid_imag : 

<twid_imag. dat>; 

INIT 

inputreal : 

cinputreal . dat> ; 

INIT 

inputimag : 

<inputimag . dat> ; 

INIT 

inplaceimag: <inputimag. dat>; 

INIT 

groups : N_ 

div_2 ; 


[N] ; 

node_space, 


14-12 




INIT 

bflys_per_group: 2 

INIT 

node_space : 2 ; 

INIT 

blk_exponent ; 0 ; 

INIT 

padding : 0 , 0 , 0 , 0 ; 


{Zeros after inplaceimag} 


. GLOBAL 
. GLOBAL 
. GLOBAL 
. GLOBAL 


twid_real, twid_imag; 
inplacereal, inplaceimag; 
inputreal, inputimag; 

groups, bf lys_per_group, node_space, blk_exponent; 


.EXTERNAL scramble, fft_strt; 

CALL scramble; 

CALL fft_strt; 

TRAP; 

. ENDMOD ; 

Listing 14.5 Main Module, Radix-2 DIT FFT 


{subroutine calls} 
{halt program} 


14.7.2 DIT FFT Subroutine 

The radix-2 DIT FFT routine is shown in Listing 14.6. The constants N and 
log2N are the number of points and the number of stages in the FFT, 
respectively. To change the number of points in the FFT, you modify these 
constants. 

The first and last stages of the FFT are performed outside of the loop that 
executes all the other stages. Treating the first and last stages individually 
allows them to be executed faster. In the first stage, there is only one 
butterfly per group, so the butterfly loop is unnecessary, and the twiddle 
factors are all either 1 or 0, so no multiplications are necessary. In the last 
stage, there is only one group, so the group loop is unnecessary, as are the 
setup operations for the next stage. 


14-13 



{1024 point DIT radix 2 FFT} 

{Block Floating Point Scaling} 

.MODULE fft; 

{ Calling Parameters 

inplacereal=real input data in scrambled order 

inplaceimag=all zeroes (real input assumed) 

twid_real= twiddle factor cosine values 

twid_imag=twiddle factor sine values 

groups =N/ 2 

bf lys_per_group=l 

node_space=l 

Return Values 

inplacereal=real FFT results, sequential order 
inplaceimag=imag . FFT results, sequential order 

Altered Registers 

10 , II , 12 , 13 , 14 , 15 , L0 , LI , L2 , L3 , L4 , L5 

MO , Ml , M2 , M3 , M4 , M5 

AXO , AX1 , AYO , AY1 , AR, AF 

MXO , MX1 , MYO , MYl , MR, SB,SE, SR, SI 

Altered Memory 

inplacereal, inplaceimag, groups, node_space, 
bflys_per_group, blk_exponent 

} 

.CONST log2N=10, N=1024, nover2=512, nover4=256; 

.EXTERNAL twid_real, twid_imag; 

.EXTERNAL inplacereal, inplaceimag; 

.EXTERNAL groups, bf lys_per_group, node_space; 

. EXTERNAL bfp_adj ; 

.ENTRY f f t_strt ; 

fft_strt: CNTR=log2N - 2; {Initialize stage counter} 

MO = 0 ; 

Ml = 1 ; 

L1 = 0 ; 

L2=0; 

L3=0; 

L4=%twid_real ; 

L5=%twid_imag; 

L6=0; 

SB=-2 ; 


14-14 



{ 


STAGE 1 


} 


IO= A inplacereal ; 
Il= A inplacereal + 1; 
l2= A inplaceimag; 
l3= A inplaceimag + 1; 
M2 =2 ; 


CNTR=nover2 ; 
AXO=DM ( 10 , MO ) ; 
AYO=DM ( II , MO ) ; 
AY1=DM ( 13 , MO ) ; 


DO group_lp UNTIL CE; 

AR=AXO+AYO, AXl=DM(I2,M0) ; 
SB=EXPADJ AR, DM ( I 0 , M2 ) = AR ; 
AR=AX0-AY0 ; 

SB = EXPAD J AR; 

DM (II, M2) =AR, AR=AX1+AY1 ; 
SB=EXPADJ AR, DM ( 12 , M2 ) =AR; 
AR=AX1-AY1, AX0=DM ( 10 , MO ) ; 
SB = EXPAD J AR, DM(I3,M2)=AR; 
AY0=DM(I1,M0) ; 
gr oup_lp : AY1 =DM ( I 3 , MO ) ; 

CALL bfp__adj ; 


{ STAGES 2 TO N-l 

DO stage_loop UNTIL CE; 
IO= A inplacereal; 
l2= A inplaceimag; 

SI=DM( groups) ; 

SR=ASHIFT SI BY -1 (LO) ; 
DM ( groups ) =SR0 ; 

CNTR=SR0 ; 

M4=SR0; 

M2=DM(node_space) ; 
11 = 10 ; 

MODIFY (II, M2) ; 

13 = 12 ; 

MODIFY (I 3, M2) ; 


} 

{Compute all stages in FFT) 
{10 ->x0 in 1st grp of stage} 

{12 ->y0 in 1st grp of stage} 

{groups / 2} 

{groups=groups / 2} 
{CNTR=group counter} 
{M4=twiddle factor modifier} 
{M2=node space modifier} 

{II ->y0 of 1st grp in stage} 

{13 ->yl of 1st grp in stage} 


14-15 



bfly_loop: 


group_loop: 


stage_loop: 



DO group_loop UNTIL CE; 
I4= A twid_real ; 

I5= A twid_imag; 

CNTR=DM (bf lys_per_group) ; 

MY0=PM ( 14 , M4 ) , MX0=DM ( II , MO ) ; 
MY1=PM < 15 , M4 ) , MX1=DM ( 13 , MO ) ; 

DO bf ly_loop UNTIL CE; 

MR=MX0*MY1 (SS) , AXO=DM (10 , MO ) ; 


{14 -> C of WO} 

{15 -> (-S) of WO} 
{CNTR=bfly count} 
{MY0=C,MX0=xl } 
{MYl=-S , MXl=yl } 


{MR=xl ( -S ) , AXO=xO } 
MR=MR+MX1*MY0 (RND) , AX1=DM ( 12 , MO ) ; 

{MR= (yl (C) +xl (-S) ) , AXl=yO} 
AY1=MR1,MR=MX0*MY0 (SS) ; 

{AYl=yl (C) +xl (-S) , MR=xl (C) } 
MR=MR-MX1*MY1 (RND) ; {MR=xl (C) -yl ( -S) } 

AY0=MR1 , AR=AXl-AYl ; 


{AYO=xl (C) -yl (-S) , AR=yO- [yl (C) +xl (-S) ] } 
SB=EXPADJ AR , DM ( I 3 , Ml ) =AR ; 

{Check for bit growth, yl=yO- [yl (C) +xl (-S) ] } 
AR=AX0-AY0 , MXl=DM ( 13 , MO ) , MY1=PM ( 15 , M4 ) ; 

{AR=xO- [xl (C) -yl (-S) ] , MXl=next yl,MYl=next (-S)} 
SB=EXPADJ AR , DM ( I 1 , Ml ) =AR ; 

{Check for bit growth, xl=xO- [xl (C) -yl (-S) ] } 
AR=AX0+AY0 , MX0=DM ( II , MO ) ,MY0=PM(I4,M4) ; 

{AR=xO+ [xl (C) -yl (-S) ] , MX0=next xl,MY0=next C} 
SB=EXPADJ AR, DM (10, Ml) =AR; 

{Check for bit growth, x0=x0+ [xl (C) -yl (-S) ] } 
AR=AX1+AY1 ; {AR=yO+ [yl (C) +xl (-S) ] } 

SB=EXPAD J AR , DM ( I 2 , Ml ) =AR ; 

{Check for bit growth, y0=y0+ [yl (C) +xl (-S) ] } 
MODIFY ( 10 , M2 ) ; {10 ->lst xO in next group} 

MODIFY (II, M2 ) ; {II ->lst xl in next group} 

MODIFY (12 , M2 ) ; {12 ->lst yO in next group} 

MODIFY ( 13 , M2 ) ; {13 ->lst yl in next group} 


CALL bfp_adj ; {Compensate for bit growth} 

SI=DM(bflys_per_group) ; 

SR=ASHIFT SI BY l(LO); 

DM(node_space) =SR0; {node_space=node_space / 2} 

DM(bflys_per_group) =SR0 ; 

{bf lys_per_group=bf lys_per_group / 2} 


14-16 




{ LAST STAGE } 

lO= A inplacereal ; 

Il= A inplacereal+nover2 ; 

I2= A inplaceimag; 
l3= A inplaceimag+nover2 ; 

CNTR=nover2 ; 

M2=DM (node_space) ; 

M4=l ; 

I4= A twid_real ; 

1 5 = A twid_imag ; 

MYO=PM ( 14 , M4 ) , MXO=DM ( 11 , MO ) ; {MYO=C , MXO=xl } 

MY1=PM ( 15 , M4 ) ,MX1=DM(I3,M0) ; {MYl=-S , MXl=yl } 

DO bf ly_lp UNTIL CE; 

MR=MXO *MY1 ( SS ) , AX0=DM ( 10 , MO ) ; {MR=xl(-S) ,AXO=xO} 

MR=MR+MX1*MY0 (RND) , AXl=DM ( 12 , MO ) ; 

{MR= (yl (C) +xl (-S) ) , AXl=yO } 
AY1=MR1,MR=MX0*MY0 (SS) ; {AYl=yl (C) +xl (-S) ,MR=xl (C) } 
MR=MR-MXl*MYl (RND) ; {MR=xl (C) -yl ( -S) } 

AYO =MR1 , AR=AXl -AY1 ; 

{AYO^xl (C) -yl (-S) , AR=y 0 - (yl (C) +xl (-S) ] } 
SB=EXPADJ AR , DM (13, Ml ) =AR ; 

{Check for bit growth, yl=yO- [yl (C) +xl (-S) ] } 
AR=AX0-AY0 , MX1=DM ( 13 , MO ) , MY1=PM ( 15 , M4 ) ; 

{AR=xO- (xl(C) -yl(-S) ] , MXl=next yl,MYl=next (-S)} 
SB=EXPADJ AR, DM (II , Ml ) =AR; 

{Check for bit growth, xl=xO- [xl (C) -yl ( -S) ] } 
AR=AX0+AY0,MX0=DM(I1,M0) , MY0=PM ( 14 , M4 ) ; 

{AR=xO+ [xl (C) -yl ( -S) ] , MX0=next xl,MYO=next C} 
SB^EXPAD J AR , DM ( I 0 , Ml ) =AR ; 

{Check for bit growth, x0=x0+ [xl (C) -yl ( -S) ] } 
AR=AX1+AY1; {AR=yO+ [yl (C) +xl (-S) ] } 

bfly_lp: SB= EXPAD J AR, DM ( 12 , Ml ) =AR; {Check for bit growth} 

CALL bfp_adj ; 

RTS; 

.ENDMOD; 

Listing 14.6 Radix-2 DIT FFT Routine, Conditional Block Floating-Point 


14-17 




14.7.3 Bit-Reverse Subroutine 

The bit-reversal routine, called scramble, puts the input data in bit- 
reversed order so that the results will be in sequential order. This routine 
uses the bit-reverse capability of the ADSP-2100 family processors. 


.MODULE dit_scramble; 


{ Calling Parameters 

Sequentially ordered input data in inputreal 


Return Values 

Scrambled input data in inplacereal 


Altered Registers 

10, I4,M0,M4, AY1 


Altered Memory 

inplacereal 

} 

.CONST N=1024 , mod_value=H#0010 ; {Initialize constants} 

.EXTERNAL inputreal, inplacereal; 

.ENTRY scramble; 


scramble : 


brev: 


.ENDMOD; 


I4= A inputreal; { 14— sequentially ordered data} 

lO= A inplacereal ; {10— >scrambled data} 

M4=l; 

M0=mod_value; {M0=modifier for reversing N bits} 

L4 = 0 ; 

L0 = 0; 

CNTR = N; 

ENA BIT_REV; {Enable bit-reversed outputs on DAG1} 

DO brev UNTIL CE; 

AY1=DM ( 14 , M4 ) ; {Read sequentially ordered data} 
DM ( I 0 , MO ) = AY 1 ; 

{Write data in bit-reversed location} 
DIS BIT_REV; {Disable bit-reverse} 

RTS; {Return to calling program} 


Listing 14.7 Bit-Reverse Routine (Scramble) 


14-18 




1 4.7.4 Block Floating-Point Scaling Subroutine 

The bfp_adj routine checks the FFT output data for bit growth and scales 
the entire set of data if necessary. This check prevents data overflow for 
each stage in the FFT. The routine, shown in Listing 14.8, uses the 
exponent detection capability of the shifter. 

.MODULE dit_radix_2_bfp_adjust; 

{ Calling Parameters 

Radix-2 DIT FFT stage results in inplacereal and inplaceimag 
Return Parameters 

inplacereal and inplaceimag adjusted for bit growth 

Altered Registers 

10, II, AXO, AYO, AR,MX0, MYO, MR, CNTR 

Altered Memory 

inplacereal, inplaceimag, blk_exponent 

} 

.CONST Ntimes2 = 2048; 

.EXTERNAL inplacereal, blk_exponent ; {Begin declaration section} 
. ENTRY bf p_ad j ; 

bfp_adj ; AYO = CNTR; {Check for last stage} 

AR= AY 0-1 

IF EQ RTS; {If last stage, return} 

AY0=-2 ; 

AXO = SB ; 

AR=AX0 -AYO ; {Check for SB=-2} 

IF EQ RTS; {IF SB=-2, no bit growth, return} 

lO= A inplacereal ; {I0=read pointer} 

Il= A inplacereal ; {Il=write pointer} 

AY0=-1; 

MY0=H#4000; {Set MYO to shift 1 bit right} 

AR=AX0-AY0 , MX0=DM ( 10 , Ml ) ; 

{Check if SB=-1; Get 1st sample} 


14-19 



strt_shif t : 


shif t_loop : 


.ENDMOD; 


IF EQ JUMP strt_shif t ; 

{If SB=-1 , shift block data 1 bit} 
AX0=-2; {Set AXO for block exponent update} 

MY0=H#2000; {Set MYO to shift 2 bits right} 

CNTR=Ntimes2 - 1; {initialize loop counter} 

DO shift_loop UNTIL CE; {Shift block of data} 

MR=MX0*MY0 <RND) , MX0=DM ( 10 , Ml ) ; 

{MR=shifted data,MX0=next value} 
DM ( I 1 , Ml ) =MR1 ; {Unshifted data=shifted data} 

MR=MX0*MY0 (RND) ; {Shift last data word} 

AYO=DM(blk_exponent) ; {Update block exponent and} 

DM { II , Ml ) =MR1 , AR=AY0-AX0 ; {store last shifted sample} 
DM (blk_exponent ) =AR ; 

RTS; 


Listing 14.8 Radix-2 Block Floating-Point Scaling Routine 



Instruction Set Reference B 15 


1 5.1 QUICK LIST OF INSTRUCTIONS 

This chapter is a complete reference for the instruction set of the 
ADSP-2100 family. The instruction set is organized by instruction group 
and, within each group, by individual instruction. The list below shows all 
of the instructions and the reference page for each. 


ALU 

Add / Add with Carry (p. 15-21) 

Subtract X-Y / Subtract X-Y with Borrow (p. 15-23) 
Subtract Y-X / Subtract Y-X with Borrow (p. 15-25) 
AND, OR, XOR (p. 15-27) 

Test Bit, Set Bit, Clear Bit, Toggle Bit (p. 15-29) 

Pass / Clear (p. 15-31) 

Negate (p. 15-33) 

NOT (p. 15-34) 

Absolute Value (p. 15-35) 

Increment (p. 15-36) 

Decrement (p. 15-37) 

Divide (p. 15-38) 

Generate ALU Status (p. 15-40) 

MAC 

Multiply (p. 15-41) 

Multiply / Accumulate (p. 15-43) 

Multiply / Subtract (p. 15-45) 

Clear (p. 15-47) 

Transfer MR (p. 15-48) 

Conditional MR Saturation (p. 15-49) 

SHIFTER 

Arithmetic Shift (p. 15-50) 

Logical Shift (p. 15-52) 

Normalize (p. 15-54) 

Derive Exponent (p. 15-56) 

Block Exponent Adjust (p. 15-58) 

Arithmetic Shift Immediate (p. 15-60) 

Logical Shift Immediate (p. 15-62) 


MOVE 

Register Move (p. 15-63) 

Load Register Immediate (p. 15-65) 

Data Memory Read (Direct Address) (p. 15-67) 

Data Memory Read (Indirect Address) (p. 15-68) 

Program Memory Read (Indirect Address) (p. 15-69) 

Data Memory Write (Direct Address) (p. 15-70) 

Data Memory Write (Indirect Address) (p. 15-71) 

Program Memory Write (Indirect Address) (p. 15-73) 

I/O Space Read/Write (p. 15-74) 

PROGRAM FLOW 
JUMP (p. 15-75) 

CALL (p. 15-76) 

JUMP or CALL on Flag In Pin (p. 15-77) 

Modify Flag Out Pin (p. 15-78) 

Return from Subroutine (p. 15-79) 

Return from Interrupt (p. 15-80) 

Do Until (p. 15-81) 

IDLE (p. 15-83) 

MISC 

Stack Control (p. 15-84) 

Mode Control (p. 15-87) 

Modify Address Register (p. 15-89) 

NOP (p. 15-90) 

Interrupt Enable & Disable (p. 15-91) 

MULTIFUNCTION 

ALU/MAC/SHIFT with Memory Read (p. 15-92) 
ALU/MAC/SHIFT with Data Register Move (p. 15-96) 
ALU/MAC/SHIFT with Memory Write (p. 15-99) 

Data & Program Memory Read (p. 15-103) 

ALU/MAC with Data & Program Memory Read (p. 15-104) 


15-1 





15.2 OVERVIEW 

This chapter provides an overview and detailed reference for the 
instruction set of the ADSP-2100 family of DSP microprocessors. 

For information regarding the ADSP-2100 Family Development Software, 
refer to the ADSP-2100 Family Assembler Tools & Simulator Manual, 
ADSP-2100 Family C Tools Manual, and ADSP-2100 Family C Runtime 
Library Manual. These manuals provide a complete guide to the 
development software. The handbooks Digital Signal Processing 
Applications Using The ADSP-2100 Family, Volume 1 and Volume 2 present 
DSP applications programs with source code and discussion. 

The instruction set is tailored to the computation-intensive algorithms 
common in DSP applications. For example, sustained single-cycle 
multiplication/accumulation operations are possible. The instruction set 
provides full control of the processors' three computational units: the 
ALU, MAC and Shifter. Arithmetic instructions can process single- 
precision 16-bit operands directly; provisions for multiprecision 
operations are available. 

The high-level syntax of ADSP-2100 family source code is both readable 
and efficient. Unlike many assembly languages, the ADSP-2100 family 
instruction set uses an algebraic notation for arithmetic operations and for 
data moves, resulting in highly readable source code. There is no 
performance penalty for this; each program statement assembles into one 
24-bit instruction which executes in a single cycle. There are no multicycle 
instructions in the instruction set. (If memory access times require, or 
contention for off-chip memory occurs, overhead cycles will be required, 
but all instructions can otherwise execute in a single cycle.) 

In addition to JUMP and CALL, the instruction set's control instructions 
support conditional execution of most calculations and a DO UNTIL 
looping instruction. Return from interrupt (RTI) and return from 
subroutine (RTS) are also provided. 

The IDLE instruction is provided for idling the processor until an 
interrupt occurs. IDLE puts the processor into a low-power state while 
waiting for interrupts. 


15-2 


Two addressing modes are supported for memory fetches. Direct 
addressing uses immediate address values; indirect addressing uses the I 
registers of the two data address generators (DAGs). 



Instruction Set Reference 


The 24-bit instruction word allows a high degree of parallelism in 
performing operations. The instruction set allows for single-cycle 
execution of any of the following combinations: 

• any ALU, MAC or Shifter operation (conditional or non-conditional) 

• any register-to-register move 

• any data memory read or write 

• a computation with any data register to data register move 

• a computation with any memory read or write 

• a computation with a read from two memories. 

The instruction set allows maximum flexibility. It provides moves from 
any register to any other register, and from most registers to/ from 
memory. In addition, almost any ALU, MAC or Shifter operation may be 
combined with any register-to-register move or with a register move to or 
from either internal or external memory. 


15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS 

The ADSP-2100 family instruction set is grouped into the following 
categories: 

• Computational: ALU, MAC, Shifter 

• Move 

• Program Flow 

• Multifunction 

• Miscellaneous 

Because the multifunction instructions best illustrate the power of the 
processors' architecture, in the next section we begin with a discussion of 
this group of instructions. 

Throughout this chapter you will find tables summarizing the syntax of 
the instruction groups. The following notation conventions are used in 
these tables and in the reference page for each instruction. 

Square Brackets [ ] Anything within square brackets is an optional 

part of the instruction statement. 

Parallel Lines I I Lists of operands are enclosed by vertical parallel 

bars. One of the operands listed must be chosen. 
If the parallel bars are within square brackets, 
then the operand is optional for that instruction. 


15-3 




CAPITAL LETTERS Capital letters denote a literal in the instruction. 

Literals are the instruction name (e.g. ADD), 
register names, or operand selections. Literals 
must be typed exactly as shown. 

operands Some instruction operands are shown in 

lowercase letters. These operands may take 
different values in assembly code. For example, 
the operand yop may be one of several registers: 
AYO, AY1, or AF. 

<exp> Denotes exponent (shift value) in Shift Immediate 

instructions; must be an 8-bit signed integer 
constant. 

<data> Denotes an immediate data value. Can also be a 

symbol (address label or variable/buffer name) 
dereferenced by the '%' or //v operators. 

<addr> Denotes an immediate address value to be 

encoded in the instruction. The <addr> may be 
either an immediate value (a constant) or a 
program label. 

<reg> Refers to any accessible register; see Table 15.7. 

<dreg> Refers to any data register; see Table 15.7. 

Immediate values, <exp>, <data>, or <addr>, may be a constant in 

decimal, hexadecimal, octal or binary format. Default is to decimal. 


15.4 MULTIFUNCTION INSTRUCTIONS 

Multifunction operations take advantage of the inherent parallelism of the 
ADSP-2100 family architecture by providing combinations of data moves, 
memory reads/ memory writes, and computation, all in a single cycle. 

15.4.1 ALU/MAC With Data & Program Memory Read 

Perhaps the single most common operation in DSP algorithms is the sum 
of products, performed as follows: 


15-4 


Fetch two operands (such as a coefficient and data point) 

Multiply the operands and sum the result with previous products 



Instruction Set Reference 


The ADSP-2100 family processors can execute both data fetches and the 
multiplication/accumulation in a single-cycle. Typically, a loop of 
multiply /accumulates can be expressed in ADSP-21xx source code in just 
two program lines. Since the on-chip program memory of the ADSP-21xx 
processors is fast enough to provide an operand and the next instruction 
in a single cycle, loops of this type can execute with sustained single-cycle 
throughput. An example of such an instruction is: 

MR=MR+MX0*MY0 (SS) , MX0=DM ( 10 , MO ) , MY0=PM ( 14 , M5 ) ; 

The first clause of this instruction (up to the first comma) says that MR, the 
MAC result register, gets the sum of its previous value plus the product of 
the (current) X and Y input registers of the MAC (MXO and MYO) both 
treated as signed (SS). 

In the second and third clauses of this multifunction instruction two new 
operands are fetched. One is fetched from the data memory (DM) pointed 
to by index register zero (10, post modified by the value in MO) and the 
other is fetched from the program memory location (PM) pointed to by 14 
(post-modified by M5 in this instance). Note that indirect memory 
addressing uses a syntax similar to array indexing, with DAG registers 
providing the index values. Any I register may be paired with any M 
register within the same DAG. 

As discussed in Chapter 2, "Computational Units," registers are read at 
the beginning of the cycle and written at the end of the cycle. The 
operands present in the MXO and MYO registers at the beginning of the 
instruction cycle are multiplied and added to the MAC result register, MR. 
The new operands fetched at the end of this same instruction overwrite 
the old operands after the multiplication has taken place and are available 
for computation on the following cycle. You may, of course, load any data 
registers in conjunction with the computation, not just MAC registers with 
a MAC operation as in our example. 

The computational part of this multifunction instruction may be any 
unconditional ALU instruction except division or any MAC instruction 
except saturation. Certain other restrictions apply: the next X operand 
must be loaded into MXO from data memory and the new Y operand must 
be loaded into MYO from program memory (internal and external memory 
are identical at the level of the instruction set). The result of the 
computation must go to the result register (MR or AR) not to the feedback 
register (MF or AF). 



15.4.2 Data & Program Memory Read 

This variation of a multifunction instruction is a special case of the 
multifunction instruction described above in which the computation is 
omitted. It executes only the dual operand fetch, as shown below: 

AX0=DM ( 12 , MO ) , AY0=PM { 14 , M6 ) ; 

In this example we have used the ALU input registers as the destination. 
As with the previous multifunction instruction, X operands must come 
from data memory and Y operands from program memory (internal or 
external memory in either case, for the processors with on-chip memory). 

15.4.3 Computation With Memory Read 

If a single memory read is performed instead of the dual memory read of 
the previous two multifunction instructions, a wider range of 
computations can be executed. The legal computations include all ALU 
operations except division, all MAC operations and all Shifter operations 
except SHIFT IMMEDIATE. Computation must be unconditional. An 
example of this kind of multifunction instruction is: 

AR=AX0+AY0, AXO =DM ( 1 0 , M3 ) ; 

Here an addition is performed in the ALU while a single operand is 
fetched from data memory. The restrictions are similar to those for 
previous multifunction instructions. The value of AXO, used as a source 
for the computation, is the value at the beginning of the cycle. The data 
read operation loads a new value into AXO by the end of the cycle. For this 
same reason, the destination register (AR in the example above) cannot be 
the destination for the memory read. 

1 5.4.4 Computation With Memory Write 

The computation with memory write instruction is similar in structure to 
the computation with memory read: the order of the clauses in the 
instruction line, however, is reversed. First the memory write is 
performed, then the computation, as shown below: 

DM (10, MO) =AR, AR=AX0+AY0; 

Again the value of the source register for the memory write (AR in this 
example) is the value at the beginning of the instruction. The computation 
loads a new value into the same register; this is the value in AR at the end 
of this instruction. Reversing the order of the clauses of the instruction is 
illegal and causes the assembler to generate a warning; it would imply 



Instruction Set Reference 


that the result of the computation is written to memory when, in fact, the 
previous value of the register is what is written. There is no requirement 
that the same register be used in this way although this will usually be the 
case in order to pipeline operands to the computation. 

The restrictions on computation operations are identical to those given 
above. All ALU operations except division, all MAC operations, and all 
Shifter operations except SHIFT IMMEDIATE are legal. Computations 
must be unconditional. 

15.4.5 Computation With Data Register Move 

This final type of multifunction instruction performs a data register to 
data register move in parallel with a computation. Most of the restrictions 
applying to the previous two instructions also apply to this instruction. 

AR=AX0+AY0, AX0=MR2; 

Here an ALU addition operation occurs while a new value is loaded into 
AXO from MR2. As before, the value of AXO at the beginning of the 
instruction is the value used in the computation. The move may be from 
or to all ALU, MAC and Shifter input and output registers except the 
feedback registers (AF and MF) and SB. 

In the example, the data register move loads the AXO register with the 
new value at the end of the cycle. All ALU operations except division, all 
MAC operations and all Shifter operations except SHIFT IMMEDIATE are 
legal. Computation must be unconditional. 

A complete list of data registers is given in Table 15.7. A complete list of 
the permissible xops and pops for computational operations is given in the 
reference page for each instruction. Table 15.1 shows the legal 
combinations for multifunction instructions: you may combine operations 
on the same row with each other. 


Unconditional Computations 


None or any ALU (except Division) or MAC 


Any ALU except Division 
Any MAC 

Any Shift except Immediate 



Data Move Data Move 

(DM-DAG1) (PM=DAG2) 


DM read 
DM read 
DM write 


PM read 

PM read 
PM write 


Register-To-Register 


Table 15.1 Summary Of Valid Combinations For Multifunction Instructions 



Multifunction Instructions 


<ALU>* + 

/ 

AXO 

= DM ( 

10 


MO 

), 

AYO 

= PM ( 

14 

/ 

<MAC>* + 


AX1 


11 


Ml 


AY1 


15 




MXO 


12 


M2 


MYO 


16 

/ 



MX1 


13 

, 

M3 


MY1 


17 

, 


M4 
M5 
M6 
M 7 


AXO 

= DM ( 

10 

, 

MO 

), 

AYO 

= PM ( 

14 

/ 

M4 

AX1 


11 


Ml 


AY1 


15 

/ 

M5 

MXO 


12 


M2 


MYO 


16 

f 

M6 

MX1 


13 

, 

M3 


MY1 


17 

, 

M7 


<ALU> 

<MAC>* 

<SHIFT>* 


DM ( 


PM ( 


<ALU> 

<MAC>* 

<SHIFT>* 


/ dreg 


DM ( 


PM ( 


MO 

Ml 

M2 

M3 

M4 

M5 

M6 

M7 

M4 

M5 

M6 

M7 


10 


MO 

) 

= dreg, 

<ALU>* 

11 

, 

Ml 


<MAC>* 

12 

/ 

M2 



<SHIFT> 

13 


M3 




14 


M4 




15 

/ 

M5 




16 


M6 




17 

/ 

M7 




14 


M4 

) 



15 

/ 

M5 




16 

/ 

M6 




17 

' 

M7 




1 

/dreg 

= 

dreg; 



15-8 


Table 15.2 Multifunction Instructions 

<ALU> Any ALU instruction (except DTVS, DIVQ) 

<MAC> Any multiply/ accumulate instruction 

<SHIFT> Any shifter instruction (except Shift Immediate) 

* May not be conditional instruction 

+ AR, MR result registers must be used — not AF, MF feedback registers. 
(See Section 15.4.1, "ALU/MAC with Data & Program Memory Read.") 



1 5.5 ALU, MAC & SHIFTER INSTRUCTIONS 

This group of instructions performs computations. All of these 
instructions can be executed conditionally except the ALU division 
instructions and the Shifter SHIFT IMMEDIATE instructions. 

15.5.1 ALU Group 

Here is an example of one ALU instruction. Add /Add with Carry: 

IF AC AR=AX0 +AY 0 +C ; 

The (optional) conditional expression, IF AC, tests the ALU Carry bit 
(AC); if there is a carry from the previous instruction, this instruction 
executes, otherwise a NOP occurs and execution continues with the next 
instruction. The algebraic expression AR=AX0+AY0+C means that the 
ALU result register (AR) gets the value of the ALU X input and Y input 
registers plus the value of the carry-in bit. 

Table 15.3 gives a summary list of all ALU instructions. In this list, 
condition stands for all the possible conditions that can be tested and xop 
and yop stand for the registers that can be specified as input for the ALU. 
The conditional clause is optional and is enclosed in square brackets to 
show this. A complete list of the permissible xops and yops is given in the 
reference page for each instruction. A complete list of conditions is given 
in Table 15.9. 

ALU Instructions 

[IF condition] AR = xop + yop ; 

AF • +C 

+ yop + C 
+ constant 
+ constant + C 

[IF condition] AR = xop - yop ; 

AF - yop + C - 1 

+ C-1 

- constant 

- constant + C - 1 


[IF condition] 

AR 

yop 1 - xop i 


AF 

| - xop + C - 1 



- xop + C - 1 



- xop + constant 

- xop + constant + C - 1 


15-9 



[IF condition] 


AR 

AF 


xop 


AND 

OR 

XOR 


y°p 

constant 


[IF condition] 

AR 

= 

TSTBIT n OF xop 


AF 


SETBIT n OF xop 
CLRBIT n OF xop 
TGLBIT n OF xop 

[IF condition] 

AR 

= 

PASS 

xop 


AF 



yop 

constant 

[IF condition] 

AR 

= 

_ 

xop 


AF 



yop 

[IF condition] 

AR 

— 

NOT 

xop 


AF 



yop 

[IF condition] 

AR 

= 

ABS 

xop 


AF 



[IF condition] 

AR 

= 

yop 

+ 1 


AF 



[IF condition] 

AR 

1 = 

yop 

-1 


AF 




DIVS yop, xop ; 

DIVQ xop ; 

NONE = <ALU> ; 

Table 15.3 ALU Instructions 

15.5.2 MAC Group 

Here is an example of one of the MAC instructions. Multiply/ Accumulate: 
IF NOT MV MR=MR+MX0 *MY0 (UU) 

The conditional expression, IF NOT MV, tests the MAC overflow bit. If the 
condition is not true, a NOP is executed. The expression 
MR=MR+MX0*MY0 is the multiply/ accumulate operation: the multiplier 
result register (MR) gets the value of itself plus the product of the X and Y 
input registers selected. The modifier in parentheses (UU) treats the 
operands as unsigned. There can be only one such modifier selected from 
the available set. (SS) means both are signed, while (US) and (SU) mean 
that either the first or second operand is signed; (RND) means to round 
the (implicitly signed) result. 


15-10 



Table 15.4 gives a summary list of all MAC instructions. In this list, 
condition stands for all the possible conditions that can be tested and xop 
and yop stand for the registers that can be specified as input for the MAC. 
A complete list of the permissible xops and pops is given in the reference 
page for each instruction. 

MAC Instructions 


[IF condition] 

MR 

MF 

= xop * 

yop 

xop 

( 

SS 

SU 

US 

uu 

RND 

[IF condition] 

MR 

MF 

= MR + xop * 

yop 

xop 

( 

SS 

SU 

US 


uu 

RND 

[IF condition] MR = MR - xop * yop ( SS ); 

MF xop SU 

US 

UU 

RND 

[IF condition] | MR = 0; 

| MF 

[IF condition] MR = MR [( RND )]; 

MF 

IF MV SAT MR; 

Table 15.4 MAC Instructions 


15.5.3 Shifter Group 

Here is an example of one of the Shifter instructions. Normalize: 
IF NOT CE SR= SR OR NORM SI (HI); 


The conditional expression, IF NOT CE, tests the "not counter expired" 
condition. If the condition is false, a NOP is executed. The destination of 
all shifting operations is the Shifter Result register, SR. (The destination of 
exponent detection instructions is SE or SB, as shown below.) In this 
example, SI, the Shifter Input register, is the operand. The amount and 
direction of the shift is controlled by the signed value in the SE register in 
all shift operations except an immediate shift. Positive values cause left 
shifts; negative values cause right shifts. 


15-11 



The "SR OR" modifier (which is optional) logically ORs the result with the 
current contents of the SR register; this allows you to construct a 32-bit 
value in SR from two 16-bit pieces. "NORM" is the operator and "(HI)" is 
the modifier that determines whether the shift is relative to the HI or LO 
(16-bit) half of SR. If "SR OR" is omitted, the result is passed directly into 
SR. 

Table 15.5 gives a summary list of all Shifter instructions. In this list, 
condition stands for all the possible conditions that can be tested. 


Shifter Instructions 


[IF condition] 

SR 

= [SR OR] ASHIFT xop ( 

HI 

LO 

[IF condition] 

SR 

= [SR OR] LSHIFT xop ( 

HI 

LO 

[IF condition] 

SR 

= [SR OR] NORM xop ( 

HI 

LO 

[IF condition] 

SE 

= EXP xop ( 

HI 

LO 

HIX 

[IF condition] 

SB 

= EXPADJ xop; 


SR 


[SR OR] ASHIFT xop BY <exp> ( 

HI 

LO 

SR 


[SR OR] LSHIFT xop BY <exp> ( 

HI 

LO 


Table 15.5 Shifter Instructions 


15.6 MOVE: READ & WRITE 

MOVE instructions, shown in Table 15.6, move data to and from data 
registers and external memory. Registers are divided into two groups, 
referred to as reg which includes almost all registers and dreg, or data 
registers, which is a subset. Only the program counter (PC) and the ALU 
and MAC feedback registers (AF and MF) are not accessible. 

Table 15.7 shows which registers belong to these groups. Many of the 
system control registers are memory-mapped (for the processors with on- 
chip memory); these registers are read and written as memory locations 
instead of with register names. 



MOVE Instructions 


reg 

- 

reg; 




reg 

= 

DM (<address>) ; 


dreg 

= 

DM ( 

10 


MO 


DM ( 


11 

12 

13 

14 

15 

16 
17 


10 

f 

MO 

11 


Ml 

12 

/ 

M2 

13 

/ 

M3 



14 

/ 

M4 

15 


M5 

16 

/ 

M6 

17 

/ 

M7 


Ml 

M2 

M3 

M4 

M5 

M6 

M7 


dreg 

<data> 


DM (<address>) = 


reg; 


reg 

= 

<data> 



dreg 

= 

PM ( 

14 

, 

M4 





15 


M5 





16 


M6 





17 

/ 

M7 

PM ( 

14 

! / 

I M4 

| ) 

= 

dre; 


15 

16 
17 


M5 

M6 

M7 


Table 15.6 MOVE Instructions 


15-13 



Registers: reg 


Data Registers: dreg 


SB 

PX 

I0-I7,M0-M7,L0-L7 

CNTR 

ASTAT, MSTAT, SSTAT 
IMASK, ICNTL, IFC 
TXO, TX1, RXO, RX1 


AXO, AX1, AYO, AY1, AR 

MXO, MX1, MYO, MY1, MRO, MR1, MR2 

SI, SE, SRO, SRI 


Table 15.7 Processor Registers: reg & dreg 


1 5.7 PROGRAM FLOW CONTROL 

Program flow control on the ADSP-2100 family processors is simple but 
powerful. Here is an example of one instruction: 

IF EQ JUMP my_label; 

JUMP, of course, is a familiar construct from many other languages. Myjabel 
is any identifier you wish to use as a label for the destination jumped to. 
Instead of the label, an index register in DAG2 may be explicitly used. The 
default scope for any label is the source code module in which it is declared. 
The assembler directive .ENTRY makes a label visible as an entry point for 
routines outside the module. Conversely, the .EXTERNAL directive makes it 
possible to use a label declared in another module. 

If the counter condition (CE, NOT CE) is to be used, an assignment to CNTR 
must be executed to initialize the counter value. JUMP and CALL permit the 
additional conditionals "FLAG_IN" and "NOT FLAG_IN" to be used for 
branching on the state of the FI pin, but only with direct addressing, not with 
DAG2 as the address source. 

RTS (return from subroutine) and RTI (return from interrupt) provide for 
conditional return from CALL or interrupt vectors respectively. 

The IDLE instruction provides a way to wait for interrupts. IDLE causes the 
processor to wait in a low-power state until an interrupt occurs. When an 
interrupt is serviced, control returns to the instruction following the IDLE 
statement. IDLE uses less power than loops created with JUMP. 

Table 15.8 gives a summary of all program flow control instructions. The 
condition codes are described in Table 15.9. 


15-14 



Program Flow Control Instructions 

[IF condition] JUMP (14) ; 

(15) 

(16) 

(17) 

<address> 

IF FLAG JN JUMP <address> ; 

NOT FLAG _IN 

[IF condition] CALL (14) ; 

(15) 

(16) 

(17) 

<address> 

IF FLAGJN CALL <address> ; 

NOT FLAGJN 

[IF condition] RTS ; 

[IF condition] RTI ; 

DO <address> [UNTIL termination] ; 

IDLE [(n)]; 

Table 15.8 Program Flow Control Instructions 


Syntax 

Status Condition 

True If: 

EQ 

Equal Zero 

AZ = 1 

NE 

Not Equal Zero 

AZ = 0 

LT 

Less Than Zero 

AN .XOR. AV = 1 

GE 

Greater Than or Equal Zero 

AN .XOR. AV = 0 

LE 

Less Than or Equal Zero 

(AN .XOR. AV) .OR. AZ = 1 

GT 

Greater Than Zero 

(AN .XOR. AV) .OR. AZ = 0 

AC 

ALU Carry 

AC = 1 

NOT AC 

Not ALU Carry 

AC = 0 

AV 

ALU Overflow 

AV = 1 

NOTAV 

Not ALU Overflow 

AV = 0 

MV 

MAC Overflow 

MV = 1 

NOT MV 

Not MAC Overflow 

MV = 0 

NEG 

X Input Sign Negative 

AS = 1 

POS 

X Input Sign Positive 

AS = 0 

NOT CE 

Not Counter Expired 


FLAG IN* 

FI pin 

Last sample of FI pin = 1 

NOT FLAG IN* 

Not FI pin 

Last sample of FI pin = 0 


Table 15.9 IF Condition Codes 

* Only available on JUMP and CALL instructions 


15-15 



15.8 MISCELLANEOUS INSTRUCTIONS 

There are several miscellaneous instructions. NOP is a no operation 
instruction. The PUSH/ POP instructions allows you to explicitly control 
the status, counter, PC and loop stacks; interrupt servicing automatically 
pushes and pops some of these stacks. 

The Mode Control instruction enables and disables processor modes of 
operation: bit-reversal on DAG1, latching ALU overflow, saturating the 
ALU result register, choosing the primary or secondary register set, GO 
mode for continued operation during bus grant, multiplier shift mode for 
fractional or integer arithmetic, and timer enabling. 

A single ENA or DIS can be followed by any number of mode identifiers, 
separated by commas; ENA and DIS can also be repeated. All seven 
modes can be enabled, disabled, or changed in a single instruction. 

The MODIFY instruction modifies the address pointer in the I register 
selected with the value in the selected M register, without performing any 
actual memory access. As always, the I and M registers must be from the 
same DAG; any of 10-13 may be used only with one from M0-M3 and the 
same for 14-17 and M4-M7. If circular buffering is in use, modulus logic 
applies (See Chapter 4, "Data Transfer," for more information). 

The FO (Flag Out), FLO, FL1 and FL2 pins can each be set, cleared, or 
toggled. This instruction provides a control structure for multiprocessor 
communication. 


15-16 



Miscellaneous Instructions 


NOP; 

[ PUSH ] STS [, POP CNTR] [, POP PC] [, POP LOOP] ; 
POP 


ENA BIT_REV [ , ] 

DIS AV_LATCH 

AR_SAT 
SEC_REG 
GJMODE 
M_MODE 
TIMER 


MODIFY ( 10 , MO ); 

11 , Ml 

12 , M2 

13 , M3 

14 , M4 

15 , M5 

16 , M6 

17 , M7 


[IF condition] SET FLAG_OUT [,] ; 

RESET FLO 

TOGGLE FL1 

FL2 

ENA INTS; 

DIS 

Table 15.10 Miscellaneous Instructions 


15-17 




15.9 EXTRA CYCLE CONDITIONS 

All instructions execute in a single cycle except under certain conditions, 
as explained below. 

1 5.9.1 Multiple Off-Chip Memory Accesses 

The data and address busses of the ADSP-21xx processors are multiplexed 
off-chip. Because of this, the processors can perform only one off-chip 
access per instruction in a single cycle. If two off-chip accesses are 
required — the instruction fetch and one data fetch, for example, or data 
fetches from both program and data memory — then one overhead cycle 
occurs. In this case the program memory access occurs first, then the data 
memory access. If three off-chip accesses are required — the instruction 
fetch as well as data fetches from both program and data memory — then 
two overhead cycles occur. 

A multifunction instruction requires three items to be fetched from 
memory: the instruction itself and two data words. No extra cycle is 
needed to execute the instruction as long as only one of the fetches is from 
external memory. (Two fetches must be from on-chip memory, either PM 
or DM.) 

15.9.2 Wait States 

All family processors allow the programming of wait states for external 
memory chips. Up to seven extra wait state cycles may be added to the 
processor's access time for external memory. Extra cycles inserted due to 
wait states are in addition to any caused by multiple off-chip accesses (as 
described above). Wait state programming is described in the "Memory 
Interface" chapter. 

Wait states and multiple off-chip memory accesses are the two cases when 
an extra cycle is generated during instruction execution. The following 
case, SPORT autobuffering and DMA, causes the insertion of extra cycles 
between instructions. 

15.9.3 SPORT Autobuffering & DMA 

If serial port autobuffering or ADSP-2181 DMA is being used to transfer 
data words to or from internal memory, then one memory access is 
"stolen" for each transfer. The stolen memory access occurs only between 
complete instructions. If extra cycles are required to execute any 
instruction (for one of the two reasons above), the processor waits until it 
is completed before "stealing" the access cycle. 


15-18 



15.10 INSTRUCTION SET SYNTAX 

The following sections describe instruction set syntax and other notation 
conventions used in the reference page of each instruction. 

1 5.1 0.1 Punctuation & Multifunction Instructions 

All instructions terminate with a semicolon. A comma separates the 
clauses of a multifunction instruction but does not terminate it. For 
example, the statements below in Example A comprise one multifunction 
instruction (which can execute in a single cycle). Example B shows two 
separate instructions, requiring two instruction cycles. 

Example A: One multifunction instruction 

AXO = DM ( 10 , MO ), a comma is used in multifunction instructions 
AYO = PM (14, M4) ; 

Example B: Two separate instructions 

AXO = dm ( 10 , MO ) ; a semicolon terminates an instruction 
AYO = PM (14, M4); 

15.10.2 Syntax Notation Example 

Here is an example of one instruction, the ALU Add/ Add with Carry 
instruction: 


[ IF cond ] 

AR 

= xop + 

yop 


AF 


C 




yop + C 


The permissible conds, xops and yops are given in a list. The conditional IF 
clause is enclosed in square brackets, indicating that it is optional. 

The destination register for the add operation must be either AR or AF. 
These are listed within parallel bars, indicating that one of the two must 
be chosen. 

Similarly, the yop term may consist of a Y operand, the carry bit, or the 
sum of both. One of these three terms must be used. 




15.10.3 Status Register Notation 

The following notation is used in the discussion of the effect each 
instruction has on the processors' status registers: 

* An asterisk indicates a bit in the status word that is changed by 

the execution of the instruction. 

- A dash indicates that a bit is not affected by the instruction. 

0 or 1 Indicates that a bit is unconditionally cleared or set. 

For example, the status word AST AT is shown below: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 

- * - - - 0 

Here the MV bit is updated and the AV bit is cleared. 


15-20 



ADD / ADD with CARRY 


Syntax: [ if cond ] ar 

af 


xop 


+ yop 

+ c 

+ yop + C 
+ constant 
+ constant + C 


Permissible xops 

Permissible yops 

AXO MR2 

AYO 

AX1 MR1 

AY1 

AR MR0 

AF 

SRI 


SR0 



Permissible conds ( see Table 15.9) 


EQ 

LE 

AC 

NE 

NEG 

NOT AC 

GT 

POS 

MV 

GE 

AV 

NOT MV 

LT 

NOT AV 

NOT CE 


Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 

0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 

-2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097, -8193, -16385, -32768 

Example: if eq ar = axo + ayo + C; 

AR = AR + 512; 

Description: Test the optional condition and, if true, perform the specified 
addition. If false then perform a no-operation. Omitting the condition 
performs the addition unconditionally. The addition operation adds the first 
source operand to the second source operand along with the ALU carry bit, 
AC, (if designated by the "+C" notation), using binary addition. The result is 
stored in the destination register. The operands are contained in the data 
registers or constant specified in the instruction. 

The xop + constant operation is only available on the ADSP-217x, ADSP-218x, 
and ADSP-21msp58/59 processors and may not be used in multifunction 
instructions. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Set if an arithmetic overflow occurs. Cleared otherwise. 
AC Set if a carry is generated. Cleared otherwise. 


(instruction continues on next page) 



ADD / ADD with CARRY 


Instruction Format: 

Conditional ALU/MAC operation. Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

3 

s 

AMF 

Yop 

Xop 

E 

0 

0 

3 

COND 


AMF specifies the ALU or MAC operation, in this case: 


AMF = 10010 for xop + yop + C 
AMF = 10011 for xop + yop 

(Note that xop + C is a special case of xop + yop + C with yop=0.) 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 


(xop + constant) Conditional ALU/MAC operation. Instruction Type 9: 
(ADSP-217X, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 

5 4 

3 2 10 

0 

0 

1 

0 


E 

AMF 

YY 

Xop 

CC 

BO 

COND 


AMF specifies the ALU or MAC operation, in this case: 

AMF = 10010 for xop + constant + C 
AMF = 10011 for xop + constant 

Z: Destination register COND: condition 

Xop: X operand 


BO, CC, and YY specify the constant (see Appendix A, Instruction Coding). 





SUBTRACT X-Y / SUBTRACT X-Y with BORROW 


Syntax: [ if cond ] ar 

AF 


xop 


- y°p ^ „ 

- yop + C — 1 
+ C-1 

- constant 

- constant + C-l 


Permissible xops 

Permissible yops 

AXO MR2 

AYO 

AX1 MR1 

AY1 

AR MR0 

AF 

SRI 


SR0 



Permissible conds (see Table 15.9) 


EQ 

LE 

AC 

NE 

NEG 

NOT AC 

GT 

POS 

MV 

GE 

AV 

NOT MV 

LT 

NOTAV 

NOT CE 


Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 

0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 

-2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097, -8193, -16385, -32768 

Example: if ge ar = axo - ayo; 

Description: Test the optional condition and, if true, then perform the 
specified subtraction. If the condition is not true then perform a no-operation. 
Omitting the condition performs the subtraction unconditionally. The 
subtraction operation subtracts the second source operand from the first 
source operand, and optionally adds the ALU Carry bit (AC) minus 1 
(H#0001), and stores the result in the destination register. The (C-l) quantity 
effectively implements a borrow capability for multiprecision subtractions. 
The operands are contained in the data registers or constant specified in the 
instruction. 

The xop - constant operation is only available on the ADSP-217x, ADSP-218x, 
and ADSP-21msp58/59 processors and may not be used in multifunction 
instructions. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Set if an arithmetic overflow occurs. Cleared otherwise. 
AC Set if a carry is generated. Cleared otherwise. 


(instruction continues on next page) 



SUBTRACT X-Y / SUBTRACT X-Y with BORROW 


Instruction Format: 

Conditional ALU/MAC operation. Instruction ty]ae 9: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

0 

AMF 

Yop 

Xop 

\L 

0 

0 

3 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 10110 for xop - yop + C - 1 operation. 

AMF = 10111 for xop - yop operation. 

Note that xop + C - 1 is a special case of xop - yop + C - 1 with yop=0. 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 


(xop - constant) Conditional ALU/MAC operation. Instruction Type 9: 
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8765 43210 

0 0 10 0 



Z 

AMF 

YY 

Xop 

CC 

BO 

COND 


AMF specifies the ALU or MAC operation, in this case: 


AMF = 10110 for xop - constant + C - 1 
AMF = 10111 for xop - constant 

Z: Destination register COND: condition 

Xop: X operand 

BO, CC, and YY specify the constant (see Appendix A, Instruction Coding ). 





SUBTRACT Y-X / SUBTRACT Y-X with BORROW 


Syntax: 

[ IF cond ] 

AR 

= 

yop - 

XO P ^ - 



AF 



xop + C - 1 


-xop + C - 1 

-xop + constant 

-xop + constant + C - 1 


Permissible xops Permissible yops Permissible conds (see Table 15.9) 


AXO 

MR2 

AYO 

EQ 

LE 

AC 

AX1 

MR1 

AY1 

NE 

NEG 

NOT AC 

AR 

MR0 

AF 

GT 

POS 

MV 


SRI 


GE 

AV 

NOT MV 


SR0 


LT 

NOTAV 

NOT CE 


Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 

0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 

-2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097, -8193, -16385, -32768 

Example: if gt ar = ayo - axo + c - 1 ; 

Description: Test the optional condition and, if true, then perform the 
specified subtraction. If the condition is not true then perform a no-operation. 
Omitting the condition performs the subtraction unconditionally. The 
subtraction operation subtracts the second source operand from the first 
source operand, optionally adds the ALU Carry bit (AC) minus 1 (H#0001), 
and stores the result in the destination register. The (C-l) quantity effectively 
implements a borrow capability for multiprecision subtractions. The 
operands are contained in the data registers or constant specified in the 
instruction. 

The -xop + constant operation is only available on the ADSP-217x, ADSP-218x, 
and ADSP-21msp58/59 processors and may not be used in multifunction 
instructions. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 

* * * 

AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Set if an arithmetic overflow occurs. Cleared otherwise. 

AC Set if a carry is generated. Cleared otherwise. 


(instruction continues on next page) 



SUBTRACT Y-X / SUBTRACT Y-X with BORROW 


Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

H 

AMF 

Yop 

Xop 

F 

0 

0 

H 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 11010 for yop - xop + C - 1 
AMF = 11001 for yop - xop 

(Note that -xop + C - 1 is a special case of yop - xop + C - 1 with yop=0.) 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 


(-xop + constant) Conditional ALU/MAC operation. Instruction Type 9: 
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 

5 4 

3 2 10 

0 

0 

1 

0 

3 

Z 

AMF 

YY 

Xop 

CC 

BO 

COND 


AMF specifies the ALU or MAC operation, in this case: 

AMF = 11010 for constant - xop + C - 1 
AMF = 11001 for constant - xop 

Z: Destination register COND: condition 

Xop: X operand 

BO, CC, and YY specify the constant (see Appendix A, Instruction Coding ). 


15-26 





AND, OR, XOR 


Syntax: 

[ IF cond ] 

AR 

= xop 

AND 


yop 



AF 

OR 


constant 





XOR 



Permissible xops 

Permissible yops 

AXO MR2 

AYO 

AX1 MR1 

AY1 

AR MRO 

AF 

SRI 


SR0 



Permissible conds (see Table 15.9) 


EQ 

LE 

AC 

NE 

NEG 

NOT AC 

GT 

POS 

MV 

GE 

AV 

NOT MV 

LT 

NOTAV 

NOT CE 


Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 

0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 

-2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097, -8193, -16385, -32768 

Example: ar = axo xor ayo; 

IF FLAG _IN AR = MRO AND 8192; 

Description: Test the optional condition and if true, then perform the 
specified bitwise logical operation (logical AND, inclusive OR, or exclusive 
OR). If the condition is not true then perform a no-operation. Omitting the 
condition performs the logical operation unconditionally. The operands are 
contained in the data registers or constant specified in the instruction. 

The xop AND/OR/XOR constant operation is only available on the ADSP-217x, 
ADSP-218x, and ADSP-21msp58/59 processors and may not be used in 
multifunction instructions. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 
- - - - 0 0 * * 

AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Always cleared. 

AC Always cleared. 


(instruction continues on next page) 


15-27 



AND, OR, XOR 


Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 



AMF specifies the ALU or MAC operation. In this case. 


AMF = 11100 for AND operation. 

AMF = 11101 for OR operation. 

AMF = 11110 for XOR operation. 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 


(xop AND/OR/XOR constant) 

Conditional ALU/MAC operation. Instruction Type 9: 
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 10 9 

876543210 

0 

0 

1 

0 

0 

[I 

AMF 

YY Xop 

CC BO COND 


AMF specifies the ALU or MAC operation, in this case: 


AMF = 11100 for AND operation. 

AMF = 11101 for OR operation. 

AMF = 11110 for XOR operation. 

Z: Destination register COND: condition 

Xop: X operand 

BO, CC, and YY specify the constant (see Appendix A, Instruction Coding). 


15-28 





TEST BIT, SET BIT, CLEAR BIT, TOGGLE BIT 

(ADSP-217X, ADSP-218X, ADSP-21msp58/59 only) 


Syntax: [ if cond l 


AR = 
AF 

TSTBIT n OF xop 
SETBIT n OF xop 
CLRBIT n OF xop 
TGLBIT n OF xop 

Permissible xops 

Permissible conds ( see Table 15.9) 

AXO MR2 

EQ 

LE 

AC 

AX1 MR1 

NE 

NEG 

NOT AC 

AR MRO 

GT 

POS 

MV 

SRI 

GE 

AV 

NOT MV 

SRO 

LT 

NOTAV 

NOT CE 


Permissible n values (0=LSB) 

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 

Examples: af=tstbit 5 of ar; 

AR=TGLBIT 13 OF AXO; 

Description: Test the optional condition and if true, then perform the 
specified bit operation. If the condition is not true then perform a no- 
operation. Omitting the condition performs the operation unconditionally. 

These operations cannot be used in multifunction instructions. 

These operations are defined as follows: 

TSTBIT is an AND operation with a 1 in the selected bit 
SETBIT is an OR operation with a 1 in the selected bit 
CLRBIT is an AND operation with a 0 in the selected bit 
TGLBIT is an XOR operation with a 1 in the selected bit 

The ASTAT status bits are affected by these instructions. The following 
instructions could be used, for example, to test a bit and branch accordingly: 

AF=TSTBIT 5 OF AR; 

IF NE JUMP set; /*Jump to "set" if bit 5 of AR is set*/ 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 
- - 0 0 * * 

AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Always cleared. 

AC Always cleared. 15-29 

(instruction continues on next page) 



TEST BIT, SET BIT, CLEAR BIT, TOGGLE BIT 

(ADSP-217X, ADSP-218X, ADSP-21msp58/59 only) 


Instruction Format: 

(xop AND/OR/XOR constant) 

Conditional ALU/MAC operation. Instruction Type 9: 
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 

8 

7 6 

5 4 

3 2 10 

0 

0 

1 

0 

0 

E 

AMF 

YY 

xop 

CC 

BO 

COND 


AMF specifies the ALU or MAC operation, in this case: 

AMF =11100 for AND operation. 

AMF = 11101 for OR operation. 

AMF = 11110 for XOR operation. 

Z: Destination register COND: condition 

Xop: X operand 

BO, CC, and YY specify the constant (see Appendix A, Instruction Coding). 


15-30 




PASS / CLEAR 


Syntax: 

[ IF cond ] 

AR 

= PASS 

xop 


AF 


yop 

constant 



Permissible xops 

Permissible yops 

AX0 MR2 

AY0 

AX1 MR1 

AY1 

AR MR0 

AF 

SRI 


SR0 



Permissible conds (see Table 15.9) 


EQ 

LE 

AC 

NE 

NEG 

NOT AC 

GT 

POS 

MV 

GE 

AV 

NOT MV 

LT 

NOTAV 

NOT CE 


Permissible constants (all ADSP-21xx processors) 

- 1 , 0,1 

Permissible constants (ADSP-217x, ADSP-2 1 8x, ADSP-21msp58/59 only) 

2, 3, 4, 5, 1, 8, 9, 15, 16, 17, 31, 32, 33, 63, 64, 65, 127, 128, 129, 255, 256, 257, 

511, 512, 513, 1023, 1024, 1025, 2047, 2048, 2049, 4095, 4096, 4097, 8191, 8192, 8193, 

16383, 16384, 16385, 32766, 32767 

-2, -3, -4, -5, -6, -8, -9, -10, -16, -17, -18, -32, -33, -34, -64, -65, -66, 

-128, -129, -130, -256, -257, -258, -512, -513, -514, -1024, -1025, -1026, 

-2048, -2049, -2050, -4096, -4097, -4098, -8192, -8193, -8194, 

-16384, -16385, -16386, -32767, -32768 

Examples: if ge ar = pass ayo ; 

AR = PASS 0; 

AR = PASS 8191; ( ADSP-217x , ADSP-218x, ADSP-21msp58/59 only) 

Description: Test the optional condition and if true, pass the source operand 

unmodified through the ALU block and store in the destination register. If the 
condition is not true perform a no-operation. Omitting the condition performs the 
PASS unconditionally. The source operand is contained in the data register or 
constant specified in the instruction. 

PASS 0 is one method of clearing AR. PASS 0 can also be combined with memory 
reads and writes in a multifunction instruction to clear AR. 

The PASS instruction performs the transfer to the AR or AF register and affects the 
ASTAT status flags (for xop, yop, -1, 0, 1 only). This instruction is different from a 
register move operation which does not affect any status flags. The PASS constant 
operation (using any constant other than -1, 0, or 1) causes the ASTAT status flags to 
be undefined. 

The PASS constant operation (using any constant other than -1, 0, or 1) is only 
available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors and 
may not be used in multifunction instructions. 

(instruction continues on next page) 15-31 



PASS / CLEAR 


Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 
--- - 00 * * 

AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV, AC Always cleared. 

Note: The PASS constant operation (using any constant other than -1, 0, or 1) 
causes the ASTAT status flags to be undefined. 


Instruction Format: 

Conditional ALU /MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

E 

AMF 

Yop 

Xop 

\± 

0 

0 

0 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 10000 for PASS yop 
AMF = 10011 for PASS xop 
AMF = 10001 for PASS 1 
AMF = 11000 for PASS -1 

Note that PASS xop is a special case of xop + yop, with yop=0. 
Note that PASS 1 is a special case of yop + 1, with yop=0. 

Note that PASS -1 is a special case of yop - 1, with yop=0. 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 


Conditional ALU/MAC operation. Instruction Type 9: 
(PASS constant; constant * 0,1 -1) 

(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 

8 

7 6 

5 4 

3 2 10 

m 

0 

1 

0 

° 

Z 

AMF 

YY j 

- j 

Xop 


H 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 10000 for PASS yop (special case of yop, with yop=constant) 

AMF = 10001 for PASS yop + 1 (special case of yop + 1, with yop=constant) 

AMF = 11000 for PASS yop - 1 (special case of yop - 1, with yop=constant) 


Z: Destination register COND: condition 

Xop: X operand 

15-32 BO, CC, and YY specify the constant (see Appendix A, Instruction Coding ). 












NEGATE 


Syntax: 

[ IF cond ] 

AR 

= - 

xop 



AF 


yop 


Permissible xops Permissible pops Permissible conds (see Table 15.9) 


AX0 

MR2 

AY0 

EQ 

LE 

AC 

AX1 

MR1 

AY1 

NE 

NEG 

NOT AC 

AR 

MR0 

AF 

GT 

POS 

MV 


SRI 


GE 

AV 

NOT MV 


SR0 


LT 

NOTAV 

NOT CE 


Example: if lt ar = -ayo; 

Description: Test the optional condition and if true, then NEGATE the 
source operand and store in the destination location. If the condition is not 
true then perform a no-operation. Omitting the condition performs the 
NEGATE operation unconditionally. The source operand is contained in 
the data register specified in the instruction. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 
____ * * * * 


AZ Set if the result equals zero. Cleared otherwise. 
AN Set if the result is negative. Cleared otherwise. 
AV Set if operand = H#8000. Cleared otherwise. 
AC Set if operand equals zero. Cleared otherwise. 


Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 11 

10 9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

Z 

AMF 

Yop 

Xop 

K 

0 

0 

0 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 10101 for -yop operation. 

AMF = 11001 for -xop operation 

Note that -xop is a special case of yop - xop, with yop specified to be 0. 


Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 




NOT 


Syntax: 

[ IF cond ] 

AR 

= NOT 

xop 



AF 


yop 


Permissible xops Permissible yops Permissible conds (see Table 15.9) 


AXO 

MR2 

AY0 

EQ 

LE 

AC 

AX1 

MR1 

AY1 

NE 

NEG 

NOT AC 

AR 

MR0 

AF 

GT 

POS 

MV 


SRI 

0 

GE 

AV 

NOT MV 


SR0 


LT 

NOTAV 

NOT CE 


Example: if ne af = not axo; 

Description: Test the optional condition and if true, then perform the 
logical complement (ones complement) of the source operand and store in 
the destination location. If the condition is not true then perform a no- 
operation. Omitting the condition performs the complement operation 
unconditionally. The source operand is contained in the data register 
specified in the instruction. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 
--- - 00 * * 

AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Always cleared. 

AC Always cleared. 

Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 11 

10 9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

Z 

AMF 

Yop 

Xop 

\t 

0 

0 

3 

COND 


AMF specifies the ALU or MAC operation. In this case, 
AMF = 10100 for NOT yop operation. 

AMF = 11011 for NOT xop operation. 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 




ABSOLUTE VALUE 


Syntax: 

[ IF cond ] 

AR 

AF 

= ABS xop 

Permissible xops Permissible conds (see Table 15.9) 

AXO MR2 

EQ 

LE 

AC 

AX1 MR1 

NE 

NEG 

NOT AC 

AR MRO 

GT 

POS 

MV 

SRI 

GE 

AV 

NOT MV 

SRO 

LT 

NOTAV 

NOT CE 


Example: if neg af = abs axo ; 

Description: Test the optional condition and, if true, then take the 
absolute value of the source operand and store in the destination location. 
If the condition is not true then perform a no-operation. Omitting the 
condition performs the absolute value operation unconditionally. The 
source operand is contained in the data register specified in the 
instruction. 

Status Generated: 

ASTAT: 7654321 0 

SS MV AQ AS AC AV AN AZ 

* o * * * 

AZ Set if the result equals zero. Cleared otherwise. 

AN Set if xop is H#8000. Cleared otherwise. 

AV Set if xop is H#8000. Cleared otherwise. 

AC Always cleared. 

AS Set if the source operand is negative. Cleared otherwise. 


Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

Z 

AMF 

0 

° 

Xop 

l! 

0 

0 

0 

COND 


AMF specifies the ALU or MAC operation. In this case, 
AMF = 11111 for ABS xop operation. 

Z: Destination register 

Xop: X operand 


COND: condition 




INCREMENT 


Syntax: 


[ IF cond ] 


AR 

AF 


= yop + 1 ; 


Permissible yops Permissible conds (see Table 15.9) 


AYO EQ LE AC 

AY1 NE NEG NOT AC 

AF GT POS MV 

GE AV NOT MV 

LT NOTAV NOT CE 


Example: if gt af = af + 1; 


Description: Test the optional condition and if true, then increment the 
source operand by H#000 1 and store in the destination location. If the 
condition is not true then perform a no-operation. Omitting the condition 
performs the increment operation unconditionally. The source operand is 
contained in the data register specified in the instruction. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


AZ Set if the result equals zero. Cleared otherwise. 
AN Set if the result is negative. Cleared otherwise. 

AV Set if an overflow is generated. Cleared otherwise. 
AC Set if a carry is generated. Cleared otherwise. 

Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 22 21 20 19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 10 

0 0 10 0 

Z 

AMF 

Yop 

Xop 

0 0 0 0 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 10001 for yop + 1 operation. 

Note that the xop field is ignored for the increment operation. 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 




DECREMENT 


Syntax: 


[ IF cond ] 


AR 

AF 


yop - 1 ; 


Permissible yops Permissible conds (see Table 15.9) 


AYO EQ LE AC 

AY1 NE NEG NOT AC 

AF GT POS MV 

GE AV NOT MV 

LT NOTAV NOT CE 


Example: if eq ar = ayi - 1 ; 


Description: Test the optional condition and if true, then decrement the 
source operand by H#0001 and store in the destination location. If the 
condition is not true then perform a no-operation. Omitting the condition 
performs the decrement operation unconditionally. The source operand is 
contained in the data register specified in the instruction. 

Status Generated: 

ASTAT: 7654321 0 

SS MV AQ AS AC AV AN AZ 
* * * * 


AZ Set if the result equals zero. Cleared otherwise. 
AN Set if the result is negative. Cleared otherwise. 

AV Set if an overflow is generated. Cleared otherwise. 
AC Set if a carry is generated. Cleared otherwise. 


Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

s 

AMF 

Yop 

Xop 

K 

0 

0 

T 

COND 


AMF specifies the ALU or MAC operation. In this case, 

AMF = 11000 for yop - 1 operation. 

Note that the xop field is ignored for the decrement operation. 

Z: Destination register Yop: Y operand 

Xop: X operand COND: condition 




DIVIDE 


Syntax: divs yop, xop ; 

DIVQ xop ; 

Permissible xops Permissible yops 
AXO MR2 AY1 

AX1 MR1 AF 

AR MRO 
SRI 
SRO 

Description: These instructions implement yop h- xop. There are two 
divide primitives, DIVS and DIVQ. A single precision divide, with a 32-bit 
numerator and a 16-bit denominator, yielding a 16-bit quotient, executes 
in 16 cycles. Higher precision divides are also possible. 

The division can be either signed or unsigned, but both the numerator and 
denominator must be the same; both signed or unsigned. The programmer 
sets up the divide by sorting the upper half of the numerator in any 
permissible yop (AY1 or AF), the lower half of the numerator in AYO, and 
the denominator in any permissible xop. The divide operation is then 
executed with the divide primitives, DIVS and DIVQ. Repeated execution 
of DIVQ implements a non-restoring conditional add-subtract division 
algorithm. At the conclusion of the divide operation the quotient will be in 
AYO. 

To implement a signed divide, first execute the DIVS instruction once, 
which computes the sign of the quotient. Then execute the DIVQ 
instruction for as many times as there are bits remaining in the quotient 
(e.g., for a signed, single-precision divide, execute DIVS once and DIVQ 15 
times). 

To implement an unsigned divide, first place the upper half of the 
numerator in AF, then set the AQ bit to zero by manually clearing it in the 
Arithmetic Status Register, AST AT. This indicates that the sign of the 
quotient is positive. Then execute the DIVQ instruction for as many times 
as there are bits in the quotient (e.g., for an unsigned single-precision 
divide, execute DIVQ 16 times). 

The quotient bit generated on each execution of DIVS and DIVQ is the AQ 
bit which is written to the AST AT register at the end of each cycle. The 
final remainder produced by this algorithm (and left over in the AF 
register) is not valid and must be corrected if it is needed. For more 
information, consult the Division Exceptions appendix of this manual. 



DIVIDE 


Status Generated: 

ASTAT: 7654321 0 

SS MV AQ AS AC AV AN AZ 


AQ Loaded with the bit value equal to the AQ bit computed on each 
cycle from execution of the DIVS or DIVQ instruction. 


Instruction Format: 

DIVQ, Instruction Type 23: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 9 8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

1 

1 

1 

0 

0 

0 

1 

0 

Xop 

± 

0 

0 

0 

0 

0 

0 

0 


DIVS, Instruction Type 24: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 11 

10 9 8 

7 6 

5 

4 

3 

2 

1 0 

0 

0 

0 

0 

0 

1 

1 

0 

0 

0 

0 

Yop 

Xop 

0 0 

0 

0 

0 

0 

0 0 


Xop: X operand Yop: Y operand 





GENERATE ALU STATUS 

(ADSP-217X, ADSP-218X, ADSP-21msp58/59 only) 


Syntax: none = <alu> ; 

<ALU> may be any unconditional ALU operation except DIVS or DTVQ.* 

Examples: none = axo - ayo; 

NONE = PASS SRO; 

Description: Perform the designated ALU operation, generate the AST AT 
status flags, then discard the result value. This instruction allows the testing 
of register values without disturbing the contents of the AR or AF registers. 

* Note that the additional-constant ALU operations of the ADSP-217x, 
ADSP-218x, ADSP-21msp58/59 processors are also not allowed: 

ADD (xop + constant ) 

SUBTRACT X-Y ( xop - constant ) 

SUBTRACT Y-X (-xop + constant ) 

AND, OR, XOR (xop • constant) 

PASS (PASS constant, using any constant other than -1, 0, or 1) 

TSTBIT, SETBIT, CLRBIT, TGLBIT. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


AZ Set if the result equals zero. Cleared otherwise. 

AN Set if the result is negative. Cleared otherwise. 

AV Set if an arithmetic overflow occurs. Cleared otherwise. 
AC Set if a carry is generated. Cleared otherwise. 


Instruction Format: 

ALU/MAC operation with Data Register Move, Instruction Type 8: 



AMF specifies the ALU or MAC operation (only ALU operations are allowed). 
Xop: X operand Yop: Y operand 


15-40 




MULTIPLY 


Syntax: 

[ IF cond] 

MR 

= xop * 

yop 



MF 


xop 


(SS) 

(SU) 

(US) 

(UU) 

(RND) 


Permissible 

xops 

Permissible yops 

Permissible conds (see Table 15.9) 

MXO 

AR 

MYO 

EQ 

LE 

AC 

MX1 

SRI 

MY1 

NE 

NEG 

NOT AC 

MR2 

SRO 

MF 

GT 

POS 

MV 

MR1 



GE 

AV 

NOT MV 

MRO 



LT 

NOTAV 

NOT CE 


Examples: IF EQ MR = MXO * MF (UU); xop * yop 

MF = SRO * SRO (SS); xop * xop 


Description: Test the optional condition and, if true, then multiply the 

two source operands and store in the destination location. If the condition 
is not true perform a no-operation. Omitting the condition performs the 
multiplication unconditionally. The operands are contained in the data 
registers specified in the instruction. When MF is the destination operand, 
only bits 31-16 of the product are stored in MF. 


The xop * xop squaring operation is only available on the ADSP-217x, 
ADSP-218x, and ADSP-21msp58/59 processors. Both xops must be the 
same register. This option allows single-cycle X 2 and XX 2 instructions. 

The data format selection field following the two operands specifies 
whether each respective operand is in Signed (S) or Unsigned (U) format. 
The xop is specified first and yop is second. If the xop * xop operation is 
used, the data format selection field must be (UU), (SS), or (RND) only. 
There is no default; one of the data formats must be specified. 

If RND (Round) is specified, the MAC multiplies the two source operands, 
rounds the result to the most significant 24 bits (or rounds bits 31-16 to 16 
bits if there is no overflow from the multiply), and stores the result in the 
destination register. The two multiplication operands xop and yop (or xop 
and xop) are considered to be in twos complement format. All rounding is 
unbiased, except on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 
processors, which offer a biased rounding mode. For a discussion of 
biased vs. unbiased rounding, see "Rounding Mode" in the "Multiplier/ 
Accumulator" section of Chapter 2, Computation Units: 


(instruction continues on next page) 



MULTIPLY 


Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

' SS MV AQ AS AC AV AN AZ 


MV Set on MAC overflow (if any of upper 9 bits of MR are not 

all one or zero). Cleared otherwise. 


Instruction Format: 

(xop * yop) Conditional ALU/MAC Operation, Instruction Type 9: 



AMF: Specifies the ALU or MAC Operation. In this case. 


AMF FUNCTION Data Format X-Operand Y-Operand 

0 010 0 xop * yop (SS) Signed Signed 

0 0101 xop * yop (SU) Signed Unsigned 

0 0110 xop * yop (US) Unsigned Signed 

0 0111 xop * yop (UU) Unsigned Unsigned 

0 0 0 01 xop * yop (RND) Signed Signed 

Z: Destination register Yop: Y operand register 

Xop: X operand register COND: condition 


(xop * xop) Conditional ALU/MAC Operation, Instruction Type 9: 
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 9 8 

7 

6 

5 

4 3 2 1 0 

0 

0 

1 

0 

0 

n 

AMF 

_! 

0 

Xop 

1 

0 

0 

1 COND 


AMF: Specifies the ALU or MAC Operation. In this case. 


AMF FUNCTION Data Format X-Operand 
0 010 0 xop * xop (SS) Signed 

0 0111 xop * xop (UU) Unsigned 

0 0 0 01 xop * xop (RND) Signed 

Z: Destination register COND: condition 

Xop: X operand register 


15-42 





MULTIPLY / ACCUMULATE 


Syntax: 


[ IF cond ] 

MR 

n 

s 

+ 

xop * yop 

(SS) 

/ 




MF 


xop 

(SU) 

(US) 

(UU) 

(RND) 



Permissible 

xops 

Permissible yops 

Permissible conds (see Table 15.9) 

MXO 

AR 

MYO 


EQ 

LE 

AC 


MX1 

SRI 

MY1 


NE 

NEG 

NOT AC 

MR2 

SRO 

MF 


GT 

POS 

MV 


MR1 




GE 

AV 

NOT MV 

MRO 




LT 

NOTAV 

NOTCE 


Examples: IF GE MR = MR + MXO * MY1 (SS) ; xop *yop 

MR = MR + MXO * MXO (SS); xop * xop 

Description: Test the optional condition and, if true, then multiply the 
two source operands, ada the product to the present contents of the MR 
register, and store the result in the destination location. If the condition is 
not true then perform a no-operation. Omitting the condition performs the 
multiply/ accumulate unconditionally. The operands are contained in the 
data registers specified in the instruction. When MF is the destination 
operand, only bits 31-16 of the 40-bit result are stored in MF. 

The xop * xop squaring operation is only available on the ADSP-217x, 
ADSP-218x, and ADSP-21msp58/59 processors. Both xops must be the 
same register. This option allows single-cycle X 2 and XX 2 instructions. 

The data format selection field to the right of the two operands specifies 
whether each respective operand is in signed (S) or unsigned (U) format. 
The xop is specified first and yop is second. If the xop * xop operation is 
used, the data format selection field must be (UU), (SS), or (RND) only. 
There is no default; one of the data formats must be specified. 

If RND (Round) is specified, the MAC multiplies the two source operands, 
adds the product to the current contents of the MR register, rounds the 
result to the most significant 24 bits (or rounds bits 31-16 to the nearest 16 
bits if there is no overflow from the multiply /accumulate), and stores the 
result in the destination register. The two multiplication operands xop and 
yop (or xop and xop) are considered to be in twos complement format. All 
rounding is unbiased, except on the ADSP-217x, ADSP-218x, and ADSP- 
21msp58/59 processors, which offer a biased rounding mode. For a 
discussion of biased vs. unbiased rounding, see "Rounding Mode" in the 
"Multiplier/ Accumulator" section of Chapter 2, Computation Units. 


(instruction continues on next page) 


15-43 



MULTIPLY / ACCUMULATE 


Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set on MAC overflow (if any of upper 9 bits of MR are not 

all one or zero). Cleared otherwise. 


Instruction Format: 

(xop * yop) Conditional ALU /MAC Operation, Instruction Type 9: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 10 0 

Z 

AMF 

Yop 

Xop 

0 0 0 0 

COND 


AMF: Specifies the ALU or MAC Operation. In this case. 


AMF 

FUNCTION 

Data Format 

X-Operand 

01000 

MR+xop * yop 

(SS) 

Signed 

01001 

MR+xop * yop 

(SU) 

Signed 

01010 

MR+xop * yop 

(US) 

Unsigned 

01011 

MR+xop * yop 

(UU) 

Unsigned 

00010 

MR+xop * yop 

(RND) 

Signed 


Y-Operand 

Signed 

Unsigned 

Signed 

Unsigned 

Signed 


Z: Destination register Yop: Y operand register 

Xop: X operand register COND: condition 


(xop * xop ) Conditional ALU/MAC Operation, Instruction Type 9: 
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

Z 

AMF 

1 

Z 

z 

Xop 

E 

0 

0 

3 

COND 


AMF: Specifies the ALU or MAC Operation. In this case. 


AMF FUNCTION 
010 0 0 MR+xop * xop 
01011 MR+xop * xop 
0 0 010 MR+xop * xop 


Data Format X-Operand 
(SS) Signed 

(UU) Unsigned 

(RND) Signed 


Z: Destination register COND: condition 

Xop: X operand register 


15-44 




MULTIPLY / SUBTRACT 


Syntax: 

[ IF cond 1 

MR 

= MR - xop * 

yop 



MF 


xop 


(SS) 

(SU) 

(US) 

(UU) 

(RND) 


Permissible xops 

Permissible yops 

Permissible conds (see Table 15.9) 

MXO AR 

MYO 

EQ 

LE 

AC 

MX1 SRI 

MY1 

NE 

NEG 

NOT AC 

MR2 SRO 

MF 

GT 

POS 

MV 

MR1 


GE 

AV 

NOT MV 

MRO 


LT 

NOTAV 

NOT CE 

Examples: 

IF LT MR = MR - MX1 * 

MYO (SU) ; 

xop * yop 


MR = MR - MXO * MXO 

(SS); 


xop * xop 


Description: Test the optional condition and, if true, then multiply the 

two source operands, subtract the product from the present contents of 
the MR register, and store the result in the destination location. If the 
condition is not true perform a no-operation. Omitting the condition 
performs the multiply/ subtract unconditionally. The operands are 
contained in the data registers specified in the instruction. When MF is the 
destination operand, only bits 16-31 of the 40-bit result are stored in MF. 


The xop * xop squaring operation is only available on the ADSP-217x, 
ADSP-218x, and ADSP-21msp58/59 processors. Both xops must be the 
same register. 

The data format selection field to the right of the two operands specifies 
whether each respective operand is in signed (S) or unsigned (U) format. 
The xop is specified first and yop is second. If the xop * xop operation is 
used, the data format selection field must be (UU), (SS), or (RND) only. 
There is no default; one of the data formats must be specified. 


If RND (Round) is specified, the MAC multiplies the two source operands, 
subtracts the product from the current contents of the MR register, rounds 
the result to the most significant 24 bits (or rounds bits 31-16 to 16 bits if 
there is no overflow from the multiply/ accumulate), and stores the result 
in the destination register. The two multiplication operands xop and yop 
(or xop and xop) are considered to be in twos complement format. All 
rounding is unbiased, except on the ADSP-217x, ADSP-218x, and ADSP- 
21msp58/59 processors, which offer a biased rounding mode. For a 
discussion of biased vs. unbiased rounding, see "Rounding Mode" in the 
"Multiplier/ Accumulator" section of Chapter 2, Computation Units. 

15-45 

(instruction continues on next page) 



MULTIPLY /SUBTRACT 


Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set on MAC overflow (if any of the upper 9 bits of MR are 

not all one or zero). Cleared otherwise. 


Instruction Format: 

(xop * yop) Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

Z 

AMF 

Yop 

Xop 

E 

0 

0 

3 

COND 


AMF: Specifies the ALU or MAC Operation. In this case. 


AMF 

FUNCTION 

Data Format 

X-Operand 

01100 

MR-xop 

* yop 

(SS) 

Signed 

01101 

MR-xop 

* yop 

(SU) 

Signed 

01 1 1 0 

MR-xop 

* y°p 

(US) 

Unsigned 

01111 

MR-xop 

* yop 

(UU) 

Unsigned 

0001 1 

MR-xop 

* yop 

(RND) 

Signed 


Y -Operand 

Signed 

Unsigned 

Signed 

Unsigned 

Signed 


Z: Destination register Yop: Y operand register 

Xop: X operand register COND: condition 


(xop * xop) Conditional ALU/MAC Operation, Instruction Type 9: 
( ADSP-217x , ADSP-218x, ADSP-21msp58/59 only) 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

E 

AMF 

0 

0 

Xop 

E 

0 

0 

3 

COND 


AMF: Specifies the ALU or MAC Operation. In this case. 


AMF FUNCTION 
0110 0 MR-xop * xop 
01111 MR-xop * xop 
0 0 01 1 MR-xop * xop 


Data Format X-Operand 
(SS) Signed 

(UU) Unsigned 

(RND) Signed 


Z: Destination register COND: condition 

Xop: X operand register 





CLEAR 


Syntax: 


[ IF cond ] 


MR 

MF 


= 0 ; 


Permissible conds (see Table 15.9) 


EQ 

NE 

GT 

GE 

LT 

LE 

NEG 

POS 

AV 

NOT AV 

AC 

NOT AC 

MV 

NOT MV 

NOT CE 


Example: if gt mr = 0; 

Description: Test the optional condition and, if true, then set the 
specified register to zero. If the condition is not true perform a no- 
operation. Omitting the condition performs the clear unconditionally. The 
entire 40-bit MR or 16-bit MF register is cleared to zero. 

Status Generated: 

ASTAT: 7 6 5 4 

SS MV AQ AS 
- 0 - - 

MV Always cleared. 

Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


3 2 10 

AC AV AN AZ 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

PE 

AMF 

1 

3 

d 

0 

Pj 

E 

0 

0 

I] 

COND 


AMF: Specifies the ALU or MAC Operation. In this case, 
AMF = 00100 for clear operation. 


Note that this instruction is a special case of xop * yop, with yop set to 
zero. 


Z: Destination register 


COND: condition 




TRANSFER MR 


Syntax: [ if cond ] 


MR 

MF 


MR [ (RND) ] ; 


Permissible conds (see Table 15.9) 


EQ 

NE 

GT 

GE 

LT 

LE 

NEG 

POS 

AV 

NOTAV 

AC 

NOT AC 

MV 

NOT MV 

NOT CE 


Example: if eq mf = mr (rnd); 


Description: Test the optional condition and, if true, then perform the 
MR transfer according to the description below. If the condition is not true 
then perform a no-operation. Omitting the condition performs the transfer 
unconditionally. 

This instruction actually performs a multiply/accumulate, specifying yop = 
0 as a multiplicand and adding the zero product to the contents of MR. The 
MR register may be optionally rounded at the boundary between bits 15 
and 16 of the result by specifying the RND option. If MF is specified as the 
destination, bits 31-16 of the result are stored in MF. If MR is the 
destination, the entire 40-bit result is stored in MR. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set on MAC overflow (if any of upper 9 bits of MR are not 

all one or zero). Cleared otherwise. 


Instruction Format: 

Conditional ALU/MAC Operation, Instruction Type 9: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

1 

0 

0 

[I 

AMF 

1 

1 

0 

0 

3 


0 

0 

I] 

COND 


AMF: Specifies the ALU or MAC Operation. In this case. 


AMF = 01000 for Transfer MR operation 

Note that this instruction is a special case of MR + xop * yop, with yop set to 
zero. 


Z: 


Destination register 


COND: 


condition 




CONDITIONAL MR SATURATION 


Syntax: if mv sat mr ; 

Description: Test the MV (MAC Overflow) bit in the Arithmetic Status 
Register (ASTAT), and if set, then saturate the lower-order 32 bits of the 
40-bit MR register; if the MV is not set then perform a no-operation. 

Saturation of MR is executed with this instruction for one cycle only; MAC 
saturation is not a continuous mode that is enabled or disabled. The 
saturation instruction is intended to be used at the completion of a series 
of multiply/ accumulate operations so that temporary overflows do not 
cause the accumulator to saturate. 

The saturation result depends on the state of MV and on the sign of MR 
(the MSB of MR2). The possible results after execution of the saturation 
instruction are shown in the table below. 


MV MSB of MR2 


MR contents after saturation 


0 0 
0 1 
1 0 
1 1 


No change 
No change 


00000000 0111111111111111 
11111111 1000000000000000 


1111111111111111 

0000000000000000 


Status Generated: No status bits affected. 


Instruction Format: 

Saturate MR operation. Instruction Type 25: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 




ARITHMETIC SHIFT 


Syntax: [ IF cond ] SR = [SR OR] ASHIFT xop 


(HI) 

(LO) 


Permissible xops Permissible conds (see Table 15,9) 


SI 

AR 

EQ 

LE 

AC 

SRI 

MR2 

NE 

NEG 

NOT AC 

SRO 

MR1 

GT 

POS 

MV 


MRO 

GE 

AV 

NOT MV 



LT 

NOTAV 

NOT CE 


Example: if lt sr = sr or ashift si (lo); 

Description: Test the optional condition and, if true, then perform the 
designated arithmetic shirt. If the condition is not true then perform a no- 
operation. Omitting the condition performs the shift unconditionally. The 
operation arithmetically shifts the bits of the operand by the amount and 
direction specified in the Shift Code from the SE register. Positive Shift 
Codes cause a left shift (upshift) and negative codes cause a right shift 
(downshift). 

The shift may be referenced to the upper half of the output field (HI 
option) or to the lower half (LO option). The shift output may be logically 
ORed with the present contents of the SR register by selecting the SR OR 
option. 

For ASHIFT with a positive Shift Code (i.e. positive value in SE), the 
operand is shifted left; with a negative Shift Code (i.e. negative value in 
SE), the operand is shifted right. The number of positions shifted is the 
count in the Shift Code. The 32-bit output field is sign-extended to the left 
(the MSB of the input is replicated to the left), and the output is zero-filled 
from the right. Bits shifted out of the high order bit in the 32-bit 
destination field (SR 3 i) are dropped. Bits shifted out of the low order bit in 
the destination field (SRq) are dropped. 

To shift a double precision number, the same Shift Code is used for both 
halves of the number. On the first cycle, the upper half of the number is 
shifted using an ASHIFT with the HI option; on the following cycle, the 
lower half of the number is shifted using an LSHIFT with the LO and OR 
options. This prevents sign bit extension of the lower word's MSB. 

Status Generated: None affected. 



ARITHMETIC SHIFT 


Instruction Format: 

Conditional Shift Operation, Instruction Type 16: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

1 

1 

0 

0 

SF 

Xop 


0 

0 

0 

COND 


SF Shifter Function 
010 0 ASHIFT (HI) 
0101 ASHIFT (HI, OR) 

0110 ASHIFT (LO) 

0111 ASHIFT (LO, OR) 


Xop: shifter operand 


COND: 


condition 




LOGICAL SHIFT 


Syntax: [ IF cond ] SR = [SR OR] LSHIFT xop 


(HI) 

(LO) 


Permissible xops Permissible conds (see Table 15.9) 


SI 

AR 

EQ 

LE 

AC 

SRI 

MR2 

NE 

NEG 

NOT AC 

SRO 

MR1 

GT 

POS 

MV 


MRO 

GE 

AV 

NOT MV 



LT 

NOTAV 

NOT CE 


Example: if ge sr = lshift si (Hi) ; 

Description: Test the optional condition and, if true, then perform the 
designated logical shift. If the condition is not true then perform a no- 
operation. Omitting the condition performs the shift unconditionally. The 
operation logically shifts the bits of the operand by the amount and 
direction specified in the Shift Code from the SE register. Positive Shift 
Codes cause a left shift (upshift) and negative Codes cause a right shift 
(downshift). 


The shift may be referenced to the upper half of the output field (HI 
option) or to the lower half (LO option). The shift output may be logically 
ORed with the present contents of the SR register by selecting the SR OR 
option. 

For LSHIFT with a positive Shift Code, the operand is shifted left; the 
numbers of positions shifted is the count in the Shift Code. The 32-bit 
output field is zero-filled from the right. Bits shifted out of the high order 
bit in the 32-bit destination field (SR 31 ) are dropped. 

For LSHIFT with a negative Shift Code, the operand is shifted right; the 
number of positions shifted is the count in the Shift Code. The 32-bit 
output field is zero-filled from the left. Bits shifted out of the low order bit 
in the destination field (SRq) are dropped. 

To shift a double precision number, the same Shift Code is used for both 
halves of the number. On the first cycle, the upper half of the number is 
shifted using the HI option; on the following cycle, the lower half of the 
number is shifted using the LO and OR options. 

Status Generated: None affected. 



LOGICAL SHIFT 


Instruction Format: 

Conditional Shift Operation, Instruction Type 16: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

1 

1 

0 

0 

SF 

Xop 

E 

0 

0 

3 

COND 


SF Shifter Function 
0 00 0 LSHIFT (HI) 

0 001 LSHIFT (HI, OR) 
0 010 LSHIFT (LO) 

0 011 LSHIFT (LO, OR) 


Xop: shifter operand 


COND: condition 




NORMALIZE 


Syntax: [ IF cond ] SR = [SR OR] NORM xop 


(HI) 

(LO) 


Permissible xops Permissible conds ( see Table 15.9) 


SI 

AR 

EQ 

LE 

AC 

SRI 

MR2 

NE 

NEG 

NOT AC 

SRO 

MR1 

GT 

POS 

MV 


MRO 

GE 

AV 

NOT MV 



LT 

NOT AV 

NOT CE 


Example: sr = norm si (Hi) ; 

Description: Test the optional condition and, if true, then perform the 
designated normalization. If the condition is not true then perform a no- 
operation. Omitting the condition performs the normalize 
unconditionally. The operation arithmetically shifts the input operand to 
eliminate all but one of the sign bits. The amount of the shift comes from 
the SE register. The SE register may be loaded with the proper Shift Code 
to eliminate the redundant sign bits by using the Derive Exponent 
instruction; the Shift Code loaded will be the negative of the quantity: (the 
number of sign bits minus one). 

The shift may be referenced to the upper half of the output field (HI 
option) or to the lower half (LO option). The shift output may be logically 
ORed with the present contents of the SR register by selecting the SR OR 
option. When the LO reference is selected, the 32-bit output field is zero- 
filled to the left. Bits shifted out of the high order bit in the 32-bit 
destination field (SR 3 i) are dropped. 

The 32-bit output field is zero-filled from the right. If the exponent of an 
overflowed ALU result was derived with the HIX modifier, the 32-bit 
output field is filled from left with the ALU Carry (AC) bit in the 
Arithmetic Status Register (AST AT) during a NORM (HI) operation. In 
this case (SE=1 from the exponent detection on the overflowed ALU 
value) a downshift occurs. 

To normalize a double precision number, the same Shift Code is used for 
both halves of the number. On the first cycle, the upper half of the number 
is shifted using the HI option; on the following cycle, the lower half of the 
number is shifted using the LO and OR options. 


Status Generated: None affected. 



NORMALIZE 


Instruction Format: 

Conditional Shift Operation, Instruction Type 16: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

1 

1 

0 

0 

SF 

Xop 

H 

0 

0 

0 

COND 


SF Shifter Function 
10 0 0 NORM (HI) 

10 01 NORM (HI, OR) 

1010 NORM (LO) 

1011 NORM (LO, OR) 

Xop: shifter operand 


COND: condition 




DERIVE EXPONENT 


Syntax: 


[ IF cond ] SE = EXP xop 


(HI) 

(LO) 

(HIX) 


Permissible xops Permissible conds (see Table 15.9) 


SI 

AR 

EQ 

LE 

AC 

SRI 

MR2 

NE 

NEG 

NOT AC 

SRO 

MRI 

GT 

POS 

MV 


MRO 

GE 

AV 

NOT MV 



LT 

NOTAV 

NOT CE 


Example: if gt se = exp mri (Hi) ; 

Description: Test the optional condition and, if true, perform the 
designated exponent operation. If the condition is not true then perform a 
no-operation. Omitting the condition performs the exponent operation 
unconditionally. 

The EXP operation derives the effective exponent of the input operand to 
prepare for the normalization operation (NORM). EXP supplies the source 
operand to the exponent detector, which generates a Shift Code from the 
number of leading sign bits in the input operand. The Shift Code, stored in 
SE at the completion of the EXP instruction, is the effective exponent of the 
input value. The Shift Code depends on which exponent detector mode is 
used (HI, HIX, LO). 


In the HI mode, the input is interpreted as a single precision signed 
number, or as the upper half of a double precision signed number. The 
exponent detector counts the number of leading sign bits in the source 
operand and stores the resulting Shift Code in SE. The Shift Code will 
equal the negative of the number of redundant sign bits in the input. 

In the HIX mode, the input is interpreted as the result of an add or 
subtract which may have overflowed. HIX is intended to handle shifting 
and normalization of results from ALU operations. The HIX mode 
examines the ALU Overflow bit (AV) in the Arithmetic Status Register: if 
AV is set, then the effective exponent of the input is +1 (indicating that an 
ALU overflow occurred before the EXP operation), and +1 is stored in SE. 
If AV is not set, then HIX performs exactly the same operations as the HI 
mode. 



DERIVE EXPONENT 


In the LO mode, the input is interpreted as the lower half of a double 
precision number. In performing the EXP operation on a double precision 
number, the higher half of the number must first be processed with EXP in 
the HI or HIX mode, and then the lower half can be processed with EXP in 
the LO mode. If the upper half contained a non-sign bit, then the correct 
Shift Code was generated in the HI or HIX operation and that is the code 
that is stored in SE. If, however, the upper half was all sign bits, then EXP 
in the LO mode totals the number of leading sign bits in the double 
precision word and stores the resulting Shift Code in SE. 

Status Generated: 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


SS Set by the MSB of the input for an EXP operation in the HI 

or HIX mode with AV = 0. Set by the MSB inverted in the 
HIX mode with AV = 1. Not affected by operations in the 
LO mode. 


Instruction Format: 

Conditional Shift Operation, Instruction Type 16: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

1 

1 

0 


SF 

Xop 

II 

0 

0 

l] 

COND 


SF Shifter Function 

1100 EXP (HI) 

1101 EXP (HIX) 

1110 EXP (LO) 

Xop: shifter operand COND: condition 


15-57 




BLOCK EXPONENT ADJUST 


Syntax: [ IF cond ] SB = EXPADJ xop ; 

Permissible xops Permissible conds ( see Table 15.9) 


SI 

AR 

EQ 

LE 

AC 

SRI 

MR2 

NE 

NEG 

NOT AC 

SRO 

MR1 

GT 

POS 

MV 


MRO 

GE 

AV 

NOT MV 



LT 

NOTAV 

NOT CE 


Example: if gt sb = expadj si ; 

Description: Test the optional condition and, if true, perform the 
designated exponent operation. If the condition is not true then perform a 
no-operation. Omitting the condition performs the exponent operation 
unconditionally. The Block Exponent Adjust operation, when performed 
on a series of numbers, derives the effective exponent of the number 
largest in magnitude. This exponent can then be associated with all of the 
numbers in a block floating point representation. 

The Block Exponent Adjust circuitry applies the input operand to the 
exponent detector to derive its effective exponent. The input must be a 
signed twos complement number. The exponent detector operates in HI 
mode (see the EXP instruction, above). 

At the start of a block, the SB register should be initialized to -16 to set SB 
to its minimum value. On each execution of the EXPADJ instruction, the 
effective exponent of each operand is compared to the current contents of 
the SB register. If the new exponent is greater than the current SB value, it 
is written to the SB register, updating it. Therefore, at the end of the block, 
the SB register will contain the largest exponent found. EXPADJ is only an 
inspection operation; no actual shifting takes place since the true exponent 
is not known until all the numbers in the block have been checked. 
However, the numbers can be shifted at a later time after the true 
exponent has been derived. 

Extended (overflowed) numbers and the lower halves of double precision 
numbers can not be processed with the Block Exponent Adjust instruction. 


Status Generated: Not affected. 



BLOCK EXPONENT ADJUST 


Instruction Format: 

Conditional Shift Operation, Instruction Type 16: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 

11 

10 9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

1 

1 

0 

0 

SF 

Xop 


0 

0 

±J 

COND 


SF = 1111. 

Xop: shifter operand 


COND: condition 




ARITHMETIC SHIFT IMMEDIATE 


Syntax: SR = [SR OR] ASHIFT xop BY <exp> 


(HI) 

(LO) 


Permissible xops <exp> 

SI MRO Any constant between -128 and 127* 

SRI MR1 

SRO MR2 

AR 

Example: SR = SR OR ASHIFT SRO BY 3 (LO); {do not use // +3"} 

Description: Arithmetically shift the bits of the operand by the amount 
and direction specified by the constant in the exponent field. Positive 
constants cause a left shift (upshift) and negative constants cause a right 
shift (downshift). A positive constant must be entered without a "+" sign. 

The shift may be referenced to the upper half of the output field (HI 
option) or to the lower half (LO option). The shift output may be logically 
ORed with the present contents of the SR register by selecting the SR OR 
option. 

For ASHIFT with a positive shift constant the operand is shifted left; with 
a negative shift constant the operand is shifted right. The 32-bit output 
field is sign-extended to the left (the MSB of the input is replicated to the 
left), and the output is zero-filled from the right. Bits shifted out of the 
high order bit in the 32-bit destination field (SR 31 ) are dropped. Bits shifted 
out of the low order bit in the destination field (SRo) are dropped. 

To shift a double precision number, the same shift constant is used for 
both halves of the number. On the first cycle, the upper half of the number 
is shifted using an ASHIFT with the HI option; on the following cycle, the 
lower half is shifted using an LSHIFT with the LO and OR options. This 
prevents sign bit extension of the lower word's MSB. 

* See Table 2.4 in Chapter 2. 

Status Generated: None affected. 



ARITHMETIC SHIFT IMMEDIATE 


Instruction Format: 

Shift Immediate Operation, Instruction Type 15: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 

11 

10 9 8 

7 

6 5 4 3 2 1 0 

0 

0 

0 

0 

1 

1 

1 

1 

o 

SF 

Xop 

<exp> 


SF Shifter Function 
010 0 ASHIFT (HI) 
0101 ASHIFT (HI, OR) 

0110 ASHIFT (LO) 

0111 ASHIFT (LO, OR) 


Xop: Shifter Operand 


<exp>: 8-bit signed shift value 




LOGICAL SHIFT IMMEDIATE 


Syntax: SR 

Permissible xops 
SI MRO 

SRI MR1 

SRO MR2 

AR 


[SR OR] LSHIFT xop BY <exp> 


(HI) 

(LO) 


<exp> 

Any constant between -128 and 127* 



Example: sr = lshift sri by -6 (Hi) ; 

Description: Logically shifts the bits of the operand by the amount and 
direction specified By the constant in the exponent field. Positive constants 
cause a left shift (upshift); negative constants cause a right shift 
(downshift). A positive constant must be entered without a "+" sign. 


The shift may be referenced to the upper half of the output field (HI 
option) or to the lower half (LO option). The shift output may be logically 
ORed with the contents of the SR register by selecting the SR OR option. 

For LSHIFT with a positive shift constant, the operand is shifted left. The 
32-bit output field is zero-filled to the left and from the right. Bits shifted 
out of the high order bit in the 32-bit destination field (SR 31 ) are dropped. 
For LSHIFT with a negative shift constant, the operand is shifted right. 
The 32-bit output field is zero-filled from the left and to the right. Bits 
shifted out of the low order bit are dropped. 


To shift a double precision number, the same shift constant is used for 
both parts of the number. On the first cycle, the upper half of the number 
is shifted using the HI option; on the following cycle, the lower half is 
shifted using the LO and OR options. 


* See Table 2.4 in Chapter 2. 

Status Generated: None affected. 

Instruction Format: 

Shift Immediate Operation, Instruction Type 15: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 

11 

10 9 8 

7 

6 5 4 3 2 1 0 

0 

0 

0 

0 

1 

1 

1 

1 

0 

SF 

Xop 

<exp> 


SF 

Shifter Function 


0000 

LSHIFT (HI) 

Xop: Shifter Operand 

0001 

LSHIFT (HI, OR) 

0010 

LSHIFT (LO) 

<exp>: 8-bit signed shift value 

0011 

LSHIFT (LO, OR) 




REGISTER MOVE 


Syntax: reg = reg ; 


Permissible registers 


AXO 

MXO 

SI 

SB 

CNTR 

AX1 

MX1 

SE 

PX 

OWRCNTRiwrite only ) 

AYO 

MYO 

SRI 

ASTAT 

RXO 

AY1 

MY1 

SRO 

MSTAT 

RX1 

AR 

MR2 

10-17 

SSTAT (read only ) 

TXO 


MR1 

M0-M7 

IMASK 

TX1 


MRO 

L0-L7 

ICNTL 

IF Ciwrite only ) 


Example: 1 7 = AR; 

Description: Move the contents of the source to the destination 
location. The contents of the source are always right-justified in the 
destination location after the move. 

When transferring a smaller register to a larger register (e.g., an 8-bit 
register to a 16-bit register), the value stored in the destination is either 
sign-extended to the left if the source is a signed value, or zero-filled to the 
left if the source is an unsigned value. The unsigned registers which 
(when used as the source) cause the value stored in the destination to be 
zero-filled to the left are: 10 through 17, L0 through L7, CNTR, PX, ASTAT, 
MSTAT, SSTAT, IMASK, and ICNTL. All other registers cause sign- 
extension to the left. 

When transferring a larger register to a smaller register (e.g., a 16-bit 
register to a 14-bit register), the value stored in the destination is right- 
justified (bit 0 maps to bit 0) and the higher-order bits are dropped. 

Note that whenever MR1 is loaded with data, it is sign-extended into 
MR2. 

Status Generated: None affected. 


(instruction continues on next page) 



REGISTER MOVE 


Instruction Format: 

Internal Data Move, Instruction Type 17: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 10 

9 8 

7 6 5 4 

3 2 10 

0 

0 

0 

0 

1 

1 

0 

1 

0 

0 

0 

0 

DST 

SRC 

DEST 

SOURCE 













RGP 

RGP 

REG 

REG 


SRC RGP (Source Register Group) and SOURCE REG (Source Register) 
select the source register according to the Register Selection Table (see 
Appendix A). 

DST RGP (Destination Register Group) and DEST REG (Destination 
Register) select the destination register according to the Register Selection 
Table (see Appendix A). 


15-64 




LOAD REGISTER IMMEDIATE 


Syntax: reg = <data> ; 

dreg = <data> ; 

data: <constant> 

'%' <symbol> 

' A ' <symbol> 

Permissible registers 


dregs ( Instruction Type 6) 

regs ( Instruction Type 7) 

( 16-bit load ) 


(maximum 14-bit load) 

AXO MXO 

SI 

SB 

CNTR 

AX1 MX1 

SE 

PX 

OWRCNTR (write only) 

AYO MYO 

SRI 

ASTAT 

RXO 

AY1 MY1 

SRO 

MSTAT 

RX1 

AR MR2 


IMASK 

TXO 

MR1 


ICNTL 

TX1 

MRO 


10-17 

M0-M7 

L0-L7 

IFC (write only ) 


Example: 10 = A data_buffer; 

LO=% datajbuffer; 

Description: Move the data value specified to the destination location. 
The data may be a constant, or any symbol referenced with the "length of" 
(%) or "pointer to" ( A ) operators. The data value is contained in the 
instruction word, with 16 bits for data register loads and up to 14 bits for 
other register loads. The value is always right-justified in the destination 
location after the load (bit 0 maps to bit 0). When a value of length less than 
the length of the destination is moved, it is sign-extended to the left to fill 
the destination width. 

Note that whenever MR1 is loaded with data, it is sign-extended into MR2. 

For this instruction only, the RX and TX registers may be loaded with a 
maximum of 14 bits of data (although the registers themselves are 16 bits 
wide). To load these registers with 16-bit data, use the register-to-register 
move instruction or the data memory-to-register move instruction with 
direct addressing. 

Status Generated : None affected. 


(instruction continues on next page) 



LOAD REGISTER IMMEDIATE 


Instruction Format : 

Load Data Register Immediate, Instruction Type 6: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 10 0 

DATA 

DREG 


DATA contains the immediate value to be loaded into the Data Register 
destination location. The data is right-justified in the field, so the value 
loaded into an N-bit destination register is contained in the lower-order N 
bits of the DATA field. 

DREG selects the destination Data Register for the immediate data value. 
One of the 16 Data Registers is selected according to the DREG Selection 
Table (see Appendix A). 


Load Non-Data Register Immediate Instruction Type 7: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 11 

RGP 

DATA 

REG 


DATA contains the immediate value to be loaded into the Non-Data 
Register destination location. The data is right-justified in the field, so the 
value loaded into an N-bit destination register is contained in the lower- 
order N bits of the DATA field. 

RGP (Register Group) and REG (Register) select the destination register 
according to the Register Selection Table (see Appendix A). 





DATA MEMORY READ (Direct Address) 


Syntax: reg = DM ( <addr> ) ; 


Permissible registers 


AXO 

MXO 

SI 

SB 

CNTR 

AX1 

MX1 

SE 

PX 

OWRCNTR ( write only) 

AYO 

MYO 

SRI 

ASTAT 

RXO 

AY1 

MY1 

SRO 

MSTAT 

RX1 

AR 

MR2 

10-17 


TXO 


MR1 

M0-M7 

IMASK 

TX1 


MRO 

L0-L7 

ICNTL 

IFCiwrite only ) 


Example: si = dm( ad_porto y 


Description: The Read instruction moves the contents of the data 
memory location to the destination register. The addressing mode is direct 
addressing (designated by an immediate address value or by a label). The 
data memory address is stored directly in the instruction word as a full 14- 
bit field. The contents of the source are always right-justified in the 
destination register after the read (bit 0 maps to bit 0). 


Note that whenever MR1 is loaded with data, it is sign-extended into 
MR2. 


Status Generated: None affected. 

Instruction Format: 

Data Memory Read (Direct Address), Instruction Type 3: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

10 0 0 

RGP 

ADDR 

REG 


ADDR contains the direct address to the source location in Data Memory. 

RGP (Register Group) and REG (Register) select the destination register 
according to the Register Selection Table (see Appendix A). 




DATA MEMORY READ (Indirect Address) 


Syntax: dreg = dm( 


Permissible dregs 

1 

AX0 

MX0 

SI 

AX1 

MX1 

SE 

AYO 

MY0 

SRI 

AY1 

MY1 

SR0 

AR 

MR2 



MR1 



MR0 




10 

t 

M0 



11 


Ml 



12 


M2 



13 


M3 



I4 


M4 



15 


M5 



16 


M6 



17 


M7 



Example: ayo = dm (13, mi); 

Description: The Data Memory Read Indirect instruction moves the 

contents of the data memory location to the destination register. The 
addressing mode is register indirect with post-modify. For linear (i.e. 
non-circular) indirect addressing, the L register corresponding to the I 
register used must be set to zero. The contents of the source are always 
right-justified in the destination register after the read (bit 0 maps to bit 0). 

Status Generated: None affected. 


Instruction Format: 

ALU / MAC Operation with Data Memory Read, Instruction Type 4: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 

9 

8 

7 6 5 4 

3 2 

1 0 

0 

1 

1 

G 

0 

0 

AMF 

0 

0 

0 

0 

0 

DREG 

I 

M 


AMF specifies the ALU or MAC operation to be performed in parallel 
with the Data Memory Read. In this case, AMF = 00000, indicating a no- 
operation for the ALU/MAC function. 

DREG selects the destination Data Register . One of the 16 Data Registers 
is selected according to the DREG Selection Table (see Appendix A). 

G specifies which Data Address Generator the I and M registers are 
selected from. These registers must be from the same DAG as separated 
by the gray bar above. I specifies the indirect address pointer (I register). 
M specifies the modify register (M register). 




PROGRAM MEMORY READ (Indirect Address) 


Syntax: 

dreg 

= PM ( 

14 

/ 

M4 


15 


M5 




16 


M6 




17 


M7 

Permissible 

dregs 




AX0 

MX0 

SI 



AX1 

MXI 

SE 



AY0 

MY0 

SRI 



AY1 

MY1 

SR0 



AR 

MR2 





MR1 





MR0 





Example: mxi = pm (I6, M5); 

Description: The Program Memory Read Indirect instruction moves the 
contents of the program memory location to the destination register. The 
addressing mode is register indirect with post-modify. For linear (i.e. 
non-circular) indirect addressing, the L register corresponding to the I 
register used must be set to zero. The 16 most significant bits of the 
Program Memory Data bus (PMD 23 _ 8 ) are loaded into the destination 
register, with bit PMD 8 lining up with bit 0 of the destination register 
(right-justification). If the destination register is less than 16 bits wide, the 
most significant bits are dropped. Bits PMD 7 . 0 are always loaded into the 
PX register. You may ignore these bits or read them out on a subsequent 
cycle. 

Status Generated : None affected 
Instruction Format: 

ALU / MAC Operation with Program Memory Read, Instruction Type 5: 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 

11 

10 

9 

8 

7 6 5 4 

3 2 

1 0 

0 

1 

0 

1 

0 

0 

AMF 

0 

0 

0 

0 

0 

DREG 

I 

M 


AMF specifies the ALU or MAC operation to be performed in parallel 
with the Data Memory Read. In this case, AMF = 00000, indicating a no- 
operation for the ALU /MAC function. 

DREG selects the destination Data Register. One of the 16 Data Registers is 
selected according to the Register Selection Table (see Appendix A). 

I specifies the indirect address pointer (I register). M specifies the modify 
register (M register). 




DATA MEMORY WRITE (Direct Address) 


Syntax: DM ( <addr> ) = reg ; 


Permissible registers 


AXO 

MXO 

SI 

SB 

CNTR 

AX1 

MX1 

SE 

PX 

RXO 

AYO 

MYO 

SRI 

ASTAT 

RX1 

AY1 

MY1 

SRO 

MSTAT 

TXO 

AR 

MR2 

10-17 

SSTAT {read only ) 

TX1 


MR1 

M0-M7 

IMASK 



MRO 

L0-L7 

ICNTL 



Example: DM ( cntljportO ) = AR; 

Description: Moves the contents of the source register to the data 
memory location specified in the instruction word. The addressing mode 
is direct addressing (designated by an immediate address value or by a 
label). The data memory address is stored directly in the instruction word 
as a full 14-bit field. Whenever a register less than 16 bits in length is 
written to memory, the value written is either sign-extended to the left if 
the source is a signed value, or zero-filled to the left if the source is an 
unsigned value. The unsigned registers which are zero-filled to the left 
are: 10 through 17, L0 through L7, CNTR, PX, ASTAT, MSTAT, SSTAT, 
IMASK, and ICNTL. All other registers are sign-extended to the left. 

The contents of the source are always right-justified in the destination 
location after the write (bit 0 maps to bit 0). 

Note that whenever MR1 is loaded with data, it is sign-extended into 
MR2. ? 

Status Generated: None affected. 

Instruction Format: 

Data Memory Read (Direct Address), Instruction Type 3: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

10 0 1 

RGP 

ADDR 

REG 


ADDR contains the direct address of the destination location in Data 
Memory. 

RGP (Register Group) and REG (Register) select the source register 
according to the Register Selection Table (see Appendix A). 




DATA MEMORY WRITE (Indirect Address) 


Syntax: 


DM ( 


10 

11 

12 
13 


14 

15 

16 
17 


MO 

Ml 

M2 

M3 


M4 

M5 

M6 

M7 


dreg 

<data> 


data: <constant> 

'%' <symbol> 
' A ' <symbol> 


Permissible dregs 


AXO 

MXO 

SI 

AX1 

MX1 

SE 

AYO 

MYO 

SRI 

AY1 

MY1 

SRO 

AR 

MR2 



MRI 



MRO 



Example: dm ( 12 , mo) = mri ; 

Description: The Data Memory Write Indirect instruction moves the 
contents of the source to the data memory location specified in the 
instruction word. The immediate data may be a constant or any symbol 
referenced with the "length of" (%) or "pointer to" ( A ) operators. 


The addressing mode is register indirect with post-modify. For linear (i.e. 
non-circular) indirect addressing, the L register corresponding to the I 
register used must be set to zero. When a register of less than 16 bits is 
written to memory, the value written is sign-extended to form a 16-bit 
value. The contents of the source are always right-justified in the 
destination location after the write (bit 0 maps to bit 0). 

Status Generated : None affected. 


(instruction continues on next page) 



DATA MEMORY WRITE (Indirect Address) 


Instruction Format: 

ALU / MAC Operation with Data Memory Write, Instruction Type 4: 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 

11 

10 

9 

8 

7 6 5 4 

3 2 

1 0 

0 

1 

1 

G 

d 

0 

AMF 

0 

0 

0 

0 


DREG 

I 

M 


Data Memory Write, Immediate Data, Instruction Type 2: 


23 

22 

21 

20 

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 

3 2 

1 0 

1 

0 

d 

G 

Data 

I 

M 


AMF specifies the ALU or MAC operation to be performed in parallel 
with the Data Memory Write. In this case, AMF = 00000, indicating a no- 
operation for the ALU / MAC function. 

Data represents the actual 16-bit value. 

DREG selects the source Data Register. One of the 16 Data Registers is 
selected according to the Register Selection Table (see Appendix A). 

G specifies which Data Address Generator the I and M registers are 
selected from. These registers must be from the same DAG as separated 
by the gray bar in the Syntax description above. I specifies the indirect 
address pointer (I register). M specifies the modify register (M register). 


15-72 





PROGRAM MEMORY WRITE (Indirect Address) 


Syntax: PM ( 14 , M4 ) = dreg ; 

15 M5 

16 M6 

17 M7 

Permissible dregs 
AXO MXO SI 

AX1 MX1 SE 

AYO MYO SRI 

AY1 MY1 SRO 

AR MR2 

MR1 
MRO 

Example: pm (16, M5) = ar ; 

Description: The Program Memory Write Indirect instruction moves 
the contents of the source to the program memory location specified in the 
instruction word. The addressing mode is register indirect with post- 
modify. For linear (i.e. non-circular) indirect addressing, the L register 
corresponding to the I register used must be set to zero. The 16 most 
significant bits of the Program Memory Data bus (PMD 23 . 8 ) are loaded 
from the source register, with bit PMD 8 aligned with bit 0 of the source 
register (right justification). The 8 least significant bits of the Program 
Memory Data bus (PMD 7 . 0 ) are loaded from the PX register. Whenever a 
source register of length less than 16 bits is written to memory, the value 
written is sign-extended to form a 16-bit value. 

Status Generated: None affected. 


Instruction Format: 

ALU / MAC Operation with Program Memory Write, Instruction Type 5 
(see Appendix A), as shown below: 



AMF specifies the ALU or MAC operation to be performed in parallel 
with the Program Memory Write. In this case, AMF = 00000, indicating a 
no-operation for the ALU / MAC function. 


DREG selects the source Data Register. One of the 16 Data Registers is 
selected according to the Register Selection Table (see Appendix A). 


I specifies the indirect address pointer (I register). M specifies the modify 
register (M register). 


15-73 




I/O SPACE READ/WRITE 

(ADSP-218x only) 


Syntax: IO (<addr>) = dreg ; I/O write 

dreg = IO (<addr>) ; I/O read 

<addr> is an 11 -bit direct address value between 0 and 2047 


Permissible dregs 


AXO 

MXO 

SI 

AX1 

MX1 

SE 

AYO 

MYO 

SRI 

AY1 

MYl 

SRO 

AR 

MR2 



MR1 



MRO 



Examples: 10(23) = axo; 

MYl = 10(2047); 

Description: The 1/ O space read and write instructions are used to 

access the ADSP-218x's I/O memory space. These instructions move data 
between the processor data registers and the I/O memory space. 


Status Generated: None affected. 


Instruction Format: 

1/ O Memory Space Read/Write, Instruction Type 29: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 

12 11 10 9 8 7 6 5 4 

3 2 10 

0 

0 

0 

0 

0 

0 

0 

1 

D 

ADDR 

DREG 


ADDR contains the 11 -bit direct address of the source or destination 
location in I/O Memory Space. 

DREG selects the Data Register. One of the 16 Data Registers is selected 
according to the Register Selection Table (see Appendix A). 

D specifies the direction of the transfer (0=read, 1= write). 




JUMP 


Syntax: [ if cond ] jump (14) 

(15) 

(16) 

(17) 

<addr> 

Permissible conds (see Table 15.9) 


EQ 

NE 

GT 

GE 

LT 

LE 

NEG 

POS 

AV 

NOTAV 

AC 

NOT AC 

MV 

NOT MV 

NOT CE 


Example: IF NOT CE JUMP topjoop ; {CNTR is decremented} 

Description: Test the optional condition and, if true, perform the 
specified jump. If the condition is not true then perform a no-operation. 
Omitting the condition performs the jump unconditionally. The JUMP 
instruction causes program execution to continue at the effective address 
specified by the instruction. The addressing mode may be direct or 
register indirect. 

For direct addressing (using an immediate address value or a label), the 
program address is stored directly in the instruction word as a full 14-bit 
field. For register indirect jumps, the selected I register provides the 
address; it is not post-modified in this case. 

If JUMP is the last instruction inside a DO UNTIL loop, you must ensure 
that the loop stacks are properly handled. If NOT CE is used as the 
condition, execution of the JUMP instruction decrements the processor's 
counter (CNTR register). 

Status Generated: None affected. 


Instruction Field: 

Conditional JUMP Direct Instruction Type 10: 


23 

22 

21 

20 

19 

18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 

0 

0 

1 

1 

0 ADDR COND 


Conditional JUMP Indirect Instruction Type 19: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 7 6 

5 

4 3 2 1 0 

0 

0 

0 

0 

1 

0 

1 

1 

0 

0 

0 

0 

0 

0 

0 

0 I 

0 

0 COND 


I specifies the I register (Indirect Address Pointer). 


ADDR: immediate jump address COND: condition 

15-75 





CALL 


Syntax: 


[ IF cond ] CALL 


(14) 

(15) 

(16) 

(17) 

<addr> 


Permissible conds (see Table 15.9) 


EQ 

NE 

GT 

GE 

LT 

LE 

NEG 

POS 

AV 

NOTAV 

AC 

NOT AC 

MV 

NOT MV 

NOT CE 


Example: IF AV CALL scale_down ; 

Description: Test the optional condition and, if true, then perform the 
specified call. If the condition is not true then perform a no-operation. 
Omitting the condition performs the call unconditionally. The CALL 
instruction is intended for calling subroutines. CALL pushes the PC stack 
with the return address and causes program execution to continue at the 
effective address specified by the instruction. The addressing modes 
available for the CALL instruction are direct or register indirect. 

For direct addressing (using an immediate address value or a label), the 
program address is stored directly in the instruction word as a full 14-bit 
field. For register indirect jumps, the selected I register provides the 
address; it is not post-modified in this case. 

If CALL is the last instruction inside a DO UNTIL loop, you must ensure 
that the loop stacks are properly handled. 

Status Generated: None affected. 


Instruction Field: 

Conditional JUMP Direct Instruction Type 10: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 0 1 1 1 

ADDR 

COND 


Conditional JUMP Indirect Instruction Type 19: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

_il 

Li 

1 

0 

0 

0 

0 

0 

0 

0 

0 

I 

ii 

1 

COND 


I specifies the I register (Indirect Address Pointer). 

ADDR: immediate jump address COND: condition 





JUMP or CALL ON FLAG IN PIN 


Syntax: 


IF 

FLAG IN 


JUMP 


<addr> 


NOT FLAG JN 


CALL 




Example: IF FLAG_IN JUMP service _proc_three; 

Description: Test the condition of the FI pin of the processor and, if set 
to one, perform the specified jump or call. If FI is zero then perform a no- 
operation. Omitting the flag in condition reduces the instruction to a 
standard JUMP or CALL. 

The JUMP instruction causes program execution to continue at the 
address specified by the instruction. The addressing mode for the JUMP 
on FI must be direct. 

The CALL instruction is intended for calling subroutines. CALL pushes 
the PC stack with the return address and causes program execution to 
continue at the address specified by the instruction. The addressing mode 
for the CALL on FI must be direct. 

If JUMP or CALL is the last instruction inside a DO UNTIL loop, you 
must ensure that the loop stacks are properly handled. 

For direct addressing (using an immediate address value or a label), the 
program address is stored directly in the instruction word as a full 14-bit 
field. 

Status Generated: None affected. 


Instruction Field: 

Conditional JUMP or CALL on Flag In Direct Instruction Type 27: 


23 

22 

21 

20 

19 

18 

17 

16 

15 14 

13 12 11 10 9 

8 7 6 5 4 

3 2 

1 

0 

0 

0 

0 

0 

0 

0 

1 

1 

Address 

\ 

Addr 

% 

FIC 

E 


^ A 


12 LSBs 2 MSBs 


S: specifies JUMP (0) or CALL (1) 


FIC: latched state of FI pin 




MODIFY FLAG OUT PIN 


Syntax: [IFcond] SET FLAG_OUT [,...]; 

RESET FLO 

TOGGLE FL1 

FL2 

Example: if mv set flagjdut, reset fli ; 

Description: Evaluate the optional condition and if true, set to one, reset to 

zero, or toggle the state of the specified flag output pin(s). Otherwise perform a 
no-operation and continue with the next instruction. Omitting the condition 
performs the operation unconditionally. Multiple flags may be modified by 
including multiple clauses, separated by commas, in a single instruction. This 
instruction does not directly alter the flow of your program — it is provided to 
signal external devices. 

(Note that the FO pin is specified by ''FLAG_OUT" in the instruction syntax.) 

The following table shows which flag outputs are present on each 
ADSP-21xx processor: 

processor flag pin(s) 

ADSP-2101 FO 
ADSP-2105 FO 
ADSP-2115 FO 
ADSP-21 1 1 FO, FLO, FL1, FL2 
ADSP-217x FO, FLO, FL1, FL2 
ADSP-21 8x FO, FLO, FL1, FL2 
ADSP-21 msp5x FO, FLO, FL1, FL2 

Status Generated: None affected. 


Instruction Field: 

Flag Out Mode Control Instruction Type 28: 



FL2 FL1 FLO FLAG_OUT 


FO: Operation to perform COND: Condition code 

on flag output pin 


15-78 




RTS 


Syntax: [ if cond ] rts ; 

Permissible conds (see Table 15.9) 

EQ NE GT GE LT 

LE NEG POS AV NOT AV 

AC NOT AC MV NOT MV NOT CE 

Example: if le rts ; 

Description: Test the optional condition and, if true, then perform the 
specified return. If the condition is not true then perform a no-operation. 
Omitting the condition performs the return unconditionally. RTS executes 
a program return from a subroutine. The address on top of the PC stack is 
popped and is used as the return address. The PC stack is the only stack 
popped. 

If RTS is the last instruction inside a DO UNTIL loop, you must ensure 
that the loop stacks are properly handled. 

Status Generated: None affected. 


Instruction Field: 

Conditional Return, Instruction Type 20: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 3 2 1 0 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 COND 


COND: condition 


15-79 




RTI 


Syntax: [ if cond ] rti ; 

Permissible conds ( see Table 15.9) 


EQ 

NE 

GT 

GE 

LT 

LE 

NEG 

POS 

AV 

NOTAV 

AC 

NOT AC 

MV 

NOT MV 

NOT CE 


Example: if mv rti ; 

Description: Test the optional condition and, if true, then perform the 
specified return. If the condition is not true then perform a no-operation. 
Omitting the condition performs the return unconditionally. RTI executes 
a program return from an interrupt service routine. The address on top of 
the PC stack is popped and is used as the return address. The value on top 
of the status stack is also popped, and is loaded into the arithmetic status 
(ASTAT), mode status (MSTAT) and the interrupt mask (IMASK) 
registers. 

If RTI is the last instruction inside a DO UNTIL loop, you must ensure 
that the loop stacks are properly handled. 

Status Generated : None affected. 


Instruction Field: 

Conditional Return, Instruction Type 20: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 3 2 1 0 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1 COND 


COND: condition 


15-80 




DO UNTIL 


Syntax: DO <addr> [UNTIL term] ; 

Permissible terms 


EQ 

NE 

GT 

GE 

LT 

FOREVER 

LE 

NEG 

POS 

AV 

NOTAV 


AC 

NOT AC 

MV 

NOT MV 

CE 



Example: DO loopjabel UNTIL CE ; [CNTR is decremented 

each pass through loop} 


Description: DO UNTIL sets up looping circuitry for zero-overhead 
looping. The program loop begins at the program instruction immediately 
following the DO instruction, ends at the address designated in the 
instruction and repeats execution until the specified termination condition is 
met (if one is specified) or repeats in an infinite loop (if none is specified). The 
termination condition is tested during execution of the last instruction in the 
loop, the status having been generated upon completion of the previous 
instruction. The address (<addr>) of the last instruction in the loop is stored 
directly in the instruction word. 

If CE is used for the termination condition, the processor's counter (CNTR 
register) is decremented once for each pass through the loop. 

When the DO instruction is executed, the address of the last instruction is 
pushed onto the loop stack along with the termination condition and the 
current program counter value plus 1 is pushed onto the PC stack. 

Any nesting of DO loops continues the process of pushing the loop and PC 
stacks, up to the limit of the loop stack size (4 levels of loop nesting) or of the 
PC stack size (16 levels for subroutines plus interrupts plus loops). With 
either or both the loop or PC stacks full, a further attempt to perform the DO 
instruction will set the appropriate stack overflow bit and will perform a no- 
operation. 

Status Generated: 

AST AT: Not affected. 

SSTAT: 7 6 5 4 3 2 1 0 

LSO LSE SSO SSE CSO CSE PSO PSE 
* 0 * 0 

LSO Loop Stack Overflow: set if the loop stack overflows; otherwise not affected. 
LSE Loop Stack Empty: always cleared (indicating loop stack not empty) 

PSO PC Stack Overflow: set if the PC stack overflows; otherwise not affected. 

PSE PC Stack Empty: always cleared (indicating PC stack not empty) 

(instruction continues on next page) 



DO UNTIL 


Instruction Format: 

Do Until, Instruction Type 11: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 0 1 0 1 

Addr 

TERM 


ADDR specifies the address of the last instruction in the loop. In the 
Instruction Syntax, this field may be a program label or an immediate address 
value. 

TERM specifies the termination condition, as shown below: 


TERM 

Syntax 

Condition Tested 

0000 

NE 

Not Equal to Zero 

0001 

EQ 

Equal Zero 

0010 

LE 

Less Than or Equal to Zero 

0011 

GT 

Greater Than Zero 

0100 

GE 

Greater Than or Equal to Zero 

0101 

LT 

Less Than Zero 

0110 

NOTAV 

Not ALU Overflow 

0111 

AV 

ALU Overflow 

1000 

NOT AC 

Not ALU Carry 

1001 

AC 

ALU Carry 

1010 

POS 

X Input Sign Positive 

1011 

NEG 

X Input Sign Negative 

1100 

NOT MV 

Not MAC Overflow 

1101 

MV 

MAC Overflow 

1110 

CE 

Counter Expired 

mi 

FOREVER 

Always 


15-82 




IDLE 


Syntax: idle ; 

IDLE (n); Slow Idle 

Description: IDLE causes the processor to wait indefinitely in a low-power 

state, waiting for interrupts. When an interrupt occurs it is serviced and execution 
continues with the instruction following IDLE. Typically this next instruction will 
be a JUMP back to IDLE, implementing a low-power standby loop. (Note the 
restrictions on JUMP or IDLE as the last instruction in a DO UNTIL loop, detailed 
in Chapter 3.) 

IDLE (n) is a special version of IDLE that slows the processor's internal clock signal 
to further reduce power consumption. The reduced clock frequency, a 
programmable fraction of the normal dock rate, is specified by a selectable divisor 
n given in the instruction: n = 16, 32, 64, or 128. The instruction leaves the processor 
fully functional, but operating at the slower rate during execution of the IDLE (n) 
instruction. While it is in this state, the processor's other internal dock signals (such 
as SCLK, CLKOUT, and the timer dock) are reduced by the same ratio. 

When the IDLE (n) instruction is used, it slows the processor's internal dock and 
thus its response time to incoming interrupts— the 1-cyde response time of the 
standard IDLE state is increased by n, the clock divisor. When an enabled interrupt 
is received, the ADSP-21xx will remain in the IDLE state for up to a maximum of n 
CLKIN cycles (where n =16, 32, 64, or 128) before resuming normal operation. 

When the IDLE (n) instruction is used in systems that have an externally generated 
serial clock, the serial dock rate may be faster than the processor's reduced internal 
dock rate. Under these conditions, interrupts must not be generated at a faster rate 
than can be serviced, due to the additional time the processor takes to come out of 
the IDLE state (a maximum of n CLKIN cycles). 

Serial port autobuffering continues during IDLE without affecting the idle state. 

Status Generated: None affected. 


Instruction Field: 

Idle, Instruction Type 31: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 1 

0 

0 

0 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 0 

0 

Slow Idle, 

Instruction Type 

31: 















23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 1 

oj 

0 

0 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1 

DV 


. DV: Clock divisor 


15-83 





STACK CONTROL 


Syntax: 


[PUSH 

POP 


STS] 


[ , POP CNTR] [,POPPC] [, POP LOOP]; 


Example: pop cntr, pop pc, pop loop; 

Description: Stack Control pushes or pops the designated stack(s). The entire 
instruction executes in one cycle regardless of how many stacks are specified. 


The PUSH STS (Push Status Stack) instruction increments the status stack pointer by 
one to point to the next available status stack location; and pushes the arithmetic 
status (ASTAT), mode status (MSTAT), and interrupt mask register (IMASK) onto 
the processor's status stack. Note that the PUSH STS operation is executed 
automatically whenever an interrupt service routine is entered. 


Any POP pops the value on the top of the designated stack and decrements the same 
stack pointer to point to the next lowest location in the stack. POP STS causes the 
arithmetic status (ASTAT), mode status (MSTAT), and interrupt mask (IMASK) to be 
popped into these same registers. This also happens automatically whenever a 
return from interrupt (RTI) is executed. 

POP CNTR causes the counter stack to be popped into the down counter. When the 
loop stack or PC stack is popped (with POP LOOP or POP PC, respectively), the 
information is lost. Returning from an interrupt (RTI) or subroutine (RTS) also pops 
the PC stack automatically. 

Status Generated: 

SSTAT: 7 6 5 4 3 2 1 0 

LSO LSE SSO SSE CSO CSE PSO PSE 


PSE PC Stack Empty: set if a pop results in an empty program counter stack; cleared otherwise. 

CSE Counter Stack Empty: set if a pop results in an empty counter stack; cleared otherwise. 

SSE Status Stack Empty: for PUSH STS, this bit is always cleared (indicating status stack not empty). 

For POP STS, SSE is set if the pop results in an empty status stack; cleared otherwise. 

SSO Status Stack Overflow: for PUSH STS set if the status stack overflows; otherwise not affected. 

LSE Loop Stack Empty: set if a pop results in an empty loop stack; cleared otherwise. 

Note that once any Stack Overflow occurs, the corresponding stack overflow bit is 
set in SSTAT, and this bit stays set indicating there has been loss of information. 

Once set, the stack overflow bit can only be cleared by resetting the processor. 


Instruction Format: 

Stack Control, Instruction Type 26: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

Pp 

Lp 

Cp 

Spp 


Pp: PC Stack Control Lp: Loop Stack Control 

15 “ 84 Cp: Counter Stack Control Spp: Status Stack Control 




STACK CONTROL 


TOPPCSTACK 

A special version of the Register-to-Register Move instruction. Type 17, is provided 
for reading (and popping) or writing (and pushing) the top value of the PC stack. The 
normal POP PC instruction does not save the value popped from the stack, so to save 
this value into a register you must use the following special instruction: 

reg = TOPPCSTACK; (pop PC stack into reg} 

{ "toppcstack" may also be lowercase} 

The PC stack is also popped by this instruction, after a one-cycle delay. A NOP should 
usually be placed after the special instruction, to allow the pop to occur properly: 

reg = TOPPCSTACK; 

NOP; (allow pop to occur correctly} 

There is no standard PUSH PC stack instruction. To push a specific value onto the PC 
stack, therefore, use the following special instruction: 

TOPPCSTACK= reg; (push reg contents onto PC stack} 

The stack is pushed immediately, in the same cycle. 

Note that "TOPPCSTACK" may not be used as a register in any other instruction type! 


Examples: 

AXO = TOPPCSTACK; (pop PC stack into AXO} 

NOP; 

TOPPCSTACK = 17 ; (push contents of 17 onto PC stack} 


Only the following registers may be used in the special TOPPCSTACK instructions: 


ALU, MAC, & Shifter Registers DAG Registers 


AXO 

AR 

SI 

10 

14 

MO 

M4 

L0 

L4 

AX1 

MRO 

SE 

11 

15 

Ml 

M5 

LI 

L5 

MXO 

MR1 

SRO 

12 

16 

M2 

M6 

L2 

L6 

MX1 

MR 

SRI 

13 

17 

M3 

M7 

L3 

L7 


AYO 

AY1 

MYO 

MY1 

There are several restrictions on the use of the special TOPPCSTACK instructions; 
they are described in Chapter 3, Program Control. 

(instruction continues on next page) 15 — 85 



STACK CONTROL 


Instruction Format: 

TOPPCSTACK=reg 

Internal Data Move, Instruction Type 17: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

1 

0 

1 

0 

0 

0 

0 

1 

1 

SRC 

RGP 

1 

1 

1 

1 

_ 

SOURCE 

REG 


SRC RGP (Source Register Group) and SOURCE REG (Source Register) select the source 
register according to the Register Selection Table (see Appendix A). 


reg=TOPPCSTACK 

Internal Data Move, Instruction Type 17: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


o 

o 

o 

o 

f— 1 

f— 1 

o 

M 

o 

o 

o 

o 

DST 

1 1 

DEST 

1111 


RGP 


REG 



DST RGP (Destination Register Group) and DEST REG (Destination Register) select the 
destination register according to the Register Selection Table (see Appendix A). 





MODE CONTROL 


BIT_REV [,...] ; 

AVJLATCH 
AR_SAT 
SEC_REG 
G_MODE 
M_MODE 
TIMER 

Example: dis ar_sat, ena m_mode; 

Description: Enables (ENA) or disables (DIS) the designated processor 
mode. The corresponding mode status bit in the mode status register 
(MSTAT) is set for ENA mode and cleared for DIS mode. At reset, MSTAT 
is set to zero, meaning that all modes are disabled. Any number of modes 
can be changed in one cycle with this instruction. Multiple ENA or DIS 
clauses must be separated by commas. 

MSTAT Bits: 


Syntax: 


ENA 

DIS 


0 SECJREG 

1 BIT_REV 

2 AV_LATCH 

3 AR_SAT 

4 MJMODE 

5 TIMER 

6 G_MODE 


Alternate Register Data Bank 
Bit-Reverse Mode on Address Generator #1 
ALU Overflow Status Latch Mode 
ALU AR Register Saturation Mode 
MAC Result Placement Mode 
Timer Enable 
Enables GO Mode 


The data register bank select bit (SEC_REG) determines which set of data 
registers is currently active (0=primary, l=secondary). 

The bit-reverse mode bit (BIT_REV), when set to 1, causes addresses 
generated by Data Address Generator #1 to be output in bit reversed 
order. 

The ALU overflow latch mode bit (AV_LATCH), when set to 1, causes the 
AV bit in the arithmetic status register to stay set once an ALU overflow 
occurs. In this mode, if an ALU overflow occurs, the AV bit will be set and 
will remain set even if subsequent ALU operations do not generate 
overflows. The AV bit can only be cleared by writing a zero into it directly 
over the DMD bus. 


(instruction continues on next page) 



MODE CONTROL 


The AR saturation mode bit, (AR_SAT), when set to 1, causes the AR 
register to saturate if an ALU operation causes an overflow, as described 
in Chapter 2, "Computation Units." 

The MAC result placement mode (M_MODE) determines whether or not 
the left shift is made between the multiplier product and the MR register. 

Setting the Timer Enable bit (TIMER) starts the timer decrementing logic. 
Clearing it halts the timer. 

The GO mode (G_MODE) allows an ADSP-21xx processor to continue 
executing instructions from internal memory (if possible) during a bus 
grant. The GO mode allows the processor to run; only if an external 
memory access is required does the processor halt, waiting for the bus to 
be released. 


Instruction Format: 

Mode Control, Instruction Type 18: 


23 

22 

21 

20 

19 

18 

17 

16 

15 14 

13 12 

11 10 

9 8 

7 6 

5 4 

3 2 

1 

0 

0 

0 

0 

0 

1 

1 

0 


TI 

MM 

AS 

OL 

br! 

SR 

GM 

Gl 

0 


TI: 

Timer Enable 

MM: 

Multiplier Placement 

AS: 

AR Saturation Mode Control 

OL: 

ALU Overflow Latch Mode 

BR: 

Bit Reverse Mode Control 


Control 

GM: 

GO Mode 

SR: 

Secondary Register Bank 
Mode 


15-88 




MODIFY ADDRESS REGISTER 


Syntax: modify 


10 

/ 

MO 

11 


Ml 

12 


M2 

13 


M3 

14 


M4 

15 


M5 

16 


M6 

17 


M7 


Example: modify (ii. Mi); 

Description: Add the selected M register (M n ) to the selected I register 
(I m ), then process the modified address through the modulus logic with 
buffer length as determined by the L register corresponding to the 
selected I register (L m ), and store the resulting address pointer calculation 
in the selected I register. The I register is modified as if an indexed 
memory address were taking place, but no actual memory data transfer 
occurs. For linear (i.e. non-circular) indirect addressing, the L register 
corresponding to the I register used must be set to zero. 


The selection of the I and M registers is constrained to registers within the 
same Data Address Generator: selection of 10-13 in Data Address 
Generator #1 constrains selection of the M registers to M0-M3. Similarly, 
selection of 14-17 constrains the M registers to M4-M7. 

Status Generated: None affected. 


instruction Format: 

Modify Address Register, Instruction Type 21: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 

1 0 

0 

0 

0 

0 

1 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

3 

0 

I 

M 


G specifies which Data Address Generator is selected. The I and M 
registers specified must be from the same DAG, separated by the gray bar 
above. I specifies the I register (depends on which DAG is selected by the 
G bit). M specifies the M register (depends on which DAG is selected by 
the G bit). 




NOP 


Syntax: nop ; 

Description: No operation occurs for one cycle. Execution continues 
with the instruction following the NOP instruction. 

Status Generated: None affected. 


Instruction Format: 

No operation. Instruction Type 30 (see Appendix A), as shown below: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 


15-90 




INTERRUPT ENABLE & DISABLE 

(ADSP-217X, ADSP-218X, ADSP-21 msp58/59 only) 


Syntax: ena ints ; 

DIS INTS ; 


Description: Interrupts are enabled by default at reset. Executing the 
DIS INTS instruction causes all interrupts (including the powerdown 
interrupt) to be masked, without changing the contents of the IMASK 
register. 

Executing the ENA INTS instruction allows all unmasked interrupts to be 
serviced again. 

Note: Disabling interrupts does not affect serial port autobuffering or 
ADSP-21 8x DMA transfers (IDMA or BDMA). These operations will 
continue normally whether or not interrupts are enabled. 


Status Generated: None affected. 


Instruction Format: 

DIS INTS, Instruction Type 26: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 


ENA INTS, Instruction Type 26: 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

0 

0 

0 

0 

0 





COMPUTATION with MEMORY READ 


DM ( 10 , MO ) 

11 Ml 

12 M2 

13 M3 

14 M4 

15 M5 

16 M6 

17 M7 

PM ( 14 , M4 ) 

15 M5 

16 M6 

17 M7 

Permissible dregs 
AXO MXO SI 

AX1 MX1 SE 

AYO MYO SRO 

AY1 MY1 SRI 

AR MRO 

MR1 
MR2 

Description: Perform the designated arithmetic operation and data 
transfer. The read operation moves the contents of the source to the 
destination register. The addressing mode when combining an arithmetic 
operation with a memory read is register indirect with post-modify. For 
linear (i.e. non-circular) indirect addressing, the L register 
corresponding to the I register used must be set to zero. The contents of 
the source are always right-justified in the destination register. 

The computation must be unconditional. All ALU, MAC and Shifter 
operations are permitted except Shift Immediate and ALU DIVS and 
DIVQ instructions. 

The fundamental principle governing multifunction instructions is that 
registers (and memory) are read at the beginning of the processor cycle 
and written at the end of the cycle. The normal left-to-right order of 
clauses (computation first, memory read second) is intended to imply this. 
In fact, you may code this instruction with the order of clauses reversed. 
The assembler produces a warning, but the results are identical at the 
opcode level. If you turn off semantics checking in the assembler (using 
the -s switch) the warning is not issued. 



Syntax: <alu> , dreg = 

<MAC> 

<SHIFT> 


15-92 



COMPUTATION with MEMORY READ 


Because of the read-first, write-second characteristic of the processor, 
using the same register as source in one clause and a destination in the 
other is legal. The register supplies the value present at the beginning of 
the cycle and is written with the new value at the end of the cycle. 

For example, 

(1) AR = AXO + AYO, AXO = DM (10, MO); 

is a legal version of this multifunction instruction and is not flagged by the 
assembler. Reversing the order of clauses, as in 

(2) AXO = DM (10, MO) , AR = AXO + AYO; 

results in an assembler warning, but assembles and executes exactly as the 
first form of the instruction. Note that reading example (2) from left to 
right may suggest that the data memory value is loaded into AXO and 
then used in the computation, all in the same cycle. In fact, this is not 
possible. The left-to-right logic of example (1) suggests the operation of 
the instruction more closely. Regardless of the apparent logic of reading 
the instruction from left to right, the read-first, write-second operation of 
the processor determines what actually happens. 

Using the same register as a destination in both clauses, however, 
produces an indeterminate result and should not be done. The assembler 
issues a warning unless semantics checking is turned off. Regardless of 
whether or not the warning is produced, however, this practice is not 
supported. 

The following, therefore, is illegal and not supported, even though 
assembler semantics checking produces only a warning: 

(3) AR = AXO + AYO, AR = DM (10, MO); Illegal! 


(instruction continues on next page) 



COMPUTATION with MEMORY READ 


Status Generated: All status bits are affected in the same way as for the 
single function versions of the selected arithmetic operation. 

<ALU> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 

___***** 

Set if result equals zero. Cleared otherwise. 

Set if result is negative. Cleared otherwise. 

Set if an overflow is generated. Cleared otherwise. 

Set if a carry is generated. Cleared otherwise. 

Affected only when executing the Absolute Value operation 
(ABS). Set if the source operand is negative. 

<MAC> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set if the accumulated product overflows the lower-order 32 

bits of the MR register. Cleared otherwise. 

<SHIFT> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


SS Affected only when executing the EXP operation; set if the 

source operand is negative. Cleared if the number is 
positive. 


AZ 

AN 

AV 

AC 

AS 


15-94 



COMPUTATION with MEMORY READ 


Instruction Format: 

ALU/MAC operation with Data Memory Read, Instruction Type 4: 



Shift operation with Data Memory Read, Instruction Type 12: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 0 1 0 0 1 

H 

0 

SF 

Xop 

Dreg 

I 

M 


Shift operation with Program Memory Read, Instruction Type 13: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

000100010 

SF 

Xop 

Dreg 

I 

M 


Z: 

Result register 

Dreg: 

Destination register 

SF: 

Shifter operation 

AMF: 

ALU/MAC operation 

Yop: 

Y operand 

Xop: 

X operand 

G: 

Data Address Generator 

I: 

Indirect address 

M: 

Modify register 


register 







COMPUTATION with REGISTER to REGISTER MOVE 


Syntax: 


<ALU> 

<MAC> 

<SHIFT> 


, dreg = dreg ; 


Permissible dregs 
AXO MXO 

AX1 MX1 

AYO MYO 

AY1 MY1 

AR MRO 

MR1 
MR2 


SI 

SE 

SRO 

SRI 


Description: Perform the designated arithmetic operation and data 
transfer. The contents of the source are always right-justified in the 
destination register after the read. 

The computation must be unconditional. All ALU, MAC and Shifter 
operations are permitted except Shift Immediate and ALU DIVS and 
DIVQ instructions. 

The fundamental principle governing multifunction instructions is that 
registers (and memory) are read at the beginning of the processor cycle 
and written at the end of the cycle. The normal left-to-right order of 
clauses (computation first, register transfer second) is intended to imply 
this. In fact, you may code this instruction with the order of clauses 
reversed. The assembler produces a warning, but the results are identical 
at the opcode level. If you turn off semantics checking in the assembler (-s 
switch) the warning is not issued. 

Because of the read-first, write-second characteristic of the processor, 
using the same register as source in one clause and a destination in the 
other is legal. The register supplies the value present at the beginning of 
the cycle and is written with the new value at the end of the cycle. 

For example, 

(1) AR = AXO + AYO, AXO = MR1; 

is a legal version of this multifunction instruction and is not flagged by the 
assembler. Reversing the order of clauses, as in 


(2) AXO = MR1, AR = AXO + AYO; 



COMPUTATION with REGISTER to REGISTER MOVE 


results in an assembler warning, but assembles and executes exactly as the 
first form of the instruction. Note that reading example (2) from left to 
right may suggest that the MR1 register value is loaded into AXO and then 
AXO is used in the computation, all in the same cycle. In fact, this is not 
possible. The left-to-right logic of example (1) suggests the operation of 
the instruction more closely. Regardless of the apparent logic of reading 
the instruction from left to right, the read-first, write-second operation of 
the processor determines what actually happens. 

Using the same register as a destination in both clauses, however, 
produces an indeterminate result and should not be done. The assembler 
issues a warning unless semantics checking is turned off. Regardless of 
whether or not the warning is produced, however, this practice is not 
supported. 

The following, therefore, is illegal and not supported, even though 
assembler semantics checking produces only a warning: 

(3) AR = AXO + AYO, AR = MR1 ; Illegal! 

Status Generated: All status bits are affected in the same way as for the 
single function versions of the selected arithmetic operation. 

<ALU> operation 

ASTAT: 7654321 0 

SS MV AQ AS AC AV AN AZ 
* * * * * 

AZ Set if result equals zero. Cleared otherwise. 

AN Set if result is negative. Cleared otherwise. 

AV Set if an overflow is generated. Cleared otherwise. 

AC Set if a carry is generated. Cleared otherwise. 

AS Affected only when executing the Absolute Value operation 

(ABS). Set if the source operand is negative. 


(instruction continues on next page) 



COMPUTATION with REGISTER to REGISTER MOVE 


<MAC> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set if the accumulated product overflows the lower-order 32 

bits of the MR register. Cleared otherwise. 

<SHIFT> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


SS Affected only when executing the EXP operation; set if the 

source operand is negative. Cleared if the number is 
positive. 


Instruction Format: 

ALU/MAC operation with Data Register Move, Instruction Type 8: 


23 22 21 20 19 18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 10 

0 0 1 0 1 Z 

AMF 

Yop 

Xop 

Dreg 

dest 

Dreg 

source 


Shift operation with Data Register Move, Instruction Type 14: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 0 1 0 0 

0 0 0 

SF 

Xop 

Dreg 

dest 

Dreg 

source 


Z: 

Result register 

Dreg: 

Data register 

SF: 

Shifter operation 

AMF: 

ALU/MAC operation 

Yop: 

Y operand 

Xop: 

X operand 





COMPUTATION with MEMORY WRITE 


Syntax: 


DM ( 


10 

/ 

MO 


) 



11 


Ml 





12 


M2 





13 


M3 





14 


M4 





15 


M5 





16 


M6 





17 


M7 



PM ( 


14 

/ 

M4 


) 



15 


M5 





16 


M6 





17 


M7 




= dreg , 


<ALU> 

<MAC> 

<SHIFT> 


Permissible dregs 
AXO MXO SI 

AX1 MX1 SE 

AYO MYO SRO 

AY1 MY1 SRI 

AR MRO 

MR1 
MR2 


Description: Perform the designated arithmetic operation and data 
transfer. The write operation moves the contents of the source to the 
specified memory location. The addressing mode when combining an 
arithmetic operation with a memory write is register indirect with post- 
modify. For linear (i.e. non-circular) indirect addressing, the L register 
corresponding to the I register used must be set to zero. The contents of 
the source are always right-justified in the destination register. 

The computation must be unconditional. All ALU, MAC and Shifter 
operations are permitted except Shift Immediate and ALU DIVS and 
DIVQ instructions. 

The fundamental principle governing multifunction instructions is that 
registers (and memory) are read at the beginning of the processor cycle 
and written at the end of the cycle. The normal left-to-right order of 
clauses (memory write first, computation second) is intended to imply 
this. In fact, you may code this instruction with the order of clauses 
reversed. The assembler produces a warning, but the results are identical 
at the opcode level. If you turn off semantics checking in the assembler (-s 

switch) the warning is not issued. „ ^ „ . 

° (instruction continues on next page) 



COMPUTATION with MEMORY WRITE 


Because of the read-first, write-second characteristic of the processor, 
using the same register as destination in one clause and a source in the 
other is legal. The register supplies the value present at the beginning of 
the cycle and is written with the new value at the end of the cycle. 

For example, 

(1) DM (10, MO) = AR, AR = AXO + AYO; 

is a legal version of this multifunction instruction and is not flagged by the 
assembler. Reversing the order of clauses, as in 

(2) AR = AXO + AYO, DM (10, MO) = AR; 

results in an assembler warning, but assembles and executes exactly as the 
first form of the instruction. Note that reading example (2) from left to 
right may suggest that the result of the computation in AR is then written 
to memory, all in the same cycle. In fact, this is not possible. The left-to- 
right logic of example (1) suggests the operation of the instruction more 
closely. Regardless of the apparent logic of reading the instruction from 
left to right, the read-first, write-second operation of the processor 
determines what actually happens. 

Status Generated: All status bits are affected in the same way as for the 
single function versions of the selected arithmetic operation. 

<ALU> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


Set if result equals zero. Cleared otherwise. 

Set if result is negative. Cleared otherwise. 

Set if an overflow is generated. Cleared otherwise. 

Set if a carry is generated. Cleared otherwise. 

Affected only when executing the Absolute Value operation 
(ABS). Set if the source operand is negative. 


AZ 

AN 

AV 

AC 

AS 



COMPUTATION with MEMORY WRITE 


<MAC> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set if the accumulated product overflows the lower-order 32 

bits of the MR register. Cleared otherwise. 

<SHIFT> operation 

ASTAT: 7654321 0 

SS MV AQ AS AC AV AN AZ 


SS Affected only when executing the EXP operation; set if the 

source operand is negative. Cleared if the number is 
positive. 


Instruction Format: 

ALU/MAC operation with Data Memory Write, Instruction Type 4: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Oil 

G 

□ 

0 

AMF 

Yop 

Xop 

Dreg 

i 

I 

M 


ALU/MAC operation with Program Memory Write, Instruction Type 5: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 10 11 

Z 

AMF 

Yop 

Xop 

Dreg 

I 

M 


(instruction continues on next page) 





COMPUTATION with MEMORY WRITE 


Shift operation with Data Memory Write, Instruction Type 12: 


23 22 

21 20 19 18 17 16 15 14 13 

12 11 10 9 

876543210 

0 0 

0 1 0 0 1 G 1 

SF Xop 

Dreg I M 

Shift operation with Program Memory Write, Instruction Type 13: 

23 22 

21 20 19 18 17 16 15 14 13 

12 11 10 9 

876543210 

0 0 

0 1 0 0 0 1 1 

SF Xop 

Dreg I M 

Z: 

Result register 

Dreg: 

Destination register 

SF: 

Shifter operation 

AMF: 

ALU/MAC operation 

Yop: 

Y operand 

Xop: 

X operand 

I: 

G: 

Indirect address register 
Data Address Generator; 

I & M registers must be from 
the same DAG, as separated 
by the gray bar in the Syntax 
description. 

M: 

Modify register 





DATA & PROGRAM MEMORY READ 


Syntax: 


AX0 

= DM ( 

10 

/ 

M0 

), 

AY0 

= PM ( 

14 

/ 

M4 

AX1 


11 


Ml 


AY1 


15 


M5 

MX0 


12 


M2 


MY0 


16 


M6 

MX1 


13 


M3 


MY1 


17 


M7 


Description: Perform the designated memory reads, one from data 
memory and one from program memory. Each read operation moves the 
contents of the memory location to the destination register. For this double 
data fetch, the destinations for data memory reads are the X registers in 
the ALU and the MAC, and the destinations for program memory reads 
are the Y registers. The addressing mode for this memory read is register 
indirect with post-modify. For linear (i.e. non-circular) indirect 
addressing, the L register corresponding to the I register used must be 
set to zero. The contents of the source are always right-justified in the 
destination register. 

A multifunction instruction requires three items to be fetched from 
memory: the instruction itself and two data words. No extra cycle is 
needed to execute the instruction as long as only one of the fetches is from 
external memory. 

If two off-chip accesses are required, however — the instruction fetch and 
one data fetch, for example, or data fetches from both program and data 
memory — then one overhead cycle occurs. In this case the program 
memory access occurs first, then the data memory access. If three off-chip 
accesses are required — the instruction fetch as well as data fetches from 
both program and data memory — then two overhead cycles occur. 

Status Generated: No status bits are affected. 


Instruction Format: 

ALU/MAC with Data & Program Memory Read, Instruction Type 1: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

1 1 

PD 

DD 

AMF 

0 0 0 0 0 

PM 

I 

PM 

M 

DM 

I 

DM 

M 


AMF specifies the ALU or MAC function. In this case, AMF = 00000, 
designating a no-operation for the ALU or MAC function. 

PD: Program Destination register DD: Data Destination register 
AMF: ALU/MAC operation I: Indirect address register 

M: 


Modify register 


15-103 




ALU / MAC with DATA & PROGRAM MEMORY READ 


Syntax: 


<ALU> 

/ 

AXO 

= DM ( 

10 

/ 

MO 

), 

AYO 

= PM ( 

14 

/ 

M4 

<MAC> 


AX1 


11 


Ml 


AY1 


15 


M5 



MXO 


12 


M2 


MYO 


16 


M6 



MX1 


13 


M3 


MY1 


17 


M7 


Description: This instruction combines an ALU or a MAC operation 
with a data memory read and a program memory read. The read 
operations move the contents of the memory location to the destination 
register. For this double data fetch, the destinations for data memory 
reads are the X registers in the ALU and the MAC, and the destinations 
for program memory reads are the Y registers. The addressing mode is 
register indirect with post-modify. For linear (i.e. non-circular) indirect 
addressing, the L register corresponding to the I register used must be 
set to zero. The contents of the source are always right-justified in the 
destination register after the read. 

A multifunction instruction requires three items to be fetched from 
memory: the instruction itself and two data words. No extra cycle is 
needed to execute the instruction as long as only one of the fetches is from 
external memory. 

If two off-chip accesses are required, however — the instruction fetch and 
one data fetch, for example, or data fetches from both program and data 
memory — then one overhead cycle occurs. In this case the program 
memory access occurs first, then the data memory access. If three off-chip 
accesses are required — the instruction fetch as well as data fetches from 
both program and data memory — then two overhead cycles occur. 

The computation must be unconditional. All ALU and MAC operations 
are permitted except the DIVS and DIVQ instructions. The results of the 
computation must be written into the R register of the computational unit; 
ALU results to AR, MAC results to MR. 

The fundamental principle governing multifunction instructions is that 
registers (and memory) are read at the beginning of the processor cycle 
and written at the end of the cycle. The normal left-to-right order of 
clauses (computation first, memory reads second) is intended to imply 
this. In fact, you may code this instruction with the order of clauses 
altered. The assembler produces a warning, but the results are identical at 
the opcode level. If you turn off semantics checking in the assembler (-s 
switch) the warning is not issued. 



ALU / MAC with DATA & PROGRAM MEMORY READ 


The same data register may be used as a source for the arithmetic 
operation and as a destination for the memory read. The register supplies 
the value present at the beginning of the cycle and is written with the 
value from memory at the end of the cycle. 

For example, 

(1) MR=MR+MX0*MY0(UU), MX0=DM(I0, MO), MY0=PM(I4,M4); 

is a legal version of this multifunction instruction and is not flagged by the 
assembler. Changing the order of clauses, as in 

(2) MX0=DM(I0, MO), MY0=PM(I4,M4), MR=MR+MX0*MY0(UU); 

results in an assembler warning, but assembles and executes exactly as the 
first form of the instruction. Note that reading example (2) from left to 
right may suggest that the data memory value is loaded into MXO and 
MYO and subsequently used in the computation, all in the same cycle. In 
fact, this is not possible. The left-to-right logic of example (1) suggests the 
operation of the instruction more closely. Regardless of the apparent logic 
of reading the instruction from left to right, the read-first, write-second 
operation of the processor determines what actually happens. 

Status Generated: All status bits are affected in the same way as for the 
single operation version of the selected arithmetic operation. 


<ALU> operation 


ASTAT: 

7 

6 

5 

4 

3 

2 

1 

0 


SS 

MV 

AQ 

AS 

* 

AC 

* 

AV 

* 

AN 

* 

AZ 

* 


AZ Set if result equals zero. Cleared otherwise. 

AN Set if result is negative. Cleared otherwise. 


AV Set if an overflow is generated. Cleared otherwise. 

AC Set if a carry is generated. Cleared otherwise. 

AS Affected only when executing the Absolute Value operation 

(ABS). Set if the source operand is negative. 


(instruction continues on next page) 



ALU / MAC with DATA & PROGRAM MEMORY READ 


<MAC> operation 

ASTAT: 7 6 5 4 3 2 1 0 

SS MV AQ AS AC AV AN AZ 


MV Set if the accumulated product overflows the lower-order 32- 

bits of the MR register. Cleared otherwise. 


Instruction Format: 

ALU/MAC with Data and Program Memory Read, Instruction Type 1: 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

1 1 

PD 

DD 

AMF 

Yop 

Xop 

PM 

I 

PM 

M 

DM 

I 

DM 

M 


PD: 

Program Destination register 

DD: 

Data Destination register 

AMF: 

ALU/MAC operation 

M: 

Modify register 

Yop: 

Y operand 

Xop: 

X operand 

I: 

Indirect address register 






Instruction Coding H A 


A.1 OPCODES 

This appendix gives a summary of the complete instruction set of the 
ADSP-2100 family processors. Opcode field names are defined at the end 
of the appendix. Any instruction codes not shown are reserved for future 
use. 


Type 1 : ALU / MAC with Data & Program Memory Read 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

1 1 

PD 

DD 

AMF 

Yop 

Xop 

PM 

I 

PM 

M 

DM 

I 

DM 

M 


Type 2: Data Memory Write (Immediate Data) 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

10 1 

G 

DATA 

i 

I 1 

i 

M 


Type 3: Read /Write Data Memory (Immediate Address) 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

10 0 

D 

RGP 

ADDR 

REG 


Type 4: ALU / MAC with Data Memory Read / Write 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 

1 0 

0 

1 

1 

G 

D 

□ 

AMF 

Yop 

Xop 

DREG 


M 


Type 5: ALU / MAC with Program Memory Read / Write 


23 22 21 20 19 18 17 16 15 14 13 12 11 

10 9876543210 

0 10 1 

□ 

0 

AMF 

Yop 

Xop 

DREG 

I 

M 


A- 1 








Type 6: Load Data Register Immediate 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 10 0 

DATA 

DREG 


Type 7: Load Non-Data Register Immediate 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 11 

RGP 

DATA 

REG 


Type 8: ALU / MAC with Internal Data Register Move 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 543 210 


0 0 10 1 

Z 

AMF 

Yop 

Xop 

Dest 

Source 






DREG 

DREG 


Generate ALU Status (NONE = <ALU>) (ADSP-21 7x, ADSP-218x, ADSP-21 msp58/59 only) 


2.3 

22 

21 

20 

19 

18 

17 

16 15 14 13 

12 11 

10 9 8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

1 

0 

3 

0 

AMF^ 



E 

0 

1 

3 

E 

0 

1 

0 


X 

ALU codes only 


Type 9: Conditional ALU / MAC 
xop* yop 


23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 10 

0 

0 

1 

0 


I] 

AMF 

Yop 

Xop 

0 0 0 0 

COND 

xop 

* xop 




(ADSP-21 7x, ADSP-21 8x, ADSP-21 msp58/59 only) 

23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 10 

0 

0 

1 

0 

0 

Z 

AMF 

0 0 

Xop 

0 0 0 1 

COND 

xop AND/OR/XOR constant (ADSP-21 7x, ADSP-21 8x, ADSP-21 msp58/59 only) 

23 

22 

21 

20 

19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 10 

0 

0 

1 

0 

0 


AMF 

YY 

Xop 

CC BO 

COND 


BO, CC, and YY specify the constant according the table shown at the end of this appendix. 


PASS constant (constant * 0,1 -1 ) (ADSP-21 7x, ADSP-21 8x, ADSP-21 msp58/59 only) 

23 22 21 20 19 

18 

17 16 15 14 13 

12 11 

10 9 8 

7 6 5 4 

3 2 10 

0 0 10 0 

E 

AMF 

YY 

Xop 

CC BO 

COND 
























Type 1 0: Conditional Jump (Immediate Address) 


23 

22 

21 

20 

19 

18 

17 

16 15 14 13 12 11 10 9 8 7 6 5 4 

3 2 10 

0 

0 

0 

1 

1 

S 

ADDR 

COND 


Type 11: Do Until 


23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

0 0 0 1 0 1 

ADDR 

TERM 


Type 1 2: Shift with Data Memory Read / Write 


23 

22 

21 

20 19 18 

17 

16 

15 

14 13 12 11 

10 9 8 

7 6 5 

4 

3 2 

1 0 

0 

0 

0 

10 0 

1 

G 

D 

SF 

Xop 

DREG 

I 

M 

Type 13: 


Shift with Program Memory Read / Write 





23 

22 

21 

20 19 18 

17 

16 

15 

14 13 12 11 

10 9 8 

7 6 5 

4 

3 2 

1 0 

0 

0 

El 


0 

1 

D 

SF 

Xop 

DREG 

I 

M 

Type 14: 


Shift with Internal Data Register Move 






23 

22 

21 

20 19 18 

17 

16 

15 

14 13 12 11 

10 9 8 

7 6 5 

4 

3 2 

1 0 

0 

0 

0 

10 0 

0 

0 

0 

SF 

Xop 

Dest 


Source 










DREG 


DREG 

Type 15: 


Shift Immediate 








23 

22 

21 

20 19 18 

17 

16 

15 

14 13 12 11 

10 9 8 

7 6 5 

4 

3 2 

1 0 

D 

0 

0 


1 

1 

D 

SF 

xop 

exponent 

Type 16: 


Conditional Shift 








23 

22 

21 

20 19 18 

17 

16 

15 

14 13 12 11 

10 9 8 

7 6 5 

4 

3 2 

1 0 

0 

0 

0 

Oil 

1 

0 

0 

SF 

Xop 

0 0 0 

0 

COND 
























Type 17: 


Internal Data Move 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 10 

9 8 

7 6 5 4 

3 2 10 

0 

0 

0 

0 

1 

1 

O 

1 

O 

O 

O 

O 

DST 

SRC 

Dest 

Source 













RGP 

RGP 

REG 

REG 


Type 18: Mode Control 


23 

22 

21 

20 

19 

18 

17 

16 

15 14 

13 12 

11 10 

9 8 

7 6 

5 4 

3 2 

1 

0 

O 

0 

0 

0 

1 

1 

0 

111 

TI 

MM 

AS 

OL 

BR 

SR 

GM 


O 


Mode Control codes: 


SR: Secondary register bank 

BR: Bit-reverse mode 

OL: ALU overflow latch mode 

AS: AR register saturate mode 

MM: Alternate Multiplier placement mode 

GM: GO Mode; enable means execute internal code if possible 

Tl: Timer enable 


11 = Enable Mode 
10 = Disable Mode 
0 1 = no change 
00 = no change 


Type 1 9: Conditional Jump (Indirect Address) 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

0 

1 

1 

O 

0 

0 

0 

0 

0 

0 


I 

E 


COND 


Type 20: Conditional Return 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

M 

COND 


Type 21 : Modify Address Register 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 

1 0 

0 

0 

0 

0 

1 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

I] 

3 

I 

M 


A-4 















Type 22: 


Reserved 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 2 10 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 


COND 


Type 23: DIVQ 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 9 8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

1 

1 

1 

0 

0 

0 

1 

0 

Xop 

Li 

0 

0 

0 

0 

0 

0 

0 


Type 24: DIVS 



Type 26: Stack Control 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 


PP 

LP 

CP 

SPP 


Type 27: Call or Jump on Flag In 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 12 11 10 9 8 7 6 5 4 

3 2 

l 

0 

0 

0 

0 

0 

0 

0 

1 


Address 

4 

Addr 

— 4 

FIC 

E 


^ ^ 


12 LSBs 2 MSBs 


Type 28: Modify Flag Out 






III 

18 

17 

16 

15 

14 

13 

12 

11 10 

9 8 

7 6 

5 4 

3 2 10 

0 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

0 

FO 

/ 

FO 

/ 

FO 

i— 

FO 

1— 

COND 


rm 


FL2 FLl FLO FLAG_OUT 










Type 29: I/O Memory Space Read/Write (ADSP-218x only) 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 13 

12 11 10 9 8 7 6 5 4 

3 2 10 

0 

0 

0 

0 

0 

0 

0 

1 3 

D 

ADDR 

DREG 


Type 30: No Operation (NOP) 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 


Type 31 : Idle 


23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 

0 

0 

D 

0 

0 

1 

0 

1 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 


Type 31 : Idle (n) (Slow Idle) 



















A.2 ABBREVIATION CODING 


AMF ALU / MAC Function codes 

ooooo No operation 


MAC Function codes 


0 

0 

0 

0 

1 

X* Y 

(RND) 

0 

0 

0 

1 

0 

MR + X * Y 

(RND) 

0 

0 

0 

1 

1 

MR-X* Y 

(RND) 

0 

0 

1 

0 

0 

X* Y 

(SS) Clear when y 

0 

0 

1 

0 

1 

X* Y 

(SU) 

0 

0 

1 

1 

0 

X* Y 

(US) 

0 

0 

1 

1 

1 

X* Y 

(UU) 

0 

1 

0 

0 

0 

MR + X * Y 

(SS) 

0 

1 

0 

0 

1 

MR + X * Y 

(SU) 

0 

1 

0 

1 

0 

MR + X * Y 

(US) 

0 

1 

0 

1 

1 

MR + X * Y 

(UU) 

0 

1 

1 

0 

0 

MR-X * Y 

(SS) 

0 

1 

1 

0 

1 

MR-X* Y 

(SU) 

0 

1 

1 

1 

0 

MR-X * Y 

(US) 

0 

1 

1 

1 

1 

MR-X * Y 

(UU) 

ALU Function codes 


l 

0 

0 

0 

0 

Y 

Clear when y = 0 

l 

0 

0 

0 

1 

Y + 1 

PASS 1 when y = 0 

l 

0 

0 

1 

0 

X + Y + C 


l 

0 

0 

1 

1 

X + Y 

X when y = 0 

l 

0 

1 

0 

0 

NOTY 


l 

0 

1 

0 

1 

-Y 


l 

0 

1 

1 

0 

X-Y+C-1 

X + C - 1 when y = 0 

l 

0 

1 

1 

1 

X-Y 


l 

1 

0 

0 

0 

Y - 1 

PASS -1 when y = 0 

l 

1 

0 

0 

1 

Y-X 

- X when y = 0 

l 

1 

0 

1 

0 

Y-X+C-1 

-X + C - 1 when y = 0 

l 

1 

0 

1 

1 

NOTX 


l 

1 

1 

0 

0 

XANDY 


l 

1 

1 

0 

1 

XORY 


l 

1 

1 

1 

0 

XXORY 


l 

1 

1 

1 

1 

ABS X 



A-7 



BO see YY, CC, BO at the end of this appendix 

CC see YY, CC, BO at the end of this appendix 

COND Status Condition codes 


0 0 0 0 Equal EQ 

0 0 0 1 Not equal NE 

0 0 10 Greater than GT 

0 0 11 Less than or equal LE 

0 10 0 Less than LT 

0 10 1 Greater than or equal GE 

0 110 ALU Overflow AV 

Olll NOT ALU Overflow NOTAV 

1 0 0 0 ALU Carry AC 

10 0 1 Not ALU Carry NOT AC 

10 10 X input sign negative NEG 

10 11 X input sign positive POS 

110 0 MAC Overflow MV 

110 1 Not MAC Overflow NOT MV 

1110 Not counter expired NOT CE 

1111 Always true 


CP Counter Stack Pop codes 

0 No change 

1 Pop 

D Memory Access Direction codes 

0 Read 

1 Write 

DD Double Data Fetch Data Memory Destination codes 

0 0 AXO 

0 1 AX1 

1 o MXO 

1 1 MX1 


A-8 



DREG 


Data Register codes 


OOOO AXO 

0 0 0 1 AX1 

0 0 10 MXO 

0 0 11 MX1 

0100 AYO 

0 10 1 AY1 

0 110 MYO 

0 111 MY1 

1 0 0 0 SI 

1001 SE 

10 10 AR 

10 11 MRO 

110 0 MR1 

110 1 MR2 

1110 SRO 

1111 SRI 


DV 


FIC 


Divisor codes for Slow Idle instruction ( IDLE (n) ) 


0 0 0 0 
0 0 0 1 
0 0 10 
0 10 0 
10 0 0 


Normal Idle instruction (Divisor=0) 

Divisor=16 

Divisor=32 

Divisor=64 

Divisor=128 


FI condition code 


1 latched FI is 1 “ FLAGJN ” 

0 latched FI is 0 “NOT FLAGJN” 


FO 


Control codes for Flag Output Pins (FO, FLO, FL1 , FL2) 



Data Address Generator codes 


0 DAG1 

1 DAG2 

I Index Register codes 


G = 

0 

1 

0 0 

10 

14 

0 1 

11 

15 

1 0 

12 

16 

1 1 

13 

17 

Loop Stack 

Pop codes 


0 

No Change 

1 

Pop 


Modify Register codes 


G = 

0 

1 

0 0 

MO 

M4 

0 1 

Ml 

M5 

1 0 

M2 

M6 

1 1 

M3 

M7 


PD Dual Data Fetch Program Memory Destination codes 

0 0 AYO 

0 1 AY1 

1 0 MYO 

11 MY1 

PP PC Stack Pop codes 

0 No Change 

1 Pop 


A-10 



REG Register codes 

Codes not assigned are reserved. 


RGP 

= 


00 

01 

10 

11 

0 

0 

0 

0 

AXO 

10 

14 

ASTAT 

0 

0 

0 

1 

AX1 

11 

15 

MSTAT 

0 

0 

1 

0 

MXO 

12 

16 

SSTAT (read only) 

0 

0 

1 

1 

MX1 

13 

17 

IMASK 

0 

1 

0 

0 

AYO 

MO 

M4 

ICNTL 

0 

1 

0 

1 

AY1 

Ml 

M5 

CNTR 

0 

1 

1 

0 

MYO 

M2 

M6 

SB 

0 

1 

1 

1 

MY1 

M3 

M7 

PX 

1 

0 

0 

0 

SI 

LO 

L4 

RXO 

1 

0 

0 

1 

SE 

LI 

L5 

TXO 

1 

0 

1 

0 

AR 

L2 

L6 

RX1 

1 

0 

1 

1 

MRO 

L3 

L7 

TX1 

1 

1 

0 

0 

MR1 

- 

- 

IFC (write only) 

1 

1 

0 

1 

MR2 

- 

- 

OWRCNTR (write only) 

1 

1 

1 

0 

SRO 

- 

- 

- 

1 

1 

1 

1 

SRI 

- 

- 

— 


S Jump/Call codes 

0 Jump 

1 Call 


A- 11 



SF Shifter Function codes 


OOOO LSHIFT (HI) 

0 0 0 1 LSHIFT (HI, OR) 

0 0 10 LSHIFT (LO) 

0 0 11 LSHIFT (LO, OR) 

0 10 0 ASHIFT (HI) 

0 10 1 ASHIFT (HI, OR) 

0 110 ASHIFT (LO) 

0 111 ASHIFT (LO, OR) 

1 0 0 0 NORM (HI) 

10 0 1 NORM (HI, OR) 

10 10 NORM (LO) 

10 11 NORM (LO, OR) 

110 0 EXP (HI) 

110 1 EXP (HIX) 

1110 EXP (LO) 


llll Derive Block Exponent 
SPP Status Stack Push/Pop codes 

00 No change 

01 No change 

l o Push 

l l Pop 

T Return Type codes 

0 Return from Subroutine 

1 Return from Interrupt 


A-12 




TERM Termination codes for DO UNTIL 


0 

0 

0 

0 

Not equal 

NE 

0 

0 

0 

1 

Equal 

EQ 

0 

0 

1 

0 

Less than or equal 

LE 

0 

0 

1 

1 

Greater than 

GT 

0 

1 

0 

0 

Greater than or equal 

GE 

0 

1 

0 

1 

Less than 

LT 

0 

1 

1 

0 

NOT ALU Overflow 

NOTAV 

0 

1 

1 

1 

ALU Overflow 

AV 

1 

0 

0 

0 

Not ALU Carry 

NOT AC 

1 

0 

0 

1 

ALU Carry 

AC 

1 

0 

1 

0 

X input sign positive 

POS 

1 

0 

1 

1 

X input sign negative 

NEG 

1 

1 

0 

0 

Not MAC Overflow 

NOT MV 

1 

1 

0 

1 

MAC Overflow 

MV 

1 

1 

1 

0 

Counter expired 

CE 

1 

1 

1 

1 

Always 

FOREVER 

X Operand codes 



0 

0 

0 


XO (SI for shifter) 


0 

0 

1 


XI (invalid for shifter) 


0 

1 

0 


AR 


0 

1 

1 


MRO 


1 

0 

0 


MR1 


1 

0 

1 


MR2 


1 

1 

0 


SRO 


1 

1 

1 


SRI 


Y Operand codes 



0 

0 



YO 


0 

1 



Y1 


1 

0 



F (feedback register) 


1 

1 



zero 



A-13 



YY see YY, CC, BO below 

Z ALU/MAC Result Register codes 

0 Result register 

1 Feedback register 


YY, CC, BO ALU / MAC Constant codes (Type 9) 

(ADSP-217X, ADSP-218x, ADSP-21msp58/59 only) 


Constant (hex) 

YY 

QQ 

BQ 

Bit# 

0001 

00 

00 

01 

bitO 

0002 

00 

01 

01 

bit 1 

0004 

00 

10 

01 

bit 2 

0008 

00 

11 

01 

bit 3 

0010 

01 

00 

01 

bit 4 

0020 

01 

01 

01 

bit 5 

0040 

01 

10 

01 

bit 6 

0080 

01 

11 

01 

bit 7 

0100 

10 

00 

01 

bit 8 

0200 

10 

01 

01 

bit 9 

0400 

10 

10 

01 

bit 10 

0800 

10 

11 

01 

bit 11 

1000 

11 

00 

01 

bit 12 

2000 

11 

01 

01 

bit 13 

4000 

11 

10 

01 

bit 14 

8000 

11 

11 

01 

bit 15 

FFFE 

00 

00 

11 

! bit 0 

FFFD 

00 

01 

11 

! bit 1 

FFFB 

00 

10 

11 

! bit 2 

FFF7 

00 

11 

11 

! bit 3 

FFEF 

01 

00 

11 

! bit 4 

FFDF 

01 

01 

11 

! bit 5 

FFBF 

01 

10 

11 

I bit 6 

FF7F 

01 

11 

11 

! bit 7 

FEFF 

10 

00 

11 

! bit 8 

FDFF 

10 

01 

11 

! bit 9 

FBFF 

10 

10 

11 

! bit 10 

F7FF 

10 

11 

11 

! bit 1 1 

EFFF 

11 

00 

11 

! bit 12 

DFFF 

11 

01 

11 

! bit 13 

BFFF 

11 

10 

11 

! bit 14 

7FFF 

11 

11 

11 

! bit 15 


A-14 



Division Exceptions 


B.1 DIVISION FUNDAMENTALS 

The ADSP-2100 family processors' instruction set contains two 
instructions for implementing a non-restoring divide algorithm. These 
instructions take as their operands twos-complement or unsigned 
numbers, and in sixteen cycles produce a truncated quotient of sixteen 
bits. For most numbers and applications, these primitives produce the 
correct results. However, there are certain situations where results 
produced will be off by one LSB. This appendix documents these 
situations, and presents alternatives for producing the correct results. 

Computing a 16-bit fixed point quotient from two numbers is 
accomplished by 16 executions of the DIVQ instruction for unsigned 
numbers. Signed division uses the DIVS instruction first, followed by 
fifteen DIVQs. Regardless of which division you perform, both input 
operands must be of the same type (signed or unsigned) and produce a 
result of the same type. 

These two instructions are used to implement a conditional add /subtract, 
non-restoring division algorithm. As its name implies, the algorithm 
functions by adding or subtracting the divisor to/from the dividend. The 
decision as to which operation is perform is based on the previously 
generated quotient bit. Each add /subtract operation produces a new 
partial remainder, which will be used in the next step. 

The phrase non-restoring refers to the fact that the final remainder is not 
correct. With a restoring algorithm, it is possible, at any step, to take the 
partial quotient, multiply it by the divisor, and add the partial remainder 
to recreate the dividend. With this non-restoring algorithm, it is necessary 
to add two times the divisor to the partial remainder if the previously 
determined quotient bit is zero. It is easier to compute the remainder 
using the multiplier than in the ALU. 

B.1.1 Signed Division 

Signed division is accomplished by first storing the 16-bit divisor in an X 
register (AXO, AX1, AR, MR2, MR1, MRO, SRI, or SRO). The 32-bit dividend 
must be stored in two separate 16-bit registers. The lower 16-bits must be 
stored in AYO, while the upper 16-bits can be in either AY1, or AF. 




The DIVS primitive is executed once, with the proper operands (ex. DIVS 
AY1, AXO) to compute the sign of the quotient. The sign bit of the quotient 
is determined by XORing (exclusive-or) the sign bits of each operand. The 
entire 32-bit dividend is shifted left one bit. The lower fifteen bits of the 
dividend with the recently determined sign bit appended are stored in 
AYO, while the lower fifteen bits of the upper word, with the MSB of the 
lower word appended is stored in AF. 

To complete the division, 15 DIVQ instructions are executed. Operation of 
the DIVQ primitive is described below. 

B.1.2 Unsigned Division 

Computing an unsigned division is done like signed division, except the 
first instruction is not a DIVS, but another DIVQ. The upper word of the 
dividend must be stored in AF, and the AQ bit of the AST AT register 
must be set to zero before the divide begins. 

The DIVQ instruction uses the AQ bit of the ASTAT register to determine 
if the dividend should be added to, or subtracted from the partial 
remainder stored in AF and AYO. If AQ is zero, a subtract occurs. A new 
value for AQ is determined by XORing the MSB of the divisor with the 
MSB of the dividend. The 32-bit dividend is shifted left one bit, and the 
inverted value of AQ is moved into the LSB. 

B.1.3 Output Formats 

As in multiplication, the format of a division result is based on the format 
of the input operands. The division logic has been designed to work most 
efficiently with fully fractional numbers, those most commonly used in 
fixed-point DSP applications. A signed, fully fractional number uses one 
bit before the binary point as the sign, with fifteen (or thirty-one in double 
precision) bits to the right, for magnitude. 

If the dividend is in M.N format (M bits before the binary point, N bits 
after), and the divisor is O.P format, the quotient's format will be 
(M-0+l).(N-P-l). As you can see, dividing a 1.31 number by a 1.15 
number will produce a quotient whose format is (1-1+1). (31-15-1) or 1.15. 

Before dividing two numbers, you must ensure that the format of the 
quotient will be valid. For example, if you attempted to divide a 32.0 
number by a 1.15 number the result would attempt to be in 
(32-1+1). (0-15-1) or 32.-16 format. This cannot be represented in a 16-bit 
register! 



In addition to proper output format, you must insure that a divide 
overflow does not occur. Even if a division of two numbers produces a 
legal output format, it is possible that the number will overflow, and be 
unable to fit within the constraints of the output. For example, if you 
wished to divide a 16.16 number by a 1.15 number, the output format 
would be (16-1+1).(16-15-1) or 16.0 which is legal. Now assume you 
happened to have 16384 (0x4000) as the dividend and .25 (0x2000) as the 
divisor, the quotient would be 65536, which does not fit in 16.0 format. 
This operation would overflow, producing an erroneous results. 

Input operands can be checked before division to ensure that an overflow 
will not result. If the magnitude of the upper 16 bits of the dividend is 
larger than the magnitude of the divisor, an overflow will result. 

B.1.4 Integer Division 

One special case of division that deserves special mention is integer 
division. There may be some cases where you wish to divide two integers, 
and produce an integer result. It can be seen that an integer-integer 
division will produce an invalid output format of (32-16+l).(0-0-l), or 
17.-1. 

To generate an integer quotient, you must shift the dividend to the left one 
bit, placing it in 31.1 format. The output format for this division will be 
(31-1 6+1). (1-0-1), or 16.0. You must ensure that no significant bits are lost 
during the left shift, or an invalid result will be generated. 


B.2 ERROR CONDITIONS 

Although the divide primitives for the ADSP-2100 family work correctly 
in most instances, there are two cases where an invalid or inaccurate result 
can be generated. The first case involves signed division by a negative 
number. If you attempt to use a negative number as the divisor, the 
quotient generated may be one LSB less than the correct result. The other 
case concerns unsigned division by a divisor greater than 0x7FFF. If the 
divisor in an unsigned division exceeds 0x7FFF, an invalid quotient will 
be generated. 

B.2.1 Negative Divisor Error 

The quotient produced by a divide with a negative divisor will generally 
be one LSB less than the correct result. The divide algorithm implemented 
on the ADSP-2100 family does not correctly compensate for the twos- 
complement format of a negative number, causing this inaccuracy. 


B-3 



There is one case where this discrepancy does not occur. If the result of the 
division operation should equal 0x8000, then it will be correctly 
represented, and not be one LSB off. 

There are several ways to correct for this error. Before changing any code, 
however, you should determine if a one-LSB error in your quotient is a 
significant problem. In some cases, the LSB is small enough to be 
insignificant. If you find it necessary have exact results, two solutions are 
possible. 

One is to avoid division by negative numbers. If your divisor is negative, 
take its absolute value and invert the sign of the quotient after division. 
This will produce the correct result. 

Another technique would be to check the result by multiplying the 
quotient by the divisor. Compare this value with the dividend, and if they 
are off by more than the value of the divisor, increase the quotient by one. 

B.2.2 Unsigned Division Error 

Unsigned divisions can produce erroneous results if the divisor is greater 
than 0x7FFF. You should not attempt to divide two unsigned numbers if 
the divisor has a one in the MSB. If it is necessary to perform a such a 
division, both operands should be shifted right one bit. This will maintain 
the correct orientation of operands. 

Shifting both operands may result in a one LSB error in the quotient. This 
can be solved by multiplying the quotient by the original (not shifted) 
divisor. Subtract this value from the original dividend to calculate the 
error. If the error is greater than the divisor, add one to the quotient, if it is 
negative, subtract one from the quotient. 


B.3 SOFTWARE SOLUTION 

Each of the problems mentioned in this Appendix can be compensated for 
in software. Listing 1 shows the module divide _solution. This code can be 
used to divide two signed or unsigned numbers to produce the correct 
quotient, or an error condition. 

In addition to correcting the problems mentioned, this module provides a 
check for division overflow and computes the remainder following the 
division. 




Since many applications do not require complete error checking, the code 
has been designed so you can remove tests that are not necessary for your 
project. This will decrease memory requirements, as well as increase 
execution speed. 

The module signed_div expects the 32-bit dividend to be stored in 
AY1&AY0, and the divisor in AXO. Upon return either the AR register 
holds the quotient and MRO holds the remainder, or the overflow flag is 
set. The entire routine takes at most twenty-seven cycles to execute. If an 
exception condition exists, it may return sooner. The first two instructions 
store the dividend in the MR registers, the absolute value of the 
dividend's MSW in AF, and the divisor's absolute value in AR. 

The code block labeled test_l checks for division by 0x8000. Attempting to 
take the absolute value of 0x8000 produces an overflow. If the AV flag is 
set (from taking the absolute value of the divisor), then the quotient is - 
AY1. This can produce an error if AY1 is 0x8000, so after taking the 
negative of AY1, the overflow flag is checked again. If it is set control is 
returned to the calling routine, otherwise the remainder is computed. If it 
is not necessary to check for a divisor of 0x8000, this code block can be 
removed. 

The code block labeled test_2 checks for a division overflow condition. The 
absolute value of the divisor is subtracted from the absolute value of the 
dividend's MSW. If the divisor is less then the dividend, it is likely an 
overflow will occur. If the two are equal in magnitude, but different in 
sign, the result will be 0x8000, so this special case is checked. If your 
application does not require an overflow check, this code block can be 
removed. If you decide to remove test_2 be sure to change the JUMP 
address in testJL to do_divs, instead of test_2. 

After error checking, the actual division is performed. Since the absolute 
value of the divisor has been stored in AR, this is used as the X-operand 
for the DIVS instruction. 15 DIVQ instructions follow, computing the rest 
of the quotient. The correct sign for the quotient is determined, based on 
the AS flag of the ASTAT register. Since the MR register contains the 
original dividend, the remainder can be determine by a multiply subtract 
operation. The divisor times the quotient is subtracted from MR to 
produce the remainder in MRO. 

The last step before returning is to clear the ASTAT register which may 
contain an overflow flag produced during the divide. 


B - 5 



The subroutine unsigned _div is very similar to signed _div. MR1 and AF are 
loaded with the MSW of the dividend, MRO is loaded with the dividend 
LSW and the divisor is passed into AR. Since unsigned division with a 
large divisor (> 0x7FFF) is prohibited, the MSB of the divisor is checked. If 
it contains a one, the overflow flag is set, and the routine returns to the 
caller. Otherwise test_ll checks for a standard divide overflow. 

In test_ll the divisor is subtracted from the MSW of the dividend. If the 
result is less then zero division can proceed, otherwise the overflow flag is 
set. If you wish to remove testJLl, be sure to change the JUMP address in 
test_10 to do_divq. 

The actual unsigned division is performed by first clearing the AQ bit of 
the ASTAT register, then executing sixteen DIVQ instructions. The 
remainder is computed, after first setting MR2 to zero. This is necessary 
since MR1 automatically sign-extends into MR2. Also, the multiply must 
be executed with the unsigned switch. To ensure that the overflow flag is 
clear, ASTAT is set to zero before returning. 

In both subroutines, the computation of the remainder requires only one 
extra cycle, so it is unlikely you would need to remove it for speed. If it is 
a problem to have the multiply registers altered, remove the 
multiply/ subtract instruction just before the return, and remove the 
register transfers to MRO and MR1 in the first two multifunction 
instructions. Be sure to remove the MR2=0; instruction in the unsigned_div 
subroutine also. 

. MODULE/ROM Divide_solution; 

{ 

This module can be used to generate correct results when using the divide primitives 
of the ADSP-2100 family. The code is organized in sections. This entire module can 
be used to handle all error conditions, or individual sections can be removed to 
increase execution speed. 

Entry Points 

signed_div Computes 16-bit signed quotient 
unsigned_div Computes 16-bit unsigned quotient 

Calling Parameters 

AXO = 16-bit divisor 

AYO = Lower 16 bits of dividend 

AY1 = Upper 16 bits of dividend 


B-6 




Return Values 

AR = 16-bit quotient 

MRO = 16 -bit remainder 

AV flag set if divide would overflow 

Altered Registers 

AXO, AXl , AR, AF, AYO , AYl , MR, MYO 


Computation Time: 30 cycles 

} 

.ENTRY signed_div, unsigned_div; 


signed_div: MR0=AY0 , AF=AX0+AY1 ; 

MR1=AY1, AR=ABS AXO; 


{Take divisor's absolute value} 
{See if divisor, dividend have 
same magnitude} 


test_l : IF NE JUMP test_2; 

ASTAT=0x4; 

RTS; 


{If divisor non-zero, do test 2} 
{Divide by zero, so overflow} 
{Return to calling program} 


test_2 : 


test_3 : 


IF NOT AV JUMP test_3; {If divisor 0x8000, then the} 

AY0=AY1 , AF=ABS AYl; {quotient is simply -AYl} 

IF NOT AV JUMP recover_sign; 


ASTAT=0x4 ; 
RTS; 


{0x8000 divided by 0x8000,} 
{so overflow} 


AF=PASS AF; 

IF NE JUMP test_4 ; 
AY0=0x8000 ; 
ASTAT=0x0 ; 

JUMP recover_sign; 


{Check for division overflow} 
{Not equal, jump test 4} 
{Quotient equals -1} 

{Clear AS bit of ASTAT} 
{Compute remainder} 


test_4 : AF=ABS MRl ; 

AR=ABS AXO; 
AF=AF-AR; 

IF LT JUMP do_divs; 
ASTAT=0x4 ; ' 

RTS; 

Listing B.1 Division Error Routine 


{Get absolute of dividend} 
{Restore AS bit of ASTAT} 

{Check for division overflow} 
{If Divisor>Dividend do divide} 
{Division overflow} 


(continues on next page) 


B-7 



do_divs : 


recover_sign : 

unsigned_div : 

test_10 : 

test_ll : 

do_divq : 


uremainder : 


.ENDMOD; 

Listing B.1 

8 


DIVS 

AYl , 

AR; 

DIVQ AR 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 

DIVQ 

AR; 


MY0=AX0 , AR=PASS AYO ; 
IF NEG AR=-AY0 ; 
MR=MR - AR * MY 0 <SS) ; 
RTS; 


{Compute sign of quotient} 


(Put quotient into AR} 

{Restore sign if necessary} 
{compute remainder dividend neg} 
{Return to calling program} 


MR0=AY0, AF=PASS AY1 ; {Move dividend MSW to AF} 

MR1=AY1 < AR=PASS AXO; {Is MSB set?} 


IF GT JUMP test_ll ; 
ASTAT=0x4 ; 

RTS; 


{No, so check overflow} 
{Yes, so set overflow flag} 
{Return to caller} 


AR=AY1-AX0 ; 

IF LT JUMP do_di vq ; 
ASTAT=0x4 ; 

RTS; 


{Is divisor<dividend?} 

{No, so go do unsigned divide} 
{Set overflow flag} 


AS TAT =0 ; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 


DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 
DIVQ AXO; 


MR2 = 0 ; 

MY0=AX0, AR= PAS S AYO; 
MR=MR - AR * MY 0 (UU) ; 
RTS; 


{Clear AQ flag} 
{Do the divide} 


{MRO and MRl previous set} 
{Divisor in MYO, Quotient in AR} 
{Determine remainder} 

{Return to calling program} 


Division Error Routine 



Numeric Formats □ C 


C.1 OVERVIEW 

ADSP-2100 family processors support 16-bit fixed-point data in hardware. 
Special features in the computation units allow you to support other 
formats in software. This appendix describes various aspects of the 16-bit 
data format. It also describes how to implement a block floating-point 
format in software. 


C.2 UNSIGNED OR SIGNED: TWOS-COMPLEMENT FORMAT 

Unsigned binary numbers may be thought of as positive, having nearly 
twice the magnitude of a signed number of the same length. The least 
significant words of multiple precision numbers are treated as unsigned 
numbers. 

Signed numbers supported by the ADSP-2100 family are in 
twos-complement format. Signed-magnitude, ones-complement, BCD or 
excess-n formats are not supported. 


C.3 INTEGER OR FRACTIONAL 

The ADSP-2100 family supports both fractional and integer data formats, 
with the exception that the ADSP-2100 processor does not perform integer 
multiplication. In an integer, the radix point is assumed to lie to the right 
of the LSB, so that all magnitude bits have a weight of 1 or greater. This 
format is shown in Figure C.l, which can be found on the following page. 
Note that in twos-complement format, the sign bit has a negative weight. 


C-i 




Bit 

15 

14 

13 2 

1 

0 


15 1 

14 

13 1 1 2 

1 

0 

Weight 

<M 

r 

2 

CM 

• 

• 

• 

CM 

2 

2 


Sign 




♦ 


Bit 








Signed Integer 


Radix Point 

Bit 

15 

14 

13 2 

1 

0 


15 

14 

13 2 

1 

0 

Weight 

2 

2 

2 • • • 2 

2 

2 


t 


Unsigned Integer Radix Point 

Figure C.1 Integer Format 

In a fractional format, the assumed radix point lies within the number, so 
that some or all of the magnitude bits have a weight of less than 1. In the 
format shown in Figure C.2, the assumed radix point lies to the left of the 
3 LSBs, and the bits have the weights indicated. 


Bit 15 14 13 4 3 2 1 0 



Unsigned Fractional (13.3) 

3 ' ' Radix Point 


Figure C.2 Example Of Fractional Format 


C-2 







The notation used to describe a format consists two numbers separated by 
a period (.); the first number is the number of bits to the left of radix point, 
the second is the number of bits to the right of the radix point. For 
example, 16.0 format is an integer format; all bits lie to the left of the radix 
point. The format in Figure C.2 is 13.3. 

Table C.l shows the ranges of numbers representable in the fractional 
formats that are possible with 16 bits. 


Format 

Number of 

Number of 

Largest Positive 

Largest Negative 

Value of 1 LSB 


Integer 

Fractional 

Value (0x7FFF) 

Value (0x8000) 

(0x0001) 


Bits 

Bits 

In Decimal 

In Decimal 

In Decimal 

1.15 

1 

15 

0.999969482421875 

- 1.0 

0.000030517578125 

2.14 

2 

14 

1.999938964843750 

- 2.0 

0.000061035156250 

3.13 

3 

13 

3.999877929687500 

- 4.0 

0.000122070312500 

4.12 

4 

12 

7.999755859375000 

- 8.0 

0.000244140625000 

5.11 

5 

11 

15.999511718750000 

- 16.0 

0.000488281250000 

6.10 

6 

10 

31.999023437500000 

- 32.0 

0.000976562500000 

7.9 

7 

9 

63.998046875000000 

- 64.0 

0.001953125000000 

8.8 

8 

8 

127.996093750000000 

- 128.0 

0.003906250000000 

9.7 

9 

7 

255.992187500000000 

- 256.0 

0.007812500000000 

10.6 

10 

6 

511.984375000000000 

- 512.0 

0.015625000000000 

11.5 

11 

5 

1023.968750000000000 

- 1024.0 

0.031250000000000 

12.4 

12 

4 

2047.937500000000000 

- 2048.0 

0.062500000000000 

13.3 

13 

3 

4095.875000000000000 

- 4096.0 

0.125000000000000 

14.2 

14 

2 

8191.750000000000000 

- 8192.0 

0.250000000000000 

15.1 

15 

1 

16383.500000000000000 

- 16384.0 

0.500000000000000 

16.0 

16 

0 

32767.000000000000000 

- 32768.0 

1.000000000000000 


Table C.l Fractional Formats And Their Ranges 


C.4 BINARY MULTIPLICATION 

In addition and subtraction, both operands must be in the same format 
(signed or unsigned, radix point in the same location) and the result 
format is the same as the input format. Addition and subtraction are 
performed the same way whether the inputs are signed or unsigned. 

In multiplication, however, the inputs can have different formats, and the 
result depends on their formats. The ADSP-2100 family assembly 
language allows you to specify whether the inputs are both signed, both 
unsigned, or one of each (mixed-mode). The location of the radix point in 
the result can be derived from its location in each of the inputs. This is 


C-3 



shown in Figure C.3. The product of two 16-bit numbers is a 32-bit 
number. If the inputs' formats are M.N and P.Q, the product has the 
format (M+P).(N+Q). For example, the product of two 13.3 numbers is a 
26.6 number. The product of two 1.15 numbers is a 2.30 number. 


General Rule: 


4-Bit Example: 


16-Bit Examples: 


M.N 

X P.Q 


1.111 

x ii.ii 

1.3 format 

2.2 format 

5.3 

X 5.3 

1.15 

X 1-15 

(M+P) . (N+Q) 


1111 

1111 

1111 

1111 

1 1 1.00001 

10.6 

3.5 format = (1+2) . (2+3) 

2.30 


Figure C.3 Format Of Multiplier Result 


C.4.1 Fractional Mode And Integer Mode 

A product of 2 twos-complement numbers has two sign bits. Since one of 
these bits is redundant, you can shift the entire result left one bit. 
Additionally, if one of the inputs was a 1.15 number, the left shift causes 
the result to have the same format as the other input (with 16 bits of 
additional precision). For example, multiplying a 1.15 number by a 5.11 
number yields a 6.26 number. When shifted left one bit, the result is a 5.27 
number, or a 5.11 number plus 16 LSBs. 

The ADSP-2100 family provides a mode (called the fractional mode) in 
which the multiplier result is always shifted left one bit before being 
written to the result register. (On the ADSP-2100 processor, this mode is 
always active; on other processors, the left shift can be omitted.) This left 
shift eliminates the extra sign bit when both operands are signed, yielding 
a correctly formatted result. 

When both operands are in 1.15 format, the result is 2.30 (30 fractional 
bits). A left shift causes the multiplier result to be 1.31 which can be 
rounded to 1.15. Thus, if you use a fractional data format, it is most 
convenient to use the 1.15 format. 

In the integer mode, the left shift does not occur. This is the mode to use if 
both operands are integers (in the 16.0 format). The 32-bit multiplier result 
is in 32.0 format, also an integer. On the ADSP-2100 only, the integer mode 


C-4 






is not available; the 32.0 result gets shifted to 31.1 format. Because the MSB 
is still available in the 40-bit accumulator, a right shift can correct the 
result. 

In all processors other than the ADSP-2100, fractional and integer modes 
are controlled by a bit in the MSTAT register. At reset, these processors 
default to the fractional mode, for compatibility with the ADSP-2100. 


C.5 BLOCK FLOATING-POINT FORMAT 

A block floating-point format enables a fixed-point processor to gain some 
of the increased dynamic range of a floating-point format without the 
overhead needed to do floating-point arithmetic. Some additional 
programming is required to maintain a block floating-point format, 
however. 

A floating-point number has an exponent that indicates the position of the 
radix point in the actual value. In block floating-point format, a set (block) 
of data values share a common exponent. To convert a block of fixed-point 
values to block floating-point format, you would shift each value left by 
the same amount and store the shift value as the block exponent. 

Typically, block floating-point format allows you to shift out non- 
significant MSBs, increasing the precision available in each value. You can 
also use block floating-point format to eliminate the possibility of a data 
value overflowing. Figure C.4 shows an example. The three data samples 
each have at least 2 non-significant, redundant sign bits. Each data value 

2 Guard Bits 

/ 

= 0000 1111 1111 1111 

= 0001 1111 1111 1111 

= 0000 0111 1111 1111 

Sign Bit 


To detect bit growth into 2 guard bits, set SB=-2 

Figure C.4 Data With Guard Bits 


C-5 


OxOFFF 
0x1 FFF 
0x07FF 




can grow by these two bits (two orders of magnitude) before overflowing; 
thus, these bits are called guard bits. If it is known that a process will not 
cause any value to grow by more than these two bits, then the process can 
be run without loss of data. Afterward, however, the block must be 
adjusted to replace the guard bits before the next process. 

Figure C.5 shows the data after processing but before adjustment. The 
block floating-point adjustment is performed as follows. Initially, the 
value of SB is -2, corresponding to the 2 guard bits. During processing, 
each resulting data value is inspected by the EXPADJ instruction, which 
counts the number of redundant sign bits and adjusts SB is if the number 
of redundant sign bits is less than 2. In this example, SB=-1 after 
processing, indicating that the block of data must be shifted right one bit 
to maintain the 2 guard bits. If SB were 0 after processing, the block would 
have to be shifted two bits right. In either case, the block exponent is 
updated to reflect the shift. 


1. Check for Bit Growth 



1 

/ 

Guard Bit 

0x1 FFF 

= 0001 

1111 

1111 

0x3FFF 

= 0011 

1111 

1111 

0x07FF 

= 0000 

1 

0111 

1111 


Sign Bit 


EXPADJ instruction checks 
exponent, adjusts SB 

1111 — ► Exponent = -2 SB = -2 

1111 — ► Exponent = -1 SB = -1 

1111 — ► Exponents -4 SB = -1 


2. Shift Right to Restore Guard Bits 


2 Guard Bits 

/ 


OxOFFF 

= 0000 

1111 

1111 

1111 

0x1 FFF 

= 0001 

1111 

1111 

1111 

0x03FF 

= 0000 

0011 

1111 

1111 


Sign Bit 

Figure C.5 Block Floating-Point Adjustment 






Interrupt Vector Addresses 


D.1 INTERRUPT VECTOR ADDRESSES 

Tables D.1-D.6 show the interrupts and associated vector addresses for 
each processor of the ADSP-2100 family. Note that SPORT1 can be 
configured as either a serial port or as a collection of control pins 
including two external interrupt inputs, IRQO and IRQ1. 

The interrupt vector locations are spaced four program memory locations 
apart — this allows short interrupt service routines to be coded in place, 
with no jump to the service routine required. For interrupt service 
routines with more than four instructions, however, program control must 
be transferred to the service routine by means of a jump instruction placed 
at the interrupt vector location. 


Interrup t Source 
RESET startup 
IRQ2 

SPORTO Transmit 

SPORTO Receive 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 
0x0000 

0x0004 (highest priority) 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 (lowest priority) 


Table D.1 ADSP-21 01/21 15 Interrupts & Interrupt Vector Addresses 


Interrup t Source 
RESET startup 

IRQ2 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 
0x0000 

0x0004 (highest priority) 

0x0010 

0x0014 

0x0018 (lowest priority) 


Table D.2 ADSP-2105 Interrupts & Interrupt Vector Addresses 




Interrup t Source 
RESET startup 
IRQ2 

HIP Write (from Host) 
HIP Read (to Host) 
SPORTO Transmit 

SPORTO Receive 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 
0x0000 

0x0004 (highest priority) 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 

0x001 C 

0x0020 (lowest priority) 


Table D.3 ADSP-2111 Interrupts & Interrupt Vector Addresses 


Interrup t Source 

RESET startup (or powerup w/PUCR=l) 
Powerdown (non-maskable) 


IRQ2 

HIP Write (from Host) 
HIP Read (to Host) 
SPORTO Transmit 
SPORTO Receive 
Software Interrupt 1 

Software Interrupt 2 

SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 

0x0000 (highest priority) 

0x002C 

0x0004 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 

0x001 C 

0x0020 

0x0024 

0x0028 (lowest priority) 


Table D.4 ADSP-2171 Interrupts & Interrupt Vector Addresses 


Interrup t Source 

RESET startup (or powerup w/PUCR=l) 
Powerdown (non-maskable) 

IRQ2 

IRQL1 (level-sensitive) 

IRQL0 (level-sensitive) 

SPORTO Transmit 
SPOR TO Receive 
IRQE (edge-sensitive) 

Byte DMA (BDMA) Interru pt 
SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 

0x0000 (highest priority) 

0x002C 

0x0004 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 

0x001 C 

0x0020 

0x0024 

0x0028 (lowest priority) 


Table D.5 ADSP-2181 Interrupts & Interrupt Vector Addresses 



Interrup t Source 

RESET startup (or powerup w/PUCR=l) 
Powerdown (non-maskable) 

IRQ2 

HIP Write (from Host) 

HIP Read (to Host) 

SPORTO Transmit 
SPORTO Receive 
Analog (DAC) Transmit 
Analog (ADC) Recei ve 
SPORT1 Transmit o r IRQ 1 
SPORT1 Receive or IRQO 
Timer 


Interrupt Vector Address 

0x0000 (highest priority) 

0x002C 

0x0004 

0x0008 

OxOOOC 

0x0010 

0x0014 

0x0018 

OxOOlC 

0x0020 

0x0024 

0x0028 (lowest priority) 


Table D.6 ADSP-21msp58/59 Interrupts & Interrupt Vector Addresses 




Control/Status Registers H E 


E.1 OVERVIEW 

This appendix shows bit definitions for 1) the memory-mapped control 
registers and 2) other (non-memory-mapped) control and status registers 
of all ADSP-21xx processors. The memory-mapped registers are listed in 
descending address order. Default bit values at reset are shown; if no 
value is shown, the bit is undefined at reset. Reserved bits are shown on a 
gray field. These bits should always be written with zeros. 


Memory-Mapped Registers 


System Control Register 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 4 3 

2 

1 0 



mi 

0 

0 

1 

0 

ll 

1 

0 

J 

1 

0 

1 1 

* 1 1 

i i 

1 

1 1 

1 1 

i 1 


DM(Qx3FFF) 


3PORTO Enable | 

I = enabled, 0 = disabled 
set to 0 for ADSP-2105) 

5PORT1 Enable 

I = enabled, 0 = disabled 

5PORT1 Configure 

= serial port 

l = FI, FO, IRQO, IRQ1, SCLK 

BFORCE 
Boot Force Bit 
(not on ADSP-2181) 



BPAGE 

Boot Page Select 
(not on ADSP-2181) 


* Bit 5 initialized to 1 on ADSP-2171, ADSP-21 msp58/59 
Bit 5 initialized to 0 on ADSP-21 01, ADSP-2105, ADSP-21 15, ADSP-21 11 


E-1 





HOST INTERFACE PORT 
(ADSP-2171, ADSP-2111, ADSP-21msp5x) 


0X3FE8 HMASK 


' 1 0X3FE5 

Status Registers 0x3FE4 


0x3FE7 HSR7 

0x3FE6 HSR6 


Data Registers 
HDRS 
HDR4 
HDR3 
HDR2 
HDR1 
HDRO 



IDMA PORT 
BDMA PORT 

PROGRAMMABLE FLAGS 
(ADSP-2181) 


IDMA Registers 

IDMA Control 
Register 


Programmable 
Flag Registers 


0x3FE5 PFDATA 


BDMA Registers 
0x3FE4 BWCOUNT 
0x3FE3 BDMA Control 
0x3FE2 BEAD 

0x3FE1 BIAD 











































Memory-Mapped Registers 


Waitstate Control Register 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



DWAIT4 DWAIT3 DWAIT2 DWAIT1 DWAITO 


DM(0x3FFE) 


or or or or or 

DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAITO 

(ADSP-2181) (ADSP-2181) (ADSP-2181) (ADSP-2181) (ADSP-2181) 


ROM Enable (ADSP-2172, ADSP-21 msp59) 
1 = enable 
0 = disable 


Timer Registers 


15 14 

13 

12 11 

10 

9 

8 

7 6 5 4 3 2 1 0 

i 

1 



i i i 

TPERIOD 

l l 1 

i i i i i i i i 

Period Register 

i i i i i i i i 



TCOUNT Counter Register 

0 0 . 

0 

0 | 

0 

||| 

m 

i i i i i i i 

TSCALE Scaling Register 

1 1 1 1 1 1 1 


DM(0x3FFD) 

DM(0x3FFC) 

DM(0x3FFB) 


Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E-3 




Memory-Mapped Registers 


SPORTO Control Register 


(Noton ADSP-21 05) 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

E 

0 

0 

0 

□ 

0 

E 

0 

E 

0 

0 

0 

E 

1 

0 

1 

0 

J 

3 


DM(0x3FF6) 


MCE - 1 

Multichannel Enable 

ISCLK 

Internal Serial Clock Generation 

RFSR 

Receive Frame Sync Required 

RFSW 

Receive Frame Sync Width 

MFD 

Multichannel Frame Delay 
(Only If Multichannel Mode Enabled ) 

TFSR 

Transmit Frame Sync Required 

TFSW 

Transmit Frame Sync Width 



SLEN (Serial Word Lengt 
DTYPE Data Format 


00=right justify, zero-fill unused MSBs 
01 =right justify, sign-extend into unuse 
10=compand using p-law 
11=compand using A-law 


INVRFS 

Invert Receive Frame Sync 


INVTFS 

Invert Transmit Frame Sync 

(or INVTDV Invert Transmit Data Valid) 

(Only If Multichannel Mode Enabled ) 


IRFS 

Internal Receive Frame Sync Enable 


ITFS 

Internal Transmit Frame Sync Enable 
(or MCL Multichannel Length: 
1=32 words, 0=24 words) 
(Only If Multichannel Mode Enabled ) 


Receive 

Word 

Enables 


SPORTO Multichannel Word Enables (Not on ADSP-2105) 

DM(0x3FFA) 


Transmit 

Word 

Enables 


31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 

19 

18 

17 

16 





0 

0 










□ 

15 

14 

13 

12 

ii 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0 







L 



L 





0 

31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 



19 

18 

_ 

17 

16 

□ 















0 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

c 

0 

_ 

_ 

_ 

_ 

_ 

_ 

0 

_ 

_ 

_ 

_ 

_ 

_ 

0 


DM(0x3FF9) 


DM(0x3FF8) 


DM(0x3FF7) 


E - 4 


1 = channel enabled 
0 = channel ignored 




Memory-Mapped Registers 


SPORTO Autobuffer Control Register (Not on ADSP-2105) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



DM(0x3FF3) 



TIREG TMREG RIREG RMREG 


BIASRND 

MAC Biased Rounding Control Bit 
(ADSP-2171, ADSP-2181, ADSP-21 msp58/59 only) 


I RBUF 

Receive Autobuffering Enable 


TBUF 

Transmit Autobuffering Enable 


CLKODIS 

CLKOUT Disable Control Bit 

(ADSP-2171, ADSP-2181, ADSP-21 msp58/59 only) 


SPORTO SCLKDIV 
Serial Clock Divide Modulus 


(Not on ADSP-2105) 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


i — i — i — i — i — i — i — i — i — i — i — i — i — i — r 

J I I I I I I I I I I I I I L 


DM(0x3FF5) 


SPORTO RFSDIV 

Receive Frame Sync Divide Modulus 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


i — i — i — i — i — i — i — i — i — i — i — i — i — i — r 

J i i i i i i i i i i i i i L 


DM(0x3FF4) 


CLKOUT frequency 

SCLKDIV = 4 y - 1 

2 * (SCLK frequency) 


SCLK frequency 

RFSDIV = 3 1 - 1 

RFS frequency 


Default bit values at reset are shown; if no value is shown , the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E-5 




Memory-Mapped Registers 


SP0RT1 Control Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



DM(0x3FF2) 


Flag Out (read-only) — 1 

ISCLK 

Internal Serial Clock Generation 

RFSR 

Receive Frame Sync Required 

RFSW 

Receive Frame Sync Width 

TFSR 

Transmit Frame Sync Required 

TFSW 

Transmit Frame Sync Width 

ITFS 

Internal Transmit Frame Sync Enable 



SLEN (Serial Word Length -1) 


I DTYPE Data Format 

00=right justify, zero-fill unused MSBs 
01 =right justify, sign-extend into unused MSI 
10=compand using p-law 
11=compand using A-law 

INVRFS 

Invert Receive Frame Sync 


INVTFS 

Invert Transmit Frame Sync 
IRFS 

Internal Receive Frame Sync Enable 


SPORT1 SCLKDIV 
Serial Clock Divide Modulus 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


i — i — i — i — i — i — i — i — i — i — i — i — i — i — r 

J I J I I I I I I I I I J I L 


DM(0x3FF1) 


SPORT1 RFSDIV 

Receive Frame Sync Divide Modulus 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


i — i — i — i — i — i — i — i — i — i — i — i — i — i — r 

J I I I I I I I I I I I L I L 


DM(0x3FF0) 


CLKOUT frequency 

SCLKDIV = v M vy - l 

2 * (SCLK frequency) 


RFSDIV = 


SCLK frequency 
RFS frequency 


1 


E-6 




Memory-Mapped Registers 


SP0RT1 Autobuffer Control Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 


(Not on ADSP-21 msp5x) 
o 


XTALDIS 

XTAL Pin Disable During Powerdown 
1=disabled, 0=enabled 
(XTAL pin should be disabled when 
no external crystal is connected) 

XTALDELAY 
y Startup From Powerdown 4096 Cycles 
1=delay, 0=no delay 
ise delay to allow internal phase locked 
loop or external oscillator to stabilize) 

PDFORCE 
Powerdown Force 
1=force processor to vector to 
powerdown interrupt 

PUCR 

Powerup Context Reset 
1=soft reset (clear context) 
Osresume execution 


i r 



n r 

J L 


DM(0x3FEF) 


RBUF 

Receive Autobuffer Enable 
TBUF 

Transmit Autobuffer Enable 
RMREG 

Receive M register 
RIREG 

Receive I register 
TMREG 

Transmit M register 
TIREG 

Transmit I register 


XTALDIS, XTALDELAY, PDFORCE, and PUCR are only on the 
ADSP-21 71, ADSP-2181, and ADSP-21 msp58/59 processors. 


Analog Autobuffer Control Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 


(ADSP-21 msp5x only) 
o 


0 0 DM(0x3FEF) 


XTALDIS 1 

XTAL Pin Disable During Powerdown 
1=disabled, 0=enabled 
(XTAL pin should be disabled when 
no external crystal is connected) 

XTALDELAY 

Delay Startup From Powerdown 4096 Cycles 
1=delay, 0=no delay 


PDFORCE 
Powerdown Force 
1=force processor to vector to 
powerdown Interrupt 

PUCR 

Powerup Context Reset 
1=soft reset, 0=resume execution 



1 ARBUF 

ADC Receive Autobuffer Enable 
ATBUF 

DAC Transmit Autobuffer Enable 

ARMREG 

Receive M register 

ARIREG 

Receive I register 

ATMREG 

Transmit M register 

ATIREG 

Transmit I register 


Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E-7 




Memory-Mapped Registers 


Analog Control Register (ADSP-21 msp5x only) 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


ADC Offset 
IGO 

ADC Input Gain (ADC PGA) 

DABY 

DAC High Pass Filter Bypass 
1=bypass, 0=insert 

ADBY 

ADC High Pass Filter Bypass 
1=bypass, 0=insert 


OG2 0G1 OGO 




DM(0x3FEE) 


IG1 

ADC Input Gain (ADC PG 
IMS 

ADC Input Multiplexer Sc 
1=AUX input, 0=NORM ir 

OG2, OG1, OGO 
DAC Output Gain (DAC F 

APWD 


IG1, IGO 

ADC Input Gain (ADC PGA) 


Gain 

IG1 

IGO 

OdB 

0 

0 

+6 dB 

0 

1 

+20 dB 

1 

0 

+26 dB 

1 

1 


OG2, OG1, OGO 

DAC Output Gain (DAC PGA) 


Gain 

0G2 

OG1 

OGO 

+6dB 

0 

0 

0 

+3dB 

0 

0 

1 

OdB 

0 

1 

0 

-3dB 

0 

1 

1 

-6 dB 

1 

0 

0 

-OdB 

1 

0 

1 

-12 dB 

1 

1 

0 

-15 dB 

1 

1 

1 


Analog Interface Powerd 
0=powerdown, 1=enable 
(Set both bits to 1 to 
enable analog interface) 


Analog Data Registers 


(ADSP-21 msp5x only) 


ADC Receive Data 


15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

□ 















□ 

15 

14 

13 

12 

11 

DAC Transmit Data 

10 9 8 7 6 5 

4 

3 

2 

1 

0 


□ 


C 

c 








□ 

□ 

□ 

□ 


DM(0x3FED) 


DM(0x3FEC) 


E-8 





Memory-Mapped Registers 


HM ASK Interrupt Mask Register (ADSP-21 71, ADSP-21 1 1, 

ADSP-21msp5x only) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


| 0 | 0 [ 0 | 0 1 0 | 0 | 0 | 0 1 0 [ 0 | o | o~[ 


DM(0x3FE8) 


ost HDR5 Read 
ost HDR4 Read 
ost HDR3 Read 
ost HDR2 Read 
ost HDR1 Read 
ost HDRO Read 



Host 


HDRO 

HDR1 

HDR2 

HDR3 

HDR4 

HDR5 


Write 

Write 

Write 

Write 

Write 

Write 


HSR7 Status Register (ADSP-21 71, ADSP-21 1 1, 

ADSP-21 msp5x only) 


15 

14 

13 

12 

ii 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

ll 

0 

HI 

Id 

it 

0 

it 

i 

□ 

it 

it 

id 

it 

it 

0 

it 


DM(0x3FE7) 


OVERWRITE 

MODE 

SOFTWARE 

RESET 



HDRO Write 
HDR1 Write 
HDR2 Write 
HDR3 Write 
HDR4 Write 
HDR5 Write 


Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 




Memory-Mapped Registers 


HSR6 Status Register 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 


(ADSP-2171, ADSP-21 1 1 
ADSP-21msp5x only) 

1 0 


111 0 °l° 

0 

o|o 

Hi 

) | 0 | 0 

) 0 0 


DM(0x3FE6) 


21 xx HDR5 Write 
21 xx HDR4 Write 
21 xx HDR3 Write 
21 xx HDR2 Write 
21 xx HDR1 Write 
21 xx HDRO Write 




Host HDRO Write 
Host HDR1 Write 
Host HDR2 Write 
Host HDR3 Write 
Host HDR4 Write 
Host HDR5 Write 


E — 10 


HIP Data Registers 

HDR5 


(ADSP-21 71, ADSP-21 1 1, 
ADSP-21 msp5x only) 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 






— 












DM(0x3FE5) 

HDR4 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


















DM(0x3FE4) 

HDR3 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


















DM(0x3FE3) 

HDR2 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


















DM(0x3FE2) 

HDR1 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



















DM(0x3FE1) 

HDRO 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


















DM(0x3FE0) 










Memory-Mapped Registers 


Programmable Flag & Composite Select Control (ADSP-2181 only) 


15 14 13 12 11 10 9 8 



DM(0x3FE6) 


Programmable Flag Data 

15 14 13 12 11 10 9 8 7 6 5 4 


i — i — r 


(ADSP-2181 only) 
0 


J_ 1 L 


DM(0x3FE5) 


-PFDATA 


E- 11 

Default bit values at reset are shown ; if no value is shown, the bit is undefined at reset. 

Reserved bits are shown on a gray field — these bits should always be written with zeros. 




Memory-Mapped Registers 


BDMA Control 

15 14 13 12 11 10 9 8 7 6 5 


(ADSP-2181 only) 


BMPAGE 


BTYPE 

00 

01 

10 

11 

Internal Memory Space 

PM 

DM 

DM 

DM 

Word Size 

24 

16 

8 

8 

Alignment 

full 

word 

full 

word 

MSB 

LSB 


1 0 

— I — 


DM(0x3FE3) 




BTYPE (see table) 

BDIR 

0 = load from BM 

1 = store to BM 

BCR 

0 = run during BDMA 

1 = halt during BDMA, 
context reset when done 


BDMA Word Count 
(MMAP=0 and BMODE=0) 

15 14 13 12 11 10 9 8 7 6 5 4 3 


11 


I | | | | | 1 

00000000 

_l I I I I I I 


or 


(ADSP-2181 only) 


1 0 

j , j 1 1 — 

10 0 ooo 

I I I I I 


BDMA Word Count 
(MMAP=1 or BMODE=1) 

15 14 13 12 11 10 9 8 7 6 5 4 


_ I I \ 

0 0 0 0 

I I i 


7% 


BWCOUNT 


1 0 

ITT" 


J I L 


E — 12 


BWCOUNT 


DM(0x3FE4) 


DM(0x3FE4) 





Memory-Mapped Registers 


BDMA External Address 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 


(ADSP-2181 only) 


7 r 7 r “n~ T 7 T "n T n' T 7 r n T ' n T~ ' ' n I'Tl' 7 T 7 

0000000000 0000 


DM(0x3FE2) 


BEAD 


BDMA Internal Address (ADSP-2181 only) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


nr 

0 

i i i i — i — i — i — i — i — i — i — i — i — 

0000000000 0000 

1 1 1 1 1 1 1 1 1 1 1 1 1 

> 



BIAD 


DM(0x3FE1) 


IDMA Control (ADSP-2181 only) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


DM(0x3FE0) 



IDMAD 

Destination memory type 
0=PM, 1=DM 


IDMAA 

Starting address 


Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E — 13 




Non-Memory-Mapped Registers 


ASTAT 


7 6 5 4 3 2 1 0 

[ 7 " 0 0 0 | 0 0 0 0 

SS MV AQ AS AC AV AN AZ 



ALU Result Zero 
ALU Result Negative 
ALU Overflow 
ALU Carry 
ALU X Input Sign 
ALU Quotient 
MAC Overflow 
Shifter Input Sign 


SSTAT (read-only) 


7 

6 

5 

4 3 

2 

1 

0 

E 

1 

0 

'\° 

1 

0 

□ 



PC Stack Empty 
PC Stack Overflow 
Count Stack Empty 
Count Stack Overflow 
Status Stack Empty 
Status Stack Overflow 
Loop Stack Empty 
Loop Stack Overflow 


MSTAT 


6 5 4 3 2 1 0 




Register Bank Select 
0=primary, 1=secondary 

Bit-Reverse Addressing Enable (DAG1) 

ALU Overflow Latch Mode Enable 

AR Saturation Mode Enable 

MAC Result Placement 
0=fractional, 1=integer 

Timer Enable 

Go Mode Enable 


ICNTL 

4 3 2 1 0 

13TT 


*— IRQO Sensitivity 

— IRQ1 Sensitivity 

— IRQ2 Sensitivity 

— Interrupt Nesting 
1=enable 
0=disable 


E — 14 





Non-Memory-Mapped Registers 


IMASK 

5 4 3 2 1 0 


0 0 I 0 0 0 0 



INTERRUPT ENABLES 

1 = enable 
0 = disable (mask) 


ADSP-2101 
ADSP-2105 
ADSP-21 15 


Timer 

SP0RT1 Receive or IRQO 
SPORT1 Transmit or IRQ1 

SPORTO Receive (must be set to 0 for ADSP-2105) 
SPORTO T ransmit (must be set to 0 for ADSP-2105) 
IRQ2 


IFC (write-only) 

11 10 987654321 0 

|o[o|o|o|o|o|o|o|o|o|o|o 


ADSP-2101 
ADSP-2105 
ADSP-21 15 
ADSP-21 11 


INTERRUPT FORCE BITS 


IRQ2 — 1 
SPORTO Transmit — 
fsf be set to 0 for ADSP-2105) 

SPORTO Receive — 
st be set to 0 for ADSP-2105) 

SPORT1 Transmit or IRQ1 — 
SPORT1 Receive or IRQO — 
Timer — 


INTERRUPT CLEAR BITS 

— Timer 

— SPORT1 Receive or IRQO 

— SPORT1 Transmit or IRQ1 

— SPORTO Receive 

(must be set to 0 for ADSP-2105) 

— SPORTO Transmit 

(must be set to 0 for ADSP-2105) 

— TRQ2 


Default bit values at reset are shown ; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E- 15 



Non-Memory-Mapped Registers 


IMASK 

7 6 5 4 3 2 1 0 

o|o|o|o|o|o|o|o 


ADSP-21 1 1 

INTERRUPT ENABLES 
1 = enable 
0 = disable (mask) 


IRQ2 
HIP Write 
HIP Read 


*— Timer 

— SPORT1 Receive or IRQO 

— SPORT1 Transmit or IRQ1 

— SPORTO Receive 

— SPORTO Transmit 


E — 16 




Non-Memory-Mapped Registers 


ADSP-2181 

INTERRUPT ENABLES 
1 = enable 
0 = disable (mask) 


Timer 

SP0RT1 Receive or IRQO 
SPORT1 Transmit or IRQ1 
BDMA interrupt 
IRQE 


IFC (write-only) ADSP-2181 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



INTERRUPT FORCE BITS 
IRQ2 

SPORTO Transmit 
SPORTO Receive 

Trqe 

BDMA Interrupt 
SPORT1 Transmit or IRQ1 
SPORT1 Receive or IRQO 
Timer 




Default bit values at reset are shown ; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E — 17 



Non-Memory-Mapped Registers 


IMASK 


ADSP-2171 


9876543210 

INTERRUPT ENABLES 
1 = enable 
0 = disable (mask) 



IRQ2 — 1 
HIP Write — 
HIP Read — 
SPORTO Transmit — 
SPORTO Receive — 


*— Timer 

— SPORT1 Receive or IRQO 

— SPORT1 Transmit or IRQ1 

— Software Interrupt 0 

— Software Interrupt 1 


IFC (write-only) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



ADSP-2171 


INTERRUPT FORCE BITS 


IRQ2 — I 

SPORTO Transmit 

SPORTO Receive 

Software Interrupt 1 — 

Software Interrupt 0 

3PORT1 Transmit or IRQ1 

SPORT1 Receive or IRQO 

Timer — 


INTERRUPT CLEAR BITS 

— Timer 

— SPORT1 Receive or IRQO 

— SPORT1 Transmit or IRQl 

— Software Interrupt 0 

— Software Interrupt 1 

— SPORTO Receive 

— SPORTO Transmit 

— 1RQ2 


E — 18 



Non-Memory-Mapped Registers 


IMASK 


ADSP-21msp5x 


9876543210 

INTERRUPT ENABLES 
1 = enable 
0 = disable (mask) 



IRQ2 — 1 
HIP Write — 
HIP Read — 
SPORTO Transmit — 
SPORTO Receive — 


L_ Timer 

— SPORT1 Receive or IRQO 

— SPORT1 Transmit or IRQ1 

— ADC Receive 

— DAC Transmit 


INTERRUPT FORCE BITS 

IRQ? 

SPORTO Transmit 
SPORTO Receive 

DAC Transmit 
ADC Receive 
SPORT1 Transmit or IRQ1 
SPORT1 Receive or IRQO 
Timer 


IFC (write-only) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


ooooloooolooooloooo 




ADSP-21msp5x 


INTERRUPT CLEAR BITS 


Timer 

SPORT1 Receive or IRQO 
SPORT1 Transmit or IRQ1 
ADC Receive 
DAC Transmit 
SPORTO Receive 
SPORTO Transmit 
IRQ? 


Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. 
Reserved bits are shown on a gray field — these bits should always be written with zeros. 


E — 19 




(ADSP-2181) 

3 3 


DMOVLAY PMOVLAY 


Width and depth vary with processor 


MAC 





RXO 

■ 

TXO 


L 1 lB 

imai^amna 


BUS EXCHANGE 



Multichannel enables 
0x3FFA RX 31-16 

0x3FF9 RX 15-0 

0x3FF8 TX 31-16 

0x3FF7 TX 15-0 

SPORTO Control 
0x3FF6 Control 
0x3FF5 SCLKDIV 


0x3FF3 Autobuffer 


ANALOG INTERFACE 
(ADSP-21msp5x) 



0x3FF1 SCLKDIV 
0x3FF0 RFSDIV 
0x3FEF Autobuffer 


HOST INTERFACE PORT 
(ADSP-2171, ADSP-21 1 1, ADSP-21msp5x) 


0x3FE8 HMASK 


1 1 0x3FE5 

Status Registers 0x3FE4 


Data Registers 
HDR5 
HDR4 
HDR3 
HDR2 
HDR1 
HDRO 



IDMA PORT 
BDMA PORT 

PROGRAMMABLE FLAGS 
(ADSP-2181) 


IDMA Registers Bl 

IDMA Control 0x3FE4 H 

Register I 


Programmable 
Flag Registers 



BDMA Registers 

0x3FE4 

BWCOUNT 

0x3FE3 

BDMA Control 

0x3FE2 

BEAD 

0x3FE1 

BIAD 


0x3FE5 PFDATA 













































Index 


1.15 format 2-2 

(x-law 1-2, 5-15, 5-23 

A 


A-law 1-2,5-23 

A/D converter 1-3, 1-10, 3-18, 8-1, 8-2, 

8-3, 8-4, 8-9, 10-14 

AC (carry) 2-2, 2-5, 2-8, 2-13, 2-36 

AC coupling 8-18 

Accumulator 1-5 

ADC, DAC interrupts 8-12 

ADC 1-3, 1-10, 3-18, 8-1, 8-2, 8-3, 8-4, 8-9 

ADC interface 13-10 

Add with carry 2-8 

Address generators 1-6, 1-7 

Address pointers 1-7 

ADSP-2181 9-13, 15-18 

AF register 2-5 

Alternate framing mode 5-13 

ALU 1-1, 1-6, 2-5, 2-8, 3-21, 

3-24, 12-2, 12-6, 15-9, B-l 

ALU arithmetic 2-2 

ALU carry (AC) 2-26 

ALU overflow (AV) 3-23, 3-24 

ALU overflow latch mode 2-8, 2-9 

ALU saturation mode 2-8, 2-9 

ALU status 2-13 

AN (negative) 2-2, 2-5, 2-13 

Analog control register 8-5, 8-6, 8-8, 8-9, 8-10 

Analog interface 1-3, 1-10 

Analog loopback program 8-12 

Analog-to-digital conversion 13-5 

AQ (quotient) 2-5, 2-9, 2-10, 2-13 

AR register 2-8, 2-22, 2-36 

AR saturation 3-23, 3-24 

Arithmetic formats 2-4 

Arithmetic operation 3-24 

Arithmetic shift 2-3, 2-22, 2-28 

AS (sign) 2-5, 2-13 

ASHIFT 2-31 

Assembler 1-10 

Assembler directives 12-10, 14-1 


ASTAT 2-10, 2-13, 2-19, 2-24, 

2-26, 2-36, 3-21, 3-24, 12-5 

Autobuffer service 5-39 

Autobuffer timing 5-37 

Autobuffering 5-3, 5-4, 5-26, 5-32, 5-38, 5-40, 


...5-41, 8-1, 8-9, 8-10, 8-11, 8-12, 
8-13, 8-14, 8-15, 9-5, 9-23, 15-18 


Autobuffer control register 5-27 

AV (overflow) ....2-2, 2-5, 2-8, 2-9, 2-13, 2-26, 2-36 

AX0 register 2-5 

AX1 register 2-5 

AY0 register 2-5 

AY 1 register ! 2-5 

AZ (zero) 2-5, 2-13 


6 


Bank select 

Barrel shifter 

Base architecture 

BCR 

BDMA 


3-23 

1 - 6 , 2-22 

1 - 1 , 1-6 

9-13, 11-6, 11-7 
15-18 


BDMA booting 9-13, 11-9 

BDMA context reset 11-6, 11-7 

BDMA interrupt 11-7 

BEAD 11-4 

BFORCE bit 10-16 

BIAD 11-4 


Binary multiplication . 

Binary string 

Bit-reverse addressing 

Block exponent 

Block floating-point .... 

BMO DE pin 

BMS 

Boot address 


C-3 

2-1 

1-7,3-23,4-2,4-6,14-18 

2-26 

1-5, 14-19, C-5 

7-3, 7-16, 10-15, 11-9, 11-12 

1-8, 7-16, 10-17 

10-18 


Boot loading 13-2, 13-5 

Boot loading sequence 10-17 

Boot loading through the HIP 7-16 

Boot memory 10-1, 10-15, 10-17 

Boot pages 10-15 

Booting operation 9-4 

BP AGE 10-16 


X-1 




Branching 3-1 

BTYPE 11-9 

Buffer length 4-5 

Bus exchange 1-5, 1-8, 2-15, 4-1, 4-9, 12-6 

Bus grant (BG) 3-18, 9-15 

Bus request (BR) 5-38, 10-15, 10-21, 13-2 

Buses 1-3, 1-8 

BWAIT 10-17 

BWCOUNT 9-13, 11-7 

Byte memory 11-9 


c 


C Compiler 1-10 

C language 14-3 

CALL 3-4, 3-8, 3-9, 3-24 

Carry (AC) 2-2, 2-5, 2-8, 2-13, 2-36 

Carry-in (Cl) 2-5 

Chip enable 10-3 


Circular buffer addressing.... 1-5, 1-7, 4-1, 4-3, 4-8 


CLKIN 9-1, 9-3, 9-4 

CLKOUT 9-2, 9-3, 9-4, 10-2 


Clock frequency 8-9 

Clock signals 9-1 

Clock synchronization (SPORT) 5-35 

Clock synchronization delay (SPORT) 5-34 

CNTR register 3-4, 3-9, 12-4 

Codec interface 13-5 

Companding 1-2, 5-5, 5-15, 5-23, 5-24, 

5-25, 5-32, 5-36, 5-37, 5-42 


Computation with data register move 15-7 

Computation with memory read 15-6 

Computation with memory write 15-6 

Computational units 1-6, 3-23, 12-1, 12-6 

Condition 3-20 

Condition logic 3-3 

Conditional instructions 3-24 

Configuring interrupts 3-14 

Context reset 11-7 

Context switching 3-12 

Continuous transmission 5-20 

Control/status registers .1-12, E-l 

Core architecture 1-5 


Count stack 3-4, 3-5, 12-5 

Counter expired (CE) 3-4, 3-6, 3-9 

Cycle stealing 11-25 


D 

D/A 10-14 

DAC 1-3 

DAC interface 13-8 

DAG1 1-7, 4-2, 12-2 

DAG2 1-7, 3-3, 3-4, 3-8, 4-2, 12-2 

Data address generators 4-1, 12-2 

Data bus 4-1 

Data memory 1-7, 1-8, 10-1 

Data memory address bus 1-3, 1-8 

Data memory data bus 1-3, 1-8 

Data memory interface 10-10 

Data memory read 15-6 

Data structures 4-7 

Data transfer 4-1 

Denormalization 1-6 

Denormalize 2-31 

Derive block exponent 2-29 

Derive exponent 2-22, 2-26 

Development tools 14-2 

Digital-to-analog conversion 13-5 

Direct addressing 1-8 

Divide primitives 2-9 

Division exceptions B-l 

Division 2-9 

DIVQ 2-10, 2-11, B-l 

DIVS 2-2, 2-9, 2-10, B-l 

DMA 15-18 

DMA bus 1-8, 10-1 

DMD bus 1-8, 2-19, 2-22, 3-4, 

3-5, 3-20, 4-10, 10-1 

DMD-PMD bus exchange 2-15, 4-1, 4-9, 4-10 

DMOVLAY 10-31 

DMS 1-8 

DO UNTIL 3-4, 3-5, 3-6, 3-8, 3-9, 3-12, 12-5 

DR input 5-2, 5-36 

dreg 15-12, 15-14 

DT output 5-2 

Dual operand fetches 1-2, 1-5, 1-7 


Edge-sensitive 3-15, 3-16, 3-18 

Edge-sensitive interrupts 9-14 

End-of-loop 3-7, 3-10 

EPROM 1-4, 10-17 


X- 2 



EXP 2-33 

EXPADJ 2-29 

Exponent compare logic 2-22 

Exponent detector 2-22, 2-26, 2-27 

External address bus 1-3, 1-8 

External clock 5-8, 9-21 

External data bus 1-3, 1-8 

External interrupts 9-14 

External memory 5-38, 10-2 

External SCLK 5-8 

Extra cycles 15-18 

EZ-ICE emulator 11-26 


F 


HMDO 7-3, 7-4 

HMD1 7-4 

Hold offs 11-25 

Host 1-2 

Host data bus 7-4 

Host handshaking 7-7 


Host interface port (HIP) ...1-2, 1-9, 3-15, 7-1, 7-4, 
9-4, 10-15, 12-2, 13-13 


Host interface timing 7-11 

Host read strobe 7-4 

Host write strobe 7-4 

HSEL 7-3 

HSIZE 7-3, 7-11 


HSR registers 


7-4, 7-5, 9-25 


Fast fourier transform (FFT) 14-1, 14-11 

Fast start-up 9-22 

FIR filter ..14-1,14-4 

Flag In (FI) 1-9, 3-24, 9-1 

Flag Out (FO) 1-9, 9-1 

Flag pins 9-15 

Floating-point 2-33 


Fractional mode 2-2, 2-3, 3-23, 3-24, C-l, C-4 

Frame synchronization ...5-2, 5-5, 5-10, 5-11, 5-12, 


5-14, 5-15, 5-30, 5-34, 9-23 


Framing 5-3, 5-16 

Full duplex operation 5-34 


G 


GO mode 

3-23, 3-24, 5-38 

H 

HACK 

7-3, 7-7, 7-9 

Harvard architecture 

1-2,10-1 

HDR overwrite mode 

7-7, 7-9 

HDR registers 

7-4, 7-5, 7-6, 7-7 

Hl-extend (HIX) 

2-26, 2-36 

HI/LO reference signal 

2-22, 2-24 

HIP configuration modes ... 

7-3 

HIP data registers 

,3-15, 7-4, 7-5, 7-6, 7-7 

HIP during powerdown 

9-24 

HIP interrupt 

....3-18, 7-9, 7-10, 7-11 

HIP pin summary 

7-2 

HIP read interrupt 

7-4 

HIP status registers 

7-6 

HIP status synchronization 

7-8 

HIP timing 

..7-12, 7-13, 7-14, 7-15 

HIP write interrupt 

7-4 

HMASK register 3-15, 7-4, 7-10, 7-11, 12-8 


I registers 4-2, 4-3, 5-26, 5-28, 8-14, 12-2 

IACK 11-12,11-13,11-25 

ICNTL register ....3-14, 3-15, 3-16, 3-20, 9-14, 12-4 

IDLE instruction 3-7, 3-10, 5-26, 9-15, 

9-19, 9-26, 9-30 

IDMA 11-12, 15-18 

IDMA booting 1 1-24 

IDMA control register 11-14, 11-15, 11-16 

IDMA hold offs 11-25 

IFC register 3-14, 3-18, 3-20, 12-4 

HR filter 14-1,14-6 

IMASK register 3-14, 3-15, 3-16, 3-19, 

3-20, 7-10, 8-12, 9-14, 12-4 

Immediate shifts 2-30 

Indirect addressing 1-8, 4-3, 12-2 

Indirect jumps 12-2 

Input formats 2-18 

Input registers 1-7 

Instruction completion latencies 5-38, 15-18 

Instruction set 15-1, A-l 

Integer 3-23, 3-24, C-l 

Integer mode 2-3, C-4 

Internal buses 1-8 

Internal memory 1-2 

Internal oscillator 9-22 

Interrupt control register 3-15 

Interrupt controller 3-1, 3-3, 3-11 

Interrupt force & clear register ..3-15, 3-18 

Interrupt latencies 3-19, 5-42 

Interrupt mask register 3-16 

Interrupt nesting 3-16 

Interrupt request 5-40, 9-1, 9-14 

Interrupt sensitivity 9-14 


X-3 



Interrupt service 3-12, 3-14, 3-16, 

3-18, 3-20, 5-39 

Interrupt vector 3-11, 3-12, 3-13, 

3-14, D-l, D-2, D-3 

Interrupts 1-9, 3-4, 3-16, 9-24, 9-30, 12-4, 12-11 

Interrupts pending 3-18 

Interval timer 3-18, 3-23, 3-24 

INVRFS 5-14, 5-16, 5-32 

INVTDV 5-32 

INVTFS 5-14, 5-16, 5-32 

IRFS 5-11, 5-32 

IRQO 1-9,3-11,5-3, 9-14 

IRQ1 1-9, 3-11,5-3, 9-14 

IRQ2 5-38, 9-14 

ITFS 5-11 


J 

JUMP 3-8, 3-9, 3-24 

L 


Length (L) registers 4-1, 4-3, 4-4, 12-2 

Level-sensitive interrupts 3-15, 9-14 

Linker 14-3 

Logical shift 2-3, 2-22, 2-28 

Loop 3-5, 3-6, 3-7, 3-9 

Loop comparator 3-3, 3-5, 3-6, 3-10 

Loop counter 1-7, 3-4, 3-5, 12-4 


Loop stack 3-4, 3-5, 3-6, 3-7, 3-22, 12-5 


LSHIFT 


2-31 


M 


M registers 4-1, 4-2, 4-3, 5-26, 5-28, 8-14, 12-2 

MAC 1-6, 2-13, 2-15, 3-21, 

12-2, 12-6, 15-9, 15-10 


MAC arithmetic 


2-3 


MAC input/ output registers 2-18 

MAC operations 2-16 

MAC overflow 2-19 

MAC saturation 2-19 


Matrix multiply 

Memory address 

Memory interface 

Memory read 

Memory wait states 

Memory write 

Memory-mapped registers 

MF register 

Miscellaneous instructions 


14-1,14-9 

3-3 

10-2, 10-37, 12-2, 12-7 

10-3 

3-18 

10-3, 10-24 

12-1 

2-15, 2-20 

15-16 


MMAP 7-16, 10-5, 10-6, 10-15 

Mode bits 12-5 


Mode control 12-5, 15-16 

Mode status register (MSTAT) 3-12, 3-22 

Modify (M) registers 4-1, 4-2, 4-3, 5-26, 5-28 

Modulo addressing 4-1, 4-4 

Modulus logic 4-3 

MOVE instructions 15-13 

MR register 2-13, 2-15, 2-16, 2-18, 2-20, 2-22 

MR0 register 2-13, 2-15, 2-18 

MR1 register 2-13, 2-15, 2-19, 2-20 

MR2 register 2-13, 2-15, 2-19, 2-20 

MSTAT 1-7, 2-8, 2-9, 2-16, 2-24, 3-12, 

3-14, 3-20, 3-22, 4-2, 6-1, 12-5 

Multichannel 1-2, 1-8, 5-3, 5-5, 5-30 

Multichannel frame delay 5-32 

Multichannel length bit 5-31 

Multichannel mode 5-30, 5-31, 5-32 

Multichannel operation 5-32, 5-33 

Multichannel setup 5-30 

Multichannel transfer 5-32, 5-33 

Multifunction instructions 1-4, 15-7, 15-19 

Multiplication 2-13 

Multiplier 2-18 

Multiplier result format 2-17 

Multiplier/accumulator 1-6, 2-13, 2-15, 3-21 

Multiply/ add 1-6 

Multiply/ subtract 1-6 

Multiprecision capability 2-8 

Multiprocessing 9-4 

MV 2-13,2-19 

MX register file 2-15 

MX0 register 2-15 

MX1 register 2-15 

MY register file 2-15 

MY0 register 2-15 

MY1 register 2-15 

N 

Nested loops 3-8 

Nesting 3-15, 3-16 

Next instruction address 3-3, 3-4, 3-7, 3-10 

Normal framing mode 5-13 

Normalize 2-22, 2-28, 2-33 

Normalize modifiers 2-35 

Numeric formats C-l 

o 

Off-chip memory accesses 15-18 

On-chip memory 1-2 

On-chip peripherals 1-2, 1-8 

Opcodes A-l 

Operating mode 3-22 


X -4 



Operation during powerdown 9-23 

OR/PASS logic 2-22, 2-24 

Output enable 10-3, 10-24 

Output registers 1-7 

Overflow (AV) ...2-2, 2-5, 2-8, 2-9, 2-13, 2-26, 2-36 

Overwrite bit 9-24 

Overwrite mode 7-7, 7-9 

OWRCNTR 3-5 


P 


Page length 

PASS 

PC 

PC incrementer 
PC stack 


PDFORCE 


10-15, 10-18 

2-32, 2-33 

3-4 

3-3 

3-3, 3-4, 3-6, 3-10, 3-11, 
.3-22, 12-5, 15-84, 15-85 


9-18 


Period register 6-1 

Periodic interrupts 6-1 

PMA bus 1-8, 3-3, 3-4, 3-8, 10-1, 10-3 

PMD bus 1-8,10-1, 10-3 

PMD-DMD bus exchange ... 1-5, 1-8, 2-15, 4-1, 4-9 

PMOVLAY 10-26 

PMS 1-8, 10-3,10-24 

Polled operation 7-7 

PORT directive 10-14 

Powerdown 8-9, 9-17, 9-20, 9-30 

Powerdown acknowledge 9-29 

Powerdown control register 9-18, 9-20 

Powerdown force control bit 9-19 

Powerup 9-20 

Powerup boot 10-16 

Primary registers 2-7 

Processor states 9-2 

Program counter 3-4 

Program flow control 15-14, 15-15 

Program memory 1-8, 10-1 

Program memory configuration 10-5 

Program memory data bus 4-9 

Program memory interface 10-3 

Program memory map 10-5, 10-6 

Program memory read 10-3, 15-6 

Program memory write 10-3 

Program sequencer 3-1, 3-5, 12-2, 12-4 

Programming model 12-1 

PUCR 9-18 

PWAIT 10-5 

PWD pin 9-19 

PWDACK pin 9-29 

PX registers 1-5, 4-9, 4-10 


Q 

Quotient format 2-12 

R 


R bus 1-6,2-15,2-18,2-22 

RAM 10-6 

Read operation 15-12 

Receive companding latency 5-40 

Receive frame sync 5-11, 5-12, 5-30 

Receive interrupt (SPORT) 5-4, 5-36 

Receive register 5-6 

Receive word enables 5-31 

Receiving data 5-6 

reg 15-12,15-14 

Register indirect JUMPs 3-8 

Register notation 15-20 

Registers 12-1, 12-3 

RESET 9-1,9-4,9-21,9-25 

Result bus 1-6 

Return 3-7, 3-10 

RFS 5-2, 5-11, 5-12, 5-30 

RFSDIV 5-12 

RFSDIV 12-7 

RFSR 5-10,5-11 

RFSW 5-13 

Rounding mode 2-20 

RTI instruction 3-11, 9-15, 9-30 

RX register 5-2, 5-4, 5-32, 5-36 

RX0 register 5-6, 5-32 

RX1 register 5-6 


s 


Saturation 

SB register 

SCLK 

SCLK frequencies 

SCLK pin 

SCLK0 

SCLK1 

SCLKDIV 


2-13 

2-22,2-29 

5-1,5-12,5-13, 5-15, 5-16 

5-9 

5-9 

5-34 

5-34 

5-9, 12-7 


SE register ...2-22, 2-24, 2-26, 2-30, 2-31, 2-33, 2-34 

Secondary register 3-12 

Serial clock 5-1, 5-5, 5-8, 5-34, 5-38 

Serial clock frequencies 5-8 

Serial port autobuffering 5-42 

Serial ports 1-8, 5-1, 5-38, 9-5, 9-23, 12-7, 

13-5, 13-6, 13-7, 13-8, 13-10 

Serial word length 5-5, 5-9 

Shifter 1-6, 3-21, 12-2, 15-9, 15-11 


X - 5 



Shifter arithmetic . 2-3 

Shifter array ..2-22 

Shifter input/output registers 2-28 

Shifter operations 2-28 

Shifter sign 2-26 

SI register .....2-22, 2-23 

Signed numbers 2-1 

Sine approximation 14-7 

SLEN 5-10, 5-16, 5-31, 5-32 

Software examples 14-1 

Software reboot 10-16 

SPORT .....1-8, 3-18, 5-1, 5-3, 5-6, 9-23 

SPORT control register 5-8, 5-10, 5-11, 5-13, 

5-14, 5-16, 5-23, 5-31 

SPORT enable 5-7 

SPORT interrupts 5-3, 5-34, 5-41 

SPORT multichannel frame delay 5-31 

SPORT programming 5-4 

SPORT timing 5-34 

SPORT configuration 5-5 

SPORTO 5-1, 5-5, 5-15, 5-16, 5-30, 

8-13, 12-7, 13-6, 13-7 

SPORTO configuration registers 5-5 

SPORTO control register 5-30 

SPORTO multichannel word enable registers 5-32 

SPORT1 5-5, 5-30,8-9, 

8-13, 9-14, 9-15, 12-2 

SPORT1 alternate configuration 5-8 

SPORT1 configuration registers 5-5 

SR register 2-22, 2-23 

SR0 register 2-22, 2-24 

SRI register 2-22, 2-24 

SSTAT 12-5 

Stacks 3-4, 12-5 

Start-up delay 9-20 

Start-up time 9-21 

Startup timing 5-38 

Status bits 3-21, 12-5 

Status condition... 3-6, 3-25 

Status logic 3-4 

Status registers 3-15, 3-20 

Status stack 3-16, 3-20, 3-22, 12-5 

Stolen cycles '. 15-18 

Subroutine 3-9 

Subtract with borrow 2-8 

Synchronization delay 9-3 

Synchronization (serial elk to processor elk) 5-38 

System Builder 1-10 

System Control Register 9-14, 9-15, 

10-17, 15-12, E-l 

System interface 9-1 


T1 interface 5-31 

TCOUNT 6-1, 6-2, 6-3, 6-4, 12-6 

TDV 5-32 

Termination condition 3-6, 3-10 

TFS 5-2, 5-11, 5-12, 5-30 

TFS0 5-30 

TFSR 5-10, 5-11 

TFSW 5-13 

Time-division multiplexed 5-30 

Timer 3-18, 3-23, 3-24, 6-1, 9-5, 12-2, 12-6 

Timer interrupt 3-19, 6-1 

Timer operation 6-3 

Timer registers 6-1, 6-2 

TOPPCST ACK ... 3-4, 3-25, 3-26, 3-27, 15-84, 15-85 

TPERIOD 6-1, 6-2, 6-3, 6-4, 12-6 

Transmit data valid 5-32 

Transmit frame sync 5-11, 5-12 

Transmit interrupt (SPORT) 5-4, 5-36 

Transmit register 5-6 

Transmit word enables 5-32 

Transmitting data 5-6 

TSCALE 6-1, 6-2, 6-3, 6-4, 12-6 

Twos-complement 2-1, 2-18, 2-33, C-l, C-4 

TX register 5-2, 5-4, 5-35 

TX0 register 5-6 

TX1 register 5-6 

u 

Underflows 2-8 

Unsigned 2-1, 2-18, C-l 

w 

Word length 5-3, 5-9, 5-32 

Write enable 10-3 

Write operation 15-12 


XTAL pin 9-1, 9-21, 9-22 

XTALDELAY 9-18, 9-20 

XTALDIS 9-18 


Zero-overhead looping 1-5, 3-1 


X-6 



2100 FAMILY 
USER’S MANUAL 


Digital signal processing is revolutionizing traditional analog applications in the areas of 
audio, video, imaging and communications, and is enabling new applications such as 
video teleconferencing, noise cancellation, and speech recognition. With 25 years expe- 
rience in real-world signal processing, both analog and digital, Analog Devices offers 
complete solutions for designers of signal processing systems: DSP microprocessors, 
mixed-signal peripherals including A/D and D /A converters, and development and 
applications software. Based on this unique perspective on signal processing applica- 
tions, the architecture of Analog Devices’ DSP processors addresses five key require- 
ments of digital signal processing: 

• Fast, flexible arithmetic for all computations including the multiply-accumulate 

• Extended dynamic range in computations to minimize scaling, truncation, and clipping 

• Program sequencing with zero-overhead looping 

• Dual data address generation with circular buffering and bit-reversed addressing 

• Three-bus Harvard architecture enabling single-cycle fetch of both instruction and two 
data values 

This manual is a comprehensive reference for Analog Devices’ ADSP-2100 Family, an 
architectural and code-compatible set of 16-bit fixed-point DSP micprocessors that offer 
varying levels of feature integration. Topics covered in this manual include: 

• Base Architecture — Computation Units, Program Sequencer, Data Address Generators 

• Integrated On-Chip Peripherals — Serial Ports, Timer, Host Interface Port, A/D and 
D/A Converters 

• System Hardware & Memory Interfacing 

• Programmer’s Model & Instruction Set Reference 

• System Design & Programming Examples 

Additional textbooks from Analog Devices and Prentice Hall include Digital Signal 
Processing In VLSI , Digital Signal Processing Laboratory Using The ADSP-2101 
Microcomputer and the Analog-Digital Conversion Handbook. 




82 - 000780-03