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IBM Personal Computer - Ethernet (IE) 
Control ier/Transcei ver 

Externa] Reference .Specifications' 
3Com Corporation 

March 15, 1983 

IBM Personal Computer - Ethernet (IE) 


External Reference Specifications ' 
3Com Corporation 

i • Introduction 

caters 3 \ir<^SrS h s n s. e ssir£2?'fr:i? r fo v ibm personai 

September 1980, as published y " t fa ^' W^o" ^ 3 ° 
exception, it implements levels one and two of ^ o' I ° ne mln ° r 
connect Model of the Inte r nat]onaT S :a n nda t :d s O 0r g t ani^Uonr StemS ^^ 

P evel 9H£ Functions , Physical Layer 

o Coax/station electrical isolation. 

o Bit transmission/reception. 

o Carrier sense. 

o Transmit collision detection. 

o Encoding/decoding. 

o Preamble generation/removal 

Level Two Functions , Data Link Layer 

o Frame check sequence generation/checking. 

o Carrier deference. 

o Transmit collision enforcement. 

Collision fragment (runt) filtering. 


o Bad packet filtering. 
o Address recognition. 

The controller on the IE incorporates a VLSI Ethernet Data r i n v n 
troller the Seeq 8001 or EDLc", and a single, two Kbyte packet \uf°fT 

sTstlTVolrr^A ^l" 'I" g23?A ° MA ~^11« fo^d "on^the ' BM 
bystem Board. it also has provisions for external lnnnh^v 1L 

the* ^tlta^"^^™' 1 ! ° f the S259A ^--uprc P o b n^oner C on 

the x/c^nTan ^.^^^n.^vS^JITS comoT^ Tell?^ 
and two functionality on one printed circuit ca ^ cora P lete Level 


2- Architecture 

The IE has a single two Kbyte packet buffer- Ma-. 

^cLTis^aTf Pa Tt t] ^^«"«»«Tna e^fve.^once^: 
packet „ transferred to the buffer for transmission and a transmit 

March ] 5, 1983 

- 2 - 

initiated, the software must intervene only in case of a collision 

To receive a packet, software selects one of several address 
t.ion modes; when a suitable packet arrives, the controller placeTit 
in the packet buffer. When enabled for multicast recoanition P ,S"^ 
software 5 ^ mUltlCaSt P aCkets ™«»t be performed' by" "the^stem 

Programs address the IE through a block of sixteen registers in the 
read status 'nformlt o f^^cess^ ^"* f^ ~™- 

™"?- ai aCt i Ce ' <*/ IE ' S baSe ^"^ "" jU m P er- set^b^ ? ^alues^ 
-r-he IE also has a four Kbyte ROM for program storage. The bl ^ 
address, of the ROM in memory space is also jumper settle ?32 

«w" ?° th * packet buffer Pitches between the system bus and the 
Ethernet under program control. Ethernet access can be receive 
transmit with automatic rollover to receive, or loopback? recelve ' 

One of the I/O registers provides a one byte window on the oacket 
k ,5 er :v An ° ther register, GP, the general purpose buffer pointer 
dow * S ^ dreSS f fcl ? e . b y te vi ^ble through the packet buffe? winl 
dow Reading and writing the window automatically increment GP per- 
mitting sequential access to the oacket buffer f™™ t^I. en f w P er 

Writina cp \h«„ ^=,^n .!. P ac * e t outter from the system bus. 

dom access. 9 wrItln 9 the wi ^ow gives the effect of ran- 

The packet buffer can be loaded and unloaded using the S237A DMA con- 

'" ° n the s p" em b ° ard t0 re P«titively read or write the window. 

The IE can request DMA service, detect the end of the transfer and 

interrupt when the DMA is done. transfer and 

K^J nter ^ S f° th r°ugh_the 8259A interrupt controller on the system 
.~a.„. oov-u type or its interrupt is enabled independently of other 

Th^'' arrant T' ^^ ""l* °™ inte "upt line" to the System 
determ^^f "quires software to scan the IE status registers to 
both ™! ° f an lnterru P fc - Consistent with IBM PC practice, 

disabled SSrV1Ce re ^ es t and interrupt request line drivers can b4 

_3- System Interface 

The IE has two sixteen bit buffer address pointers (registers), GP and 
the receive buffer pointer, rp. rb is used only by the rec v s 
°^ h V 0ntr0l i" f ° r P acket reception. The transmit side ofthe Pth! 
ernet logic and the system bus use GP for access to the oacket bnff^. 
bOopoacK operation uses both. ' " 

Transmit packets are end-aligned within the packet buffer. Software 
uses GP when filling the buffer. before transmitting the buffer 
software reloads GP so that it points to the first byte of the packet'. 

Receive packets are front-aligned in the buffer. Therefore, after the 

March L5, 19*33 

- 3 - 

Pack^en^xleeds'the T^LT' P T, e \^ th ln ^ teS - » the 
saved in g the buffer After the S,, 1 'Z'"' *° 4 ° bytes wi " be 
any buffer overwrite reading a ItXt ^ "£'' e RP l0 °* S Up Preventing 
RP indicates a packet o? at Last Toll bytes ° f '° 48 (8 °° hSx) fr °™ 

buffer. A maximum length packet cfn hi f pac * et front-aligned in the 
packet may overwrite part of the tr Zt , ^ „ The received 
requires the IE to be connected to ?„ transnut ted Packet. Loopback 
external transceiver, or fitted ^ h ^hernet by the onboard or 
Plugs by the user. Wlth s P ecla l BNC or DA-15 loopback 

The IE's Ethernet station address is stored in » doam x. 
are accessible through another one byte window teaTster «° S - , COnte ^ s 
window register used to access the oacket buf f ~ 9 c ^ Slmllar fc o the 
address the station address prom »vf n,K^ " ? ? oftware uses GP to 

with station address bvte zero »* 1^ ln locat ions zero thru five 

packet buffer, reading the t „ ^ SS Z ' r °' UnMke access to the 

software must'expl iciUy^ncrement Jtf"'" *** ™" ^"i cement GP; 

laaress^One^et^s re^onW- S^" tor . the Et ^rnet station 
must program the statl^'address'by tTtlLTt^ write ^T ^^ 

March 15, L983 

- 4 - 

3.1. IE Controller Register Map- 













Receive Status 

Transmit Status 

GP Buffer Pointer [LSB] 

GP Buffer Pointer [MSB] 

RCV Buffer Pointer [LSB] 

RCV Buffer Pointer [MSB] 

Ethernet Address Prom Window 

Auxiliary Status 
Buffer Window 


Station Addr 

Station Addr 1 

Station Addr 2 

Station Addr 3 

Station Addr 4 

Station Addr 5 

Receive Command 
Transmit Command 
GP Buffer Pointer [LSB] 
GP Buffer Pointer [MSB] 
RCV Buffer Pointer Clear 

Auxiliary Command 
Buffer Window 

March 15, L983 

5 - 

-'-* Transmit Command Register 

3! 2rTT~ol 

T T T 1 

Detect Underflow 
Detect Collision 
Detect Collision 16 
Detect Successful Transmi 


•> Unused 

without successful tranSmi ssion *n£' " x * eenth successive collision 
data remains in the p v ?h. w ^ AftSr eaCh c °H^ion, 
reset GP and explicitly restart ^f f " ^asturbed; but, software »s 
IE delays the appropriate amount of M^k^ " 7 °" Ce "Parted, the 
ting the packet. After the sTxteL^ bef0re actua1 ^ retransmit- 
attempts to retransmit should be *£„« con " cutlve collision further 
network is overloaded or h!s faHed " th * """"P"** that the 

^ i-wvauaue operation of the controller. 

tronT^is^e^^^oeer^f Sne^nlhe" °' deteCt "* <* th * «»' condi- 
the condition; a Lro ignores the L^f, reSPOndln9 bit Potion detects 
not sufficient to generate an ^?n«.™ £ ; Detectin 9 * condition is 
erate interrupts, software must ' „ In ° rder for the " to gen- 

Enable, orcware must also set Request Interruot and DMA 


See the description of ♦.>.= * ■ i • 

details concerning n und°e f rf^ anT^er^r^ 

Register below for 

March 15, 1983 

- 6 - 

3. e .3» Transmi t Status Reqister 


I I I 
I I I 
I I I 

I 1 

I I 



> Underflow 

> Collision 

> Collision 16 

> Ready for New Frame 

> Undefined 

The controller loads the transmit status register only after each 

'""!™jr l0n ° r a "r PtSd trans ™i s "on. If interrupts are enabled lor 

transmit, reading the status register clears the interrupt. 

2-4. Receive Command Reqister 

> Detect Overflow Errors 

'-— ■> Detect FCS Errors 

> Accept Dribble Errors 

> Detect Short Frames 

> Detect Frames Without Overflow Error 

> Accept Good Frames 

> Address Match Mode 

- Receiver Disabled 

1 - Receive all addresses 

2 - Receive station address and broadcast 

3 - Receive station address and multicast 

Software can program the IE to detect only certain classes of packets- 
all unwanted packets are discarded without intervention. The Address 
Match Mode controls whether to accept packets by examining their de" 
a "°" ^dresses. If the match mode is zero/the IE will not detect 
any packet; mode one accepts packets regardless of the contents of 

March 15, 1983 

- 7 - 

registers zero through five. registers stored ln IE 

Other bits in the command register allow software .-„ c ^ 
packets before detecting them The ^J™! f further qualify 
•ta (legal size, no PCS error and no 1 P *f °? Iy Wel1 formed pack " 
formed packets software £^4 ,*?►>," °, overflow '-- to receive well 

indicates the packet did not end on a bvte^ *?" *'T ^ D " bble 
extra bits after the last hvf, ™ Y ^^"V? t*ere were a few 

with dribble errors as long as* the ole^T I ^ " a ° Cept pac * ets 
wrong with it and softwar^sets Accent nrihnTf 2°* haVe a ^ thi n9 ^Ise 
are useful only to detect pt errors TrT'conJ 1 ^ WtS 
not accept packets with errors- Si, <-=„** controller will 

to keep counts for d agnlsUc purposes Ihort" ? -teCt thSm ln ° rder 
whose length is less ti,,, m purposes. Short frames are packets 
are probably collision fragments te '' ? TClu <"«9 Preamble and FCS? these 
computed o/receit d no? match the FclTn SE"" ^VT byte FCS 
Ethernet "alignment error" is eouiva?^^ packet. (Note that an 
FCS errors.) Overflow errors h^n! ? a P ^ ket With dribble and 
accept a packet, out ^he picket S ? i? 1 *",. the . oontroller tries to 
might already have i packet or thf h ,4 "°* availab1 *- The buffer 
bus rather than the Ethernet! ""^ ml9ht bel °" g to the ^^ 

2-5.. Receive Status Register 

5T4|~3| 2 1 1| 01 


I I.-.-"* Overflow error 

-> FCS error 

-> Dribble Error 

■>. Short Frame 

■> Received well formed packet 

•> Undefined 

•> Stale Receive Status 


lUT.r c d omma n nd registe^ °The * con t rone 9 " ^^ ^ **^ «>. 
after any packet goes by' on th^" n" work whether ^of*^ ^^ 
interesting. if the controller- ^*« I wn, T tner or not it was 
Stale Receive Status goes to °o „ " ' S ™ interesting packet, the 

zero the control ler^discards "an" oac^ts unUl^olt^ StatUS is 
status register; this guarantees that software rl,L ^ " S rMl a the 
elated with the detected packet. Re^nf"^^^'* register"^^; 

March 15, 19Q3 

fl - 

Stale Receive Status back to one; the IE can then detect the next 
interesting packet that comes by on the Ethernet. If receive inter- 
rupts are enabled, reading the status register also clears the inter- 
rupt. Ci 

3.-1- Auxiliary Command Register 





I > Transmit Packets with Bad FCS 

> Unused 

■> Packet Buffer Control 

- System bus has access to the buffer 

1 — Transmit followed by receive 

2 - Receive 

3 - Loopback 

> Unused 

•> DMA Request 

•> Request Interrupt and DMA Enable 

> Reset 

Writing a one in Reset, resets all control and status registers in the 
IE. Software must explicitly set this bit to zero after setting it to 
one; leaving Reset on has the effect of perpetual lv rp.e^i'na ** e 
controller, " " ~ 

Request Interrupt and DMA Enable, RIDE, permits the IE to drive both 
the interrupt request, IRQ, and DMA service request, DRQ, signals on 
the system bus. Jumpers on the IE card select DMA channel (either one 
or three), and interrupt channel (either three or five). When RIDE is 
zero, the IE_ _cannpt_ generate interrupts or DMA transfers. Bits in the 
transmit and receive command registers can be set to detect certain 
conditions; however, no interrupts can result until RIDE is a one. 

Software must manipulate RIDE with care. When RIDE is zero the state 
of the associated IRQ and DRQ lines on the system bus can be unde- 
fined. Leaving these lines in an undefined state when their associ- 
ated DMA and interrupt channels are active can result in strange and 
unpredictable behavior. Software must insure that the associated IRQ 
and DRQ lines are not used by other peripheral devices before settinq 
RIDE to one. Neither setting of RIDE is safe under all circumstances * 

Setting DMA Request to one starts a DMA transfer. 
at the completion of the transfer. 

The IE interrupts 
Setting DMA Request to zero, 

March 15, 1983 

- 9 - 

di sable s DMA serv'i 


ce request, clears DMA Done, and clear: 



Bits two and three of the auxiliary command register control a „ 
the packet buffer. if both bits are zero, the buffer »S n ^l** t0 
system bus; software is free to read and write the w f 9 t0 the 
interference from the Ethernet. If either of the bits f" Wlth ° Ut 
the packet buffer belongs to the Ethernet If bit 3 Ts one^thf "" 
troll er will accept one packet from the network The 2?;. /° n " 
receive command register can discard certain dlL !f S 9 ° f the 
guarantee that only "interest! na" J^v^o classes of packets and 
packet buffer. After recetvTna a oaev^ L*™ detected a ^ reach the 

packet buffer. pacxet t> a ck into the beginning 

causes 9 the *?? T"^ Wt ° f th * *«"i»ry command register to one 
for^estiS £ re^ncTc?rcu^r y : lth ^ ^ ™ ! Mt " -^ 

2-2- Auxiliary Status Register 

T ~T T ~T 


> Receive Busy 

> Unused 

■> Packet Buffer Control 
•> DMA Done 
> DMA Request 

Request Interrupt and DMA Enable 
Transmit Busy 

^mH*ESS a S=s«Sr 

software clears DMA Done by setting DMA Requwt to zero. *'' 

n^vir ^ g °v S t0 ° ne . uhenevec the controller is armed to receive a 
packet; this happens implicitly after transmitting a nacket or 

bacr^L^rBus? VoeTTo" ££•%££"£„" 'fj * - ^ 
Packet. Software must wa'it SOO^Snco^ft.^rS^^.V^'tS 

March 15, 1983 

- 10 - 

zero before reading the receive status register. 

Transmit Busy is meaningful only when the packet buffer control is set 
for loopback or transmit; while the packet buffer is switched to the 
bus or is in receive mode Transmit Busy will be set. Transmit Busy 
remains at one when software starts a transmit by setting^the^Packet 
Buffer Control to one. Transmit Busy goes to zero upon a collision or 
a successful transmission. Software can distinguish between these two 
cases by examining the transmit status register. Switching the packet 
buffer back to the bus sets Transmit Busy back to one. 

4. I_E Programming 

To transmit a packet, first set the Packet Buffer Control to zero- 
this gives the system bus access to the buffer. Load the packet into 
the buffer so that the last byte of the packet coincides with the last 
byte of the packet buffer. Load GP so that it points to the first 
byte of the packet in the buffer. Start the transmission by setting 
the Packet Buffer Control to one. The transmission terminates when 
Transmit Busy goes to zero? read the transmit status register to 
determine whether there was a collision or a successful transmission. 

In case of collision, set the Packet Buffer Control to zero, reload 
GP, and set the Packet Buffer Control to one; this retransmits the 
packet. Again wait for Transmit Busy to go to zero: then, read the 
tra J^mit status register to determine why the transmission terminated. 

Receiving packets requires both one time initialization of the con- 
troller and manipulation of the IE for each packet that arrives. The 
one time initialization includes reading the station address PROM, 
loading the station address registers, and setting the receive command 
register. In the programming example the routines "getaddr" and 
setaddr", read the station address PROM and write the station address 
registers respectively. 

To^ receive a packet clear RP and set the Packet Buffer Control to two; 
this initializes the read pointer and gives the packet buffer to the 
Ethernet. 800 nanoseconds after Receive Busy goes to zero, the 
receive status register has the status of the packet just received. 
The size of the packet, in bytes, is in RP. Software must set the 
Packet Buffer Control to zero before reading the packet from the 

The following code, written in C, initializes the controller, 
transmits a single packet of 1000 bytes, and then receives well formed 
broadcast and packets addressed only to the station. The main program 
is found at the end of the example. The routines "inb", "inw", 
"outb", and "outw" read and write words and bytes on the IBM PC's I/O 
bus; the routine ,, inbs M reads a byte sign extended into a word. All 
of the examples are polled I/O; no use is made of the interrupt circu- 
i try. : _ 

/* the various IE command registers */ 
^define IE(num) (0x300+0xl0*num) 

March 15, 1983 

_* define 
f define 
tdef ine 
tdef ine 
tdefi ne 

- 11 - 

EDLC_ADDR|num) -- (num) - 
EDLC_RCV(num) ((num) +0x6) 
EDLC_XMT(num) ((num) +0x7) 
IE_GP(num) ((num)+0x8) /* 
IE_RP(num) ((num)+0xa) /* 
IE_SAPROM(num) ( (num)+0xc) 
IE_CSR(num) ((num)+0xe) /* 
IE__BFR(num) ((num)+0xf) /* 

/* 1™Z nation address, 6 bytes,-*./ 
/* ™S receive command and stat#- 
, r L C transmit command and status 
transmit, station address PROM bp */ 
receive buffer pointer */ 

T /* l by * e ^ndow on station address 

lb command and status */ 

1 byte window on packet buffer */ 

tdefine: EDLC NONE ' OxSo AZLT^ °" "**•' St * tUS » he » ~ad 

#define EDLC"alL 0x4^ /* ^ ^ ln MtS 5 ~ 6 ' writ e only */ 

tdefine EDLC^AD 0x80 /* IttToTT^rltT^^ ? it9 ° nly *' 

#define EDLC^MULTI OxcO /* station Zaa ** P J Ua broadcast V 

- UXJ - uxcu / station address plus multicast */ 

■# define EDLC_STALE 
#define EDLC_GOOD 
#define EDLC_ANY 
tdefine EDLC_SHORT 
tdefine EDLC_FCS 0x02 
tdefine EDLC OVER 0x01 


0X80 0x*0 reCe /r C ^ ? tatUS P rev ^sly read */ 
0*1 n/* ' , WeU f ° rmed P acke ts only */ 

OxOS / 7 * Zrrfra^ ^ ^ ^ ^ *' 
0x04 /* dribble error */ 
/* CRC error */ 
/* data overflow */ 

!2SS SHST ffiEyssasaBK'saB-'™-"-' 

/* bits in IE__CSR */ 

#'£££ iS'S? ° X8 ° /; 40 "-« *• eontroll.r V 

Jdefine IE D „ A 2**° l * "? uest interrupt/DMA enable */ 

t define IE _ E o M r s«s f f : »* ££•■* V 

tdefine IE LOOP Ov-n^ /* o w 

*ae fine IE _s7s^f LC 0x00 ^^Is^L^o'essT^ *' 

tdefine IE CRC 
tdefine IE~~RCVBSY 

n*«? f ,l causes CRC error on transmit */ 
OxOl /* receive in progress */ 

/* miscellaneous sizes 
tdefine BFRSIZ 0x800 
tdefine RUNT 60 
tdefine GIANT 1514 


/* number of bytes in a buffer */ 

/* smallest legal size packet, no fcs */ 

/ largest legal size packet, no fcs */ 

error(s) char * S; (printf('^ s \ s);} 

/* can DOS to test for keystroke, if its *c get bao* to DOS V 

March 15, 19R3 

- 12 - 

sense_key() [char c; 

if (dos(Oxb)) [if (( c s dos(8)&0177)==3) exit(O). rfl f , x > 
else return(O)-} exitioj; return(c);) 

( ) ; } 

/* low level transmit routines * 
iereset(base) short base; [ 

outb(Oxa, 5); /* 



outb(0x2T, OxaO)- 7* tUr J? off DMA channel 1 

If r ( M b I?^ R(ba ? e)) != 0x80 > error ("Can't reset 
if (dnb(EDLC XMT base))&OxOf) i= Q) lrmr("rl^t , - 
if r(inKfpn T ^-n/,»/ Kaea ,. ";: u; error ( Can t clear EDr.r xm^'M - 

-- ^-»-^yLv._^vvoase);ft«ux9f ) != EDLC STALE) "— _*m* ). 

error ( Can't reset EDLC RCV");} ~~ 

IE CSR") ; 


int size; { 

_start(base, size) short base? 
char c= inb(EDLC XMT(base))- 

outb(lE_CSR(base), IE_RIDE|lE XMTEDLC) ; } ~ ~ * ' 



/* returns _ o for successful 

1 timed out 

2 collision 

3 data underflow 

4 idle not set after transmit 

5 16 collisions */ 
xmt_wait(bas e/ size, stall) short base- 

int i; char c; 

if ( (inb (lE_CSR(base))&IE__XMTEDLC) == 0) 
i = stlll^"^^ n0t switched to transmit, 
do f 

if ( inbs(IE_CSR(base) ) < c 
c = inb(EDLC__XMT(base) ) ; 
if (c&EDLC_UNDER) return(3) 
if (c&EDLC_16) return(5) 

if (c&EDLC_JAM) return(2), 
if (inw(lE GP (base)) -=0x800) { 
if (iTinb(EDLC XMT(base)) 
return(O);}} ~ 

whi le(i — >=0 ) ; 


int stall, size; [ 

xmt__wai t" ) ; 

continue ; 


underflow */ 
16 successive 
collision? */ 

collisions? */ 

& EDLC_IDLE)) return(4) ; 

mod e , size; [ 

retransmit(base, mode, size) short base, 

int i = 0, org = BFRSIZ-size, k; 

if ( Unb(lE_CSR(base))&lE XMTEDLO == m 

whnI ( r bUf K e f T ^ 0t s V itched "to transmit/retransmit" 
while ( inbs(lE__CSR(base) ) < ) 

if (++i > 1000) (error ("retransmit- time. 

make IE idle 

outb(lE_CSRfbase), IE RIDE)- / 

outwflE_GP(base), org!; 

if ( (inb(EDLC_XMT(basem(EDLC JAM I EDLC 16) 

d out") 

break; } 

— ) return 

March 15, 1903 

- 13 - 

°y tbllE__CSR Cbase-)- T - -IE-1W DE I mode) - r } 

/* returns on failure, 1 on success */ 
xmt_done(base, size, stall) short base, size, stall- { 
retry: swi tch( xmt_wai t (base, size, stall)) { 

case 1: error ( "Transmi t timed out"); iereset (base ) • 
case 0: return(l) ; ' 

case 2: 

error ( "Jam") ; 

retransmit(base, IE_XMTEDLC, size); 

sense_key ( ) • 

goto retry; 
case 3: error ("underflow on transmit"); iereset(base) ; break- 
cafe V- ?er^w£ le ? 0t S6t after Xmt " ); ^esetfbase); break; 
case b: iereset (base ) ; 

error( "excessive col lisions" ) ; 

default: error("xmt done: bad arqument")-] 
return(O) ; ] ~ 

/* low level receive routines */ 
rcv_start(base, mode) short base; char mode- { 

outb(EDLC_RCV(base) / EDLC NONE)- 

outb(lE_CSR(base), IE__RIDE ) ; 

outw(lE_RP(base), 0); 

inb(EDLC_RCV(base)) ; /* he'll discard until we read the status */ 

outb IE_CSR(base), IE RIDE I IE RCVEDLC); ' 

outb (EDLC_RCV (base), mode I EDLC_G00D) ; } 

rcv_wait(base, stall) short base; int stall; { 
char status; int i = stall; 
do ( 

if Unb(lE_CSR(base))&lE_RCVBSY) continue- 

status = inb(EDLC__RCV(base))&(EDLC STALE I EDLC RMASK)- 

while(i-->io^ tUS&(EDLC "- ANYlEDLC -- RE:RRORy) != ° } r¥turn ^ statu s);} 
return(O);} ' /* timed out */ 

rcv_chk( status) char status; { 

if (status&EDLC_FCS) error ( "FCS error")- 
if (status&EDLC_DRIBBLE) error ( "dribbl e' error ") • 
if status&EDLC_OVER) error ( "over flow on receive")- 
if (status&EDLC_SHORT) error ( "si ze" ); } 

rcv_done(base, stall) short base; int stall; { 
char status; 

if ((status = rcv_wait(base, stall)) == 0) return(O)- 
if (status < 0) [errorC'not fresh status"); return(-l)-] 

outb IE_CSR(base), IE_RIDE!lE SY55BFR); /* aive buffer' to orocessor */ 
outb(EDLC__RCV(base), EDLC NONE); /* shut iovn ^he POLC */ 
rcv_chk ( status ) ; ~ 

return(status&Oxff) ; } /* guaranteed to be non-zero ,it this point */ 
qetaddr (base, cp ) short base; char *cp; (int i; 

March 15, I'^n 

- 14 - 

:or(i=0; i<6,- i++) { 

outwf IE_G?(base) , i ) r 

*cp++= inpfiE_SAPROM(base) ); } } 

r ; _^ 

setaddr(base, cp ) short base- ^ a - *— . , .«. { 

for(i=0; i<=5; i++ ) outb(EDLC_ADDR(base ) +i , c P [i]);} 
7* fin packet with constant pattern */ 

ou't^X^^C^^sp^^^T^^SB^n a Sh ° rt " *" ^- *' 

outWlEJP(base), BFRSIZ-sizej^" **"*'' °" WOrd boundar y V 

fot ( i=size>>i ; i>0; i — ) { 

outb(IE_BFR(base), pat); outb(IE_BFR(base) , pathi ) ; ) ) 

xmt_pkt(base, size, stall) short base; int size stall- f 
xmt_start(base, size); xmt_done(base" sltV, "aJl);| 

rcv_pkt(base, rcv_mode) ( 

int status, stallcon = 0x400- 

rcv_start(base, rcv_mode); 

whi 1 e ( (status = r^v donefhfl^s efa ii rt ,\ rt » 

return(status);} ~ ' stalicon) )«0) senseJeyO; 

main() ( 

char myaddrre]; int ie = ie(0), size, i; 

/* one time only initialization */ 

Ltaddr e' "yaddr ) '. /* re ^statio n> address from -<0M */ 

DrintfrMrA m tp d ' ■ Set the stati ^ address * / 

pr-i.ntr r 3Com IE Programming Exa^lp Vprcinn r nnV. 

fill_pkt(ie, 1000, 0x5555); /* fin „ ac v p ,. tji ^ 

xmt oktfie, 1000 1000). >* «.,., ' -Z ; ~ ' cons i int pattern */ 

- ' 1LJU ' ujuuj; ,- * transmit packet of 1000 bv-es *' 

/* receive those rackets */ 
prmtfC'Otart receive loooO)- 
while (1) * 

if (rcv_okt(ie, EDLC_ALL I EDLC GOOD) > n) f 
size = inw(lE RP(ie))- ~/* Mn- 1 - -u« 

: Jt i'lv.i.i ?cl , S1Z9);} * ' 

else i ereset f i e ) r ^ 

'■larch 15, I9fll 

- 15 - 

5_. Setting the Jumners 

^; a "° ry settings on the IE work with software supplied bv 3Ccm 
Only extraordinary circumstances or use with non-lc™ Inl Y 1 
require alteration of the factory settings software would 

the DIX connector ^s the fifrll lndriCal conne «or for a coaxial cable; 
select the hm! ? ^ P1 " conne ct°r. The DMA1/DMA3 jumoers 
select the DMA cnannel used by IE. The DMA function requires a otir 

XUT3/istI S! , SUrS , h3t the settin ^ of the two jumper agree, ^e 

" s-^^^r^se^^^L^r^hr^re^rl^he XT "' ^ 

factor ' JT' PR0M<19 "^> ••!•« thVbasfad^es^of « S^roS*"^ 
factory address setting is ecOOO, hex; however, the PROM is disabled 

^,^^ F " L when = han <5in<? the jumpers. If the jumpers are imorooerlv 
installed, lt is possible to short together +5V and GND lra P r °Perl/ 



Factory Settina 
















selectabl e 












PROM 19 




P ROM 1 8 



PROM 17 



P ROM 1 6 



selectabl e 

n R0M15 



sel ectabl e 

v ROM 14 



P ROM 1 3 


P ROM 1 2 


PROM ENABLE JP1 4 disable 

6. Ethernet Interface 

The IE provides two options for connection to an ^thernef w , Jf , MM 
by a mmner. ^h- -,-«=* ,• = .u., ^,„^-., ~. ,- '_ ernet ' ^electable 

fun: ^-atlb,/ 1 '^n,:;: ^^% ™:^ ni < outI -- «*"="-• 

sceiver -jble W-^ ^ ^ l ■ ou.lot attaches no a standard tran- 

scei/.r ,.,ble, «,..*<.•.. :n -irn 1, connoctc-d to any Ethernet transceiver. 

March ] ( 5, i^q 

- 16 - 

This would presumably be the usage when an Ethernet was ore-installed 
with "thick" Ethernet cable. 

The other Ethernet interface uses the onboard transceiver and is 
designed to be used with, "thin", low-cost (50 ohm) RG-58A/U coax. 
The integral transceiver is attached to the Thin Ethernet cable via "a 

s 1 n ? ] e 8 .NC connector on the box, to be mated with a BNC "T" pre- 

installed on the RG-58 coax. The station can be couDled and uncoupled 
without affecting network operation. The integral transceiver pro- 
vides complete electrical isolation. 

The RG-58 Ethernet is electrically compatiole with the vellow Ethernet 
coax. In fact, the RG-58 Ethernet can be attached to a yellow Ether- 
net^by^ simply coupling them with an N-series/BNC adapter, and IEs can 
couuuuniuate with any other station on the RG-58 or yellow coax. One 
drawback of the RG-58 Ethernet is that the distance limitation is more 
severe: approximately 300 meters of an RG-58-only segment. 

2« Known Rugs Found on Early Production IEs 

Receiving a runt packet can lock. up the controller while in receive 
mode regardless of the setting of Detect Short Frames, bit three of 
the Receive Command Register. Reading the Receive Status Register 
after reception of a runt permits reception of further oackets. This 
is not a problem for software using polled 10; such software can read 
the Receive Status Register in the same loop that checks the Auxilli- 
ary Status register for Receive Busy. Interrupt driven software must 
set Detect Short Frames to insure that runts generate interrupts: 
interrupt level software can then read the status register in order to 
receive subsequent packets. 

It is possible to get one false interrupt for each wrine to the 
Receive or Transmit Command Register. Software can distinguish false 
interrupts from true ones by examining Receive Busy and Transmit Busy, 
bits zero and seven respectively of the Auxilliary Status Register. 
Well written software would routinely check for * these conditions 
before taking action to disturb the state of the controller. 

Software running at interrupt level can easily prevent false inter- 
rupts by reading the status register immed i atel v after writing the 
control . register. 

Software running at main program level cannot nrevent false interrupts 
that way because an interrupt would occur beforo main urogram level 
could read the status register. Interrupt lovol v^u : 2 then be respon- 
sible for clearing the interrupt by reading -he status reaisters. 

March i r i, l r »9.i