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3Com 



computer communication compatibility 

3G400 Multibus 

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Reference Manual 



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3ComCaporatbn 

f computer communication compatibility 



Model 3C400 

MULTIBUS Ethernet (ME) Controller 

Reference Manual 

May 18, 1982 



ABSTRACT 



This document describes the 3Com 3C400 Multibus Ethernet Controller that 
connects any Multibus compatible system processor to a DEC- Intel -Xerox 
Ethernet Communication System. 



3Com Corporation 1390 Shoreblrd May, Mountain View, California 94043 USA 

C415) 961-9602 Telex: 345546 



Table of Contents 



3C omCaporation 

computer communication compatibility 

TABLE OF CONTENTS 
CHAPTER 1 - 3COM ME CONTROLLER SPECIF ICATiONS 

1.1 DESCRIPTION 

1 .2 ME FEATURES 

1.3 ME SPECIFICATIONS 

CHAPTER 2 - BACKGROUND INFORMATION 

2.1 BASIC ETHERNET SUBSYSTEMS 

2.2 EXAMPLE FILE TRANSFER 

2.3 HOW 3COM PRODUCTS IMPLEMENT ETHERNET 
FOR MULTIBUS COMPATIBLE SYSTEMS 

2.4 ETHERNET OPERATION 

2.5 TRANSMISSION SUBSYSTEM 

2.6 ME CONTROLLER SUBSYSTEM 

CHAPTER 3 - PHYSICAL DESCRIPTION 

3.1 ENVIRONMENT 

3.2 PACKAGING 
3.1 BLOCK DIAGRAM 

CHAPTER 4 - 3COM ME PROGRAMMING 

4.1 MEMORY ALLOCATION 

4.2 TRANSMIT/RECEIVE 

4.3 PROGRAMMING ANOMALIES 

4.4 OPERATION 

CHAPTER 5 - INSTALLATION AND CONFIGURATION CONS I DERATIONS I 

5.1 INSTALLATION CHECKLIST 

5.2 ETHERNET ADDRESSING CONSIDERATIONS 

CHAPTER 6 - FACTORY WARRANTY 
APPENDICES 

A. ORDERING INFORMATION \ 

B. BIBLIOGRAPHY 



3ComCaporation 

j- S^putifcbmmunication compatibly 



Specifications 
Description 



CHAPTER t 
3CX)M ME CONTROLLER SPECIFICATIONS 



1.1 DESCRIPTION 

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to Ethernet for any Multibus compatible system processor. It consists of 
one Multibus (IEEE-796) board that plugs Into the Multibus. (See Figure 
1-1 below). 




FIGURE 1-1. 3COM MULTIBUS ETHERNET CONTROLLER BOARD SET 



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Specifications 
3COITI CapOration Description 

computer communication compatibility 

Connection from the 3C400 ME Controller to Ethernet Is made via the 

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juurn ciiici uei iranbteiver ana iransceiver ^auio, wi any win^i i_...~. ..^. 
compatible transceiver and cable. 

The 3C400 Controller, 3C100 Ethernet Transceiver and the 3C110 
Transceiver Cable conform to the Ethernet specifications, version 1.0, 
published by DEC, Intel, and Xerox on 30 September, 1980. When coupled 
with customer supplied driver software, they implement layers one 
(physical) and two (data link) of the International Standards 
Organization Reference Model for Open Systems Interconnection, Any 
Multibus compatible system processor so equipped will be compatible with 
any other Ethernet-based system at the physical and data jink ieveis. 



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3Com Corporators *~' *£»™ 

computer communication compatibility 

1 .2 ME FEATURES 

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• Compatible with Multibus UEEE-796). 

• Connects to Ethernet using 3Co i ' Fernet Transceiver and Transceiver 
Cable or any other transceiver and cable that conform to the Ethernet 
specification. 

• Controller, transceiver, and cable together provide a complete hardware 
fmnj ©mentation of the Ethernet specification except for multicast address 
comparison and random number generation for retransmission timing. 

• Includes 8K byte dual -ported me*mory which appears In Multibus memory 
space. Transmission between the dual-ported memory and Ethernet do not 
consume Multibus cycles, allowing concurrent processing. 

• Three 2K byte buffers can each handle maximum packet size allowed by 
Ethernet specification. One buffer is dedicated to transmission, two to 
reception of Ethernet packets. 

•Under software control, each packet buffer may be independently 
connected to either the Ethernet or the Multibus. 

• Multibus-addressed buffers allow in-place packet assembly, processing 
and multiplexing. 

• Can receive minimally spaced packets. 

• Controller can be selectively enabled to recognize packets containing 
station address, broadcast packets, multicast packets or a I i packets. 

• Ethernet address assigned by 3Com is held in PROM on controller and can 
be referenced or replaced by software when loading address recognizer. 

• Manchester decoding using phase- locked loop circuitry. 

• 32-blt CRC generated on transmission and verified on reception. 

• Hardware generation and removal of preamble. 

• Hardware retransmission timing with random number supplied by software. 

• Hardware detection of oversized and undersized packets and alignment 
errors. 

• Functions as 16-bit memory slave and is compatible with 8-bit and 
16-blt masters. 

• Contained on one Multibus board. 



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3Com Caporatbn 

computer communication compatibility 

1.3 ME SPECIFICATIONS 



Specifications 
ME Technical 



Compat I b 1 1 1 ty 

Ethernet 

Multibus 
IEEE-796 
Functions 



Memory 

Transmit 

Rece I ve 

Control 4 Status 



Conforms fully to Ethernet specification, 
version 1.0, published 30 September, 1980, by 
DEC, Intel, and Xerox. 



Conforms fully to Multibus specification. 
Functions as 16— bit memor w s'a^'e 
with 8-bit and 16-bit masters. 






Compliance Is D16 M24 V0 (16-bit transfers, 
24-bit addressing, non-bus vectored 
interrupts). 



Ser I a I / p ar a I I e I and para I I e I / ser I a I 

conversions. 

Transmit and receive buffering. 

Framing of packets. 

Manchester encoding and decoding. 

Address recognition 

Collision and error detection. 

Preamble generation and removal. 

Carrier sense and deference. 

Backoff and retransmission timing. 

Collision fragment filtering. 

Frame check generation and detection. 

Alignment error and overrun filtering. 



One 2K byte dual -ported RAM memory. 

Two 2K byte dual -ported RAM memories. 

Registers which occupy 2K bytes'- of Multibus 
address space. * 



Byte Ordering 



Address 



Low order first or high order first, switch 
selectable. 

Occupies 8K bytes of Multibus memory address 
space. Starting address set by switches at 
any 8K byte address boundary In range to 
1016K bytes. 



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3Com Corporation 

computer communication compatibility 



Specifications 
ME Technical 



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Bit Rate 
Packet Spacing 
Transmit Delay 
Receive Delay 
Jam Time 



10 million bits per second 

9.6 microseconds minimum 

1 microsecond typical, without deference 

3 microseconds typical 

Transmits 32 bits of zeroes when collision is 
detected. 



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Ethernet Packet Format 

Length 

Format 



Frame check sequence 



rreamD i e 



512 bits minimum, 12,144 bits maximum, 
excluding 64-bit preamble. 

Destination Address 48 bits 

Source Address. •••... ••••48 bits 

Type.. ....16 bits 

Data 8n bits 

where n=46 minimum, 1500 maximum 
Frame Check Sequence..... 32 bits 

32 bit CRC generated on transmit, verified on 
receipt. 

Generated and removed by control ier. 



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3ComCaporatbn 

Address Recognition 



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Address Recognizer 



Specifications 
ME Technical 



Unique 48-bit address assigned by 3Com. Held 
In socketed PROM on controller, appears In 
Multibus address space. 

Station Ethernet address held In RAM memory, 
may be loaded from Ethernet address PROM or 
with an address supplied by software. Can be 
selectively enabled by software to recognize 
packets containing: 

Station or broadcast address 

Station, broadcast, or multicast address 

Any -address 



Error Hand S I ng 



Controller can be selectively enabled by 
software to reject packets with FCS, a I Ignment 
or range errors. 



I nterrupts 

Interrupt Conditions 



Priority levels 



Software Functions 



Installation 

Size 



Selectively enabled by software: 

Transmit done 
ReceUe buffer A ful I 
Receive buffer B full 
Col I is ion (jam) 

Al ! interrupts use a common priori iy isvci, 
jumper selectable from INTO to INT7. 



The following functions must be performed by 
customer software: 

Loading of Ethernet address 
Multicast address comparison. 
Random number generation for 
retransmission timing after collision. 



One Multibus-standard board 

30.5cm X 17.1cm 
12in X 6.75in 



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3ComCaporation 

Siots 



Specifications 
HE Technical 



Power 



Bus loading 



Requires one slot. 

5 A at +5V 

0.5A at +12V for transceiver 

One DC load 



Transceiver cable connector Ethernet-standard female 15-pln "D" 

subminfature connector attached to the 
controller via cable. 



Transceiver cable 
Ethernet address 

Operating Environment 

Temperature 
Humidity 



Uses Ethernet-standard transceiver cable which 
must be ordered separately. 

Unique address suppl ied by 3Com for each 
controller, contained in onboard PROM. 






1 0/6 to 90$ without condensation 



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3ComCorpaatbn 

^^iToSSSScation compatibility 



Background information 
Ethernet 



CHAPTER 2 

BACKGROUND INFORMATION 

This chapter covers some background Information about both the 
Ethernet and the 3Com ME Controller. 

In the last decade, computers have grown from a luxury to a 
necessity in most businesses. Similarly, in the next decade, 
Inter-computer communication will grow from a luxury to a necessity. 

me k-iiiOi iJSi hoiWOi i\ , ucvciv^cu iwi iiiav.tiiiic iiiqv>iiiiic v,uiMiiiuiii^ai ium, 

was pioneered at Xerox Corporation as an appropriate implementation for 
inter-computer communications. In use since 1974, the Ethernet has 
evolved to an Industry standard, documented In the Ethernet 
Specification, published September 30, 1980 by DEC, Intel, and Xerox. 

The benefits of modern computerized workstations are now magnified 
as they communicate information to other devices at 10 million 
bi ts-per-second over the Ethernet. What's more the Ethernet network can 

be tailored to end user's needs and workstations once the Ethernet 

i 
coaxial cable is in place. This means multiple workstations can share 



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2-1 



3 ComCorporation 

resources such as: 



Background Information 
Ethernet 



Word processors 

Printers 

E I ectron I c ma 1 1 sy stems 

Graphics stations 

Transaction workstations 



Data bases 

Process control stations 

Array processors 

Laser printers 

Etc. 



Individual workstations and shared resources are plugged into 
Ethernet information Outlets in the wall the same way telephones are 
plugged into telephone wall-outlets. However, the Ethernet's 15-pin 
connector Is more complex than a telephone connector. 

Each Ethernet device is assigned a unique address (like a unique 
telephone number), therefore, it can be moved around and plugged into any 
convenient Ethernet information outlet. Further, all devices plugged 
into the Ethernet can talk to each other, by mutual agreement, similar to 
two people talking on the telephone. 

Ethernet, due to Its standardized physical and logical protocol, 
allows users to mix and match equipment from multiple vendors. 

In the future a voice capability will probably be integrated Into 
Ethernet for store-and-forward voice communications to complement 
electronic mai I. 



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2-2 




3Com Corporation 

^^^^Eat«n compaUbAW 

2.1 BASIC ETHERNET SUBSYSTEMS 



Background Infornatlon 
Ethernet Subsystems 



( 



The Ethernet Is a bus-oriented communication system that supports up 
to 100 stations using a 50 ohm coaxial cable as the bus. 

Figure 2-1 below shows the basic parts of a typical Ethernet system, 
... * 4-k uAri/e'fa+inne ^Annor+eH +n +he F+hemet coaxial cable. 

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The Transmission Subsystem is made up of 50 ohm coaxial cable, 
terminators, transceivers, and transceiver cables. 

The Controller Subsvstem is the set of controller boards and the software 




FIGURE 2-1. BASIC ETHERNET SUBSYSTEMS 



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2-3 



Background Information 
3COITI CorpaatbTI Ethernet Subsystems 

f computer communication compatibility 



I 



supporting them. 

The Station Subsystem Is everything else associated with the station, 
such as, the terminal, processor, disk, and higher level protocol 
software. 

These three subsystems are discussed again later in this chapter, in 
terms of 3Com product implementation! 

Meanwhile, the following example describes how a file of information 
is transferred from one device to another using Ethernet. 



2.2 EXAMPLE FILE TRANSFER 

(This is an example text file transfer using a File Transfer Program 
running on the host processor.) 

1. The terminal user runs the File Transfer Program, connects to the 
receiver, and specifies the file to be transferred. 

t 

2. The file's characters are mapped into device-independent virtual 

* 

characters (by software) to meet protocol specifications. 

3. The mapped character stream is then routed to a virtual circuit set up 
between the two devices. 

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" ' Background information 

3COITI Caporatbn Examp I e F 1 1 e Transfer 

/ computer communication compatibility 



4 S The virtual circuit protocol software breaks the character stream Into 
packets for transmission. (It also retransmits corrupted packets, and 
limits data rate to avoid overruns.) 

5. The packets are then passed to the Ethernet driver software. 

6. The Ethernet driver then copies the packet Into a packet buffer and 
tells the controller to transmit it. 

7. The controller waits until the coaxial cable is not in use, then 
transmits the packet. 

8. The Ethernet transceiver receives the packet's bit stream and injects 
it onto the coaxial cable, (if the transceiver detects a collision, it 
signals the controller to retransmit.) 

9. The receiving station recognizes its address and reverses the above 
procedure: bits are received by the transceiver, fed to the controller, 
passed to software that reassembles the packets, maps the characters, and 
stores the data. 



5/18/82/TC0MME2/ 2-5 



Background Information 
3Com Corporation 3Com Implememtation 

^ computer communication compatibility 

2.3 HOH 3COM PRODUCTS IMPLEMENT ETHERNET FOR MULTIBUS COMPATIBLE DEVICES 



For a complete local computer network, there are only three 
additional components needed by Multibus compatible systems: 

1. 3Com Ethernet Transceiver - fully conforms to published Ethernet 
specifications and connects directly to the Ethernet coaxial cable. 

2. 3Com Ethernet Controller - plugs directly into the Multibus 

3. Higher-level Protocol Software - providing high-level network protocol 

services - including data link drivers. 3Com f s UNET Software is UNIX 

f 

I compatible and provides the Internet Protocol (IP), Transmission Control 

Protocol (TCP), file transfer protocol (UFTP), electronic mail protocol 

(UMTP), virtual terminal protocol (UVTP), etc. 



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V cc 



Background Information 
3Com Corporation Ethernet Operation 

computer communication compatibility 

2.4 ETHERNET OPERATION 



The Ethernet Is a carrier sense, multiple access transmission system 
with collision detection (CSMA/CD). To transmit a packet, a station 
waits for quiet on the network (defers). When the network Is quiet. It 

i ui i a t \* f i uiuiii i i ■ no ua^.r\C i . 

During packet transmission, the station also watches for collisions 
with other transmitters; these may occur within one round-trip time 
through the network. The station Is said to have "acquired the network" 
If no collision occurs In that time Interval. If a collision does occur, 
. the station transmits 4 to 6 additional bytes of data (jam) and the 

| aborts the packet. The extra bytes insure that any other participant in 
the collision is sure to see it. The station then waits a random amount 
of time (backoff) before retransmitting (after deferring to packets in 
progress on the network ) » 



2.5 TRANSMISSION SUBSYSTEM 



The transmission subsystem, In the form of a 3Com "starrer package", 



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Background Information 
Transmission Subsystem 



{ 3Com Caporation 

I computer communication compatibility 

(Model 3C440) Is shown In Figure 2-2 below. It consists of four types 
of components: transceiver cables, transceivers, coaxial cable, and 
terminators. These are described below. 

Transceiver Cable - The transceiver cable Is a 15 meter shielded twisted 
pair cable that connects the controller to the transceiver* It has 4 
pairs, one each for transmit, receive, collision detect, and power. It 
has a male 15 pin connector with lock posts on the controller end and a 
femaie 15 pin D connector with slide lock assembly on the transceiver 
end. Thus the cables can be concatenated to make a longer cable, up to 
the maximum length of 50 meters. 



Station No. 1 



Station No. 2 



Station No. 3 






Transceiver 

Cable 

15 meter 



Transceiver No. 1 



V 



Terminator 



Transceiver 

Cable 

15 meter 



Transceiver No. 2 



I 

> C=*=f f C T3 < 

Coaxial Cable 
15 meter 






Transceiver 

Cable 

15 meter 



Transceiver No. 3 



i 0=s 

> C^3 if- cj A 

Coaxial Cable 
15 meter 



Terminator 



30 meter - 



Ethernet Transmission System 



FIGURE 2-2. 3COM ETHERNET TRANSCEIVER STARTER PACKAGE 



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Background Information 
Transmission Subsystem 



3 Com Corporation 

computer communication compatibility 

To minimize EMI (electro magnetic Inteference), the connectors have 
jn+ S rna! shields connecting the cable shield to the shell of the 
connector. 

The male cable connector can either be brought out of the wall to the 
station or mounted on a cover plate providing a bulkhead disconnect at 
the wall. When mounted on the cover plate, it has been referred to as 
the "Information Outlet." (see Figure 2-3 below) 

Transceiver - The 3Com transceiver Is compatible with the DEC, Intel and 
Xerox Ethernet specification, it makes a high Impedance connection to 
the common coaxial cable and provides electrical isolation oeTween tne 







Ethernet 

Information 

Outlet 







P ; 









FIGURE 2-3. INFORMATION OUTLET 



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«*™«rnrrvYatinn Background Information 

3UOm UCXpOraiur 1 Transmission Subsystem 

/ computer communication compatibility 

coaxial cable and the twisted pair cable. 



The transceiver Injects transmit signals from the controller Into the 
coaxial cable. The transceiver also receives signals from the coaxial 
cable which appear on the receive lead of the transceiver cable with 
balanced signal I Ing. 

The receiver also provides correction for signal distortions caused by 
traveling through long lengths of coaxial cable. 

The collision signal appears If there Is a signal present from any other 
station on the network. When transmitting, this Indicates a collision. 
( When not transmitting, it Indicates the presence of other signals on the 

network. 

Coaxial Cable- The coaxial cable Is a 50 ohm cable with multiple 
shields to minimize susceptabi I ity to strong RF fields. 

Cable Connectors - Cable sections are terminated with standard N-series 
connectors. Rubber boots cover the connectors to prevent multiple 
connections of the coaxial shield to building grounds -j a potential 
source of ground Induced noise Into the coaxial shield. Coaxial cable 
sections are joined by Insulated barrel connectors (N-Serles 
female-female adapters). 

Terminators - The ends of a coaxial cable segment are terminated with 50 
5/18/82/TC0MME2/ 2-10 






Background Information 

3Com Corporation Transmission Subsystem 

computer communication compatibility 

ohm terminators with Insulated outside covers. 



2.6 ME CONTROLLER SUBSYSTEM 

The ME Ethernet Controller Interfaces the transceiver to the 
Internal bus of the Multibus system to which It Is connected. It 
performs serial-parallel and parallel-serial conversion, buffering, CRC 
generation and checking, address recognition, phase encoding and decoding 

- discussed below. The I/O structure and speed of the processor 
determine kqw these functions are partitioned between hardware and 
software (or microcode) in the Ethernet station. 

Buffering: Most processors have bus transfer rates that are unduly 
stressed by the 10Mbps Ethernet bandwidth, therefore, full packet buffers 
are provided to keep pace with the bit rate of network traffic. 

CRC Generation And Checking: The cyclic redundancy code (CRC) uses the 
32 bit polynomial from the U.S. Department of Defense Autodin II system. 
The CRC function is implemented in hardware on the ME. 

Address Recognition: The controller watches every packet that passes to 

i 

deterrri /nether to accept the packet, based on its destination address. 

The MF r^n+rnllor Imn I pme>n+c aHrlroQc rprnnnftinn ?n harriwgre to minimize 

CPU overload. 

Phase Encoding, Decoding, and Transceiver Interface: Manchester 
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Background Information 
3COITI CapaatOI 3Com Controller Subsystem 

computer communication compatibility 

encoding Is used for data transmission on the Ethernet. It has a 50$ 

j. j... • - ti.. xi j. l_ix _x _ Ltj. ..it /-nn+aim; +he comD I ement of the 

ouiy uy 1. 1 c ii ic i 1 1 a i iiair wt a uii wi i ^w. .-.--- __ r 

bit and the second half of the bit cell contains the bit. 



Phase Encoding is done in the controller by exclusIve-ORing the clock 
with the data. (Decoding is also performed In the controller. 
Partitioning of encode-decode functions Into the controller rather than 
the transceiver minimizes wires to' the transceiver while minimizing 
transceiver size and power dissipation.) 

Phase Decoding in the ME Controller is done by an analog phase-locked 
loop technique. This technique has the advantage of tolerating more 
phase jitter than alternative techniques in use, twice the tolerance of a 
typical one-shot decoder and four times the tolerance of a typical 
digital state-machine decoder. 

The Transceiver Interface contains line drivers and receivers. 



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3Com Corporation 

computer communication compatibility 



Physical Description 
Env I ronment 



CHAPTER 3 



~ .**«»■ na a nrpftOIDTiny 

mT^IWU. UCOWXirnun 



3.1 ENVIRONMENT 

The ME Controller interfaces a Multibus compatible processor to an 
Ethernet transceiver. 

The ME Controller plugs into the same Multibus backplane as the 
processor and resides in the same enclosure with it. An Ethernet 
transceiver cable (approximately 50 feet long) connects the ME Controller 
to the Ethernet transceiver. The Ethernet transceiver in turn taps 
directly into the Ethernet coaxial cable. 

According to the International Standards Organization Open Systems 
Interconnection Reference Model, the ME Controller performs part of both 
the physical and link layer services, the first and second of seven 



l : ':S/S;-/TC0MME3/' 



3-1 



3Com Corporation 

computer communication compatibility 

layers of service (see Figure 3-1 below). 



Physical Description 
Environment 



The two main functions of the ME In the link layer of the ISO Model are: 

1. Data Encapsulation 

o framing (frame boundary delimitation) 

o addressing (handling of source and destination addresses) 

o error detection (detection of physical channel transmission errors) 



APPLICATION 

PRESENTATION 

SESSION 

TRANSPORT 

NETWORK 

LINK 
PHYSICAL 



LEVEL 
PROTOCOLS 



NET 




HOST COMPUTER 



■CONTROLLER BOARD 
-TRANSCEIVER 
■COAXIAL CABLE 



FIGURE 3-1. ISO PROTOCOL HIERARCHY 



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f - 



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r 



Physical Description 
3C om CapaatJOn Environment 

computer communication compatibility 

2* Link Management 

o channel ai location (collision avoidance) 

o contention resolution (collision handling) 

In the physical layer of the ISO model, the controller performs 
preamble generation/removal and bit encoding/decoding (between binary and 
phase-encoded form). 

3.2 PACKAGING 

The ME Controller is a single multibus compatible PC board whose 
overall dimensions are 12 inches x 6.75 Inches. It uses one Multibus 



5/18/£;-vt::;-:'. r.3/ 3-3 



3Co mCapaation 

^mputer communication compatibility 

backplane slot as shown in Figure 3-2 below. 



Phys!ca! Description 
Packaging 



On the edge opposite the gold fingers is a 14 pin male header. A 
shielded cable, with four twisted pairs terminated to a female socket at 
one end, mates the ME Controller to the Ethernet Transceiver Cable. At 
this end of the shielded cable is a tin plated sub-miniature D connector, 

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it w ii i v» i w wtwin vviinbv i d iw iii« Jiueiv vi i • i i w • n i .* t w |^w ■ i vuk i w mi in** 

controller end. This shield drain is to be connected to the chassis 
ground of the Multibus cardcage. 

The ME Controller is a high density four layer PC board with two 
circuit trace layers plus continuous ground and Dower planes. 




FIGURE 3-2. ME PACKAGING ENVIRONMENT 



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3-4 



Physical Description 
3Com CapOratDn Packag I ng 



computer communication compatibility 



I 



( 



j^_* —..i , i- - 



me ru layouT oesign ruies toi iowea are: 

o Ten mi I traces 

o Ten mi I air gaps 

o At most two traces between IC leads 

o Four layer pcb 

o Intact internal voltage and ground planes 

The ME Controller can be used with any transceiver that conforms to 
the DEC- Intel -Xerox Ethernet specifications. 



5/18/82/TC0MME3/ 



■? _n 



3ComCaporation 

^^irro^muncation compatibility 



Physical Description 
Block Diagram 



T X m DTK n I AftPAM 



The major ME Controller components are shown In Figure 3-3 below. 

The ME Controller presents to the Multibus a full 16 bit interface. 
All bus transfer instructions to a 16 bit slave device are implemented on 
this control ler. 

The 3Com Multibus Ethernet Controller is memory-mapped and therefore 
appears as 8K bytes of memory on the Multibus; 4K is used for two receive 
buffers and 2K is used for one transmsr buner. mere a. e .~u, - r .~~ ^. 



ETHER. 

ADDRESS 

MEMORY 



STATUS 
& CONTROL 



1 



16 BIT 



RECEIVE 
MEMORY 



ADDRESS 
COMPARE 



RECEIVE 
SYNCH 



PARALLEL 
CONVERS 



4 



ADDRESS 
MULTIPLEX 



UJ 



I RECE i VE 
SEQUENCE 



BYTE 
COUNTER 



CRC 
SECTION 



ECL 
SECTION 



XCVR 



ADDRESS 
MULTIPLEX 



L 



BUS 
TIMING 



TRANSMIT 
CLOCK 



TRANSMIT 
MEMORY 



SERIAL 
COUNTERS 



TRANSMIT 
SEQUENCE. 



FIGURE 3-3. PC CONTROLLER FUNCTIONAL BLOCK DIAGRAM 



5/16/82/TCOMME3/ 



| 3Com Corporation ""''""biSadi"'*'* 

f computer communication compatibility ** 

control and two words of status In the lowest 2K of memory. The actual 

device address Is switch selectable on any 8K boundary. 



On transmit, the processor loads the packet to be sent Into the 
TRANSMIT MEMORY (see Figure 3-3 above). Once the transmit bit Is set in 
the control byte no further processor Intervention Is required. 
Successive bytes are taken from the TRANSMIT MEMORY and placed Into the 
SERIALIZER where they are converted to a serial bit stream. The 
serialized data is fed to both the CRC (Cyclic Redundancy Check) and to 
the ECL SECTION which does a level conversion to be compatible with the 
Ethernet Transceiver. The CRC is automatically appended to the end of 
the transmit data packet. 

( 

I 

On receive, the processor must first make available to the ME one or 

both of the RECEIVE MEMORIES available (see Figure 3-3 above) by setting 
■ u6 proper control bits. Since hardware address recognition is 
incorporated Into this design, the receive packet is further qualified. 
The ME can be hardware configured to receive only packets with correct 
physical, multicast, and/or broadcast addresses. After address 
recognition, the Ethernet data enters the ECL SECTION where a phase lock 
loop generates a proper synchronizing clock from the incoming date. Also 
the ECL SECTION does a level cpnverslon to TTL signals. The serial data 
Is sent to the PARALLEL CONVERSION logic (and converted to a byte format) 
and to the CRC SECTION. The CRC Is calculated and compared to the CRC 
[' code appended to the end of the packet by the transmitting station. If a 

CRC error occurs, (Frame Check error) a flag is set in the first byte of 

the RECEIVE MEMORY. 

5/18/6?.'™" ~3/ 3~" 



3C omCapqation 

f computer communication compatibility 



Programming 
Memory Allocation 



CHAPTER 4 

HE PROGRAMMING 

The following chapter Is important for development of software 
drivers. 

4.1 MEMORY ALLOCATION 

The ME occupies 8K bytes of the Multibus 24 bit address space. See 
Figure 4-1 below. Switches on the controller select the base address of 



MECSR Control and Status 


Regi 


ster 


MEBACK 


Retransmission 


Backoff 


Counter 


C+a+!«n 


AHHrocc PHM 












Station 


Address RAM 








Transmi 


t Buffer 








Receive 


Buffer A 








Receive 


Buffer B 









MEBASE 


+ 


2H 


MEBASE 


+ 


400H 


MEBASE 


+ 


600H 


MEBASE 


+ 


800H 


MEBASE 


+ 


1000H 


MEBASE 


+ 


1B00H 
1 



FIGURE 4-1. ME BUFFER ORGANIZATION 8K BYTES, 
ADDRESSES IN HEX 



5/18/82/TCCMME^ 



4-1 



3Com Corporation 

computer communication compatibility 



Programming 
Memory Allocation 



the ME memory called MEBASE. MEBASE must be aligned on an 8K byte 
hnynHaru The control I er n 3rt!ons Its mernor u Into six re n !ons as 
follows: (Also see Figure 4-1 above.) 



1 . Control region 

2. Station address ROM 

3. Station address RAM 

4. One 2K byte transmit buffer 

5. First 2k byte receive buffer 

6. Second 2k byte receive buffer 



(MEBASE) 

(MEBASE + 400H) 

(MEBASE + 600H) 

tMEBASE + 800H) 

(MEBASE + 1000H) 

(MEBASE + 1800H) 



Software uses the registers In the control region to manipulate the 
controller and read its status. There are two registers in the control 
region: 

1. MECSR, the control and status register, at MEBASE 

2. MEBACK, the retransmission backoff counter, at MEBASE+2. 

NOTE: The byte-ordering switch, TRB (See section 5.1) will affect the 
ordering of the bytes In both MECSR and MEBACK. If the TRB switch Is 
OFF, MECSR and MEBACK are as shown In In Figure 4-2. If the TRB switch 



5/18/82/TC0MME4/ 



4-2 



■— ' """ Programming 

3Com Corporation T *>i°«+ion 

-computer communication compatibility 

Is ON the bytes of MECSR and MEBACK are reversed. See Figure 4-2 below, 



The station address ROM, at MEBASE+400H, holds the six byte station 
address of the controller. The address recognition circuitry uses the 
station address RAM, at MEBASE+600H, to compare the destination address 
of packets from the ether when deciding whether to accept a packet, 

Software must write the sta+Inn aHdr&*z*z Into the RAM anH "nfwoM +h*a 

address to the controller by writing one Into AMSW. Any further 
references to the address memory are Ignored until reset. 



<3|U 


13 


12 


11 


10 


9 


8 


7 


6 


5 


4 


3 



PA 








JINTEN 








TINTEN 








AINTEN 








B i NTEN 








reset (reads 


as zero) 


not used 








F83BA state of 


A w 


ten B 


arrives 








AMSW 1 => 


be I 


ongs 


to 


Ether 








•JAM, writ 


n S 


1 clears 


jam 








TBSW 1 => 


be I 


ones 


fro 


Ether 








ABSW 1 => 


bel 


ongs 


to 


Ether 








BBSW 1 => 


bel 


ongs 


to 


Ether 









FIGURE 4-2. MECSR=MEBASE, THE MULTIBUS ETHERNET 
CONTROL AND STATUS REGISTER 



5/.18/82/TC0MME4/ 



^-3 



3Co mCaporation 

computer communication compatibility 

( 4.2 TRANSMIT/RECEIVE 



Programming 
Memory Allocation 



The transmit buffer starts at MEBASE+800H {see Figure 4-1). The 
first word of the buffer Is MEXHDR, the transmit buffer header, as shown 
In In Figure 4-3 below.. To transmit, align the packet In the buffer so 
the last byte of the packet coincides with the iast byte of the transmit 
buffer. Set up MEXHDR to contain the offset of the first byte of the 
packet. Finally, set TBSW to one.. As long as TBSW remains one, the 
transmit buffer Is busy and belongs to the controller; (any reference to 
It Is Ignored). When TBSW becomes zero, transmission Is complete and the 
transmit buffer Is available to software once again. In the event of a 

CQ\ I ? Q ! on +ho r-on+rrkl I or ep+e I AM +*■» ^n*a T*% s = £ .4-^ s «^«:^- «*.u -. »k „. _~ t, -. -t 

~.^. . ._.„.., ...w ■«*/.. > • v ■ i vi 3© i s wAi"i iv wnSt i v i € i i an sin i i i nc DaCisc i . 



MEXHDR=MEBASE+800, I HE TRANSMIT BUFFER HEADER 



unused 



11 



offset of first byte 



FIGURE 4-3. MEXHDR=MEBASE+800, THE TRANSMIT BUFFER 



5/18/82/TC0MME4/ 



4-4 



— Programming 

3COITI CapOrafon Transmit/Receive 

compute, communication compatibility 

software must write the two*s complement of the number of siot times to 
delay into MEBACK; then write a one back into JAM. Writing Into MEBACK 
when JAM Is not set produces unpredictable results. 

The ME provides two buffers to receive packets from the ether. 
Software controls these buffers with two bits in MECSR; one for each 
buffer. ABSW controls receive buffer A which starts at MEBASE+1000H. 
BBSW controls receive buffer B which- starts at MEBASE+1800H, (See Figure 
4-1 on Page 4-1) To receive a packet In A, set ABSW to one. While ABSW 
remains a one, any reference to A will be Ignored. ABSW will remain one 
as long as the buffer belongs to the controller; when ABSW becomes zero 
the buffer contains a packet and belongs to the software. To receive a 
packet In B, the software manipulates BBSW similarly. If both ABSW and 
BBSW are zero after giving both receive buffers to the controller, RBBA 
helps the software decide which buffer has the oldest packet: If RBBA Is 
zero, then the packet In A Is older than the packet In B. If RBBA is one 
the packet in B Is older than the packet In A. 

The header (first) word of both receive buffers are cal led, MEAHDR 



5/18/82/TC0MME4/ 4-5 



Pr<uQi an hi ! ng 
Transm I t/Rece I ve 



3Com Capaation 

computer communication compatibility 

and MEBHDR, see Figure 4-4 below* The received packet minus the preample 
starts Immediately after the buffer header. After a packet arrives, the 
controller writes a status word In the buffer header. The low order 
eleven bits specify the offset of the first free byte after the packet. 
The high order bits contain various status flags, starting with the sign 
bits fcs error, broadcast, range error, station address match, and 



PA allows the software to select which packets the controller will 
accept on receive. The controller classifies all packets on the ether, 
as fol lows: 



MEAHDR=MEBASE+1 000, MEBHDR=MEBASE+1 800 
THE A AND BE RECEIVE BUFFER HEADERS 



15 


14 


13 


12 


11 








■first free byte 
•framing error 
address match 
range error 
broadcast 
fcs error 



FIGURE 4-4. A AND B RECEIVE BUFFER HEADERS 



5/18/82/TC0MME4/ 



4-6 



3ComCaporatbn 

^SputeTcommunicaiion compattoiirty 

Ail 



Range 

FCS 

Frame 

Mine 

Multi 

Broad 

Errors 



Programming 
Transm ? t/Rece I ve 



the universe of packets on the ether 

runts and oversized packets 

packets with frame check sequence errors 

packets with a! ignment errors 

packets with destination address = station address 

multicast packets 

broadcast packet 

range+fcs+frame 



The software sets PA to receive only selected classes of packets. 

u a ! ! 

1 all- errors 

2 all- fcs - frame 

3 mine + multi 

4 mine + multi - errors 

5 mine + muiti - fcs - frame 

6 mine + broad 

7 mine + broad - errors 

8 mine + broad - fcs - frame 

i 
Jumpers on the board select a single interrupt level for the ME 

controller. Setting JINTEN enables Interrupts when JAM is set. Setting 

TINTEN enables Interrupts when TBSW Is zero. Setting AINTEN and BINTEN 

enables interrupts when ABSW and BBSW are zero respectively. The ME 

interrupts whenever any of the masked bits meet the conditions stated 



5/18/82/TC0MME4/ 



4-7 



Programming 
Transm I t/Rece I ve 



3Com Capaaton 

l^p^ieTcommuncation compatibility 

above; in particular, Interrupts are not edge triggered, but ievel 
^rinncroH An intsrruD+ routine should not leave an Interrupt enabled 

II lyyvi v»t _.. . _ r - . . _ . _ 

unless it turns around the buffer that caused the Interrupt. If the 
interrupt routine does not turn around the associated buffer and leaves 
the interrupt enabled, the controller will immediately reinterrupt as 
soon interrupt routine completes. 



r 



5/18/82/TC0MME4/ 4-8 



_ Programming 

3Co m CapaatOn Anomalies 

computer communication compatibility 



4.3 PROGRAMMING ANOMALIES 

MECSR and MEBACK are replicated all through the control region. 
There Is no method to read the value of MEBACK. If the software attempts 
to read MEBACK, It wfii read MECSR Instead. 

The station address ROM Is the first six bytes of an eight byte 
block; this eight byte block is replicated throughout the region. 

The station address RAM Is the first six bytes of an eight byte 
uiock; this eight byte block Is repi icated throughout the region. 

The Interrupt enables for the transmit or receive buffers must NOT 
be set until that buffer has been assigned to the Ether. Enabling the 
interrupts before that time will result In an Immediate interrupt going 
to the processor. Part of the interrupt service routine must include 
disabling the Interrupt enables; otherwise, the processor will stay 
Interrupted. The JAM Interrupt can be left In the enabled state as long 
as desired. 

i 
NOTE:The packet stored into the packet buffer by the 

processor does not include the preamble or FCS, but does 

Include the Ethernet data link layer header fields 

(destination address, source address, and type field) along 

with the data. Since the maximum legal packet size on the 

-V18/0-2/TCOMME4/ 4-9 



Programming 

3Com Corpaatbn Anoma 1 1 es 

^^Tcommunicalion compatibility 

Ethernet is 1514 (excluding the frame check sequence (FCS) 
field), at least 532 bytes of each transmit packet buffer 
will always be unused. Conversely, since the minimum legal 
packet size is 60 bytes (again excluding the FCS field), at 
most 1986 bytes of each transmit packet will be left unused. 

cspuiidi ui ii ly Oi Tiic ui ivci sui irqic iu i iisui c 



_!_ 1_ l_ 



maT minimum ana maximum pacKeT size requiremems are 
observed. 



5/"£/82/TC0MME4/ 4-10 



Programming 
3C om CorpaatOl Operation 

computer communication compatibility 

4.4 OPERATION 



The transmitter and receiver operate Independently, giving the 
programmer the illusion that the Ethernet Is a full -duplex device. In 
fact, only one packet may exist on the coaxial cable at a time. 

Whenever the Ethernet channel is not in use, the packet supplied to 
the transmitter is transmitted as, quickly as possible. The ME hardware 
separates packets by the minimum packet spacing (9.6 - 10.2 
microseconds). 

Whenever @ D?*Cke+ a n n o a r c r\r\ +ho P+horno+ fov^an-l- & K t I « 

* ^ — *•-•■.■**■ *« f* f* ■»* «« ■ «* w > • ■ • ■ w ^ ■ ■ i \* ■ ii v ■ | \ws\w^fc/i Will I O 

transmitting) it is read into a buffer previously supplied to the 
receiver. 

One aspect of the transmit process, the binary exponential backoff 

w . a wi • • , i s i iii p i emeu icu uy i nc; i*tc uai uwai e ai)Q requires SOTTWQTe 

support only for random number generation. When the controller detects a 
collision it sets the JAM bit In the transmit control register which 
causes a 32-bit jam signal to be transmitted and, if the JINTEN bit Is 

set, an interrupt occurs. The software must store a random number into 

i 
the MEBACK register to cause a delay (back off) of tha .j ropriate time 

after a collision. After the delay, the same packet is retransmitted. 

If a collision happens again, the cycle repeats. 



The delay time is an Integral multiple of a slot time (512 bit-times 

5/1 8/52/7 CO 1 -"-^/ 4-11 



Programming 

3ComCapaation operation 

or 51.2 microseconds). The Integral multiple is chosen as a uniformly 
*,:^!h..+ ft rf random Inteaer areater than or equal to zero and less than 2 k 
(2 to the kill power), where k Is either the number of retransmission 
attempts for the packet being transmitted or 10, whichever Is less. This 
algorithm doubles the mean of the delay time each time a collision 
occurs, ensuring the stability of the Ethernet even under extreme 
loading. 

If the number of retransmission attempts exceeds 15 (probably a 
transmission subsystem malfunction), an error should be reported. 

The processor overhead to support backoff In software Is minimal. 
Studies show that Ethernet packets typically experience collisions less 
than 0.03$ of the time. 



5/18/82/TC0MME4/ 4-12 



3ComCorporBtion ln ,t..i«tion 

^u,er commun.cat,on compatibility Check I ! St 



CHAPTER 5 
INSTALLATION AND CONFIGURATION CONSIDERATIONS 

5.1 INSTALLATION CHECKLIST 

BEFORE OPENING THE SHIPPING CARTON, Inspect ft for damage or water 

stains, If so, 

Write a brief description of the damage on the bill of 

lading, and 
Request that the carrier's agent be present when the carton 

is opened. 
Save the carton and packing materials to show the carrier in 

case the controller was damaged. The carrier is liable for 

shipping damage. 

Unpack the ME Controller module gently by removing the foam packing 

material. 



./82/TC0MME5/ 



3Co m Corpaatton 

computer communication compatibility 



Instal lation 
Crteck I i ST 



Verify that all components are present. (See Figure 5-1 below.) 
One PC Board 
One Cable 




FIGURE 5-1. ME CONTROLLER PARTS 



5/-fc/£2VTCOMME5/ 



3Com Caporatbn 

computer communication compatibility 



Instal I at Ion 
Checklist 



I 



Locate the byte ordering switch labeled TRB, see legend In Figure 
5-2 below. 

The byte ordering switch is configured at the factory to address 
high-order bytes first, like the Motorola 68000 microprocessor. If 
the ME Controller is going to be operated by a processor that 
addresses bytes in the reverse order (low-order first like the 
Intel 8086 microprocessor) turn the switch to the ON position. 

Locate l/0-Memory jumpers (labeled MRDC,MWTC, I0RC, I0WC). (See 
Legend In Figure 5-2)* To configure the ME Controller on the 
memory side, connect the memory jumpers labeled MRDC and MWTC. To 



3 Com_ © 
]wXLwjjj 



B 




TRB 

Interrupts 
ADR13/ 
10 Memory Jumpers 



A0R17/ 



FIGURE 5-2. ME CONTROLLER BOARD LEGEND 



5/18/82/TC0MMi5/ 



5-3 



3ComCorporafon lns + a iiat.on 

computer commun.cat.on compatibility Checklist 

configure the ME Controller on the I/O side, connect the I/O 
jumpers, I0RC and I0WC. 



Locate the address switches labeled ADR13/ and ADR17/. (See 

Figures 5-2, 5-3, 5-4). The switches labeled ADR13/ specify the 
most significant bit for 20-bit addressing. Switch ADR17/ 
specifies the most significant bit for 24-bit addressing. If the 
factory default settings (80000H) are satisfactory, go the next 
step, otherwise change the switch settings to meet your specific 
needs. 

Locate the interrupt jumpers labeled INTERRUPTS. (See Figures 5-2, 

5-3). Set the interrupt switches to the interrupt level desired: 
From O^hfghest, to 7= lowest. 

(Installation procedures continued after figures and tables on following 
pages.) 



5/18/82/TC0MME5/ 5-4 



3Co m Capaatbn 

cbmputer communication compatibility 



Installation 
Checklist 






3 e 



3 C 



3 L 



»QaE 



B > u»" i £ 



3D", 



CL 



^[h^ 



c^i 



Dc 



> ■■■« \ [ 

on 



rc 



I 3Com 



Q > uv> -f g 1 £ 



ECZ 



DC 



CE 



DC 



3 D D 

O c 



cCE 






EZ^I 



1 r > ■■■«"" 



dD=^U 



11 - -n - 

go==zzi > »"> > y> ~-> i r - ^ 



"iQ * -"■ ' [ b '"» ' 



-==—,£ 



]E 



] > *■» I E 



3 i i st: jy? ^" Lft ? *"* ly E7^ ly Lg I 5 




FIGURE 5-3. ADDRESS SWITCHES ADR13/ TO ADROD/ AND TRB SWITCH 

(Also see Figure 5-4.) 



5/18/82/TCCMME5/ 



3Corn Capaation 

5S^r coiwnuScaion compat.bil.ty 



Installation 
Checklist 









[DDDDDDD ^S^HHHWMfc. 




FIGURE 5-4. ADDRESS SWITCHES ADR17/ TO ADR14/ 

(Also see Figure 5-3*) 



5/18/fl7/TCOMMF«5/ 



■5-fi 



3ComCaporatbn 

^^^^^tion compatibility 



Instal latlon 
Checklist 



TABLE OF SWITCH AND JUMPER SETTINGS 



. . * j • 



De^ui iptfun, owiicnes 



rouiui y i/o i «w i • 



Cwl+rk Mama 



Buffer Memory Base Address 80000 H Memory ADR17/-ADR0D/ 

Byte ordering OFF TRB 

(Most significant byte at EVEN address) 

e.g. UNLIKE the 8086! 



Description, Jumpers 


Factory Default 


Jumper Name 


24-bit Addressing 


1 nserted 


JP1 


20-bit Addressing 


Inserted 


JP2 



Memory Configuration 





JP1 


JP2 


24-bit Addressing 


Inserted 


Inserted 


20-bit Addressing 


Out 


' Inserted 


16-bit Addressing 


Out 


Out 



5/18/82/TC0MME5/ 



5-7 



3Com Corporation , nsta , , a+ , on 

computer communication compatibility - Checklist 



Turn the DC power to the backplane OFF. 

Plug the serial cable supplied Into the 14-pfn connector on the 

back edge of the ME. The Notched Position of the Serial Cabie 
14-pin leader has "component-side" orientation. 

Plug the Multibus board into the Multibus backplane. 

Plug the Ethernet transceiver cable (not supplied) into the 

submj mature - end of the serial cable, 

Attach the lug at the end of the pigtail on the serial cable (near 

the board) to any convenient chas sis ground. PROPER GROUNDING IS 
CRITICAL TO THE PROPER OPERATION OF THE ETHERNET. 



5/18/82/TC0MME57 5-8 



3ComC0rp0[Btl0n Installation 

< ^ m ^ier communicabo compatibility . 



5.2 ETHERNET ADDRESS CONSIDERATIONS 

Each station on an Ethernet has a 48-bft Ethernet address associated 
with ft that Is unique across all Ethernets In the universe. The station 
address is assigned by the manufacturer of the station. For stations 
assembied from components from multiple manufacturers, the assignment of 
Ethernet addresses Is ambiguous. Th-is section describes the conventions 
to be followed to maintain unique Ethernet addresses under various 
configurations of components. 

Each ME Controller manufactured by 3Com Is shipped with a unique 
Ethernet address. The address is contained in a special address 
recognition PROM, and is also printed on the PC board in indelible ink. 
For stations that contain only a single ME Controller, the station 
address is the one supplied with the ME Controller. For stations that 
contain mu i i i p i e ME ^oniroi iers, such as gaieways, one Oi m8 cotiiroi isrs 
should be arbitrarily selected to contribute its Ethernet address as the 
station address. The hardware address recognition in the station must be 
programmed to respond to the chosen Ethernet address in all the ME 
Controllers attached. 

It may become necessary In order to analyze a hardware problem to 
swap boards between stations at a user site. In that case it is the 
user's option either to have the Ethernet address to follow the board, or 
to disassociate the board from the address In software. The advantage of 
the former is that the address recognized always matches the address 



5/18/82/TC0MME5/ 



3Com Capaation 

^^ii^'mmun.cat.on compatibility - HS 81 latfon 

^ Ethernet Address Considerations 

printed on at least one of the controllers in the station. The advantaae 
of the latter Is the ability to swap hardware around without changing any 
station name/station address directory entries for the network. 



If a board is sent back to the factory for repair, the board that 
comes back may not have the same Ethernet address printed on It. The 
customer has the option of using either the new Ethernet address or the 
old. Both addresses are allocated to the customer and are under the 
customers control. 

.. .s ,,,e customer's responsibility to manage the allocated Ethernet 
addresses. Addresses can be assigned in any manner as long as none are 
duplicated on more than one station. The recommended practice is to add 
each ME Controller Ethernet address to a site-wide pool of addresses 
maintained independently of the hardware. That way, ME hardware can be 
moved around among stations or sent back to 3Com for repair without 
affecting any software. 



5/ 1 8/82/TC0MME5/ 5-10 



7/21/82 



This is an addendum to the 

Model 3C400 

MULTIBUS Ethernet (ME) Controller 

Reference Manual 

of 

May 18, 1982 



CORRECTIONS: 

Page 4-6: The "address match" status bit is inverted. In other 
words, the bit is if the destination address of the received 
packet is equal to the station address, and 1 if it is not. 

Page 4-6: The "broadcast" status bit is also inverted. In other 
words, the bit is if the the destination address is the 
broadcast address (all ones), and 1 if it is not. 



Page 4-5: The JAM bit is cleared by setting it (writing a one 
into the JAM bit) . 

Page 4-5: The TBSW bit remains 1 during all JAM processing. It 
does not become again until the packet has been successfully 
transmitted. 

pang a_a* There is no status bit indicating a multicast racket 
which is not a broadcast packet. Such a packet is identified by 
a broadcast status bit equal to 1 (false) and the multicast bit 
in the destination address being 1 (true). Multicast packets 
will only appear in receive buffers if the receiver is enabled to 
accept them. 

Page 4-7: Broadcast is a special case of multicast. Enabling 
the receiver for multicast (modes 3,4,5) includes the .broadcast 
address. , 

f 
Page 4-7: The multicast bit of the destination address is the 
least significant (low order) bit of the first byte of the 
packet. In a receive buffer, this is the byte immediately 
following the buffer header word. 

Page 4-12: The number of retransmissions normally exceeds 15 
only when the Ethernet is broken. When this occurs the only way 
to get the ME to return the transmit buffer to the processor is 
to reset the controller by setting bit 8 of MECSR.