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The original Commodore Business Machines 


PLUS/4 docs 




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##### Original Files donated by Tibor Biczo 




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Offered on the web by Mi 


ke Dailly 




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##### ASCII Version by Oliver 


Heun aka 




###### 




###### The Paranoid / Paranoia 




######### 






######## Absolutely no warranties 


are taken by the 




###### author of this textfile 


for the accuracy 










and correctness of this 


document nor about 










its legal status. 












There are a lot of typos 


and misspellings 










in this text, but most are the original 










typos of the original Commodore docs which 










have not been corrected 


in this document. 










Spellchecked, slightly e 


dited and converted to PDF by 










Lidovski V., 2003 




I . 






Scope 


2 




II. 






Related Documents and Standards 
System Overview 


3 




2. 






System Architecture 


3 




3. 






System Specifications 


4 




3.1 






TED System Diagram 


5 




3.2 






Memory Map 


6 




3.3 






Power Consumption 


6 




3.4 






BUS Loading 


7 




3.5 






Configuration 






3.6 






Environmental Specification 






3.7 






Timing Chart 






3.8 






Timing Diagram 






4 






The 7360 Text Display Chip 


7 




4.1 






Overview 


7 




4.2 






Features 


7 




4.3 






Chip Characteristics 


8 




4.3 


1 




Pinout 


8 




4.3 


2 




Signal Description 


9 




4.4 






Electrical Specifications 


10 




4.4 


1 




Absolute Maximum Rating 


10 




4.4 


2 




Video Voltage Specifications 


11 




4.4 


3 




Luminance Levels 


11 




4.4 


4 




Color Phase Angles 


11 




4.5 






General Timing 


11 




4.5 


1 




BUS Timing 


11 




4.5 


2 




DMA Timing 


12 




4.5 


2 


1 


TED DMA Timing 


12 




4.5 


2 


2 


TED DMA Timing Diagram 


12 




4.5 


3 




Video Timing 






4.5 


3 


1 


Horz Timing 






4.5 


3 


2 


Vert Timing 






4.5 


3 


3 


Video Timing Diagram 






5. 






The 7501 Microprocessor 


14 




5.1 






Description 


14 




5.2 






Pinout 


14 





1/40 



5.3 


Electrical Specifications 




14 


5.3.1 


Maximum Ratings 




15 


5.3.2 


Electrical Characteristics 




15 


5.4 


Signal Description 




15 


5.5 


Processor Timing 




16 


5.5.1 


Timing Chart 




16 


5.5.2 


Timing Diagram 




17 


6. 


Dynamic RAMs 




18 


6.1 


Electrical Specifications 




18 


6.2 


Characteristics 




18 


6.2.1 


Package Pinout 




18 


6.2.2 


Selection Criteria 




18 


6.3 


Timing 




18 


6.3.1 


Timing Chart 






6.3.2 


Timing Diagram 






7. 


The User Port 




19 


7.1 


Description 




19 


7.2 


Physical Pinout 




19 


7.3 


Electrical Specifications 




19 


7.4 


Timing 




20 


7.5 


6551, 6529 Timing 




21 


7.6 


PLA Program Chart 




21 


7.7 


PHI 2, CS Clocks 




22 


8. 


The Video Section 






8.1 


Video Interface 






8.2 


Modulator Specifications 






8.3 


Monitor Output 






8.4 


Video Connector Pinout 






9. 


The Serial Bus 




22 


9.1 


Serial Bus Specifications 




22 


9.2 


Serial Bus Connector Pinout 




22 


10 


The Expansion Bus 




23 


10.1 


Expansion Bus Pinout 




23 


10.2 


Expansion Bus Signal Description 


23 


11. 


Read Only Memory 




24 


11.1 


System ROM Description 




24 


11.2 


Banking Operation 




24 


11.3 


ROM Electrical Specification 




24 


11.4 


ROM Pinout 




25 


11.5 


ROM Timing 




25 


12 


The Keyboard 




26 


12.1 


Keyboard Connector Pinout 




26 


12.2 


Keyboard Matrix 




26 


12.3 


Keyboard Electrical Specification 


27 


13 


The Circuit Board 






13.1 


Physical Dimensions 






13.2 


Parts Placement 






I. 


Scope 






This do 


cument contains information concerning the architecture. 


hardware description, timing analysis, 


peri 


pheral specification and 


driving 


software description for the Commodore system based on the 7360 


I.e. (h 


ereafter referred to as the TED 


I.e. 


) and the TED system. This 


documen 


t does not attempt to fully describe 


software aspects of the TED 


system 


and information concerning this 


sub j 


ect can be found 


in the 


appropriate documents listed in 


sect 


ion II. 



2/40 



1 . System Overview 

The TED system is based on the 7501 microprocessor, which is 
an HMOS version of the 6510, working in conjunction with the 7360 TED 
video processor. System RAM consists of 64K bytes of dynamic RAM 
composed of eight 648 X 1 devices. A system program is contained in two 
16K X 8 ROMs, and in it's standard configuration, consists of 
Kernal and Basic version 3.5. The current implementation of the 
architecture for the Ted system supports up to 128K x 8 of ROM banked 
in 16K sections. ROM can be completely banked out and RAM banked 
in for a true 64K of RAM (minus two 256 byte pages) . This allows 60,671 
bytes available for Basic. The ROM/RAM banking is controlled by the 
7360 under software control. 

Keyboard scanning is done by outputting the row data on the 
Data bus while addressing a particular register in Ted, which will in 
turn cause Ted to latch the column information. Joystick scanning is 
done in the same manner. 

Peripherals consist of standard serial bus products, (1541 
disk drive, serial printer, etc.) cassette, TTL Serial ASCII which is 
intended to drive an RS-232 adapter. The expansion port supports ROM 
cartridges and a parallel disk drive interface. 

SUMMARY OF TED SYSTEM FEATURES 

- 7501 ( 6502 compatible ) 8 bit CPU 

- 7360 VLSI video, voice, DRAM controller 

- 6 4KByte RAM 

- 32KByte ROM for use in Kernal and Basic 

- 32KByte ROM for Function Key software 

- 32KByte ROM for Cartridge software 

- Version 3.5 Basic with advanced graphics and DOS ( compatible with C64 ) 
-40 X 25 display with 128 colors 

- 320 X 200 graphics resolution 

- 2 Voices and white noise 

- 64 Keys including function keys 

- Screen Editor with virtual Windows 

- Dual speed system clock for increased processing throughput 

- External power supply (same as c64) 

- Low chip count, high system integration 

2. SYSTEM ARCHITECTURE 



The Ted system employs a shared bus concept which 
allows the video processor and the microprocessor to access the 
same memory and I/O devices on alternate halves of the system clock. 

Bus access control is generated by the 7360. To increase 
microprocessor throughput, when this interleaving is not needed, the 
system clock doubles in frequency and the microprocessor is allowed full 
time on the bus. This occurs when no video information is being fetched 
by the 7360 (horizontal or vertical retrace, blank screen) . There is an 
exception to this, and that is when the 7360 DMA' s the 7501 micro to 
accomplish attribute fetch and character pointer information. 

Dynamic RAM control signals are generated by the 7360. /RAS 
is generated once each memory cycle, while /CAS is generated depending 
on whether the memory cycle is a DRAM memory cycle or not. MUX is 
generated to control the multiplex of Row and Column addresses going to 
the DRAMs . MUX also controls the holdoff of the R/W line as generated 
by the 7501. The R/W line is latched by the 7501 until the MUX line 
goes high signifying the end of the memory cycle. Refresh is provided by 
the 7360, refreshing 5 row locations (RAS only refresh) every raster line, 

Selection of either ROM or RAM is accomplished by writing a bit 
in a TED register. When RAM is selected, the whole 64K memory map 
is comprised of RAM with the exception of 2 registers for the 

3/40 



7501 port, 1 page for TED control registers, and 1 page for I/O. This 
method yields 60.671 pages of RAM available for Basic program 
storage. When ROM is selected, the program residing in ROM appears in 
place of RAM. The exception to this is a write operation to ROM 
will always 'bleed through' to underlying RAM. 

Kernal and Basic can also be selectively swapped out and 
replaced with other 16 K sections of ROM. 2 sockets are 
provided internally for application programs (referred to as 
function key software) and address space is allocated for 2 ROMs 
external to the system (cartridge use, etc.) . Swapping is taken care 
of by a Kernal routine that does not swap out, (located at $FCOO) . 

The cassette port and the Commodore serial bus port are 
implemented using the zero page ports available on the 7501 and using 
software control of hardware handshake. 

The serial bus works with Commodore serial components, 
except for older peripherals that have a handshake timing problem. 

The User Port is intended for external RS-232 adapters, and modem 
adapters. Transmission and reception is accomplished using a 6551 ACTA 
with handshaking assistance from a 6529 single port I.C. 

The Joystick ports are functionally compatible with the 
standard Commodore 5 switch type joystick. They are not compatible with 
analog type peripherals such as paddles, tablets, etc., as well 
as not being pin compatible. 

The video connector has composite video as well as separate 
chrome and luminance outputs for use with monitors. The 1701, 1702 
type Commodore monitors interface directly to this connector. 

The RF output Jack supplies an RF signal compatible 
with the resolutions pertaining to TV interface devices, and is 
switch selectable between channels 3 and 4. Both NTSC and PAL 
television standards are supported. 



3. SYSTEM SPECIFICATIONS 

This section covers the range of system operation by discussing 
various constraints and features of the TED system as a whole. Included 
are descriptions of the system as configured and limiting factors of power, 
loading, and environment. 



4/40 



3.1 



TED 64 SYSTEM DIAGRAM 



Expansion 

Connector 

/\ 



/ 



/\ 
/ \ 
I I 



16K X 8 

Function 
"Hi" 

l_l 



16K X 8 

ROM 
Function 

"Low" 

I I 



16K X 8 

ROM 

"Kernal" 
l_l 



16K X 8 

ROM 

"Basic" 



I I 

I I 

I I. 
I 



I. 



/\ 
/ /\ 
1/ I. 



User 
Port 



/\ 
/ \ 



RF/TV Out 
Video /Monitor 
Output 



/ \ 



I /._/_/./! 



1/ 
l_l / 
/ / 
_. / 
1/ 
I / 
1/ 
I / 
l_l/ 
/ / / 
_./ 
I / 
1/ 
I / 
1/ 
_l / 

/ / 
_. / 
1/ 
I / 
1/ 
I / 
l_l/ 
/ / / 
_./ 
I / 
1/ 
I / 
1/ 



.l_l. 



6 
4 
K 

D 

Y 

N| 

A| 

Ml 

I 

C 

R| 
A| 
Ml 



(8) I I 

I I 

i~ T ~i 

I Mux I Mux I 
I I I 



1/ 



I ._ 

I 

ID 

|A 

IT 

|A 



A 
D 
D 
R 
E 
S 
S 



6529 
Port 



l_l_l_l 

6551A 
UART 



6529 
PORT 



Key- 
board 

Matrix 



/ 
../ 
/ 
/ 
/ 



K 
E 
Y 



D 
A 
T 
A 



L I Modulator I 

A I I 

T INTSC/PAL I 

C I I 

H 



C 

H L S 
R U 
M U 
MAN 
A D 



7501 



7360 



CPU 



"T E D" 



I I 

I I 

I I 

\ / 

\/ 

Cassette 

Port 



I I 

I I 

I I 

\ / 

\/ 

Serial 

Port 



1 1 




1 14. 
|MH2 


3182 1 
. Osc 1 



5/40 



3.2 



TED MEMORY MAP 6 4K 



$FF40 
$FFOO 
$FEOO 
$FDOO 
$FCOO 



$A000 



$8000 



$1000 

$C00 

$800 

$500 

$200 

$100 

$02 

$00 

3.3 



RAM 

TED Registers 



I/O (Disk) 
I/O 



RAM 



Text 


Screen 


Color 


+Attribute 


Kerna 


1 Variabl. 


Basic 


Variables 


N Proc Stack 


Zero 


Page 


7501 


Port 



$D800 
$D000 



Kernal 


TED 


Registers 


I/O 


(Disk) 




I/O 


Non-Banking 


Ker 



/ External ROM / 
./ / 



nal 



Kernal 
Character ROM 



KERNAL 



BASIC 



POWER CONSUMPTION 



Part 



I total 
(typ) 



7501 

7360 

23128 

74LS257 

modulator 

555 

7406 

74LS08 

74LS04 

7700-xx 

4164-2 

6551A 



80 

200 

155 

24 

80 

10 

32 

4 

4 

85 

336 

34 



I total 




(max) 




125 


ma 


250 


ma 


220 


ma 


38 


ma 


150 


ma 


15 


ma 


51 


ma 


9 


ma 


7 


ma 


120 


ma 


480 


ma 


60 


ma 



Func 


tion Hi 


TED 


Registers 


I/O 


(Disk) 


I/O 


Non-E 


ianking Krn 



FUNCTION 
HI 



FUNCTION 
LOW 



Kernal, Basic 



6/40 



6529B 


56 80 




ma 




6529B 


56 80 




ma 


W/0 Function Key Soft 




1156 1685 




ma 


23128 


155 220 




ma 


Function Key ROM 
TED W/Function Soft 




1311 1905 




ma 


23128 


155 220 




ma 


Cartridge ROM 

TED64 Function and Cart 




1466 2125 




ma 


RS-232 


1536 2225 




ma 


TED64 Func. w/Cart 
& RS-232 


* * 


1.53 A Typ. 2.2 A Max. 








3.4 


BUS LOADING 






Ras 


Device 


Address Data 




R/W 


Cas 


7501 


12 15 




12 


pf 


7360 


10 10 




10 


10 pf 


4164 


20 




80 


80 pf 


7700 


8 




- 


8 pf 


6551 


10 10 




10 


pf 


(2) 6529 


20 




20 


pf 


74LS257 


5 




- 


pf 


(2)23128 16 16 




- 


pf 




61 91 




132 


98 pf * 




77 107 




132 


98 pf ** 




93 123 




132 


98 pf *** 


* 


TED64 








* * 


TED64 W/Function ROMs 








* * * 


TED64 W/Function & Cart 








4 


THE 7360 TEXT DISPLAY CHIP 










This chapter will discuss the 


various 


aspects of the 7360 


Text Display Chip. 








4.1 


OVERVIEW 








The 7360 (or TED) is intended for low end 


6502 


family based personal 


home computers systems . s The 7360 is a 


48 


pin 


device which controls video 


output, 


(all signals are necessary to ere 


ate c 


omposite video) , system 


timing, 


dynamic RAM control, ROM contro 


1, 


and 


keyboard scanning. The 


7360 contains 34 control registers whic 


h 


are accessed through the 


standar 


d 6502 microprocessor data bus. 


Th 


3 7360 uses the MOS technology 


HMOS process, and is upgradable to HMOS 


2 


• 




4.2 


FEATURES 








Hardware features: 










Dynamic RAM refresh 










Sound generation 










Programmable video time standar 


ds 








(compatible with either NTSC or 


PAL St 


andards) 



7/40 



40 


CO 


lumn X 25 row 


character display 


8 X 


8 


ch 


aracter dot 


mat 


rix 


320 


X 


200 pixel resolut 


ion 


16 


uniqu 


B colors, 8 


luminance levels 


har 


dw 


are 


flash 






har 


dw 


are 


cursor 






har 


dware 


reverse vi 


deo 




pro 


gr 


ammable charac 


ter 


information source (ROM or RAM) 


dua 


1 


speed clock 






screen blanking for 


DMA 


sensitive environments 


4.3 CHIP 


CHARACTERISTICS 




Th 


is 


section discusses 


some of the physical characteristics 


of the TED 


ch 


ip. 








4.3.1 PINOUT 








Pin 




Designation 


D 


escription 


1 






A2 




Address Bit 2 


2 






Al 




Address Bit 1 


3 






AO 




Address Bit 


4 






VCC 




Power Supply +5 


5 






CSO 




Low ROM Chip Select 


6 






CSl 




Hi ROM Chip Select 


7 






R/W 




Read/Write Line 


8 






/IRQ 




Interrupt Request 


9 






MUX 




Address Multiplex Control 


10 






/RAS 




Dynamic RAM Row Address Strobe 


11 






/CAS 




Dynamic RAM Column Address Strobe 


12 






OOUT 




System Clock 


13 






COLOR 




Chroma Output 


14 






OIN 




Master Clock 


15 






KO 




Keyboard Latch 


16 






Kl 




Keyboard Latch 1 


17 






K2 




Keyboard Latch 2 


18 






K3 




Keyboard Latch 3 


19 






K4 




Keyboard Latch 4 


20 






K5 




Keyboard Latch 5 


21 






K6 




Keyboard Latch 6 


22 






K7 




Keyboard Latch 7 


23 






LUM 




Composite Sync and Luminance 


24 






VSS 




Power Supply Ground 


25 






DBO 




Data Bit 


26 






DBl 




Data Bit 1 


27 






DB2 




Data Bit 2 


28 






DB3 




Data Bit 3 


29 






DB4 




Data Bit 4 


30 






DB5 




Data Bit 5 


31 






DB6 




Data Bit 6 


32 






DB7 




Data Bit 7 


33 






SND 




Sound Output 


34 






BA 




Bus Available 


35 






AEC 




Address Enable Control 


36 






A15 




Address Bit 15 


37 






A14 




Address Bit 14 



8/40 



38 


A13 


39 


A12 


40 


All 


41 


AlO 


42 


A9 


43 


A8 


44 


A7 


45 


A6 


46 


A5 


47 


A4 


48 


A3 



Address Bit 13 

Address Bit 12 

Address Bit 11 

Address Bit 10 

Address Bit 9 

Address Bit 8 

Address Bit 7 

Address Bit 6 

Address Bit 5 

Address Bit 4 

Address Bit 3 

4.3.2 SIGNAL DESCRIPTION 

Address Bus Pins 1 thru 3 and 36 thru 48 

The 16 bit address bus is bidirectional. As an input, the microprocessor 
can access any of the 34 TED control registers. In the output mode TED 
uses the addresses to fetch Video Matrix Pointers, Attribute Pointers or 
character cell information. For microprocessor interface TED resides in 
locations FF00-FF3F in memory. 

Data Bus Pins 25 thru 36 

The 8 bit data bus is also bidirectional. The data bus activity can 

be separated into 2 categories: microprocessor interface and video data 

interface during the above mentioned fetches. 

Keyboard latch Pins 15 thru 22 

The 8 bit keyboard latch is used as the keyboard interface. Upon 
instruction by the microprocessor to write to the keyboard latch, the 
information on the keyboard pins is latched by the TED and stored until 
it is retrieved by the microprocessor on a read keyboard instruction. 
The 7360 also provides active pull ups on the keyboard matrix lines. 

KO and Kl (2 of the keyboard lines) also provide testing functions. When 
these pins are externally driven to 10 volts, they provide specific testing 
features. It should be noted however, that these pins are high impedance 
and if subjected to high energy electromotive fields, could cause false 
generation of testing functions. This can protected against through use of 
diodes to insure the potential KO and Kl never exceeds VCC. KO generates a 
system freeze function, and sets all horizontal flop-flops to force TED 
into dynamic RAM refresh period and single clock. All flip-flops are then 
released to allow their manipulation by the horizontal resistor. Kl forces 
the internal clock division into the NTSC mode. 

Chip Selects Pins 5 and 6 

TED generates ROM chip selects based on address decoding. CSO is 
active during the memory block of 8000-BFFF (HEX) . CSl corresponds 
to COOO-FFFF (HEX) in memory. The ROM area of memory can be banked out 
to overlay RAM, see the description of Registers 3E and 3F (HEX) . 

Dynamic RAM Control Pins 9 thru 11 

TED generates /RAS and /CAS for dynamic RAM access. The signal MUX is 
also generated to externally multiplex the RAM row and column addresses. 

Read/Write Pin 7 

R/W is an input to TED to distinguish the type of operation to be performed. 
TED will actively pull up the system read line during all TED fetches. The 
read signal is qualified with MUX. The pin is an open source output. 

Interrupt Pin 8 

The interrupt pin is an open drain output. TED contains 

four interrupt sources: 3 internal timers and the raster comparator. 

9/40 



PHI Out Pin 12 

For increased processor throughput, TED doubles the frequency 

of the system clock during horizontal and vertical blanking. The 

actual single clock boundaries are: 

1) Raster lines 0-204 and horizontal positions 400-344 

2) Horizontal positions 304-344 

PHI In Pin 14 

For use in NTSC television systems, TED requires a 14.31818 MHz +/- 
70 ppm single phase clock input. For PAL systems, the input clock must 
be 17.734475 MHz +/- 70 ppm single phase. 

Composite Color Pin 13 

The color output contains all chrominance information, including the color 
reference burst signal and the color of all display data. The color output 
is open source and should be terminated with IK ohms to ground. 

Composite Sync and Luminance Pin 23 

The luminance output contains all video synchronization as well 

as luminance information for the video display. The pin is open drain, 

required an external pullup of IK Ohm. 

Sound Pin 33 

This pin provides the output of the 2 tone generators. The output must 
be integrated through an RC network and then buffered to drive an 
external speaker. 

Bus Available Pin 34 

Bus Available indicates the state of TED with respect to video memory 
fetches. BA will go low during phase 1, 3 single clock cycles before TED 
performs any memory access and will remain low for the entire fetch. 

Address Enable Control Pin 35 

During Double Clock mode, AEC is always high allowing the 7501 complete 
control of the system buses. For single clock time periods, when BA has 
not gone low, AEC will toggle with PHI2 out. This allows TED PHIl, time 
to complete its memory accesses of video dot information while the 7501 
performs during PHI2. When TED needs both halves of the cycle to perform 
its customary PHIl dot fetches and PHI2 attribute and pointer fetches, BA 
will go low. On the fourth PHIl out, AEC will remain low until the end of 
the PHI2 video fetch. 

4.4 ELECTRICAL SPECIFICATIONS 

This section discusses some of the electrical properties 
and considerations of the 7360 TED chip. 

4.4.1 ABSOLUTE MAXIMUM RATINGS 

Input Voltage (Vin) -2V to +7.0 VDC 

Supply Voltage (Vcc) -2V to +7.0 VDC 

Operating Temp (Ta) to 70 'C 

Storage Temp -55 to 150 'C 

Input Leakage Current -1 . uA 

Dynamic Characteristics Vcc = 5.0V +/-5% 

Input High Voltage (VIH) Vss+2.4V to Vcc+lV 

Input Low Voltage (VIL) VSS-2V to VSS+.8V 

Output High Voltage (VOL) VSS+2 . 4V 
(IOH=-200uA VCC=4.75VDC) 

10/40 





Output Low 


Voltage (VOL) VSS+.4V 




(IOL=-3.2ma 


VCC=5.25V) 






Max Power S 


upply Current 250ma 


4.4.2 


VIDEO VOLTAGE SPECIFICATIONS 




Chroma Out 




IVp-p min. w/2Volt Offset Open Source 




Lum Out 




0-5V (blanking = . 5V) Open Drain 


4.4.3 


Luminance L 


evels (R7) 






Level 


Voltac 


[e 




00 


2.00 


V 




01 


2.4 


V 




02 


2.55 


V 




03 


2.7 


V 




04 


2.9 


V 




05 


3.3 


V 




06 


3.6 


V 




07 


4.1 


V 




08 


4.8 


V 


4.4.4 


COLOR PHASE 


ANGLES 






Color 


HUE Phase (relative to SIN, in degrees) 






NTSC 


PAL 




Black 


— 


— 




White 


-- 


— 




Red 


70 


103 




Cyan 


250 


283 




Magenta 


20 


53 




Green 


208 


241 




Blue 


314 


347 




Yellow 


134 


167 




Orange 


90 


129 




Brown 


115 


148 




Yllw-Grn 


162 


195 




Pink 


50 


83 




Blu-Grn 


232 


265 




Lt-Blu 


290 


323 




Dk-Blu 


350 


23 




Lt-Grn 


180 


213 


4.5 


GENERAL TIMING 






This section explores 


the various timing considerations 


and constraints related to the 


TED chip. 


4.5.1 


BUS TIMING 






Parame 


ter 


Symbol 


Min Max Unit 


TED Addr Setup 


TADS 


150 ns 


Input 


Data Setup 


TDSU 


50 - ns 


Input 


Data Hold 


TDH 


10 - ns 


Output 


Data Stable 


TDSO 


160 - ns 


Output 


Data Hold 


TDHO 


80 120 ns 


R/W Stable Period 


TRWS 


178 ns 


MUX to 


R/W Setup 


TMRWS 


70 ns 


MUX to 


R/W Hold 


TMRWH 


30 - ns 


Chip S 


elect Setup 


TCSS 


320 ns 


Chip S 


elect Hold 


TCSH 


70 - ns 


Address Hold 


TAH 


60 - ns 



11/40 



Address in Tristate 



TADTH 



135 



ns 



4.5.2 



DMA TIMING 



The 7360 perf 
video display 
as a cell 8 X 
obtain the ch 
can be found 
is interprete 
1 ) The system 
AEC starts to 
line goes low 
before DMA be 
fetches per c 
back on the b 
engaged in re 
(equiv. to 8 
DMA for row 1 
cycles of sin 



orms DMA' s 
Twice per 
bits) to 
aracter poi 

In bit map 
d different 
clock comes 

toggle, al 
. 3) Three c 
gins. 4)40 
ycle. 5)BA 
us . 6) 5 cy 
freshing th 
cycles of s 

of next ch 
gle speed a 



to fetch additional information to mai 
each row of characters, (a character 
obtain the attributes for each charac 
nter which points to where the charact 
mode, these DMA' s still occur, but th 
ly. The sequence of events in a DMA cy 
out of double speed for 1 cycle. At t 
lowing the 7360 on the bus. 2 ) The Bus 
ycles are given to the 7501 to complet 
cycles of single clock where the 7360 
goes high at the same time as AEC alio 
cles follow of single speed where the 
e dynamic RAM. 7)16 cycles of double s 
ingle) 8) If last DMA was row 8 of cha 
aracter is initiated. If screen is bl 
re still present for dynamic RAM refre 



ntain a 
being defined 
ter and to 
er pattern 
e information 
cle are: 
he same time 
Available 
e operation 
is doing 2 
wing the 7501 
7360 is 
peed - 

racter, then 
anked, the 5 
sh. 



4.5.2.1 TED DMA TIMING (REFER TO 4.5.2.2 TED DMA TIMING DIAGRAM) 





cycles 


THALT 


3 


TDMA 


40 


TRFSH 


5 


IDS 


16 


TS 


1 



time 






3us 


Time, 


Halt 


46us 


Time, 


DMA 


5us 


Time, 


Refresh 


9us 


Time, 


Double Speed 


lus 


Time, 


Synchronize 



65 



64us 



Diagram 4.5.2.2 represents the occurrence of when two DMAs are 'back to 
back' . I.E. character row 8 DMA' s, then character row 1 of the next 
character DMAs, separated only be one horizontal retrace. 



4.5.2.2 TED DMA TIMING DIAGRAM 
BA AEC 



Sgn . 



36us 
3c. 



T 
H 
A 
L 
T 



0. 













































12/40 



46us 
40c. 



_V_ 
T 

I 
I 
I 
I 
I 



1 




./' 


1 
1 




1 


1 

V 




1 


T 






5us 1 


T 




5c. 1 


R 
F 
S 





/' 
/' 



/' 
/' 



I H 



9us 
16c, 



I 

_V 

T 

I 

I T 
I D 
I S 



Ic. 
lus 



_V 

T 

I T 
I s 
V 






13/40 



5 THE 7501 MICROPROCESSOR 

This section describes some of the properties and 
functions of the type 7501 microprocessor. 

5.1 7501 DESCRIPTION 

The 7501 is an HMOS version of the 6502 family or more specifically, the 
6510CBM. The 7501 is software compatible with existing 6502, 6510 code. The 
7501 contains a 7 bit bi-directional port used to directly drive the serial 
bus and cassette. The port is at location $0000 while the data direction 
register is at $0001. The 7501 is Tri-statable and through use of the AEC 
(address enable control) line and is used extensively in the TED shared bus 
concept. DMA is accomplished using the AEC line and the RDY line (called BA 
on TED) . A control line is provided (GATE IN) to hold off the R/W line 
until /RAS makes the transition from low to hi. This prevents the Real line 
from making an early transition to the write state which would cause an 
improper Early Write Cycle to occur. 

5.2 7501 PINOUT 

Pin Name Description 



1 


PHI In 


System Clock Input 


2 


RDY 


DMA Rqst 






3 


/IRQ 


Interrupt Rqst 


4 


AEC 


Address 


Enable Control 


5 


VCC 


Power Su 


pply +5V. 


6 


AO 


Address 


Bit 





7 


Al 


Address 


Bit 


1 


8 


A2 


Address 


Bit 


2 


9 


A3 


Address 


Bit 


3 


10 


A4 


Address 


Bit 


4 


11 


A5 


Address 


Bit 


5 


12 


A6 


Address 


Bit 


6 


13 


A7 


Address 


Bit 


7 


14 


A8 


Address 


Bit 


8 


15 


A9 


Address 


Bit 


9 


16 


AlO 


Address 


Bit 


10 


17 


All 


Address 


Bit 


11 


18 


A12 


Address 


Bit 


12 


19 


A13 


Address 


Bit 


13 


20 


GND 


Power Su 


pply Ground 


21 


A14 


Address 


Bit 


14 


22 


A15 


Address 


Bit 


15 


23 


GATE In 


R/W Gate 






24 


P7 


Port Bit 


7 




25 


P6 


Port Bit 


6 




26 


P4 


Port Bit 


4 




27 


P3 


Port Bit 


3 




28 


P2 


Port Bit 


2 




29 


PI 


Port Bit 


1 




30 


PO 


Port Bit 







31 


DB7 


Data Bit 


7 




32 


DB6 


Data Bit 


6 




33 


DB5 


Data Bit 


5 




34 


DB4 


Data Bit 


4 




35 


DB3 


Data Bit 


3 




36 


DB2 


Data Bit 


2 




37 


DBl 


Data Bit 


1 




38 


DBO 


Data Bit 







39 


R/W 


Read/Wri 


te 




40 


RES 


Reset 







5.3 7501 ELECTRICAL SPECIFICATIONS 

This section describes some of the electrical 

14/40 



constraints and specifications of the system. 

5.3.1 MAXIMUM RATINGS 

Rating Symbol Value Unit 

Supply Voltage Vcc -0.3 to +7.0 Vdc 

Input Voltage Vin -0.3 to +7.0 Vdc 

Operating Temperature Ta to +70 C 

Storage Temperature Tstg -55 to +150 C 

5.3.2 ELECTRICAL CHARACTERISTICS 

Characteristic Symbol Min Typ Max Unit 

Input High Voltage 

PhiO (in) Vss + 2.4 Vcc Vdc 



Symbol 


Min 




VIH 








Vss + 2 


4 




Vss + 2 


2 


VIL 








Vss-0 


3 



/RES, P0-P7, /IRQ, Data Vss+2. 2 Vdc 

Input Low Voltage 

PhiO (in) Vss-0. 3 Vss + 0.5 Vdc 

/RES, P0-P7, /IRQ, Data Vss+0.8 Vdc 

Input Leakage Current Tin 
(Vin=0 to 5.25V, Vcc=5.25V) 

Logic 2 . 5 uA 

PhiO(in) 10.0 uA 

3-State(0ff) Inp.Cur. ITSI 
(Vin=0.4 to 2.4V, Vcc=5.25V) 
Data Lines 10.0 uA 

Output High Voltage VOH 
(IOH=-100uAdc, Vcc=4.75V) 
Data, A0-A15,R/W,P0-P7 Vss+2.4 Vdc 

Output Low Voltage, VOL 
(I0L=1 . 6mADC, Vcc=4.75V) 
Data, A0-A15,R/W,P0-P7 Vss+0.4 Vdc 

125 mA 



Power Supply Current 


ICC 


Capacitance 


C 


(Vin=0,Ta=25 C, _ f=lMHz) 




Logic, P0-P7 


Cin 


Data 


Cout 


A0-A7 


Cout 


Phil 


CPHil 


Phi2 


CPHi2 






10 


pF 





15 


pF 





12 


pF 


30 


50 


pF 


50 


80 


pF 



5.4 SIGNAL DESCRIPTION 

CLOCK ( PHI ) - This is the dual speed system clock and 
is a standard TTL level input. 

ADDDRESS BUS ( AO - A15) - TTL output. Capable of driving 2 TTL loads 
at 130 pf. 

DATA BUS ( DO - D7) - Bi-directional bus for transferring data to and from 
the device and the peripherals. The outputs are tri-state buffers 
capable of driving 2 standard TTL loads and 130pf. 

RESET - This input is used to reset or start the processor from a power 
down condition. During the time that this line is held low, 
writing to or from the processor is inhibited. When a positive 
edge is detected on the input, the processor will immediately 
begin the reset sequence. After a system initialization time 
of 6 cycles, the mask interrupt flag will be set and the 
processor will load the program counter from the contents of 
memory locations $FFFC and $FFFD. This is the start location for 

15/40 



program control. After VCC reaches 4.75 Volts in a power up routine, 
reset must be held low for at least 2 cycles. At this time the R/W 
line will become valid. 
INTERRUPT REQUEST (IRQ) - TTL input, request that the processor 

initiate an interrupt sequence. The processor will complete 
execution of the current instruction before recognizing the 
request. At that time, the interrupt mask in the Status 
Code Register will be examined. If the interrupt mask is not 
set, the processor will begin an interrupt sequence. The Program 
Counter and the Processor status register will be stored 
on stack and the interrupt disable flag is set so that no other 
interrupts can occur. The processor will then load the program 
counter from the memory locations $FFFE and $FFFF. 
ADDRESS ENABLE CONTROL (AEC) - The Address Bus is only valid when 

the AEC line is high. When low, the address bus is in a high 
impedance state. This allows easy DMA' s for shared bus systems. 
I/O PORT (P0-P4, P6, P7 ) - Bidirectional port used for transferring 
data to and from the processor directly. The Data Output 
Register is located at location $0001 and the Data Direction 
Register is located at location $0000. 
R/W - TTL level output from processor to control the direction 

of data transfer between the processor and memory, peripherals, etc. 
This line is high for reading memory and low for writing. This line 
is latched by the Gate In line to synchronize between a DRAM memory 
cycle and the processor clock cycle. If AEC is low when Gate In 
makes a low to high transition, the R/W line will go to a high 
impedance until the next transition of the Gate In line and AEC is 
high prior to the transition. 
GATE IN - TTL level input, used to gate the R/W line to prevent 
the R/W line from going low during a read cycle, before 
RAS and CAS so high (resulting in a Read/Write cycle) . Normally 
connected to the MUX line in a system configuration to synchronize 
the DRAM memory cycle to the processor clock cycle. 
RDY - Ready. TTL level input, used to DMA the 7501. The processor 

operates normally while RDY is high. When RDY makes a transition to 
the low state, the processor will finish the operation it is on, and 
any subsequent operation if it is a write cycle. On the next 
occurrence of read cycle the processor will halt, making it possible 
to tri-state the processor to gain complete access to the system bus. 



5.5 PROCESSOR TIMING 

This section explores the timing considerations of the 7501 processor unit 

5.5.1 TIMING CHART 

o o 
Electrical Characteristics Vcc = 5v + 5%, Vss = Ov, TA = C to 70 

Characteristic Symbol Min Max Units 

MUX input high 

AEC setup time 

MUX to RW setup or tri-state 

MUX to RW hold 

Up data setup from PHO 

Up write data hold 

Up data setup from Mux 

Data bus to tri-state from MUX 

Data bus to tri-state from AEC 

Read data stable 

Read data hold 

Address setup from PHO 

Address hold 

Address setup from AEC 

Address tri-state from AEC 

Port input setup 

16/40 



TMH 


60 


110 


ns 


TAEC 


25 


60 


ns 


TMRWS 




70 


ns 


TMRWH 


30 




ns 


TMDS 




130 


ns 


THW 


60 




ns 


TMXDS 




120 


ns 


TMXDT 


30 




ns 


TAEDT 




120 


ns 


TDSU 


40 




ns 


THR 


40 




ns 


TADS 


40 


150 


ns 


THA 


40 




ns 


TAADS 




75 


ns 


TAEAT 




120 


ns 


TPDSU 


105 




ns 



Port input half 

Port output data valid 

Cycle time 

PHO (in) pulse width @1.5v 

PHO (in) rise time 

PHO (in) fall time 

RDY setup time 



TPDH 


65 




ns 


TPDW 




195 


ns 


TCYC 


500 




ns 


PWHPHO 


250 


275 


ns 


TRPHO 




10 


ns 


TFPHO 




10 


ns 


TRDY 


80 




ns 



5.5.2 



TIMING DIAGRAM 



TFOO 



\ 
(1)0 \ 



MUX 



AEC 



R/W 



DATA 



MPU 



DATA 



MEMORY 



ADR 



READY 



PORT 



TCYC 

I I 
-> I I <-TR0O 

I I I 



<- PWOOL -> 



/ 



_/ 
TMH 



TMRWH 

l<- 

I 

I 
_l 

\/\/ 

_/\/\ 
< > 

TMRWS-> 



TADS 
l<- 
I 



\/l 
./\l. 



> I TPDSC 



\/ 



/ 



<-PW0OH-> 



TMDS I < 



I. 



_/l 
\l. 
->l 



TDSU-> 



TAEAT-> 
TRDY 

l< — 

_ I 

\/l 
_/\l 



TPDH 



\/ 
/V 



1/ 
./ 

I 
I 



/ 

/I 

TAEC I 
|<- + - 

_ I I 
\l I 

\_l 

I I TMRWS 

— + ->| 

I I 
->l 



I 



I _ 
1/ 

/ 

I 
TAEC 
_l_ 
/ I 



.1/1 I 



->l 



I 



\/ 
/V 



l< + - 

I I I TMRWH 

+>!<+ I 
I I I _ l_ 
.l_l_l/ \/ 
I I l\_/\_ 

I l< >l 

I I TMRWS I 



TAEDT 



l\ 
_l/ 
l<- 
I THW 

_ I 

\l 

_/l 
<- + - 

I <-THR 
_l I 

\l 

_/l 

l<- 
■>l l< — 
I THA 



I I 

I I 

.l_l. 



I 
I I. 
.1/1 



I l< — >l\l. 



TMXDT I I I 

+> I TMXDS 

I I 

I 

I 

I TAADS 
— >| |< — 

I I 

l_/l 

I \l 



I 
l<- 



I 



< — TPDW 



\/ 
./\ 



17/40 



DYNAMIC RAMS 



This chapter covers the constraints and features of 
dynamic random access memories used in the TED system. 



6.1 



ELECTRICAL SPECIFICATIONS 



Input Voltage (Vin) 
Supply Voltage (Vcc) 
Operating Temp (Ta) 
Storage Temp 
Input Leakage Current 
Dynamic Characteristics 
Input High Voltage (VIH) 
Input Low Voltage (VIL) 
Output High Voltage (VOH) 

(IOH=-200uA VCC=4.75VDC) 
Output Low Voltage (VOL) 

(IOL=-4.2ma VCC=5.25V) 
Max Power Supply Current 



-IV to +7.0 VDC 
-IV to +7.0 VDC 
to 70 'C 
-55 to 150 'C 
-10.0 uA 

Vcc = 5.0V +/-5% 
Vss+2 . 4V to Vcc+lV 
VSS-IV to Vss+. 8V 
VSS+2 . 4V 

VSS+. 4V 

8 0ma 



6.2 



CHARACTERISTICS 



This section covers some of the characteristics of 
the 64K by 1 bit RAM that is used in the TED 64 system. 



6.2.1 



PACKAGE PINOUT 



PIN 



NAME 



DESCRIPTION 



1 


NC 


2 


Din 


3 


/WE 


4 


/RAS 


5 


AO 


6 


A2 


7 


Al 


8 


VCC 


9 


A7 


10 


A5 


11 


A4 


12 


A3 


13 


A6 


14 


Dout 


15 


/CAS 


16 


VSS 



Data in 

Write Enable (Active Low) 

Row Address Strobe (Active Low) 

Address Bit 

Address Bit 2 

Address Bit 1 

Power Supply +5 

Address Bit 7 

Address Bit 5 

Address Bit 4 

Address Bit 3 

Address Bit 6 

Data Out 

Column Address Strobe (Active Low) 

Power Supply Ground 



6.2.2 



SELECTION CRITERIA 



The TED system uses low cost 200 ns access RAMs . Qualified parts must meet 
all timing parameters as specified in section 6.3.1 'TIMING CHART' and 
6.3.2 'TIMING DIAGRAM'. 



6.3 TIMING 

This section illustrates the required timing constraints in dealing with 
DRAM. 

( The next 2 scans [32,33] depicting the RAM timing chart 
are definitely unreadable and therefore missing ) 



18/40 



THE USER PORT 



This chapter details the system User Port. 

7.1 DESCRIPTION 

The USER PORT is included to allow various terminal and modem 
devices to connect to the TED system. Transmission and reception 
is via a 6551 ACTA, with handshaking assistance from a 6529 single port 
device. The 6551 and the 6529 are each accessible to the TED system 
in software, thus allowing their programming for various applications. 

The 6551 ACTA is enabled by addresses $FDOO to $FDOF. The least 
significant two bits of the address will choose the mode, which may be 
set for transmit/receive, receive status, or programming of either the 
command register or the control register. Similarly, the 6529 is 
activated by the addresses $FD10 to $FD1F. It permits seven bits of 
either input or output, depending upon the status of the Read/Write line. 
The eighth bit, bit two to be exact, is used as the cassette sense input. 
It may be possible to utilize this bit of certain precautions are taken in 
software. ( I.E. Insure that cassette sense is not grounded.) 

The User Port itself provides access to various signals generated 
by these two chips, in addition to the ATN and Buffered Reset (BRESET) 
lines of the TED system. The port also provides ground, +5VDC and +9VAC 
for use by connected devices. 

7.2 PHYSICAL PINOUT 

PIN NAME DESCRIPTION DIRECTION 



A 


GND 


Ground 








B 


PO 


I/O Port 


Bit 




Input/Output 


C 


RxD 


Receive Data 




Input 


D 


RTS 


Request to Send 




Output 


E 


DTR 


Data Terminal Re 


ady 


Output 


F 


P7 


I/O Port 


Bit 7 




Input/Output 


H 


DCD 


Data Carrier Det 


ect 


Input 


J 


P6 


I/O Port 


Bit 6 




Input/Output 


K 


CTS 


Clear to 


Send 




Input 


L 


DSR 


Data Set 


Ready 




Input 


M 


TxD 


Transmit 


Data 




Output 


N 


GND 


Ground 










1 


GND 


Ground 










2 


+ 5 


+ 5VDC 










3 


/BRESET 


Buffered 


System 


Reset 


Output 


4 


P2/CST Sense 


I/O Port 


Bit 2 




Input/Output 


5 


P3 


I/O Port 


Bit 3 




Input/Output 


6 


P4 


I/O Port 


Bit 4 




Input/Output 


7 


P5 


I/O Port 


Bit 5 




Input/Output 


8 


RxC 


Receive Clock 




Input/Output 


9 


ATN 


Attention 




Output 





+ 9 


+ 9 VAC 










1 


+ 9 


+ 9 VAC 










2 


GND 


Ground 









7.3 ELECTRICAL SPECIFICATIONS 
I/O Ports (P0,P2 . .P7) 



These ports are capable of driving up to four TTL type 
loads each in output configuration. 

Buffered Reset (/BRESET) 



The buffered reset line is capable of driving at least 
one TTL level load. It can drive a total of ten TTL loads 

19/40 



between the User Port, the Serial Port, and the Expansion Port. 

Attention (ATN) 

This line is capable of driving at least one TTL level 
load. It can drive a total of ten TTL loads between the User 
Port and the Serial Port . 

Receive Data (RxD) 

The Receive Data input may be driven by a single TTL 
level driver. 

Other Inputs (DCD, DSR, CIS) 

The remaining data inputs are buffered by TTL buffers. 
Each may be driven by a single TTL level driver. GTS is sensed 
via 6529 under software control. 

Receive Clock (RxC) 

The Receive Clock, when acting as an output, can drive 
a single TTL level load. As an input, it must be driven by at 
least one TTL level load. 

Transmit Data (TxD) 

The Transmit Data output is capable of driving a single 
TTL level load. 

Other Outputs (RTS, DTR) 

The remaining outputs are each buffered by a TTL buffer, 
thus each of them will drive ten TTL level loads. 

Five volt source (+5) 

The five volt source is regulated DC, capable of supplying 
100 mA worst case. 

Nine volt source (+9) 

The nine volt source is an unregulated nine volt (RMS) 
supply, capable of supplying a worst case current of 400 DC mA. 



PARAMETER 


SYMBOL 


MIN 


MAX 


UNIT 


Transmit /Receive 
Clock Rate 


Tccy 


400 


- 


ns 


Transmit /Receive 
Clock High Time 


Teh 


175 


- 


ns 


Transmit Receive 
Clock Low Time 


Tel 


175 


- 


ns 


XTALl to TxD 
Propagation Delay 


Tdd 


- 


500 


ns 


Propagation Delay 
(/RTS, /DTR) 


Tdly 


- 


500 


ns 



/IRQ Propagation Tirq - 500 ns 
Delay (Clear) 

( The next 3 diagrams [in the 37 scan] depicting the 

20/40 



User port timing are too tiny to 
read and have been skipped ) 



7.5 



6551, 6529 TIMING 



PARAMETER 


SYMBOL 


MIN 


MAX 


UNIT 


PHI 2 PW 


PW02 


248 


350 


ns 


Address Set 
Up Time 


TACR 
TACW 


72 


- 


ns 


Address Hold 


TCAH 
TCAR 


25 


- 


ns 


R/W Setup 


TWCW 
TWCR 


71 


- 


ns 


R/W Hold 


TCWH 
TWCR 


93 


- 


ns 


Data Bus 
Setup 


TDCW 


148 


- 


ns 


Read Access 


TCDR 


195 


- 


ns 



Read Data 
Hold 



THR 



35 



ns 



( The following two diagrams, Write Cycle and 

Read Cycle [in the 38 scan] are too tiny to read and have been 
skipped ) 



7.6 



PLA PROGRAM CHART 



PRODUCT TERM 















INPUT 


VARIABLE 








N 


-- 


--- 


--- 


-- 


-- 


-- 




















U 


1 


1 


1 


1 


1 


1 


— 


-- 


-- 
















-- 


M 


5 


4 


3 


2 


1 





9 


8 


7 


6 


5 


4 13 


2 


1 






1 


L 


— 


— 


— 


— 


— 


— 


H 


— 


— 


— 


— 1 — 


— 


H 


H 


2 


- 


H 


H 


H 


L 


H 


H 


- 


H 


L 


L 


L 1 L 


H 


H 


- 


3 


L 


H 


H 


H 


L 


H 


H 


- 


H 


L 


L 


L|H 


H 


H 


H 


4 


L 


H 


H 


H 


L 


H 


H 


- 


H 


L 


L 


H|H 


H 


H 


H 


5 


- 


H 


H 


H 


L 


L 


H 


- 


H 


- 


- 


- 1 - 


H 


- 


- 


6 


L 


H 


H 


H 


L 


H 


H 


- 


H 


H 


H 


L|H 


H 


H 


H 


7 


L 


H 


H 


H 


L 


H 


H 


- 


H 


L 


L 


H|L 


H 


H 


- 



AlO A13 A8 MUX A7 A5 A15 F7 

RAS All A9 A14 A12 A6 A4 PhO 



ACTIVE LEVEL 

HHLLLLHL 

OUTPUT FUNCTION 
765413210 



\ . . 






\ . . 


1 . . A - 


. . A 
. A . 
. . . 1 


1 A . 
1 . A 

\\ . . 


A 



A K K A 

REED 

M R Y D 

N P R 



R C 



$ $ 



L F F 

K D D K 

1 

$ X X 



P S 

H P 

1 E 

2 E 
C 

C H 
L 



D F 
3 D 
X D 

X 



$ 
F 
D 
2 
X 



21/40 



( 7.7 TED PHI 2 Generation and 
PLA Internal Logic [40th scan] 
are hard to turn to ASCII and 
partly too tiny to read ) 



THE SERIAL BUS 



SERIAL BUS SPECIFICATION 
SERIAL BUS CONNECTOR PINOUT 



Pin 

1 
2 
3 
4 
5 



I 
- + - 



Type 



Serial SRQIN 

GND 

SERIAL ATN IN/OUT 

SERIAL CLK IN/OUT 

SERIAL DATA IN/OUT 



RESET 



DATA BYTES 



Ready-to-Send 
Talker Sending 



I I I I I I I I I I I I I I I 
l_l l_l l_l l_l l_l l_l l_l I. 



ATN 



->l ? I<- 



I II I 211 311 411 511 611 71 
l_l l_l l_l l_l l_l l_l l??l 

-> : 

Data Valid 
Listener Ready for Data 



I 



/ 5 1 \ 
I // 6 \\ I 
I . -=- . I 

\4* . *2/ 
- *3 - 



: <> 



|_ Listener Data Accepted 



I I I I I I I I I 

l_l l_l l_l l_l l_ CLOCK 
I ?? I I 



SERIAL BUS TIMING 







Symbol 


Min 


Typ 


Max 


ATN Response (Required) 


(1) 


TAT 


- 


- 


lOOOus 


Listener Hold-Off 




TH 





- 


oo 


Non-EOI Reponse to ??? 


(2) 


TNE 


- 


40ns 


200us 


Bit Set-Up Talker 


(4) 


TS 


20us 


70us 


- 


Data Valid 




TV 


20us 


20us 


- 


Frame Handshake 


(3) 


TF 





20 


lOOOus 


Frame To Release to ATN 




TR 


20us 


- 


- 


Between Bytes Time 




TBB 


lOOus 


- 


- 


EOT Response Time 




TYE 


200us 


250us 


- 


EOT Reponse Hold Time 


(5) 


TE 


60us 


- 


- 


Talker Response Limit 




TRY 





30us 


60us 


Byte Acknowledge 


(4) 


TPR 


20us 


30us 


- 


Talk Attention Release 




TTK 


20us 


30us 


lOOus 


Talk Attention Acknowl-DOS 


TDC 





- 


- 


Talk Attention Ack.Hold 




IDA 


50us 


- 


- 


EOT Acknowledge 




TFR 


60us 


- 


- 



(5) TEI Min. Must be 80us for external device to be a Talker 

(4) TV and TPR min must be 60us for external device to be a Talker 



22/40 



(3) If Max. Time exceeded, Frame Error. 

(2) If Max. Time exceeded EOT Response required 

(1) If Max. Time exceeded, Device not present Error 

Notes : 

( Both diagrams and table are partly hand-written and are 
hard to read. Some of the times might be ms instead of us, 
some of the labels might be wrong ) 



10. THE EXPANSION BUS 



10.1 EXPANSION BUS PINOUT 

PIN NAME PIN NAME 



1 


GND 


A 


GND 


2 


+ 5 


B 


CILOW 


3 


+ 5 


C 


/BRESET 


4 


/IRQ 


D 


/RAS 


5 


R/W 


E 


PHIO 


6 


CIHI 


F 


A15 


7 


C2L0W (reserved) 


H 


A14 


8 


C2HI (reserved) 


J 


A13 


9 


/CSl 


K 


A12 


10 


/CSO 


L 


All 


11 


/CAS 


M 


AlO 


12 


MUX 


N 


A9 


13 


BA 


P 


A8 


14 


D7 


R 


A7 


15 


D6 


S 


A6 


16 


D5 


T 


A5 


17 


D4 


U 


A4 


18 


D3 


V 


A3 


19 


D2 


W 


A2 


20 


Dl 


X 


Al 


21 


DO 


Y 


AG 


22 


AEG 


Z 


NC 


23 


EXT AUDIO 


AA 


NC 


24 


PHI 2 


BB 


NC 


25 


GND 


CC 


GND 



10.2 EXPANSION CONNECTOR SIGNAL DESCRIPTION 

AO - A15 System Address Bus - unbuffered. Output. 

DO - D7 System Data Bus - unbuffered. Output. 

/CSO, /CSl Internal ROM Chip Selects. Output. 

/CILOW, CIHI External Cartridge Chip Selects. Active Low. Output 

/RAS DRAM Row Address Strobe. Output. 

MUX DRAM Address Multiplex Control Signal. Output. 

/CAS DRAM Column Address Strobe. Output. 

BA Bus Available. Low for DMA. Output Only. 

PHI 2 Artificial PHI 2. Address Valid Rising Edge. 

Data Valid Falling Edge. Output. 

R/W System Read Write Line. Output. 

23/40 



/IRQ 
/BRESET 
EXT AUDIO 



Interr. Request. Input. 

Buffered Reset. Output. 

External Audio. Input. 1 V p-p Full Scale, 
AC Coupled. 



11. 



READ ONLY MEMORY 



11.1 



SYSTEM ROM DESCRIPTION 



figuration, 
only memory 

in the upp 
f the lower 
on, is the 
try points 
gher level 
ed above th 

space alio 
on $D000 - 
ROM not use 





In a basic con 


resides 


in 32K of read 


ROM. The 


KERNAL resides 


as High 


ROM) and some o 


The Kernal, by definiti 


computer 


, with fixed en 


to facil 


itate use by hi 


for the 


Kernal is locat 


$FFF9) C 


ontained in the 


character ROM at locati 


containe 


d in the lower 



the TED operating system 
contained in two 16K X 8 
er 16K ROM (referred to 

16K ROM (LOW ROM) . 
operating system of the 
into usable subroutines 
programs. The entry table 
e 7360 in memory. ($FF40 - 
cated for the Kernal is the 
$D7FF. 'BASIC is 
d by the Kernal . 



11.2 



BANKING ROM OPERATION 



Although the system can only ' see' 32K of ROM 
at a time, up to 64K can be installed on bpard, with 
an additional 32K on as external cartridge. This 
is possible using the scheme known as 'banking' . 
Banking is accomplished by writing to three address 
range of $FDDO - $FDDF. When a write to this address 
range occurs, the lower four bits of the address bus 
select 2 of 8 banks (each 16K) . Refer to the chart below. 



AO 



Al 



BANK 












1 


1 





1 


1 



low internal #1, 'BASIC 

low internal #2, 'FUNCTION LOW' 

low external #1, 'CARTRIDGE LOW' 

reserved 



A2 



A3 



BANK 









hi internal 


#1, 





1 


hi internal 


#2, 


1 





hi external 


#1, 


1 


1 


reserved 





'KERNAL' 
'FUNCTION HI' 
'CARTRIDGE HI' 



Even when the Kernal is banked out, part of 
the Kernal remains accessible. This is the part of 
the Kernal that does the actual banking and is located 
in the address range of $FCOO to $FCFF. This section 
of ROM will not assert itself if ROM is banked out 
for RAM. 



11.3 ROM ELECTRICAL SPEC 

Absolute Maximum Ratings 
INPUT VOLTAGE (Vin) 



5V to +7.0 VDC 



24/40 



SUPPLY VOLTAGE (Vcc) 
OPERATING TEMP (Ta) 
STORAGE TEMP 



-. 5V to +7.0 VDC 
to 70 'C 
-55 to 150 'C 



D.C. Characteristics 



INPUT LEAKAGE CURRENT 
DYNAMIC CHARACTERISTICS 
INPUT HIGH VOLTAGE (VIH) 
INPUT LOW VOLTAGE (VIL) 
OUTPUT HIGH VOLTAGE (VOH) 

(IOH=-200uA VCC=4.75VDC) 
OUTPUT LOW VOLTAGE (VOL) 

(IOL=-3.2ma VCC=5.25V) 
MAX POWER SUPPLY CURRENT 



-10 ua 

Vcc = 5.0V +/-5% 
Vss+2 . 4V to Vcc+lV 
VSS-. 5V to Vss+. 8V 
VSS+2 . 4V 

VSS+. 4V 

12 mA 



11.4 



2 312 8 ROM PINOUT 



PIN 



NAME 



DESCRIPTION 



1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 



NC 

A12 

A7 

A6 

A5 

A4 

A3 

A2 

Al 

AG 

DO 

Dl 

D2 

GND 

D3 

D4 

D5 

D6 

D7 

/CS 

AlO 

/CE 

All 

A9 

AS 

A13 

CS or CE 

VCC 



Address Bit 12 

Address Bit 7 

Address Bit 6 

Address Bit 5 

Address Bit 4 

Address Bit 3 

Address Bit 2 

Address Bit 1 

Address Bit 

Data Bit 

Data Bit 1 

Data Bit 2 

Power Supply Ground 

Data Bit 3 

Data Bit 4 

Data Bit 5 

Data Bit 6 

Data Bit 7 

Chip Select / Active Low 

Address Bit 10 

Chip Enable / Active Low 

Address Bit 11 

Address Bit 9 

Address Bit 8 

Address Bit 13 

Chip Select or Chip Enable / Active High 

Power Supply +5 



11.5 



ROM TIMING SPECIFICATION 



Address INVALID \ 
Inputs / 



Chip 



Select DISABLED 
Inputs 



High 

Data 

Outputs Impedance 



VALID 



\ I / ENABLED 
./l\ 

I 

I < — 'CO — > 



INVALID 



/INVALID \/ 
\ /\ 



' ACC 



VALID 



\ I / DISABLED 

./l\ 

I 



.1 



High 



\/ INVALID \ 

/\ / Impedance 



25/40 



PARAMETER SYMBOL MIN. MAX. 



ACCESS TIME TACC 300 - ns 

OUTPUT ENABLE TOE 120 - ns 

Note: TACC available from system is 338ns and TOE available is 12 



12. THE KEYBOARD 

12.1 KEYBOARD CONNECTOR PINOUT 

PIN NAME DESCRIPTION 



1 


1 


D5 


Data Bit 5 






1 


3 


K7 


Key Latch Bit 


7 




3 


4 


GND 


LED GND 






4 


- 


+ 5V 


LED +5Volt 20ma 


Max 


5 


6 


D7 


Data Bit 7 






6 


7 


K4 


Key Latch Bit 


4 




7 


8 


Dl 


Data Bit 1 






8 


9 


K5 


Key Latch Bit 


5 




9 


10 


K6 


Key Latch Bit 


6 




10 


11 


D3 


Data Bit 3 






11 


12 


D2 


Data Bit 2 






12 


13 


D4 


Data Bit 4 






13 


14 


K2 


Key Latch Bit 


2 




14 


15 


Kl 


Key Latch Bit 


1 




15 


16 


D6 


Data Bit 6 






16 


17 


K3 


Key Latch Bit 


3 




17 


18 


KO 


Key Latch Bit 







18 


19 


DO 


Data Bit 







12.2 KEYBOARD MATRIX (Plus4 C16) 

Keyboard Matrix 





P 




(18) (15) (14) (3) (7) (9) (10) (17) C16 






L 




(17) (14) (13) (2) (6) (8) (9) (16) Plus 


4 


c 
1 

6 


U 
S 
4 




1 1 1 + + + + 

1 1 1 1 Run 1 1 1 1 








( 6) 
( 8) 


( 5) 
( 7) 


D7 


1 1 IClr ICtrl 1 Stop | Space | C= | Q | 2 

1 1 1 1 1 1 1 1 




Dl 


13 1 W 1 A 1 Shift 1 Z IS IE | 4 
15 |R ID |X |C IF IT 16 


/ 1 
--0 0-- 1 
Shift Lock 


D2 


(12) 


(11) 


D3 


|7 |Y |G IV IB |H |U 18 


SW 


(11) 


(10) 


D4 


+ + + + + + + + 

19 II |J IN |M |K 10 10 




(13) 


(12) 





+ + + + + + + + 




( 1) 


( /) 


D5 


1 \l/ 1 P 1 L 1 , 1 . 1 : 1 - 1 /|\ 

1 <- 1 * 1 ; 1 / 1 ESC 1 = 1 + 1 -> 




D6 




(16) 


(15) 


DO 


+ + + + + + + + 

1 DEL IRetrnlUKP | @ | fl | f2 | f3 | Help 




(19) 


(18) 





+ + + + + + + + 





K|0 K|l K|2 K|7|K|4 K|5 K|6 K|3 > TED 

I 
V 

(4) /\/\/\ 

Plus4 I 

(3) (|<|) I 



26/40 



12.3 KEYBOARD ELECTRICAL SPECIFICATION 

1) Maximum Rating 12VDC, 200uS pulse width 1/50 duty cycle Ima 

2) Chattering 5mSEC Initial, lOmSEC over life 

3) Contact Resistance 500 Ohm max. 

4) Capacitance lOOpf max. 

5) Insulation res. 50M Ohm min. 

6) Withstand voltage 250VAC Imin. 

7) Operating force 65s typ. 

Zero trav force 15+/-10g at .5mm trav 

Full trav force 90+/-25g at .5mm above full trav 

8) Operating life 500 million times 
Function keys 300 million times 

9) Operating Temp -5 - +50 'C 

10) Storage Temp -20 - +65 'C 

7360R7 TIMING SPECIFICATIONS NTSC ONLY 

Single clock lo Single clock hi Double Clock lo Double clock hi 
min max min max min max min max 



1117 1118 558 559 558 559 

535 585 275 295 260 285 

60 110 60 110 

220 260 220 260 

60 110 60 110 

260 290 260 290 

60 110 60 110 

300 365 300 365 

420 470 420 470 

20 20 

35 35 

75 75 

160 160 

305 305 305 

40 110 40 110 

10 40 



Tcyc in 


69.81 


69.88 


PW in lo 


25 


45 


PW in hi 


25 


45 


Tcyc 


1117 


1118 


Clock PW 


535 


585 


Tclkraslh 


60 


110 


Tclkrashl 


220 


260 


Tclkmuxlh 


60 


110 


Tclkmuxhl 


260 


290 


Tclkcaslh 


60 


110 


Tclkcasrd 


300 


365 


Tclkcaswr 






Traslmuxl 


20 




Tmuxlcasl 


35 




Traslcasl 


75 




Tcaswrash 


160 




Tclkcsl 




305 


Tclkcsh 


40 


110 


Tclkaec 


10 


40 


PWras lo 


360 


440 


PWras hi 


120 


200 


PWcas lo 


170 


360 


PWcas hi 


200 


390 


Taddoutac 




150 


Taddoutrl 




40 


Tdoutstp 






Tdouthld 






Tdinstp 




90 


Tdinhld 




10 


Taddinstp 






Taddinhld 







150 
40 
160 160 

40 120 40 120 

90 90 

10 410 

400 400 



27/40 



Approved: | 
4/19/83 I 
I. 



Released 




DIE SIZE: X:206 Y:19i 



7 6 5 4 

\ \ \ X I 

\ \ \ \ I 



I 



9 I 

10 I 

11 I 

_l 
12_/ . I 

13 I 

. I 



14 



.1 



15 



\. 



16 I 

17 I 

18 I 

19 I 

_l 
2 0_/ 



3 2 1 4i 
I I I I 
I I I I 



47 46 45 44 43 
/ / _/ _/ _/ 
I / / _/_/ 



I 



.4 2 

.41 

40 

.3 9 

.3 8 

37 

.3 6 

.3 5 

34 

33 



\ 
I \ \ 

17 7 ~\~\~\ I I I \I\_ 31 
/ / / / I I \ \ \ \ 
21 22 23 24 25 26 27 28 29 30 



1 
2 
3 
4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 



A2 2 5 

Al 2 6 

AO 27 

Vdd 2 8 

29 

CS 30 

CSI 31 

R/W 32 

IRQ 33 

MUX 3 4 

RAS 3 5 

CAS 3 6 

PhiOUT 37 

Color 38 

PhilN 39 

KYBDO 40 

KYBDl 41 

KYBD2 42 

KYBD3 43 

KYBD4 44 

KYBD5 45 

KYBD6 4 6 

KYBD7 47 
LUM/Sync 48 
VSS 



7360R0 
DBO 
DBl 
DB2 
DB3 
DB4 
DB5 
DB6 
DB7 
SND 
BA 
AEC 
A15 
A14 
A13 
A12 
All 
AlO 
A9 
A8 
A7 
A6 
A5 
A4 
A3 



Package: 48 Lead Plastic 

Die Attach Area: X:290 Y:280 Scale: 20X 
+ + 

48 Lead bonding diagram | Page of | Specification No. 
+ + 

SCOPE 

This specification covers the detailed requirements for a high resolution 
video display chip utilizing HMOS technologies. This device is intended for 
use in low end 6502-based personal home computer systems. 

The TED chip is a 48 pin device which controls video output, system timing, 

dynamic RAM control, ROM chip selects, and keyboard control. The TED contains 

34 control registers which are accessed through the standard 6502 

microprocessor data bus. It will access up to 64K of memory for display 
information . 



CHARACTER MODES 



In any of the character modes, the TED chip displays 25 lines of 40 characters 
per line. Each character on the screen can be set to any of 16 possible 
colors, with 8 possible luminance levels. 

The character pointers in the VIDEO MATRIX determine what character will be 
display in a particular place. Associated with each location of the video 
matrix is an 8 bit color memory location, called the ATTRIBUTE byte. The 
attribute byte determines the color, luminance level, and wether that 



28/40 



character will flash. 

The TED chip fetches character pointers from the area of memory known as the 
VIDEO MATRIX area, and color information from the ATTRIBUTE area. 
The video matrix consists of 1000 consecutive locations in memory, each of 
which contains an 8 bit character pointer. The location of the video matrix 
is determined by the VIDEO MATRIX BASE REGISTER in the TED (bits 3-7 of 
Register #20), which provides the 5 MSB of the video matrix address 
(A15-A11) . The address AlO is always set to a 1 . This gives 32 possible 
locations for the start of the video matrix. 



The following chart makes this clear: 
BASE ADDRESS LOCATION 



BASE ADDRESS 



LOCATION 



00000 
00001 
00010 
00011 
00100 
00101 
00110 
00111 
01000 
01001 
01010 
01011 
01100 
01101 
OHIO 
01111 



$0400 

$ocoo 

$1400 
$1C00 
$2400 
$2C00 
$3400 
$3C00 
$4400 
$4C00 
$5400 
$5C00 
$6400 
$6C00 
$7400 
$7C00 



10000 
10001 
10010 
10011 
10100 
10101 
10110 
10111 
11000 
11001 
11010 
11011 
11100 
11101 
11110 

11111 



$8400 
$8C00 
$9400 
$9C00 
$A400 
$ACOO 
$B400 
$BCOO 
$C400 
$CCOO 
$D400 
$DCOO 
$E400 
$ECOO 
$F400 
$FCOO 



Each memory location in video matrix is used as a pointer to the actual 
character dot data which makes up the characters. The eighth (MSB) bit of 
each character pointers (VM7) can be interpreted in two different 
ways. If the RVS on bit of Ted Register 7 is a 0, the MSB of the video 
matrix (VM7) will determine if the character will be displayed reversed or 
not. If VM7 is set to 0, the character will be displayed normally. If VM7 is 
set to a 1, the character at that location will be displayed in reverse. Use 
of this feature limits the number of different character definitions to 128. 
If the RVS ON bit is set to a 1, the reverse feature feature is turned off, 
which allows the use of 256 different character definitions. 



VIDEO MATRIX ADDRESS 
A15 A14 A13 A12 All AlO A9 A8 A7 A6 A5 A4 A3 A2 Al AO 



VM4 VM3 VM2 MVl VMO 1 



VC9 VC8 VC7 VC6 VC5 VC4 VC3 VC2 VCl VCO 



The attribute memory also consists of 1000 consecutive locations, and con- 
tains the FLASH bit, the 4 bits of color and the 3 bits of luminance for each 
character location. The location of the attribute memory is also controlled 
by the VIDEO MATRIX base register. Like the video matrix, the upper 5 bits of 
the address of the attributes are the VIDEO BASE REGISTER. However, for 
attribute memory, AlO is always set to a 0, so is always IK below the video 
matrix. For example, if the video matrix is at $0C00, the attribute bytes 
are at $0800. 



ATTRIBUTE MEMORY ADDRESS 
A15 A14 A13 A12 All AlO A9 A8 A7 A6 A5 A4 A3 A2 Al AO 



VM4 VM3 VM2 MVl VMO 



VC9 VC8 VC7 VC6 VC5 VC4 VC3 VC2 VCl VCO 



Each character is matrix of 8 by 8 dots, stored in the character ROM as 8 
consecutive bytes. The location of this CHARACTER memory is set by CB4 to CBO 



29/40 



of TED Register 19. These bits are used as the 5 most significant bits of the 
character base address. The next 8 bits of the address of a particular 
character pattern come from the value of that particular location in the video 
matrix. (The last 3 bits come from a counter.) 

CHARACTER DATA ADDRESS 

A15 A14 A13 A12 All AlO A9 A8 A7 A6 A5 A4 A3 A2 Al AO 

CBS CB4 CB3 CB2 CBl VM7 VM6 VMS VM4 VM3 VM2 VMl VMO 

CBO (with REVERSE bit on) 

STANDARD CHARACTER MODE 

In standard character mode, the character display is an 8 dot horizontal by 8 
dot vertical character location formatted in 2S rows of 40 characters per row. 
Each character location in the video matrix has a unique color set by its 
attribute byte and share a common background color. Eight sequential bytes 
from character memory are displayed directly on the 98 lines of each character 
location. A '0' bit causes the color/luminance in background color register 
to be used; a ' 1' bit causes the color/luminance of the associated byte of 
attribute memory to be displayed. 



bit of character data 



color source 



luminance source 



background reg 0, bits 0-3 bkgd reg 0, bits 4-6 
attribute bits 0-3 attribute bits 4-6 



MULTICOLOR CHARACTER MODE 



Mult 


icolor 


charact 


colors per 


charact 


Mult 


icolor 


mode is 


to a 


1. Th 


is cases 


diff 


Brent manner. 


is a 


the 


charact 


character. 


If bit 


as a 


multicolor ch 


on a 


singl 


3 screen 


colors, however. 


data 


is defined as 


byte 


. The 


charact 


dots 


twice 


as wide 


inte 


rprete 


1 as fol 




dot p 


air 




00 






01 






10 






11 





er mode provides 
er location) at a 

selected by sett 

the data in char 
When in multicolo 
er at that locati 
3 of the attribut 
aracter. This al 
Only the first 
When a character 

eight sequential 
er is displayed a 

as in standard c 
lows : 



additional 

cost reduc 
ing the mul 
acter memor 
r mode, if 
on will be 
e is a 1, t 
lows the tw 
8 colors a 
is displaye 
bytes of c 
s a 4 by 
haracter mo 



color fl 
ed horiz 
ticolor 
y to be 
bit 3 of 
displaye 
hat char 
o charac 
re avail 
d in mul 
haracter 
dot matr 
de. The 



exib 
onta 
bit 
inte 

the 
d as 
acte 
ter 
able 
tico 
, wi 
ix, 

dot 



ility (up 
1 resoluti 
(TED Regis 
rpreted in 

attribute 

normal (h 
r will be 
types to b 

as foregr 
lor, the c 
th 4 dot p 
with the h 

pairs are 



to four 
on . 
ter 7) 

a 

byte 
ires) 

displayed 
e mixed 
ound 

haracter 
airs per 
orizontal 



color source 
bkgd reg 0, bits 0-3 
bkgd reg 1, bits 0-3 
bkgd reg 2, bits 0-3 
attribute bits 0-2 



luminance source 
bkgd reg 0, bits 4-6 
bkgd reg 1, bits 4-6 
bkgd reg 2, bits 4-6 
attribute bits 4-6 



Each character location can contain 4 colors, one unique to the character 
location, the other 3 in common with all other characters on the screen. 

EXTENDED COLOR MODE 



EXTENDED COLOR MODE allows the individual 
foreground colors in each character locat 
location can select one of the 16 foregro 
background registers. The character dot 
color mode (with foreground color/luminan 
' 1' data bit), but the two MSB of the cha 
the background color/luminance for that s 
the character pointer are in use, this me 
definitions in the character memory are a 
and A9 to 0) . 



selection 
ion on the 
und colors 
data is dis 
ce determin 
racter poin 
creen locat 
ans that on 
vailable . 



of both background and 
screen. Each character 
and one of 4 available 
played as in standard 
ed by the attribute for a 
ters are used to select 
ion. Since the 2 MSB of 
ly the first 64 character 
(The TED chip forces AlO 



30/40 



Bits 6 & 7 
character pointer 

00 

01 

10 

11 



BACKGROUND COLORS 
color source 

bkgd reg 0, bits 0-3 

bkgd reg 1, bits 0-3 

bkgd reg 2, bits 0-3 

bkgd reg 3, bits 0-3 



luminance source 

bkgd reg 0, bits 4-6 

bkgd reg 1, bits 4-6 

bkgd reg 2, bits 4-6 

bkgd reg 3, bits 4-6 



ADDRESS 


$0000 


$2000 


$4000 


$6000 


$8000 


$A000 


$C000 


$E000 



STANDARD (HIRES) BIT MAP MODE 

In bit map mode there is a one to one correspondence between each displayed 
dot and memory bit. Standard bit map mode provides a screen resolution of 
320 dots by 200 vertical dots. Each 8 by 8 square (corresponding to the 
character locations in standard character mode) can have an individually 
controlled background and foreground color. 

The start of the bit map data area comes from the BIT MAP BASE register. The 
3 bits of the bit map base are used as the A15-A13 of the address. The bit 
map data area is 8K, therefore bit map areas must start on 8 K boundaries. 

BIT MAP BASE 

000 
001 
010 
Oil 
100 
101 
110 
111 

When in bit map mode, both the video matrix and the attribute memory are used 
for color data. The address of the bit mapped data is formed by combining 
the 3 bit BIT MAP BASE register as the MSB of the data address with the 10 bit 
character position counter and the 3 bit raster counter. This addressing 
scheme results in each 8 sequential memory locations being formated as an 8 by 
8 block on the video display, something like this: 

byte byte 8 byte 16 byte 312 

byte 1 byte 9 byte 17 byte 313 

byte 2 byte 10 byte 18 byte 314 

byte 3 byte 11 byte 19 byte 315 

byte 4 byte 12 byte 20 byte 316 

byte 5 byte 13 byte 21 byte 317 

byte 6 byte 14 byte 22 byte 318 

byte 7 byte 15 byte 23 byte 319 

byte 320 byte 328 byte 336 byte 632 

byte 321 byte 329 byte 337 byte 633 

byte 322 byte 330 byte 338 byte 634 

byte 323 byte 331 byte 339 byte 635 

byte 324 byte 332 byte 340 byte 636 

byte 325 byte 333 byte 341 byte 637 

byte 326 byte 334 byte 342 byte 638 

byte 327 byte 335 byte 343 byte 639 

etc . 

(or it could be represented like this:) 

A15 A14 A13 A12 All AlO A9 A8 A7 A6 A5 A4 A3 A2 Al AO 

BB2 BBl BBO CP9 CP8 CP7 CP6 CP5 CP4 CP3 CP2 CPl CPO VS2 VSl VSO 

31/40 



When in standard bit map mode, the color information is derived from the data 
stored in the video matrix, while the luminance information comes from the 
attribute data. This allows for 2 colors to be independently selected in each 
8 by 8 area. When the bit to be displayed is a '0', the color of the dot 
output is set by the lower 4 bits of the video matrix; the luminance is 
selected by bits 4-6 of attribute memory. When a bit to be displayed is a 
'1', the color is set by the upper 4 bits of the video matrix; the luminance 
is set by bits 0-2 of attribute memory. 



dot 

1 



color source 

video matrix bits 0-3 

video matrix bits 4-6 



luminance source 
attribute bits 4-6 
attribute bits 0-2 



MULTICOLOR BIT MAP MODE 



MULTICOLOR bit map mode bears the same relationship to standard bit map mode 
as multicolor character mode does to standard character mode. Multicolor bit 
map mode allows greater color selection at the cost of horizontal resolution. 
Using multicolor mode, up to four different colors can be displayed in each 
8 by 8 bit block. 

The bit map data area is addressed exactly the same as in standard bit map 
mode. The dot data and color information is interpreted differently, however. 

Multicolor bit map mode is selected by setting both the multicolor bit and the 
bit map bit to ' 1' . 

As in multicolor character mode, multicolor bit map mode uses the concept of 
'dot pairs' to specify one of our pixel colors. Sine two bits select one dot 
color, the horizontal resolution is halved (160H by 200V) . Each multicolor 
pixel is twice as wide as hires pixel. 



dot pair 
00 
01 
10 

11 



color source 
bkgd reg 0, bits 0-3 
video matrix bits 4-7 
video matrix bits 0-3 
bkgd reg 1, bits 0-3 



luminance source 
bkgd reg 0, bits 4-( 
attribute, bits 4-6 
attribute, bits 4-6 
bkgd reg 1, bits 4-( 



ADDITIONAL FEATURES 



Hardware Cursor 



The hardware cursor is controlled by a 10 bit cursor compare register 
(Register 12 and 13) . This allows 1024 possible positions. Setting the 
cursor compare register bits to a value from to 999 results in the cursor 
appearing in the specified location (the top left corner of the screen is 0, 
the bottom right corner is 999, etc.) . The cursor will blink at the rate of 
2Hz, by switching the foreground and background colors in that location. 
Note: The hardware cursor can only appear during standard character mode. 

Flash 

The TED chip provides the ability to Flash any or all characters on the screen 
when using standard character mode, when the TED chip Flash bit is enabled. 
Flash is selected on a character by character basis, via the MSB of the 
attribute memory location for that character. When a character is flashing 
the foreground color of that character will turn off (change to background 
color) and on again at the rate of 2 Hz. 

Dynamic Ram Refresh 

Dynamic RAM refresh operation is controlled by the TED chip. Five, RAS only 
refreshes are performed during every raster line, immediately following 



32/40 



character fetches. TED guarantees a maximum delay of 3.26msec between the 
refresh of a single row address in a 256 address refresh scheme. This refresh 
is totally transparent to the system, since refresh occurs during phase one of 
the single speed system clock. 

System Clock Doubling 

For increased processor throughput, the system clock output from TED doubles 
frequency from 894KHz (NTSC) to 1.788KHz (NTSC) , during non-display times. 
The horizontal position register counts 456 dots, to 455. During counts of 
400-344, wile in raster lines to 204, the TED device outputs single clock. 
During this time TED is doing processor handshaking (counts 400-432), 
character fetches (counts 432-304), and dynamic RAM refresh (counts 304-344) . 
Outside of this horizontal window TED outputs double clock (1.788KHz) . During 
raster lines 205-261 for NTSC (205-311 for PAL), TED outputs double clock at 
all times except horizontal counts 304-344 which are single clock to allow for 
dynamic RAM refresh. If the blanking bit (Register #6) is cleared, the active 
display is cleared, the screen is filled with border color, and double clock 
is enabled at all times except refresh. 

Sound 

The TED device has two separate square wave generators. The frequency base 
for voices 1 and 2 are 10 bit registers (Register #24 and 18 for Voice 1 and 
Register #15 and 16 for Voice 2. Voice 2 can be selected to be either a 
square wave generator or a white noise generator. The voice selection and 
volume control mechanism is Register #17. There are 9 volume levels in TED, 
ranging from being off to 8 being loud. Programming values of 9-15 in the 
lower nibble at this register is identical to programming the loudest, volume 
8, level. Bits 4-6 of this register each individually select Voice 1, Voice 
2, or white noise respectively. Voice 2 and white noise cannot be enabled 
together, instead Voice 2 selection will override white noise selection. The 
frequency generated by TED is: 

FREQUENCY = 111860.781 

(1024-x) for NTSC 

= 110840.45 

(1024-x) for PAL 

A sampling frequency chart follows. 

NOTE BASE REGISTER VALUE ACTUAL FREQUENCY (HZ) 





(1028-x) 


A 


1017 


B 


906 


C 


855 


D 


762 


E 


679 


F 


641 


G 


571 


A 


508 


B 


453 


C 


428 


D 


381 


E 


339 


F 


320 


G 


285 


A 


254 


B 


226 


C 


214 


D 


190 


E 


170 


F 


160 


G 


143 



110 

123.5 

130.8 

146.8 

164.7 

174.5 

195.9 

220.2 

246. 9 

261.4 

293.6 

330 

349.6 

392.5 

440.4 

494. 9 

522.7 

588.7 

658 

699 

782.2 



33/40 



A 127 




880.7 




B 113 




989.9 




C 107 




1 


.045K 




D 95 




1 


.177K 




E 85 




1 


.316K 




F 80 




1 


.398K 




G 71 




1 


.575K 




Internal Operation 










All internal timing operations are 


based on th 


B horizontal dot counter. 




Particular events occur in response to certain 


counts o 


f both the horizont 


al 


position register and the vertical 


line regist 


ar . 






HORIZONTAL DECODES 




HORIZONTAL COUNT 




Horizontal Sync Start 






358 




Stop 






390 




Horizontal Equalization Pulse 


1 Start 
Stop 




152 
170 




Pulse 


2 Start 
Stop 




380 
398 




Horizontal Blanking Start 






344 




Stop 






416 




Burst Start 






384 




Stop 






408 




Character Windows Start 






432 




Stop 






296 




External Fetch Window Start 






400 




Stop 






288 




Refresh Single Clock Start 






288 




Stop 






328 




Character Window Single Clock 


Start 
Stop 




432 
296 




40 Column screen Start 






451 




Stop 






315 




38 Column screen Start 






3 




Stop 






307 




Video Shift Register Start 






440 




Stop 






304 




Increment Blink 






336 




Increment Vertsub Counter 










Increment Refresh Start 






296 




Stop 






336 




Increment Character Position Reload 




424 




Increment Character Position 


Start 
Stop 




432 
288 




Latch Character Position to Reload 




290 




End of Screen - Clear Vertical Line, Vert 


leal 


384 




Sub and Character Reload Registers 








Increment Vertical Line 






376 




Many of the events are qualified by a vertical 


line count. 




VERTICAL DECODES 




VERTICAL COUNT 




End of Screen PAL 






311 




End of Screen NTSC 






261 




Vertical Sync PAL Start 






254 




Stop 






257 




NTSC Start 






229 




Stop 






232 




Vertical Equalize PAL Start 






251 




Stop 






260 




NTSC Start 






226 




Stop 






235 




Vertical Blanking PAL Start 






251 




Stop 






269 





34/40 



NTSC Start 226 

Stop 244 

Attribute Fetch Start 

Stop 203 

Frame Window Stop 204 

Vertical Screen Windows 25 Row Start 4 

Stop 204 

24 Row Start 8 

Stop 200 

TED REGISTER DESCRIPTION 

Internal Timers, Register through 5 

Ted contains three 16 bit decrementing interval timers, each partitioned 
into 2, 8 bit registers. To initiate a new count value, loading the low 
Byte inhibits counting until the high Byte is loaded. The timers 
decrement at a 894 KHz rate for NTSC television systems, 884 KHZ for PAL 
systems. Each counter generates an interrupt upon decrementing to 0. The 
sequence for writing to the timers should be: 

Disable all interrupts 

Write low Byte 

Write high Byte 

Enable desired interrupts 

Care should be taken that long time intervals, more than 125u seconds, do 
not occur between writing the low and then the high Bytes. 

Timer 1 is a sequence interval timer. Registers and 1 when written to 
initiate the reload value of the timer. When timer 1 is decremented to 0, 
the next count occurs from the reload value. Reading Registers and 1 
gives the current count valve. 

Timers 2 & 3 are free running counters. Upon decrementing to the timers 
roll over to FF and continue counting. Writing to timer 2 and 3 
registers loads directly into the active count. Reading these registers 
yields the current count . 

Register 6 

Bits 0-2 of this register determine the vertical scroll position. For a 
normal 25 row picture with no scroll these bits should be a ' 3' . Bit 3 is 
the 24/25 row select. A '0' in this both corresponds to 24 rows and a ' 1' 
yields 25 rows. For vertical scroll to occur, bit 3 should be cleared and 
bits 0-3 all set. Decrementing bits 0-2 moves character position up 
scrolling off the uppermost character row. Bit 4 is the blanking bit. 
Setting this bit to a ' 1' gives a normal picture. Setting it to a '0' 
blanks the screen and disables all fetches from occurring, allowing for the 
system clock to run at twice the frequency (1.788MHZ NTSC, 1.768MHZ for 
PAL) except for 5 refresh cycles per raster line. Bits 5 and 6 are 
display mode Bits. Setting Bit 5 to a '1' enables Bit mapped mode, while 
setting bit 6 enables extended color mode. Bit 7 is a bit used for I.e. 
testing and must remain a ' 0' . 

Register 7 

Bits 0-2 determine the horizontal scroll position. A '0' in these bits 
allows for no scroll. To institute scroll bit 3 of this register, the 
38/40 column bit, should be set to '0' . This displays 38 columns and 
scroll can occur cleanly. Incrementing the 3 LSB of this register pans 
the character positions to the right. 

Bit 4 is multicolor mode bit. Setting this bit to ' 1' enables multicolor. 
The freeze bit is bit 5. Setting freeze high stops TED from incrementing 
the horizontal position, the timers and the vertical position. The system 
is forced into single clock (894KHZ) and system refresh of dynamic rams. 
Bit 6 is PAL/. Setting this bit high forces NTSC mode, low corresponds to 
the PAL mode. Bit 7 is the reverse video off bit. Under normal condi- 

35/40 



tions, bit 7=0, there are 128 character locations. The reverse video 
character is implemented by setting the MSB of the video matrix pointer to 
a '1' . This enables the TED chip to invert the character data and thus 
reverse video. If an alternate character set of 256 locations is desired, 
this bit can be set high turning the reverse video feature off and 
allowing the the MSB of the video matrix to define the additional character 
locations . 

Register 8 

This register is the keyboard latch. Writing to Register 8 scans the 
keyboard lines and latches the appropriate data. Reading the register, 
reads the latched data. 

Register 9 

The interrupt register indicates any TED interrupt source. Possible 
interrupt sources are: 

Bit 1 raster interrupt -compares raster register to active count 

Bit 3 timer 1 interrupt -timer 1 has decremented to '0' 

Bit 4 timer 2 interrupt - " 2 " 

Bit 6 " 3 " " - " 3 " " " " " 

Bit 2 indicates a light pen interrupt. The TED computer does not have 
light pen. This bit is for future expansion. Bit 7 is the interrupt bit. 
It is the inversion of the interrupt pin. Writing a '1' to the interrupt 
register clears the individual interrupt bit. 

Register 10 

Register 10 is the interrupt mask register. The individual mask bit 
corresponds to each of the possible interrupt sources. Setting the bit 
high enables interrupts to occur. The LSB of this register is the MSB of 
the raster register. (see Register 11 description) 

Register 11 

In an NTSC television system. 262 raster lines are produced (0 to 261), 
312 for PAL (0-311) . To detect all possible raster lines a 9 bit register 
is needed. Register 11 contains the low order 8 bits of this raster 
register. Register 10 contains the MSB. The raster register is an 
interrupt source. The raster register value is compared to the current 
vertical line count. An interrupt is generated 8 cycles before the 
character window. For a 25 row display, the visible raster lines are from 
4 to 203. 

Register 12 

Register 12 contains the 2 MSB of the cursor position register. Bits 
and 1 correspond to the cursor bits 8 and 9. 

Register 14 

Register 14 contains the low byte of Voice 1 frequency base. All TED 
sound generators produce square waves. 

Register 15 

The low order eight bits of the frequency base for the second voice source 
are contained in this register. This voice is selectable for either white 
noise or another square wave generator. This selection is available in 
Register 17 . 

Register 16 

This registers contains the 2 MSB of Voice 2. 

Register 17 

has 4 bits of volume control ranging from = OFF to '8' being 

36/40 



loud. Also 3 voice selects are available. Voice 1 select, Voice 2 square 
wave select and Voice 2 white noise select. The MSB of this register is a 
bit used for testing. The sound reload bit will clear the sound toggle 
flops and initiate the reload value of each voice to initialize the active 
sound count during the appropriate voice incrementing time. This bit will also 
initiate the white noise random number generator to 'I's. 

Register 18 

This register contains the three bit bit map mode address base, the 
ROM/RAM bank bit, and the 2 bit MSB of voice 1 frequency base. The bit 
map base determines where in the memory map the bit map dot data can 
reside. Bits 3 through 5 correspond to BMBO to BMB2 . During TED dot 
fetches in the bit map mode, BMB2 will become A15, BMBl - A14, and BMBO- 
A13. The ROM/RAM bank bit, bit 2, will force TED dot and character 
fetches from either ROM or RAM. A '1' in this bit will force ROM 
execution a ' 0' will force RAM. 

Register 19 

This register contains the character base, force single clock bit, and the 
status bit. The force single clock bit, when set high, inhibits the PH 
out of TED from doubling frequency during horizontal blanking. The status 
bit is a read only bit indicating the state of the 2 phantom Registers 62 
and 63. If this bit is high it indicates that TED is operating for the 
ROM bank memory. This bit does not indicate where TED will fetch character 
or dot information is coming from. 

Register 20 

The 5 bit video matrix base, bits 3 through 7, comprise Register 20. The 
video matrix base determine the memory mapping of the video matrix 
pointers and the attribute data as shown: 



A15 


A14 


A13 


A12 


All 


VM4 


VM3 


VM2 


VMl 


VMO 



The attribute and video matrix fetches occur on the raster line preceding 
the character row (attribute) and the first raster line of the character 
row. During these fetches TED will DMA the processor and take complete 
control of the system bus for both halves of the clock cycle, for 40 
consecutive clock cycles. 

Register 21 

This register contains a three bit luminance code and a four bit color 
code for background Register 0. This allows for eitht separate luminance 
level for each 16 colors. 

Register 22 

contains the same data as Register 21 for background Register 1. 

Register 23 

Background Register 2 data is stored here. 

Register 24 

is comprised of luminance and color data for background Register 3. 

Register 25 

Luminance and color information for the exterior register (border) is 

stored in Register 25. 

Register 26 

The two MSB of the character position reload register are bits and 1 of 
this register. The character position reload increments by forty each 
character row completed. For example, during the first character row this 
register will contain ' 0' . Upon completion of the eighth raster line of 
the row, the character position bit map reload register will be updated to 40 

37/40 



Register 27 

The low byte of the character position reload register is located here. 

(See Register 26) . 

Register 28 

This register contains only 1 bit, the MSB of the vertical line register. 
The vertical line register contains the current raster line being 
displayed. For NTSC systems this register will count from to 261, for 
PAL, to 311. 

Register 29 

The low byte of the vertical line register is contained in Register 29. 

Register 30 

Register 30 is the horizontal position register. Register 30 contains the 
upper 8 bits of this nine bit register. The LSB increments at a rate too 
fast to be of any use in programming. Since the horizontal position 
register actually increments from to 455, Register 30 will contain 
values of to 228. Negative true data is to be written to this register 
while positive true data is read. 

Register 31 

This register contains the 4 bit blink rate register and the 3 bit 
vertical subaddress register. The blink rate register contains the 
current count of the blink rate times. This register is incremented once 
per screen. On overflow a 2HZ signal is generated initializing the cursor 
reverse video and any flashing characters. The vertical subaddress counts 
the eight raster line per character row. 

Register 62 and 63 

These registers do not physically exist on the TED chip. A write to these 
locations controls the TED system memory map. Any write to Register 62 
results in ROM being selected in memory locations $8000 (HEX) to $FFFF (HEX) 
excluding $FDOO (HEX) to $F3FF (HEX) for I/O space and TED space. The TED 
chip will generate the necessary chip selects and inhibit CAS until a 
write to Register 63 occurs. Upon this occurrence, the same locations 
$8000 (HEX) to $FFFF(HEX) excluding $FDOO(HEX) to $F3FF (HEX) are banked to 
RAM. CAS occurs when appropriate and chip selects are suspended. 

All TED registers, unless otherwise noted, are read/write. It should be 
noted that care should be taken when writing to Register 26 through 31. 
These are internally controlled registers. Writing to them can result in 
a flicker on the screen. 



PINOUT 



PIN # DESIGNATION 



1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 
14 



A2 

Al 

AO 

VDD 

CSO 

CSl 

R/W 

IRQ 

MUX 

RAS 

CAS 

Oout 

COLOR 
Oin 



SIGNAL 
DIRECTION 

input/output 



input 

output 

output 

input/output 

output 

output 



SIGNAL 
POLARITY 

+true 



5V 
-true 

n 

+true 
-true 



+true 



input 



DESCRIPTION 

address bit 2 
fi If -1 

" " 

power supply 

low ROM chip select 

high ROM chip select 

read/write 

interrupt 

address multiplex switch 

RAM row address strobe 

RAM column address strobe 

894.9KHZ CPU clock (NTSC) 

886.7KHZ CPU clock (PAL) 

chrominance 

14.31818MHZ single phase 



38/40 



15 
16 
17 
18 
19 
20 
21 
22 
23 

24 
25 
26 
27 
28 
29 
30 
31 
32 
33 
34 
35 
36 
37 
38 
39 
40 
41 
42 
43 
44 
45 
46 
47 
48 



KO 
Kl 
K2 
K3 
K4 
K5 
K6 
K7 
LUM 

VSS 

DBO 

DBl 

DB2 

DB3 

DB4 

DB5 

DB6 

DB7 

SND 

BA 

AEC 

A15 

A14 

A13 

A12 

All 

AlO 

A9 

A8 

A7 

A6 

A5 

A4 

A3 



input/int pullup 



output 

input 
input/output 



output 
output 

input/output 



input/output 





+/-10% (NTSC) 




17.734475MHZ single phase 




+/-10% (PAL) 


lup " 


keyboard latch 




1 




2 




3 




4 




5 




6 




7 




composite sync and 




luminance 


OV 


power supply 


+true 


data bit 


IT 


11 11 -| 


II 


11 11 n 


II 


11 11 o 


II 


11 11 ^ 


II 


" 5 


II 


" 6 


II 


n 11 n 


+true 


sound 


+true 


bus available 


n 


tri-state control 


II 


address bit 15 


II 


"14 


II 


"13 


II 


" 12 


+true 


address bit 11 


n 


"10 


II 


9 


II 


8 


II 


7 


II 


6 


II 


5 


II 


4 


II 


3 



PIN FUNCTIONS 

ADDRESS BUS pins 1 thru 3 and 36 thru 48 

The 16 bit address bus is bidirectional. As an input, the microprocessor can 
access any of the 34 TED control registers. In the output mode TED uses the 
addresses to fetch Video Matrix Pointers, Attribute Pointers or character cell 
information. For microprocessor interface TED resides in locations FF00-FF3F 
in memory. 

DATA BUS pins 25 thru 36 

The 8 bit data bus is also bidirectional. The data bus activity can be 
separated into 2 categories: microprocessor interface and video data 
interface during the above mentioned fetches. 

KEYBOARD LATCH pins 15 thru 22 

The 8 bit keyboard latch is used as the keyboard interface. Upon an 
instruction by the microprocessor to write to the keyboard latch, the 
information on the keyboard pins is latched by TED and stored until it is 
retrieved by the microprocessor on a read keyboard instruction. The keyboard 
pins also provide the active pull up on the keyboard matrix lines. These pull 
ups source a minimum 600u amps and maximum 900m Amps current. The trip point 
of the keyboard latch is 2.0 Volts. 

Two of the keyboard pins also provide testing functions. When these pins are 
externally driven to 10 volts, they provide specific testing features. KO 
generates a system freeze function, stoping the horizontal counter, thus 
freezing the position, and sets all horizontal flip-flops to force TED into 
the dynamic RAM refresh period and single clock. All flip-flops are then 
released to allow their manipulation by the horizontal register. Kl forces 



39/40 



the internal clock division into the NTSC mode. 

CHIP SELECTS pins 5 and 6 

Ted generates ROM chip selects based on address decoding. CSO is active 
during the memory block of 8000-BFFF (HEX) . CSl corresponds to COOO-FFFF 
(HEX) in memory. The ROM area of memory can be banked out to overlay RAM, see 
the descriptions of Registers 3E and 3F (HEX) . 

DYNAMIC RAM CONTROL pins 9 thru 11 

TED generates RAS and CAS for dynamic RAM access. The signal MUX is also 

generated to externally multiplex the RAM row and column addresses. 

READ/WRITE pin 7 

R/W is an input to TED to distinguish the type of operation to be performed. 
TED will actively pull up the system read line during all TED fetches. The 
read signal is qualified with MUX. The pon is an open source output. 

INTERRUPT pin 8 

The interrupt pin is an open drain output. TED contains four interrupt 

sources: 3 internal timers and the raster comparator. 

PHI OUT pin 12 

For increased processor throughput, TED doubles the frequency of the system 
clock during horizontal and vertical blanking. The actual single clock 
boundaries are: 

1) raster lines 0-204 and horizontal positions 400-344 

2) horizontal positions 304-344 

PHI IN pin 14 

For use in NTSC television systems, TED requires a 14.31818 MHZ single phase 
clock input. For PAL systems, the input clock must be 17.734475MHZ single 
phase . 

COMPOSITE COLOR pin 13 

The color output contains all chrominance information, including the color 
reference burst signal and the color of all display data. The color output is 
open source and should be terminated with IK ohms to ground. 

COMPOSIT SYNC AND LUMINANCE pin 23 

The luminance output contains all video synchronization as well as luminance 
information of the video display. This pin is open drain, requiring an 
external pullup. 

SOUND pin 33 

This pin provides the output of the 2 tone generators. The output must be 
integrated through an RC network and then buffered to drive an external 
speaker . 

BUS AVAILABLE pin 34 

Bus Available indicated the state of TED with respect to video memory fetches. 
BA will go low during phase 1, 3 single clock cycles before TED performs any 
memory access and will remain low for the entire fetch. 

ADDRESS ENABLE CONTROL pin 35 

During double clock mode, AEC is always high allowing the 6510 complete 
control of the system buses. For single clock time periods, when BA has not 
gone low, AEC will toggle with 02out. This allows TED PHil, time to complete 
its memory accesses of video dot information while the 6510 performs during 
Phi2 . When TED needs both halves of the cycle to perform it customary Phil 
dot fetches and Phi2 attribute and pointer fetches, BA will go low. On the 
fourth Phil out, AEC will remain low until the end of the Phi2 video fetch. 



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