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HEWLETT-PACKARD

JOURNAL

April 1992

^eM

HEWLETT
PACKARD

H E W L E TT-PA C K A R D

JOURNAL

AprM 1902 Volume 43 • Nunibfir2

Articles

r\ VXIbus: A Standard for Test and Measurtment System Architectural by LawrBncB A. Dasjardin

Q The HP VXIbus Mainframes

I < VXIbus Terminology

I K The VXIbus From an Instrument Designer's PerspectivCp by Steven J. Narciso and Gregory A. Hill

/[] Examples of Message-Based VXIbus Instruments

/ / SmalL Law-Cost Mainframe with a Register-Based Interface

J A Design of Mainframe Firmware in an Open Architecture Environment, by Paul B. Worrell

y M Real-Time Multitasking of Instruments in the VXIbus Command Modules, by Christopher P. Kelly

*s K VXIbus Programming \nC,by Lee Atchison

A J Achieving High Throughput with Register-Based Dense Matrix Relay Modules i by Sam S, Tsai
and James B. Durr

Mass Interconnect for VXIbus Systems^ hy Calvin L Erlcksan

Km A Manufacturing-Oriented Digital Stimulus/Response Test Instrument by David R Kjosness
r\ M D igital Test Development Softwa re for a VXIbus Tester, by Kenneth A. Ward

The VXIbus in a Manufacturing Test Environment by Larry L Carlson and Wayne H. Willis

EclftDT, RiEhani F Dolan • A^sociBte Editcjf. CIrafIs L. Leatti • Putfiration ftBdwrt'ni^ Majiager. Susars E. WrigM
CiHfiwIfitt-PacljBrti Company J 932 F^irrtBiJ in.U:SA

2 April 1 992 Hewlett-Packard Journal

©Copr. 1949-1998 Hewlett-Packard Co.

Q 1 The Peak Power Analyzer, a New Microwave Tool, by Dietsr Scherer, WMam £ Strassen
James D. McVey, and Wayne M. Kelly

\\lX Multilayer Shiefding Proteats Microvolt Signals in High-Interference Environment

y n OaAs Technology in Sensor and Baseband Design, by Mhhael C Fischer, MichaelJ.

Schoessow, and Reter long

M ZL H armo n i c Errors and Ave r a g e ve rsu s Pea k D etecti on

Mq Automitic Calibration for Easy and Accurate Power Measurements, by David L Barnard, Henry
Biack, and James A. Thafmann

y M Testing the Peak Power Analyzer Firmware

J fj J An Advanced B-Hz-to- 500-MHz Network Analyser witfi High Speed, Accuracy, and Dynamic
Range, by Koichi Yanagawa

1 [J A High-Performance Measurement Coprocessor for Personal Computers, by Mike Moore and
Eric N Gulferud

11/ Measurement Coprocessor ASIC

1 1 ZL Measurement Coprocassor History

Departments

4 In this Issue

5 Cover

S What's Ahead

77 Authors

Ttie Hewlett Psckafd Joumisl isptiblishtd bimonthly? fry rtie Hewfett-Pacfesfd CoffipinyiD recognize technical contribuTions marfe by Hewlatt Packar^J

(HP] persam^\. Wtiile rhe infermstiQn: found m [Jiis putiNcanon is belf&ved tD be accurate^ l*ig Hewlett-PackBfd Campany disclaims all iflfarrgnttes of
mercJiBntabintv and fitness for a particular purpose and bH obliigatiDna and Jiahltes for dflfnagas, siduding bnJt not Nfnted to ^ndi^Ba, special, or cnnse-
quentiat damageSr atforng-y"* and experts faes, ancf court costs, arising out of ar in cnnnaeticir* witfi tbis publication

Subscripliong- The Hewiett-Packard JournaJ is distributed free oJ cfiarge to HP reseafch. tfesign and manufacturmg engirTeermg personn-el, as well as to
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Submissiong. Although articles in the Hewvtett- Packard Jnumaf are primarily authored by HP empfovees, articfes from non-HP authors dealing vvith HP-
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before submitting such articJas. Also, the Hewlett-Packard Journal encourages tec hmcaj discussions o[the topics presented in recent articles and may
publish latters ojtpacleii to be otinrefest to readers. Latters should be brief, and are subject to aditfng by HP.

CopyrigfM io 1392 Hewfett-Packartf Company. Afl rifllits reserved. Permisston to copv wittioulfee all or part of l+iis publication is hereby gramad provided
that H Iha copies are not made, used, displayed, or di^stributed for commercial advantage, 2] the Hewlett-Packard Company copyright notice end the title
of ttte publscatton and date appaar on the copies; and 3} a noiice stating that the copying is by permission ol the Hewlett-Packard Company.

Please actdress mquififis. submissions, and requests to. Editor. Hewlett -Packard Journal 3200 Hilluiew Avenue, Palo Aho, CA^4304 U.S.A.

April 1992 Hewlett-Packard Jountd 3

)Copr. 1949-1998 Hewlett-Packard Co.

In this Issue

VXlbus is a new interconnection standard for modular instruments. It defines an
architecture, communication protocols, and electromagnetic compatibility re-
quirements for a mainframe cardcage and for instrument modules that plug into
the mamframe and work together as a system. The architecture ts open to all
manufacturers, so users can mix instruments from different manufacturers m
^^■^rmivii ^^^ ^^^^ system. The history of the VXlbus begins in 1979, when Motorola
iSl^^m iM ■ I Semiconductor Products Corporation published a description of what came to
be known as the VMEbus. Three years later, the International Electrotechnical
Commission proposed that it become an international standard. In 1987, under
pressure from both military and commercial customers for an open architecture
for modular instruments, a group of instrument manufacturers, including HR agreed to develop a modular
instrument standard based on the VMEbus. The VXlbus is the result. VX! stands for "VMEbus extensions
for instrumentation," The VXlbus doesn't replace the widely used HP -IB standard (IEEE 468, 1 EC 6251, In
fact, its very common for VXlbus systems to communicate with a computer or other controller over the
HP-IB, and for HP-IS instruments and controllers, VXlbus mainframes, and MMS mainframes |MMS is
another open modular architecture optimized for microwave applications! to coexist in the same measure-
ment system. HP VXlbus products include mainframes, existing HP instruments redesigned to fit on VXlbus
cards, and new instruments designed specifically for the VXlbus. The article on page 6 describes the VXl-
bus standard and gives several examples of VXlbus measurement systems. Details of HP's implementation
are covered in the articles on pages 15, 24, and 29, which deal with internal HP standards that supplement
the VXlbus standard, the design of HP's mainframe firmware, and the operating system for HP VXlbus
command modules, A library of C functions that helps test programmers create VXlbus applications using
the high-level C language is the subject of the article on page 35. HP VXlbus switching and interconnect
products are described in the articles on pages 41 and 52, and the hardware and software designs of a
VXlbus functional tester for digital electronic assemblies are presented on pages 59 and 69. HP's own use
of VXlbus instrumentation for manufacturing test is discussed in the article on page 75.

In radar, telemetry, navigation, and communications, microwave signals are typically pulsed rather ttian
continuous. Engineers designing and testing such systems need to make many measurements on the en-
velope of the microwave pulses, such ss peak and average power, rise and fall times, pulse width and
repetition rate, overshoot, and others. Until now, the best way to make these measurements was a micro-
wave detector connected to an oscilloscope. Like many homemade solutions, this arrangement is difficult
to calibrate for accurate measurements. Among the reasons are the noniinearity and temperature sensi-
tivity of the diode detector, the frequency response of the detector output, mismatch error, and harmonics.
This solution also suffers from slow response and limited oscilloscope sensitivity. Overcoming these prob-
lems was the motivation for the development of a new type of microwave instrument, the HP 8990A peak
power analyzer Taking a fresh look at the challenges of diode detection, the designers created special
power sensors using gallium arsenide detector diodes. In the analyzer design, they incorporated switched
amplification and processing of the pulse envelope signals, leveraged modern digital oscilloscope
technology, and used microprocessor power to implement a new calibration approach that makes calibra-
tion mostly autometic. The article on page 81 describes the problems of microwave pulsed power mea-
surements and tells how the design of the peak power analyzer addresses them. The contributions of gal-
lium arsenide technology to the sensor and analyzer designs are discussed in the article on page 90. The
calibration approach and firmware design are covered in the article on page 95.

April 1S92 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

A more familiar instrument, the network anatyier, measures the response of some device to a stimulus
signal and displays the response as a function of the frequency of the input signal. The device under test
might be a filter, a resonator such as a quartz crystal, a circuit an integrated function block, or a complex
discrete device. The HP 8751A network analyzer is designed to deliver state-of-the-art performance in its
frequency range of 5 hertz to 500 megahertz, both for testing such devices in production and for evaluating
them in the development laboratory. Its three-processor design achieves a very fast measurement speed
of 400 microseconds per point, which not only improves production throughput but also gives the analyzer
a real-time response that displays the results of adjustments as they are made. The HP 8751 As accuracy,
resolution, sensitivity, and dynamic range match or exceed those of other comparable HP network analyz-
ers. It has the powerful built-in analysis functions that users have come to expect, and it offers some new
capabilities, such as simulating impedance matching networks for the device under test, making simulta-
neous high-speed and high-accuracy measurements in separate frequency ranges, and simultaneously
displaying the three key parameters for filter applications The design of this analyzer is described in the
article on page 101.

In the early 1980s, when the HP 9000 Series 200 computer was HP's primary instrument controller, HP BA-
SIC became a widely used instrument control programming language. A few years later, many HP custom-
ers were using personal computers for instrument control but wanted to continue to program in HP BASIC,
and HP responded by offering a plug-in BASIC language processor card for the PC. The third generation of
this card, the HP 82324A measurement coprocessor, is described in the article on page 110. Its contribu-
tions are higher calculation speed, faster HP-IB input/output performance, and data transfer by direct
memory access for better overall system performance. The card also provides more efficient communica-
tion between its own processor and the PC's and makes it possible to develop complex applications in-
volving up to three measurement coprocessors interacting with PC applications such as a spreadsheet

R.RDolan
Editor

Cover

A view of a VXIbus module and the backplane of a VXIbus mainframe. Because the backplane is the embodi-
ment of an industry standard, modules from different manufacturers can communicate over it. Restrictions on
the VXIbus mainframe and modules ensure electromagnetic compatibility.

What's Ahead

The June issue will feature recent developments in system software for HP 9000 PA- RISC workstations, includ-
ing the latest optimizing compilers, shared libraries, and the HP-UX operating system for the recently
introduced, very fast HP 9000 Series 700 workstations. There will also be three research reports that were pre-
sented at the 1991 HP Technical Women's Conference. One is on a parallel computing architecture for ray-
traced image generation, one is on the evaluation of printed image quality using spatial frequency methods,
and one is on integration of an electronic dictionary into a natural language processing system.

April 1^2 Hewlett-Packard JoumaJ 5

)Copr. 1949-1998 Hewlett-Packard Co.

VXIbus: A Standard for Test and
Measurement System Architecture

The VXIbus standard defines an open architecture that allows
instrumentation and processors from various manufacturers to operate
together within a single chassis or mainframe.

by Lawrence A. DesJardin

In July 1987, Hewlett-Packard and four other msyor
electronic instrument manufacturers jointly anno unc eel
their support for a new instrumentation standard called
VXIbus J An abbreviation for l^lEbus Extensions for
Instrumentation J \^XIbus is an open arcliitecture that
allows Lnstnmientation and processor modules from
various manufacturers to operate together within a single
chassis or mainframe. The VXIbus Consortium was
formed shortly thereafter to develop and mam tain the
VXIbus specification, the primary technical document that
describes the mechanical, electrical, and communication
interface requirements for VXIbus products. Since that
time, more than 50 manufacturers have announced
hundreds of \^Ibus products encompassing mainframes,
instrument modules, computer modules, interfaces,
fixturing, and software. VXIbus appUcations range from
research of high-encrgj' physics to computer-aided test
systems for production test of electronic assemblies, and
VXIbus is rapidly becoming a mainstream test and mea-
surement architecture. This article presents an overview
of the \QQbus standard, and describes how the \^bus
architectural features are used at a system level to create
a VXIbus measurement system.

What is VXIbus?

The \'Xlbus is based on the VMEbus computer backplane
standard. While VMEbus has two module sizes. A and B,
VXIbus offers four sizes by adding C and D sizes (see
Fig. 1). The C and D-size modules are wider, allowing two
printed circuit boards and envelopuxg shields to be used.
Mainframes also come in these four sizes and include
methods for accepting smaller modules as w^ell (see "The
IIP \'XIbus Mainframes/' on page 9). To keep the archi-
tectm-e flexible for a wide range of applications, the
VXIbus does not speciiy the amount of power or cooling
a given mainframe must supply, but it does specify the
w^ay in which module and mainframe power requirements
and capabihties must be documented. This aEows a user
to select modules and mainframes for a given application,
knowing a priori that a particular product set will w^ork
together. VXIbus defines three backplane connectors,
labeled Pi, P2, and P3. Only the PI connector is required
of all modules and mainframes; the others are optional.
PI contains the required VMEbus data transfer bus
capability; and can address the A 16 (64K-bjte) and A24
(i6M-byte) address spaces using S-bil or 16-bit data
transfers- The VXIbus autocorifiguration registers and the

Slandard
VME

AddJttonal

Module
Sizes

IDxIGcin
(3.SxG.3in|

23^x16 cm
19.2x6.3 ml

23.3x34 cm

3G.7 X 34 cm
|14J X 13.4 in)

Stol
Spacing

2 cm
{O.B in)

2 cm
{0.8 in!

3 cm
(1.2 in|

3 cm
(1.2 ml

VXI Additions

Mechanical:
Module Sizes
Cooling

Electrical:
Power
Triggering
Clocks

EMC:

Conducted
Radiated

Communication;
Auto cofifig oral ion
Register- Based
Mess age -Based

Fig, 1, The V'XIbus standard (VMEbus Extensions for Instrumenta-
tion) includes the two original V^iEbus module si^es, A and B^ plus
two new moduies, C and D. Smaller modules can be inserted into
mainframes designed for the larger sizes.

protocol registers for message-based devices are located
in the A16 address space, allowing all required commu-
mcation to occur using only PL The V2 connector,
optional on B, C, and D sizes, extends the data transfer
bus to include 32-bit transfers and the A32 (4G-byte)
address space^ as in the VMEbus standard. However,
while VMEbus left 64 pins of P2 undefined, VXIbus
de&nes these remaining pius to be a set of clocks,
identification lines, power supplies, and trigger buses." It
also defines a local bus that connects adjacent slots using
these pins. The optional P3 is only found on D-size
modules, and is fully defined as additional clocks, power,
trigger buses and local bus lines.

Electromagnetic compatibility is guaranteed in the \OQbus
architecture by stringent requirements on how much any
module can radiate into the adjacent modules and how
much ac and RF current it creates on each of the power
buses. Likewise, each n\odule is required to meet its
measuremenl specifications when subjected to radiation
from other modules within the specified VXIbus Umits, or
powered within a specified voltage ripple range. If the
sum of the dynamic module currents, which must be
documented for each module \n a data sheet, is less than
the specified mainframe dynamic current capacity, then

6 April 1992 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Sip«r«ie Unit
or Embeitdfld

Host Comrollet

HP'IB, LAIi Of Oifvct GMMCtion

McHtufat
Measurement

IMMSI

Swrtthed Signel:

T Separate Unit
QfEinbedded
-^ftxturjng

OflviCflUn^BfTHt

Fig. 2. The measurement system architecture for a t^^ical com-
puter aided test system consistmg of HP-IB, VXJbus, and MMS

instruments.

the system is guaranteed to be compatible. The main-
fcame is required to limit power supply voltage ripple on
any of its power buses to be within the specified ranges,
even when all modules are producing their maximum ac
and RF currents. This combination of requirements
ensures electromagnetic compatibility.

Finally, VXlbus adds autoconfiguration and communica-
tion protocols. All devices must have a set of registers
available for control and status to perform self-test and
initialization functions. Register-based devices have
additional registers that access the device's specific
functions. Message-based devices communicate using the
VXlbus word-serial protocol (described later) to transfer
ASCII commands and data between modules. Some
devices include both modes of communication ^ using
SCPl-based"^ ASCII commands for easy development and
direct register access for higher speed. SCPT, register-
based instruments, and message-based instruments are
described in detail in the article on page IB.

This range of VXlbus functions provides a very scalable
architecture in terms of size, power, performance, and
cost for addressing a wide range of applications. The
VXlbus standard is also upward compatible, that is,
products that are designed to work with less mainframe
resources in terms of si^e, connectors, or power will also
work in mainframes that deliver more resources. This
gives the user a breadth of products to choose from,
making it possible to select only the performance needed
for the present applications while preserving an upgrade
path if future applications require more performance.

Measurement System Architectures
One of the most common applications of the VXlbus is
testing an electronic product such as a printed circuit
board. Fig. 2 shows the measurement system architecture

* SCPI means Standafd Command? far Progrscnmable Instrurr^ts.

of a typical functional test s>^tem. It consists of a com-
puter, various mstruments, and a switciiing sj'stem con-
nected to the de\ice under test (DLH'). The computer can
be any computer ^vith an HP-IB or other intexface, and is
commonly called the host controller The instruments can
be any combination of three formats: HP-^IB, MMS, and
VXlbus. HP'EB instruments communicate through the
HP-IB (rEEE-48S.L lEC 625) interface de^^eloped by
Hewlett-Packard in the early 1970s. These are often bench
instniments that supply an HP-IB interface port for
conmnand and control, and can be rack-mounted into a
standard EIA rack cabinet. Many products, such as power
supplies, will continue to be controOed priniarily via the
HP-IB. MMS, the Modular Measurement System, is anoth-
er open architecture modular instrument system devel-
oped during the same time as VXlbus. Also maintained by
a multimanufacturer consortium, MMS is a modular
architecture optimized for RF and microwave applica-
tions, and works well in unison with HF-IB and VXlbus
instrumentation and control

The controller, though showTi logically as a separate unit
in Fig. 2^ may actually be embedded in the VXlbus
mainframe or m one of the o titer instrument architec-
tures, allowing a direct connection between the instru-
ments and the controller. Likewise, the switching unit
may exist as an HP-IB m^it or a group of VlQbus or MMS
modules. Typically, HP-IB cables are used to interconnect
the various instruments and mainframes, though some
applications have used RS'232, LANs, and MXIbus**
cables.

Fig. 3 shows a typical VXlbus system that is controlled by
an external HP-IB controller Each \'XIbus instrument or
instmment set (e.g., a set of switches) acts as an inde-
pendent HP'IB instrument w^hen controlled over an
IEEE-43B.l'to-\^bus interface device installed as a
module within the \^bus mainframe. The \^bus specifi-
cation refers to this interface functionality as a 488-VXl'
bus interface device. In Fig. -J this functionality is in-
cluded on the command module. The command module
owns one primary HP-IB device address, and accesses
each VXlbus instiiunent or grotip of instruments through
a unique EIP-IB secondary address. HP-IB cables are used
to connect to other extenial instnmients and mainfrajixes,
Signals to the OUT are routed from the various instru-
ments through electronic switches to an interface connec-
tor assembly (ICA) mounted on the rack cabinet, TVpJcal-
ly, for each product to be tested by this system there will
be a removable mating connector assembly that connects
the interface connector assembly and the device under
test. This fixture assembly is often called an interface test
adapter (ITA) and is unique for each elecrlronic product
type tested on the particular lesier. This allows one tester
to test different products by changing only the intercon-
nect test adapter and the softwaie program that controls
the instnjments. iCAs and ITAs are described in detail in
the article on page 52,

* MXIbiJS IE a flexible intmconftect tabfe tike M HP-iB, but represents the W(fbiisdata
transfer bus an its conductors witfi only a smati lass of performance MXIbus f^as also
been used as a high-speed link ffom VXlbus to an exiemal computer and an e^tendar
link between VXlbus and the instrumEnt msjntraines,

April 1392 Hewleci-F^kanl Jouma] 7

)Copr. 1949-1998 Hewlett-Packard Co.

Host CDntroller
Typically HP-UX.
DOS. or HP BASIC

Other VX I Frames

MMS Frames

Power Supplies

DttterHPIB

HF4B

HP'I8
SCFl Commands

Signals

10 or from

DUT

tnterfac« ConiiBotitr Assambl^
UCA)

Intersctivft Tast Genarator
Soft Front PaneJs with Tast Exacutiva

Interf nee Test Adapter

inrAl

Fig, 3, A block diagram of a typi-
cal VXIbus test system using the
HP -IB as the interconnection from
the controller.

The test system in Fig. 3 is controlled by test executive
software running on the external controller Often, the
developer will use the HP interactive test generator or a
similar software package that displays soft front panels
for faceless VIGIdus instnmients auc! the other HP-IB and
MMS instroments. This software caix be used to generate
the ASCIJ commands for the instniments atitoniatically; or
the user may develop these I/O commands directly. The
mdustry-st^ndard SCPl language provides commands that
a developer can use to control all instruments, regardless
of the particular instnmient architecture. In this example
all \'XIbus, MMSt and HP-IB instruments are programmed
exactly as HP-IB jjist rumen ts.

Fig. 4 shows an example of a system in which the
controller is a VXIbus module embedded within the
VXIbus mainframe. Since this configuration has an em-
bedded controller that allows direct access to the VXIbus
instrument modules, higher speeds are attainable %ia
direct VXIbus communication. Also, because the control-
ler is embedded, rack space is reduced. The register
interfaces to these instmments can be directly mapped
into the memory space of the controller^ allowing ex-
tremely high-speed command and control. Often, an
embedded controller will be operated in a diskless
environment by interfacing through a LAN to a server. As
in P'ig. ri, a developer may choose to integrate \TVIEbus

IcQnTinued on page 10J

HP Et480

Embedded

HP-UX
Control lar

"^^l

■

brzi'n

! *■

^^Hl

^^1

^Hnl

fi *<

■a

1 s

T i*

<Sl

Ik.

5 ^

Digital -t
Set 1

IntaractivB Test Generalcr
Soft Front Panals with Tast Exectitiv

SCPl Commands

' Oltiar VXI Frames

MMS Frames

Pewar Supplias

HP-IB

Other HP-IB
Instruments

Int&rface Connector Assembly

tiCAJ

Intadacre Test Ada|Vti
(ITAJ

Fig. 4. A VXIbus siystem controlled
hv an embedded HP-UX controller.

8 April 1092 Hewiett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

The HP VXIbus Mainframes

Ttie HP 75QO0 lacrniy of VXfbos prodiicis delf^rs a scatabie offering af instnj-
mems. swTtete, anrf efnbedded cDrrtmiier^ The HP 75OT Series B mairtfnme |HP
€T3O0l provides ihree A-srze and nirie B-stie [two imemal) sloTs. and a two-lFi®
display and ijiyboanJ {see Fig 1 1 The mainframe can aim be configured tq incliMte
embedded harti and flembii disk drrves Command module functionality (HF IB and
resourcemanagar} is pefmanerrliv embedded in itie mainframe along with two

internal slots "Rie command module m ilte HP £1300 mamframe can be upgraded
to an embedded contmllef with tbe IBAS3C (Instrument BASIC! option Sefies B
products deliver a very sist-effectrve mjIuIioo for cases m whicb rrHideraie peftor-
manca is r>eeded

(tontimed orr page TOt

Fig. t. HP 7500D Serjes B mamframB {HPISOO
[a) FrpnE view, fbl Rear view stinwmg the
fDcaiian o( the Asfze and Bsj/e slats.

Fig, Z HP 75000 Series C mamlrame

(HP E 1 4(30) and some of the C-sm products

April 1 9^2 HewleU - 1 'at: k jm I Jr mniaJ 9

)Copr. 1949-1998 Hewlett-Packard Co.

[continued fiom page 9^

The HP El 400 Series C mainframe (Fig. 2] provides a 13-slDt C-si^e mainframe- an
embedded HP-UX' workstation controller, a single-sJot command moduJe. and
numerous high-performance mstruments and swftches C-si^e modules are typical-
ly constructed within shrelded enclosures and mount vertically wirhm the main-
frame. Module adapters are available that allow convenient insertion of A-size and
B-size modules mto the Dsize mainframe. Series C products offer the highest-per-
formance capabLlJties. yet can be intermixed wnti Series B products to attain the
most economical system solution

(cofttfoued from pays B)

modules into the system or develop custom TO J bus
modules to create unique functionality that cannot be
purchased fis a slimdard producl- If high-speed register
access lo additional VXibus mainframes is desiied,
MXlljus cables can be used to interconnect to adchtional
mainframes direcUy.

VXIbus Electrical Architecture

h is importanl to understand the basic internal VXIbus
stmctures so that a system can be configured to take
advantage of the VXIbus architecture. The \^bus is a
backplane bus composed of the VMEbus data transfer bus
m\d various [Kjwen trigj^er, and clocking lines atided by
the VXIbus specification. For die rnosl part, these lines
are implemented as standard paraJlel ijuses^ that is,
conductors connect the same pin of each connector in
every slot. For example, pin la of PI in slot is con-
nected to the same pin in slot 1, slot 2. and so on. TXv'o
otJier topological structures exist in the \^bus: local
buses and star buses (see Fig, 5a). The widely-used
\TVlEbus paT'Jillel bus structure has a memory -mapped
architeclun^ Ukal eim support data transfer rates of up to
40 Mbytes/s between any two ntodules. It also includes
the Interrupt bus slrutjrture atid various system control
and bus arbitration functions. The VMKbus data transfer
bus can function u.sing only the requited PI connector,
although die P2 connector is required to use any of the
32-bit modes. VXIbus defines trigger lines on the P2 and
P3 connectors that have parallel connections to all
instaHed modules. This allows tight synchronization of
instmnients without any external cabling.

The second bus topology, known as the local bus^ only
connects ac|jacent slots of the backplane. On a B-size or
C-si2e system, 12 very short lines connect from the right
row of the P2 connector to the left row of the P2 con-
nector in the at^jacenl slot. Thus, except for the slots on
the end of the backplane, all slots have 12 local bus lines
coming in on the left and going out on the right (see Fig.
5b). These bus Unes can be used by manufacturers to
connect signals or other private ct:jmnmnication paths in
one set of ruodules mthout interfering with or degrading
the communications occiuring in another set. Thus, the
local bus can supply extremely tight coupling between
modules w^here required, and complete Isolation otber-
wise. Since the \rXIbus allows a wide range of ar^alog and
digital signals on the local bus, there was a potential for
electrical damage caused by accidentally plugging tw^o
incompatible modules into adjacent slots. This was soh^ed
in the VXIbus specification by requiring a unique local
bus mechanical keying scheme on a module's faceplate

{^\

^2v son

son

'Hr

Signals

Fig. 5. (a) The paralkl. local, and star bus structures used on the
\'XnjUK backplane, (b) A detailed look at the signals a vailahle on
the P2 connector.

that prevents modules with Incompatible local bus signal
types from being inserted next 1o each other

The third bus topologj^ used in VXIbus is known as a star
bus. Here, signals are routed from one slot in the back-
plane to each of the other slots, A star bus structure is
used on the VXIbus P2 connector to route a 10-MHz
clock signal knowTi as CLKlO from the leftmost slot to all
of tlie other slots on the backplaJie (see Fig. 5b). The
CtKlO signal is independently buffered to each slot on the
backplane, Tlius I lie loading characteristics of any sloJ
have a negligible effect on the signal received a! each of
the other slots, allowing a very stable reference frequency
wiUi minimal phase jitter to be distributed to all modules.
A derivative of the star bus structure is also used on the
VXIbus P2 connector by routing a total of twehe different
signals from the leftmost slot to each of the twelve slots
to its right, with one signal going to each slot. These are
known as MDDID (module identification) signals and allow

1 April 19S3 Hewletl-PackanJ JouitmiI

)Copr. 1949-1998 Hewlett-Packard Co.

the system to detect the absence or presence of a module
m each slot, e\'en if ii is a failed or non operating module.
MODIQ lines are also used to match each \^XIbus logical
device and address with its slot number. In the \'XIbiis,
the leftmost slot is al^^ys known as slot 0. The modules
that receive the CLKIO and MOD 10 signals are sequentially
numbered starting at slot I to the immediate right of sloi
0, and may number up to slot 12, All slots with common
CLKia and MQDIO signals, and the slot module they
connect to, are coilectlveiy known as a \^Kfbus subsys-
tem.

The above description iiighlights the uniqueness of slot
and the module inserted into it. Is slot the only unique
slot? Not necessarily. To support the data transfer bus.
VMEbus requires that the leftmost module contain a
sy^stem arbiter, generate the 16-MHz clock SYSCLK and
drive the intetrtipt acknowledge chain. This functJonaliiy
is known as the \^lEbus system controller, and exists on
the PI connector Since a \^bus subsystem topically
starts from the leftmost slot also, slot and \'MEbus
system controller ftmctionality are almost always conv
bined on the same module and refened to collectively as
slot 0. Technically speaking, this is not always the case.
Since F2 and P3 arc optional connectors, and only PI is
required by VXIbus, a system may be defined that has a
\'TVIEbus system controller but not slot D. This may be
implemented in low-cost systems such as the HP E1300A
B"Size VXIbus mainframe. In an imconunon but allowed
architecture, a \^XIbus subsystem begins with slot to
the right of the VMEbus system controller, allowing a few
slots to be pure VMEbus slots to the left of .slot 0. Here,
slot and the VMEbus system controller would be imique
modules. However^ in most cases, slot functions and
VMEbus system controller functions are combined m the
leftmost slot.

VXIbus Logical Architecture

The VXIbus is based extensively on the VMEbus memory
map. VMEbus defines 16-bit, 24-bit, and 32-blt address
spaces that exist independently and simultaneoijsly. Tlvey
contain 64K bytes. 16M bytes, and 4G bytes of address
space respectively. VMEbus also has 8-bit, 16-bit, and
32-bit wide accesses to these ntemor}^' spaces. Each
module presents a block of addresses that allows another
device to access that module's fimctionality. A VTVIEbus
master is a device that has control of the bus, and can
read from or write to any address. A slave is a device
that never has control of the bus, but has registers
located within lis address space that are accessed by one
or more bus rna^sters. There can be multiple bus masters
in a system but only one can control the bus at any time.
The bus arbiter on the \TVIEbus system controller module
decides which device is granted control of the bus.

In a VMEbus system, a user typically has to create a
memory map that shows the address blocks grajited to
each device so that one device's address space does not
overlap another's. Next the user notes the startuig ad-
djesses for each address block and (■onfigures jumt>ers on
each module to set it up. Finally, the user finds the
location and definition of any control and status registers
and writes a driver so that afler power is applied, one of
the bus masters can access tliese registers on each device

to check for proper system configuration, perform self-
test, and then mitJailze the systen^ After initialization the
user can proceed wiili the application.

In VXIbus, this is much simpler. TOIbus requires a stan-
dard definition of the control and status registers for all
devices. Furthermore, the locations of all control and
status registers are standardised To implement this, the
upper quarter (16K bjies) of the IS-bit address space is
reserved for this information. It is split into 2-56 blocks of
64 bytes apiece. The lowest el^t bytes of a block contain
the control and status information, including the manufac-
turer identification and model code. The 256 blocks are
numbered from to 255. Each block number represents
the logical address of a VXIbus device. Topically, a
\^XIbus de\ice has switches that allow a user to set the
logical address to a unique number although a totally
switchless configuration mode also exists. Thus, setting
the address of a \^XIbus module is ver>^ similar to settiJig
the address of an HP-IB de\1ce, and the user can remain
virtually unaware of how devices are actually using the
VXIbus address space. A de\ice is free to use the remain-
der of the 64-byte block for operational registers that
access the device's ftmcUons. The article on page 41
show^s how these 64-byte blocks are used for matrix relay
addiessing.

Of course, some device on the bus must still access each
of the control and status register locations to see if a
device is present, check the self-test residts, and perform
a proper system initialization. This functionality, typically
a software or finnware program, Ls called the msoun^e
mmiagen The resoiu'ce manager is defijiecl to be at
logical address 0, and is the only device allowed to
access the bus immediately after power-up and system
reset. It checks for the presence of a device at each
logical address and will synchronize the operation of ajiy
slot functions to identify the slot tiumber of each
device. If a device's i'unction requires more than the 64
bytes of address space given to it. iti the 16- bit address
space, the device will list how much additional address
space is needed in its configuration registers, and the
resource manager will assign the base address for this
memory by writing to another configiu^tion register. All
tliis is done automatically without interv^ention from the
user. Once the resource manager finishes its tasks, it tells
other bus masters that they may now^ request use of the
bus and operation catx begin.

VXIbus Communication Protocols

V'MEbus devices are typically controlled by accessing
register's in the module's address space. This allows very
high-speedt interactive control. However, HP-IB iiLstru-
ments are typically controlled by sending aiul receiving
ASCII commands and numbers. Because of the finite time
required by the instrument to interpret ASCII conmiat^ris
and translate between ASCII and binary numbers, this
mode of operation tends to be slower than direct register
access. However, the speed of the measurement may limit
system speed, so ASCII conmumications woukt not
present a speed bottleneck, but could deliver a significant
improvement in ease of use. This is particularly true if
the ASCII commands conform to industry standard SCPl
so that there is a single set of ASCn ctjnmiancls to

April 1 992 HewlenrPackorrJ .Jo iiri lal 1 1

)Copr. 1949-1998 Hewlett-Packard Co.

control instruments, and a single niess^e exchange'
prot-ocol to exchange data and status.

VXIbus supports both of the above conimunieatlon
methods. If a de\1re only supports register accesses, it is
known as a register-based devif:e. If n supports ASCII
communication using the V'XIbus-deJlnecl word-serial
protocol, it is called a message-based device. Message-
l>ased de\ices may also support direct register access for
cases in which increased speed is important.

Word -Serial Protocol

The word -serial protocol used by message-based V^KIbus
devices provides a standard way to send and receive
ASCII messages between devices of different manufactur-
ers. This is implemented by defming additional commu-
nication registers next to the configuration registei>» in
the l(>b!t address space aitd stajKlaidiiiing their operation.
Essentially, 16 bits can be sent at a time, with data
represented in the lower 8 bits, and additional control
information in the upper 8 bits.

Therfe is a one-to^me correspondence between any HP-IB
operation and its equivalent word-serial operation. Ttiis is
a key feature of tine VXIbus. Becanse of this eqnivalenr^e,
It is possible to build a device that translates from the
HP-IB at one end to \^lbus word-serial protocol at the
other without any knowledge of the function of the ASCII
commands toeing sent. This aliens s -a user to program
\OLlhus irisinirnents from any t (nniiuler that lias an MP-IB
interface as if they were HP-IB irtstniments. A translatitju
module used to translate between the two proto<*ols is
known as a 488-VXIbus interlace device. A typical metliod
of translating between HP-IB addresses (32 prin\aiy
addresses with 32 secondary addresses each) and VXIbus
logical addresses (256 total) is to use the HP-IB second-
aiy addressing feature. This can be done by assigning
each mainframe's 4S8-VXlbys interface device an MP-JB
primary address and each en^ bedded VXIbus insf fument. a
Ludque secondary addi'ess. The five most-significant bits
of the VXIbus logical address are used to deteiTiiine the
HP- IB secondiiry address. In fact, Jissuming the three
least -significant bits are already sel to aero, setting the
five most -signi tic ant bits can t>e exactly the sinne proce-
dure as setting the five address bits for an HP- IB itistni-
ment. Since the three 1 east-si gnificant bits are set to isero,
a single-module instrument always has a logical address
that is divisible by eight. For a single instrument com-
posed of several modules, the modules can be set to
consecutive logical addresses, but controlled from a single
secondary' HP-IB address. This allows vendors to tieliver
naturally modniar instnin^ents, such as swiiches or
scanning volinieters, that operate as a single instrument.
If a resource manager is included on the 488-VXIbus
interface module, it will be found at secondary address
zero since, by defmition, it must be set to logical address
^ro,

HP-IB translation works well for communicating with
message-based devices, but something else is needed for

regisler-based devices, A common method for communi-
cating wiUi register-based instruments using ASCD com-
mands is for a manufacturer to include the instrument's
AS(^n interpreter firmware on a 488-VXIbus hiterface
device. An instrument's interpretation firmware is often
referred to as its driver. At power-up, the HP- IB interface
device would recognize which modules are register-based
and which modules it has drivers for, and invoke the
driver whenever that instrument's equivalent HP-IB
secondary address is accessed. Using tills method, regis-
ter-based modules behave as message-based modules, and
they both appear as independent f IP-IB instruments when
accessed from a 488-\TCIbus device. If no fimiware driver
exists for the module, it can still be accessed by com-
majiding the resource manager to perform the proper
register reads and writes.

Since VXIbus is a multiple-master arc^hitecture, there must
be some method of determining which slaves belong to
which masters. For this reason, VXlbns has created a
commander-servant hierarctiy. A commander is a device
that controls other devices. Tlie devices it controls are
called its servants. A VXJbus device can only have one
commander, hut it can have any number of servants.
Since only bus masters can control the bus, a commander
must be a master, and slaves can only be servants. A
conmikmder can ^liso be a sei'van! to smother commander,
forming a hiertirchial command system. VXIbus has the
additional requirement that commanders must be mes-
sage-based devices. TI\is allows the resource manager to
eontlgure the commatider-servant hierarchy witli com-
manders from multiple vendors iLsing standard word-serial
conmiands>

The commander-servant hierarchy is determined by the
resource manager after power-up. Each commander or
potential conmiander has an attribute called its serv'ant
tirea. This is a number, which the user typically sets by a
switch, that determines how rtiany logical addresses a
de\ice may own as serv^ants. For instance j if a device is
at logical address 24, and has a servant area of three,
then it has exclusive control over devices at addressee 26,
26, and 27. If there are ot her conmianders at these
addresses, tlie commander at address 24 can control
those also, but not those conimandeiis' serv^ants. Tliis
allows hierarchial command stnictures.

This featiu'e can be used to make register-based devices
appear message-based by configuring a conunander to
peribnn the ASCII command translation and register
acce^ for a set of registei-based instruments. A user can
control the set of modules by commurucaLing with the
commander vising ASCII messages, while the commander
perfonns the register accesses required. If a particular
commander doesn't translate for all the modules in a
given system, and there is ar^other commander in the
system that translates for the remaining modules, both
commanders can be configured in the same system
without conflict by setting up the commander-servant
hieraix'hy correctly.

12 April 1992 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

VXIbus Tbrminology

The foHowinig deitnitfws should be heipful \n undefstanding ttie tefminology ysed
here and in other VXIbus s^tieies in this issue

Bind ing, Ihe pmc^s c^ assoc^ting a ftrniware function {like a VXIbus device
driver } with 3 paiticulaf pmce of hardware

addfffis and input and outpui buffers, and ttse atiility to share system resQurces
such as tfie human interface with other instruments Some rn^struments hafve op-
board inteliigence fmessage-&ased tnstrun^fits) and some requite supponfrof?! a
command modufe *o' me\hQmcB (register-tjasad instftimentsl

end Modub, This module eomams ms inteilrgerice Ipmcessor) that con-
trols register' based devices. The human interface, and flS'232 resoufces. In addi-
nm. thts module may contain m^m tie VXIbus stoi or (Jatacomm functionalitv

Consote. The human tntejlacs port that is used by the sysfem to report povAffif-on

and diagnostic information to the user

Datacomm. This is tJie port through which an eirternal hm (computer) can control

the mainframe. An example of thts tvpe of port is the HP-f8 connection, which is
used by the host to send commands to and read data from the instruments in the
mamframe.

Dewlce. A component of a ^/Xfhus system NonrraUy a device will consist of one
VXIbus module that occupies one slot. However, multipie-sJot devices and multi-
ple-device modules ere permitted. Some examples of ijevices are computers.
multimeters, switches, operator interfaces, and CQunters.

Driver, A firmware or software program that controls a device-
Host, This is typiceJIy a computer that contains the test system executive software

ar>d has an HP-iB connection to the test system However, the host can he an
embedded controller in the instrument mamframe {e.g.. the HP Et480A V/360A
embedded controller).

Human Interface. This is the path through which a user interacts with the main-
frame TIijs path can be implemented via different hardware interfaces such as the
front panel of the HP El 300 a-S!£e mainframe, or a terminal connected to the
mamframe via an RS'232 port.

Instrument An instrument is a collection of hardware and firmware functions that
are addressable by the host as a complete unit. An instrument has its own HP IB

HP IflstnHneet BASIC (IBASICK A sub^t of HP BASIC that can reside mside the
mairrframe and has the afritity to control mstruments and tJther resources tn tl^
^\fSTe^ such 3s The cfispsay and keytaoard.

Mamframe or Canicage* The VXIhus cage that contains VXIbus modules

ModuJe, This rs typically a primed circuit board assembly and m associated
mechanical parts, front panel, optional shields, ami so on,

Peripheral CorTtroJ. VVhen the mainframe or one of its instruments is controlling

an external device such as a disk, plotter printer, or another ir^sirument, it is being
used to do peripheral control Mote that the HP-IB, RS-23Z, or other physical com-
munication paths can be used to CDntrol peripherals, but thjs functionality should
not be confused with datacomm One other important note is that peripheral con-
trof IS only supported via certain IBASfC commands

Rack-and-Stack Instniment This is a traditional stand-alone instmment that
consists of a cabmet, jnsirument functionafity, power supply, user interface, and
computer interface.

Resource Manager. Tfiis is a VXIbus device located at logical address {some-
times the command module ur embedded controller), which provides configuration
management services such as A24 and A32 address space configuration, com-
mander/servant configuration, power-up self-test, and diagnostic test manage-
ment.

VXI-OS, A set of software services that reside on top of the pSOS **" operating
system. These services consist of interrupt handlmg, shared data space manage-
ment, and operation of specific hardware features of the command module that
enable instrument drsvers to implement the two -task model for handling instru-
ment and user interface I/O (see artfcle on page 29)
pSOS is a U.S. trademark Qf Software Corrtpcinsnts Group, Im:.

Since the slot module is a speciaJ device to begin wit h^
it is convenient to place all system reBOiirces on this
mociule. This includt?s slot 0, tfie VMEbus system control-
ler, the resource manager, the 48S~VXIbus interface
de\itM', and the instnmteiit drivers for any register-based
instnmients made by the same manttfacturer This com-
bination device will be refetred to as a commnnd module
in this series of articles. There Is no industry standarcl
term for this conuTion module, and it is sometimes
referred to by one of its functions suc^h as slot or
resource manager.

Flig, 6 shows the aJtemate communication paths allowed
in a VXIbus system and the role of the command module
m this system. If the controller is an external computer, it
will typically interface through HP IB cables since no
direct VXtbus path will be available. The instruments will
be controlled using ASCII coiiuu^mds, typically complying
with the SCPI standard. If the instrument is a message-
based device, instrument cotnmands will be routed
through Ihe command module directly to the message-
based itistmment for mteqiretation ajul exeeulititi, IT the
insUument is registt>r-based, the commatid module will
intercept and interpret, the conmiand and then perform
the proper binary register accesses to the device to
execute the function. From the controller, both device
types connected to the comntand module appear to be
SCPI message-based devices-

If ati entbedded controller is used, it can still communi-
cate over its HP-IB control port to the command modulej
or it can control any or all devices diiect ly from its
VXJbus interface, ('ontrary to many preconceptions,
controlling a message-based device directly from an
embedded computer will dehver very little or no increase
in speed. This is because ASCII command Inteqiretation
and number building Result in delays much greater than
bus hajidshake time and thus speeds are kept contparable
to HP-IB communication. However, accessing the hard-
ware registers directly on a register-based device cmi

SCPI Commands

HP-IB

VXIbus
{OptianaMy MXfbus)

Mutfule

Binarv

Sased

Binary

Device

Fig. 6. Alternate eommunicatifjii paths allowed in a VXIbus system.

April mm Hewlett-P^kflfd Jouniaj 13

)Copr. 1949-1998 Hewlett-Packard Co.

provide dramatic increases in continuous and interactive
throughput, sometimes approaching three orders of
magnitude. Therefore, the highest-speed path in a VXJbus
system is direct access to the internal registers of a
device, and is the only path that can consistently exceed
HP-IB speeds.

The recently introduced MXIbus interface allows external
controllers access to VXlbus registers by mapping the
\'X[bus data trajisfer bus onto a Oexible interconnect
cable. This allows external cootTollers to access the
high-speed \^Xrbus architecture with only a modest
degradation of totai system performance compared to an
embedded controller This modest throughput degradation
is sUll much higher than can be expected froni the IIP- IB.

Many users choose SCPI ASCII commands to develop
their test systems initiaOy, and then fine tune the identi-
fied bottlenecks by accessing registens directly where
needed- Some message-based devices also support register
access for functions in which speed is unportanl. These
may be registers in shaied memory' space thai hold
blocks of binary data for fast continuous data transfer, or
registers thai access the instruments configuration
hardware whenever higii, interactive throughput is de-
sired.

high-performance instrument systenis. Instiimient vendors,
system intcgratoi's, and end users have unprecedented
opportunities to address a wide variety of applications
using the \'XIbus architectural features. By using tJie
HP-IB as an interface, users can mix and match VXlbus
products with modular measurement system (MMS)
modules and HP-IB instiiiments to perfoim an even wider
range of measurements, while retaining a single model of
interfacing with the instmments. This migration path from
the IIP-IB, the compatibility with MMS and HP-IB archi-
tectures, and the high-perfonnance capabilities of the
VXlbus architecture promise to make VXlbus a widely
used architecture.

References

1. K. Jessen, "'\TCIbus: A New Intercormection Standard for Modular
Instruments," Hmtielt- Packard Jou/nial, Vol. 40, no. 2, April 1989.
pp. 91-95.

2. Ibid., p. 92.

HP-UX IS bas&d on and i& compatible wtth UNIX System Laboratories' LfNEK' aperatiog
system ft ahu complies wxf\ VOpen's* XPG3. POSIX tOD3 ? and .SVI02 miertaCB specifSca-
lions

UNIX ts a registered trade ma ri< of UNlXSv^tem LaboraLones Inc. in th&U.S A and other
countries.

X/Qpen IS 2 trademark of X/Open Company Limittd in the UK and other countrtes,

Summary

The VXIbuH offers a high degree of flexibiUty in module
size, bus stniclure, and coitununi cation protocols for

14 Ap ril 1 992 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

The VXIbus From an Instrument
Designer's Perspective

HP has defined a set of internal standards to compensate for some
missing aspects of the VXIbus standard that are critical to instrument
design.

by Steven J. Nareiso and Gregorj' A* Hill

The \^bus specification defines a technically sound
modular instrument standard that addresses eiectrical,
mechanical, EMC/power, and commimication requirements
for instrument modules. Although extensive, the ^'Xlbus
standard does not cover certam information that is
critical to an mstrumenfs design. For this reason, it
becomes necessai^' for a VXIbus instrument manufacturer
to define an internal standard to supplement the VXIbus
specification.

The internal standards developed by HP enable instru-
ment designers to provide customers ^ith a consistent
•^look and feel" and functional interoperability. These
standards also pro\1de designers with c^ommon hardware
interface and firmwaie design guldeiines so that they can
focus on specific instrument features and not on system
design.

HP has concentrated its interna] standardization efforts in
four areas: a conmicjn instrument language, hardware
interface, soft front-panel design, irmd industrial and
mechanical design. This paper will cover these areas ajid
other supplemental HP standards*

SCPI: A Common Instrument Language

Until recently a test engineer had to deal with a variety
of instniment programming languages and formats. Dat^
was transferred in almost every format imaginaijle, from
ASCn to device dependent compacted binary. UTien a
new instrument was introduced, the engineer could look
forwaid to rewriting tiie m^ority of the instrument driver
code, even if the new instrument was a direct replace-
ment from the same manufacturer

In 1987, IEEE standard 488.2 was approved. This standard
provides a ievel of standardisation in message and data
formats, message exchange protoc^ols, and common
commands to be shared among a wide range of devices.
This standard allows computer Imiguages to speak in a
consistent manner to instmments and enables higher-level
instrument; test executives to be written.

IEEE 488.2 defmes a few common commands that ad-
dress the housekeeping functions of the instalment. The
standard intentionally does not define commands that are
necessary for measurement or signal configuration. This is
the area that the industiy's Standard Commands for

Programmable Instruments fSCPI) addresses. SCPI is used
by all of HP's \\?CIbus modules.

Originally HP's Test and Measiuement System Language,
SCPI builds upon existing standards wherever possiblej
including IEEE standard 488>2 and IEEE Standard 754.
The result is a language that is orthogonal, powerful,
extensible, and yet familiar and fidendiy to users. The
language never refers to instniment tjpes, only to instru-
ment functions. Therefore, SCPI applies to a wide variety
of instruments, from power supplies to network analyzers.
We refer lo this consistent coverage of all instnmients as
horizontal compatibility. The language also offers vertical
compatibilit>', or consistent coverage of succeeding
generations within an instrument family.

Mnemonics

SCPI uses a formal set of truncation rules to generate
mnemonics. The niles sre stated as follows:

• If a koyvt^ord is four characters or few er, the key^^^ord
itself is the mnemonic (e.g., AUTO, ON » OFF).

• If the keyword is longer than four characters the nme-
monic is the first four characters of the keyword (e.g.,
OUTPuO.

■ If the resulting mnemonic ends with a vowel , tlie nme-
monic is truncated to three characters, dropping the trail-
ing vowel (e.g., ATTenuator).

» if a ptu^ase is used instead of a single word, the keyword
uses the first character of the first words, followed by the
entire last word { e.g., Kaiser BESsel).'*'

Hierarchical Structure

Keywords are joined lo form a compound header element
consistent with IEEE 488.2. This produces a hierarchical
language. Thus, to set the input attenuator the command
would be lNPut:ATrenuator There are several reasons for
choosing a hierarchical stnicture. First, a four-character
nmemonic becomes quickly overloaded, even within a
single instrument. Collisions often occm* that must be
resolved by \iolating the mnemonic generation rules. By
making the language hierarchical, keywords can have
meaning within the context of their tnn^ position, and
collisions effectively disappear. For example, to set an
output attenuator, the command would be
OUTPut: ATTenuator. Both the input and otitput subsystems

■ The t&ur cheractej- rule restriets the keyword ta KflES

Apri I 1902 UewJetl-l^ckanl Journal 1 5

)Copr. 1949-1998 Hewlett-Packard Co.

use tJ\e keyword ATTenuator without conflict because they
appear in different places in the tree.

Default Node

Soine functions are execuleci more often than others, and
the most common functions need lo have short and
easy-to-use keywords. SCFI accommodates this by placing
default nodes at critical points in the tree. Default nodes
do not n^^ to be sent as part of the command. For
example, there are several commands assoc^iated with
output cfjnditioning such as attenuator, filtering, offsets,
and output enabling. We detemiinc*d that output enabling
was the most commonly used function. Therefore, we
added the command OUTPut[:STATeL whicti enabJes the
instnmient's output. The application can send either
OUTPut-STATe ON or simply OUTPut ON to enable an output.

Default nodes piay an equally important role in allowing
the language to be extensible. For exaoipie, if we had a
command in the output section calletl FELTer, which
enabled a low-p^iss filter, and we wished to add a com-
mand that enabled a high -pass fiUer, a con Hie t would
exist. Tlie new command creates a further quali Heat ion of
the keyword Filter. To add the new command, one would
add a default node lo the existing command under filter,
describing the additifjnaJ qualillcation. Thus, the existing
command would become OUTPut: Fl tier [IPASsl. We could
then add the new command as OUTPut:FlLTer:HPASs. It is
important to extend by adding default nodes because the
default node allows applications written for the old
instnmient lo continue to work with the new exiended
capability instalment. The ap])licatioji can still send
DUTPut:FlLTer and expect it to function the same as it did
before the extensions were made.

Standard Parameter Forms

SCPI provides seveial standardized parameter fonns and
discourages the use of fomis that do not conform to the
standard. These standardized fom^s include:

Nymeric Parameter In addition to accepting ASCII numeric
input, the numeric parameter also accepts several ciata
apprf)ximations. For example, INFinity is represented in
SCPI as 9.9 E^T, and tlie command NAN, or "not a
number," is represented as 9.91 Ei37, All numeric parame-
ters nntsf also accept MAX and MIN which represent the
maximum and mininnmi values thai the function can be
set to, while giving consideration to other settings within
the instrument,

MlN and MAX are also required as parameters to the query
fonn of a command, Tliis fonn allows the application to
determine the maximum and minimum legal values that
can be sent without error. For example, if an input
attenuator can be set to values of to 70 dB, then for
the quei^^ IN Put; ATTenuator?, MAX would return the v^alue
70. Attempting to set a value greater than 70 would result
in an error. Sending any vtdue within the range of to 70
dB would cause the attenuator to be set to the closest
available value. For cxi^miple, if the attenuator had steps
of 10 dB, receipt of the command IN Put: ATTenuator 38
would cause the attenuator lo be set to 40 dB. with no
error generated.

SCPT requires the use of numeric parameters whenever a
parameter am be expressed 4is a number Qualitative
tem^s such as FltTer:CUToff tOWlHIGH are not allowed
because one instrument's tOW is another s HIGH,

Boolean Parameter A Boolean parameter accepts ON. OFF, 1,
\>i as values. DN and 1 are ahiises as are OFF and Q. The
query form returns 1 and to be compatible with the
values returned by the IEEE 488.2 common commands.

Discrete Switch Parametet Ttie discrete switch parameter
allows for select inn munag several different options.
These selertions are specified as character data. An
example would be

TRlGger:SOURce INTemaJ I EXTemal I BUS l IMMediate

where I indicates alternate selections.

Parameter Couplings. When a function can be coupled to
another function, SCPI controls the couplit^g through the
AUTO keyword. Tuming AUTO on allows the function's
value to be automatically determined by other settings in
the instrument. AUTO hiis the paramelers ON I OFF i ONCE.
ONCE is an event that has the effect of tuming AUTO ON
and then OFF, thus allowing the value to be automatically
determined tmd then frossen at that valtie. The AUTO node
is a subnoik^ of I he function, producing an unbalanced
tree hke that in the following example:

SENSE
: ATTenuator <value>
AUTO <Boolean> 1 ONCE

Minimization of Parameters

Most conm^ands that control instrument settinjjs have a
single parameter associated with them. When nu>re than
one parameter is specified, the function tends lo become
overloaded and confusing to use, Wien the two paranie-
ters arc broken into separate commands, the use he-
comes more obvious an<i easier to learn. An example is a
proposed commainl that sets a power level and controls
the output port. The proposed form is POWerlEVel 5 W, ON.
This is broken into tw^o conmiands, one that sets power
level (POWei :LEVel 5 W), and one that controls the output
switch (OUTPut:STATe ON).

Signal -Oriented Measurements

When making measurements, the particular type of
hardw^are has traditionally controlled the specific mea-
surement technique. This meant that the application had
to know how the measurement was being performed in
terms of the hardware. The VS. Air Force's MATE/CllL
program was the first to recognize that measurements
should be performed in terms of the sigtuil being mea-
sured and that the instrument should perform the hard-
ware setup necessary to make that measurement.

A signal measurement is performed througli a set of
layered connnands. At the highest level the MEASure
command is used. This command configures the instru-
ment, triggers acquisition of data, and then processes the
data into final form. Thus, sending the command
M£ASure:VOLTage:PERiod ? would return the period of the
voltage signal.

16 Ap ril 1992 Hewlett-Packard JoumaJ

)Copr. 1949-1998 Hewlett-Packard Co.

SCH

HP-IB

SCF1

Connnanib

VUtms

Difecl

Registef

Access

tiY Ifitemal

Cofnputer

Birtary

SCP1

ComntANds

msciii

Tramlates SCPI Conimands \m HP
Regtster-Based Modutes

Passes ilirougb 5CPI ar otli«r ASCII
ComRiands to any Message -Ba.sed
Module

VXtbus

Message-
Based
Mod life

■

Regtsier-
Based
Module

There Is a need to be able to fme tune the measurement
beyond what the instmment can pro\irie. Therefore, the
MEASure command has two additional associated com-
mandSt CONFi^urc and READ. The pinpose of CONFigure is
to perfonn tiie static setup of the aietisiu-ement. The READ
command perfonns the data acquisition and postprocess-
ing functions. The just iHcation is thai the application is
able to cojifigiu-e the measurement, make smalt device-
dependent a4iustments to the setup, and then complete
the high-level measurement process through the READ.

The READ is further broken down into INfTiate, which
causes acquisitions to occur, and FETCl^ wirich performs
the postprocessing. This allows sevei-ai postprocessing
operations to occur on the same acquired data. Tliis
feature is especially valuable when the acquired data is
nonperiodic.

Parameters to all of these commands are described in
terms of the desired measurement. Ranges are avoided,
and replaced with expected value parameters, Accmacy
parameters are expresstxi in absolute values as opposed
to a percentage of range. For example, MEAS:VOLT:DC? 5, .001
configures the instrument to a range capable of 5 Vd(^
with an accuracy of 1 mV.

A Cominoii Hardware Interface

Hewlett-Packard bases its VXIbus instruments on two
different haixlware interfaces: message-based and register-
based. Whenever space and cost allow, the message -based
interface is used because it allows the ultimate freedom
in interoperability tmd independence of commanders*
since the instnmient's language is contained within the
module. For other instnmients the register-based design
provides small si>;e and low cost> Both interfaces are
VXIbus revision L3 compatible.

The IIP El 405 conunand tnodule (whif h alstj provides
slot functions) contains ttie SCPl language processor for
all HP register- based modules and allows transpart^nt
fEEEi 488.2 or SC'Pl control of register-based and mes-
sage-based modules. Addressing is identical to thai used
for rack-and-stack instniments in that there is a primary

■ A cDmmjjntfer is a dsvica that controEs other devices on the VXIbus (sea page 12).

Rei)ist«r
Read^ and
Writes
I Binary)

iased

■

fle§rsler-
Sased
(Utadute

Fig, I. Altemat^e communication
paths lor VXl>us instruments.

address for each VXIbus mainframe and there are second-
ary' addresses for each instniment. Module combmations.
such as HP's VXIbus switches, can be configured together
as a single instnmient. Embedded computers may speak
directly on the VXIbus using SCPI for message-based
modules and register-level instructions for register-based
modules. They may also speak to register-based modutes
with SCPI \ia the HP-IB and the command module. Fig. 1
shows these communicatiort paihs for \^XIbus instru-
ments.

The finnwaie for both message-based and register-based
instmments is based on a generic conunand parser design
which is IEEE 488.2 c(mipatihle. For the \'XlbiLs interface
code in a message-based instnunentj the parser and the
execution routines all reside in the instnmient module.
The register-based instruments have their corresponding
code in the HP E14U5 conmituid module or the HP
E13(K)/1A mainframe's built-in commander. This nm 1 1 it ask-
ing design alloc^ates each HP register-based instnimetU. its
owTi task, allowing iransparent programming of each as
an individual instrunieni, wfuk^ substantially reducing
overall cost beci^ause die CPU ^^ shared by all register-
based modules. The article on page 2f* describes the
multitasking scheme for VXIbus conuumid modules.

The Message- Based Interface

The purj^ose of the generic HP message-based interface is
to control the operation of the instrument's hardware
througli c^onnnands received over the VXIbus directly
front the controller. These commands generally take the
form of IEEE 4aS.2 ASCII strings using \r5abus^defmed
word-serial protocol (see page 12), but can also be simple
register reads and w^rites. The ASCII strings allow the
user to program the instnnnent module in the same
manner as its rac k-and-stack eciuivalent. The simple
register reads and writes allow higher-speed communica-
tion for tasks such as mo%ing lai^e blocks of data be-
tween the Lnstnmienl and a computer.

One of the promises of VXIbus is that by designing to a
connnon architecture, insirumenl designers can foctis
development efforts on the irislnunentation fimctions
instead of on the digital interface, and therefore be able
to release new products wit It a lower up-froni invest ment

April 1 ml Hewlett-Par kard I oi mial 1 7

)Copr. 1949-1998 Hewlett-Packard Co.

68000

Proaessor
Ini Efface

Privats Bus

^^9 ^^M

Initrumenl

Control

Reg isle rsi

VXIIlMS

Intfiirface
Gale Arrety

Sh«rftif Bt]$

Ifi^rufnerit

Cnntidl

Registers

Fig. 2. HP message-based instni-

meril block diagram.

and slioilor developtnent time. Achitnirig tliis goal is not
an automatic by-produei of choosing V'XJbus as a com-
mon platrorm, II requires conunitmenl to a single instni-
ment architecliirc frorti Lop to bottom. HP's family of
message-based inslnmients is based on such an arcfiilec-
ture. Stalling with the IIP E1410A digital multimeter,
every message-based instrument has bcn^n built arount! a
common core. This core includes a high-performance
SCPl parser, a flexible real-time operating system, and
common VXI driver code, all running in a conmion
hardware environment.

At the fotmdation of this architecture is a 68000 micro-
processor and two gate arrays ^ which guarantee that the
<*onimon fimctions are identical within the various instru-
ments (see Fig. 2). With this h aid ware core, designers
ciui easily concentrate design efforts on the instrumenta-
tion functions, instead of on the microprocessor, VXIbus
interface, and contmon finnware.

The Processor Interface, One of the gate arrays pro\ides
resources common to most microprocessor-based instru-
ments, hi a single 124-pin package, it performs the work
of more Ihan 250 SSI and MSI iniegrated circuits. Its
functions include address decoding, interrupt conditioning,
various timing functions, and single-bit 1/0-
Th is gate array defines a standard memory map, as
showTi in Fig. 3. It has separate output pins for selecting
ROM, private RAM, shai'ed RAM, the \^bus, several local
peripheral de\ices, and a 32K-byte adciress block. It
generates the ai^propriatc V^XIbus signals for accessing the
A16 (64K-bjte) and ^24 (IBM-byte) addressing modes as
well as execnting VXTbus interrupt acknowledge cycles.

There is signal conditioning for 16 different interrupt
sources J incluciing three imemal timing soiu'ces. Each
interrupt can be programmed to one of seven priority
levels. When an interrupt is asserted, the gate array
drives the appropriate priority code onto the microproces-
sors three IRQ luies. The microproc^essor then executes an
interrupt cycle, in which it fetches a vector fiom the gate
array, Tliis vector indicates w-hich of the various sources
is mterrupting. To provide complete Qexibihtjv each of the
intemipt inputs can he programmed to select the signal
polarity* attd v\'hether it is edge or level sensitive (see
Fig, 4),

The processor interface gate array also includes a pacer
function. HTien triggered either by software or an exter-
nal signal, the pacer generates a series of pulses. The
number of pulses and the pulse frequency are both
progranmiable as 24- bit values.

VXIbus Interface. The other gate array provides the inter-
face lo the VXIbus, This gate array coiitairis the VXIbus
configuration and communication registers, VXIbus access
control, and support of shared liAM, It resides on a
shared bus between the microprocessor and the VXIbus,
as shown in Fig. 2. The shared bus is accessible to both
the onboard inicroprocessor and external VXIbus devices.

The configuration registers are the key to identifying a
device within a VXIbus system. In addition, they provide
a standard mechanism for reporting deface self-test status
and assigning device addresses. The conmiuni cation
registers provide the mechanism for SCPI commtmication
between a commander and its servants.

The VXIbus interface gate array supports the full set of
message-based capabilities defined by the VXIbus specifi-
cation incluciing the vailous word-serial protocols, the
shared-memory protocol, static and dynamic configura-
tion, shared A24 or A32 RAM, and VXIbus master capa-
bility.

djfFFFFFF
l^xRlDOOO

Privnte RAM

QjtEOOOOO

Shared RAM

0x200000

VXtbusA24
UGM Bytes)

OkIFODOO

VXfbusAie
l&4K6yt&s}

OxiEEOOa

VXIbus mo Achnowiflifgfi

OxtECOOO

VXIbus RegisltFB

(httEAOOO

Registers

OxiEBOOO

Pmiphitmh

OkIEODOO

Mtscellafiaoits

OxGOOOOO

ROM

Fig. 3, Standard memory map for HP message-ba^ed devices.

IS April 1992 Hew!ett-Fackard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Edgc/l^wf

Qotptit

AckiTowledge —
Fig, 4. IiileiTQpL signal coiidilioi urig.

The bus access control capability supports eight diffcreni
access modes. The onboard microprocessor caii directly
access the gale array registers or the shared RAM Any
\^Ibus master can access the gate array's registers or the
shared RAM The onboard nucroprocessor can access
other VXlbus slaves,'*' and it can access the gate array or
shared RAM as VXlbus slaves. In addition, the gate array
itself can initiate \QQbus transactions.

Ife reduce bus traffic, the gate airay can be programmed
to send a signal to the device's commander to indicate
certain events, Tliis mode allows the commander to
attend to tasks other than polling, which is otherwise
required. Similarly the gate array can interrupt the local
microprocessor to notify it of certain events, including the
arrival of a word-serial comnnand.

The gate array also impJements hardware decoding of
conmion word-serial commands. This feature increases
command processing speed by eliminating the need to
interpret word-serial commands in firmware.

Direct Register Access. HP's message-based devices are
normally controlled via SCPI commands passed through
the \^bus uiterface. The onboard microprocessor inter-
prets these messages and then executes a series of reads
and writes to and from the instrument's internal control
registers shown in Fig. 2. Some of HP's message- based
instruments provide a more efficient mode for critical
high-speed operations, bt these instruments, the internal
control registers are accessible from the V.\lEbas (they
are interfaced to the shared bus much like the shared
A24 or A32 RAM). This architecture allows a \Oabus
controller to control the instrument's operation directly
without the overhead of SCPI command transmission and
parsing. In effect, these instruments can be operated as
register-based devices when the application demands the
highest possible speed.

The Complete FamKy. This common architecture has been
implemented in more than 15 different HP message-based
instruments. Some of these instruments include:

HP El 405 Command Module
HP EUIOA 64/2 Digh Multimeter
HP El 446 A Arbitraiy Fimction Generator
HP E1416A Power Meter**

* Since the fimcessDi can access and be interrupted by other VXlbus modules, it can func-
tion as a commander and as a sar^/ant of a commandai.

'' See "Btamplesof Message-Baaed VXi Instruments" on rhe next page

HP E1440A Synth^ized Funcdon/Sweep Generator^

HP E1420B Universal Counter

HP EU26A Digitizing Ctecilloscope**

HP E142SA Digitizmg OsciUoscope

HP 75000 Series 90 Modular SONETySDH Analyzer

The generic HP register-based inierfare is controlled by
simple register reads and wiites, which aUow high-speed
communication to the insintment, ASCII strings can also
be used to program all HP register-based modules through
the SCPI language processor in the HP E1405 command
module or the HP E1300/1 mainframe.

HP's regisier-based devices aU have a simple, consistent
interface to the VXIbtis backplane. Fig. 5 show^ a block
diagram of a t>pical register-based interface. The interface
is ideally suited for any Low-cost instrument application
ha\ang straightfon^'ard control requirements. To simplify
the firmware development tasks, these interfaces have
been designed to have a consistent "look ^md feel" among
similar tjpes of instrument modules. Each register-based
instnutienl includes the required \^bus configiuation
registers as well as the device dependent registers needed
for instrument control. The key to both the low cost and
high speed of these devices is their simplicity. Many
fmictions. such as closing a relay can be executed by just
a single renter write from the VXlbus.

The interface hardware consists of some address and data
buffers, an address decoder, a small gate array, and the
various data registers. The gate array takes care of aH the
tuning details for the various handshake and control
signals between the VXlbus and the device's registers.
The interface functions as a VXlbus servant ^ and provides
the device with the capabihty of generating inteniipts on
the \'lCIbus* This interface is used in more than 30 as-
sorted HP Series B and Series C modules including
low-cost multimeters, counters, digital-to-analog convert-
ers, and switches. It is also offered in both Series B and
Series C breadboard modules.

The Model D20 digital functional test gystem described on
page 59 uses register-based interface hardware to achieve
the high I/O speed reqmred to move large blocks of
digital patterns to and from the computer.

VXlbus
Configtiralicm

Instrument

VXlbus

Fig. S. Register-based interface.

April 1992 Hewlett'FackHtd Joimml 19

)Copr. 1949-1998 Hewlett-Packard Co.

Examples of Message-Based VXI Instruments

To incorporate the capabilities of existing nan-VXIbus instrumems into modules
that could fit into VXIbus msmframes. the designs and features of some instru-
ments were reengineered to make liiem into VXfbus message- based msiryrrtertts.
The following sections describe the design considerations thai went into creatirig
these msTruments and the benefits denved from thesr VXIbus rmp I e mentation,

HP Et426A 500-MHz Digitizing Oscilloscope

To create the HP EU26A. engineefs leveraged technotogy developed for the HP
5450 3 A 50 Q- MHz digitiiing oscilloscope. This lechnoiogy provided ar^ excellent
platform to implement a four-channel 5Q0-MH;?. high-accuracv acquisition system
in a twQ-$!ot VXIbus module. A high level of ir>teQration created all the elements
necessary to implement the acquisitian system on one board and the control and
interface circuitry on the second board. The scope functions were integrated using
the foJ lowing HP semjconductor processes

» Preamp: HP-5 integrated clrcoit process

► Track and hofd: LTCMOS
* High-speed trigger HP-5
» Logic trigger: MMDS HIS
»Timebase HQMOS
MB'ChsnneiOAC: LTCMOS.

The CPU system was designed to take maximum advantage of the existing firm-
ware allowjng a htgh level ai compattbrlity between the HP E14Z6A and the HP
54503 A. The HP Et426A offers the user many advantages over its counterpart, the
HP 545D3A. Along with the benefits of standardizatton of the VXIbus, the user can
configure a single VXIbus frame with up to 24 500-MHz acquismon channels, alt
synchronized via the ECL/TTL backplane trigger The E142BA firmware was cus-
tomized to take advantage of the removal of the display from the traditional oscil-
loscope architecture to optimize the Ihroughpul to itie VXIbus This, coupled with
shared memory, has resulted in a significant improvement in throughput compared
to the IEEE 488 IHP-IB) based HP 545Q3A. In addition to SCPL the E142fiA also
accepts H? 545D3A IEEE 48B,Z commands.

HP E1440A ZVMH^ Synltiesizer and Furtcticn Generator

Tlie HP EI440A .-synthesizer circuits are derived from the HP 3324 synthesized
function/sweep generator and the HP 3325 synthesizer/function generator With
this leverage it was easy to provide a full-featured instrument. All features
associated with the HP 3325 are available, includirtg AM and PM. plus extra bene-
tits like SCPI programming.

+ 24V

CP1 ~ C2

lOffnF

Vcihage
RL»g:Ulnlor

-0+5V

V V

C3
100 nF

To Voltage Regulators

Fig. 1. The dc-to-dc converter usad in th@ EfP £1 440A ^the^i^er and function generator

2 Ai ml 1992 Hewleit-Pai^kard Jounml

)Copr. 1949-1998 Hewlett-Packard Co.

The HP E1440A plyg-m module occupies two C-srie mainframe slots and h3S a
stanctertJ front paitel provfding BM^ tyije eiectrical cofinectors SM\ (sufface moum
leeruiologvJ was nsBS^i^ ^ tJie signal boani to achieve ttie fugJvpscfcage dstsi-
ty of tti^ rmdiile

All cntical sectto^s nf the sv^thesizer. such as the VCO. mtxer. preamp, and rBfer-
enceosEiKalorar- "n a two-stded metal covsrta reduce any

induced mjise, es: - frejuencv divicters and Other swttchrng

Ctrcujts. Addflional snieiding oi y>^ power SAjppSy a»>d micnjipfocessor board area
vi^s necessarv tE improve the purity o1 ttm outpul signal Id avoid crosstalk from
the switcher of the module ptrwsr supply to the output amplifier, the whole dc-to-
dc converter with the oytpyt titters had to be shielded wiih a steel box The printed
circuit board has fi^dthroughs araurxl the dc-to-dc (inverter area so thai ttiis box
totally encloses all switching circuits This shield is also necessary to satisfy VX1-
bus specif icatj DOS for magnetic field radiation on the module surface

Both boards are fnounted with screws (every 3 inches} to the module cover The

chassis ground and floating ground are coupled with 1 -nF capacitors vja these
screws For the same reason. BNC connectors are mounted with ring capacitors
(like a washer] The PI and P2 connectors are shielded with grounding brackets to
reduce the radiation throughout the connectors and to make a good, iow- inductive
digital ground connection from the microprocessor board to the mainframe With
gaskets on nearly all slots, this module meets the VDE Class-B RFI regulations.

Possible ground loops caused by interconnected instruments are reduced by isolat-
ing signal ground from the VXIbus and chassis ground. All microprocessor- related
control signals are coupled via nptocauplers while the analog signals to and from
the VXIbus are coupled by small transformers The number of optocouplers is
reduced by serializing the connection between the microprocessoi and the signal
board. Standard components are used, such as an MC66651 USART on the co ntrof
board and standard shift registers on the signal hoard for serial -to-parallel conver-
sions and vice versa With a transfer rate of 800 kilobaud, a data rate of about 40
khytes/s is achieved for random access to the device bus, which has seven ad^
dress, one RM and eight data bits.

For generating floating voltages of +5V, I5V, and 30V with very low ripple l< 1 mV),
a new concept for the dc-to-dc converter was needed it consists of two forward
converters with a duty cycle greater than 50%. running 1B0 degrees out of phase
(see Fig, 1 \ The rechfied voltages of both conveners are connected together re-
sulting in a voltage with 100% duty cycle. For this reason the LC filter does not
need to filter the high-voltage ripple from a smgte forward converter It only has to
reduce the switching spikes caused by the rectifier diodes.

HP t41§A RF Power Meter

The F1416A VXlbus RF power meter evolved from tiie HP 701 OOA power meter
used in the HP 70000 modular measurement system [MMSf and the VXIbus HP
£U1 OA voltmeter Ttie E1416A has a high level of reuse and leverage from the
deslgos of these two products, which reduced the cost of R&D and the time to
mafkm.

The measuremef^t of power is often made *n Jocstions that have high levels of RF
noise, so there is a need for good shrefdrng fmm RF fields and immunrty from noise
condi/ded into iM unit via cables The VXIbus specrficaTion dictates 3 high level of
immunity to both conducted and ciose-fretd radiated mterference ffom withtn the
VXlbjs mainframe V30bus also specifies the fa^BJ erf do^-fi^ radiated irrteffer-
ence gen^ataJ by the insinimerc

To handle the ftF rKiise probtem in tte HP Et416A a decision was made to use iwo
ti(£u\i boards, an analog boani for the low-level power meter cm:uiis and a digital
board for the VXIhus interface ar>d instrument controtlei This is important for both
performance and manufacturing consideratiorts There was a poteniiat problem

wfth the coupUng of high*ffequency noise generated by the digital hardware into
the measurenvent Signal This is eased considerably by separating the circuits and
their grounds. In addition, ustng two boards improves utilization of the printed

circuit panels and allows the analog sectEon to use a less-enpensive tWfo4ayer
constfuctJDn

The tMjard layout and grounding are significant factors in meeting the VXIbus
perfonnance and electro rriagnetic compatibility s pec tficat ions. The digital tioard
uses B ground'pfane layer to reduce the inductance of the ground traces The
analog board is constructed on a two-layer printed circuit board with a gridded
ground System for the digital interface and separate ground systems for noisy and
quiet analog cin:uits These grounds are connected togetlier on the digitai board at
a star point

The sensltEve analog input circuits have a ground reference that floats at the same
potential as the sensor, whtch may differ from that of the rest of the instrument
because of long sensor cable lengths, This ground reference is a separate single
point ground system driven by a broadband opamp, supplying all of the ac section
of the power meter up to the synchronous detector. To ensure trouble-free opera-
tion m environments with high levels of f^F radiation, the HP El 41 6A circuit boards
fit into an aluminum alloy case of high shielding integrity. The number of apertures
and their size were reduced as much as possible and each seam around the case is
either firmly clamped or sealed with a conductive gasket. The case also functions
as runners that slide into the mainframe guides

500- MH: Digitizing Oscilloscope
Don Smith
Project Manager
Colorado Springs Division

21 -MHz Synthesizer and Function

Generator

Ha raid Mattes and Helmut Senrtewald

Project Engineers

B5bliogen Instrument Division

RF Power Meter

Tony Lymer

project Engineer

Queensferry Microwave Division

Front-Panel Design

Since raibus inslrumrnts lack sufficient front-panel space
for displays and controls, tl^e instmnienl designer RUJSt
turn to a cotnpiiLer for a \irmal front panel. HP's interac-
tive t^st generator (ilP ITG) .software allows the progranv
mer to control VXfbus and rack-and-stack instruments
interactively and speeds tievelopnient of test programs,

HP ITG is a program that ntns on HP BASIC worksta-
tions, HP BAH1C;/ITX, and MS-DOS. Therefore, it offers the
power and perfomianc(^ of HP BASIC in tht^ devekjpinenl
or exix'ution environment, as well tis compatibility with
industry standard operating systems.

The software has two different environments. The first is
the development environment. This is the windows or
panels environment in which instrument panels are used
to generate code that is displayed in the Editor window of
this environment and then stored to a file for execution.
A mouse is used to select from pop~up windows and
pull-down menus (see Fig. 6. page 23). The second
environment is the execution en\ironment. In this run-
time environment, the application is executing, not HP
ITG. No front panels are seen, and the application
executes rapidly

Instruinent States

W\iQn the instrument is in a desired configiiraLi<jn, or
setup, the user can save this setup as an instmiuent slate.

April 1992 HewIett'P;ickard Jaumal 2 1

)Copr. 1949-1998 Hewlett-Packard Co.

Small, Low-Cost Mainfranie with a Registei^Based Interface

The HP El 300Ayi A VXfbus mainframe is designed for high performance and tow
cost- For cost and sue reasons, tne VXlbus B-size or VMEdus 5U format was cho-
sen. The desire to maximire the number of available card slots with field wtring
brought about the idea of an interdigitated backplane with seven 8-size and three
A'Size siots for external moduJes and three internal B-size slots for the built-in
command module arid the two-slot HP E13ZG multimeter

The mairframe with the huilt-in command module is stand-alone. This required the
addition of other features not found in other VXlbus mainframes such as i;eyboard
and display, dc power operation, and mass storage. Careful design was necessarv
TO minimize the conducted and radiated nofse er>vironment that the shieldless
B-$ize cards operate in. The power system is able to operate from either ac, or
optionally, dc power with "bumpless" transfer between power sources. There are
fWD power supplies, one OEM offline switcher providing + 5 and i: 12 Vdc and an
optional dc40'dc converter that is connected between the ac mafn and the tirst
supply This second power supply senses when the ac power becomes unusable
and switches to dc power operatson transparently.

The mass storage devices were leveraged from the HP 9153C disk dnve. TTie con-
troller board, ruggedized hard disk, and flexible disk drive were integrated into the
mainframe around the internal VXIbus slots and power supplies. Communication
with the disks is accomplished by piggybacking on the huilt-in command module's
HP-IB port,

Designing the HP E13XX series of Wlbus cards provided many ctiallenges Size
was the foremost challenge with only appTOximately one-half inch of vertrcal
space and 50 square inches of horizontal space in which to design Shields in this
limited vertical space were out of the question. Therefore, an extra effort was
made to minimize noise sources by using good ground gnddmg tachmques. mlni-
m.izing clock and power supply loop areas, and controlling signal rise times. The
register-based interface was chosen for space and cost reasons. An ASIC was
developed to do the handshaking and timing tor the regi star-based interface.

T]ie greatest space challenge was in the development of the field wiring terminal
housing, This housing has to contam screw lerminat bbcks large enough to handle
250 Vac, support a 35-pound load, and be less than 0.8 inch wide. Wa did a lot of
20 and 3D modeling to create liiis design. This housing design has been scaied up
for use in HP's C-$ize VXIbus offerings.

Cost was also a major challenge in designing the cards. Two-layer printed circuit
boards were the rule rather than the exception, further increasing the noise reduc-
[lon challenge. Most of the cards' backplane interfaces were common, many right
down to tiie layout of the components This leverage helped to decrease costs and
time to market.

Von Campbell

Project Manager

Loveland Instrument Division

HP !TG will record this instmment setup in memor>^ as a
list of values for each instrument function or control. The
user gives this instrument state a unique name. The tjser
can then recall this instrtmient setup at any time by using
the state name instead of having to set each individual
value separately.

Another feature is caUed automatic incremental state
progranuuing. This simply means that the software will let
the controller determine the fewest commands necessary
to reconfigure the instrument to the state selected by the
user. \^en changing an in.strument from its current state
to some other state, the list of values for the current
state is compared with the list of values for the next
state. The software then identifies the values that need
updating and sends ordy the commands neccsstuy to
update those values. Tliis can speed lip the execution
time substantially compared to traditional techniques.

Instruinent Drivers

The drivers lor HP's VXIbus ii^truiuents generate SCPl
conunands. These drivers are ASCII text files that contain
the SCPl command information and HP ITG panel layout
information for a particular instrument, Thest^ Hies are
loaded into memory by the development eiwlromuent.

Instrument drivers are written in an independent language
developed by HR This means that tl^ese drivers are uoi
tied to a particular operating system. This allowed HP to
bring HP ITG fimctionaiity to another operating sy stent
wititoul having to rewrite any drivers.

HP ITG also allows the creation of application panels, a
panel that represents a group of instnmients, tinique
subprograms, or both. The task is similar to writing an
instrument driver fde. Once this file is created, it can be
used by any person with a develop me lU system that has
access to the application driver file.

Industrial and Mechanical Design

In addition to colors and graphic styles, HP has adopted
several other standards for external ease of use. Series C
instruments have at least three LED annunciators (Failed,
Access, and Error) to assist in system configuration and
rroubleshooting. Failed indicates an interface failure, Access
indicates \OQbus backplane acti\aty, and Error indicates an
SCPl user progranuning error. Additi^onal LEDs indicate
instrument-specific activities.

Series C instruments are normally positioned vertically
causing cables to hang down. This can obsctu*e the LEDs
or connector labels. Hence, aH LEDs are located on the
top of the module and all labeling must be on the side of
the cormectors. In addition, triggering, c locks, and syn-
chronizing signals are located centrally on the panel and
analog signal input and output are on the bottom.

A dual three- wire analog bus standard has been defined
which is suitable for microvolts but also has approximate-
ly a lOMHz bandwidth. There are six HP modules pres-
ently using this siandard including multimeters and
scanners.

2E Apdi 1992 Hcwtett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

All calibraiion controls (e.g., potenliometers) on HP
VXIbus instruments are either electronic or are accessible
from the front panel so module removal is not necessary
for ac^justinents. Swilciics for logical address and inter-
rupt and bus request level are accessible without remov-
ing shields.

Fig, 6. HP ITG development
enviroruuent, showing t^^pical
instmment soft front panels.

Acknowledgments

The authors would like to thank Jay Nemeth- Johannes,
Don Smith, Helmut Sennew^ald, Harald Mattes. Tony
l^vmer, and Von Campbell as well as aU of the others who
helped make HP VlQbus a truly interdivisional effort.

April J mi Hewtetf-Packard Journal 23

)Copr. 1949-1998 Hewlett-Packard Co.

Design of Mainframe Firmware in an
Open Architecture Environment

Compatibility, portability, expandibility, usability, scalability, and
compliance with SCPI are some of the attributes designed into HP's VXIbus
mainframe firmware.

by Paul B* WorreU

The \^Ibus common fimiware architecture Ls designed to
mee! ihe needs or HP's instmmenl niamfraine products
that are based on the VXIbus (\''MEbiJS Extensions for
Instnimentatlon). The design and dennition ot this archi-
tecture was based on experience with other IIP main-
frames such as the HP :M97A, HP 3S52A. and HP ;32:i5A,
and the needs of two newer products, the HP Bi3D0
B-size \TObus mainframe and caids and the HP K14()()
C-size \^XIbus mainframe and cards.

Tlie desigt^ of the fimiwarp tor rJiese mainframes Wiis
influenced by many external factors. Some oj' these
factors included the IEEE 488.2 standard, the evol\4ng
^'Xlbus instrument standai'd, the emerging SCPI standaid,
tmd the need to support I he arch i lecture on multiple CPl^
platforms. Tliis article will discuss some aspects of the
design environment aiul the resulting impact on the
llmware architecture, as well as product features m-
eluded in the desigit.

This mainframe Hrmwarc architecture was designed witli
the following goals:

• Compafibility with the IEEE 488.2 instrument program-
ming metaphor

• Compliance with SCPI and leverage of the HP SCPI Ian-
guage parser for all instniment development

• Expandability and openness to support for future en-
hancements or changes

• Better ease of use than our previous generation of prod-
ucts

• Support for the creation of a scalable family of VXIbus-
compatible products from multiple HP divisions

• Support for a smooth migration between existing rack-
aitd-stack uistruments and modular VXIbus instruments.

IEEE 488,2 Compatibility

The IEEE 488.2 srajidaid had just been ratified when the
design efibn for the VXIbus fmnware architecture was
started. IEEE 48S.2 clarifies many aspects of instrument
imi>iemenlation that were previously left up to the design-
er's interiJretation. This clarification inevitably removed
some nexJbility to promote interoperabilitj^ between
instnmients.

For instance, under IEEE 488,2, an instrument is required
to continue to respond to bus messages when ui local
mode, even when there is simultaneous front-panel
activity. This requirement forces an IEEE 488.2 instrument

to consist of at least two tasks, one to handle the IEEE
488 bus (HP-IB) and one to handle frtinf -panel operations,
IEEE 488.2 introduces tiie cfjncepi of s<M]uenLial versus
overlapped o]>eration. A se<|uent1al conimand always
finishes before the next conunand is executetl. An over-
lapped comntand allows execution of subsequent com-
mands while the device operations initiated by the first
overlapped command are still in progress. Overlapped
commands typically require one additional task per
simultimeously opera! ing overlapped command. The
article on page 29 describes the two tasks dissociated
with handling bus and front-panel activity.

IEEE 488.2 instruments aren't allowed to perform some
operations that pre%ious generations of instnuuents were
capable of doing. An example of one of these illegal
actiorys is a measurement operation that will never
complete. The fEEE 488,2 message excliange protocol
requires that all commands execute to a definite comple-
tion. Another example is the case of a classical voltmeter,
which when it is put in in tenial-t rigger mode wiE always
have its latest reading ready to be output to the bus. This
type of mslnmicnt behavior is also a violation of the
message exchiiiige i)rotocol because the readings ivreiVi
the expiicit result of the execution of a conunand, and
the readings do not have the defined IEEE 488/2 response
separators.

In exchange for these functional restrictions^ the IEEE
488-2 standard specifies device hebavior in the following
areas:

Standard message handling protocols that include error
handling

I -nanibiguous syntactic stmctiu'es for program and re-
sponse messages

Conmion commands for instnmtent systems
Standard status reporting structures and mechanisms.

The standard message exchange protocol describes how
messages are received by an instrument and how re-
sponses to these messages are generated. This protocol
also defines most of the error conditions that cait arise
between a controller ^md an Instntment, One of tJte new
error conditions that IEEE 488.2 defines Ls a query error.
This error can result from either sending a new command
to a device before reading all of the response of a pre-
vious command, or by requesting a response from a
device that has not received a query.

24 April 1 992 Hewlett-Packaurd Journal

)Copr. 1949-1998 Hewlett-Packard Co.

The message exchange protocol also describes in detaiJ

the actions of an instnnnent in response to several
asynchronous signals such as clear and trigger It de-
scribe fuUy the operation of the input and output buffers
of an instrument^ e\'en during error conditions such as a
deadlock.

The IEEE 4S82 program and response menage syntax
allows for handling different lyjies of data in one stan-
dard way. The program message syntax defines character,
decmial numeric, nondecimal numeric^ string, arbitrary
block, and expression data that can be received by
instruments. The response message syntax aliows charac-
ter, three types of decimal numeric, hexatiecimal. octal,
binaiy, sfring, and arbitrmy' ASCII data to be returned
from instruments. It also allows for definite- and indefi-
nite- length arbitmr>' blocks, which are useful Tor transmit-
ting large quantities of data, 8-bit extended ASCII codes,
or other data that is not displayable directly.

The common commands enable t^ontrol ajid interrogation
of instruments with a standard syntax. One example of a
common command is t!ie *IDM? query, which retnms a
unique instrument i<lentifier that contains the instrument
manufacturer, model specifier, and firmware revision
number Other conuuands configure the status subsystem,
pro%ide for message synchronization, resei the instnmient
and initiate mtemal instrumei\t self-tests.

The common device status reporting model of IEEE 488.2
allows the liser to generate a generic status handler that
can operate with multiple instruments. The status subsys-
tem is configured \1a common commands thai specify
masking options and SRQ (status request) generation. The
status subsystem also provicies a way of causing an SRQ
on several conmion device errors such as an execution
error, a command error, or a query enor. It also aJlows
SRQ generation for common events such as power-up or
operation complete.

Because of the potential for design and in^plenu^ntation
leverage between instnjments, we determined that, the
common firmware archlteetm^^ for the VXIbus wouiti
require that all in.stmments be IEEE 488.2 compliam. hi
addition to internal leverage, the conmionality of a
programming metaphor was thought to be an ease-of-use
advantage for fmr customers. With the emergence of the
sen mdtistr>^ standard instmmcnt language, IEEE 488.2
compliance is now an accepteti design practice,

SCPI Compatibility

Concurrently wttli the development of our VXIbus firm-
ware architecture, HP's Measurement Systems Operation
(MSO) was in the process of generating a common
language for all of HP's test and measurement instru-
ments. TMSL (test and measurement system language), as
it was being called, was designed to provide both hori-
jsontal and veriicai language portability between instnj-
ments. Tlie management team saw the potential for
stan<iardization mid implementation leverage with TMSL
and decided that all VXIbus instrument's would be TMSL
compliant.

MSO decided that to support the new langtiage more
fully it would be appropriate to provide software support.

This support was deli\^red in the form of a highi^erfor-
mance TMSL parser that was wTitten for the Motorola
MCOSOOO microprocessor. Since our VXIbus conunand
module hardware is based on the MC68000, this parser
became an integral part of all our \'XIbus instruments.
The performance characteristics of this parser imple-
menlation enable our \TCIbu5 instruments to deliver better
throughput than our previous generation of instruments.

The need for a standard programming language across aH
test equipment was recognized by other test and measure-
ment equipment manufacturers in 1989. These manufac-
turers formed a consortium to generate tl\e SC'FI (Stan-
dard Conmiands for Progranmiable Instrumentation)
language specification. The initial core of the SCPI
language was based on HP's TMSL. Since our instruments
were designed to be TMSL compatible, we had to make
only a few minor changes to be compbant with SCPI
1990.0.

Expandable Architecture

Early in tlie development of our common VXIbus firm-
ware architecture, w^e detennined that modularity' and
Oexibiiity were the best ways to ensure a long hfe for the
architecture. Modularity' allows independent design and
implementation of the various niofhiles once their inter-
faces are specLfied. It aLso allows for upgrading modules
to add new capabiUty while keeping the old interfaces for
backwards compatibility.

We were particularly careful to provide flexibility in the
areas of instntmeni creation and binfling because the
design requirententi* specified that the architecture must
have the ability to:

• Easily add drivers for new register-biised modules

• Replace an existing deviec driver with a new driver with
enhanced capabilities

• Supply replacement drivers for rapid turnaround of de-
fect fixes to customers and to HP field service and sup-
port organizations

• Allow creation of custom instruments that could be easily
integrated by customers

• Allow construction of virtual instruments, which are aiiii-
traiy combinations of message-based and register-based
devices

• Allow construction of pseudoinstruments, which are
code-only modules with an instrument'like interface .

Driver ReplaGement. Replacuig existing drivers in HP's
VXIbus firmware architecture simply involves download-
ing the driver from the host machine to the command
module in the mainframe. The downloaded driver is
placed in nonvolatile EiAM so that it w^ill remain in place
after power cycling. During power-up the driver RAM area
is fii^f searched by the resource manager when it is
binding devices to drivers. This guarantees that down-
loaded drivers will always be able to replace a ROM
version that handler I he same devices. New drivers can
also be added i)y ti own loading. Downloadable drivers
ensure rapid distribution of defect fixes since the custom-
er only needs to be sent a disk with the driver software
rather tlian a new ROM.

April 1 9fi2 Hewlett-Packard Journal 25

)Copr. 1949-1998 Hewlett-Packard Co.

select an instnimeni ._

1 E^^^tmi^ iMijiUii3 imi£ia4 Uimifl t\ n s

Fl^, 1. First -level insirument
!5 election menu for a system
containing a voltmeter, a
switch, aiid HP TBASIC,

Custom Instruments. Drivers for custom instnimenls art^
eitsily incDri>oratefl into the mainframe system just like
liny other downloadable ciriver At configuration time,
these flrivers tell the resource manager abi>ut Lhe de\ices
and resources they need- The resource manager ttien
starts them like any other driver, and since they are
dov^Ttloadable, custom drivers can replace any ROM
driver hi the system.

Virtual Instruments, A \Tjtual instrument Is a j^oup of
individual insinmieni drivers bound together in one
driver. To become a virtual instrument, a driver must;
indicate to the resource manager during configuration
1 hat it needs a particular set of devices. The resource
manager will bind those deviceJis to the driver and start it.
One of the first virtual instruments is the scanning
\^oltmeter, which consists of a voltmeter device and one
or more switch devices. The scarunng voltmeter behaves
like a voltmeter with many input terminals, which are
selected via channel specifiers. Customers can dov*mJoad
their own configuration tables that control the binding of
devices to drivers.

PseudQJnstruments. Some programs running in the VXIbus
mainframe do not conununicate with devices directlyj hut.
they do require some support from the system. These
prognmis are called pseudoinstruments, or code-only
instruments. After all the instrument devices in the

system have been bound to drivers, the resource manager
looks for drivers that ideniiry themselves as pseudoinstru-
ments. ft then determines the resource lequirements for
these drivers and starts tliem. IIP I BASIC is an example
of a pseudoinstrument driver IBASIC has an SCPI pro-
gran uning language that is used to cormnunicate with tJie
1 BASIC execution engine, but it doesn't require any
VXIbus devices to function.

Better Usability

To provide better ease of use, we decided to perform
extpnsive usability testing. In the design phase of this
jjrtjject, a user interface and front-panel prototype was
constructed. This prototype was used to test design
alternatives for the front-panel layout and menu system
organization. A fest script that consisted of a list of user
tasks was generated ajid then people from various depart-
ments were asked to follow the list. Their questions,
reactions, successes, failures, and comments were re-
corded. This input was used to refine the design of the
VXIbus system display functionality. With user feedback it
was possible to test for reactions to different types of
menu presentation and organization.

Customers of our earlier products appreciated being able
to use IEEE 488 bus syntax directly from the tont panel.

swrrcK

SWITCH 32:

! swrrCH_3Z;

SWnCH_3Z:
Enter cartf number 1
1

SWrTCH^32:
Ent&f card number 1

SWITCH 32:

HEWLETT-PACKAHD. E1345A,O.A.03.(M

SWITCH_aZi
Ent«r cafil number

SWITCH_3Z:

"IS ChaniiBl Relav Mux"

Fig, 2. The range of selections available after seleciing SWITCH from the first -level menu in a system containing an HP 1345 A relay multiplex-
er on card L The 1 that appears where it says "Etiter card number/' is entered by the user.

26 April 1G92 Hewlett-Paekai'd Journal

)Copr. 1949-1998 Hewlett-Packard Co.

We fell that this was a key feature thai we had to pro-
vide in the \'XIbus common firmware architeetuie since it
is easy to leana and debug instrument syiitax by ii>ing it
on the front panel

TTiere were also many customer requests for single- key
setups for common measurement functions. This need
was addressed by pro\idjng a menu s>^em for the front
panel Fig. I show^s the first-level instnunent selection
menu for a ^mem containing a \olimeler. a switch, and
IBASIC. Fig. 2 shows some of the possible menu selec-
tions that appear once the SWITCH menu item is selected.

When a specific instrument is selected, an histrument-spe-
cific ftmction menu appears. These function menus are
nested with the most likely selections appearing firsl
Usability testing was agaui valuable here ui tuning the
menu choices. Once a menu key is pressed, the user is
prompted for any additional re(|uired information, the
measurement is executed, and the result is returned to
tile display. Tlie user can at any time recall the SC'Pl
command that corresponds to the last menu choice. This
feature allows users to intenogate the instrument for
SCPl strings to prognim specific functions, ^md has been
viewed as enhancing SCPl ease of learning,

VXIbus Product Scalability and Leverage

One of the early design goals for the Ormware was
leverage between the B-size and C-size VXIbus products.
This was accompUshcd by designing a system that in-
cludes all lire featiues required by hotit the IIP EL300 and
IIP E1400 mainframe projects and then subset ling the
implementation as necessarj^ The overall arc liitec Lure was

first put together with HP Teamwork SA, a tool that

stit^ports structured analj^is and structured design.
Structured analysis helped the design team \enfy the
completeness and correctness of the architecture* and
helped the management team mth effort estimation and
job partitioning.

Fig. 3 shows the first-level structxired analysis diagram for
the \^?abus firmware architcH'ture. This diagram show^s the
interfaces to IBASIC, external terminals, built-in front
panels, message-based devices, and so on. This graphical
depiction of the system was %^ery useful in explaining
functionality to management and communicating architec-
ture trade-ofis within the design team.

Tlie RSr-2:32 temunal drivers are essentially the same for
both products. The front-panel display driver is unique lu
the B-size proiiuct since the current C-size product has no
built-in front panel. The resource^ manager functionality is
also common except Tor message-based device handling
(which is unsuppailed because of haidwaie resf del ions in
the B-size product) and user-defined system configuration
tables that were added to the C-size product.

The operating system for both products, c^led VXI-OS, is
generated from common source code w-hich is retargeted
for the specific hardware features of the various plat-
forms. The operating system presents a consistent inter-
face to the rest of the system despite certain hardware
dependent features present on specific platforms. VXI-OS
Ls dc^scribed in the article on page 29,

IVtessage-Saserf
Servant EJevtces

Commands

Respofises

MP ftegist«i-Biisiac|
S&rvaeil Devices

Instru ntent Besp oitsas
InstTiimflnt flesponsds

Interrupts

Intefnfil From Panel

(HP £1300 8 Stfe

fAinnUm\ii]

Displays

Djsptay^^'

Displays^' Input
Events.

Enernef Terminjil

l££€4BflfHP-IBI
Conlfolliir

Fig, 3. Structured analysis dla-
gram far the VXItms nrmware
architeciure.

April 199£ HewiGLt-Packard Journal 27

)Copr. 1949-1998 Hewlett-Packard Co.

Most of Lht* inBtnunenl drivei^ are identicai in both
products. The only exceptions arc cases in whicli addi-
tional c^apability is provided by the C-size product and the
driver takes advaiitage of it. Even in those cases, there is
only one coi>y of the source code, which Is conditionally
compiled.

In addition to the VXIbus c^ommon firmware architecture,
we developed a comnif>n message-based kernel for use in
all message-based instnmients developed at HP. This
message-based kernel Includes the real-time, multitasking
pSOS operating system, a common SCPI parser, and a
recommended hardware layout.

Migrating Rack -and- Stack Test Systems to the VXIbus

Since application portability from rack-and-stack systems
to the VXIbus was one of our goals, we had tu develop a
scheme that enstu^^s that verj^- little or no change has to
be ma<Je to applications written for rack-and-stack archi-
tectures when they are ported to the VXIbus environment.

A rack-and-stack system consists of separate instruments
which all have their own lElEE 488 addresses. To allow
maximujii portability, this type of progranuning melaphor
should be preserved. Early in the design pliase, tire idea
of embedding addressing infoniiation into the fiata stream
was considered. Several problems with this design
emerged.

For example, consider tbe case in which the rommand
SELECT: DVM is used to specify thai succeeding commands
go to \]w voltmeter, and SEtECTCMR is used to specify
that succeeding comnmnds go to to coimter. In the simple
case, if the developer sends SELECT:DVM, then sends a
measurement command, and then reads the response, the
response will be from the voltmeter that received the
measurement command. In a more complicaied scenario,
if the developer sends SELECT:DVM and a voltmeter mea-
surement comniand, then sends SELECT:C^fTR and a counter
measurement con\niand, and then reads tlie response, the
response thai is read is dependent on the timing of the
voltmeter and tlie counter nieasuretrients-

In this type of setup, the system software developer
views the test systen^ as t:)ne large instnunent with parts
that can be selected via commands. There is only one
input buffer, one output buffer, and one copy of the
status information. With this configuration, the software
developer has to keep track of which instrument is
currently processing information from the i^nput buffer.
Also, any of the instnmients could be putting their results
into the output buffer. Tlie software developer must know
which instruments have put what data in what order in

the output buffer. If the timing between the initiation of a
measurement and tiie result appearing in the output
buffer changes^ then it is possible for results to be placed
in the output buffer with tin^e dependent ordering. This
task is even more complicated because errors could have
occurred on any or all of the instrunu^nLs, creating
unexpected results.

Device status is another area in which information
sharing is problematic. There is normally only one service
request bit in the device status register, which is shared
among all the instruments capai>le of requesting service.
When a service request is asserted, the software develop-
er must tr>' Ui imravel which entity in the system Ls really
requesting service.

To solve these problems HP's VXIbus system provides a
progranunuig melaphor in which each instrument has its
own ijiput buffer, f>u(put buffer, and device status in-
fomuitLon. Tliese VXIbus instniments behave exactly like
separate IEEE 488.2 instruments. The softw^are developer
is able to use the stmie progiammiiig rnetiiphor used with
separate instruments in the rack-and-stack implementa-
tion. Porting the code to the VXIbus system can be as
simple as substituting the IEEE 488.2 secondary address
of the VXIbus instrument for the lEEK 488 address of the
instnimeni in the rack-and-stack system.

Ac know ! edgm e nts

When it became evident, tliat. with the available resources
neither the HP El 300 or the MP E1400 niainlrame proj-
ects could be implemented on scliedule as separate
projects, our R&D n^anager tx>mbined the two design
teams and itsed those resources to design a common
architecture for both i^roducts. Therefore, Joe Marriott
deserv^es much of tlie CTedit for the success of the
implementation of the firmware Jirchilecture, since he was
able to provide an environment in which it wiLs possible
to sliare the architecture design. The team that
constructed the VXIbus contmon architecture consisted of
Chuck Platz who provided the resource manager, Chris
Kelly who provided the operating system, Rick Hester
who provided the terminal inclependent display system,
and Karen Moy who provided thc^ front-panel and menu
systems. Martin Meyer, t)ilip Murarijan, Jerry Metz, Bryan
Sutula, and Dave Rustlci were responsible for the design
and consttijction of individual instnjment drivers. Addi-
tional thanks go to An BojTie and Darren Kwock who
wrote hardware drivers. Ron Firooz provided initial
project guidance and w^as almosi single-handedly responsi-
ble for the integration of the two project teams.

2 8 April IW2 Hewlett-Packard Joumat

)Copr. 1949-1998 Hewlett-Packard Co.

Real-Time Multitasking of Instruments
in the VXIbus Command Modules

The operating system in HP s command modules uses two reentrant
processes to handle communication between the user and instruments on
the VXIbus.

by Christopher P. KeUy

The ROM-based program (Rrniware) in the IIP \'X]i>iis
controllers provides the '"personality" that users interact
with when operating the mstmmenls in the \vKrbus
cardcage. The tactors that affected the design of the
firmware m tJiese products include;

• The VXIbus standard, which was evolving during firm-
ware development, describes certain required functions.

• The SCPI instmmenl language was chosen as the stan-
dard iiinguage for ail HP VTObus products. Tlie fEEE
48S.2 language standaid (upon which SC'PI is based) de-
fines certain instrument behavior and some language
constructs.

• Support had to be provided for both message-based and
register-based VKIbus instrtnnents with no progranmiing
differences visible from the HP-IB interface.

• The firmware was targeted to run on the on the CPUs for
both the B size HP EiSOO and the C-size HP El 400 prod-
uct fajuilies,

• Since ongtjing tlevehjpment of instrimients for the VXIbus
is ex|)e(1ed, the finnware had to allow the addition of
new instrunient drivers to the existing products with
minimum develoiJiuenl and upgrade effort.

• Software development for many register-based instru-
ments from different divisions had to be coordinated.

This articie explores the design of HP's VXIbus mull i task-
ing reai-time operating system, or VXl-OS, and the system
configuration firm ware called the resource manager. A
significant portion of the VXI-OS provides suppoil for
regLster-based instmments. To use tlie high-level SCPI
language, register-based instruments with less on-card
intelligence require more support from the host CPU than
message-based instnunents. Because of this fact most of
the discussion in this article will be specific to VXI-OS
support for register- based instruments.

The VXIbus Instrument Model

The VXIbus instnimcnt model can be described as an
**instrunient on a card," meaning that each card acts as an
independent instnjment. This contrasts w1di some pre-
vious generations of HP card-based instmments. The
older products use languages in wliich all llie instruments
in the cardcage operate as a single instrument. Also, fJie
older architecture provides the integrated services of
many different cards with a single, massive command
langiiage- The new model treats each trard as a single

instrument, but also allows combining several cards into a
more complex \irtual instnmient.'^

By adopting the new model, I'XIbus instruments allow the
use of a standard cent m and language shared by both caid
and rack-and-stac*k instrumerus. For example, a I'XIbus
DMM and a rack-and -slack f)MIVI use the same SCPI
language in the same way This provides some hardware
independence to the user, wi)o can now choose between
performance, cost, and space without requiring changes in
the software dri\ing the instmments. Tlie SCPI language
stiUidard protects the sizeable softwai'e investment the
typical customer has made in the softw^are for an instru-
ment system.

The two major classes of \'Xlbus instmnients are mes-
sage-based devices and regisler-bas(^d de\ices. Message-
based devices usually include all langua|*e processing and
a large well-detlned register set on the Lnstmment card.
Protocols for communications between a conunander and
a message-based instrument Jire well-defined iind aimed at
multivendor compatibihty. By t^ontrast^ register- based
devices have a smaller required register set and a simpler
progranmiing interface. These devices are usually smaller
and less expensive than equivalent message-based instru-
meiUs, but may require more support from the command
nKjdule, VViien programmed at the binary register level,
register- based devices can be orders of magnitude faster
than equivalent message-based devices that use a higher-
level language.

One goal of the VXI-OS firmware team was to provide the
same language and programming interface for both
register-based and message-based instruments. Tliis means
that both types of instrument interfaces should answer
the I IP-IB communications bus in exactly the same w^ay
and should operate using exactly the same SCPI language
regardless of the instrument type.

Register-based irLsiruments, with tittle or no intelligence
on each card, retiuire the sendees of a microprocessor to
use the SCPI language. This microprocessor can be
shared by several instJiiments, since in most cases an
instrument does not require full and continuous use of
the microprocessor's power. This sharing of expensive,

■ See page 26 for more about virtual irt^uuments.

April 1992 Ht?vrlett-Pjackani ,Iounuil 29

)Copr. 1949-1998 Hewlett-Packard Co.

intelligent l^ardware can result in lower systx^m cost than
in alteniatJve designs. In llie HP ViCIbiis systems, the
c(>nuT\iind ntodule provides this shared microprocessor
wh it'll iirtjf t'Hst^s comnmnds and data for many register-
based iiistninienl cards.

The HP Series 75000 nxodels E1300 and E1405 VXIbus
command modules are based on the Motorola 6800D
microprocessor. The ti-size El 300 and the C-size El 405
[>rovicie an tfP-IB inleri'ace to many HP rc^gi^sler-bosed
devices, TIh^ E1105 additi<inally provides full \^bus slot
conmtaiul module and resource manager functions for
message-based devices (see the article on page 6 for
more about slot fimctions), Tlie design of the nmiware
in these modules pen nits jjower-on system eonnguiation
t>ased on the instrument card mix. It also supports
intJependent operation of muhiple instruments in the
cai'dcage, and the addition of new instrunn^nt tlrivers.
Both modules are also able to use HP Instrument BASIC
(IBASICJ to control the instnunents.

The nucroprocessor must do the following tasks:
Receive commands from the HP4B interface for one or
several instruments

Receive commands from the instrument front panel and
RS-232 interface

Process the SCPI language for register-based instruments
Exeeute drivei^ functions for register-based instruments
Pass through conmiands from the HP- IB to message-
based instruments

Operate register-based and message-based instruments
inciependently.

In addition to these product-oriented needs, several
requirements were added that were dri^^en by the devel-
opment enviixmmt^nt. One of these requirements was the
need t(j ensure prodnctivity for developers writing instnj-
menl driver software. During development, several devel-
opers were simultaneously writing instntment driver
software for many different instruments. This software
was essentially htu'dware drivers, which typically means
real-tiuTC programming techniques and some assembly
language prograjruning for peak perfonnance and niiixi-
nnun control of the instrument. In addition, these devel-
oi>ers were retjuired to solve nuuiy sinviUir real-time
progranmiing iiroblerns for each driven However, to be
most productive, these developers needed to be able to
use a high-ievel progranuning language such as C whenev-
er possible.

To address these real-time ]irograniming (problems in a
general way, a real-time operatuig system w^as developed
that provides a set of function calls for the instnnnent
developer. This system has a C language programming
interface that permits the instnmient driver designers to
use C and gain the high progiamniing pro<:luctiv1ty levels
associated with liigh-level languaj^es and at the same time
satisfy ttie needs of real-time progiamming.

Using a single general model for instrument operation, the
resulting operating system, called VXl-OS^ also frees the
instrument designer from many of the problems of
real-time software design. For example, simple rules
regarding timing of instnmient funetions and use of

HP-IB

Display or
RS-212

H^^^^^^

■

HP-m 1

Orivst H

■

Dalac

^^H

InlBrface
Task'

omm 1^

Task- ^

Data
Space**

VXI'OS

Afbilraljiin

^^H

Command Moduli^
leg. HPE1405or
HP £1300 CPU}

VXIb^

Cant ai Some Logical Address H

1
Matnlrame

!■„„ UD ClAfUII.

^^H f<-'3

Contains SCPI Pstsbt am! Execution Routines
' Contains VXI-OS Tables, Task -Specific Data, and
Instrument'SpecrMc Daia

Ftg* 1^ Two tightly coupled (i^in)
tasks operate the instrument hard-
ware in \^Ibiis register- based
instruments.

SO April 1992 Hewlett-Packard JoumaJ

)Copr. 1949-1998 Hewlett-Packard Co.

HP-IB

Disptayor

UlftT

Comntand Module
(e.g., HPEl405or
HPEiaOOCPU)

Mainlrame

Fig. 2. ,4ji illustration of reeitiraii-
cy. T\vo register-based courtters
are driven from one copy of the
code kiT the datat'omni task and
one copy of the code for the user
iiiLerface task.

interrupts allow cooperative inter operation of many
instniinents in the same CPU,

A calling mechanism that is address independen! allows
addition of RAM-loaded instrnment drivers to the ROM-
based system. This scheme supports a strategy of instru-
ment driver upgrade and addition of new instruments to
existing ROMhased VXJbus systems. At power-on, the
system conilgures to the instnmieni cards found ot^ the
VXIbus, and is capable of finding and stalling instntmerU
drivers that have been RAM loaded. This allows driver
upgrade or addition of new instniment drivers long after
the initial system ilnnwarc is completed. See the aiticle
on page 24 for more about downloading instnmient
drivers.

The VKl-OS Instrument Model

To meel the requirements oi' IEEE 438.2, instruments
should be able to respond to front-panel commands while
processing HP-IB commands- TTiis approach differs from
some instnmierU models used in the piist. in which all
instrument measurement hardware was operated by only
one interface at any time. For many VXIbus instalments
this is not an issue^ since most message-based instru-
ments do not have a front panel in the same sense as
rack-and-stack instruments. However, for IIP VXIbus
register-based instruments the instrument model does
include a front panel.

Since this model requires active commantl recepiion from
both interfaces, in the VXIbus instrument model each
instrument is implemented as two closely coupled tasks
operating the same instrument hardware. These two tasks
are called the user interface task and the daUi^omm task
(see Fig. 1).

The user interface task receives comn\ands from the
display system, which is a task that operates the front
panel of the instninienL This front panel may be a
keyboard and a display that, are integral to the chassis (as
in the IIP EI300 series), or it may be a terminal con-
nected to the c(mtroller by an RS-232 or RS422 interface.
The datacomm task receives commands from the HP-IB
interface.

As indicated in Fig. 1^ tlie twin tasks of aiiy giveti instru-
ment are partners in operating the instrument fiardware.
These tasks are separate processes in the operating
system with separate stack space and other memory
allocations, but share the same global variables (data
space in Fig. 1).

Together with these shared global vai-iat>les» a rnimber of
resource locking functions in the operating system pro-
vide the tools necessai^^ for cooperative use of the
instnjment hardware. These fimctions are represented by
the block labeled VXl-OS arbitration in Fig. h The two
tasks of a given iiLSinnnenl are nearly identical mth the
exception of the communications interface, which de-
fjends tipon whether the task is serving the HP-IB or the
front panel

These tasks are written as reentrant firmware, so several
instruments of the same type can be present in the
VXJbus system simultaneously. These instrument tasks
execute the same progiam at the same ROM address, but
use separate data spaces to (jf'^^^'itlf' indei>endenl opera-
tion. This reentiancy allows the customer to operate any
combination of register-based instruments simply by
plugging in the cards required to perform the desired
measurement.

April 1992 Htjwlett-Paclcard Ju n nail 3 1

)Copr. 1949-1998 Hewlett-Packard Co.

Fig. 2 shows the case in which more than one register-
based counter of the same type Lure plugged hi to the
VXlbiis. Because of reentrancy, the twin lasks execute
one copy of the dataconini and user mterface ROM code
specific to the counters. However, bt^cause the counters
are at different addresses and may have different setups,
the tasks use st^parale ciata spac^es to distiiigiash one
counter from the otlier Fig. 3 shows the software orga-
nization in the command module to hajidle three different
register-based insLninients plugged into the VXIbus
mainframe.

Resource Management

When power is applied to the HP VXIbus system, the
VXIbus controller contlgnres itself to operate the particu-
lar set of instniments piesent on the VXIbus. The firm-
ware that causes this action is the wsource manager.

Foltowing the power-on reset and the CPU self-test, the
resource mimagcr scans all \^bus logical addresses for
instrument identification registers. These registers can
appear at any V^XIbus logical ad chess from through 255,
(in the A 16 address space the identification registers
appear at regular inler\^iils.) The resulting hsl of instru-
ments is us (Hi to generate a configuration table that
includes the card mmudacturer identifier, model number,
logical address, aji<i other data. Ttie resource manager
also identifies failed devices and places them into safe
states.

The resource manager also configures the memory map
of the \TGbus A24 and AlVl memory space, and thp seven
VXIbus inteniipl lines Eire assigned to VXIbus command-
ers. Since the VXIbus allows hierarchical instrument
ownership, the commander/servant hierarchy is estab-
lish ecJ at this time. This action assigns uistruments to
commanders based on the logical address of each.

After the instnmient card set is identified, the resource
man tiger assigns instrument drivers to the rej^ister-based
cards. This is done by asking each driver in the library'
whether il recognizes a partic^ular set of cards, Wien a
match is found, the driver is flagged for later startup m
an instrument task, mapping to a particular set of cards.

This sclieme allows ntultiple copies of any instrument
t>pe — one for each card or card set matcliing the driver.
For example, three digital multimeter cards on the bus
will trigger the startup of three thgital multimeter instru-
ments, one for each of the three cards. This is possible
because, as describecJ above, the drivers (which become
datacomm and user interface tasks when started) are
written i\B reentrant code.

Once this phase of resource management is completed,
the resource manager calls each flagged driver to deter-
mine the th^iver s needs for mernor>' iind other system
resources. A cumulative list of resources us compiled and
j^assed to the VXI-OS operating systjem. This information
is comp^ed to availabie resources to see whether the

HP-tB

Datictiinnt

^ — 1

User

IfltfifffflCS

V ,

Task

Data Space tor
HPB32BA

Oatacomm

"1 i

Us«f
liit«ffa«B

Task

DaUicdinni
Task

■1

Usf»r
Inttrfaca
Task 1

^^■F^^^

Data Space for
HP £1330 A

Data Space for
HPE132«A

VXI^OS
ftrbitrflfjon

VXIlHiB

vxriMs

Command IVIodule
(e 9 , HP E140S or
HP Et3M CPU}

HP E1329A ftegfst»^Basa1l DAC

At AiUresES

HP E133flA ttetistsf B«ieil

CouiileratAdffr«ss1E

HP ItS^KA Reglstar-fiasail
Valimeler at Addrass fi4

Mainframe
l<,g..HPEt4O0)

Fig, 3, Command module software organization for handlii^ three different types of register-based instniments.

B2 April t932 Hi^wlett-Fackani Jourrml

)Copr. 1949-1998 Hewlett-Packard Co.

system cmn be successfiiUy started with the present card
set. Later, the information is again used to assign the
required resources to each itislrument task as the task is
started.

The next phase of startup resenes the required memory

and other resources, and configures the operating sj'Biem
to match the present card set. The operating system is
started and In turn it starts the resource manager pass 2
process as its first and highest-priorjt>' task. The resource
manager pass 2 process uses the card configuration fable
mentioned earlier to spa^iv and activate the instrunaent
tasks that are associated witJi the V'XIbus instruments
fotmd earlicL These tasks are assigned to instruments at
particular logical addresses, and are also assigned HP-IB
secondary addresses.

The resource manager pass 2 process wiU spawn ^md
acthate only the first of each pair of instnmient tasks.
The first task of each pair started is the user interface
task. This action is performed by a Si>ecial operating
system call. Each of these initial instnmient tasks is
responsible for starting its trvrai task, the datacomni taskn
using anottier operatittg system call. Tliese calls establish
the shared global data areas and other operating systeni
data structures that provide the tight coupling between
the tasks.

An additional special instrument called the s^stmti instru-
menf. is also started. This system instrument allows
certain systent-wide operations to be controlled. These
operations include mapping of triggers on the VXIbus and
the setup of communication interfaces and system time,
date^ and diagnostic functions.

When the resource manager completes the startup of all
instruments, it starts a task to control each display
interface. These display tasks each control a from panel
or RS-2;^2 interface. The resource manager then pauses
(becomes dormant) until later operations require its
services. As soon as the resource manager pauses, tiie
lower-priority instrument tasks begin to nin. Each instru-
ment task pair (user interface and dat^comm) calls the
operating system to identify the addresses of any inst.m-
ment hardware allocated to that instrument. Also at this
time, resource sharing locks and other data structures are
initialized, a self-test is performed on the hardware, and
the connections to the HP-IB and the display system are
estal)lished. Flntdly, each task pauses until commands are
received for that instrument.

Communication with VXIbus Instruments

Since there are usually several instruments served by the
two communication interfaces (HP-IB driver and display
task), the Interfaces must select which instniment is to
receive the incoming command strings. In the HP-IB
interfac:e, this selection is performed using HP-IB second-
ary addressing* In the display system, this selection is
performed by ASCII commands to the display system, or
by softkey escape sequences.

In the HP-IB interface, most communication is handled by
a TMS 9914 interface IC. This chip handles prin^ary'
address actions satisfactorily, but secondary addressing
presents additional challenges tjo the interface. Support

FrimafY Address

StpgndarY
Address

Switch Control

S^em

Insiruinenr

euFfer

Instrumeitt
1

tdstrumenl
2

Fig* 4. An lUiistration showing huw the HP- IB secondary address Is
used to select an tnstmmenl in a VXIbus system,

for secondary addressing is provided by a custom ItP-IB
assistatit gate array IC, In the secondare' addressing
scheme, the VXIbus controller listens to a priniar>' ad-
dress, for example, address 9. When a primaty address
sequence is received, it is followed by a secondary
address sequence. This secondary address, between and
30, is used by the IlP-lB interface to select one of the
instruments connected to the controller at the specified
printar>' address. If for example, a voltmeter has been
assigned to secondary address 6, the HP- IB address for
this device would be 906,

If the device were being addressed by an HP 9000 Series
WO controller using workstation HP BASICS the full
address used by the prograninier would be 70J)06, where
Ihe 7 represents the H!^-IB card address in the worksta-
tion. Another device in the same VXIbus system might
answer at 70904, meaning secondary address 4.

To make addressing of devices easier, a relationship has
been establisbefi between the VXIbus logical address and
the HP-IB secondary address assignments. The relation-
ship is that an HP- IB secondary address equals 1/8 of the
VXIbus logif'al address. So a voltmeter s€^t at \\Xibus
logical address 48 would be assigned I IP-IB secondary'
address 48/8 = fi.

When the HP-IB interface has received the full addressing
sequence, it uses the secondary address to select which
instnnnent buffer to use for the incoming communications
strings. This routes conmiajid strings to the appropriate
instnnvient task, where the strings ai'e processed and the
commands are executed. Fig. 4 iises the analogy of a
switch to illustrate choosing the destination of a com-
mand string. The switch is controlled by the secondary
address received from the HP-IB addressing sequence.

In the case of commands received through a display
system interface, the instrimient selection is made
through more human-readable means. ASCII strings and
labeled soft keys are used to select which instrument is to
be addressed. After an instmment is selected, the display
system is connected to that ijistrument task and the
display format is controlled by the mstrument. In this

April im'-i Hewlett-Packard JoumaJ 33

)Copr. 1949-1998 Hewlett-Packard Co.

manner, instruments with differing human interface needs
can each present the user with appropriate prompts and
control displays. Softkeys allow the user to perform
measurementSj change instrument setup, view measure^
ment data, and perform other typical instrument front-
panel functions.

instrument Operation

Ulien a regisler-bcised instrument receives a command
string, the SCPI parser interprets the string and calls an
execution routine to perfonu the action that corresponds
to that string. Before a task can operate upon its instiu-
ment hardware, it must be sure the hardware is not
already in use by the other twin task. To prevent colli-
sions between the HP-IB task and the display system
task, each will request control of the instnmient hardware
through a call to a VXI-OS function. This function call
executes in less than 50 nticroseconds In the 8-MHz
MC68000. The caller is blocked if the hardw^are is already
in use, and is again made runnable whenever the hard-
ware becomes available.

When an instrument function requires an extended time
to complete, the instrument task may decide to w^ait for a
hardware interrupt indicating completion of the measure-
ment function- A call to the operating system allows the
caller to connect the instrument's interrupt service routine
with the interrupts from an instruntent card and then
pause the task until the intermpt arrives. Upon interrupt
assertion, the instrument service routine begins execution.
The instrument service routine has access to the shared
global data area of the two parent tasks of the instru-
ment, and also can be passed pointers to the data buffers
or other variables. Wlten the instnmient service routine
has completed its function, it can signal the parent task
to a weaken from the pause condition.

This fonn of operation can result in high efficiency in the
use of the shared CPl', since many tnstnaments such as
switches (e.g.. relay multiplexers) have relatively short
con^^^and sequences and relative ly long relay closure
times, Uithout Ihis intermpt technique, the CPU would
w^aste time waiting for relay closure to complete. This
allow^s other instrument driver tasks to use the CPU time
for other purposes, effectively overlapping the operations

of several instruments. Guidelines based on the speed of
the pause, interrupt, and awaken functions tell instrument
driver w^riters the timing circumstances in which these
tools are appropriate.

The VXl-OS has a sinular function to perfonn the required
operations resulting from the HP-IB Device Clear command.
Device Clear is an as^mchronous command used by the
HP-IB interface to force an instninient into a condition in
which it can accept conuuands. It can be used to abort
ongoing measurements, and when properly implemented,
requires an instrument to be interruptable in any of its
possible slates.

To awaken an instrument task that is paused waiting for
resources or waiting for an interrupt, the VXl-OS contains
a "clear instrument" function. This function sends wakeup
signals to an instrument task that awaken the task from
any of the pause conditions. If the task is awakened in
this manner, the return value from the "wait for interrupt''
function will indicate that Device Clear was received, not
the expected interrupt.

Conclusion

The VIQ-OS is a real-time multitasking operating system
developed for HP VXIbus command modules. VXUOS
contains many functions that support instrument drivers
for V'XIbus registei-based cm*ds. The instrument model for
these cards includes features allowing multiple indepen-
dent instruments to share one CPU. SoKIng these prob-
lems once for all instruments, V'KI-OS provides the
instrument finnware with a high level of stylistic similari-
ty and increases Ihe productivity of instrument fun^ware
writers.

Ackno w i e d gmen ts

Many thanks to Chuck Platz, w^ho wrote the resource
manager for both the HP Ei405 and the liP E1300 Series
commanders, for his assistance and ideas* Thanks also to
Martin Meyer and the other instmmenl driver writers at
HP's Loveland Instnmient Division w^ho provided helpful
suggestions regarding enhancements to the original
\0Q-OS definitions. Their patience and skill during the
parallel development of the opemting system and instru-
ments enhanced the results of both efforts.

34 ApriJ l992H#wletl-I^GkaridJouiTiai

)Copr. 1949-1998 Hewlett-Packard Co.

VXIbus Programming in C

A iibrary of C functions provides functionality that makes it easier for test
program developers to create applications that communicate with HP-IB
and VXIbus instruments.

by Lee Atchison

The VXIbus is a standard insTrament control bus that
allows high-speed access to test system insinimentation.
To achieve liiese high speeds, control! ens tunnecled to
the VXIbus nratnfrajiies require sophisticated test soft-
ware. These controllers must also be powerful enough to
take advantage of VXI bus's speed anti versatility. This
paper describes a modular instrument comnumications
library that is designed to work with \^Ibus interfaces.
The library is designed to be extensible and applicable to
several different computer architectures, operating sys-
tems, and instrument communication interfaces.

Lihrary^ Features

Tlie instrument hbrary defines a core set of runctionaUty
that will work on ail test-system instnnneiTt commimi ca-
tion ifilerfaces. This core includes read and write, ad-
dressing, timeout, locking, triggering! interrupt handling,
and status reporting. When using just this core functional-
ity, an applicaijon c^m be written lo use HF-iB instru-
ments (or VXlbiis jnstniments through an llP-TB-lo- VXIbus
translator such as the HP R1405 command m{Hlult\). lii^ter,
the appUcation can be porled with hi tie or no change to
talk to VXIbus instruments directly from a VXFbus-based
controUer (bypassing the HP-IB completely).

Tliis (!ore fuuctiorvality is sufficient for most measurement
application needs. 1 lowever, If ^m application requir(\s
additional functionality, features can be addt^l that apply
only to that application and its associaletl interface lo the
test instnmients. VXIbus adcls extended triggering capabil-
ities (ITL and ECL trigger line control), mapping (aUow-
ing access t<.> register-b;ii;etl and memory-mapi>etl de\ices},
and enhanced interrtipf handling. When using the addi-
tional VXIbus functionaUty, a test progranj (while no
longer portable to the IIP-IB) can still be ported to other
VXIbus controller environnu^nts. The same lest program
should work on VXIbus embedded cotilrolters and exter-
nal ccjntrollers using a mauiframe expander such iis
MXlbus.

Improved Productivity

The libnuy rtmlaitvs features that help to improve the
productivity of a test engineer developing a measurement
application. These features include easy-to-usp routines,
high-level I/O comnimids, and a functional unifonnity
across applications.

Ease of Use, Thc^ libraiy routines ari^ tlesigned to be easy
to use ajul understand. The hbr^uy uicorporates the

features specifically needed to communicate with instru-
mentation, especially iastnimenis (hat look or act like
IEEE 488.2 or SCPl instnintents. This differs tron) other
communication libraries tiiai allow communication widi
devices that may or may not be instruments (such as
printers, plotters, disk drives, etc,).

High-Levef Commands. High-level formatted I/O comnnmds
are available \o make test jirograms easier to write. These
include routines tliat allow converting to and front a
number of data formats iLsed by most instruments. For
example, number converters are available to convert data
to and from sbc different numeric formats that are t>TDical-
iy used m IEEE 488,2 imd St PI instiiiments. These
formatted 1/0 routines, while based on the C language
stdio routines prinif mid scarf, iiave extensions specilicatly
for instnimentation, such as controlling EOl and END bits,
IEEE 488.2 number and sliing formats, and so on.

Uniformity, I'sers need to learn only one set of routines
despite the number of com roller and interfatx's l>eing
used. This means thai once a test i>rograinrner le^jims
these library routines, ttiere is no need to re leant a rtew
set of routines when using a different controller,

Tlie folk) wing (' program takes a simple measurement
from a SCPl-biised voltmeter.

mainIK

INST dvm;
double res:

/* Prim message and terminate on error */
fanBrrorlLERR08_EXIT);
r Open the voltmeter */
dvm-iopen( "voltmeter*' I;

/• Take a measurement */
iprmtf|dvm;'MEAS:VOtT;DC?\n"),
/* Read the results 7
fscanf(dvmp''%r\&res);

r Pmt the results V
printfC'Resuft is %f\n",res|;

This program shows sevei-al different things about the
instnmK^nt library:
* It shows how to install an encir hantller, in this case, a
standard etTor handler that prints an enor nu^ssage and
then tenninates.

Aprit m2 Hewiett-^Pilckard JoiintJil 35

)Copr. 1949-1998 Hewlett-Packard Co.

• It shows how to address an iiustmnient using a symbolic
name. This isolatc^s hardware dependencies in Ihe struc-
ture of the address.

• II shows a simple example of the fomiatted I/O capability
to send a command anrl read ar>d parse the response*

Addresising an Instrument

Before conmiunicaling with an instmmenl, a Unk must be
established between the lesi application iind the instru-
ment. This link is created with the iopen"^ routine. This
routine takes as a parameter ihe address of au instru-
ment It then establishes a session with that instrujuenl
and retmns a number that uniquely itlenlifles ihe session
with the iustmment. This unique number, calletJ an INST
identifier, is used by all other routines iri the librar>^ to
communicate with the particular instnnneni set up in the
lopen call. A number of other parameters, such as timeout
values, can be set on a session-by-session basis.

The address of a VXIbus instrument can take one of two
different forms:

vxi,<ladiir> (e.g., vxi,24 or vjtiJ2B)

<symbolic_name> (e.g., voltmeter, dmrn, scope)

The fu^t address fomiat specifies a VXIbus instniment by
its logicaJ adilress <Jaddr>, wliich can he any number from
to 255. Tlie second fonnat allows an atidress to be a
symbolic name for an instrunu^nt. Tliese symbolic names
must be assigned by some other system resource (such
as the resource manager or a configiuation file) to refer
to a specific iiislannent at a specific address. For exam-
ple, voftmeter may he the symbolic nanie of the instrument
located at, VXIbus logical address 24,

High- Level Interface

The high-Ievf I iiip-rface provides a formatted I/O mecha-
nism thai is similar to the C stdio mechanism, except that
it Ls designed specifically for instniment communication
and is optimized for IEEE 488.2 compatible instnnnents.
Three main routines are available:

• iprirTtf. Send a fonruitled mt^ssage to a given Lnstrmnent.

• kcBni Receive a formatted message from a given instru-
ment.

• ipromptf. Send a formatted message to a given instmment
and then immediately read a formatted response.

These rormatled routines allow writing and reading of
several different fonnats of data. The fonuats include the
following standard stdio data types:

%d - Integer data

%t - Floatinji^-point data

%c - A single character

%s - A string of characters

The following data types have been added :^ecifically for
VXIbus ijistruments:

• %b/%B. Defmes binarynroded data that uses IEEE 488,2
definile-lenglh and indefmite-length arbitrary block re-
sponse data formats. Several options are available includ-
ing byte -swapping values from the tiyle ordering of the
instniment to the byte ordering of tlie controller. Tliis

• All of Ihe instfumeflt W^iy ruutinss are prsfxad wrth "i '

allows fast n*ading and writing of large blocks of binary
daia in a manner consistent v\ith IEEE 488,2 and SCTI.

' %e/%C. f)efines characters and strings of characters that
indicate end of data such as the EOl line for the Hr^4B mul
the END bit for the VXIbus. This includes optionally set-
ting thc^ END indicator on a write call and waiting for an
END indicator on a read call

' %S. Defines IEEE 488,2 string response data. This is es-
sentially a stritig enclosed in double quotes (with em-
bedded doul)le Quotes esc:aped). The SCPI language also
uses the string fonnat.

Numerif data can be read and writteri in any of tlie
following data fomtats:

®1 - IEEE 4Sa2 NEI format (integers such as SI)
@2 - IEEE 488.2 NR2 format (reai nun^bers without

exponents such as 53.5)
@3 - IEEE 4B8;2 Um format (real nimibers with

exponents such as 5.35E1)
@H - IEEE 4SB.2 slajidard hexadecimal number

format (such as #HHf4e)
@Q " IEEE 488.2 standard octal number formal

(such as #g377)
@B - IEEE 488.2 standard binary number fonnat

(such as#B01I01100)

WTren writing to an instnnnent, tmy ninnber can be
converted into any of the above fonnals by specifying the
fonnat desired. When reading from an instmment, any of
the above formats c^an be read and automatically deci-
pher*' d (the data fonnat does not have to hv specified).
Thus, if a number is read fron^ an instniment, the control-
ler does not have to know what format ilie number wiU
be in because the library wiU determine the number^s
format and act appropriately.

An optional buffering mechanism is avaiiable that can
draniai icaliy improve the performance of instniment,
communication (especially to VXIbus ins tnmi cuts). UTien
buffering is enabled on writes, chtu-acters sent to the
instnmitmt are buffered until an END indicator (or new-
line) is given and then the entire buffer Ls written to the
device. The END indi<*at.or for output data conesponds to
the end of a standard IEEE 488.2 piogram message.
Wlien buffering is enabled on reads, all characteis are
read from the device up to the EMD mdicator and buffered
in the controller. The END indicator for input data corre-
sponds to a complete IEEE 488.2 response message. The
controller then uses the buffer to satisfy data read
requests from the appbciition*

This buffering works fme with all IEEE 488.2 and SCTl-
based instniments. For older instnmients, buffering can
be disabled if it interferes with the inslmment/s functions.
The sizes of both read and write buffers can be set
indeix^ndently for each session so that tiie buffers can be
tuned for the requirements of individual instrumerus.
Finally, the read and write buffers are linked so that data
is flushed to and from the instnmient as appropriate to
maintain the IEEE 488.2 Message Exchange Protocol
synchronization.

36 Apiil i99£ Hewlett-Packard Jountal

)Copr. 1949-1998 Hewlett-Packard Co.

These formarting capabilities make it easy to talk to
\OQI>us and non-VXIbus instnmients.

Low-Level Interface

The low-level interface provides a nonformatted I/O
mechanisni that allows fast trans nussion of nonformatted
bmar>' strings. This mechanism, while it cannot be used
siniullaneoiisiy with the high-level interface, allows
greater control of the instrument I/O than the high-leveJ
interface. The low-fevel library routines allow sending
arbitrary data of arbitrary' length while controlling the END
indlcaton They also alJow data to be received and termi-
nated by a predetermined maximum count, an END indica-
tor, or an S-bit pattern character such as a line feed

These routines provide veiy tight control over I/O to a
particular instninientH allowing activities to be performed
that aren't possible with the lugh-le\'el interface. The
following low-level routines are a%^ailable:

• fwrite. Send a block of data to iui instrument. The END indi-
cator can he optionally set on the last byte.

• iread. Read an arbitraiy-length block of data from an
instrument. The read can be tenninated by the number of
bytes read, the END indicator, or a pattern character such
as a line feed. This routine will return Uie reason the read
terminated.

» rtermchr. Set the S-bil pattern character that causes an

iiead to temiinaie,
» inbwnte and inbread* These are the nonblocking equivalents

of iread and iwrite.

Memory Mapping and Register-Based Cards

The library provides routines to control register-b^ised
VXTbus cards and other memory-mapped devices. The imap
routine maps an arbitraiy^ section of VXIbiis memtjry into
iin application's data space and the routine rjnmap re-
moves memory mapping. Once a section of \^bus
memory is mapped into an application's data space, tiie
VXIbus memoiy can be accessed jusi like other parts of
the application's data space. In particular, normal C
pointer arithmetic can be used to read and write the
registers of VXIbus instruments.

Using register-based instnimenls this way allows extreme-
ly fast access to instmments from a measurement applica-
tion. This is becaij.se the operations needed to program a
register- based instnnnent are simply register reads and
writes— operations that lake microseconds to perform.
This is opposed to message-based instruments that
require several milliseconds to parse and execute the
requested ASCII commands, losing register-based devices
in this way, while not as easy as using a message-based
SCPI instrument, can allow measurements to complete 10
to 1000 times faster than message-based instruments.

The following program uses imap to talk to a VXIbus
register-basted voltmeter.

typedef unsigned short word:
struct dvm^dats {

word id;

wnrd devtype:

word Stat, ctd,

word offset;

word holdlS];

word range;

ward measure;

double result:
1;
main(K

mSJ dvm;

double res;

dvTTi_d3ta *dvrTtp;

/*Pnm message and terminate on error */
ionerrorfLERROR^EXITt;
ropert ttie voltnieter */
d vrr(- 10 pe n\ "" voltm eter" ):

/* Get pointer to registers */
dvmp=imap(dvTTTJ_MAP_VXIOEV,lJJ,0);

/* Set the range */
d vm p->ra n g e={bc3d4e :

r Take a measurement 7

dvmp->measure^1;

/* Wait for rt to complete */

wfiNe{dvmp->mea sure !=0);

/* Read the result 7

res=dvmp->resuli:

/* Print the results 7
printf("Resuit is %f\n'\res);
}

The followmg mapping options are available for imap:

• I_MAP_A16, Maps in a section of VXIbus A16 address
space.

■ l_MAP_A24. Maps in a section of VXIbus A24 address
space.

• (_MAP_A32. Maps in a section of \00biis A32 address
space.

» Lft/1AP_VX1DEV- Maps in the 64-byte device registers for the
given instrument. Tliese are the device configuration reg-
isters in A 16 space (see article on page 41).

► l_MAP_EXTEND. If the given device ha-^ A24 or A32 address
memory, then iliis routine tnaps in some portion of this
device's A24 and A82 address memory. The location of
this device's extended nienioiy is determined by reading
the identifier and offset registers in the device's 04-byte
device registers. Tins c^an be very useful in locating a de-
vice's A24 OT A32 address spare without having to refer to
conngiinition tables or resource manager files.

By using these routines, all or a portion of the given
address space can be mapped into a process at any given
time. However, hardw^are in Uie VXIbus controller can
limit the number of simultaneous mappir^gs availabie. This
is because of the limited number of mappUig windows
av^ailable in a given VXIbus controller. If an application
needs to work with several different controller tyiJes but
still wants to take advantage of as many map windows as
there are available on a given controtler, it needs to
modify' its mapping requests based on the hardware
resources available.

To get tliis information, the imapinfo routine is used. This
routine returns, for a given address space, the number of
map windows the hardware provides and the maxinnim
size of these windows. This information cm\ be used t)y
an application (,o manage the mapping and uninapping of
large chunks of VXIbus memory.

April imZ Hfiwlett-Puckctfd Journal 37

)Copr. 1949-1998 Hewlett-Packard Co.

Interrupts

Tlve VXH>us instrumerit library enables a process to he
mfomied of asynchronuus events happening on the
VXIbUK inlCTfaee. There are core internipt conditions that
can occur on any type of interface, and therp are inter-
rupt conditions spe{:ific for the gi%'cm Xype of interface
such as VTCRius. The following is the lis! of core interrupt
conditions and what tliey mean;

• STB. The conmiaiider just read a status byte.

• DEVCLR. The commander sent a de\ice clear.

• DARRIV. The commander has sen I data.

• OREO. Tlu* commander has read some data.

• I NT FACT. The interface has just become active. For V^bus,
Ihis means normal operation, and for tlie I IP-IB, this
me^ms that the instmnieni receives control of the bus.

• INTDEACT. The inlerfaee htis just l>e<*onie inactive. For VXI-
bus, ttiis means the instmment is no longer in normal
operation because of either a soft or a haixi reset . For tlie
I IP- IB, this means ttiat the instrument has piissed control
to imotticr mstrument.

• TRIG. A trigger has occurred. For VXIbus, this could be
any of t he TTL or ECL trigger lines.

The R>howiug intemipt conditions are VXlbus-specifit:

• LLOCK. A lock or clear lock word-serial coniniand [las ar-
rived.

• SIGMAL. A write to the signal register or an inteiriipt oc-
cuiTed from an application s VXibus servant dtHice, and
the value ret umetl indicates an event signal that the h-
brajy ditl not fumdle.

• VXI. An inteniipt occ^urred from a \^bus device that is
not one ofltie applications scnanls.

• SYSRESET. A VXIbus system reset has occun'cd.

A program can be set up either to wait for an interrupt
to occur, or to have a procedui'e executed when an
intemtpt arrives (or both). Ttie ionrntr, Isetintr, and iwaitridir
itjiitines work together to handle inteniipts. Also^ the
ionsrq routine can be used To process service rtNjuests
(SRHsj from a device. The* following prograiii liaiidies
interrupts.

^define on 1
?!fdefine off

void myhandlerflNST idjong reasonjong secH
printft/'An interrupt occurred l\n");
/* See what caused the interrupt */
switcMreasonK

esse l_INTR_TRIG:
/* sec' contains the trig */
r Nne that fired, */
break:
case l_INTR„VXI.SiGNAL:
/* 'sec' coniains the value */
/* written to the signal */
r register */
break;
case l_INTR_VXLVMEi
/* 'sec' contarns the 'iack' 7
/* value that was read while 7
/* acknowledging the VME 7
/* interrupt. 7
break;
}
}

matnJH
IMST dvm:

double res;

/* Print message and terminate on error 7

ionerrar(l_ERROR_EXtT);
/* Open the voltmeter 7

dvm=iopen("voltmeter");

r Install the interrupt handler 7
f n i ntri d vm ,mv handler);

/* Enable the appropriate interrupts 7
fseiintrjdvmJ_INTR_TRIG,

l_TRlG_nL2ll_TRIG_nL5);

isetintr! dvm,l_l MTR_VXLSI G NAUn);

isetintr(dvm,LINTR_VXI_VME,on);

/* Wait for an intsrrupt to occur 7
r with a 10 second timeout 7
iwaithdlr{10};

/* Continue wrth other processing 7

}

Besides the above capabUities, the iintron and iintroff
routines are available to disable intemipts globally. This
allows developers to create critical sections of code.
WTaen Int.ernipts are disabled with iintroff they are queuetl
until an iintron occurs. This pn^vents interrupt.s from beui^
lost during the exet^ution of critical sections. Also, t he
iwaithdir rotitine will automatic tilly recnablc inteinipts
when it is called. Using iintroff or iintron with iwaithdir allows
interrupts to be queiied tintil iwafthdlr is called, preventing
iwaithdir from missing an early inteiTUpt.

Multiproeess Locking

The instrument libraiy is designed to work on multipro-
cessing systems such as HP-LTX.'^' In such a system, many
programs can tr>^ to access a given de\1ce sirnulliuieously
which call cause instnuiient contention problems to
occur. To prevent such problems, a locking rnechanistn is
available. This locking rnecharvisni allows one process to
grab control of an instriimer^t aiid lock out other pro-
cesses.

The ilock routine will lock the gj^-en insinimt^nt or inter-
face to the calHng process. The calling I^ru( t^ss can
access the instnimenl or interface, but all other processes
will he prevented from accessing the instnmient or
tnteilace. The iunfock routine will remove a lock.

\Mien a process attempts to access an inslnniient that Ls
locked by another pi^ocess, one of two things will happen.
Either I lie call iLsed to access the instnunent will relum
an errcjr, or tlie call will block until the instrument is no
longer locked. The isetlockwart routine is used lo set the
action to be taken.

Error Handling

The instrument library provides a convenient mechanism
for hiuidling errors. This mechanism has substantial
advantages over other I/O libraries because error hantiiing
code is located away from the heart of the test prograjii.
This makes reading and understanding the test program
easier Topically in test programs error handling code is
iiUennixed with the test code as in the following test
program.

38 A^sril 1992 Hewtett-Packard Jounval

)Copr. 1949-1998 Hewlett-Packard Co.

matn(H
INST dvm:
double resp;
im res;

if<tdvm=mpenf"voltmeierl]==NULiH
printf("£rror oceurred in HjpBn\f**'|;
printt( " Error:%£\n ' J errorsfi errno] J;

}

res=iprJntf(-|VIEAS:VOLT:OC?\n'');

printfrEfror occurred in iprirFtf\n*'|;
prirttfl "Error %s\fi " J erro rsfrerm ol );
exrtfl);
]

res=(scanft"%r,&resp);
if(res<OH
printfC^Error occurred in iprintf\n*'l:
p ri ntff " E r ror : %s Vn " ,i e r fo r s|i errno j );
exitdl;
}

pnntff'Voitage is %f\n"',resp};
}
Notice that code is inserted after every I/O call to check
to make sure the call completed successfully. In this
exainple, il' an error occurs, a simple message is printed
along with the error that occurred and the program is
terminated.

A test program that uses the enhanced error handling
mechanism pro\ided by the instrument Ubraty would look
like:

mainfH
INST d\/m;
dQubJe resp;

/* Install an error handler */
/* Use a predefined one */
ionerroriLERROR.EXITh

dvm=iapen("voftmeter");

iprrntf["MEAS:VOLT:DC?\nl;

iscanfl '%f'\Sirespl;

printfi "Voltage is %f\n'\resp);
}
Notice that, no special error handling code is iiiserted
between 1/0 calls. Instead, a single line at the top (calling
bnerror) installs an error handler that gets called any time
an error occui^. In this example, a standard, system-de-
fmed eiTor handler is installed thai priuLs an error me-S-
sage and terminates. However, a user-supplied error
handling procedure can be specified as well. With this
enhar\ce<l error handling mechanism, not only does the
test program become shorter, bur it also becomes easier
to write, read, and understand.

If the tiser installs a custom error handler, the enor
handler is passed the en'or numljer that occurred and the
INST identifier of the session that generated the error.
With this information, the error handler can perfomT
actioas such as:

• Talking to the instrument to get more detailed error in-
fomiation

• Printing a reasonable error message based on the error
nuniber

• Setting a (lag that b checked by ibt* main program for
error conditions

• Using setjmp, lortgimp. or HP's try /recover mechanisms to
pass the error back to an error block within the main test
program

• Accessing session-specific data used by the main test
program using the isetdata and igetdata routines, which are
described below

• Attempting to recover from the error.

If the test program is compiled using an _AN'S1 C compiler,
then a debugging mode can be enabled that provides
more information to the error handler, such as:

• A string containing the name of the librai>' routine Uiat
created the error

• The name of the source file of the test program that con-
tained the call to the routine that failed

• The line number in the source file that contains the rou-
tine that failed,

UTien using the standard LERROR_EXIT error handler, this
information and the error that occurred are printed
before the apphcation is teiminated. This infonnation can
be extremely useful in tracking down how and where an
error occurred.

Other Functionality

The hbrai^^ contains many other routines that provide
more functionality, too many to discuss in this paper. The
following types of additional functionality are provided in
the library:

• Device and interface clear and reset functions

• Read and set ihe status byte (STB)

• Triggering activities

• Control cjf data transfer preferences such as DMA, polied^
and interrupt driven I/O

• Function timeouts

• Access to interface and device status infonnation.

The library also provides the isetdata and igetdata routines,
which allow a test application to ,store dtul retrieve
application-specific data. This data is stored and is
available on a session-specinc basis, so one pari of a test
program can store data that is used by another part of
the test program. This data can be stored and sorted on
an instrument -by-instrument basis. This is especially
useful for eiTor handler procedures and interrupt liandler
tirof'cdures. Any appUcation-specUic data can bc^ stored
with tile session, including things such as the instnm^eiit
statCj measurement statistics, and current svntch fixture
settings.

Putting it Together

The following program uses many of the features dis-
cussed in this paper It inciudes reading and writing,
register-based access, iniemjpts, locking, and error
htuidling.

^define on 1

#define nff
struct dvnri_ctal3 (

word rd;

word devtype,

word stat_ctrl;

word offset

word holdlSl;

ward range;

April 1 992 HewleJ r-Pai ■ ksird J mnTiiU 39

)Copr. 1949-1998 Hewlett-Packard Co.

word measure;
doubie result;
};
/*

* Error Handler
V

volatde mt error_escape^;
void errhdlrllNST idjnt error)f
/* try/recover/escape handling */
if(error_escape}
esc 3 pe{ error);
/* Otherwise, print and exit */
pnntf("ERROB Occurred!\n");
printf( "Error: %sVn"Jerror[errorlh
printf( "Filename: %s\n ",de huQ_f ile};
printf("Unenum=%d\n",dehug_line};
exil{1);
}

volatile unsigned short vmeiack;
void intrhdIrONST id, long reasonjong secH
/* See if it was a VME interrupt */
if(^eason==l_I^^TR_VXI_VMEK

vmeiack=sec;
)else{

printf{" Invalid lnterrupt\n");
exrt(1);
}
}
main(K

INST src,dvml,dvm2;
dvm^data *dvm2p"
double voft.amp;

/* Install error handler */
ionerrarlerrhdErl;

/* Open the devices */
src^iopen("source"l;
d vm 1 =i D p e n ( " vo Itm ete r " );
dvm2=iopen| "ammeter" I;

r Lock the instruments */

ilocM^rc);

i 1 c k( d V m 0; i io c k( d vm2h

/* Get registers for register-based 7
r ammeter 7
dvm2p=imap(dvmJ_MAP_VXIDEVAU0);

/* Setup an interrupt handler */

/* for register based ammeter 7

ionintr(dvm2,intrhdlr);

isetintrl d vm2j_l NTR_VXi_VM E.on );

/* Turn on the source 7
r Catch error if occurred '/
tfyi

errDr^esc3pe-1:

iprintf(srcrSOUR:0!SABLE\n'*j;

fprintf(src,"SOUR:FREQ lOO^n"^;

iprintf{srcrSOUR:AMP 25\n"};

iprintf(sfc;'SOUR:WIDTH 20\n");

iprintf(sfcrSOUR:DURATION 30\nl;

iprintftsrc.'^SOUR:ENABLE\n'');
}recovef{

printfrCan'l set up SQiirce\n''):

printfCContinuing with test\n"};

iprintffsrc;'S0UR:RESET\n1;
}
error_escape=0;

/* Take voitage reading 7

/* Terminate tf error occurs */

ipromptf(dvmi;'MEAS:VOLT:DC?\n"r%f,&volt);

/• Take current reading 7

/* Device is register- based */

iintroffOn /" Set up critical section */

dvm2p->range-0xl5d2,

dvm2p->measure=l;

vmeiack=0:

whiie(vmeieck==OH

fwaithdIrtO);/* Wait for interrupt! 7
)

iintronl}; /* Finish crilfcal section 7
amp=dvm2p->result;

r prim the results */
printf{ "Voitage = %f\n",voit);
printfC'Current = %f\n".amp);

}

Conclusion

This library represents a ni^or improvement over pre-
\ious I/O library designs. Unlike many other libraricSt it
pro%itles features and ease of use required s]3ecificaily for
instrument control. With this hbrary, any test engineer
familiar with the C programming language can rapidly
create fast, efficient test applications that are easy To
understand and support.

HP-UX is based on and is CDrnpaiiblG wuii UNIX Svstem tabor atones' UNIX' opeiatmg systEm

It also complies with X/Open's* XPG3, POSIX 1003. t and SVIDZ interface specifics tiDns.

UNIX ts a regisEef&d t^ademairtt or UNIX Sys^tem Laboratories inc. in tiie U.S.A. and cither

countfies

X/Open is 3 trademark of X/Open Company Limited \n the UK and other countries.

40 April 1992 Hewlett-Packarti Journ^

)Copr. 1949-1998 Hewlett-Packard Co.

Achieving High Throughput with
Register-Based Dense Matrix Relay
Modules

With an onboard FIFO buffer and register-based programming, HPs VXIbos
dense matrix relay modules provide high throughput and a downsized,
low-cost solution to matrix switching.

By Sam S, Tsai and James B. Durr

Matrix switching, througl:\ whicli several instnmients can
be connected to multiple devices under test (DUT^)
selectively, is a popular switching teclinique used in
electronic test. In traditional rack-and-slaek systems,
matrix switching requires large ainoutUs of mck space
and is costly because of the ainomU of hardware re-
quired. The HP E1465A. HP E1466A, and HP E1467A
dense matrix relay modules described in this article
provide a do\^Ti sized, low-cost solution to matrix switch-
ing. These VXIhus matrix switching niodules each occupy
one C-size VXTbus mainframe sk)t, and witii 256 relays
per module are one of the higliest-densily switch modules
available.

These devices are suited for \^XIbus reglster-hased sys-
tems and register-based pjogramming. In addition lo their
design, this article covers relay module programming aiul
provides benchmarks of throughput speeds achieved with
ASCII nicssage-based and regisler-based programs.

Dease Matrix Relay Modules

The dense nmtrix relay module shown in Fig. 1 Is a
tw^O'Wire, 256 tme rrosspoint matrix switch. True cross-
point means tliat any row" can be connected to any
colmmi simultaneously. In this design, four 4-by-16 subma-
trices have been implemented on the main printed circuit
board with 256 latching relays. Tenmnal cards convert the
submatrices into 4-by~*34 (IIP EM66AJ. 8-by-:32 (HP
E14G7AJ, or 16-by-16 (IIP E1465A} matrices. The tennmal
card also provides screw terminals to connecting the
OUT,

Latching Relays

Til ere are several advantages to using laictung relays.
First, with 256 relays on the dense matrix module,
latching relays prevent excessive current from the power
supply if tlie user closes too many relays accidentally.
Second, energy is saved since power is not continually

Fig. i. A dense matrix relay
nuxlulo.

April 1992 Hc^wlplt-Packard Jonnml 41

)Copr. 1949-1998 Hewlett-Packard Co.

applied lo keep a latching relay closed. Third, because
power rs not continually applied, the relay coil does not
heat up. Tliis is iniportant because llie two metal contacts
inside the relay in effect fonn a iht^miocouple. Thus,
tempeialure diiierences on the relay crontacts c:ause a
themiai EMF lo be generated. Also, the life of the latch-
ing relay Is usually longer than the nonlatching relay
becaiise of the power thai must he continually applied to
close a nonlatching relay.

The priniaiy disath-^intage of latch in j* relays is thai the
relay stale Is ui] changed at power-on, power-off, or reset.
Therefore, the device's firmware must ensure that all
relays are open following these conditions.

Matrix Topology

An exainijle of the relay module's matrix arrangement is
shown in Fig. 2. Represented is the matrix for I tie HP
E1467A 8-hy-:32 flense n^atnx relay motlule. The 84jy-32
matrix is fonned by connecting together the rows of
suhmatrices A and C, the rows of submatrices B and L),
the c olurnns of submatrices A and B, ^md the columns of
submatrices C aiRt D,

On the 8-by-32 dense matrix relay module, the rows in
siibnr a trices A and C aie rows tlirough 3. and tiie row^s
in submatrices B and D aie rows 4 through 7. The
columns in submatrices A and B are columns througli
15, and the columns in submatrices C' and D are columns
16 through :U.

mgh-Throughput Design

In con%^en1ional \lQbiis switch module designs, the
module interrupts its commander's CPU each time a relay
is opened or closed. The interrupts cause the CPU to
take more time to service other instruments, which
decreases system throughput. The dense matrix relay
modides make efficient use of the CPU by lncon>oratmg
first -in- first-out (FIFO) memoiy blocks. When a function
and channel list are sent to the relay module, botJi are
dow^iloaded into the FIFO memory- The CPU is then free
to do other tasks. Only afier the last channel in the list is
opened (or closed 1 is the CFt^ interrupted.

To show^ the advantage of the FIFO buffer consider a
reset of the switch module. Following the reset, each
channel relay must be open. Because lal clung relays are
used, firmw^are must write data to each channel to ensure
that it is open. V\lthout the FITO memory, the CPLT would
be intermpted 256 times (once for each relay) during the
reset sequence.

How the Dense Matrix Relay Module Functions

Fig, 32 ami the following sequence describe how the
switch relay module operates:
A command is sent to the rielay module and stored in
FIFO memory.

Once the data is in memory, the \TVIEbus timing PAL (pro-
grammable array logic) asserts the signal DTACK*. This
signals the CPU on the relay module s commander that it
is now free to service other instruments.

• The VMEbus timing PAL signals the FIFO interface PAL
to execute the commatid. During exeeution, the data bus
FIFO Empty* flag signals the FIFO interface PAL to read

I he fitita l>us and address bus FIFOs and generate 7-ms
IRilses to acHvate the relays. Only one 7-nis pulse is re-
quired per relay bank (16 relays}*

• The FIFO Inlerrace PAL reads the data bus and address
bus FIFOs iiniih he Empty* flag signals the FIFO interiace
PAL thai llu^ FIFO memor>' is empty,

• When the MFfJ is empty, the FIFO iiUerface 1*AL signals
I he VMI^^bus tuning PAL which asserts IRQc- This inter-
njj "ih (he command module CPU after the last relay has
[ks ri activated.

Because the relay module only asserts IRQ* after the last
relay is activated, the (^PU is not continually interrupted,
thus enhancing system throughput.

Programming the Dense Matrix Relay Modules

In a VXlbus system tliere art^ mess age -based and register-
based devices. Message-based devices have an onboard
microproc*essor, which interprets ASCII conmiand strings
and returns ASCII formatted results. Register-based
devices, such ys thc^ dense matrix relay mfulules, do not
Iiave an onboard processor Conunmiication with tliese
devices is tfirougb access to the device registers. How the
registers are accessed affects system tfiroughpuL

SCPI Programming

One way ft) |>rogram the dense matrix relay moduU^s is
with higli-level SCPI (Stantlard Connuantls tor Program-
mable Instnjments) cotrmiands. SCPI is an ASCII-based
instrument comtiiand language designed for electronic test
and measurement instnnnents (see the article on page 15
for a discussion of SCPI conmiands). SCPI defmes stan-
dard sets of commands that allow different devices doing
the same fimctions to be programmed with the same
commantls.

Programming the relay modules with SCPI conunands
requires the HP El 40.^ conunand module. Instrument
drivers in the command module convert the SCPI com-
mands to register "peeks" and "pokes." The command
module eriables the relay modules to be progranmied the
same as message-based devices.

In a program using SCPI commands, a relay module
command is sent over the HP-IB to the command module
(Fig. 4}. The command statement includes the relay
module's HP-tB address, the command, and the data. The
format of a tj^ical statement is

OUTPUT 7O908:TLQS [©lOOOOr.

w^hich is a conmiand from an HP 9000 Scries 200 or 300
computer {select code ?) to the relay module at HP-IB
secoadar>' address S \ia the HP EI 405 t^onunand module
at the IIPTB primary address 9. (For HP VXlbus systems,
the HP-IB secondary address is defmed as tJie logical
address di\ided by 8.)

42 Apn\ 1992 Hewlett-Packaxd Jounml

)Copr. 1949-1998 Hewlett-Packard Co.

Matrix Mculule

Tflmtinal Block

Column OH

////////////////

BBnki

n2iM^ 120T him ^%m\m i2ob W' 1291 ■ tan' 'laos ^mo' ^1211' "^lair 1213 'izm^i

C-C C C C iLC^^L C^C CCC C C- i

r 1^ i"^ i^ ^*^ ^*^ fC^^ ^*^ (j^ 4^ ^^ r r (^ ^

\im 1401^401 1404 M40i M4W 14OT 1«» '^t4« 14tfl MII1*^1411 ^1413 1414 1

j^J^^"^ ^<f jr~J^J^J^J^^<f ^<f i"^ jji'^ ^"^

Fig, 2. An 8'by-32 rel^ matrix topology.

April 1 092 He wlett-Paicrkaid J oiin lal 43

)Copr. 1949-1998 Hewlett-Packard Co.

Power

Address

System
Rese{ and

Status and
CoMlrol
Register

_n_

Latching
Relay

Power

Ground

Fig, 3. Pujiinionai block diagram

for the HP EJ46E^A, HP E1466A,
and HP El4ti7A dense niatrix
relay modulei^.

The comiTiand module's HP-IB driver stores the ASCII
text CLOS {©10000 J in tlie input buffer of the relay module,
and signals the parser that the input has a command to
be parsed (interpreted). The command (CLOS) is reduced
to a call (with a parameter of lOOQO) to a routine that
writes register data to the F[p'0 meniorj' on the relay
card.

The SCPi commands most often used with the relay
modules are:

lROUTe:]CLOSe (©channeljist)
IROUTe:]OPEN (©chanreljist)
iROUTe:iSCAN (©channeljst)

Channel lists are specified m the format nrrcc:nrrcc

where:

n = relay module number. The module number is
based on the module's logical address and the num-
ber of modules being progranuned. For example, if a
switchbox instrument contains three relay modules
(which must have consecutive logical addresses), the
module wi\h the lowest logical address is module
number 1. The module with the next lowest logical
address is module number 2, and so on.

rr =the row to be connected to column cc,
cc =the column to be connected to row rr.

For example, on relay module I, to scan row column 4
through row column 8 (relays 4 through 8 in Rg. 2),
the channel would be specified as;

SCAN i@10004):(1D008^

Note that the nrrccmrrcc format was Implemented before
the format currently used by the SCPI standard:
n(rrtcc:rr!cc).

SCPI Advantages and Disadvantages

The advantage of programming the relay modules with
SCPI commands is that this instrument language is

conmion to all HP matrix relay modules and easy to
understand. Also, the user only needs to specify a module
number row, and eoiiunn to comiect a row to a column.

The disadvantage of SCPI programming is decreased
throughput because of command parsing by the HP E1405
command module, Iloweveri as the benchmark programs
will show, the speed of the IIP E1405 commatid int^erpret-
er is such that significant throughput gains are only
achieved by eliminating command parsing witJi direct
register access over the VXJbus backplane.

Register-based programming accesses the device registers
directly (Fig. 5). Register programming increases through-
put since it eliminates SCPI command parsing by the
command module.

Locating the Registers. Register addresses for register-based
devices are locateii in the upper 25% of the \^XIbus A16

External
Corttrdller

HP IS

SCPI CDmmafids

Coitim«nri WInriiile

Binary Register Oats

Oetise Maitiic
Relay Module

Fig. 4* SCPI communication path to the dense matrix relay mod-
ules.

44 April 1992 Hewi&tt-Packard Jotirnal

)Copr. 1949-1998 Hewlett-Packard Co.

HP-IB

SCPI ComiTtands

VXIbus

Sinary

HPEi40S
Commanij Modiitc

VXJbus

Slnarr flaglstsr Data

CommgiilcQtion

Petti

Rttsy Module

Fig. 5, Register programndng communication path Lo the dense
matrix relay modules,

address space in the embedded controller or the con^
mand moduJe. Every VXlbus device (up to 256 per
system) is allocated a 04-byte block of addresses. De-
pending on the number of registers a device has, the
device niay not use all the addresses. Fig. 6 shows how
register addresses are mapped into the A 16 address
spaces of the HP EHSOA V7360 embedded controller and
the HP EI 405 command module.

When programming a rei^ster-based device, a hexadecimal
or decimal register adciress is specified. The register
address is defmed as:

The Base Address. The base address used to determine the
register address depends on the location of the A16
address space. If an embedded controller such as the HP
E148(JA V/3eO controUer (Fig. 6a) is used, the base
address is computed as:

COOOh + (imm x 64)h

49,152 ^ (UDOR x 54)

where COOOh (49,152) is the starting location of the

register addresses in the embedded controller's A16
address space, lADDR is the logical address of the register-
based device, and 64 is the number of address bytes per
device.

If an HP El 405 command module (Mg. 6b) is used, the
base address is computed as:

IFCOOOh 4^ (tADDR x 64)h

2,080,768 + (LADDR X 64)

w-here IFCOOOh r2,080J68) is the starting location of the
register addresses in the IIP E1405 A 16 address space,
LADDR is the logical address of the register-based device,
and (54 is the number of address bytes per device.

The Register Offset. The register offset is the register's
location in the block of 64 address bytes in the A 16
address space. Table 1 lists the register offsets of tlie
dense matrix relay mtjdulcs.

Addres!> Map

FFFh

ami

149,152}

DescrJptiDn

3Eli

3€li

Gi-byte Raaiater Map

ia)

FFFFFfh

Address Map

1fCCK3Eh

Regisier
Addriisii^es

iFCOOQh
(2.090,768}

Off'.l l>W-:Hpl«e«

3£li
3Ch

OCh

DAh

06h

04 K

Stnliis^anrrai Reflrslar

02li

Dgvpcq Type R^gi^tef

ooii

(d(?nlificatmn Ruf islor

64-byte Rflgistar Map

Fig. 6. Register mapping within
the A16 address space, (a] A16
address mapping for flie HP
1480A W/Sm controller (b) A16
address mapping for the HP 1405
command module.

April 1&92 Rewiett-Packard Journal 45

)Copr. 1949-1998 Hewlett-Packard Co.

When specifying the bank on which to close a relay to
connect a row to a column, the offset is added to the
base address to form the complete register address^ For
example, assuming the Alfi address space is inside the
HP 1480A V/360 embedded controher, the logical address
of the relay module is 64, and the relay is on bank 0, the
complete register addresses is:

Taiile l
Register Offsets in the Matrix Retay Modules

Begistei
Offset

Read/
Write

Description

3Eh

Relay Driver

Write

Bank 15

3Ch

Relay Driver

Write

Bank 14

3Ah

Relay Driver

Write

Bank 13

3Sh

Relay Driver

Write

Bank 12

3^1

Relay Driver

Write

Bank 11

34h

Relay Driver

Write

Bank 10

32h

Relay Driver

Write

Bank 9

3€h

Relay Driver

Write

BankB

2Eh

Relay Driver

Write

Bank?

2Ch

Relay Driver

Write

Bank 6

2Ah

Relay Driver

Write

Banks

28h

Relay Driver

Write

Bank 4

26h

Relay Driver

Write

Bank 3

24h

Relay Driver

Write

Bank 2

22h

Relay Driver

Write

Bankl

20h

Relay Driver

Write

BankO

ie:f:

N/A

04h

Status/Control

Read/
Write

Module
Status/Control

02h

Device IVpe

Read

Device IVpe

OOh

Identification

Read

Manufacturer's

Identification

Number

** Register Offsets 06h, 08h, OAh, OCh, OEh, OlOh, 12h, 14h,
16h, lah, lAli, ICh, lEh

Register Data. The base address and register offset specify
a register's location in A16, Programming the relay
modules at the register level also requires that the data
that opens or closes the relay be sent. There are 16
relays on each bank on the dense matrix relay modules
(see Fig. 2). These relays have corresponding bil values
of 2*^ through 2*'^. For example, to specify^ relay 05, 32

(2^) or 20h would be the data v^alue sent. Similarly, to
specify a!l 16 relays on a bank, -1 (65,535) or FFFFli
would be sent,

Register-Sesed Commands, The commands used to program
the relay module depend on die controller used. The
commands used in the benchmark programs given later in
this article include:

WRITEIO <setect code>,<register_number>,cregister data>

and

Dl AGnnstic: POKE <address>,<w(dtli>,<data>.

WRJTEID is used with the HP V/360 controller and HP
E1405 IBASIC (Instrument BASIC). For example, execut-
ing:

WRITEtO -16, Register_numt}Br.t

on the V/360 writes one word of data on the VXlbus
baekphme (select code -16) to close the relay whose
address (and bank offset) are specified by the variable
Register.number. Executing the conmtand from IBASlC
closes the relay whose addrejss Ls specified by the vari-
able Re gister_ad dress:

WRITEIO -9326,Register^address.l

D I AG: POKE is an SCPI command that allows users t^)
program the relay module registers without using an
embedded controller. This command is executed by the
HP E1405 conunand module. For example, the statement

OUTPUT 7Q900;"D]AG:POKE #HlFOO20,16,r^

closes relay on bank of the relay module.

The command module parses the command header
DIAG:POKE. llov^ever, the register addiess and data are
written direcUy to the relay modide's FIFO memory.

Advantages a ltd Disadvantages. The primar>^ advantage of
register-based programming is increased throughput,
which is achieved by elijuinating SCPI command parsing
and accessing registers from the VXlbus backplane.

The disadvantage of register-based programnuiig is that
programming at a manufacturer-specific binary level often
causes the programs to be more complex than SCPI
progi-ams. Unlike specifying a relay module number, row,
and colunm in an SCTl program, the register-based
programs require the programmer to specity a register
address, offset, and weighted bit (channel) vaJue.

Benchmark Programs

The following programs measure throughput speed, which
is defined here as the time r^quhvd to send a cofmfKtnd
to the dense rnatrh: relay module and for a reifty to
dose. The programs, written as they might appear m an
actual test system, compare typical ihrougliput speeds
obtained using SCPI ajid register-based programs with
different controllers and programming languages. Table 11
summarizes the throughput speeds.

46 April 1962 HewIett-^PackHid Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Table 11

Throughpyt

SummarY

Controller

Command

Pro-

Command

Module

gram

Execu-
tion
Time*

HPE14S(JA

—

WfilTEIO

7.3 n\s

HPE1480A

E1406

DIAGPOKE

15.0 ms

HP E14S0A

HP
E1405

13.5 ms

HP 9000 Model

OIAG:PQKE

20.0 ms

217

E1405

HP 90(K) Model

15.0 nis

217

E1405

HP 9000 Model

DIAGiPCKE

15.0 ms

370

El 405

HP 9000 Model

IIP

13.0 ms

370

El 405

HP E1405/TBASIC

—

WRITEm

8.5 nis

HP E1405/IBASIC

—

OIAG:POKE

23.0 ms

HP E1405/1BASIC

—

16.5 ms

HPVectra/T\irbo

OIAG:POKE

10.0 ms

C++

EI 405

HP Vectra/Turbo

13.0 ms

C++

E1405

HPE1480A/

^ij:

8.6 ms

HP-UX 7,0

IfP E1430A V/360 (Slot Q.
sn6 E&sflurce Manager I

*Each benchmark includes 7-ms busy time required for
tlie relay to close and settle. (One 7-ms busy lime is re-
quired per relay hank.)

''^^Direct register access in a multitasking system.

The highest throughput is arhieved when SCPI ronmiand
parsing is eliminated. This oc:€urs when the relay n\od-
ule's FIFO memoi>^ is accessed directly via WRITE! from
tiie VXIbus backplane with an embedded controller or
with I BASIC Note that register-based programming using
DIAGiPOKE offei-s Utile If any throughput advantage over
the high-level CLOSe command. This is because of the
command modules fast command parser.

Benchmark 1

• Configuration: Fig. 7.

• Command: WRITEIO <select code>,<register numbers

<rBgiste: d3t3>

• Language: HPBASlC/WSaO

• Program:

10 CONTROL 16,25;2 I Map the W360 A1B addr. space for WRITEIO

20 8ase_addr=DVAL("D0O0M6) IConvert base address to a REAL

30 [number

40 Reg_addr=Base_addr+32 !Add register offset, ^ore registei

50 [address

60 INTEGER I

70 Tl^TIMEDATE !Tlme WRITEIO

ao FOR 1=1 TO too

ielay Module HP 1466A
4 X 64 Matnir Switch
(Logic i I Address G4}

Ottfcr Modifies

HP S133 Disk Drive

Pig. 7* Gonfifiuration for bencJmiark L

90 WRITEIO -16,Reg_addr;l [Connect row to column on bank

100 REPEAT

no UNTIL B[T(REAOIOt-16,Base_addr+4j,7) [Monitor relay card status

120 ! register bit 7 (busy bit) to determine when relay is closed

130 NEXT I

140TZ-TIMEDATE

150 PRINT 'V/360 (WRITEID): ";((T2-Tn/lOO.n.Ei-3rms"

160 ! Compute time

170 END

Result: V/360 fWRITElO): 7.2093046875 ms

Benchmark 2

Configuration: F^g. B.

C omman d : D [ AG nostie : P K E <add ras5>,< vyicfth>,<data>

Language: HP BASICAVS 6.0.

Program:

10 INTEGER I

20 ASSIGN ©Comm TO 70900

[Declare loop counter variable
[Assign I/O path

E mbad de d Ca ntro I ler H P ! 405

HP E148DA V/3ea {Slat 0, Command

and Resource Manager) Module

i -»

Relay Module HP 1466A
4 -^ $4 Matriif Switch
{Lafical Address 64)

Other Modules

Mainframt

Slots to 3

HP 9133 &iilt Drive
Fig- 8, Gorifiguratinn for tjcnchmarks 2 and 3,

April 1 992 Hewlett-Packard Journal 47

)Copr. 1949-1998 Hewlett-Packard Co.

Relay Module HP 1466A
4 ■-■ 64 Matrix Switch
(Logical Address €4)

Other Modules

HP 9000 Model 217

or
HP SOW Model JJH

SlDlO

HP-IB
Fig. 9, Configuration for benchmarks 4, 5h 6. ^d 7.

30 Tl^TIMEDATE ITlme OIAG;POKE

40 FOR \=] TO 10

50 OUTPUT @Comm;"DIAG:POKE #H1FD020J6,1" ! Connect row to

GO ! column on bank statjs bit 7 {busy).

70 REPEAT

80 OUTPUT ig!CDmm;"OIAG:PEEK? #H1FDD04J6" IMonitor relav card

90 [to determine when the relay is closed

100 ENTER @Comm;Status

no UNTIL BIT(StatLJS.7)

120 NEXT I

130 T2=TIME0ATE

140 PRINT "V/360 iDIAG:POKE}: ^;(IT2-Tl)/10.n.E+3rms" ICompute time

150 END

• Result: V/360 IDfAGiPOKE); 14.9993896484 ms

Benchmark 3

• Configuration: Fig. 8.

• Command: [ROUT:]GLOS (®channeljist^

• Language: HP BASICAVS 6.0.

• Program:

[Deciare loop counter varrabli
[Assign ]/0 path

10 INTEGER i

20 ASSIGN ©Switch TO 70908

30 Tl-TIMEDATE ITlmi CLOS

40 FDR 1 = 1 TO 10

50 OUTPUT @Switch;"CLDS (@10000|;*OPC?" IConnect row lo

60 IcolLmn on bank and Wait for relay to close (*OPC?)

70 ENTER @Switch;A

80 OUTPUT ©Switch;^' OPEN (@10OOO);*OPC'^ I Wait for relay to open

90 ENTER @Switch;A

lOD NEXT I

nOT2=TIMEDATE

120 PRINT 'V/360(CL0S C0MMAND|:";({T2-Tl|/20rTE*3;"ms" ICompute

130 ITime

140 END

• Result: V/360 ICLOS COMMANDh 114994506836 ms

Benchmark 4

• Connguration: Fig. 9.

• Command: DIAG: POKE <address>,<:width>,<data>

• Unguage: HP B.^SICA^^S G.O.

• Program: The saiiie as benchmark 2 except for line 140.

140 PRINT "217/B6 (DIAG;PDK£}: ":|[T2-T1)/10)*1 E+3fms"

• Result: 217/B6jDIAe:P0KE}: 19.9981689453 ms

Benchmark 5

• Configuration: Fig. 9.

• Coniniaiid: [ROUTjCLOS (©channeljtsi)

• Unguage: HP BASIC:WS 6.0

• Program: The same as benchmark 3 except for line 130.

130 PRINT "217/B6 SCPI (CLOS COMMAND): ";(|T2-Tl)/20.ri.E+3;"'ms^^

• ResuJf: 217/Be SCPI ICLDS COMMAND}: 15.0009155273 ms

Benchmark 6

• Configuration: Fig. 9.

• Corrmiaiid: D1AGnostic:P0KE<address>,<width>,<data>

• Language: IIP BASICAVS 6,0

• Program: Same as benchmark 2 except for line 130.

140 PRINT "Zn/WS (DIA6:P0ICE): ";((T2"Tl)/104*1.E+3rms"

• Result: 370/WS (0IAG:PDKE|: 149993896484 ms

Benchmark 7

• ConOguralinn: Fig. 9.

• Command: [RDUT:]GLOSf@channei_list)

• Language: HP BASICMS iySl

• Program: The same ajs benchmark 3 except for line 120.

120 PRINT "37CVWS SCPI (CLOS COMMAND): ^{(T2-Tl)/20.ri.E+3;"ms"

• Result: 370/WS SCPI ICLOS COMMAND): 13.0004882813 ms

Benchmark S

• ConHguration: Fig. 10.

• Command: WRITEIO <select code>,<register number>,cregister
data>

• Language: HP IBASIC

• Program:

10 INTEGER I \ Declare loop counter variable

20 Base_3ddr=OVALnFD0O0 M6) IConvert base address to a REAL

30 'number

40 Reg_addr^Base„3ddr+32 !Add register offset, store register address

50 Tl-TIMEDATE ITime WRITEIO

60 FOR Ul TO 100

70 WRITEIO -9826,Reg_addr;l (Connect row to column on bank

80 REPEAT

HP 1405

CDminand

Module with

IBASIC

H0fay Module HP 1466A
4x64MBtn}(Sw9tcli
I Logical Address 64]

- Other Modules

Slot!}

Fig. 10, Configuration for bejidunarks 8» 9, and IQ.

48 April 1992 Hewlett-Packard Jounml

)Copr. 1949-1998 Hewlett-Packard Co.

30 UNTIL eiT(REA0IQ(-%26,Base_addr^}J) IMonltOf relay card status
TOO 1 register bit 7 fbusyf m deiermme v^wf\ tfit relay is closed

T20 T2=TIME0ATE

130 PRINT "JBASICfWRITEIOh ';in"2-T1|/lflO,rTE+3rms" ICompufe time

140 END

• Result: IBASIC(WRITEIO); 8-49975585338 ms

Benchmark 9^

• Configuration: Fig. 10.

• Command: D[AG;POKE <address>,<widtli>,<data>

• I^igiiage: HP IBASIC.

• Program: Same as benchinark 2 except for lines 20 and
140.

20 ASSIGN @Comm TO BO9O0. 'Assign I/O path

140 PRINT "IBASIC (Dl AG 'POKE): ";(rr2-Tn/lQO)*10OO,f ms^^

• Result: IBASIC (OIAG:POKE):21Q009765625ms

Benchmark 10

• Configuration: Fig. 10,

• Command: [ROUT:]CLDS (©channeljist)

• Language: HP IBASIC.

• Program: Same as benchmark 3 except for lines 20 and
120,

20 ASSIGN ^Switch TO 80908. I Assign I/O path

120 PRINT 'IBASIC (CtOS COMMAND): ":f[T2 Tl J/20, n 000.;" ms"

• Result: IBASIC jCtOS COMMAND): 16,4993286133 ms

Benchmark 11

• Configuration: Fig. II

• Command: OtAGn:POKE<address>,<width>,<d3ta>

• Language: Borland T\irbo C++- Version LO.

• Program:

r Include the following header fites 7

^include <stdio.h>

#rnclude <string,h>

/include ctime.h>

/include <chpib.h> /* File is in HP-f8 command Irbrary */

rfinctude <cfunc.h> /* File is in HP-IB cammand library 7

/• Defines the cominend module HP-IB addfess 7
Idefine ADDR 709001

Relav Moriule HP t46fiA
4 X 64 Matrix Switch
(Logkal Address 64|

Other Modules

/* Defines the relay imidules register address 7
/define D1AG_DUT ''DlAG:POKE #H1FD020,16J"
/define DIAGJN "DlAGrPEEK? /H1FO004J6'

int mainlvoid]

}

time_t

float

Tl, T2:

loop;

ifih:_status. last status = 0,;

r Set HP-18 timeout for error checking */
errDr_handier (lOTIMEOUT (7U5.0J. "TIMEOUT"J;

/* Get irtrtial status bit value 7
error_handlBJilOOUTPUTSfAODa DIAGJN. strlBn{01AG_IN|l

"OLiTPUT command");
efrQr_handler{IOENTER{ADDR. &inrt_statusl "ENTER command" J;

/* Determine initial time of test 7
Tl = time(NUtt);

/* Start to op to determine time 7
fcr {loop = 1; loop <= 1000: loop ++)
{

/* Close relay for each loop 7
error^handlerflQOUTP[JTS(ADDR, DfAG.OUT

stFlen(DIAG_OUT)), "OUTPUT command");

/* Determine if relay is closed before executing next loop7
while(tintt_status - iast_status| \= 128)
{

/* Read status value 7

error^handlerj 10 DUTPUTSiAOOR, DIAGJN,

strlentDlAG IN)), 'OUTPUT command");
errDr_handler[IO£NTEfi(ADDR, Stlast^status), 'ENTER
command");
)
r Reset the status value for nexT loop 7

Iast_st3tus = 0.;
}

/* Determine time at end of test 7
T2 = timefNULL);

/* Calculate and display test time 7

printfrTime = %f seconds", (dtfftime(T2Jl) / lOOO));

return 0;

/* Error checking routine */
Int error_handler {int error, char *routine}
{

char ch;
if terror !
{

NOERR)

prlntf {"\n Error %d %s \n", error, errstrlerrorJh
printf C in call to HP-IB function %s \n\n", rotrtine);

printf ('Press 'Enter' to exit: ");

scant f"%c'', Sch);

exitfO):

1
return 0;

}

• Result: Time - 0.010000 seconds

HP Vactra Computer Mith
ait HP e23a5 HP-18 Card

SlotO

Fig* IL f ItjufigufaLiorr far tx^ncfunarks 11 /ind 12.

April 1992 Hcwleti-Paokard Journal 49

)Copr. 1949-1998 Hewlett-Packard Co.

Bertehmarlc 12

• Configiiraticm: Fig. 11.

• Conimand: [ROUT:]CLOS {©channeljist)

• Lariguage: Borland Turbo C++ Version 1.0.

• Program:

/• Include the fallowing header files */

^include <stdio.h>
^incfude <tjfne,h>
#include <chpib,h>

/* Defines the relay module HP-iB address*/
#defTne ADDR 70908L

/*■ Defines the relay open coftimand 7
^define SCPLCLOSE ' CLOS (®10000};*OPC?"
^define SCPI_OPEN "OPEN {@10000);^OPC''^

int main(\/oid)
t

tinie_t Tl, T2;

int loop, length = 5;

char into[B];

/* Set HP-IB timeout for error checking 7
ermr.handler UOTIMEOUT (7U5.0h TlMEOUr);

r Deiermine inEtial lime of lest 7
T1 = timelNULL);

r Start loop to determine time 7
for (loop " 1; loop <= 500; loop ++)
{
errof_handler(IOOUTPUTS(AODR, SCPLCLOSE,

strlen(SCPI_CLOSE)L 'OUTPUT command");
error_handler(iOENTERS(ADDR, into. &length),

'ENTER command"!:
errof_handler|IOOUTPUTSfADDR, SCPI_OPEN,
strlen(SCP!_OPEN)). "OUTPUT command"!;
error_handJer|10ENTERS(ADDR, rnto, SiJength).
""ENTER command"):

)

/* Determine time at end of test 7
T2 = time! NULL);

r Calculate and display test time 7

prmtfC'Time = %f seconds", (difftime(T2Jl} / 1000)1;

Embedded CoEitroller
ttP £14S0A {V/3G4). Sbt 0,
and Resource Manaf er!

Rdsy Modute HP 14fi6A
4 '■ 64 Matrix Switch
(Logical Address fi4}

Otfier hlfoddes

UN #

HP 9133 Dfsl( Drive
Fig. 12, Configuration for benchmark 13.

Benchmark 13

• Configuration: Fig. 12.

* Command: Direct register access*

• Language: C,

* Program:

return 0:

finclude

<t[me.h>

#inclLde

"sys/vxi.h"

#include

#inciude

#defrr)e U 64

#define looptimes S.O

mainO f

int Stat;

int fd;

int i;

int j;

}

/* Error checking routine 7
tnt error_hindler lint error, char *routine)
{

char ch;

if (error 1= NOERR)
{

printf {"\r\ Error %d %s Vn", error, err str| error));

printf (" in call to HP-IB function %s \n\n", routine);

printf rPress 'Enter' to exit: "S;

scant r%c", &ch};

exit(O);

}
return 0;

struct dev_regs {

jnstgned short id_reg,
unsigned short device_type;
unsigned short statLis_reg;
ynsigned short dummyflSl:
unsigned short bankO_channels;

} *dav;

struct timeval first,
second.

}

• Result; Time = 0.013000 seconds

struct timezone t2p;

/* open the device file 7
fd=openf7dev/v)(i/primary",0_RDWR);
if (fd<0) {

perrDr("open");

exttd):

5 April 1 992 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

<3ev=(s^uct dev_regs *JvxLg&t_al6_addr(M.LAk

/^ crtati T-ms bysy time */
^ettimeafcfay (Sffrst^tzp);
for (j=0; j<=7000; i +^):
gettimecffiiay f&second.Stzp);

if (first.tv_usec > secDnd,tv_usecJ {
second.tv_us€C ^^ lOOOOOO^;
secand.tv_sec — ;

}

lapsed;tv_usec = second,tv_usec -- firsLtv_usec;
Japsed,tv_sec = second.tv_sec - first.tv_sec;

printf ("Ctianfiel closing (busy) time - %ld see %ld usee

\n " Ja p^ed tv^secjapsed.tvjsec);

g ett I me of d a y ( S(f i rst Sitz p ):
for (i=0; K-lDOptimes; [ ++)

{
/* Close channel 1, wait 7-ms jhusy time) 7

dev->bank0^channels=0x0001;

for (j=0, i<=7000; j ++);

d e v-> bank 0_ channel s=OxOOOO-

for IH; 1^=7000; j ++J;

}

getiimeafday (8isecand,&trp);

[f (firsttv_LJsec > second,tv_usec) {
second. tv_tjsec +- 1000000;
second. tv_sec- — ;

}

lBpsed.tv_usec = (second.tv_usec - first.tv_usec)/lO.;
lapsed. tv_sec = j second. tv^^ec - first tv_sec^/1D.;

prfntfr'Command execution end busy time = %ld sec %ld usee

\n"jepsed,tv_secjapsed,tv_usec);
/*rtprio|0.RTPRlO_RTQFF):7

}

► Results: Channel closing (busy I XmB = Q sec 7322 usee

Command execution and busy time ^ Osec 871B usee

ConcIusioD

The dense niatnx relay modules are among the highest-
density ^TClbus switch modules available today. FIFO
memoiy on the relay modules enhances system through-
put by allowing the modules ro interrupt ti^eir conuuand-
er's CPU only after the last relay in their channel list is
closed.

The relaj' modules can be programmed using ASCII-based
SCPI commands and the HP El 405 command module, or
can be progranuned directly at the re^ster level. Bench-
mark programs show that the highest throughput is
achieved with register-based programs in which SCPI
command parsing is eliminated, and the registers are
accessed from the VXlbus backplane. Subtracting the
7-ms relay settlii^g time from each benchmark shows that
access from the VXlbus backplane Ls up to 26 times
faster than the HP-IB, However, it is the command
parsing time, rather than IIP-IB or VXlbus speeds, that
has tiie greatest impact on throughput.

Benchmarks using D I AG: POKE were run because of its
similarity to commands supported by other command
parsers. The results show that DIAGPOKE, an SCPI com-
mand that writes data directly to the relay modules FIFO
memoiy, offered approximately the same throughput
performance as the high- level CLOSe command. This is
attributed to the efficient SCPI parsing algoritluns of the
HP E1405 command module and shows that with a fast
command parser, there is little throughput advantage to
register-based progranmung imless command parsing is
eliminated entirely,

Ac kn owl edgm en ts

We would like to thank Ron Hanson, Chuck Platz, and
Conrad Proft for the useful technical discussions. A
special thanks goes to Peter Meyer for his C programs
for the IIP Vectia c^ompuier, and to Art Boyne and Frank
Goss for their reviews.

Bibliography

1 VMEhus Ejrte7isiofis for huUrumentation System Bpeciji^alion,
Revision L3, Juiy 1989.

2. Standard CommaitdJ^for Frogramma^lM Instrummtt^ Manual,
Version 19fK).{), April imU,

3. HP E1S26E/E141 IB fj m-DigU MiUtiimter User's Manual, Edi-
tion J, HP Parr Niimbf^r El 326^90003.

4. L. DesJardin, "VXlbus versus (jPIB: Is VXlbus actually faster?,**
VXlbus Jourrml, November 1990, pp. 1M4.

April 11:^:^1 lew let^Pa^!kard Journal 51

)Copr. 1949-1998 Hewlett-Packard Co.

Mass Interconnect for VXIbus Systems

The HP 750D0 family of VXIbus products includes a set of interconnect
hardware that enables automatic test system developers to mount OUTs
easily to HPs VXIbus mainframe.

by Calvin L, Erickson

The interconnect harciwajc in an autoniatic tost system
consists of the components that connect the device under
test (DUT) to the test system mainframe. Typically,
automatic test equipment (ATE) product development has
focused on instrumentation, controllers, and software. The
resuh is that the interconnect hardware in a test system
has hecome a m^ctr comt>oiien1 of ^iysteni cost. In niosl
test systems, interconnects consist of chscrete wire and
connector harnesses, and their fabn cation is custom and
labor intensive. Many systenis also require a mass inter-
connect for interfacing with niultiple devices under test
DLITs.

The development of the VXIbus has brought these issues
into sharper focus, tireater density requires that more
signal lines must be packed into less space. Higher
speeds require shorter lead lengths and better connectors.
Finally, economics and time-to-market constraints demand
standard parts suitable for n\any applications.

This paper discusses the development of mass intercon-
nect products specifically for VlObus systems. Based on
the HP ATS 2000 system resource interface, these prod-
ucts mount directly on the front of the IIP VXIbus
mainframe. Tlris paper also discusses the trade-offs
involved in incori^joratiivg a mass interconnect into a
VXIbus test system.

HP Interconnect Components

As pail of the UP 75000 family of VXIhus uistruments. a
numl>er of mass interconnect products are available for
use in VXIbus test systems. These products, known as the
IIP 75000 system resource interface, allow^ a single test
system to service a large variety of units under test. Fig.
1 shows the products included in the IIP 75000 system
resource interface.

The interface connector assembly (ICA) is the heart of
the system. It seri'es as the primary interface between the
test system and the DUT. The ICA is typically rack-
mounted and wired directly to test system resources such
as switching, sensoi"s, and sources. The ICA provides
locations for mounting ICA connector blocks and aligning
connector blocks and their mating halves, and a mecha-
nism for overcoming the connector mating forces. Tlie HP
75000 system resource interface connector assemblies
include:

The HP 0420A ICA. This is the standard rack-mount ver-
sion shov^Ti in Fig. 1 .

■ The HP E3720A \^XIbus ICA. This ICA mounts directly on
the front of a VXIbus niainframe. it also allows direct

Imerfacfi ConnectDr
AssembtytlCA^

Interface Te&
Adaptei {\TA}

Contt«c(4ir Bittcks

Fig. 1. The kinds of interconnect products in the HP T5000 system
resource interface.

access to VXIbus modules and provides the greatest op-
portunity for short lead length.

The HP F:3722A hinged ICA, This ICA also mounts direct-
ly on the front of a mainframe and hinges down to allow
access to VXIbus modules.

The interface test adapter (TTA) is the frame that mates
with the ICA It. provides locations for mounting connec-
tor blocks. Typically, several ITAs are purchased, one for
each type of DVT. A frame or fixture is often built on the
ITA, customizing it to the particular DIT. Fig, 2 shows an
ITA customized for functional testing of a printed circuit
board. The IW 75000 system resource interface includes
two different ITAs:

The HP 942 1 A. Ttiis TTA is used with the HP 9420A ICA
and the HP E3722A hinjied ICA.

Tlie HP B3721 A VXIbus ITA. This ITA is used witlt the HP
E3720A \OClbus ICA,

Different kinds of connector blocks are available for use
with the fCAs and ITAs (see Pig. 3). These blocks are
wired and Uien installed in tlie appropriate location

52 Apdl 1992 HewJett-Packard Journai

)Copr. 1949-1998 Hewlett-Packard Co.

Fig. 2. A Hypical autoniatit test application m which an interface
test adapter (ITA) is ciistonii!xed Tor Lhe fimctional testing of a
printed circuit board.

within the ICA or ITA. Tiif three pritTiary choices are
192-pin general-puriMisc', 36-(^ontact coaxial, and 24-can'
tact power Ttiese connector blocks iire compatible with
each EGA and ITA choice listed above.

Customer Eequirements

The Bst of customer requirements for mass interconnect
in a VXIbiis test systetn is extensive. Most of these
requirements derive from the need to test a large variety
of DUTs. The mass Interconneet must have a variety of
coimectors that can handle different types of signals.
These include low-level precision signals, iiigh-fiequency
sigtials, and high-power signals. Some rimes, it is neces-
sary to keep lead lengths as short as possible to maintain
signal integrity. The connectors must have a long life to
allow frequent changes of the ITA. The ITA must have a
nigged and versatile eonstniction to allow the add! I ion of
a variety of fixttues suitable for testing everytliing from
printed circuit assemblies to automobiles.

Most test ."systems requhre many modes of wire routing.
For tJie VXn^us, tliese modes include:

• VXI-to-ICA. For example, a VXIbus relay module c^m liave
many connections directly to an K'A eoniiecMor blrjck,

• VXl-to-VXI. The same relay module vim have aji analog
bus connection to a neigiiboiing module in the same
mainframe.

• \9Cl-lo-System. A VXIbus slot module niay require an
11 [MB connection to the controller.

• It;A-to-Systeui. A non-VXlhus sigi\iil gerterator may re-
quire connection to an ICA connector l>lock.

Test systems must be ^rsy to configure and reconfigure.

This requires that VXIbus modules must be easy to install
and remove. Wiring should be accessible. Standard cable
4issemblies should be available that satisfy' most of the
wiling requirements. Dlffeit^nt ICA configurations should
be available for mounting in from of VXIbus or standard
rack mounting.

Finally, some customers require that the mass intercon-
nect conform to industry standards such as .^INC 608
and MATE.

Product Development

The project definition dictated that we rely on ejdsting
protlucts to satisfy citstomer requirements. From a
Ijractical standpoint, a lack of resources prevented us
from designing a new product from scratcli. Therefore,
one of our m^jor decisions concerned the selection of a
vendor. There were two viable choices. One vendor liad
already luodified their existing interconnect product line
(connector block, ICA, aitd fTA) to fit on the \iabus.
Their design was generally sound, and contained only a
few minor problems. Another vendor had a different
product line that conformed to the recently emerging
industry' standard ARINC 608, which has become increas-
ingly important in some segments of the marketplace.
.\lthough this product line had not been adapted to
VXIbus, it was already established within HP, Both
products were similar in cost, quality, and density. In the
end, the decision to tjse the second vendor was based on
two primaiy criteria: leverage and industry' standards.

We gained leverage from previous HP engineering experi-
ence in lest systems, the willingness of the vendor to
provide engineering expertise, and the use of the same
connector blocks acrross the entire ftmiily of ICAs arul
ITAs, HP's Advanced Manufacturing Systems ()peratit>n
(AMSO) had the products set up on the liP ATS 2000
product line. This allowed us to adopt the IIP 9420A ICA,
the HP 9421 A ITA, and tlie contiector blocks without

ICA Connector Blocks

ITA Connector Blacks

Fig, 3, ITA and \VA tujuH/ctor blocks,

April 1 1)92 HpwU'tt^PatTimr^ JournaJ 53

)Copr. 1949-1998 Hewlett-Packard Co.

Connector E)clen&ion

Bulkhaad PaneJ

ftttJit

Top

Mounting BlQck

VX^btis Modute

ICA CBnitectDr
SJoolt

Fig. 4. An HP E(J730A interface terminal module (TtM) with the
cover remove £;l.

going throiigli full qualific^ation testing. We still had to
solve the problem thai these interconnect components ditl
not mount on the front oJ' a \'XIbus mainframe. The
vendor solved this problem for us by agreeing to make
modifications to the standard ICA based on our design
concepts. Finally, we made the decision to use the same
connector blocks across the entire family. This pi evented
duplicate docun^entation and qualification efforts.

Modifications to the statidard ICA for use on the front of
a VXIbus mainframe faced several design challenges. A
primary design goal was to minimize the wire length
betv^een the VKTbus mrjdule and the ICA connector block.
This meant that the connector block had to be assembled
directly to the \OGbus module. An interface terminal
module (ITM) similar to those already used in the HP
VXIbus switch products was a logical choice. This inter-
face terminal module attaches to a VXIbus ntotliile on one
side and includes an ICA connector lilock on the other
(see Fig. 4). The two ends are wired together, minimizing
vvnre length- Note that a better solution would [lave been

to include the ICA connector block as part of the VXIbus
module. This was not practical because VXRjus does not
specify the type and lo<*ation of front-panel connectors.
Most systems include modules from various vendors,
Thus, there is no way to control all the connectors and
their locations.

The next challenge was providing easy installation and
removal of V'^bus modules past an ICA monnlod on the
front of ttie mainframe. The first vendor demonstrated
one solution to this problem. Tlieir ICA simply hinged
down and out of the way. Although this pro\ided excel-
lent module access, it had two problems. The first w^as
the requirement for ver>' tight alignment tolerances
between the mainframe and l:he ICA. The second was that
the VXIbus module, and not the sturdy ICA frame » sup-
polled the interconned mating forces. We decided that
inslailirtg the ITM-to-\OiIbus assembly directly thi'ough a
stationary VXIbns I CIA was a better solution (see Fig. 5).
If the c^oimector block were allowed to Ooat witliin the
interface terminal module, tolerances between the main-
frame and the ICA could be kept loose. Also, if the
connector block could be screw^ed into the iCA as origi-
nally designed, mating forces would be properly sup-
ported. There was only one problem: the standard ICA
was not tall enough to allow a VXIbus module to pass
through the opening. Increasing the height of the ojjening
just enough to allow passage of a VXIbus module solved
this problem. A connector extender was designed to
increase the height of the standard connector blocks to
fit in (he new^ stretched VXIbus ICA. This modification did
not affect the ICA alignment and closure mechanisms
because only the top member was changed. These mecha-
nisms reside in the bottom and sides.

Another challenge was that the standard connector blocks
are on 19.05-nnn f0.75-in) centers. C-size VXIbus modules
are on 30.48-mm (1.2-in) centers. This was handled by
simply ac^usting the hole pailems in the VXIbus ICA and
VXIbus ITA, making the inierface lenninal module 3048
mm (1.2 in) wide, and supplying appropriate filler panels

Wiring Access Penel

Front '

Cnnnector
Block ~

Interface
Teminat
Maifulfl

(mwi)

t^^

VXibus Module

VXIbus
ICA

VXIbus Mainframe witti Cable Tray

Fig. 5, An HP E:5720A\'Xlbni! ICA
Mth an interface temiirial rtrndule.

54 April 1992 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

for use with the narrower connector blocks. A side effect
of this is that the IIP E3r2(*A V^KIbus ICA is no longer
tmfy compatible with ARINC 6()S, We decided that this
was an acceptable comproniise if all the connector blacks
were the sanie.

Other challenges included the need to main tain easy
access to modules and to facilitate ail modes of system
wiring. These neetfe were satisBed ^ifh careful placemeni
of the \^bus ICA relative to the rack mcmnting surface
and the inclusion of access panels for wiring and a
special tool for the module mounting screws.

The clevelopment of the IIP E3722A hinged ICA was
much more opportunistic. A customer rtN^ue-sted that we
supply an ICA hittged to the front of a mainframe. For
this product, interface terminal modules are no! used and
all wires between the VKIbus module and the ICA con-
nector block are flexible, so that opening the hinged ICA
allows access to the \^lbus modules. The vendor devel-
oped the changes based on one of their previous designs.
Customer interest has remained strong and the E3722A is
now a standard product (see Fig. 6).

Product Description

The three ICAs and their associated ITAs and connectors
described above meet system wiring requirements in
different ways. The following sections describe and
illustrate these differences by showing the ICAs installed
in a typical! rack-mounted test system.

HP 94Z0A Interface Connector Assembly. The HP 9420A
mterconnect products are identical to those used in the
HP ATS 200D product. These include the HP 9420A ICA,
die HP 9421 A ITA, and three sets of connector blocks
(general -purE)0se, coax, and pcjwer)- These products are
not specific to VXIbus and can be useful in any rat^k-
mount application,

T^ie HP f)420A ICA can \)e rack-mounted in any location
in a test system. II confonns Kj ARINC 608, and provides

VXIbus Mf}riyle in
l^ecessc^d Aiainfrinw

Reverse Mounted
Instruments

Fi>^- 7. Typical system wiring for an HP 9420A ICA.

Fig, 6. An HP E3T22A tiinged ICA,

21 slots on 19.a5-nun (0,75-in) centers. Although it is the
most versatile ICA, it may use more rack space and
require longer lead lengths tttan desired (see Fig. 7).

The HP ^M21A ITA is designed to mate with the HP
042DA ICA. It, has a frame widt 21 slots. Tapped holes are
provided for attaching additional framework specific to
each [)LTT Tliis frajuework and associated wiring must be
provided by the customer.

The general-purpose connector blocks (ICA and ITA)
include two Ofvpin connectors. The coax connector blocks
inchnlc^ positions for 36 conl^cts, purchased sepai'ately.
The power connector blocks include 24 sense contacts
iiiid positions for 24 30-A contacts, purchased separately.
All the contacts have a life of 25,000 cycles.

HP E372DA VXIbus tfiterface Connector Assembly (VXIbus ICA).

The HP K3720A is im ICA modified 1t> fit on I he front of
a VXIbus mainframe. It provides 13 positions on ;K).48-nun
(1.2-inJ centers. Each position is aligned with the corre-
sponding slot h\ the mainframe. The main differences
between the HP E3720A and the standard HP 9420A ICA
Include:

Flanges to position the VXIbus ICA relative to the VXIbus
mainfranu> (thejse flanges also allow rack mounting any-
where in the test system)

April 1992 Hewlett-Packard Journal 55

)Copr. 1949-1998 Hewlett-Packard Co.

' Access panels above and below the VXIbus ICA (mmoval
of these panels provides access to sysr.eTti wiring and
eases the task of module installation and removal)
The lop horizontal bar shifted up a sufficient distance to
allow VXlbus modules to be inserted through the VXlbus
IC^A

The l)ottom horizontal bar cut out to allow greater access
to system wiring

■ Support by both horizontal bars for 13 connector blocks
instead of the standard 21

A special tool to gain easter access to the VXlbus module
mounting screws.

Fig. 8 shows wire routing in a slot that does nni refjiiire
an interface tenninal modtile.

The HP E3730A interface terminal module (rTM) is a
housing that mounts on the front of a VXlbus module
(see Fig. 9). It is designed for use only with the IIP
3720A \rXIbus ICA. Featmes of this prtjduct include:
Mounting blocks For mounting the ITM onto most VXlbus
modules (This is accomplished by removing the handles
from a module and replacing them with the blocks.)
Standard connector blocks that mechanically float rela-
tive lo the !TM (Tliis accommodates tolei"ance buildup
between I he mainfrtmie and the VXlbus ICA.)
Bulkhead panels for connections Lo other parts of Uie
system

Provisions for installing te mi in al boards (see Fig. tO)
supphed with many HP VXlbus switcli products (These

VXlbus Module in
Re c esse if id a intra me

V)(lbus Meduie

Instrument

Fig. 8. Typical system ulrlng for an HP E3720A VXtbu5 ICA with-
out an inlerface terminat rm>dule.

ITM

kfK

VXtbus Module in
Recessed Mainframe

VXttius Module

Irtsinuneiit

Fig. 9. Typical sysLeni wring for an HP ESTIDA VXJljiis ICA \^ith
itii tiP E3730A intcvf^fM-^ tr^nninal inrKinliv

boards supply functions such as matrices, rhemiocouple
reference, and so on.)

• A "funner for tool guidance when installing a module in
the main frame

• A pull ring to ease the task of removing modules.

The E3721A \Oflbus interface test adapter fV^bus ITA) is
designed to mate with the E372QA VXlbus ICA. It is
identical to the HP 9421 A ITA except that il supports 13
conned or block^ij instead of 21.

HP E3722A Hinged Interface Coiinecfor Assembly (Hinged ICA).

The I IF E3722A is another ICA I hat has been modified lo
fil on the front of a VXlbus nuiin frame. Like the HP
9420A It:A, it conforms to ARINC 608 and provides 21
slots on 19.05-nuti (0,75-in) centei^. The main (iifteiences
between Ihe HP E:iT22A hinged ICA and the standard HP
*H2t)A ICA include:

• Flanges to position the hinged ICA relative to the VXJLms
mainframe, which include hinges on the bottom and
knurled screw tied owns on top

• lapped holes across the bottom for cable tie points.

Fig. 11 shows the wire routing with a hinged ICA.

System Integration Process

The process of including a mass interconnect in test
system developmer^t is very complex. The following
simplified procedure may hetp the system integrator
through many of tiie issues.

56 April J 992 IlewIi*ii'PadcMd Jmimat

)Copr. 1949-1998 Hewlett-Packard Co.

Pig. 10. In the foregroimii is an HV E'STSOA inLerface terminal
riiodulp tenminaJ board mih the fovpr rornovpfJ. In Llip backgrf)und
is an HP E'^TSO VXIbns irittTface connector assembly attac:hed to
an HP 75000 Series C cardcagf*.

1. The first step is to identify the number and type of
BVTs that will be tested Ijy I lie system. Usual ly, a differ-
ent ITA will be built for each DlIT, with one more for
system selMest, A list of necessary' system resources
should be created for each ITA. Each list should include
sources such as power supplies, sensors such as voltme-
ters and counters, and components for switching and
communication. The different ITA lists can be combined
iiito a single list of system resources required for all
tests. Each ilern on the list will translate into a single line
on the ICA.

2. The second step is to determine if a mass interconnect
is necessary. The follow ijig questions should help in ttiis
decision.

• How many different DlIT^ wUl be tested? More than two
or three n>ay indicate a need for mass inlerconnect,

• Flow offen will ITAs be changed? More than 4f)0 to 50()
times through the life of the system may indicate a rieed
for mass interconnect.

• How^ many lines must be fed through the mass intercon-
nect: more than 200 to 400 general -purpose lines, or more
than 20 to 50 coax or power lines? If so, mass intercon-
nect may be appropriate.

' What type of signals must be connected?

• Do appropriate mass interconnect connectors exist?

In many cases, a mass interconnect Is not appropriate. A
hish-quality, militaiy-slyle circulai" connector may be
adequate.

3. The next step is to refine the list made in step 1.

Trade-offs must be made between maximizing system
riexibihty, minimizing complexjiy and cost> and maintain-
ing critical performance specifications. Particular attention
should be given to switching networks. Consider the
following:

• Cusiom configurations behind the ICA limit system flexi-
bility, but they also reduce ITA complexity and cost,

• Switch networks are essential for minimizing resources
and providing system flexibUity^ but switches have lim-
ited life. They add complexity and reduce system perfor-
mance.

Add lines to the list to account for switching networks,
ITA identification, and so on. To each line, attach any
important performance specifications stich as frequency,
voltage, and current.

4, The next step is to make a preliminary^ layotit of the
entirL^ system. In most cases, it is best to start with a
block diagram. The diagnim can then be used to make a
skett^h of a rack showing all systent components. This
sketch should include all sources, sensors, switches, mass
interconne<'ts, controllers, and so on. Now is the time to
think aboui wiring issues such as grouiuliJig and critical
lead lengths* Remember to leave room for growth and
flexibility.

Selection of the appropriate ICA occurs at tliis time. This
decision should be based on the above considerations and
the following:

• Is compatibility required with other ITAs? These ITAs
may already exist or they may be planned as part of a
large prcyject.

• Is compatibility required with an industry standard such
as ARINC 608? This would limit the choice to the HP
9420A or the IIP E3722A.

• What type of signals will be connected? How many lines
will be connected? UTiat is the required cycle life of the
connectors? The answers to these questions may indicate
the use of less-t^xjiensive interconnect products such as
the HP 34592A quick intercomiect.

Fig. IL 'IVpical system wiring for an BP E3722A hinged ICA.

April mz Hewlett-Packard Joiim;i] 57

)Copr. 1949-1998 Hewlett-Packard Co.

Is rack space limited? If so, the HP E3720A or HP E3722A
may be the best choice. Botli ICAs niouril on the front of
the VXIbus mainframe. Remember, however, thai other
sysiem components may be reverse mounted behind the
IIP 9420A without sacrificing rack space.
Is a reduction in access to VXIbus front panels accept-
abie? Any ICA mounted in front of the \OQbus mainframe
wiU limit acx-ess to VXIbus modules. Front-panel indica-
tors will not be visible and modifying modules and wiring
will be more difficult.

Is short lead length between the VXIbus modules and the
ICA connector important? If so, the HP E3720A may be
the best choice.

Do most of the ICA wines {at least 60 to 75 percent) con-
nect lo VXIbus nu)dules directly in a single niainlVanie? If
so, the HP E'3720A may be the best choice. If there are
many wires that cormect elsewhere in the system, Ihe IIP
9420 A could be a better choice.

Are the limitations of the IIP E3722A hinged ICA accept-
able? A practical hniitalion in density is imposed by the
requirenient tliat all wires must bend every iliue the ICA
is hinged down. Because the hinge is at the bottom, ali
wires must l:*e tied at tliat point. This impedes wiring that
must connect to resources above the VXIbus mainframe.

5. The fifth step is to refme the system layout and
interconnect list. In partieuiar, add detail on the layout of
connector blocks in the ICA, including pinout definitions
for each block. It is usually a good idea to retain a
generic funclioniil grouping. In other words, dedicate
some blocks to sources, some to sensors, some to power,
some to liiglt frequency, some to switching networkst and
some for groviib, Tliis functional grou|nng is jiarticularly
important for systems that will he testing many different
DlTTs. Remember that many of the rustom cormecfions
can be made inside the ITA.

6. tlnatly, it is time to compile a list of all parts and
products, For the system side, this should include the
ICA, interface terminal modules (for the E;3T20AJt ICA
connector blocks and blanks, cable assemblies, and
contacts. For the DLT side, this should include ITAs, ITA
connector blocks and blanks. cat)le assembhes, contacts,
and all parts necessary to customize the ITA for a partic-
ular DUT

Conclusion

The integration of mass intercormect into a test system
adds significant, but often essential, complexity. The
.system integrator is required to consider many factors.
These factors include Dl^T quantity and type, signal
chararteri.stirs and tiensity, system components, available
rack space, diagnostics, reconfiguration, and so on. One
of the most importaJit factors is the availability of ap-
propriate mass interconnect products. The HP 75000
system resource interface provides an excellent set of
tools for use with VXIbus-based lest systems. Appropriate
use of these products can greatly influence system cost,
de%^elopment time, and perfomiance.

Aek n owl ed gm e tits

I would Uke to thank the following people for their key
roles. At IIFs Advanced Manufacturing Systems Opera-
tion, Mike Stefan isko for his teclmical expertise and
advice, Dari Meitus and Jim McGitlivary for their support.
At Mac Panel Company, TYoy Rector and Kellie Coble for
their responsiveness. At HP's Love land Instrument Divi-
sion, Chailie Srlrmiflt for the riesign of (Jie ITM, and in
pailiculai; Bryan Thompson for his uivolvement in the
defmition and in the details of introducing these new
products.

58 April 1992 HewItFtt-Packard Joiimal

)Copr. 1949-1998 Hewlett-Packard Co.

A Manufacturing-Oriented Digital
Stimulus/Response Test Instrument

This digital functional tester consists of pattern I/O, tinrring. and command
modules configured in a VXIbus mainframe. The maximum pattern rate is
MHz and pin-to-pin skew is less than 6 ns.

by David P. Kjosttess

Test en^neers and system integrators have tised analog
instm mentation for years in their automate d functional
test systems, tinljl t^ow. however, there lias been little iii
the way of cost-eflecti^ e, manufacturing-oriented digital
instnmientaiion with which to round out their toolkits.
The HP 75000 Model D20 was created to nil this void.

The decade of the 1980s saw an explosive increase in the
ainount of digital circuitry- used in all nianner of electron-
ic assemblies. Today, an estimated Bi>^> of all circuit
boards are uiamtfactured with substantial digittd content.
In the 1990s, the use of digital cirrulti'y will continue to
increase p as will the use of advanced packaging such as
fme-pitch surface n)ouni tcchnologj^ (SMT) and multichip
modules (MC'Ms). Also, the proUferation of open architec-
tures w^ill require testing to rigid specifications. The effect
of these developments will be a greater emphasis on
digital functional testing in future manufaciuiing schemes.

Functional testing involves tlie transfer of information to
and from the device under test (DIT). A stimulus is sent
to the OUT tti ovcike some response, which is then
anal>^ed to detennine If the IlL^T is operating correctly tf
the stinuilus and response art^ digital, then it is a digital
functional test. If some part of the stimulus or response
IS not digitiil (i.e., atuilog or uux-hanical), then it can be
said to be* a mixed-signal lesf hi functional testing, the
stimulus application and response measurement are
generally performed through the assembly s edge eonnec-
tors; connections to inten^al nodes are kept to a muii-
mum.

The uses for functional testing can vary considerably
St>me manufacturers use it simply to verify connections
from connector pins to internal components. Others use it
to exercise thp functions of their assemblies in go/no-go
tests. Still olhers develop complex fault isolation and
cUagnostic tests to pinpoint fmled components within their
assemblies. Regardless of lest complexity, there is a need
for cUgital instrumentation that can be jntegrat€Hi with
analog mslruments like voltmeters and counters.

A General Model for Digital Interfaces

t>igii;U interfaces ccjme in myiiad forms. There are
standard backjjlanes [like VXIbus) and proprietary back-
planes specific to certain products, fheri^ are iUso non-
backpiane interfaces, both stajidard (like SCSI) and
proprietaiy. However different, all digital interfaces shai'e

certain characteristics which can be exploited when
designing a digital stimukis/response instrument.

The signals of ilie interface fall into two major categories.
First, all but a few of the tines tue dedicated to canying
information ro or from the DUT. These include the data
and address buses on a computer backplane, for example,
and will be called patlem luws here. Second, there are a
few signals, the control and handsfmke lines, which
facilitate the infomiaiion transfers on the pattern lines.
Control signals are created liy the tester to regulate the
transfer process; strobes and clocks are typical examples.
In many interiaces, the DUT responds to control signals
wqtli a handshake signtil to acknowledge a data transfer
or to modify the rate of transfer.

Let's define some terms. A ci/de is the sequence of events
necessary to transfer one bit to or from the DUT on each
of the interface's pattern luies. A particular interftice
specification may define more than one type of cycle —
read and write, for instance. The specification of a cycle's
pattern data along with that cycle's type forms a vector.
An ordered list of vectors is a called a sequence, A
complete test consists of \he execution of one or more
sequences.

As an exan>ple, consider a data transfer cycle on the
VTVIE (or VXl ) bus. Suppose that the tester is acting in the
bus master role, writing dala to the Dt.T (Fig. la). At the
beginning of the cycle, the tester places valid information
on the address (A01A31), addi'ess modifier (AMO-AtVlSj^ long
word(LWORD*) and inlemipt acknowledge (IACK*j hues,
.^er allowing for propagation delay and st^ttling time, tlie
addreas strobe (AS* J is asserted. Also, near the beginning
of the cycle, WRITE* is asserted and the data to be w^ritten
is put on the data bus (DSM-OSI). This is followed, again
after a suitable delay by the assertion of one or both of
the data strobes (DSO*, DSU). It is now up to the DUT to
acknowledge the data transfer by asserting DTACK*. after
which the tester will negate ttie address and data strobes,
then wait for the DUT to negate OTACK*. When DTACK-
goes false, the cycle is complete and another cycle can
begin.

A read cycle (Fig. lb) is similar, except that the tester
tiegates WRfTE* and tristates (do<\sn't drive) the data bus.
Instead, when tJie data strobes are asserted, the DLIT
puts its response^ data on tlie data bus and assert-s

Apri! imi Hewlett-Pac; karxi ,J^ >iiri i :il 5 9

)Copr. 1949-1998 Hewlett-Packard Co.

DTACK*. The tester then accepts the response and negates
the flaia strobej>, causing the PUT to iristale the data bus
and negate DTACK'*', conipletinjLj the read cycle.

hi this exaniph\ the address, address modifier, and data
tiuscs are identified as ]) at tern lines. The address and
datii strobes are control signals and DTACK* is a hanci-
shake line. LWORD*. IACK#. ajid WRfTE^ roiiid be treated as
pattcm Unes but are really control-like in nature since
they serv^e to define tjie type of cycle-

Some observations about the two categories of signals aie
in order here, beginning with pattern lines. First, pattcm
iines each assume a single value in each cyc^le: they make
at most orte tninsition per cycle. St*cond, pattern lines jire
mosi often collecfed into sets that have coninion func-
tions and timing. These sets are ealletl buM'.s and usually
contain multiples of eight patlem lines. There might be a
16-bit data bus or a 24-bit address bus, for example. A
third ot)senation is Ifiat some, but usually not all pattern
lines jnay t>e bidirectional. That is, they may caro'^ in-
lonnatiou first one way and then Lite otlier during the
course of the test. Data buses, for example, are typically
bidirectional but address buse^ are generally not.

The few control and handshake lines in an interfare differ
from the patleni lines in a number of ways. Firsl. [Iu y
are sinj^le lines, not contained within buses. (Sonu^tin\es
an interface will have wiial is ctUled a c:onlrol bus, whicli
is really a collection of individual control and handshake
signals, not: the same as a patteni bus). Another differ-
ence is that these lines usually make more than one
transition in each cycle. In the \TVlEbus exanii)le above,
the data and address strobes, as well as DTACK*, are first
asserted^ then negated, thereby making two transitions in
each cycle. There can be many repetitions of a clock
sigrjal in a cycle. A third difference is that control mid
handshake lines are nnidireetional, not bidirectional.
Finally, for a given cycle type, the control and handshake
lines have the same* behavior regardless of the irifuntia-
tion on the pattern lines.

Handshaking can be either synchronous or as^TichronoLis.
If there is no exphcit clock signal in the hit erf ace, it Ls an
asynchronous handshake. The VME and VXl buses employ
this type. On the other hand, if there is a clock signal in

the interface, then handshake and control transitions must
usually lie synchronized to the clr>ck transitions, creating
the synchronous variety. An exantple of this is when a
device requests a wait state in a personal computer.
When there is a clock signal in the interface, it can be
generated either by tlie tester or by the DHT In the latter
case, the tester Jiiusi be able to synchronize itself with
the Dtrr-supphed clock, and this forms a type of hand-
shake as welL

Model 020 Requirements

To be useful, a digital stimulus/response instrument must
be capable of entulating the DlIT's interfaces. Its applica-
tion to manufacturing test Ing imposes other requirements,
including high test quality ai\d throughput, ease and
flex ibi lily of integration and use, attd low downtime.

Achieving high test quality places several demands on the
instnmient s timing capabilities. The tester must first of
all be capable of exercising the DLIT at full speed. Also,
timing relationships at the DiFT must closely resentble
those defined by the interlace specification. This means
that the tester must have good resolution and accuracy
for edge placement and cycle duration. Since different
tyT:)es of cycles may have different durations or different
(iming relationships between the various signals, the
tester must l)e capable of changing timing on the fiy.
Finally, since there may have to be a substantial length of
cable between tlie VXIbus mainframe and the DITT, there
must be some means of compensating for the restdtant
cable propagation delays.

Good signal fidelity is another requirement for high test
quality. A tester must deliver clean stimulus waveforms to
the DIJT and not be difficult for the DUT to drive cleanly,

Maximis^ing test throughput requires not only that devices
be tested at fuU speed, but that time spent transferring
infonnation between the test controller and the tester be
minimizefl. The amount of data tliat must be transferretl
must be small, and the transfer rate must be high.

Fixturing is an important aspect of production testing, so
a variety of methods of connection to the DIT must be
accommodated. In some cases it is possible to put the

mi-A3\

luyoRn +

Valid Stfmirlris

lACK*

, Asserted

Negated

AS<

WfttTi'

\ AssAited

(KnD31

ValiitStiinutus

Asserted ;
~\Ass«r&d

Negated

DSD*

Negated
K«§atBd

0S1*

DTACK *

\ Asserted

A01 A31 ,
AMU- AM 5 y-
LWOflO .
IACK4

AS 4

WRnt '

nm*

DTACK ^

Iftilid StiiBuliia

\As$ert id

Negaisd

Tiistflte

Bespoitta

■ Asserted

tteflftte d^

' Asserted

jlega ted

^^ Asserted

Neg ated

(a) (b|

Fig, 1, (a) VMElius v,tile cycle timing diagram, (b) VMEbus read cycle timiiig diagram-

60 April 1992 Hewlett-Packard Jouma]

)Copr. 1949-1998 Hewlett-Packard Co.

DL1T dose to the instrument, but in others there may be
one or two meters of enable separating them. There may
also be a mass interconnect de\ice involved, such as the
HP 9420A or E3722A interface connector assemblies.

V\lien <ic>iiig mixed-signaJ testing, the digital instruraent
must be synchronized with analog instrumentatioR.
Flexible trigger inpuL^output capabiMt>' is therefore need-
ed.

Functional test systems use a \^anet>' of instrument
controller platfonns: peisona] computers. UNIX* worksta-
tionSf and HP BASIC workstations, to nanie a few. To be
compatible with all controUere. a digital instrument
should have an ASCII command language like the other
instruments in the system. SCPl [Standard Commands for
Programmable InstnmienLs. a superset of FEEE 488.2)
comnumd format is preferred. There should also be
efficient non-ASCII opiions for transferring large volumes
of patteai data.

Finally, reducing downtime requires a reUable instnnment
with built-in self-test to identify failed modules quickly
Replacing a module must not rec^uiie time-consmning
recalibralion to meet specifications.

Model D20 Architecture

With an eye to the tibove requirements, the HP 75000
Model D20 design team in^-estigated various digital
stimulus/response instrument arcliitectures. We looked at
a number of existing products as well as several new
proposals. What follows is a discussion of the architec-
ttu^e tliat emerged from our Investigation and the deci-
sions that siiaped it.

The fact that interface signals fall into two categories
(pattern and conlrol^iandshakc) suggested a similar
division of roles in the Motlel D20, We therefore created
pattcni I/O modules (UP K 1451 A and El 452 A) for pat-
lenis anrl a timing module (HP E1450A) for control
signals and Itandshaking.

The timing module generates eight control signals an ft
performs both synchronous and asynchronous h^indshak-
ing with the DfTT, It also accepts and generates triggers
for synchronization with t>iher Insinnnenialion, and it
provides timing Infonnation to Iht* patttTU 1/U modules in
the form of twelve patleni clocks on the VXJbus local
bus.

Each patttni I/O module has thirty-two channels, ar-
ranged as four eight-bit porfs. Ports sltv independenl of
one another and can be progranuncd for stimulus output
or response input. The two types of pattern I/O modules
are identical except that the HP K 1451 A passes pattern
clocks on to the next, mainframe slot and the HP E1452A
tennhiates them.

A Model D20 system is configured as shown in Pig. 2.
The IIP E1450A timing module is placed farthest to the
left, followed by a number of HP El 451 A patleni I/O
ntodules. One HP E1452A terminating pattern I/O module
completes the instrument.

' UiytX is B rag(stsred tfadematk of UiyiX Syslefi] Laboratories Iric in thg tJ.SA and other
coufiines

Local Bus
(Pa^em Clocks)

Fig. Z. HP 75000 Madpl D20 conliguraUon,

A single tiniini^ OKKiule can service^ up to ten pattern f/0
modules, a full mainrrame. Furlliennore, up to three
timing modules can be linked in a master/slave arrange-
ment, allowing up lo thirty pattern ]/0 modules to he
included in the instrument. Tlie timing module is optional
when an cxiemal clock source is avtiilable. As a result,
instnmients with from 32 to 960 patleni lines and from
to 24 control Imes can be assembled.

Tlie pattern I/O and timing modules cat^ interface directly
to the DITT, but En ca*^e the DPT nnist be some distance
from the mainframe, pods are provided. A pod cont^ains
active circuitry at the end of a two-meter cable. It buffers
and reconstnicts stimulus waveforms, chminating any
distortions a length of cable might cause, and gives a
lower output impedance than a cable would. It also
buffers responses from Ihc OUT, pro%iding high-imped-
ance inputs which are easier to drive cleanly than long
cables. The IIP E1454A pattern I/O pod liuffers sixteen
bits of pattern data; two pods are used with each pattern
I/O module. Tlie HP KHri;iA timing t>o<i huffet^ the
control and handshake signals associated with the tinting
niodtile. The HP E1I456A and E14B5A pods are electrically
identical to the IIP E 1454 A and E1453At respectively, but
arc mechanically diflerenl to allow them to bi* mount e«i
in the HP 942()A and Er3722A interface connector assem-
blies.

Given this basic architecture for the Model D20, attention
was turned to the question of message-based versus
register-bEised programming interfaces. Message-biised
inteifac(*s simplify instnimcn! iiiogr^iiuniing and provide
for controller independence. Since they employ onboard

April 1992 1 [4 w iL tt - Pa< kiml Mm rtial 6 1

)Copr. 1949-1998 Hewlett-Packard Co.

processors, they allow butll-m self4est for quick klentin-
t:ali()ii fjf failures, Srjphisiicatrd nu^j^sage-fjased intiTfaces
can, however, slow data traiislVr mtcs, linuting through-
put. They require sigiiifjcant iuooimts of hoard space, an<l
in the case of the Model D20, w here therp is not one
inudyie guaranteed to be a part of tiie instnintent , each
module would he recjuired 1o have one. This would raise
the cost significaiidy.

Register-based interfaces, on Itie other hand, provide
direct control of the liardware and maximum data trans-
fer rates. They are less expensive and take less hoard
space. Programming regis ter-hased uiodides as complex as
the Model D20's can he a daimting task, however.

Fortunately, recent versions of the HP K14(J5 command
module, with their downloadable fin n ware capability,
provide a single place from which lo control umltipie
regis! er-based modules with an SCPl command lanj^uage.
This approach was taken with I he Model [)20, reali>^ing
the benefUs of a niessage-hiisetl interface while still
allowing fast, unrestricted regisier-based operation.

Maximmn pattern rate is a key specification for a digital
instrument, and many standard and proprietary interfaces
wtTc examined to determine how fast the Model 1)20
sliould nin. Ttie VME iu\d VXl buses have a maxinnnn
patleni rate of 10 Ml Ik, Personal conipulers, while having
clock rates of 25 MHz or more, have pattern rates of 12.5
MHz or less. Most other interfaces have speeds of the
same order. It became apparent, then, that an insfnmient
capable of 20-MHz pattern rates would be viable, jjro-
\1ded it could produce control signals at tip to 40 MHk.

Picking 20 MHz as a maxinnim pattern rate meant that
much of the Model D2(fs circuilo' could be implemented
with oft'the-shelf CMOS technology- The low power of
CMOS places !ow^ demands on the niain frame i)ower
supply and coohng system and minimizes failure rates.
Losing conmioniy available technology minimized both the
time to market and the cost.

Since the vast n^jority of cllgital devices Imve either T'fL
or CMOS interface levels, the Model D20 needs to be

compatible with both. To tjiia end, all outputs swing to
CMOS levels (ground to +5 volts), allowing Uie inslrtmu^nt
lo drive either TTL or CMOS DITT inputs. Conversely, all
inputs have i.5-\T>lt tyi>ical thresholds, allowing them to
be driven by either rfL or CMOS DlIT outputs.

Pattern I/O Modules

Realizing thai nu>st of the parten^ signals in a DUT
interface can be collected into buses that have multiples
of eiglit lines led to the concept of the pattern I/O port. A
port Ls a self-corLtained. independent, eight-hit 1/0 struc-
ture with a single clock to control its timing. Each
pattern I/O module contains four pons. Compared w-ith
so-called *' per- pin" architectures, this "per-hyte'' approacli
reduces cost considerably without seriously limiting
flexibility in real applications.

As shown in Fig. 3^ each port consists of an address
counter, a pattern and control memory, input and output
stages, clock seleclion and delay cij'cuitiy iuid a compara-
tor. At the beginning of a sequence, the address counter
is preset It then increments for each cycle (vector) of
that sequenc(\ The memorj^ has tj,5,5;i(j (t>4K) iwelve-bit
words. Eighl bits of each word are used for pattern data
while the remaining four pro\1dc cycle-by-cycle cojitrol
lor I he port. The output and in [in I slices provide the
interface to (he DUT (ii' there is no pod) or to the pod
cable. The clock for each port can be one of the pattern
clock signals from the timing module or an external clock
signal Sincr* there Ls only one pattern value associated
with earh wt lor, a single c^lock edge per cycle provides
all the timing information a poil nec^ds. Pattern clocks are
subjected to a variable delay for the puiposes of deskew
and cable-length compensation, to be described below.

A port can be programmed to perfonn one of tJiree
different tasks, with its memory assuming a different role
for each. The first mode of operation is stimulus, in
which the eight [lalletTi bits of each rnerriot^' word are
sent through the output stage to tiie UCT In this mode,
one of the control bits provides c^cle-by-cycle tristate

Clock Select ion and Delav

Pattern ro
or frojTi
DUT

Compare Expected Actual
Enable Respanse ■ Respoitse

Cornpatatoi

Fig, 3. Pattf^n I/O port block dlaitram.

62 A [1 ri I 1992 tie wlett-Packaid JoumaJ

)Copr. 1949-1998 Hewlett-Packard Co.

Mast^f SectJOfi

Slav« Section

From

Timiflf { Q0-Q3-!^
Pod

Fro fit Panet
Malice r
Outputs

TTl ) VXIIius
ECIJ Trigger

Marfier

ShmuJjjs
TtmJng GeneratDr

Response
rtrifiitg GenefdlDi

Paflem Clocks
to I/O Modules
via Uc^l Bus

Ffont Panel

Canlrol
Ttmifig {^cneralor

Confiol Outputs
~^ to OUT

Cantral

Fig. 4. Tinting module hlock rjiagram.

control for the whole port; when tristated, outputs as-
sume a hlgh-nnpedance state — ntnlher high nor low. An
additional iiiput to the output stage allows lixtemal
Lristate control.

The second mode is record, in which eight bits of re-
sponse pattern data are sampled by tlie input stj^e and
written into the niemoiy in each cycle. Final ly, there is a
compare mode, which brings the comparator section into
play. In this mode, eight bits of exjiected response data
fron^ the niemor>' are compared with the eight bits of
actual response from the DCT. Another control bit. en-
ables this comparison on a cyckvby-cycle basis, and there
Is a static mask register that allows any bits to be de-
clared "don't care"". When a coniparison fiiils, tlie port
stops, thus preserxing the memory address of the first
failure and both the expected and Lhe actual responses.

One of the remaining two control bits is used to indicate
the end of a sequence, causing the port to stop. The last
is a branch Ijit used to implement a diagnostic looping
feature by forcing the adchess counter to loatl a nonse-
quential address from a branch destination register (not;
shown in Fig, 3).

Tltere Is a high degree of llexibility in this port concept.
Multiple ports witb duplicate progranuuing ancl the same
pattern clock can form pin groups conesponding to the
Dirfs buses. IEEE 488.2, the basis for SCPT, restricts
integer data to thirty-two bits or less, thereby limiting
firmware supiiort for pin groups to no more than four
ports. Laiger buses c^m t)e cEnulated by dupli<"aTing the
progranmiiiig for more than one pin grcjup. Ports (^an be
programmati rally reassigned to diffen^nt pin groups as
necessary to test different devices.

Bidirectional buses can be tested by connecting a stimu-
lus pin grou{> in parallel with a response pin group, Aji
advantage of this approach is that the I wo pin groups mv
othcrwisi^ irui(*]!endt^n!, allowing ctnnplde nexihility in
liming ami making cable-delay compensation possible.

Another advantage Is that the resources to implement
bidirectional buses need only be purchased for those
pattern lines that are bidirectional, and not necessarily
for alL

Paralleling pin groups creates other possibilities, <is well
Responses can be simultaneously recorded and compared,
for example. Also, multiple stimulus or response pin
groups can be combined, to double, triple, or even
quadntple tfie Model D20s pattern rate and memory
depth.

Compare mode mid fieep memory' incTease test tbrough-
pui by reducing the amount of information that must flow
between the inslimnent and the c'ontroller for each device
tested. Compare mode does this by eliminating the need
to move whal could be millions of bits of response data
into the controller for go/no-go analysis after each se-
quence. It is only neeessiiry to inten'ogate two registers in
each response port. Of those ports indicating a contpari-
son error, tfie one witii the lowest memory acklress
identifies lhe first failure. Deep memory allows a long
sequence or nuiUipIe shorter ones to reside In the Model
D20. This reduces the incidence of reloads during testing.

Timing Module

The IIP E1450A timing module accepts a number of
inputs from the DUT and/or olJier instrumentiition and
produces control outputs to the DUT and pattern ttlocks
to the pattern I/O mcjduies. It also generates triggers for
other instruments. Its overall block diagram is shown in
Fig. 4.

The tiJiiing mt>dule's inputs it\clude triggers from various
sources, two READY lines for synchronous handshaking,
and ten lines (aO-Q9} thai are used mainly for asynchro-
nous haiulshaking imd trigger quaiification.

All of these mputs must be synchronized with the internal
160-MHz oscillator, and al! lhe timing modules in the

April i ^2 Hewlett-P^l^catd .lounial 63

)Copr. 1949-1998 Hewlett-Packard Co.

iiLstniment must "see" the mputs at the same time. For
til is reason, thp riming modulo is divided into master tmd
slave sections, which ai'e linked by an external cable. A
timing module becomes a slave by ha\iiig its slave
section connected to the master section of another timing
module.

Maiiter Section

As Fi^. 4 sIkjws, I tie master section accepts in purs,
processes ttieni, and synchronizes I hem with the internal
oscillator. The two READY lines, one from a front-panel
coimector and one from the pod, are ANDed together, then
sent to the slaves after being synchronized. Lines QG-Q9
become variables in fotir tiser-ilenned Boolean expres-
sions. These lines address a fast meiuoi^ tiiat has been
II I led with Ihe tnitii tables of the expressions (laljeled
"Boolean Expression Evahialors'' in Fig. 4), and the
results appear on four conchtion lines. Three <jf the
conditions (CON DO, C0ND1, mid C0ND2) are for general
liandshaking and synchronization, and are sent to the
slaves, while the foiulh (C0ND3) becomes a trigger qualiii-
er Available trigger sources include the eight TTL and
two BC'L VXlbus trigger buses on the backijiane, an input
on the timing pod, and Ijoth ITLrlevel and ECHevel
front"pai\el connectors. Positive or negative slopes can be
selected for Hie pod and front-panel trigger inputs but
slopes for the VXlbus trigger buses are ITxed by the
VXlbus standard. Trigger qualincation is done by sampling
tlie state of C0ND3 when the selected edge from the
selected source occurs. If C0ND3 is true, then the trigger
event is recognized, but it is not passed on to the slaves
until after a prognuimiable delay. This trigger delay is
provided by a sixteen-bil coimter, giving a range of zero
to (2J*5 - l)xa25 ns (almost 409.0 us). READY, CDMDO,
CONDh C0ND2, the ciiiahfied and delayed trigger, and the
oscillator signal appear at three front-panel connectors,
from which they drive the slave sections via master/slave
cables.

Slave Section

While the mtister section deals with inputs to the timing
module, the slave section is concerned with the rtmdule's
outputs, namely control signals, pattern clocks, and
triggers. Recall that control signals ai'e generally higher-
speed than patterns, with possibly many transitions per
cycle. They are essentially arbitrary digital waveforms.
Pattern clocks (which provide timing infoniiation to the
pattern I/O modules \ia the VXlbus local bus) and trigger
pulses can be thought: of and created in the same way.
Therefore, the timing module has three similar timmg
generators: one to create marker (trigger output) pulses
and six stimulus pattern clocks, one for six response
pattern clocks, and one for the eight control signals. To
acconrplish system deskew and pod/cable delay com-
pensation (discussed later), the three timmg generators
need to operate in different time frames and tberefore
must be separate. Tliese timing generators, along with a
prescaler a sequencer, several control state machines,
and some cable-length compensation and deskew^ circuits,
make up the timing modnie's slave section.

Fig. 5 show^s the slave section in more detail. Tlie stimu-
lus, response, and control timing generators are all
similar, consisting of a ten-bit address counter, 1024

w^ords of memory, an output register, and a little random
logic. At the beginning of each cycle, the address counter
loads a new value, then begms incremer\ting through
successive memory addresses. The memory data is
clocked through the output register, creating waveforms.
Cycles are defmed by putting appropriate data into a
range of memory locations, each corresponding to what is
termed a a u bey vie. Many cycles can be defmed at the
same time, as long as the simr of all of the subcycle
locations does not exceed the size of the memory.

(Oscillator frequeircy determines tlie riming resoludon of
the instrimientj anci shotild therefore be as high as
|)ossil:jle. However, memory access time and logic delays
limit the maxinmm oscillator frequency. Sticking to the
policy of using relatively inexpensive, reaiUly available
parts, a 16t>MHz osciilalor is used, for a best -case resolu-
tion of 0.25 ns. This ntmiber is an even divisor of 50 ns
(the pattern VO ports' mininumi cycle time) and provides
ade(iuate resolution In most cases.

The control timing generator's memory is eight bits wide,
each bit corresponding to a control signal output. Similar-
ly, tlie response timing generators memory is six bits
wide, one per response pattern cloc:k signal. The slintuhrs
tinrirrg generator has twelve-bit w^ords, however Six bits
are for stimulus pattern crlot^ks and the rest are for the
ECL marker' pulse, for testiJig lite three conf lit ions fronr
the master section, and for' both conditior\al ar^d uncondi-
tional end -of- cycle definition.

Two synchronous bits control each limhig generator. The
foLU' resulting operations are next subcycle^ next cycle,
hold, and inhibit. The next subcycle operation causes the
address counter to incremertt aird the new^ memory data
to be clocked out on the next oscillator' cycle. The next
cycle operatrorr is sinrMar, except that instead of iucre-
nrenting, the address counter loads the first address of
another cycle. Thc^ hold operation freezes the address
counter but allows the outptjt register to u|>date its
contents. Pin ally, the inhibit operation causes the oscilla-
tor to be completely ignored; notliing changes state.

The prescaler is a programmable sixteen-bit, di\ide-by-N
counter which causes the timing generators to hold for
N - 1 out of every N oscillator cycles. This lengthens each
subcycle and changes the Model D20's timing resolution
to N X 6.25 ns. The maximum subcycle duration is
2**'^ X 0.25 ns (409.6 |is).

At the end of each cycle, a next cycle operation occurs.
The timing generator address counters are loaded with an
address determined by the sequencer. This sequencer
makes the Model D20's on-t he-fly timing changes possible
by either causing the sante cycle to be repeated or
switching to a different cycle. Ilie sequencer functions
like a pattenfr I/O port configured for stimulus opemtion,
except that its memory contains eight-bit tags instead of
pattern data, and its four control bits have different
functions. Tlie sequencer is clocked once, fiUTrishmg one
tag per cycle. Startmg addresses in the timing generator
memories are formed by multiplying the tags by four
(left-siiiffing tjiem two places). Tliree of the four remain-
ing bits per-mit cycle-by-cycle control of trigger anning.

64 April 1 992 Hewleu-Packarci JouniaJ

)Copr. 1949-1998 Hewlett-Packard Co.

marker (trigger output) pulse generation, and breakpoints, of several state machines. T^e outputs of the run/stop.
The last bit designates the end of the sequence. tngger, conditioa and EOC/SEQCLK state machines are

combined with the prescalers output (PCLK) into the two
State Machines timing generator control bits. The EOC/SEQCUC state ma-

As can be seen in Fig. 5. the control logic section pro- chine monitors the nearH?nd-of-cycle (NEOCj bit from the

\ides control of the timing generators through the actions stinmlus timing generator memoi:>^ to deiermine when the

Se({ueftcer

Tinting Cycle Tag

Master

End of Sequence

Breakpoint

Arm Trigser

pTescaler

INH

PCLK

Frnm
lAaster '
Section

B Control
Outputs

g Response
► Pattern
Cliicks

Fig. 5, Timing module slavf? ,'3«ctlon detail.

ApriJ lDfl2 Hewiett P&ckarti Jnnrruil 65

)Copr. 1949-1998 Hewlett-Packard Co.

end of the cycle is at hand. It causes another cycle to
begin by initialing a npx! cycle operation in the last
oscillator period of the current cycle. It also issues a
clock pulse to tlie sequencer to make the next tag and
control bits available.

An end-if-ready (EIR) bit in the stimulus timing generator
memory works like NEDC, except that it is ANOed with the
READY line from the master section. If the Dirf is indicat-
ing that it is ready for tlie next cycle to begin when EIR is
encountjered, the cycle Ls terminated in a manner similar
to when NEOC occm^s.

An example will show how this end-if ready feattjre forms
the basis for synchronous Iratidshaking. Suppose that the
Dirr is a device that requires a continuous clock input
(to be provided by a Model 1320 control output) and that
it can request wait states, wMch must lengthen a cycle by
whole clock periods, up to some maximum number. This
is tyi)ical of a personal computer card. The Model 1)20
cycles would Ihen be progra mined to be thu maximum
length alio wed J but an EJR would be placed at the poiiil
where a cycle normally ends and at whole DLTT dock
periods thereafter. If the DUT is not requesting a wait
state, it drives READY true, and the cycle tenni nates at the
first EIR. If J on the other hand, the t)lT needs a wait
state^ it makes READY false, causing the cycle to go past
the EIR. The cycle will then tenninate at a subsequent EIR,
once READY goes true, or at the end of the cycle as
defmed by NEOC. Placing EIRs at DITT clock period inter-
vals ensures that the tester will always generate DUT
clocks with the proper period.

For each of the condition lines from the master section
there are a corresponding st^te machine and control bit
from the stimulus timmg generator memory. When a
control bit is true, the associated state machine tests its
condition at the end of that subcycle. If the condition is
false, the timing generators m\d prescaler are inhibited,
and all activity stops. Once all the conditions being tested
become true, operation resumes.

Referring back to the VMKbus example above (FHg. 1),
recall that the instniment must first wait for the asser-
tion, then negation, of DTACKm. by the DUT. For this
example^ two conditions couid be progranuned to c'orre-
spond to the assertion and negation of DTACK^. respective-
ly. The Model D20 would then be progranmied to test
these conditions at appropriate points in its cycles.

Wlien the sequencer arms the trigger in a particular cycle,
the trigger state machine inhibits the timing generators
and prescaler immediately before the beginning of that
cycle. Operation continues once a trigger is received from
the master section. Trigger events that arrive while the
trigger is not armed are ignored.

The Model D20 can be synchronized with an external
clock signal by feeding the clock into a trigger input and
then arming the trigger immediately before the expected
clock edges. The variable trigger delay (in the master
section. Fig. 4) provides the means to change the phase
of the instrument relative to the external clock. Tliis is a
Simple way to align stimulus patterns and control signals
with other events in the BUT. However, trigger inputs are

synchronized with the internal 160~MHz oscillator, result-
ing in 6.21^ ns of random error, or jitter

The run/stop state machine can he idle, paused, or
running. If it is idle (its initial state) or paused, the timing
generators and prescaler are inhibited. The running state
is entered, allowing operation to begin, when a rtm
eonunand is teceivt^d, A pause fl^, which can be set or
cleared at any time, is tested at the end of each cycle,
with the paused state resulting if it is true. A run com-
mand with the pause fiag set causes a single cycle to be
executed, while a rim eonunand with the flag cleared
either starts or continues the sequence. At the end of a
sequence, firmware places the instrument back into the
idle state.

The breakpoint and end-of-sequence control bits from the
sequencer are ORed together and then fed to the run/stop
state machine. The resulting sequencer pause line has the
same effect as the pause flag. Thus, the instrument
pauses at each break^^oint and at the end of the se-
quence. These two bits are separate so that breakpoints^
can be distinguished (by reading a status register) from
the ends of sequences.

The fourth control bit from the sequencer causes the
stimulus linung generator to produce two types of nuirker
pulses. Orie type is aJways two subcycles wide and can
be directed to one or both of the X'XIbus ECL trigger
buses. The second type of marker pulse lasts the whole
cycle and can be sent to any or all of the VXIbus TTL
trigger buses. This second pulse also appears in both
active-high and active-low forms on the front panel

System Deskew and Cable -Length Compensation

Suppose that two outputs from a digital instnmient wre to
have transitions that happen at exactly the sante time.
Tills is impossible to achieve In reality, and the difference
in tune between the transitions is called skew. A similar
notion applies to inputs that are supposed to sample DIJT
responses at the same time, but don't. Skew is llie main
component of tester timing error and should therefore be
minimized at the DUT.

There are many sources of skew in an instnmient like the
Model D20. A big contributor is the statistical variation in
delay between instances of otherwise identical timing or
data paths. T^o pattern 1/0 ports can have substantially
different delays from their pattern clock inputs to their
stimulus outputs. Pods will also differ from unit to miit.

Even two modules with equal delay wOl have skew
between their outputs because of backplane propagation
time. The farther a pattern 1/0 module is from the timing
module, the later it will receive pattern clocks. Each slot
introduces a delay of about 800 ps.

Now suppose that there are pods (and their cables)
between a Model D20's pattern I/O ports and a DIJT (see
Fig. 6). Suppose also that a stimulus transition is meant
to occur at the same instant (t = 0) as a response transi-
tion at the OUT For this to occur, the instniment nmst
generate the stimulus before t = 0. Likewise, the response
arrives at the response port after t - 0, To create the
proper timing relationships at the DUX response pattern

66 April 1992 Hewlett-Packard Jouinal

)Copr. 1949-1998 Hewlett-Packard Co.

clocks irmst lag stimultis paltem clocks by ^proxiniately
twice the delay of a pod and its cable.

Mmimizing skew and compensating for pod/cable delay
both require that internal timing relationships be atijusted
according to the actual delays of v^arious parts of the
sj^em. When a Model D20 module or pod Is manufac-
tured, its delays are measured and stored in electrically
erasable read-only memory (EEROM) in that module or
pod. Ever>^ time the instrument is turned on, its EEEOMs
are read by the firmware- which then uses the informa-
tion to compute how much delay to add using variable
delays in the pattern I/O and timing modules. This com-
pensates for the m^or eontributoi'S to skew, as weU as
the pod/cable delays, without any special measurements,
n^turing, or progranuiiing on the part of the user Even
after a failed module or pod \s replaced, the instrument
automatically meets its skew specifications.

In many cases there will be a significant length of cable
between the instrument (with or without podsj and the
DIJT, For these situations, there is a command that
aJlows users to specify the delay to the DIT and back.
The Model D20 then corrects for this round-crip time as
well as its own, in the manner described above. Since
many cables have specified propagation veloci^, timing
accuracy can be maintained at the DUX even in the
absence of pods. This feature also makes it feasible to
build custom interface circuitr>' and compensate for its
delay. For example, translators to and from ECL levels or
differentia] drivers and receivers for the SCSI bus could
be employed.

Integrator

^r HP 75000 V
Made! D20

Stimulus

rp Port :|

R«spans«

Stimulus at v/

Model DZO A.

Slimitlus
ai DUT

Response
lit DUT

Response at
Model 020

Stimulus
p0d/CibFe

0«l4V

Pad/Cable
Oeley

JCZ

t«0

Fig. 6 Foil aiid rable delay compensation.

Paflem
Clock

Comparitor

Ctock

V-

Pettern

Clock

Integrator .

Voltoge i x^ /

ThrEshotd Voltage ^ ^v,/

(From OAC} r

Pattern ' f I

cjock ^;^ ^

Delay
Fig. 7. \ariahlf: clock dr-lay.

The maximum possible delay from a pattern clock at the
output of tlie tinxing module to a stimulus outpui (includ-
ipg backplane, pattern I/O port, and pod delays) is a
knovtTi constant. Since actual delays are always lower, the
Model D20 can be deskewed by adtUag an appropriate
delay in each port's clock path. The circuit that does this
is shown in Fig. 7. When the pattern clock arrives, it sets
the Hip -flop, which opens the switch and allows voltage
to star! building on the integrator capacitor Wlien this
voltage crosses a threshold set by the digital-! rj- analog
converter (DAC), the comparator trips. This generates the
delayed clock signal and resets the flip-flop, closing the
switch and rai)idly resetting the integrator in [ireparation
for the next patient clock. Thresholds that are more
negative take longer to reach and therefore result in
longer delays. The total range of delay variation is 25 ns
and the worst-case resolution is 130 ps.

To contpensate for pod and cable delays, response pattern
clocks nnist be delayed with inspect to stimulus pattern
clocks by approximately 50 ns. The cable length com-
pensation circ:ulLry in the timing module (Fig. 5 J accom-
plishes I his by delaying the two control bits to the
response timing generator with a twelve-stage tapped shift
register This results in up to 75 ns of delay in 6, 25-115
steps. The clock delay circuit in each response port
interjiolates tiiese steps and deskews the port as de-
scribed in the paragraph above.

The control timing generator is much faster than a
w^orst-case stimulus port located at the far entl of the
back^Dlane. Delay must therefore be introduced to deskew
the control signals. This is done with the same tapped
shift register thai is used for the response timing genera-
tor The tw^o control bits and the accompanying oscillator
signal are then fed through ta^pped delay lines to subdi-
vide the 6.25-ns shift register steps into tjiiarters. Thus,

April 1 092 Hewiett-Packitrd if >iim al 67

)Copr. 1949-1998 Hewlett-Packard Co.

control timing generator delay can be a4justed with
1.56-ns resolution,

Tlie most-sign ifieant causes of skew are nieasiirpd or
characterized at tiie factor^' and conipensated in the
deskew process. The many factors that cannot be com-
pensated combine to form tlie Model D20's skew specifi-
cation. Two main somx'cs of this residual skew are the
differences in delay among the eight bits of a port and
between rising an<i falling edges. (Jther contributors
include power supply and temperature variations, aging,
inconsistency between backplanes, and available deskew
resolution. The net effect is that stmiulus transitions
(excluding going into or out of tristate), control signal
transilions, and actual response sampling times, will aH
be within ±3 ns of their programmed vtUiics. This gives
the Model D20 a pin-to-pin skew of 6 ns.

Since all actions are initialed by ci^stal-coii trolled circuit-
ry, an additional error of only 0.01% is introduced for
events that are separated in time. This is usually insignifi-
cant, being on the order of picoseconds in most cases.

Goncitision

The HP 75000 Model D20 was created to fill the need for
digital stimiilus/n.*sponse capabilitj"^ in a wide range of

manufacturing functional test applications. Characteristics
of digital interfaces and the VXlbus platform were ex-
ploited in the design, resulting in a high-perfonnance
instmment that is both cost-effective and easy to inte-
grate and use,

Acknowl e d gme nts

No project of tiiis size is brought to completion without
honest efforts from too many people to name here. Tlie
author would, however, like to recognize the accomplish-
ments of the rest of the R&D hardware and firmware
teanL Lee Gregory's architectural insight and sohd cLrcuil
design put the Model 1)20 on firm fooling from the
beginning. Phil Mlzuno intplemented the patteni t/()
modules. Tim Lock designed cost-effective yet EMl-pro<>f
packaging for both modules and pods. Rick Adams wrote
all the fmnware with the exception of the timing correc-
tion algorithms, which fell upon Jim Epstein's shoulders.
Bob Hetzel and Dave Swigen designed and built the
production test ajid calibration systems, respectively,
while Bob Vienot's technical skills continued to amaze us
all Plnally^ Lirr>^ Jones provided the leadership and the
glue for the team, making the tough calls when necessary^

68 .^pril 1992 Hewiett.'Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Digital Test Development Software for
a VXIbus Tester

This software provides ease of use and direct control for the complex
hardware of the HP 75000 Model D20 tester It uses a spreadsheet
paradigm and separates the programming of pattern data from that of
timing,

by Kenneth A. Ward

The HP EI496A digital lest development software is
designed to make it quick and e^isy to use the HP 75000
Model D20 VXIbus digital funclional tester (see article,
page 59). In one sense, the software acts as a front panel
for the iiistnnnent; since the Model 1)20 consists of
VXIbus modules, it has no conventional front panel. The
IIP E1496A digital test development sofi^vare provides the
user ^Ith a graphical environment in which digital tests
can be developed and debugged. The challenge for
softwaie Uke this is to let users think in temis of the
problem they need to solve instead of thinking of how to
program the hardware.

Hardware Overview

The HP 75000 Model 1)20 hardware consists of two types
of modules: the HP E1450A timing module and the HP
EI451A and E1452A pattern \/0 modules. The pattern 1/0
modules contain l.he digiUil stimulus and response data.
Each module has 32 channels, divided into four port*s of
eight bits each. Each port can be prograimned for either
stimulus or response, and has the aljility to do a real-time
compaje or to record the response data. Each port can
store up to 65,535 patterns, and cait be clocked at up to
20 MHz. Stimulus data for each port can be an eight-bit
value or can be tri state (not driven). Expected response
data can be an eight- bit value or don't care. Up to four
ports can be grouped together to foim pin groups up to
32 bits wide. Each port can be externally paced, or can
be programmed to take timing from the timing ntoihde
via one of twelve timing channels. Although each port
can be clocked at most every 50 ns (20-MHz maximum
clock rate), the timing module provides 6.25-ns resolution,
so two different port^s can be clocked just 6.25 ns apait.

The timing module provides the timing for the pattern
modules along with high-speed control outputs, condition
inputs, and triggers. There aie six tijning channels for
stimulus timing and six timing channels for response
timing. The eight high-speed control output lines can be
programmed to provide arbitraty digital control wave-
forms at clock rates up to 40 MHz. Ten condition input
lines and a ready irHHit line allow h;mdshaking with the
device under test (DDT). The timing module also hiis the
ability to wait for and produce triggers so the test can be
coordinated with other tnstniments.

The tiniing module is progranimed in terms of timing
cycles. Each timing cycle specifies the length of time for
the cycle, when each timing channel will produce a clock,
what the wavefomi for each control output is, and whai
to do with the condition and ready uiputs. Up to 256
timing cycles can be defined. Each of the 65,536 vectors
can refer to any of these tinting cycles, potentially using a
different timing cycle for each vector and switching
between them with no pause in the test. This is called
changing timing on the fly.

Massive amounts of data are involved here. For a system
with ten pattern VO modules, there can be over five
megabytes of pattern data. There can be 256 different
timing cycles, each specifying timing for twelve timing
channels and waveforms for eight control output lines- A
friendly means of entering, editing, aiid viewiiig all of this
data is highly desirable. The Model D20 modules have a
conunand set that is coitipatible with the Standard Com-
mands for Programmable Inslni merits standard (SCPI),
but SCPI is a textual, prograuHnatic interface. Wha.t is
needed is a visual interface that gives the user a feeling
of direct control of the hardware.

Software Desfign Decisions

Presenting massive amounts of pattern data to the user
Wiis the first problem to solve. After surv' eying several
different methods, tJie spreadsheet parytligm was chosen.
It was exix^cterl that users would already have some
fanUharity witii spreadsheets, and could apply that knowl-
edge to make the IIP Ei496A digital test development
software more immediately intuitive.

The next important decision was to separate the program-
ming of pattern data from the programming of riming.
The hai-dwaie Ls divided in this manner, and there are
many benefits that c^m be realized by separating the two.
The most common DUTs envisioned for the HP 75000
Model D20 hardware are digilal devices, which usually
function in tenns of cycles. Anytime a cycle is executed
on a bus, the times when the values change on the bus
and the states of the bus control lines remain constant
every time the cycle is executed. The only things that
change are the values on the bus. Separating the timing
from the pattern data allows the user to program the

April 1992 Hewlett-Packard Jotunal 69

)Copr. 1949-1998 Hewlett-Packard Co.

-I —

Pfh Group Nflme Type

Oefmg Pifi [jro^fps

Address

Number of Pins

♦ Pattern I/O
^ Contol Output

Mode

# Stimulus

^ Compare

^ Record

StimuEuS Timing

Response Timing

^ Ejctemai Pos

^ Ejttefngl Meg

^ Stimulus Ttming

^ Stimulus Timing

^ Stimulus Timlf^

^ Stimulus Timing

^ Eiflernol Pos

^ E/ternal Neg

^ Response Timing

^ Response Timing 1

^ Response Timing 2

^ Response Timing 3

^ Response Timing 4

^ Response Timing 5

DataOut(16)

Pattern I/O

StimyJus

Stimulus

Timing 1

DataN16J

Pattern I/O

Compare

Response

Timing

AddrStfobe

ConlroJ Output

2 C

ADD

2 I

DELP-E

2 C

Clear

2 I

CANCEL

Fig. 1 . Oefirre Pin Groups dialog box.

digital test \hu same way I ho DUT works, a mEyor advan-
tage.

For the HP E 1496 A digital test development software, this
meant that there woidd be two spreadsheets: one for
pattern data and one for timing cycle definitions. The
tinting events are specified graphically, since timing
infonnation is inherently graphical, like a data sheet
timing diagram.

The HP E1496A digital test development software is
designed specifically for the HP 75000 Model D20 haid-
ware. [t is not meant for general-purpose instrument
control or for integrating multiple instmmenls into a
complete test system. Tlie ptn^^ose of this software is lo
create and edit the digital test, run the hardware for the
purpose of debugging that test , and produce an SCP!
output fde that contains all of the commands to program
the hardware with the defined test.

Denning Pin Groups

The user wants to program in terms of DIJT names, such
as address, rather than in terms of the tester, such as slot
4, port. 1. The software allows the user to enter names
that represent the pin groups on the DUT Tw'o types of
pin groups can be defined: pattern I/O and control output.
For Dl^T pin groups that have large nmnbers of pins and
values that change oi^ly once per timing cycle, it is best
to use the pattern module ports and the pattern I/O pin
group tyi^e. For this type of pin group, three other
attributes must be specified: the number of pins, ttie
mode, and the timing channel. The nuntber of puis can
range from one to thurty'two. The mode determines
whether the pin group is to be a stimulus to the DUT. to
perform a real-time comparison of the response from the
DUT, or to record the response from the DUT The timing
channel specifies which timing-module timing channel the
pin group will use for timing, or if it is to be externally

paced. W\wu assign ir^g timing channels, if two pin groups
specify the same liming channel they will always have
I be same timing. If two pin groups specify different
timing channels, they can have different timing.

Fig. 1 shows the Define Pin Groups tlialog box with the pin
group Address being defined. As a result of this definition,
the software will assign three ports of a i>attem 1/0
module io be Address, and will program them to be
stimulus ports that are clocked from stimulus Tiniing
channel 0. The assignment of pin group names to tester
ports is automatic, taking the first available ports where
there are enough contiguous unassigncd ports to satisfy
the specified number of pins. This assigiunent can later
be viewed and modified by the user.

For DIFT pin groups that are control pins, it is best to
use the timing module control outputs and the control
output pin group type. Control output tjpe phi groups can
only be one pin wide, and the mode and timing channel
attributes do not apply, since they are for controlling
pattern I/O ports. A pin group assigned to be a control
output is automatically assigned to the first available
control output line, like the automatic assignment of
pattern 1/0 type pin groups to pattern I/O ports.

Defining Timing

The tiniing cycle spreadsheet (Fig. 2) allows the user to
enter Dl'T timing infonTiation graphically. The spread-
sheet has DUT pin group names down the left side, one
per row. and has tinting subcycle numbers across the top,
one subcycle per column. There are 1020 subcycles
available. Each timing subcycie has a cell for defining a
timing event for each pin group. The timuig subcycles are
grouped together and named to fomi the timing cycles.
Each subcycle represents a period of time equal to the
system tiniing resolution, which can be set by the usen
Eac!i tiniing cycle represents a period of time equal to

70 .^piil 1992 Hewlett-P^'kard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

*-J

"Tr^snc CyC'S Spreadsheet

— j

Resolution fs:

12.50 nSec CLifrent sub eye it ■$

' - " " " *c 5Z50 nSec

Pm Group

Cyctes

Read

1 ' ~ '■ -- ' 5 c

" • - J

Address [24]

Stim ->

X : ; :

. : iX : J ; ■ :

. 1

1 DataOut [16]

Stim 1 ->

-f^

; : : '. y ' ■ -

1. r

i^ :

: [n^;

Datain [16]
AddrStrobe

Resp <-

CntlO ->

' i 14 i

:::j::j:::j:::;jii;::t:T:;;;:;:;v;;;r:r:T:_ii

\\~^ i

.„.:.... :....i^^.„J ; !

- .J _J^ ' " "

* 1 1

1 1 < 1 < "

r:>

-1

Fig, 2, Tmiirtg cycJe spreadsheet ^s^iih tiniing fUIed in,

thc^ system tiniing resolution times the number of sub-
cycles m the timing cycle, and must be at least 50 nano
seconds long (20- MHz maximum clock rate). The system
timing resolulion must be a multiple of 6.25 ns. the
minimum system resolution. The maximum Timing resolu-
tion is 0.4096 nis (65,536 times 6.25 ns).

Ever>' pattern L/0 tjpe pin group must have one antl only
one timing event per timing cycle. The control output
type pin groups can have multiple timing events per
timing cycle. Timing information is entered into the timing
cycle spreadsheet by selecting a cell, and then selecting
the timing event to go into that cell from the Timing Cell
Values menu (Fig. 3),

Once the timing cycle waveforms have been entered, the
length of the timing cycle must be set. This is done by
selecting the suhcycle column that is to be the last
subc*ycle in the timing cycle, imd then selecting a menu
choice. A heavy vertical bar at the end of the subcycle
indic:ates the end of the cycle. Beyond the end of the
cycle, the subcycle tnimbering starts over again from
zero, since this represents Uie mmiber of the subcycle
relative to the start of the cycle. The subcycles lo the

Timing C«ll Values

Ta Deia
To 3 State
thsnge Dale
Change 3 State

Sentple Data
Ofin'tC&re

r n
1 ^

TdI

Too

Y««

lYi^l

CItar

1 1

Fig* 3. Timing Cell Valu a a menu.

right of the end of the cycle are now a\'ailable to define
another timing cycle.

Finally, each timing cycle must be given a name. These
symbolic names are used by vectors in the pattern
sequence spreadsheet lo reference the timing cycles.
Timing cycles are named by selecting the entire tinnng
cycle and then selecting a menu choice, which brm^ up
a tlialog box for entering the desired name.

Defining Patterns

The pattern sequence spreadsheet (Fig. 4) allows the user
to view iuxd edit the test vectors. The pattern I/O type
DLJT pin group names are on the left, one per row.
Across the top arc vector immbers, one per column.
There are 65,5^35 vectors available. Each vector has a cell
for the value for each pin group, and in tJie row labeled
Timing Cycle^ a cell for specifying the name of the timing
cycle to be used For applying that vector. Tliese timing
cycle names link the vectors to timing cycles defined in
the timing cycle spreadsheet. The timing cycle defines
wheti a pin groups port data is clocked, while the pattern
sequence spreadsheet defines what that data is. In the
example shown in Figs. 2 and 4, each vector that refers
to timing cycle Read will be 50 ns long, and will clock out
the Address value immediately Any vector that refei's to
timing cycle Wnte will be 100 ns long, and will clock out
the Address value after a delay of 25 ns.

Data is entered into the pattern sequence spreadsheet by
selecting a ceU and then entering or editing the value for
the cell by using menu choices or the keyboard. The
operations of entering data and mo\ing from cell to cell
are consistent vsith other spreadsheet programs. If a
timing cycle name is specified for the vector and that
timing cycle specifies that a pin group should be Instate
or don't care, then the corresponding cell on the pattern
sequence spreadsheet contains an X to indicate tltat no
data needs to be entered for that cell. Data can also be
specified as tristate or don't care hy entering an X into
the c^ell For pin grfiups of more than one pin, the pin
group can be expmided Into one row per bit, allowing the
values to be viewed and edited as binary digits. The base

April 1992 Hp w I ei:t-Pai' kard Joiimul 7 1

)Copr. 1949-1998 Hewlett-Packard Co.

in which the pattern sequence spreadsheet displays data
is selectable.

When the development system software is connected
directly to the HP 75000 Model D20 hardware, more
pattern sequence spreadsheet features become available
that are very useful when debugging the test. For pin
groups that are programmed to record input data, the
data wiJl be read back from the tester and displayed on
the pattern sequence spread shed when the test pauses or
stops. If a comparison error is detected by the hardware,
the pattern sequence spreadsheet will update and display
the vector thai failed. For each pin group for which a
failure was dctectctl, the actual received data is displayed
along with the expected result and the pin group mask
value. For each pin group programmed to compare data,
the compLue data mask value caii be set to mask off
individual bits from the comparison. Breakpoints can be
set on vectors; these cause execution to pause before the
vector is executed.

Importing Pattern Data

For users who generate vectors with a program or with a
sinmlator, the development system software can import
files m the pattern capture format (PCF). This is an
ASCII file format designed by the Manufacturing Test
Division of Hewlett-Packard for just this pur]>ose. If the
user produces vectors in the PCF format j or translates
simulator output to the PCF format, the HP E1496A
digital test development software can bring those vectors
into the pattern sequence spreadsheet.

Combining Tests

Tests can be combined by melting the currently loaded
test with a test stored in a file. This allows a test to be
developed in a modular fashion. A test can be created as
a number of short tests, each for a different p^ul of the
DUT, and then all of the sections can be brougfit together
to form the complete test.

Mixed^Signal Testing

Mixed-signal testing requires the ability to coordinate with
other instnunents. The HP 75000 Model D2Q hardware
does til is by using triggers* On the pattern sequence
spreadsheet there are two rows labeled Arm TrEgger and

Assert Marker. Entering On into a vector on the Arm Trigger
row will eatise the tester to wait for a trigger before
executing that vector. Entering On into a vector on the
Assert Marker row wUl cause the tester to produce an
output trigger pulse.

Handshaking with the DUT

Synchronous and asynchronous buses both typically use
some kind of handshaking protocol to indicate when
more time is needed and when transfers can continue.
Asynchronous buses tyi^ically have control lines that tell
the DUT when there is data available, and other control
lines for the DUT to indicate when it is ready to go on.
For the control lines to tlie DUT, control output type pin
groups can be used. For the control lines from the DUT^
three conditional tests can be checked in the timing
cycles. Each conditional test is defined by gi\ing it a
nanie and specifying a Booleai^ logical expression that
uses ten timing module input lines (QO-09) as variables,
WTten a conditional test is enabled, a row for it appears
on the timing cycle spreadsheet, with its name shown at
the left (Fig. 5).

If Yes is entered into tbe condition row for a particular
subcycle, the test will execute tmtil a vector specifies this
timing cycle. Execution of this timing cycle will continue
imtil the subcycle containing the Yes is encountered. The
tester wUl then wait, until the result of the Boolean
expression becomes tnie.

Syi^chronous DUTs tyijically work in a different fashion. If
the DLT camiot respond at the expected time, it will
change the state of a control line to indicate that it is not
ready. This is sampled during the cycle, and if the DUT is
not ready a wait state is inserted into the cycJe. The
timing module has a special input tine just for situations
like this. Tills line can be checked with the End If Ready
test, which is enabled in the same way as the other
conditional tests. Another row appears on the ttnung
cycle spreadsheet when this test is enabled; it is labeled
End If Ready,

If Yes is entered into the End If Ready row for a subcycle,
the test will execute tmtil a vector specifies this timing
cycle. This timing cycle will continue to execute until the
subcycle containing the Yes is encountered. The READY

1 1

Pattern

Sequence Spreadsheet

Number Base

: 10

Pin GroLJp^^^^^

Vector

Address

00256

00139

01234

00235

A
V

Data In

00016

'00032 1 X

DataOut

00075

X i 00128

— 1 p ^

i i { \ \

r r
1 1

i_^^ — — _^_^

TinninQ_ Cycle

Read

^Write

jRead IWrite

L^ .-^

Arm Trigger 1

1 1

Assert Marker

1 1 1 1 F

—
^ \ 1 _l

^ ^ ^ 1 J

Fig- 4. PaUeni sequence spreadsheet with four vectors filled in.

72 April 199^2 HewJett-Packflttl Joumal

)Copr. 1949-1998 Hewlett-Packard Co.

_»

Timing Cycle Spreadsheet |

Resofutton Is:

1Z50 nSec Current sybcycle is

: 50.00 to 52.50 nSec

Cycles

Read

Write 1

Pin Group

Q '1 ;2 :j

^ ; 2 : 3 : 4 : 5

e - lo

1 ; 2 : 3 ' 4

Address [24]

StimO -'

:< ; :

;X : : :

DalaOul [t6]

Stim 1 ->

: !\ :

* ■ i I y ■

—^-

.; .

I ; : :<v .

Datalri 116]

CntlO ->

!♦ ;

r::i:::i;;;jB;:j;::j:;;;:;;::

AddrStfobe

■^ ;

i j. .M J

\ \ ]

.._,_|_„4— H*~

CondO

: . . ; :ves:

End If Ready

i t ►

* t 1 i i t
1- t 1 ] .1 «

4 1(411

^ —

> ■

Fig. 5* Timing cycle spreadsheet with condition and End ft flea dy at bottom.

input to the tiniiiig module is then sampled. If it is true,
the timing cycle ends just as if the subcycle had been
specified as the end of the cycle. If the line is not true,
the timing cycle will continue to execute. The subcycles
foJloi^ing the End Jf Ready would be programmed to provide
the wait state. If it is necessar>^ to check for more wait
states, the process can be repeated as long as there me
subcycies available. In this way, the test can be pro-
grammed to tolerate a variable nuntber of DUT wait
states.

Debugging the Digital Test

There are two aspects to debugging the digital test:
running the built-in rules check to citeck for violations of
tester rules and constraints, and running the test. The
rules check does extensive checking on the lest defined.
Many constraints need to be observed to ensuie thai the
test will execute in the manner expected. For example,
consecutive vectors may have been defined such thai
when the tinrung cycles they specify are put back to back,
they place timing events within 50 ns of each other. The
rules check ensures that the lest violates none of Ihe
constraints of the hardware.

To nin the test, the user selects a menu choice that
brings up a dialog box thai allows the user to nm the
defined test directly on the HP 75000 Model D20 hard-
ware. Fig. 6 shows the Run Test dialog box. From this
dialog box, the user can nm the test and examine any
data recorded or failures found as a result of running the
test. The test can be single^-stepped from either the start

of the test or from a breakpoint set in the pattern se-
quence spreadsheet. Ulien the test is paused, execution
can be continued tmtU the next breakpoint or imtil the
end of the test, whichever occurs first. The tiser can also
request direct I/O, which presents a dialog box that gives
the user direct control of the pins on the HP 75000 Model
D20.

Producing the SCPl File

The object of the HP E1496A digital test development
software is to produce a test that rmis on the HP 76000
Model D20 hardware. This is done by producing art
output file of SCPI commands. This file contains all of
the SCPl commands to program the instrument with the
defined test. It can be produced in either a portable
ASCn format or a more compact binary format. The
resulting file cait be later incorporated into whatever test
environment the user may have.

Conclusion

The HP Eli9*5A digital test development software is an
ImporlajU addition to the IIP 75000 Model D20 tester. It
allows the user to concentrate on creating the test for the
DUT instead of on programming Ihe hardware. The
graphical presentation allows the user to tmdcrstaod and
use the features of the hardware quickly and easily. The
spreadsheet metaphor allows convenient manipulation of
the large amounts of data involved. The software's abUity
to create and debug digital tesLs, yet cooperate in an
open environment by allowing vectors to be brought m

ll Load I II Run 1 |j Step J | Contmue j

Number ot limes lo run test: |i || Current Iteration; I

(1 .. :52767, or -1 for infinite) U=J l_J

Status

ll Pause I I Stop ^
|| Direcl I/O- II

} Completed tester bad> waiting m idle siote.

Quit Debug rxecgtimn

]

Fig. 6. Run Tesi dialog box.

April 1S92 Hewlett Packanl JoumaJ 73

)Copr. 1949-1998 Hewlett-Packard Co.

from Dtiier sources, and its ability Lo produce a test that Ackjiowledgments

is p*>rtaljle to other environments, make this software a Hie crfalion of this software was a leaxn effort. My

powerful tool thanks to the otlier menibers of the team for their help

with this papen Special thanks to Joe Ward, Jake Smaltz,
;md Don Lenhert for their help as well.

74 April 1992 Hewlett-Packard Journal

©Copr. 1949-1998 Hewlett-Packard Co.

The VXIbus in a Manufacturing Test
Environment

Engineers at HP's Loveland Instrument Division have found that using the
VXIbus and the SCPI programming language provides benefits such as
reduced test development time and system support costs.

by Larr>^ L* Carlson and Wa>Tie H. WlUis

The adoption of an indiLstry-staiitiard tnodulai' iiistninient
architecture was the natural evolulion for botli tlie
defense and commercial indugitries. Now, VXIbus is fasf
becoming one of the moduiai- arciiilectures of choice and
VXibus vendors aie providing usetB with a broad choice
of test tools such as instruments^ switches, DlIT inter-
faces, and special-purpose fimctions. Recentl}^ new
pro<kicls with tesJ capability not available in the IIP-IB
have enierged, \rXJbus users have access (o the same
compatibility benefits the industry has enjoyed for years
integrating HP-IB instnimeniation. 'VXIbus along with l.he
new standard insinunent language, SCPI (Standard
Conmiands for Progranunable Instnmients) promises
users greater nexibillty for building systems that are
much easier and less costly lo reconfigure or upgrade to
meet growing test requirements.

This article focuses on the benefits of the VXIbus and
SCPI in a commercial manufacturing application for
functional rest, The inforniation is ir^ai on the imple-
mentation of a new lest strategy and experience e gained at
HP's Loveland Instmmeut Division wiiert> piecLsion digital
multimeters and modular instruments are manufacture*!
This article also explains how^ I lie VTCItms and SCPI are
implemented to reduce test development time and system
support costs. It examines I he importance of these new
standards in building a stantlard test platform liiat is
designed to be easily upgraded and conngured for a
variety of testing applications.

Functional Test on the Manufacturing Floor

Tlie manufacturing profile at HP's Lowland Instrument
Division is characleriKed as low-volume ;iJid high product
mix. This means tluit production volumes ai^e on the
order of 10 to lOOs per month and the total number of
different products rs high, more than 250. Production
characteristics siic*h as thest^ typically mean that the cost
of testing can be very high because of the need for a
wide variety of test capability. Botli in-ciicuit and func-
tional test are employ e<l in this produc^tion situation.
Functional lest is almost always used because of the need
to do calibration and in-circuil test is used when the
economies justify it.

Functional Tester Characteristics

Historically, modular instrumenlalioii iias been an impor-
tant part of the test strategy. Test systems were typically

built using HP-IB rack-tmd-stack instruments along with
modular instrument products for housing switching and
some functional capability such as digital muhimeters.
counters, aitd digital UO. Lack of a laige breadth of
modular products to choose from w^as one of the ob-
stacles to taking full adi^euitage of these proprietary
modular systems. Finlhermore, their obsolescence meant
that few, if any, replacemerus w^ere available for upgi^ad-
uig tiie system, and long-term system maintenance was a
problem. An industry standard arcliitectLUe such as
VXIbus solves the breadtJi of product offering and ob-
Stjlescence issues.

Custom engineered products aie t>i:»ically built mto test
systems to meet special nieasuremenl and control needs
for functions not commercially a\'ailable. Custom equip-
ment is expensive to design and build and costly to
document and support. Modular instniment systems have
provided a v^ehicie for custom designs because of the
availability of breadboard modules that are powered by
mainframe power. The package, interface, and docimienta-
tion are providetl by the module suppber leaving the task
of designing and documenting the unique circuitry to the
test englnecning design tetuu. Eireadboard modules are
usually availatile for most modular systems including
VXIbus. However, VXIbus development tools (not avail-
able for tiie earlier modular systems) facilitate the job of
custom design. The real advimtage of the VXIbus is thai it
protects custom design iavestiuents because they can be
used on other compatible test plalfonus (jn die manufac-
t.unng tloor. On the other haird, because of the broad
choice of VXIbus (and compatible VMEbus) functions
available on the market, tlie tu^ed to build custom func-
tions is greatly reduced.

Standard Test Platform

In the Uist te[i yeai*s a large number of different test
systems werc^ developed t<i test Uie various product-S
introduced Into manufacturiiTg. There is a very high cost
associated with maintaining and supporting so many test
systems. Some of the older test subsystems have become
especiiilly difficuK to sappcHi because of poor parts
availabihty and equipmeul obsolescence. Today, products
are being developed at a faster pace, and competitive
pressures are driving the need for shorter time to market.
Therefore, test system (k^velopntenl titnt^ and cost ttuist
tie reduced. Also, the number of test platfonns required

April 1992 HewMt-Pii^kan! Journal 75

)Copr. 1949-1998 Hewlett-Packard Co.

Interlace
Tesi AdsptBr

fiigiijil
FuncliQrtii

Relay Duve
AC^C Powe<
Fixtum IdenlitJer
Tempemtuni
HP4BorRS-Z32

IftterconnecT

Assembly

Ftxiure

to test a rapidly expanding mix of pioriiicts rniist hp
reduced. This requires devising a test strategy' that not
only includes an upgrade path, but also ailows a suffi-
eiently equipped system to be reconfigured easily to t(\st
any one of many DOTs,

A generic test platform using standard hardware and
sofi ware architectures and a flexible DIJT inlerfaee is the
bfisis for this test strategy. Fig. 1 depicts this test plat-
fomi, which can lest numerous modular-type products.
T]m test plalfomi can be configured to test products
from simple switch nuiltiplexers lo precision digital
multimeter moduk^s. A flexlijJe Dl T interlace that allows
rapid system reconfiguration has a replaceable weajHHit
mechanism for protecting tJie interface adapter's connec-
tions.

Because of an anticipated broad offering ot prtulucts from
\^bus vendors, the generic test system can he upgraded
with new capability so that it can keep pace with new
product test needs and still keep the size of the test
system to a minimum. Also, by including the lest require-
ments of many existing products, w^e can migi"ate them to
I his new^ system to reduce the number of different test
platforms. As manufacturing is expanded to other loca-
tions around the glob<\ this generic test platform becomes
important in containing the cost of system duplication
and support,

SCPl plays an imporiant role in test development pnxluc-
U%ity and system upgrade strategy. Upgrading an older
test system's test code, typically written in various instni-
ment -specific languages, is difficult because the program
typically has not been well-documented and the original

Fig. 1. Test platform for testiiiig
modular type prodtK't^.

design engineer is ntit available lo make the modifica-
tions. The SCPi statidard instrument lattguage opens the
door for developing a test software that is haidw^are
independent. This allow^s subslitution of new^ hardw^are
[usually a superset of the old ) for old hardware and
requues only minor or no programming chtmges. Because
SCPI is an integral part of j:m upgrade strategy, products
are chosen that support it,

SCPI contributes significantly to test development produc-
tivity. Once a test programmer learns SCPI, there is no
need lo spend time leiUTiing the iustrument-s]jecific
CO n I man 1 1 language for each piece of equijiment in the
systeni, A 6:1 time savings in writing instnuuent drivers
using SCPI has been experienced by our manufacturing
test engineering group.

Floor space in numufacturing is costly The use of VXIbus
has lielped reduce a three-bay system to two bays- As
more VXIbus products becon^e available, equivalent HF-IB
rack-and-siack functionality will be put Into Uie VXIbus
mainframe to free space either for other rack-and -stack
fiuiciionality not yet available in ^Itlbus, or to further
size reduction.

Capacity flexibility is another key benefit of the generic
test platfonn. Having an entire production line go idle
because one instrument in the test system is down is
something manufaeturing managers fear. Having more
than one of the generic test platforms means that if one
system goes tlown for any reason, within a few minutes
one of the others can be reconfigured to get the produc-
tion line running again, thus cutting dow^ntime losses.

76 April 1992 Hewt^tt-P^kard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Test Throughput

WiUiout question, test throughput js an issue for the manufac-
turer who produces products in great volume. However, when
production volume is relatively low, tiiroughpul is an issue
when test system capacity is reached. The ability to inci^ase
throughput can eliminate the cost of equipping and building
duplicate systems in which more equipment has to be main-
tained, calibrated, and supported, thus raising overall support
costs. Tlie \^?Qbus is expected to enhance the ability to line
tune the generic test system for optimum throughput.

So how does t-he \rxibus improve system throughput? \^XIbus
manufacturers are pro\iding the test-and-measurement mar-
ket with intelligent message-based TOTbus Instrument mod-
ules whose measurement through|?iit is much greater than the
previous generation of HP-IB instruments* Advances in tnstni-
ment language interpreters and faster instnuttent reconfigura-
tion designs are responsible for much of this improvement.
For even higher throughput speeds, register-based program-
ming \1a direct memory-mapped access to regisiei's on either
register-based or message-based instruments is possible. Hav-
ing the flexibility of both register-based and niessage-based

programniing available in a single VX^us mainfiwne allows
test developers to develop the test, program quickly in the
fiigli-le\'Cl SCPl language, then improve it later w'ith register-
level programming where throughput bottlenecks have been
identified. See the article on page 41 for more about register-
based throughput.

Conclusion

Punctional test strategies based on industry standards hold
great promise for reducing time-to-niarket and total lest cost.
The VXIbus architecture can lower custom engineering in-
vest iTients because it is an easier environment to design and
support VXlbus c^an save costly rack space and protect in-
vestments from product obsolescence. l^XIbus integrates easi-
ly into a system with rack-and-stack HP-IB instrumentation,
and With SCPl implementations on both architectores, soft-
ware development and reuse lue virtually architectm'e inde-
pendent. Tliis gives the systems designer the greatest latitude
m matching the hardware to meet the test needs. Finally, with
\'XIbus implementations, the test developer has the flexibility
of accelerating the system's throughput to increase manufac-
turing productivity and minimize costly test system dupUca-
tiOE.

Authors

April 1992

Lawrence A. DesJardin

Larry DesJardiri is VXfbus
program managef at HP's
Love I and Instrument Divi-
sion, He also serves as sec-
retary on the board of direc-
tors af the VXf bus
Consortium He joined HP
Laboratorie?! in 1977 after
receiving a BS degree in
engrneenng from the Californsa Instdute of Technolo-
gy, He atso has an MSEE degree (1978) from Stanford
University Larry has held various engineerirfg and
management positions far HP's vol f meter and com-
pdter-aided-rest product lines. An expert on the VXl-
bus standard, he has written several techmcai ar-
ticles on the standard and is the recipient of the John
Fluke, Sr Memortal Award for participaiion in its tre-
at ion. His work with test equipment has resulted in
two patents on instrumentation techojqyes. He is a

meinher of the IEEE Insirumentation Society and the
American Society of Test Engineers, Larry was born in
Redwood City. Caltfornia and now lives v^/ith his wife
in Long mom. Colorado. Skiing, bikmg, scuba diving,
and boanjsailing ere among his leisure activities,

14 D e s ig ne r's Pe rsp ecti v e ,

Gregory A. Hill

Software development engi-
nner Greg Hill developed tv/o
\jf the gale arrays used in
HP's VXlbus products. He is
one of the authors and archi-
tects of the VXthus specifi-
cation His current re spans i-
bilittesirfctucfepanicipaiiiiy
as a technical representative
to the VXlbus Consortium and as VXlbus Technical
coordinator ai HP's Loveland Instrument Division {LIOJ,
Greg received his BSEE 1 1 977) and MSEE f 1 970]

Aprtt 1092 Ht^wli^ir-r^iit'kHrd ,liujmal 77

)Copr. 1949-1998 Hewlett-Packard Co.

degrees from Te^as Tech University He joined LID in
197S_ Before joinmg HR he worked on higti-vottage
pylse generation and EMP testing at BDM Corpora-
tion. HP products lie has worked on include ilie HP
3497A/3498A data acquisition and control unit and
the HP 323&A switch and lest unit. He also developed
a process control system and software for LID's
printed circuit board shop. Greg is the aythoi of two
articles on VXIbus protocol for tfie VXtbus Journal and
FS involved in VXIbus, VMEbus. and Futurebus+ stan-
dards activities. He was born ^n Wichita. Kansas and
now lives in Love I a nd^ Colorado with his wife and
two young boys. He is active m cbiirch activities and
ministnes.

Steven J. IVarciso

HP's VXIhus technical direc-
tor Steve MarcjscD joined
HP's Lave land Instrument
Division in 1979 He received
his BSEEdegreejn 1978 and
hi^MSEE in 1979 from Pur-
due University. He led the
m^^^ r design team in the develop-

^^'— ^' men! of itie HP 3Z45A uni-

versal source and assisted in the design of the HP
3235A switch and test unit. Before joining HP Steve
worked for NASA designing data commDnication in-
terfaces He has written several papers on the VXIbus
which have been presented at various test confer-
ences. His efforts in circuit design have resulted in a
patent for reducing settling time in filters. He was
born in Englewood, New Jersey and currently lives in
Longmont, Colorado with his wife and three children.
In his leisure time, Steve enjoys tennis, hikmg, train-
ing his golden retriever, and spending time with his
cfiildren.

24 Mainframe Firmvvare ~^^^H

Paul B.Worrell

Currently a project manager

for new software projects,
Paul Worrell worked as a
firmware design engineer
and project manager on the
VXIbus mamframe firmware,
^s^ Pay I b ega nhiscareeratHP
as a summer intern at HPs
Love I and Insirumeni Division
in 1979, arrd became a fulUtime employee in 1960. He
received his BSEE degree from the University of Mis-
souri in 1979 and an MSEEfrom Stanford University
in 1 984 througti HP's honors coop program Paul has
worked on the HP 3421 A data acguisition control unit
and the HP 4445BA software package, He has also
sen/ed as a technical representative to the VXIbus
Consortium. Paul was born in Hannibal. Missouri and
cuTemly lives with his wife in loveland, Colorado
His ouiside-of-woric interests include home improve-
ments, constructing automobiles, and building audio
equipment.

30 Real Time Multtteskin^ ]

Chnstopher P Kellv

^^^^P^^H Design engineer Chris Kelly

^^^^^^^I^^H was responsible for the f irm-

^^K flf^l warenntheHPi300B^si2e

^■^ ^^H ^nd HP 140EC'Size VXIbus

^^ft^, ': ^^1 controllers. Chr I sjoinedHP's

^H| ^^1 '- ^^^^^ ^^ ' ^^^^^ ^^ ^^ ^ ^^ '^ '^^

^^-^^ ■ ■■'^ ^^ I n 1 9 33 afte r r eceivi ng a n
mmiljjr mm jy s degree m computer sci-
^^m m mM ence from Colorado State
University that same year. He also holds a BS degree
in biology and chemistry (19751 from the University of
New Mexsco One of his past assignments was the
firmware revision for the HP 3457A multimeter Be-
fore joining HR Chris worked on real-lime data ac-
quisition systems, analysis systems, and control sys-
tems at Lovelace Biomedrcal Environmental Institute
in Albuquerque. New Mexico. He has authored and
coaiuithored several articles and papers in electronic
test magazines, computer science symposiums, and
scientific journa's Because he likes to work on the
boundary between ha^aware and firmware, his pro-
fessional interests include real-time operating sys-
tems and data acquisition firmware Work in church
organizations, public service communications wjth
ham radio, and severe weather spotting for the Na-
tjonal Weather Service are some of the activities he
is involved in. Born in Seattle, Washington, Chris now
lives in Love I and, Colorado wtth his wife and three
young boys, fn his spare time, he enjoys amateur ra-
dio {advanced class), shootmg sports, fishing, and
camping.

■35

VXIbus ProgranTTiiing In C

Lee Atchison

^^^^^ S oftware des i gn engs near

^^^^^^ Lee Atchison joined HP in
^^"^Pl 1 987 at the InformatJon Wet-

^^9i^MP. '.vorks Division in Cupertino,
California, where he worked
on SNA network software
drivers. He is now located at
HPs Measurement Systems
Operation, in Level and. Colo-
rado, Lee received BEE and BCS [computer science)
degrees from the University of Minnesota m 1987. For
yie VXIbus project, he worked on the instrument I/O
library, the instrument communication strategy, and
the software drivers for die HP V/36D controller Lee
is a member of the IEEE Test and fv^easurement So-
cial and the IEEE Computer Society, and participates
in VXIbus Consortium activities. He is also chairman
of the IEEE P-1 174 standards committee. His profes-
sional interests include mstrument I/O. networks, and
operating systems. Lee was born in Minnesota and
lives wEth his wife m Ft, Collins. Colorado. He is a
Walt Disney memorabilia collector

41 Matrix Relay Modules {

James B. Durr

Learning products developer
Jim Durr wrote the SCPI and
reg^ster-based benchmark
programs for the VXIhus
dense matrix relay module
Jim received a BSEET from
DeVry Institute of Technolo-
gy in 19B1. He joined HP^s
Lake Stevens Instrument
Division in 1931 and later relocated to HP's Lovefand
Instrument Division. Jim has developed user manuals
that cover SCPI and register- based programming for
VXIbus products. He has also developed manuals for
the HP 3245A universal source and for the HP 3852A
data acquisition and control unit, He was born in Riv-
erton, Wyoming and currently lives in Lovefand, Colo-
rado with his wife and two children He en|oys bird
hunting, skiing, and biking into backcountry lakes and
streams.

Sam S. Tsai

The electrical and mechani-
cal design for several of the
VXIbus modules such as the
HP El47ZAfiF multiplexer,
ihe HP Ei403AA/B active
module earner, and the HP
E1466A 4x64 matrix switch
are some of Sam Tsai's con-
tributions to HP's VXIbus
product line. Sam received a BSME degree in 1975
from National Cheng-Kung University in Taiwan, an
MSME in 1979 from Te>;as Tech University, and an
MSEE in 1987 from Colorado State University. He
joined HP's Loveland Instrument Division in 1979, One
of his early contributions was to the design of the HP
3235 A switch and test unit. Sam was born in Taiwan
and now lives in Westminster, Colorado with his wife
and two daughters. Teach mg Mandarin to his chil-
dren, watching movies, and landscaping are some Qf
his leisure activities.

Calvm L Erickson

A graduate of Colorado
State University (BSME
1978) and the University of
Manchester Institute of Sci-
ence and Technology
[MScEE 19851 in Manches-
ter, England, Calvm Erickson
joined HP in 1979 at the for-
mer Civil Engineering Divi-
sion in Loveland, Colorado Calvin was the project
manager for the VXIbus C-size system hardware and
switches and was the mechanical representative on
the original VXIhus standardization committee He
has worked as the mechgmcaf engineer on various
voltmeter and cardcage product developments at HP's
Loveland Instrument Division. .At the Civr I Engineering
Division, Calvm worked on distance meter product
development. He participates in the development of
young scientists and engineers by working in the vis-
tting scientist program at the high school where his
wife teaches He is also active in church activities

78 f>lot)er 1991 Hewtctt-Packaiid Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Catvin was born m Greeley, Cotarsrfo and currsitly
lives m LxjvelBnil. Colorado Travel, hiking, and ^iwq
5fe tiis maiD trrterests outside d woric

SS Diaitai Test Eqiittniieiil ^^^B

David R Kjosness

The devefopment of the HP
E1450A Timing moduie was

ihe mam responsfbility of
desjgn engcneer DavE K]OS'
p^ss. Dave joined HP in 1979
after receiving an MSEE de-

p^^^^^^P^ ^^_ gree 1rom the University of
ll^^ S^ Colorado that same year H^

^^^ ' also received a BA degree in

physfcs and ntathematics m T976 frorr* Western Slate

Coffege of Colorado . In ihe past Dave has worked on
an inie^ratBd ctrcuii for a fractional-N fretiuency syn-
thestzer, a timing generator for a proprtetary inte-
grated circyit tester, and various switching modules
for the HP 3235 A switch and test unit. His work has
resulted in two patents related to HF switching, and
his pro less I orta I interests include high-^peed analog
and di-gital drcustry. Gave was born in Gunnison, Col-
orado and now lives m iongmont. Colorado He is
married, has two children and is active in scouting.
To stay m shape. Dave enjoys running, bfcyding, and
wejghthfting He a^sa enjoys camping and handgun
shooting

69 Development Software ^^H

Kennetti A. Ward

Ken Ward is a member of
'hfi leam that developed the
L^ri^ware for the HP 75000
Model D20 digital functional
s ester He jomed HP's Love-
land Instrument Division in
1982 He received a BSEE
J -^ degree f 1 978) from Kansas
"* '^ S tale U n ivers i ty a n d an M S
m computer and informatmn spence \ 1 9801 from Ohio
State University. Before joining HP. he worked as a
software engineer at BeiS Tfilephone Labor atones in
Columbus, Ohio. Ken is a member of the IEEE and the
ACM. Born in Manhattan, Kansas, he now lives with
his Wife in Loveland. Colorado His leisure activities
include playing trumpet with several local groups,
hiking^ and camping rn the mountains.

tW v^mwMBmm^

ring ^^g

Wayne H.WJHis

Fonnerly a manufacturing

test engm Bering manager at
HP's Love I and Instrument

Division. Wayne Willis is
currently a sales devalop-
ment manager at the same
^ . .. * division. Before jOrning HP in

h^ ' \ 1979. he worked as an RSD

^^ ^ engineer for a company that

mariufaciursrG water analysis instrumentation.
Wayne received a BSEE degree from Iowa State Uni-
versity in 1973. He was born in Marshal Itown^ Iowa

and correotly dves with his wife and three children in
Lovelarwi. Colorado Wavne si^ftds mtich of his spare
lime playing with his ditldren and is an avid cimputm
hobbyist

Larry L Carlsan

Carrefitly a product manager
ai HFs Loveland [nsirument
Division, La^v Carison jomed
" n 1 9i2 after ^ecEiv^ng a
5-IiEE degree from Colorado
State University that same
year He aJ so received an
fvlSEE in 1957 from the same
school Larry has held post-
lions in prodoction engineering, product development
(analog voitmetersl, and marketing His publit^tjons
Include several application notes, and he is a coau-
thor of a basic instrumentation handbook. He was
borri and currently lives in Love land, Colorado with
his Wife and two children, both of whom are studying
engineermg at the University of Cotorado. Larry's hob-
bies and other interests include tennis, hiking, and
biking

81 Peak Power Afialy^erj

Dieter Scherer

Dieter Scherar was praject
manager for development at
the HP 8990A peak power
analyzer a? HP's Stanford
' ' /_A Park DivisFon. Born in Bad
J5c!^ Reichenhall in Gavana, he
U||HflpP attended the Technical Uni-
:S^^H^ vorsity of Munich, graduat'

"**^^^^^*^ ing in 1 967 with a Diplom
IngenieuT m eiecirical engineering At Stanford Park,
which he joined in 1967, he dessgned WEdeband hy-
brid ampJiliers, microwave oscillators, and mi.xers for
the HP 8ESQ family of synthesizers, was responsible
for the BF moduias of the HP 8662A synthesized sig-
nal generator and the fow phase noise circuits tor
that instrument, developed GaAs fiybrid circuits for
micfO wave signal generators, and served as project
manager for phase noise measurement mstru menta-
tion and the HP 6990 A One patent on a gain strobing
technique has resulted from his work In 1972 he re-
ceived an MSEE degree from Stanford LJnrversity. A
senior member of the IEEE, he has authored papers
on low phase noise design, RF synthesizer design,
phase nofse measurement, peak power sensors, and
peak power measurement. Since 1 9S1 , he has been a
part-time lecturer in RF design at Stanford University
Dieter's interests include furniture design, photogra-
phy, hiking, and boardsailing. He's married and has
two sons

William E. Strasser

Bill Strasser did analog de-
sign for the RF power and
ajicilloscnpe channels of the
H? B930A peak power meter
Since joining HP's Stanford
Park Division in 19B4, he has
designed power, phase
noise, and noise figure
instrumentation A memher
of the IEEE microwave theory and techniques group,

he is narrjed as a cthinventor on two paienis, orte on
a w^de dyoamfc rarrge amplrfi©' and one on pin
strobir^, Bill was hmn in Washir^n, U.C Hb re-
ceived his BSEE degree m 1984 from Lehigh Universi-
ty and his ME£ degree in 1986 frum Coinell Univefsi-
ty, spec" "" ^ ' :^owave theory and
etectfor s married. Wren he's rHS at HP

Of wtsfking rr. s ome, he etijoys tertisanrngand
other oiftdaor actrvitma

James D. McVey

tR&D engineer Jim McVey
was one of ttie designers of
the HP B390A peak pawer
analyzer ar HP's Stanford
Park DivtSEOn. He came to HP
in 1985 after rsieivingES
and MS degrees in etorical
engineering from Stanford
University in 19B4 and 1985
In addition to the HP 8990 A, he h^s contributed to the
design of the HP 8780A and 87B?A vector signal gen-
erators, the HP 117536 II F channel simulator, and tfte
HP 89810 vector modulation analyzer.

Wayne M. Kelly

Wayne Kelly received his
BSEE and MSEE degrees
from California State Univer-
sity at San Jose in 1963 and
1965, After ten years with
GTE Sylvania designing mi*
crowave components and
subsystems, he joined HP's
Microwave Semiconductor
Division itneit HP Assocfaies) m t975 and designed a
radar preamplifier. After moving to the Stanford Park
Division, he rtesigned a vector modulator for the HP
8780A and HP B702A vector signal generators and a
frequency agile upconvertor for the HP 8791 Models
n and 21 frequency agile signal simulators For the
HP 8990 A peak power analyzer, he designed the
1 05-GH/, +10-dBm sensor check source. A member
of the IEEE microwave theory and techniques group,
he has authored a paper on a figure of merit for X-
hand GaAs power amplifiers., and hrs work has ra-
suited in a patent on mixers and multipliers using
slot/cop I an ar transmission line. Born m Oakland,
Califnrnra, Wayne is married and has two cfiifdren,
He's a skier and has developed the special skill of
building massive wood decks on concrete retaining
walls

90 GaAs Technoiegy

Micfiael C. Fischer

CD eve I Dpm en t eng inee r M ike
.^^ Fischer has been with HP

..„£Si^^l since 1973. He has worked

on phase noise measure-
ment, developed frequency
standards, and contributed
to the development of the
HP 8990 A peak power ana-
lyser, for which he did sys-
tem design and testing, sensor amplther design and
testing, and verification source design. He's presenily
doing producibibty improvement engineermg. A mam-
ber of the IEEE and the Audio Engineering Society, he

)Copr. 1949-1998 Hewlett-Packard Co.

April imZ EewleU4'ai^km^] Jutimal 79

has aLJthored many techrncaf papers and ariicies on
the measurement and control of phase noise and fre-
quency stability, and is named an inventor on seven
patents on signal prooessmg and measyremeni and
on frequency standards A nattve ni Colenian, Texas,
he received his BSEE degree from tfie University of
Texas in 19B6. Before coming to HP, he designed fre-
quency standards and navigation receivers for Tracor,
Inc. and Magnsvox, Mike has three chtldren. He
serves as a Boy Scout leader and is interested in au-
tomobites, audio equipment, sailing, and photogra-
phy.

Michaet J. Schaessow

Mike SchoessGW joined HP's
Stanford Park Division in
19B1 as a production engi-
neer, then moved to RSiD in
1987 Since then, he has
contributed to the design of
the HP 36792A agile upcon-
verterandtheHP70lQDA
povver meter for the HP
8990A peak power analyzer, he vwas responsible for
the baseband circiiit design, ground management,
and electrical interference rnanagement. A member
of the Audio Engineering Society, he has coauthored
papers on graphic equaiizer design and Joudspeaker
equalization. Mike wes born in Milwaukee. Wiscon-
sin and received his BSEE degree from the University
[)f Wisconsin in 1981 He is married His interests
include ultrahigh -voltage research, kite frying, restor-
ing antique radios, goormet cooking, and hiking. In his
spare time, he vvorks on a design for the "ultj-
mate"cdmmunic3tions receiver

Peter Tong

^ Mow studying for JD and

MBA degrees at 3anta Cfara
V University, Peter Tong has
^ moved from the R&D lab to
I* "^^H^ * become a legal associate on
y , - ^^t- .Jim HPs corporate legal staff. A
native of Hong Kong, he re-
^^^^ ceived his BSEE degree in
*^^^^^^ 1 980 fro m the U ni vers i ty o f
Hawaii and his MSEE and PhO degrees in 1 981 and
19B5frnm the California Institute of Technology As
an R&D engineer with HP's Stanford Park Division
starting in 19B4, he was responsible for the design
and production introduction of the HP Ra47B and
fl347B noise sources and for microwave design and
calibration of the HP 8481 2/1 3/1 4A peak power sen^
sors He has published eight technical papers in the
fields of microwave design, optical systems, and
semiconductor technology, Peter is married, enjoys
tennis and swimmmg. and is presently serving as vice
president ol the California Institute of Technology
Alumni Association.

% Autoinatic CaJifaration

David L Barnard

^tttk A software des ig n engi rieer

^^^^s with HP's Stanford Park DivE-

^^ j^^ s ion, Dave Barnard was re-

hP ^^^ s pons ibke tor firmware de-
^. igr sign for the HP 899QA peak
y^l^^ power meter With HP smce

^^^^^^^^ 1 9BD, he did reliabi lity engi-
^^^^^^^^k 'leering for two years before
^^^^^^^^* ■ -'G V I ng to the RSi D Ja h ,
where he v^oiked on ihe HP 1 I729C carrier noise test
set. He received his BSEE degree m 1 980 from the
University of Colorado at Boulder and is a member of
the EE. Dave is active in his church and is interested
in music, particularly guitars. 1<eyboards, and MIDI
sequencing He enjoys traveling in Latin America and
studying the culture, and he participates in a bilingual
tutoring program He's a native of Longmont, Colorado.

James A. Thatmann

^0f- ■ J i m T ha I ma nn received his

^^F^ \ BSEE degree from the Uni-
■ ,^te^| versity of lllinojs in t976and

1 I'SilBtf fordUnivefSity in 1979.

Jl^*' Sirice 1 376, he's been a da-

Jffc ve Jopment eng i ne er with

jBP* HP's Stanford Park Division
*^^^ and has contributed to the

design of the HP 8683/84 signal genera la rs, the HP
lt729A carrier noise test set, and tiie HP 11759A/B
RF channel simulators. He also worked on the firm-
ware and automatic calibration scheme for the HP
B390A peak power analyzer. In his spare time, he's an
avid cyclist.

HenrY Black

Henry Black joined HP's Stanford Park Division in
19B8a& an R&D engineer He was responsible for
firmware development for the HP 701 OQA MIVIS pow-
er meter and the HP 8990A peak power analyzer Be-
forB coming to HP, he dtd earJy design work on syn-
chronous data communications with ICL and designed
6Q-Hz energy measurement instrumentation with Ro-
binton Products. Inc. He recently left HP to become
chief engineer with Information Consultants. Inc. A
registered professional engineer and an amateur ra-
dio operator, he was born in Wallasey. England and
received his BA degree from The Open University.

m m-iyilliWBtmrhftnttwtT

Koichi Yartagawa

Koichi Yanagawa was proj-
ect manager for develop-
mem of the HP 8751 A net-
work analyzer He's been
with Yokogawa 'Hewlett-
" ' Packardsince1974;andhas

n^. ^^^^ CO n tr i boted to the de s rgn of

P^ ^^ the HP 4194A impedance/

'•*' gain-phase analyzer, the HP

4278 A capacitance meter, and the HP 42841 A bias

current source. His work has resulted in one U,S, pat-
ent and several Japanese patents on analog circuits.
Born m Toyama, Japan, he received his BS degree m
electrical engineering from Tohoka University in 1971
and his MS degree m electrical engineering from Kyo-
to University m 1974, Has a member of the Institute
of Electronics, Information, and Communication Engi-
neers. Koichi IS married, has two children, and enjoys
rnusic and hiking.

110 M easy rem ent Co pr o cess or

Michael P. Moore

a Mike Moore was project
leader for the HP 8Z324A
high-performance measure-
ment coprocessor He joined
HP's Corvallis Division m
1 973 and contributed to the
design of the HP 85 and HP
. ^ -.: 87XM computers and the HP

'- ■ ' "^-- 82300AandHP82324A

measurement coprocessors When the HP 82 324 A
project moved from the Corvallis Workstation Opera-
tion to the Measurement Systems Operation (nuw the
Measurement Software Division^, Mike followed it to
Colorado, where he now fives. A native of San Fran-
cisco, he graduated from the U.S Naval Academy
with a BS degree in electrical science in 1 968 and
served ten years in the U.S. Mavy, attaining the rank
of lieutenant commander Jn 1975 he received his
MSEE degree from Oregon Stete University, specializ-
ing in solid-state electronics. He is married, has two
daughters, and enjoys camping, hpking, fishing, cross-
country and downhill skiing, and running.

Eric N. GulNrud

EricGullerud is a software
devebpment engineer vvith
HPs Measurement Software
Division. Born in Colorado
Springs, Colorado, he re-
ceived his 8SEE degree from
the University of Illinois in
19B1 and joined HPs Corval'
Its Division the same year
He served as a chip designer for HP Series 10 calcula-
tors, developed software for Northwest IC Division
design tools and for [C testing, and developed soft-
ware' for the HP a23D0A and HP 82324A measure-
ment coprocessors, mov^rrg back tu his nahve Colora-
do when the HP 823 ?4 A project moved. Enc is
married and has three children His leisure interests
include music, camping, and hiking.

80 October ISQl Hewlett-Packard Joumat

)Copr. 1949-1998 Hewlett-Packard Co.

The Peak Power Analyzer, a New
Microwave Tool

Gallium arsenide sensor design, a new calibration approach, switched
amplification and processing of the envelope signals, leveraged digital
oscilloscope technology, and micropracessor control provide
calibration-free, accurate pulsed microwave power measurements.

by Dieter Scherer, WilUajti E* Strasser, James D» MeVey, and Wayne M, Kelly

Microwave signals used in radar, telemetry, navigation,
and coinnumlcations applications are typically pulsed. A
Doppler radar, for example, operates on the basis of
pulse modulation and is critically dependent on die
characteristics of the pulse power envelope, such as peak
and average power, rise and fall times, puLse width, duty
cycle, and pulse repetition rate. For satellite communica-
tion links in TDMA (time division multiple access) mode,
the concerns arc absolute and relative power levels m\6
delays between uidividual pulses within a frame or from
fraiTie to frame. Even if the microwave signal is only
frequency keyed or phase swiiched, like a QPSK signal in
a digital radio application, it is often iniportant to mea-
sure power overshoot and ringing at transition times.

The perfomumce tjf systems like these can be detenninf^d
to a large degree by accurate power imd Lime nieasure-
nient5 of the microwave pulse envelope. One stage earlier,
the desigii, performance, and stress of the components
making up such systems can be characterised by pulse
parameters such as rise time, overshoot, peak powen
power compression, spike leakage, pulsed gain and
reflection, and gain suppression. Delay measurements are
also imptJriant:, not only along the nucrowave signal path,
but also bet ween tile control sigiiul and the micruwave
puise response, (teneraiiyj the microwave response of a
system or component to control stimuli is relevant in
analyzing pulsed perfomimice.

Common Ways to Measure PuJsied Microwave Power
What are the common ways to measure pulsed micro-
wave power? The simplest approach is the use of a
tliennocouple sensor and a power meter like the IIP
43 7B. This combination rc?ads the average iKJwer of tJie
microwave pulse train. Knowing the pulse tluty cycle and
tissuming a rectangular pulse shape, the FIP 437B can
calculate the pulse-top power.

Tlie spectnim analyzer can also be a tool for measuring
microwave pulses. For coiTecl atni)litude determination^
the desensiti^ation factor needs lo be added to the
displayed amplitude and the user has to distinguish
between line and pulse spectra Tlie spectrum analyzer
yields infonnation on pulse repetition fretjuency pulse
width, and pulse power. The accuracy uf tlie latter two
measurements again depends on the assumption of

rectangular pulse shape. Either method is highly inaccu-
rate if the pulses show significant overshoot, ringing, or
droop, and w^ouldn't work at all with an irregular pulse
train like the pulsed frames of TDIVL^ signals.

High-bandwidth oscilloscopes can be used in these cases.
The F!P 54124T, for instance, is capable of displaying the
RF signal diiectiy up to 50 GHz. Miile the sampling
oscilloscope has plentj^ of speed to observe the rise dme
and ringing in the applications mentioned above, it falls
short witJi regard lo accuracy and dynamic range.

Diode Detector with Oscillosrope

None of the above solutions can comprehensively satisfy
the measurement needs indicated at the begi ruling of this
article. What is missing is an instrumenl thai accurately
detects and displays the power envelope of conxpiex
pulsed microwave signals, allows instantaneous power
measurements on I he pulses and convenient measure-
ments of pulse paranu^lers, all at an ecoiiomic price.

A potential solution has been m use on benches for a
long time: a niicTowave detector connected to a 5(^ohm
oscilloscope input. However, it is dLfficult and cumber-
some to make meaningful measurements on the displayed
pulse with this setup. The video output of the detector is
far from being an accurate replica of the microwave
pulse envek^tie. vokage or powej'. The causes reside in
part in tiie oonideal detector, and in part in the limita-
tions of the oscilloscope.

Detector NQnIinearity. The diode detector has a square-law
response al kiw power (the video voltage is proportional
to llie square of I he RP" voltage), a linear response at
high j>ower. and a wide transition nuige in lietween
(approximately - 15 to +10 dBni). Even if tlie user
manages to calibrate tlie top level of the displayed signal
with a substituted known RF signal, any meiisurement
invoKing other levels, such as rise time, is highly inaccu-
rate.

Detector Temperature Dependence. The Temperature sensitive
ity of the diode dt^iector is high and complex, changing
rapidly with signal level and lemperature. For instance, a
lO^C change from calibration can cause errors in power
measurement as great as 5tM Very large enors can result

April 1992 Hewletl-Parkafti JcniniiiJ 81

)Copr. 1949-1998 Hewlett-Packard Co.

Detector Djade

jTypicaElv a

Low-Barrier

Schottky Diode}

Input RF Shurtt

Matching

Fig. 1. The basic diode tJet.ector,

from connecting the detector to a device under test thai
is hot or warming up.

Frequencv Response of the Video Oytput. The diode Junction
cajjaciiLuicc and device lead iniku lance are the nia^jor
device parasitics affecting Uie freciuency response of the
detector output. Tlie junction resistance aiso ehat^ges al
high signal levels, wliich indirectly causes tite frequency
response to vary with the signal level to some degree.
ThL^ unflatness of a low-barrier Schottky diode detecl<;>r in
X bantl may be around ±0.3 dB, which translates to a
± 7% en'or in powx^r

Mismatch Error. Mismatch representii a major enor source.
It is proportional to the product of the reflection coeffi-
cients of the detector iind the device under test fDlJT). A
typical low -barrier Scholtky detei tor (SWR < 1.5) con-
nected k> a t^LT with an SWli of 2.0 may give a maxi-
mum mismatch error of ± 13%. Unless tlie detec^tor and
DIJT impedatices are accurately known in rnagniLude and
phase, this error cannot, be calibrated out.

Microwave Signal Harmonics. The microw^ave signal and
harnioMics of die signal are detected as a vector sum
when the detector t^pe rales in tlie lineai* range. A
-2(l-dBc harmonic may therefore cause as UMich as a
21% error in powder measurement.

Slow Video Response. A detector reQiiires a RF bypass
capacitor on the video side (see Fig. 1). In combination
with the capacitive loading of the oscilloscopej this
capacitor slow^s dow^n the rise time of the ionise envelope
signal. The time constant can he decreased by choosing a
low^-impedance termination for the oscilloscope input, say
50 olmis. Unfortunately, the lower impedance also causes
a corresponding decrease in detector sensiti\ily because
the diode detector at low signal tevels represents a
current source.

Limited Oscilloscope Sensitivity. The low \ideo signal levels
obtained with a low-impedance termination are two
orders of magnitude below^ typical oscilloscope sensitivi-
ties.

This list of obstacles doesn^t yet inclnde the problems of
accurately calibrating the measurement. Nevertheless, the
concept of envelope detection is viable and holds die
promise of an economic solution. It requires only one
broadband microw^ave component to translate the pulsett
microwave signal to a video signal wiiere it am be
processed at much lower cost.

Commercial solutions based on the principle of diode
detection have been on the market for some time- For
example, the IIP 89t)0C/D peak powxT meters use diode
detectors, but represent only partial solutions. More
advanced are several non-HP peak power meters w^hich
address the detector deficiencies witli a calibration source
and limited calibration processing.

New Peak Power Analyaser

Tlie Ht* B9110A jjcak power analyzer (Tig 2) is a new tyi>e
of instrnrrieni lliat represents a comprehensive solution to
the f>rol>leni. Tin* design team took a fresh look at the
challenges of diode detection. Our goal w^j;is to trails lb rm
the inaccurate, cumbersome bench setup into a ( ar'efree
product that measures accurately and meets the complex
measurement leijuiremenls of modern microwave systems.
The use of GaAs IC technology in the sensor design, a
new calibration approach, switched amplification and
processing of t be envelope signals, broad leveraging of
niodeni digital oseilloseope teeimology, and extensive use
of microprocessor power in signal calibration and pro-
cessing accomplished this task.

Fig. 3 is a block diagram of the HP 89D0A peak power
analyzer.

Sensor. A new approach was taken in the sensor design J
Ij involves a Ga^As-based diode technology, integration of
a balanced circ nit on GaAs, and a new^ calibration scheme
(st^e the aiticle "GaAs Technology in Sensor and Base-
band Design,*" page 90). The use of planar doped barrier
diode technology improves the frequency response and
consistency of the diode characteristic.

A balanced diode circuit including the terminating load is
implemented as a t^aAs IG. The integration of the detec-
lor circuit minimizes mismatch loss^ thanks lo the veiy
low parasitic reactances on the 10. The bakmced circtut
effectively minimizes the potential problem with even-or-
der hannonics of tlie RF signal Both integration and
l)alancetl design help minimi^se I he effect of thennoelec-
trie voltages, which f oulci otheiwise mask low-levei
signals.

A three-dimensional calibratior^ scheme takes care of the
problems of nonlinearity, temperature dependence^ and
frequency response. Extensive calibration data is taken
over a wifle range of power levels, frequencies, and
temperatures. Condensed as a matiix of coetTicient sets,
the calibration data is stored on an EEPROM supplied
within the sensor. Wlien a sensor is connected to an
analyzer, the analyzer reads the calibration matiix and
reconstructs a precise curve of sensor output voltage
versus input powder for a given frequency and tempera-
ture. Tiie frequency is entered by the user^ and the
temperature is measured by a them^istor chip close to the
detector IG. The analyzer continuously rea<is the thennis-
tor chip and automatically triggers the rebuilding of the
sensor cune for ^my minor temperatiue shift. Tliis feakue
of caiefree calibration is especially helpful when a sensor
at room temperature is connected to a hot device under
test, such as a power amplifier (see the article, "Automat-
ic Calibration for Easy and Accurate Power Measure-
ments," page 9b},

82 April 1 992 H<?wlelt4'at.kcircl J oiunaJ

)Copr. 1949-1998 Hewlett-Packard Co.

Fig, 2. Tlie HP 8990A peak power
analyzer has two DOO-MHz-to-40'
GHz microwave input channels
and two 100- MHz ndeo input
channels. It makes calibration-
free power measurements on
pulsed microwave signals and can
display the video dri\ing signals
simultaneously. It operates with
the HP 848 12/1 a/1 4Atoiiiy of
peak power sensors.

Currently, three sensor versions cover input frequencies
from 500 MHz to 18 GHz, 26.5 GHz, aitd 40 GHz, respec^
tively. Sensors are specified from +20 tlBm to -32 dBni
and are usable down to -40 dBm*

Sensor Amplifier The problem of slow video response must
be addressed right at the detector output with the sensor

amplifier The system goal of <5-ns rise time requires
special measures to deal v^ith pulse flatness as well as
drift and low-sensitivity issues. Conflicts between speed
(\idco signals range from dc to 10-ns-wide pulses) and dc
stability are resolved with a split-path design (see article,
page 90). A microprocessor-controlled chopping circuit
ahead of all dc-coupled circuits perfonits an autozeroing

Postamplifief

O.Sto40aHz ^0^^^ ^^^

Ext Trig/ ^^^^
100 MKz Stope

OJtoWiSHz

ExtTfig/ ^^^
lOO-MH; Sco|»e

CfM

CHI

i:h2
urn

CH4

Impediince
Converter

Impedance
Coiivsner

Baiisbaiiid
Ampliliers

1.05 GKz
-)-iadBm ^
Pulsed

V o

TngCHI I

ltsck-B<i6-HoM
Circuit

AcqMisilion
IVlemiirv

1S Sttps

ISMHz

Trig CH2

Trig CH3

lOMtij
X Postampiilier

Ir nek -and -Ho Id
Circuit

Acciuisition
Memory

Trig CH4

11 Steps

TiniG-Basc

Micro
proue'S^df

Sensor
Chech S<iurce

mmHi Crysml
Beleijjnce
Dscillaiar

Fig, 11. 1''unctional block diagram of the HP 80^0 A peak power analyzer.

April 1992 H&wlett'Padsard Journal 83

)Copr. 1949-1998 Hewlett-Packard Co.

Multf layer Shielding Protects Mtcrovoft Sfgnals in High-Jnterference EnvirDninent

MultHayer shielding fs employed in the HP 3990 A peak power analyzer to minimize
interference from magnetic field sources. All three shielding mechanisms — reflec-
tion, absorption, and shunting — are used where apprapriate (see Fig 1 ).

The leveraging of an HP digital oscilloscope chassis, display, display driver, and
power supply creates a highly constrained design problem because the field
source and receiver geometrv is f i?;ed. Consequently, ttie interference ranr^ot he
reduced by orientation or physical separation of the sources and receivers The
most sensitive receivers are the baseband boards with their almost lOD dB of gain.
Aluminum castmgs provide channeJ-to-channel isoJation, gam stage isolation, and
substantial electric field shielding. However, these onboard shields are ineffective
in comhatmg the magnetic fields emitted by several internal corrponents. In addi-
tion to the switching power supply operating at 40 kHz, the CRT and the CRT driver
circuitry emit magnetic fields at 60 Hz and 25 kHz, plus harmonics.

The low frequency and close proximity of these magnetic sources result in a low
wave impedance, which is difficult to reflect with a conductive shield. Common
practice suggests the use of a high-permeability shield enclosure to shunt the flux
away from the baseband hoards, and a mu-metal enclosufe around the baseband
boards was designed for this purpose. With a\y assist from the partial CRT enclo^
sure, this enclosure lowers the 60-Hz interference to an acceptable level However,
the mu rtietal loses most of its permeability at the higher ( > 25 kHz) f retjuenciBS,
decreasing its ability to shunt the flux. An additional shielding mechanism, absorp-
tion loss, is caused by ohmic losses and is proportional to the square root of the
product of frequency, permeability, and conductivity. Although the mu metal con-
tributes some absorption at these frequencies, it is not enough. Even 1045 SAE
steel would probably do better.

To achieve the necessary shielding, an additional layer of O.OU-inch copper is
placed on the baseband shield on the sides facing the sources. Diis layer has a
negligible effect on the low frequencies, but it is increasingly effective as the
frequency mcreases. For example, although the copper does not shunt the fields, it
reflects an estimated 18 dB and absorbs an estimated B dB at 25 kHz Moreover, at
the 100-kHz harmonic of the fast CRT sweep, these values increase to 25 dB re-
flection and 15 d6 absorption. Th^s increasing attenuation of the higher harmonics
lowers the p^aks of the 25 kHz waveform m the time domain to an acceptable
levet.

The mu-metal CRT shield is used to lower the 60-Hz field further and has only a

minor effect on the higher f > 25 kHz) frequencies. This shield has an unusual
shape in that it does not fully enclose the yoke, which is the recommended method
of shunting the field. Although this geometry seriously limits its performance, the
CRT beam path is not distorted^ and the yoke need not be magnetically adjusted to
the shield. In addition, it is easily installed and removed The installation of the
baseband and CRT shields ret|U[res the addition of only two screws to the original
chassis.

The multilayer shielding achieves the required 40 to 55 dB of near-field shielding
white, leveraging the inexpensive CRT and CRT driver components.

James L. Sertsch
Charles W. Cook
Development Engineers
Stanford Park Division

CRTShielit

CRTYokB

Power Supply

Comrol Board

Onboard Shield
Aluntmum

Mu-Mctal —
Baseband Ba&rti Shm\i

Baseband Circuits ^^

Rg. 1. Shielding m tt^ HP 8SS0A pe^k pcFwer enatyr^r

84 April 1992 Hewlett-Packarti Joimtal

)Copr. 1949-1998 Hewlett-Packard Co.

function at appropriate breaks m the acquisition proce^.
This process, which is transpaient to the user allows the
system 10 correct offsets and offset drift with temperature
along the dc-coupled signal path. The dc and fast paths
are reunited before lea\ing the sensor head Both ends of
the standard D-foot sensor cable need lo be well-niatched
to avoid vidcK) signal reflections.

Baseband Circuits, Mo\1ng from the sensor to the instm-
nieni. the \ideo signal undergoes 94 dB of switchable
gain. This gain resolves the problem that the limited
sensitivity of an ^oscilloscope wotdd present with micro-
volt signal levels. The dc-coupled amplifiers, si^itched
with GaAs switch ICs. MM a dual task. First, they
project the sensor \ideo signal in coarse gain steps into
the limited dynamic range of the track-and-hold circuit
and later the analog- to-digitai converter (ADC). Second,
they limit broadband noise. The bandwidtli of the amphfi-
Cfs changes from > 150 MIz for higher signal levels to
2.5 kHz for the lowest power decade. Correspondingly,
the system rise tmie increases from a specified < 5 its to
<2&0 MS (see article, page 90)-

Acquisition and Digital Signal Processing Circutts. The

acquisition ci.rcuii:s follo\\ing the baseband circuits and
the digital signal pro<:essing circuits are to a large degree
leveraged from the digital oscilloscope technology of the
HP 54500 family. The puise envelope signal roughly
scaled by the baseband circuits, is subsequently sampled
by a track-and-hold ctrcuit at a rate of 10 MHz (see
"Acqtiisition Process'' later in this article). The hold level
of the track-and-hold output then passes through a
postanipliner wirli 15 One gain steps. In combination with
the baseband gain blocks, the postamp guarantees that
any input level in the specified -32-to-+2(J-dBm rar^ge
can fiU tiie ADC window.

The 8-bit resolution of the flash converting ADC repre-
sents a bit range of to 255. This t ranslates to 24 dB of
dynamic range referenced to the sensor input, if the
sensor wcn^ to operate solely in the s<juare-law range, or
to 48 dB for operation strictly in the Imear range. The
wide transition range betw^een square and Unear operation
causes most applications to fall between these numbers.
Tiie ADC output is captured by tlie 2K-byte-wido circular
acquisition memory.

The task f>f accurate time placement of t he received
pulse envelope is carried out by the powerful trigger and
time-base ICs. A 40-MHz crystal oscillator is responsible
for the time-base accuracy of 0.005%. A 68000 micropro-
cessor controls the signal processing and the monochro-
matic 9-in display The control code resides on a separate
memoiy board ai\d takes up roughly f>OOK bytes of ROM
space.

Dual Sensor and Trigger/Oscilloscope Channels, The peak
power analyzer is equipped with two sensor channels:
channels 1 and 4. This facility allows pulse comparisons
and delay measurements at different probing points along
a microwave path or between systems. With the capabihty
of displaying ratios of the channel inputs, the IIP 8990A
can measure pulsed gain and pulsed return loss (using
external dirt^tional couplers). The sensor channels have

internal trij^ering down to -30 dBm and a trigger
band^\1dth of 1 MHz,

Mtdtiplexed with each sensor channel is a \ideo input
channel. The purpose of the \ideo channels (channels 2
and 3) is twofold: they can be inputs for external trigger
signals when fast triggering Cbandwldth <I00 MHz) is
required, and they also serve as oscilloscope inputs with
100-MHz bandwidth and limited sensitnity (100 mV/div to
500 mV/dh'). With these channels, the HP 8990A can
simultaneously display control signals and the resulting
irucTowave pulse envelope and measure delay times
between them. It can also meastu-e transfer characteris-
tics like the power-versus-controI'Valtage sensitivity of a
pulse modulator.

Sensor Check Source, A built-in source provides a puJsed
or CW signal of +10 dBm ±0.5 dB at 1050 MHk. This
serxes two pun^oses. First, k acts as a source to verify
the operation of a sensor. Peak power sensors are fre-
quently used around high-power signals. Tlie sensor check
source Ls a convenient signal for checking the sensors if
the user suspects sensor damage after an inadvertent
connection to a high power level (damage level is speci-
fied at IW peak power for 1 ^is, not to exceed 200 mW
average). Second, the check source supplies a signal for
time calibration of the trigger circuits and the timing
between the four channels.

AcQuisitioii FrocesB

The time-base portion of the acquisition process is a
dtiplicate of that found in the HP 54500 family of oscillo-
scopes, while the vertical hardware processing was
modified to accommodate the greater dynamic range
requu-ements of the HP 8990A,

The sampling method used m the peak pow^er analyzer is
random repetitive sampling. In contrast to real-time
sampling, where the sampling rate must be at least twice
the highest frequency of the digitized signal (Nyquist
rate), random repetitive sampling can sample at less than
the Nyquist rale and still avoid aliasing.-^ Consequently,
lower-speed circuits can be used in random repetitive
sampling to achieve the same nominal bandwidth as
real-time sampling.

The transition from a higher-bandwidth circuit require-
ment: to a lower bandwidth is achieved in hardware
through the track-iind-hold diode bridge. Ideally, the
bridge is modeled as an SI'ST switt^h operating at 10
MHz, closed during the track mode for 50 ns and open
during the hold mode for 50 ns. In die track mode, the
capacitor tracks the input sigiiiil, and in the hold mode
the capacitor is isolated from the input signal. The charge
residing on the capacitor during the hold time is a
renmant of the input signal immediately before the bridge
opened. During this 50-ns hold period, the 8-bit flash ADC
digitizes the waveform. Conversion is initiated at a time
when the sampled signal has settled.

The practical bandwidth lindtations in the track-and-hold
process arc* a nonzero hold capacitanre and a finite diode
switching lime. PVjr the HP 8990 A, this translates to
appn>xiruately 2-ns rise and fall timers or a 175-MHz

April 1992 Bewlett-Packard Jfiunml 85

)Copr. 1949-1998 Hewlett-Packard Co.

bandwidth. Random repetitive sampling provides 100-ps
resolution at the fastest tinie-base settings. This theoreti-
cally translates to aix effective sampling rate of 1/100 ps =
10 GHz." Of course, tMs bandwidth is not realized be-
cause the track-and-hold circuitry limits the speed and
thus acts as a siurogatc anti-aliasing filter.

The 100-ps resolution results from the time-base IC and
the fine interpolator circuit, which time-s(re(ch«^s the
uncertainty of one 40-Mllz clock cycle. The iU-Milz clock
is used to count the separation between the trigger event
and the nearest data siuiiple. Hence the possible error is
from zero to one full clock cycle or eguivalently froni
to 25 ns. Instead of truncation, tliis residual time Is fed
into a time-stretcher circuit which accurately expands the
time duration of the signal The stretched signal is then
counted with the same 40-Mlk clock. The resultant
uncertainty of one full clock cycle is divided by the
stretch ratio, which is 250 in the HP 8990A. Hence the
equivalent uncertainty (one clock cycle) is 1/(40 MHz)/250
= too ps.

The input signal is continuously sampled at lOO-ns inter-
vals for the fastest tinie-base settings. The sampled data
is then successively placed into a circular acquisition
RAM that has 2048 frames (see Fig. 4J. At the end of an
acquisition cycle, tlie RAM data*s location relative to a
trigger event that occurred during the acquisition cycle is
determined. The samples are taken at exactly lOO-ns
intervals and therefore only one data sample's position
relative to the trigger event need be determined to place
the data appropriately in time. Botii pretrigger and
post-triggeT' data is gatiiered for each trigger event. The
proportions of pretrigger and post-trigger data are deter-
mined by counters, which are set according to the time-
base range and delay settings and the choice of left,
center, or right screen placement.

The sampling signal and the input signal are asynchro-
nous, so eventually all of the time slots, or buckets, will
be filled with samples. Since the samples are randomly
skewed in time between success ii^e trigger events, no
missing data or holes result in the recreated waveform.
Thus a requirement of the input signal is that it be
repetitive with a stable trigger event. For slower time-
base settings the time buckets will be greater than 100 ps
wide, reflecting the display's fmite number of horizontal
bits.

t, = Sampling Perind {10Q ns)

t Trlggof
2. Triggar^ J

3.Triig«r

Fig. 4, (a) Random repetitive sampling. The number at each sam-
ple indicates the trigger event used, (b) Circular acQulsirion
memory with 2048 time T>uckets".

Continuous random repetitive sampling offers mayor
advantages over sequential sampling. In sequential sam-
pling only one saitiple per trigger is taken, with each
successive trigger having an increased sample delay. In
random repetitive sampling, data is continuously acquired
at the san^ple rate, thus achieving a mucii faster display
and providing pretrigger and post-trigger data as well.

\Vhi\Q the oscilloscope design is mainly aimed at the
analysis of repetitive signals, it is also capable of captur-
ing single-shot events. The 10-MHz sampling rate records
the event with sample points every 100 ns, Witlt a criteri-
on of 10 sample points per event, the HP 8990A offers a
single-shot bandwidth of 1 MIlz.

Microwave Pulse Measurement Features

Digital signal processing makes full use of the pow-erful
timing and trigger ICs and the properties of random
repetitive sampling. The resulting features have already
found wide acceptance in the HP 64500 digital oscillo-
scope family^ whose feature set was heaviJy leveraged in
the HP B990A. The following are some of the capabilities
thai are most important for microwave pulse measure-
ments.

Time Windowing. The user of a peak powder analyzer often
rieetis to analyze a detail on a single pulse while keeping
the full pulse train in view. Time windowing provides this
horizontal zoom capability m\d allows measurements
within the time window.

Trigger Conilitioniiig. Many micro w^ave applications present
complex trigger situations that require more than a simple
edge trigger function to achieve a stable display. Trigger
holdoff prevents recurrent triggering on the subsequent
edges of nonperiodic pulse trains, pulse packets, or
bursts. Pattern trigger helps to specify a particular pulse
within a frame of pulses to be triggered on^ a useful
feature when chasing sporadic misfires of a niicrowave
transmitter, for example. Trigger delay, speciiled in time
or pub>e count, can be useful on long pulse trains to
zoom in selectively on a particular pulse.

Persistence and Envelope Mode, Radars often operate with
pulses that are extremely narrow compared to their pulse
repetition interval. The doty cycle can be 0.01% or less.
These signals are quite a challenge to fmd since most of
the time the pulses fall between sample times and are not
captured in the limited niunber of time buckets. With
iniinite persistence and envelope mode, they wiU eventu-
ally appear in a single pixel width and can then be
expanded by using time windowing. Random repetitive
sampling is a great advantage in this situation; a system
based on sequential sampling would take a prohibitively
long time to plot out such a low-repetition-rate signal.

Averaging. As lower-level signals are detect ed^ broadband
noise increasingly widens the trace of the amplified
signal. Choosing a narrower bandwidth, if possible, cuts
down on noise, but also slows down the systen^ rise time.
Averaging in the context of random repetitive sampling
means av^'raging sample points associated with the same
point in time with respect to the trigger event, but from
different acquisitions. With increasing averaging, pulses

86 April 1992 He wic'tt-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

hidden in noise eniei^e and take shape. The distal
averaging process filters noise like a low-pass filter viith
one important difference: it doesn*t result in a rise time
degradation.

Ratio in g Channel Inputs. Hie Waveform Matt? menu allows the
user to display ihe ratio of any two channel inputs, in
addition to performing many other useftil functions. For
exanipie. die ratio of the two sensor channels can convc-
nientiy show pulse compression when probing the input
and output of a limiter, or the irarisfer function (mWAl
of a pulse modulator can be displayed as a ratio of a
^nsor channel to a video channel

Amplitude@lline Markers. The HP 8990 A pro\ddes not only
amplitude and time nuu'kers, but also amplitude @time
markers. These denote power (or voltage for channels 2
and 3), power difference, and power ratio for a start time
and a stop time. The feature is useful in determining
power or gain variations along a pulse, such as pulse
droop.

Thirteen Measurements. Automatic level measurements on
micTowave pulses, including pulse peak, average, or
pulse-top power, and lime measurements on pulses,
including rise time, pulse width, and duty cycle are
implemented as siitiple bltie-key shift functions. The
rpfprenre levels for these measiu^emenis, that is, pidse top
(lOOKt) and pulse base (0%), are histogranvbased accord-
ing to IEEE standards.

Applications

The combination of two microwave sensors and two
video inputs, able to make complex microwave and video
pulse-measurements in one instrument and relate them in
level and time, promises broad applications in many
areas.

Radar Components and Systems. Starting out with a tradi-
tional area of peak power measurements, the character-
ization of the power transmitter is central to radar
perfomtance. Peak and average power, rise time, over-
shoot ^ and droop are standard measurements at the

output of the transmitter, ^"ith the use of coi^lers, the
dual microwave channels facilitate measurements of
pulsed gain, gain compression, and pulsed return loss.
Coupler losses can be compensated numerically in the HP
8990.^

On the receiver side, the receiver protection limiter needs
to be characterized in terms of spike leakage and spike
compression. Fig. 5 displays the output of a limiier. The
time windowing feature is lised to focus on the spike
detail and markers spell out the spike leakage in dB. The
ratio of the input of the limiter to its output would show
the power compression along the pulse.

At the system level, the peak power analyzer performs
delay measurements between, for Instance, pulse drive
and transmitter output. The concurrent and time-cali-
brated display of the drive signal and the microwave
puise avoids cumbersome calibration tasks.

Analyzing the transfer characteristic of the puise modula-
tor is another example of the combined use of sensor and
video inputs. The transfer characteristic can be displayed
as a ratio of the microwave channel to the video channel
and examined for linearity.

Complex Communication Signals. The pow^erful trigger
capability of the HP 8990 A comes into play w^hen signals
like the pulse bursts of a TDMA (time division multiple
access) system are to be evaluated. For instance, trigger
holdoff stabilizes the display by Inhibiting recurrent
triggering on subsequent edges. IVigger delay allows the
user to select^ say, tJie 231st pulse of a long pulse train.
Trigger pattern lets the aser trigger on specific pulses,
like gUtches, within a train or burst. The dual time base
is useful for observing and measuring time or power from
burst to burst and simultaneously on individual pulses
within a burst (see Fig. G).

Not so obvious is the application of the peak power
analyzer to communication signals keyed in frequency or
phase. The peak power analyzer can be used here to
measure accurately the power glitches and changes that

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305 UW

173 UH

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fine

Pig. 5. Spike leakage measure-
ment at the output of a radar
receiver protector

Apiil 1 mi Hewletl-P^kard Journal 87

)Copr. 1949-1998 Hewlett-Packard Co.

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frames uf different ieveis repre-
senting maximuni, minimum, and
typical frame spec: ificati oris.

accompany phase and frequency switching. More complex calibration to account for control signal and instnimenta-

digital modulation formats, like the 16QAM signal of a
digital radio, can be examined with regard to level
transitions, overshoot, and power (ampLitude) compres-
sion. Infinite persistence is useful for recording multiple
traces (see Hg. 7).

Transient Response of Components. Transient measurements
on microwave components usually require cumbersome

tion delays. The time calibration provided in the IIP
8990 A between the sensor channels and the video input
channels and the simultaneous display of both the control
stimulus and the microwave response make this task
easy.

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88 Apili 19^2 Hewlett-P^kard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

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Fig. S- Delay time measurement

3 ~L ^SO itiV on a pin switch.

The pin switch in Fig. 8 is turned on by the falling edge
of the control signal. A single blue-key operation mea-
sures the delay between the mesial points of the falling
control signal (lower display) and the rising microw^ave
pidse at the pin switch output. The wide pretrigger range
makes it possible to view the fall tum-on region of the
transition.

Conclusioii

The apph cations Listed above give an indication of tlie
versiitility of the HP 8990 A peak power analyzer. The
integration of advanced sensor and calibration technology
wiih the trigger and signal processing power of HP's
advanced digital oscilloscopes results in an instrument
thai delivers carefree and acciu'ate measurements on
microwave pulses and dri\Tng control signals.

Acknowledgments

We would like to thank the HP Colorado Springs Di\i-
sion*s HP 54500 team for their tinie and technical support.

The enthusiastic collaboralion of Helen Muterspaugh and
her firmware tean^, and on the hardware side, Laura
VMiiteside and Yvonne Utzig, was key to the successftil
leveraging of digital oscilloscope technology and gave a
powerful initial boost to the peak power analyzer devel-
opment Acknowledgments to the production engineering
team, headed by Jay Anderson. Their efforts were critical
for the fast-paced introduction of the project Credit also
goes to Darren McCarthy who wits the driving Force in
reliability lesting, to Alien Edwards for his technical
contributions and his support as section manager, and to
Jim Jensen who led the fiiTnware effort.

Refereoees

1. D, Scherer, "Designing Sensors to Read Peak Power of Pulsed
Wavefonns," Mirm waves & RF] Fcbniaiy 1990.

2. R.A. Witte, ** Understanding Digitizing Oscilloscopes," RF Expo
Digest, 1989.

April 1992 Hewlett-Packard Journal 8 9

)Copr. 1949-1998 Hewlett-Packard Co.

GaAs Technology in Sensor and
Baseband Design

In the HP 8990A peak power analyzer design, the detector diodes for the
sensors are GaAs planar doped barrier diodes, and the switches in the
switchable-gain baseband amplifier use GaAs FETs.

by Michael C. Fischer^ Michael J. Schoessow, and Peter Tong

The hardware design of the signal patli of the IIP 8990A
peak power analyzer presented the conflicting requlre-
ments of wide bandwidth, high dynamic range, excellent
dc performance, and a controUable gain range of more
than 100 dB.

The signal path begins at the microwave detector, which
is followed by a preaiiipliner, both residing in the sensor
The delected (baseband) signal then goes to a switchable-
gain amplifier located within the analyzer The stringent
performance and reliability goals set for these circuits
were met with the help of recent advances in galliuni
arsenide technology.

GaAs Balanced Detectors

Three different sensors aie offered. They differ in their
upper frequency limits o( IB, 26.5, and 40 GHz, and
correspondingly in their RF input connectors, which are
type N, 3.5-min, and 2.4-nini respectively. All three types
use the same circuit configuration, but each is tested and
cahbrated only over its specified range.

The coaxial input connector interfaces with the circuit \ia
a small cylindrical bellows that acts as a spring to accom-
modate mechaiMcai tolerances between the input connec-
tor and the following sapphire substrate. The liellows also
carries the input dc blocking capacitor. This capacitor
sets a lower limit on the input frequency.

The coupling capacitor is pushed against the input end of
a coplanar waveguide on the substrate by pressure from
the bellows. A coplanar waveguide has the advantage of
single-layer simplicity with convenient ground paths and
also pro\iries a good match to the coaxial input line
because the field patterns are similar. The coplanar line
includes a 3-dB pad to improve the input match at some
cost in sensitivity. This pad drives the GaAs detector
diodes and a 65-ohm shunt resistor to establish a net RF
input impedance of 50 ohms for the detector circuit.

The MMIC (microwave monolithic integrated circuit) chip
containing the detector diodes is bonded in a flipH:hip
manner onto the thin-fiim sapphire substrate to connect it
to the coplanar structure. This integrated approach
extends the upper frequency limit of the sensor to 40
GHz,

Gallium arsenide planar doped barrier diodes are used in
the detector. The average saturation velocity of GaAs is

nmch greater than that of silicon, and this allow^s the
construction of diodes having the nt^cessary very small
junction capacitance with low junction series resistance,
A low junction resistance lowers the RC lime const^ant of
the junction and raises the diode cutoff frec]uer\cy. A
planar doped barrier diode is less frequency-sensitive than
a normal pn junction tiiode because of the intrinsic layer.
In a pn junction diode the equivalent capacitance of the
junction changes w^ith power level, but in the planar
doped barrier diode, junct ion capacitanc^e is tletemuneil
by the intrinsic layer, which remains almost constant as a
function of power

A specialized GaAs \C process allows custom tailoring of
the doping to control the height of the Schottky barrien
This control makes ii practical to operate the detector
diodes in the current mode for all its advtmtages (see
''Harmonic Errors and Average versus Peak Detection,"
page 94). while keeping the video resistance low enough
to maintain high sensitivity.

The detector circuit employs two diodes, tJeposited
synmietrically about the center of the coplanar line. They
are driven in a push-pull manner to effect full-wave
rectification. This scheme securer a number of advan-
tages;

* Common-mode noise or interference riding on the
ground plane is canceled at the detector output.

* Thermoelectric voltages resulting from the joining of dis-
similar metals, a serious problem below^ -30 dBm, are
canceled.

* Measurement errors caused by even-order harmonics in
the input signal are suppressed.

' A 3-dB signal-to-noise improventent is realized by having
two diodes. The output signal is doubled in voltage (qua-
drupled In power) while the noise output is doubled in
power, since the donunant noise sources (in the input
stages of the amplifiers) are uncorrelated.

Each diode is comiected in series with a small integrated
resistor at its output, foUow^ed by an RF bypass capacitor
to ground. These resistors further improve the iitput
match of the detector circuit. The in^pedance at the input
side of the diodes consists of the 65-obin resistor to
ground in parallel with the loads presented by the two
diodes. The junction resistances vary quite widely as a
function of input power level, and the series resistors are
there to reduce the effects of this variation. The choice of

90 April 1992 Hewrlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

resistance is a compromise between minimizir^g the
impedance vaiiation and reducing detector sensitivity.

The output of the detector circuit drives a transresistance
amplifier (essentially a wideband current-to-voltage
converter) wi\h a low input resistance, forcing the diodes
to operate in current mode rather than voltage mode.
This prevents peak detection and ensures thai the detec-
tor remains substantially average-responding, even at high
power levels. Average-responding power detectors are
sagnificantly more accurate than peak detectors when the
input RF carrier contains harmonics (see ""Harmonic
Errors and Average versus Peak Detection," page 94).

Diode saturation current and the thermal voltage kT/q are
both strongly temperature dependent. This shifts the
diode V-1 curv^e and affects detection efBciency. A chip
thermistor, mounted acUacent to the GaAs detector chip
on the sapphire substrate, provides temperature data. The
data is used to adjust firmware calibration coefficients
automatically^ thereby continually maintaining the analyz-
er's accuracy over temperature.

Thousands of hours of testing at maximum power and
maximum operating temperature have confirmed the
long-term stability of the detector sensitivity.

Sensor Video Amplifier

The amplifier circuit board in the sensor performs the
initial processing of the rectified signals from the detector
diodes. It also carries the EEPROM that contains the
calibration data for that particular sensor The sensor
amplifier forms the interface for the balanced output of
the detector diodes, pro\1des chopping for dc siabilit^^ at
low levels, provides wideband gain from dc to over 3O0
MHz, and drives the 5CkDhm cable to the analyzer.

The diode outputs must be loaded with a low impedance
to keep the detection in a current mode rather than allow
peak detection or voltage mode to occur. Signal-to-noise
ratio is the limiting factor for low-level detection, so the
amplifier also has to have low noise.

To provide submicro volt-level dc stability along with
hundreds of megahertz of band width, the amplifier is
constructed with separate paths, each optimized for its
respective task (see Fig, Ij, This requires that the initial
circuit in the signal path be a diplexer to split the signals
into dc/low -frequency and high-frequency paths.

Associated with the diplexer in the low-frequency path is
the chopping stage, which disconnects the detector diodes

40 GHZ

Cable

Low- Drift Diffemntist Amplifier
Usiing OperBtiojifll Amplrfia

Chop Control

Temperature Datji

Calibraiion Data

Fig. 1. Sensor amplifier design.

April 1 992 He wlett-PackaKi Journal 9 1

)Copr. 1949-1998 Hewlett-Packard Co.

from the amplifier while the aniplifier dc offset is being
sensed and corrected using a combination of hardware
and software techniques Ln tiie liost analyzer, A bipolar
jtuiction trarisistor is used as a shunt chopper. It nearly
shorts together the two opposite-polarfty signals from the
two diodes. The bipolar jiinct ion transistor ofTers an on
resisttmce of very few ohms tmd an off capacitance of
only a few tens of picofarads, both iinpoilanl for this
function. This shunt chopper is driven through a pair of
junction FETs, which pro\idc the tum-(Hi current for the
chopper, and have low leakage and offsets when the
chopper is turned off.

The most important part of the chopping is performed by
the next devices on the signal paths, a pair of junction
FKTs in series with the signals from the detector diodes.
These FETs have on resistances of only a few ohms to
preserv^e the low input resistance of the amplilien When
these FETs are turned off, the low-frequency amplifier
circuits are open-circuited, allowing their offset voltages
and any other offsets in the entire active signal process-
ing chain tx) be zeroed automatically.

After the chopper stage in the low-frequency path come
Ihe trans resistance amplifiers. Tliese are operational
amplifiers, each having a feedback resistor that converts
an incoming cunent to a corresponding output voltage. A
pair of these aniplifieiis processes the balanced signals.
These amplifiers are referenced to the diode and RF
comiector shell ground for fre<]|uencies below 10 Ilz^ and
to the ground plane on Ihe circuit board for higher
frequencies. This separation of grounds allows the man-
agernent of groimd ciurents that might otherwise superun-
pose dc errors on the signal to be measured. One typical
source of such interference is the potential difference
between the chassis of various pieces of dectronk
equipment.

The outputs of the transresi stance amplifiers are next
combined differentially in the following stage by an
operational amplifier with balanced inputs and a single-
ended output. This single-ended signal is then reconibined
with the higtt-freqiiency component of the rectified
envelope,

Tlie recombined signals are fed to the high-frequency
ampUner, a silicon bipolar junction transistor connected
with collec"tor-to-base feedback resistance to make it
function as another transresistaiK-e amplifier with iow
input resistance. This fast ampfifier nmsi also handle the
dc component of the signal To stabilize it, an operational
amplifier is connected to compare the input current with
the output voltage of the stage and diive the base to
force correspondence, witli accuracy detenTuned by ttie
dc accuracy of the operational amplifier. The feedback in
the fast amplifier stage lowers its output impedance
significantly, so a series resistance is inserted to back-ter-
minate the coaxial cable to the instrument properly.
Combined with this back tenuinalion is a shunt resis-
tance. Together, these two resistors standardize the
overall sensiti\1ty of each sensor so that it closely
matches all others.

Several adjustments allow compensation for component
tolerances to yield a very flat time-domain pulse re-
sponse.

Postsensor Gain Requirements

The sigrial vcjitage lev (I at the output of the sensor
ranges from roughly 2 fiV to 300 mV, corresponding to an
RF input range of 100 nW to 150 mW.

An input power range of 62 dB results in an output
voltage range of 104 dB. Most of this "range expansion"
occure at power levels be^ow - 1 5 dBm, where the
detector diodes operate in the sqtiare-law legion. Here a
l-dlJ input power change results in a 2-dB output voltage
chcUige. This effect substantially increases the gain
requirements of the succeeding circuits.

Baseband Board Circuitry

The \ideo processing circuitry of the IIP 8990 A requires
at least 50 mV of signal, so considerable amplification of
the sensor output is necessaiy in most cases before the
signal can be processed. The baseband amplifier provides
this amplification, along with a variable-bandwidth capa-
bility to optimize the noise perfoimance.

The baseband board also contains additional circuitry to
facilitaie gain calibration and offset correction.

Pig- 2 shows a functional block diagram of the baseband
board. Five separate low-pass amplifier blocks can be
switched in, curnulativi^ly. hs more gain is required. The
first three blocks use oJTi tie-shelf operational amplifiers,
while the last two are discrete wideband amplifiers with
dc servos to ensure low offset.

\^l^en no amplifiers are switched in, tliere is typically 12
dB of loss along the signal path because of losses in the
switches. Baseband gain can be set to six different values
from - 12 dB to +82 dB. Finer control of the overall gaitt
is provided downstream in the video processing circuitiy.

In any high-gaui amplifier chain, circuit noise is an issue
that must be addressed. In this case the noise originates
primarily in the sensor amplifier, and if unchecked^ will
saturate the video cicuitry at the liigher gain settings. The
standard method for controlling noise is bandwidth
I invitation J and that is pan, of the solution here, along
with digital processing of the \1deo signal. There are
always trade-offs, however, and in this case the trade-off
is between rise time and dynamic range. At low sensitiv-
ity settings (for example 500 [iW/div) noise is not a
problem and tlie maximum bandwidth of 150 MIIz is
available, while no noise is visible on the screen. Howev-
er, as sensitivit>^ is increased a band of noise begins to
appear about the trace, limiting the precision of the
display.

Digital signal processing allows the user to reduce the
displayed noise through the use of trace averaging for
repetitive wavefomis. This is a powerful tool but it does
have limitations. First, the waveform no longer appears in
real time because a certain nmnber of averages of the

)Copr. 1949-1998 Hewlett-Packard Co.

GaAs
Switcbes

Td VldeD
Si g nil I
^ Processing
Circuils

Fig. 2, Furniiotial blfick diagram uffhe baseband board.

same waveform must accumulate before the (unciirre-
lated) noise is canceled out. Second, the riigiiai [jrocess-
ing captures only signals appearing on the display. Noise
peaks beyond the boundaries of the display are ignored
during averaging and this can lead to an offset error in
the averaged dispUiy for cases where tlie ntnse is exces-
sive or where I lie trace conies close to the top of the
display in the presence of noise.

The iiniitaiions of tUgital trace averaging don't apply to
the i)an<l width liniitalion method of noise control. Howev-
er, there is an adverse effect on rise time that always
comes with lower bandwidth.

In the HP S990A a judicious application of both tech-
niques provides optimum performance over a wide range
of test and nieasurement apphcations.

As the baseband boaid gam is increased by switching in
more amplifier blocks, the bami width is reduced in steps
to limit noise to a moderate level whiie not sac^tificing
rise time too much. The bandwidth is set by tJie aiupUfi-
ers themselves or in some cases by swttchable filters, as
shown in Fig. 2. The use of switchable alters, plus 30 dB

of fine gain c^onirol tlownstream in the video circuits,
provides fiexibiiity in the setting of l>aseband gain and
btmdwidth. This flexibilily allows the user to select the
bamlwidth best suiting a particular application via a
Low/Auto/High switch. For example, a rise time of 5 ns is
available at r> ^W/div with the bandwidth set to High, but
the dynamic range is limited by the high noise hnel,
whicli must be reduced through averaging. The dynamic
range reduction results from the requirement that the
noise must be contained within the borders of the display
before avera0ng, as explained above. With the bandwidth
set to Law, a negligible noise level is achieved at the same
sensitivity without the use of averaging, buf at the ex-
pense of a 25-Lts rise time. Tlie (default) Auto banclwiflth
setting falls between these two cases.

A critical consideration in the design of the baseband
board was the performance of the switches used to select
the amplifiers. The performaiK^e requirements include low
on resistance^ low capacitance, small si^e, low power
dissipation (low heat generation), arid good dc accuracy.
The requirement for simultimeous low resistance and low

April 1^92 Hewlett-l^c-lcajtl Soumal 93

)Copr. 1949-1998 Hewlett-Packard Co.

Harmonic Errors and Average versus Peak Detection

Envelope detectors can be operated m a voltage mode by loading them with a high
impedance, or m a current mode by loading them with a low impedance. In the
voltage mode, at high signal leveEs, ctetectors perform peak detection, that fS, their
output response is proportionaf to the peak voltage amplitude of the input wave-
form, Historically, most microwave envelope detectors have been designed to
operate as peak -res ponding detectors, often to maximize their voltage sensitivity.

Current-mode detectors (as in the HP 84812/1 3/1 4A sensors] keep the diodes in
conduction over most of each half-cycle and this results in a detector thaj is sub-
stantia Hy average- responding, even at the highest input power levels.

Detectors that operate in the peak mode in their Jmear range suffer from the Iran-
srtion betvi/een square- law and linear response, and from the change from an
average response in the square-law region to a peak response in the linear region.
Peak-mode detectors also have much slower rise and fall times than average-
mode detectors, and the peak-responding detector incurs the full errur penalty
ffom harmonic content, en error that is only partially improved hy balanced full-
wave detectbn with differential emplificaiion.

The mode of operation {average or peai<] of a detector is established by con trof ling
the ratio of diode video resistance to video load resistance, taking into consider-
aticin the HF bypass capacitance and any other reactive components of the video

load seen by the djode.

At low input power levels (< — 10 dBm], both voltage-mode and current-mode

detectors are in their sCfua re-law region, A detector in its square -law region is
inherently average-responding. This square-law average response combines the
energy in the fundan>ental and anv harmonic components present to give a true
total average power result However, at high signal levels, a vol tag e-m ode detec-
tor responds to the instantaneous peak of the waveform, the vector sum of the
components. The f of lowing table shows the errors caused by harmonic content for
different detection methods

Worst-Case Error Caused by

-20 dBc HamioniG Content

Detector Type

Second Harm on jc

Third Harmonic

Peak'

Z1%

21%

Responding
IMost Detectors]

Peak-
Responding
with Balance

21%

Average-
Responding

Average-
Responding
with Balance

(HPB990A)

A signal having a second-harmonic conterrt of - 20 dBc can suffer a 21 % error in
a peak-mode detector, while the average-mode detector can reduce this to 3%,
even at high power levels in the linear region. Balanced average detection can
further reduce this error to 1 %.

Third-harmonic content can cause the same magnitude of en'or in a peak detector,

while average detedian gives a factor of 3 improvement. Balancing gives no im-
provement for odd hannonics.

Michael C Rscher
Development Engineer
Stanford Park Division

capacitance ruled out the use of *TFETs and the dc
accuracy requirement eliminated the possibility of diode
switching. The choice fmally was between mechai\it:al
relays and GaAs PET switches. Monolithic Ga.*^ switches
were chosen for their advantages iti size and power
consumption. Tin ere was also concern about the reliability
of mechanical relays in some ATE applications in which
the switches coiiJd see more than a million cycles in a
relatively short period of time.

The on resistance of the switches is low^ but not iiegligi-
ble^about four ohms. With tw^elve such switches in
series, tlie impedance of the signal patli could deviate
significantly from 50 oluns, depending upon the switch
settings, and this would cause gain and frequency re-
sponse errors leading to poor pulse response. The prob-
lem was prevented by placing resistors or RL networks
between ground and each switch pole to equiilize the
impedance along the signal path in a distribut^ed manner.

Two digitaUto-anaiog converters (DACs) feed into the
baseband signal path, as shown in Pig. 2. The fme DAC at
the input of the hoard can be progranmied to output
specific dc voltages or currents with ver>' high accuracy.
This DAC is used to measure the dc gain and input
impedance of the board during vertical calibration. The
coarse DAC is used primarily to acljust the dc level of the
signal path during zeroing.

The very high gain of the baseband board and subsequent
circuits makes interference from electric and magnetic
fields a msyor design consideration. This is especially true
with a switching power supply and a CRT tlisplay residing
in the same box. Mu-metal shield structures are employed
around the board and around the CRT components (see
''Multilayer Shielding Protects Microvolt Signals in lligh-hi-
terference Environment," page 84). In addition, the
printed circuit layout of the amplifier chain and the
routing of input cables are configured to keep signal loop
areas small The input cables pass Oirough common-mode
chokes that reduce ground -loop currents at the 25- kHz
CRT sweep frequency. These extreme measures ensure
that interfering signal levels at the input to the baseband
board remain below 100 nV peak to peak.

Ackn o wledgme iits

The authors would like to acknowledge the contributions
of Riiss Riley and Lee Colby for sensor development. Bill
Strasser for the initial baseband design, and Sandy Dey,
Rust>' Myers, and Marc Tognaccini in sohing the many
intricate problems of assembling, testiiig, and establishing
the calibration of these devices.

M April 1992 Hewlett-Packard Joiimal

)Copr. 1949-1998 Hewlett-Packard Co.

Automatic Calibration for Easy and
Accurate Power Measurements

Changes in input power, carrier frequency, and sensor temperature are
automatically compensated for. The user is not required to disconnect the
sensor from the device under test and connect it to a calibration source.

by David L* Barnard, Henry Black, and James A. Thalmann

The HP 8990A peak power anal^^er is designed to mea-
sure the power of pulsed signals accuralely over a wide
d>Tiainic range, A well-designed calibration sirateg^^ was
required lo achieve the specified accuracy over all of the
specified operating conditions. EIP 8990A calibration
includes both calibration of the power sensor and calibra-
tion of the analyzer.

Calibration of the Sensor

The sensitivity of the sensor is strongly influenced by the
operating conditions. Calibration of the analyzer and
sensor to compensate for changes in sensor sensitivity
over these varying conditions became a significant design
issue. There are three parameters thac affect the sensitiv-
ity of the sensor: the incident power le\'el, the carrier
frequency of the applied signal, and the operating temper-
ature of the sensor diode (see Fig. 1). These needed to
be carefully considered in the development of the calibra-
tion scheme.

Besides the accuracy requirement, other goals affected
the selection of a calibration strategy. One of these was
ease of use. We wanted to minimize the effort on the part
of the user to perform a cahbration. For example, we
didn't want to require the user to disconnect the sensor
from the device under test and connect it to a calibration
source. This would be especially objectionable if frequent
calibrations v^ere required. Another goal waa to avoid the

High Powtr

Planas o1 Constant

D elector Outfiut

Vnltage

Ffeqiiency

Fig. 1- Power sensor sensitivity is atfecXed by the incident power
level, the carrier frequency of the applied signal, and the tempera-
ture of the sensor diode. Automatic calibration of the HP 8990 A
peak power analyser compensates for changes in these parameters.

need for a lot of specialized calibration hardware that
would add significantly to the cost of the anal^-zer. We
didn't want the analyzer to perform excessi\e computa-
tion during normal tise, w^hich could make operation slow.

Sensor Characteristics

The sensitivity of the sensor diode is a nonlinear function
of the incident power. At low power levels, the diode
response has a square-law characteristic, so the voltage
appearing at the output of the sensor is proportional to
the power of the appUed signal At high power k\^els, the
response approaches linear operation. In this operating
region f the sensor^s output voltage is approximately
proportional to the signal voltage. A broad transition
region starts to appear above 10 ^W and is still evident in
the high-power region, so linear operation is never fully
achieved. For this reason, no simple mathematical model
exists to describe the voltage -versus-power transfer
function of the sensor over the specified power range.

The sensor is required to operate over a broad frequency
range, which brings into play the frequency dependent
characteristics of the diode. The dominant effect is a
roU-off of sensitivity that occurs at higher carrier frequen-
cies. This roll-off is strongly dependent on the incident
power level. In addition, there are some minor ripples in
sensitivity starting near the middle of the frequency
range. These frequency dependencies are much more
noticeable at low incident powers (see Fig. 2).

The sensitivity of the sensor shows a significant tempera-
ture dependency The sensitivity changes quickly at low
temperatures and flattens out at high temperatures. Again,
this effect is most noticeable at low incident powers (see
Fig. 3).

Calibration AJternatitves

We concluded that each sensor would have to be cali-
brated over its specified power range at a given operating
point of carrier frequency and temperature. No way was
found to model the physical processes in the sensor
diode with sufficient accuracy to reduce this requirement.
Several calibration alternatives were considered.

One solution would be to use a calibration source capa-
ble of producing accurate power levels over the power
and iTeqiieney range of the sensor. The sensor could then

April 1992 Ifewlett-Packanj Journal 95

)Copr. 1949-1998 Hewlett-Packard Co.

O 1 GHz
iS 9 GHz

10
B
§

D D n D D o D D a ag a p ^ o

-20

-10

Input Power Prnldfiin)

Fig. 2. Sensor sensitivity as u fujttilloii of powt^r for thre«?
carrier frequendes,

bt^ calibrated before use, regardless of its current uperal-
ing Leriiperature. However, such a calibration souree
wtiulcl be proliibilively expensive. Also, this approacfi
would reqirire the user to disconnect the sensor from tlie
source under test tcj perform the calibration, and the
cahbration would have to be repeated whenever the
operating temperature of the sensor changed.

A more economical solution would be to have a single-
freqiiency calibration source. As before, tlie calibration
w^ould be perronueil over the sensor's input power range,
Fi'equency calibration data rnight be stored in the sensor
to correct for the change in sensitivity over frequency.
This approach would be less accurate, since the frequen-
cy response of the sensor diofle is uot iiHlependcnt of
power and temperature. It would also suffer from the
need for manual intervention by the user

HP 8»90A Approach

The disadvantages of these calibration approaches led us
to consider a dramatic tdly different approach — character-
izing the sensor over temperature, frequency, and power,
and storing this intbmiation in the sensor for use by the
analyzer. TJiis scheme relies on the long-term stabihty of
the sensor diode technology, which was shown to be
excellent in the course of extensive reliabitity testing.

To make use of the data characterizing the sensor, the
analyzer must know the operating conditions of the
sensor. The operating powder is not a problem since the
analyzer always knows wdmt range it is set to. Since the
analyzer has no way of determining the carrier frequency,
the frequency must be specified by the user, but this
w^ould also be true for any of the previously mentioned
calibration schemes. Tlie one new item of information
reqtured by this scheme is the sensor's operating tempera-
ture.

To support this calibration scheme, the sensor is designed
with a thermistor located in close proximity to the sensor
diode. The analyzer can read the thermistor with an
analog-to-digital converter to learn the operatirtg tempera-
ture. This, along with the carrier frequency supplied by
the user, gives the analyzer sufficient information to

iitteipret the sensor data to perform a calibrated power
measurt^menb

Im piemen tat ion

To iniplenieru tire selected calibration scheme, we needed
to find m^ efficient way to represent the sensor's behav-
ion As pi'eviously mentioned, we concluded that the
sensor's nonlinear relationship of input power to output
voltage precluded the use of a simple rrtathematicai
model This led us to test each sensor over the specified
l>ower range. Since the effects of tempera t me anti fre-
quency infiiience each other and are not easily niodeled.
it became apparent that the power-to-voUagc trtuisler
function of each sensor would have to be measured at a
nmnber of different temperatures and frequencies,

A sensor test system was designed to perform the needed
measurements. It measures the sensor output voltage as a
function of powder over the specified range fif (he sensor.
The souices ai"e broadband, allowing any test frequency
in the specified range of the sensor to be used. The
sensor under test is placed In a temperature chamber so
it can be characterized over temperature.

A grid of temperatures and frequencies is constructed for
each sensor model Ptjr each temperature, power-versus-
voltage data is collected at eacli test frequency. After
correction for mismatch errors, tlie resulting test data
forms a three-dimensional matrix of power and voltage
pairs.

Processing the Sensor Test Results

The matrix of measurements delivered by the sensor test
system is too bylk>' to stoie directly in the sensor. We
decided to try processing ihe data with numerical curv^e-
tltting techniques to yield a more compact representation.
We were concerned that the representation be usable by
the analyzer without a lot of timeHi'onsuming floating-
point processing. Such processing could cause large
delays wirenever the analyzer recomputed the sensor's
response.

This niled out the use of logaritluuic or exponential
functions. Instead, we chose polynomials. To cover the
large dynamic range, we broke the power-to- voltage curve
Into four segments. For each segment, a curve Is fit to

oooo oooooo ^

^. 15

A^^AAAAAAA^^Ii^^O

25 C

nan ^

I lOl D O ODD pO^
-3°C

~3Q

-2D

-n

Irrput Power Pji^ {dBm|

Fig. 3, Sensor sensitivity as a function of power for three tempera-
tures.

9e April 19fl2 Hewlett-Pacl(2ffd Journal

)Copr. 1949-1998 Hewlett-Packard Co.

the daia by the least squares method with the added
constrain! of making the endpoints mat rh rhe ac^acent
segments. Tlie rx^sulting polynomial coefficients are much
more compact than the original data, making storage in
the sensor's intcnial EBPROM practical. Also, polynomials
can be efficiently calculated in the analj^er

Analyzer CalcuJattotiB

The analyzer reads the coeRicients and associated data
from the sensor's EEPEOM ai iK)wer-up or when the
sensor is plugged in. The analyser then uses the coeffi-
cdents to calculate tJie polynomials, which give power as
a function of sensor output voltage. Each set of coeffi-
cients, and therefore each polynomial, applies at a single
point in a two-dimensional grid of temperature and
frequency. Thus, the power at a given operating poini is
calculated by inien>f>lating between the powei^s at the
nearest test frequencies and temperatures. This interpola-
tion is implemented by a spline surface-fitting algorithm^
and is included as pait of the overall voltage-to-power
function.

The voltage-to-power function is applied in two ways. The
first step is calculating the amount of internal gain that
the analyzer must insert to anipiify the detected voltage
to match the selected full-scale power sensitivity. This
requires the inverse function, power to voltage, w^hich is
calculated from the original function by a version of
Newton s method,^ Once the gain is set, we are assured
that applying tlie power corresi>onding to the top of the
screen to the sensor will result in the an^pliHed output
voltage corresponding to Hie top quantization level of the
analog-to-digital converter (ADC). Independently, the
offset leveling, which is automatically performed, ensures
that the lowest ADC' reading coiTesponds to zero power.

The fmal step is to calibrate the rest of the ADC levels. A
table maintained inside the analyzer translates the ADC
levels to calibrated (>ower. The voltage-to-power function
is used to calculate the values in this tabic.

This process must be repeated whenever a new analyzer
sensitivity is selected, when a new carrier frequency is
entered^ when the sensor temperature changes, or when a
new sensor is plugged m.

The analyzer continually monitors the sensor thermistor
to check for t.empcTatiu-e changes. If the temperature
deviates more than a certjiin muount, the calibration
procedure is automatically performed- This relieves the
user from the worry of manually recalibrating the analyz-
er when the sensor's operating environment changes.

Calibration of the Analyzer

The calibration of the analyzer is c:omplicaled by a
number of constraints. These include circuit i\ on lineari-
ties, the large dynamic range, iind the nature of the signal
in the UP 8990 A, A systems design approach was re-
quired, including both hardware and software design,

OfTset Voltage

Even igtKJring tlie effects of the GaAs switches in the HP
S99QA signal path, offset voltage is a design issue, since
the amplifiers iii the sensor produce an offset, that de-
pends upon ambient temperature and other factors and so

tends to drift slowly in operation. The HP 84810 Series
sensors incorporate a "chop" line, which commands the
sensor circuitrv^ to simulate a con<lition of no inciderit RF
power. This permits offset leveling without operator
intenention. The offset is periodically reieveled to pre-
sent any drift out of tJie specified accuracy' over time. It
doesn't matter where in the signal jyrocessing path the
offset variation originates; a single swift automatic level-
ing effectively compensates for the offset,

Channel Resistance

The channel resistance of the GaAs switches is knowTi to
vdny with operating temperature, so it is important to be
able to con\pensate for the effects of channel resistance
variation during analyzer self-calibration. One reason
channel resistance effects are so inn>ortant Ls that they
affect the imped at ice n\atch bet wee u amplifier stages and
so influence the overall gain of the analyzcT. Consequent-
ly, the voltage gain is measured during self-calibnition.

Another effect of channel resistance variation is that it
du-ecOy affects the (nominally 50-ohm) input resistance of
the IIP 8990 A The sensors are calibrated in terms of
their output to a load of exactly BO ohms. During self-cal-
ibration the HP S990A measures its own mput resistai^ce
to determine the match betw^een the sensor and the
analyzer

Offset DAC Circuits

In a sense, (he HP 8990 A self-calibration subsystems are
built around the precision One-DAC circuit t which is
constructed of highly stable precision components. The
circuit can operate as either a low-impedance source
(voltage mode) or a precise mediimi-impedancc source.
The IIP 8990A also has a coarse DAC, which is not a
precision t)AC. The coarse DAC ipjects into the signal
path downstream of some amplification (jr atteniuition
from the pomt of ipjection of the precision fme DAC (see
Fig. 4).

Automatic Offset Leveling

To level the offset in the general case, the analyscer is
fiist set up as follows. With the sensor chop line '^pulled"
aittl the j>recision line DAC set to its starting position in
niedium-hnpedance mode, the slick t)At'j which pro\icles
the reference voltage to tiic flash ADC (see Fig. 4), and
tlie coarse offset DAC are set to midrange. Then the fijish
ADC is used to take many data samples. Typic^illy the
ADC output is at its upper or lower limit at this time
since the coarse DAC is pro hah ly in the wrong position.
A conventional binar>^ chop search is made for the coarse
DAC settmg that will bring tlie signal level within the
range of the ADC. Tlien^ because the fine DAC is ex-
tremely linear, an extrapolation can be done ttsing two
pairs of fine DAC settings and ADC readings to calculate
tlie fine DAC setting that Just gives an ADC reading of
zero. This completes offset leveling for tlxe simple case.

The coarse DAC has a relatively long settling time, so
when offsel leveling is perfomiedi cart^ is taken to avoid
changing the ct>arse DAC setting unless absohitely neces-
sary. Since different vertical ranges typically require
different coarse DAC settings, changing the range can
result in a delay because of the biiuuy search needed lo

April 1992 Hewlett-t^ kard ,ki\ i rnal 97

)Copr. 1949-1998 Hewlett-Packard Co.

Baseband Boflnl

First
Post^mp lifter

Second
PostampliFiei

Fig* 4* Analog model of the HP 8 9 90 A used in calibration-
find the new coarse DAC setting. To avoid this delay,
once offset leveling is performed in a particular vertical
range, the coarse DAC setting for that range is stored.
When that range is revisited, which might happen after
the user makes a series of range changes, the stored
coarse DAC setting is used. This eliminates the need for
the tinie-consuniing binary search except w^hen the offset
voltages have changed significantly.

A manual zero feature analogous to that of Hewlett-Pack-
ard average powder meters is provided- This feature can
be time-consuming to use but is available for best accura-
cy w^hen the signal is below^ —30 dBm. It is capable of
correcting for offsets that precede the chop switch*

Vertical Calibration

Essentially, vertical calibration of the HP 8990A answers
the question: How^ much signal from the sensor corre-
sponds to fiiU scale at the ADC?

Within its operating range, the sensitivity of the HP 8990A

is, for practical purposes, continuously ac^ustabie. Thus

the purpose of vertical calibration is to provide data so

the vertical setup subsystem can select the analj-zer

hardware settings that will provide the desired sensitivity.

The vertical calibration data includes:

Vertical sensitivity expressed in ADC counts per volt.

Input resistance expressed in ohms.

Compensation coefficients for correcting analyzer nonlin-

earity.

This data is repeated for each combination of v^ertical
amplifier settings.

The actual measurement of vertical sensitivity^ is relatively
simple: the precision fme DAC is placed in its low imped-
ance mode (also known as voltage-source mode) and its
count is changed. The ratio of the change in the fine-DAC
count to the corresponding change in the ADC count,
together with the absolute sensitivity value k of the
precision fme DAC, provides the needed value:

Sensitivity

^ A(fme DAC)
ACADC)

Mathematical techniques such as linear regression and
drift modeling are used to minimize execution time and
maximize accuracy.

Input resistance can be measured with or without a
sensor attached. The input resistance calibration is
performed using the precision fine DAC as a stimulus. If
a sensor is connected to the input of the analyzer, the
sensor output impedance forms a load in parallel with the

HP 8990 A

input
Resistance

Fig. 5. Input resistance calibration equivalent circuit.

Sensor

Output

Resistance

98 April 1992^ Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

Testing the Peak Power Analyzer Firmware

The fsfjr^ware quality assiirance plan for the HP 8S0A Umvme had !he foiiowing

• Extewiv?^ ?tst elf HP 89904 functtcwTaiity to meet nhinmrnt cmsria

• Oe Tomatedie^" -rifrcationof

tte," ;3ns3ridpos' ;>es

• Leverage as many tesi loots as possible.

An jnternafiv deveioped toot called the HP-IB Interactive Test System (HITSI was
leve^apd frmn previous projects and used for automated testing. The program
^^s moditfed to add various new features and commands to test H? 8990A tunc-
tiorrality, HrrS is a ^^1C pcc^ram that runs in the RMB4JX environment on HP
9000 Series 30Q workstations tt takes fn HITS mpyt test files and creates corrB'
spondrng Signature files The HP-UX m utihty \$ used to compare the output sig-
nature files against verified reference files Any discrepancies point to a change
With the new firmware revision which should be mvestigated as a potential proij-
lem

The HITS test files contain a sertes of commands, usually or^e per line The com-
mand format is as follows:

CCXXXX,..XYYyYYY,.Y

The CC field contarns a two-character command that specffies how to interpret the
other two fields. For example:

CQCHANNELliRANGElOmw

The CQ tells HITS to send the command Chaniv£li:Ran3£ lOmw and then send
the query CHAf^NELT RANGE? The command, query, response, any error mes-
sages, and status information are logged to the signature file.

HITS provides the folfowmg capabiltties:

» Send a command

" Send a query and get a response

■ Send a command followed by a query

■ Perform a measuremenT and limit-check the result

• Perform random key testing for a specified number of key presses

■ Randomly set parameters in a specified range a specified number of times

• Perform a series of tests in sequentjai order

■ Repeat a series of tests in random order a specified rromber of times
•Test IEEE 48B.2 functionality

• Test dtgiti^ation functional ity of the HP B990A

• Test autoscale functionality of the HP 899DA

• Interact with the OUT to facilitate development of test cases and other functions
i Log commands and queries to a file (no responses, errors, or status messages are

logged},

All the commands and the resulting queries, responses, error messages, and sta-
tus infornriation are logged to signature hies,

The HP B990A is a fairly compter analyzer with over two hundred and fifty func-
tions- To test this large set of features, both subsystem and scenario- based testing
were used. As a first step, subsystem tests were written to verify the basic func-
tional itv of each subsystem Then scenario tests were written to test various
measurement scenarios and the interactions end couplings between the various
functions About 60% of the automated test development time was spent generat-
ing the scenario tests

Time was also devoted to manual testing of front panel operation, the display
subsystem. calibratJEK^ scenarios, interaction wrlh different contra Her platforms,
ar^a^r options, and features that cannot be tested m an automated fashi^ Jn
addttien. all code was run through the C program ct^ec*^^^ vPTfi^' --y^! ■ and the
C syniBx cirecicer tool insiieci *

In addition to HITS, a second BASIC program called IKTEBP was used for oomial
inTeraction with the analyzer and for testing new functionality The If^TERP pro-
gram was written by ttie projects HP-18 engineer as a development tool This
program takes an HP4B command, sends it to the analyier and automatically
reads the responses to queries, tt prints mor messages and status information,
and provides svppQrt for readtng and sending block data and for recalling previous
commands. The program can also read commands from a file. This feature was
used to recreate problems, with inptit provided by the file created by the HITS log
feature.

The automated tests pn:ved to be very useful After changes to the firmware a
successful test run helped us verify that a bug fix had not introduced any new
problems. When bugs were found that were not detected by the automated tests.
the tests were updated to check for those specific problems. This improved the
coverage of the automated tests. The automated tests were also run to verify that
hardware changes had not had any unexpected impact on firmware functionality

The firmware shipment goal for the HP 8390A peak power analyzer was to reach a
defect rate of <0.05 defects/fiour of test time. To stop testing, the defect rate had
to exhibit a trend of <0,05 defects/hour and the product had to go through a period
of 40 hours of test time without discovering any defects.

During the final phase of quality assurance testing an automated/manual test

cycle was used. Once the firmware passed the automated tests the product was
released to a group of marketing and P&D engineers This group performed ap-
plicatjon-specihc and function -specific testing for a period of 24 hours. Any de-
fects found were fixed and the cycle was repeated until the shipment criteria were
met.

The HP B99DA has a total of 99,351 lines of noncomment source statements

{NCSS). Since this was a leveraged product, a better metric is the number of lines
of code that were modified or added. Approximately 40.0D0 NCSS were addtju u^
modified During the product development cycle. 355 defects were togged. This
gives a defect rate of 0.86 defects per thousand lines of code

The testing process worked well in helping the HP 8990 A firmware team meet all

of Its quality assurance objectives

Acknowledgments

I would like 10 EhanK Tatsuo Yano and Mark Johnston for their help with HITS. Jim
Thalmann for writing IhTfERP, and the Colorado Springs Division's HP 545DG team
for their help in resolving venous defects.

JayeshK Shah

Development Engineer
Stanford Park Division

* insfifict IS a trademark of ATgiT

analyzer input resistance (see F!g. §). In essence the

resistance calibration consists of finding two prt^ision
fine-DAC stimuli, one in low-iinpcdancc mode and one in
medium -impedance mode, that produce tfie same effects
at the ADC converter. The Thevenin equivalenl source
reststimce of the sensor is a%^ailabie from the sensor*s
awn EEPKOM coenici<*nts. The sensor's parallel conduc-
tance is corrected for mathematically.

The compensation coefficients correct for small changes
in analysjer sensitivity that occur if iht* caliliration hard-
ware setup is not the same as the meiisurement hiu-dware
setup. One such coefficient corrects the Input resistance
for llie differeore in voltage gain betwtnn^ calibration and
measurement. Another coefficient accounts ft>r the effects
of offset voltiige feedback. The error component is only a
small pari of the gain, so a ver>^ simple model of it is
good enough.

April 1 992 Hewl etl-Packard Journal 99

)Copr. 1949-1998 Hewlett-Packard Co.

Vertieai Setup

To see how the vai-ions calibration factors interact, it is
illustrative to look at what fiappens when a new vertical
sensitivity is selected. In part the process involves making
some apparently arbitrary- decisions at the otitset to set
an overaJ] gain or sensitivity. The process then converges
to a solution . It begins when the user selects a desired
sensilivity in nncrow^ave power level per screen division.
This detenmines the full-scale power level. From this
level, the sensor data, the teniperature, aitd the carrier
frequency, a full-scale Thevenin equivalent circuit of the
source (openHTircuit voltage and source resistance) can be
determined. Making an approximation for analyi^er input
resistance, the full-scale power level is converted to an
input voltage at the analyzer front panel and the amount
of baseband board aniphfi cation required to produce a
roughly correct signal level at the flash ADC- converter is
selected. Recall that the baseband board anipliQ cation is
available in steps of approximately 20 dB, Once the
baseband board amplifiers and appropriate low-pass filters
arc selected, the intntt resistance and the full-scale input
voltage can be determined accurately. Since the full-scale
input vohage is knowUt the lookup table (which expresses

the nonlinear relationship between power and voltage)
can be constructed. The postamplifier settings can also be
selecti^d. Having converged this far^ the setup is within
about ± I dB of the desired sensitivity, After a fmal
iteration of the calculation, ti^e linal value of the stick
DAC setting is deduced so as to arrive at precisely the
desired sensitivity. The stick DAC: provides the reference
voltage to the flash ADC^ converter and is the rirml
adjusttnei\t of sensitivity. Offset leveling is theit all that
remains to be done to complete Ihe veitieal setup of the
analyzer.

Acknowledgments

Tom Menten developed and refined the curve-fitting
algorithm that is used to process the sensor data. Sandy
Dcy provided production support of the sensor etdibration
process. Kari Santos helped develop the vertictd calibra-
tion firmw^are.

References

1. CI Dalik|iiist and A. H^orK NimiericQ'i Methods, Prentice-Hall,
1974, p. VM.

2. ibid, p. 5,

1 00 April 1992 Hewlen-Paclcard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

An Advanced 5-Hz-to-500-MHz
Network Analyzer with High Speed,
Accuracy, and Dynamic Range

A thfee-processor design provides a measurement speed of 400
microseconds per point, fast enough to keep up with manual adjustments.
Maximum frequency resolution is 0.001 Hz. Dynamic accuracy is ± 0.05
dB in amplitude and ±0.3 degree in phase. Sensitivity of the three
receiver channels is - 130 dBm, and dynamic range rs llOdBor 130dB,
depending on the sweep mode.

by Koichi Yanagawa

Higher productivity with lower cost is an etenial theme in
all industries, not only in production but also in ihe
laboraJory. Several of the design objectives for the IIP
8751 A network analyzer were based on tMs obser%^ation.
For example, a faster network analyzer directly increases
productivity. In production, it increases throughput by
reducing test time. If the line has a tuning process, such
as for LC fillers, then a network analyzer fast enough to
give a real-time response improves linitng efficienry.
Powerful analysis capabilities built into a network analj'z-
er improve the efficiency of component evaluation,
thereby contributing to reduced development cycles in
laboratories imd reduced lest time in production.

Customer re<pirenients for network analyzer functions
and performance are becoming more varied and demand-
ing because these customeii^ have an incrt^asing need for
component evaluation and testing to ensure higher quality
for their own products. For example, a c^uslomcr might
want to measure the passband characteristics of high-Q
quartz crystal or ceramic rdters with less than 0, 1-dB
resolution and relatively coarse frequency resolulion, the
st.op-bfmd spurious below - 100 dB with very fine fre-
quency resolution, and the oven one characteristics of
these devices, all in the same sweep measurement on the
same screc?n. Just as the filter or resonator characteristics
to be evaluated aie many and complex ^ powerful analysis
capabilities for ripple, insertion loss, Q, bandwidth, center
fre<tuericyt resonant frequency, and so on are desired as
bulh-in fun tn ions of a network analyzer

HP network analyzer customers also want a common user
interface with earlier HP i>roduris for reasons of familiari-
ly, ease of use, and a ciuick iuiroductian to their working
environments. The user interface includes the soft key
operation, the HP-IB control ((jmmajids. and the program-
ming language.

New Network Analyzer

The HP 8751 A network analyzer (Fig.l) provides solutions
for these customer requirements. The HP 8751 A is de-
signed to improve the tesLing of filters and resonators for

telecommunications and commercial products^ and to
simplify- the design and evaluation of circuits, function
blocks, and discrete complex devices in the development
laboratorv^ It inherits the look ajid feel of HP 8752/3
analyzers, making it easy to become familiar with and
introduce into a production line. Among its new features
are;

* Simulation of impedance matching networks for a device
imder test

» A ILst sweep mode for measuring at various aser-defined
frequency points, power levels, and IF band widths

* An order base display mode useful with list sweep for
making simultaneous high-speed and high-accuracy mea-
surements in separate frequency ranges

» Simultant^ous display of gain, return loss, group
delay— the three key parameters for filter applications.

In addition to these functions, the HP 8751 A offers
inea^suremcnt iH^rformance as high as existing HP prod-
iu1s (jr higher. Its frequency range is 5 Hz to 5()0 MHz. It
lias three tuned receiver charmels with - ItiO-tlBni sensi-
tivity and a maximum frequency resoluf ion of (KtlOl Hz,
Sint^e dynamic accuracy is one of the most important
parameters for network antdyzers, the receiver section is
designed for typical (tynamic accuracy several times
better ttvan the specifications of 0.05 dB and 0.3 degree.
Typical dynamic accuracy has been meastu-ed as less than
0.01 dB and 0.1 degree as described in "^Dynamic Accura-
cy** later in this arficle.

The HP 8751A has a maximum sweep rate of 80 milUsec-
onds for 200 points with a 4-kHz IF bandmdth. This is
fast eni>ugh to give a near-real -time response. In a tuning
prfHTCss, production personnel can see the measured
characteristics varying as fast as they make adjustments,

A 130-(iB d>iiamic range wiih list sweep (!10 dB for
oihvr sweep modes) gives higtily accurate spurious
measurements of high-Q ciystal filters. The wide dynamic
range makes lower-level spurious detection possible. With
the order base display capability, the measureuR^nts can
be indicated in a natural form on the CRT screen.

April 1992 Hewlc^tt-Packartl Journal 101

)Copr. 1949-1998 Hewlett-Packard Co.

I i I I i I k i- h h k t ^

* ft I I » > I r r IV V ir
_t f r t t t I t I t t »

N • n 'I

1 I I h 1 I

Fig. l.TlK'HPSTrjlAS-Hz-
lo-SOO-MHz network anaiy^er with
theHP8?5UA100^kHz^
lo-500-MHz s-parameter test set
and a keyboard for the optional
HP Instrument BASIC . Designed
for both t.he produclion line and
the laborat.oiyj it offers a maxi-
mum measurement speed of 400
lis/poini, list sweep, conjugate
matching capability, and many
dedicated functions for resonator
and filter manufacturers.

The HP 875IA's 25-dB to 35-flB power sweep range is
useful for evaluating the gain tonipression of amplifiers
or measttring the drive-level dependency of resonators. No
mechanical relays are used, so reliable and faster power
sweep measurements can be made with no discontinuity
of the applied sigrml. C(jntinuity of this signal is important
for smooth measurements on devices with drive-level
dependency such as ciystal resonators.

A built-in coi\iuga1e matching capability pro\ides circuit
designers with a poweii'ul design tool that makes imped-
aitce matching problems easy tt:> solve. This capability is
aiso useful for simulating the effects of inserted LC
elements, Aii example is the simulation of the effects of
load capacitance in resonator measurements.

Many built-in functions, such as ripple and bai^dwidth
analysis for filter appii cations or resonant parameter
analysis for resonator applications, provide high-speed
analysis capability.

A btiilt^n ;l'';!-anch flexible disk drive is standard. MS-
DOS'-' fonnai is supported for easy data transfer hetw^een
the IIP 8751 A and personal computers. Users can manipu-
late measured data using available PC software, such as
LOTUS^^ 1-2-3^3

The HP Instrument BASIC option provides control of
measurement sequences, data manipulation, attd external
devices, making it possible to build a low -cos! system
without an external computer I/O capabilities include the
HP-IB (IEEE 488, lEC 625), the HP-HIL for an external
keyboard, anci a ger^eral I/O port that pro\ides four bits
for m]iut and eigiit bits for output and is used to control
external apparatus such as sequencers, handlers, or
searmers*

* MS-DOS ts a U.S registered tredecnark of Microsoft Co rporati an.

'totus and 1-2-3 are U.S. registered iFademarics of Lntus Dijyelopm&nt CorpUfatinn,

Measurement Examples

The main applieatiotvs for the HP 8751 A are testing ajid
evaluation of components and circuits such as filtei's and
amplifiers. Fig. 2 shows a three-trace display for a crystal
filter obtained in a single swept measurement. Fig. 3
shows wideband and naiTow band characteristics of a
cry^stal filter on the same screen using list sweep. Stop-
band rejection at lower fi'equencies is greater than 130
ilB. Pig. 4 shows another application f>f list sweep. The
fundamental and overtone responses are measured in one
sweep and displayed on the same screen using the order
base display mode. Fig. 5 show^s the coryugate matching
capability used in an LC filter application. The siinple
simulation capability of coryugate matching can be used,
for example, to simulate the load capacitance of a reso-
nator

System Overview

The m^or .sections of the HP 8751 A are the signal
source, the receiver, the digital control section, and the
power supply.

In the analog sections, many of the 3800 electrical com-
ponents are mounted on 2-layer or 4-iayer boards of 3500
cm- area using suiface mount technology to save board
area. Through-hole components are also moimted on
these boards. Fig. 6 shows a typical analog board, the RF
and local oscillator (LO) board.

Most of the filters on the printed circuit boards w^ere
designed using the IIP Microwave Design System (HP
85L50B).

In the digital control section, about 600 electrical compo-
nents are momited on 4- layer or 6-iayer boards of about
1600 citi^ area using standard through-hole technology
and leaded components. Both sides of the digital boards

102 Aph\ 1992 Hewlett-Packard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

CHI SSI
CH2 S 1 1

a e 1 a V
Ipg MAG

lO us/ REF
2 dB/ REF

B2.i415 us

-11. 309 dB

Hid

CENTER S9 . 99S MHz

SPAM 50 kHz

fig, 2, Simulianeom measure-
ment of gain, reiiint loss, arid
group delay makes fiiter evalua-
Lion easier and faster, Here the
heavier solid line shows tht' gain
<jf a filter, the thinner solid line
shows its return loss, and the
dashed iiiie shows its group delay
charactenstic-

are covered by the llxed-potential planes, that b, the
ground plane and the +5V plane, to inhumize electromag-
neiic Lnierference from the printed circuit traces.

As a member of the HP B752/3 family, the HP 8751A has
the same footprint as its predecessors, bpt is 1.75 inches
taller to accommodate the flexible disk drive.

GHl SSI
CH9 SSI

las MAe
lag MAG

IS dB/ REF O dB

10 dB/ ^HEF

1: —1*10 . 3^ da

l: -3 . 7B04 dB

Hid

CHi START 1 MH5£

Cna CENTER B9.995 MHz

STOP 200 MHX

SPAN sgo kHz

Fig. 3. hi the Hst sweep mode,
the user can set the power level
and IF bandwidth for each fre-
quency list sweep segment. Dy-
namic ran^e is 130 dB. ShowTi
here is the niagnltude of i he gain
characteristic of a 70-MHz crj^stal
fiiten The solid line shows the Ust
sweep with the frequency range
of I MHz to 200 MHz divided into
three segments; 1 MHk lo WM
MB;:, m.92 UHz to 70.07 MUz,
and 701)7 MHz to 200 MH^. The
!iaJ:ihed line .shows a nonnaJ tinear
sweep with 69.995- MHz (tenter
frequency and 500- kHz span.

Aprtl 1992 Hefwiett'Packard Journal 103

)Copr. 1949-1998 Hewlett-Packard Co.

CHI Z: R

CHS Z: R

Cpr

lag MAG
phase

lO dB/ HEF

£2.5 ""Z REF

SO dB

o "

31 . aa u

Hid

. 099 ^

^63 a^6 MNr

_/"

''^\

[

.371 A

33^ 3e"^S.,5^Hz

\ /

\
\

-1

V Jlj

V__

START ag ,365 MHz

STOP 100. O07 MH^

Fig. 4. Qvf*rr.orie cimmcteri sties

car !)[■■ i-vTtJij.atod iirone sweep on
^ .siai^li' M'nH'ii LLsing list sweep.
Ht^re the leiL side shows Ihe fun-
danit'iiLal charaLeristics [niagiij-
tiide and phase) ai^l tlie right side
shows the fifth overtone chamc-
tPTOtics of an AT-cut crystal reso-
nator.

The signal stuirce section consists of three oscillators. MHz. I'he variabie osciDator gent^rates a variable frequen-

The RF osc:illat.or getierates a tlxed rrequency [rjt = a5(J ry f^y + j;, where fr is the measurement frequency at the

or 848.484848484 lVIH:fi. The local oscillator (LO) generates front-panel RF OUT connector and varies from 5 Hz to 500

a fixed LO frequency Ui) = ^rf - hvh where Tifi = L5d75 MHz,

CHI Sll

CHE Bl 1

Hid

log MAG

5 dB/ REF O dB

5 dB/ HEF O dB

l: -IB , B31 dS

l: "S6 . 936 dB

Cn j

Hid

1
'^

B , 1S7

5 MHz

us: 3

1 . 5B±

nH C

p: 1 .

76 (

START 1 MHz

STOP ISO MHz

Fig. 5. The conjugate matehtnj?
capahUity shows that the return
toss characteristics can be im-
proved by adding a 32 -nH induc-
tor and a 1 .3-pP capacltnr.

1 04 April 1 992 I [p wIelt-Packard JoiimaJ

)Copr. 1949-1998 Hewlett-Packard Co.

I«fvf«f«vi«viwpipvwpn««»»fvvm«v^g

Fig. 6. Mosi of the analog boards contain both through-hole m\6
suiface mnujit (!evires. Tln^ tract* iniluttors Tor filters wer^ de-
signed using file U? Microwave Desjjin Sy.stem.

The HP 8751 A contains thrt^e identical rec Diver sections
for the R, A, aiui B input ports of a conventional network
analyzer The signal from eacti input port is convertett to
the first intemietiiate frequency fjpi by a double balanced
mixer* This signal is amplified and fiUered and then
converted to the second liitemiediate fraqneney fip-2,
which is 5 kHz. Tlte f|pj signal is processed hy the
ranging and nUering circuits and then converted into
digital fonu by an analog- to-digital converter (ADC),

The digital control section consists of the master CPU
and the analog control circuits. The master CPC is a
12.5-MHz MC68HC:tKK) microprocessor with a 25-MIiz
MC68882 coprocessor. It controls the HP-IB, the display.
the keyixiard, the flexible disc drive, the test set. and the
I/O port at the rear panel The analog control section also
has a 12.5-MHz MC68HC01M} CPU and controls the analog
section through bus lines to tlie analog boardn. This
configuration was determined by trading off cost and
measurement speed.

Signal Source

Fig. 7 shows a block diagram of the signal source. It
contains five phase-locked loops.

The RF loop generates the fixed frequency called Trp.
Normally 850 Miix is selected as fRp-, but in 37 special
frequency regions, 84S.484M8484 MHz is selected to avoid
residual responses caused by spurious signals generated
at the LO mixer. However, this frequency change is
canceled if the IF bandwidth is 4 kHz because an in-
creased noise level hides the spurious responses. The f^p
frequency change is made by changing the division
number of the reference divider, w^hich divides its 50-MHz
iEiput by 32 or 33 to output 1.5625 MHz or 1.515151515
MHz, respectively. The f^p signal is phase locked to this
reference frequenqy and to another 25-MHz reference.

The LO frequency fuj is divided by two and phase locked
to rRF/2 and to half of the first intermediate freiiuency
twi to generate fRp ~ fiFi- Th*^ first IF of 1.5675 MHz is

HFloofi

SOMHi O

SMtl2 O-H^

100 kHz O-

BflkH; O-

Fig. 7. Blork dia^raiTj of thi^ sij^rtal source section of tlii^ HP 875] A network analyz<!r. Fast settling? and low spurious outputs w(tp the key
per fo m lanc e gtuil5 .

^rit 1 992 UewtHt-Packartl Juunial 1 05

)Copr. 1949-1998 Hewlett-Packard Co.

= 15675 MUX

Second IF
^5 kHz

5.25 MHz

generated by dividing 25.08 MHz by 16. The 25.08^MHz
signal IS created in another phase-locked loop.

The variable frequency t\ from f^p + 5 Hz up to Thk ^ 500
MHz is generated by the step phase-locked loop and the
fraclionai-N phase-locked loop. The output frequency of
the fractional-N phase-locked loop varies from 56 MHz to
69 MHz depending on the frequency f^. This signal is
divided by 20 and summed in a mixer vi^ith 25 MHz to
generate a signal from 27.8 MHz to 28.46 MHz- This
frequency divided by 16 is Ihe reference input to the step
phajse-lockcd loop. The output frequency of the step
phase-locked loop varies from 850 MHz to 1350 MHz as
the division number f4M, where M is an integer) is
incremented. Each step is orte Iburth of the reference
frequency, so as the reference frequency from the frac-
tional-N phase- locl<ed loop varies, the output frequency of
the step phase-locked loop varies with 1-niIIz resolution.
In other words, the output frequency of the fractional -N
phase-locked loop varies with enough resolution to give
1-inHz resolution at the output port of the HP 8751A.

The output signals of the RF phase4ocked loop and the
step phase-locked loop are the mputs to the RF mixer
The RF mixer output, after being amplified by the RF
amplirierj is the measuring signal of frequency fr- The
outputs of the LO phase-locked loop and the step phase-
locked loop fire the inputs to the LO mLxer. Tlie output of
the LO mixer is spht into three branches, one for each
receiver, and is amplified and leveled to generate the
local oscillator signals for the first mixers of the receiv-
ers. Since the residual responses of a network aitaiyzer
are caused by the spurious signals appearing on the LO
signal, the isolation betw^een the RP' signal path and the
LO signal path is a key design parameter The reason for
using fLc/2 and f7ip/2 instead of fu) and f^p in phase
locking these two frequencies is to isolate these signals
and to reduce ttie cost of mixing. Buffer amplifiers at the
outputs of phase-locked loops and at the input ports of
mixers are also important for isolation.

The voltage-controlled attenuator at the RF Input port of
the RF mixer has a 35-dB attenuation range. This perfor-
mance is essential for the powder sw^eep and list sweep
modes. A cai>acitive divider coidiguration is used for
attenuator stability

Combined with the O-dB-io-30-dB fixed attenuators, which
are switchable in 10-dB steps, the 35-dB voltage-con-
trolled attenuator giv^es an output power level range of
-50 dBm to +i5dBm. With a 0-dB fixed attenuator setting,
the output powder range is -20 dBm to +15 dBm. With a
10-dB fixed attenuator range, it is -30 dBm to +5 dBm,
mid so on.

Ta Digital
S set ton

Fi«. 8. HP 8751 A receiver section.
Tlie dynamic accuracy depends

mainly on this section.

The maximum power sweep range varies from 25 dB to
35 dB, depending on the stop pow-er setting. If the stop
power is set to +6.0 dBm, the fixed attenuator is set to
10 dB and the maximum power sw^eep range is -30 dBm
to +5 dBm, or 35 dB. If the stop power is set to +5.1
dBm, the fixed attenuator is automatically set to dB,
and the maximum power sweep range is -20 dBm to +5.1
dBm, or 25.1 dB.

At the output of the RF mixer are two active-L circuits
for absorbing dc offset of the mixer otitput, which occurs
w^hen a coarse frequency change is made. 'IV o inductors
can be switched in^ depending on the frequency settings.

The RF amplifier at the fmal stage of the RF path pro^
vides +15-dBm output power A level detector feeds back
the output level to the voltage-controlled attenuator to
level the output powder at frequencies of 501 kHiS and
above. (Below 501 kHz, the frequency response of the
output amplifier is very flat, so for faster settling, the
output power is unleveled.) The LO amplifiers at the fmal
stage of the LO path are for splitting the local oscillator
signal to the first mixers of the three receivers and for
isolating the receivers.

Receiver

Fig. 8 shows a block diagram of a receiver section. The
receiver is a double-conv^ersion type. The received signal
at the input port is introduced to the first mixer through
an input att^enuator and a buffer amplifier and is con-
verted to the first IF The attenuation of the input attenu-
ator is either 20 dB or dB; ii is selected by the user to
set the maximum input level to dBm or -20 dBm,
respectively. The first mixer is a commercially available
double balanced diode mixer Its input level affects the
upper-range dynamic accuracy of the analyzer. The first
IF output from the first mixer is amplified and filtered to
reject the unw^ anted upper sideband and is introduced
into the second mixer. The second mixer, a monolithic
analog switch, converts the first IF signal to the second
IF The second IF of 5 kHz was selected as a trade-off
among measurement speed, the conversion rate of the
following ADC, the simplicity of the ranging amplifier, and
the ease of generation of the second LO signal. The
ranging ampiifier amplifies Oie second IF by L 8, or 64
depending on the signal level. Because the amplifier's
linearity and ranging stability affect the midrange dynamic
accuracy, much care was taken in the design of die
amplifier to optimize the signal levels and phase changes
at the range switching points. The conversion rate of the
ADC is 50 microseconds per point; thus, four data sam-
ples equally spaced in time are obtained in one cycle of

106 April 1992 Hewlett-Paekai^ Joumai

)Copr. 1949-1998 Hewlett-Packard Co.

s n A B
# • II #

HP3456A
OVM

Birffef Amplifier

RatioTra(»sfi»nner

Fig, &. Test configuration for step 1 of the d^Tianiic accumcj* mea-
surf^HK'iit. Mid range performance was measured using a raUo
ifansfornier at 2 kHz. HP 8751 A settings: power sweep vvith 6 dBm
c^enter and II dB span, A/R measurementt 21 points, A channel
attenuation - 20 dB, R f:!iannel attenuation = 20 dB, H'^ bandwidth
= 20 Hz. avera^in^ factor - 64. CW frequency = 2 JcHz.

the second IF. The ADC is a comniercially available,
16-bit, sLiC'cessive approximation type.

Dynamic Accuracy

To verify the design. I he dynamic accuracy perfomiance
of the tip 8751 A network analyzer wasi tested in rlire^
steps during the development phaae. Since die perfor-
mance data obtained in these tests was well below the
specified accuracy of 0.05 dB and 0.3 degree, the HP
8751 A is verified in production tising easier and less
costly methods whose accuracy ratio to the specificaticjns
is still quite high. Sophisticated atttt)rttaied tests now
under development will result in better specifications
without degrading I lie accuracy ratio or the testing
efficiency. The perftjrmaruT tests were as ibllows:

Step L The first step was an overall performance test
from the input port to the final ADC using a ratio Iratis-
former at 2 kHz as shown in Fig. 9. The change in the
measured values relati%'e to the value measured at the
-20-dB (= O.IOOOOCK)) setting of the ratio transformer was
measured for ever>' 10-dB change of the ratio transformer.
At the low power range, 64 measurements were averaged
to reduce the error caused by random noise. The mean
value and the standard <1eviatic>n (o) w^ere calctdated for
the measured data from 18 receiver boards kind it was
found tliat tlie mean plus L3a in the range from ~&) dB
^ "10 dB was within 0.01 dB for the magniUide ratio
measurement and within 0.1 degree for the phase mea-
surement. The mean plus 1.3o reiyresents the range in
which SQ^Hi of the samples are expected, assuming a
Gatissian distribution. This result is shown as typical
perfomiance in the instrument specifications.

Step II. The second step was the testing of the frequency
dependent tiortion of the signal path before the firs!
mbter near the maximum input range. The linearity of this
portion becomes better as the signal level decreases, so it
is sufficient to test at around the maximum input level
Fig. 10 shows the measurement conflgiiration for this test.

A 2<MB fixed attenuator was placed at the reference

cJiannel input (e.g.. the R channel) Id apply a level 20 dB
low^er than that at the test channel input (e.g.. the \
channel). Tlie powrer level applied to both channels was
\^aried by a step attenuator ahead of the power splitler-
The measured data taken in a .swepi- frequency measure-
ment from 1 MHz to 5<X» MHz with a O-dBm input level a!
the lest channel was compared with data taken with a
-2(MBm input level at the test channel to find the
frequency at w^hich the data changed most. Then the
dependency on the signal level w^as measured at that
frequency, using the powder sweep mode up to the maxi-
mum input level. The mean \alue and the standard
deviation were calctdated for the measured data from 9
boards and the mean ^alue plus L3ti was adopted as a
typical valtte at full-scale input, that is, at dB. The Ldo
values for amphtude and phase were 0JJ14 dB ;md 0*44
degree, well below the specifications of 0. 1 dB and 1.2
de^ee. Since a cur^^e fit to the Unearity data obtained in
step II showed that the nonlinearity decreases quickly
when the input level is 10 dB or more below full scale,
the data obtained in step II wus adopted as typical
perfomiance for the maximtmi input level.

Step III. The third step was a test of the dependency of
the magnitude imd phase measurements on the phase
change. Fig, 11 shows the configuration for this test. The
frequency of the HP 8751 A sotirce was set to the worst
case found in step il above, and a signal from another
signal source, which was frequency locked with the HP
8751A, was applied through a (able long enough to give
some phase difference between the reference and test
channels. With the frequency of the signal source slightly
different from thai of the HP 8751A, the phase difference
between the input signal and the inleiTial phase reference
of the HP 8751 A rotates at. a rate equal to the frequency

HPai&tA

Network
Aiinly^er

S fi A B
a <i II #

Power Splitttr

Fig, 10. Test configuration for step II nf the dynamic accuracy
UK ;isurrment. Hi^h-range perfomiance of the frequency depen-
denl iJorMon (if the signal path was tested. HP 8751 A settings: lin-
ear frequericy sweep with 1 -MHz start frequency and BtifJ-xMHz stop
frt?quency, A/R mea^surement, power = f5 dBm, IF bandwidth = 20
Hz, A channel attenuation ^ 20 dB, R channel attenuation - 20 dB.

April li'm Up wiptt-Packard Jounral 1 07

)Copr. 1949-1998 Hewlett-Packard Co.

differeiife. If tlit* receiver depends on the phase of the
signal cvjniparecJ wiLli llic ir\leni;il reference, (he (race of
(he magnitude or pha^se will change smusoi(lalI>'. I'he
peak-to-peak value of this trace gives a ineasiire of this
dependency. The resulliint values are 0.(J02 dB peak tt^
peak for the niagnhnde ratio ajrd i)X\] degree peak to
peak for the pfiasf nu^asurenienl. These results si tow iha(
the dependence of (he measurements on itje phase
change is small en<M!^^)i To he neglecled.

Digital Section

Pig. 12 is a block diagram of the digitid section of Ihv IIP
8751A. A 12.5 MHz MCliBHC'OOO CPV caUed the master
CPIT controls the overall measuring sequence, the graph-
ics system processor, the IIP-IB. the disk drive, the test
set, the keyuS on (he front panel, the general I/O port, and
Ore HP-IIIL for tiie external keyt>oard of the HP Instnj-
ment BASIC option. A 25-MHz Mt*68882 floating-point
coprocessor is used for the c:omplex matiiematical f^pera-
tions involved in conecting and fonnatting the measured
data, A 1M-I>v1:e ROM contains the operating system and
other control routines. Tlie firmware for the HP Instru-
ment BASIC option is contained in 1.5M bytes of ROM, A
16K-byte EEPROM contains (he setup and correction da(a
for Ihe analog rirruits. A (ilK-bytc SRAM backed up by a
large capacilur hukis the cfilibration tiataj the users
disjjiay colors, the date and limej and the RAM disk.

A i2.5-MTiz MC68HC(K)0 CPU called the slavt CPU
controls the analog sections, h ext hanges commands and
da(a witti tbe nmster CPL^ rh rough a MK-byte eomrnuniea-
tion HAM. A 128K-h,vie ROM holds the slave CPU ilrm-
ware, and a b4K-t\>'te SRAM sei^'^es as a work area.

To maximize the nieasuremenl speed, the master CPU is
isolated from ttiany (x>ntrol tasks and Irom the setting of
tlie analog boards hy the slave CPU. The master CPft is
isolated from the display tasks by the graphics system
processor This configuration, uUmg with pipelined pro-
cessing of tlic nieasiu*ement jobs luid the correcting and

teMH?

HPB751A

Ai^d(yfe^

SAAB
• ft fl •

Step Attenuator

-t-

Power Sptrlter

HP 8120 fl7B2

orHPHSOOB

Cable

Fig. II. n^st con fig umf inn Um .-^lep III of the dynaniif acciu'acy
measuremeRt. Phase dependency' of ttie accuracy characterisLics
v^ lesied. HP 4ID5A setting: 340.32 MHz - 0.05 Hz. HP a751 A
settiJigs: frequency = 340.32 MHz, sweep time = 20 s. Step attenua-
tor setting = dB

KP-tB

Fig. 12, HP S751A digital section.

calculating jobs, doubles the measin-enient rate. Tlie slave
CPli sets the stimulus, reads the outpul data from the
ADC in 50 j.ts after waiting for a settling time of 200 ^s
for Oie analog sections, transfers the data to the master
CPIJ through the communication RAM, mxd then starts to
set the stimulus for the next measurement. The master
CPU, with the aid of the MC68^2 coprocessor, corrects
the raw data for internal errors and user calibration,
formats the corrected data for the display, and transfers it
to (he graphics system processor. This process takes less
than 350 as per point. While the master CPU is process-
ing, the slave CPU is collecting the data for the next
measmement point.

Firmware Design

In developing the Ormware for the HP 8751 A, efforts
were made not to specialize but to genei^ize. The

108 April 199-Z Itr w'lrtT -PiirkarTi Joiimal

)Copr. 1949-1998 Hewlett-Packard Co.

Fig. 13. (a) HP 87512At.ransniissioiL''reflec:noii t.esl set., (bj HP
418G2A 1 -Ma input. ada|)l,er.

operating system is designed to provide a general Gn\ii'on-
ment for other firmware routines, similar to that in
computers, rather than an instmmentHDriented environ-
ment like that in earlier analyzers. Almost all of the
firmware code is written in the C language, taking into
account the portabUity of the code to future products.
The code for the slave CPU and part of the c;ode for the
master CPU are written in assembly language for maxi-
mum speed. The compatibility of the user ititerface with
that of existing products is taken into account in the
design. The HP-IB commands for the same functions arc
tJie same as for the IIP 8753A/B/C, and the softkey
allocations and the structure of the service functions are
almost the same.

Installing HP Instrument BASIC into the instrument
environment requLred special considerations. One was
how to share the I/O resources, such as the CRT the
kej^boards. and the HP-IB port. Another was how to
share the processing time between the instnunent and HP
Instrument BASIC. To resoh'e the first item, display
allocation is designed to be user-selectable by soft key.
The user can select aU instrument, half instrument and
half BASIC, or all BASIC to determine how the CRT
screen is allocated. To resolve the second item* the
processing time is sUced into lOO-ms intervals and is
shared almost equally between the instrument and HP
Instrument BASIC. The inter\-al of about 100 ms is tuned
so as not to interrupt measurements during a sweep
operation in the fastest sweep mode.

To keep HP Instrument BASIC programs in the HP 8751 A
as consistent as possible with those in external control-
lers, select code 8 is used for the HP S751A, following
the example set by other HP products.

Fixtures

Tw^o types of test sets and an adapter for a high-imped-
ance probe are available. The HP 87511 A 50-ohm test set
and the IIP 8751 IB 75-ohm test set are UX)-kHz-
to-500-MHz s-parameter test sets for measiuHng device
s-parameters in both forward and reverse directions. The
HP 875 12A 50-ohm test set and the HP 875 12B 75-ohm
test set are 5-Hz-to-500-MHz reflection/transmission test
sets that are essentially resistive di\iders for measuring
reflection and tiansmission characteristics at iow cost.
For adequate directivity, these test sets must be cali-
brated using standards stipplied witli them. The HP
41802A is an adapter that converts the HP 875 lA input
impedance from 50 ohms to 1 megolim for the conve-
nience of using the high- impedance probes matched to a
1 -megohm termination that are widely available for
oscilloscopes. Pig. 13 shows the HP 87512 A test set aiid
the HP 41802A adapter. The HP 875 11 A test set appears
in Fig. 1.

Ackn o w ledgm e iits

The HP 8751 A design team members who deserv^e special
recognition are Hitoshi Imaizumi, KazuhJsa Utada, Satoshi
Roppongi, and IVoy Morin for the signal source section,
Hiroaki Ugawa for the receiver, Kazuhiro Matsui for the
power supply and test set, Jun Kadowaki, the leader of
the softvt^are and digital group, Akira Nukiyama. Kohichi
Takeuchi, Katsuhiro Hakamada, Atsushi Hattori, and
Hideki Yamashita for software, Ken-ichiro Nakaya, Kotaro
Yamauchi, and Mutsuhiko Asada for software and digital
hardware, Akira Uchiyama, Koji Takeda, and Norio
Nakano for mechanical design, and Kenichi Katoh for
industrial design. Special thanks are also due Kazuyuki
Yagi for his general management, design ideas, and
encoiu-agement to the team, Masahiro Yokokawa and
Satoru Hashimoto who managed the software group,
Ihroshi Shiratori who managed the mechanical and
industrial design group, and Masao Noguchi for his
general management.

AprU 1 992 Hewlett-Packard Journal 1 9

)Copr. 1949-1998 Hewlett-Packard Co.

A High-Performance Measurement
Coprocessor for Personal Computers

This plug-in card brings test and nneasurement coprocessing power to ISA
(Industry Standard Architecture) personal computers with greater
calculation speed and better HP-IB performance than its predecessor It
also has DMA capability.

by Michael P. Moore and Eric N. Guile rud

The IIP 8232M high-porformancp measuTGmenl coproces-
sor is a plug-in card for PIP Vectra and compatible
computers that turns an ordinary PC into a multiprocess-
ing test and measurement workstation. The coprocessor is
programmed witlun the DOS environment using HP
BASIC, a de facto standard test and measurement pro-
gramming language.

The HP 82324 A high-performance measurement coproces-
sor is designed to meet customer needs for higher cal-
culation speed and better HP-IB performance than its
predecessor, as well as DMA for better overall system
performance. To minimize duplicated effort and maxim isse
reliability^ the design of the measurement coprocessor is
leveraged from the HP 9000 Model 332 computer The
Model 332 was chosen because of its low cost, high
performance, and potential for fitting onto a single
fun-size PC I/O card.

Hardware Ardutecture

Fig. 1 is a block diagram of the high-performance mea-
sxirement coprocessor At the heart of tbe design is the

16-MIlz MC68030 CPU with its integral memoo' manage-
ment unit. The MC68882 floating-point coprocessor can be
installed as a socketed option. A custom DMA controller
allows rapid transfers of data between niemorj' and
devices. Plug-in RAM boards, similar to the Model 332
RAM boards, are available in lM-b>te and 4M-byte sizes.
One or two RAM boards can be plugged into the main
board , allowing RAM configurations of IM, 2M, 4M, 5M,
and BM bytes. Built-in HP DIO input/output bus circuitry
provides a connection to companion HP GPIO and HP
SRM (shared resource manager) interface cards, and the
onboard HP-IB interface allows direct connection to
HP-IB (IEEE 488, lEC 625) instruments and devices.

Features eliminated from the Model 332 design include
the display circuitry, keyboard controller, timer, speaker,
and serial I/O. Those functions are performed by PC
resources through an emulation process discussed later.
Space constraints required the elimination of the memory
parity circuitrv'. The boot ROMs were replaced by a
scheme tliat uses the CPU's memory management unit to
remap RAM downloaded from the PC into the boot ROM

Fig, 1. Block diagram of the HP 82324 A high-performance measurement coprocesson

1 10 April 1902 Hewlett-Packard JoumaJ

)Copr. 1949-1998 Hewlett-Packard Co.

PC Address

fCiiiti

T — r

1 — r

B»ak
Sfkct

Bank

i/QAddtesi
Decode

DIP

Switch^

1-4

MsMUifiwem CofirDGes^or D«t»

J L

Fig» Z. Btock dia^gram of the application-specific integrated drciiiL In the measurement coprocessor.

address space. Added to the Model 332 design is an ASIC
(application-specific integrated circuit) that provides an
enhanced Interface to the PC backplane. It includes the
same interface mechanism used by its predecessor
(detailed in the section below on de\ice emulation), as
well as a new memory-based mechanism that allow^s a
higher-bandw^idth data path to the PC. Fig. 2 is a block
diagram of the ASIC.

PC Backplane Interface

The inlerface to the PC backplane consists of two banks
of eight H-bit UO registers, two 1024-byte menioo' buffers,
and three interrupt sources. The base address of the I/O
registers is configurable by a DIP switch at the top of the
main board. The base address of the memory buffer and
the intentip! level are both configurable through the I/O
registers. The user can reconfigure the card whhout
having to remove it from the computer and without
turning off the computer Four switches aie used to
select the base address of the I/O registers. Two of the
switches select one of four adtlress ranges within the
PC/s standard 10-bit I/O address range. These addresses
are 250h, 280h, 330h, and 390h, The other two switches
select one of four "alias'* address ranges outside of the
PC's 10- bit I/O address ranges making the base address a
12-bit value. In other words, if the first two switches
select a base address of 250h, then the other two
switches further qualify the address as one of 250ht 650h,
A50h, or E50h. This addressing scheme allows up to four
HP 82324A cards to be mapped into a single S-bit register
bank, conserving scarce PC I/O resources. Finally, the
second bank of registers is selected by the thirteenth
address bit. Thus, if the first eight registers are at 250h
through 257h, the second eight are at 125€h through
1257h. Again, this scheme conserves PC I/O resources.

One of the I/O registers selects one of eight possible PC
interrupt lines and one of eight base addresses for the
memoiy buffer. It also selects either the 8-bit or the 16-
bit access mode of the memoiy buffer or disables tt
completely.

Another I/O register is used to generate interrupts to the
68080 from the PC. ThLs enables the PC software to
emulate devices that generate interrupts , such as the
keyboard controller This register is also used to enable
or disable the three interrupt sotirces that generate PC
interrupts. These interrupt sources are a lO-millisecond
periodic interrupt, a PC mailbox interrupt, and an addre^
match interrupt.

The 10-milhsecond interrupt source is used as the time
base for the keyboard controller emulation. In an HP
9000 Series 300 computer, the keyboard contxoHer con-
tains timers used for keeping the time and date, for
timeouls. for periodic event generation, and for delays.
These timers all have a resolution of 10 milliseconds.
Since the PC's periodic system interrupt occurs only
approximately every 55 milliseconds, the 10-millisecond
interrupt source on the measurement coprocessor w^as
necessar>^ The mailbox interrupt occurs when the 68030
sets the PC mailbox flag. The purpose of this flag is
discussed later The address match interrupt occurs when
a bus cycle initiated by the 68030 is within an address
range reserved for device emulation. This intemipt source
can be used to implement intern^pt-driven device emula-
tion instead of polled device emulation.

Device Emulatlott

When the 68030 (or some other DIO bus master, such as
the DMA controller) generates a bus cycle within a
certain range of addresses, the ASIC freezes the bus cycle
and waits for PC software to complete it. If the 6S030 is
performing a write operation^ the PC software can read
the value and release the bus cycle. If the 68030 is doing
a read, the PC software can place a value on the data
bus and release the bus cycle. To the 68030, nothing
different is happening from writing to an actual hardware
device, such as the built-in HP-IB interface, except that
the bus cycles take much longer to complete. The PC has
complete control over the termination of one of these
"trapped'* cycles, and can take its time determining
whether to terminate the bus cycle nonnaliy or abort it
with a bus error

(continuKttJfi page 113)

Aprii 1 992 Hewktt-Packartl JoomaJ 111

)Copr. 1949-1998 Hewlett-Packard Co.

Mea§iireinent Coprocessor ASIC

The ciistam. ap pJ ica linn- spec rfJc integrated circiiit (ASIC) in the HP 82324A mea-
surement coprocessor dessgn contains the mtarface between the Industfy Stan-
dard Architecture [[SAJ backplane bus of the PC and the CPU bus of the measure-
meni coprocessor The interface to the PC supports either 8-bit or 1 6-bi1 access
modes while the measurement coprocessoi mterface is hxed at 16 bits.

The ASJC has outputs directly connectetl to six interrupt lines on the measurement
coprocessor interface so that PC software can generate multiple mterrupts. On the
PC. each interrupting device must have a dedicated interrupt line. At boot time,
three software-controlled outputs select ore of eight possible interrupts to con-
nect to the ISA bus by external circuitry.

Sixteen registers in the ASIC are addressable from the PC interface and six are
addressable from the measurement coprocessor interface. In the PC interface the
registers provide a view and limited control of the state of the measurement co-
processor bus. Data can be read from or written to the data bus during trapped

Mastsf

HfSU nnd imtial £lal^ of
REQ IS ckHircd '

Put Wrilf! Tu nln¥i?. !■ ot hytss.

bujchsui? inro buHur A

StBva

RESn jiiiti initial state of
ACK IS "set ^

Set nEQ m ClCBf ACK and

siAfiiiy; I he 1i offers; copy Btock

MmH 1} to buffer B

^»^ #

Got Writtf IQ ituvB. 4 at hyies,
bic^ckiifc from tiiiffer A; set ACM
10 siynBl ready aild ule^r REH

Sot I^EO 1Q clitsr ACK and

swjni} ihe bixffers, €Opy Block

2 tor H\ Id biitfeT A

Copy Slack 1 traai buffer B:

set ACK 10 signal ^eady and

cleainiQ.

Copy Btack H from buffer A:

£«t ACK tu signal ready anri

clear HECL

Master

RESET and inilial state of
RHQ IS 'cleared "

Pul Rfailtroinslavii, i of bvli3%.
^loctturr rnta bulfer A

litnckie/t; IroiTl buflfir A

Copy Block 1 into buffer A,

set AC^K to signal ready and

clenr req

Set R£U lu clem ACK iind

swing Ike buffers, copy Block

}\oiN II from bulfer A

<4 ^

Yfts

Copy Block 2 [or fU) inio

buffer B; sei ack to signal

ready and clear REQ

Set RtD 10 clear ack and
swing the bulfejfs, cepy
Black rj Irom buffer B.

Rg. 2. Dats transfer from slave to master

accesses, and the cycle is then ended under register control, (for a description of
trapped accesses, see "Devfce Emulation" in the accompanying artjclef. The PC
can else assert any of the six shared priority-level interrupts on the measurement
coprocessor, A typical use of tfiese interrupts fs as follows. The PC receives a
keystroke for the measurement coprocessor and asserts an interrupt as if it were
the keyboard controller. The measurement coprocessor responds to the interrupt by
addressing the keyboard controller register to read the keycode. Tfie read cycle is
trapped and recognized by the PC, wh^ch writes the keycode to the measurement
coprocessor data bus and asserts the signal to end the read cycle.

There are three types of interrupts for the PC, which can be enabled separately.
These are generated by s lO-mHIisecond tfmer, a semaphore flag in the measure-
ment coprocessor mterface, and address matches, Matching addresses are exter-

Fig. 1. DaiB transfer from rrtaster to ^lave,

112 April 1992 Uewlett-F^ksrd Jouma]

)Copr. 1949-1998 Hewlett-Packard Co.

nally decoded tnd cat^orizsd by three inputs m ifie ASIC: aip}^ ^?c^se$^ grapiv
ic$ accesses, and a! I others. Ttie PC can view these categortes to detenTune wtiai
action needs to ^ taktn

The DMA EontroJIer on the me^urement ct^rocessor reli^ on extetjal rea^urces
to perfonn dyte folding, ttiat is, duplicating data fiam the few byte of tfie bus to
ihe htgh byte when necessary for tiwistefS [nvoMng 8-t)st toices iyte foldinQ is
haml^ed w?thm the ASiC on ifemand hrim the DMA cwrtmller

Byte addressing by the Motorola CPU of the messy remem coprocessor is diffennt
from byte addressing by the imsl CPUs used in PCs The least'Significant byte of a
WQtd has an odd address for MotorDfa and an even address for Imel For files as
well as for some data types, it i% necessary to swap bytes whenever they are
stoi^ed on the PC. The ASIC can perform byte swapping in hardware if enabted via
3 register ir> the PC interfKe.

Two banks of 512 x T6 bits of RAM are included in the ASIC to facilitate fast block
transfers between the measuremem coprocessor and the PC, The two RAM banks
are configured as a "swing buffer" called the HyperChannel. Each bank can be
accessed from either the PC interface or the measurement coprocessor mterface

but mt fwm boih simuhan^MJSly While the PC is ao^sslng one t@nk. the tr^a-
sur^nent copfocessor can be irKJeperxlently accessing the oih^ When both xfm
PC and the m^sufemem copfoeessor have frntshed their resf^ctive accesses, tfie
buffers can tre swaj^ied or "swung" beivween the two interfaces. This allows one
[nterface to be continuous ly hllfng buffers while the other Tmerface is continuously
emptying them m a fully simultaneous process. In this way. a transfer can be
accomplished at the full speed of the slower interface

An jdentJcal set of registers is providal tor each imerface to syncrrFonsie transfers
using the HyperChannel. Only one interface can initiate a uansfer and is therefore
considered the owner or master of the HyperChannel, whtle the other mterface is
considered the slave Either interface can be master, but ownership can onjy be
relinquished by the current master, not pfeemptively seized by the slave tdentical
sets of four sfngle-hit write registers and one read register exist in each interface
to conirof the HyperChannel. The read registers include four bits indicating the
state of each of the wrJte registers. The write roisters allow the assertion of the
signals request [REQL acknowledge lACK}. error (ERR} and change master. The
master asserts REQ, which in turn clears ACK and swings the buffers. The slave
asserts ACK, whtch in tum clears REO. Figs i and 2 show the protocol for trans-
ters between master and slave

The PC can handle the emulation of devices either by
waiting for an address match interrupt, as mentioned
abovet or by polling the status of the 6803O's bus. The
polling method allows the PC to emulate devices faster
than an inrerrupt.-based method, but emulation software
must be constantly polling the interface instead of waiting
for an event.

While the trapped address mechanism simplifies the PC
software and initially eliminated the need to modify HP
BASIC software, it has two msyor drawbacks. First, the
rate of data transfer betw^een the PC and the measure-
ment coprocessor is relatively slow. This often makes the
transfer of large blocks of data the bottleneck in PC/mea-
surement coprocessor performance. Second, no interrupts,
even nonmaskable, can get through lo the 68030 when it
is m the trapped address state. This makes interrupt-driv-
en I/O without hardware handshaking unreliable at best,
and impossible in some situations-
Improved Interproces^or Communication
To circumvent these drawbacks, the PC interface has a
secondary^ communication channel called the HyperC'han-
nel. This memory-based mechanism consists of two
1024-byte buffers and three handshaking flags. When one
of the buffers is accessible to the PC, the other is acces-
sible to the 68030. and vice versa Whichever processor is
designated the channel master controls the swapping of
the buffers when both processors are ready. Since the
buffers are being accessed simultaneously, the sustained
data transfer rate is as fast as the slower of the two
processors. In addition to the performance advantage, this
protocol allows the measurement coprocessor and the PC
to transact business while both processors remain com-
pletely intermptible by other tasks. See "Measurement
Coprocessor ASiC," page 1 12, for a detailed description of
the bttffer protocol.

A third commtmication mechanism has been added to
make the interface even more flexible. This communica-
tion path consists of two mailbox flags, one for the PC
and one for the measurement coprocessor Both mailbox

flags can be read by either processor, but only the
mailbox flag owned by a processor can be set or cleared
by it. When the measurement coprocessor sets its mail-
box flag, an interrupt can be generated to the PC, The
two processors can then synchronize operations by
waiting for both mailbox flags to be set, clearing their
mailbox flags, and waiting for both mailbox flags to clear.
This protocol allows the measurement coprocessor to
generate a PC interrupt without having to be frozen in
the trapped address state.

Software Arehitecture

There are two types of software for the measurement
coprocessor: software that runs on the measurement
coprocessor itself, and software that runs on the host PC*
Both groups of softw^are work cooperatively and concur-
rently to exploit the capabilities of the measurement
coprocessor architecture.

The software that runs on the measurement coprocessor
is HP's version of the BASIC language, w^hich has been
prevalent in the instrument control world for many years.
Because the hardware architecture is leveraged from the
HP 90O0 Series 300 product line, existing HP BASIC
programs can run on the measurement coprocessor,
usually without modification. Also, the reference manuals
are identical to those shipped with HP BASIC for
workstations. Even the measurement coprocessor version
of the HP BASIC system is compiled from the same
source code that is used to generate the workstation
version. (For the history of the development of HP BASIC
for the PC, see "Measurement Coprocessor History/ page
114.)

In addition to running the HP BASIC system, the mea-
surement coprocessor emulates the system boot ROM in
RAM, eliminating the requirement for ROMs on the
measuremejtt coprocessor. To achieve ROM-less operation,
the PC loads a small boot loader program into the
measurement coprocessor's RAM. After testing system
RAM, this boot loader program copies the boot ROM
im^e from the PC to the bottom of system RAM, initial-
izes the 68030's memory management unit to map logical

April 1992 Hewlett-Packard Journal 113

)Copr. 1949-1998 Hewlett-Packard Co.

Measurement Coprocessor History

In the early 1980s, the HP 900D Series ?0O computer was HP's premier instrument
controller With HP's version at the BASIC lengtiage, the Series 200 made automat-
ir>g pan or all of the test and measuremem task mych easier HP 8ASJC became e
de facto standard tesi and measurement language.

The early 1 980s also saw the introduction of the IBM personal computer IPC].
Within a few years, the IBM PC ar>d compatitile machines replaced ttie Series ZOO
and 300 computers as instrument controllers for a large portion of the test and
measurement market. However, there was no implemenlatinn of BASIC for the PC
that offered the rich feature set HP BASJC customers had come to expect HP's
answer ta this problem was the BASIC language processor — a pEug-in card forttie
PC that temporarily turned the PC into an HP 9000 Series 200 instrument controller

Two basic strategies for porting the HP BASIC environment to the PO platform
were initially considered. One approach was to rewrite the HP BASEC software so
that It would run directly in the DOS environment. Because HP BASIC was heavily
optimized for the HP 90 DO hardware environment, this approach required the
commitment of many resources and involved unknown risks.

The other approach was to "port" enough of the HP 9000 hardware to the PC
platform so that HP BASIC would run mdirectly m the DOS envifonmeni. In otiier
words, HP BASIC programs would run on a coprocessor card, while the PC emu-
lated HP 9D0O hardware that wasn't on the coprocessor card. While this approach
eased the software effort, it required the customer to purchase additionai hard-
ware for the PC-
After weighing and considering the two approaches, HP chose the latter This
approach eliminated many of the teclinicai liurdles involved in moving the HP
BASIC programming environment to a completely different aperatmg system while
retaining compatibility witti the original envtronmenL

In the middle of 1987, the BAStC language processor was introduced. It featured
an B-MHi 680DQ CPU. an HP- IB interface, tioot ROMs, half a megabyte of RAM, an
HP 010 bus interface, and special circuitry to interface to the PC's backplane. The
heart of the interface circuitry was a mechanism that allowed a program running
on the PC to emulate hardware not present on the BASIC language processor.
Daughter hoards were available to add mare RAM or ROM. Sister boards were
available to provjde HP GPfO and HP SRM {shared resource manager) interfaces.
The same HP BASIC software that ran on HP 9000 Series 200 computers ran un-
modified on the BASiC language processor with an emulator program running on
the PC. Even the boot ROMs were Series 200 boot ROMs,

The emulator software that ran on the PC had three major functions. First,, it
mapped the 1/0 resources of the PC onto Series 200 hardware. Second, the emula-
tor software allowed HP BASiC programs to access the DOS operating system by
sendmg data to and reading from an imaginary GPIO interface. Standard DOS
comma r^ds, commercial applications software, and custom programs could all he
invoked from the HP BASIC environment Third, the emulator software allowed a
limited form of background operation. The emulator could be placed in the back-
ground, allowing the BASIC language processor to execute the current HP BASIC
program whHe a completely different application, suches an editor or spreadsheet
program, ran on the PC

Because of the hardware emulation scheme, most programs that ran on Senes 200
computers could be run on the BASIC language processor with little or no modifi-
cation. Even programs that directly accessed hardware (such as the graphics frame
buffer} could run unmoddied However, this degree of compahbtlit^ had a price:
severe performance degradation. Improving performance quickly became a priority.

The next major revision of the software included four major architectural changes.
Rrsi, the boot BDMs were rewritten to speed up the boot process by an order of
magnitude. Second, a new HP BASIC binary program was written that implement-
ed the DOS file system This provided a way for HP BASIC programs to access DOS
hies directly, without the clumsy emulatfon scheme described above Third, inter-
nal alpha, graphics, and DOS file system operations were reorganised on a trans-
action basis rather than a hardware emulation basis. In other words, the HP BASIC
binaries that implemented alpha and graphics video operations and the new DOS
file system binary program generated transactions insiead of register-level ac-
cesses. The emulator program on the PC was rewritten to service these transac-
tions as well as its hardware emulation tasks, and the background mode of opera-
tion was enhanced to allow DOS file system operations in the background,
enabling an HP BASIC program to fog data to disk while another DOS application
was running. Fourth, a mechanism for a background HP BASIC program to commu-
nicate with a foreground DOS application {such as a spreadsheet) was added.
Because of these expanded foreground/background capabilities, the BASIC lan-
guage processor was renamed the measurement coprocessor It represented a
great improvement in boot performance, graphics operations, and mass storage
operations, and provided greater versatility in die DOS environment.

However, while the new software emulator made significant improvements in
some areas of performance, the remaining issues could only be addressed by
upgrading the hardware. These issues included increased computation speed,
HP-IB I/O throughput, and DMA capabilities. From this effort came the high-perfor-
mance measurement coprocessor described tn the accompanyirig article.

references to boot ROM address space to t)ie image in
RAM, and transfers control to the RESET exception vector
ill the boot ROM image. FVom that point on, the boot
ROM and the IIP BASIC system operate as if a boot ROM
were actually present.

Host PC Software

The software that runs on the host PC is grouped into
four parts. The system software configuration part is
handled by the CONE EXE program. The boot process
and w^orkstation emulation parts are coordinated by the
BASIC.EXE program. DOS/!IP BASIC communication is
handled partly by the BASIC.EXE program and the
HPBLRSYS device driver, and partly by the POP-
COMX:OM program.

The CONF.EXE program allows the user to alter the
software configuration interactively so that the PC's
keyboard, serial ports, and HPJB cards can be remapped
as desired. It also allows the user to specify how to map
the PC's disk drives to appear as emulated LIP (HP
logical interchange format) disk drives. Configuration

infonmatioii is stored in a file that is used by the emula-
tion programs described below.

Boot Process

Tile BASIC.EXE program is the main control program for
the boot and workstation emulation tasks* UTien BA-
SIC EXE is run, it first checks to see if the measurement
coprocessor has been booted. If it has not. It starts the
boot process. The boot process is handled by two sepa-
rate programs, both of which are run from BASiCEXE*

The first program, BO. EXE, is responsible for starting the
measurement coprocessor and loading the boot ROM
image into it. The second program, B2.EXE, is responsible
for managing the boot process, which is an emulation of
the HP workstation boot process. Both programs request
hardware configuration information from a device driver
(HPBLHSYS), which is installed by CONFIG.SYS when
DOS boots up.

When BO. EXE begins execution, it requests the hardware
configuration information for the measurement coproces-
sor being booted from the HPBLRSYS device driver and

114 April 1992 tJpwlett Patkard Journal

)Copr. 1949-1998 Hewlett-Packard Co.

verifies ihat there are no hardware configuration conflicts
with DOS or other applications. It then resets the mea-
surement coprocessor, which leaves the 68030 frozen in
the trapped address state trving to fetch the si-ack pointer
from address SOOOOOOOO. BO.EXE then copies a boot
loader program to the HjperChannel buS^er, and emulates
boot HOM accesses long enough to cause the 68030 to
exchange buffers and run the pro^-am in the buffer. Once
the boot loader program is running, BO. EXE copies the
actual boot ROM image to the measurement coprocessor
over the HyperChannel,

ThB B2.EXE program handles the boot process for ^e

measurement coprocessor. This program cooperates with
the boot code loaded by the BO. EXE program to simulate
the Series 300 boot process. Systems can be booted from
a ^^ariety of sources, including the optional HP SRM
interface or external HFS (HP hierarchical file system)
disks. To the user, the PC behaves like an HP 9000 Model
332 computer booting up.

Workstatian Emulation

After successfully booting the measurement coprocessor,
the BASIC.EXE control program, in conjunction with the
B3.EXE program and the IIPBLP.SYS de\ice diiver,
emulates the portions of the workstation hardware not
present on the measiuement coprocessor. The emulation
services provided inckide the emulation of the worksta-
tion's display, keyboard, beeper, and mouse, mapping of
the PC HP-IB, serial, and printer ports to emulated
workstation I/O cards, and mapping of PC disk drives to
workstation LJF and DOS formatted disk drives. A mecha-
nism for rurming DOS conunands from the measurement
coprocessor is also provided.

The workstation emulation task can be run either in the
foreground or in the background. In foregroimd mode, the
PC behaves as if it were an HP 9000 Model 332 computer
running OP BASK*. In the background mode, the user
runs DOS applications while the measurement coproces-
sor concurrently runs an HP BASIC program without a
visible display or keyboard.

The BASIC.EXE program is responsible for emulation
services common to both foreground and background
modes. These services include access to the DOS file
system, emulation of the timekeeping and beeper parts of
the workstation keyboard controller, and the buffering of
alpha video. When HP BASIC is placed in the background
mode, BASIC.EXE remains resident in DOS memory wliile
other DOS applications execute.

The full workstation emulation is provided by the B3.EXE
program, which is started by BASIC.EXE. B3.EXB pro-
vides all emulation services not provided by BASIC.EXE,
Communication between BASIC.EXE and BaEXE is
facilitated by code and data resident in the HPBLPSYS
device driver The common data includes state variables
and procedure entry points, and the common code
includes interrupt service routines*

Becatise B3,EXE is not executing during background
operation^ all processing on the measurement coprocessor
stops when an HP BASIC program tries to access emu-
lated services available only in foreground mode* Process-

mg resumes when the measurement coprocessor is
switched back into foregroimd mode.

DOS/HP BASIC Communication

Because the measurement coprocessor runs concurrently
with the he^t PC, iliere is a potential for dividing the test
and measurement task between the processors. To take
advantage of this potential, the measurement coprocessor
must be able to communicate with DOS and DOS s^pli ca-
tions. The measurement coprocessor software supports
this interprocessor comniuni cation with three basic
meclianisms: shared file access, MultiCom^ and PopCom.

When the measurement coprocessor is in the background
mode, an HP B.ASIC program can write to or read from a
DOS file, even if a foreground application is using the file
system. While DOS is not a multitasking operating system,
il is possible for a collection of interrupt service routines
to give a background application access to the DOS fUe
system when the foreground application is not using it.
The background service routines in BASIC.EXE, in
cory unction with the interrupt service routines in the
HPBLPSYS device driver create this ilkision of concur-
rent use of the DOS file system, which is the basis for
this form of interprocessor communication. \^Tiiie this
scheme can be used by any application that can access a
DOS file, it is relatively slow.

The MultiCom mechanism for DOS/HP BASIC communica-
tion uses the existing I/O capabilities of DOS and HP
BASIC compiled subroutine libraries to aOow IIP BASIC
programs to send messages to and receive messages from
DOS applications. With MultiCom, an HP BASIC program
running in the background can generate keypresses to the
DOS application running in the foreground by calling one
of several compiled subroutines. Converse ly, a DOS
application running in the foreground can send messages
lo tlie HP BASIC program running in the background by
writing to a measurement coprocessor device file (similar
to the ,PRN file for a printer). To illustrate this mecha-
nism, assume that the user wants to run a test, then
integrate the data into a spreadsheet to generate a
printed report. The user programs the measurement
coprocessor to handle the setup, initiafion, and data
gathering parts of the test, using MultiCom to receive
parameters from and send data to the spreadsheet pro-
gram. The user programs the spreadsheet program to
start the test on the measurement coprocessor, receive
the data, and graph the results on a form. The user uses
HP BASIC for the test task and the spreadsheet program
for the presentation task instead of trying to do both
tasks in one environment or the other.

Another use of the MultiCom mechanism is to support
multiple measurement coprocessor configurations. With
MultiCom, a DOS application can communicate with up to
three measurenvent coprocessors in a PC. In addition, one
measurement coprocessor can conununicate with another
independently of the DOS application running in the
foreground. In this manner, powerful multiprocessing test
systems can be configured and controlled in one host PC.

Finallyj a user may simply want to start a test mnnlng on
the measurement coprocessor, then go do something else

Aprli 1 992 Hewlett-Packard JotimaJ 115

)Copr. 1949-1998 Hewlett-Packard Co.

in DOS, such as reading electronic mail or writing a
document. However, if the user wants to be notified when
the test finishes, or just wants to see how far along it is,
it would be annoying to have to stop working, start up
HP BASIC, type a couple of commands, exit HP BASIC,
and restart the DOS apphcation. The PopCom mechanism
supports a kind of "pop-up" interface to HP BASIC
running in the background. With PopCom installed, an HP
BASIC program in the background can cause a dialog
window to pop up over the foreground DOS application,
temporarily taking control of the PC. After the user
enters a response^ the pop-up window disappears, and the
foreground application continues execution. This type of
pop-up interface is already popular with PC users, and
fits naturally into the DOS environment.

Acknowledgments

The original HP 9000 Model a32 CPU board design was
done by Mark Anderson of the former Fort Collins
Systems Division. Cari Thomsen did the ASIC design
before transferring to the Vancouver Division before the
end of the project. Greg Parets joined the project tow^ard
the end and was instnimental in the final stages of
development and release to manufacturing. The software
development ream for the HP 82324As predecessor, the
IIP 82300A basic language processor, was managed by
Andy Rood and included Terry Leepcr (project leader),
Everett Kaser, Leon Nelson, Roberto Orozco, and Tony
Yokoyama. Roberto also took over as project manager
from Andy during the second major revision of the BLP
software. David Kepler managed the hardware design and
softw^are Q.4 of both tlie HP B2300A and the HP 82a24A.
Support from the RMBAV^S team at MSO was invaluable.

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April 1S92 Votume 43« Number 2

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