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VOICE OF THE ENGINEER 



Rex 6000 PDA Pg 18 

SOI Industry 
Consortium stalks the 
"green thing" Pg 6 

Baker's Best Pg 16 

Design Ideas Pg 39 

Product Roundup Pg 46 

Tales from the Cube: 

Finger on the trigger 
Pg48 



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EDN 8,20.09 

i contents 



Transporting high-def 
video broadcasts: Are 
wireless networks up 
to the task? 

^"N A High-resolution video- 
J /\ streaming support is 
I supposedly a key justi- 
fication for 802.1 1 n versus its 
802.1 1 a and 802.1 1 b/g prede- 
cessors. So why doesn't it deliver 
on its promises? by Brian Dipert, 
Senior Technical Editor 




Take advantage of 
open-source hardware 

O /^Basing your product on a 
^ preference design or demo 
board can speed time to market. 

by Gerald Coley 
Texas Instruments 







i -I 

1 MEMMAX 

■schedule 





64MX16X2 BITS 



Addressing interleaved 
multichannel memory 
challenges 

O O Interleaving addresses in 
O multiple DRAM channels 
can greatly improve memory band- 
width, but it is not a trivial task. 

by Drew E Wingard, PhD, 
Sonics Inc 




Dilbert 



10 Trigger, decode, and graphing 
packages simplify scope- 
based audio-bus debugging 

Intel introduces speedy, 
inexpensive, 34-nm solid- 
state drives 



Rotary-encoder IC meets 
all auto specs 

Design and test combine 
to speed yield learning 



Lithium-battery formulation 
suits medical applications 

13 Western Digital packs 

1 Tbyte into 2.5-in. disk 

ASIC demultiplexes to multiple 
displays from one DisplayPort 
signal 

14 Voices: Asset InterTech Inc's 
Tim Dehne: seeking growth 
in embedded instrumentation 




DESIG 



IDEAS 




Triac tester allows for manual or automatic operation 
Handheld DMM copes with logic nanosecond-pulse-width waveforms 
Build a simple complementary-bracket-pulse generator 
Power-miserly voltage reference needs just one pin 



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contents 8.20.09 




DEPARTMENTS & COLUMNS 

EDN.comment: SOI Industry Consortium stalks the "green thing" 

Baker's Best: One circuit provides system resolution and 1 2-bit 
accuracy 

Prying Eyes: Rex 6000 PDA 
46 Product Roundup: Cooling and Enclosures, Integrated Circuits 
48 Tales from the Cube: Finger on the trigger 

EDN online contents www.edn.com 

ONLINE ONLY 

Check out these Web-exclusive articles: FROM EDN'S BLOGS 

Top 1 6 CEO lies 

From Leibson's Law, by Steve Leibson 
It seems my peanut gallery's gotten all mumbly 
about Guy Kawasaki's 1 lies that engineers tell. 
Perhaps they hit too close to home. So here's 
another of his lies list, 1 6 lies that CEOs tell 
and four things you wish they'd mouth instead. 
Maybe this'll loosen your tongues. 
^www.edn.com/090820tod 



NSF research funds could benefit EDA 
-or not 

t From Practical Chip Design, 

by Ron Wilson 

Jeannette Wing, assistant director 
^^^^H in charge of the National Science 
^^^^ Foundation CISE (Directorate 
for Computer and Information Science and 
Engineering), spoke to a packed luncheon audi- 
ence on the subject of the NSF and EDA. 
^www.edn.com/090820toc2 

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Publication/Volume 54, Number 16 (Printed in USA). 



Designing a multicore + 
coprocessor security system 

Network and communications pro- 
cessors are moving to heteroge- 
neous processor configurations for 
efficiency, cost, and best-of-breed 
flexibility. 

www.edn.com/article/ 
CA6662010 



Choosing between an ARM7 
and a Cortex-M3 processor 

The Cortex-M3 offers compelling 
features over the ARM7, but the 
ARM7 currently has a larger man- 
ufacturers and tools ecosystem. 

www.edn.com/article/ 
CA6673293 



E D N . C O M M E N T 




BY RON WILSON, EXECUTIVE EDITOR 



SOI Industry Consortium 
stalks the "green thing" 

n these days, only government spending seems to drive the economy, 
and everyone is lining up to be under one of those government spig- 
ots. This situation is tricky for the semiconductor industry because 
it's hard to make a case for a fabless semi company as being essential 
to bailing out Morgan Stanley, rebuilding our highway infrastructure, 
or checking the spread of swine flu. However, there is one area — en- 
ergy saving — in which chips and foundries can claim some home turf. 

Accordingly, just about half of new 
marketing programs have the word 
"green" — frequently capitalized — 
somewhere in the first paragraph of 
their promotional materials. Often, 
this approach is little more than spu- 
rious: an amplified echo of last year's 
key phrase, "low power." In some cas- 
es, though, the appeal to "greenness" 
makes sense, even without adding 
chlorophyll to the package epoxy. 

One such situation is a new ini- 
tiative — "Simply Greener" — by the 
SOI (silicon-on-insulator) Indus- 
try Consortium (www.soiconsortium. 
org). Part of the point is to hitch SOI 
to the green bandwagon. But there's 
content in there, too: One of the sig- 
nificant advantages of SOI is its abil- 
ity to deliver a better speed-pow- 
er product on a given project than 
a similar-geometry bulk-CMOS de- 
sign. Some of the more prominent 
press coverage of SOI — AMD's tra- 
vails and the heat problems with in- 
dustry-leading game consoles, for ex- 
ample — may have obscured this fact. 
Nonetheless, it is true. 

The SOI folks want to make clear 
the point that you can use that speed- 
power-product advantage to save sig- 
nificant power at the same speed. To 




The consortium 
wants you to know 
that SOI brings 
built-in power 
savings, and it is 
mainstream. 

underline that fact, a recent presen- 
tation gives examples of benchmark 
tests from ARM and IBM, which show 
side-by-side designs of blocks in SOI 
and in bulk CMOS. In ARM's case, a 
45-nm-datapath design, the SOI ver- 
sion achieved an almost-threefold re- 
duction in leakage and an approxi- 
mately 20% reduction in dynamic 
power. IBM's example was more ap- 
ples-to-oranges: a full-chip migra- 
tion from 65 -nm bulk CMOS to 45- 



nm SOI, resulting in an approximate- 
ly one -third reduction in power and a 
50% speedup. In these instances, the 
choice of SOI instead of the bulk pro- 
cess appears to be making more differ- 
ence than the use of aggressive power 
management. 

The mechanism for the efficien- 
cy gain seems to be simple — proba- 
bly simpler than it actually is. Because 
SOI builds its transistors directly over 
a buried insulating layer, the parasit- 
ic capacitances from the source, drain, 
and channel are much less than in a 
bulk wafer. By reducing these capac- 
itances, a SOI transistor can operate 
with lower drive current and, hence, 
can be smaller; have a higher thresh- 
old voltage; or offer both features. 
Thus, both leakage and dynamic cur- 
rents can be smaller at the same per- 
formance level. 

A second point the SOI Consor- 
tium wants to emphasize is that SOI 
is available as an off-the-shelf foundry 
process, not just as a full-custom tech- 
nology. "There's a wide range of regu- 
lar users now," says Horacio Mendez, 
executive director of the consortium. 
"Almost everything IBM is building at 
45 nm is in SOI, as are all of Freescale's 
latest networking chips. Casio is using 
the technology at extremely low pow- 
er levels for watches, and some vendors 
are applying the technology in auto- 
motive applications." Foundry service 
is available from IBM and Chartered 
Semiconductor, among others. 

SOI not only is a viable option for 
ordinary design teams but also has a 
road map, the organization claims. 
Processes are available in 65 and 45 
nm, and both 32- and 22-nm pro- 
cesses are on the drawing boards. The 
main ideas the consortium wants you 
to know are that SOI brings built-in 
power savings, and it is mainstream. 
Those points deserve some discussion, 
even from teams that are tooling up to 
work on bulk CMOS.EDN 

Contact me at ronald.wilson@reed 
business.com. 



6 EDN | AUGUST 20, 2009 




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EDITED BY FRAN GRANVILLE 




INNOVATIONS & INNOVATORS 



Trigger, decode, and 
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The serial AudioBus triggering, decod- 
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AudioBus uses color-coded overlays on vari- 
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graphing packages 
audio-bus debugging 



L%is; il 


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OB 



A WaveRunner Xi scope with the AudioBus 
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mute, clip, and glitch, help to isolate rare prob- 
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LeCroy Corp, www.lecroy.com. 



m FEEDBACK LOOP 
"What would 
those knotheads 
know about in- 
novation? Some 
of my best work 
has begun with 
those little, fleet- 
ing moments 
when something 
you weren't even 
thinking about 
before suddenly 
gels in the mind 
and shapes up 
into something 
neither I nor any- 
body else an- 
ticipated or were 
even looking for." 

—Consulting engineer and 
designer Thomas Fay, in EDN's 
Feedback Loop, at www.edn. 
com/article/CA6666234. Add 
your comments. 



10 EDN | AUGUST 20, 2009 



ROTARY-ENCODER 
IC MEETS ALL AUTO 
SPECS 

The AS5163 magnetic-rota- 
ry-encoder IC from austria- 
microsystems satisfies the 
stringent automotive-IC- 
protection requirements in 
angle-sensing applications. 
The device provides over- 
voltage protection as high 
as 27V, and reverse- polar- 
ity protection withstands 
-18V reverse polarity at 
the supply pins. The de- 
vice also has a short-cir- 
cuit-monitoring function. 



digital magnetic-sensor rotary 
encoder and operates at 
automotive temperatures. 



Its designers envisage 
that applications for the 
chip will include throttle- 
pedal sensing. 

The AS5163 features a 
single-wire interface that 
you can configure as a 
14-bit digital, 12-bit PWM 
(pulse-width-modulated), 
or ratiometric-analog out- 
put. You can also set it to 
cover any system-specific 
angle range by setting a 
start and end position of 
the rotational movement. 
The device operates at 
-40 to +150°C, comes in 
a TSSOP-14 package, and 
requires a 5V supply. 

—by Graham Prophet 

a ust r i a m i crosystems, 
www.a ustri a m icro 
systems.com. 



Intel introduces speedy, inexpensive, 
34-nm solid-state drives 



Although Intel and Micron's 
(www.micron.com) IM 
Flash Technologies 
partnership last November 
announced mass produc- 
tion of 34-nm lithography- 
based, 32-Gbit MLC (multi- 
level-cell) NAN D-f lash mem- 
ories, Intel fabricated its first 
generation of MLC-derived 
solid-state drives, along with 
their SLC (single-level-cell) 
siblings, on 50-nm ICs. In 
July, Intel unveiled its sec- 
ond-generation 34-nm, MLC 
solid-state-drive products, al- 
though, at first glance, you 
might scratch your head at 
what the fuss is all about. Intel 
still calls the drives the X25-M 
family, and they come in the 
same 80- and 1 60-Gbyte ca- 
pacities as their 50-nm prede- 
cessors, although they show- 



case a revised silver-case 
paint scheme. 

Real-life performance im- 
provements due to the 34-nm- 
fabrication reduction, especial- 
ly considering recent firmware 
updates of the 50-nm X25- 
M line, are also unclear. Intel 
says that the X25-M offers 
25% lower latency and nota- 
bly faster random-write opera- 
tions than its 50-nm predeces- 
sor. The reduced latency offers 
quicker access to data, oper- 
ating at 65-jxsec read latency 
compared with approximate- 
ly 4000 |xsec for a hard-disk 
drive. Random-write perfor- 
mance has increased twofold 
for the 80-Gbyte version and 
2.5-fold for the 1 60-Gbyte 
version. According to the com- 
pany, the X25-M delivers as 
much as 6600 4-kbyte write- 

The X25-M family 
comes in 80- and 
1 60-Gbyte capacities. 




I/O operations/sec-8600 for 
the 1 60-Gbyte version-and as 
many as 35,000 read-l/O op- 
erations/sec. 

Intel also admits that it does 
not expect substantial gains on 
application-based benchmarks 
versus its first-generation MLC 
solid-state drives. Conversely, 
targeted synthetic benchmarks 
and tests will reveal more no- 
ticeable differences. Lingering 
delays in 6-Gbps SATA (serial- 
advanced-technology-attach- 
ment) system-side support are 
likely a notable limiting factor 
in fully showcasing solid-state 
drives' speed strengths. How- 
ever, Intel is passing along 34- 
nm-process-lithography cost 
reductions to its customers. In 
July, the company was quoting 
channel prices for the 80- and 
1 60-Gbyte X-25M of $225 
and $440 (1000), respective- 
ly, a decrease from $595 and 
$945, respectively, at the 50- 
nm-based product introduction 
a year ago. Intel is now ship- 
ping MLC solid-state drives in 
the 2.5-in. hard-disk-drive form 
factor, with 1 .8-in. counterparts 
becoming available by the end 
of this quarter. Intel currently 
doesn't comment on the avail- 
ability of 34-nm-derived SLC 
solid-state drives. 

-by Brian Dipert 
Intel, www.intel.com. 



DILBERT By Scott Adams 



DILBERT SAYS tAY 
PLAN WONT WORK. 
I NEED A SECOND 
OPINION. 




HYPOTHETICALLY, IF 
I SAY YOUR PLAN IS 
TERRIFIC WOULD I 
END UP BEING THE 
ENGINEER UHO HAS 
TO IrAPLEIAENT IT? 



ttAYBE. 




YOUR PLAN 
REEKS OF 
INFEASI— 
BILITY. 




AUGUST 20, 2009 | EDN 1 1 



Ise 



LITHIUM-BATTERY 
FORMULATION 
SUITS MEDICAL 
APPLICATIONS 

EaglePicher Medical Power 
recently introduced a 
lithium-CFX (carbon-mono- 
fluoride)-battery chemistry, 
an enhancement of the 
company's proprietary 
CFX- battery technology. It 
results in a self-discharge 
rate of less than 1% per 
year at room temperature. 
Although lithium thionyl 
has a similar self-dis- 
charge rate, it increases 
rapidly with higher tem- 
peratures, making its use 
a liability in implantable 
medical devices, which 
must operate at 98.6°F. 

The CFX formulation 
also offers energy density 
of 180 Whr/l-approximate- 
ly 25% more than that of 
battery technologies that 
medical devices currently 
use. CFX lets battery-pack 
designers choose between 
a larger battery that runs 
for 25% longer and a 25% 
smaller one with an equiv- 
alent runtime. 

The CFX formulation 
incorporates an end -of - 
life indicator to accurately 
predict battery depletion 
six months in advance, re- 
quiring fewer replacement 
surgeries for implantable 
medical devices. The indi- 
cator manifests itself as a 
sharp falloff in voltage yet 
still maintains adequate 
voltage and power to 
operate. The new technol- 
ogy will be available in a 
number of configurations 
at powers of less than 350 
mAhrto 10 Ahr. 

—by Margery Conner 

EaglePicher, www.eagle 
picher.com. 



Design and test combine 
to speed yield learning 



Verigy has introduced its 
Yield Learning Solution, 
which integrates on- 
tester, real-time capture and 
analysis of electrical failures 
on complex SOC (system- 
on-chip) devices. The product 
combines preanalysis modules 
on the Verigy V93000 SOC 
test platform, including a de- 
sign-centric analysis and vi- 



DESIGN 

FABRICATION 

INSPECTION 
ELECTRICAL 



sualization tool set. The Yield 
Learning Solution comprises 
the V93000 scalable test plat- 
form plus the Triage Fault Lo- 
cator and YieldVision software 
tool sets for failure data cap- 
ture and yield analysis. Triage 
provides on-tester fault local- 
ization and includes an on- 
tester sampling engine; Yield- 
Vision supports offline data 
analysis. 

The scalable architecture of 
the V93000 allows for com- 
plete integration with the Yield 
Learning Solution. The Triage 
software's proprietary algo- 
rithms enable efficient data 
processing, and the YieldVi- 
sion analysis and visualization 



tools reduce the time required 
to diagnose problems. By 
seamlessly linking electrical 
test with physical-layout data, 
the tools allow fast localiza- 
tion of the root-cause physical 
defects. 

Diagnosing problems in 
nanometer-level-device de- 
sign and manufacture is be- 
coming more challenging, 



DEFECT Wj^^^^K^^M 

SEARCH M^^^B ^^B 

LAYOUT 
I EXTRACTION 



^^^^^^H FAULT 

| SIMULATION 

ASSEMBLE ^^^^B^^B 
PARTS 



which makes it essential to 
close the loop between design, 
fabrication, and test, says Colin 
Ritchie, vice president of mar- 
keting for DFX (design-for- 
test/manufacture/yield) prod- 
ucts at Verigy. Verigy's Yield 
Learning Solution addresses 
the design/fab matching that 
is essential for a success- 
ful business. He notes that 
design-for-manufacturability 
problems can result from li- 
thography-unfriendly design 
or failure to adequately follow 
increasingly restrictive design 
rules. The inability to quickly 
isolate and fix such problems, 
he says, can lead to billions of 
dollars in lost annual revenue, 



citing VLSI Research (www. 
vlsiresearch.com) figures. 

Ritchie notes that traditional 
approaches to yield diagnosis 
can require many days to iden- 
tify design problems that lead 
to yield loss; such iterative ap- 
proaches often require retest of 
failed devices plus a sequence 
of fault simulation and layout 
extraction to physically locate 
faults. The process not only is 
time-consuming but also can 
generate terabytes of data. In 
contrast, says Ritchie, Verigy's 
on-tester approach generates 
only kilobytes of data and de- 
livers results in minutes. 

The Yield Learning Solution 
efficiently links test back into 
both design and the fab, pro- 
viding logic bit maps for both 
stuck-at and difficult-to-detect 
timing faults in scan chains and 
logic. The Yield Learning Solu- 
tion provides both the accu- 
racy necessary for the lab and 
the high throughput necessary 
for production-critical for both 
new-product introduction and 
ongoing manufacturing moni- 
toring. Ritchie says that Triage 
can perform on-tester local- 
ization of blocked scan chains 
and hold-time faults while per- 
forming on-tester character- 
ization. YieldVision, he says, 
"speaks the language of the 
designer and the language of 
the fab," providing diagnosis at 
the wafer, die, and component 
levels. Ritchie cites customer 
results indicating a four-week 
acceleration in time to market, 
an increase in entitlement yield 
of as much as 6%, and a ten- 
fold reduction in the number of 
waivers required to reach en- 
titlement yield. 

-by Rick Nelson 
Verigy, www.verigy.com/ 
go/yield. 



Verigy's on-tester analysis capabilities can shave weeks off the 
time it takes to make design revisions based on manufacturing 
test data, eliminating retest, fault-simulation, layout-extraction, and 
defect-search steps. 



12 EDN | AUGUST 20, 2009 



Western Digital packs 1 Tbyte into 2.5-in. disk 



Western Digital re- 
cently broke its own 
record, becoming 
the first to shoehorn 1 Tbyte 
into a 2.5-in. hard-disk drive. 
This breakthrough comes on 
the heels of the company's 
becoming, in January, the first 
to ship a 2-Tbyte, 3.5-in. drive 
by squeezing four 500-Mbyte 
platters into the form factor. 
This approach was reminiscent 
of Hitachi's (www.hitachi.com) 
four-platter approach, land- 
ing that vendor in first place to 
cross the threshold for 1 -Tbyte, 
3.5-in. hard-disk-drive storage 
in early 2007. The company mi- 
grated to a three-platter con- 
figuration 1 8 months later. 

Western Digital's drive, the 
WD Scorpio Blue, has a 3- 
Gbps SATA (serial-advanced- 
technology-attachment) in- 
terface and an 8-Mbyte RAM 
cache. The MSRP (manufac- 



turer's suggested retail price) 
is $249.99; a 750-Gbyte ver- 
sion, the WD7500KEVT, sells 
for $189.99. External USB 
(Universal Serial Bus)-inter- 
face variants are also avail- 
able. MSRPs for the 1 -Tbyte 
and 750-Gbyte version; 
the My Passport Essentic 
SE are $299.99 and 
$199.99, respectively. 4 
All these drives fea- " 
ture an atypical 5200- 
rpm speed versus the more 
common 5400 rpm— wheth- 
er for additional per-platter 
storage potential, to enhance 
the drives' power-consump- 
tion capabilities, or for other 
reasons. 

Speaking of platters, the 
company accomplished its 
achievement by bumping the 
total per-drive platter count to 
three versus the more typical 
one- and two-platter specifi- 




The 2.5-in., 1 -Tbyte WD 
Scorpio Blue hard-disk drive 
has a 3-Gbps SATA interface 
and an 8-Mbyte RAM cache 
(a). The 1 -Tbyte and 750- 
Gbyte versions of the My 
Passport Essential SE are 
external USB-interface ver- 
sions of the Scorpio Blue (b). 

cations. This augmentation in- 
creases drive height to 0.49 in. 
(1 2.5 mm), thereby making the 
drives unusable in some ultra- 



thin-system designs, which re- 
ly on the more usual 0.374-in. 
(9.5-mm) thickness. As such, 
it's unclear how much if any 
per-platter areal-density lead- 
ership Western Digital has over 
competitors, such as Seagate 
(www.seagate.com). 

Seagate is now promoting 
a 640-Gbyte, 2.5-in. hard-disk 
drive with an external USB in- 
terface. Presumably, the com- 
pany based the product on as- 
yet-unannounced, two-platter, 
single-drive technology, trans- 
lating to 320 Gbytes per plat- 
ter. Compare this data point 
to the 250- and 333-Gbyte/ 
platter specifications of West- 
ern Digital's latest offerings, 
and you can see how close 
the two companies are in this 
respect. 

-by Brian Dipert 
Western Digital Corp, 

www.wdc.com. 



ASIC DEMULTIPLEXES TO MULTIPLE DISPLAYS FROM ONE DISPLAYPORT SIGNAL 



HDMI (high-definition multimedia interface) and DVI 
(digital-video interface) transmit video data as continu- 
ous bit streams, whereas DisplayPort transmits the data 
in packets and allows for asymmetric two-way transfers. 
If your application is simply connecting a graphics chip to 
a display, packetizing creates a lot of overhead for little 
real benefit. If you are driving multiple displays, however, 
there are some advantages to all that extra work. Chip 
designers and mechanical engineers who have to multi- 
task need multiple displays. Both operating-system de- 
velopers and the graphics-system designers have made 
provisions for this requirement. The question is how to 
get the data to the right display. One approach has been 
to use an additional display-driver card per monitor in 
the computer chassis. Another is with an external splitter 
box. Both of these approaches can cost hundreds of dol- 
lars and consume 100W or so. Another alternative is to go 
to USB (Universal Serial Bus)-display links, but that ap- 
proach quickly runs into bandwidth problems. 

IDT (Integrated Device Technology) may have a bet- 
ter idea with the VMM (virtual-machine-monitor) 1300 
PanelPort ViewXpand chip. This device, powered by the 
DisplayPort cable at less than 1.5W, is basically a router 
for DisplayPort micropackets. The chip inspects incoming 



micropackets, sorts them based on the pixel addresses, 
modifies the address to correspond to the screen coordi- 
nates on the appropriate monitor, and routes each packet 
to that monitor. The chip works as a hub in a dongle, in 
which it can route packets to any of three output ports, or 
in a daisy-chain topology, in which you use only two out- 
puts, and you can string together as many chips and mon- 
itors as your graphics bandwidth allows. 

The chip can also function as a protocol converter, so, 
when it is in hub mode, you can drive legacy display in- 
terfaces on the chip outputs. The chip routes the Display- 
Port packets, so it requires no new driver software and is 
compatible with DisplayPort standards, including HDCP 
(high-bandwidth-digital-content protection) Version 1.3-a 
requirement for monitors that handle content-protected 
video. 

At initialization, the chip uses identification cycles to 
figure out what monitors it will be driving and to map the 
viewing window onto the various monitors' screen coor- 
dinates, thereby setting up the routing table. The VMM 
1300 is available for sampling, and production chips will 
become available this month. 

—by Ron Wilson 
Integrated Device Technology, www.idt.com. 



AUGUST 20, 2009 | EDN 13 



)ulse 



VOICES 

Asset InterTech Inc's Tim Dehne: 

seeking growth in 
embedded instrumentation 

Tim Dehne, until recently a longtime executive with National 
Instruments Inc, has joined the board of directors of Asset 
InterTech Inc, a supplier of boundary-scan and embed- 
ded-instrumentation tools. Over a career stretching more than 
21 years at Nl, Dehne led global marketing and R&D at the 
company, which reported $824 million in revenues in 2008. 
During his tenure at Nl, he held positions including vice presi- 
dent of strategic marketing and senior vice president of R&D. 
EDN recently spoke with Dehne. A portion of that interview fol- 
lows. You can read the full interview at www.tmworld.com. 



This move represents a 
major change for you. 

Yes, you could say that. 

I had been looking at a 
number of different options, 
but Asset InterTech presented 
a nice opportunity based on 
my experiences and relation- 
ship with Glenn [Woppman, 
Asset's chief executive officer 
and chairman]. It made sense 
to me, and I was happy to join 
the board. 

What do you see as the 
similarities and differences 
in the directions of the 
two companies? National 
Instruments started out 
as a test company, but, as 
it grew, it's gone in lots of 
different directions, includ- 
ing control and design. 

Growth potential is one 
of the things that got 
me excited when Glenn and 
I first started talking after I 
announced my departure from 
National Instruments. Asset's 
history is in boundary scan, 
which basically "niched out" as 
a market. Asset did very well 



and is one of the leaders, but 
the space didn't grow as much 
as Asset and the other play- 
ers in the marketplace hoped 
it would. But Asset is still fun- 
damentally a hardware/soft- 
ware play, and that [approach] 
is very similar to National 
Instruments'. 

But where the company is 
going is what got me excited. 
The semiconductor world is 
moving to many, many cores 
and even to multiple I P [intellec- 
tual-property] cores from multi- 
ple vendors. That world needs a 
kind of test strategy not only at 
the semiconductor level, where 
you figure out what's going on 
with the silicon and what may 
be causing some of the yield 
or performance issues, but 
also at the board level to moni- 
tor the interactions among 
all those different chips with 
all those multiple vendors' IR 
Addressing these challenges 
involves structural test, which 
is different from what National 
Instruments does, but it seems 
to be an area of growth and an 
exciting technology develop- 




ment. We feel that embedded 
instrumentation is an area in 
which the company can grow 
to quite a good size if we do 
things right. 

What are the prospects for 
mergers and acquisitions? 

I'm not saying what 
Asset's plan is, but, in 
the design space, mergers 
and acquisitions happen all the 
time. They're not as frequent 
in the test area, but, of course, 
they occur there, too. But the 
most important thing now with 
Asset is to get the company 
growing organically with these 
new initiatives with the proces- 
sor-controlled test and embed- 
ded instrumentation, so that's 
what we are going to focus on 
doing. 

Do you plan to form part- 
nerships with complemen- 
tary vendors? 

"Partnerships"-and I 
use that term loosely— 
typically fall into three cate- 
gories. There can be a sales/ 
distribution agreement, there 
can be just a marketing or 
message story, or there can 
be some in-depth joint devel- 
opment. The last type can be 
significant. Examples are the 
partnerships that Nl had with 
Analog Devices [regarding 
NTs LabView graphical-devel- 
opment module for Analog 
Devices' Blackfin processors] 



and Luminary Micro [regarding 
a LabView graphical-develop- 
ment module for ARM targets 
on a Luminary Micro evalu- 
ation board]. These partner- 
ships involve developers' sit- 
ting down and co-developing 
and creating something new 
in the marketplace. With joint- 
development efforts, generally 
there's money on the line; you 
are committing real resources, 
so you work harder to make 
those things work. 

What is your role as a 
board member-the tradi- 
tional board of directors' 
governance role? 

■I Certainly, anybody on the 
■J board has that role. But 
I'm a little bit different from the 
other board members, and I'm 
thankful to Glenn for recogniz- 
ing the ways he could leverage 
my experience. When I started 
at National Instruments, the 
company employed 100 peo- 
ple, and I went up the market- 
ing ranks for about a decade 
and then went into R&D for 
another decade. So given that 
experience base, Glenn and 
some of the other board mem- 
bers felt I could probably play 
a different role in addition to 
the corporate-governance role. 
I could also be a little bit more 
active in the marketing and 
R&D aspects, 
-interview conducted and 
edited by Rick Nelson 



14 EDN | AUGUST 20, 2009 



Special Advertising Section 




Rarely Asked Questions 



Some Chips Have Moving Parts! 



Q. Is it true that over the years 
electrical devices have evolved 
to where they have no moving 
parts at all? 

A» While it is true that any machinery 
becomes more reliable as the number 
of moving parts where friction can 
cause wear is reduced, there are actu- 
ally integrated circuits (ICs) which only 
work because of moving parts on the 
surface of the chip. 

These are known as Microelectromechanical 
Systems, or MEMS. They use standard IC 
process technology to make structures in 
metal, silicon and silica on the surface of 
a chip. Such structures may be designed 
to move and thus perform many useful 
functions. 

Moving parts of such chips flex, but do 
not usually bear on other surfaces, so 
friction is not often a problem. They are 
usually made of silicon, which has very 
low mechanical hysteresis with defor- 
mation, and therefore great resistance 
to fatigue. Silicon does not change its 
properties or suffer damage even when 
flexed many trillions of times. 

The first commercial MEMS devices with 
visibly moving parts were accelerome- 
ters. Electronic accelerometers once cost 
hundreds or thousands of dollars, today 
the least expensive cost only a dollar or 
two making it economical to use them 
in inexpensive gadgetry, air bag deploy- 
ment (their first major application), joy- 
sticks for computer games, shock protec- 
tion for disk drives and athletes ankles, 
keystone correction in projectors, orien- 
tation detection in hand-held monitors, 
and a thousand other uses. 



Traditional gyroscopes rotate, but it's 
quite possible to make a gyroscope that 
vibrates rather than rotating; and this 
can easily be done in a MEMS structure. 
MEMS gyroscopes are used wherever 
rotation is measured; their low cost 
enables hitherto unaffordable applica- 
tions such as optical image stabilization, 
safety controls in motor vehicles and 
short-range inertial navigation for GPS 
receivers when no satellite is visible. 

MEMS structures allow the manufacture 
of high quality microphones on an IC 
chip. These are smaller, more cost-effec- 
tive and reliable than any other micro- 
phone technology and are starting to 
replace the electret microphone in 
many applications. 

The linked articles describe all these 
chips with moving parts, and their many 
uses, in much more detail. 



To Learn More About 
MEMS Technologies 

http://designnews.hotims.com/23114-101 




Contributing Writer 
James Bryant has 
been a European 
Applications Manager 
with Analog Devices 
since 1982. He holds 
a degree in Physics 
and Philosophy from 
the University of Leeds. 
He is also C.Eng., Eur. 
Eng., MIEE, and an FBIS. 
In addition to his passion 
for engineering, James 
is a radio ham and holds 
the call sign G4CLF. 



Have a question 
involving a perplex- 
ing or unusual analog 
problem? Submit 
your question to: 
raq@reedbusiness.com 



For Analog Devices' 
Technical Support, 
Call 800-AnalogD 



SPONSORED BY 




ANALOG 
DEVICES 



AUGUST 20, 2009 | EDN 15 



BAKER'S BEST ■ 



BY BONNIE BAKER 



One circuit provides system 
resolution and 1 2-bit accuracy 

Handheld meters, data loggers, and automotive and moni- 
toring systems typically require a multiplexed system 
with the low-cost combination of high accuracy and 
high system resolution. A system that can handle this 
diversity requires a multiplexer, a gain cell, and an ADC. 
A feasible approach has a 10-channel PGA (program- 
mable-gain amplifier) teaming up with a medium-speed, 12-bit SAR 
(successive-approximation-register) ADC (Figure 1). The single-supply, 



10-channel PGA has a rail-to-rail I/O 
with a gain adjustment of 1 to 200 V/V. 
The PGA's low-noise performance of 
12 nV/A/Hz at 10 kHz is appropriate 
for a 12-bit system. 

The analog interface between these 
two devices includes an operational 
amplifier in a buffer configuration and 
an RC circuit. The 12-bit, capacitor- 
based SAR ADC has an inherent sam- 
ple/hold function and requires the RC 
circuit, which facilitates the charg- 
ing action of the ADC's input struc- 
ture. The calculated value of the PGA 
noise, referred to the output, is equal 
to the PGAs noise density at 10 kHz 
(12 nV/VHz) times the square root 
of the PGAs closed- loop bandwidth 
times the square root of tt/2. The mul- 
tiple of V(tt/2) accounts for the noise 
in the frequency region beyond the 
PGAs bandwidth. You then multiply 
this number by the gain of the PGA. 
The following equation uses a PGA 
gain of 1 6V/V: PGA rms . NO i se = 12 nV/ 
VTSxVOo MHzXtt/2)X16V/V= 
304 |xV rms. The ADC noise of 43 1 |jlV 
rms from this converter is well below 
1 LSB or 1.22 mV in this 5V system. 
The noise from the buffer amplifier, 
which is 39 jjlV rms, contributes little 
or no noise to this system. 



The combined noise of the PGA, 
op amp, and ADC is 529 u>V rms, 
which is still less than 1 LSB of the 
12-bit converter. You calculate this 

digital _ 
y sclk I/O i cs 



value using a root-sum-square equa- 
tion or the following equation: Noise 
referred to output = V ( PG A RMS , NOISE 2 

+ op amp RMS , NO isE 2 + ADC rms , NO ise 2 )- 
The equivalent 12-bit accuracy of 
this system when the PGA is in a gain 
of 16V/V is 0.432 LSB: Noise referred 
to outputX2 N /FSR (full-scale range), 
where N is 12 and FSR is 5 V/V. If you 
look at this system across the PGAs 
gain range of 1 to 200V/V, you find 
that the PGA dominates the noise- 
contribution portion in this circuit. 
Once the PGA gain exceeds approxi- 
mately 125 V/V, this system no longer 
matches the 12-bit-accuracy criteri- 
on. However, the system's referred- 
to- input LSB voltage size becomes 
smaller (Figure 2). The trade-off for 
a smaller LSB is a decrease in the sys- 
tem's effective number of bits. 

The system in Figure 1 provides 
an adequate gain range for the PGA 
when 12-bit accuracy is required and 
an equally adequate gain range when 
good system resolution is required. EDN 



CHO 

cm 

CH2 
CH3 
CH4 
CH5 
CH6 
CH7 
CH8 
CH9 





SPI 


MULTI- 




PLEXER 


PGA -f 







SCLK 




SDO 



Figure 1 This system uses a multiplexed PGA and an operational amplifier that 
drives a 1 2-bit converter. 



1 

EQUIVALENT 
12-BIT °-8 
LSB 

0.6 
0.4 




SYSTEM 

0.100 LSB ' 

REFERRED 
TO INPUT 

(mV) 



Figure 2 The system accuracy is better than 0.01 % with PGA gains of 1 to 1 25V/V. 
With PGA gains of 1 25 to 200V/V, the system accuracy is better than 0.02%. 



EDN | AUGUST 20, 2009 




NUMONYX® FORTE™ SERIAL FLASH MEMORY 

Product Family I Density Range I Voltage/Solution 



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:]:Other names and brands may be claimed as the property of others 



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innovative, memory, solutions. 



PAUL RAKO TECHNICAL EDITOR 



Rex 6000 PDA 



M 

\+\ Go to www.edn.com/pryingeyes 
for past Prying Eyes write-ups. 



Franklin Electronic Publishers introduced the Rex electronic orga- 
nizer at the 1997 Comdex show- The Rex was a Type Incompatible, 
3.4X2.1 X0.134n., 1.4-oz PCMCIA, or PC-Card. The company later 
introduced a version with 512 kbytes of memory. Xircom bought the 
Rex line in 1999 for $13.25 million. Intel acquired the Rex as part of 
its acquisition of Xircom, which was completed in March 2001. A month ear- 
lier, Xircom had introduced the Rex 6000, which Citizen Watch Company of 
Japan produced and marketed as the DataSlim-2. The organizer held phone 
numbers, a to-do list, an appointment calendar, a memo list, and several utili- 
ties, such as a calculator and some games. The Rex 6000 had 2 Mbytes of 
flash memory and 32 kbytes of RAM. It initially sold for $150. Intel canceled 
the project shortly after its acquisition of Xircom. 



Two 3V CR-201 6 lithium batter- 
ies with 90-mAhr capacity power 
the PDA. The operating system 
shows a low-battery icon when 
power decreases to 2.86V and 
emits a warning at 2.82V. 



The five hardware buttons connect 
through a six-circuit ribbon cable to 
a connector on the motherboard. 
The ribbon goes under the battery 
clip and snakes through a gap in 
front of the connector. 




Analog chips include an Epson 
SCI7661 charge-pump dc/dc 
converter to make a negative bias 
for the LCD. A Texas Instruments 
quad, 10-bit, 85k-sample/sec 
TLV1 544 ADC senses the 
touchscreen. Other analog chips 
include several linear regulators. 



The gray-scale, 240 X 1 20-pixel, 
2.6-in.-diagonal LCD has no back- 
light. The display connects to a rib- 
bon cable soldered to the mother- 
board. The row- and column-driver 
chips mount on the LCD glass. 




A piezoelectric actuator lies on 
top of the chips to provide alarm 
and beeping sounds. Plastic 
tape over the back of the case 
ensures that the actuator and 
the battery do not short out. 



The 4.3-MHz Rex 6000 CPU is 
a Toshiba microprocessor that is 
compatible with the Zilog Z80. 
A separate 32.768-kHz watch 
crystal provides the real-time 
clock, two Fujitsu 29DL1 64BD- 
90 chips provide flash memory, 
and the fourth digital chip is an 
LCD controller. 



A tab of metal forms a crude 
reset switch that users actu- 
ate through a small hole in 
the back of the case. 





The resistive touchscreen connects 
to the motherboard by a small, five- 
pin ribbon connector with only four 
used circuits. Icons on the bottom of 
the touchscreen provide seven soft 
buttons for the four primary PDA func- 
tions as well as a network download, 
a calculator, and a clock function. 



A 



The PCMCIA form factor of the Rex 
6000 allows you to synchronize it by 
sliding it into the PC-Card slot of a 
laptop computer. Alternative offerings 
are RS-232 and USB docks. The 
Rex does not use the PCMCIA bus 
to communicate; it uses the UART 
channel that is part of the PCMCIA 
standard. The USB cradle also emu- 
lates a serial UART. 



18 EDN 



AUGUST 20, 2009 



Agilent 

Tektronix 

LeCroy 

Rohde & Schwarz 

National Instruments 

Anritsu 

Keithley 

Yokogawa 

Tabor 

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any designers are familiar with open- 
source software, such as Linux, in which 
the source code is available to all How- 
ever, fewer are familiar with organiza- 
tions offering open-source hardware. 
These organizations release free infor- 
mation, including schematics, BOM 
(bill-of-materials) information, and PCB (printed-circuit- 
board) -layout data, covering the overall hardware design. 
Designers with this information can build or add to a freely 
available design. In many cases, open-source software sup- 
ports the original design, providing additional advantages. 
Some aspects of open-source hardware go beyond the shar- 
ing of the design itself. These aspects can save time and 



TAKE 



BASING YOUR PRODUCT 
ON A REFERENCE DESIGN 
OR DEMO BOARD CAN 
SPEED TIME TO MARKET. 




ADVANTAGE of 

OPEN-SOURCE 

HARDWARE 

BY GERALD COLEY • TEXAS INSTRUMENTS 

money for not only hardware developers but also PCB designers and fabrica- 
tors, contract manufacturers, and even software developers. 

You can license open-source projects from organizations such as Creative 
Commons, which offers the Attribution- Share Alike licensing program. Cre- 
ative Commons stipulates that a user must attribute the open-source work 
in the manner that the original designer specifies but not in a way that 
indicates that the original designer endorses the user's work. Likewise, if 
users provide that work as open-source hardware, releasing it back to the 
community for access by others, then they must provide that work un- 
der the same Attribution- Share Alike licensing (Reference 1). Other 
licenses, such as the modified BSD (Berkeley Software Distribution), 
allow for the assignment of copyrights and provide certain restrictions to the 
use of the hardware design (Reference 2). Be sure to read the license that comes 
with an open-source design before using it. If users are considering creating their own 
open-source design, they need to figure out which license works best for them. 

You must consider several factors, including power, cost, and documentation, 
when selecting an open- source -hardware platform. Make sure that the license pro- 
vides comprehensive, high-quality documentation, including schematics, BOM, 
and PCB data. The documentation must have the support of a large community of 
users, and it must align with your product's needs. 

Some popular open-source-hardware platforms include Gumstix, Arduino, and 




Figure 1 The BeagleBoard (bottom 
left) and the Overo expansion boards 
from Gumstix (top right) are examples 

of available open-source hardware. 



20 EDN | AUGUST 20, 2009 



the BeagleBoard (Figure 1)- Gumstix 
uses an open-source-hardware model in 
posting the schematics and layouts of all 
the company's Overo- series expansion 
boards- Arduino employs a microcon- 
troller as its hardware and has its own 
community of designers and hobbyists. 
Arduino 's schematics come in Eagle and 
PDF (portable-document format), and 
the PCB information is in Eagle- The 
Creative Commons license covers li- 
censing for the platform, and extensive 
libraries and software support are avail- 
able. The BeagleBoard uses a Texas In- 
struments OMAP3530 (Reference 3). A 
large, Linux-based open-source-software 
community supports the BeagleBoard, 
and schematics are available in PDF and 
Cadence's OrCAD. The BOM is in Mi- 
crosoft Excel, and PCB information is in 
Cadence's Allegro and Gerber files. 

Due to its high technology level, the 
BeagleBoard presents some interesting 
challenges for users of the OMAP3530 
device, but you can overcome the chal- 
lenges by taking advantage of open-source 
hardware. The 515-pin OMAP3530 de- 
vice uses 0.4-mm-pitch balls and supports 
POP (package-on-package) technology, 
which mounts the memory devices on 
top of the processor. This technology can 
create challenges, including schematic 
design and PCB layout, fabrication, and 
assembly. 

STREAMLINE THE DESIGN 

You can reduce risk by basing designs 



AT A GLANCE 

□ Open-source hardware offers an 
advanced start on your design. 



□ Open-source software comple- 
ments open-source hardware. 



□ Open-source hardware prepares 
your PCB (printed-circuit-board)- 
fabrication and -assembly houses 
for high-volume production. 



El You may want to share your 
improvements by making them 
open-source additions, as well. 



on open-source hardware and taking ad- 
vantage of a proven design that has op- 
erated successfully in the past. Thus, you 
can work from a known starting point 
and easily see what's there, what's miss- 
ing, and what is unnecessary because 
you have access to both the finished 
hardware and the complete design. It 
also saves development time. Having 
access to the complete BOM with part 
numbers enables you to quickly adjust 
it. You can look for places to substitute 
your favorite capacitors and resistors 
and get access to the information on 
any unfamiliar parts. As long as the cost 
and specification of the part in use are 
on target, you should have no problem 
with using it. If you are unfamiliar with 
a part, however, you can improve the 
design by selecting a part better suited 
for your design's needs. 

For instance, the OrCAD schematic 



tool lets you quickly and easily add de- 
vices to the schematic. It takes advan- 
tage of the unused pins on the processor 
and even replaces devices on the open- 
source-hardware design. Creating com- 
ponents can take a lot of effort, so using 
those on the schematic saves time and 
reduces the risk of errors. Alternatively, 
you can use a PDF version of the hard- 
ware schematic to create schematics 
with your favorite tool. This approach 
can be an advantage because re-creat- 
ing the design gives you more in-depth 
knowledge of how the design works and 
where problems might arise. The Bea- 
gle-Board's documentation includes a 
fairly detailed reference manual that can 
answer questions about the design. Us- 
ers also can access the support commu- 
nity for additional help. Don't be afraid 
to ask for help; open-source hardware is 
all about learning from other people's 
mistakes. 

Using the Allegro file format is the 
shortest path to completing a layout. 
You can import footprints from this 
database to your library, saving a sig- 
nificant amount of time. Because you 
already have a working board, you can 
use these footprints with confidence. If 
your board or prototype is similar to the 
BeagleBoard design and you need to add 
several components, you can simply do 
an ECO (engineering-change order), 
meaning that you use the current layout 
and add only key components so that 
you don't disturb the basic layout. 



PSB 



PASTE 



PASTE 



SMT 



REFLOW 



PASTE 



PASTE 



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REFLOW 




POP MEMORY 




SHORTS 



AUTOMATED 

OPTICAL 
INSPECTION VISUAL 



MANUAL 
ASSEMBLY 




Figure 2 A board-assembly flow begins with a PCB and ends with a visual inspection of the work. 



AUGUST 20, 2009 | EDN 21 



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Allegro has a useful free viewer for 
reading design files- This viewer exposes 
the layer stacks and all of the PCB in- 
formation, which provides a guide when 
designing the board on your own tool- 
In this way, you can see board routing, 
trace widths, and trace spacing. Anoth- 
er option is to convert the database to 
other tools using available and third- 
party tools- You must be careful not to 
lose design information when using this 
method, however. You can use Gerber 
files to double-check the information 
and as learning tools. These files are not 
user-friendly but can be helpful in creat- 
ing your layout. The OMAP3530 device 
also includes a design-guideline applica- 
tion note to assist in layout. 

GETTING UP TO SPEED 

Many new devices use more advanced 
technology, including blind vias, stacked 
vias, narrow traces, and via-in-pad tech- 
nology, than the technology from your 
PCB supplier. Although the suppliers 
may be able to handle these advances, 
they may not have previously needed to 
provide it. If a user is comfortable with 
a PCB vendor because it's a known en- 
tity, though, it may be worth getting the 
vendor to the point at which it can han- 
dle the new needs. However, depending 
on your requirements and confidence 
level, you may be better off going to a 
vendor that has experience with the 
type of board you are working on. Using 
the available CAD data, the PCB ven- 
dor can get up to speed and prototype an 
initial board so that you are confident 
that the company can build it. If the 
vendor needs to adjust certain aspects 
of the design, it can modify the Gerber 
files for its normal processes. 

Expected yield determines the cost of 
building boards. Building the board as it 
is gives vendors insight into yield. They 
can then prevent any problems that arise 
when building the new board. For ex- 
ample, if they have problems with via- 

FOR MORE INFORMATION 



Arduino 

www.arduino.ee 

BeagleBoard 

www.beagleboard.org 

Berkeley Software 
Distribution 

www.bsd.org 

Cadence 

www.cadence.com 



Creative Commons 

http://creative 
comnnons.org 

Gumstix 

www.gumstix.com 

Realtime Technology 

www.realtimedsp. 
com.cn 

Texas Instruments 

www.ti.com 



in-pad technology, you should avoid us- 
ing it in your design. The assembly house 
also may encounter problems in assem- 
bling your board. You can get the as- 
sembly house up to speed by using open- 
source hardware. Alternatively, you can 
use your own assembly house, if applica- 
ble, to build the entire board or a subset 
of the board. 

In many cases, it can take several pass- 
es to work out the wrinkles in assembly. 
By using the open- source-hardware de- 
sign and assembling as many boards as 
you need, you can solve any problems. It 
is better to work on these problems with 
a proven and tested board instead of 
your first prototype, on which it may be 
more difficult to find issues. The Beagle- 
Board also has a POP assembly guide- 
line (Reference 4)- As in the case of the 
PCB-layout guidelines, it also uses the 
BeagleBoard design (Figure 2). 

There is always pressure to complete 
the hardware so that you can start the 
software verification. Basing your design 
on open-source hardware allows an early 
start on software development by us- 
ing the available open-source-hardware 
boards to begin the development effort. 
Because open-source hardware typically 
also has a software component, the soft- 
ware team can jump-start its efforts by 
using the available code. This approach 
allows the hardware team to make sure 
it gets the design right on the first pass. 

In addition, the software team may 
discover that it needs to change the 
hardware to improve performance or to 
add a feature. Making a lot of changes to 
the basic design quickly diminishes this 
advantage, however. Make sure that the 
basic design components, including the 
memory, power management, and key 
debugging peripherals, remain the same. 
Additionally, pay careful attention to 
the available software to see whether it 
offers the necessary applications or func- 
tions. Although software developers can 
write the software themselves, they typi- 
cally would rather use the already- avail- 
able software. 

In summary, using the OrCAD sche- 
matic design tool or implementing your 
own version using open-source hard- 
ware reduces risk and saves develop- 
ment time. You then need to focus only 
on what to add or remove from the basic 
design to complete the final design. You 
can use the Allegro CAD files or Ger- 
ber files to provide a map with which 



you can reuse whatever works correctly- 
Next, select a PCB vendor to accurate- 
ly build the technology and save time 
and cost for the prototype run. This ap- 
proach increases the chance of first-pass 
success and reduces the number of cost- 
ly problems that would require re-spins 
and debugging during the prototype 
phase- Then, focus on getting the as- 
sembly house to build the open-source- 
hardware board- Now that the hardware 
prototypes are ready to run software and 
you have tested the software from the 
open-source-hardware board, there is a 
much higher chance of success. 

GIVING BACK 

Open-source hardware is about shar- 
ing work with others for everyone's ben- 
efit. It is acceptable if you never meant 
for the product to be open. You need 
not make your changes available to the 
community. In the spirit of open-source 
hardware, however, it's beneficial for 
all parties to provide upgrades and ad- 
ditions to the community whenever 
possible so that the next user can add 



other enhancements. When you add a 
function to hardware, it affects the soft- 
ware, which adds a reason to enhance 
and improve the overall performance 
of the software to take advantage of the 
new feature. As developers design prod- 
ucts based on this design, another com- 
munity member has perhaps added the 
function with the already-completed 
software work to help make it a better 
product. 

In the future, more companies will 
offer varying levels of open-source hard- 
ware to their customers and the commu- 
nity at large, creating an environment in 
which developers spend most of their ef- 
forts on improving rather than re-creat- 
ing the design. The community can ben- 
efit from this common goal, so keep your 



EE Go to www.edn.com/090820df 
and click on Feedback Loop to post 
a comment on this article. 

EE For more technical articles, go to 
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eyes open for the next entrant in the 
world of open-source hardware.EDN 

REFERENCES 

\M "License Your Work," Creative Com- 
mons, http://creativecommons.org/ 
choose. 

9 Nelson, Russell, "The BSD License," 
Berkeley Software Distribution, Oct 31 , 
2006, www.opensource.org/licenses/ 
bsd-license.php. 

3 "OMAP3530 Applications Proces- 
sor," Texas Instruments, www.ti.com/ 
omap3530-oshw. 

J Gutierrez, Keith, and Gerald Coley 
"PCB Assembly Guidelines for 0.4mm 
Package-On-Package (PoP) Packages, 
Part II," Texas Instruments, April 2008, 
www.ti.com/litv/pdf/spraav2. 

AUTHOR'S BIOGRAPHY 

Gerald Coley is a systems engineer at Tex- 
as Instruments, where he has worked for 
13 years. Coley focuses on the OMAP 
processors and has designed more than 20 
development boards, including the Beagle- 
Board. 




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HIGH-RESOLUTION VIDEO-STREAMING SUPPORT IS SUPPOSEDLY 
A KEY JUSTIFICATION FOR 802. 1 1 N VERSUS ITS 802. 1 1 A AND 802. 1 1 B/G 
PREDECESSORS. SO WHY DOESN'T IT DELIVER ON ITS PROMISES? 



TRANSPORTING HIGH-DEF 

VIDEO BROADCASTS: 

BY BRIAN DIPERT • SENIOR TECHNICAL EDITOR 

ARE WIRELESS 

NETWORKS UP TO 

THE TASK? 

It all seemed so simple, at least at first glance. I have a Microsoft Windows Vista 
Ultimate-based notebook PC, a Dell XPS M1330- I have two Xbox 360s, one 
in the living room and the other in the bedroom (Figure 1)* I have reasonably 
solid over-the-air television reception at my home office (Reference 1). I'm 
not using the XPS M1330 as a work PC because I've migrated to mostly Apple 
systems — in some cases running Windows XP virtualized- So I decided to con- 
vert the Dell PC to a PVR (personal video recorder), leveraging its built-in 
Media Center capabilities and streaming both live television and recordings to 
the game consoles acting as Media Center Extenders. 



I don't have Category 5 Ethernet cable running to 
any of the three LAN nodes, so I at first tried con- 
necting them to the router and each other using Net- 
gear's XAV101 HomePlug AV power-line-network- 
ing adapters (Figure 2). This arrangement worked 
fairly well, especially once I stuck ac-noise filters on 
the refrigerator and furnace fans' power connections 
(see sidebar "Revisiting power line"). Erratic band- 
width still resulted in more frequent glitches in the 
playback than I preferred, sometimes but not always 
when ceiling or window fans or other potential pow- 
er-grid noise sources were operating. With annoying 
regularity, one or both Extenders would also refuse 
to connect to the laptop until I power-cycled one, 
some, or all of the HomePlug AV adapters in use. 

Finally, one day I threw up my hands in frustra- 
tion, determined to find some alternative way — 
other than crawling under the house and punching 
holes in floors to string Category 5 cable — of inter- 
connecting these nodes. Ideally, I hoped to com- 
pletely dispense with power-line networking in my 



LAN. (I was also using HomePlug AV to tether an 
Insteon home- automation controller to the router, 
thereby making the controller LAN- and WAN- 
accessible.) The XPS Ml 330 embeds a Broadcom 
802.1 In transceiver, my Apple router is 802.1 ln-ca- 
pable, and 802.1 ln-based bridges and switches claim 
to allow legacy devices to leverage the IEEE's latest 
and greatest wireless-networking technology. Could 
802.1 In be my mentor to Media Center nirvana? 

THE DEVIL'S IN THE DETAILS 

Before diving into the sordid step-by-step story, 
here is some important background information. 
First, the Broadcom Wi-Fi IC in the XPS M1330 is a 
BCM4328, which Dell refers to as the Wireless 1505 
Module, and, in conjunction with its mated MIMO 
(multiple-input/multiple-output) antenna array, it is 
dual-stream- and dual-band-capable (Reference 2). 
Conversely, the XPS M1330's wired-Ethernet trans- 
ceiver, a Broadcom 59XX-series IC, is not GbE (giga- 
bit-Ethernet) -cognizant; it supports only 10- and 



AUGUST 20, 2009 | EDN 25 



100-Mbps Ethernet. The XPS M1330, 
which is in the living room and less than 
25 feet away from the same-room router, 
sources video streams whose parameters 
are also critical to this project's outcome. 
MPEG- 2 -based Media Center serves files 
that are on average larger and, therefore, 
have higher playback bit rates than those 
that more modern video codecs, such as 
MPEG-4 and VC-1, create. Microsoft of- 
fers four quality-versus-bit-rate settings, 
but they apply only to analog recordings. 

With ATSC (Advanced Television 
Systems Committee) sources, Media 
Center does no re-encoding and other- 
wise does not alter the incoming MPEG- 
2 video and Dolby Digital audio data; 
Microsoft simply embeds it as is within 
the proprietary DVR-MS "wrapper" for- 
mat. You should assume, therefore, that 
each live-TV or recording audio-plus- 
video stream you want to route around 
your network is worst-case roughly 20 
Mbps, accounting for DVR-MS over- 
head beyond the 19.2-Mbps ATSC bit 
rate. Media Center employs UDP (User 
Datagram Protocol) as the transport pro- 
tocol, along with RTP (Real-Time Trans- 
port Protocol) for multimedia streaming 
and RTSP (Real-Time Streaming Proto- 
col) for control functions. 

In addition to Xbox 360s, the network 
nodes in my living room — 12 feet away 
from the router — and in my bedroom 
also both include a Sony PlayStation 3. 
An Apple TV is in the living room, and 
the bedroom contains both a Roku Net- 
flix Player and SoundBridge. I had been 
using a 10/100-Mbps Ethernet switch at 
each node to share the HomePlug AV 
connection among multiple pieces of 
gear because the HomePlug AV adapters 
aren't GbE-capable. (I have rarely had 



AT A GLANCE 

□ Power-line networking's long- 
standing shortcomings encour- 
aged me to assess the validity of 
802.1 1 n's performance promises. 



□ Windows Media Center's 
reliance on MPEG-2 results in 
substantially higher bit rates than 
necessary with more modern video 
codecs. 



□ A single-channel, 5-GHz 
802.1 1 n topology couldn't deliver 
sufficient sustained bandwidth, due 
in part to my intra-LAN streaming 
scheme. 



□ A dual-channel approach 
improved the wireless network's 
peak speeds but also resulted in 
mysterious packet-dropping glitches. 



□ Gigle Semiconductor's 
Mediaxtream power-line-networking 
technology doesn't yet deliver on 
its GbE (gigabit-Ethernet) claims, at 
least in my setup. 



more than one piece of gear simultane- 
ously active at each node.) 

Although all of these client devices 
support at least one IEEE 802.11 flavor, I 
wanted to simplify and optimize the per- 




formance of my migration from Home- 
Plug AV to 802.1 In. I therefore planned 
to swap out each of the 10/100-Mbit 
wired-Ethernet switches for D-Link's 
DAP- 1522, which combines a four-port 
GbE-capable switch and a dual-band, 
dual-stream 802.1 In subsystem. The In- 
steon controller's single -client network 
node would require the use of only Link- 
sys' simpler WGA600N or WET610N 
bridge devices. 

BAND, ENCRYPTION CHOICES 

A bit of upfront research fortunately 
saved me some later hassles. An online 
review of the D-Link DAP- 1522 re- 
vealed that the unit had subpar perfor- 
mance in 802.11n's 2.4-GHz band versus 
the 5 -GHz alternative and that it per- 
formed worse with WEP (Wired Equiv- 
alent Privacy) and WPA (Wireless Pro- 
tected Access )-plus-TKIP (Temporary 
Key Integrity Protocol) encryption than 
with the more modern WPA/AES (Ad- 
vanced Encryption Standard) combina- 
tion (Reference 3). My Apple 802.1 In- 
cognizant router also supports bonding 
together two wireless channels to boost 
the resultant bandwidth capability on- 
ly in the 5 -GHz ISM (industrial/scien- 
tific/medical) band. I was motivated to 





rl 



Figure 1 By connecting a 
Windows Vista Ultimate- 
based Dell notebook PC 
(a) through Apple's Airport 
Extreme N router (b) to 
Microsoft's Xbox 360 (c) 
and Linksys' DMA2100 
Media Center Extender (d), 
I had hoped to be able to 
view high-quality live and pre- 
recorded ATSC broadcasts. 



26 EDN | AUGUST 20, 2009 



lift the high-performance section of my 
Wi-Fi LAN above the already-cluttered 
2.4-GHz spectrum that microwave ov- 
ens, wireless-surround-sound-speaker- 
transmitter/receiver combos, neighbors' 



access-point signals, and other broad- 
casters populate- Also, in my diminutive 
open-air geodesic dome, the 2.4- versus 
5-GHz-range discrepancy was not a prac- 
tical concern. 



The 5 -GHz ISM band is compara- 
tively crystal-clear in my rural locale. I 
therefore bound the Dell XPS M1330- 
to-router-to-D-Link DAP- 1522 chain 
by means of a WPA-plus-AES-encrypt- 



REVISITING POWER LINE 



I have so far been unable to dispense with HomePlug AV 
in my LAN, so I've spent some time determining whether 
I could improve the technology's robustness. In a sense, 
the power-line approach has an inherent advantage: The 
adapters can directly transfer data between them over 
the power grid with minimal router interaction. However, 
surge protectors and noise filters are equal parts curses 
and blessings for power-line networking. You can't plug an 
Ethernet-to-power- line adapter into them because the fil- 
ter circuitry siphons off the networking data stream that's 
multiplexed on the ac-waveform carrier signal. Their omis- 
sion from power-grid noise sources is equally debilitating 
to the power- line network, however. 

Some signal attenuators are fairly obvious, notably 
motor-based products, such as stand-alone fans, heat- 
ers, air conditioners, refrigerators, vacuum cleaners, hair 
dryers, and the like. Other more obscure noise sources 
include the switching power supplies in ac/dc converters 
and battery chargers. Companies such as Cal-Lab sell spe- 
cialized hardware that combines an unfiltered outlet for 
the power-line-networking adapter and a filtered connec- 
tion, which also protects against lightning and other power 
surges, for noise-generating gear (Figure A). Similarly, 
Intellon recently sent me two PowerNet 200 HomePlug AV 
adapters that Monster Cable sells; the adapters integrate 
two filtered and protected power outlets. 

Gigle Semiconductor recently partnered with Belkin 



to unveil Belkin's F5D4076 gigabit power-line-network- 
ing adapters, which Gigle based on its GGL541 IC. 
The GGL541 supports both HomePlug AV, which oper- 
ates in the 2- to 28-MHz band, and Gigle's proprietary 
Mediaxtream technology, which uses the 50- to 300- 
MHz band. Like 5-GHz Wi-Fi versus 2.4-GHz 802.11, 
Mediaxtream's higher frequency delivers potentially 
higher performance. Indicative of this promise, the 
F5D4076 includes a 1-GbE (gigabit-Ethernet) transceiver, 
whereas consumer HomePlug AV adapters belie their 
"200-Mbps" marketing claims by embedding only 10/100- 
Mbps PHY (physical-layer) interfaces. 

However, again as with 5-GHz versus 2.4-GHz wire- 
less, Mediaxtream has notably shorter usable range 
than does HomePlug AV. The initial production firmware 
in the Belkin adapters selects either HomePlug AV or 
Mediaxtream mode, depending on the power-grid char- 
acteristics that the ICs' embedded DSPs determine at 
power-up. As you can see from the Network Performance 
Tuner plot, the adapters have selected HomePlug AV 
mode in my setup. In fact, they run slightly slower than 
my Netgear HomePlug AV-dedicated hardware, even at a 
two-node deficit. Gigle is working on firmware improve- 
ments, both to increase the number of supported nodes 
and to bond the HomePlug AV and Mediaxtream channels 
together rather than using a more elementary either-not- 
both approach. 




(b) 



Figure A Cal-Lab's adapters filter out signal-attenuating noise sources and provide 
power-line adapters with direct access to the power grid (a). Belkin's gigabit power- 
networking adapters (b), which employ Gigle Semiconductor's ICs, forecast higher- 
HomePlug AV speeds that aren't yet a reality in my setup (c). 



line- 
than- 



AUGUST 20, 2009 | EDN 27 






(b) 

Figure 2 Netgear's HomePlug AV adapters (a) were the initial means by which I connected various network nodes. Power-line 
networking's unreliability encouraged me to evaluate the 802.1 1 n wireless alternative, enabled by D-Link's integrated switch plus 
access point (b), and two generations' worth of Linksys single-client bridges (c and d). 



Network Tuner 



Network Tuner 



Network Performance Monitor 



Network Performance Monitor 



Try the following while watching this 
■ Reduce obstructions between the c< 
- Reposition the Extender or wireless 



Try the following while watching this display: 

• Reduce obstructions between the computer and the Extendi 

• Reposition the Extender or wireless access point 



(a) (b) 

Figure 3 A HomePlug AV-only topology might be somewhat flaky (a), but it delivers faster streaming video than a single-channel, 
bonded 802.1 1 n alternative (b). 



ed 802.1 In wireless spur running on 
Channel 149— that is, 5.745 GHz. I also 
tried other 5-GHz-band channels dur- 
ing later debugging. Initial streamings 
attempt results were horrible: Windows 
Media Center's Network Performance 
Tuner utility measured best-case speeds 
of less than 8 Mbps. Nothing I tried im- 
proved the situation until I noticed that 
the laptop's Broadcom- sourced Win- 
dows Vista-driver suite carried a publi- 
cation date of December 2006. Dell was 
still shipping it in the system that I had 
purchased in July 2008 (Reference 4)! 

A visit to Dell's support Web site un- 
earthed a slightly newer driver dated 
October 2007 available for download- 
ing. At press time, Dell had made avail- 
able no newer version. Installing the 
200 7 -dated driver notably improved the 



average speed of the wireless link but 
still not to a level at which it would re- 
liably sustain streaming of a high-defi- 
nition recording from the laptop to the 
game console (Figure 3). The Network 
Performance Tuner generates plots that 
define 22 Mbps as the requisite HDTV 
(high-definition-television)-bandwidth 
threshold and 8 Mbps as the accept- 
able-for-TV bandwidth. My 802.1 In 
network's bandwidth capability also 
woefully undershot the 150-Mbps, sin- 
gle-stream and 300-Mbps, dual-stream 
claims of the technology's backers. 

Pondering the problem uncovered a 
possible partial explanation, which sev- 
eral Wi-Fi-silicon-vendor representa- 
tives later confirmed. If my DSL (digi- 
tal-subscriber-line) connection were 
capable of 20-Mbps sustained speeds 



(it isn't), and if I were watching a 20- 
Mbps video from the Internet (I can't), 
the incoming data would enter the LAN 
through the router's wired-Ethernet 
WAN port, and it would then stream to 
the Xbox 360 over Wi-Fi. However, my 
video-streaming setup was intra-LAN 
in nature, and I was therefore using one 
Wi-Fi channel for two simultaneously 
transmitting, 20-Mbps data streams: one 
from the laptop to the router and anoth- 
er from the router to the game console. 
Even though that 802.1 In channel had 
a 40-MHz-wide bonded-spectrum foot- 
print, it was still insufficient for shoul- 
dering the entire bit load. Temporar- 
ily disabling the XPS M1330's 802.1 In 
transceiver and instead connecting its 
Ethernet port to a Linksys WGA600N 
bridge yielded no improvement and 



28 EDN | AUGUST 20, 2009 





Network Tuner 



Network Performance Monitor 



Try the following while watching this display: 

• Reduce obstructions between the computer and the Extendei 

• Reposition the Extender or wireless access point 



Network Tuner 



Network Performance Monitor 



Try the following while watching this display: 

• Reduce obstructions between the computer and the Extern 

* Reposition the Extender or wireless access point 




(f) (g) 

Figure 4 The Apple router's lack of simultaneous dual-band support necessitates the inclusion of an 802.1 1 g access point for legacy 
LAN clients (a). Netgear's WNHDE1 1 1 created a second 5-GHz bonded 802.1 1 n channel (b), and I also used Apple's Airport 
Express N access point during debugging (c). Regardless of their frequency bands, the simultaneous operation of two 802.1 1 n sig- 
nals resulted in quality-degrading packet-loss glitches (d), which did not occur when part of the source-to-destination span relied on 
HomePlug AV (e) or Category 5e wired Ethernet (f). Diagnostics reports point to the router's switch as the culprit (g). 



proved that the laptop's wireless subsys- 
tem wasn't the weak link. 

DUAL CHAN N E LS = G LITCH ES 

Apple's latest routers and router-plus- 
hard-disk-drive products, Time Capsules, 
can single-handedly support simultane- 
ous 2.4- and 5 -GHz wireless networks, 



but my second-generation Airport Ex- 
treme N router is single-band, operating 
at either 2.4 or 5 GHz but not both at 
once. I had therefore already attached a 
WEP-encrypted Belkin F5D7130 access 
point to it for use with legacy 802.1 lg de- 
vices (Figure 4). Given the initial subpar 
results for single-channel 802.1 In, I fur- 



ther expanded my access-point topology 
with Netgear's 5-GHz-only WNHDE1 1 1 
device, thereby creating an additional 
802.1 In bonded beacon. This second 
signal, on 5.18-GHz Channel 36, does 
not overlap and is spectrally as far away 
as possible from the Apple router's 5.745- 
GHz Channel 149 signal. 



AUGUST 20, 2009 | EDN 29 



My initial approach involved 
streaming from the Dell laptop to the 
WNHDE111, from there to the router 
over Category 5e cable, and from the 
router to the DAP4522 over the router's 
built-in 802.1 In facilities. Although the 
average bandwidth of the dual-channel, 
5 -GHz approach was notably higher than 
with its single-channel predecessor, as- 
yet-unseen glitches randomly emerged. 
From the Network Performance Tuner 
plot, you can see how significantly they 
impeded bandwidth; they were also as 
much as 5 seconds wide, and they there- 
fore created egregious degradations in 
image and sound quality. 

I ruled out ambient interference as 
their cause by shutting off every other 
potential wireless beacon regardless of 
its transmitting frequency. I followed 
with an intensive sweep of the ISM 
spectrum to confirm an absence of noise 
from neighbors' electronics. I tried out a 
variety of 5 -GHz bonded-channel com- 
binations to confirm noninteraction 
between them, and I also reversed the 
datapath through the network, disabled 
SSID (service-set-identifier) broadcasts, 
attempted streaming between 5- and 
2.4-GHz 802.1 In variants, and even 
shut off the router's Wi-Fi system and 
instead relied on external access points. 

As before, I tried disabling the lap- 
top's Wi-Fi transceiver, instead us- 
ing the WGA600N bridge adapter. To 
rule out the DAP- 15 22, I also streamed 
to a Linksys DMA21 00 Media Cen- 
ter Extender, which contains a built-in 
802.1 In subsystem. Nothing helped. 
Time and again, I encountered glitches 
only when I was streaming data through 
the Apple router's internal switch be- 
tween two internal or external 802.11 
access points. Conversely, the glitches 
disappeared when the laptop-to-console 
span consisted of an 802.1 ln-plus-Cat- 
egory 5 or 802.1 ln-plus-HomePlug AV 
hybrid combination. This hybrid topol- 
ogy represents my current workaround. 

Neither Apple's Airport Extreme N 
router nor its Airport Express N access 
point, which I also used in debugging, 
provided the statistical reporting nec- 
essary to determine which part of the 
LAN chain was generating the glitches. 
Fortunately, I had access both to diag- 
nostics utilities for the laptop and to sta- 
tus screens on the WNHDE111 access 
point, which revealed that the wireless 



EE See the "Transporting high-def video 
broadcasts" posts at www.edn.com/ 
briansbrain for supplemental information 
on this article's topics. 

EE Go to www.edn.com/090820cs 
and click on Feedback Loop to post 
a comment on this article. 

EE For more technical articles, go to 
www.edn.com/features. 



portions of the topology were robust. 
Conversely, they bolstered my belief 
that the packet drops were occurring 
within the router's switch subsystem. 
Unfortunately, my attempts to contact 
Apple bore no fruit, and a recently re- 
leased router firmware update did not 
improve performance. Key semiconduc- 
tor suppliers to the Airport Extreme N 
design, Atheros and Broadcom, have 
also not commented on a possible root 
cause, perhaps so that they won't anger 
their customer. 

THE SAGA CONTINUES 

As time and personal-network band- 
width allow, I'll be replacing the Airport 
Extreme N router with other potential 
LAN -controller candidates: Apple's sec- 
ond-generation Time Capsule, which 
the company based on a third-generation 
router design; D-Link's DIR-825; Linksys' 
WRT600N; and Netgear's WNDR3300, 
WNR3500, and WNDR3700. All of 
these routers, except for the WNR3 5 00, 
can operate simultaneously at 2.4 and 5 
GHz, enabling me to retire the Belkin 
F5D7130 802.1 lg access point. 

Ordinarily, the Apple Time Capsule 
would be the only feasible alternative 
router candidate because I rely on Ap- 
ple's Mac OS 10.5 Time Machine fea- 
ture for system backup — historically, to 
an external hard-disk drive that I teth- 
ered to the Airport Extreme N router 
over USB (Universal Serial Bus). How- 
ever, I've recently moved my backups 
to a Netgear/Infrant ReadyNAS NV+ 
network- storage device, which supports 
Time Machine protocols through a re- 
cent firmware update (Reference 5). I 
hope that at least one of these alterna- 
tive routers' switches exhibits no baf- 
fling dropped-packet glitches between 
two 802.1 In transceivers' channels. 
And, if single-channel 802.1 In capa- 
bilities end up being sufficient, perhaps I 



can retire the WNHDE1 1 1 802.1 In ac- 
cess point, too.EDN 



REFERENCES 

9 Dipert, Brian, "Thin air: ATSC recep- 
tion isn't always easy," EDA/, May 1 4, 
2009, pg 20, www.edn.com/article/ 
CA6656302. 

3 Dipert, Brian, "802.1 1 n: a complicat- 
ed spec to be is about to become even 
more messy," EDA/, April 1 5, 2009, 
www.edn.com/blog/400000040/ 
post/1 970043397.html. 
3 Higgins, Tim, "D-Link DAP-1 522 
Review: Dual-band Draft 1 1 n for the 
Masses?" SmallNetBuilder, June 2, 

2008, www.smallnetbuilder.com/ 
content/view/30455/96. 

9 Dipert, Brian, "CES: IEEE 802.1 1 n: 
the vendor-neutering of a once-promis- 
ing standard," EDA/, Jan 8, 2007, www. 
edn.com/article/CA64051 95. 
EU Dipert, Brian, "Accelerating con- 
sumers' NAS adoptions: assessing 
your product options," EDA/, June 25, 

2009, pg 30, www.edn.com/article/ 
CA6666226. 



ACKNOWLEDGMENT 

I'm particularly grateful to Netgearfor sup- 
porting this project by providing a prepro- 
duction version of the WNDR3700 for 
testing purposes . 



FOR MORE 1 


NFORMATION 


Apple 


Intellon 


www.apple.com 


www.intellon.com 


Atheros 


Linksys 


Communications 


www.linksysbycisco. 


www.atheros.com 


com 


Belkin International 


Microsoft 


www.belkin.com 


www.microsoft.com 


Broadcom 


Monster Cable 


www.broadcom.com 


Products 


Cal-Lab 


www.monstercable. 


www.cal-lab.com 


com 


Dell 


Netgear 


www.dell.com 


www.netgear.com 


D-Link 


Roku 


www.dlink.com 


www.roku.com 


Gigle Semiconductor 


Sony 


www.gigle.biz 


www.sony.com 



You can reach 
Senior Technical Editor 



at 1-916-760-0159, 
bdipert@edn.com, 
and www.bdipert.com. 



30 EDN | AUGUST 20, 2009 



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BY DREW E WINGARD, PhD • SONICS INC 



Addressing interleaved 
multichannel memory 
challenges 

INTERLEAVING ADDRESSES IN MULTIPLE DRAM CHANNELS CAN GREATLY 
IMPROVE MEMORY BANDWIDTH, BUT IT IS NOT A TRIVIAL TASK. 



Achieving the total external-memory-bandwidth 
requirements of consumer SOCs (systems on 
chips) at acceptable costs gets more difficult with 
each generation of electronic systems and the 
DRAM technologies that serve them. SOC de- 
signers must optimize for total DRAM efficiency 
to enable the system to reach the highest performance and to 
minimize DRAM-subsystem costs- As SOCs move to more ad- 
vanced DRAM technologies, such as DDR3, that have larger 
minimum burst lengths, challenges arise in delivering optimal 
memory throughput- Using multichannel DRAM subsystems 
helps maximize efficiency by ensuring that the DRAM bursts 
are smaller than the processor- and I/O-interface accesses. 

WHY MULTICHANNEL? 

Discussions of DRAMs introduce terms such as "banks," 
"ranks," and "channels" (Reference 1). Each term describes 
a mechanism for arranging multiple arrays of DRAM cells, 
either within the same chip or across multiple chips, to increase 
memory density, memory performance, or both. The multibank 
architecture of current SDRAM devices enables SOC DRAM 
controllers to improve performance by exploiting parallelism 
across the banks inside a DRAM chip to hide the page-closing 
and -opening penalties of the internal DRAM cell arrays. You 
could employ the same principle with multiple chips, but few 



consumer SOCs support multiple ranks of DRAM devices, in 
which multiple DRAM chips connect to the same data signals 
to increase the total supported memory size, because few con- 
sumer-electronics systems need that much memory. 

The substantial increases in performance in consumer SOCs 
require both more total on-chip processing and substantial in- 
creases in DRAM bandwidth. Although the data-pin band- 
width of DDR SDRAM devices has improved over time, these 
improvements have not kept pace with the requirements of 
several key consumer-SOC markets, such as HDTV (high- 
definition television). As a result, the total number of data 
pins necessary to satisfy DRAM -bandwidth needs is growing 
for such SOCs. 

The combination of increasing minimum burst length asso- 
ciated with DDR3 and the increasing data-pin count leads to 
substantial increases in the minimum burst size of single-chan- 
nel DRAM systems. When these bursts become larger than 
the data objects that the initiators on the SOC are accessing, 
effective throughput declines as the DRAM transfers become 
less efficient. 

One approach to this challenge is to further increase the 
available DRAM bandwidth to compensate for the loss of ef- 
ficiency. However, the bandwidth increase must come without 
further increase to the DRAM burst size, or you lose even more 
efficiency. A better approach is to introduce multiple channels. 



b b a a a a aaa m 

^^^^^^^g I j^^^^^^g ^M^^^^M j^^^^^^^ 




SONICSSX 





MME=MULTI MEDIA ENGINE 



64MX16X2BITS 64MX16X1BIT 

Figure 1 Moving from a single DRAM channel to two channels can increase peak bandwidth. 



64MX16X1 BIT 



32 EDN | AUGUST 20, 2009 



The key benefit of a multichannel DRAM 
system is an improvement in access ef- 
ficiency due to shorter bursts that more 
closely match the size of the data types 
transferring to memory. Note that the 
DRAM bursts are smaller but not short- 
er because only the word is smaller. The 
prefetch degree of the SDRAM type in use 
still largely determines the burst length. 

A second benefit of the multichannel 
system is a likely reduction in efficiency loss due to page-clos- 
ing and -opening delays because an N-way multichannel sys- 
tem has N times as many banks and can therefore manage N 
times more open pages. However, the fact that the pages are 
only 1/Nth as large mitigates this benefit, so some transactions 
that might have found their page to be open in a single-chan- 
nel system — due to a previous transaction's accessing memory 
locations at a similar address, for example — can find a closed 
page instead in a multichannel system. In a consumer SOC 
with many initiators, enough data flows are often waiting for 
access to DRAM that the benefit of more open pages out- 
weighs the smaller page. 

To quantify the efficiency benefits available from a multi- 
channel memory system, consider the migration of a produc- 
tion HDTV SOC from a DDR2 SDRAM baseline to a next- 
generation design based on DDR3 devices. A static analysis of 
the memory traffic from the original design — currently in high- 
volume production — assigns the memory efficiency to be 100% 
as a point of reference. For the next generation of this SOC, 
compare two memory-system architectures: a single-channel 
DDR3 system with a word size of 32 bits and a two-channel 
system in which each channel has a word size of 16 bits (Figure 
1). Note that both configurations 
offer the same peak DRAM band- 
width and use the same number and 
type of DRAMs. 

You might expect the single- 
channel DDR3 design to have lower 
memory efficiency because DDR3 
devices use a prefetch- 8 architec- 
ture and thus have a minimum efficient burst length of 8 words, 
whereas the reference system has the 4-word burst character- 
istics of DDR2. When you consider the efficiency loss due to 
both minimum DRAM bursts that are larger than the SOC 
traffic patterns and address-alignment problems that also result 
from larger bursts, you can see that the single-channel DDR3 
system loses a substantial amount of efficiency. In contrast, the 
dual-channel system has longer bursts that are half as wide, so 
the basic burst size and alignment do not change. Therefore, the 
dual-channel DDR3 system is as efficient as the single-channel 
DDR2 system of the same size. Table 1 shows the efficiency dif- 
ference, which directly translates into usable memory-system 
bandwidth. 

Note that this static analysis ignores any of the bandwidth 
increases that are available due to the higher operating fre- 
quencies available with DDR3 SDRAMs. It compares only 
the relative efficiency of the memory usage. It also ignores 
the likelihood that the DDR3 design will have higher over- 
all performance requirements and, thus, higher total external- 
memory-bandwidth requirements, which are likely to outstrip 



THE KEY BENEFIT 
OF A MULTICHANNEL 
DRAM SYSTEM IS 
AN IMPROVEMENT 
IN ACCESS EFFICIENCY 





DDR2 


DDR3 


DDR3 


Channels 


One 


One 


Two 


Data word width (bits) 


32 


32 


16 


Effective bandwidth (%) 


100 


84 


100 



the frequency benefits of the DDR3 tran- 
sition. More important, the analysis as- 
sumes that you can schedule the memo- 
ry-system traffic for maximum efficiency 
in all cases and balance it evenly across 
the dual-channel configuration. 

Most scenarios require you to balance 
traffic across the channels to deliver mul- 
tichannel benefits. For example, applica- 
tions that require high memory efficiency 
normally have a fair amount of queuing to cover the latency 
between memory requests and responses, including the arbitra- 
tion delays on the SOC among the initiators. If a lightly loaded 
channel runs out of requests to service while the other channels 
are busy, then that channel's throughput and the efficiency ben- 
efits of the multichannel approach decrease. If the channels act 
as independent regions in the memory map, the SOC architect, 
accelerator designer, firmware developer, or application devel- 
oper should carefully allocate data structures in memory so that 
the initiators' access to those structures is well-balanced over 
periods as short as a few microseconds. It is difficult to manage 
this task with a dual-channel memory system and nearly impos- 
sible with the four-channel systems of the future. 

Another challenge with this static load-balancing approach 
is that transaction-ordering requirements often prevent a single 
initiator from sharing memory bandwidth from multiple chan- 
nels at once. This problem arises from the nature of the initia- 
tors' communication protocols, which specify that request and 
response order should match, and from the fact that DRAM 
channels have significant latency variations. So the response 
to a first request to a first channel may likely be unready for de- 
livery until after the response from a second channel is ready. 

Using flow control to hold off the 
second channel is typically unac- 
ceptable because it would cause 
the DRAM to stop servicing re- 
quests while waiting, which reduc- 
es DRAM throughput. The result 
is that static load balancing gen- 
erally requires that most initiators 
communicate only with a single channel, which makes sharing 
and load balancing substantially more difficult. 

WHY IS INTERLEAVING THE ANSWER? 

The ideal approach for load balancing a multichannel 
DRAM system would be one that achieves excellent balanc- 
ing of traffic, is largely independent of the number of channels, 
and requires no extra work in the design of either the initiators 
or the software that controls them. Rather than treating the 
channels as independent memory regions with the resulting 
load-balancing challenges, interleaving the channels in the ad- 
dress space enables them to appear as a single, logical memory 
region and offers the promise of achieving all of these goals. 

To understand why channel interleaving can achieve auto- 
matic load balancing, it is important to understand the memo- 
ry-access behavior of the initiators in the SOC. The initiators 
access data structures in DRAM, so the type of stored data or 
the processing algorithm in use with the data determines the 
expected access patterns to those data structures. Streaming 
accelerators, communication processors, cameras, displays, and 



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CHOOSING THE INTERLEAVING BOUNDARIES IS A 
KEY TASK IN ACHIEVING GOOD LOAD BALANCE. 



I/O interfaces all normally manage large 
data buffers in DRAM. They typically ac- 
cess those data structures using midsized 
to long burst transactions, with each 
burst transaction starting at the sequen- 
tial address following that of the previous 
transaction, until they reach the end of 
their buffer. In contrast, a CPU access- 
es a variety of data structures in memo- 
ry, from small control structures through 
large buffers- Because most CPUs in con- 
sumer SOCs have internal caches, the 
dominant accesses to DRAM are cache- 
line-sized, and the principles of spatial 
and temporal locality teach that many of 
the accesses in a time window have simi- 
lar addresses. 

For many consumer SOCs, the video 
decoder offers a particularly challenging 
case. The video decoder accesses sever- 
al frames of uncompressed video images, 
each of which may comprise 2 million 
pixels of storage, and an incoming stream 
of compressed data that tells the decoder 
how to decode the next frame. The in- 
coming stream frequently tells the decod- 
er to fetch an arbitrary macroblock from 
the frame storage, with each macroblock 
comprising a 2-D set of pixels. Because 
the required macroblock can start at any 
pixel address, it is unlikely that the mac- 
roblock will fit nicely into a few DRAM 
bursts. Furthermore, the total required 
macroblock bandwidth is high enough 
that mapping the macroblocks into effi- 
cient DRAM transfers is essential. 

Earlier interleaving often focused on 
improving memory bandwidth by access- 
ing multiple physical DRAMs in an in- 
terleaved manner to improve pin band- 
width. These systems relied on spreading 
a burst transaction across several DRAMs. 
This approach differs greatly from one in 
which you intentionally create smaller 
channels of memory to reduce, rather 
than increase, the burst size. Some of the 
latest PCs, including servers and desktops, 
also use multiple interleaved channels. 
These channels are normally interleaved 
at CPU cache-line boundaries in an at- 
tempt to best exploit the spatial locality 
of computing applications. These bound- 
aries are finer than optimal for consumer 
SOCs, in which the access patterns tend 
to have more regularity. 



The choice of interleaving boundar- 
ies can greatly affect the load balanc- 
ing. Some of the accelerators access data 
structures in a fairly predictable pattern, 
in which the address of the next memory 
request is spaced a fixed distance away 
from the previous one. These strided ac- 
cesses reduce the channel balance when 
the stride value is a multiple of the inter- 
leaving size because consecutive accesses 
may map to the same channel. Because 
there can be a close correlation between 
memory data structures and strided ac- 
cess patterns, the designer can optimize 
overall throughput by selecting different 
interleaving boundaries for different re- 
gions of memory based on the data struc- 
tures they each store. 

The challenge of balancing the traf- 
fic loading increases with the number 
of channels. The interleaving approach 
can balance the traffic as long as most 
initiators regularly access each of the 
channels — in other words, as long as the 
number of channels times the size of the 
interleaving boundary is smaller than the 
range of addresses the initiators are ac- 
cessing. Thus, optimizing the interleav- 
ing boundaries is related to the number 
of channels. Choosing the interleaving 
boundaries is a key task in achieving good 
load balance, and you may achieve better 
balance when you divide the DRAM ad- 
dress space into several subregions with 
different interleaving boundaries. Ad- 
ditionally, because the best boundary 
choice can depend on the data structure 
and access patterns and because these pa- 
rameters can both change based on the 
operating mode of the SOC, it is some- 
times valuable to change these boundar- 
ies when the mode changes. 

A major benefit of interleaving the 
channels is in isolating the initiators 
from the channel configuration, which 
enables simpler design and much great- 
er reuse of the processors, accelerators, 
and software for the SOC. However, 
this isolation ensures that the initiators 
are not channel- aware, thus increas- 
ing the importance of maintaining high 
throughput for initiators that are access- 
ing several channels at once. Computer 
systems maintain throughput by build- 
ing reordering buffers near the initiators, 



so channels that service requests soon- 
er than an initiator is ready to receive 
them must have a place to store their 
responses- However, the large number 
of initiators in a consumer SOC and 
the growing depth of the DRAM -access 
pipeline mean that the total amount of 
required storage for this reorder buffer- 
ing would be too large and expensive in 
the markets these SOCs serve. 

It is equally important to ensure that 
the SOC memory controllers have a 
great degree of flexibility for scheduling 
traffic to the DRAM channels to ensure 
the highest efficiency and throughput. 
The interleaving system should there- 
fore limit neither the number of transac- 
tions that can be outstanding to chan- 
nels nor the controller's ability to sched- 
ule the transactions that it has received. 

One approach that could address many 
of these challenges would be to manage 
the interleaving in the memory control- 
ler itself. This approach has the advan- 
tages that it localizes the information 
about the number of channels and in- 

INTERLEAVED MULTI- 
CHANNEL TECHNOLO- 
GY MANAGES FLEXIBLE 
INTERLEAVING BOUND- 
ARIES AMONG MULTIPLE 
DRAM CHANNELS IN 
THE INTERCONNECT. 

terleaving boundaries into one location 
on the SOC, minimizing the disruption 
to other architectures and hardware, and 
allows the use of shared buffering in the 
controller to manage ordering and al- 
low many transactions to be outstanding 
across the channels. However, such an 
architecture requires most of the system 
communications to pass through a sin- 
gle point on the SOC, which is likely to 
create a performance bottleneck in both 
wire routing and memory efficiency. This 
memory-efficiency loss can result from 
the same access-granularity problem that 
happens in a single-channel DRAM sys- 
tem: that the internal interface carry- 
ing the memory traffic may become so 
wide — to carry the total DRAM band- 
width for the SOC — that a DRAM burst 
for a single channel may not pack effi- 



ciently into the internal-interface word. 

The SonicsSX interconnect from Son- 
ics (www.sonicsinc.com) uses another 
approach, which employs IMT (Inter- 
leaved Multichannel Technology). IMT 
manages flexible interleaving boundar- 
ies among multiple DRAM channels 
in the interconnect, rather than in the 
RAM controller, providing the ben- 
efits of automatic load balancing and 
high throughput without creating per- 
formance bottlenecks or requiring reor- 
dering buffers. You measure the DRAM 
efficiency as the fraction of the DRAM 
clock cycles during which a useful data 
word is transferring to or from DRAM. 
Although achieving DRAM efficiency 
of 60% is relatively straightforward for 
most designs, targeting efficiencies of 75 
to 90% is more challenging and normal- 
ly requires substantial analysis and opti- 
mization during the SOC-design phases. 

Choosing the right multichannel ar- 
chitecture involves selecting the proper 
number of DRAM channels, allocating 
the DRAM address space across one or 
more multichannel memory regions, and 
selecting the interleaving characteris- 
tics for each region. The SOC designer 
normally chooses the minimum number 
of channels that provide the required 
memory-system efficiency and through- 
put. This configuration generally mini- 
mizes system costs because it results in 
the minimum DRAM costs and reduces 
the number of DRAM-related control 
and address pins on the SOC. 

Single-channel SOCs normally treat 
DRAMs as single pools of address space 
that all of the initiators share. The soft- 
ware that executes on the host CPU 
during booting allocates some of this 
DRAM to specific uses and initiators, 
and the operating system dynamically 
allocates the rest of the DRAM space. 
In an interleaved multichannel system, 
the strided access patterns of some ini- 
tiators can cause channel imbalances 
with certain interleaving boundaries. 
When several such initiators share the 
memory system, the designer may wish 
to allocate multiple subregions in the 
logical DRAM address space with differ- 
ent interleaving boundaries that better 
match the access characteristics of the 
initiators that share each subregion. 

When multiple subregions are in use, 
the operating system normally allocates 
one, and designers have optimized this 



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subregion for more gener- 
al-purpose traffic, typically 
with a small interleaving 
boundary — perhaps at the 
cache-line level, as in a 
PC- The booting process or 
the device drivers normally 
assign the other subregions 
for collections of initiators 
with more predictable ac- 
cesses. Such subregions are likely to have 
larger interleaving boundaries- Designers 
can support multiple operating modes 
with multiple address subregions by allo- 
cating more total DRAM address space 
than the DRAMs contain and allowing 
the subregions to alias their contents on- 
to each other in memory. This approach 
relies on careful allocation of data struc- 
tures in the subregions to ensure that you 
do not simultaneously allocate a given 
area in physical DRAM to multiple data 
structures in different subregions. 

Designers normally map each sub- 
region onto all of the physical DRAM 
channels. But aggressive power-man- 
agement schemes, in which some of 
the channels may power down in some 
operating modes, provide an exam- 
ple in which a designer may populate 
and power some subregions with only 
enough channels to deliver the required 
memory throughput for those modes. 

Once designers know the number of 
channels in a subregion and the ini- 
tiator-access characteristics, they can 
choose the interleaving boundary for 
the subregion. The choice of an inter- 
leaving boundary is critical for achiev- 
ing good load balance among the traffic 
that targets that subregion. 

ESTIMATING RESULTS 

SOC designers do performance esti- 
mation and analysis using spreadsheets, 
cycle- accurate simulation in SystemC, 
and RTL (register- transfer- level) simu- 
lation. Although each technique has its 
advantages and disadvantages, many de- 
signers apply several of the techniques 
to a design. It is therefore important to 
have a consistent vocabulary for perform- 
ance-oriented characteristics of the de- 
sign with instrumentation to measure or 
calculate those characteristics. Key mea- 
surement parameters include through- 
puts, latencies, and DRAM channel effi- 
ciencies, which you measure in the tim- 
ing domain of the initiators that gener- 



EB Go to www.edn. 
com/ms4326 and click 
on Feedback Loop to 
post a comment on 
this article. 



EE For more technical 
articles, go to www. 
edn.com/features. 



ated the traffic. It is useful 
to have access to these per- 
formance results both as ag- 
gregated summary data and 
at the granularity of indi- 
vidual transactions. 

SOC designers must 
compare these performance 
results with the quality-of- 
service requirements of the 
system. Knowing the granularity of in- 
dividual-transaction results helps SOC 
designers debug simulation results to un- 
derstand why the performance may be 
different from what they expect. Tool- 
ing that helps designers track transac- 
tions as they propagate from the initia- 
tor, across the interconnect, through the 
memory scheduler, and into the DRAMs 
increases visibility into challenging per- 
formance-debugging situations. Once 
designers gain insight into the reasons 
for performance results, they can use it 
to modify the SOC and memory-system 
configuration to further optimize perfor- 
mance. 

The substantial increases in DRAM- 
bandwidth requirements of consumer 
SOCs and the prefetch architecture of 
DDR SDRAMs have caused single- 
channel DRAM systems to lose substan- 
tial efficiency as bursts become larger 
than SOC transactions. This scenario 
leads designers to select multichannel 
DRAM systems. However, only inter- 
leaved multichannel systems that sup- 
port multiple subregions with different 
interleaving boundaries deliver the au- 
tomatic load balancing and hardware 
and software transparency necessary for 
consumer SOCs.EDN 

REFERENCE 

M Wingard, Drew, "DRAM technology 
for SOC designers and-maybe-their 
customers," EDA/, Aug 6, 2009, pg 34, 
www.edn.com/article/CA6674038. 

AUTHOR'S BIOGRAPHY 

I Drew E Wingard, PhD, co- 
W _ ^JH founded Sonics in September 

I J 996 and is currendy chief 
^.^/B technical officer and secre- 

I tary. He received a bachelors 
HA^^I degree in electrical engineer- 
ing from the University of Texas — Austin 
and masters and doctorate degrees in elec- 
trical engineering from Stanford University 
(Stanford, CA). 



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EDITED BY MARTIN ROWE 
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READERS SOLVE DESIGN PROBLEMS 



Triac tester allows for manual 
or automatic operation 

Abel Raynus, Armatron International, Maiden, MA 



Triacs are bidirectional ac switch- 
es that can control loads with 
currents as high as 25 A rms at voltages 
as high as 600V. They find wide use in 
motor-speed, heater, and incandescent- 
lamp controls. Logic triacs are especial- 




NC=NORMALLY CLOSED 
NO=NORMALLY OPEN 



Figure 1 A triac tester uses a switch to reverse 
the polarity of the test signal. 



ly attractive for microcontroller-driven 
devices. You can activate a triac direct- 
ly from microcontroller-output ports 
because of the triac's trigger current of 
only 3 to 10 mA. As with any electron- 
ic device, triacs can have some internal 
problems that you can de- 
tect before using them in a 
design. 

Figure 1 shows a simple 
and inexpensive test fixture 
that tests the L2004F31, 
L2004F61, L2004L1, and 
L4004V6TP triacs from 
Littelfuse (www.littelfuse. 
com), but you can use it 
to test any other leaded 
triac because all the stan- 
dard packages, including 
TO-220AB, TO-202AB, 
TO-251, and IPak, have 
the same pin layout. An 
IC socket provides easy 
insertion of a triac under 
test. You can also apply 




O 1 20V AC 
O 1 20V AC 



Figure 2 With a resistive load, the tester uses two 
LEDs to indicate pass and fail in both directions. 



DIs Inside 

41 Handheld DMM copes 
with logic nanosecond-pulse- 
width waveforms 

42 Build a simple complementary- 
bracket-pulse generator 

44 Power-miserly voltage 
reference needs just one pin 

To see all of £DA/'s Design 
Ideas, visit www.edn.com/design 
ideas. 



this idea to SMDs (surface-mount de- 
vices), provided that you can find or 
create an appropriate test socket. Po- 
larity switch Sj, a DPDT (double-pole/ 
double-throw) device, lets you check 
conductivity in both directions. Trig- 
ger switch S 2 , a momentary SPST (sin- 
gle-pole/single-throw) pushbutton de- 
vice, activates the triac under test by 
connecting the gate (Pin 3) with MT 2 
(Pin 2) through resistor R 2 (Figure 1). 

The test takes less than 5 seconds 
and comprises four steps (Table 1 ). An 
LED indicates the result of each step 
to the test operator. A triac is good if 



TRIAC UNDER TEST 



Ci : 
0.047 |jlF 



Ri 
100 



LOAD 



NEON 
LAMP 



R 3 

4.7k 



I A^V — I 

LED, r-i-i 



LOAD 



R 2 
30k 



LED 



LED 2 



-O120V AC 
-Q120V AC 



Figure 3 For an inductive load, add a neon lamp to minimize leak- 
age current. 



AUGUST 20, 2009 | EDN 39 



designideas 



TRIAC UNDER TEST 



G / MT 1 



0.047 |xF 



Ri 
100 



LOAD 



LOAD 



NEON 

6M-A1C ^ OPTOCOUPLER 

— <Q — av^- 



PS2501-2 



-0 1 20V AC 



-0 1 20V AC 




Figure 4 An optocoupler isolates the triac from ground. 




7 + p + 

100k 4n C 

^2.2 jxF 



o 3 

"2.2 |xF 



MICRO- 
CONTROLLER 

ADC0 

ADC1 



T 



Figure 5 RC filters let you use PWM signals. 



it passes all four tests. You should per- 
form another triac test during manu- 
facturing to ensure that there is no 
problem with the subassembly board 
and that the triac works properly. This 
test saves time and labor in case you 
detect a problem after assembling the 
entire product. You perform this test 
with the triac soldered into place on 
the board. You use the nominal pow- 
er-supply voltage of 120/220V ac. The 
test should have minimal influence on 
the DUT and should use minimal time 
and labor. This test uses the triac tes- 
ter in place of a load. The connection 
from the tester to the DUT can vary, 
and be sure to take some safety mea- 
sures when connecting 120/220V ac. 

You use a different test fixture for 
triacs that drive a resistive load, such 
as an incandescent lamp or a heater 
(Figure 2). Each LED checks conduc- 



ac is closed, both LEDs should be off. 
When it is open, both LEDs should be 
on. In the case of an inductive load, 
such as a motor, use an RC snubber 
circuit comprising C 1 and R 1 in paral- 



lel with the triac (Figure 3). Unfortu- 
nately, the snubber circuit introduces 
a small current leakage into the test 
circuit even when the triac is closed. 
The circuit in Figure 3 shows you how 



TEST FOR TRIACS 


Step no. 


Operations 


LED status 


Result 


1 


Insert triac under test into 


Off 


OK 


the socket; turn on power 


On 


Shortage inside triac 






Off 


Break inside triac 


2 


Push and release trigger 


Stays on 


OK 




switch S 2 


On but goes off 
after you release S 2 


Bad "hold" function 
in triac 


3 


Move polarity switch S 1 


Off 


OK 


into another position 


On 


Shortage inside triac 






Off 


Break inside triac 


4 


Push and release trigger 


On 


OK 




switch S 2 


On but goes off 
after you release S 2 


Bad "hold" function 
in triac 



40 EDN | AUGUST 20, 2009 



to avoid this problem using resistor R 2 
and a neon lamp with an ac break- 
down voltage of 95V. 

The indicators of the test result in 
figures 1,2, and 3 are LEDs. Some- 
times, the triac test is part of a multi- 
tasking test system that checks oth- 
er components or parameters of the 
whole device, which includes the triac. 
This test involves a sequence of mea- 
surements, and a system operator gets 
only one of two possible signals: pass or 
fail. These tests use a microcontroller- 
based system. Thus, all the interface 
signals should be in digital format: high 
or low. 

You can also use analog signals by ac- 
tivating the microcontroller's ADCs. 
This approach is less preferable, how- 
ever, because of the limited number 
of ADCs in low-end microcontrollers 



and more complicated software. Inter- 
facing the triac under test with the mi- 
crocontroller creates no problem if the 
triac 's MT 1 pin is grounded. In most 
cases, MT 1 and MT 2 are isolated from 
the ground. When this scenario occurs, 
you can use an optocoupler, such as the 
PS2501-2 from California Eastern Lab- 
oratories (www.cel.com, Figure 4). It 
comprises two optically coupled isola- 
tors containing LEDs and NPN pho- 
totransistors with a maximum voltage 
of 80V. 

If the triac output comprises a se- 
quence of pulses, such as a PWM 
(pulse-width-modulated) signal for 
motor-speed or lamp-brightness con- 
trol, then use a lowpass RC filter be- 
fore the microcontroller's ADC inputs 
(Figure 5). The time constant of this 
filter, t=R 6 XC 2 , depends on the PWM 



signal period and duty cycle. The mea- 
surement in the chain of tests should 
start no earlier than 3 — 5t. Using the 
microcontroller's ADC requires addi- 
tional firmware. To avoid this require- 
ment, you can compare the voltage af- 
ter the filter with a reference voltage 
with a comparator, such as the LM393 
from National Semiconductor (www. 
national.com), to produce a logic-high 
level for the microcontroller's input. 
Reference 1 describes an alternative 
approach with minimal external com- 
ponents for the expense of the firm- 
ware complication.EDN 



REFERENCE 

9 Raynus, Abel, "Microcontroller 
detects pulses," EDA/, July 24, 
2008, pg 58, www.edn.com/article/ 
CA6578137. 



Handheld DMM copes with logic 
nanosecond-pulse-width waveforms 

Marian Stofka, Slovak University of Technology, Bratislava, Slovakia 



When testing sequential-logic 
circuits, you may find that, al- 
though the repetition frequency of a 
logic signal is within the range of your 
DMM (digital multimeter), you can't 
measure it- The displayed frequency 
value is either dubious or chaotically 
changing in time- The DMM may also 
behave as if there were no signal- Any 
of these undesired states might appear 
when the duty cycle of the measured 



waveform is either close to zero or is ap- 
proaching one — in other words, when 
the width of a pulse — high or low — is 
much narrower than the repetition pe- 
riod of these pulses. This problem occurs 
because you can't expect a DMM with 
an upper frequency limit of perhaps 200 
kHz to measure 100-nsec-wide pulses, 
even if the repetition rate of these puls- 
es is well below the upper limit of the 
DMM's frequency range — perhaps just 



POWER-SUPPLY TERMINAL ( 



i C 1 

1 100nF 
i 

i 

; r i 

i 100 

LOGIC SIGNAL O — vW— 



gnd6- 

■ 

LOGIC CIRCUIT UNDER TEST ! 



8 



PRE V DD 

D | Cl Q 
SN74AUC1 G74 

FLIP-FLOP 
>CLK 

CLR GND 



3 

op- 1 



DMM 



T 



Figure 1 A binary divider turns low- or high-duty-cycle waveforms into square 
wave so that you can measure their frequencies. 



5 kHz. For a rough estimation of band- 
width for measuring at a pulse width 
of 100 nsec, consider this pulse to be a 
half-period of a square-wave signal Use 
the following equation to calculate the 
required bandwidth: 



1 



1 



2T W 2x10' 



= 5 MHz. 



This frequency is well beyond the 
bandwidth of most DMMs. The second 
cause of failing to measure the repeti- 
tion rate of logic waveforms with too- 
low or too-high duty cycles lies in the 
internal ac coupling of the DMMs dur- 
ing frequency measuring. Due to this 
coupling, the decision threshold of an 
internal comparator, which you derive 
from the mean value of the measured 
waveform, is close to either the low or 
the high level of this waveform. In the 
case of narrow pulses, the operation of 
the internal comparator becomes am- 
biguous, and any noise in the measured 
waveform or that the comparator itself 
generates may cause an error. 

You can address the problem by plac- 
ing a binary divider between the source 
of a logic signal and the DMM. The bi- 
nary divider comprises IC^ a positive- 
edge-triggered, D-type flip-flop (Figure 
1). The supply pin of IC 1 connects to 
the supply terminal of the tested logic 



AUGUST 20, 2009 | EDN 41 



designideas 



circuit- Therefore, you can run 
the logic at any industry-stan- 
dard supply voltage of 1.2, 1.5, 
1.8, or 2.5V. In testing 3.3V 
logic, use an external 2.5V 
source to supply IC r The in- 
ternal protective diodes at Pin 
1 of ICp along with resistor 
R p reduce the voltage swing 
at Pin 1 to an acceptable level 
in such a case. 

A square-wave signal is at 
the output of the binary di- 
vider (Figure 2). The DMM 
no longer sees nanosecond 
pulses at its measuring termi- 



INPUT LOGIC SIGNAL 



SMALL DUTY CYCLE . 



INPUT LOGIC SIGNAL 



LARGE DUTY CYCLE 



Figure 2 The flip-flop output, Q, produces a signal with a 
50% duty cycle. 



nal. You have only to mul- 
tiply the displayed frequen- 
cy value by two to obtain 
the correct frequency. Due 
to relatively low values of 
R 1 and of the input capaci- 
tance, approximately 2.5 
pF, at the clock input of the 
flip-flop, you need not worry 
about frequency compensa- 
tion. The time constant of 
R^XC^ is merely 0.25 nsec. 
The width of pulses — either 
low or high — at the input of 
the circuit can decrease to 
1 nsec.EDN 



Build a simple complementary- 
bracket-pulse generator 

Horst Koelzow, Global Thermoelectric, Calgary, AB, Canada 



When building push-pull 
switching power converters or 
motor controllers, you often need alter- 
nating pulses with a small amount of 
dead time between them to minimize 
simultaneous conduction in output- 
switching devices. Switching control- 
ler ICs have this feature, but they usu- 
ally operate within closed loops to min- 
imize IC pin count. When optimizing 
switching output stages, you may need 



open-loop control. Figure 1 shows how 
you can build such a generator with just 
two common ICs. As a bonus, both the 
overlapping, P-channel drive and the 
nonoverlapping, N -channel drive are 
available simultaneously. 

The circuit's input, Pin 10 of IC^ 
comes from clock generator IC 2F . A 
slightly delayed and inverted version 
occurs at IC^s Pin 9 from IC 2A . IC 1 then 
decodes the original and delayed inputs 



to form the desired outputs (Table 1). 
Because IC 1 is an analog demultiplex- 
er, you can set its outputs either active 
high or active low with pull-up or pull- 
down resistors. You determine the high 
or low inactive state by tying the X or Y 
pins to either the power-supply voltage 
or ground. Depending on the state of 
IC 1A 's A and B inputs, internal switches 
in IC 1 close between X and X0 to X and 
X3, as well as from Y and YO to Y and 
Y3. Buffers IC 2B through IC 2E buffer and 
invert the resulting outputs. You can 
use the remaining gate as a variable- 
frequency or variable-duty-cycle gen- 
erator. You determine the dead time, 



T c t CD4584 






V CC V C 




"ClB 

CD4052 


R 3 : 

10k < 




: r 4 

► 10k 

9 


XO 


12 Q ( 






X1 

X X2 


14 






15 


i 11 






X3 


11 n 





"C 1C 
CD4052 



IC 2D 
CD4584 



Y0 
Y1 

Y 

Y2 
Y3 


5 3 


2 




5 


^6 < 

10k « 


l 

M 


►10k 



CD4584 



IC 2B 
CD4584 



ic 2L 

CD4584 



NONOVERLAPPING 
l l l l l 



i i i 

i i i 

m 

i i i i 

i i i i 

i i i i 

i i i i 

i i i i 

i i i i 

i i i i 

i i i i 

i i i i 



OVERLAPPING 



Figure 1 You can build a simple pulse generator with just two commonly available ICs. 



42 EDN | AUGUST 20, 2009 



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designideas 



which is independent of frequency or 
duty cycle, using the time constant of 
R 1 and C r Depending on output-device 
characteristics and switching frequency, 
output buffers may require an addition- 
al stage, or you can replace them with 
MOSFET-gate-driver devices. Sup- 
ply voltage is not critical but should 
be high enough to guarantee that out- 
put devices fully turn on. In general, a 
higher supply voltage allows for higher- 
speed operation. The MCHxxx series 
of ICs is the same as the CD4xxx series. 
If you need higher-frequency operation 



ORIGINAL AND 
DELAYED INPUTS 


Pin 9 
(Input 
B) 


Pin 10 
(Input 
A) 


Sequence 





1 


Phase A 


1 


1 


Dead time 


1 





Phase B 








Dead time 



at lower supply voltages, then use the 
74HC4xxx-series devices. All of these 
ICs are available from a number of 



manufacturers, including Texas Instru- 
ments (www.ti.com, Reference 1 ) and 
On Semiconductor (www.onsemi.com, 
Reference 2) 



REFERENCES 

9 "CD4051B, CD4052B, 
CD4053B," Texas Instruments, Octo- 
ber 2003, http://focus.ti.com/lit/ds/ 
symlink/cd4052b.pdf. 
9 "Semiconductor and Integrated 
Circuit Devices," On Semiconductor, 
www.onsemi.com/pub_link/collateral/ 
mc14584b-d.pdf. 



Power-miserly voltage reference 
needs just one pin 

Peter T Miller, Applied Inspirations LLC, Bethlehem, CT 



The supply rail normally pow- 
™™ ers a microcontroller's voltage- 
reference source. In power-critical bat- 
tery-operated applications, the con- 
stant drain, even of a few 10s of micro- 
amps, can be prohibitive- This situa- 
tion requires adding a pin to turn the 
reference voltage on and off- By adding 
a 0.1-juuF capacitor in parallel with the 
voltage reference and a simple bit of 
software that you can download from 
the online version of this Design Idea 
at www-edn.com/090820dia, you'll 
need just one pin to both power and 
read the reference voltage. 

When you connect the voltage refer- 
ence as in Figure 1 , the software con- 
figures the Microchip (www.micro- 
chip.com) PIC chip's V REF (reference- 
voltage) pin as a switched-on output. 
After approximately 300 fxsec, the 
voltage across the capacitor stabilizes 
at 1.225V. 

There is an initial overshoot when 
the ZXRE4041 powers up. The pin is 
then reconfigured as an analog input 
for the ADC's reference-voltage source. 
The reference voltage quickly drops 
by 20 mV in the next 50 jxsec as the 
ZXRE4041 shuts down. With a 0.1-jxF 
capacitor, the voltage then slowly drops 
60 mV over 2 msec because of leakage. 
Although this delay is exponential, the 
rate is so slow that, for practical pur- 



GP1/AN1/V REF 


6 




PIC12F675 
MICROCONTROLLER 




: R i 

► 10k 




► 3 




NCO-i-rj 

ZXRE4041 
1.225V 


J 

► 2 













: o 1 

0.1 |xF 



Figure 1 A voltage reference and a capaci 
tor provide a reference voltage for a micro 
controller. 



poses, you can consider it linear for this 
short time window. 

You must also consider that the 
ADC also draws current through the 
10-kH resistor during conversion, caus- 
ing voltage drop. Although Microchip 
doesn't characterize this voltage drop 
in its documentation, tests consistently 
measured a drop of 80 mV for sever- 
al devices, giving a calculated current 
of 6.67 fiA. Using a conservative in- 
ternal 4-MHz clock and allowing an 
ADC clock of frequency oscillation di- 
vided by 16 for operation at the min- 
imum operating voltage, one conver- 
sion takes 45 fisec. This action slightly 
drains the capacitor, but this drainage 
appears to be only 2 or 3 mV. Calcu- 



lations of initial watt-seconds minus 
watt-seconds used yield even lower 
values. Subtracting these fixed, repeat- 
able losses from the initial steady-state 
1.225V yields a new reference voltage 
of 1.225V REF -0.020V shutdown 
drop-0.080 IR drop= 1.145V. 

Allowing 75 fxsec to do the an- 
alog-to-digital conversion, store 
the value, and set up for the next 
conversion on another channel, 
1 1 conversions will result in the 
last one's reference voltage being 
lower by 22.5 mV — that is, 10 
conversions X 75 |JLsecX(60 mV/ 
2000 fxsec). This error is only 
1.9% compared with the first 
conversion's results. 

If you just need an approxi- 
mate voltage for a consumer 
product, for example, to warn 
of low battery voltage, you can use an 
LED instead of the ZXRE4041. Just 
change the value of R t to 300H to pro- 
vide sufficient current to turn on the 
LED. Although LEDs lack the tem- 
perature stability of dedicated voltage- 
reference chips, the variation may be 
acceptable for the application because 
most consumer products find use with- 
in the comfort range of humans. If an 
LED is already part of the system, then 
the voltage-reference cost is only that 
of the software. Using this technique, 
an LED can now provide status- indica- 
tor, photodetector, and voltage-refer- 
ence functions and enter a zero-power 
state using only software to reconfigure 
the changes.EDN 



44 EDN | AUGUST 20, 2009 



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productroundup 

COOLING AND ENCLOSURES 




Sequential connecting box 

provides a secondary lock for added safety 

□ Linking generators to low-voltage networks, the PowerLock Box sequential 
connecting box uses 2U of rack space in a 19-in. rack. The devices come in 
standard packages that seal only when you mate the connectors and in a sealed 
package with a lid covering the connector ports- A secondary lock activates a micro- 
switch joining a two-pin connector on the back of the unit to a circuit breaker or an 
alarm circuit- Meeting IP65 standards, the environmentally sealed connector box 
comes in 400 and 600 A versions. The devices have a 1 000 V- ac/1 5 00 V-dc voltage 
rating with a —30 to +85°C operating-temperature range and 500-connection life 
cycles- Prices for the PowerLock Box sequential connecting box range from $500 to 
$600, depending on quantity. 
ITT Interconnect Solutions, www.ittcannon.com 



240VNEMA-rated 
enclosures have Euro- 
pean-style power plugs 

□ The 240V, NEMA-rated equip- 
ment-enclosure series with built- 
in European-style power plugs requires 
no plug adapters or converters. Appli- 
cations include heaters, cooling fans, 
and vented enclosures, and options in- 
clude ABS plastic or fiberglass construc- 
tion, allowing designers to protect both 
wired and wireless communications 
equipment. Prices for the 12 enclosures 



range from $49.99 to $469.99. 
L-com Inc, www.l-com.com 

Waterproof computer 
uses heat-pipe cooling 
technology 

□ The waterproof, rugged, small- 
footprint, fanless WPC-500F com- 
puter features power, video, serial, and 
USB connectors that couple through 
watertight, locking, bayonet-style con- 
nectors used in military-designed hard- 



ware. Meeting IP67.NEMA 6 environ- 
mental specifications, the watertight 
construction survives liquids, chemicals, 
dust, and dirt. Using no cooling fans, 
the device cools the internal CPU us- 
ing advanced heat-pipe technology. An 
aluminum chassis acts as a heat sink, 
dissipating internal heat, and provides 
noise-free operation. The computer uses 
Intel's Atom processor and has a 10 to 
30V-dc input-power range. Measuring 
191X298X75.5 mm, the basic configu- 
ration of the WPC-500F costs $1995. 
Stealth.com, www.stealth.com 

DC blowers suit 
hybrid-electric vehicles 

□ The ODB600PT and the ODB- 
9733 dc-blower series come in 12, 
24, and 48V models. The blowers fea- 
ture brushless-dc motors, locked rotor 
and polarity protection, and auto-restart 
functions. Available in 1800-, 2500-, 
and 3000-rpm speeds, the blowers have 
a 25- to 35-cfm airflow range. The 
ODB600PT and the ODB9733 measure 
120X120X32 and 97X94X33 mm, re- 
spectively, and suit use in cooling fuel 
cells in hybrid-electric vehicles, telecom 
equipment, and other battery-powered 
products. The ODB600PT dc-blower 
series costs $23.50 for the 12 and 24V 
models and $27.50 for the 48V model. 
The ODB9733 series costs $18.50 for 
the 12 and 24V models and $20.50 for 
the 48V model. 

Orion Fans, www.orionfans.com 

Condenser uses 
airflow in the chassis 
to cool CPU 

□ Suiting use in noise-sensitive 
workstations, the SilentFlux pas- 
sive pro cooler high- efficiency condens- 
er uses airflow within the chassis to cool 
the CPU. The condenser uses bubble- 



46 EDN | AUGUST 20, 2009 



pump technology, a nonmechanical, 
self-contained system that uses CPU- 
generated heat to create hot liquid 
and gas bubbles, which move through 
hermetically sealed, closed-loop tub- 
ing and a condenser/radiator to cool 
the system. The bubbles continue cir- 



culating, condensing, and returning, 
creating the bubble pump. The alu- 
minum design reduces the need for 
high-power, high-noise airflow. The 
SilentFlux passive pro cooler costs 
$30 (1000). 

Noise Limit, www.noiselimit.com 



INTEGRATED CIRCUITS 



ADC enables daisy- 
chaining of as many 
as eight devices 

□ The four-channel, simultane- 
ously sampling MAX 1 1 040 
ADC allows daisy-chaining of as 
many as eight devices, providing a 
3 2 -channel sampling capacity. The 
24-bit converter provides cascade 
SPI, QSPI, and Microwire interfaces. 
Featuring a minimum of 90 dB of SI- 
NAD and 91 dB of SFDR, the device 
aims at industrial power-grid-protec- 
tion equipment, medical EKG/EEG 
equipment, and applications requir- 
ing accurate conversion of simulta- 
neously sampled channels between 
0.25k and 64k samples/sec. The con- 
verter provides overvoltage protec- 
tion against ±6V voltages. Avail- 
able in a TSSOP-38, the ADC costs 
$13.45 (1000). 
Maxim Integrated Products, 



www.maxim-ic.com 



Multiplexers provide rail- 
to-rail analog capabilities 

□ The eight-channel DG508B 
and dual four-channel DG509B 
CMOS analog multiplexers enable 
±15V high-precision, low-noise signal 
switching, suiting use in data-acqui- 
sition, medical-system, and test-and- 
measurement equipment. Features in- 
clude rail-to-rail analog capability, 3-pA 
channel off-leakage, 3-pF parasitic ca- 
pacitance, and 2-pC charge injection. 
Operating over a —40 to + 125°C tem- 
perature range, the multiplexers con- 
sume 10 |iA at 25°C with a 600- fx A 
maximum consumption over tempera- 
ture. The devices have a 200-MHz, — 3- 
dB bandwidth with crosstalk and off- iso- 
lation of -40 dB at 100 MHz. Available 
in SOIC-16 and TSSOP-16 packages, 
the DG508B and DG509B CMOS ana- 
log multiplexers cost $1.15 (1000). 
Vishay Intertechnology, 
www.vishay.com 



ADVERTISER INDEX 



Company 




Company 




Advance Devices Inc 


47 


Mentor Graphics 




Agilent Technologies 


8 


Mill Max Manufacturing Corp 


9 


Allied Electronics 


37 


Mouser Electronics 


4 


Analog Devices Inc 


15 


National Instruments 




BuyerZone 


C-3 


Numonyx 




Coilcraft 


7 


Pico Electronics 




Digi-Key Corp 


1 




22 


Express PCB 


23 




34 


International Rectifier Corp 


5 


Sunstone Circuits Inc 




Keil Software 


36 


Trilogy Design 




Linear Technology Corp 


C-4 


Xilinx Inc 


38 


LS Research 


23 


EDN provides this index as an additional 
service. The publisher assumes no liability for 
errors or omissions. 


MathWorks Inc 


19 


Maxim Integrated Products 


43 




45 




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AUGUST 20, 2009 | EDN 47 



TALES FROM THE CUBE 



ERNEST TANNER • LATTICE SEMICONDUCTOR 



Finger on the trigger 




Ve been working in the electronics field for more years than 
I like to admit. The equipment and techniques we have 
available now are much more powerful than I could have 
imagined — a good thing, given that the problems we have 
to solve have evolved just as much. 
My company is a semiconductor manufacturer that makes 
CPLDs and FPGAs- Because most of my career has been in the 
lab, I spend most of my time testing and debugging. Sometimes, 
a customer s design is not working properly, and I have to figure 



out what the problem is. If it turns out 
to be a problem with the design and 
not with our part, we like to have solid 
proof before blaming the mistake on 
the customer. 

One customer's board had pulses — 
definitely coming from our part — that 
shouldn't have been there- Most of the 
prototypes had the unwanted pulses, 
so it wasn't just one broken chip. Ide- 
ally, that signal was normally high with 
low-going pulses of varying widths — 1 7 
fisec being the longest- The problem 
pulses were about 100 nsec wide and 
appeared fairly regularly. 

Just for the record, this design looked 
like a well-done job. We could find no 
obvious problems. 



PROGRAMMABLE LOGIC 
ALLOWS YOU TO EASILY 
MODIFY THE DESIGN. 

While probing the input signals, we 
noticed that the problem disappeared 
when the probe was on a particular in- 
put. Aha! We'd all seen this one before. 
There was a small glitch; it had to be 
very small for the 0.7-pF capacitance 
of the probe — a FET probe, in this 
case — to eliminate it. 

Fortunately, the customer had sub- 
mitted good information about the 
design, and we were able to inspect 
the schematic for the board and the 
source code for the programmable part. 



The design used that signal all over the 
board as a clock. It wasn't a very fast 
clock, but the edge rates were approxi- 
mately 1 nsec. The signal was an old- 
fashioned TTL (transistor- transistor- 
logic) -level signal, with an input low 
voltage of 0.8V, an input high voltage 
of 2V, and an output high voltage of 
approximately 3 V. I had enough infor- 
mation to convince me, but I wanted 
more. Just to test the theory, we sol- 
dered a 10-pF capacitor to the trace, 
and the problem went away. No engi- 
neer I know would use this as a solu- 
tion, but it was good confirmation. 

We had previously not had a good 
trigger, so it was hard to get a good look 
at one part of the signal. We took a lot 
of single-shot pictures and determined 
that the longest pulse on the output 
was about 17 Lisec. Because this was 
2006, not 1976, we had some nice op- 
tions for triggering. Setting the trigger 
to capture a negative-going pulse great- 
er than 15 fisec gave us a nice, stable 
look at the output. The glitches were 
occurring at consistent places, which 
made it possible to zoom in and take a 
good look at the suspicious clock. The 
falling edge had a little bump starting 
at about 0.6V and peaking at 0.9V be- 
fore starting back down. 

Still, we wanted to get even more 
evidence. One good feature of pro- 
grammable logic is that it allows you 
to easily modify the design to bring out 
an internal signal. We created a buffer 
that brought the clock signal back out 
to an unused pin. If the bump was not 
enough to cause the glitch, then the 
buffered output should be clean. Oth- 
erwise, we'd get a significant pulse. We 
got a nice, clean 1-nsec pulse at a volt- 
age as high as 2.3V. And we were able 
to give the customer a detailed report 
that settled the issue for good.EDN 

Ernest Tanner is an application engi- 
neer at Lattice Semiconductor. 



EE Go to www.edn.com/090820tales 
and click on Feedback Loop to post a 
comment on this article. 

EE www.edn.com/tales 



48 EDN | AUGUST 20, 2009 





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