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Programmable servo filters smooth motion control Page 15 

April 28, 2005 




Digital Power 

Flexibilitv & 150-ps PWM Resolution 



UCD7K Family Fusion Digital Power™ Drivers 



Interface digital controller to power 
stage; provide protection and bias . 



UCD8K Family Fusion Digital Power™ PWM Controllers K.^a1dt'iT"o^rsr?he1i^p''°« 



UCD9K Family Fusion Digital Power™ Controllers 



Close multiple loops digitally; provide 
communication and supervision 



Combining expertise in analog power management and DSP, the revolutionary new family of 
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High Performance. Analog. Texas Instruments. 



For Samples, Reference Designs and Datasheets, 
visit www.ti.com/digitalpower 





Fusion Digital Power, Technology for Innovators and the red/black banner are trademarks of Texas Instruments. M6560 © 2005 Tl 



^ Texas Instruments 




BDU.B^^.^SBB . www.digikey.cam • 218.E81.338D 

Enter 1 at www.edn.com/info 




Enter 2 at www.edn.com/info 



A Burning Issue. 



Design Example: 




100 150 
Performaiice (MHz) 

Design Example: LX60 vs. 2S60. Target Frequency = 200 MHz. Worst-case process. 
20K LUTs, 20K Flip-Flops, 1Mbit On-Chip RAM, 64 DSP Blocks, 128 2.5V I/Os 
Based on Xilinx tool v4.0 and competitor tool v2.1 
For higher density devices, achieve up to 5W lower power 



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250 



^ vjgXgy Get 1-5W lower power per FPGAy 
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K XILINX* 

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© 2005 Xilinx, Inc. AH rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. AH other trademarks are the property of their respective owners. 








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29 LIN simplifies and standardizes 
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EDN"^' (ISSN#0012-7515), (GST#123397457, R.B.I. IntI Pub Mail #0280844) is published biweekly, 25 times per year, by Reed Busi- 
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April 28, 2005 | edn 7 



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Dilbert. Page 16 



cnntents4.?8.05 




Coplanar connector 
has low insertion 
loss and crosstalk. 
Page 84 



LEADING EDGE 



DESIGN IDEAS 



15 


Programmable servo filters smooth motion control 


75 


Camera serializer/deserializer chip set reduces 


15 


Resistor array divides, so design conquers ratio needs 




wire count for keypad 


16 


Power-industry coalition announces PMBus standard, 
forms SIG 


76 


Rearranged reference helps ADC measure 
its own supply voltage 


16 


Wi-Fi chip attaches via PCI Express 


78 


Difference amplifier measures high voltages 


16 


Dilbert 


80 


Linear potentiometer provides nonlinear light- 


18 


Midpriced, 1.5-GHz-bandwidth DSOs provide 




intensity control 




an array of features 


DEPARTMENTS & COLUMNS 


18 


VOlP-adapter design boasts $6 price 


24 


Crosstalk in differential vias with grounds 


20 


Structured ASIC offers memory-for-logic swapping 




by Howard Johnson, PhD 


20 


Even jacks are getting smarter 


26 


Perception problem dogs engineering 


22 


FPGA development kit targets designs that "race" 




by John Dodge, Editor in Chief 


22 


Single-chip FM tuner enables embedded broadcast receiver 


43 


Editorial Staff 


PRODUCTS 


44 


Business Staff 


84 


Connectors 


86 


Advertisers Index 


84 


Microprocessors 






86 


Electronic Design Automation 








llllllllllll 

dffiign . 



ideas 



The Best of Design Ideas 

A selection of your 
best tricks for tricky problems. 
www.edn.com/bestofdesignideas 

Submit a Design Idea: 
Make $150 

www.edn.com/index.asp?layout= 
sitelnfo&docjd=30988 



ONLINE ARTICLES 

You think backward compatibility 
is tough today? 

►iwi/i/i/ edn. com/artide/CA5161 18 

IC design must embrace network effects 

►iwi/i/i/ edn. com/article/CA5161 15 

Reconfigurable-processing IP targets 
CESOCs 

►iwi/i/i/ edn. com/artide/CA516142 

Intel releases new NOR for embedded 
market 

►iwi/i/i/ edn. com/article/CA515863 

Digital Den: Coaxial adapters 
don't disrupt TV 

p^www. edn. com/article/CA514859 



BLOGS 

(Our editors spout off. You spout back.) 
On The Verge 

by Maury Wright Editor at Large 

• Need 1 terabyte for movies and music? 

• Video bypasses mobile networks, arrives 
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For a free subscription, go to www.getfreemag.com/edn 



April 28, 2005 | edn 9 



4+32= More Channels. 
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Intersil Switching Regulators 



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Regulators 


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# of Outputs 


Device 


PWMs 


Linears 


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Package 


4 


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3 




5 


20 


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1 


2 




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QFN-24 




ISL6455A 


1 


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5 


0.6 


QFN-24 


3 


ISL6537 


2 


2 + Ref 




2.5, 12 


20 


QFN-28 




ISL6532A 


1 


2 




5, 12 


20 


QFN-28 




ISL6441 


2 


1 




4.5 to 24 


6 


QFN-28 




ISL6443 


2 


1 




4.5 to 24 


10 


QFN-28 




LSI 6??7 


? 







4 5 to 24 


16 






ISL6440 


2 







4.5 to 24 


10 


QSOP-24 


2 


ISL6539 


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5 to 15 


8 


SSOP-28 




ISL6530/1 


2 


Ref 




5 


1 


SOIC-24, QFN-32 




ISL6528 


1 


1 




3.3,5 


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SOIC-8 




ISL6529 


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intei kil 

HIGH PERFORMANCE ANALOG 



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Enter 7 at www.edn.com/info 



Empowered by Innovation 



There will only ever 

BE ONE VAN DREBBEL. 

Just like now there's only one 
d'Espaignet, Evans, Loukianov, Maassel, 
Patulea, Peterson, Schatte, and Ursu. 



They all started out with the same mission: design some- 
thing cool using microcontrollers from NEC Electronics. 
But in the end, only a select few earned the right to 
have their name mentioned in the same breath as 
Cornelius Van Drebbel. Here's to the innovations-and 
the innovators-that would have made Cornelius proud. 




CONGRATULATIONS to the winners 
OF THE NEC Electronics microcontroller design contest. 



HARDWARE CATEGORY ONE 
[ EV9835 board ] 

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Dmitrii Loukianov 
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LCR Meter 

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Brian Evans 

Vancouver, British Columbia 
Aquarium Management Unit 

THIRD PLACE 

John Peterson 
Menlo Park, California 
NEC Tilt Handheld Game 



HARDWARE CATEGORY TWO 
[ EV0338 & K0RE9418 boards ] 

FIRST PLACE 

Alain dTspaignet 
Jacksonville, Florida 
SmartPlanter 

SECOND PLACE 

Gabriel Patulea 
Kanata, Ontario 
Digital Audio Filter 

THIRD PLACE 

Alvin Schatte 
Trenton, Texas 
Turbine Power Meter 



E-PAPER CATEGORY 
FIRST PLACE 

Marcel Ursu 

Burnaby, British Columbia 
BrainlRac 

SECOND PLACE 

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Fargo, North Dakota 
Car Stereo Tester 



What makes a winner a winner? Find out at 



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©2005 NEC Electronics America, It 



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eadD 





What's hot 
in the 
design 
community 

Edited by 
Fran Granville 



Image issue 

''As long as we continue 
to view engineering as 
about widgets and not 
about people, we will 
continue to have 
a perception problem/' 

-Geoffrey Orsak, Dean, 
Southern Methodist University, 
School of Engineering, on the 
shortage of US engineering 
graduates 



Programmable servo filters 
smooth motion control 

By Warren Webb 



T 



ARGETiNG MEDICAL, Sci- 
entific, and general-au- 
tomation applications. 
Performance Motion Devices 
recently announced the Mag- 
ellan-PCI motion controller 
with dual biquad filters. Avail- 
able in one-, two-, three-, and 
four- axis versions, the high- 
performance Magellan -PCI 
motion-control card supports 
dc brush, brushless, micro- 
stepping, and pulse and direc- 
tion motors. The dual biquad 
filters can produce two polar- 
ities of lowpass output, as well 
as highpass, bandpass, and 
notch filters. 

Additional features include 
trajectory generation, servo- 
loop closure, quadrature-sig- 
nal input, motor-output sig- 
nal generation, servo trace, 
on-the-fly changes, and com- 
mutation. The device supplies 
servo-loop rates as fast as 50 



|jLsec/axis, a 5 million-count/ 
sec quadrature-encoder- input 
rate, and pulse and direction 
output as fast as 5 million 
pulses/sec. The card accepts 
input parameters, such as po- 
sition, velocity, acceleration. 



deceleration, and jerk, and au- 
tomatically generates the pro- 
grammed trajectory. Magel- 
lan-PCI prices start at $638 
(OEM quantities). 
►Performance Motion De- 
vices, www.pmdcorp.com. 




With dual biquad filters at the output of the servo loop, the new 
Magellan-PCI motion controller delivers reduced resonance, faster trans- 
fers, and smoother motion. 



Resistor array divides, so design conquers ratio needs 

^^^^^^^^^^^^^^^^^^M The venerable resistor divider is still a BI fabricated the resist 




Get precision voltage division using a 
low-drift, close-tracking ratiometric 
resistive divider in a two-element 
SOT-23 or a three-element SOT- 143 
package. 



The venerable resistor divider is still a 
staple of high-precision analog circuits, be- 
cause it enables measurement architectures 
that depend not on absolute component 
values, but only on their ratios, which are 
more stable. BI Technologies has put a se- 
ries-connected, two-resistor divider into a 
three-lead SOT-23 package, forming a pre- 
cision voltage divider. The ultrastable resis- 
tors of the SSI series are available in stan- 
dard ratios of 1-to-l, l-to-4, and 1-to-lO. 
Tolerances are as tight as 0.1%, and the 
more critical temperature coefficient is 
±25 ppm/°C with tracking tolerance better 
than ± 5 ppm/°C. 



BI fabricated the resistors using ni- 
chrome thin-film technology on a silicon 
substrate. The device's size lets designers 
place it close to the circuit area of interest, 
thus "eliminating the need for the long 
traces and complex routing schemes re- 
quired for large networks," according to 
Mike Torres, application engineer and 
product marketing manager for BI. The SSI 
series is also available with three resistors in 
a network in a four-lead SOT- 143 package. 
Prices begin at 30 cents (10,000). 

— by Bill Schweber 
►BI Technologies, www.bitechnologies. 
com. 



www.edn.com 



April 28, 2005 | edn 15 



Power-industry coalition announces 
PIVIBus standard, forms SIG 



A COALITION OF POWER-SUPPLY and Semicon- 
ductor companies led by Artesyn Technologies 
has released Version 1.0 of the PMBus (Power 
Management Bus) specification, which defines a 



protocol to manage power 
converters and a power sys- 
tem using communication 
over the SMBus digital-com- 
munication bus. The coalition 
has also announced the for- 
mation of an SIG (special in- 
terest group), the SM-IF (Sys- 
tem Management Interface 
Forum), to further develop 
and promote the PMBus 
power operating system. The 
SM-IF comprises the PMBus 
Implementers Forum and the 
Smart Battery System Imple- 
menters Forum. SM-IF will 
also take over responsibility 
for the SMBus. 

The SMBus is essentially 
compatible with the PC bus, a 
popular two-wire bus that 
handles inter- IC control. "The 
PC bus is a highly prevalent 
interface on embedded mi- 
croprocessors; it's just all over 
the place," says Michael Ste- 
fani, director of product mar- 



keting for Artesyn. "SMBus 
adds an alert line to PC, mak- 
ing it just a short step from PC 
to SMBus." 

In addition to Artesyn, the 
initial coalition comprises 
Astec Power and semiconduc- 
tor manufacturers Intersil, 
Microchip Technology, Texas 
Instruments, Volterra Semi- 
conductor, Summit Micro- 
electronics, and Zilker Labs 
(www.astecpower.com, www. 
intersil.com, www.microchip. 
com, www.ti.com, www.vol 
terra.com, www.summit 
micro.com, www.zilkerlabs. 
com). 

Conspicuously absent from 
the SIG is Power-One (www. 
power-one.com), which last 
year launched its proprietary 
Z-One bus and in December 
announced a design, manu- 
facturing, and marketing 
agreement with C&D Tech- 
nologies (cdtechno.com). Ac- 



cording to Dave Hage, execu- 
tive vice president of Power- 
One, "For complex systems, 
PMBus does not provide a 
configuration- controlled, 
standardized programming 
interface like the Z-One GUI. 
Lack of standardization in 
PMBus converters could 
make the creation and man- 
agement of a uniform PMBus 
GUI virtually impossible." 

Hage also points out that a 
bus architecture is overkill 
and adds too great an expense 
for some low-end designs. 
"For low- complexity systems, 
customers have requested a 
configurable point-of-load 
supply that does not require a 
bus and is more cost-effec- 
tive." Power-One developed 
its "no-bus" ZIOOO supplies 
for these applications. 

— by Margery Conner 
►Artesyn Technologies, 
www.artesyn.com. 
►System Management In- 
terface Forum, www.power 
sig.com. 

►Power Management Bus 
Implementers Forum, 

http://pmbus.info/specs. 
html. 



By Scott Adams 



I NEED A DESCRIPTION 
OF YOUR PROJECT AND 
ITS PROTECTED COST. 



THATS 
IMPOSSIBLE, 




THE PROJECT UNCER- 
TAINTY PRINCIPLE SAYS 
THAT IF YOU UNDER- 
STAND A PROJECT. YOU 
UON T KNOW ITS COST. 
AND VICE VERSA. 





THAT 

DOESN'T 
(AAKE IT 
WRONG. 



WI-FI CHIP ATTACH- 
ES VIA PCI EXPRESS 

Broadcom has released what it 
claims is the first 802.11 wire- 
less-LAN chip that supports 
the PCI Express bus architec- 
ture. The 802.1 la/g BCI\/14311 
baseband processor integrates 
a MAC (media-access con- 
troller). The chip's all-CMOS 
design, high integration, and 
small footprint provide design 
flexibility for wireless-enabled 
notebook PCs, printers, and 
other client devices, according 
to Broadcom. "This is a wire- 
less-LAN chip set with our 
BroadRange technology, 
which allows devices to hear 
better in noisier environments 
with 2- and 5-GHz-band 
radios," says Brian Bedrosian, 
Broadcom's senior product- 
line manager for wireless-LAN 
clients. 

The BroadRange DSP tech- 
nique allows devices to stay 
connected at distances as 
much as 50% farther from a 
wireless router than previous- 
generation technologies, 
according to the company. 
The chip's lead-free package 
and more efficient footprint 
make it a good fit for next- 
generation PC designs. 

The device works with the 
company's OneD river soft- 
ware, which offers various fea- 
tures, including SecureEasy 
Setup software and 125 high- 
speed mode, to augment the 
Wi-Fi (wireless-fidelity) net- 
work. The software aims to 
make setup and configuration 
user-friendly, and the high- 
speed mode delivers as much 
as 40% greater throughput 
than most other 802.1 Ig and 
802.1 la/g systems. Broad- 
com's BCM4311, available 
now in sample quantities, 
costs $10 (10,000). 

-by Jeff Berman 
►Broadcom, www.broadcom. 
com. 



►The No. 1 thing consumers search for when they go to the Ask Jeeves search engine is the name of rival search engine "Google," accord- 
ing to Hitwide Inc, a researcher that analyzes the online activities of 10 million US consumers. 



16 EDN I April 28, 2005 



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J 



Midpriced, 1.5-GHz-bandwidth DSOs 
provide an array of features 



ACCORDING TO Boyd Shaw, 
product manager of Yo- 
kogawa Corp of Ameri- 
ca's Test and Measurement 
Division, the company's DSOs 
(digital storage oscilloscopes) 
are among the best kept se- 
crets in the US electronics in- 
dustry. Shaw says that YCA's 
scope sales place it fourth in 
the United States but that the 
Japan -headquartered compa- 
ny does far better not only in 
Asia, but also in Europe. Shaw 
beheves that YCA's US DSO 
market share will receive a big 
boost from the introduction 
of the DL9000 series, which 
includes four four- channel, 1- 
and 1.5-GHz-bandwidth real- 
time-sampling scopes, whose 
prices start at $10,995. 

In the two-channel mode, 
the 1-GHz units acquire 5G 
samples/sec on each channel. 
(With all channels active, the 
sampling rate drops to 2.5G 
samples/sec on each channel.) 
The 1.5-GHz units can sam- 
ple twice as fast. At each band- 
width, you can choose be- 
tween units with maximum 
memory depth of 2.5 or 



6.25M samples/channel. 

The scopes provide an im- 
pressive array of operational 
and connectivity features, 
some of which may be unfa- 
miliar to users of US-manu- 
factured DSOs. For example, 
most US suppliers have now 
standardized on color grading 
to indicate the duty ratio of 
pixel illumination. YCA, how- 
ever, is sticking with intensity 
modulation, not, as you might 
think, because intensity mod- 
ulation is less expensive or 
easier to implement than col- 
or grading — in a DSO, it is 
not — but because many users 
fmd intensity-modulated dis- 
plays more intuitive. In this 
regard, the DL9000s' intensi- 
ty-graded displays mimic ana- 
log-scope displays in a way 
that many users are bound to 
find more informative and 
user-friendly than color-grad- 
ed displays. 

The DL9000 designs go to 
great lengths to rapidly ac- 
quire lots of waveforms with 
minimal time between acqui- 
sitions and to quickly display 
the acquired data in the most 




DL9000 series scopes do a few things that some other DSOs can't do. For 
example, DL9000S can display Lissajous figures (lower half of the screen). 



meaningful ways. By segment- 
ing memory when the record 
length is shorter than the full 
memory depth, the scopes can 
acquire waveforms with min- 
imal time between acquisi- 
tions. One display mode uses 
the intensity- grading feature 
to create a single display that 
overlays the multiple acquisi- 
tions. However, all data from 
each acquisition remains in 
memory, and you can individ- 
ually inspect each waveform 
to search for anomalies. If the 
accumulated length of all 
waveforms exceeds the mem- 
ory depth, the unit discards 
the oldest acquisitions from 
the FIFO memory. 

Other features include both 
front- and rear-panel USB 
ports, an optional lOOBase- 
TX/lOBaseT Ethernet inter- 
face, a trigger-comparator 
output for use with external 
equipment, a go/no-go out- 
put for use in production test- 
ing, an optional built-in strip - 
chart recorder, and two 
PCMCIA slots. (By installing 
an appropriate card in one of 
these slots, you can add an 
IEEE 488 interface.) The units 
have many built-in filtering 
and statistical functions. Un- 
like most Windows-based 
DSOs, these scopes run under 
a ROM -resident version of 
Windows CE. Shaw says that 
the results are faster start-up, 
greater operational stability, 
and more room for your data 
on the optional 20-Gbyte in- 
ternal hard drive. 

— by Dan Strassberg 
►Yokogawa Corp of America, 
1-770-254-0400, www.yoko 
gawa.com/us/. 



VOIP-ADAPTER 
DESIGN BOASTS 
$6 PRICE 

Telecommunications and net- 
working vendor Vocal 
Technologies has rolled out a 
line of VOIP (voice-over- 
Internet Protocol) ATA (analog- 
telephone-adapter) designs, 
including a simple ATA with a 
$6 BOM (bill-of-materials) cost 
and a full-motion IP video- 
phone with a $30 BOM. 

The designs employ DSP 
resources and thereby elimi- 
nate the need for an addition- 
al RISC processor, according 
to the company. The adapter 
design offers a single PSTN 
(public-switched-telephone- 
network) port and connects to 
a PC via USB. The design sup- 
ports two telephone lines, two 
Ethernet lines, and a PSTN 
"life-line" port for automated 
voice-service switching in the 
event of a power outage or a 
network disconnection. 

John Blume, Vocal's chief 
executive officer, says that 
these designs reduce the 
number of common building 
blocks and components nec- 
essary for developing ATAs. 
"Our approach to ATA is differ- 
ent from many others, be- 
cause we eliminate the RISC 
processor, which, in turn, 
drives down the BOM for 
designers," Blume says. When 
developing its designs. Vocal 
looked at alternatives using 
both DSPs and RISC proces- 
sors and found that a recent- 
generation DSP is suitable for 
running the entire application. 
"The idea here is to take away 
most of the mystery for 
designers and suppliers, so 
that they have what they 
need," Blume says. 

-by Jeff Berman 
►Vocal Technologies, www. 
vocal.com. 



►According to a recent report from IBM, 76% of all e-mails in February 2005 were spam, down from a summer 2004 peak of nearly 95%. 

18 EDN I April 28, 2005 www.edn.com 




FPGA Design | Ever feel tied down because your design tools didn't support the FPGAs you needed? Ever spend a weekend 
learning yet another new design tool? Maybe it's time you switch to a truly vendor independent FPGA design flow. One that 
enables you to create the best designs in any FPGA. Mentor's full-featured solution combines design creation, verification, 
and synthesis into a vendor-neutral, front-to-back FPGA design environment. Only Mentor can offer a comprehensive flow that 
improves productivity, reduces cost and allows for complete flexibility, enabling you to always choose the right technology 
for your design. To learn more visit us at www.mentor.com/techpapers or call us at 800.547.3000. 



©2005 Mentor Graphics Corporation. AIL Rights Reserved. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. 

Enter 1 at www.edn.com/info 



^Menlor 
Graphics 



Structured ASIC offers memory-for-logic swapping 



Configurable-core and 
structured- ASIC vendor eAS- 
IC Corp and its partner Flex- 
tronics Semiconductor have 
released a structured ASIC 
that allows users to configure 
the amount of logic, memo- 
ry, and reprogrammable log- 
ic they need for a given design. 
The company's executive vice 
president for marketing, Ron- 
nie Vasishta, says that the 
new FlexASIC 




Implemented on 0.13-micron 
STMicroelectronics silicon, the 
FlexASIC architecture boasts as 
many as 3 million ASIC gates, as 
much as 1.5 Mbits of SRAM, and 
operation as fast as 400 MHz. 

fabric gives users the best of 
the FPGA and the ASIC 
worlds: the density and speed 
associated with ASICs with- 
out the NRE (nonrecurring- 
engineering) costs and the 
programmability of FPGAs 
without the power and per- 
formance shortcomings. 
"FlexASIC offers a 25- to 30- 
times density improvement 
over FPGAs with power den- 
sity and performance akin to 
cell-based design," says Vasish- 
ta, claiming FlexASIC operates 
at approximately 400 MHz. 

The FlexASIC architecture 
boasts a field of proprietary 
SRAM three-input LUT (look- 
up-table) -based logic cells. 



called eCells (embedded cells), 
surrounded by embedded- 
SRAM blocks, PLLs, an 8051 
microcontroller, and ROM 
blocks. Configurable I/O sur- 
rounds all of these blocks. The 
FlexASIC architecture allows 
users to swap eCells for extra 
SRAM if a design requires. For 
example, the biggest device in 
the FlexASIC family, the 
FA3000, boasts 3 million ASIC 
gates in the form of 92,000 
eCells, or 194,000 LUTs, plus 
2.8 million bits of embedded 
single-port SRAM. 

Designers can configure 
some eCells after fabrica- 
tion to reprogrammable- 
logic blocks. The compa- 
nies program a de- 
vice's eCells, RAM, and 
embedded RAM dur- 
ing fabrication using 
"e-beam" technology, 
which customizes the vias be- 
tween the sixth and seventh 
layers of the eight-layer pro- 
cess. The routing customiza- 
tion differs from program- 
ming the logic and pro- 
grammable-logic blocks. The 
companies use a bit stream for 
this programming and can re- 
load the blocks for debugging 
after fabrication. 

The companies also built a 
clock tree into the fabric, 
which means that users need 
not build it but also that they 
can t adjust it. The companies 
offer users two design flows to 
configure and program the 
devices. Using the first flow, 
designers feed a Verilog or 
VHDL netlist into Synopsys' 
(www.synopsys.com) Design 
Compiler, which creates a 
gate-level netlist. Users then 
perform chip -resource alloca- 
tion, assigning memory, clocks, 
and I/O on the design. Then, 
using a proprietary eTools 
suite, users perform mapping, 
placement, and, with technol- 



ogy from OEM Golden Gate 
Technology (www.ggtcorp. 
com), global routing. Users 
then perform final routing, 
finishing, and BIST (built-in 
self-test) with eASIC tools. 
They can use any vendor's 
tool to perform ATPG (auto- 
matic-test-pattern-genera- 
tion) testing. With the second 
flow, users feed a Verilog or 
VHDL netUst into an eAS- 
IC\Flextronics-only version of 
Magma's (www.magma-da. 
com) Blast SA, which incor- 
porates the Aplus physical- 
synthesis tool. The tool per- 
forms synthesis and place- 
ment and then feeds into 
eASIC's router, finishing tools, 
and BIST. As with the other 
flow, users can perform ATPG 
with any vendor's tool. 

The companies currently 
fabricate the FlexASIC devices 
on STMicroelectronics' (www. 
st.com) 130-nm process. The 
companies claim that cus- 
tomers incur no NRE charges; 



eASIC and Flextronics accom- 
modate low-volume orders 
because they can implement a 
number of customers' designs, 
even if targeting a different 
part number of the eASIC 
family, on a single wafer. Va- 
sishta says that companies 
have ironed out the lithogra- 
phy and design-for-manufac- 
turing issues. A debugging 
technology is available, but 
customers can receive sample 
silicon as early as two weeks 
after tape-out so they can test 
their designs in their systems 
in real time. Package support 
for the family ranges from 
100-pin TQFPs to 896-pin 
FBGA packages; eASIC is cur- 
rently receiving tape -outs 
from beta customers and ex- 
pects prototyping silicon by 
May and production silicon 
by July. 

— ^by Michael Santarini 
►eASIC, www.easic.com. 
►Flextronics, www.flextron 
ics.com. 



Even jacks are getting smarter 

Though not the first jacks in audio's history with an 
auxiliary function, a new series from FCI USA brings the 
concept to the 38.5-mm-high BTX (Balanced Technology 
Extended) form factor, as well as to the 3 8. 5 -mm- tall 
jacks for the ATX (Advanced Technology Extended) form 
factor. The company's Smart Audio Jack series of triple- 
stack connectors features an isolated switch 
so that associated circuitry can detect con- 
nector presence and also sense when a mi- 
crophone, an audio input, or a speaker is 
plugged into the port. (Some designs use an 
electronic- circuit technique to make the 
same determination, but that approach can 
become complex because the jack must 
sense a completed — but highly variable and 
uncontrolled — signal path.) 

The color- coded jacks, targeting 192-kbps, high-deflni- 
tion audio designs, have initial 50-mH contact resistance 
and are rated for lA current and 1000 insertion cycles. 
Price is 32 cents to 68 cents (1000), depending on conflg- 
uration. — by Bill Schweber 
►FCI USA, www.fciconnect.com. 




20 EDN I April 28, 2005 



www.edn.com 



1 1 

4 



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RPM 
X1000 



-7 




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Today's must-have notebook PCs feature supercharged performance, great battery life, sleek designs 
and dual-channel DDR2 memory. Get it from the DDR2 leader, Samsung, with the broadest selection 
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Enter 1 1 at www.edn.com/info 



FPGA development kit targets designs ttiat race 



MERCURY Computer Systems has rolled out a 
development kit supporting the company's 
FPGA computing systems that employ its high- 
speed Race++ switch fabric. The FDK (FPGA 
Compute Node Developer's Kit) 2.0 platform, 
which includes software, IP (intellectual property). 



and design consultation, of- 
fers the interconnect, com- 
munications, command and 
control, memory, and I/O 
functions for flexibility and 
quick deployment, according 
to the company. 

The kit supports the com- 
pany's IP cores for the ROC 
(Race-on-chip) high-band- 
width interconnect, a patent- 



pending technology that ex- 
tends the fabric inside the 
FPGA to access other IP 
cores, such as high-speed 
DRAM, SRAM, sensor-I/O, 
and system-level fabric inter- 
faces, according to the com- 
pany. The kit supports the 
PCI-based VantageRT FCN 
(FPGA-based compute node) 
and VME-based MCJ6 FCN 



systems. Both of those prod- 
ucts feature multimillion- 
gate Xilinx (www.xilinx. 
com) FPGAs connected to 
Race + + , which is Mercury's 
implementation of the indus- 
try-standard Raceway Inter- 
link high-performance inter- 
connect fabric. 

Rich Jaenicke, Mercury's 
director of product manage- 
ment, says that FDK 2.0 helps 
users load bit streams into 
their FPGA and IP, providing 
an FPGA interface to compo- 
nents such as memories, 
switch fabric, and I/O. "Users 
have data streaming from a 
sensor into an I/O interface 
and are computing and stor- 
ing data in memory and send- 
ing results over the switch fab- 
ric," Jaenicke says. "We are 



providing infrastructure in- 
terfaces, which are helpful for 
our customers, because this 
approach allows them to fo- 
cus on algorithms and not 
have to spend time on infra- 
structure." Engineers will also 
fmd the kit beneficial because 
it includes a dual DMA mas- 
ter/slave switch-fabric end- 
point. "Switch fabrics are all 
the rage now, and this IP says 
that we have the switch fabric 
and all the protocol layers di- 
rectly on the chip," Jaenicke 
says. FDK 2.0 is available now 
and costs $23,000 for the first 
development seat, which in- 
cludes 20 hours of develop- 
ment support. 

— by Jeff Berman 
►Mercury Computer Sys- 
tems, www.mc.com. 



Single-chip FM tuner enables embedded broadcast receiver 



What would EH Armstrong say? The FM (and super- 
heterodyne) pioneer never envisioned an all-CMOS, sin- 
gle-IC FM tuner, such as the Si470x series from Silicon 
Laboratories. This highly integrated, 4X4-mm digital com- 
ponent needs just a bypass capacitor and takes less than 20 
mm^ of board space overall, far less than the typical ap- 
proach, which requires a 6X6- mm IC, more than 30 sup- 
port components, and 150 mm^ of space. 

The single-chip tuner, the vendor asserts, is the indus- 
try's first all-CMOS device. It simplifies embedding a con- 
ventional broadcast FM receiver, spanning 76 to 108 MHz, 
into a cell phone or an MP3 player, for example, and thus it 
is "easy and cost-effective to add FM radio as a 
standard feature to virtually any application," 
according to Ed Healy, vice president at Silicon 
Labs. And, even if you think broadcast radio is 
dead, many consumers do not; it is increasingly 
a feature on portable wireless devices. 

The Si4700 version needs no alignment. It 
includes the required filtering, AGC (automatic 
gain control), a frequency synthesizer with a 
VCO (voltage-controlled oscillator), a low- 
dropout amplifier for direct battery connec- 



tion, and audio-processing functions. The Si4701 adds an 
integrated preprocessor for the European RDS (Radio Data 
System) and the US RBDS (Radio Broadcast Data System) 
formats at a 57-kHz offset, which adds station ID and song 
name along with the music and allows alternate -channel 
(frequency) information, which European radio provides, 
in which a single broadcaster uses multiple frequencies. 

The Si4700 sells for $3 (10,000), and the Si4701 sells for 
$3.50. The companion evaluation board costs $150. 

— by Bill Schweber 
►Silicon Laboratories Inc, www.silabs.com. 




The all-digital, CMOS Si470x FM tuner does it all and in a 4X4-mm package, allow- 
ing designers to easily incorporate broadcast tuning into wireless handheld products. 



►Checks accounted for 45% of all payments that were not made with cash in 2003, down from 57% in 2000, and 32% of US households 
used the Internet to pay bills in some fashion in 2004, according to TowerGroup. 



22 EDN I April 28, 2005 



www.edn.com 



Two complex RF signals. 
Three rms values. One IC. 




AD8364 TruPwr Detector 

• RMS power measurement from low frequency to 2.7 GHz 

• Simultaneous dual-channel with difference output ports 

• Integrated on-chip temperature sensor output 

• Wide dynamic range: 60 dB @ 2.2 GHz 

• Precision temperature-stable linear-in-dB rms outputs: ±0.5 dB 

• Operation: single 5 V supply, -40°C to +85°C 

• Price: $7.85 in 1k quantities 

The AD8364 features a small footprint, 
5 mm X 5 mm LFCSP package and provides 
lower cost and design-time advantages compared 
to logarithmic and discrete alternatives. 



Introducing the industry's first dual-channel rms detector. 

Accurately measuring complex, high order modulation signals, such as 
CDMA or OFDM, has long been one of the most difficult challenges RF 
designers face. With our introduction of the AD8364 TruPwr detector, 
designers will be able to precisely measure two rms values as dc 
outputs, along with a difference output between the two inputs and 
monitor temperature, in one IC. The AD8364 has the ability to measure 
signals with up to 60 dB of dynamic range and is independent of input 
frequencies up to 2.7 GHz, enabling the control of gain or loss within a 
transceiver. Or, with both inputs at the same frequency, the AD8364 can 
monitor a power amplifier's gain or VSWR. For more information, or to 
view the data sheet, please visit our website. 





www. analog. com/TruPwr 



ANALOG 
DEVICES 



THE LEADER IN HIGH PERFORMANCE ANALOG 



Signalintegrity Ry Hmnard Inhnsnn PhD 



Crosstalk in differential 
viaswith grounds 

IN 2002, THE XFP (10-Gbit small-form-factor plug- 
gable-module) committee, working on standards for 
10-Gbps interconnections, published some terrific 
guidelines for high-speed differential vias (Reference 1). 
The guidelines propose surrounding your differential pair 



with an oval clearance and pinning 
the reference planes together at 
either end of the clearance hole 
with ground vias (Figure 1). 

The guidelines assume that no 
long dangling via stubs connect to 
your signal path, meaning that 
either (a) your signal goes all the 



DRILL 0.3 mm 
PAD 0.56 mm 




GROUND VIA 
GROUND PLANE 
OVAL CLEARANCE 



0.7 TO 1.0 mm 



POWER CLEARANCE 



Figure 1 



These proposed pc-board-layout 
dimensions for 10-Gbps stan- 



dards help with proper performance. 



TABL 



^CROSSTALK IN MILLIVOLTS 
WITH GROUND VIAS 



Row/Column 





1 


2 


3 


4 


5 








42 


5 


1 








1 





23 


1 











2 





3 


2 











3 





3 














4 


1 







































L/Jj]l ^ CROSSTALK IN MILLIVOLT^ 


PirrH GROUND VIAS REMOVED ' 


Row/^o'"*"" 





1 


2 


3 


4 


5 








85 


27 


13 


7 


5 


■l 





14 


15 


10 


6 


4 


2 


35 


14 


1 


4 


4 


3 


^ 3 


14 


10 


3 





1 


2 


4 


8 


6 


4 


1 





1 




5 


4 


3 


2 


1 






way from the top layer to the bot- 
tom, or (b) in a less-than-full- 
length transition, you have cut off 
the dangling ends of the via 
beyond the point at which signal 
current actually flows. 

In boards as thick as 100 mils and 
with rise times on the order of 100 
psec, the recommended struc- 
ture produces a good, lOOH 
transition between layers. 

If you want to use this 
design in a dense architecture, 
you need to know about the 
crosstalk between these struc- 
tures. To make the math easy, I 
will assume your layout pro- 
vides a uniform grid of possi- 
ble via locations, with a grid 
spacing of 0.8 mm and hole 
diameters of 0.3 mm. Index 
the grid by rows and columns. 

Place one installment of the 
layout from Figure 1 with the 
topmost via at position Row 
0, Column 0. The crosstalk 
voltages (millivolts) into this 
spot from other possible via 
locations appear in Table 1. 
For example, placing an 
aggressor pair one position to 
the right (one column over), 
the crosstalk from Table 1 in 
position Row 0, Column 1, 
reads 42 mV. I did these quasi- 
static calculations using 
MathCad. 

Because the layout in Fig- 
ure 1 is four positions long, 
if you stay in the same col- 
umn, the closest you can place 
the next structure (shifting 




straight down) is four units. The 
shaded areas in the table designate 
impossible positions. 

This table assumes a 2V p-p dif- 
ferential signal (that is, IV p-p on 
each wire), driving 100H differen- 
tial traces with 100-psec rise and 
fall times. The important aspect of 
this specification is the total 
change in current per unit time 
(dl/dt). Crosstalk in millivolts 
scales in proportion to dl/dt. If you 
have a lower voltage, a slower rise 
time, or a larger trace impedance, 
then scale down the numbers in 
Table 1 according to the extent of 
that difference in your architec- 
ture. As the table shows, crosstalk 
quickly plummets to small values 
as you separate aggressor from vic- 
tim. Enforcing white space be- 
tween signals is the surest way to 
guarantee low crosstalk. 

What happens if you omit the 
ground vias? In that case, signals 
pass through the via in much the 
same way, but the crosstalk floats 
generally higher. More important, 
crosstalk falls off less rapidly with 
distance (Table 2). Ground vias 
help contain the electromagnetic 
fields emanating from each differ- 
ential structure, arresting the 
spread of crosstalk. □ 

Reference 

1. 10-Gigabit small- form- factor 
pluggable module. Revision 2.0, 
XFP multisource agreement. 

Howard Johnson, PhD, author of 
High-Speed Digital Design and 
High-Speed Signal Propagation, 
frequently conducts technical work- 
shops for digital engineers at Oxford 
University and other sites world- 
wide. howie03@sigcon.com. 

Talk to us 

Post comments via TalkBack at the 
online version of this column at 
www.edn.com. 



24 EDN I April 28, 2005 



www.edn.com 




UNLEASH BROADBAND WITH 
FUJITSU'S WiMAX 802.16-2004 SoC. 



With a MAC-to-PHY implementation based on the 
IEEE 802.16-2004 broadband wireless access 
standard, the Fujitsu WiMAX SoC, MB87M3400, 
offers a cost-effective solution for both subscriber 
station and base station applications. This highly 
integrated SoC implements MAC, PHY, radio 
control and all the necessary analog circuits for the 
appropriate 2 to 11 GHz licensed or license-exempt 
bands. The Fujitsu WiMAX SoC fully complies with 
the IEEE 802.16-2004 standard using an OFDM PHY. 

ADVANCED FEATURES 

• 256 OFDM PHY with 64QAM, 16QAM, 
QPSK and BPSK modulation 

• Uplink subchannelization 

• Flexible baseband interface with integrated 
high-performance ADC and DAC 

• Security implementation using DES, CCM 
encryption/ decryption 

• Rich set of integrated peripheral and RF control 




For more information, call (800) 866-8608 or 
visit http://us.fujitsu.com/micro/wimax 



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THE POSSIBILITIES ARE INFINITE 

Enter 12 at www.edn.com/info 



edn.COmment By Jnhn Dodge, Editor in (Ihief 




Perception problem dogs engineering 



LURING COLLEGE-BOUND STUDENTS into engineering 
has never been more difficult. From an attractiveness 
standpoint, engineering enjoyed brief life during In- 
ternet's early years, but has since returned to the more con- 
servative realm that encourages only math and science 



geeks. Since 1990, the number of 
bachelor's degrees in engineering 
has dropped 8%. More disturbing is 
a 20% decline in math degrees 
(Link l).The reason for these de- 
clines is twofold, according to Ge- 
offrey Orsak, School of Engineering 
dean at SMU (Southern Methodist 
University): One is that high-school 
students often shun science and 
math; most avoid taking them in 
college if they can. The other prob- 
lem is image, and we can do some- 
thing to improve it, contends Orsak, 
who is the antithesis of the engi- 
neering stereotype that, fairly or 
unfairly, has long tarnished the pro- 
fession s image. 

"Most believe it's one of the 
toughest majors, and so we are 
competing over a very small group 
of kids. But clearly engineering has 
an image problem even more than 
the perception that it's a challeng- 
ing discipline," he says. That salaries 
for new engineers are among the 
highest compared with other pro- 
fessions doesn't seem to matter. 
"People see it as a bridge career 
from lower working class to a mid- 
dle-class career. Once you reach that 
level, you want to go beyond it into 
law, medicine, and business leader- 
ship," he says. 

That idea surprises me. I always 
admired people with a strong apti- 
tude for math and science, probably 
because the two were not my strong 
suits. My civil- engineer uncle built 
interstates for 39 years, and I admire 
him. As a 19-year-old, his formida- 
ble math skills and intestinal forti- 
tude landed him in the navigator's 
seat of a B -24 during World War II 



and in an Rensselaer Polytechnic 
Institute classroom after that on the 
GI Bill. My 17-year-old son just 
aced the SAT II test in math. What 
does he want to be? A lawyer. 

The decline in US engineers has 
become more noticeable because 
developing economies in countries 
such as China are cranking out new 
ones at four to six times the rate in 
the United States. And strong 



Jack Welch is a chemical engineer. 
Jimmy Carter is a nuclear engineer. 
Yasir Arafat was a civil engineer 
(Link 2). "If a doctor develops a 
new surgical technique, we cele- 
brate it. We don't do that in engi- 
neering. I could name 10 famous 
doctors, but I could not name 10 fa- 
mous engineers," says Orsak. That's 
why SMU has partnered with Texas 
Instruments to develop the Infini- 
ty Program, which attempts to dis- 
pel the myths and stereotypes that 
plague engineering in high-school 
classrooms (Link 3). The program 
trains high-school math and sci- 
ence teachers to make engineering 
fun, cool, interesting, and accessible 
to broader range of prospects. 

That the numbers of new engi- 
neers hasn't changed for decades in- 



WE CAN'T LOWER THE ACADEMIC BAR, SO WE HAVE 
TO INSTEAD SPRUCE UP ENGINEERING'S IMAGE. 



growth in retirements as the engi- 
neering workforce ages will com- 
pound the problem. More than half 
of the engineers in the United States 
are older than 40, says the NSB re- 
port. 

What can the United States do 
about this problem? Clearly, we 
can't lower the academic bar, so we 
have to instead spruce up engineer- 
ing's image. "We have to celebrate 
our people. As long as we continue 
to view engineering as about widg- 
ets and not about people, we will 
have a perception problem," says 
Orsak. Engineering needs highly 
visible heroes, just as the business 
world has Michael Dell and Bill 
Gates. Such heroes motivate stu- 
dents to take a similar path. But en- 
gineering has plenty of Dells and 
Gates. The problem is that they gen- 
erally don't seek recognition, ex- 
cept, perhaps, from peers. There are 
plenty of successful engineers, but 
they either labored in obscurity or 
took another path. Former Gener- 
al Electric Chief Executive Officer 



dicates the magnitude of the prob- 
lem. And what we do now to 
convince more high-school stu- 
dents to choose engineering won't 
pay off in national competitiveness 
for a decade. Currently, approxi- 
mately 65,000 engineers a year 
graduate from US schools, says Or- 
sak. "It's never been over 100,000 
and never below 50,000 for the past 
30 years. But many more kids go to 
college today, and we thought a ris- 
ing tide would lift all boats." □ 

Do you have an engineering hero? 
Write me atjohn.dodge@ 
reedhusiness.com. 

Links 

1. "Science and Engineering In- 
dicators 2004," National Science 
Board, www.nsf.gov/sbe/srs/seind 
04/cO/cOsl.htm. 

2. The Encyclopedia Britannica, 
www.britannica.com/nobel/micro/ 
30_l.html. 

3 . www. infmity-pro j ect . or g/j oin/ 
join_video.html. 



26 EDN I April 28, 2005 



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designfeature Ry David Mar,<^h, CnntrihutinQ Technical Editor 



THE GROWTH OF ELECTRONIC SUB- 
SYSTEMS IN VEHICLES DEMANDS 
NETWORKS FROM THE MISSION- 
CRITICAL TO THE MUNDANE. THE 
LOCAL-INTERCONNECT-NETWORK 
PROTOCOL TACKLES THE TASK. 




LIN simplifies 
and standardizes 

IN-VEHICLE NETWORKS 



WITH PREDICTIONS Suggesting a global annual- compound- 
growth rate of some 8.3% over the next five years, the 
automotive sector continues to be our industry's fastest 
growing market. It's sobering to consider that, barely 20 years 
ago, the sole electronics content within most vehicles was a ra- 
dio. Then came the electronic ignitions, engine-management 
units, and antilock-braking systems that are standard in today's 
entry-level cars. Now, of course, vehicles include previously un- 
heard-of luxuries, and top-of-the range vehicles adopt sophis- 
ticated electronics, such as intelligent cruise controls that auto- 
matically maintain a safe distance from the vehicle ahead. 
Estimates suggest that the electronics content of an average car 
now accounts for no less than 22% of its manufacturing cost, 
creating markets for the embedded controllers, power devices, 
and communications technologies that link its ECUs (electron- 
ic-control units). 

Recognizing the need for a robust in-vehicle network to man- 
age distributed intelligence and reduce wiring-harness dimen- 
sions, Bosch in 1986 designed a CAN (controller- area network). 
Today, CANs dominate in-vehicle networking and have also 
made the transition to multiple industrial uses. In the meantime, 
other networking systems have appeared to tackle emerging au- 
tomotive applications. These technologies include D2B (do- 
mestic-digital-databus), FlexRay, and MOST (media-oriented 
system transport), aU of which employ fiber media for speed and 
EMC resistance. TT-CAN (time-triggered extensions to CAN) 
improve the protocol's determinism, as well as the TTP (time- 
triggered-protocol) series that competes with FlexRay for safe- 
ty-critical use (Reference 1). Because these systems serve \vv^- 

www.edn.com 



end applications and are relatively expensive, designers require 
a low-cost alternative to serve mundane tasks, such as to con- 
trol body functions from seats to sunroofs. As a result, car mak- 
ers increasingly embrace LINs (local- interconnect networks), 
which position themselves at the lowest level in the automo- 
tive-networking hierarchy (Figure 1). 

The first LIN specification appeared in 1999. Among the 
founding members of the LIN Consortium, its design authori- 
ty, are car makers BMW, DaimlerChrysler, Volkswagen Audi 
Group, and Volvo Cars, together with hardware and networking 
expertise from Freescale Semiconductor and Volcano Automo- 
tive Group. Design influences include the Vlite bus that several 
car makers use, as well as lessons accruing from many years of 
CAN evolution and development. Several amendments culmi- 
nated in LIN Version 1.3 in November 2002, which many ob- 
servers regard as the first stable release. Further work resulted 
in a major revision that appears as the current Version 2.0 of Sep- 
tember 2003, which the LIN Consortium recommends for all 
new development. 

Meanwhile, in North America, the Society of Automotive En- 
gineers issued its J2602 recommended practice, "LIN Network 
for Vehicle Applications," with key car-maker representation 
coming from Ford and General Motors. The main differences 
between LIN 2.0 and J2602 include limiting the transmission 
rate to 10.4 kbps and modifying some protocol details, such as 
error handling. Some observers feel that J2602's objectives in- 
clude limiting feature creep, thus making it easier to meet LIN's 
overriding low-cost target using, for example, state-machine log- 
ic rather than microcontroller-based intelligence. 

April 28, 2005 | edn 29 



Master your 
next design 
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are registered trademarks of National Semiconductor Corporation. AU rights reserved. 



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Na tional 

Semiconductor 

The Sight & Sound of Information 



designfeature Loc al- in t erconn e ct n et works 



The LIN Consortium s objectives for its 
new system don't stop with low cost, al- 
though, because LIN is markedly cheap- 
er than CAN or the J 1850 domestic-US 
standard, cost is the prime driver. In fact, 
with original predictions for LIN lying at 
around $l/node, it is currently proving 
hard to meet this cost target. But, in its 
primary role as a sub-bus, LIN's design 
ensures that it functions as a logical and 
scalable extension of CAN and J 1850. It 
provides acceptable reliability for non- 
safety- critical tasks, with less-than-100- 
msec response times and predictable 
worst-case timing characteristics. Learn- 
ing from previous bus evolutions, the de- 
velopers were also careful to consider 
tool-chain-support issues. Such consider- 
ations have become crucially important as 
the car makers forge seamless co-devel- 
opment links with their system suppliers. 

Naturally, the specification must ensure 
hardware and software interoperability 
among multiple vendors, as well as min- 
imizing peripheral but critical issues, such 
as EMC. From the outset, LIN's specifi- 
cations accordingly subdivide into three 
main parts that describe the transmission 
medium and its communication proto- 
cols, a configuration language, and APIs 
(application-programming interfaces) 
(Figure 2). Representing the lowest two 
levels of the ISO/IEC 7498-1:1994 open- 
systems-interconnect model, the protocol 
specification tackles the physical-layer 
and data-link-layer mechanisms. At the 
highest level, an API abstracts the user's 
code from lower level network mechan- 
ics; in between, a signal interaction and 
diagnostic layer decouples the application 
from the network. To furnish a standard 
interface between LIN nodes from mul- 




AT A GLANCE 

> LIN (local-interconnect network) chal- 
lenges CAN (controller-area network) for 
lowest cost in noncritical applications. 



> Version 2.0 introduces new plug- 
and-play capability but costs memory. 



> Vendors offer a dazzling palette 
of hardware support. 

> Future growth prospects include 
consumer goods and industrial use. 



tiple suppliers, the LIN configuration- 
language description defines the format 
of the files that configure the network. 
These configuration files also provide 
hooks into development tools. In a fur- 
ther and major forward step, 2.0 intro- 
duces the LIN-node-capability language, 
easing integration via a plug-and-play 
concept (see sidebar "LIN 2.0 goes plug 
and play" on the Web version of this arti- 
cle at www.edn.com). 

ONE-WIRE MASTER/SLAVE ARCHITECTURE 

To minimize cost and wiring weight, 
LIN uses a single-conductor, wire-OR 
bus that takes advantage of a car's body 
shell to serve as a common ground. Each 
LIN subnet comprises one master and at 
least one slave node to a maximum of 16 
devices per bus. Nodes can participate on 
more than one LIN bus, and masters may 
also operate as bridges into other net- 
work environments, typically CANs. 
Maximum transmission speed and reach 
are 20 kbps and 40m, respectively, using 
UART/SCI communications. This tech- 
nology makes LIN implementations pos- 



DATA RATE 

(BITS) 



EMBEDDED CONTROL 



MULTIMEDIA 



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OPTICAL RING 



I FLEXRAY, TTX 



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TIME TRIGGERED (TDMA) 
FAULT TOLERANT, 
DEPENDABLE 
2X2-WIRE/0PTICAL 




I LIN 

I TIME TRIGGERED 
MASTER-SLAVE 
SINGLE WIRE, 
NO QUARTZ 



CAN-B 

ARBITRATION 
FAULT TOLERANT 
DUAL WIRE 



BLUETOOTH 

WIRELESS MEDIUM 



J 



_l_ 



Figure 1 



RELATIVE COMMUNICATION COST PER NODE ($) 



LIN tackles the lowest level of the in-vehicle-networking hierarchy. 



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Na t tonal 

Semiconductor 

The Sight & Sound of Information 



designfeature Loc al- in t erconn e ct n et works 



SOFTWARE 
LEVEL 



HARDWARE 
LEVEL 



ELECTRONIC-CONTROL UNIT 
OPERATING SYSTEM 
APPLICATION SOFTWARE 



I 



SIGNAL-DATABASE MANAGER 



["lTn application INTE^FACE__J 


QCONFIGURATION LANGUAGE_J 


[ confIgur^^^^^^^B 


COMMUNICATION MANAGER 


NETWORK-CONFIGURATION 
GENERATOR 






LIN PROTOCOL^____J 




BUS ANALYZER/EMULATOR 
(LINSPECTOR) 


BUS TRANSCEIVER 










.LIN PHYSICAL LAYER 



VEHICLE LIN NETWORK 



Figure 2 



LIN defines the physical-layer, protocol-handler, and application-program- 



ming interfaces with support from a configuration language. 



sible with drivers ranging from simple 
state-machine logic to "bit-bashing" an 
I/O pin in software to using serial pe- 
ripherals. Such low speeds also constrain 
interference generation and ease timing 
issues, assisted by a master-driven self- 
synchronization facility that allows slave 
nodes to dispense with crystal or res- 
onator timers. 

Physical-layer exchanges employ an 
enhancement to the ISO-9141 standard 
that dominates European and Japanese 
vehicle-diagnostic systems. LIN-compat- 
ible line drivers limit slew rate to around 
2V/|jLsec to avoid creating interference 
due to fast edges. Such a line driver as- 
serts the "dominant" logic-zero state by 
driving the bus line to within 20% of sys- 
tem ground; a "recessive" logic one re- 
quires driving the line to within 20% of 
battery voltage. To allow for effects such 
as ground shift, receivers allow more tol- 
erance, acknowledging levels within 40% 
of the respective rails (Figure 3). The 
master terminates the bus with a 1 -kfl 
resistor to battery voltage, and each slave 
defaults its I/O line high with a 30-kn 
pullup resistor. A diode in series with the 
termination resistor prevents devices on 
the bus from backfeeding into the bat- 
tery-voltage rail if the supply fails. Mas- 
ters and slaves also each present around 
220 pF to the line up to a maximum of 10 
nF per bus, which results in a system time 
constant of 1 to 5 fxsec. In a region in 
which AM radios still proliferate, SAE- 
J2602's I0.4-kbps limitation further eas- 
es compatibility issues for the North 
American market. 

Unlike CAN, LIN's master/slave archi- 
tecture avoids data-traffic collisions and 
the need for arbitration logic by having 



the master supervise message transmis- 
sions, thus ensuring that only one mes- 
sage transmits at any time. A frame con- 
sisting of the master's header, a pause, and 
a slave's response encapsulates each mes- 
sage exchange (Figure 4a). Start and stop 
bits surround each byte, resulting in a 10- 
bit transmission per byte. There are sev- 
eral frame types, starting with diagnostic 
frames that carry diagnostic or initializa- 
tion information. By contrast, "uncondi- 
tional frames" always carry signals of as 
many as eight bytes. These are the frame 
types typify applications. "Sporadic" 
frames also always carry signals, but slaves 
respond only if new data is available, oth- 
erwise leaving the data field blank — an at- 
tempt to add some dynamic behavior into 
the system's schedule without compro- 
mising its determinism. Polling infre- 
quently responding nodes generates bus 
traffic. To improve system responsiveness 
by reducing the bus traffic, the protocol 
includes an event-triggered frame. This 
frame accommodates as many as seven 
data bytes, because the first field carries an 
identifier that associates the frame with its 
task. Again, slaves respond only if they 
have new data. The protocol also provides 



LINE DRIVER 




Figure 3 



for user-defined frames and reserves an- 
other type for future use. 

To initiate a data transfer following an 
interframe space or bus-idle condition, 
the master transmits a header compris- 
ing a synchronization-break period, a 
single-byte-synchronization field, and an 
identifier byte. The identifier byte carries 
six bits of information and two parity 
bits, allowing 64 message identifiers (Fig- 
ure 4b). In normal operation, there is no 
addressing as such; rather like CAN, the 
identifier byte uniquely defines the pur- 
pose of the frame. Identifier decimal val- 
ues of zero to 59 carry signals; 60 and 61 
are master- request and slave -response di- 
agnostic frames, respectively; user-de- 
fined frames have a header value of 62; 
and 63 is reserved. Each slave waits for the 
synchronization break and locks onto the 
synchronization byte before scanning the 
bus message. One or more slaves then re- 
ceives data, or a single slave transmits re- 
sponse data. The data field accommo- 
dates eight bytes; the data field's as- 
sociation with its identifier byte prede- 
fines the field's length. A single -byte check 
field terminates the transmission, pro- 
viding an error- detection facility. The 
master is responsible for all error han- 
dling, which is in turn the application 
programmer's responsibility; LIN 2.0 has 
no defined error-handling mechanism. 

Because it's imperative to preserve bat- 
tery power when the vehicle is inopera- 
tive, slaves automatically enter sleep 
mode if the bus is idle for more than four 
seconds. The master can also force slaves 
into sleep mode by sending the diagnos- 
tic master-request frame with the first 
data byte set to zero. The master subse- 
quently monitors the bus when it is idle, 
looking for wake-up signals from slaves 
that require service. Any bus node can re- 
quest wake-up by asserting the dominant 
state for 250 fisec to 5 msec, which makes 
5 msec the dominant state's longest valid 



RECEIVER 



^BAT 

60% 
40% 

ov 









-/ RECESSIVE \ 






-/ DOMINANT \ 




T 



Receivers tolerate levels of as much as 40% of the supply rails to account 
for effects such as ground shifts. 



32 EDN I April 28, 2005 



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LMSlOx Typical application circuit 



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Na t ion a I 

Semiconductor 

The Sight & Sound of Information 



© National Semiconductor Corporation, 2005. National Semiconductor, ^, and LLP are registered trademarksof National Semiconductor Corporation. All rights reserved. 




designfeature Loc al- in t erconn e ct n et works 



run. Most transceivers incorporate a 
watchdog timer that disconnects nodes 
exceeding this maximum, because such 
behavior indicates an error condition that 
would otherwise monopolize the bus. 
Slaves must wake up and be ready to 
transmit data within 100 msec of the end 
of the wake-up signal. Crucially, because 
the message length, interframe-spacing 
parameters, and device -wake -up times 
are known, it's easy to calculate worst- 
case response times for any system. Mas- 
ters typically use a static, round-robin 
scheduler, although adaptive schedulers 
provide greater flexibility to permit de- 
cision-based systems that similarly have 
guaranteed determinism. 

An exception to the zero -collision rule 
occurs when the master polls for an event- 
triggered frame and more than one slave 
responds within the same time slot. This 
situation might arise, for example, when 
the master polls all the doors within a cen- 
tral-locking application using an event- 
triggered frame. The response would nor- 
mally be blank, but if more than one door 
button is active at this instant, more than 
one slave responds. The master resolves 
the collision by requesting all of the un- 
conditional frames of similar association 
and checks their event flags before again 
requesting the event- triggered frame. This 
sequence avoids the possibility of a slave s 
withdrawing from a collision without cor- 
rupting the data, which the master would 
not detect, and thus lose the slave's re- 
sponse. Because application software im- 
plements these sequences, the program- 
mer must ensure that the bus has enough 
time to complete its operations without 
compromising the system's 
schedule. At the scheduler level, 
it's not permissible to include 
unconditional frames that are as- 
sociated with either a sporadic or 
an event-triggered frame within 
the same schedule table as the 
sporadic or the event-triggered 
frame. 



baud- and slew- rate limiting, it's impor- 
tant that the system withstands severe 
levels of radiated and conducted emis- 
sions. Against a background of emissions 
and interference issues, car makers have 
developed a range of in-house tests for 
evaluating in-vehicle networks. These es- 
sentially consist of injecting RF interfer- 
ence into the bus and varying the signal's 
frequency, amplitude, and modulation 
depth until the system fails. Many com- 
mon elements of these proprietary tests 
appear in the LIN-conformance test 
suite, which agencies such as the Com- 
munication and Systems Group at Fach- 
hochschule University of Applied Sci- 
ences specialize in applying on behalf of 
its clients. 

Scott Monroe, system architect at Texas 
Instruments' mixed- signal power and 
control group, explains that bulk-current- 
injection tests are popular in the United 
States, whereas European car makers fa- 
vor DPI (direct-power-injection): "With 
DPI, you increase the RF-power levels into 
a bus of, say, three or four transceivers, via 
an RC coupler until the system breaks. 
With bulk current injection, the bus runs 
through a coupling coil, and you again 
vary the interference levels, looking for the 
point where message transmissions fail." 
Monroe notes that the LIN specifications 
don't mention protection against reverse- 
battery faults and negative-going tran- 
sients, such as those that inductive loads 
create. These tests form part of the 
CISPR (International Special Committee 
on Radio Interface) -25 and ISO (Interna- 
tional Organization for Standardization) - 
7637 transient-immunity standards for 



SIMPLICITY BELIES CHALLENGES 

Although LIN is conceptual- 
ly simple, device vendors still 
face significant challenges. The 
first difficulty is to fabricate bus 
transceivers that withstand au- 
tomotive conditions, notably se- 
vere EMC-test compliance. Al- 
though LIN constrains inter- 
ference generation through 



MESSAGE FRAME 



HEADER (MASTER) 



SYNCHRON- 
IZATION 
BREAK 



SYNCHRON- 
IZATION 
FIELD 



IDENT 
FIELD 



TRANSMIT/RECEIVE (SLAVE) 



DATA 
\ FIELD 



DATA 
FIELD 



DATA 
FIELD 



DATA 
FIELD 



CHECKSUM 
FIELD 



IN-FRAME 
RESPONSE SPACE 



INTERBYTE 
SPACE 



BYTE-FIELD 
SCI/UART FORMAT 



(a) 



























IDO 


ID1 


ID2 


ID3 


ID4 


ID5 


PO 


PI 






START BIT 










STOP BIT 



(b) 



Figure 4 



Each message exchange comprises a master- 
initiated header followed by a slave's recep- 
tion or transmission (a). The master sends an identifier byte that 
uniquely defines the frame's purpose within a system (b). 



automotive ICs. With a ±40V bus fault 
and as much as 17-kV ESD protection, 
TFs TPIC1021 withstands these rigors 
and improves system reliability with fea- 
tures such as dominant- state time-out. Its 
I/O pins use a 5 V- tolerant 3.3V structure 
for maximum logic compatibility. With 
thermal and bus-terminal protection 
from shorts to either supply rail, the chip 
doesn't disturb other bus communica- 
tions in its inactive state. It responds to 
wake-up requests from the bus, from an 
enable pin that connects to the host mi- 
crocontroller, or to a battery- voltage lev- 
el-switch input. In sleep mode, quiescent 
current consumption falls from a maxi- 
mum of around 2.5 mA to about 20 fxA. 
The chip can also control an external volt- 
age regulator, making it possible to pow- 
er down a microcontroller or other LIN- 
protocol logic. 

Other vendors that offer LIN trans- 
ceivers include AMI Semiconductor, At- 
mel, Freescale, Infineon, Melexis, Mi- 
crochip, On Semiconductor, Philips, 
STMicroelectronics, Yamar, and ZMD. 
Like the TI part, many of these devices 
offer similar pinout and functions to 
Freescale's MC33399 and Philips' TJA- 
1020 market-leading transceivers. Philips 
has a useful application note that illumi- 
nates LIN-transceiver issues (Reference 
2). There are, however, detail differences 
between the electrical specifications in 
various competitive products, such as in 
the fault-voltage tolerance that vendors 
quote. For example, Atmel's ATA6661 
withstands bus voltages of as much as 
60V for use in 42V PowerNet environ- 
ments. There are also some subtle differ- 
ences between apparently 
similar pinouts. For example, 
although most transceivers 
run directly from the vehicle's 
battery voltage. On Semicon- 
ductor's NCV7380/7382 re- 
quires a 5V supply on Pin 3, 
which is typically a battery- 
voltage-compatible wake-up- 
signal pin. The NCV7380 
variant also dispenses with 
sleep-mode logic to minimize 
cost. 

Gilles Guillaume of On 
Semiconductor's European 
marketing operation notes 
that the company offers de- 
signers extra flexibility, such 
as a voltage -regulator option 
to derive auxiliary power. In- 



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designfeature Loc al- in t erconn e ct n et works 



tegrating a low- dropout- voltage regula- 
tor, the company's NCV7361A employs 
a modified eight-pin format to provide 
a 5V, 50-mA output. Melexis offers a sim- 
ilar part with its TH8061. Other exam- 
ples of transceivers with integral voltage 
regulators include Microchip s MCP201, 
which trades the typical Pin 3 wake -up 
function to furnish a 5V, 50-|jlA output. 
An external pass transistor can boost this 
capability for more demanding loads. An 
enhanced version, the MCP202, with 
higher ESD resistance and lower standby 
current will become available for sam- 
pling this summer. Texas Instruments 
also plans a transceiver variant with volt- 
age-regulator-output capability. 

MICROCONTROLLERS PLAY STATE MACHINES 

The low cost and competitive nature of 
the LIN market complicate system inte- 
grators' choice of architecture. This choice 
even may differ within the same system 
due to the requirements of masters and 
slaves. Traditionally, pc-board designers 
gain maximum flexibility by using sepa- 
rate transceivers and microcontrollers. 
Because designers build these devices 
around a familiar product family and de- 
velopment-tool chain, this route is often a 
favorite, especially for masters. It may also 
provide an easy bridge into a CAN envi- 
ronment. Alternatively, microcontrollers 
with onboard transceivers and applica- 
tion-specific peripherals provide tightest 
integration, shrinking size and potential- 
ly offering the lowest cost for high-volume 
applications. Ross Mitchell, 8/16-bit-sys- 
tem software -application manager at 
Freescale, notes that size is often crucial, 
because trying to integrate, say, a mirror 
controller within plastic molding can 




prove challenging: "It's typically desirable 
to have the control module as close as pos- 
sible to its load, because this strategy min- 
imizes wiring and can improve EMC per- 
formance." 

But for lowest cost, state machines chal- 
lenge microcontrollers and expensive 
on-chip memories. Such memories are 
necessary for supporting in-system con- 
figuration, which is one reason that some 
users want to stay with hardware that is 
compatible with LIN 1.3. Microchip's 
Johann Stelzer, European marketing 
manager for automotive products, be- 
lieves that US customers in particular will 
adopt a subset of 2.0: "From a cost view- 
point, diagnostics and in-system config- 
uration are a negative developments that 
threatens the $l/node target," he says. 
More than one competitor acknowledges 
that today's low cost of CAN may erode 
the advantages of a complex LIN imple- 
mentation. According to TI's Monroe, the 
optimal balance is crucially application- 
dependent. His company is supplying sys- 
tem makers with fuUy integrated products 
based on both state-machine and intelli- 
gent logic, although these devices are not 
yet available as catalog items. Many of 
these custom devices are three-pin slaves 
that fulfill roles as diverse as oil- quality 
and temperature sensors for engine-con- 
trol systems to seat-weight sensors for oc- 
cupant detection. 

Monroe says, "From the lowest cost 
viewpoint, constraining feature creep 
and keeping it simple are obviously the 
ways to go." But in common with his 
peers, Monroe recognizes that there is a 
tendency among some designers to de- 
sire ever more features. As a result, a stag- 
gering array of controller options are 



N OUT 
LT1121 
HSHDN 
GND 



T 



VSUP INH 

El 

MC33399 



MAX6611 
SHDN REF 
VCC TEMP 

GND GND 



, MC68HC908QY 

- PTB7 PTBO 

- PTAl/ADl/TCHl PTBl -O 

- PTB2 PTB3 

O- PTAO/ADO/TCHO PTB4 

- PTA5/0SC1 PTB5 

- PTA4/0SC2 PTB6 1 



O- PTA3/RST PTA2/I RQ -O 



Ik 
Ik 
Ik 



Figure 5 



A reference design from Freescale illustrates a typical microcontroller- 
based implementation of a slave node. 



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designfeature Loc al- in t erconn e ct n et works 




available from vendors, including almost 
all of the transceiver suppliers. Current- 
ly, Atmel and On Semiconductor supply 
only the physical-layer interface, but both 
companies plan to offer the protocol log- 
ic, as well. Marcel Hennrich, Atmel's 
marketing manager for LIN products, 
confirms that derivatives of the compa- 
ny's AVR range will include the LIN 
transceiver, a 5V regulator, and a system 
watchdog. To assist its modular- devel- 
opment strategy, the company will offer 
a LIN-protocol stack from a third-party 
supplier to complement its normal tool 
chain. At On Semiconductor, the com- 
pany's automotive -applications manag- 
er, Leo Airchriedler, says that the next 
step is to offer a LIN transceiver with an 
integral voltage regulator: "We will be 
carefully watching the market, and, if the 
demand is there, we will consider inte- 
grating the protocol logic, too." This 
combination forms the so-called SBC 
(system-basis-chip) . 

Available SBC examples include 
Freescale's MC33689, which bundles the 
transceiver, protocol handler, and voltage 
regulator into a 32-pin, 0.65-mm-pitch, 
surface-mount outline. This chip also in- 
cludes three protected high-side drivers 
two of which support PWM; an uncom- 
mitted op amp intended as a current- 
sense amplifier; two high- voltage wake- 
up inputs; a configurable watchdog 
window timer; and an interrupt output 
that can signal undervoltage- and over- 
voltage -supply problems. An SPI port 
enables setup from a host, including sev- 
eral low-power-mode and slew-rate op- 
tions. The chip also includes additional 
hardware-protection features, such as 



overtemperature shutdown and over- 
current limiting. 

Freescale shows some representative 
applications on its Web site, such as 
AN2623's temperature-sensor example 
(Figure 5). Here, the application runs 
under supervision from a 68HC908QY 
microcontroller with 4 kbytes of flash. 
The example shows the MC33399's 
handling the physical-layer-level trans- 
lation and controlling the node's pow- 
er supply by driving the Inhibit Pin of 
Linear Technology's LTl 121 micropow- 
er low-dropout-voltage regulator. The 
software uses Freescale's LIN driver that 
is freely available from its Web site. 

Freescale's Ross Mitchell says that it is 
just about possible to code a simple ap- 
plication into less memory, such as the 1 .5 
kbytes on the entry-level 908 family 
members, but considers 4 kbytes as a 
practical minimum. He and other ven- 
dors concur that the "sweet spot" for LIN 
lies somewhere around the 8 -kbyte area 
for slaves, enabling applications such as 
window lifters with occupant-pinch de- 
tection. Intelligent-distributed-control 
chips, such as the MM908E625, employ 
the company's SmartMOS process to 
tighten integration for space-constrained 
nodes that require H-bridge motor con- 
trol, such as headlamp levelers and mir- 
ror controllers. A new 908 family mem- 
ber, the MC68HC908QL4, includes an 
on-chip LIN-protocol handler and auto- 
matically synchronizes to the bus timing 
to suit slave use. The product is available 
now, and the company offers a $199.95 
evaluation board that complements its 
LINkit demo boards. 

According to Microchip's Stelzer, the 



DUAL-TASK MIX4 



TASK RUNS 
THE PROTOCOL HANDLER 



TASK 1 IS FREE 
FOR THE APPLICATION 
SOFTWARE ---^ 



API 
(INTERTASK 
COMMUNICATION) 



CLASS A HARDWARE CELL- 



PHYSICAL INTERFACE- 



SYSTEM 




FAULT 




BUS-FAILURE 


SYNCHRONIZATION 




CONFINEMENT 




MANAGEMENT 




TASK 1 : 




TASK 0: 


APPLICATION 


LIN 


■^PROTOCOL 


SOFTWARE 


API 


SOFTWARE 



DIGITAL 
LIN INTERFACE 



PHYSICAL 
INTERFACE 




LOGICAL LINK LAYER 

• ACCEPTANCE FILTERING 

• RECOVERY MANAGEMENT 

• MESSAGE VALIDATION 

• TIMEBASE SYNCHRONIZATION 



MEDIUM-ACCESS CONTROL 

• DATA ENCAPSULATION/ 
DECAPSULATION 

• ERROR DETECTION 

• ERROR SIGNALING 

• SERIALIZATION/DESERIALIZATION 



OSI 
MODEL 



PHYSICAL LAYER 



• BIT TIMING 

• BIT SYNCHRONIZATION 

• LINE DRIVER/RECEIVER 



J 



Figure 6 



The IVILX4 core from Melexis runs the LIN task and application software in 
two separate areas to emulate a two-task RTOS in hardware. 



38 EDN I April 28, 2005 



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designfeature Loc al- in t erconn e ct n et works 




requirement for slaves to synchronize to 
the master's baud rate requires as many 
as 16 bits of timing resolution; hence, con- 
ventional UARTs aren't up to the job. For 
this reason, the company offers LIN-en- 
hanced UARTs on chips such as its 
PIC16F688, which also includes features 
such as auto-wake-up on bus activity. This 
device uses the modified Harvard RISC 
architecture that is familiar to PIC users, 
and carries 4k words of program flash 
with 256 bytes of EE? ROM for in-system- 
configuration data. Stelzer states that C 
programmers often favor higher end 
chips, such as the PIC18 family that pro- 
vides more memory and substantially 
more computing power. The latest mem- 
bers are the PIC18F4x20/18F2x20 that of- 
fer 6 to 64 kbytes of program memory, 
speeds as high as 10 MIPS, and 28- and 
44-pin QFN packages. They enjoy the 
same LIN enhancements as the F688, in- 
cluding Microchip's nanoWatt power- 
management technology that can reduce 
sleep-mode current drain to less-than-1- 
fxA levels. All Microchip's LIN-slave prod- 
ucts include on-chip RC oscillators that 
eliminate external resonators or crystals. 
For master tasks, Stelzer recommends the 
PIC18F4680, a 64-kbyte device with 1 
kbyte of data EEPROM and the compa- 
ny's LIN-specific enhancements among 
its total of 36 I/O pins. This chip also car- 
ries Microchip's enhanced CAN interface, 
enabling use as a CAN-to-LIN bridge. 

Melexis took a different path with its 
LIN-specific MLX4 core. Michael Bender, 
the company's marketing manager for 
LIN products, says that this core appears 
in the TH8100, a single-chip slave for in- 
telligent-switch modules, and forms the 
basis of several new chips that will roll out 
over the coming months. The TH8100 
embodies the bus transceiver and its syn- 
chronization logic, with a LIN 1.3-com- 
pliant protocol handler and internal volt- 
age regulation that powers the chip from 
the 12V rail. Requiring minimal external 
components, it includes 17 switch inputs, 
three ADC channels, and three PWM out- 
puts. Its 4-bit MLX4 core has two inde- 
pendent register sets that partition and si- 
multaneously handle the LIN protocol 
and the application (Figure 6). Each task 
owns a private set of peripherals, such as 
a timer and UART, and a private memory 
area. Flags and mutual- exclusion logic 
protect intertask data transfers to prevent 
both tasks from simultaneously writing to 
the same RAM address. Because register- 



set switching occurs after every instruc- 
tion, each task has 50% of the core's 4- 
MIPS capacity. The system can also dy- 
namically share the available processing 
power; if one task enters wait mode, all 
processing power becomes available to the 
other task. 

Additional sources of LIN-enabled 
hardware include Japanese microcon- 
troller giants Fujitsu, NEC, and Renesas, 
as well as programmable-logic specialist 
such as Xilinx, and IP (intellectual-prop- 
erty) -core designers Intelliga and Fraun- 
hofer Institut. LIN now appears on the 32- 
bit ARM platform, too, courtesy of 
Philips' SJA2020. Now available for sam- 
pling in a 144-pin package, this 60-MHz 
device carries 256 kbytes of flash and sup- 
ports as many as six CAN channels and 
four LIN masters. Analog Devices intends 
to add a LIN 2.0 -compliant transceiver to 
its ARM7-core AD|jlC702x series, which 
currently supports the protocol via a 
UART-based software implementation. 

This widespread support suggests a 
bright future for a technology that is only 
just beginning to emerge in production 
applications. Issues that industry insiders 
are keenly monitoring 
include the protocol's I 
acceptance in the ' 
Japanese market, its 
progress toward ISO- 
standard recognition, 
and its penetration into areas outside au- 
tomotive. As Microchip's Stelzer ob- 
serves, freezing LIN 2.0 was an essential 
step toward getting the technology into 
design wins. He also notes that consumer 
applications, such as white goods, can be 
even cheaper by dispensing with the 12V 
medium: "They can use a single-wire, 5V 
system, because 12V is simply an extra 
effort." □ 

References 

1. Marsh, David: "Network protocols 
compete for highway supremacy," EDN 
Europe, June 2003, pg 26. 

2. TJA 1020 LIN transceiver, application 
note AN00093, Philips, 2002, www.semi 
conductors .philips . com . 

3. For a list of vendors referenced in this 
article, please see the online version at 
www.edn.com. 



Talk to us 

Post comments via TalkBack at the online 
version of this article at www.edn.com. 



You can reach 
Contributing Technical 
Editor David Marsh 
at forncett@ 
btinternet.com. 



www.edn.com 



POWER management! 



J^lj^ Texas Instruments 



Analog Applications Journal 



Understanding Power Supply Ripple Rejection in 
Linear Regulators 

By John C. Teel • Analog IC Designer, Member Group Technical Staff 



Power Supply Ripple Rejection (PSRR) is a measure of how 
well a circuit rejects ripple at various frequencies coming 
from the input power supply and is very critical in many RF 
and wireless applications. In the case of an LDO, it is a measure 
of the output ripple compared to the input ripple over a wide 
frequency range (10Hz to 10MHz is common) and is 
expressed in decibels (dB). The basic equation for PSRR, and 
more specifically PSRR for an LDO, can be written as: 



PSRR = 20 log 



RippleiNpuT 
RippleouTPUT 



where Ay is the open-loop gain of the regulator feedback 
loop and Ayo 'S the gain from V||^ to Vqut with the regulator 
feedback loop open. 

PSRR = 20 log 



From this equation it can be seen that to increase the PSRR it 
is beneficial to increase the open-loop gain and decrease the 
gain from Vin to Vqut- Typically, Ayo is significantly less than 
OdB with -10 to -15dB being typical and this is entirely 
driven by parasitics (internal and external) from input to 
output and at the gate of the pass-FET. Figure 1 shows a 
simplified block diagram of a PMOS pass-FET. 



Figure 1 




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Another parameter that is closely related to PSRR is line 
transient response. PSRR is specified at specific frequencies, 
whereas a line transient essentially contains all frequencies 
due to the Fourier components of a step function; however, 
the primary difference is that PSRR is a small signal 
response, whereas line transients are large signal and thus are 
theoretically much more complicated in nature. However, 
what improves PSRR improves line transient response and 
typically vice versa (unless what improves the line transient 
is only a large signal improvement) so many times it is 
convenient to just improve one or the other knowing that 
both will be improved. Therefore, all of the effects on PSRR 
discussed in this article will also have the same effect on the 
line transient response. 

A curve showing PSRR over a wide frequency range is shown 
in Figure 2. 

Figure 2: 



1,000 10.000 100,000 1,000,000 

Frequencv (Hz) 



As mentioned previously the open-loop gain of the LDO 
feedback circuit is the dominant factor in PSRR (at least in a 
limited frequency range) and therefore LDOs requiring 
good PSRR typically have high gain with a high unity-gain 
frequency (large gain-bandwidth product); however, this 
also makes the loop more difficult to stabilize and that 
keeps a limit on how much the gain-bandwidth product can 
be increased to improve PSRR. It is important to have a 
high unity-gain frequency so that the amplifier does not 
lose open-loop gain at relatively low frequencies thus 
causing PSRR to also roll off. 

The curve In Figure 2 shows that PSRR for an LDO can be 
broken down into three basic frequency regions. The first 
region is from DC to the rolloff frequency of the bandgap 
filter and is dominated by both open-loop gain and 
bandgap PSRR. The second region extends from the 
bandgap filter rolloff frequency up to the unity-gain 
frequency and in this region PSRR is dominated mainly by 
the open-loop gain of the regulator. Above the unity-gain 
frequency is region three and here the feedback loop has 
very little effect because there is no longer any open-loop 
gain and the output capacitor dominates along with any 
parasitics from V|n to Vout- Also the gate driver's ability to 
drive the pass-FET gate at high-frequency has an effect in 
region three . A larger output cap with less ESR will typically 
improve PSRR in this region. It should be noted that 
although increasing Cqut can improve PSRR it can also 
actually decrease the PSRR at some frequencies. This is 
because increasing the output capacitor lowers the 
unity-gain frequency thus causing the open-loop gain to 
rolloff earlier therefore lowering PSRR in that region. 
Although a larger output capacitor will cause the PSRR to 
roll off earlier, the minimum PSRR that occurs at the 
unity-gain frequency will typically be Improved. 

Anything affecting the gain of the feedback loop also affects 
PSRR in region two. One example is load current. As load 
current increases the open-loop output Impedance of the 
LDO decreases (a MOSFET's output impedance is inversely 
proportional to the drain current) thus lowering the gain. In 
addition to lowering the gain, increasing the load current 
also pushes the output pole to higher frequencies thus 
broadbanding the feedback loop. So the net effect of 
increasing the load is a reduction in the PSRR at lower 
frequencies (because of the reduced gain) along with an 
increase of PSRR at higher frequencies. 

Another example that affects PSRR by changing the regulator 
open-loop gain is the differential DC voltage between input 
and output. As Vin-Vout 's lowered less than about IV, the 
internal pass-FET (which provides gain In a PMOS design) 
starts to be pushed out of the active region (saturation) of 



operation and into the triode/linear region thus causing the 
feedback loop to lose gain. The dividing line between 
the active region and the triode region is proportional to the 
square-root of the drain current (load current). So as 
the load current is increased the necessary voltage across 
the device (Vin-Vqut ) to keep it in the active region increases 
as the square-root of load current. So, for example, having 
V|N-VouT at only 0.5V may have no negative effect on PSRR 
at light load currents because the pass device doesn't need 
much headroom to stay in the active region so the gain is 
preserved. However, at heavier loads 0.5V may no longer 
be sufficient and the pass device will enter the triode region 
and the circuit will lose gain and PSRR will be reduced. 
When comparing PSRR among various LDOs, it's always 
Important to compare them at identical Viim-Vqut and 
I LOAD conditions (it's also important to compare LDOs at 
identical output voltages since PSRR is usually better at 
lower output voltages). 

One of the dominant internal sources of PSRR in an LDO Is 
the PSRR of the bandgap reference. Any ripple that makes 
its way on to the reference will get gained up and sent to 
the output so it's important to have a bandgap reference 
with high PSRR. Typically, the solution that is chosen is to 
simply filter the bandgap with a low-pass filter. This way 
only the PSRR at low-frequencies (I.e. line regulation) is 
important for the bandgap thus greatly simplifying the 
bandgap, design because the LPF takes care of all the ripple 
at frequency. This LPF is almost always accomplished with 
an internal resistor and an external capacitor (large resistors 
are much easier to fabricate on-chip than large capacitors). 
The effect of this LPF can be seen in Figure 2 and as can be 
seen below the RC filter frequency (region 1), the PSRR is 
reduced somewhat by the PSRR of the bandgap coming 
Into play. 

As has been shown there are many things that can be done 
to improve the PSRR in a LDO application. The most important 
being to start off with an LDO designed for high PSRR such 
as the TPS793/4/5/6XX family of low-noise, high-PSRR LDOs 
and the TPS799xx low-noise, high-PSRR, Iow-Iq LDO. The 
next most critical decision is the selection of the output 
capacitor with a low ESR ceramic capacitor being the best 
choice and the capacitance value being determined 
depending on at which frequencies PSRR is most important. 
Finally, board layout must be carefully done in order to 
reduce the feedthrough from input to output via board 
parasitics. 







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© 2005 Texas Instruments. All trademarks are property of their respective owners. 00010 



POWERBim\& #2 



J L 



J I I I I L 



Playing it Safe with Output 
Overload Protection 



sponsored by 
J 1 U 



by Peter Vaughan 
Manager of Product Applications 
Power Integrations 



'POWER 

^INTEGRA TiONS 



Ti 1^1 r I 1 1 I I I I I 1 I i I" 
ake a break from your daily routine and test your power supply design knowledge by trying your hand at 
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The schematic to the right shows a flyback power 
supply built with a TOPSwitcJi-GX power conver- 
sion IC. The following questions concern the 
output overload characteristics of the power 
supply. 



1 I r 



[Question 1: beginner 



Output Overload Power vs. Line 





Which of the curves in the graph to the left (A, B or C), - 
represent the overload characteristic of output power versus 
input voltage for a typical flyback power supply that is not 
compensated for line voltage? 



Flyback drain current 
waveforms* X, Y and Z 
were taken at 85 VAC 
and 265 VAC. Match 
the waveform pairs to 
curves A, B and C 
above. ~ 



1 I I 




I I 



Waveform X : 



I 



Waveform Y : 



II I 



Waveform Z : 



*Test Conditions: Upper trace (1) V^^ = 85 VAC, lower trace (2) Vj^ = 265 VAC, both traces 0.5 A/div, 2 |LLs/dr 



[Question 3 : expert 

_ It's possible to compensate the output overload characteristic of a typical flyback power supply by controlling the 
peak drain current limit of the converter. When using TOPSwitch-GX, compensation is achieved by correctly 
choosing the value of just one passive component, R2 in the schematic above. What are the advantages of 

— achieving a flat output overload characteristic? -) 1 1 1 ( 1 j 1 ( 1 1 1 1 



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The constant current I re F is set with 
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constant voltage is fixed at 4.2V. 



End-of-charge (EOC) current indicated 
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To Input 

*7T- 



BAT 








IREF 




IMIN 




ISL6294 




CHG 




PPR 


EN 






GND 



1REF 

— 



VSAr— + 



To Battery^ 



3 



If the battery voltage is below 2.6V the ISL6294 charges the battery with a trickle 
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Datasheet, free samples, and 
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Enter 22 at www.edn.com/info 



Intersil - Switching Regulators for precise power delivery. 

©2005 Intersil Americas Inc. All rights reserved. The following are trademarks or services marks owned by Intersil Corporation 
or one of its subsidiaries, and may be registered in the USA and/or other countries: Intersil (and design) and i (and design). 




EDN 



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DSP OPTIONS CONTINUE TO EXPAND AND ARE TARGETING OPTIMIZED CONFIGURATIONS 
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FOR A DETAILED VIEW OF CURRENT DEVICE AND CORE OFFERINGS. 



WELCOME TO THE 2005 EDN DSP DIRECTORY. This directory con- 
tinues to grow at a substantial rate each year-so much so, 
that this year's edition comprises an annual update of com- 
panies and products that is available in both EDN's print and online 
editions and a comprehensive table listing devices and cores that is 
available exclusively on the Web. The table presents DSP-market of- 
ferings in a dense format, highlighting the latest developments in the 
market and providing an up-to-date listing of current and valid 
processor offerings. Find it at the Web version of this article at 
www.edn.com, where you can also share your thoughts for making 
the directory even more useful as the market continues to change. 

According to market-research company Forward Concepts 
(www.fwdconcepts.com), the DSP-chip market grew 27.2% during 
2004. The wireless market accounts for almost three-quarters of that 
growth at 71.5% (up from 68% in 2003). It's noteworthy that most 
of the gains occurred in the first half of last year, because the (most- 
ly) Chinese cell-phone makers had to deal with a glut of inventory. 
Forward Concepts has lowered its forecast for the 2005 DSP-mar- 
ket growth from 20 to 10%. 

As signal-processing designs become more complex, device and 
IP (intellectual-property) vendors are developing and packaging bun- 
dled resources, platforms, or reference designs to demonstrate to 
designers how to use their products for specific applications. DSP 



vendors are committing serious design resources to developing ref- 
erence designs, which continue to gain importance as tools to se- 
cure strategic design-in wins. These reference designs often go be- 
yond samples and application notes-in some cases, to the point of 
turnkey implementations. Currently, finding a vendor's available ref- 
erence designs is neither straightforward nor consistent within a 
company's product material. EDN plans to highlight reference-de- 
sign information in this directory, and this year in its 2005 Micro- 
processor Directory, as well as in annual updates. 

EDN has loosened the criteria for inclusion in the DSP directory 
to better accommodate the many ways to implement signal pro- 
cessing, including hybrid combinations of software-programmable 
DSPs, fixed-function devices, reconfigurable devices, and host mi- 
croprocessors. Standard processor devices with multiple DSP and 
RISC cores and the development tools that support these devices 
continue to become more common. The current online table cate- 
gorizes DSP offerings not by application space but rather by ven- 
dor. If you have ideas about column headings that would be more 
useful to your search for the perfect DSP product, please drop us a 
line. Likewise, if you have ideas for how to incorporate other types 
of signal-processing options, such as fixed-function blocks, reference 
designs, and platforms, please e-mail your ideas to us at dspdirec 
tory@edn.com. 



By Robert Cmvotta, Technical Editor 



46 EDN I April 28, 2005 



^-ALTERA 

Over the previous year, Altera continued to extend its pro- 
grammable-logic products and tools. The Hardcopy II line 
of structured ASICs features an FPGA front-end design 
methodology; Altera built the architecture around a fine- 
grained collection of transistors called HCells that support 
the seamless migration from an FPGA to realize the densi- 
ty, cost, performance, and power benefits of ASIC technol- 
ogy. Altera also unveiled the Stratix II EP2S180 device — its 
largest and fastest FPGA. Version 4.2 of the Quartus II de- 
sign software includes new PowerPlay power- analysis and 
-optimization technology. Altera s SOPC (system-on-pro- 
grammable-chip) software-development tools and IP cores 
help designers target applications in the communications, 
computer peripheral, and industrial markets. 

Altera maintains Web resources, including FAQs, device 
and IP support, design-software support, and mySupport, 
with which users can create, view, or update service requests 
and manage software subscriptions or IP licenses. The Cy- 
clone II DSP-development kit to assists developers with wire- 
less-infrastructure, medical- diagnostics, imaging, and test- 
and- measurement equipment. In addition to a development 
board, the development kit includes the latest version of The 
MathWorks' Simulink software. Altera s DSP Builder, and the 
Quartus II design software. Altera provides reference designs 
for broadcast, automotive, computing, and wireless appli- 
cations that designers can use to reduce design time and im- 
prove their understanding of Altera products' capabilities. 

Ml SEMICONDUCTOR 

Over the previous year, AMI Semiconductor acquired 
DSPfactory, which focuses on the medical market, specifi- 
cally in providing digital- signal processing as ASICs and 
standard products for ultralow-power medical wireless ap- 
plications. It also introduced the Orela 4500 series, which 
targets DSP-based, mixed-signal audio systems to provide 
audio processing and exceptional sound quality for digital 
hearing aids that require sophisticated processing capabili- 
ties and advanced features. The BelaSigna 200 series targets 
high-performance DSP-based audio systems, such as wire- 
less, industrial, and specialty headsets, and other ultralow- 
power, small-form-factor audio applications. AMI Semi- 
conductor introduced bundled signal-processing algorithms 
for use with the BelaSigna 200, including streaming audio 
for wireless reception of high-fidelity stereo sound on Blue- 
tooth stereo applications and telecom algorithms for com- 
munication in Bluetooth telecommunication headsets. The 
reconfigurable, DSP-based Toccata Plus system targets 
midrange to high-range hearing-aid applications. 

AMI Semiconductor offers a suite of simulation, evalua- 
tion, development, and application tools for each of its de- 
vices. Evaluation and development kits include a board for 
rapid prototyping, evaluation, and testing; sample code 
demonstrating real-time algorithms; bundled UltraEdit ad- 
vanced and integrated development editor with AMIS ex- 
tensions; firmware support for developing real-time algo- 
rithms; a complete compilation-tool chain; low- and 



source-level debuggers; an EEPROM-manager-layout tool; 
and documentation. The Hybrid demonstrator board en- 
ables digital-hearing-aid developers to connect AMIS Orela 
4500 series hybrids directly to transducers, switches, trim- 
mers, and other peripherals to evaluate the real-world per- 
formance of their designs. The Advanced Headset reference 
design, which RF Micro Devices and AMI Semiconductor 
jointly developed, provides an end-to-end option for wire- 
less streaming audio. The hardware incorporates the AMIS 
BelaSigna 200 DSP-based audio system with an integrated 
codec. Possible applications include streaming audio from a 
PC, notebook, portable audio player, or other analog source 
to a headset. 

-^ANALOG DEVICES 

The 16/3 2 -bit Analog Devices Blackfin embedded proces- 
sor targets the computational demands and power con- 
straints of embedded audio, video, and communications ap- 
plications. Based on the MSA (Micro Signal Architecture) 
that Analog jointly developed with Intel, the Blackfin Proces- 
sor family combines a 32-bit RISC-like instruction set with 
16-bit dual MACs (multiply/accumulate) units. Dynamic 
power management enables lower power consumption by 
allowing the simultaneous adjustment of system operating 
frequency and voltage under application control. Analog De- 
vices' Crosscore tools support development for the Black- 
fin processors and consist of the VisualDSP + + develop- 
ment and debugging environment, EZ-kit Lite evaluation 
kits, EZ-Extender daughterboards, and emulators. Release 
4.0 of VisualDSP++ incorporates TCP/IP and USB sup- 
port, a processor configuration/start-up code wizard, and 
multiple-project management. 

The recently available ADSP-BF534/36/37 devices are a 
functional extension of the ADSP-BF53 1/32/33 processors. 
The higher performance ADSP-BF537 offers more embed- 
ded memory, enabling higher throughput needs for em- 
bedded-system applications, such as video security/sur- 
veillance and industrial-environment-based distributed- 
control and factory-automation applications. The ADSP- 
BF536 targets low-cost connected devices, such as remote 
monitoring devices, VOIP (voice over Internet Protocol), 
and biometrics applications. The ADSP-BF534 processors' 
system peripherals include an integrated CAN (controller- 
area network) 2. OB controller; a two-wire interface con- 
troller; UART and SPI ports; external DMA request lines; 
32-bit timers (some with PWM capability); a real-time 
clock; a watchdog timer; and a parallel peripheral interface. 
The ADSP-BF536/537 further extends these features by 
adding an integrated IEEE- compliant 802.3 10/100 Ether- 
net MAC and an enhanced DMA system for high network- 
bandwidth capability. 

ARC INTERNATIONAL 

The five-stage-pipeline ARC 600 family of configurable 
and extendable cores provides embedded control, computa- 
tion, and digital-signal-processing tasks targeting battery- 
operated and cost- sensitive consumer, networking, and au- 



tomotive applications. The architecture includes memory 
options, such as single-cycle, closely coupled memories for 
instructions and data, as well as configurable instruction and 
data caches. Multiple 32-bit ports, including main memo- 
ry, auxiliary registers, and closely coupled memories support 
external memory access. The architecture supports BVCI- 
and AHB (AMBA hardware bus) -configuration options. 

The seven-stage-pipeline ARC 700 family of configurable 
cores combines a powerful 3 2 -bit CPU and a full- featured 
DSP engine in a unified architecture to target the more de- 
manding tasks of graphics, media codecs, and packet pro- 
cessing. The ARC 700 architecture supports embedded op- 
erating systems, such as Linux. It also supports memory 
options and extends external memory access via multiple 
32- or 64-bit ports. ARC 600/700 DSP extensions include 
16- and 32-bit MAC and saturating arithmetic instructions 
with access to configurable banks of XY memory. The ARC 
DSPlib library of custom instructions accelerates common 
DSP calculations. 

ARM 

ARM bases its VLIW (very-long-instruction-word) Op- 
timoDE Framework, which it launched last year, on key tech- 
nology it acquired from Adelante Technologies. ARM Op- 
timoDE Data Engines are licensable IP with an associated 
tool environment, a datapath functional-resource library, 
and preconfigured microarchitectures with varying paral- 
lelism and performance. Designers can use OptimoDE, 
which targets high-performance embedded signal-process- 
ing applications, as stand-alone processors or in designs with 
microprocessor cores. It supports parallelism, a virtually un- 
limited datapath configuration (including mixed widths), 
user extensibility, and access to fixed-function or repro- 
grammable data engines. OptimoDE Data Engines are com- 
patible with arm's DSP Interface Specification, which de- 
scribes the interfaces between the cores for mailbox-based 
command- and- control messaging and bulk data passing, de- 
bug and trace interfaces and protocols for multicore debug- 
ging, and software APIs for interprocessor communications. 

By supporting reprogrammability, the OptimoDE design 
process enables designers to freeze the Data Engine archi- 
tecture and continue to tune the algorithm through software 
changes. This approach enables multiple algorithms with 
similar requirements to use the same Data Engine hardware. 
Developers can reprogram OptimoDE Data Engines once 
they have committed the design to manufacture or they are 
shipping it in volume. They can regenerate code to accom- 
modate incremental design changes or alternative algorithms 
without altering the underlying hardware architecture. 

The tool environment enables designers to configure and 
extend the type and number of datapath- resource units. De- 
signers may also configure the size and topology of local 
storage and the level of interconnect. ARM provides a C 
compiler and profiling- analysis tools that enable designers 
to program OptimoDE Data Engines in C or C + + . The Op- 
timoDE tool environment automatically generates simula- 



tion models that designers can use to verify the integration 
process, once the data engine is incorporated within a de- 
sign. OptimoDE Data Engines are AMBA- compliant and 
work with a variety of ARM System IP. 

-^-ATMEL 

Atmel's high-performance, 40-bit, floating-point, VLIW 
Magic DSP can perform as many as 10 arithmetic opera- 
tions per cycle and enable a single-cycle EFT Butterfly. It pro- 
vides native support for complex arithmetic and vectorial 
SIMD (single-instruction-multiple-data) operations. The 
dual-processor Diopsis 740 device integrates a Magic DSP 
and an ARM7TDMI microcontroller core with 1.9 Mbits 
of RAM. The product targets complex-domain, floating- 
point, high-precision, embedded-system applications, in- 
cluding professional-quality audio, speech processing for 
hands-free phones, radar-based automobile -collision avoid- 
ance, acoustic diagnosis of mechanical equipment, and soft- 
ware-based ultrasound scanners. 

Over the previous year, Atmel has added features to the 
MADE (multicore-application-development environment) 
debugging capabilities. MADE, the Diopsis integrated de- 
velopment environment, includes C compilers for both 
ARM and Magic DSPs, a high-level Magic DSP macro-as- 
sembler/optimizer, an eCos RTOS, a library of C-callable 
DSP functions, and a unified debugging environment in- 
terfacing with a cycle -accurate simulator or a Diopsis board. 
The C-callable DSP library has grown from 75 to 125 func- 
tions. The library includes a variety of FFTs, IIRs, and FIRs 
on single- sample sequences or input- data streams; vectori- 
al square roots; vectorial magnitudes; and vectorial arith- 
metic and trigonometric operations, and a rich set of ma- 
trix functions. Atmel also introduced two boards for the 
Diopsis DSP — the Test and Evaluation Board and a Dual 
Diopsis PCI mezzanine card. 

CAMBRIDGE CONSULTANTS 

Cambridge Consultants' configurable VLIW APE2 DSP 
targets adaptive datapath signal-processing applications. The 
company based it on a software-DSP-generator tool kit. 
APE2 targets consumer-market applications such as wire- 
less, audio, and measurement systems by minimizing silicon 
cost and maximizing performance. For example, an APE2 
configured for a hearing- aid application requires fewer than 
20,000 gates and consumed less than 50 mW. De- 
signers use the generator tool kit to configure a 
VLIW DSP from ready-to-use processing 
elements it draws from the APE module 
library together with dynamic 
datapath routing. The starting 
point for algorithm design is generally 
Matlab, and the same operations are 
simulated using the APE software-tool 
kit. Once the system is working, the tool 
kit produces an APE2 DSP in the form 
of a Verilog netlist, together with the 



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assembly language to run the signal-processing task. 

During the previous year, Cambridge Consultants ex- 
tended the range of APE2 processing modules for math-in- 
tensive operations with trigonometric, vector, ratio, recip- 
rocal, coordinate-transform, square-root, exponent, and 
logarithmic functions. These modules complement the 
MAC, ALU, radix-4 FFT, sequencing, I/O registers, and 
memory- interface modules that were already available. De- 
signers can license the software-tool kit and transfer the 
APE2 technology into their teams. Alternatively, Cambridge 
Consultants can analyze a design s requirement and produce 
a silicon-ready APE2 IP core for integration into a licensee's 
ASIC project. APE2 license fees have no per- chip royalty. 

CEVA 

Last year, Ceva announced the Ceva-X architecture 
framework, a scalable VLIW-SIMD DSP architecture tar- 
geting baseband and multimedia applications, such as 3G 
multimedia phones, PDAs, digital cameras and camcorders, 
DTV and high- definition DVD. The first implementation 
of the Ceva-X family, the Ceva-XI620, combines micro- 
controller and signal-processing functions in a variable- 
width (16/32-bit) instruction set. The Ceva-X1620 can si- 
multaneously issue as many as eight instructions and offers 
high code compactness using SIMD concepts. The Ceva- 
XSllOO and Ceva-XS1200 are new complete systems built 
around this DSP architecture that include peripherals, in- 
terconnections, and interfaces to external memories, I/Os, 
and CPU systems. The Ceva-XSl 100 and Ceva-XS1200 are 
two DSP subsystems built around the Ceva-XI620 DSP. 
These subsystems include a 3-D DMA coprocessor to bet- 
ter target multimedia applications. The Ceva-XS includes 
interfaces to Level 2 memories, APB peripherals, and a CPU 
system based on 64-bit AHB-Lite master/slave ports. 

Ceva announced the Mobile-Media, a DSP-based multi- 
media platform that consists of a DSP core (based on Ceva- 
Teak or Ceva-X), a DSP subsystem (Xpert-Teak or Ceva- 
XS), and a set of optimized software modules that target the 
mobile multimedia market. The I6-bit-fixed-point, gener- 
al-purpose Ceva-Teak DSP core features a dual-MAC ar- 
chitecture for complex signal processing. It includes built- 
in accelerators for FFT and Viterbi to target portable- 
multimedia and wireless-communication applications. 
Ceva built the Xpert Teak subsystem around the Ceva-Teak 
dual-MAC DSP core; it includes a power- management unit, 
an interrupt controller, general-purpose I/Os, timers, on- 
chip emulation, TDM ports, and a code-replacement unit. 
It also includes a 3-D DMA engine to support multimedia 
applications through video-related data transfers. 

Ceva s fully programmable Mobile -Media platform sup- 
ports H.264 encoding and decoding at full Dl resolution, 
30 frames/sec, without any hard- wired acceleration. Other 
than the H.264 codec, Mobile-Media includes MPEG4, 
H.263, JPEG, and AAC codecs. Other audio codecs, such as 
MP3, WMA, AAC+, and AMR, are optional. Ceva also an- 
nounced the Ceva-TeakLite-II, a rewed-up DSP architec- 



ture based on its predecessor, the Ceva-TeakLite, to target 
2G/2.5G handsets and optical-disk applications. Other im- 
provements to the architecture include increased memory 
space and a higher level of system integration. 

-^-CHIPWRIGHTS 

Fabless semiconductor company ChipWrights offers 
video-processing technology to reproduce lifelike imagery 
in mobile personal-entertainment products, digital 
video/digital still "dual cams," and high-demand video ap- 
plications, such as security cameras and digital television. 
The new ChipWrights CW552I SIMD processor combines 
a RISC processor, a parallel processor with 16 32-bit data- 
paths, enhanced video-sensor features, USB, audio-codec 
compact flash, and secure digital- card interfaces. 

The ChipWrights development environment includes a 
software -development kit that integrates a compiler, a sim- 
ulator, a profiler, a linker, and a debugger into the Metro- 
werks Code Warrior integrated- development environment. 
The Reference Application Specific Libraries include re- 
sources for image processing, video and audio codecs, a 
ChipWrights BIOS, and development boards. 

-^-CIRRUS LOGIC 

Cirrus Logic's 32-bit CS4961XX family features an audio 
systems processor that integrates a DSP with dual MACs; 
dual memory moves; dual index registered update; and 
log/exp assist. Optimizations for butterfly FFT, FIR, and IIR 
with CobraNet technology deliver uncompressed digital au- 
dio over Ethernet networks. Cirrus Logic supports a library 
of audio algorithms, including THX Ultra2, DTS ES 96/24, 
Dolby Surround Pro Logic IIx, and a modular programming 
environment for easy customization. Cirrus Logic intro- 
duced the Intelligent Room Calibration software for auto- 
matic speaker setup and room equalization using its 
CS495XX and CS494XX DSPs. The framework includes 
state-of-the-art decoders, virtualizers, surround simulators, 
and audio-enhancement algorithms. Cirrus Logic's DSP 
A/V- receiver reference design includes a library for firmware 
feature differentiation. 

-^-CRADLE TECHNOLOGIES 

Cradle's 32-bit CT3000 family of programmable DSPs 
targets media-processing applications with a focus on 
video -surveillance applications, such as PC-based 
and embedded DVRs, IP streamers, and digital- 
video cameras. Other target applications 
include imaging and broadcasting. Over 
the previous year. Cradle intro- 
duced the CT3600 multiprocessor 
DSP family, comprising the CT3608, 
CT36I2, and CT3616. Each device con- 
sists of two computational quads made j 
up of processing cores, local data and in- 
struction memory, and separate ad-^ 
dress and data buses. In the CT3616, 



w.edn.c 



the family's highest performing member, each quad consists 
of eight single-issue pipelined DSP cores and four simple 
RISC-like general-purpose processors. A three-tiered mem- 
ory hierarchy increases performance predictability and scal- 
ability. Each quad includes 128 kbytes of shared data mem- 
ory and 32 kbytes of instruction cache, which the four 
general-purpose processors share. Each DSP has its own lo- 
cal instruction memory- and data- register file that enables 
the cores to run fairly autonomously. The family provides 
an I/O subsystem consisting of 18 programmable 8-bit pin- 
groups that can support interfaces including video 
(CCIR601/656), audio (PCM), 10/100 Ethernet, and IDE. 
This family provides a DDR-SDRAM interface. 

The CT3600 family uses the same multiprocessor DSP ar- 
chitecture as the CT3400, but it supports program execu- 
tion at 1.5 times the operating frequency and can include 
twice as many computational elements. Power consump- 
tion is 1 to 5W depending on device size, application, and 
operating frequency. The DSP instruction set supports spe- 
cial video and imaging instructions. The SAD (sum-of-ab- 
solute-difference) instruction accelerates the processing of 
motion estimation, and the PIMAC (packed-integer-mul- 
tiply- accumulate) instruction can perform 16 8 -bit MACs 
in a single cycle. 

DSP ARCHITECTURES 

This year, DSP Architectures began offering the full mil- 
itary version of the MILDSP24 and MILtMMU24 general- 
purpose signal processors. These products support extend- 
ed-temperature and 75 -MHz operation, which is higher 
than the commercially available 65-MHz DSP24. DSP Ar- 
chitectures has implemented a program to offer commer- 
cial (DSP24), military (MILDSP24), and rad-hard (RHD- 
SP24) silicon cores for customer-proprietary designs. 

The high-performance DSP24 vector-processor chip and 
its associated IP cores for signal and image processing in the 
frequency domain target applications that perform opera- 
tions on large arrays of data. It is a pass-based processor, with 
each function valid for one complete pass. Each operation 
code defines a basic flow for the desired operation that re- 
peats for multiple pairs of data to complete one pass. For 
typical array-processing applications, such as FFTs, the de- 
vice sets up a function code (for example, BFLY32). Radix32 
butterfly and then clocks the whole data array into the 
DSP24 and applies the function to it. Latency occurs when 
you implement the DSP24 functions, which the MMU24 au- 
tomatically compensates for when you use it in a system. The 
pipelined systolic structure allows you to cascade multiple 
DSP24s for increased performance and higher radices. This 
structure permits high-speed operation on an unlimited ar- 
ray size with support for enhanced read-only EFT, double- 
length EFT, dual EFT, and stacked EFT to reduce latency. 

EQUATOR 

Equator's MAP series of video-centric processors, which 
includes the MAP-CA, BSP-15 and the BSP-16 processors. 



performs the central functions of digital imaging, commu- 
nications, and media applications as software. The BSP-16 
device is the newest member of Equator's BSP (Broadband 
Signal Processor) family, which includes the DataStreamer 
DMA engine, an onboard IDE controller, and Ethernet 
MAC, all operating as fast as 500 MHz. The VLIW BSP-16 
CPU performs computationally intensive numeric and mul- 
tidimensional matrix operations in video- and signal-pro- 
cessing operations. It can run video- and image-processing 
algorithms, operating systems, network stacks, middleware, 
virtual machines for Java, and Internet browsers. 

The iMMediaTools software-development-tool kit con- 
sists of a suite of software tools, device libraries, and utili- 
ties for creating and optimizing video-centric applications. 
It features a VLIW tool chain with an ANSI C/C+ + com- 
piler; drivers to implement advanced video features, such as 
PIP (picture in picture); native support for Linux; Windows 
CE drivers; support for optimized audio and video per- 
formance from C/ C + + ; a multiformat media-player in- 
frastructure that supports trick play, PIP window, and 
graphics overlay; GDB source-level debugging; and an op- 
erating-system abstraction layer for codecs, application 
code, and player/ recorder infrastructure. 

Over the previous year. Equator introduced cost-reduced 
reference designs, including the Starfish and Babelfish set-top- 
box reference designs. The company expanded the platform's 
support for audio- and video-software codecs to include Win- 
dows Media Advance Profile, H.264, RealVideo, and aacPlus. 
The platform also includes support for additional condition- 
al-access and DRM (digital-rights-management) capabilities, 
such as Windows Media DRM 10. Equator hardware refer- 
ence platforms also include reference designs targeting IPTV 
(Internet Protocol television), digital home and consumer 
electronics, security/surveillance, and videoconferencing. 

-^FREESCALE 

This year, Freescale introduced the MSC71xx family of 
DSPs, basing it on StarCore technology, with a DDR- 
SDRAM controller. This family of devices targets enterprise 
VOIP, IP PBX (private-branch-exchange), and network- 
edge and -access applications scaling from four to hundreds 
of channels in fractional or multiple Tl/El increments. The 
family varies by peripheral sets, with the MSC7116 and 
MSC7113 targeting developers of Ethernet-only 
equipment. The MSC711x family of devices is 
pin-to-pin compatible and offers the same in- 
struction-set and binary software com- 
patibility with Freescale's StarCore 
technology-based MSC8 Ixx fam- 
ily. It also provides Ethernet, 
DMA, and TDM communications 
peripherals. 

The MSC81xx family of devices in- 
cludes both high-performance single- 
core and multicore digital-signal 
processors. The single-core devices 



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EDN2m DSP DIRECTORY 



MSC8101 and MSC8103 and the multicore devices 
MSC8102, MSC8122, and MSC8126 are all software-com- 
patible. Both product lines target computationally intensive 
infrastructure DSP applications, including packet telephony, 
media gateways, multichannel modem banks, and third-gen- 
eration wireless systems. The newest devices, the MSC8122 
and MSC8126, are available with 300-, 400-, and 500-MHz 
core speeds, and Freescale bases them on 90-nm-process 
technology. The MSC8122 and MSC8126 can deliver 8000 
DSP MMACS at 500 MHz, yielding an effective performance 
equal to 2 GHz. 

Freescale also announced the addition of a 275 -MHz speed 
to the DSP5632 1 , a member of the DSP563xx family that can 
perform 550 MMACS when its Enhanced Filter Coproces- 
sor is in use. This device maintains the same full temperature 
qualification of — 40 to + 105°C as its predecessors. Freescale s 
24-bit, floating-point-architecture DSP563xx processor fam- 
ily targets wireless and wireline infrastructure and commu- 
nications equipment, as well as packet telephony, professional 
audio, scientific test and measurement, industrial control, 
and healthcare related medical equipment. This family 
includes the DSP56321, DSP56311, DSP56L307, DSP56309, 
DSP56303,and DSP56301. 

Freescale also introduced the 56F8100 series of devices for 




price -sensitive industrial and consumer applications. It bases 
the series on the 56800E hybrid digital-signal-controller 
core, which integrates the instruction set of a DSP with the 
control functions of an embedded microcontroller in a sin- 
gle core. The 56800 family targets applications that tradi- 
tionally use 16-bit microcontrollers but also require DSP 
functions, such as point-of-sale and voice-recognition ap- 
plications, digital-telephone-answering devices, motor-con- 
trol systems, and applications requiring voice, audio, or data 
processing. 

Freescale's CodeWarrior tool suite from Metrowerks, in- 
cluding the SmartDSP operating system and CodeTest soft- 
ware-analysis tools, provides development support for all of 
these processor families. Freescale's Smart Packet Telephony 
Hardware Reference Design is for small- to large-scale me- 
dia-gateway equipment capable of voice, fax, or modem data 
services. System architects may use this evaluation platform 
to assess the capabilities of Freescale's DSPs for voice com- 
pression and echo cancellation. Trinity Convergence provides 
the VeriCall software framework to provide a flexible, open 
architecture for VOIP designs based on Freescale's MSC7I Ix 
and MSC81xx family of DSPs, the PowerQuicc family of in- 
tegrated communications processors, PowerPC host proces- 
sors, and C-3/C-5 network processors. 



> HYPERSTONE 

Hyperstone's HyNet32S, a scaled-down version of the 
HyNet32XS networking processor, features the same El- 
32XSR RISC/DSP core but adds PCI bus funcfions. Hyper- 
stone builds the HyNet series of networking processors 
around the E1-32XSR core and adds integrated peripherals 
supporting high-speed communications (Ethernet, Real 
Time Ethernet, Serial, ATM), additional internal RAM, video 
interfacing, PCI support, DMA, and more. These proces- 
sors target applications requiring high-speed signal process- 
ing; communications, including real-time Ethernet; or both. 

Hyperstone's El - 16XSR/32XSR RISC/DSP processors pro- 
vide seamless integrated RISC/DSP functions for any appli- 
cation requiring a high-speed microprocessor coupled to a 
high-performance DSP. These processors feature dual execu- 
tion units (RISC/DSP) in a pipelined architecture sharing the 
same registers. Developers can transparently mix RISC- and 
DSP-specific programming. Devices execute RISC/DSP 
instructions with a high degree of parallelism, resulting in high 
throughput. Typical target applications for use are telephony, 
video, digital cameras, general signal processing, and more. 

Hyperstone offers hardware- and software- development 
tools, including a real-time kernel, a C compiler, an assem- 
bler, a linker, an EPROM formatter, a source-level debugger. 



and several hardware target boards. Also available is the 
HyNetOS full- featured operating system, which includes a 
collection of communication-protocol stacks, including real- 
time Ethernet; a file system; and memory management. Hy- 
perstone is also offering an application- specific hardware tar- 
get board for use in the development of real-time Ethernet 
applications, such as Ethernet Power Link. 

LSI LOGIC 

The ZSP Products Division of LSI Logic is a licensor of sig- 
nal-processing cores and products. LSI Logic also offers stan- 
dard product offerings for lower volume designs and 
prototype implementations. The ZSP processor ar- 
chitecture targets 3G wireless handsets, mul- 
timedia, and networked voice appliances. 
ZSP Solution Partners augment the 
technology with software tools, EDA- 
modeling support, and a portfolio of ap- 
plication software. Over the previous year, 
the ZSP Products Division expanded its sig- 
nal-processor family to include the ZSP- 
540 licensable core, the less-than-$4 (high 
volumes) LSI403LC standard product, 
and the off-the-shelf, bundled silicon/ 







We don'tjust malorintegrated products, 



we develop integreated solutions 



Americas Headquarters 

Lisle, Illinois 60532 
U.S.A. 

Tel: 1-800-78MOLEX 
amerinfo@molex.com 

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Headquarters 

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Tel: 81-462-65-2324 

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© 2005, Molex 



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Whether you're looking 
to consolidate connector 
content into a sub-module 
or consolidate signals for 
higher density and higher 
speed, Molex Integrated 
Products teams can help. 
Need an I/O hub with a 
mix of connector content? 
Want to consolidate switch 
and connector functionality 



onto a single PCB? Or 
maybe you just need a 
matching connector and 
cable assembly- 
Whatever your challenge, we 
collaborate with your design 
team to model the most 
technologically appropriate 
solution and then coordinate 
production worldwide to 



achieve outstanding quality 
and deliver a great solution 
with increased value to both 
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Molex has the global 
technology, facilities and 
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ensure rapid quoting and 
prototyping, real time 
collaboration, end-to-end 



project tracking and 
management, consistent 
quality control across facilities 
and the shortest time-to- 
market possible. Our 
engineers are experts at 
understanding the context of 
your application, the context 
of your signal requirements 
and the context of your total 
applied cost parameters. 



Call Molex today or visit 
us at www.molex.com/ 
product/ ipd to find out 
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add integreated value to 
your application. 



molex' 



Bringing People & Technology 
Together, Worldwide"^ 



www.molex.com/product/ipd 



Enter 28 at www.edn.com/info 



software Z. Voice- 729 package for VOIP applications. 

The high-performance, power- efficient, quad-MAC, six- 
ALU ZSP540 DSP core deUvers 1.2 GMACS on a 0.13-mi- 
cron process. The ZSP540 core includes the Z.Turbo tech- 
nology for application- specific acceleration targeting 2.5/3G 
baseband processing, multimedia wireless/mobile devices, 
WLAN, and VOIP applications. The LSI403LC DSP targets 
cost- sensitive applications requiring low power consump- 
tion and can gluelessly interface to popular microproces- 
sors. Its large on-chip memory eliminates the need for ex- 
ternal memory. ZSPneo, a new entry point to the ZSP road 
map, targets cost- sensitive applications that require control 
processing beyond 8- and 16-bit-microcontroller perform- 
ance but cannot tolerate the cost and overheads associated 
with a 3 2 -bit microcontroller. ZSPneo also targets one- or 
two-channel VOIP, audio players, speakerphones, wireless 
application processors, toys, and servo and vehicle controls. 

LSI Logic's DSE (DSP Solutions Engineering) team, a 
worldwide network of DSP systems experts, provides di- 
rect consultation, training, application notes, bulletin 
boards, and access to the KnowledgeBase FAQ database. DSE 
works with ZSP Solution Partners to develop reference de- 
signs and sample systems in the form of boards, RTL, and 
SystemC models. 

MICROCHIP 

Microchip this year released to production 15 devices in 
the dsPIC30F DSC (digital- signal- controller) family. The 
two sensor devices target space-constrained applications 
with package options as small as 6X6 QFN. The nine gen- 
eral-purpose devices support a range of flash-program- 
memory sizes from 24 to 144 kbytes. The four motor-con- 
trol/power-conversion devices feature a PWM and an ADC. 
Microchip also introduced a series of application libraries, 
including noise suppression, echo cancellation, speech 
recognition, and encryption that designers can evaluate for 
a $5 license fee. 

Microchip s dsPIC30F DSC, a 16-bit modified Harvard 
machine, combines the control advantages of a microcon- 
troller with the computation speed of a fully implemented 
DSP in a single-chip, single -instruction- stream architecture. 
All dsPIC30F DSCs execute from flash program memory 
and feature a familiar microcontroller architecture and de- 
sign environment. The dsPIC DSCs feature flash memory, 
EEPROM, software stacks, a strong interrupt structure, 
mixed-signal capability, low-pin-count options, and real- 
time emulation. The dsPIC DSC also features dual-operand 
fetches, a barrel shifter, zero-overhead loops, and single-cy- 
cle 16X16 MAC with twin 40-bit accumulators. 

The dsPIC30F tools operate seamlessly within Mi- 
crochip's Mplab integrated development environment, a 
free tool suite that includes the Mplab ASM30 assembler and 
the Mplab SIM software simulator for writing and testing 
dsPIC30F code. Also available is the dsPIC30F Visual De- 
vice Initializer. A full-featured 60-day demo of the Mplab 
C30 C compiler is available in a download. Hardware tools 



include the ICE4000 Emulators, ICD2 in- circuit debuggers, 
and programmers to assist with in-circuit serial program- 
ming. Third parties have extended their lines of embedded 
cross-compilers to cover the dsPIC30F devices. 

-^-MORPHO TECHNOLOGIES 

Morpho Technologies' MSI -16, an optimized rDSP IP 
core, targets high-performance wireless-infrastructure and 
power- optimized mobile devices, such as multimode wire- 
less base stations and multimode 3G wireless handsets. The 
cores are optimized for the baseband-processing require- 
ments in wireless standards. The M-rDSP architecture com- 
bines the power of a software-programmable, 32-bit RISC 
processor (mRISC) and an eight- to 64-cell reconfigurable 
cell array. Each reconfigurable cell contains an ALU, a MAC, 
and logic units, as well as specialized functional units that 
designers can use for wireless applications. The reconfig- 
urable cell array can switch from one application- specific 
set of instructions to another in one clock cycle. For 3G wire- 
less chip -rate processing, each reconfigurable cell contains 
a complex- correlator unit as a specialized functional unit. 

Morpho has mapped optimized software-kernel libraries, 
based on various communication algorithms, into its M- 
rDSP core and provides reference -software applications that 
demonstrate communications protocols and standards. 
Morpho provides a fully synthesizable core, a C + + cycle- 
callable simulation model of the M-rDSP Core, synthesis 
scripts/test benches, a "C" compiler, a simulator (bit accu- 
rate/cycle accurate), a library of preoptimized kernels, de- 
bugging tools, and detailed documentation. It offers hard- 
ware-development systems and software tools that it bases 
on a proprietary software-tool chain that follows the most 
commonly used and understood tools in the market today. 

PHILIPS SEMICONDUCTORS 

The PNXI700, the newest member of Philip's Nexperia 
family of media processors, targets connected multimedia 
products, such as IP set-top boxes, digital-media adapters, 
personal video recorders, videophones, and televisions. In 
addition to having high- definition video capabilities, the 
PNX1700 connected media processor doubles the per- 
formance of previous generations, and maintains hardware 
and software compatibility. It features a 500-MHz, 32-bit, 
superpipelined TriMedia CPU core integrated with 
a TFT (thin-film-transistor) LCD controller, an 
Ethernet 10/100 MAC, and multimedia and 
floating-point instructions for image scal- 
ing, advanced deinterlacing, and 2-D 
graphics acceleration. The PNX- 
1700 supports dynamic frequency 
and power management that enables 
designers to tailor power consumption 
to the application requirements. 

Philip's Nexperia PNX5220 cellular 
multimedia baseband, with dual Ade- 
lante 16-bit RD 16024 DSP cores and 



ALL THINGS E L E C T R N I C- S T A R T WITH MICROCHIP 




mm 




Approximate size of tlie dsPiCSOF QFN package 



The cost-effective 6x6 mm dsPIC® 
lowers your product cost. 

The dsPIC Digital Signal Controller is a single chip, 
single instruction stream blend of a 30 MIPS 
DSP and a full-featured 16-bit microcontroller. 
All devices execute from Flash memory and can 
be reprogrammed in the field. These devices are 
currently in production and have best-in-class 
C code density, the smallest package in its 
performance class, significant integrated peripheral 
options, mixed-signal capability and cost-effective 
price points. All products have PC™, i Msps 10-bit 
ADC or 200 ksps 12-bit ADC, timers, an EEPROM 
range between 1024 and 4098 bytes. Selected 
devices have a codec interface or an advanced 
PWM and quadrature encoder interface to offer the 
perfect solution for your next design. 

The dsPIC Digital Signal Controller shares the same 
MPLAB'' Integrated Development Environment (IDE) 
with all Microchip microcontrollers. Visit us online to 
learn more about this exciting family and download 
a free 60-day MPLAB C30 C Compiler demo today. 



Digital Signal Controller reduces components and 



Product 


Pins 


Program 
Memory 
(Kbytes) 


RAM 
(Bytes) 


Codec 
Interface 


Capture/ 
Compare 


UART 


SPI™ 


1 

CAN 


dsPIC30F2010 


28 


12 


512 





4/2 


1 


1 





dsPIC30F3010 


28 


24 


1024 





4/2 


1 


1 





dsPICSOFSOll 


40/44 


24 


1024 





4/4 


2 


1 





dsPIC30F3012 


18 


24 


2048 





2/2 


1 


1 





dsPICSOFSOia 


28 


24 


2048 





2/2 


2 


1 





dsPIC30F3014 


40/44 


24 


2048 





2/2 


2 


1 





dsPIC30F4011 


40/44 


48 


2048 





4/4 


2 


1 


1 


dsPIC30F4012 


28 


48 


2048 





4/2 


1 


1 


1 


dsPIC30F4013 


40/44 


48 


2048 


AC97, PS 


4/4 


2 


1 


1 


dsPIC30F5011 


64 


66 


4096 


AC97, FS 


8/8 


2 


2 


2 


dsPIC30F5013 


80 


66 


4096 


AC97, PS 


8/8 


2 


2 


2 


dsPIC30F6010 


80 


144 


8192 





8/8 


2 


2 


2 


dsPIC30F6011 


64 


132 


5144 





8/8 


2 


2 


2 


dsPIC30F6012 


64 


144 


8192 


AC97, PS 


8/8 


2 


2 


2 


dsPIC30F6013 


80 


132 


6144 





8/8 


2 


2 


2 


dsPIC30F6014 


80 


144 


8192 


AC97, PS 


8/8 


2 


2 


2 



MI&^iaCHIP 

ONLINE CATALOG 

One-stop shopping for MCUs, digital signal 
controllers, analog and serial EEPROMs. 



Jump start your designs with software 
libraries available for only $5!"^ 

Looking to add noise suppression, encryption, acoustic eclno 
cancellation or speech recognition to your application? These libraries 
and others are available now for the dsPICSOF devices with a $5.00 
license fee for evaluation or development, and a low one-time fee for 
production. 




Now- 



Microchip 

www.microchip.com/dsPIC 

Enter 29 at www.edn.com/info 



' Evaluation license containing the same software as the production license. Visit www.microchip.com for more information. The Microchip name and logo, the Microchip logo, dsPIC and MPLAB are registered 
trademarks of Microchip Technology Incorporated in the USA and in other countries. ©2005 Microchip Technology Incorporated. All rights reserved. 



an ARM926 subsystem, targets feature-rich mobile hand- 
sets and smart-phone appHcations. It supports quadband 
850-, 900-, 1800-, and 1900-MHz operation for GSM, GPRS, 
and EDGE and dual-band operation for UMTS. One DSP 
core handles the communication modem, and the other 
core performs the advanced audio features. Audio-process- 
ing support includes 64-voice stereo polyphony, enhanced 
AAC+ codecs, MP3 decoding, and wideband speech pro- 
cessing. Baseband-processing support includes a full soft- 
ware EDGE receiver and up to class 123 and SAIC (single- 
antenna interference cancellation). The Nexperia PNX5220 
uses the 208-MHz ARM926 subsystem with hardware ac- 
celerators for application processing. 

The PNX5220 memory architecture for the baseband 
processing uses multiple parallel buses to support NAND 
flash, SDRAM, cellular RAM, and burst-mode/page-mode 
memory. The ARM9 processor core uses a multilayer AHB 
structure to separate slow external peripherals from fast ex- 
ternal memories to optimize the interaction with on- and 
off-chip memories. The PNX5220 has built-in Java accel- 
eration and uses independent processing units as bus mas- 
ters to enable the functional units to form a balanced net- 
work. The PNX5220 runs video at 30 frames/sec in GIF 
resolution and provides the hooks for GPS and other con- 
nectivity functions, such as WLAN and Bluetooth. It also al- 
lows the phone to connect via mobile connectivity stan- 
dards, such as USB OTG (on the go) and fast IrDa. 

The Philips' Adelante DSP technology includes the 16-bit 
RD 1 602x DSP core family and the 24-bit RD24 1 2x DSP core 
family with a user- definable VLIW architecture. The 
RD 16024 is the newest 16-bit programmable DSP core. The 
24-bit Philips' Adelante RD24121 DSP core, with its 56-bit 
accumulator size, has an advanced instruction-set architec- 
ture suitable for audio applications requiring a high dynam- 
ic range. This architecture enables designers to trade between 
performance and operating voltage to enable lower power 
operation. The RD24121 includes an eight-stage pipeline 
with an orthogonal-register-file approach beneficial for the 
C compiler. 

The Adelante software-development kit for multicore 
SOC architectures includes a graphical front-end with ac- 
cess to the underlying tool components, such as the com- 
piler, assembler, linker, simulator, emulator, and profiler. It 
also offers a standard DSP firmware library with a set of 
DSP-related functions, such as FFT, FIR, and geometric 
functions. Philips makes available an FPGA-mapping of the 
DSP core and subsystem. 

RC MODULE 

RC Module bases its NeuroMatrix NM6403 DSP family 
of dual-core application-specific DSP processors on the 
NeuroMatrix Core. It targets video-image processing, radio- 
navigation, and radar applications and provides scalable 
performance by employing a programmable operand width 
of 1 to 64 bits; this flexibility allows designers to trade pre- 
cision for performance. The NM6403 processor includes a 



32/64-bit RISC processor and a 1- to 64-bit vector co- 
processor that supports vector operations with elements of 
variable bit lengths. 

This year, RC Module introduced a new software-devel- 
opment kit for the NeuroMatrix NM6403 RISC/DSP 
processor. The NM-SDK Version 2.0 includes an optimiz- 
ing C+ + compiler (ISO/IEC 14882:1998 standard) and 
real-time DSP and video-image processing libraries. The 
compiler more closely adheres to the C+ + standard, in- 
cluding templates, and uses the enhanced optimizing algo- 
rithms that allow increasing program execution speed and 
decreasing code size. The assembly language has an intuitive 
syntax and is close to high-level languages so it can simpli- 

the development and understanding of source code for 
math- intensive real-time algorithms. 

The MC2301 PCI digital- signal memory-evaluation 
board targets high-frequency analog- signal processing, com- 
plex high-frequency analog-signal generation, and DSP 
software/hardware prototyping and development. The 
MC2301 has one 1879BM3 DSM SOC, a 64-Mbyte SDRAM 
bank, analog input and output buffers, and a PCI-host in- 
terface. The shared memory is accessible for reading and 
writing both from the digital-signal memory chip and from 
the PCI bus. The MC2301 features a programmable 128-bit 
on-chip controller; a DSP core; 2-Mbit on-chip SRAM; two 
600M-sample/sec, 6-bit ADC inputs; two 600M-sample/sec, 
8-bit DAG outputs; and 64 Mbytes of onboard SDRAM. 

-^-SENSORY 

Sensory's RSC family of devices performs recognition, 
speech synthesis, and general-purpose product control. The 
RSC line includes a 16-bit ADC, a 10-bit DAG, an alterna- 
tive PWM output amplifier, 128 kbytes of on-chip ROM, 4 
kbytes of on-chip RAM, comparators, timers, and general- 
purpose I/O. The RSC-4x provides on-chip integration of 
features, including a microphone preamplifier, twin-DMA 
units, vector accelerator, hardware multiplier, timers, and 4.8 
kbytes of RAM. You can build a complete system with little 
more than a battery, a speaker, a microphone, and a few re- 
sistors and capacitors. Multiple ROM options are available. 

Over the previous year. Sensory introduced FluentChip 
firmware, which enables higher accuracy, larger vocabular- 
ies, improved speech compression, better trigger- word de- 
tection and rejection, more noise tolerance, improved 
speaker- dependent recognition performance, and 
more instruments for music. The RSC line sup- 
ports speaker-independent recognition, 
speaker-dependent recognition, speak- 
er verification for voice biometric 
security, speech compression for 
speech playback (high-quality, 2400- 
bps compression), and music synthesis 
at no additional cost. 

The RSC programming and debug- 
ging tools include the Phyton macro 
assembler, a C compiler, and an in- 



The Missing Link 





ardCopy 




The Structured ASIC that Links the FPGA & ASIC Worlds. 



No compromises. 



When you need the performance, power consumption, 
HARDCOPY II and cost of an ASIC with the flexibility and time-to- 
market of an FPGA, HardCopy®II devices are the 
answer. Altera offers the only structured ASIC solution available 
with an FPGA front-end design methodology. Minimize development 
cost and risk by verifying your design in-system with a Stratix®II 
device, then move seamlessly to a HardCopy II structured ASIC for 
volume production. 

Supported by ^ 

Visit www,altera.com/hardcopy2 today and link 
your design to risk-free, high-volume production quartus'ii 
without compromises. 



• First-silicon success guaranteed 

• Up to 2x faster than FPGAs 

• Less than half the power of FPGAs 

• Fully supported by industry-standard tool flows 

• Priced for high-volume, cost-sensitive applications 



The Programmable Solutions Company® 
www.altera.com/hardcopy2 



Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, tlie stylized Altera logo, specific device designations, and all other words and logos that are 
identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names 
are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyriglits. "First-silicon success 
guaranteed" means that HardCopy devices are guaranteed to be functionally equivalent to the Altera FPGA defined in the customer's design files. 

Leading through innovation. 

Enter 30 at www.edn.com/info 





circuit emulator, all running in an integrated development 
environment. Hardware demonstration and evaluation 
boards are available for testing and prototyping. The speech 
tools include Sensory's QuickT2SI speaker-independent 
recognition- set development tools and QuickSyn thesis 
speech compression for playback of voice files. 

i^STARCORE 

StarCore develops and licenses the StarCore processor ar- 
chitecture to OEMs and semiconductor suppliers as a fam- 
ily of fully synthesizable cores and subsystems. The StarCore 
subsystems provide scalable performance across a range of 
communication, wireless, and multimedia applications. 
They include a complete set of subsystem IP blocks, such 
as memory controllers, an interrupt controller, and an ac- 
celerator interface to reduce development time. The design 
is fully synthesizable, making it readily transferable from one 
foundry to another as market and product needs change. 

StarCore has expanded the SCI 000 instruction set to in- 
clude video-processing instructions, improved code densi- 
ty, and enhanced RTOS support for mobile multimedia ap- 
plications, such as smart phones, digital still cameras, and 
digital camcorders. StarCore also offers the SC2000 family, 
which is fully binary compatible with the SCI 000 series of 
products, for video and portable multimedia. The two-MAC 
SC2200 and four-MAC SC2400 include dedicated video- 
processing instructions, additional RTOS support, im- 
proved code density, and improved power consumption. 
The SC2400 family of processors offers a 60% improvement 
in multimedia performance over the SCI 400 family of 
processor products. 

The SC2200 and SC2400 processor cores are available in 
synthesizable Verilog RTL. The SP2201 and SP2401 subsys- 
tems support embedded applications, featuring enhanced 
multimedia performance with on-chip emulation, memo- 
ry interfaces, a DMA interface, an AHB- compliant system 
bus-interface, a clock-control unit, and an interrupt-con- 
trol unit. The SP2202 and SP2402 subsystems support ad- 
vanced applications, including all the features of the SP2201 
and SP2401 subsystems, plus data- and program-cache con- 
trollers, a memory-protection unit, and a high-speed inter- 
face to connect application-specific accelerators. 

■^STMICROELECTRONICS 

STMicroelectronics' new ST 140 quad-MAC DSP core ex- 
tends the ST 122 dual-MAC implementation of the ST 100 
architecture that targets cellular-phone -infrastructure ap- 
plications. The ST 140 DSP is available as soft IP or hard 
macros, and it includes Viterbi- specific instructions and the 
ability to support user-defmed operators. STMicroelec- 
tronics can map the core in various technologies and offers 
it with a full set of interfaces, peripherals, and memory IP. 
The architecture maintains software legacy between both 
cores and emphasizes the C ST 100 compiler technology to 
benefit from a high level of processing parallelism directly 
from C source code. 



The development environment supports modeling, pro- 
filing, optimizing, and debugging for any ST 1 40 -based ap- 
plication, including multicore designs. The STMicroelec- 
tronics technical-support team provides on-site training and 
brings day-to-day dedicated support to customers. 

-^-TENSILICA 

Tensilica's configurable, extensible, and synthesizable 
Xtensa LX processor core enables designers using the Ten- 
silica processor-generator tool to build Xtensa LX proces- 
sors that exactly fit the target task. The designer selects and 
configures predefined processor attributes and, by using 
TIEs (Tensilica Instruction Extensions), adds Verilog de- 
scriptions of execution datapaths, I/O ports, and registers 
that can deliver performance, area, and power characteris- 
tics equivalent to custom-logic design. Over the previous 
year, Tensilica introduced the Xpres compiler, which can an- 
alyze the designer's C/C+ + code and automatically suggest 
and generate the TIE instructions to optimize the proces- 
sor for the application. 

Tensilica's Xtensa LX processor core with Vectra DSP en- 
gine supports wide datapaths and traditional DSP tasks. The 
system can deliver RTL- equivalent I/O through a ports- and 
queues-mechanism that directly connects to the processor's 
execution unit to bypass the load/store operation. The Vec- 
tra LX DSP engine takes advantage of the Flix architecture 
and uses 64-bit instruction words containing three issue 
slots for ALU, MAC, and load/store operations. Tensilica of- 
fers Web -based design support and an FPGA-based devel- 
opment board and can customize the Vectra LX DSP engine 
on a consulting basis. 

TEXAS INSTRUMENTS 

Texas Instruments' 90-nm, 1-GHz TMS320C6414T, 
C6415T, and C6416T DSPs target audio, speech, video, and 
imaging applications. Also new is a 720-MHz version of the 
TMS320DM642 DSP-based digital-media processor target- 
ing consumer electronics and set-top boxes. The DM642 de- 
livers high-definition video streams in Microsoft's WMV 
HD (Windows Media Video high-definition) at 720-pixel 
resolution and processes standard- definition video decod- 
ing for the H.264 format. The new TMS320R2811 and 
R2812 digital- signal controllers target industrial, automo- 
tive, sensing, flow metering, and e-metering applications 
by providing 20k words of on-chip SRAM and al- 
lowing developers to add unlimited external 
memory to their designs via the SPI port. 
They include an integrated high-speed, 
multichannel, 12-bit ADC to 
measure system parameters and 
respond quickly to meet the input- and 
output-intensive requirements specific 
to applications such as precision e-me- 
ters and flow meters. 

The TMS320C6000 DSP platform 
comprises the TMS-320C64x, TMS- 



niRRUS LOGIC 



Leading the Digital Entertainment Revoiution ^ 



WW 




M f I! 




High-End Performance 



• 24-bit, up to 192 kHz sample rates 

• Multi-bit Delta-Sigma architecture 

• 1 05 dB dynamic range 
•-95 dB THD+N 

• Analog input multiplexer, 6 stereo pairs 
and pass-through mode 

• PGA: ±1 2 dB gain, 0.5 dB step sizes 
with zero crossing 

• Digital volume control 

• Overflow detection 

• +3.3 V or +5 V power supply 

• 48-pin LQFP, lead-free assembly 

• CS4245 CODEC price: US $2.45 ( 1 OK) 

• CS5345 ADC price: US $ 1 .95 ( 1 OK) 
Authorized Distributors 

North America 

Memec Insight 
800-677-7716 

www.insight.na.memec.com 

Newark InOne 

800-463-9275 
www.newarkinone.com 



New ICs Deliver Excellent Audio Performance 
in Today's Entertainment Systems 

Innovative Designs Lower BOM Costs and Reduce Board Space Requirements 



CS4245/CS5345 



Consumer electronic designers now have 
an integrated IC solution that delivers 
premium audio performance and stream- 
lines product development while reducing 
board design complexity, size and cost. 

Cirrus Logic's new CS4245 stereo 
CODEC and CS5345 stereo ADC are 
pin-compatible, highly integrated audio 
converters. The front-end of both IC's 
features an integrated analog input selec- 
tor to accommodate up to 6 stereo audio 
sources. Also included is a program- 
mable gain amplifier capable of ±12 dB 
analog gain in 0.5 dB step sizes with zero 
crossing, click-free transitions to maintain 
audio quality. One pair of inputs has a 
dedicated microphone pre-amplifier in its 
path that provides +32 dB of gain. 

A multi-bit Delta-Sigma stereo A/D con- 
verter provides 24-bit conversion and 
output sample rates up to 192 kHz. A 
high-pass filter is included for DC offset 
removal, and a dedicated pin is available 
for detecting overflow conditions. The 
24-bit, 192 kHz stereo DAC in the 



Applications 



• DVD recorders 

• DVD receivers 

• Digital video recorders 

• Digital televisions 

• Set-top boxes and home media centers 

• Automotive entertainment systems 

• PC sound cards 

• Effects processors 

CS4245 stereo CODEC is also based 
on a multi-bit Delta-Sigma architecture, 
includes digital attenuation, and pro- 
vides high-quality single-ended outputs 
with Cirrus Logic's patented Popguard® 
technology to eliminate power cycling 
clicks and pops. 

Engineered for performance, this new 
CODEC and ADC pair delivers profes- 
sional audio quality at a breakthrough 
price point. To order samples or obtain 
further product information, please con- 
tact your local Cirrus Logic distributor or 
visit our Web site today. 



www.cirrus.com/proaudio 

Enter 31 at www.edn.com/info 



© 2004 Cirrus Logic, Inc. All rights reserved. Cirrus Logic, Popguard, and Leading the Digital Entertainment Revolution are trademarks of Cirrus Logic, Inc. 
Other brand and product names may be trademarks or service marks of their respective owners. 



fM2005 PSR DIRECTORY 




1 



320DM64x and TMS320C62x fixed-point generations as 
well as the TMS320C67x floating-point generation. The 
C64x generation of high-performance DSPs targets broad- 
band and video infrastructure as well as video and imaging 
applications. The DM64x generation of programmable 
DSP-based media processors targets streaming and multi- 
media applications. The C62x fixed-point family targets 
multichannel, multifunction applications; the C67x float- 
ing-point DSP generation targets home audio, industrial au- 
tomation, voice and speech recognition, as well as high-end 
graphics and imaging. 

The TMS320C5000 DSP platform comprises the 
TMS320C54X and TMS320C55x fixed-point generations. 
The C54x generation consists of more than 17 code-com- 
patible devices covering a range of performance and pe- 
ripheral options, as well as low-power operation. The 
TMS320C55X generation includes power- efficient DSPs. 
The new TMS320C5503, TMS320C5507, and TMS320C- 
5509A DSPs offer a combination of performance, memo- 
ry, peripherals, and low power, targeting mobile, portable, 
and other low-power, real-time-signal-processing applica- 
tions. These devices feature standby power at 0. 12 mW. The 
new TMS320C5405, a 16-bit, fixed-point DSP available in 
a 7X 7-mm package targets systems emphasizing small size, 
low power consumption, and lower cost. 

Texas instruments also released the C5000 Low-Power 
Design Tools within the eXpressDSP tools. The design-tool 
suite includes power-planning tools to create trial configu- 
rations and determine the net power consumption; power- 
management routines within the DSP/BIOS to automati- 
cally implement power saving strategies at the operating- 
system level; a power- scaling library to implement power 
scaling through dynamic control of the runtime core fre- 
quency and voltage; and integration with National Instru- 
ments' application power-measurement tools to help de- 
signers visually measure and analyze power in their systems. 

Texas Instruments' TMS320C2000 digital-signal 
controllers combine DSP technology with micro- 
controller-peripheral integration. The TMS- 
320C28x generation includes 32-bit DSP-based 
controllers with onboard flash memory or ROM 
and offers performance to 150 MIPS for control 
algorithms in real time, such as sensorless speed 
control, random PWM, and power-factor correc- 
tion supporting control-, automotive-, and in- 
dustrial-motor applications. The TMS320C24x 
generation offers 20 to 40 MIPS of DSP performance with 
integrated flash memory or ROM and targets control algo- 
rithms in cost- sensitive and space-constrained applications, 
such as consumer white goods. 

Texas Instruments and Ateme jointly announced the net- 
work-video-development kit, based on the I -GHz TMS- 
320C64x DSP, targeting broadcast head-end and advanced 
digital-media and video applications. Texas Instruments 
and Wintech Digital Systems offer the videophone-devel- 
opment platform for designing point-to-point IP-based 



You can reach Technical 
Editor Robert Cravotta at 
1-661-296-5096, e-mail 
rcravotta@edn.com. 




videophone systems using the 600-MHz DSP-based TMS- 
320DM643 digital-media processor. 

-^-3DSP 

The soft-IP-core, fixed-point DSP family, bus controller, 
peripherals, and microprocessor interfaces from 3DSP use 
a scalable 3 2 -bit SuperSIMD architecture. The core supports 
multiprocessor systems, program cache or direct-mapped 
program memory, prioritized interrupts, and a JTAG-only 
debugging interface. The 3DSP core supports two SIMD 
multiplier options. The first option is a dual 24 X 16-bit mul- 
tiplier that can perform two 24 X 16-bit multiplies, four 
16 X 16-bit multiplies, or eight 8 X 16-bit multiplies in a sin- 
gle cycle. The second option is a dual 32 X 32-bit multiplier 
that can perform all the functions of the 24 X 16-multiplier 
and two 32 X 32-bit multiplies in one cycle. 

The programmable, five-stage-pipelined DSP SP-3 core 
targets MP3 -player, home-audio (AAC, AC3), wireless- 
GSM-phone, GPS, and CPE (customer-premises-equip- 
ment) VOP (voice-over-packet) -processing applications. 
The programmable, superscalar, dual-issue, five-stage- 
pipelined SP-5 core DSP targets 3G wireless, VOIP gateway, 
xDSL, MPEG2, MPEG4, and wireless-LAN apphcations. 
The programmable, dual-mode, nine-stage-pipelined SP- 
20/UniPHY DSP- IP core targets multimedia applications 
including multimedia over wireless. The "soft- datapath" 
technology and programmability enable a "softPHY" im- 
plementation that facilitates modification for changing 
physical-layer standards. 

XILINX 

Xilinx supplies programmable-logic devices, design tools, 
algorithms, and services. The Virtex-4 family of FPGAs de- 
livers as many as 512 500-MHz XtremeDSP slices that tar- 
get high-performance applications, such as digital radios 
and baseband cards for narrowband, spread- spectrum, mul- 
ticarrier communication systems, and high-per- 
formance video- and image-processing systems. 
The lower cost Spartan-3 family of FPGAs targets 
high-volume applications, such as multimedia 
boxes and displays. 

Xilinx and its partners support Xilinx 
XtremeDSP, which includes more than 100 algo- 
rithms, and the System Generator for DSP 
tool, which enables designers to build so- 
phisticated systems including Matlab, 
Simulink, and HDL models. System Gen- 
erator allows designers to automati- 
cally generate FPGA bit streams 
and supports high-bandwidth hard- 
ware in the loop for system verification. □ 



Talk to us 

Post comments via TalkBack at the 
online version of this article at 
www.edn.com. 



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Call 800-927-9474 to talk with a Vicor 
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Enter 32 at www.edn.com/info 




Intersil Digital Potentiometers 



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5-bit 
Up/Down 
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5-bit 
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Memory 



Store and 
Control 
Recall 
Circuitry 



Vss_ 




Key Parameters 



Description 


Conditions 


MIN 


TYP 


MAX 


Unit 


Supply Voltage 


X93154 


2.7 


3 


3.3 


V 




X93155 


4.5 


5 


5.5 


V 




X93156 


2.7 




5.5 


V 


End-to-end Resistence 




35 


50 


65 


kQ 


Rh. Rl Terminal Voltages 









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Rtotal = 50 KQ 






1 


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Noise 


Ref: 1 kHz 




-120 




dBV 


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X93156 






1100 


Q 


Wiper Current 








0.6 


mA 


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3 




% 


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-40°C 




+85°C 


C 



Features 

3-wire up/down interface 

^ 32 wiper tap points. Wiper position 
stored in non-volatile memory and 
recalled on power-up 

Low power CMOS, with Vcc of 
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of 1 jjA max 

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^ Available in 8-lead MSOP and 
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Enter 33 at www.edn.com/info 



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©2005 Intersil Americas Inc. All rights reserved. The following are trademarks or services marks owned by Intersil Corporation 
or one of its subsidiaries, and may be registered in the USA and/or other countries: Intersil (and design) and i (and design). 




designfeature Ry Pava Rmttnn, Zetp.x Semicnnductnrss 



DESIGNING A SWITCHING AMPLIFIER IS ONE THING; 
DESIGNING ONE THAT SOUNDS GREAT IS ANOTHER. 



Sound advice for Class D amplifiers 



CLASS D SWITCHING AMPLIFIERS bring Undeni- 
able benefits to audio applications in circuit ef- 
ficiency, size, and cost improvements. But 
meeting the needs of today s consumer electronics — 
such as audio-video receivers that demand more 
than lOOW of output power with less than 0.05% 
distortion and more than 100-dB dynamic range — 
can be challenging using Class D amplification. 
These amplifiers also have to "sound good," a re- 
quirement that's far more subjective than simply 
measuring and meeting target specifications for dis- 
tortion noise and dynamic range. Analysis of a well- 
designed Class D amplifier yields a number of prac- 
tical design guidelines that can help you to meet all 
of these goals. 

The key to a Class D amplifier's efficiency im- 
provements over Class AB amplifiers is the use of a 
switching output stage rather than a conventional 
linear one. In a traditional analog-audio environ- 
ment, a typical system requires a modulator to con- 
vert incoming signals to a PWM (pulse-width-mod- 
ulation) bit stream and an output-driver stage and 
filter to convert the PWM back to analog power lev- 
els that suit the load. Contemporary digital- audio 
environments, such as CD and DVD, directly pro- 
vide serial data, which can be processed in the digi- 
tal domain before interfacing with the output-driv- 
er stage (Figure 1). This requirement leads to a new 
class of amplifier ICs — digital modulators — which 
feature controls, such as volume and equalization, 
and key processing circuits, such as noise shaping 



and digital filtering, to enable signal reconstruction. 

Modulator bit- resolution, noise-shaper order, and 
the relationship between PWM- and master- clock 
frequencies all considerably influence audio quality. 
Another key consideration is the architecture of the 
on-chip digital filters, which help to maintain the de- 
tail of the recovered audio signal. The output driv- 
er also requires careful design to preserve pulse 
shape, minimize distortion, and ensure the best au- 
dio performance. Protection circuits are essential for 
safe operation, especially at high output-power lev- 
els, but they, too, must not compromise sound qual- 
ity. The effects of power-supply and reference-clock 
quality on overall system performance are also im- 
portant factors to consider. 

MODULATOR 

Digital filters are fundamental to the modulator 
architecture. Coefficients that relate to the tap length 
of the filter repeatedly multiply data samples. The ef- 
fect of this process can degrade audio performance. 
Consider current audio standards, such as DVD -A, 
which can feature a maximum bit resolution of 24 
bits; conventional digital amplifiers have internal 
datapaths of only 24 bits. In the multiplication 
process, this situation leads to the truncation of low- 
er levels within the input signal to keep the larger sig- 
nals within the available bit size. The result is a loss 
of low-level signal accuracy, degrading the listener's 
ability to hear background detail and hampering 
depth perception. A modulator with higher bit res- 



Figure 1 




SYSTEM 
CONTROL 



SYSTEM 
CLOCK 



















VOLUME 




DIGITAL 




NOISE 




PWM 


□ 


EQUALIZER 




FILTER 




SHARER 






□ 
















□ 
















□ 



CONTROL 



PWM 
OUTPUT 



PWM 
OUTPUT 



COEFFICIENT 
ROM 



CLEAN-CLOCK 
GENERATOR 



SMPS AND 
SUBSIDIARIES 



" ^ ^ 

lES N ^ 





3 






3 






















GATE 




H-BRIDGE 




DRIVERS 




DRIVE STAGE 





SYSTEM 
SYPPLY 



PROTECTION 
CIRCUITS 



I 
I 



OUTPUT 
FILTERS 



>0] 



A typical digital-input Class D amplifier converts audio signals to a high-power PWM filtered output before delivery to the load. 



www.edn.com 



April 28, 2005 | edn 65 



designfeature class D am p li fi ers 



5.5V O- 



P-DRIVE 
LOGIC 
LEVEL 

o — 



N-DRIVE 
LOGIC 
LEVEL 
O — 



Figure 2 



ipi 

0P3 
IP2 
GND 



IC3 

NC7NZ17K8X 



VCC 
OPl 
IPS 
0P2 



GP 


DP 


DP 




SP 




DP 


ZXMC3AM832 


GN 




DN 




SN 


DN 


DN 



5.5V O 



IPl 
0P3 
IP2 
GND 



NC7NZ17K8X 



VCC 
OPl 
IPS 
0P2 



GP 


GP 


DP 




SP 




DP 


ZXMC3AM832 


GN 




DN 




SN 


GP 


DN 



" 1 |xF 

P-CHANNEL 
GATE DRIVE 
O 



- ^28 
"1 |XF 

N-CHANNEL 
GATE DRIVE 

O 



Tiny logic devices and complementary FETs provide high-speed drive for bridge-FET gates. 



olution produces less truncation, so au- 
dio quality improves accordingly. In 
practice, a 32-bit modulator offers a per- 
ceptible advantage, but it's debatable 
whether finer resolution further im- 
proves sound quality. 

FILTERING, TAP LENGTHS, AND TRANSIENTS 

The FIR (finite-impulse-response) in- 
terpolation filter is a key element within 
any digital amplifier. Typically, these fil- 
ters employ oversampling techniques 
to shift the aliasing images of the input _ 
signal beyond the audio spectrum. Such 
images exist at the harmonics of the 
data's sampling frequency. The imple- 
mentation of the filter can introduce var- 
ious compromises that you must consid- 
er when selecting a modulator to 
minimize their impact on audio per- 
formance. 

General practice removes images at as 
high as eight times the sampling fre- 
quency — as high as 352.8 kHz for 44.1- 
kHz recordings, for example. Analog fil- 
ters can remove images beyond this limit. 
Some modulators oversample as many as 
48 times, rather than the conventional 
eight. This higher order filtering ensures 
that very-high-frequency images neither 
generate intermodulation distortion nor 
degrade the jitter performance of noise 
shapers. 

Higher sampling rates can improve 
sound quality, as comparisons between 
DVD-A's 96-kHz recordings and CD's 
44.1 -kHz offerings demonstrate. How- 
ever, compromises between silicon area 
and speed can limit the capabilities of a 
digital modulator's on-chip filters. An 
ideal filter would have a brick- wall cutoff 
characteristic that would require an in- 
finite tap length, which is impractical. 
Generally, modulators with long taps are 
preferable; 256 taps represent one of to- 
day's longer implementations. 

Even so, many systems with high over- 
sampling levels and long taps include fil- 
ter-performance compromises that cre- 
ate signal-reproduction inaccuracies. 
One explanation for this sound- quality 
degradation is the loss of transient tim- 
ing information within the audio signal. 
Zetex, for instance, claims that its pro- 
prietary ZTA- filter algorithm preserves 
such timing information, which is criti- 
cal to the sonic performance of its am- 
plifiers. Successfully combining high 
oversampling levels with long filter tap 
and preserving transient information can 



achieve smoother, more focused sound 
quality, with a deep and precise sound 
stage and tight bass definition. 

NOISE SHAPER, PWMs, AND RESOLUTION 

A Class D amplifier that employs dig- 
ital processing has an apparent disad- 
vantage compared with its analog equiv- 
alent. Although digital PWM produces a 
quantized output signal, analog- PWM 
architectures offer theoretically infinite 
pulse-width resolution. To compensate, 
digital amplifiers employ noise shaping 
to reduce errors that the finite resolution 
causes. Noise shaping is conceptually an 
averaging process, but the process in re- 
ality is recursive. Because the PWM fre- 
quency is much higher than the highest 
frequency audio content, it's easy to cor- 
rect errors in any given pulse width with 
a subsequent pulse. 

Many digital modulators employ a 
PWM noise-shaping system that switch- 
es at 384 kHz with a 98-MHz master 
clock for a 48 -kHz sample rate. Other 
topologies can improve audio perform- 
ance, such as lowering noise at higher fre- 
quencies. For example, the Zetex ZXCW- 
8100 uses a 1-MHz PWM switching 
frequency; a 3 3 -MHz master clock; and 
a fourth- order noise shaper, which yields 
a resolution of 33-to-l, or about 5 bits. 
The 384-kHz system's resolution is 



around 255-to-l, or about 8 bits. The 
384-kHz system appears to have a reso- 
lution advantage of 255/33, or around 18 
dB. But if you consider the correction its 
noise shaper gives, the 1-MHz architec- 
ture holds the advantage. Because noise 
shapers correct at nominally 6 dB per or- 
der per octave, a fourth-order noise 
shaper corrects at around 24 dB/octave. 
If the two noise-shaper architectures 
were the same, the 1 -MHz system's ad- 
vantage would be 1M/0.384M, or 2.6— 
equivalent to 1.38 octaves. 

In practice, the I -MHz device runs its 
noise shaper at twice the PWM frequen- 
cy by converting on both edges of the 
clock, so its advantage is 2.38 octaves, or 
57 dB; overall, the 1-MHz noise shaper's 
advantage becomes 57—18 dB, or 39 dB. 

Because 384-kHz systems use higher 
order noise shapers, such as seventh-or- 
der, you might expect each additional or- 
der to provide another 6-dB improve- 
ment. This situation rarely occurs, 
however. Even if you achieve an 18-dB 
improvement from the 384-kHz system's 
three additional orders of noise shaper, 
the 1-MHz architecture still wins. 

After the modulator, the PWM output 
requires amplification to drive a speak- 
er, almost invariably using power MOS- 
FETs in a bridge configuration. Gate- 
driver circuits must provide level- shifting 



66 EDN I April 28, 2005 



www.edn.com 



Go Configure 



Vdut 




Vs. = 2.7V to 36V f 'l^^illA". 



Non-lhvertin^ Gia\n=? 






Gam df lo Bn49e Amplif ie^ 



RSENSE 



• 28V Supply 




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S\f\^t SuppV AC Caup\e4 Arnpiif ier 



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Hundreds of Gain Configurations without External Resistors 

The LT®1991 and LT1995 are extremely versatile op amps. Complete with internal precision resistors, these single chip solu- 
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G = 1 to 8 


Inverting 


G = -0.08 to -13 


G = -1 to -7 


Gain Accuracy (Max.) 


0.04% 


0.20% 


Gain Drift (Max.) 


3ppm/°C 


25ppm/°C 


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50|iV 


2.5mV 


Gain Bandwidth 


560kHz 


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wvm. 

TECHNOLOGY 



Enter 34 at www.edn.com/info 



designfeature class D am p li fi ers 



Dy ■ 

ZHCS1006' 




SUD10P06- 
280L 

Q5 



SUD10P06 
280L 



SUD10P06- 
280L 
Qi 



SUD10P06- 
280L 



Figure 3 



SHORT-CIRCUIT 
-O PROTECTION 
(H1/H2) 




•^18 

220 |xF : 
50V 



-O50V 



Cl4 

220 jjlF 
50V : 



. '-'13 

■470 nF 



~^470 nF 1" 



^25 1 '-'67 

470 nF -r470 nF 



Li 
10 |xH 



: C3 
470 nF 
POLY 



: 

2.2 nF 



Complementary FETs in a BTL configuration show one-half of the BTL output bridge. 




This bridge-sense circuit protects an amplifier that can deliver 150W into SH. 



and current drive but without distorting 
pulse shape (Figure 2). These circuits use 
tiny NC7NZ17 logic devices with com- 
plementary ZXMC3AM832 FETs to — 

provide a high-current, high-speed 

drive to a bridge in a 1-MHz PWM sys- 
tem. Speed is critical to maintaining the 
pulse integrity that preserves dynamic 
range and minimizes distortion. A 33- 
MHz master clock and 1-MHz PWM 
clock require a 30-nsec pulse resolution; 
typically, the driver must switch in 8 nsec 
and support about 4A peak current. Be- 
cause a significant trade-off exists be- 
tween distortion and dissipation in the 
bridge, it's also essential to control the 
shoot-through current that flows in the 
fractional time that both top and bottom 
bridge FETs conduct. Here, resistors in 
the gate-drive buffers limit shoot- 
through by controlling the on-times of 
the N- and P-channel FETs. P-channel 
control focuses more on minimizing 
ringing, but slowing the N channel's on- 
time balances its switching point to 
match the slower P channel's response. 

OUTPUT-STAGE BRIDGE DESIGN 

Because Class D amplifiers typically use 
an open-loop topology, there's no bene- 
fit from feedback. Audio performance can 
then be susceptible to matching errors in 
the bridge. A single-ended output is sim- 
ple and offers the possibility of bridging 
outputs to deliver more power but lacks 
inherent cancellation. A full H-bridge op- 
timizes cancellation to provide the best 
performance and delivers maximum 
power from any given supply voltage. 



In designing a bridge, you can choose 
complementary or all-N-channel de- 
vices. Complementary bridges are sim- 
pler to drive, because all-N-channel ver- 
sions require bootstrap circuits to 
enhance the high-side FETs. Power lev- 
els below about 200W into 811 favor 
complementary bridges, but finding ap- 
propriate P-channel devices becomes in- 
creasingly difficult above this level. Fig- 
ure 3 shows one -half of the bridge using 
complementary FETs in a full BTL 



(bridge-tied-load) configuration. 

The output bridge uses 60V-rated 
Vishay-Siliconix SUD10P06-280L and 
SUD15N06-90L devices that can switch 
15A in about 20 nsec. Parallel operation 
of FETs is a good choice for several rea- 
sons. First, current sharing minimizes 
dissipation and allows good thermal de- 
sign with minimum heat- sinking. Paral- 
lel operation also enables the FETs to op- 
erate on the most linear part of their 
on-resistance versus current curve. This 



68 EDN I April 28, 2005 



www.edn.com 



48V to Any Volts 




Any Topology, Any Power Level, Any Layout 

Linear Technology's growing portfolio of primary and secondary side controllers support simple, flexible and cost-effective 
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'Info & Online Store 



Function 


Part Number 


Description 


Package 


Flyback Controllers 


LTC®3803 


Constant Frequency 200kHz with adjustable slope-compensation 


ThinSOT™ 


LT®1725 


No optoisolator required; Senses Vqut ffom primary side winding 


SO-16, SSOP-16 


LT1737 


No optoisolator required; Low 4.5\/min supply voltage 


SO-16, SSOP-16 


Single Switch 
Forward Controllers 


LT1952 


Synchronous; Programmable volt-second clamp 


SSOP-16 


LT1950 


3V to 25V input voltage range; Onboard auxiliary boost converter 


SSOP-16 


LTC3900 


Secondary side synchronous rectifier driver for forward controllers 


SO-8 


2-Switch Forward 
Controllers 


LTC3705 


PolyPhase™; No need for separate bias regulator 


SSOP-16 


LT3781 


12\l operation; Synchronizable for multiple controller systems 


SSOP-20 


Push-Pull Half- & 
Full-Bridge PWM 
Controllers 


LTC3723 


Synchronous; Adjustable dead-time and synchronous timing 


SSOP-16 


LTC3721-1 


Adjustable dead-time; 4mm x 4mm QFN package 


SSOP-16, QFN 


LTC3901 


Secondary side synchronous driver for push-pull and full-bridge 


SSOP-16 


Full-Bridge 
ZVS Controller 


LTC3722 


Current and voltage mode with adaptive or manual delay control for 
zero voltage switching 


SSOP-24 


Secondary Side 
2-Switch Forward 
Controllers 


LTC3706 


Fast, PolyPhase current mode 


SSOP-24 


LTC1698 


Secondary side synchronous rectifier controller 


SO-16 


Secondary Side 
Post Controllers 


LT3710 


Regulated auxiliary output in isolated DC/DC converters; 
Synchronous drivers; Programmable current limit 


TSSOP-16 


LT3804 


Regulates two secondary outputs; Integrated optocoupler driver 


TSSOP-28 


MOSFET Drivers 


LTC4440 


80V operation; 100V transient tolerant; Fast gate drive 


ThinSOT, MSOP-8 


LTC4441 


6A peak output current; 5V to 8V adjustable gate drive 


MSOP-10; SO-8 


LTC1693 


Single & dual N-, P-channel MOSFET drivers 


SO-8, MSOP-8 


Optocoupler Driver 


LT4430 


600mV, 1% accurate reference; prevents overshoot 


ThinSOT 


Overvoltage 
Protection Controller 


LTC1696 


±2% overvoltage threshold accuracy; Gate drive for SCR crowbar or 
N-channel disconnect MOSFET; Monitors two output voltages 


ThinSOT 



www.linear.com 

Literature: 1-800-4-LINEAR 
Support: 408-432-1900 




U, LTC and LT are registered trademarks and ThinSOT, 
PolyPhase and SwitcherCAD are trademarks of Linear 
Technology Corporation. All other trademarks are the property 
of their respective owners. 



.^^^ TECHNOLOGY 

Enter 35 at www.edn.com/info 



designfeature class n amplifiers 



0.9 
0.85 
0.8 
0.75 
0.7 
0.65 



(%) 



0.55 
, 0.5 
0.45 
0.4 
0.35 
0.3 
0.25 



Figure 5 



detail is important, be- 
cause any on-resistance 
modulation can cause 
odd-order harmonic dis- 
tortion. In this example, 
parallel devices reduce 
output impedance, re- 
sulting in an increase in 
damping factor, improv- 
ing the tightness of the 
bass response. Here, the 
output impedance is 
0.2H — equivalent to a 
damping factor of 40 
with an SH load. 

A lowpass filter re- 
moves high-frequency 
content before the 
speaker. Typically, these 
filters require a frequency response that's 
flat up to 20 kHz, but some audio stan- 
dards demand a controlled response up 
to 96 kHz. For good audio performance, 
the inductors provide excellent linearity 
characteristics and a tolerance of only a 
few percentage points. They also require 
minimal series resistance and core losses 
and must not saturate under heavy load 
conditions. Distributed-air-gap, iron- 
powder cores are often the best choices. 

The system's PWM frequency affects 
output component values, and the 1- 
MHz architecture minimizes inductor 
size. This high-frequency switching also 
enables a higher filter- cutoff frequency, 
which helps meet specifications such as 
SACD (super- audio compact disc) with 
a high degree of tolerance to variable-im- 
pedance loads. Filter capacitors are sim- 
ilarly critical, because poor-quality com- 
ponents can increase THD (total har- 
monic distortion) and degrade reliabili- 
ty. Use RF-quality, low-ESR (equivalent- 
series-resistance) types. 

Adequately protecting an amplifier is 
not trivial. Any scheme must operate cor- 
rectly with widely varying dynamic con- 
ditions, both in signal level and output- 
load impedance, but must trip if a fault 
occurs, regardless of audio conditions. 
Ensuring protection with shorts at the 
smallest signal levels can be more im- 
portant than the more obvious high- 
power conditions. 

First, consider whether you're protect- 
ing the amplifier, the load, or both. Then, 
consider the fault conditions that you 
need to guard against. Conventional pro- 
tection ensures that users can abuse the 
external connections of an amplifier 



- 
































































































- 


















































- 




































































































z 




































































































= 




































































































\ 


























































































































































































































































































































































1 



































































































OUTPUT POWER (W) 

A 10-mn sense resistor in the bridge power rail causes mini- 
mal additional distortion. 



without damaging it or the speaker. 
However you apply it, the protection cir- 
cuit must trip whenever a short across 
the amplifier outputs or a short from any 
amplifier output to ground occurs. 

SHORT-CIRCUIT PROTECTION 

Current-sense circuits normally pro- 
vide short-circuit protection, either with- 
in the system's power supply or directly 
at the bridge; a combination of both can 
offer excellent protection. Current lim- 
its in the power supply are easy to apply, 
because they're often parts of the stan- 
dard SMPS (switch-mode-power-sup- 
ply) circuit; applying protection in the 
bridge is somewhat more difficult. Fig- 
ure 4 shows a bridge-sense circuit that 
protects an amplifier that can deliver. 
150W into 8H. Figure 3 shows the sense 
components. Sense resistors between the 
positive bridge supply and each half of 
the output bridge (lO-mll in Figure 
3) develop voltages proportional to the 
current flowing in the bridge. These volt- 
ages supply the differential inputs of the 
protection circuit — in this case, a 
ZDT751 dual-PNP transistor (Q^). When 
an overcurrent of sufficient magnitude 
occurs, the differential voltage drives 
"mute" low. 

Circuit setup is important. For exam- 
ple, the balance between C^^ and R^^ de- 
sensitizes the inputs to fast transients. 
Output-filter-inductor choice is critical, 
too, because circuit operation relies on 
nonsaturating inductors. Select compo- 
nents with a saturation current well 
above the expected amplifier's maximum 
output current under normal conditions. 
In this example, inductors with satura- 



tion current well over 
20A suit a trip point of 
12 A. Also consider 
speaker impedance 
variations. In this case, 
allowing for a 411 load 
requires a balance be- 
tween trip-point selec- 
tion and the current 
that's necessary for full 
power into 40. This 
circuit setup cuts in 
somewhat below 3W, a 
level low enough to al- 
low safe operation of 
the amplifier driving 
into shorts with the 
lowest of signal levels. 
Power supplies have 
a profound influence on audio perform- 
ance. As a result, a sense resistor in the 
bridge supply rail can influence audio 
quality. In practice, measurements con- 
firm that the lO-mfl sense resistor caus- 
es minimal degradation (Figure 5). 

Open-loop Class D ampHfiers demand 
extra consideration for the influence of 
support circuits. The system's power 
supply, particularly the supply to the 
bridge, is a major contributor (see side- 
bar "Power- supply quality and capacity 
for details" with the version of this arti- 
cle atwww.edn.com). Poor system clocks 
may also degrade sound quality (see 
sidebar "Keep system clocks clean," also 
with the Web version of this article). 

The study of many implementations of 
digital- input Class D circuits shows how 
easy it is to create an amplifier that does- 
n't do itself justice in measurement or 
sound quality. Although time and space 
do not permit this article to consider 
every angle of design, practical imple- 
mentation and attention to the key areas 
can significantly enhance performance 
and potentially produce the best sound- 
ing digital amplifiers. □ 



Author's biography 
Dave Brotton is a technical marketing 
manager for audio products with Zetexplc, 
where he has worked for 13 years, origi- 
nally as product-line manager for power- 
management products and for the last four 
years developing the Zetex Class D switch- 
ing-audio program. 

Talk to us 

Post comments via TalkBack at the online 
version of this article at www.edn.com. 



70 EDN I April 28, 2005 



v.edn.c 



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DESIGN 
NOTES 



Simple Battery Circuit Extends Power over Etinernet (PoE) 

Peck Current - Design Note 361 
Mark Gurries 



Introduction 

Power over Ethernet (PoE) is a new development that 
allowsforthedelivery of powerto Ethernet-based devices 
via standard Ethernet CATS cable, precluding the need for 
wall adapters or other external power sources. The PoE 
specification defines a hardware detection protocol where 
Power Sourcing Equipment (PSE) Is able to identify PoE 
Powered Devices (PDs), thus allowing full backwards 
compatibility with non-PoE-aware (legacy) Ethernet 



L1 
3.3^iH 



devices. The PoE specification also sets an upper limit on 
the power that can be drawn by a PD. The problem is: what 
happens when a PD must draw more power than allowed 
by the PoE standard? Examples may be the spin up of a 
disk drive or a period of sustained transmission of data 
fromanRFtransmitter. If the ai/eraflre power load of these 



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Figure 1. Simple Battery Charger/PowerPath™ Controiier (LTC4055) Augments PoE Regulator's 
(LTC4267) Peak Output Power to Overcome PoE Power Constraints 



04/05/361 



applications is less than the available PoE power, one 
solution is to store power in the PD when power con- 
sumption is low and then tap the reserve to augment PoE 
power when needed. For many applications, a recharge- 
able battery fits the bill. 

Of course, one can't just throw a battery and a battery 
charger Into the mix. The power path must be able to 
change seamlessly, on the fly, from PoE-powers-device- 
and-charges-battery, to PoE-and-battery-power-device, 
to battery-powers-device. Figure 1 shows a complete and 
compact solution. 

The PoE Circuit 

By default, power over the Ethernet is available. The 
standard calls for a protocol to be implemented that 
allows the Ethernet hub to identify the device needing 
power. The LTC®4267 simplifies the design of PDs by 
providing wholesale implementation of the protocol and 
power management functions. 

PoE power comes in the form of -48V at 350mA. If the 
PoE current is allowed to exceed 400mA, the standard 
calls for the PSE to break the circuit. This is a problem for 
devices that occasionally need a little more juice than PoE 
will offer. Another problem is that -48V does not easily 
convert to commonly used positive voltage supply rails. 
Designers are forced to provide DC isolation along with 
the inverted down conversion to a more usable voltage. To 
meet these requirements, the LTC4267 used in Figure 1's 
circuit implements an input current limited DC input 
isolatedflybackconverter,providingauser-settable regu- 
lated low voltage. 

The LTC4267 circuit in Figure 1 supplies 5V at 1 .8A. 5V is 
a popular supply voltage to run logic, interface with other 
devices such as USB, and of primary concern in this 
application, to charge a single Li-Ion cell to its target 
termination voltage of 4.2V. 

PowerPath and Charger Circuit 

In Figure 1 , the LTC4055 provides triple PowerPath con- 
trol and Li-Ion battery charging. One path is created by 
connecting an external Schottky diode to the LTC4055's 
OUT pin and the built-in wall adapter detection circuits. In 
this case, the "wall adapter" power comes from the 
LTC4267 5V power supply called 5V PoE. The second path 
is for USB power, not used in this application. The third 



path is the battery discharge path. When the 5V PoE power 
goes away or drops out of regulation, the LTC4055 
automatically switches the battery power over to the OUT 
pin using its internal ideal diode circuit. There is no delay 
in the switchover, so power is never lost. 

When 5V PoE power is restored, the battery is discon- 
nected from the load and charging is permitted. The 
LTC4055 charge current is adjustable and in Figure 1 , the 
circuit is limited to 900mA which is drawn from the OUT 
pin. That leaves 900mA to run the system while charging. 
Powered devices connected to the OUT pin mu st be 
compatible with the Li-Ion voltage range. The ACPR pin of 
the LTC4055 can be used to indicate which power source 
is providing power, allowing the PD to configure itself 
accordingly. 

High Transient Load or Continuous Current 
Load Operation 

When the power limit of the 5V PoE supply is reached, the 
voltage drops and the battery charger shuts down to 
relieve the PSE of the charge current load. If the voltage 
continues to collapse, the battery automatically is placed 
into parallel operation with the 5V PoE power supply, thus 
increa sing the available peak load current. The LTC4055 
ACPR signal is active high during the overload. Battery 
charging automatically resumes once the overload goes 
away and the 5V PoE voltage has risen enough to show 
recovery. 

Optimization Options 

If sustained currents approaching 1 .8Aare expected from 
the 5V PoE and there are thermal management issues 
related to the diode's heat dissipation, the diode D9 can be 
replaced with the LTC441 1 ideal diode for more efficient 
operation. Recommended DC/DC converters to generate 
logic supplies in this application include the LTC3443 
buck-boost and/or the LTC3407-2 dual buck regulators. 

Conclusion 

The highly integrated LTC4267 and LTC4055 simplify the 
design of compact, simple and complete battery-based 
power systems that run from Ethernet power. More 
importantly, seamless PowerPath control enables cir- 
cuits that can use a battery to augment Ethernet power 
when an application momentarily demands more than the 
PoE standard allows. 



Data Sheet Download 



http://www.linear.com 



For applications help, 
call (408) 432-1900, Ext 2364 



Linear Technology Corporation 

1630 McCarthy Blvd., Milpitas, CA 95035-7417 
(408) 432-1900 • FAX: (408) 434-0507 •www.linear.com 



dn361f LT/TP 0405 SOSK • PRINTED IN THE USA 

J^^F TECHNOLOGY 

© LINEAR TECHNOLOGY CORPORATION 2005 



Illllllllllllllllllll 








ideas 




Thfi hfist nf 




] Check it out at: 
www.edn.com/bestof 
designideas 



Edited by Brad Thompson 



Camera serializer/deserializer chip set reduces 
wire count for l^eypad 

Wallace Ly, National Semiconductor Corp 



I ANY SYSTEMS that require a user to 
manually enter data feature a key- 
I board similar to that in Figure 1. 
Although early keypads comprised arrays 
of individually wired switches, a typical 
modern keypad comprises a matrix of x 
and y lines. Pressing a key creates a mo- 
mentary connection between an x line 



m m m 
m m m 
m m m 
m m H 



Figure 1 



A typical keypad pro- 
vides a limited number 
of numeric keys and two 
symbols-the asterisk (*) 
and the octothorpe (#). 



DATA[02_ 
DATA[1^ 
DATA[22_ 
DATA[3] 



Figure 2 



In a matrix keypad, pressing a key 
creates a connection between a 
row wire and a column wire. 



and a y line. For example, an individual- 
ly wired keypad comprising discrete 
switches arranged in four rows and three 
columns (also known as a 4X3 layout) 
would require 24 wires. The more eco- 
nomical matrix approach in Figure 2 re- 
quires only seven signal wires, but even 
that number can sometimes prove diffi- 
cult to route to a micro- 
controller. To further re- 
duce the number of 
interconnecting wires 
from seven to three, plus 
a ground return, you can 
adapt a configurable seri- 
alizer/deserializer such as 
National Semiconduc- 
tor's LM2501. 

The device typically 
finds use in adapting 
video buses, such as wide, 
low- voltage CMOS-video 
interfaces for portable 



■: 1 


-: 2 


-; 3 


: "4" 


-■["5 " 


-.;"5 


■"7 " 


-■["s" 


-.;"9 


''T 


-■■"0" 


-■i" #" 


Do 


"T" 

Di 


'2 



Camera serializer/deserializer chip set 
reduces wire count for keypad. 75 

Rearranged reference helps ADC 
measure its own supply voltage 76 

Difference amplifier measures 

high voltages 78 

Linear potentiometer provides 

nonlinear light-intensity control. 80 

Publish your Design Idea in EDN. Make 
$150. Visit www.edn.com. 



electronics to Mobile Pixel Link service. 
The LM250rs typical application circuit 
features low- voltage and low- current op- 
eration and produces low levels of EMI 
(Figure 3). The circuit requires only two 
support devices — a counter (a CMOS 
CD4017 decade counter) and a 10-MHz 
clock-oscillator module (Figure 4). In 
operation, the host microcontroller 
drives the deserializer's WCLK input pin 
with a low-voltage-CMOS clock pulse. 



MICROCONTROLLER 



CAMERA 
INTERFACE 



LM2501 MPL DESERIALIZER 



H 



YUV[7:0] 



PCLK 



MODEO 
MODEl* 



MODE[1:0]=00'B 



Figure 3 



WCLK, 



wc 



LM2501 MPLSERIALIZER 



MC 



MD 



MG 



WCLKn 



PD 



H 



YUV[7:0] 



PCLK 



MODEO 



MODEl 
PD 



^^CAM^^ 



MCLK 



I^C 



MODE[1:0]=00'B 



STS 



SCK 



CONTROL 



In a typical application, a pair of LIVI2501S converts multiconductor video data to serial data and restores the data to multiconductor format. 

www.edn.com April 28, 2005 I edn 75 



Illlllllllllllllllllll 

Ideas 




RESET 



You can apply the LIVI2501 to reduce the number of signal lines a keypad-to-microprocessor interface requires. 



which translates to an MPL-level signal 
and then is applied to the serializes The 
serializer reconverts the WCLK pulse, 
which drives the counter's clock input. 

Unlike divide-by- 10 encoded-output 
decade counters, the CD4017's inter- 
nal organization comprises a Johnson 
counter that activates only one of its 10 
outputs at a time. Thus, the counter's 
outputs Dq, D^, and sequentially apply 
a logic one to the keypad's column lines, 
and output resets the counter to zero. 
When a user presses a key and connects 
a column line to one of four row lines, the 
serializer samples the keypad's row lines. 



converts the selected active line to a seri- 
al signal, and transmits the signal to the 
deserializer. 

For example, suppose that the user 
presses the 5 key. The first clock pulse 
that the CD4017 receives drives column 
line Dp to a logic one, but, because the 
user does not press keys 1, 4, 7 and row 
lines A, B, C, and D remain at logic zero. 
The second clock pulse drives column 
line to a logic one, and pressing key 5 
connects row line B to logic one, where- 
as lines A, C, and D remain at logic zero. 
The pseudocode fragment in Listing 1, 
available in the online version of this De- 



sign Idea at www.edn.com, instructs the 
microcontroller to decode which key a 
user is currently pressing. In practice, ad- 
ditional code enables the microcon- 
troller to reject multiple simultaneous 
key closures. 

You can expand the architecture to ac- 
commodate a keypad matrix as large as 
8X10 keys by using more of the counter's 
outputs and wiring the Nth output to the 
counter's reset input. The keypad's rows 
connect to the serializer's data inputs, 
and both of the LM250Is' unused inputs 
connect to pullup resistors, ground, or 



Rearranged reference helps ADC 
measure its own supply vo tage 

Bjorn Starmark and Orville 
BuenaventurUy Maxim 
Integrated Products Inc, 
Sunnyvale, CA, and Soren 
Kdcky Audiovdxlar, Sweden 



IF YOU USE an ADC to monitor a sys- 
tem's power- supply voltage, you may 
encounter situations in which the sup- 
ply voltage exceeds the ADC's reference 
voltage (Figure 1). However, the ADC's 
input voltage cannot exceed its reference 
voltage. You can use an external resistive 
divider to bring the supply voltage with- 
in the ADC's input range, but even 0.1%- 



IN 




MAX6025 5 






OUT 


2.5V^ 






GND 




3 







1 

I 



0.1 |jlF 



TRANSDUCER ( 




1 

I 



0.1 |jlF 



2/ REF 

'aini 



MAX1087 DOUT 



AIN2 CNVST 
3\ GND 



T 



0.1 ijlF =!= 



MICROCONTROLLER 



T 



I 



Figure 1 



A precision resistive divider brings the power-supply voltage within this 
ADCs input range but introduces measurement errors. 



76 EDN I April 28, 2005 



www.edn.com 



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Illllllllllllllllllll 

Ideas 



tolerance resistors may introduce an ob- 
jectionable error. You can solve the prob- 
lem by eliminating the divider, connect- 
ing the ADC's reference input to its 
power supply, and connecting one of the 
ADC's inputs to a precision voltage ref- 
erence — in this case, a 2.5V MAX6025A 
(Figure 2). 

In this configuration, the ADC meas- 
ures its inputs with respect to the sup- 
ply voltage. Using the digitized reference 
voltage as a standard, the system's soft- 
ware computes the ratio of the reference 
voltage with respect to the power- supply 
voltage and corrects the remaining in- 
puts' measurements. The ADC must ac- 
commodate an external reference volt- 
age that equals its power- supply voltage, 
and any noise on the supply rail disturbs 
measurements of all channels. Thus, to 
quiet the supply rail in electrically noisy 
environments, you may need to add a 
lowpass filter to provide extra decou- 
pling at the ADC.D 



2.7 TO 3.6V 




0.1 |xF d= 



TRANSDUCER 



Figure 2 



To eliminate the resistive divider, you connect the ADCs reference voltage 
to its power supply and measure the precision voltage reference's output. 



Difference amplifier measures higli voltages 

Moshe Gerstanhaber and Chau Tran, Analog Devices, Wilmington, MA 




(a) 



Figure 1 



(b) 

To measure high voltages, you can use discrete resistors to assemble an 
input voltage divider and buffer (a) or an attenuating inverter (b), but per- 



formance suffers due to thermal mismatch. 



FIGURE 1 shows two large-signal- 
measurement methods. The first 
uses a two-resistor voltage divider 
and an output buffer, and the second 
comprises an attenuating inverter and a 
high-value input resistor. Both of these 
approaches introduce measurement-lin- 
earity errors because only a single resis- 
tor dissipates power, which leads to self- 
heating and its associated change in 
resistance. In addition, the amplifier and 
the remaining resistors introduce a com- 
bination of offset current, offset voltage, 
CMRR ( common -mode - re j ection - ratio ) 
effects, gain error, and drift, which may 
significantly reduce the system's overall 
performance. 

Based on Analog Devices' AD629, the 
circuit in Figure 2 can measure inputs in 
excess of 400V p-p with less than 5-ppm 
linearity error. The circuit attenuates its 
input signal by a factor of 20 and deliv- 
ers a buffered output. Packaging the am- 



plifier and attenuator resistors together 
ensures that both resistors in the atten- 
uator string operate at the same tem- 
perature. The amplifier's input stage 
employs superbeta transistors to mini- 
mize offset current and errors due to 
bias current errors. Applying 100% feed- 



back at low frequencies introduces no 
noise gain, and the offset voltage and its 
drift add almost no error. 

The AD629 is unstable with 100% 
feedback, and the 30-pF capacitor adds 
a pole and a zero to the feedback gain to 
stabilize the circuit and maximize the 



78 EDN I April 28, 2005 



www.edn.com 



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© 2005 Maxim Integrated Products, Inc. All rights reserved. 



Enter 39 at www.edn.com/info 



Illllllllllllllllllll 

Ideas 



system bandwidth. The following equa- (27t(20 kll) X 30 pF) = 265 kHz. shows linearity for a 50V/division input 

tion calculates the pole frequency, Figure 3 shows the amplifier's per- signal and a 5V/ division output. Figure 

fpi fp= 1/(277(380 kn + 20 kll) X30 pF= formance with a 400V p-p input (upper 5, a linearity-error plot, shows nonlin- 

13 kHz. The following equation deter- trace) and its corresponding 20V output earity versus a 400V p-p input signal. □ 

mines the zero frequency, f^: f^^l/ (lower trace). In Figure 4, a cross plot 




Figure 2 



An integrated approach moves external resistors 
into the device's package for improved thermal 



tracking and greater accuracy. 





































Chi 50.6 V g 

' t 1 1 t i • - 1 [ j 1 , • ■ 


\SM 5-00 V 

-i-i-i-i ^ i i i : " 


ivi 10.0ms Chi 

' ' ' • I • • ■ ■ \ . ■ ■ ■ 


f 

i i i i 


-2 V 



Figure 4 | plotting input versus output shows minimal 
departure from an ideal straight line for a 400V p-p input. 













/ 














A 










J..} , 








:i: / 


























100 V 


Gh2 I 




200|as cHt\ 





Figure 3 



The circuit in Figure 2 delivers a 20V p-p output 
for a 400V p-p input. 





































































Chi 50.0 


SiB 2Q.omv ^,1 M 500ms 


Ch3 s 


Q V 



Figure 5 | ^ scatter plot of nonlinearity error for a 400V 
p-p input displays error of less than 10 ppm over the input range. 



Linear potentiometer provides 
nonlinear light-intensity control 

Stephan Goldstein, Analog Devices, Wilmington, MA 



THE HUMAN EYE s highly nonlinear re- 
sponse to light levels poses problems 
for designers of adjustable lighting. 



Simple hardware or software linear-con- 
trol methods compress most of the ap- 
parent intensity variation into a relative- 



ly small portion of the adjustment range. 
A strongly nonlinear control characteris- 
tic is necessary. Such a characteristic 



80 EDN I April 28, 2005 



www.edn.com 



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t10k-up recommended resale B-grade, FOB USA. Price provided is for design guidance and is FOB USA. 



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© 2005 Maxim Integrated Products, Inc. All rights reserved. 



Enter 40 at www.edn.com/info 



Illlllllllllllllllllll 

ideas 



Spreads the intensity adjustment over a 
wider range and offers a more natural 
feel. This Design Idea shows how to use 
an inexpensive linear potentiometer to 
develop a satisfactory hardware tech- 
nique. In an experiment in a darkroom, 
one of the room's corners was too dark 
because a fixed barrier shielded safe light. 
Using spare parts from a junk box, you 
could assemble a simple red LED-based 
auxiliary safe light, but if the light level 
were adjustable, you could balance the 
light levels and minimize the risk of fog- 
ging the printing paper. However, the ex- 
perimenters in this case lacked an audio- 
taper intensity- control potentiometer 
and wanted to avoid paying for one. 

Figure 1 shows a simplified version of 
the technique. Diode-connected transis- 
tor and an AD589 1.235V reference, 
IC^, produce a reference voltage of 
1.235V+Vj3^(Q^) at Node A. Connected 



12V 



between Node A and Q^'s emitter, linear 
potentiometer and resistor cause 
Q2's emitter and collector current to vary 
as 1.235V/(R2 + R3). The relationship is- 
n't exact because the V^^ voltages of 
and Q2 vary slightly as you adjust the po- 
tentiometer, but, in practice, this nonlin- 
ear — if not logarithmic — characteristic 
works well. 

Transistor Q^'s collector current gen- 
erates the control voltage across R^, and, 
whereas always operates close to sat- 
uration, the components limit Q2's col- 
lector-base forward bias to an acceptable 
200 mV. When you set R2 to its minimum 
resistance for maximum light intensity, 
resistor R^ limits LED current, and, when 
you set R^ to its maximum resistance for 
minimum intensity, R^ limits the current 
through IC^. 

The reference voltage produced at Q2's 
collector drives a standard integrating 



servoamplifier comprising an AD8031 
rail-to-rail op amp, IC^; an IRFDOlO low- 
power MOSFET, Q3; R3 ;R^; and C^. The 
servo sets the current through R^ to R4/R5 
times the current through R^. Resistor R^ 
isolates Q^'s gate capacitance to prevent 
load- induced instability in IC^. A 12V-dc 
module supplies power to the circuit and 
allows the use of four LEDs per string, for 
a total voltage drop of approximately 8V 
across each string. To prevent current 
hogging and provide a maximum of ap- 
proximately 20 mA for each series-con- 
nected LED string, resistors R^ through 
R^^ divide Q3's drain current into four. 
Voltage drop across each resistor is IV, 
leaving to support a 3V drain-source 
voltage and an approximately 250-mW 
power dissipation. If you increase the 
number of LEDs or the power-supply 
voltage, you may need to replace Q3 with 
a higher dissipation MOSFET. □ 



12V 



Qi 

2N3906 







<4.3k 


NODE A 




3 

R2 i 
50k< 


AD589 




1 


2N3906^ 



Figure 1 




RED LEDs, 
Vp-2V 



A handful of components provides linear adjustment of a darkroom's safe light. 



82 EDN I April 28, 2005 



www.edn.com 



Intersil High Speed Op Amps 




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Intersil offers a wide portfolio of High Speed 
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^ 8.5mA per channel supply current 



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EL5367 



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1.4GHz bandwidth 

6000V/|JS slew rate 

Less than 9mA 
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1 


500 


4000 


1.5 


1 


100 


±3.6 


5 


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1 


600 


4700 


3.5 


1 


140 


±3.8 


3.5 


IeL5166/7 












160 


±3.8 5 1 


EL5260/1 


2 


200 


2000 


0.75 


1 


70 


±3.4 


5 


EL5262/3 


2 


500 


2500 


1.5 


1 


100 


±3.6 


5 


EL5462 


4 


500 


2500 


1.5 


1 


100 


±3.6 


5 



75£2 



Part No. 


BW 
(MHz) 


SR 
(V/Ms) 


Is 

(mA) 


Av (min) 
(V) 


lOUT 
(mA) 


VOUT 
(V) 


EL5360 


200 


1700 


0.75 


1 


70 


±3.4 


EL5362 


500 


2500 


1.5 


1 


100 


±3.6 


EL5364 


600 


4200 


3.5 


1 


140 


±3.8 


EL5367 


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lililiBI 




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Part No. 


#of 
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BW 
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SR 

(V/JJS) 


Vn 
(nV/V Hz) 


IS 
(mA) 


lOUT 
(mA) 


VoUT 
(V) 


Vos 

(max) 
(V) 


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1 


300 


2200 


10 


2.6 


100 


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EL5102/3 


1 


400 


2200 


6 


5.2 


150 


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5 


ELS 104/5 




700 




14 








EL5202/3 


2 


400 


2200 


6 


5.2 


150 


±3.9 


5 


EL5204/5 


2 


700 


3000 


10 


9.5 


160 


±3.8 


10 


EL5300 


3 


200 


2200 


10 


2.5 


100 


±3.4 


4 


EL5302 


3 


400 


2200 


6 


5.2 


150 


±3.7 


5 


EL5304 


3 


700 


3000 


10 


9.5 


160 


±3.8 


10 



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Intersil - Amplify your performance with advanced signal processing. 

©2005 Intersil Americas Inc. All rights reserved. The following are trademarks or services marks owned by Intersil Corporation 
or one of Its subsidiaries, and may be registered in the USA and/or other countries: Intersil (and design) and i (and design). 




Connectors 



componentsshowcase 




Coplanar connector has 

low insertion loss and crosstalk 

AirMax VS system's coplanar version allows 
for insertion of add-in boards for system 
upgrades. The system uses air as the dielec- 
tric between adjacent conductors, facilitating 
high signal density and exhibiting low inser- 
tion loss and crosstalk. The product allows 
designers to freely mix as many as 63 differ- 
ential-pair lines per inch, as many as 95 sin- 
gle-ended signals per inch, and a power 
supply in one connector. The high-density, 
25-mm card slot also includes a two-piece 
header-receptacle connector system in 3- 
and 2-mm column spacing in a 150-posi- 
tion, five-pair configuration for 25-mm-slot- 
pitch applications and a 120-pitch, four-pair 
connector for 20-mm-slot-pitch applica- 
tions. The coplanar connector cost 10 cents 
per mated line. 

FCI, 1-800-237-2374, www.fciconnect.com 




Adapter has carrier-class 
connectivity for European-sourced 
DS3/video products 

TheUADF20M110 
adapter couples a 
1.6/5.6 DIN plug to a 
full BNC jack and 
delivers true 75H 
performance. The 
adapter enables con- 
nectivity of Euro- 
pean-sourced prod- 
ucts to DS3 telephone- 
company-network and video-broadcast 
applications in the North American 
conventional footprint. $40.80 (100). 
Trompeter, 1-800-982-2629, www. 
trompeter.com 

BMI connector has self-aligning feature 

The Spox BMI (blind-mate-interface) 
connectors have a self- aligning feature 
^■■pm^^^H for a lower instal- 
95 ^H^H lation time and 

m ^^^^^H expanding design 

W| ^Hl options in wire- 

J^^H to-board and 
wire -to -wire applications. The low pro- 
file allows for a mated stack distance of 



Connectors 84 

Microprocessors 84 

Electronic Design Autonnation 86 



1 1 mm. The dual-row, panel-mount de- 
sign on a 2.5-mm centerline provides 
support for BMI applications and sup- 
ports as much as 3 mm of horizontal and 
vertical misalignment between connec- 
tors before engagement. The connectors 
come in wire gauges as large as #22 AWG 
for 3A current at 250V. The six-position 
wire-to-board mated connector costs 70 
cents in high volumes. 
Molex Inc, www.molex.com 



Connector suits critical 
high-density applications 

The 1.25- 
mm-pitch, 
top- and 
side-entry 
wire-to- 
board GH 
Series SMT 
connectors feature positive locking, includ- 
ing audible-click/tactile feedback, when 
mating to headers. The connector is avail- 
able with two to 15 circuits rated 1 A ac/dc 
AWG #26 at 50V ac/dc; it accommodates 
wire sizes AWG #30 to #26. 
JST Corp, 1 -800-947-1 1 10, www.jst.com 




Microprocessors 



SOCs have touchscreens and 
programmable LCD controllers 

The 16/32-bit LH79525 and 32-bit 
LH79524 SOCs (systems on chips) in- 
clude an on-chip, programmable, color 
LCD controller, an onboard 10/ 100BaseT 
Ethernet MAC (media-access con- 
troller), USB functions, serial ports, and 
external DMA. The LCD controller sup- 
ports 65,536 colors in the LH79524 and 
4096 colors in the LH79525, and both 
SOCs feature a direct interface to STN 
(supertwist-neumatic), color STN, TFT 
(thin-film-transistor), and Sharp's Ad- 
vanced-TFT panels. The products' pe- 
ripherals include 16 kbytes of on-chip 



SRAM, PC, PS, counter/timers, an 
SDRAM controller, and a watchdog 
timer, as well as all types of flash memo- 
ry The LH79524 comes in a CABGA- 
208, and the LH79525 comes in an 
LQFP-176. Both components will be 
available in mass -production quantities 
early in the second quarter of this year. 
Sharp Microelectronics of the 
Americas, www.sharpsma.com 

JPEG compression suits 
FPGA-based intelligent cameras 

The high performance CTJPEG-04 
JPEG-compression IP (intellectual-prop- 
erty) core suits FPGA-based intelligent 



cameras. The core can sustain 500 
frames/sec at a resolution of 1 280 X 1024 
pixels. Based on the JPEG ISO/IEC IS 
110917-1 standard image-compression 
algorithm, the core uses a configurable 
user interface to compress images from 
FastVision's cameras and then transmits 
the images to a host through a USB-2- 
standard interface. The core is synchro- 
nous and autonomous, and it features 
localized graceful image degradation. In- 
put to the core comes from a Micron 
Imaging-type sensor at a pixel rate of 10 
pixels of 10 bits on every cycle of a 66- 
MHz clock. The core frequency-trans- 
forms samples using a discrete cosine 



84 EDN I April 28, 2005 



www.edn.com 



EDN 



Product Mart 



This advertising is for new and current products. 

For additional information from manufacturerSy 
please enter number or visit www.edn.com/info 




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Ultrasonic Sensor Source 

' Electrostatic Sensors • Piezoelectric Sensors 
onents, Kits 





r 



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These are the same ultrasonic sensors and components 
formerly made by Polaroid and are now manufactured 
by SensComp. Visit www.senscompxom for complete 
product information. 



Phone: 734-953-4783 
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ENTER 232 



ENTER 233 



To advertise in Product Mart, call Dara Juknavorian at 888.248.7324 



April 28, 2005 | edn 85 



Microprocessors 



transform with an 18 -bit internal accura- 
cy and feeds them through one of two 
Huffman and quantization tables, which 
are configurable during compression. 
The core outputs JPEG-JFIF- or motion- 
JPEG-compressed data that users can 
convert back to standard image formats. 
The product requires no external memo- 
ry, suits Xilinx Virtex XC2V2000 FPGAs, 
and is available in configurations accept- 
ing a variable number of pixels per cycle 
and pixel resolution. 
Cadre Codesign Inc, www. cadre 
codesign.com 



Third-party vendor provides 
real-time OS support 

Enea's OSE RTOS provides real-time oper- 
ating-system support for Texas Instruments' 
C64x DSP, as well as all previous-genera- 
tion C64x DSPs in both single-processor 
and multiprocessor configurations. The OSE 
provides interprocessor-communications 
mechanisms that allow multiple processes 
running on multiple DSPs to communicate 
as though they were on the same DSP 
Enea Embedded Technology, 
www.enea.com 



Electronic Design Aut omation 



ISE plugs directly into EDA design flows 

The ISE (integrated software environ- 
ment) 7.1i integrates key power- analysis, 
hierarchical-design, simulation, and de- 
bugging features and supports Linux- 
based design environments. The ISE fea- 
tures a design-summary view and mess- 
age filtering, highlighting important de- 
sign information. A technology viewer 
displays postsynthesis-implementation 
results in a schematic view. The product 
also includes the ISE simulator and 
ModelSim Xilinx Edition-Ill; ChipScope 
Pro, providing remote system debugging; 
and the ability to directly plug into EDA 
design flows, including deep integration 
to third-party EDA-partner design tools. 
The product integrates with the vendor's 
PlanAhead option, allowing a new layer 
of hierarchical design and decreasing de- 
sign cycles with incremental compiling, 
fewer timing iterations, and efficient in- 
tellectual-property planning and reuse. 
The ISE 7.1i suits the company's Virtex-4 
and Spartan-3e FPGA families and sup- 
ports 64-bit Linux. Prices range from 
$695 to $2495. 
Xilinx Inc, www.xilinx.com 



Programmable bridge 
targets use in Intel PXA2XX 

QuickLogic Corp has announced its 
first product in a series of uWatt pro- 
grammable bridges for Intel PXA2XX 
processor line, which QuickLogic based 
on the Intel XScale microarchitecture. 
The QuickPCI -based bridge allows de- 
signers to expand the Intel XScale mi- 
croarchitecture's native peripheral set to 
communicate with PCI-based peripher- 
als, such as Wi-Fi, Ultra Wideband, and 
USB 2.0 to aid users targeting applica- 
tion such as handheld GPS, portable 
medical systems, voice-over-wireless- 
LAN PDAs, and smart phones. In addi- 
tion to the bridge, QuickLogic has de- 
veloped a Wi-Fi product comprising a 
daughtercard that plugs into Intel's 
PXA270-based mainstone processor de- 
veloper's kit using a VLIO (Variable La- 
tency I/O) connector and a Linux OS 
board-support package. QuickLogic 
plans to support the Windows CE and 
Windows Mobile operating systems 
over the coming months. 
QuickLogic Corp, www.quicklogic.com 



Upgrade automatically reads and checks SDC 

Chip2Nite Version 2.1'$ upgrade allows for automated reading and checking of SDCs (Synopsys 
design-constraints) files, enabling logic designers to verify the files early in the design process, 
reducing overall design-cycle time. The product includes automatic macro placement and block 
floorplanning capabilities, as well as support for groups and floorplans, allowing designers to 
classify logic into groups and assign them to regions of the floorplan; postplacement-analysis 
features, such as pin density to reduce congestion and to support top-level pins; and five to 10 
times speed and capacity improvements over typical-database loading times, which are critical 
to performing rapid prototyping and what-if analyses. 
Silicon Dimensions, 1-508-281-5170, www.sidimensions.com 



adverti sersinde x 



COMPANY 


PAGE 


CIRCL 


Actel Corp 


14 


8 


Adobe Systems Inc 


4-5 




Altera Corp 


59 


30 


Analog Devices Inc 


6 






23 




Cirrus Logic Inc 


61 


31 


Dataq Instruments Inc 


85 




Datel Inc 


77 


38 


Digi-Key Corp 


1 


1 


Epcos AG 


43 


23 


Express PCB 


44 




Fujitsu Microelectronics America, Inc 25 


12 


Gage Applied Technologies, LLC 


36 


16 


International Rectifier Corp 


45 


25 


Intersil 


11 


6 




28 


14 




35 


15 




42 


22 




64 


33 




83 


41 


LeCroy Corp 


10 


5 


Linear Technology Corp 


67 


34 




69 


35 




71 


36 




72 


37 




73-74 




Magnetek 


12 


7 


Maxim Integrated Products 


79 


39 




81 


40 


Maxstream Inc 


44 


24 


Mentor Graphics 


19 


10 


Micrel Semiconductor 


27 


13 


Microchip Technology 


57 


29 


Mill-Max Mfg Corp 


37 




Molex Inc 


54, 55 


28 


Monolithic Power Systems 


39 


18 


Mouser Electronics 


C-3 


42 


National Instruments 


38 


17 




49 


26 


National Semiconductor 


30 






31 






33 




NEC Electronics 


13 




NewarklnOne 


53 


27 


Power Integrations Inc 


41 




Samsung Semiconductor 


21 


11 


Samtec USA 


2 


2 


Senscomp Inc 


85 


230 


Sensirion Ag 


85 


232 


STMicroelectronics 


C-4 


43 


Tech Tools 


85 


231 


Techrecovery 


40 


19 


Tern 


85 


234 


Texas Instruments 


C-2 




40- 


8 

B, 40-A 






51 




Vicor Corp 


63 


32 


WinSystems 


17 


9 


Xilinx Inc 


3 


3 



This index is provided as an additional service. The 
publisher does not assume any liability for errors or 
omissions. 

For immediate information on products and serv- 
ices, go to Reader Service at www.edn.com. 



86 EDN I April 28, 2005 



www.edn.com 




DLP 

Design 



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