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NEC  Electronics 


NEC 


MICROCOMPUTER  PRODUCTS 


SEC 


1983/1984  MICROCOMPUTER  CATALOG 


The  information  in  this  document  is  subject  to  change  without  notice.  NEC  Electronics 

Inc.  makes  no  warranty  of  any  kind  with  regard  to  this  material,  including,  but 

not  limited  to,  the  implied  warranties  of  merchantability  and  fitness  for  a  particular 

purpose.  NEC  Electronics  Inc.  assumes  no  responsibilities  for  any  errors  that  may 

appear  in  this  document.  NEC  Electronics  Inc.  makes  no  commitment  to  update 

nor  to  keep  current  the  information  contained  in  this  document. 

No  part  of  this  document  may  be  copied  or  reproduced  in  any  form  or  by  any  means 

without  the  prior  written  consent  of  NEC  Electronics  Inc. 

©  1983  by  NEC  Electronics  Inc. 
Printed  in  the  United  States  of  America 


CONTENTS 
GENERAL  INFORMATION 
SINGLE  CHIP  4-BIT  MICROCOMPUTERS 
SINGLE  CHIP  8-BIT  MICROCOMPUTERS 

MICROPROCESSORS 
PERIPHERALS 

PACKAGE  OUTLINES 

QUALITY  &  RELIABILITY 
OF  NEC  MICROPROCESSORS 

REPRESENTATIVES  &  DISTRIBUTORS 


NEC 


FUNCTIONAL  INDEX 


SINGLE  CHIP 

4-BIT  MICROCOMPUTERS 

Selection  Guide   2-1 

Alternate  Source  Guide   2-4 

ROM-Based  Products  Ordering 

Procedure   2-6 

|xCOM-4    3-1 

M-PD557L    3-13 

*jiPD552/553    3-15 

jxPD550/554    3-17 

^PD550L/554L   3-19 

|xPD556B  Evaluation  Chip   3-21 

lxPD7500  Series  Introduction  . .  3-25 

HPD7501    3-35 

|xPD7502/7503    3-41 

|xPD7506    3-47 

jjlPD7507/7508    3-53 

|xPD7507S   3-61 

H,PD7508A   3-67 

|jiPD7508H    3-75 

HPD7514    3-81 

M,PD7519/75CG19E   3-89 

fxPD7520    3-97 

HPD7527/7528/7537/7538    3-103 

|xPD7500  Evaluation  Chip   ....  3-105 

MC-430P   3-113 

SINGLE  CHIP 

8-BIT  MICROCOMPUTERS 

Selection  Guide   2-2 

Alternate  Source  Guide   2-4 

ROM-Based  Products  Ordering 

Procedure    2-6 

lxPD7800    4-1 

|xPD7801/7802    4-11 

jjiPD78C06/78C05   4-35 

MPD7809J7807/78P09   4-45 

|xPD7810/7811    4-51 

jxPD8021    4-65 

|xPD8041  A/8741  A   4-71 

(xPD8048H/8035HL    4-83 

*xPD8748    4-91 

piPD80C48/80C35   4-103 

fxPD8049H/8749H/8039HL   4-119 

|xPD80C49/80C39   4-127 

MICROPROCESSORS 

Selection  Guide   2-2 

Alternate  Source  Guide   2-4 

|xPD780   5-1 

fiPD8085AH/iiPD8085A-2    ...  5-15 

ptPD8086    5-27 

HPD8088    5-39 


PERIPHERALS 

Selection  Guide   2-3 

Alternate  Source  Guide   2-4 

ROM-Based  Products  Ordering 

Procedure   2-6 

MPD765A/7265    6-1 

^PD7201A   6-15 

fxPD7210   6-31 

^PD7220    6-47 

|xPD7225    6-71 

^PD7227    6-79 

|xPD7228    6-87 

fxPD7261    6-93 

|xPD7720    6-115 

(xPD77P20    6-123 

fjiPD7751    6-131 

|xPD7752    6-133 

IXPD7761/7762//MC-4760    6-135 

fxPD81 55/81 56    6-137 

^PD8155H/^PD8156H    6-145 

|xPB8212   6-153 

^PB821 6/8226    6-159 

^PD8237A-5    6-163 

(xPD8243    6-175 

M-PD82C43    6-181 

|xPD8251  A/8251  AF    6-187 

^PD8253-2/n-PD8253-5    6-205 

|xPD8255A-2VPD8255A-5  .  ..  6-213 

jjlPD8257-2/^PD8257-5   ..      ..  6-221 

|xPD8259A/fxPD8259A-2   6-231 

^PD8279-2/pPD8279-5    6-249 

M.PB8282/8283    6-259 

^PB8284A   6-263 

|xPB8286/8287    6-269 

|xPB8288    6-275 

^PB8289    6-283 

fxPD8355/M,PD8355-2/ 

M-PD8755A    6-293 

PACKAGE  OUTLINES   7-1 

QUALITY  & 
RELIABILITY  OF  NEC 
MICROPROCESSORS    8-1 

REPRESENTATIVES  & 
DISTRIBUTORS    9-1 


1-1 


1-2 


NEC 


NUMERICAL  INDEX 


PRODUCT  PAGE 

M-COM-4    3-1 

MC-430P   3-113 

MC-4760    6-135 

|xPD550   3-17 

fjiPD550L    3-19 

|xPD552   3-15 

^PD553   3-15 

(xPD554   3-17 

fxPD554L    3-19 

^PD556B   3-21 

fJ»D557L    3-13 

^PD765A   6-1 

|aPD780   5-1 

|jlPD7201A   6-15 

fxPD7210    6-31 

>jlPD7220    6-47 

M-PD7225    6-71 

M-PD7227    6-79 

|xPD7228    6-87 

M.PD7261    6-93 

ptPD7265    6-1 

fxPD7500  Evaluation  Chip    3-105 

fxPD7500  Series  Introduction   3-25 

^PD7501    3-35 

M.PD7502    3-41 

HPD7503    3-41 

M.PD7506    3-47 

|xPD7507    3-53 

(xPD7507S   3-61 

*aPD7508    3-53 

^PD7508A   3-67 

H-PD7508H   3-75 

jjlPD7514    3-81 

1XPD7519    3-89 

M,PD7520    3-97 

IAPD7527    3-103 

^PD7528    3-103 

|xPD7537    3-103 

^PD7538    3-103 

|xPD7720    6-115 

^PD77P20    6-123 

*xPD7751    6-131 

M-PD7752    6-133 

^PD7761    6-135 

M-PD7762    6-135 

MPD7800    4-1 

(xPD7801    4-11 

fxPD7802   4-11 

|xPD78C05   4-35 

jjlPD78C06   4-35 

jiPD7807    4-45 

^PD7809    4-45 

HLPD78P09    4-45 


PRODUCT  PAGE 

|xPD7810    4-51 

fjLPD7811    4-51 

pPD8021    4-65 

M-PD8035HL   4-83 

|xPD80C35   4-103 

HPD8039HL   4-119 

HPD80C39   4-127 

M-PD8041A   4-71 

HPD8048H   4-83 

|xPD80C48   4-103 

MPD8049H   4-119 

H-PD80C49   4-127 

|xPD8085AH   5-15 

H-PD8085A-2    5-15 

|xPD8086    5-27 

^PD8088    5-39 

|xPD8155   6-137 

M-PD8155H    6-145 

|xPD8156    6-137 

HPD8156H   6-145 

M-PB8212    6-153 

IXPB8216    6-159 

(jlPB8226    6-159 

jjlPD8237A-5    6-163 

fxPD8243    6-175 

M-PD82C43   6-181 

M-PD8251A   6-187 

fxPD8251AF   6-187 

|xPD8253-2    6-205 

M-PD8253-5    6-205 

M-PD8255A-2    6-213 

fji,PD8255A-5   6-213 

I0.PD8257-2    6-221 

fxPD8257-5    6-221 

|xPD8259A    6-231 

H.PD8259A-2   6-231 

|xPD8279-2    6-249 

M-PD8279-5    6-249 

H,PD8282    6-259 

txPD8283    6-259 

|xPD8284A   6-263 

M-PD8286    6-269 

H,PD8287    6-269 

^PD8288    6-275 

(XPD8289    6-283 

|xPD8355    6-293 

^PD8355-2    6-293 

|xPD8355A   6-293 

|xPD8741  A    4-71 

(xPD8748    4-91 

|xPD8749H   4-119 

fiPD8755A   6-293 


1-3 


NEC 


GENERAL  INFORMATION 


SEC 


MICROCOMPUTER  SELECTION  GUIDE 


SINGLE  CHIP  4-BIT  MICROCOMPUTERS 


DEVICE 

FAMILY 

ROM 

RAM 

I/O 

PROCESS 

OUTPUT 

FEATURES 

SUPPLY 
VOLTAGE 

PINS 

|xPD553 

ZUUU  X  o 

96  x  4 

35 

PMOS 

O.D. 

A 

— 10 

42 

|xPD557L 

(AUUIVI-^ooL 

ZUUU  X  o 

96  x  4 

21 

PMOS 

U.U. 

A 

—  8 

28 

\xruooz. 

.. rny  aavx 

(JlLUIVI-'Rrl 

1 nnn  v  q 
iuuu  x  o 

64  x  4 

35 

rlvlUo 

r\  Pi 
U.U. 

A 

— 10 

42 

|XrUOOU 

..POM  /IK 

640  x  8 

32  x  4 

21 

DMPiC 

rlvlUo 

p«  n 
U.U. 

A 

— 10 

28 

(xrUooUL 

■  ■POM  ^Kl 

640  x  8 

32  x  4 

21 

PMOS 

O.D. 

A 

—  8 

28 

ixruoo'f 

/IK 

U-UUIVI-'kJ 

IUUU  x  o 

32  x  4 

21 

PMOS 

O.D. 

A 

— 10 

28 

..pptiv/i  >iki 
|AUUIV1-'k)L 

1  nr\f\  v  q 
IUUU  X  o 

32  x  4 

21 

rlvlUo 

U.U. 

A 

—  8 

28 

(JLrUDDDtS 

„priM  A1 

External 

96  x  4 

35 

DMPiC 

rlvlUo 

p<  n 
U.U. 

B 

— 10 

64 

MP  /IUAP 
IVlU-4oUr 

,.rriM  /lo 

ZUUU  X  o 

96  x  4 

35 

rlvlUo 

U.U. 

G 

— 10 

42 

UV  EPROM 

[XPD7500 

|aPD7500  Series 

External 

256  x  4 

46 

CMOS 

O.D. 

C 

+  2.7  to  5.5 

64 

|jPD7501 

u,PD7500  Series 

1024  x  8 

96  x  4 

24 

CMOS 

O.D. 

D 

+  2.7  to  5.5 

64 

IXPD7502 

|xPD7500  Series 

2048  x  8 

128  x  4 

23 

CMOS 

O.D. 

D 

+  2.7  to  5.5 

64 

U.PD7503 

jaPD7500  Series 

4096  x  8 

224  x  4 

23 

CMOS 

O.D. 

D 

+  2.7  to  5.5 

64 

M-PD7506 

u,PD7500  Series 

1024  x  8 

64  x  4 

22 

CMOS 

O.D. 

+  2.7  to  5.5 

28 

|xPD7507 

(xPD7500  Series 

2048  x  8 

128  x  4 

32 

CMOS 

O.D. 

+  2.7  to  5.5 

40/52 

|xPD7507S 

P-PD7500  Series 

2048  x  8 

128  x  4 

20 

CMOS 

O.D. 

+  2.7  to  5.5 

28 

uPD7508 

IAPD7500  Series 

4096  x  8 

224  x  4 

32 

CMOS 

O.D. 

+  2.7  to  5.5 

40/52 

|xPD7508H 

u,PD7500  Series 

4096  x  8 

224  x  4 

32 

CMOS 

O.D. 

+  2.7  to  5.5 

40/52 

u,PD7508A 

|xPD7500  Series 

4096  x  8 

208  x  4 

32 

CMOS 

O.D. 

A 

+  2.7  to  5.5 

40 

M-PD7519 

M-PD7500  Series 

4096  x  8 

256  x  4 

28 

CMOS 

O.D. 

F 

+  2.7  to  5.5 

64 

u,PD7520 

U.PD7500  Series 

768  x  8 

48  x  4 

24 

PMOS 

O.D. 

E 

-6to  -10 

28 

|xPD7514 

(xPD7500  Series 

4096  x  8 

256  x  4 

31 

CMOS 

O.D. 

D 

+  2.7  to  5.5 

80 

u,PD7528/38 

|aPD7500  Series 

4096  x  8 

160  x  4 

35 

CMOS 

O.D. 

A 

+  2.7  to  5.5 

42 

M-PD7527/37 

jxPD7500  Series 

2048  x  8 

160  x  4 

35 

CMOS 

O.D. 

A 

+  2.7  to  5.5 

42 

A  =  - 35VVF  Display  Drive 

B  =  |xCOM-4  Evaluation  Chip 

C  =  jjiPD750X  Evaluation  Chip 

D  =  LCD  Controller/Driver 

E  =  LED  Display  Controller/Driver 

F  =  VF  Display  Controller/Driver 

G  =  Pin-Compatible  with  ^.PD546 

O.D.  =  Open  Drain 


2-1 


SEC 


MICROCOMPUTER  SELECTION  GUIDE 


S/NGLE  CHIP  8-BIT  MICROCOMPUTERS 


DEVICE 

SPECIAL  FEATURES 

ROM 

RAM 

I/O 

PROCESS 

OUTPUT 

CYCLE 

SUPPLY 
VOLTAGE 

PINS 

. . Dnoni 1 
|Ar  DoU£  I 

Zero-Cross  Detector 

lUZ'f  x  o 

64  x  8 

21 

Miv/inc 

on 

O.  R  MU-* 

o.d  ivlnZ 

+  5 

Oft 

..  DrtQnocui 
|xrUoUobriL 

H-PD8048  w/External  Memory 

External 

64  x  8 

07 

UMflC 

niviuo 

tc  on 

1  O,  DU 

R  MU-7 

o  ivinz 

+  5 

A(\ 
H\J 

(xrUoUoynL 

|xPD8049  w/External  Memory 

External 

1  Oft  v  ft 
Izo  X  o 

07 

uiv/tnc 
nivtUo 

tc  on 

1  O,  DU 

I  I  ivinz 

+  5 

A(\ 

|xr UoU4  I 

Peripheral  Interface  w/Slave  Bus 

IU^4  x  o 

RA  v  ft 

1  ft 

M  moc 

INIVIUO 

tc  on 

1  O,  DU 

R  MU-7 
D  IVInZ 

4-5 

A(\ 

ixruou'r  i  A 

tnnancea  ixrueuHi 

mo4  v  ft 

RA  v  ft 
Oh  X  o 

18 

*  MM  HQ 
INIVIUO 

TC  RH 
1  O,  DU 

6  MHz 

4-  R 
T"  0 

40 

(ir  UoUHon 

Expansion  Bus 

1024  x  8 

64  x  8 

27 

HMOS 

TS  BD 

6  MHz 

4-  R 

40 

. .  Dnon/iou 
|xrUo04»n 

nign  opeea  fxruowo 

ZU4o  X  o 

128  x  8 

27 

niviuo 

TS,  BD 

1  1  MU-7 
I  I  IVI  HZ 

+  5 

40 

..  Dr»Q*7/l  1  A 
fJirUo/4  I A 

UV-trnUIVI  ixruou'r  1 A 

I       x  o 

RA  v  ft 
Oh-  X  o 

1  ft 
io 

IN  IVIUO 

TC  pn 

1  O,  DU 

R  MU-7 

d  ivinz 

+  0 

/in 

(JlrUo/40 

UV-trnUIVI  |XrUoUH-o 

I  UZ'r  x  O 

RA  v  ft 
0*1  X  o 

CI 

MMHC 
IM IVIUO 

tc  nn 

1  O,  DU 

r  MU-7 

d  ivinz 

-i-  R 

An 

..  Dn07/IQU 

fxrUo/4yn 

UV-trnUIVI  |JLrUoU4y 

OClAQ  -v  ft 
ZU4o  X  o 

128  x  8 

07 

UMnc 
niviuo 

tc  on 

1  O,  DU 

1  1  MU-» 
I  I  IVInZ 

+  5 

AC\ 

fjtPD80C35 

CMOS  8035 

External 

64  x  8 

27 

CMOS 

TS,  BD 

6  MHz 

+  2.7  to  5.5 

40 

yPD80C48 

CMOS  8048 

1024  x  8 

64  x  8 

27 

CMOS 

TS,  BD 

6  MHz 

+  2.7  to  5.5 

40 

M.PD80C39 

CMOS  8039 

External 

128  x  8 

27 

CMOS 

TS,  BD 

8  MHz 

+  2.7  to  5.5 

40 

(xPD80C39H 

CMOS  8039H 

External 

128  x  8 

27 

CMOS 

TS,  BD 

12  MHz 

+  2.7  to  5.5 

40 

|xPD80C49 

CMOS  8049 

2048  x  8 

128  x  8 

27 

CMOS 

TS,  BD 

8  MHz 

+  2.7  to  5.5 

40 

HPD80C49H 

CMOS  8049H 

2048  x  8 

128  x  8 

27 

CMOS 

TS,  BD 

12  MHz 

+  2.7  to  5.5 

40 

|xPD7800 

Development  Chip 

External 

128  x  8 

48 

NMOS 

TS,  BD 

4  MHz 

+  5 

64 

M.PD7801 

8080  Expansion  Bus 

4096  x  8 

128  x  8 

48 

NMOS 

TS,  BD 

4  MHz 

+  5 

64 

64K  Memory  Address  Space 

^PD7802 

Expanded  (xPD7801 

6144  x  8 

64  x  8 

48 

NMOS 

TS,  BD 

4  MHz 

+  5 

64 

^PD78C05 

CMOS  Microprocessor 

External 

128  x  8 

46 

CMOS 

TS,  BD 

4  MHz 

+  5 

64 

fiPD78C06 

CMOS  Microcomputer 

4096  x  8 

128  x  8 

46 

HCMOS 

TS,  BD 

4  MHz 

+  5 

64 

(xPD7807 

7809  w/Ext.  Memory 

External 

256  x  8 

40 

HMOS 

TS,  BD 

12  MHz 

+  5 

64 

fxPD7809 

8/16  Bit  Microcomputer 

8192  x  8 

256  x  8 

40 

HMOS 

TS,  BD 

12  MHz 

■-  +  5 

64 

(xPD7810 

Romiess  |xPD781 1 

External 

256  x  8 

44 

NMOS 

TS,  BD 

12  MHz 

+  5 

64 

M-PD781 1 

8  Channel  A/D/8-16  Bit  Micro 

4096  x  8 

128  x  8 

44 

NMOS 

TS,  BD 

12  MHz 

+  5 

64 

MICROPROCESSORS 


DEVICE 

PRODUCT 

SIZE 

PROCESS 

OUTPUT 

CYCLE 

SUPPLY 
VOLTAGES 

PINS 

fxPD780 

Microprocessor 

8-bit 

NMOS 

3-State 

2.5  MHz 

+  5 

40 

IAPD780-1 

Microprocessor 

8-bit 

NMOS 

3-State 

4.0  MHz 

+  5 

40 

HPD780-2 

Microprocessor 

8-bit 

NMOS 

3-State 

6.0  MHz 

+  5 

40 

^PD8085A 

Microprocessor 

8-bit 

NMOS 

3-State 

3.0  MHz 

+  5 

40 

jjlPD8085A-2 

Microprocessor 

8-bit 

NMOS 

3-State 

5.0  MHz 

+  5 

40 

M-PD8085AH 

Microprocessor 

8-bit 

NMOS 

3-State 

3.0  MHz 

+  5 

40 

jjlPD8086 

Microprocessor 

16-bit 

NMOS 

3-State 

5.0  MHz 

+  5 

40 

|aPD8086-2 

Microprocessor 

16-bit 

NMOS 

3-State 

8.0  MHz 

+  5 

40 

jjiPD8088  ' 

Microprocessor 

8-bit 

NMOS 

3-State 

5.0  MHz 

+  5 

40 

2-2 


SEC 


MICROCOMPUTER  SELECTION  GUIDE 


SYSTEM  SUPPORT 


DEVICE 

PRODUCT 

SIZE 

PROCESS 

OUTPUT 

CYCLE 

SUPPLY 
VOLTAGES 

PINS 

^PD765A 

Double  Sided/Double  Density 
Floppy  Disk  Controller 

8-bit 

NMOS 

3-State 

8  MHz 

+  5 

40 

(XPD7201A 

Multi-Protocol  Serial  Controller 

8-bit 

NMOS 

3-State 

4  MHz 

+  5 

40 

(XPD7210 

IEEE  Controller  (Talker,  Listener, 
Controller) 

8-bit 

NMOS 

3-State 

8  MHz 

+  5 

40 

(xPD7220 

Color  Graphic  Display  Controller 

8-bit 

NMOS 

3-State 

5  MHz 

+  5 

40 

|xPD7225 

Alpha  Numeric  LCD 
Controller/Driver 

8-bit 

CMOS 

2.7  to  5.5 

52 

(xPD7227 

Dot  Matrix  LCD  Controller/Driver 

8-bit 

CMOS 

- 

- 

2.7  to  5.5 

64 

|xPD7228 

Dot  Matrix  LCD  Controller/Driver 

8-bit 

CMOS 

2.7  to  5.5 

80 

jjlPD7720 

Signal  Processor 

16-bit 

NMOS 

3-State 

8  MHz 

+  5 

28 

(xPD77P20 

EPROM  Version  of  jjlPD7720 

16-bit 

NMOS 

3-State 

8  MHz 

+  5 

28 

P-PD8155H 

256  x  8  RAM  with  I/O  Ports 
and  Timer 

8-bit 

HMOS 

3-State 

+  5 

40 

M,PD8155-2 

256x8  RAM  with  I/O  Ports 
and  Timer 

8-bit 

NMOS 

3-State 

- 

+  5 

40 

jxPD8156H 

256x8  RAM  with  I/O  Ports 
and  Timer 

8-bit 

HMOS 

3-State 

_ 

+  5 

40 

jjlPD8156-2 

256  x  8  RAM  with  I/O  Ports 
and  Timer 

8-bit 

NMOS 

3-State 

- 

+  5 

40 

|jlPB8212 

I/O  Port 

8-bit 

Bipolar 

3-State 

+  5 

24 

(xPB8216 

Bus  Driver  Non-Inverting 

4-bit 

Bipolar 

3-State 

+  5 

16 

^jlPB8226 

Bus  Driver  Inverting 

4-bit 

Bipolar 

3-State 

+  5 

16 

jjlPD8243 

I/O  Expander 

4x4  bits 

NMOS 

3-State 

+  5 

24 

IXPD82C43 

I/O  Expander 

4x4  bits 

CMOS 

3-State 

- 

+  5 

24 

(xPD8251  A/AF 

Programmable  Communications 
Interface  (Async/Sync) 

8-bit 

NMOS 

3-State 

A-9.6K  baud 
S-64K  baud 

+  5 

28 

txPD8253-2/-5 

Programmable  Timer 

8-bit 

NMOS 

3-State 

4.0  MHz 

+  5 

24 

fjLPD8255A-2/-5 

Peripheral  Interface 

8-bit 

NMOS 

3-State 

+  5 

40 

M,PD8257-2/-5 

Programmable  DMA  Controller 

8-bit 

NMOS 

3-State 

4  MHz 

+  5 

40 

fiPD8259-2/-5 

Programmable  Keyboard/Display 
Interface 

8-bit 

NMOS 

3-State 

+  5 

40 

jjlPB8282/8283 

8-Bit  Latches 

Bipolar 

3-State 

5  MHz 

+  5 

20 

jiPB8284A 

Clock  Driver 

Bipolar 

3-State 

5  MHz 

+  5 

18 

jjlPB8286/8287 

8-Bit  Bus  Transceivers 

Bipolar 

3-State 

5  MHz 

+  5 

20 

jjlPB8288 

Bus  Controller 

Bipolar 

3-State 

5  MHz 

+  5 

20 

fiPB8289 

Bus  Arbiter 

Bipolar 

3-State 

5  MHz 

+  5 

20 

jjlPD8355/-2/A 

2048  x  8  ROM  with  I/O  Ports 

8-bit 

NMOS 

3-State 

+  5 

40 

(XPD8755A 

2048  x  8  EPROM  with  I/O  Ports 

8-bit 

NMOS 

3-State 

+  5 

40 

|xPD8759A/A-2 

Programmable  Interrupt  Controller 

8-bit 

HMOS 

3-State 

5/8  MHz 

+  5 

28 

SPEECH 
PRODUCTS 

^PD7751 

ADPCM  Speech  Synthesizer 

8-bit 

NMOS 

3-State 

6  MHz 

+  5 

40 

^PD7752 

Formant  Speech  Synthesizer 

8-bit 

CMOS 

3-State 

3  6  MHz 

+  5 

28 

^PD7761  ^ 
H,PD7762  > 
lxMC-4760  J 

K  3  Chip-SR  Speech  Recognition 
Chip  Set 

16-bit 
8-bit 

NMOS 
NMOS 
Hybrid 

3-State 
3-State 
3-State 

8  MHz 
4  MHz 
2  MHz 

+  5 
+  5 

+  5,  ±12 

28 
64 
24 

2-3 


NEC 


MICROCOMPUTER  ALTERNATE  SOURCE  GUIDE 


MANUFACTURER 

PART  NUMBER 

DESCRIPTION 

NEC  REPLACEMENT 

AMD 

AM8085A 

Microprocessor  (3.0  MHz) 

HPD8085A 

AM8155 

Programmable  Peripheral  Interface 
with  256  x  8  RAM 

fxPD8155 

AM8156 

Programmable  Peripheral  Interface 
with  256  x  8  RAM 

HPD8156 

AM8212 

I/O  Port  (8-Bit) 

|xPB8212 

AM8214 

Priority  Interrupt  Controller 

M.PB8214 

AM8216 

Bus  Driver,  Inverting 

(xPB8216 

AM8226 

Bus  Driver,  Non-Inverting 

|xPB8226 

AM8251 

Programmable  Communications 
Interface 

|xPD8251 

AM8255 

Programmable  Peripheral  Interface 

HPD8255 

AM8257 

Programmable  DMA  Controller 

|xPD8257 

AM8355 

Programmable  Peripheral  Interface 
with  2048  x  8  ROM 

(xPD8355 

AM8048 

Single  Chip  Microcomputer 

|xPD8048 

AMI 

7500  Family 

4-Bit  CMOS  Microcomputer 

|xPD750X 

78C06/78C05 

8-Bit  CMOS  Microcomputer 

M.PD78C06/78C05 

7810/7811 

16-Bit  High-Performance 
Microcomputer 

M.PD781 0/7811 

7807/7809 

16-Bit  High-Performance 
Microcomputer 

HPD7807/7809 

7720 

Signal  Processor 

|xPD7720 

INTEL 

8021 

Microcomputer  with  ROM 

(xPD8021 

8035HL 

Microprocessor 

|xPD8035HL 

8039HL 

Microprocessor 

jjlPD8039HL 

8041 A 

Programmable  Peripheral  Controller 
with  ROM 

MPD8041A 

8048H 

Microcomputer  with  ROM 

MPD8048H 

8049H 

Microcomputer  with  ROM 

|xPD8049H 

8085A 

Microprocessor  (3.0  MHz) 

HPD8085A 

8085A-2 

Microprocessor  (5.0  MHz) 

M-PD8085A-2 

8086 

Microprocessor  (1 6-Bit) 

HPD8086 

8155/8155-2 

Programmable  Peripheral  Interface 
with  256  x  8  RAM 

|xPD81 55/81 55-2 

8156/8156-2 

Programmable  Peripheral  Interface 
with  256  x  8  RAM 

M-PD81 56/81 56-2 

8212 

I/O  Port  (8-Bit) 

HPB8212 

8214 

Priority  Interrupt  Controller 

MPB8214 

8216 

Bus  Driver,  Non-Inverting 

|xPB8216 

8226 

Bus  Driver,  Inverting 

MPB8226 

8243 

I/O  Expander 

|jlPD8243 

2-4 


SEC 


MICROCOMPUTER  ALTERNATE  SOURCE  GUIDE 


MANUFACTURER 

PART  NUMBER 

DESCRIPTION 

NEC  REPLACEMENT 

INTEL  (CONT.) 

8251A 

Programmable  Communications 
Interface  (Async/Sync) 

|xPD8251A 

8253-5 

Programmable  Timer 

MPD8253-5 

8255A-5 

Programmable  Peripheral  Interface 

MPD8255A-5 

8257-5 

Programmable  DMA  Controller 

M-PD8257-5 

8259A 

Programmable  Interrupt  Controller 

fjiPD8259A 

8272 

Double  Sided/Double  Density 
Floppy  Disk  Controller 

|xPD765 

8279-5 

Programmable  Keyboard/Display 
Interface 

HPD8279-5 

8282/8283 

8-Bit  Latches 

|xPB8282/8283 

8284 

Clock  Driver 

|jlPB8284 

8286/8287 

8-Bit  Transceivers 

pPB8286/8287 

8288 

Bus  Controller 

pPB8288 

8355 

Programmable  Peripheral  Interface 
with  2048  x  8  ROM 

(xPD8355 

8741 A 

Programmable  Peripheral  Controller 
with  EPROM 

^PD8741A 

8748 

Microcomputer  with  EPROM 

^PD8748 

8749H 

Microcomputer  with  EPROM 

|jlPD8749H 

8755A 

Programmable  Peripheral  Interface 
with  2Kx  8  EPROM 

^PD8755A 

8274 

Multiprotocol  Serial  Controller 

|xPD7201 

NATIONAI 

IN98fl<48 

IINOOU*+0 

Microcomputer  with  ROM 

■i  PnsnAft 

|Xr  UoU'to 

INS8049 

Microcomputer  with  ROM 

^PD8049 

8212 

I/O  Port  (8-Bit) 

JJIPB8212 

8214 

Priority  Interrupt  Controller 

^PB8214 

8216 

Bus  Driver,  Non-Inverting 

(XPB8216 

8226 

Bus  Driver,  Inverting 

^PB8226 

INS8251 

Programmable  Communications 
Interface 

pPD8251A 

INS8253 

Programmable  Timer 

pPD8253-5 

INS8255 

Programmable  Peripheral  Interface 

jxPD8255A-5 

INS8257 

Programmable  DMA  Controller 

MPD8257-5 

INS8259 

Programmable  Interrupt  Controller 

M.PD8259A 

T.I. 

SN74S412 

I/O  Port  (8-Bit) 

|xPB821 2 

2-5 


NEC 


ROM-BASED  PRODUCTS  ORDERING  PROCEDURE 


The  following  NEC  products  fall  under  the  guidelines  set  by  the  ROM-based  Products  Ordering  Procedure: 


|xPD7801 
fiPD7802 
|xPD78C06 
|xPD7807 
fxPD7808 
|xPD781 1 
|jlPD8021 


|xPD8041AH 
M.PD8048H 


|xPD80C48 
jjiPD8049H 
^PD80C49 


(xPD8355 
(jlPD550 
fjuPD550L 
|xPD552 
|xPD553 
(jlPD554 


|jlPD554L 

|xPD557L 

|xPD7501 

|xPD7502 

|jlPD7503 

fiPD7506 

MPD7507 

|jlPD7507S 

(jlPD7508 


fxPD7508A 

fiPD7508H 

|xPD7514 

fxPD7519 

|jlPD7520 

|jlPD7527 

|xPD7528 

fjiPD7537 

|xPD7538 

|xPD7720 


M-PD2308A 

pPD2316E 

^PD2332 

|xPD2364 

M-PD2380 

^PD23128 

fjiPD23256 

jjlPD231000 

M.PD23C128 

fxPD73128G 

jxPD23C256 

|xPD731000 


NEC  Electronics  Inc.  is  able  to  accept  mask  patterns  in  a  variety  of  formats  to  facilitate  the  trahsferral  of  ROM  mask  informa- 
tion. These  are  intended  to  suit  various  customer  needs  and  minimize  turnaround  time.  Always  enclose  a  listing  of  the  code 
and  a  complete  "ROM  Code  Submission"  form.  The  following  is  a  list  of  acceptable  media  for  code  transferral. 

•  PROM/EPROM  equivalents  to  ROM  devices 

•  Sample  ROMs  or  ROM-based  microcomputers 

•  ISIS-II  compatible  8"  floppy  disks 

•  CP/M  (®  Digital  Research  Corp.)  compatible  8"  single-density  floppy  disk 

Thoroughly  tested  verification  procedures  protect  against  unnecessary  delays  or  costly  mistakes.  NEC  Electronics  Inc.  will 
return  the  ROM  code  patterns  to  the  customer  in  the  most  convenient  format.  Unprogrammed  EPROMs,  if  sent  with  the 
ROM  code,  can  be  programmed  and  returned  for  verification.  Earth  satellites  and  the  world-wide  GE  Mark  III  timesharing 
systems  provide  reliable  and  instant  communication  of  ROM  patterns  to  the  factory. 

The  following  is  an  example  of  a  ROM  code  transferral  procedure.  The  |jlPD8048H  is  used  here;  however,  the  process  is  the 
same  for  all  other  ROM-based  products. 

1.  The  customer  contacts  his  local  NEC  Electronics  Inc.  Sales  Representative,  concerning  a  ROM  pattern  for  the 
|xPD8048H  that  he  would  like  to  send. 

2.  Since  an  EPROM  version  of  that  part  is  available,  the  |xPD8748  is  proposed  as  a  code  transferral  medium. 
Alternatively,  a  |jlPD2716  or  a  floppy  disk  may  be  used. 

3.  Two  programmed  |xPD8748s  are  sent  to  NEC  Electronics  Inc.,  along  with  a  listing  and  the  "ROM  Code  Submission" 
form.  A  floppy  disk  may  also  be  sent  as  back-up. 

4.  NEC  Electronics  Inc.  compares  the  media  provided  and  enters  the  code  into  GE-TSS.  The  GE-TSS  file  is  accessed 
at  the  NEC  factory  and  a  copy  of  the  code  is  returned  to  NEC  Electronics  Inc.  for  verification.  One  of  the  |jlPD8748s 
is  erased  and  reprogrammed  with  the  customer's  code  as  the  NEC  factory  has  it.  The  |xPD8748s,  a  listing,  and  a 
"ROM  Code  Verification"  form  are  returned  to  the  customer  for  final  verification. 

5.  Once  the  customer  has  notified  NEC  Electronics  Inc.  in  writing  that  the  code  is  verified,  and  has  provided  both  the 
mask  charge  payment  and  a  hard-copy  purchase  order,  work  begins  immediately  on  production  of  his  fjiPD8048Hs. 

Please  contact  your  local  Sales  Representative  for  assistance  with  all  ROM-based  product  orders. 


2-6 


NEC 


ROM  Code  Submission 


To  NEC  Electronics  Inc. 
252  Humboldt  Court 
Sunnyvale,  CA  94086 


Date- 


Attn    ROM-Based  Product  Administrator 


We  are  ready  to  place  our  purchase  order  for  our . 


. your . 


Customer  Part  Number  NEC  Part  Number 

submitting  Two  copies  of  the  ROM  Code  on  the  following  medium/media  (Please  check  all  applicable  boxes)- 


,  and  are 


□  UPD2716  □  uPD8741A  □  CP/M®  compatible  8"  single-density  floppy  disk 

□  UPD2732  □  uPD8748  □  Intel  ISIS-II  compatible  8"  single-density  floppy  disk 

□  UPD2764  □  UPD8749H  □  Intel  ISIS-II  compatible  8"  double-density  floppy  disk 

□  UPD27128  □  UPD8755A 


Please  manufacture  this  device  with  the  special  marking.. 


 ,  and  with  the  I/O  Port  Loading  Op- 
tions (available  only  on  the  jjPD7519,  UPD7527,  jjPD7528,  juPD7537,  /uPD7538,  UPD8021,  iuPD80C48,  and  UPD80C49, 
and  not  available  on  all  other  NEC  ROM-Based  Products)  selected  on  the  back  of  this  page 


The  mask  charge  payment  and  the  ROM  code  listing  are  also  enclosed 


Please  return  the  processed  ROM  code  to  the  following  individual  for  our  verification 


Company 


Shipping  Address  (not  a  P  O  Box  please) 


City 


Zip 


Telephone  Number 

Send  this  form  along  with  the  ROM  code,  a  listing,  and  the  mask  charge  payment,  in  a  package  clearly  marked  with  "ROM 
CODE  ENCLOSED"  to  the  attention  of  the  ROM-Based  Product  Administrator  at  the  address  above 


CP/M  is  a  registered  trademark  of  Digital  Research  Corp 


2-7 


Device 

Port 

I/O  Port  Loading  Option 

(JPD7519 

SO 

□ 

open  drain 

□ 

pui 

-down 

resistor  to  V  LOAd 

S1 

□ 

open  drain 

□ 

pul 

-down 

resistor  to  V  LOAD 

S2 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  LOAd 

S3 

□ 

open  drain 

□ 

pul 

-down 

resistor  to  V  LOad 

S4 

□ 

open  drain 

□ 

pul 

-down 

resistor  to  V  LOad 

S5 

□ 

open  drain 

□ 

pul 

-down 

resistor  to  V  LOad 

S6 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  LOad 

S7 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T8/S8 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T9/S9 

i — i 
U 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T10/S10 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T1 1 /S1 1 

D 

open  drain 

□ 

pul 

-down 

resistor  to  V  load 

T12/S12 

□ 

open  dram 

□ 

pull 

-down 

resistor  to  V  load 

T13/S13 

□ 

open  dram 

□ 

pull 

-down 

resistor  to  V  load 

T14/S14 

□ 

open  dram 

□ 

pull 

-down 

resistor  to  V  LOad 

T15/S15 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

TO 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T1 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

12 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T3 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

T4 

□ 

open  dram 

□ 

pull 

-down 

resistor  to  V  load 

T5 

□ 

open  dram 

□ 

pull 

-down 

resistor  to  V  load 

T6 

□ 

open  drain 

□ 

pull 

-down 

resistor  to  Vload 

T7 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

POo/INTo 

□ 

direct  connection 

□ 

zero-crossing  detector 

(no  zero-crossing  detector) 

P23-P2, 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P33-P30 

□ 

open  dram 

□ 

pui 

-down 

resistor  to  V  load 

P43-P40 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P53-P50 

n 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P80 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P81 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P82 

□ 

open  drain 

□ 

pul 

-down 

resistor  to  V  load 

P83 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

pPD7527 

P90 

i — i 
u 

open  dram 

i — i 
U 

pul 

-down 

resistor  to  VLoad 

juPD7528 

P9i 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

jUrU/oo/ 

P92 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

JUPD7538 

P93 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P100 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P10, 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P102 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P103 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P11o 

□ 

open  drain 

□ 

pul 

-down 

resistor  to  V  load 

P11i 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

P112 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

PH3 

□ 

open  dram 

□ 

pul 

-down 

resistor  to  V  load 

JUPD8021 

T1 

□ 

zero-crossing  detector 

□ 

TTL-compatible 

P00-P07 

□ 

open  dram 

□ 

TTL-compatible 

UPD80C48 

P10-P17 

□ 

CMOS  (-5uA) 

□ 

TTL-compatible  ( -  50uA) 

jjPD80C49 

P20-P23 

□ 

CMOS  (-5|jA) 

□ 

TTL-compatible  ( -  50uA) 

P24-P27 

□ 

CMOS  (-5pA) 

□ 

TTL-compatible  ( -  50uA) 

2-8 


SEC 


SINGLE  CHIP  4-BIT  MICROCOMPUTERS 


SEC 


fiCOM-4 


4-BIT  SINGLE  CHIP  MICROCOMPUTER  FAMILY 


DESCR IPTION  The  piCOM-4  4-bit  Microcomputer  Family  is  a  broad  product  line  of  14  individual 
devices  designed  to  fulfill  a  wide  variety  of  design  criteria.  The  product  line  shares  a 
compatible  architecture  and  instruction  set.  The  architecture  includes  all  functional 
blocks  necessary  for  a  single  chip  controller,  including  an  ALU,  Accumulator,  Byte- 
wide  ROM,  RAM,  and  Stack.  The  instruction  set  maximizes  the  efficient  utilization 
of  the  fixed  ROM  space,  and  includes  a  variety  of  Single  Bit  Manipulation,  Table 
Look-Up,  BCD  arithemetic,  and  Skip  instructions. 

The  juCOM-4  Microcomputer  Family  includes  seven  different  products  capable  of 
directly  driving  35V  Vacuum  Fluorescent  Displays.  Four  products  are  manufactured 
with  a  CMOS  process  technology.  juCOM-4  Microcomputers  are  ideal  for  low-cost 
general  purpose  controller  applications  such  as  industrial  controls,  instruments, 
appliance  controls,  intelligent  VF  display  drivers,  and  games. 

FEATURES  •  Choice  of  ROM  size:  2000  x  8, 1000  x  8,  or  640  x  8 

•  Choice  of  RAM  size:  96  x  4,  64  x  4,  or  32  x  4 

-  Six  4-Bit  Working  Registers  Available 

-  One  4-Bit  Flag  Register  Available 

•  Powerful  Instruction  Set 

-  Choice  of  80  or  58  Instructions 

-  Table  Look-Up  Capability  with  CZP  and  JPA  Instructions 

-  Single  Bit  Manipulation  of  RAM  or  I/O  Ports 

-  BCD  Arithmetic  Capability 

•  Choice  of  3-Level,  2-Level,  or  1 -Level  Subroutine  Stack 

•  Extensive  I/O  Capability 

-  Choice  of  35  or  21  I/O  Lines 

42/52-Pin  Packages  28-Pin  Package 

-  4-Bit  Input  Ports  2  1 

-  4-Bit  I/O  Ports  2  2 

-  4-Bit  Output  Ports  4  2 

-  3-Bit  Output  Ports  1  - 

-  1-Bit  Output  Port  - 


1 

Programmable  6-Bit  Timer  Available 
Choice  of  Hardware  or  Testable  Interrupt 
Built-in  Clock  Signal  Generation  Circuitry 
Built-in  Reset  Circuitry 
Single  Power  Supply 
Low  Power  Consumption 
PMOS  or  CMOS  Technologies 

Choice  of  42-pin  DIP,  28-pin  DIP,  or  52-pin  Flat  Plastic  Package 


3-1 


fiCOM-4 


Internal  Registers 

The  ALU,  the  Accumulator,  and  the  Carry  Flag  together  comprise  the  central  portion 
of  the  juCOM-4  Microcomputer  Family  architecture.  The  ALU  performs  the  arithmetic 
and  logical  operations  and  checks  for  various  results.  The  Accumulator  stores  the 
results  generated  by  the  ALU  and  acts  as  the  major  interface  point  between  the  RAM, 
the  I/O  ports,  and  the  Data  Pointer  registers.  The  Carry  F/F  can  be  addressed  directly, 
and  can  also  be  set  during  an  addition.  The  aiPD546,  mPD553,  juPD557L,  and  juPD650 
also  have  a  Carry  Save  F/F  for  storage  the  value  of  the  Carry  F/F. 

Data  Pointer  Registers 

The  DPh  register  and  4-bit  DP|_  register  reside  outside  the  RAM.  They  function  as  the 
Data  Pointer,  addressing  the  rows  and  columns  of  the  RAM,  respectively.  They  are 
individually  accessible  and  the  L  register  can  be  automatically  incremented  or 
decremented. 


RAM 

All  jl/COM-4  microcomputers  have  a  static  RAM  organized  into  a  multiple-row  by 
16-column  configuration,  as  follows: 


MICROCOMPUTER 

RAM 

ORGANIZATION 

DPH  DPL 

MPD546,  juPD553, 
HPD557L,  andjuPD650 

96  x  4 

6  rows  x  16  columns 

3  4 

mPD547,juPD547L 
AiPD552,and  juPD651 

64x4 

4  rows  x  16  columns 

2  4 

mPD550,mPD550L, 
mPD554,mPD554L, 
and  mPD652 

32  x  4 

2  rows  x  16  columns 

1  4 

The  /IPD546,  /iPD553,  /iPD557L,  and  /iPD650  also  have  a  4-bit  Flag  register  and  six 
4-bit  working  registers  resident  in  the  last  row  of  the  RAM.  Their  extended  instruction 
set  provides  10  additional  instructions  with  which  you  can  access  or  manipulate  these 
seven  registers. 

ROM 

The  ROM  is  the  mask-programmable  portion  of  the  £tCOM-4  Microcomputer  which 
stores  the  application  program.  It  is  organized  as  follows: 


MICROCOMPUTER 

ROM 

ORGANIZATION 

FIELDS 

PAGES 

mPD546,mPD553, 

2000  x  8 

8 

16 

MPD557L,  and  juPD650 

mPD547,mPD547L, 

1000  x  8 

8 

8 

kPD552,mPD651 

AiPD554.  MPD554L, 

1000x8 

8 

8 

and  MPD652 

MPD550  and/uPD550L 

640x8 

8 

8 

FUNCTIONAL 
DESCRIPTION 


3-2 


fiCOM-4 


FUNCTIONAL    Program  Counter  and  Stack  Register 

DESCRIPTION    The  Program  Counter  contains  the  address  of  a  particular  instruction  being  executed. 
(CONT.)     It  is  incremented  during  normal  operation,  but  can  be  modified  by  various  JUMP  and 
CALL  instructions.  The  Stack  Register  is  a  LIFO  push-down  stack  register  used  to  save 
the  value  of  the  Program  Counter  when  a  subroutine  is  called.  It  is  organized  as  follows: 


MICROCOMPUTER 

STACK 
ORGANIZATION 

ALLOWABLE 
SUBROUTINE  CALLS 

juPD546,  MPD553, 
MPD557L,  andjuPD650 

3  words  x  1 1  bits 

3  Levels 

MPD651 

2  words  x  10  bits 

2  Levels 

juPD547,juPD547L, 
and  mPD552 

1  word  x  10  bits 

1  Level 

juPD550,juPD550L, 
juPD554,juPD554L, 
and  juPD652 

1  word  x  10  bits 

1  Level 

Interrupts 

All  juCOM-4  microcomputers  are  equipped  with  a  software-testable  interrupt  which 
skips  an  instruction  if  the  Interrupt  F/F  has  been  set.  The  TIT  instruction  resets  the 
Interrupt  F/F. 

In  addition,  the  /iPD546,  juPD553,  MPD557L,  and  juPD650  have  a  level-triggered  hard- 
ware interrupt,  which  causes  an  automatic  stack  level  shift  and  interrupt  service  routine 
call  when  an  interrupt  occurs. 

Interval  Timer 

The  juPD546,  juPD553,  /iPD557L,  and  /iPD650  are  equipped  with  a  programmable 
6-bit  interval  timer  which  consists  of  a  6-bit  polynomial  counter  and  a  6-bit  binary 
down  counter.  The  STM  instruction  sets  the  initial  value  of  the  binary  down  counter 
and  starts  the  timing.  The  polynomial  counter  decrements  the  binary  down  counter 
when  63  instruction  cycles  have  been  completed.  When  the  binary  down  counter 
reaches  zero,  the  timer  F/F  is  set.  The  TTM  instruction  tests  the  timer  F/F,  and  skips 
the  next  instruction  if  it  is  set. 


Clock  and  Reset  Circuitry 

The  Clock  Circuitry  for  any  /iCOM-4  microcomputer  can  be  implemented  by  connect- 
ing either  an  Intermediate  Frequency  Transformer  (I FT)  and  a  capacitor,  or  a  Ceramic 
Resonator  and  two  capacitors,  to  the  CLrj  and  CLi  Inputs.  The  Power-On-Reset 
Circuitry  for  any  /iCOM-4  microcomputer  can  be  implemented  by  connecting  a 
Resistor,  a  Capacitor,  and  a  Diode  to  the  RESET  input. 


3-3 


fiCOM-4 


I/O  Capability 

The  juCOM-4  microcomputer  family  devices  have  either  35  or  21  I/O  lines,  depending 
upon  the  individual  device,  for  communication  with  and  control  of  external  circuitry 
They  are  organized  as  follows: 


PORT 

SYMBOL 

FUNCTION 

MPD546,  mPD547, 
MPD547L,  juPD552, 
juPD553,  juPD650, 
and  mPD651 

AtPD550,)uPD550L, 
juPD554  juPD554L 
MPD557L,  and  juPD652 

Port  A 

PA0-3 

4-Bit  Input 

• 

Port  B 

pB0-3 

4-Bit  Input 

• 

Port  C 

PCrj-3 

4-Bit  Input/Output 
(VF  Drive  Possible) 

• 

* 

Port  D 

pDfj-3 

•  4-Bit  Input/Output 
(VF  Drive  Possible) 

• 

* 

pp.  _ 
Kt0-3 

4-Bit  Output 

(VF  Drive  Possible) 

Port  F 

PFO-3 

4-Bit  Output 

(VF  Drive  Possible) 

• 

Port  G 

PGfj-3 

4-  Bit  Output 

(VF  Drive  Possible) 

• 

PGO-1 

1  -Bit  Output 

(VF  Drive  Possible) 

• 

Port  H 

PH0-3 

4-Bit  Output 

(VF  Drive  Possible) 

• 

Port  I 

P'0-2 

3-Bit  Output 

(VF  Drive  Possible) 

• 

Development  Tools 

The  NEC  Development  System  (NDS)  is  available  for  developing  software  service  code, 
editing,  and  assembling  source  code  into  object  code.  In  addition,  the  ASM-43  Cross 
Assembler  is  available  for  systems  which  support  either  the  Intel  ISIS-II  Operating 
System  or  the  CP/M  (®  Digital  Research  Corp.)  Operating  System. 

The  EVAKIT-43P  Evaluation  Board  is  available  for  production  device  emulation  and 
prototype  system  debugging.  The  SE-43P  Emulation  Board  is  available  for  demon- 
strating the  final  system  design.  The  juPD556B  ROM-less  Evaluation  Chip  is  available 
for  small  pilot  production. 


FUNCTIONAL 
DESCRIPTION 
(CONT.) 


3-4 


MPD546,  juPD553, 
juPD557L,  MPD650 
BLOCK  DIAGRAM 


fiCOM-4 


PAO-3    CZ=^>  A 


mPD547,mPD547L, 
/xPD552/iuPD651 
BLOCK  DIAGRAM 


Note    Block  diagram  above  applies  to  ;uPD546,  /iPD553,  and  mPD650  4-bit  microcomputers  The 
MPD557L  block  diagram  is  similar  to  the  above,  except  that  PBrj.3,  PG1.3,  PHo-3,  and 
Plfj-2  nave  been  eliminated  to  accommodate  the  juPD557L's  28-pin  package 


PC.  ,  <^>  C 
?&0  3  C=> 


3  ^ 


RAM 
DECODER 


CT1 


RAM 
64x  4 


UP  DOWN 
COUNTER 

n 


INSTRUCTION  BUS  8  BIT 


5 


L!=j  oph  £2 


RAM 
BUFFER 


I  O 

INTERFACE 


Q  BUS 
4  BIT 


CONTROL 

AND 
DECODE 


TV 


CLO  0 
CL1  « 


CLOCK 
GENERATOR 


ROM 
1000x  S 


IZSZ 


10-BIT 

PROGRAM  COUNTER 


INT 

F/F 

STACK  1 
(ajPD651  ONLY) 


INT  RES 


3-5 


|iC0M-4 


PG0     <J=  G  <$2 


pfq3  <Jzz  f  ^ZZZZZZ/ 


PEO-3  <=   E  $2 


pD0-3  <JZ>  D 


PCn  3   <Jz>  C 


/ 


/ 
/ 
/ 


RAM 
DECODER 


RAM 
32X4 


/7777 


juPD550,/;PD550L, 
MPD554,  MPD554L, 
juPD652 

BLOCK  DIAGRAM 


UP/DOWN 
COUNTER 


u. 


INSTRUCTION  BUS  8  BIT 


DPl 


777V> 


dph  <£ZZ 


RAM 
BUFFER 


I/O 

INTERFACE 


~  Qzzzzzzzzzzzz. 

 4  BIT 


#1  ^ 


Q-BUS 
4  BIT 


CONTROL 

AND 
DECODE 


7V 


ROM 

MPD550  ) 
WPD550L ' 

640  x  8 

mPD'554  J 

MPD554L 

1000  x  8 

,uPD652  ) 

10-BIT 

PROGRAM  COUNTER 


INT 

F/F 


CLO  « 
CLi  « 


CLOCK 
GENERATOR 


The  MPD546,  juPD553,/iPD557L,  and  juPD650  execute  all  80  instructions  of  the  INSTRUCTION  SET 

extended  juCOM-4  instruction  set.  The  22  additional  instructions  are  indicated  by 

shading. 

The  /ZPD547,  MPD547L,  fxPDbSO,  juPD550L,  juPD552,  juPD554,  juPD554L,  MPD651 , 
and  //PD652  execute  a  58  instruction  subset  of  the  juCOM-4  instruction  set. 


3-6 


jiCOM-4 


INSTRUCTION  SET 
SYMBOL  DEFINITIONS 


The  following  abbreviations  are  used  in  the  description  of  the  /uCOM-4  instruction  set: 


SYMBOL 

EXPLANATION  AND  USE 

Acc 

Accumulator 

AcCn 

Bit  "n"  of  Accumulator 

address 

Immediate  address 

C 

Carry  F/F 

C 

Carry  Save  F/F 

data 

Immediate  data 

Dn 

Bit  "n"  of  immediate  data  or  immediate  address 

DP 

Data  Pointer 

DPh 

Upper  Bits  of  Data  Pointer 

DPl 

Lower  4  Bits  of  Data  Pointer 

FLAG 

FLAG  Register 

INTE  F/F 

Interrupt  Enable  F/F 

INT  F/F 

Interrupt  F/F 

P(  ) 

Parallel  Input/Output  Port  addressed  by  the  value  within  the  brackets 

Pn 

Bit  "n"  of  Program  Counter 

PA 

Input  Port  A 

PC 

Input/Output  Port  C 

PD 

Inout/Outout  Port  D 

PE 

Output  Port  E 

R 

R  Register 

s 

S  Register 

SKIP 

Number  of  Bytes  in  next  instruction  when  skip  condition  occurs 

STACK 

Stack  Register 

TC 

6-Bit  Binary  Down  Timer  Counter 

TIMER  F/F 

Timer  F/F 

W 

W  Register 

X 

X  Register 

Y 

Y  Register 

Z 

Z  Register 

(  ) 

The  contents  of  RAM  addressed  by  the  value  within  the  brackets 

[  ] 

The  contents  of  ROM  addressed  by  the  value  within  the  brackets 

«- 

Load,  Store,  or  Transfer 

«•» 

Exchange 

Complement 

V 

LOGICAL  EXCLUSIVE  OR 

Applies  to  juPD546,  AiPD553,  juPD556B,  juPD557 L,  and  juPD650  only 

3-7 


fiCOM-4 


INSTRUCTION  SET 


INSTRUCTION  CODE 

SKIP 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7 

D6 

D5 

D4 

D3 

D2 

01 

D0 

BYTES 

CYCLES 

CONDITION 

LOAD 

LI  data 

Aqq  D3^) 

Load  Acc  with  4  bits  of  imme- 
diate data;  execute  succeeding 
LI  instructions  as  NOP 
instructions 

1 

0 

o 

1 

D3 

D2 

D1 

D0 

1 

1 

String 

L 

ACC  -  (DP) 

Load  Acc  with  the  RAM  contents 
addressed  by  DP 

0 

0 

1 

1 

1 

0 

0 

0 

1 

1 

LM  data 

ACC«-(DP) 
DPH-DPH  V  Di4> 

Load  Aqc  with  tne  RAM  contents 
addressed  by  DP;  Perform  a 
LOGICAL  EXCLUSIVE-OR 
Between  DPh  and  2  bits  of 
Immediate  Data,  Store  the  result 
in  DPh 

0 

0 

1 

1 

1 

0 

D1 

D0 

1 

1 

LOI  data 

DP  -  De-0 

Load  DP  with  7  bits  of  immediate 
data 

0 
0 

0 

D6 

0 

D5 

1 

D4 

0 

D3 

1 

D2 

0 

D1 

1 

D0 

2 

2 

LDZ  data 

DPh-0 
DPL«-D3.0 

Load  DPh  with  0, 
Load  DPl  with  4  bits  of 
immediate  data 

1 

0 

0 

0 

D3 

D2 

D1 

DO 

1 

1 

STORE 

S 

<DP)-ACC 

Store  Acc  m*0  the  RAM  location 
addressed  by  DP 

0 

0 

0 

0 

0 

1 

0 

0 

1 

1 

TRANSFER 

TAL 

DPL<-ACC 

Transfer  Acc  to  °Pl 

0 

0 

0 

0 

0 

1 

1 

1 

1 

TLA 

ACC  -  dpl 

Transfer  DPl  to  Acc 

0 

0 

0 

1 

0 

0 

0 



1 

1 

TAW 

Transfer  Acc  «*  W 

HI 

111 

0 

111 

■ill 

0 

HHi 

HHl 

TAZ 

Transfer  Aqc  to  Z 

0 

1 

o 

0 

0 

0 

0 

1 

2 

THX 

x<~oph 

Transfer  CH»h  to  X 

Q 

1 

0 

0 

0 

t 

1 

t 

2 

TtY 

Transfer  DP^  to  V 

0 

1 

0 

0 

0 

1 

0 

t 

2 

EXCHANGE 

X 

ACc«*(DP) 

Exchange  A  with  the  RAM  con- 
tents addressed  by  DP 

0 

0 

1 

0 

1 

0 

0 

0 

1 

1 

XI 

Acc-(DP) 
DPL<-DPL  +  1 
Skip  if  DPL  =  OH 

Exchange  Aqc  with  RAM  con- 
tents addressed  by  DP,  increment 
DPl,  Skip  if  DPL  =  0H 

0 

0 

1 

1 

1 

1 

0 

0 

1 

1  +S 

DPL  =  0H 

XD 

ACc**  (DP) 
DPL"-DPL-  1 
Skip  if  DPl=  FH 

Exchange  Acc  with  tne  RAM 
contents  addressed  by  DP, 
decrement  DPl,  Skip  if  DPl  =  FH 

0 

0 

1 

0 

1 

1 

0 

0 

1 

1  +S 

DPl  =  FH 

XM  data 

Acc-(DP) 

DPh  *-  DPh  V  D1.0 

Exchange  Acc  with  the  RAM 
contents  addressed  by  DP,  Per- 
form a  LOGICAL  EXCLUSIVE- 
OR  Between  DPh  and  2  bits  of 
immediate  data,  store  the  results 
in  DPh 

0 

0 

1 

0 

1 

0 

D1 

D0 

1 

1 

X Ml  data 

Ace*-  (DP) 
DPh-DPh  V 
DPL-DPL+  1 
Skip  if  DPl  =  OH 

Exchange  Acc  with  the  RAM 
contents  addressed  by  DP,  Per- 
form a  LOGICAL  EXCLUSIVE- 
OR  Between  DPh  and  2  bits  of 
immediate  data,  store  the  results 
in  DPh  increment  DPl,  Skip  if 
DPL  =  0H 

0 

0 

1 

1 

1 

1 

D1 

DO 

1 

1  +s 

DP  i_  =  OH 

XMD  data 

ACC~<DP) 
DPH -DPH  V  D^ 
DPl-DPl-  1 
Skip  if  DPl  =  FH 

Exchange  Acc  with  the  RAM 
contents  addressed  by  DP,  Per- 
form a  LOGICAL  EXCLUSIVE- 
OR  Between  DPh  and  2  bits  of 
immediate  data,  store  the  results 
in  DPh  decrement  DPl,  Skip  if 
DPl  »  FH 

0 

0 

1 

0 

1 

1 

D1 

D0 

1 

1  +s 

DPl  =  FH 

XAW 

Exchange  Acc  w'th  w 

0 

111 

0 

Illlll 

111 

HHl 

XAZ 

Exchanqe  Acc  w'th  Z 

0 

0 

0 

9 

1 

0 

2 

XHfl 

DPh**  B 

Exchange  DPh  with  R 

0 

0 

0 

1 

0 

1 

2 

XHX 

dph~* 

Exchange  DPh  with  X 

0 

0 

0 

1 

1 

1 

2 

XLS 

OPt.**S  Register 

Exchange  DP^  with  $  Register 

0 

0 

0 

1 

0 

0 

2 

XLY 

DPL  »  V 

Exchange  DP*,  w»th  Y 

0 

0 

0 

1 

i 

0 

2 

XC 

Exchange  Carry  F/F  with 
Carry  Saw  fff 

0 

0 

0 

0 

1 

0 

1 

3-8 


INSTRUCTION  SET 
(CONT.) 


jiCOM-4 


INSTRUCTION  CODE 

SKIP 
CONDITION 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7 

D6 

D5 

D4 

03 

02 

01 

DO 

BYTES 

CYCLES 

ARITHMETIC 

AD 

AcC"  Acc+  (DP) 

Add  the  RAM  contents  addressed 
generated 

0 

0 

0 

0 

1 

0 

0 

0 

1 

1  +S 

Overflow 

ADC 

ACC*-Acc+(DP>  +  C 
if  overflow  occurs, 
C-1 

Add  the  RAM  contents  addressed 
by  DP,  and  the  Carry  F/F  to  Acc; 
if  overflow  occurs,  set  carry  F/F 

0 

0 

0 

1 

1 

0 

0 

1 

1 

1 

ADS 

Acc-Acc  +  IDPJ  +  C 
if  overflow  occurs, 
C    1  and  skip 

Add  the  RAM  contents  addressed 
by  DP  and  the  carry  F/F  to  Acc< 
if  overflow  occurs,  set  Carry  F/F 
and  skip 

0 

0 

0 

0 

1 

0 

0 

1 

1 

1  +s 

Overflow 

DAA 

AcC*-ACc  +  6 

Add  6  to  Acc  to  Adjust 
Decimal  for  BCD  Addition 

0 

0 

0 

0 

0 

1 

1 

0 

1 

1 

DAS 

Acc^- Acc  +  10 

Add  10  to  Acc  to  Adjust 
Decimal  for  BCD  Subtraction 

0 

0 

0 

0 

1 

0 

1 

0 

1 

1 

LOGICAL 

EXL 

ACC  -  ACC  V  (DP) 

Perform  a  LOGICAL 
EXCLUSIVE-OR  between  the 
RAM  contents  addressed  by  DP 
and  Acc.  store  the  result  in  Acc 

0 

0 

0 

1 

1 

0 

0 

0 

1 

1 

ACCUMULATOR 

CLA 

ACC^0 

Clear  Acc  to  zero 

1 

0 

0 

1 

0 

0 

0 

0 

1 

1 

String 

CM  A 

ACC-  ACC 

Complement  Acc 

0 

0 

0 

1 

0 

0 

0 

0 

1 

1 

CIA 

ACC  -  ACC  +  1 

ComDlement  A.  Increment  A 

0 

0 

0 

1 

0 

0 

0 

1 

1 

1 

RAFt 

C~AcCgf»*t**3* 

Rotate  A(X  r&nt  through 
Carry  F/P 

,  0 

a 

Will. 

-1 

0 

0 

'J  1  -  ' 

CARRY  FLAG 

CLC 

C-0 

Reset  Carry  F/F  to  zero 

0 

0 

0 

0 

1 

0 

1 

1 

1 

1 

STC 

C-1 

Set  Carry  F/F  to  one 

0 

0 

0 

1 

1 

0 

1 

1 

1 

1 

TC 

Skip  if  C  =  1 

Skip  if  Carry  F/F  is  true 

0 

0 

0 

0 

0 

1 

0 

0 

1 

1  +s 

C-1 

FLAG 

SF8 

FLAGftfe-l 

SetasmgtebMderotedby  O^l 
.  of  FLAG  Register  toon* 

0 

ilii 

llll 

ill 

llll 

■\K 

RFB 

Reset  *  single  Wt  <efcnote«J  by 
END©)  of  FLAG  Register  to  mo 

p; , 

1  ; 

t 

r  1  '; 

*: 

;,  ~  sr.;.  ; 

FBT 

9M0tr  FUW3t»it*1 

Skip  if  »  strtgte  bit  (denoted  by 
Ol  Do)  of  m  Ft  AG  Reufcter  is  . 

o. 

1 

t 

'«   t  • 

f' 

"  V 

FBF 

SkH»»f  FLAG^*© 

Skip  if  a  single  bit  (denoted  by 
OlD0)  of  m  FLAG  Register  * 

0 

"1: 

o 

Jiw; 

'  1  ' 

INCREMENT  AND  DECREMENT 

INC 

ACC     ACC  +  1 
Skip  if  overflow 

Increment  A;  Skip  if  overflow 
is  generated 

0 

0 

0 

0 

1 

1 

0 

1 

1 

1  +S 

Overflow 

DEC 

ACC  *~  ACC  -  1 
Skip  if  underflow 

Decrement  A,  Skip  if  underflow 
occurs 

0 

0 

0 

0 

1 

1 

1 

1 

1 

1  +s 

Underflow 

IND 

DPL-DPL+  1 
Skip  if  DP|_  =  0H 

Increment  DPi_, 
Skip  if  DP|_  =  0H 

0 

0 

1 

1 

0 

0 

1 

1 

1 

1  +s 

DP|_  -  OH 

DED 

DPL-DPL-  1 
Skip  if  DPL=  FH 

Decrement  DPt_, 
Skip  if  DPl  =  FH 

0 

0 

0 

1 

0 

0 

1 

1 

1 

1  +s 

DPL=  FH 

fNM 

IDP)  -  (DP)  +  J 
Skfptf  (DPI  =OH 

increment  the  RAM  contents 
addressed  by  DP ;  Skip  if  the  .  - 
contents  *  OH 

0 

111 

0 

111 

lllll 

''t 

0 

t  ' 

lllllllllllll 

\m*m  * . 

(DP)  *-  (DW  -  1 
Skip  if  itm  *  FM 

Decrement  tlw  RAM  contents 
addressed  by  DP;  skip  if  the 
contents  *  FH 

0 

0 

1 

t 

1 

1 

.  1  ■ 

i 

K*|«F»  • 

3-9 


/iCOM-4 


INSTRUCTION  SET 
(CONT.) 


INSTRUCTION  CODE 

SKIP 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7 

D5 

D4 

03 

D2 

D1 

D0 

BYTES 

CYCLES 

CONDITION 

BIT  MANIPULATION 

RMB  data 

<DP)bit<-0 

Reset  a  single  bit  (denoted  by 
D1-D0)  of  RAM  at  the  location 
addressed  by  DP  to  zero 

0 

1 

1 

0 

1 

0 

01 

Do 

1 

1 

SMB  data 

(DP)bn  *~ 1 

Set  a  single  bit  (denoted  by  D-|Drj) 
of  RAM  at  the  location  addressed 
by  DP  to  one 

0 

1 

1 

1 

1 

0 

D1 

Do 

1 

1 

REBdata 

PEb.t-0 

Reset  a  single  bit  (denoted  by 
D1  Do)  of  output  Port  E  to  zero 

0 

1 

1 

0 

0 

1 

D1 

D0 

2 

SEBdata 

PEb.t  -  1 

Set  a  single  bit  (denoted  by  D1  Do) 
of  output  Port  E  to  one 

0 

1 

1 

1 

0 

1 

01 

DO 

2 

RPBdata 

P(DPL)blt-0 

Reset  a  single  bit  (denoted  by 
D1  Do)  of  the  output  port 
addressed  by  DPl  to  zero 

0 

1 

1 

0 

0 

0 

D1 

D0 

1 

SPB  data 

P(DPL)b,t«-1 

Set  a  single  bit  (denoted  by  D1  Do) 
of  the  output  port  addressed  by 
DPL 

0 

1 

1 

1 

0 

0 

D1 

D0 

1 

1 

JUMP,  CALL  AND  RETURN 

JMP  address 

P10-0-D10-0 

Jump  to  the  address  specified  by 
1 1  bits  of  immediate  data 

1 

D7 

0 

D6 

1 

D5 

0 

D4 

0 

03 

D10 

D2 

D9 
Dl 

D8 
D0 

2 

2 

JCP  address 

P5-0  -  D5.0 

Jump  to  the  address  within  the 
current  ROM  page  specified  by 
6  bits  of  immediate  data 

1 

1 

D5 

D4 

D3 

D2 

01 

D0 

1 

1 

JPA 

P5-2  -  ACC 
P^-00 

Jump  to  the  address  within  the 
current  ROM  page  modified  by 
ACC 

0 

1 

0 

0 

0 

0 

0 

1 

1 

2 

CAL  address 

Stack  <-  P  +  2 
p10-0-Dio-0 

Store  a  return  address  (P  +  2)  in 
the  stack,  call  the  subroutine  pro- 
gram at  the  location  specified  by 
1 1  bits  of  immediate  data 

1 

D7 

0 

06 

1 

D5 

0 

D4 

1 

03 

D10 
D2 

D9 
Dl 

08 
D0 

2 

2 

CZP  address 

Stack  *-  P  +  1 
Pl0-6-0°°°0 
P5-2  -  D30 
P1.O+-00 

Store  a  return  address  (P  +  1 )  in 
the  stack,  call  the  subroutine  pro- 
gram at  one  of  sixteen  locations  in 
Page  0  of  Field  0,  specified  by  4 
bits  of  immediate  data 

1 

0 

1 

D3 

D2 

Dl 

DO 

1 

1 

RT 

P  *-  Stack 

Return  from  Subroutine 

0 

1 

0 

0 

1 

0 

0 

0 

1 

2 

RTS 

P  -  Stack 

Skip  unconditionally 

Return  from  Subroutine,  skip 
unconditionally 

0 

1 

0 

0 

1 

0 

0 

1 

1 

2  +  S 

Unconditional 

SKIP 

CI  data 

Skip  if  Aqc  =  D3-0 

Skip  if  Acc  equals  4  bits  of 
immediate  data 

0 

1 

0 

1 

0 
0 

0 

0 

D3 

1 

D2 

1 

D1 

1 

D0 

2 

2  +  S 

ACC  ~  O3-0 

CM 

Skip  if  ACC  =  (DP) 

Skip  if  Acc  equals  the  RAM 
contents  addressed  by  DP 

0 

0 

0 

0 

1 

0 

0 

1  +S 

ACC  =  <DP) 

CMB  data 

Skip  ,f  ACCb|t  =  (DP)b,t 

Skip  if  the  single  bit  (denoted  by 
D1  Dq)  of  Acc- ,s  eP"3' to  tne 
single  bit  (also  denoted  by  D1  Do) 
of  RAM  addressed  by  DP 

0 

0 

1 

1 

0 

1 

01 

D0 

1 

1  +S 

ACCblt  =  <DP>b,t 

TAB  data 

Skip  if  ACcblt  «  1 

Skip  if  the  single  bit  (denoted  by 
D1D0)  of  Acc  <s  true 

0 

0 

1 

0 

0 

1 

Dl 

D0 

1 

1  +  S 

Accblt  - 1 

CLI  data 

Skip  tf  DPL=  D34 

Skip  if  DP|_  equals  4  bits  of 
immediate  data 

0 

1 

0 

1 

0 

1 

1 
0 

0 

D3 

1 

D2 

1 

01 

0 

D0 

2 

2  +  S 

DPL  =  D3.0 

TMB  data 

Skip  if  (DP)blt  =  1 

Skip  if  the  single  bit  (denoted  by 
D1  Do)  of  the  RAM  location 
addressed  by  DP  is  true 

0 

1 

0 

1 

1 

0 

Dl 

D0 

1  +S 

(DP)blt  =  1 

TPA  data 

Skip  if  PAbit  =  1 

Skip  if  the  single  bit  (denoted  by 
D1D0)  of  Port  A  is  true 

0 

1 

0 

0 

1 

01 

D0 

2  +  S 

PAb.t  =  1 

TPB  data 

Skip  if  P(DPL)b|t  =  1 

Skip  if  the  single  bit  (denoted  by 
D-|Do)  of  the  input  Port 
addressed  by  DP|_  is  true 

0 

1 

0 

1 

0 

0 

Dl 

DO 

1 

1  +  S 

P(DPL)b)t  =  1 

STM 

TIMER  F/F  «-0 
HHHHH 

Re$et  Turner  F/F  to  zero.  Load 
Timer  Count <r-with  6  bits  of 
immediate  data;  Start  timer 

0 
1 

0 

iff  111* 

0 
D5 

IBi 

0 

D3 

1 

D2 

0 

0 

llli 

2 

2 

TTM 

•  8kip*fTWEfi  F/f  *  1 

Skip  tf  Timer  fVF  is  true 

0 

0 

0 

0 

1 

0 

1 

1      |      t  +S 

TIMEB  Pif  •  1 

3-10 


pCOM-4 


INSTRUCTION  SET 
(CONT.) 


INSTRUCTION  CODE 

SKIP 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D6 

D5 

D4 

D3  D2 

D1 

DO 

BYTES 

CYCLES 

CONDITION 

INTERRUPT 

TIT 

Skip  if  INT  F/F  =  1 

Skip  if  Interrupt  F/F  is  true, 
Reset  Interrupt  F/F 

0 

0 

0 

0 

0  0 

1 

1 

1 

1  +S 

INT  F/F  =  1 

,, 

<v 

MB 

Bllli 

■M 

TT  

:K##eW  ^./.- :.  * 

8 

■1 

PARALLEL  I/O 

IA 

ACC  -  PA 

Input  Port  A  to  Acc 

0 

1 

0 

0 

0  0 

0 

0 

1 

2 

IP 

ACC<-P<DP|_) 

Input  the  Port  addressed  by 
DPLto  ACc 

0 

0 

1 

1 

0  0 

1 

0 

1 

1 

OE 

PE-Acc 

Output  Acc  to  Port  E 

0 

1 

0 

0 

0  1 

0 

0 

1 

2 

OP 

P(DPL)*-ACC 

Output  Acc  to  tne  P°rt 
addressed  by  DPl 

0 

0 

0 

0 

1  1 

1 

0 

1 

1 

OCD 

P02-0  *■ 
PC3.0  -  D3_o 

Output  8  bits  of  immediate 
data  to  Ports  C  and  D 

0 

D7 

0 

D6 

0 

D5 

1 

D4 

1  1 

D3  D2 

1 

D1 

0 

D0 

2 

2 

CPU  CONTROL 

NOP 

Perform  no  operation,  con- 
sume one  machine  cycle 

0 

0 

0 

0 

0  0 

0 

0 

1 

1 

3-11 


pCOM-4 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  fxCOM-4C 
Plastic  Miniflat,  |xC0M-4G 


MCOM4DS-2-82-CAT 

3-12 


SEC 


ftPD557L 


DESCRIPTION 


PIN  CONFIGURATION 


4-BIT  SINGLE  CHIP  MICROCOMPUTER  WITH 
VACUUM  FLUORESCENT  DISPLAY  DRIVE 
CAPABILITY 

The  MPD557L  is  a  4-bit  single  chip  microcomputer  which  has  the  same  architecture  as 
the  /JPD553,  but  is  pin-compatible  with  the  MPD550L  and  the  juPD554L.  The  MPD557L 
contains  a  2000  x  8-bit  ROM  and  a  96  x  4-bit  RAM,  which  includes  six  working  regis- 
ters and  the  FLAG  register.  It  has  a  lever-triggered  hardware  interrupt  input  INT,  a 
three-level  stack  and  a  6-bit  programmable  timer.  The  jUPD557L  provides  21  I/O  lines 
orgamzed  into  the  4-bit  input  port  A,  the  4-b.t  I/O  ports  C  and  D,  and  the  4-bit  output 
ports  E  and  F,  and  the  1-bit  output  port  G.  The  17  I/O  ports  and  output  ports  are 
capable  of  being  pulled  to  -35V  in  order  to  drive  Vacuum  Fluorescent  Displays  directly. 
The  //PD557L  typically  executes  all  80  instructions  of  the  extended  /LtCOM-4  family 
instruction  set  with  a  25  fis  instruction  cycle  time.  It  is  manufactured  with  a  modified 
PMOS  process,  allowing  use  of  a  single  -8V  power  supply  and  is  available  in  a  28-pin 
dual-in-line  plastic  package. 

The  //PD550L  and  the^PD554L  are  upward-compatible  with  thejuPD557L. 

PIN  NAMES 


PA0-PA3 

Input  Port  A 

PC0-PC3 

Input/Output  Port  C 

PD0-PD3 

Input/Output  Port  D 

PE0-PE3 

Output  Port  E 

PF0-PF3 

Output  Port  F 

PG0 

Output  Port  G 

Tnt 

Interrupt  Input 

CLq-CLt 

External  Clock  Signals 

RESET 

Reset 

vgg 

Power  Supply  Negative 

vSs 

Power  Supply  Positive 

TEST 

Factory  Test  Pin 
(Connect  to  V$s) 

ABSOLUTE  MAXIMUM    Operating  Temperature  -10°Cto+70°C 

RATINGS*    Storage  Temperature   -40°C  to  +125°C 

Supply  Voltage,  VGG  ■   -15to+0.3V 

Input  Voltages  (Port  A,  INT,  RESET)  -15to+0.3V 

(Ports  C,  D)  -40to+0.3V 

Output  Voltages  -40to+0.3V 

Output  Current  (Ports  C,  D,  each  bit)   -4  mA 

(Ports  E,  F,  G,  each  bit)   -25  mA 

(Total,  all  ports)   -100  mA 


Ta  =  25°C 

*COMMENT  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


Rev/1 

3-13 


/1PD557L 


t3  - -iof c to  +70°c.  vGG  -8.0V  ±  10%  Dc  CHAR ACTE R ISTI CS 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Voltage  High 

VIH 

0 

-2.5 

V 

Ports  A,  C,  D,  INT,  RESET. 

Input  Voltage  Low 

v.Ll 

-6.5 

VGG 

V 

Ports  A,  INT,  RESET 

V|L2 

-6.5 

-35 

V 

Ports  C,  D 

Clock  Voltage  High 

V0H 

0 

-0.6 

V 

CLo  Input,  External  Clock 

Clock  Voltage  Low 

V0L 

-5.0 

VGG 

V 

CLo  Input,  External  Clock 

Input  Leakage  Current  High 

'lih 

+10 

ma 

Ports  A,  C,  D,  INT,  RESET 
V|  =-1V 

Input  Leakage  Current  Low 

>LILi 

-10 

ma 

Ports  A,  C,D,  INT,  RESET 
V  |  = -9V 

'LIL2 

-30 

juA 

Ports  C,  D,  V|  =  -35V 

Clock  Input  Leakage  Current  High 

'L0H 

+200 

MA 

CL0  Input,  V0H  =  0V 

Clock  Input  Leakage  Current  Low 

I  i_0L 

-200 

ma 

CLo  Input,  V<£L  =  -9V 

Output  Voltage  High 

Vrvu 

-1.0 

v 

Ports  C  through  G, 
Iqh  =~2  mA 

V0H2 

-4.0 

V 

Ports  E,  F,  G,  Iqh  =  ~20  mA 

Output  Leakage  Current  Low 

'LOLt 

-10 

ma 

Ports  C  through  G, 
V0  =  -9V 

'lol2 

-30 

ma 

Ports  C  through  G, 
V0  =-35V 

Supply  Current 

•gg 

-20 

-36 

mA 

CAPACITANCE 


LIMITS 

TEST 

PARAMETER 

SYMBOL 

MIN 

TYP 

MAX 

UNIT 

CONDITIONS 

Input  Capacitance 

C| 

15 

PF 

Output  Capacitance 

c0 

15 

PF 

f  =  1  MHz 

Input/Output  Capacitance 

C|0 

15 

PF 

Ta  =  -10°C  to  +70°C,  Vqg  =  -8.0V 

±  10% 

LIMITS 

TEST 

PARAMETER 

SYMBOL 

MIN 

TYP 

MAX 

UNIT 

CONDITIONS 

Oscillator  Frequency 

f 

100 

180 

kHz 

Rise  and  Fall  Times 

tr-tf 

0 

0.3 

MS 

Clock  Pulse  Width  High 

VWh 

2.0 

8.0 

MS 

External  Clock 

Clock  Pulse  Width  Low 

t0WL 

2.0 

8.0 

MS 

AC  CHARACTERISTICS 


CLOCK  WAVEFORM 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 


Plastic,  |xPD557LC 

Plastic  Shrinkdip,  jaPD557LCT 


3-14 


557LDS-REV  1-2-82-CAT 


NEC 


MPD552 
jiPD553 


4-BIT  SINGLE  CHIP  MICROCOMPUTERS  WITH 
VACUUM  FLUORESCENT  DISPLAY  DRIVE 
CAPABILITY 


DESCRIPTION 


PIN  CONFIGURATION 


ABSOLUTE  MAXIMUM 
RATINGS* 


The  juPD552  and  the  juPD553  are  pin-compatible  4-bit  single  chip  microcomputers 
which  have  similar  architectures. 

The  jiiPD552  contains  a  1000  x  8-bit  ROM  and  a  64  x  4-bit  RAM.  It  has  a  testable 
interrupt  input  INT,  a  single-level  stack,  and  executes  all  58  instructions  of  the 
/iCOM-4  family  instruction  set.  The  jiiPD552  is  upward  compatible  with  the  juPD553. 

The  MPD553  contains  a  2000J,x  8-bit  ROM,  and  a  96  x  4-bit  RAM  which  includes  six 
working  registers  and  the  Flag  register.  It  has  a  level-triggered  hardware  interrupt,  a 
three-level  stack,  and  a  programmable  6-bit  Timer.  The  juPD553  executes  all  80 
instructions  of  the  extended  juCOM-4  family  instruction  set. 

Both  the  /iPD552  and  the  juPD553  provide  35  I/O  lines  organized  into  the  4-bit  input 
Ports  A  and  B,  the  4-bit  I/O  Ports  C  and  D,  the  4-bit  output  Ports  E,  F,  G,  and  H,  and 
the  3-bit  output  Port  I.  The  27  I/O  ports  and  output  ports  are  capable  of  being  pulled 
to  -35V  in  order  to  drive  Vacuum  Fluorescent  Displays  directly.  Both  devices  typically 
execute  their  instructions  with  a  10  jus  instruction  cycle  time.  The  juPD552  and  the 
juPD553  are  manufactured  with  a  standard  PMOS  process,  allowing  use  of  a  single 
-10V  power  supply,  and  are  available  in  a  42-pin  dual-in-line  plastic  package. 

PIN  NAMES 


CLi  C 
PCfjC 
PCiC 
PC2C 
PC3C 

untt  c 

RESET C 

PDnC  8 

PDiC  9 
PD2C  10 
PD3C  11 
PEOC  12 
PEhC  13 
PE2C  14 
PE3C  15 
PFoC  16 
PF1C17 
PF2  C  18 
PF3  □  19 
TEST  C  20 
VSSC  21 


juPD 
552/ 
553 


42DCL0 

41  3VGG 
40DPB3 
39  □  PB2 
38IIPB1 
37  □  PB0 
36  □  PA3 
35  □  PA2 
34  □  PA1 
33  □  PArj 
32  □  Pl2 
31  UPh 
30  □  Pl0 
29  □  PH3 
28  IJPH2 
27  H  PH1 
26lPH0 
25  □  PG3 
24  □  PG2 
23DPG1 
22  □  PG0 


PA0-PA3 

Input  Port  A 

PB0-PB3 

Input  Port  B 

PC0-PC3 

Input/Output  Port  C 

PD0-PD3 

Input/Output  Port  D 

PE0-PE3 

Output  Port  E 

PF0-PF3 

Output  Port  F 

PG0-PG3 

Output  Port  G 

PH0-PH3 

Output  Port  H 

PI0-PI2 

Output  Port  I 

INT 

Interrupt  Input 

CL0-CL1 

External  Clock  Signals 

RESET 

Reset 

vgg 

Power  Supply  Negative 

vss 

Power  Supply  Positive 

TEST 

Factory  Test  Pin 
(Connect  to  Vss) 

Operating  Temperature  -10  C  to +70  C 

Storage  Temperature  -40  C  to  +125  C 

Supply  Voltage,  Vqg  -15to+0.3V 

Input  Voltages  (Port  A,  B,  INT,  RESET)  -15to+0.3V 

(Ports  C,  D)  -40to+0.3V 

Output  Voltages  -40  to  +0.3V 

Output  Current  (Ports  C  through  I,  each  bit)  - 1 2  m A 

(Total,  all  ports)  -60  m A 

Ta  =  25°C 

♦COMMENT  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


3-15 


MPD552/553 

Ta  =  -10°C  to  +70°C,  VGG  =  -10V  ± 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Voltage  High 

V|H 

0 

-3  5 

V 

Ports  A  through  D,  INT, 
RESET 

Input  Voltage  Low 

V1L1 
"-1 

-7  5 

VGG 

V 

Ports  A,  B,  INT,  RESET 

V|L2 

-7  5 

-35 

,  V 

Ports  C,  D 

Clock  Voltage  High 

V0H 

_08_ 

V 

CLfj  Input,  External  Clock 

Clock  Voltage  Low 

V</>L 

VGG 

CLo  Input,  External  Clock 

Input  Leakage  Current  High 

'LIH 

+10 

ma 

Ports  A  through  D  INT 
RESET,  V|  =  -1V 

Input  Leakage  Current  Low 

>LILi 

-10 

MA 

Ports  A  through  D,  INT, 
RESET,  V|  =  -11V 

'lil2 

-30 

HA 

Ports  C,  D,  V,  =-35V 

Clock  Input  Leakage  Current  High 

>L0H 

+200 

MA 

CL0  Input,  V^h  =  0V 

Clock  Input  Leakage  Current  Low 

>L0L 

-200 

ma 

CL0  Input,  V0L  = -11V 

Output  Voltage  High 

V0H 

V 

Ports  C  through  I, 
'OH  =  ~*8  mA 

Output  Leakage  Current  Low 

"LOLt 

-10 

ma 

Ports  C  through  I, 
V0  =  -11V 

'lol2 

-30 

ma 

Ports  C  through  I, 
V0=-35V 

Supply  Current 

•gg 

-30 

-50 

mA 

DC  CHARACTERISTICS 


Ta  =  25° C 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

C| 

15 

pF 

f  =  1  MHz 

Output  Capacitance 

CO 

15 

PF 

Input/Output  Capacitance 

ClO 

15 

PF 

CAPACITANCE 


Ta  =  -io°cto+7o°c,VGG  =  -iov±io%  AC  CHARACTERISTICS 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Oscillator  Frequency 

f 

150 

440 

KHz 

Rise  and  Fall  Times 

tr.  tf 

0 

03 

MS 

EXTERNAL  CLOCK 

Clock  Pulse  Width  High 

VwH 

05 

5.6 

MS 

Clock  Pulse  Width  Low 

0.5 

56 

MS 

CLOCK  WAVEFORM 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 


Plastic,  |xPD552C/553C 


3-16 


552/553DS-2-82-CAT 


SEC 


fiPD550 
fiPD554 


DESCRIPTION 


PIN  CONFIGURATION 


4-BIT  SINGLE  CHIP  MICROCOMPUTERS  WITH 
VACUUM  FLUORESCENT  DISPLAY  DRIVE 
CAPABILITY 

The  juPD550  and  the  //PD554  are  pin-compatible  4-bit  single  chip  microcomputers 
which  have  the  same  architecture.  The  only  difference  between  them  is  that  the 
MPD550  contains  a  640  x  8-bit  ROM,  whereas  the  juPD554  contains  a  1000  x  8-bit 
ROM.  Both  devices  have  a  32  x  4-bit  RAM,  a  testable  interrupt  input  INT,  and  a 
single-level  stack.  The  /uPD550  and  the  juPD554  provide  21  I/O  lines  organized  into* 
the  4-bit  input  port  A,  the  4-bit  I/O  ports  C  and  D,  the  4-bit  output  ports  E  and  F, 
and  the  1-bit  output  port  G.  The  17  I/O  ports  and  output  ports  are  capable  of  being 
pulled  to  -35V  in  order  to  drive  Vacuum  Fluorescent  Displays  directly.  The  juPD550 
and  the  juPD554  typically  execute  all  58  instructions  of  the  jiiCOM-4  family  instruc- 
tion set  with  a  10  jus  instruction  cycle  time.  Both  devices  are  manufactured  with  a 
standard  PMOS  process,  allowing  use  of  a  single  -  10V  power  supply,  and  are  available 
in  a  28  pin  dual-in-line  plastic  package. 


PIN  NAMES 


CMC 
PCoC 
pciC 
pc2C 
pc3C 

PDqC  6 
PDlC  7 
PD2C  8 
PD3C  9 
PEoC  10 
PE1  C11 
PE2  C  12 
PE3  C13 
VSS  C  14 


juPD 
550/ 
554 


28  □  CL0 
27  □  Vqg 
26  □  RESET 
25  □  INT 
24  □  PA3 
23  □  PA2 

□  PA1 

□  PA0 
3  PG0 

□  PF3 

□  PF2 

□  PFi 

H  pf0 

□  TEST 


PA0-PA3 

Input  Port  A 

pc0-pc3 

Input/Output  Port  C 

PD0-PD3 

Input/Output  Port  D 

PE0-PE3 

Output  Port  E 

PF0-PF3 

Output  Port  F 

PG0 

Output  Port  G 

CLo-CLt 

External  Clock  Signals 

Tnt 

Interrupt  Input 

RESET 

Reset 

VQG 

Power  Supply  Negative 

vSs 

Power  Supply  Positive 

TEST 

Factory  Test  Pin 
(Connect  to  Vss> 

ABSOLUTE  MAXIMUM   Operating  Temperature    -10°Cto+70°C 

RATINGS*  Storage  Temperature  -40°C  to  +125°C 

Supply  Voltage,  VgG-   -15to+0.3V 

Input  Voltages  (Port  A,  INT,  RESET)  -15  to  +0.3V 

(Ports  C,  D)  -40to+0.3V 

Output  Voltages  -40  to  +0.3V 

Output  Current  (Ports  C,  D,  each  bit)  -4  mA 

(Ports  E,  F,  G,  each  bit)  -15mA 

(Total,  all  ports)   -60  m A 


Ta  =  25°C 

*COMMENT.  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


3-17 


MPD550/554 

Ta  m  -1Q°C  to  +70°C;  Vqq  » -10V  *  10% 


PARAMETER 

SYMBOL 

LIMITS 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

UNIT 

Input  Voltage  High 

V|H 

0 

-2.0 

V 

Ports  A,  C,  D.  TNT,  RESET 

Input  Voltage  Low 

-4.3 

VQG 

V 

Ports  A.MT,  RESET 

V|L2 

-4.3 

-35 

V 

Ports  C,  D 

Clock  Voltage  High 

V0H 

0 

-0.6 

CLq  Input,  External  Clock 

Clock  Voltage  Low 

V0L 

-6.0 

vqg 

CLq  Input,  External  Clock 

Input  Leakage  Current  High 

'LIH 

+10 

— — 
ma 

Ports  A,  C,  D,  INT,  RESET 
V|  =-1V 

Input  Leakage  Current  Low 

ILIL, 

-10 

ma 

Ports  A,  C.D.TnT,  RESET 
V,  = -11 V 

•LIL2 

-30 

ma 

Ports  C,  D,  V|  =  -35V 

Clock  Input  Leakage  Current  High 

'L0H 

+200 

ma 

CLo  Input,  V0H  "  0V 

Clock  Input  Leakage  Current  Low 

'L0L 

-200 

ma 

CLq  Input,  V^L  =  -11V 

Output  Voltage  High 

VOH-i 

-1.0 

V 

Ports  C,  D,  Ioh  =  ~2  mA 

VOH2 

-2.5 

V 

Ports  E,  F,  G,  Ioh  =  -10  mA 

Output  Leakage  Current  Low 

'LOL! 

-10 

MA 

Ports  C  through  G, 
V0  =  -11V 

'LOL2 

-30 

ma 

Ports  C  through  G, 
V0  -  -35V 

Supply  Current 

'GG 

-20 

-40 

mA 

Ta  -  25°  C 

PARAMETER 

LIMITS 

UNIT 

TEST 
CONDITIONS 

SYMBOL 

MIN 

ryp 

MAX 

Input  Capacitance 

C| 

15 

pF 

f  =  1  MHz 

Output  Capacitance 

c0 

15 

pF 

Input/Output  Capacitance 

C|Q 

15 

PF 

Ta  =  -10°Cto+70°C;VGG  --10V*  10% 

PARAMETER 

LIMITS 

UNIT 

TEST 
CONDITIONS 

SYMBOL 

MIN 

TYP 

MAX 

Oscillator  Frequency 

f 

150 

440 

KHz 

Rise  and  Fall  Times 

tr,tf 

0 

0.3 

MS 

External  Clock 

Clock  Pulse  Width  High 

VwH 

0.5 

5.6 

MS 

Clock  Pulse  Width  Low 

0.5 

5.6 

MS 

DC  CHARACTERISTICS 


CAPACITANCE 


AC  CHARACTERISTICS 


CLOCK  WAVEFORM 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 


Plastic,  (jiPD550C/554C 
Plastic  Shrinkdip,  (xPD550CT 
Plastic  Shrinkdip,  |xPD554CT 


3-18 


550/554DS-1-82-CAT 


ftPD550L 
MPD554L 


4-BIT  SINGLE  CHIP  MICROCOMPUTERS  WITH 
VACUUM  FLUORESCENT  DISPLAY  DRIVE 
CAPABILITY 

DESCRIPTION     The/iPD550L  and  the  juPD554L  are  pin-compatible  4-bit  single  chip  microcomputers 
which  have  the  same  architecture.  The  only  difference  between  them  is  that  the 
MPD550L  contains  a  640  x  8-bit  ROM,  whereas  the  MPD554L  contains  a  1000  x  8-bit 
ROM.  Both  devices  have  a  32  x  4-bit  RAM,  a  testable  interrupt  input  INT,  and  a  single- 
level  stack.  The  jUPD550L  and  the  /UPD554L  provide  21  I/O  lines  organized  into  the 
4-bit  input  port  A,  the  4-bit  I/O  ports  C  and  D,  the  4-bit  output  ports  E  and  F,  and  the 
1-bit  output  port  G.  The  17  I/O  ports  and  output  ports  are  capable  of  being  pulled  to 
-35V  in  order  to  drive  Vacuum  Fluorescent  Displays  directly.  The  juPD550L  and  the 
jiiPD554L  typically  execute  all  58  instructions  of  the  juCOM-4  family  instruction  set 
with  a  25  /is  instruction  cycle  time.  Both  devices  are  manufactured  with  a  modified 
PMOS  process,  allowing  use  of  a  single  -8V  power  supply,  and  are  available  in  a  28-pin 
dual-in-line  plastic  package. 

The  juPD550L  and  the  juPD554L  are  upward  compatible  with  the  jiiPD557L. 

PIN  NAMES 


PIN  CONFIGURATION 


CM  C 
PCoC 
pciC 
pc2C 
pc3C 

PDoQ  6 
7 
8 
9 


PD2C 
PD3C 

PE0C10 
PEi  C11 

PE2  C  12 
PE3C13 
VSS  C14 


juPD 
550  LI 
554 L 


28  □  CL0 
27  □  Vqg 
26  □  RESET 
25  □  INT 
24  3  PA3 
23  □  PA2 
22  3  PA! 
21  □  PA0 
20  □  PG0 

3  PF3 

□  PF2 

□  PF1 

□  PFO 
15  □  TEST 


PA0-PA3 

Input  Port  A 

PC0-PC3 

Input/Output  Port  C 

PD0-PD3 

Input/Output  Port  D 

PE0-PE3 

Output  Port  E 

PF0-PF3 

Output  Port  F 

PG0 

Output  Port  G 

CLo-CLt 

External  Clock  Signals 

"inT" 

Interrupt  Input 

RESET 

Reset 

VQG 

Power  Supply  Negative 

vSs 

Power  Supply  Positive 

TEST 

Factory  Test  Pin 
(Connect  to  V$s) 

ABSOLUTE  MAXIMUM 
RATINGS* 


Operating  Temperature  -10  C  to  +70  C 

Storage  Temperature  -40°C  to  +125°C 

Supply  Voltage,  Vqg-   -15to+0.3V 

Input  Voltages  (Port  A,  INT,  RESET)  -15  to  +0.3V 

(Ports  C,  D)  -40to+0.3V 

Output  Voltages  -40  to  +0.3V 

Output  Current  (Ports  C,  D,  each  bit)  -4  mA 

(Ports  E,  F,  G,  each  bit)  -15  mA 

(Total,  all  ports)  -60  mA 


Ta  =  25°C 

*  COM  ME  NT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


3-19 


jiPD550L/554L 


Ta  =  -10°C  to  +70°C,  Vqg  =  -8  OV  ±  10% 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Voltage  High 

VlH 

0 

-1  6 

V 

Ports  A,  C,  D,  INT,  RESET 

Input  Voltage  Low 

V|L1 

-4  5 

vgg 

V 

Ports  A,INT~,  RESET 

V|L2 

-4  5 

-35 

V 

Ports  C,  D 

Clock  Voltage  High 

V0H 

0 

-0  6 

V 

CLo  Input,  External  Clock 

Clock  Voltage  Low 

V0L 

-5  0 

vgg 

V 

CLo  Input,  External  Clock 

Input  Leakage  Current  High 

I  LI  H 

+  10 

MA 

Ports  A,  C,  D,INT,  RESET 
V|  =  -1 V 

Input  Leakage  Current  Low 

I  LI  l_i 

-10 

ma 

Ports  A,  C,  D,  INT,  RESET 
V|  =  -9V 

ILIL2 

-30 

ma 

Ports  C,  D,  V|  =  -35V 

Clock  Input  Leakage  Current  High 

'L0H 

+200 

ma 

CLo  '"Put,  V0H  =  0V 

Clock  Input  Leakage  Current  Low 

!L0L 

-200 

mA 

CLo  Input,  V0L  =  -9V 

Output  Voltage  High 

voht 

-1  0 

V 

Ports  C,  D,  Ioh  =  -2  mA 

VOH2 

-2  5 

V 

Ports  E,  F,  G,  Ioh  =  -10  mA 

Output  Leakage  Current  Low 

'LOL-1 

-10 

ma 

Ports  C  through  G, 
V0  =-9V 

'LOL2 

-30 

mA 

Ports  C  through  G, 
V0  =-35V 

Supply  Current 

'GG 

-12 

-24 

mA 

Ta  -  25°  C 

PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

Cl 

15 

pF 

f  =  1  MHz 

Output  Capacitance 

C0 

15 

pF 

Input/Output  Capacitance 

C|0 

15 

PF 

Ta  =  -10°C  to  +70°C,  Vqg  =  -8.0V  ±  10% 

PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Oscillator  Frequency 

f 

100 

180 

KHz 

Rise  and  Fall  Times 

V  *f 

0 

0.3 

MS 

Clock  Pulse  Width  High 

VwH 

2.0 

80 

MS 

External  Clock 

Clock  Pulse  Width  Low 

l0WL 

2.0 

8.0 

MS 

vss 

V0H 

vqg 


-i/f- 


■  t0WH  - 


-t0WL  - 


DC  CHARACTERISTICS 


CAPACITANCE 


AC  CHARACTERISTICS 


CLOCK  WAVEFORM 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 


Plastic,  fxPD550LC/554LC 


3-20 


550  L/554  LDS-2-82-CAT 


fiPD556B 


fiCOM-4  4-BIT  SINGLE  CHIP 
ROM-LESS  EVALUATION  CHIP 

DESCRIPTION     The  MPD556B  is  the  ROM-less  evaluation  chip  for  the  juCOM-4  4-bit  single  chip  micro- 
computer family.  The  /IPD556B  is  used  in  conjunction  with  an  external  2048  x  8-bit 
program  memory,  such  as  the  /LtPD2716  UV  EPROM,  to  emulate  each  of  the  14  differ- 
ent /iCOM-4  single  chip  microcomputers. 

The  juPD556B  contains  a  96  x  4-bit  RAM,  which  includes  six  working  registers  and  the 
Flag  register.  It  has  a  level-triggered  hardware  interrupt,  a  three-level  stack,  and  a  pro- 
grammable 6-bit  timer.  The  juPD556B  executes  all  80  instructions  of  the  extended 
/iCOM-4  family  instruction  set. 

The  juPD556B  provides  35  I/O  lines  organized  into  the  4-bit  input  Ports  A  and  B,  the 
4-bit  I/O  Ports  C  and  D,  the  4-bit  output  Ports  E,  F,  G,  and  H,  and  the  3-bit  output 
Port  I.  It  typically  executes  its  instructions  with  a  10jus  instruction  cycle  time.  The 
juPD556B  is  manufactured  with  a  standard  PMOS  process,  allowing  use  of  a  single  -10V 
power  supply,  and  is  available  in  a  64-pin  quad-in-line  ceramic  package. 


PIN  CONFIGURATION 


PIN  NAMES 


CL0 
GND  C 


PA0-PA3 

Input  Port  A 

PB0-PB3 

Input  Port  B 

PC0-PC3 

Input/Output  Port  C 

PD0-PD3 

Input/Output  Port  D 

PE0-PE3 

Output  Port  E 

PF0-PF3 

Output  Port  F 

PG0-PG3 

Output  Port  G 

PH0-PH3 

Output  Port  H 

PI0-PI2 

Output  Port  I 

INT 

Interrupt  Input 

'0-7 

Instruction  Input 

PCo-10 

Program  Counter  Output 

Acc/PC 

Accumulator/Program 
Counter  Select 

BREAK 

Break  Input 

STEP 

Single  Step  Input 

CLq-CLt 

External  Clock  Source 

RESET 

Reset 

VGG 

Power  Supply  Negative 

vSs 

Power  Supply  Positive 

TEST 

Factory  Test  Pin 
(Connect  to  V$s) 

3-21 


/iPD556B 


BLOCK  DIAGRAM 

ACC/PC 


HO170 


Operating  Temperature  -  10°C  to  +70°C 

Storage  Temperature   -40°C  to +125°C 

Supply  Voltage,  Vqg  -15Vto+0.3V 

All  Input  Voltages  -15Vto+0.3V 

All  Output  Voltages  -15V  to  +0.3V 

Output  Current  (total,  all  ports)  -4  mA 


ABSOLUTE  MAXIMUM 
RATINGS* 


Ta  =  25  C 

*COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


3-22 


pPD556B 

DC  CHARACTERISTICS  Ta.-io°cto*7o°c,vGG--ioviio%.vss.ov   


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  High 
Voltage 

V|H 

0 

-2.0 

V 

Ports  A  to  D,  1 7.0 

BREAK,  STEP,  INT,  RESET, 

and  Aqq/PC 

Input  Low 
Voltage 

V|L 

-4.3 

VGG 

V 

Poits  A  to  D,  I 7.q 

BREAK,  STEP,  INT,  RESET, 

and  Aq^qIPC 

Clock  Hiqh 
Voltage 

V,  ,h 

0 

-0.8 

V 

C Lq  Input,  External  Clock 

Clock  Low 
Voltage 

V,,,L 

-6  0 

VGG 

V 

CLq  Input,  External  Clock 

Input  Leakage 
Current  High 

1  LIH 

no 

HA 

Ports  A  and  B,  1 7.9 

INT,  RESET,  BREAK,  STEP, 

ACC/PC,V|=-1V 

MO 

mA 

Ports  C  and  D,  V|  =  -1 V 

Input  Leakage 
Current  Low 

"LIL 

-10 

/jA 

Ports  A  and  B,  1 7.0 

INT,  RESET,  BREAK,  STEP, 

Acc/pc-  vl  =-HV 

-10 

A<A 

Ports  C  and  D,  V|  =  -1 1 V 

Clock  Input 
Leakage  High 

1  L(.)H 

+  200 

HA 

CLq  Input,  External  Clock, 
V0H  ^  0V 

Leakage  Low 

'  L',')  L 

-200 

li  A 

CLq  Input  ExtGrnsI  Clock 
V^L  =  -11V 

Output  High 
Voltage 

vOH1 

-1  0 

V 

Ports  C  to  I,  Pio-O 
l0H  = -1.0  mA 

vOH2 

-2.3 

V 

Ports  C  to  I,  P 10-O 
l0H  =  ~3-3  mA 

Output  Leakage 
Current  Low 

•lol 

-30 

ma 

Ports  C  to  I,  P 10-0 
V0  =  -11V 

Supply  Current 

!gG 

-30 

-50 

mA 

AC  CH  AR  ACTE  R I  ST  ICS    t3  =  -io°c  to  +7o°c,  vGG  =  -iov  ±  10% 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Frequency 

f0 

150 

440 

KHz 

Clock  Rise  and  Fall  Times 

tr,  tf 

0 

0  3 

his 

Clock  Pulse  Width  High 

V'WH 

0  5 

5  6 

MS 

Clock  Pulse  Width  Low 

x<tW  L 

0  5 

5  6 

MS 

Input  Setup  Time 

*is 

5 

Input  Hold  Time 

*IH 

0 

MS 

BREAK  to  STEP  Interval 

tBS 

200 

MS 

f  =  400  KHz,  "1"  Written 

STEP  to  RUN  Interval 

tSB 

200 

MS 

f  =  400  KHz,  "1"  Written 

STEP  Pulse  Width 

*ws 

30 

MS 

f  =  400  KHz,  "1"  Written 

BREAK  to  Ace  Interval 

*BA 

200 

f  =  400  KHz,  "1"  Written 

AGc/pc  Pu|se  Width 

*WA 

30 

MS 

f  =  400  KHz,  "1"  Written 

STEP  to  Ace  Interval 

tSAI 

200 

MS 

f  =  400  KHz,  "1"  Written 

PC  to  STEP  Overlap 

^A2 

5 

MS 

f  =  400  KHz,  "1"  Written 

PC  to  RUN  Interval 

^B 

0 

MS 

f  =  400  KHz,  "1"  Written 

ACC/PC  -  P10-0  Delay 

^API 

15 

MS 

f  =  400  KHz,  "1"  Written 

tDAP2 

15 

MS 

f  =  400  KHz,  "1"  Written 

CAPACITANCE   Ta  =  25°c 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

C| 

15 

pf 

f  =  1  MHz 

Output  Capacitance 

CO 

15 

Pf 

Input/Output  Capacitance 

ClO 

15 

Pf 

3-23 


fiPD556B 


CLOCK  WAVEFORM 


„  0WH 


TIMING  WAVEFORMS 


(PC)n 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Ceramic  Quil,  |xPD556B 


3-24 


556BDS-1-82-CAT 


MFC  MPD7500  SERIES 

^  ^  w  CMOS  4-BIT  SINGLE  CHIP 

MICROCOMPUTER  FAMILY 


Description 

The  jL*PD7500  Series  CMOS  4-Bit  Single  Chip 
Microcomputer  Family  is  a  broad  product  line  of  16 
individual  devices  designed  to  fulfill  a  wide  variety  of 
applications.  The  advanced  4th  generation  architecture 
includes  all  of  the  functional  blocks  necessary  for  a 
single  chip  controller,  including  an  ALU,  Accumulator, 
Program  Memory  (ROM),  Data  Memory  (RAM),  four 
General  Purpose  Registers,  Stack  Pointer,  Program 
Status  Word  (PSW),  8-Bit  Timer/Event  Counter, 
Interrupt  Controller,  Display  Controller/Driver,  and  8-Bit 
Serial  Interface.  The  instruction  set  maximizes  the 
efficient  utilization  of  fixed  Program  Memory  space,  and 
includes  a  variety  of  addressing,  Table-Look-up, 
Logical,  Single  Bit  Manipulation,  vectored  jump,  and 
Condition  Skip  Instructions. 

The^PD7500  Series  includes  four  different  devices, 
the/^PD7501,)uPD7502,)uPD7503,  and  juPD7514,  capa- 
ble of  directly  driving  Liquid  Crystal  Displays  with  up  to 
16  7-segment  digits.  The  /iPD7508A,  /4PD7528, 
MPD7517,  ^PD7538,  mPD7537,  and  ^PD7519  can  direct- 
ly drive  up  to  35V  Vacuum  Fluorescent  Displays  with  up 
to  8  7-segment  digits,  and  the  ^PD7519  can  directly 
drive  up  to  35V  Vacuum  Fluorescent  Displays  with  up  to 
16  7-segment  digits. 

All  16  devices  are  manufactured  with  a  Silicon  gate 
CMOS  process,  consuming  only  900juA  max  at  5V,  and 
only  400nA  max  at  3V.  The  HALT  and  STOP  power- 
down  instructions  can  significantly  reduce  power 
consumption  even  further. 

The  flexibility  and  the  wide  variety  of  jiPD7500  Series 
devices  available  make  the  /iPD7500  series  ideally 
suited  for  a  wide  range  of  battery-powered,  solar- 
powered,  and  portable  products,  such  as  telecommu- 
nication devices,  hand-held  instruments  and  meters, 
automotive  products,  industrial  controls,  energy 
management  systems,  medical  instruments,  portable 
terminals,  portable  measuring  devices,  appliances,  and 
consumer  products. 

Features 

□  Advanced  4th  Generation  Architecture 

□  Choice  of  8-Bit  Program  Memory  (ROM)  size: 

-  1K,  2K,  4K  internal,  or  8K  external  bytes 

□  Choice  of  4-Bit  Data  Memory  (RAM)  size: 

-  64,  96,  128,  208,  224,  or  256  internal  nibbles 

□  RAM  Stack 

□  Four  General  Purpose  Registers:  D,  E,  H,  and  L 

-  Can  address  Data  Memory  and  I/O  ports 

-  Can  be  stored  to  or  retrieved  from  Stack 


□  Powerful  Instruction  Set 

-  From  58  to  110  instructions,  including: 

-  Direct/indirect  addressing 

-  Table  Look-up 

-  RAM  Stack  Push/Pop 

-  Single  byte  subroutine  calls 

-  RAM  and  I/O  port  single  bit  manipulation 

-  Accumulator  and  I/O  port  Logical  operations 

-  10  ms  Instruction  Cycle  Time,  typically 

□  Extensive  General  Purpose  I/O  Capability 

-  One  4-Bit  Input  Port 

-  Two  4-Bit  latched  tri-state  Output  Ports 

-  Five  4-Bit  input/latched  tri-state  Output  Ports 

-  Easily  expandable  with  MPD82C43  CMOS  I/O 

Expander 

-  8-Bit  Parallel  I/O  capability 

□  Hardware  Logic  Blocks  —  Reduce  Software 

Requirements 

-  Operation  completely  transparent  to  instruction 

execution 

-  8-Bit  Timer/Event  Counter 

-  Binary-up  counter  generates  INTj  at 

coincidence 

-  Accurate  Crystal  Clock  or  External  Event 

operation  possible 

-  Vectored,  Prioritized  Interrupt  Controller 

-  Three  external  interrupts  (INTrj,  INTi,  INT2) 

-  Two  internal  interrupts  (INTj,  INTs) 

-  Display  Controller/Driver 

-  Complete  Direct  Drive  and  Control  of  Multi- 

plexed LCD  or  Vacuum  Fluorescent  Display 

-  Display  Data  automatically  multiplexed  from 

RAM  to  dedicated  segment/backplane/digit 
driver  lines 

-  8-Bit  Serial  Interface 

-  3-line  I/O  configuration  generates  INTs  uP°n 

transmission  of  eighth  bit 

-  Ideal  for  distributed  intelligence  systems  or 

communication  with  peripheral  devices 

-  Complete  operation  possible  in  HALT  and  STOP 

power-down  modes 

□  Built-in  System  Clock  Generator 

□  Built-in  Schmidt-Trigger  RESET  Circuitry 

□  Single  Power  Supply,  Variable  from  2.7V  to  5.5V 

□  Low  Power  Consumption  Silicon  Gate  CMOS 

Technology 

-  900  mA  max  at  5V,  400  mA  max  at  3V 

-  HALT,  STOP  Power-down  instructions  reduce 

power  consumption  to  20  mA  max  at  5V, 
10mA  at  3V  (Stop  mode) 

□  Extended  -  40°C  to  +  85°C  Temperature  Range 

Available 

□  Choice  of  28-pin,  40-pin,  42-pin  dual-in-line  pack- 

ages, or  52-pin,  64-pin,  or  80-pih  flat  plastic 
packages. 


Rev/1 


3-25 


Features 

7500 

7501 

7502 

7503 

7514 

7506 

7507 

7507S 

7508 

7508A 

7519 

7527 

7528 

7537 

7538 

Internal  ROM 
(8-bit  words) 

1K 

2K 

4K 

4K 

1K 

2K 

2K 

4K 

4K 

4K 

2K 

4K 

2K 

4K 

Expandable  to 

8K 

RAM 

256x4 

96x4 

128x4 

224x4 

256  x4 

64x4 

128x4 

128x4 

224x4 

208x4 

256x4 

160  x  4  160  x  4 

160  x4  160x4 

I/O  Lines 

32 

24 

23 

23 

67 

22 

32 

20 

32 

32 

28 

35 

35 

35 

35 

8-Bit  Timer/Event 
Counter 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

8-Bit  Serial  Interface 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

• 

Registers  Outside  RAM 

4x4 

2x4 

4x4 

4x4 

2x4 

4x4 

4x4 

4x4 

4x4 

4x4 

2x4 

2x4 

2x4 

2x4 

Instructions 

110 

63 

92 

92 

92 

58 

92 

91 

92 

92 

92 

66 

66 

67 

67 

Min  Cycle  Time  (/us) 

6.67 

6.67 

6.67 

6.67 

5 

6.67 

6.67 

6.67 

6.67 

6.67 

6.67 

4 

4 

4 

4 

CJ 

4 

4 

4 

4 

2 

4 

4 

4 

4 

4 

3 

3 

3 

3 

Stack  Levels 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

RAM 

Display 

Controller/ 

Driver 

LCD 

LCD 

LCD 

LCD 

VFD 
drive 
only 

VFD 

VFD 
DRIVE 
ONLY 

VFD 
DRIVE 
ONLY 

VFD 
DRIVE 
ONLY 

VFD 
DRIVE 
ONLY 

Analog  I/O 

14-bit 
D/A 

Current  Consumption 
(max) 

Normal  Operation 

 900  mA  at  5V  ±  10%;  400 /iA  at  3V  ±  10%- 

Stop  Mode 

 20  pA  at  5V  ±  10%;  10/iA  at  3V  ±  10%— 

Operating 

Temperature  Range 

-10°C 
to-«- 

-40°C 

—  to  — 

+  70°C 

+  85°C 

Packages 

28-pin  DIP 

• 

• 

40-pin  DIP 

• 

• 

• 

52-pin  Flat 

• 

• 

• 

64-pin  Flat 

• 

• 

• 

64-pin  QUIL 

• 

• 

42-pin  DIP 

• 

• 

• 

• 

80-pin  Flat 

• 

o 

Ul 

o 
o 

to 

m 

39 

m 
to 


MPD7500  SERIES 


Instruction  Set 

The  jiPD7500  Series  Instruction  Set  consists  of  110 
powerful  instructions  designed  to  take  full  advantage  of 
the  advanced  /iPD7500  architecture  in  your  application. 
It  is  divided  into  two  subsets,  according  to  the 
complexity  of  the  device. 
Instruction  Set  "A"  is  available  for  the  higher- 
performance  jiPD7500  Series  devices  having  either  a 
2K  x  8-bit  or  a  4K  x  8-bit  Program  Memory.  It  can  be 
used  with  the  jiPD7500,  mPD7502,  mPD7503,  jiPD7507, 
MPD7507S,  fiPD7508,  MPD7508A,  /iPD7519,  mPD7514, 
MPD7527,  fiPD7528,  jiPD7537,  and  MPD7538  products. 
Instruction  Set  "B"  is  available  for  the  lower-cost 
/iPD7500  Series  devices  having  a  1 K  x  8-bit  Program 
Memory.  Its  instructions  are  a  compatible  subset  of 
Instruction  Set  "A,"  and  can  be  used  with  the 
/iPD7500,  jiPD7501 ,  and  mPD7506  products. 


Instruction  Set  Symbol  Definitions 

The  following  abbreviations  are  used  in  the  description 
of  the  ^PD7500  Series  Instruction  sets: 


Symbol                                       Explanation  and  If  so 

A 

Accumulator 

An 

Bit  "n"  of  Accumulator 

addr 

Address 

bit 

Operand  specifying  one  bit  of  a  nibble 

Bn 

Bit  "n"  of  two-bit  operand 

Bi      Bo      Bit  Specified 

0        0        Bit  0  (LSB) 

0        1        Bit  1 

1        0        Bit  2 

1        1        Bit  3  (MSB) 

Bank 

Bank  Flag  of  PSW  GuPD7500  only) 

borrow 

Resulting  value  is  less  than  OH 

C 

Carry  Flag 

data              Immediate  data  operand 

D 

D  Register 

Dn 

Bit  "n"  of  immediate  data  operand 

DE 

DE  Register  Pair 

DL 

DL  Register  Pair 

E  Register 

H 

H  Register 

HL 

HL  Register  Pair 

IER 

Interrupt  Enable  Register 

IER  bit:           0           12  3 

Interrupt:      INTj      INTo/S      INT1  INT2 

IME 

Interrupt  Master  Enable  F/F 

INTn 

interrupt  "n" 

IRFn 

Interrupt  Request  Flag  "n" 

L 

L  Register 

overflow 

Resulting  value  is  greater  than  FH 

P(  ) 

Parallel  Input/Output  Port  addressed  by  the  value  within  the  parentheses 

PC 

Program  Counter 

PCn 

Bit  "n"  of  Program  Counter 

PSW 

Program  Status  Word 

PSW  bit:        0           12  3 

Flag:          Carry     Bank     SKo  SKi 

rp 

Register  Pair,  specified  by  the  3-bit  immediate  data  operand  D2-0,  as 

follows: 

D2      D1      Do       rp                Additional  Action 

0       0       0      DL        none  (instruction  set  "A"  only) 

0       0       1       DE        none  (instruction  set  "A"  only) 

1        0       0      HL-      decrement  L;  skip  if  L  =  FH 

1        0       1       HL+      increment  L;  skip  if  L  =  OH 

1        1        0      HL  none 

S 

Skip  Cycles:  0  when  skip  condition  does  not  occur 

1  when  skip  condition  does  occur 

SIO 

Serial  I/O  Shift  Register 

SIOCR 

Serial  I/O  Count  Register 

SP                Stack  Pointer 

String 

String  Effect;  in  a  string  of  similar  instructions,  only  the  first 

encountered  is  executed;  the  remainder  of  the  instructions  in  the  string 

are  executed  as  NOP  instructions 

taddr 

Operand  specifying  ROM  Table  Data 

Tn 

Bit  "n"  of  ROM  Table  Data 

TCR 

Timer  Counter  Register 

TMR 

Timer  Modulo  Register 

(  ) 

The  contents  of  the  RAM  location  addressed  by  the  value  within  the 

parentheses 

I  1 

The  contents  of  the  ROM  location  addressed  by  the  value  within  the 

brackets 

Load,  Store,  or  Transfer  right  operand  into  left  operand 

«     »          Exchange  the  left  and  right  operands 

NOT 

Logical  NOT  (One's  complement) 

AND 

LOGICAL  AND 

XOR  LOGICAL  Exclusive  OR 

[;  ;;;.  Instruction  pertains  to  ^PD7500  only 


3-27 


juPD7500  SERIES 


Instruction  Set  "A" 

For  the  fxPD7500,  \xPD7502,  nPD7503,  iuPD7507,  nPD7507S,  nPD7508,  nPD7508A,  and  \iPD7519  devices  only 


Mnemonic 

Function 

Description 

Instruction  Code 

Bytes 

Cycles       Skip  Condition 

Oj 

06 

D5 

D4 

D3 

D2 

D1 

D0 

HEX 

Load 

LADR  addr 

A-(D7-0) 

Load  Accumulator 
from  directly 
addressed  RAM 

0 

0 

D6 

1 

D5 

1 

D4 

1 

D3 

0 

D2 

0 

D1 

0 

DO 

38 
OO-FF 

2 

2 

LAI  data 

A~D3-0 

Load  Accumulator 
with  immediate 
data 

0 

0 

0 

1 

D3 

D2 

D1 

DO 

10-1F 

1 

1  String 

LAM  rp 

A-(rp) 

rp  =  DL,  DE,  HL-,  HL  +  ,  HL 
if  rp  =  HL  - ,  skip  if  borrow 
if  rp  =  HL  +  ,  skip  if  overflow 

Load  Accumulator 
from  Memory, 
possible  skip 

0 

1 

0 

D2 

0 

0 

D1 

D0 

40,  41 
50-52 

1 

1  +  S       See  explanation 
of  "rp"  in  symbol 
definitions 

LAMT 

(^rU/5U0,  fiPD75UZ 

only) 

ROM  addr  =  PC10-6. 

0,  C,  A3  Q 

A-[ROM  addrj7-4 
(HL)-«-[ROM  addr]3.rj 

Load  Accumulator 
and  Memory  from 
Table 

0 

1 

0 

1 

1 

1 

1 

0 

5E 

1 

2 

LAMTL 

(nPD7500,  mPD7503, 
MPD7507,  nPD7507S, 
MPD7508,  mPD7508A, 
MPD7519,  only) 

ROM  addr  =  PCn-8, 

A3-O,  (HL)3-0 
A*-[ROM  addr]7-4 
(HL)~-[ROM  addr] 3.0 

Load  Accumulator 
and  Memory  from 
Table  Long 

0 
0 

0 
0 

1 
1 

1 
1 

1 
0 

1 
1 

1 
0 

1 
0 

3F 
34 

2 

2 

LDEI  data 

D-D7.4 
E-D3.0 

Load  DE  register 
pair  with  immedi- 
ate data 

0 

D7 

1 

D6 

0 

D5 

0 

D4 

1 

D3 

1 

D2 

1 

Dl 

1 

Do 

4F 
OO-FF 

2 

2 

LDI  data 

D*-D3-o 

Load  D  register 
with  immediate 
data 

0 

0 

0 

0 

1 

1 

1 

0 

1 

D3 

1 

D2 

1 

Dl 

0 

Do 

3E 
20-2F 

2 

2 

LEI  data 

E-D3.0 

Load  E  register 
with  immediate 
data 

0 
0 

0 
0 

1 

0 

1 

0 

1 

D3 

1 

D2 

1 

D1 

0 

DO 

3E 
00-OF 

2 

2 

LHI  data 

H-D3.0 

Load  H  register 
with  immediate 
data 

0 
0 

0 
0 

1 
1 

1 
1 

1 

D3 

1 

D2 

1 

D1 

0 

DO 

3E 
30-3F 

2 

2 

LHLI  data 

H-D7.4 
L-D3.0 

Load  HL  register 
pair  with  immedi- 
ate data 

0 

D7 

1 

D6 

0 

D5 

0 

□4 

1 

D3 

1 

D2 

1 

D1 

0 

DO 

4E 
OO-FF 

2 

2  String 

LHLT  taddr 

ROM  addr  =  0C0H  +  D3.0 
H«-[ROM  addrj7-4 
L*-[ROM  addr]3-o 

Load  HL  register 
pair  from  ROM 
Table 

1 

1 

0 

0 

D3 

D2 

D1 

DO 

CO-CF 

1 

2  String 

LLI  data 

L-D3.0 

Load  L  register 
with  immediate 
data 

0 
0 

0 
0 

1 
0 

1 
1 

1 

D3 

1 

D2 

1 

D1 

0 

DO 

3E 
10-1 F 

2 

2 

Store 

ST 

(HL)-A 

Store  A  to  Memory 

0 

1 

0 

1 

0 

1 

1 

1 

57 

1 

1 

Transfer 

TAD 

D-A 

Transfer  A  to  D 

0 

0 
0 

1 
1 

1 
0 

1 
1 

1 
0 

1 
1 

0 
0 

3E 
AA 

2 

2 

TAE 

E-  A 

Transfer  A  to  E 

0 
0 

1 

0 

1 

0 

1 
1 

1 
0 

1 
1 

0 
0 

3E 
8A 

2 

2 

TAH 

H*-A 

Transfer  A  to  H 

0 
0 

1 
1 

1 
1 

1 
1 

1 
0 

1 
1 

0 
0 

3E 
BA 

2 

2 

TAL 

L*-A 

Transfer  A  to  L 

0 
0 

1 

0 

1 
1 

1 
1 

1 

0 

1 
1 

0 
0 

3E 
9A 

2 

2 

TDA 

A— D 

Transfer  D  to  A 

0 
0 

1 
1 

1 

0 

1 
1 

1 

0 

1 
1 

0 

1 

3E 
AB 

2 

2 

TEA 

A"-E 

Transfer  E  to  A 

0 
0 

1 

0 

1 

0 

1 
1 

1 

0 

1 
1 

0 

1 

3E 
8B 

2 

2 

THA 

A-H 

Transfer  H  to  A 

0 
0 

1 
1 

1 
1 

1 
1 

1 

0 

1 
1 

0 

1 

3E 
BB 

2 

2 

TLA 

A«-L 

Transfer  L  to  A 

0 
0 

1 

0 

1 
1 

1 
1 

1 

0 

1 
1 

0 

1 

3E 
9B 

2 

2 

Exchange 

XAD 

A**D 

Exchange  A  with  D 

0 

1 

0 

0 

1 

0 

1 

0 

4A 

1 

1 

XADR  addr 

A«*(D7-0) 

Exchange  A  with 
directly  addressed 
RAM 

0 

D7 

0 

D6 

1 

D5 

1 

D4 

1 

D3 

0 

D2 

0 

D1 

1 

Do 

39 
OO-FF 

2 

2 

XAE 

A~E 

Exchange  A  with  E 

0 

1 

0 

0 

1 

0 

1 

1 

4B 

1 

1 

XAH 

A**H 

Exchange  A  with  H 

0 

1 

1 

1 

1 

0 

1 

0 

7A 

1 

1 

XAL 

A**L 

Exchange  A  with  L 

0 

1 

1 

1 

1 

0 

1 

1 

7B 

1 

1 

XAM  rp 

A~(rp) 

rp  =  DL,  DE,  HL  - ,  HL  + ,  HL 
if  rp  =  HL  - ,  skip  if  borrow 
if  rp  =  HL  + ,  skip  if  overflow 

Exchange  A  with 
Memory,  Possible 
Skip 

0 

1 

0 

D2 

0 

1 

D1 

DO 

44,  45 
54-56 

1 

1  +  S       See  explanation 
or  "rp"  in  symbol 
definitions 

XHDR  addr 

H«(D7-0) 

Exchange  H  with 
directly  addressed 
RAM 

0 

D7 

0 

D6 

□5 

1 

D4 

1 

D3 

0 

D2 

1 

D1 

0 

DO 

3A 
OO-FF 

2 

2 

XLDR  addr 

L~(D7-0) 

Exchange  L  with 
directly  addressed 

0 

D7 

0 

□6 

1 

D5 

1 

D4 

1 

D3 

0 

D2 

1 

D1 

1 

DO 

3B 
OO-FF 

2 

2 

3-28 


MPD7500  SERIES 


Instruction  Set  "A"  (Cont.) 

For  the  \iPD7500,  \xPD7502,  \xPD7503,  \xPD7507,  nPD7507S,  \xPD750B,  \xPD750BA,  and  \xPD7519  devices  only 


Mnemo 

nlc  Function 

Description 

Instruction  Code 

Bytes 

Cycles 

Skip  Condition 

D7 

D6     Ds  D4 

D3 

D2 

D1 

DO 

HEX 

Arithmetic 

ACSC 

A,  C*-A  +  (HL)  +  C 
skip  if  carry 

Add  with  carry, 
skip  if  carry 

0 

1        1  1 

1 

1 

0 

0 

7C 

1 

AOSC 

A-A  +  0 

—  ■    i 

Arid  D  tn  A  skin 
if  overflow 

0  11111 
0        10       10  0 

1 

*  +  * 

AESC 

AfiH  Ftn  1  akin 

1 

0     0  0 

1 

1        1  0' 
0       0  1 

,u  J?  JL„ 

89 

P^ 

m 

2+S 

 ^  

AHSC 

0 

0     1  1 

1     1  0 
0     0  1 

£!  2 

B9 

li 

AISC  data 

A--A  +  D3.0 
skip  if  overflow 

Add  immediate 
skip  if  overflow 

0 

000 

D3 

D2 

D1 

DO 

00-0F 

1 

1  +S 

Overflow 

Add  H  to  A.  skip 

0 

0     1  1 

1  0 

; 

0 
1 

mm 
|» 

ASC 

A«-A  +  (HL) 
skip  if  overflow 

Add  memory;  skip 
if  overflow 

0 

1      1  1 

1 

1 

0 

1 

7C 

1 

1+S 

Carry  =  1 

SDSB 

skip  if  borrow 

Subtract  0  from  A, 
skip  if  borrow 

0 

0      1  1 

0  :^1-;vV4  ;••! 

1 

;  :.:<*•• 

'•••'<*-•••; 

0 

2 

SESB 

skip  if  borrow 

Subtract  E  from  A, 
skip  If  borrow 

0  h 

i-:v 

0       1  1 
0        0  0 

-f 

.  ,.?.q,- 

0 
0 

SHSB 

Subtract  H  from  A, 
skip  if  borrow 

1 

0        1  1 

1 

0 
0 

SLSB 

Subtract  L  from  A, 
Skip  if  borrow 

0 

-t 

0     1  1 

001 

1 
1 

° 

0 

-r* 

0 

98 

Logical  I 

ANL 

A^A  AND  (HL) 

AND  Accumulator 
and  Memory 

0 

1 

0     1  1 
0     1  1 

1 
0 

1 
0 

1 
1 

1 

0 

3F 
B2 

2 

2 

EXL 

A*-A  XOR  (HL) 

Exclusive-Or 
Accumulator  and 
Memory 

0 

1     1  1 

1 

1 

1 

0 

7E 

1 

1 

ORL 

A*-A  OR  (HL) 

OR  Accumulator 
and  Memory 

0 

1 

0     1  1 
0     1  1 

1 
0 

1 
1 

1 
1 

1 

0 

3F 
B6 

2 

2 

Accumulator 

CMA 

A-NOT  A 

Complement 
Accumulator 

0 

1     1  1 

1 

1 

1 

1 

7F 

1 

1 

RAL 

a3*-a2 

• .',     i-yM^M   r ,': ;  <  -  -  -  .. 
/AaMStfcWV-  -:- 

Rotate 

Accumulator  left 
through  Carry 

0 

0     1  1 

1 
0 

1 

11™ 

•  ■ 

Wmi 

1 

3F 
B7 

2 

2 

RAR 

C-Ao 
Ao^Ai 
A1-A2 
A2-A3 
A3«-C  (old) 

Rotate 

Accumulator  right 
through  Carry 

0 

1 

0      1  1 
0      1  1 

1 
0 

1 
0 

1 
1 

1 
1 

3F 
B3 

2 

2 

Program  Status  Word 

RC 

C-0 

Reset  Carry 

0 

1      1  1 

1 

0 

0 

0 

78 

1 

1 

SC 

C-1 

Set  Carry 

0 

1      1  1 

1 

0 

0 

1 

79 

1 

1 

Incromont  and  Docromant 

DDE 

■   ■  Decrement  o£  . ' 

0 

1 

0      1  1 
n     o  0 

1 

1- 

;  1  - 

0 

0 
0 

3E 
8C 

2 

f|||1|ffj 

DDRS  addr 

(D7-0)-(D7-0)-1 
skip  if  (D7.0)  =  FH 

Decrement  directly 
addressed  RAM; 
skip  if  borrow 

0 

D7 

0      1  1 

D6      D5  D4 

1 

D3 

1 

02 

0 

D1 

0 

DO 

3C 
00-FF 

2 

2  +  S 

(D7-0)  =  FH 

DES 

E*-E  -  1 
skip  if  E  =  FH 

Decrement  E;  skip 
if  borrow 

0 

1         0  0 

1 

0 

0 

0 

48 

1 

1  +S 

E  =  FH 

DHL 

Decrement  HL 

0 

1 

0     0  1 

1 

"1  - 

1 

1 
0 

0 

0 

36 
9C 

'  - 

DLS 

L-L  -  1 
skip  if  L  =  FH 

Decrement  L,  skip 
if  borrow 

0 

1      0  1 

1 

0 

0 

0 

58 

1 

1+S 

L  =  FH 

IDE 

DE-DE  +  1 

Increment  DE 

0 

1 

0  '   1     t  ■ 

9       0  0 

1 
1 

-  ,    1  ,M 
1 

':-.t? 
0 

0 

1 

3E ; 

8D 

.  2 

IDRS  addr 

(D7_0)*-(D7_0)-1 
skip  if  (D7.0)  =  OH 

Increment  directly 
addressed;  skip  if 
overflow 

0 

D7 

0        1  1 
D6      D5  D4 

1 

D3 

1 

D2 

0 

D1 

1 

Do 

3D 
00-FF 

2 

2+S 

(D7.0)  =  OH 

IES 

E-E  +  1 
skip  if  E  =  OH 

Increment  E;  skip 
if  overflow 

0 

1         0  0 

1 

0 

0 

1 

49 

1 

1+S 

E  =  OH 

IHL 

; ;        IL^ml  +  .1  " • 

increment  HL 

0 

1 

0       1=  1 

s     0  *  X  . 

1 
1 

1  •; 
1 

1 
0 

0 

1 

•  3E 
9D 

-    2  = 

ILS 

L-L  +  1 
skip  if  L  =  OH 

Increment  L;  skip 
if  overflow 

0 

1        0  1 

1 

0 

0 

1 

59 

1 

1+S 

L  =  OH  1 

Bit  Manipulation 

RMB  bit 

(HL)bit-O 

bit  =  Bi-o  (0-3) 

Reset  Memory  bit 

0 

1        1  0 

1 

0 

B1 

Bo 

68-6B 

1 

1 

SMB  bit 

(HL)bit«~1 

bit  =  Bi-o  (0-3) 

Set  Memory  bit 

0 

1        1  0 

1 

1 

B1 

B0 

6C-6F 

1 

1 

3-29 


juPD7500  SERIES 


Instruction  Set  "A"  (Cont.) 

For  the  fiPD7500,  \iPD7502,  \iPD7503,  \jPD7507,  \iPD7507S,  \xPD7508,  \xPD7508A,  and  nPD7519  devices  only 


Mnemonic 

Function 

Description 

Instruction  Code 

Bytes 

Cycles 

Skip  Condition 

D7 

D6 

D5 

D4 

D3 

D2 

Dl 

D0 

HEX 

Branch 

CALL  addr 

(SP-1)^PC7-4 

(SP-2)*-PC3.o 

(SP-3)*-PSW 

(SP-4)-PCiM8 

SP*-SP-4 

BANK-0 

PC11-O 

PCl  0-0*~Dl  0-0 

Call  subroutine 

0 

0? 

0 

D6 

1 

D5 

1 

D4 

0 

D3 

D10 
D2 

D9 
D1 

D8 
DO 

30-37 
00-FF 

2 

2 

CALT  addr 

(SP-D-PC7-4 

(SP-2)<-PC3-o 
(SP-3)*-PSW 
(SP-4)-PCli.8 
ROMaddr  =  OCOH  +  D5.O 
BANK-0 

PCl  1.10^00 
PC9-7*-[ROM  addrj7-5 
PC6-5-OO 

PC4-0-IROM  addrj4-0 

Call  subroutine 

thrnimh  DOM  TaHIa 

inrougn  nuivi  1  aoie 
(single  byte) 

1 

1 

□5 

□4 

D3 

D2 

D1 

DO 

D0-FF 

1 

2 

JAM  data 

PC11.8-D3.O 

PC7.4-A 

PC3-0-(HL) 

Vectored  Jump  on 
Accumulator  and 
Memory 

0 
0 

0 
0 

1 
0 

1 
1 

1 

D3 

1 

D2 

1 

D1 

1 

DO 

3F 
10-1F 

2 

2 

JCP  addr 

PC5-0^D5-0 

Jump  within 
current  page 

1 

0 

D5 

D4 

D3 

D2 

D1 

DO 

80-BF 

1 

1 

JMP  addr 

PCn-O^Dn-o 

Jump  to  specified 
address 

0 

D7 

0 

D6 

1 

D5 

0 

D4 

011 
D3 

D10 
D2 

D9 
D1 

D8 
DO 

20-2F 
00-FF 

2 

2 

JUMPL  aedr 
RT 

BANK-D12 
PC11.0*  D11.0 

PC11.8-(SP) 
BANK~-(SP  +  1) 
PC3-0^(SP  +  2) 
PC7-4^(SP  +  3) 
SP-SP  +  4 

Jump  Long  to 
specified  address 

Return  from 
Subroutine 

0 

Oy 
0 

mi 
ill 

D6 
1 

1 
012 

D5 
0 

jjgji 
111 

D4 

1 

1 

Oil 

D3 
0 

D2 
0 

j§(J 
D9 

JDl  _ 
1 

1 

D8 

DO 
1 

3> 
0C-0F 
20-2F 
00-FF 

53 

3 
1 

1 

RTPSW 

PC11.8-(SP) 
PSW-(SP  +  1) 
PC3-o«-(SP  +  2) 
PC7-4^(SP  +  3) 
SP-SP  +  4 

Return  from 
Subroutine  and 
restore  PSW 

0 

1 

0 

0 

0 

0 

1 

1 

43 

1 

2 

RTS 

PCl1-8«-(SP) 
BANK^(SP  +  1) 
PC3-0-(SP  +  2) 
PC7-4*-(SP  +  3) 
SP«-(SP  +  4) 
Skip  unconditionally 

Return  from 
Subroutine;  then 
skip  next 
instruction 

0 

1 

0 

1 

1 

0 

1 

1 

5B 

1 

1+S 

Unconditional 

Stack 

POPDE 

E-(SP) 
D-(SP  +  1) 
SP^SP  +  2 

Pop  DE  register 
pair  off  Stack  ( 

0 
1 

0 
0 

1 
0 

1 
0 

0 

1 

3E 
8F 

2 

2 

POPHL 

L-(SP) 
H*-(SP  +  1) 
SP-SP  +  2 

Pop  HL  register 
pair  off  Stack 

0 
1 

0 
0 

1 

0 

0 

1 

3E 
9F 

2 

2 

PSHDE 

(SP-1)*-D 
(SP-2)~-E 
SP*-SP-2 

Push  DE  register 
pair  on  Stack 

0 
1 

0 
0 

1 

0 

0 
0 

3E 
8E 

2 

2 

PSHHL 

(SP-1)-H 
(SP-2)-L 
SP-SP-2 

Push  HL  register 
pair  on  Stack 

0 
1 

0 
0 

1 

0 

0 
0 

3E 
9E 

2 

2 

TAMSP 

SP7-4^A 

SP3-1-(HL)3-1 

SPo*-0 

Transfer  Accumu- 
lator and  Memory 
to  Stack  Pointer 

0 
0 

0 
0 

1 
1 

1 
1 

3F 
31 

2 

2 

TSPAM 

A-SP7-4 

(HL)3-1~SP3-1 

(HL)0*-0 

Transfer  Stack 
Pointer  to 
Accumulator  and 
Memory 

0 
0 

0 
0 

1 
1 

0 

0 

1 
1 

3F 
35 

2 

2 

Conditional  Skip 

SKABT  bit 

Skip  if  Abit  =  1 
bit  =  Bi.  0(0-3) 

Skip  if  Accumulator 
bit  true 

0 

1 

0 

B1 

BO 

74-77 

1 

1+S 

Abit  =  1 

SKAEI  data 

Skip  if  A  =  D3-0 

Skip  if  Accumulator 
equals  immediate 
data 

0 
0 

1 
1 

1 

D3 

D2 

1 

D1 

1 

DO 

3F 
60-6F 

2 

2  +  S 

A  =  D3.0 

SKAEM 

Skip  If  A  =  (HL) 

Skip  if  Accumulator 
equals  Memory 

0 

0 

1 

1 

1 

5F 

1 

1+S 

A  =  (HL) 

SKC 

Skip  if  C  =  1 

Skip  if  Carry 

0 

0 

1 

1 

0 

5A 

1 

1+S 

C  =  1 

SKOEI  data 

Skip  if  D  =  D3.0 

Skip  if  D  equals 
immediate  data 

0 
0 

1 
1 

1 

D3 

D2 

1 

D1 

0 

DO 

3E 
60-6F 

2 

2  +  S 

D  =  D3.0 

SKEEI  data 

Skip  if  E  =  O3-0 

Skip  if  E  equals 
immediate  data 

0 
0 

1 

0 

1 

D3 

D2 

1 

D1 

0 

DO 

3E 
40-4F 

2 

2  +  S 

E  =  D3-0 

SKHEI  data 

Skip  if  H  =  D3.0 

Skip  if  H  equals 
immediate  data 

0 
0 

1 
1 

1 

D3 

D2 

1 

D1 

0 

DO 

3E 
70-7F 

2 

2  +  S 

H  =  D3-0 

3-30 


MPD7500  SERIES 


Instruction  Set  "A"  (Cont.) 

For  the  \xPD7500,  \aPD7502,  \iPD7503,  ^PD7507,  \xPD7507S,  yiPD750B,  nPD7508A,  and  \xPD75i9  devices  only 


Instruction  Cod* 

Mnomonle  Function  Description  "     Bytos     Cycles      Skip  Condition 

P7     P«     PS     D4     D3     P2     Pi      Dp  HEX  


Conditional  Skip  (Cont.) 


SKLEI  data 

Skip  If  L  =  D3-0 

Skip  if  L  equals 
immediate  data 

0 
0 

0  1 

1  0 

1 
1 

1 

D3 

1 

D2 

1 

D1 

0 

DO 

3E 
50-5F 

2 

2  +  S 

L  =  D3-0 

SKMBF  bit 

Skip  if  (HL)bit  =  0 
bit  =  B  1-0(0-3) 

Skip  if  Memory 
bit  false 

0 

1  1 

0 

0 

0 

B1 

BO 

60-63 

1 

1+S 

(HL)blt  =  0 

SKMBT  bit 

Skip  if  (HL)bit  =  1 
bit  =  B  1.0(0-3) 

Skip  if  Memory 
bit  true 

0 

1  1 

0 

0 

1 

B1 

BO 

64-67 

1 

1+S 

(HL)bit  =  1 

mm 

Skip  H  Memory 
equals  immediate 

data 

0 

«  1 

ll|||||j|ll||B| 

1 

Iff 

1 

i 

02 

; r: 

1  " 
00 

.  ■■<#■■  ■■: 

1 

; 

Timer/Event  Counter 

TAMMOD 

TMR7-4^A 
TMR3-0-(HL) 

Transfer 

Accumulator  and 
Memory  to  Timer 
Modulo  Register 

0 
0 

0  1 
0  1 

1 
1 

1 
1 

1 
1 

1 
1 

1 
1 

3F 
3F 

2 

2 

TCNTAM 

A-TCR7-4 
(HL)*-TCR3-0 

Transfer  Timer 
Count  Register  to 
Accumulator  and 
Memory 

0 
0 

0  1 
0  1 

1 
1 

1 
1 

1 
0 

1 
1 

1 
1 

3F 
3B 

2 

2 

TIMER 

TCR7.0<-0 
IRFT*-0 

Start  Timer 

0 
0 

0  1 
0  1 

1 
1 

1 
0 

1 

0 

1 
1 

1 

0 

3F 
32 

2 

2 

Interrupt  Control 

Dl  data 

IME  F/F-0  if  data  =  0 
IER3.0-IER3-0  AND  NOT 
D3.0  if  data  <>0 

Disable  Interrupt, 
Interrupt  Master 
Enable  F/F  or 
specified 

0 

1 

0  1 
0  0 

1 

0 

1 

D3 

1 

D2 

1 

D1 

1 

DO 

3F 
80-8F 

2 

2 

El  data 

IME  F/F-1  if  data  =  0 
IER3.o^lER3.0  OR  D3.0 
if  data  <>  0 

Enable  Interrupt, 
Interrupt  Master 
Enable  F/F  or 
specified 

0 

1 

0  1 
0  0 

1 
1 

1 

D3 

1 

D2 

1 

D1 

1 

DO 

3F 
90-8F 

2 

2 

SKI  data 

Skip  if  IRFn  AND  D3-0  <>  0 
IRFn^lRFn  AND  NOT  D3-0 

Skip  if  Interrupt 
Request  Flag  is 
true 

0 
0 

0  1 

1  0 

1 

0 

1 

03 

1 

D2 

1 

D1 

1 

DO 

3F 
40-4F 

2 

2  +  S 

IRFn  =  1 

Serial  Interface 

SIO 

SIOCR-0 
IRFo/S*-0 

Start  Serial  I/O 
Operation 

0 
0 

0  1 
0  1 

1 
1 

1 
0 

1 
0 

1 
1 

1 
1 

3F 
33 

2 

2 

TAMSIO 

SI07-4*-A 
SIO3-0*-(HL) 

Transfer  Accumu- 
lator and  Memory 
to  SI  Shift 
Register 

0 
0 

0  1 
0  1 

1 
1 

1 
1 

1 
1 

1 
1 

1 
0 

3F 
3E 

2 

2 

TSIOAM 

A-SIO7-4 
(HL)-SIO3-0 

Transfer  SI  Shift 
Register  to  Accumu 
lator  and  Memory 

0 
0 

0  1 
0  1 

1 
1 

1 
1 

1 
0 

1 
1 

1 
0 

3F 
3A 

2 

2 

Parallel  I/O 

ANP  data 

P(P3-0)-P(P3-0)  AND  D3-0 

AND  output  port 
latch  with 
immediate  data 

0 

D3 

1  0 
02  D1 

0 

DO 

1 

P3 

1 

P2 

0 
P1 

0 

PO 

4C 
00-FF 

2 

2 

IP  port 

A-P(P3-0) 

Input  from  port, 
immediate  address 

0 

1 

0  1 

1  0 

1 

0 

1 

P3 

1 

P2 

1 

P1 

1 

PO 

3F 
CO-CF 

2 

2 

IP1  (except 
MPD7507S) 

A-P(1) 

Input  from  Port  1 

0 

1  1 

1 

0 

0 

0 

1 

71 

1 

1 

IP54 

A-P(5) 
(HL)-P(4) 

Input  Byte  from 
Ports  5  and  4 

0 
0 

0  1 
0  1 

1 
1 

1 
1 

1 
0 

1 

0 

1 

0 

3F 
38 

2 

2 

IPL 

A-P(L) 

Input  from  Port 
specified  by  L 

0 

1  1 

1 

0 

0 

0 

0 

70 

1 

1 

OP  port 

P(P3-0)-A 

Output  to  port, 
immediate  address 

0 

1 

0  1 

1  1 

1 

0 

1 

P3 

1 

P2 

1 

P1 

1 

PO 

3F 
EO-EF 

2 

2 

OP3 

P(3)-A 

Output  to  Port  3 

0 

1  1 

1 

0 

0 

1 

1 

73 

1 

1 

OP54 

P(5)-A 
P(4)-(HL) 

Output  Byte  to 
Ports  5  and  4 

0 
0 

0  1 
0  1 

1 
1 

1 
1 

1 
1 

1 

0 

1 

0 

3F 
3C 

2 

2 

OPL 

P(L)-A 

Output  to  port 
specified  by  L 

0 

1  1 

1 

0 

0 

1 

0 

72 

1 

1 

ORP  data 

P(P3-0)*-(P3-0)  OR  D3.0 

OR  output  port 
latch  with 
immediate  data 

0 

D3 

1  0 
D2  D1 

0 

DO 

1 

P3 

1 

P2 

0 

P1 

1 

PO 

4D 
00-FF 

2 

2 

RPBL 

mPD82C43  I/O  Expander  Port 

^>bit(Li-0)-0 

Reset  Port  Bit 
specified  by  I 

0 

1  0 

1 

1 

1 

0 

0 

5C 

1 

1 

SPBL 

MPD82C43  I/O  Expander  Port 

0-3-2)  <M-0>~1 

Set  Port  Bit 
specified  by  L 

0 

1  0 

■Hj 

1 

III 

1 

50 

1 

t 

CPU  Control 

HALT 

Enter  HALT  Mode 

0 
0 

0  1 
0  1 

1 
1 

1 
0 

1 
1 

1 
1 

1 

0 

3F 
36 

2 

2 

NOP 

No  operation 

0 

0  0 

0 

0 

0 

0 

0 

00 

1 

1 

STOP 

Enter  STOP  Mode 

0 
0 

0  1 
0  1 

1 
1 

1 
0 

1 
1 

1 
1 

1 
1 

3F 
37 

2 

2 

3-31 


fiPD7500  SERIES 


Instruction  Set  "B" 


For  the  \xPD7500,  \xPD7501,  and  nPD7506  devices  only 


onlc  Function 

Description 

Instruction  Code 

Bytes 

Cycles 

Skip  Condition 

Mnemi 

D7 

D6  D5 

D4 

D3 

D2 

D1 

D0 

HEX 

Load 

LADR  addr 

A-(D6-0) 

Load  Accumulator 
from  directly 
addressed  RAM 

0 
0 

0  1 
D6  D5 

1 

D4 

1 

D3 

0 

D2 

0 

D1 

0 

DO 

38 
00-5F 

2 

2 

LAI  data 

A— D3-0 

Load  Accumulator 
with  immediate  data 

0 

0  0 

1 

D3 

D2 

D1 

D0 

10-1F 

1 

1 

String 

LAM  rp 

A-trp), 

rp  =  HL-,  HL  +  ,  HL 

If  rp  =  HL  - ,  skip  if  borrow 

if  rp  =  HL  + ,  skip  if  overflow 

Load  Accumulator 
from  Memory, 
possible  skip 

0 

1  0 

1 

0 

0 

D1 

DO 

50-52 

1 

1+S 

See  explanation 
of  "rp"  in  symbol 
definitions 

LAMT 

ROM  addr  =  PC10-6, 

0,  c,  A3.0 
A-[ROM  addr]7-4 
(HL)~-[ROM  addr]3-0 

Load  Accumulator 
and  Memory  from 
Table 

0 

1  0 

1 

1 

1 

1 

0 

5E 

1 

2 

LAMTL 

ROM  addr  =  PC1O-8. 

A3.D,  <HL)3.0 
A-IROM  8ddrl7-4 
(HL)~fftOM  addrfc-O 

Load  Accumulator 
and  Memory  from 
Table  Long 

0 

111 

mi 
ill 

Ha 

Hal 

lllllll 

BB 

IB 

3F 
34 

LHI  data 

H3-O 
H2-0^D2-0 

Load  H  register  with 
immediate  data 

0 

0  1 

0 

1 

D2 

D1 

DO 

28-2F 

1 

1 

LHLI  data 

H3-1-0 
Ho*-D4 
L*-D3-0 

Load  HL  register 
pair  with  immedi- 
ate data 

1 

1  0 

D4 

D3 

D2 

D1 

DO 

CO-DF 

1 

1 

String 

Store 

ST 

(HL)-A 

Store  A  to  Memory 

0 

1  0 

1 

0 

1 

1 

1 

57 

1 

1 

STII  data 

(HL)-D3-0 
L-L  +  1 

Store  immediate 
data  and 
increment  L 

0 

1  0 

0 

D3 

D2 

D1 

DO 

40-4F 

1 

1 

Exchange 

XADR  addr 

A«(D6-0) 

Exchange  A  with 
directly  addressed 
RAM 

0 
0 

0  1 

D6  D5 

1 

D4 

1 

D3 

0 

D2 

0 

D1 

1 

DO 

39 
00-5F 

2 

2 

XAH 

A**H 

Exchange  A  with  H 

0 

1  1 

1 

1 

0 

1 

0 

7A 

1 

1 

XAL 

A**L 

Exchange  A  with  L 

0 

1  1 

1 

1 

0 

1 

1 

7B 

1 

1 

XAM  rp 

A-(rp) 

rp  =  HL  - ,  HL  + ,  HL 

if  rp  =  HL  - ,  skip  if  borrow 

if  rp  =  HL  + ,  skip  if  overflow 

Exchange  A  with 
Memory,  Possible 
Skip 

0 

1  0 

1 

0 

1 

D1 

DO 

54-56 

1 

1+S 

See  explanation 
or  "rp"  in  symbol 
definitions 

XHDR  addr 

H«(D6-0) 

Exchange  H  with 
directly  addressed 
RAM 

0 
0 

0  1 
D6  D5 

1 

D4 

1 

D3 

0 

D2 

1 

D1 

0 

DO 

3A 
00-5F 

2 

2 

XLDR  addr 

L~(D6-0) 

Exchange  L  with 
directly  addressed 
RAM 

0 
0 

0  1 
D6  D5 

1 

D4 

1 

D3 

0 

D2 

1 

D1 

1 

D0 

3B 
00-5F 

2 

2 

Arithmetic 

ACSC 

A,  C-A±(HL)  +  C 
skip  if  carry 

Add  with  carry; 
skip  if  carry 

0 

1  1 

1 

1 

1 

0 

0 

7C 

1 

1+S 

Carry  =  1 

AISC  data 

A«-A  +  D3-0 
skip  if  overflow 

Add  immediate; 
skip  if  overflow. 

0 

0  0 

0 

D3 

D2 

D1 

DO 

00-0F 

1 

1+S 

Overflow 

ASC 

A-A  +  (HL) 
skip  if  overflow 

Add  memory;  skip 
if  overflow 

0 

1  1 

1 

1 

1 

0 

1 

7C 

1 

1+S 

Carry  =  1 

Logical 

ANL 

A*-A  AND  (HL) 

AND  Accumulator 
and  Memory 

0 

1 

0  1 
0  1 

1 
1 

1 
0 

1 
0 

1 
1 

1 
0 

3F 
B2 

2 

2 

EXL 

A-A  XOR  (HL) 

Exclusive-Or 
Accumulator  and 
Memory 

0 

1  1 

1 

1 

1 

1 

0 

7E 

1 

1 

ORL 

A^A  OR  (HL) 

OR  Accumulator 
and  Memory 

0 

1 

0  1 
0  1 

1 
1 

1 
0 

1 
1 

1 
1 

1 

0 

3F 
B6 

2 

2 

Accumulator 

CMA 

A*-NOT  A 

Complement 
Accumulator 

0 

1  1 

1 

1 

1 

1 

1 

7F 

1 

1 

RAL 

Rotate 

Accumulator  left 
through  Carry 

0 

■jj 

jjjlB 

Bill 

■SB 
Mb 

BIB 

3F 
B7 

BHHI 

RAR 

C*-Ao 
Ao^Ai 
A1-A2 
A2*-A3 
A3-C  (old) 

Rotate 

Accumulator  right 
through  Carry 

0 

1 

0  1 
0  1 

1 
1 

1 
0 

1 
0 

1 
1 

1 
1 

3F 
B3 

2 

2 

Program  Status  Word 

RC 

C-0 

Reset  Carry 

0 

1  1 

1 

1 

0 

0 

0 

78 

1 

1 

SC 

C«-1 

Set  Carry 

0 

1  1 

1 

1 

0 

0 

1 

79 

1 

1 

3-32 


MPD7500  SERIES 


Instruction  Set  "B"  (Cont.) 


For  the  \aPD7500,  ixPD7501,  and  \xPD750B  devices  only 


Mnemonic 

Function 

Description 

Instruction  Code 

Bytes 

Cycles 

Skip  Condition 

D7 

D6 

D4 

D3 

D2 

Dl 

DO 

HEX 

Increment  and  Decrement 

DDRS  addr 

(D6-0)-(D6-0)-1 
skip  if  (D6-0)  =  FH 

Decrement  directly 
addressed  RAM; 
skip  if  borrow 

0 

0 

0 

D6 

1 

05 

1 

D4 

D3 

1 

02 

0 
D1 

0 

DO 

3C 
00-5F 

2 

2  +  S 

(D6-0)  =  FH  - 

DLS 

L-L  -  1 
skip  if  L  =  FH 

Decrement  L;  skip 
if  borrow 

0 

1 

0 

1 

0 

0 

0 

58 

1 

1+S 

L  =  FH 

IDRS  addr 

(D6.0)-(D6.0)  +  1 
skip  if  (D6.0)  =  OH 

Increment  directly 
addressed;  skip  if 
overflow 

0 
0 

0 

D6 

1 

D5 

1 

04 

D3 

1 

D2 

0 
01 

1 

DO 

3D 
00-5F 

2 

2  +  S 

(D6.0)  =  OH 

ILS 

L-L  +  1 
skip  if  L  =  OH 

Increment  L;  skip  if 
overflow 

0 

1 

0 

1 

0 

0 

1 

59 

1 

1+S 

L  x  OH 

Bit  Manipulation 

RMB  bit 

(HL)bit*"0 

bit  =  Bi-o  (0-3) 

Reset  Memory  bit 

0 

1 

1 

0 

0 

B1 

BO 

68-6B 

1 

1 

SMB  bit 

(HL)bit-1 

bit  =  Bi-o  (0-3) 

Set  Memory  bit 

0 

1 

1 

0 

1 

B1 

BO 

6C-6F 

1 

1 

Branch 

CALL  addr 

(SP-1)*-PC7-4 

(SP-2)*-PC3-0 

(SP-3)<-PSW 

(SP-4)-PCiO-8 

SP-SP-4 

BANK*-0 

PCio-O^D10-0 

Call  subroutine 

0 

D7 

0 

D6 

1 

D5 

1 

D4 

0 

D3 

D10 
D2 

Dg 
D1 

D8 
DO 

30-37 
OO-FF 

2 

2 

CAL  addr 

(SP-1)*-PC7-4 
(SP-2)-PC3-0 
(SP-3)«-PSW 
(SP-4)-PClO-8 
BANK-0 
PC10-0^ 
001D4D3000D2D1D0 

Call  short  to 
CAL  address 
subrountine 

1 

1 

1 

D4 

D3 

D2 

01 

DO 

EO-FF 

1 

2 

JAM  data 

PC10-8-D2-0 

PC7.4-A 

PC3-0-(HL) 

Vectored  Jump  on 
Accumulator  and 
Memory 

0 
0 

0 
0 

1 
0 

1 
1 

1 
0 

1 

02 

1 

D1 

1 

DO 

3F 
10-17 

2 

2 

JCP  addr 

PC5.0-D5.O 

Jump  within 
current  page 

1 

0 

D5 

D4 

D3 

D2 

D1 

DO 

80-BF 

1 

1 

JMP  addr 

PCio.O«-DiO-0 

Jump  to  specified 
address 

0 

,„PZ„„ 

0 

D6  , 

1 

D5 

0 

04 

0 

D3 

D10 
D2 

09 
D1 

08 
DO 

20-27 
OO-FF 

2 

2 

BAHKHBta 

Jump  Long  t° 
speclfta*  atfdr*** 

0 

III! 

07 

9  . 
HI 

jaL 

t 

D12 

I 

lllllS 

',oV 

ill 

1 

Old 

'0* 

III 

Of 

0* 
Oo 

.3*  ' 

00-or 

OQ-FF 

-     *  .  . 

»; 

RT 

PCiO-8-(SP) 
BANK>(SP  +  1) 
PC3-0-(SP  +  2) 
PC7-4*"(SP  +  3) 
SP-SP  +  4 

Return  from 
Subroutine 

0 

1 

0 

1 

0 

0 

1 

1 

53 

1 

1 

RTS 

PCiO-8*-(SP) 
BANK-(SP  +  1) 
PC3-0-(SP  +  2) 
PC7-4HSP  +  3) 
SP-SP  +  4 
Skip  unconditionally 

Return  from 
Subroutine;  then 
skip  next 
instruction 

0 

1 

0 

1 

1 

0 

1 

1 

5B 

1 

1+S 

Unconditional 

Stack 

TAMSP 

SP7-4-A 

SP3.1*-(HL)3-1 

SPo-0 

Transfer  Accumu- 
lator and  Memory 
to  Stack  Pointer 

0 
0 

0 
0 

1 
1 

1 
1 

1 
0 

1 
0 

1 
0 

1 
1 

3F 
31 

2 

2 

T8PAM 

Transfer  Stack 
Pointer  to 

111! 

0 

tit- 

1 

III 

t 

llfli 

1 

111 

t 

Hi 

1 

111:: 

3F 
35 

2 

2 

Conditional  Skip 

SKABT  bit 

Skip  if  Abit  =  1 
bit  =  B  lo(0-3) 

Skip  if  Accumulator 
bit  true 

0 

1 

1 

0 

B1 

BO 

74-77 

1 

1+S 

Abit  -  1 

SKAEI  data 

Skip  if  A  =  D3.0 

Skip  if  Accumulator 
equals  immediate 
data 

0 
0 

1 
1 

1 
0 

1 

03 

D2 

1 

01 

1 

DO 

3F 
60-6F 

2 

2  +  S 

A  =  03-0 

SKAEM 

Skip  if  A  =  (HL) 

Skip  if  Accumulator 
equals  Memory 

0 

0 

1 

1 

1 

1 

5F 

1 

1+S 

A  =  (HL) 

SKC 

Skip  if  C  =  1 

Skip  if  Carry 

0 

0 

1 

1 

1 

0 

5A 

1 

1+S 

C  >  1 

SKLEI  data 

Skip  If  L  m  D3.0 

Skip  if  L  equals 
immediate  data 

0 
0 

1 

0 

1 
1 

1 

03 

D2 

1 

D1 

0 

DO 

3E 
50-5F 

2 

2  +  S 

L  «  D3-0 

SKMBF  bit 

Skip  if  (HL)blt  =  0 
bit  =  B  1-0(0-3) 

Skip  if  Memory 
bit  false 

0 

1 

0 

0 

B1 

B0 

60-63 

1 

1+S 

(HL)bit  =  0 

SKMBT  bit 

Skip  if  (HL)bit  =  1 
bit  =  B  1-0(0-3) 

Skip  if  Memory 
bit  true 

0 

1 

0 

0 

B1 

BO 

64-67 

1 

1+S 

(HL)bit  =  1 

SKMEi 

Skip  it  Memory 
equals  immediate 

1 

H 

1 

HI 

1 

03 

0* 

t 

Dl 

■Hi 
o« 

3F 
70.7F 

HH 

2+S 

(HL)  m  03^ 

3-33 


/JPD7500  SERIES 

Instruction  Set  "B"  (Cont.) 


For  the  yiPD7500,  ^PD7501,  and  nPD7506  devices  only 


Instruction  Code 

Mnemonic 

Function 

Description 

Bytes 

Cycles       Skip  Condition 

07 

D6 

D5     D4     D3     D2  Di 

D0 

HEX 

Timer/Event  Counter 

TAMMOD 

TMR7-4^A 
TMR3-0*"(HL) 

Transfer 

Accumulator  and 
Memory  to  Timer 
Modulo  Register 

0 
0 

0 
0 

11111 
11111 

1 
1 

3F 
3F 

2 

2 

TCNTAM 

A-TCR7.4 

Transfer  Timer 

0 

0 

11111 

1 

3F 

2 

2 

(except  mPD7506) 

(HL)*-TCR3-0 

Count  Register  to 
Accumulator  and 
Memory 

0 

0 

1110  1 

1 

3B 

TIMER 

TCR7.0-0 
IRFT-0 

Clear  Timer 
Counter  Register 

0 
0 

0 
0 

11111 
110        0  1 

1 
0 

3F 
32 

2 

2 

Interrupts 

SKI  data 

Skip  if  IRFn  AND  D3-0  <>  0 
IRFn*-IRFn  AND  NOT  D3-0 

Skip  if  Interrupt 
Request  Flag  is  true 

0 
0 

0 

1 

11111 

0       0        0       D2  D1 

1 

DO 

3F 
40-47 

2 

2  +  S       IRFn  =  1 

Serial  Interface 

SIO 

(except  mPD7506) 

SIOCR*-0 
IRFo/S*"0 

Start  Serial  I/O 
Operation 

0 
0 

0 
0 

11111 
110        0  1 

1 
1 

3F 
33 

2 

2 

TAMSIO 

(except  mPD7506) 

SI07-4*-A 
SIO3-0-(HL) 

Transfer  Accumu- 
lator and  Memory 
to  SIO  Shift  Register 

0 
0 

0 
0 

11111 
11111 

1 
0 

3F 
3E 

2 

2 

TSIOAM 

(except  mPD7506) 

A-SIO7-4 
HL-SIO3-0 

Transfer  SIO  Shift 
Register  to 
Accumulator  and 
Memory 

0 
0 

0 
0 

11111 
1110  1 

1 
0 

3F 
3A 

2 

2 

Parallel  I/O 

IP  port 

A-P(P3-0) 

Input  from  port, 
immediate  address 

0 

1 

0 

11111 
0       0       P3      P2  P1 

1, 

P0 

3F 
C0-CF 

2 

2 

IP1 

A-(1) 

Input  from  Port  1 

0 

110        0  0 

1 

71 

1 

1 

IP54 

A-P(5) 
(HL)-P(4) 

Input  Byte  from 
Ports  5  and  4 

0 
0 

11111 
1110  0 

1 

0 

3F 
38 

2 

2 

IPL 

A-P(L) 

Input  from  Port 
specified  by  L 

0 

110        0  0 

0 

70 

1 

1 

OP  port 

P(P3-0)-A 

Output  to  port, 
immediate  address 

0 

1 

11111 
1        0       P3      P2  P1 

1 

P0 

3F 
E0-EF 

2 

2 

OP3 

(except  mPD7506) 

P(3)-A 

Output  to  Port  3 

0 

110        0  1 

1 

73 

1 

1 

OP54 

P(5)-A 
P(4)-(HL) 

Output  Byte  to 
Ports  5  and  4 

0 
0 

11111 
11110 

1 

0 

3F 
3C 

2 

2 

OPL 

P(L)^A                                Output  to  port 
specified  by  L 

0 

110        0  1 

0 

72 

1 

1 

8P8L 

uPD82C43  I/O  Expander  Port      Reset  Port  Bit 
0-3-2)  bit  (ti^)>-0                  Specified  by  L 
,/PD82C43  I/O  Expander  Port      Set  Port  Bit 
(L3-2)  bit  <M<o)- 1                 Specified  by  L 

0 

1 

SI 

5D' 

l' 

CPU  Control 

HALT 

Enter  HALT  Mode 

0 
0 

0 
0 

11111 
11011 

1 
0 

3F 
36 

2 

2 

NOP 

No  operation 

0 

0 

00000 

0 

00 

1 

1 

STOP 

Enter  STOP  Mode 

0 
0 

0 
0 

11111 
11011 

1 
1 

3F 
37 

2 

2 

Development  Tools 

For  software  development,  editing,  debugging,  and 
assembly  into  object  code,  the  NDS  Development 
System,  designed  and  manufactured  by  NEC 
Electronics  U.S.A.,  Inc.,  is  available.  Additionally,  for 
systems  supporting  either  the  ISIS-II  ( ©Intel  Corp.), 
CP/M  (©Digital  Research  Corp.)  operating  systems,  or 
Fortran  IV  ANSI  1966  V3.9,  the  ASM 75  Cross- 
Assembler  is  available. 

Once  software  development  is  complete,  the  code  can 
be  completely  evaluated  and  debugged  with  hardware 
by  the  Evakit-7500  Evaluation  Board.  Available  options 
include  the  Evakit-7500-LCD  LCD  driver  board  (for  the 
MPD7501,  juPD7502,  and  ^PD7503),  Evakit-7500-VFD 
Vacuum  Fluorescent  Display  driver  board  (for  the 
jiPD7508A  and  ^PD7519),  and  the  Evakit-7500-RTT 
Real  Time  Tracer.  The  SE-7502  System  Emulation 
Board  will  emulate  complete  functionality  of  the 

3 


|uPD7501,  ^PD7502,  or  /iPD7503  for  demonstrating  your 
final  system  design.  The  SE-7508  System  Emulation 
Board  will  emulate  complete  functionality  of  the 
/iPD7506,  ^PD7507,  MPD7507S,  mPD7508,  or  ^PD7508A 
for  demonstrating  your  final  system  design.  All  of  these 
boards  take  advantage  of  the  capabilities  of  the 
/uPD7500  Rom-less  evaluation  chip  to  perform  their 
tasks. 

Complete  operation  details  on  any  /iPD7500  Series 
CMOS  4-Bit  Microcomputer  can  be  found  in  the 
^PD7500  Series  CMOS  4-Bit  Microcomputer  Technical 
Manual. 


7500DS-REV1  -7-83-TRIUM-CAT 

-34 


#jJ*D7501 
CMOS  4-BIT  SINGLE  CHIP 


WW 


MICROCOMPUTER  WITH  LCD 

"ilk  X% 


CONTROLLER/DRIVER 


Pin  Identification 


NEC 


Description 

The  jiPD7501  is  a  CMOS  4-bit  single  chip  microcom- 
puter which  has  the  ^PD750x  architecture. 

The  fiPD7501  contains  a  1024  x  8-bit  ROM,  and  a  96  x 
4-bit  RAM. 

The  jiPD7501  contains  two  4-bit  general  purpose 
registers  located  outside  RAM.  The  subroutine  stack  is 
implemented  in  RAM  for  greater  nesting  depth  and  flex- 
ibility, providing  such  operations  as  the  pushing  and 
popping  of  register  values.  The  mPD7501  typically  exe- 
cutes 63  instructions  of  the  ^PD7500  series  "B" 
instruction  set  with  a  10jus  instruction  cycle  time. 

The  /4PD7501  has  two  external  and  two  internal  edge- 
triggered  testable  interrupts.  It  also  contains  an  8-bit 
timer/event  counter  and  an  8-bit  serial  interface  to  help 
reduce  software  requirements.  The  on-board  LCD  con- 
troller/driver supervises  all  of  the  timing  required  by  the 
24  Port  S  segment  drivers  and  the  4  Port  COM  back- 
plane drivers,  for  either  a  12-digit  7-segment  quadri- 
plexed  LCD,  or  an  8-digit  7-segment  triplexed  LCD. 
The  fiPD7501  provides  24  I/O  lines  organized  into  the 
4-bit  input/serial  interface  Port  0,  the  4-bit  input  Port  1 , 
the  4-bit  output  Port  3,  and  the  4-bit  I/O  Ports  4,  5,  and 
6.  It  is  manufactured  with  a  low  power  consumption 
CMOS  process,  allowing  the  use  of  a  single  power  sup- 
ply between  2.7V  and  5.5V.  Current  consumption  is 
less  than  900^A  maximum,  and  can  be  lowered  much 
further  in  the  HALT  and  STOP  power-down  modes.  The 
HPD7501  is  available  in  a  space-saving  64-pin  flat 
plastic  package. 

The  jiPD7501  is  upward  compatible  with  the  jiPD7502 
and  the  jl(PD7503. 


Pin 

Function 

No. 

Symbol 

1 

NC 

No  connection. 

2-4,  64 

P33-P30 

4-bit  latched  tri-state  output  Port  3  (active  high). 

5 

P03/Sl 

4-bit  input  Port  0/serial  I/O  interface  (active  high). 

7 
55 

PO2/SO 

PO^fCK 

POq/INT! 

This  port  can  be  configured  either  as  a  parallel  input  port, 
or  as  the  8-bit  serial  I/O  Interface,  Under  control  of  the 
serial  mode  select  register.  The  Serial  Input  SI  (active 
high),  Serial  Output  SO  (active  low),  and  the  Serial  Clock 
SCK  (active  low)  used  for  synchronizing  data  transfer, 
comprise  the  8-bit  serial  I/O  interface.  Line  P00  is  always 
shared  with  external  interrupt  INT-j. 

8-11 

P63-P60 

4-bit  input/latched  tri-state  output  Port  6  (active  high), 
individual  lines  can  be  configured  either  as  inputs  or  as 
outputs  under  control  of  the  Port  6  mode  select  register. 

12-15 

P53-P50 

4-bit  input/latched  tri-state  output  Port  5  (active  high).  Can 
also  perform  8-bit  parallel  I/O  in  conjunction  with  Port  4. 

16-19 

P43-P40 

4-bit  input/latched  tri-state  output  Port  4  (active  high).  Can 
also  perform  8-bit  parallel  I/O  in  conjunction  with  Port  5. 

20,  21 

X2, 

Crystal  clock/external  event  input  Port  X  (active  high).  A 
crystal  oscillator  circuit  is  connected  to  input  X-j  and  out- 
put X2  for  crystal  clock  operation.  Alternatively,  external 
event  pulses  are  connected  to  input  Xi  while  output  X2  is 
left  open  for  external  event  counting. 

22 

VSS 

Ground. 

23-25 

VLCD3»  VLCD2' 
VLCD! 

LCD  bias  voltage  supply  inputs  to  LCD  voltage  controller. 
Apply  appropriate  voltages  from  a  voltage  ladder  con- 
nected across  VDD. 

26,  58 

vDd 

Power  supply  positive.  Apply  single  voltage  ranging  from 
2.7V  to  5.5V  for  proper  operation. 

27-30 

COM3-COM0 

LCD  backplane  driver  outputs. 

31-54 

s23-s0 

LCD  segment  driver  outputs. 

56 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse  initializes 
MPD7501  after  power-up. 

57,  59 

CL,,  CL2 

System  clock  Input  (active  high).  Connect  82kQ  resistor 
across  CL1  and  CL2,  and  connect  33pF  capacitor  from 
CLi  to  Vgs-  Alternatively,  an  external  clock  source  may 
be  connected  to  CL-j,  whereas  CL2  is  left  open. 

60-63 

P13-P10 
(PI0/INT0) 

4-bit  input  Port  1  (active  high).  Line  P10  is  also  shared 
with  external  interrupt  INTq. 

Pin  Configuration 


POo/'NTt  C 
RESET  C 


1  40  39  38  37  36  35  34  33 


O   MPD7501  O 

O 

S    6    7     8    9   10  11  12  13  14  15  16  17  19 


ZIS22 
ZJS23 
^|COM0 


ZJCOMi 

13  com3 

ZJV0D 
rjVt-CD, 
VLCD2 
=3VLCD3 

Zlvss 


•  *  *  *  I  €  £  i  i  i  i  £  £  £  £  £  i 


Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Power  Supply  Voltage,  Vqd 

-0.3V  to  +7.0V 

All  Input  and  Output  Voltages 

-0.3VtoVDD  +03V 

Output-Current  (Total,  All  Output  Ports) 

•OH  =  -20mA 

Iql  =  30mA 

*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


Rev/1 
3-35 


jkPD7501 

Block  Diagram 


P02/S0 


Count 
Clock 
Generator 


Clock 
Control 
Circuit 


LCDCL 


Timer/Event 
Counter 


PO0/INT1  INT0/P10 


Test 
Controller 


INTs 


Serial  I/O 
Interface 


Tt     Tt  iT 


H 


10-Bit  Program  Counter 


Program  Memory 
1024  x  8-Bit  ROM  foPD7501) 


ALU 


A  (4) 


General  Registers 


Instruction 
Decoder 


H(4)  I  L(4) 


Stack  Pointer  (7) 


Data  Memory 
96  x  4-B*  RAM  (MPD7501) 


r  r 


System 
Clock 
Generator 


1  r 


CL1  CL2 


Standby 
Control 


LCD  Controller/Driver 


Port  0 
Buffer 


PO0-PO3 


Port 
Buffer 


1  A 


/I  K        Port  4 

\  j/       Buffer  Y~/ 


"A       Port  3 
i  Latch 
-/  Buffer 


3 


P4Q-P43 


/  \        Port  5 

'  )  Latch 
\ — ^  Buffer 


Port  6 

k  1  Latch 
Vy  Bu,,er 


P60-P63 


RESET        VDD  VSS 


VLCD1.  S0-S23  COM0-COM3 

VLCD2- 

VLCD3 


3-36 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  2.7V  to  5.5V 


MPD7501 


Limit* 


Parameter 

Symbol 

Mfn 

Tjfp 

Max 

Unit 

Test  Conditions 

0.7  VDD 

vDd 

All  Inputs  Other  than  CL-,,  Xt 

Input  Voltage  High 

V|H2 

vDD-0.5 

vDd 

V 

CL^ 

V|HDR 

0.9VDDdr 

vDDdr+o.2 

RESET,  Data  Retention  Mode 

Input  Voltage  Low 

v.Ll 

0 

0  3  VDD 

V 

All  Inputs  Other  than  CLi,  X1 

V'L2 

0 

0.5 

CLlX, 

Input  Leakage  Current  High 

'LIH1 

3 

MA 

All  Inputs  Other  than  CL-j,  X-, 

V|  =  Vqq 

'«-lH2 

10 

Input  Leakage  Current  Low 

>LIL1 

-3 

nA 

All  Inputs  Other  than  CL1t  X1 

V|  =  OV 

'LI,, 

-10 

CL^ 

Output  Voltage  High 

V0H 

vDD  -  1-0 

V 

Vqq  =  5V  ±  10%,  l0H  =  -1.0  mA 

VDD  -  0.5 

VDD  =  2.7V  to  5.5V,  l0H  =  -100  mA 

Output  Voltage  Low 

Vol 

0.4 

V 

VDD  =  5V  ±  10%,  l0L  =  1.6  mA 

0.5 

VDD=  2.7V  to  5.5V,  l0L  =  400  mA 

Output  Leakage  Current  High 

'loh 

3 

MA 

v0  =  vDD 

Output  Leakage  Current  Low 

'lol 

-3 

ma 

v0  =  ov 

RCOM 

5 

WUMq  tO  IAJM3,  £.fV  S  Vlcd  Vqq 

Vqq  =  5V  ±  10% 

Output  ImpodsncG 

5 

Vqq  =  2.7V  to  5.5V 

RS 

20 

kQ 

&q  to  &23>        *  VLCD  ^  VDD 

Vqq  =  5V  ±  10%  | 

20 

Vqq  =  2.7V  to  5.5\| 

Supply  Voltage 

VDDDR 

2.0 

V 

Data  Retention  Mode 

'DD! 

300 

900 

Normal  Operation 

Vqq  =  5V  ±  10%  1 

150 

400 

Vqq  =  3V  ±  10% 

Supply  Current 

'dd2 

2 

20 

Stop  Mode,  X1  =  0V 

Vqq  =  5V  ±  10% 

0.5 

10 

MA 

Vqq  =  3V  ±  10% 

'dddr 

0.4 

10 

Data  Retention  Mode 

VDDDR  -  2.0V 

AC  Characteristics 

Ta  a  -10°Cto  +70°C,  VDD  =  2.7V  to  5.5V 


Limit* 

Parameter 

Symbol 

Mfn 

Typ 

Max 

Unit 

Test  Conditions 

120 

200 

280 

R  a  82  kQ  ±  2% 
CL1)CL2  C  =  33PF±5% 

VDD 

5V  ±  10% 

tec 

60 

100 

130 

R/C  Clock  r  _  150  kQ  ±  2% 

vDd 

3V  ±  10% 

System  Clock  Oscillation  Frequency 

60 

180 

KHz 

C  =  33  pF  ±  5% 

Vqq 

2.7V  to  5.5V 

*c 

10 

200 

300 

CL1f  External  Clock 

vDd 

5V  ±  10% 

10 

135 

vDd 

2.7V  to  5.5V 

System  Clock  Rise  and  Fall  Times 

tCR'  *CF 

0.2 

MS 

CL-),  External  Clock 

System  Clock  Pulse  Width 

lCH>  *CL 

1.5 

50 

V* 

CL-| ,  External  Clock 

vDd 

5V  ±  10% 

3.5 

50 

Vdd 

2.7V  to  5.5V 

fXX 

25 

32 

50 

X1 ,  X2  Crystal  Oscillator 

Counter  Clock  Oscillation  Frequency 

0 

300 

KHz 

X1 ,  External  Pulse  Input 

vDd 

5V  ±  10% 

0 

135 

vDd 

2.7V  to  5.5V 

Counter  Clock  Rise  and  Fall  Times 

*XR>  *XF 

0.2 

fiS 

X-) ,  External  Pulse  Input 

Counter  Clock  Pulse  Width 

tx„.txL 

1.5 

MS 

X-j ,  External  Pulse  Input 

vDd 

5V  ±  10% 

3.5 

vDd 

2.7V  to  5.5V 

4.0 

SCK  is  an  input 

vDd 

5V  ±  10% 

SCK  Cycle  Time 

*KCY 

7.0 

vDd 

2.7V  to  5.5V 

6.7 

MS 

SCK  is  an  output 

vDd 

5V  ±  10% 

14.0 

vDd 

2.7V  to  5.5V 

1.8 

SCK  is  an  input 

vDd 

5V  ±  10% 

SCK  Pulse  Width 

^H'^L 

3.3 

vDd 

2.7v  to  5.5V 

3.0 

MS 

SCK  is  an  output 

vdd 

5V  ±  10% 

6.5 

vdd 

2.7V  to  5.5V 

SI  Setup  Time  to  SCKt 

lS\K 

300 

ns 

SI  Hold  Time  after  SCKt 

*KSI 

450 

ns 

SO  Delay  Time  after  SCK1 

lKSO 

850 

ns 

Vqq  =  5V  ±  10% 

1200 

Vqq  =  2.7V  to  5.5V 

|NT0  Pulse  Width 

10 

MS 

INT1  Pulse  Width 

MS 

RESET  Pulse  Width 

*RSh>  *rsl 

10 

MS 

RESET  Setup  Time 

tSRS 

0 

ns 

RESET  Hold  Time 

*HRS 

0 

ns 

3-37 


MPD7501 

Capacitance 

Ta  =  25  °C,  Vdd  =  OV 


Umlf 

Test 
Conditions 

Parameter 

Symbol  1 

Win     Typ  Max 

Unit 

Input  Capacitance 

C| 

15 

pF 

f  >  1  MHz 

Output  Capacitance 

c0 

15 

pF 

Unmeasured  pins 

Input/Output  Capacitance 

Cl/O 

15 

PF 

returned  to  Vgg 

Timing  Waveforms 

Clocks 


*CF  — 


*XF-~ 


«CL" 


J 


-  V,(,H 

-  V*L 


-V,j,L 


Serial  Interface 

SCK  


-tKCY- 


Valid 
Input  Data 


1 


" — ^SO  ~~ 


_A_ 


Valid  Output  Data 


X 


—  V|H 

—  V|L 


—  V|L 


~ — V|H 
V|L 


External  Interrupts 

INTq  


—  V|H 

—  V,L 


—  V,H 

—  V|L 


Reset 


V 


—  V|H 
V|L 


Data  Retention  Mode 

VDD  


^SRS"*  \ 


-Data  Retention  Mode- 


'JhrsH 


3-38 


_  v,H 

=  "«HDDDRR 
_—  V||_ 


MPD7501 


Operating  Characteristics 

Typical,  Ta  =  25°C 


Supply  Current 
vs 

Supply  Voltage  (Note  © ) 


Supply  Current 
vs 

Supply  Voltage  (Note  (2)) 


2  3  4  5   1  1  S= 

Supply  Voltage  VDD  (V)  2  3  4 

Supply  Voltage  Vqd  (V) 


Notes: 

®  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 
®  Only  crystal  oscillator  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 


3-39 


juPD7501 

Operating  Characteristics  (Cont.) 
Typical,  Ta  =  25  °C 


System  Clock  Oscillation  Frequency 
vs 

Resistance 


|  CL2     CL1  | 

C  =  33pF  : 
i 

r 

Vqd  =  5V 

VDD  =  3V 

U>  

50  100  200 

Resistance  R  (K  ohms) 


System  Clock  Oscillation  Frequency 
vs 

Supply  Voltage 


|  CL2  C 

n  i 

.  C 

"  =  33pF 

R  =  82kQ 

R  =  160kQ 

Supply  Voltage  VDD  (V) 


Recommended  R  and  C  Values  for  the 
System  Clock  Oscillator  Circuit 


Ta  =  -10-  +70°C 


Supply  Voltage  Range 

Recommended  Values 

Frequency  Range 
(kHz) 

Mm      Typ  Max 

R 

C 

Min 

Typ 

Max 

4.5V  <  VDD  <  6V 

82kfi  ±  2% 

33pF  ±  5% 
(|dC/°C|  <  60  ppm) 

150 

250 

2.7V  <  VDD  <  6V 

160kfi  ±  2% 

33pF  +  5% 
(|dC/°C|  <  60  ppm) 

75 

135 

VDD  =  3V  ±  10% 

160kO  ±  2% 

33pF  ±  5% 
(|dC/°C|  <  60  ppm) 

75 

120 

2.5V  <  VDD  <  6V 

240kO  ±  2% 

33pF  ±  5% 
(|dC/°C|  <  60  ppm) 

50 

85 

2.5V  <  VDD  <  3.3V 

240kfi  ±  2% 

33pF  ±  5% 
(|dC/°C|  <  60  ppm) 

50 

80 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Miniflat,  |xPD7501G 


3-40 


7501 DS-REV1-7-83-CAT 


MFC  MPD7502 

MPD7503 
CMOS  4-BIT  SINGLE  CHIP 
MICROCOMPUTERS  WITH  LCD 
CONTROLLER/DRIVER 


Description 

The  fiPD7502  and  the  jiPD7503  are  pin-compatible 
CMOS  4-bit  single  chip  microcomputers  which  have  the 
same  juPD750x  architecture. 

The  /iPD7502  contains  a  2048  x  8-bit  ROM,  and  a  128  x 
4-bit  RAM.  The  |iPD7503  contains  a  4096  x  8-bit  ROM, 
and  a  224  x  4-bit  RAM. 

Both  the  pcPD7502  and  the  ^PD7503  contain  four  4-bit 
general  purpose  registers  located  outside  RAM.  The 
subroutine  stack  is  implemented  in  RAM  for  greater 
nesting  depth  and  flexibility,  providing  such  operations 
as  the  pushing  and  popping  of  register  values.  The 
MPD7502  and  the  jiPD7503  typically  execute  92  instruc- 
tions of  the  /iPD7500  series  "A"  instruction  set  with  a 
10fiS  instruction  cycle  time. 

The  jiPD7502  and  the  ^PD7503  have  two  external  and 
two  internal  edge-triggered  hardware  vectored  inter- 
rupts. They  also  contain  an  8-bit  timer/event  counter 
and  an  8-bit  serial  interface  to  help  reduce  software 
requirements.  The  on-board  LCD  controller/driver 
supervises  all  of  the  timing  required  by  the  24  Port  S 
segment  drivers  and  the  4  Port  COM  backplane  drivers, 
for  either  a  12-digit  7-segment  quadriplexed  LCD,  or  an 
8-digit  7-segment  triplexed  LCD. 
Both  the  jiPD7502  and  the  /iPD7503  provide  23  I/O 
lines,  organized  into  the  3-bit  input/serial  interface 
Port  0,  the  4-bit  input  Port  1,  the  4-bit  output  Port  3, 
and  the  4-bit  I/O  Ports  4,  5,  and  6.  They  are  manufac- 
tured with  a  low  power  consumption  CMOS  process, 
allowing  the  use  of  a  single  power  supply  between  2.7V 
and  5.5V.  Current  consumption  is  less  than  900^A  max- 
imum, and  can  be  lowered  much  further  in  the  HALT 
and  STOP  power-down  modes.  The  jLtPD7502  and  the 
|liPD7503  are  available  in  a  space-saving  64-pin  flat 
plastic  package. 

The  jbtPD7502  is  downward  compatible  with  the 
/iPD7501 . 

Pin  Configuration 


Pin  Names 


Pin  No.      Symbol  Function 

1 

NC 

No  connection. 

2-4,  64 

P33-P30 

4-bit  latched  tristate  output  Port  3  (active  high). 

5 

P03/Sl 

3-bit  input  Port  0/serial  I/O  interface  (active  high) 

6 

7 

P02/SO 
PO^SCK 

This  port  can  be  configured  either  as  a  parallel  input  port, 
or  as  the  8-bit  serial  I/O  Interface,  under  control  of  the  serial 
mode  select  register.  The  Serial  Input  SI  (active  high),  Serial 
Output  SO  (active  high),  and  the  Serial  Clock  SCK  (active 
low)  used  for  synchronizing  data  transfer,  comprise  the  8-bit 
serial  I/O  interface 

8-11 

P63-P6() 

4-bit  input/latched  tristate  output  Port  6  (active  high).  Indi- 
vidual lines  can  be  configured  either  as  inputs  or  as  outputs 
under  control  of  the  Port  6  mode  select  register 

12-15 

P53-P50 

4-bit  input/latched  tristate  output  Port  5  (active  high).  Can 
also  perform  8-bit  parallel  I/O  in  conjunction  with  Port  4. 

16-19 

P43-P40 

4-bit  input/latched  tristate  output  Port  4  (active  high).  Can 
also  perform  8-bit  parallel  I/O  in  conjunction  with  Port  5 

20,  21 

x2,  X1 

Crystal  clock/external  event  input  Port  X  (active  high).  A  ' 
crystal  oscillator  circuit  is  connected  to  input  X-j  and  output 
X2  for  crystal  clock  operation.  Alternatively,  external  event 
pulses  are  connected  to  input  X1  while  output  X2  is  left 
open  for  external  event  counting. 

22 

vSs 

Ground 

23-25 

VLCD3-  VLCD2< 
VLCD! 

LCD  bias  voltage  supply  inputs  to  LCD  voltage  controller. 
Apply  appropriate  voltages  from  a  voltage  ladder  connected 
across  Vqd. 

26,  58 

vDd 

Power  supply  positive  Apply  single  voltage  ranging  from 
2.7V  to  5  5V  for  proper  operation. 

27-30 

COM3-COM0 

LCD  backplane  driver  outputs. 

31-54 

S23-S0 

LCD  segment  driver  outputs. 

55 

INT-j 

External  Interrupt  INT-J  (active  high).  This  is  a  rising  edge- 
triggered  interrupt 

56 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse  initializes 
MPD7502  or  ^PD7503  after  power-up. 

57,  59 

CL^  CL2 

System  clock  input  (active  high).  Connect  82kQ  resistor 
across  CL-j  and  CL2,  and  connect  33pF  capacitor  from  CL1 
to  VSS'  Alternatively,  an  external  clock  source  may  be  con- 
nected to  CL-|,  whereas  CL2  is  left  open. 

60-63 

P13-P10 
(PI0/INT0) 

4-bit  input  Port  1  (active  high).  Line  P10  is  also  shared  with 
external  interrupt  INT0,  which  is  a  rising  edge-triggered 
interrupt. 

Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Power  Supply  Voltage,  Vqq 

-0.3V  to  +7.0V 

All  Input  and  Output  Voltages 

-0.3VtoVDD  +0.3V 

Output-Current  (Total,  All  Output  Ports) 

'OH  =  -20mA 

IQL  =  30mA 

*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 

Rev/1 
3-41 


MPD7502/7503 
Block  Diagram 


P01/SCK  p03/s, 
P02/SO 


INT1       into/  Pi0 


Count 
Clock 
Generator 


Clock 
Control 
Circuit 


FT 


Timer/Event 
Counter 


INTj 


Interrupt 
Control 


INTs 


Serial  I/O 
Interface 


Tt     Tl  U 


H 


Program  Counter 

11 -  Bit  (mPD7502) 

12-  Bit  (MPD7503) 


Program  Memory 
2048  X  8-Bit  ROM  (MPD7502) 
4096  x  8-Bit  ROM  (MPD7503) 


CL1  CL2 


General  Registers 


3 


r  r 

System 
Clock 
Generator 

Standby 
Control 

Instruction 
Decoder 


E(4) 


Stack  Pointer 


Data  Memory 
128  x  4-Bit  RAM  (MPD7502) 
224  x  4-Bit  RAM  (MPD7503) 


LCD  Controller/Driver 


Port  0 
Buffer 


Port  1 
Buffer 


A-N 
W 


AA 
NrV 


RESET  VDD 


VLCDi- 
VLCD2. 
VLCD3 


S0-S23  COM0-COM3 


Port  3 
Latch 
Buffer 


Port  5 
Latch 
Buffer 


Port  6 
Latch 
Buffer 


P00-P03 

P10/INT0 
P10-P13 


3 


P3Q-P33 


\| — y       Buffer        \j  / 


ft 


Capacitance 

Ta  =  25  °c,  vDD  =  ov 


Limits 

Test 

Parameter  Symbol 

M/n    Typ  Max 

Unit 

Conditions 

Input  Capacitance  C( 

15 

pF 

f  =  1  MHz, 

Unmeasured  pins 
returned  to  Vss 

Output  Capacitance  C0 

15 

PF 

Input/Output  Capacitance  C)/0 

15 

PF 

3-42 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  2.7  to  5.5V 


MPD7502/7503 


Umlta 


Parameter 

 Symbo'  

Typ 

Unit 

V|H1 

0.7  VDD 

Vdd 

All  Inputs  Other  than  CL<| ,  X-j 

Input  Voltage  High 

VIH2 

VDD-0.5 

Vdd 

V 

CLi.X! 

V'HDR 

0.9VDDdr 

VdDdr+0.2 

RESET,  Data  Retention  Mode 

Input  Voltage  Low 

VIL1 

0 

0.3  vDD 

V 

All  Inputs  Other  than  CLj,  X1 

V,L2 

0 

0.5 

CLi.X, 

Input  Leakage  Current  High 

'"m 

3 

yA 

All  Inputs  Other  than  CL1(  X-\ 

vi  =  vDD 

'lih2 

10 

CL^X! 

Input  Leakage  Current  Low 

"lil1 

-3 

ma 

All  Inputs  Other  than  CLj,  X1 

V,  =  ov 

'lil2 

-10| 

CL^X! 

rtiitmit  V/nltnnA  UlnH 

v/uipui  voiiagv  mgn 

V0H 

VDD  -  1.0 

y 

vDd  =  5V  ±  10%,  Iqh  =  -1.0mA 

VDD  -  0.5 

VDD  =  27V  to  5.5V,  Iqh  ■  -100  mA 

Output  Voltage  Low 

vol 

0.4 

VDd  =  5V  ±  10%,  lOL  =  1.6  mA 

0.5 

v 

VDD  =  2.7V  to  5.5V,  lOL  =  400  »JV 

Output  Leakage  Current  High 

•loh 

3 

mA 

VO  =  VDD 

Output  Leakage  Current  Low 

•lol 

-3 

ma 

vo  =  ov 

"COM 

5 

vDd  ■  5V  ±  10% 

Output  Impedance 

5 

kQ 

COMq  to  COM3,  2.7V  <  Vlcd  <  Vdd  ~ 

VDd  =  2.7V  to  5.5V 

RS 

20 

Vdd  =  sv  ±  10%  I 

20 

S0  to  S23,  2.7V  <  VLCD  <  VDd 

VDD  =  2.7V  to  5.5V  | 

Supply  Voltage 

vd°dr 

nntfi  R  At  Ant  inn  UaHa 

300 

900 

vDd  =  sv  ±  10%  I 

lDD1 

150 

400 

Normal  Operation 

vDd  =  av  ±  10% 

Supply  Current 

>OD2 

2 

20 

ma 

vdd  =  sv  ±  10% 

0.5 

10 

Stop  Mode,  X,  =  0V 

Vdd  =  3V  ±  10% 

'DDDR 

0.4 

10 

Data  Retention  Mode 

VddDr  =  2.ov 

AC  Characteristics 

Ta  =  -10°Cto  +70°C,  Vdd  =  2.7Vto5.5V 


Limits 


Parameter 

Symbol 

Typ 

Max 

Unit 

Test  Condition 

s 

120 

200 

280 

R  =  82  kQ  ±  2% 
C  =  33  pF  ±  5% 

vDd 

5V  ±  10% 

fcc 

60 

100 

130 

CL1(  CL2  R  =  160  kQ  ±  2% 

vdd 

3V  ±  10% 

System  Clock  Oscillation  Frequency 

60 

180 

kHz 

R/C  Clock  C  =  33  pF  ±  5% 

vDd 

2.7V  to  5.5V 

10 

200 

300 

CLr,  External  Clock 

vDd 

5V  ±  10% 

*c 

10 

135 

vDd 

2.7V  to  5.5V 

System  Clock  Rise  and  Fall  Times 

tCR^CF 

0.2 

MS 

CL17  External  Clock 

System  Clock  Pulse  Width 

tCH.tCL, 

1.5 

50 

CL1?  External  Clock 

vDd 

5V  ±  10% 

3.5 

50 

MS 

vDd 

2.7V  to  5.5V 

'xx 

25 

32 

50 

Xi,X2  Crystal  Oscillator 

Counter  Clock  Oscillation  Frequency 

*x 

0 

300 

kHz 

X-|,  External  Pulse  Input 

vDd 

5V  ±  10% 

0 

135 

vDd 

2.7V  to  5.5V 

Counter  Clock  Rise  and  Fall  Times 

0.2 

MS 

X-| ,  External  Pulse  Input 

Counter  Clock  Pulse  Width 

*XH'*XL 

1.5 

X1 ,  External  Pulse  Input 

vDd 

5V  ±  10% 

3.5 

MS 

vDd 

2.7V  to  5.5V 

4.0 

SCK  is  an  input 

vDd 

5V  ±  10% 

SCK  Cycle  Time 

!KCY 

7.0 

vDd 

2.7V  to  5.5V 

6.7 

MS 

SCK  is  an  output 

vDd 

5V  ±  10% 

14.0 

vDd 

2.7V  to  5.5V 

1.8 

SCK  is  an  input 

vDd 

5V  ±  10% 

SCK  Pulse  Width 

*KH'*KL 

3.3 

vDd 

2.7v  to  5.5V 

3.0 

MS 

SCK  is  an  output 

vDd 

5V  ±  10% 

6.5 

vDd 

2.7V  to  5.5V 

SI  Setup  Time  to  SCKt 

*SIK 

300 

ns 

SI  Hold  Time  after  SCKt 

lKSI 

450 

ns 

SO  Delay  Time  after  SCK1 

*KSO 

850 

Vdd  =  5V  ±  10% 

1200 

ns 

Vdd  =  2.7V  to  5.5V 

INT0  Pulse  Width 

tlOH'^OL 

10 

MS 

INT-,  Pulse  Width 

tl1H,t|1L 

MS 

RESET  Pulse  Width 

tRSH>*RSL 

10 

MS 

3-43 


MPD7502/7503 

Timing  Waveforms 


Clocks 


*CL- 


*CR 


Serial  Interface 


-  *KCY  - 


-tSIK- 


Valid 
Input  Data 


J 


—  lKSO  . 


X 


Valid  Output  Data 


X 


-  V|H 

-  V|L 


—  V|H 
~—  Vil 


~  V|H 


External  Interrupts 

INTO  


t'OH 


 V|H 

—  V|L 


*"1H  - 


—  V|H 

—  V|L 


Reset 


/ 


tRSH 


—  V|H 
_—  V|L 


Data  Retention  Mode 

vdd  


*-*SRS  — 


-Data  Retention  Mode~ 


^HRS^J 


__  VIH 
-^DDD 
=  y.lHnF 


3-44 


Operating  Characteristics 

Typical,  Ta  =  25°C 

Supply  Current 
vs 

Supply  Voltage  (Note  0 ) 


Supply  Voltage  Vqd  (V) 


MPD7502/7503 


?  10 


Supply  Current 
vs 

Supply  Voltage  (Note  (2) ) 


|    X1       X2  | 

Ci  : 
> 

R1 
Ci 

HTJH 

i  r 

=  330kQ 
=  20pF 

—it— 

C2  =  30pF 
Xta|  =  32.768KHZ 

Supply  Voltage  Vdd  (V) 


Notes: 

®  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active, 
(g)  Only  crystal  oscillator  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 


3-45 


MPD7502/7503 

Operating  Characteristics  (Cont.) 

Typical,  Ta  =  25°C 


System  Clock  Oscillation  Frequency 
vs 

Resistance 


50  100  200 

Resistance  R  (K  ohms) 


System  Clock  Oscillation  Frequency 
vs 

Supply  Voltage 


8  100 


|  CL2  C 

li  i 

.  c 

'  =  33pF 

— =~ 

R  =  82kQ 

R  =  160kQ 

Supply  Voltage  Vqd  (V) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Miniflat,  >jlPD7502G/03G 


3-46 


7502/7503DS-REV1-7-83-TRIUM-CAT 


SEC 


MPD7506 
CMOS  4-BIT  SINGLE  CHIP 
MICROCOMPUTER 


Description 

The  jitPD7506  is  a  CMOS  4-bit  single  chip  microcom- 
puter which  has  the  ^PD750x  architecture. 
The  /iPD7506  contains  a  1024  x  8-bit  ROM,  and  a  64  x 
4-bit  RAM. 

The  /iPD7506  contains  two  4-bit  general  purpose 
registers  located  outside  RAM.  The  subroutine  stack  is 
implemented  in  RAM  for  greater  nesting  depth  and  flex- 
ibility, providing  such  operations  as  the  pushing  and 
popping  of  register  values.  The  juPD7506  typically  ex- 
ecutes 58  instructions  of  the  juPD7500  series  "B"  in- 
struction set  with  a  10^s  instruction  cycle  time. 
The  fiPD7506  has  one  external  and  one  internal  edge- 
triggered  testable  interrupts.  It  also  contains  an  8-bit 
timer/event  counter  to  help  reduce  software 
requirements. 

The  fiPD7506  provides  22  I/O  lines,  organized  into  the 
2-bit  input  Port  0,  the  4-bit  output  Port  2,  and  the  4-bit 
I/O  Ports  1 ,  4,  5,  and  6.  It  is  manufactured  with  a  low 
power  consumption  CMOS  process,  allowing  the  use  of 
a  single  power  supply  between  2.7V  and  5.5V.  Current 
consumption  is  less  than  600^A  maximum,  and  can  be 
lowered  much  further  in  the  HALT  and  STOP  power- 
down  modes.  The  ^PD7506  is  available  either  in  a 
28-pin  dual-in-line  plastic  package,  or  in  a  space-saving 
52-pin  flat  plastic  package. 

The  juPD7506  is  upward  compatible  with  the  /iPD7507 
and  the  /iPD7507S. 

Pin  Configuration 


Pin  Configuration  (Cont.) 


Z  X  2  Q-   >  Z  >  Q. 

nnnnnnnnnnnnn 


39  38  37  36  35  34  33  32  31  30  29  28  27 


**  UJ 


P43  CZ  1 
X2  LZ  2 

P03/X1  cz  3 

P20/PSTB  CZ  4 

P21/PTOUT  CZ  5 

P22  CZ  6 

P23  C  7 

P60  cz  8 

P61  CZ  9 

P62  CZ 10 

P63  cz  11 

CM  C12 
CL2  CZ  13 

vdd  C1 14 


(Top  View) 



MPD 
7506C 


Z]  vss 

27  Zl  P42 
26  JZZD  P41 
P40 

PO0/INT0 
P53 
P52 

ZD  P51 

P50 

Z3  P13 
ZD  P12 
ZD  Pii 

P10 
ZD  RESET 


Rev/ 2 
3-47 


Pin  Names 

28-Pin 
DIP 

52-Pin 
Flat 

Symbol 

Function 

1,  25-27 

24,  29,  30,  34 

P40-P43 

4-bit  input/latched  tristate  output  Port  4  (active 
high).  Can  also  perforin  8-bit  parallel  I/O  in  con- 
junction with  Port  5. 

2,  3 

36,  41 

X2,P03/  X! 

Crystal  clock/external  event  input  Port  X  (active 
high).  A  crystal  oscillator  circuit  is  connected  to 
input  X-)  and  output  X2  for  crystal  clock  opera- 
tion. Alternatively,  external  event  pulses  are 
connected  to  input  X-|  while  output  X2  is  left 
open  for  external  event  counting.  Line  X-|  is 
always  shared  with  Port  0  input  P03. 

4-7 

42-45 

P20-P23 

PVPSTB 

P21/PT0UT 

4-bit  latched  tristate  output  Port  2  (active  high). 
Line  P2q  is  also  shared  with  PsfB> tne  Port  1 
output  strobe  pulse  (active  low).  Line  P2-)  is 
also  shared  with  Ptout>  the  timer-out  F/F 
signal  (active  high). 

8-11 

47-50 

P6Q-P63 

4-bit  input/latched  tristate  output  Port  6  (active 
high).  Individual  lines  can  be  configured  either 
as  inputs  or  as  outputs  under  control  of  the  Port 
6  mode  select  register. 

12,  13 

3,  5 

CL1f  CL2 

System  clock  input  (active  high).  Connect  120kQ 
resistor  across  CL-j  and  CL2.  Alternatively,  an 
external  clock  source  may  be  connected  to  CL-j , 
whereas  CL2  is  left  open. 

14 

7,  33 

vdd 

Power  supply  positive.  Apply  single  voltage 
ranging  from  2.7V  to  5.5V  for  proper  operation. 

15 

8 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse 
initializes  nPD7507  or  ^PD7508  after  power-up. 

16-19 

9-11,  16 

P10-P13 

4-bit  input/tristate  output  Port  1  (active  high). 
Data  output  to  Port  1  is  strobed  in  synchroniza- 
tion with  a  P2q/Pstb  pulse. 

20-23 

16-18,  21 

P50-P53 

4-bit  input/latched  tristate  output  Port  5  (active 
high).  Can  also  perform  8-bit  parallel  I/O  in  con- 
junction with  Port  4. 

24,  3 

23,  41 

P00/INT0 

2-bit  input  Port  0  (active  high).  Line  P00  is 
always  shared  with  external  interrupt  INT0 
(active  high).  Line  P03  is  always  shared  with 
crystal  clock/external  event  input  X1  (active 
high). 

28 

31 

vSs 

Ground. 

2 

1.  2,  4,  6 
12-15,  19,  20, 
25-28,  32, 
35,  37-40,  46, 
51,  52 

NC 

No  connection. 

MPD7506 
Block  Diagram 


PO3/X1    /  X2 


P00/INTo 


Count 
Clock 
Generator 

Clock 
Control 
Circuit 

Timer/Event 

Interrupt 

r 

Counter 

Controller 

H 


10-Blt  Program  Counter 


Program  Memory 
1024  x  8-Bit  ROM  (»iPD7506) 


r  t' 

System 
Clock 
Generator 

Standby 
Control 

3 


ins 


V 

ALU 


Instruction 
Decoder 


I    t  t 

RESET        VDD  Vss 


General  Registers 


H  (4)  I  L  (4) 


Stack  Pointer  (6) 


Data  Memory 
64  x  4-Bit  RAM  (MPD7506) 


c 

A  (4) 

Port  0 
Buffer 


M 
W 


Port  1 
Buffer 


to 


A 


\  )/       Buffer        \j  / 


Port  5 

1  j  Latch 
\j — j/  Buffer 


NrV 


Port  6 
Latch 
Buffer 


PO0-PO3 


Port  2   \ 

A  Latch  4  \ 
y        Buffer   / 


P20/PSTB, 
P21/PTOUT 


P4Q-P43 


00 


P60-P63 


Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Power  Supply  Voltage,  Vqd 

-0.3V  to  +7.0V 

All  Input  and  Output  Voltages 

-0.3VtoVoD  +0.3V 

Output-Current  (Total,  All  Output  Ports) 

•OH  =  -20mA 

IqL  =  32mA 

*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


Capacitance 

Ta  =  25°C,  VDD 


ov 


Symbol     Mfn  Typ 


Input  Capacitance 


Output  Capacitance 


c0 


Input/Output 
Capacitance 


cl/0 


Unmeasured  pins 
returned  to  Vgg  c 


3-48 


MPD7506 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD 


2.7V  to  5.5V 


Umlf 

Parameter 

Symbol 

Mfn 

Typ 

Max 

Unit 

Test  Conditions 

V|H 

0.7  VDD 

vDD 

All  Inputs  Other  than  CL1(  X-j 

Input  Voltage  High 

V|H2 

VDD-0.5 

vDd 

V 

CL1(X! 

V'HDR 

0.9VDDdr 

vDDdr+o.2 

RESET,  Data  Retention  Mode 

Input  Voltage  Low 

V|L 

0 

0.3  Vdd 

V 

All  Inputs  Other  than  CL,,  X1 

V,L2 

0 

0.5 

CL,,  X, 

Input  Leakage  Current  High 

'lih 

3 

MA 

All  Inputs  Other  than  CL1f  X1 

vi  -  vDD 

'lih2 

10 

CL^X, 

Input  Leakage  Current  Low 

'uL 

-3 

pA 

All  Inputs  Other  than  CLj,  X1 

V,  m  0V 

'lil2 

-10 

CL1t  X, 

Output  Voltage  High 

V0H 

VDD  -  1.0 

V 

VDD  -  5V  ±  10%,  l0H  -  -1.0mA 

VDD  -  0.5 

Vdd  x  2.7V  to  5.5V,  Iqh  -  -100mA 

Output  Voltage  Low 

Vol 

0.4 

Vqq  =  5V  ±  10<M»,  l0L  =  1.6mA 

0.5 

V 

VDD=  2.7V  to  5.5V,  Iql  =  «00mA 

Output  Leakage  Current  High 

'loh 

3 

ma 

v0  -  vDD 

Output  Leakage  Current  Low 

•lol 

-3 

ma 

v0  =  ov 

Supply  Voltage 

vw>dr 

2.0 

V 

Data  Retention  Mode 

lDD1 

200 

600 

vDd  =  sv  ±  10%. 

100 

300 

Normal  Operation 

vDd  =  sv  ±  10% 

Supply  Current 

'dd2 

1 

10 

MA 

vDd  -  5V  ±  10% 

0.3 

5 

Stop  Mode,  X-,  =  0V 

Vdd  =  3V  ±  10% 

'dddr 

0.3 

5 

Data  Retention  Mode 

VDDDR  -  2  0V 

AC  Characteristics 

Ta  =  -  io°c  to  +  70°c,  vDd 

=  2.7V  to  5.5V 

Limits 

Parameter 

Symbol 

Mln 

Typ 

Max 

Unit 

Test  Conditions 

120 

200 

260 

R  =  82  kQ  ±  2% 

Vdd 

=  5 V  ±  10% 

tec 

60 

100 

130 

kHz 

CL1t  CL2   R  =  160  kQ  ±  2% 

vdd 

=  3 V  ±  10% 

System  Clock  Oscillation  Frequency 

60 

180 

vdd 

=  2.7V  to  5.5V 

10 

200 

300 

CL1f  External  Clock 

vdd 

=  5V  ±  10% 

tc 

10 

135 

vdd 

=  2.7V  to  5.5V 

System  Clock  Rise  and  Fall  Times 

tCR.tCF 

0.2 

MS 

CL1t  External  Clock 

System  Clock  Pulse  Width 

1.5 

50 

CLi,  External  Clock 

vdd 

=  5V  ±  10% 

tCH.tCL 

3.5 

50 

MS 

vdd 

=  2.7V  to  5.5V 

*xx 

25 

32 

50 

X1,X2  Crystal  Oscillator 

Counter  Clock  Oscillation  Frequency 

0 

300 

kHz 

X-|,  External  Pulse  Input 

vdd 

=  5V  ±  10% 

*x  - 

0 

135 

vDd 

=  2.7V  to  5.5V 

Counter  Clock  Rise  and  Fall  Times 

tXR.tXF 

0.2 

MS 

X1;  External  Pulse  Input 

Counter  Clock  Pulse  Width 

1.5 

MS 

Xf,  External  Pulse  Input 

vDd 

=  5 V  ±  10% 

tXH'IXL 

3.5 

vdd 

=  2.7V  to  5.5V 

Port  1  Output  Setup  Time  to  P§TBt 

1/(2f^-800) 

VDD  =  5V  ±  10% 

lPST 

1/(2^-2000) 

ns 

VDD  *  2.7V  to  5.5V 

Port  1  Output  Hold  Time  after  P§TBt 

300 

350 

500 

ns 

Vdd  =  sv  ±  10% 

*STP 

300 

1500 

VDD  =  2.7V  to  5.5V 

P§fB  Pulse  Width 

1/(2ff800) 

Vdd  -  sv  ±  10% 

*swL 

1/(2f+-2000) 

ns 

VDd  =  2.7V  to  5.5V 

INT0  Pulse  Width 

10 

MS 

RESET  Pulse  Width 

tRSH.tRSL 

10 

MS 

3-49 


juPD7506 
Timing  Waveforms 

Clocks 


CM- 


tCf  - 


»CL- 


Output  Strobe 
pi0-pi3   


PSTB- 


-  *PST  - 


tsT, 


-  ^TP  - 


—  V|H 
Vil 


—  V|H 

—  Vil 


External  Interrupt 

INTO  


"1 


l«OL  " 


—  V|H 

—  V|L 


Reset 


■  !RSi 


-»RSu 


"  V|H 

-  vil 


Data  Retention  Mode 

VDD  


-^!SRS 


A 


-Data  Retention  Mode- 


/ -^HRS— I 


~  VILDR 


3-50 


Operating  Characteristics 

Typical,  Ta  =  25°C 


1  100 


Supply  Current 
vs 

Supply  Voltage  (Note  (T) ) 


I  CL1      CL2  I 
R 

F 

*  =  120kQ  . 

R  =  240kQ 

? 10 


Supply  Current 
vs 

Supply  Voltage  (Note  ®) 


MPD7506 


|    X1       X2  | 

Ci: 

; 

R1 
Ci 

I  f 

=  330kQ 
=  20pF 

C2  =  30pF 
Xta(  =  32.768KHZ 

Supply  Voltage  Vqd  (V) 


Supply  Voltage  Vdd  (V) 


System  Clock  Oscillation  Frequency 
vs 

Resistance 


System  Clock  Oscillation  Frequency 
vs 

Supply  Voltage 


I  CL2     CLj  I 


50  100  200 

Resistance  R  (K  ohms) 


i  4  5 

Supply  Voltage  Vdd  (V) 


Notes: 

0'  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active, 
(g)  Only  crystal  oscillator  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD7506C 
Plastic  Miniflat,  ^PD7506G 
Plastic  Shrinkdip,  |xPD7506CT 

3  -  51  7506DS-REV2-7-83-TRIUM-CAT 


Notes 


3-52 


SEC  MPD7507 

MPD7508 
CMOS  4-BIT  SINGLE  CHIP 
MICROCOMPUTERS 


Description 

The  fiPD7507  and  the  jiPD7508  are  pin-compatible 
CMOS  4-bit  single  chip  microcomputers  which  have  the 
same  ^PD750x  architecture. 

The  mPD7507  contains  a  2048  x  8-bit  ROM,  and  a  128  x 
4-bit  RAM.  The  mPD7508  contains  a  4096  x  8-bit  ROM, 
and  a  224  x  4-bit  RAM. 

Both  the  mPD7507  and  the  mPD7508  contain  four  4-bit 
general  purpose  registers  located  outside  RAM.  The  sub- 
routine stack  is  implemented  in  RAM  for  greater  nesting 
depth  and  flexibility,  providing  such  operations  as  the 
pushing  and  popping  of  register  values.  The  j*PD7507 
and  the  ^PD5708  typically  execute  92  instructions  of  the 
jiPD7500  series  "A"  instruction  set  with  a  10^s  instruc- 
tion cycle  time. 

The  fiPD7507  and  the  f*PD7508  have  two  external  and 
two  internal  edge-triggered  hardware  vectored  interrupts. 
They  also  contain  an  8-bit  timer/event  counter  and  an 
8-bit  serial  interface  to  help  reduce  software  requirements. 
Both  the  /iPD7507  and  the  f*PD7508  provide  32  I/O  lines 
organized  into  the  4-bit  input/serial  interface  Port  0,  the 
4-bit  input  Port  2,  the  4-bit  output  Port  3,  and  the  4-bit  I/O 
Ports  1 ,  4,  5,  6,  and  7.  They  are  manufactured  with  a  low 
power  consumption  CMOS  process,  allowing  the  use  of  a 
single  power  supply  between  2.7V  and  5.5V.  Current  con- 
sumption is  less  than  900jiA  maximum,  and  can  be 
lowered  much  further  in  the  HALT  and  STOP  power-down 
modes.  The  ^PD7507  and  the  jnPD7508  are  available  in 
either  a  40-pin  dual-in-line  plastic  package  or  in  a  space- 
saving  52-pin  flat  plastic  package. 

The  jaPD7507  is  downward  compatible  with  the  ^PD7506 
and  the  mPD7507S. 

Pin  Configuration 


o.  a.   o.  a.  z 


o  t-    in  it   o   it  o 

>    X     >    Q.    Z    Q-  Z 


X2d 
P20/PSTBC 
P21/PTOUTC 
P22d 
P23C 
P10C 
P1lC 
P12C 
P13C 
P30d 
P31C 
P32C 
P33C 
P70C 
P7iC 
P72C 
P73C 
RESET  □ 
CL1C 

vddC 


HPD7507C 
MPD7508C 


□  xi 

□  vss 

□  P43 

□  P42 

□  P41 

□  P40 

□  P53 

□  P52 

□  P51 

□  P50 

□  P63 

□  P62 

□  P61 

□  P60 

□  PO3/SI 

□  PO2/SO 

□  po1/SCR 

□  PO0/INT0 
22  □  INT1 

21  □  CL2 


NC  I 

3S 
40 

38  37 

36  35  34  33  32  31 

30  29  28  27 
26 

P41 

P10  I  ' 

41 

25 

P40 

P11  I  1 

42 

24 

P53 

P12  I  

43 

23 

P52 

P13  I  

44 

22 

P51 

NC  I  

P30  ' 

45 
46 

MPD7507G 
MPD7508G 

21 
20 

P5o 
P63 

P31  I 

47 

19 

P62 

P32  C= 

48 

18 

P61 

P33  I 

49 

17 

P60 

P70  C= 

50 

O 

16 

PO3/SI 

P71  I  

51 

15 

P02/SO 

P72  C= 

52 

1 

2  3 

4    5     6     7    8  9 

14 

10  11   12  13 

NC 

r-    o  \X  O 


Pin  Identification 


40-Pln 
DIP 

52-Pln 
Flat 

Symbol 

Function 

1,40 

32,  34 

X2>  X1 

Crystal  clock/external  event  input  Port  X  (active 
high).  A  crystal  oscillator  circuit  is  connected  to 
input  X-)  and  output  X2  for  crystal  clock  opera- 
tion. Alternatively,  external  event  pulses  are  con- 
nected to  input  Xi  while  output  X2  is  left  open 
for  external  event  counting. 

2-5 

36-39 

P20-P23 

P2o/PSTB 

P21/PT0UT 

4-bit  latched  tri-state  output  Port  2  (active  high). 
Line  P2q  is  also  shared  with  P§TB>  the  Port  1 
output  strobe  pulse  (active  low).  Line  P2-j  is  also 
shared  with  PTn,iT.  the  timer-out  F/F  signal 
(active  high).  UUI 

6-9 

41-44 

P10-P13 

4-bit  input/tri-state  output  Port  1  (active  high). 
Data  output  to  Port  1  is  strobed  in  synchroniza- 
tion with  a  P2n/PsfB  pulse. 

10-13 

46-49 

P30-P33 

4-bit  latched  tri-state  output  Port  3  (active  high)' 

14-17 

50-52,  2 

P70-P73 

4-bit  input/latched  tri-state  output  Port  7  (active 
high). 

18 

3 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse 
initializes  hPD7507  or  mPD7508  after  power-up. 

19,  21 

5,9 

Ch,  CL2 

System  clock  input  (active  high).  Connect  82kQ 
resistor  across  CL-|  and  CL2,  and  connect  33pF 
capacitor  from  CL-j  to  Vss-  Alternatively,  an 
external  clock  source  may  be  connected  to  CL1, 
whereas  CL2  is  left  open. 

20 

7,  33 

vDd 

Power  supply  positive.  Apply  single  voltage 
ranging  from  2.7V  to  5.5V  for  proper  operation. 

22 

10 

INT1 

External  Interrupt  INT1  (active  high).  This  is  a 
rising  edge-triggered  interrupt. 

23-26 

11,  12 
15,  16 

P0()/INT0 
P0-,/SCK 
P02/SO 
PO3/SI 

4-bit  input  Port  0/Serial  I/O  Interface  (active  high). 
This  port  can  be  configured  either  as  a  4-bit 
parallel  input  port,  or  as  the  8-bit  serial  I/O  inter- 
face, under  control  of  the  serial  mode  select 
register.  The  Serial  Input  SI  (active  high),  Serial 
Output  SO  (active  low),  and  the  Serial  Clock  SCK 
(active  low)  used  for  synchronizing  data  transfer 
comprise  the  8-bit  serial  I/O  interface.  Line  P00 
is  always  shared  with  external  interrupt  INT0 
(active  high)  which  is  a  rising  edge-triggered 
interrupt. 

Rev/1 
3-53 


MPD7507/7508 

Pin  Identification  (Cont.) 


Absolute  Maximum  Ratings* 


40-Pln 
DIP 

52-Pln 
Flat 

Symbol 

Function 

27-30 

17-20 

P6a-P6o 

4-bit  input/latched  tri-state  output  Port  6  (active 
high).  Individual  lines  can  be  configured  either 
as  inputs  or  as  outputs  under  control  of  the  Port 
6  mode  select  register. 

31-34 

21-24 

P50-P53 

4-bit  input/latched  tri-state  output  Port  5  (active 
high).  Can  also  perform  8-bit  parallel  I/O  in  con- 
junction with  Port  4. 

35-38 

25,  26, 
28,  30 

P40-P43 

4-bit  input/latched  tri-state  output  Port  4  (active 
high).  Can  also  perform  8-bit  parallel  I/O  in  con- 
junction with  Port  5. 

39 

31 

vSs 

Ground. 

1,  4,  6,  8, 
13,  14,  27,  29, 
35,  40,  45 

NC 

No  connection. 

Ta  s  25°C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Power  Supply  Voltage,  Vqd 

-0.3V  to  +7.0V 

All  Input  and  Output  Voltages 

-0.3VtoVDD  +0.3V 

Output-Current  (Total,  All  Output  Ports) 

Iqh  =  -20mA 

Iql  =  30mA 

*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


DC  Characteristics 


Ta  =  -io°cto  +70°c,  vDd  = 

i  4E.rV  IO  9i9V 

Limit* 

t 

Parameter 

Syml 

>ol  MVn 

Typ 

Max 

Unit 

Test  Condition 

a 

V|H 

0.7  VDD 

vDd 

All  Inputs  Other  than  CLj,  X1 

Input  Voltage  High 

V|H2 

vDD-0.5 

vDd 

V 

CLt .  X-i 

VIHDR 

0-9VDDdr 

VDDDR+0.2 

RESET,  Data  Retention  Mode 

V|L 

0 

0.3  VDD 

V 

Ail  Inputs  Other  than  CL1(  X1 

Input  Voltage  Low   

V,L2 

0 

0.5 

CLj.X, 

Input  Leakage  Current  High   

'L«H 

3 

(iA 

All  Inputs  Other  than  CL-j,  X1 

V,  =  VDD 

'lih2 

10 

CL^X, 

-3 

MA 

All  Inputs  Other  than  CL^  X1 

V|  =  ov 

Input  Leakage  Current  Low   

•lil2 

-10 

CL1>  *1 

Output  Voltage  High 

V0H 

VDD  -  1.0 

v 

Vqq  =  5V  ±  10%,  Iqh  =  -1-0  mA 

VDD  -  0.5 

VDD  =  2.7V  to  5.5V,  l0H  =  -100  mA 

Output  Voltage  Low 

vol 

0.4 

VdD  =  5V  ±  10%,  Iqj.  =  1.6  mA 

0.5 

y 

Vqq  =  2.7V  to  5.5V,  Iql  =  400  pA 

Output  Leakage  Current  High 

•loh 

3 

MA 

v0ut  =  vDd 

Output  Leakage  Current  Low 

'lol 

-3 

MA 

V0UT  ■  0V 

Supply  Voltage 

VDDDR 

2.0 

V 

Data  Retention  Mode 

lDD1 

300 

900 

Normal  Operation 

Vpp  =  5V  ±  10% 

150 

400 

Vqq  b  3V  ±  10% 

Supply  Current 

'dd2 

2 

20 

Stop  Mode,  X-,  =  0V 

VDD  =  5V  ±  10% 

0.5 

10 

MA 

vDD  58  3v  ±  10% 

'dddr 

0.4 

10 

Data  Retention  Mode 

VDDDR  -  2  0V 

AC  Characteristics 

Ta  a  -10°CtO  +70°C,  VDD  =  2.7V  to  5.5V 

UmlU 

Parametor 

Symbol 

Mfn 

Typ 

Max 

Unit 

Test  Condltl 

ions 

120 

200 

280 

R  =   82  kQ  ±  2% 
C  =  33  pF  ±  5% 

Vdd  =  sv  ±  io% 

fcc 

60 

100 

130 

CL1,CL2   

R  =  160  kQ  ±  2% 

vDd  »  3V  ±  10% 

System  Clock  Oscillation  Frequency 

60 

180 

KHz 

C  =  33  pF  ±  5% 

VDD  =  2.7V  to  5.5V 

10 

200 

300 

CL-j,  External  Clock 

vDd  =  sv  ±  10% 

'c   

10 

135 

VDD  =  2.7V  to  5.5V 

System  Clock  Rise  and  Fail  Times 

tCR,tCF 

0.2 

CL-j ,  External  Clock 

System  Clock  Pulse  Width 

1.5 

50 

CL-,,  External  Clock 

VDD  =  5V  ±  10% 

tCH'tCL 

3.5 

50 

MS 

VDD  =  2.7V  to  5.5V 

'xx 

25 

32 

50 

X^X2  Crystal  Oscillator 

Counter  Clock  Oscillation  Frequency 

0 

300 

KHz 

X1 ,  External  Pulse  Input 

vDd  -  5V  ±  10% 

♦x   

0 

135 

VDD  -  2.7V  to  5.5V 

Counter  Clock  Rise  and  Fall  Times 

V^XF 

0.2 

MS 

X-| ,  External  Pulse  Input 

Counter  Clock  Pulse  Width 

1.5 

Xj ,  External  Pulse  Input 

Vqq  =  5V  ±  10% 

tXH^XL   

3.5 

MS 

Vqq  =  2.7V  to  5.5V 

3-54 


AC  Characteristics  (Cont.) 


MPD7507/7508 


Limit* 


Parameter 

Symbol 

Mfn 

Typ  Max 

Unit 

Test  Condltl 

Ions 

4.0 

SCK  is  an  input 

VDD  =  5V  ±  10% 

SCK  Cycle  Tim* 

7.0 

Vqq  =  2.7V  to  5.5V 

*KCY  " 

6.7 

M» 

SCK  is  an  output 

VDD  =  5V  ±  10% 

14.0 

VDD  =  2.7V  to  5.5V 

1.8 

SCK  is  an  Input 

VDD  =  5V  ±  10% 

SCK  Pulse  Width 

3.3 

VDD  =  2.7v  to  5.5V 

*KH'*KL 

3.0 



SCK  is  an  output 

VDD  =  5V  ±  10% 

6.5 

Vqp  «  2.7V  to  5.5V 

SI  Setup  Time  to  ScTTt 

lSIK 

300 

ns 

SI  Hold  Time  after  35Kt 

*KSI 

450 

ns 

SO  Delay  Time  after  SCK4 

850 

VDD  =  5V  ±  10% 

*KSO 

1200 

ns 

VDD  =  2.7V  to  5.5V 

Port  1  Output  Setup  Time  to  PffBt 

1/(2^-800) 

VDD  =  5V  ±  10% 

1/(2^-2000) 

ns 

VDD  =  2.7V  to  5.5V 

Port  1  Output  Hold  Time  after  P§YSt 

300 

350  500 

VDD  =  5V  ±  10% 

*STP 

300 

1500 

VDD  =  2.7V  to  5.5V 

PsfB  Pulse  Width 

f/(2f|-800) 

VDD=  5V  ±  10% 

tSWL 

f/(2f+-2000) 

ns 

VDD  m  2.7V  to  5.5V 

INT0  Pulse  Width 

10 

MS 

INT-j  Pulse  Width 

2/U 

MS 

RESET  Pulse  Width 

*RSH'  *RSL 

10 

MS 

RESET  Setup  Time 

*SRS 

0 

ns 

RESET  Hold  Time 

*HRS 

0 

ns 

Capacitance 

Ta  =  25 °C,  VDD  =  OV 


Limits 

Teat 

Conditions 

Parameter 

Symbol 

Mfn     Typ  Max 

Unit 

Input  Capacitance 

C| 

15 

f  =  1  MHz 

Output  Capacitance 

c0 

15 

PF 

Unmeasured  pins 

Input/Output  Capacitance 

cl/0 

15 

returned  to  VSs 

3-55 


MPD7507/7508 
Block  Diagram 


P02/SO 


J_L 


INT1      into/  po0 


Count 
Clock 
Generator 


n 


Program  Counter 


Program  Memory 

2048  x  8-Bit  ROM  (MPD7507) 
4096  x  8-Bit  ROM  (MPD7508) 


System 
Clock 
Generator 


Standby 
Control 


n 

CL 

Clock 
Control 
Circuit 

Timer/Event 
Counter 

Interrupt 
Controller 

Serial  I/O 
Interface 

J 

O 

0 

~\r~ 

ALU 


Instruction 
Decoder 


Data  Memory 
128  x  4-Bit  RAM  (uPD750; 


224  x  4-Bit  RAM 


(uPD7507) 
(MPD7508) 


t  t 


C 

A  (4) 

General  Registers 

D(4)  | 

E(4) 

H(4)  J 

L(4) 

Stack  Pointer 

P00P03 


0 


Port  1 
Buffer 


4  ^  P3Q-P33 


A 


W 


Port  3 
>i  Latch 
y  Buffer 


Port 
Latch 
Buffer 


Port  5 

i  j  Latch 
\j — ^  Buffer 


„  ^ — ^ 

CO 


Port  6  /! — K 
Latch  ,  4  ) 
Buffer  \ — J 


P6O-P63 


A—K  Port  7  AJV 
t  )  Latch  [  4  > 
hfy       Buffer  W 


RESET  VDD 


vss 


3-56 


MPD7507/7508 


Timing  Waveforms 

Clocks 


CM- 


x1- 


Serial  Interface 

§CK  


»cf  — 


\ 


*CR 


-»XL  - 


-  «KCY  - 


-  *SIK  - 


-*KSI 


Valid 
Input  Data 


—  tKS0- 


J. 


Valid  Output  Data 


A. 


X 


-  V*H 

-  V^L 


-V^L 


-  V|H 

-  V|L 


—  V|H 
"— V|L 


-V|H 
-V|L 


Output  Strobe 
pi0.pi3   


-  tpST  - 


-tSTP  - 


J 


> 


—  V|H 
~—  V|L 


—  V|H 

—  V|L 


-tSTL  - 


External  Interrupts 

INTq  


INTv 


Reset 


*RSL 


-  V|H 
'  V|L 


Data  Retention  Mode 

VDD  


J 


2=4 


-Data  Retention  Mode- 


-4HRS~| 


3-57 


jJ>D7507/7508 

Operating  Characteristics 
(Typical,  Ta  =  25 °C) 


Supply  Current 
vs 

Supply  Voltage  (Note  (T)) 


Supply  Voltage  Vdd  (V) 


Supply  Current 
vs 

Supply  Voltage  (Note  (2)) 


Supply  Voltage  Vdd  (V) 


Notes: 

(D  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 
®  Only  crystal  oscillator  clock  is  operating  and  consuming  power.  AH  other  internal  logic  blocks  are  not  active. 


3-58 


Operating  Characteristics  (Cont.) 
(Typical,  Ta  =  25°C) 


System  Clock  Oscillation  Frequency 
vs 

Resistance 


100  200 
Resistance  R  (K  ohms) 


MPD7507/7508 


System  Clock  Oscillation  Frequency 
vs 

Supply  Voltage 


8  100 


|  CL.2  C 
R 

*  I 

.  C 

"  =  33pF 

R  =  82kS2 

R  =  160kQ 

3  4  5 

Supply  Voltage  Vqd  (V) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  ^PD7507C/08C 

Plastic  Miniflat,  uPD7507G/08G 

Plastic  Shrinkdip,  |xPD7507CU  uPD7508CU 


3-59 


7507/7508DS-REV1-7-83-TRIUM-CAT 


NOTES 


3-60 


NEC 


MPD7507S 
CMOS  4-BIT  SINGLE  CHIP 
MICROCOMPUTER 


Description 

The  jiPD7507S  is  a  CMOS  4-bit  single  chip  microcom- 
puter which  has  the  same  ^PD750x  architecture. 
The  fiPD7507S  contains  a  2048  x  8-bit  ROM,  and  a  128 
x  4-bit  RAM. 

The  fiPD7507S  contains  two  4-bit  general  purpose 
registers  located  outside  RAM.  The  subroutine  stack  is 
implemented  in  RAM  for  greater  nesting  depth  and  flex- 
ibility, providing  such  operations  as  the  pushing  and 
popping  of  register  values.  The  ^PD7507S  typically  exe- 
cutes 91  instructions  of  the  ^PD7500  series  "A"  instruc- 
tion set  with  a  10fiS  instruction  cycle  time. 
The  jkPD7507S  has  two  external  and  two  internal  edge- 
triggered  hardware  vectored  interrupts.  It  also  contains 
an  8-bit  timer/event  counter  and  an  8-bit  serial  interface 
to  help  reduce  software  requirements. 
The  jiPD7507S  provides  20  I/O  lines  organized  into  the 
4-bit  input/serial  interface  Port  0,  the  4-bit  output  Port  2, 
the  4-bit  output  Port  3,  and  the  4-bit  I/O  Ports  4  and  5. 
It  is  manufactured  with  a  low  power  consumption 
CMOS  process,  allowing  the  use  of  a  single  power  sup- 
ply between  2.7V  and  5.5V.  Current  consumption  is 
less  than  900jxA  maximum,  and  can  be  lowered  much 
further  in  the  HALT  and  STOP  power-down  modes.  The 
jiPD7507S  is  available  in  a  28-pin  dual-in-line  plastic 
package. 

The  jiPD7507S  is  upward  compatible  with  the  jiPD7507, 
and  downward  compatible  with  the  jiPD7506. 

Pin  Configuration 


Pin  Identification 


P43  C 
XI  C 

P20  C 
P21/PTOUT  C 
P22  □ 
P23  C 
P30  C 
P31  C 
P32  C 
P33  C 
RESET  □ 
CL1  □ 
VDD  C 


24 
23 

MPD7507S22 

21 

I  20 


□  vss 

□  P42 

□  P41 

□  P40 

□  P53 

□  P52 

□  P51 

□  P50 

□  PO3/SI 

□  P02/SO 

□  P01/SCK 

□  PO0/INT0 

□  INT1 

□  CL2 


Pin 

Function 

No. 

Symbol 

1,  25-27 

P40-P43 

4-bit  input/latched  tri-state  output  Port  4  (active  high).  Can  also 
perform  8-bit  parallel  I/O  in  conjunction  with  Port  5. 

2,  3 

X2,  X-\ 

Crystal  clock/external  event  input  Port  X  (active  high).  A 
crystal  oscillator  circuit  is  connected  to  input  X-j  and  output  X2 
for  crystal  clock  operation.  Alternatively,  external  event  pulses 
are  connected  to  input  X-)  while  output  X2  is  left  open  for 
external  event  counting. 

4-7 

P20-P23 
P21/PT0UT 

4-bit  latched  tri-state  output  Port  2  (active  high).  Line  P2-|  is 
shared  with  Pt0ut'  the  t,mer"out  F/F  8,9nal  (active  high). 

P3q-P33 

4-bit  latched  tri-state  output  Port  3  (active  high). 

12 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse  initializes 
jiPD7507  or  fjPD7508  after  power-up. 

13,  15 

CL-j ,  CI-2 

System  clock  input  (active  high).  Connect  82kfi  resistor 
across  CL-)  and  CL2,  and  connect  33pF  capacitor  from  CL-|  to 
VgS.  Alternatively,  an  external  clock  source  may  be  connected 
to  CL1 ,  whereas  CL2  is  left  open. 

14 

VDD 

Power  supply  positive.  Apply  single  voltage  ranging  from  2.7V 
to  5.5V  for  proper  operation. 

16 

INT -j 

External  Interrupt  INT1  (active  high).  This  is  a  rising  edge- 
triggered  interrupt. 

17-20 

P00/INT0 

4-bit  input  Port  0/serial  I/O  interface  (active  high).  This  port 

PO-j/SCK 

P02/SO 

PO3/SI 

can  be  configured  either  as  a  4-bit  parallel  input  port,  or  as  the 
8-bit  serial  I/O  interface,  under  control  of  the  serial  mode 
select  register.  The  Serial  Input  SI  (active  high),  Serial  Output 
SO  (active  low),  and  the  Serial  Clock  SCK  (active  low)  used  for 
synchronizing  data  transfer  comprise  the  8-bit  serial  I/O  inter- 
face. Line  P00  is  always  shared  with  external  interrupt  INTg 
(active  high)  which  is  a  rising  edge-triggered  interrupt. 

21-24 

P50-P53 

4-bit  input/latched  tri-state  output  Port  5  (active  high).  Can  also 
perform  8-bit  parallel  I/O  in  conjunction  with  Port  4. 

28 

vSs 

Ground. 

Absolute  Maximum  Ratings* 

Ta  = 

25°C 

Operating  Temperature 


-10°Cto  +70°C 


Storage  Temperature 


-65°Cto  +150°C 


Power  Supply  Voltage,  Vqd 


-0.3V  to  +7.0V 


All  Input  and  Output  Voltages 


-0.3VtoVDD  +0.3V 


Output-Current  (Total,  All  Output  Ports) 


IqH  =  -17mA 
■OL  = 


-34mA 


*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


Rev/1 
3-61 


MPD7507S 

Block  Diagram 


X1  X2 


pcyspK  po3/si 
po2/so 


It 


INT1         INTo/  P00 


Count 
Clock 
Generator 

Clock 
Control 
Circuit 

Timer/Event 
Counter 

Interrupt 
Controller 

Serial 
Interface 

A- 

v- 

Port  0 
Buffer 

CL 

tout  ^£ 

O 

H 


11 -BIT  Program  Counter 


Program  Memory 
2048  x  8-BIT  ROM  (MPD7507S) 


H 


A  (4) 


General  Registers 


r  r 

System 
Clock 
Generator 

Standby 
Control 

Instruction 
Decoder 


E(4) 


L(4) 


Stack  Pointer  (8) 


Data  Memory 
128  x  4-BIT  (f<PD7507S) 


0 


P00-P03 


 K       Port  2   \ 

j  Latch  4  > 
 V       Buffer   y 


A — \       Port  4       A  \ 

v  )  Latch  ,  4  \ 
\  Y        Buffer        \|  / 


Port  3   \ 

Latch  4  \ 

Buffer  —y 


P2o/P23 
(P21/PT0UT) 

P3Q-P33 


AA 
W 


Port  5 
Latch 
Buffer 


P5Q-P53 


RESET        VDD  VSS 


3-62 


MPD7507S 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  2.7V  to  3.5V 


Limit* 

Parameter 

Symbol 

Mln 

TVP 

Max 

Unit 

Teat  Conditions 

V|H 

0.7  VDD 

vdd 

All  Inputs  Other  than  CL1t  X1 

Input  Voltage  High 

V|H2 

VDD-0.5 

Vdd 

V 

CL1,X1 

VIHDR 

09VDDDR 

vDDdr  +  0.2 

RESET,  Data  Retention  Mode 

Input  Voltage  Low 

V|L 

0 

0.3  Vqq 

V 

All  Inputs  Other  than  CL-, ,  X1 

V,L2 

0 

0.5 

CL1,X1 

Input  Leakage  Current  High 

'lih 

3 

MA 

All  Inputs  Other  than  CL1f  X1 

V|  -  vDd 

VLIH2 

10 

CL^X! 

Input  Leakage  Current  Low 

»L.L 

-3 

ma 

All  Inputs  Other  than  CL-j,  X1 

V,  =  OV 

VLIL2 

-10 

CLVXA 

Output  Voltage  High 

V0H 

VDD  -  1.0 

V 

Vqd  =  5V  ±  10%,  Iqh  =  -10  mA 

Vqd  -  0.5 

Vqd  ■  2.7V  to  5.5V,  l0H  ■  -100  MA 

Output  Voltage  Low 

VOL 

0.4 

Vqd  =  5V  ±  10%,  Iql  *  1-6  m A 

0.5 

VDD=  2.7V  to  5.5V,  l0L  =  400  MA 

Output  Leakage  Current  High 

•loh 

3 

ha 

v0  =  vDD 

Output  Leakage  Current  Low 

'lol 

-3 

fA 

v0  =  ov 

Supply  Voltage 

vddDr 

2.0 

V 

Data  Retention  Mode 

,DD1 

300 

900 

Normal  Operation 

VDD  =  5V  ±  10% 

70 

300 

Vqd  =  3V  ±  10% 

Supply  Current 

'dd2 

1 

20 

MA 

Stop  Mode,  X-,  =  0V 

VDD  =  5V  ±  10% 

0.3 

10 

Vqd  =  3V  ±  10% 

'dddr 

0.4 

10 

Data  Retention  Mode 

VDDDR  =  20V 

AC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  2.7V  to  5.5V 


Parameter 

Symbol 

Mln 

Max 

Unit 

Tost  CondKh 

MVS 

150 

200 

240 

R  =  82  kQ  ±  2% 
CM,  Cta  C  =  33PF±5% 

Vdd 

5V  ±  10% 

System  Clock  Oscillation  Frequency 

»cc 

75 

100 

120 

R/C  Clock  R  -  160  kQ  ±  2% 

vDd 

3V  ±  10% 

75 

135 

KHz 

C  =  33  pF  ±  5% 

vDd 

2.7V  to  5.5V 

*c 

10 

200 

300 

CL1t  External  Clock 

vDd 

5V  i  10% 

10 

135 

vDd 

2.7V  to  5.5V 

System  Clock  Rise  and  Fall  Times 

*CR'  *CF 

0.2 

CL-|,  External  Clock 

System  Clock  Pulse  Width 

tCH'tCL 

1.1 

50 

CLj,  External  Clock 

vDd 

5V  ±  10% 

3.5 

50 

MS 

vdd 

2.7V  to  5.5V 

*xx 

20 

32 

50 

X-,,  X2  Crystal  Oscillator 

Counter  Clock  Oscillation  Frequency 

0 

300 

KHz 

X-| ,  External  Pulse  Input 

vdd 

5V  ±  10% 

*x 

0 

135 

vDd 

2.7V  to  5.5V 

Counter  Clock  Rise  and  Fall  Times 

txR'  »xF 

0.2 

MS 

X-j ,  External  Pulse  Input 

Counter  Clock  Pulse  Width 

*xH»  *xL 

1.5 

MS 

X-|,  External  Pulse  Input 

vDd 

5V  ±  10% 

3.5 

vDd 

2.7V  to  5.5V 

4.0 

SCK  Is  an  input 

vDd 

5V  ±  10% 

SCK  Cycle  Time 

lKCY 

7.0 

MS 

vDd 

2.7V  to  5.5V 

6.7 

SCK  is  an  output 

vdd 

5V  ±  10% 

14.0 

vDd 

2.7V  to  5.5V 

1.3 

SCK  is  an  input 

vDd 

5V  ±  10% 

SCK  Pulse  Width 

lKH»  *KL 

3.3 

MS 

vDd 

2.7V  to  5.5V 

2.2 

SCK  is  an  output 

vdd 

5V  ±  10% 

6.5 

vDd 

2.7V  to  5.5V 

SI  Setup  Time  to  SCK! 

XS\K 

300 

ns 

SI  Hold  Time  after  SCKt 

XKS\ 

450 

ns 

SO  Delay  Time  after  SCKi 

*KSO 

850 

VDD  =  5V  ±  10% 

1200 

ns 

VDD  =  2.7V  to  5.5V 

INT0  Pulse  Width 

^OH'W 

10 

M« 

INT1  Pulse  Width 

t|1H.t,1L 

2/fc 

MS 

RESET  Pulse  Width 

tRSH>*RSL 

10 

MS 

RESET  Setup  Time 

lSRS 

0 

ns 

RESET  Hold  Time 

*HRS 

0 

ns 

3-63 


MPD7507S 


Capacitance 

Ta  a  25CC,  Vpp  =  QV 


Umit* 

Test 

Parameter 

Symbol  1 

•in     Typ  Max 

Unit 

Input  Capacitance 

15 

pF 

f  *  1  MHz 

Output  Capacitance 

Co 

15 

pF 

Unmeasured  pins 

input/Output  Capacitance 

cl/0 

15 

PF 

returned  to  Vss 

Timing  Waveforms 

Clocks 


CM 


*1 


Serial  Interface 


External  Interrupts 

INTo  ~* — 


tlQL 


tlOH 


—  V|H 

—  V|L 


-  V|H 
-V|L 


t«sL 


«RSu 


-  V(H 

-  V|L 


Data  Retention  Mode 

VDD  


-Data  Retention  Mode- 


3-64 


._  vih 


Operating  Characteristics 
(Typical,  Ta  =  25  °C) 


MPD7507S 


Supply  Current 
vs 

Supply  Voltage  (Note  0) 


fc  50 


CL1      CL2  | 


C 

J=  33pF 


2  3  4  5 

Supply  Voltage  Vdd  (V) 


I" 
t  5 

f 


Supply  Current 
vs 

Supply  Voltage  (Note  @) 


y- 

|    Xi       X2  | 

Ci: 
i 

R1 
Ci 

HDH 

I  f 

-  330kQ 
=  20pF 

—it— 

C2  =  30pF 
Xta,  =  32.768  KHz 

Supply  Voltage  Vdd  (V) 


Supply  Current 
vs 

System  Clock  Oscillation  Frequency 
(Note  0) 


100  200  300  400  500 

Oscillation  Frequency  f<j>  (KHz) 


Supply  Current 
vs 

System  Clock  Oscillation  Frequency 
(Note  ©) 


% 
o 
9 


CL2     CLj  I 


"5 


vdd  =  3.ov 


c  =  100  pF 


C  =  39pF 


100  200  300  400  500 

Oscillation  Frequency  f$  (KHz) 


Notes: 

0  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 
®  Only  crystal  oscillator  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 


3-65 


MPD7507S 

Operating  Characteristics  (Cont.) 
(Typical,  Ta  =  25  °C) 


System  Clock  Oscillation  Frequency 
vs 

Resistance 


1  CL2     CL1  I 

C  s  33pF  : 

J 

r 

VDD  =  5V 

VDD  =  3V 

U,  

100  200 
Resistance  R  (K  ohms) 


System  Clock  Oscillation  Frequency 
vs 

Supply  Voltage 


CL2     CM  \ 


3  4  5 

Supply  Voltage  Vdd  (V) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD7507SC 

Plastic  Shrinkdip,  jxPD7507SCT 


3-66 


7507DS-REV1-7-83-CAT 


\FC  MPD7508A 
^  ^  ^  CMOS  4-BIT  SINGLE  CHIP 

MICROCOMPUTER  WITH  VACUUM 
FLUORESCENT  DISPLAY  DRIVE 

CAPABILITY 


Description 

The  jiPD7508A  is  a  CMOS  4-bit  single  chip  microcom- 
puter which  has  the  ^PD750x  architecture.  It  is  identical 
to  the  jiPD7508,  except  for  a  slightly  smaller  RAM,  and 
16  lines  of  vacuum  fluorescent  display  drive  capability. 
The  jiPD7508A  contains  a  4096  x  8-bit  ROM,  and  a  208 
x  4-bit  RAM. 

The  /iPD7508A  contains  four  4-bit  general  purpose 
registers  located  outside  RAM.  The  subroutine  stack  is 
implemented  in  RAM  for  greater  nesting  depth  and  flex- 
ibility, providing  such  operations  as  the  pushing  and 
popping  of  register  values.  The  jl<PD7508A  typically  ex- 
ecutes 92  instructions  of  the  juPD7500  series  "A"  in- 
struction set  with  a  10/iS  instruction  cycle  time. 
The  j<tPD7508A  has  two  external  and  two  internal  edge- 
triggered  hardware  vectored  interrupts.  It  also  contains 
an  8-bit  timer/event  counter  and  an  8-bit  serial  interface 
to  help  reduce  software  requirements. 

The  fiPD7508A  provides  32  I/O  lines  organized  into  the 
4-bit  input/serial  interface  Port  0,  the  4-bit  output  Port  2, 
the  4-bit  output  Port  3,  and  the  4-bit  I/O  Ports  1,  4,  5,  6, 
and  7.  Ports  3,  4,  5,  and  6  are  capable  of  being  pulled 
to  -  35V  in  order  to  drive  vacuum  fluorescent  displays 
directly.  It  is  manufactured  with  a  low  power  consump- 
tion CMOS  process,  allowing  the  use  of  a  single  power 
supply  between  2.7V  and  5.5V.  Current  consumption  is 
less  than  900*iA  maximum,  and  can  be  lowered  much 
further  in  the  HALT  and  STOP  power-down  modes.  The 
^PD7508A  is  available  in  a  40-pin  dual-in-line  plastic 
package. 


Pin  Configuration 


Pin  Names 


40-Pln 
DIP 

Symbol 

Function 

1,  40 

X2,  X, 

Crystal  clock  external  event  input  Port  X  (active  high).  A  crystal 
oscillator  circuit  is  connected  to  input  X-|  and  output  X2  for 
crystal  clock  operation.  Alternatively,  external  event  pulses  are 
connected  to  input  X1  while  output  X2  is  left  open  for  external 
event  counting. 

2-5 

P20-P23 
P20pSTB 
P21/PT0UT 

4-bit  latched  tristate  output  Port  2  (active  high).  Line  P20  is 
also  shared  with  P§TB- tne  Port  1  output  strobe  pulse  (active 
low).  Line  P2-j  is  also  shared  with  PTntiT' the  ,imer  out  F/F 
signal  (active  high). 

6-9 

P10-P13 

4-bit  input/tristate  output  Port  1  (active  high).  Data  output  to 
Port  1  is  strobed  in  synchronization  with  a  P2n/P§fB  pulse. 

10-13 

P30-P33 

4-bit  latched  tristate  output  Port  3  (active  high). 

14-17 

P70-P73 

4-bit  input/latched  tristate  output  Port  7  (active  high). 

18 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse  initializes 
MPD7507  or  ^PD7508  after  power-up. 

CL„CL2 

System  clock  input  (active  high).  Connect  82kQ  resistor  across 
CL-|  and  CL2,  and  connect  33  pF  capacitor  from  CL1  to  VSs- 
Alternatively,  an  external  clock  source  may  be  connected  to 
CL1t  whereas  CL2  is  left  open. 

20 

Vqq 

Power  supply  positive.  Apply  single  voltage  ranging  from  2.7V 
to  5.5V  for  proper  operation. 

22 

INT1 

External  Interrupt  INT-(  (active  high).  This  is  a  rising  edge- 
triggered  interrupt. 

23-26 

POq/INTq 
PO^SCK 
P02/SO 
P03/Sl 

4-bit  input  Port  0/serial  I/O  interface  (active  high).  This  port  can 
be  configured  either  as  a  4-bit  parallel  input  port,  or  as  the  8-bit 
serial  I/O  interface,  under  control  of  the  serial  mode  select 
register.  The  Serial  Input  SI  (active  high),  Serial  Output  SO 
(active  low),  and  the  Serial  Clock  SCK  (active  low)  used  for  syn- 
chronizing data  transfer  comprise  the  8-bit  serial  I/O  interface. 
Line  P00  is  always  shared  with  external  interrupt  INTg  (active 
high)  which  is  a  rising  edge-triggered  interrupt. 

27-30 

P60-P63 

4-bit  input/latched  tristate  output  Port  6  (active  high).  Individual 
lines  can  be  configured  either  as  inputs  or  as  outputs  under 
control  of  the  Port  6  mode  select  register. 

31-34 

P50-P53 

4-bit  input/latched  tristate  output  Port  5  (active  high).  Can  also 
perform  8-bit  parallel  I/O  conjunction  with  Port  4. 

35-38 

P40-P43 

4-bit  input/latched  tristate  output  Port  4  (active  high).  Can  also 
perform  8-bit  parallel  I/O  in  conjunction  with  Port  5. 

39 

vSs 

Ground. 

X2C 
P20/PSTB  C 
P21/PTOUT  C 
P22  C 
P23  C 
P10  C 

pn  c 

P12  C 
P13  C 
P30  C 
P31  C 
P32  C 
P33  C 
P70  C 
P71  C 
P72  C 
P73  C 
RESET  C 
CL1  C 
VDD  C 


u  MPD7508A 


□  xi 

□  vSs 

□  P43 
3  P*2 
D  P41 

□  P40 

□  P53 

□  P52 

□  P51 

□  P50 

□  P63 

□  P62 

□  P61 

□  P60 

□  P03/Sl 

□  P02/SO 

□  PO^SCK 

□  POn/INTo 

□  "NT1 

□  CL2 


Absolute  Maximum  Ratings* 


Ta  =  25«C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Power  Supply  Voltage,  Vqd 

-0.3V  to  +7.0V 

Input  Voltages,  Ports  4, 5,  and  6  (Vqd 

-40.0)Vto(VDD  +0.3)V 

All  Other  Input  Ports 

-0.3VtoVDD  +0.3V 

Output  Voltages,  Ports  3, 4, 5,  and  6  (Vqd 

-40.0)Vto(VDD  +  0.3)V 

All  Other  Output  Ports 

-0.3VtoVDD  +0.3V 

Output-Current  (Total,  All  Output  Ports) 

Iqh  =  -150mA 

Iql  =  50mA 

*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 

Rev/2  device  reliability. 

3-67 


MPD7508A 

Block  Diagram 


P01/SCK  p03/s| 
P02/SO 


l_i 


INT1       into/  po0 


Count 
Clock 
Generator 


u 


Program  Counter 


Program  Memory 
4096  x  8-Bit  ROM  (mPD7508A) 


r  r 


System 
Clock 
Generator 


Standby 
Control 


Clock 
Control 
Circuit 

Timer/Event 
Counter 

Interrupt 
Controller 

Serial  I/O 
Interface 

Instruction 
Decoder 


Data  Memory 
208  x  4-Bit  RAM  (mPD7508A) 


CL1  CL2 


D(4) 

I  E(4) 

H(4) 

I  L(4) 

Stack  Pointer 

Port  0 
Buffer 


3 


W 


/-A 


Port  2 
Latch 
Buffer 


Port  3 
Latch 
Buffer 


Port  4 
Latch 
Buffer 


Port  5 
j  Latch 
\j  j/  Buffer 


A  \        Port  6 

'  ^  Latch 
\f— j/  Buffer 


3 


P00-P03 


P10-P13 


P2n/PSTB. 
P21/PTQUT 


P4Q-P43 


VV   Buf,er  w 


RESET  VDD 


vss 


3-68 


MPD7508A 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  2.7V  to  5.5V 


Limits 

Parameter 

Symbol 

M/n 

Typ 

Max 

Unit 

Test  Conditions 

V|H 

0.7  VDD 

vDd 

All  Inputs  Other  than  CL1t  X1 

Input  Voltage  High 

V|H2 

VDD  -  0.5 

Vdd 

V 

V'HDR 

0.9VDD[)R 

Vdddr  +  °-2 

RESET,  Data  Retention  Mode 

V|L1 

0 

0.3VDD 

All  Innnts  Othar  than  PI  -           Drtrta  A  (> 

Mil  inputs  vsiner  inan  wL-^ ,      ,  rwi8  n,  9, 

Input  Voltage  Low 

V"-3 

VDD  -  35.0 

0.3VDD 

V 

Ports  4,  5,  and  6 

VIL9 
2 

0 

0.5 

CL-j, 

'lih-, 

3 

AH  Inputs  Other  than  CL-j,  X-|,  Ports  4,  5, 

and  6  V|  =  Vdd 

Input  Leakage  Current  High 

'lih2 

10 

MA 

Ports  4  5,  and  6, 

Vi  =  Vnn 

vl  -  ¥DD 

<LIH3 

60 

C\-i,  X1 

1.11-1 

-3 

All  Inputs  Other  than  CL^,  X-j 

 v  -  ov  

Input  Leakage  Current  Low 

'LIL2 

■10 

ma 

Vj  =  -30.0V 

'LIL3 

-30 

CLi.X, 

Output  Voltage  High 

V0H 

VDD  -  2.0 

V 

Vdd  =  ®V  ±  10%,  Iqh  =  -1-OmA 

Vdd  ~  0-5 

vDd  =  2-7V  to  5.5V,  i0H  =  -ioomA 

Output  Voltage  Low 

vol 

0.4 

V 

Vdd  -  5V  ±  10%,  Iql  =  1.6mA 

0.5 

VDd  =  2  7V  to  5.5V,  l0L  =  400f4A 

Output  Leakage  Current  High 

'loht 

v0  =  vDD 

'loh2 

30 

ma 

Ports  3,  4,  5,  and  6, 

V0  =  -30V 

Output  Leakage  Current  Low 

•lol2 

-3 

yA 

v0  =  0V 

•lol2 

-30 

ma 

Ports  3,  4,  5,  and  6, 

V0  =  -30V 

Supply  Voltage 

vdddr 

2.0 

V 

Data  Retention  Mode 

300 

900 

Normal  Operation 

Vdd  =  sv  ±  10% 

lDD1 

70 

300 

Vdd  =  3V  ±  10% 

Supply  Current 

1 

20 

ma 

Stop  Mode,  X1  =  0V 

vDd  ■  5V  ±  10% 

•dd2 

0.3 

10 

vDd  =  3V  ±  10% 

'ddDr 

0.4 

10 

Data  Retention  Mode,  VDoOR  =  2.0V 

Capacitance 

Ta  =  25°C,  vdd  =  ov 


_____  Test 
Symbol      Mfn      Typ     Max     Unit  Conditions 


Input  Capacitance 


Output  Capacitance        C0                              20        pF       Unmeasured  pins 
  returned  to  Vgs 


Input/Output 
Capacitance 


cl/0 


3-69 


MPD7508A 


AC  Characteristics 

Ta  =  -  10°C  to  +  70°C,  VDD  =  2.7V  to  5.5V 


Parameter 

Symbol 

Mfn 

Typ 

Max 

Unit 

Test  Conditions 

150 

200 

240 

R  =  82kQ  ±  2% 
C  =  33pF  ±  5% 

Vqq  =  5V  ±  10% 

System  Clock  Oscillation  Frequency 

fcc 

75 

100 

120 

KHz 

CL1>CL2 

R  =  160kQ  ±2% 

Vqq  =  3V  ±  10% 

75 

135 

R/C  Clock 

C  =  33pF  ±  5% 

Vqq  =  2.7V  to  5.5V 

10 

410 

CL1t 

External 

Clock 

Vqq  =  5V  ±  10% 

fC 

10 

125 

Vqq  =  2.7V  to  5.5V 

System  Clock  Rise  and  Fall  Times 

tCR'kJF 

0.2 

MS 

CM  >  External  Clock 

System  Clock  Pulse  Width 

*CH«  *CL 

1.1 

50 

MS 

CM- 

External 

Clock 

Vqq  *  5V  ±  10% 

3.5 

50 

Vqq  =  2.7V  to  5.5V 

fxx 

25 

32 

50 

X1tX2  Crystal  Oscillator 

Counter  Clock  Oscillation  Frequency 

0 

410 

KHz 

Xf ,  External  Pulse  Input 

Vqq  =  5V  ±  10% 

*x 

0 

135 

Vqq  =  2.7V  to  5.5V 

Counter  Clock  Rise  and  Fall  Times 

txR'Vp 

0.2 

MS 

X1t  External  1 

»ulse  Input 

Counter  Clock  Pulse  Width 

^XH.^XL 

MS 

Xi.  External  Pulse  Input 

Vnn  -  5V  4-  10% 

VQQ   —  5*V    X  IV7H 

3.5 

Vqq  =  2.7V  to  5.5V 

3.0 

SCK  is 

Vqq  -  5V  ±  10% 

SCK  Cycle  Time 

*KCY 

an 

input 

Vqq  -  2.7V  to  5.5V 

5.0 

MS 

SCK  is 

Vqq  »  5V  ±  10% 

14.0 

an 

output 

Vqq  =  2.7V  to  5.5V 

1.3 

SCK  is 
an 

input 

Vqq  =  5V  ±  10% 

SCK  Pulse  Width 

tKH'tKL 

3.3 

Vqq  =  2.7V  to  5.5V 

2.2 

MS 

SCK  is 

Vqq  =  5V  ±  10% 

6.5 

an 

output 

Vqq  =  2.7V  to  5.5V 

SI  Setup  Time  to  SCKt 

'SIX 

.3 

MS 

SI  Hold  Time  after  SCKt 

*KSI 

.45 

MS 

SO  Delay  Time  after  SCKi 

*KSO 

850 

VDD  =  5V  ± 

1200 

VDD  -  2.7V  to  5.5V 

Port  1  Output  Setup  Time  to  PsTB* 

1/(2  V 
800) 

Vqq  =  5V  ± 

10% 

1/(2fc. 
2000) 

VDD  m  2.7V  to  5.5V 

Port  1  Output  Hold  Time  after  Pstb* 

*STP 

100 

vDD  =  5y  ±  10% 

100 

ns 

Vqq  =  2.7V  to  5.5V 

PSTB  pulse  Width 

1(2fc- 
800) 

Vqq  =  5V  ±  10% 

»SL 

1/<2fc- 
2000) 

ns 

Vqq  =  2.7V  to  5.5V 

INT0  Pulse  Width 

Wkn. 

10 

MS 

INT1  Pulse  Width 

t|1H.t|1L 

\ 

MS 

RESET  Pulse  Width 

tRSH^RSi. 

10 

M« 

3-70 


MPD7508A 


Timing  Waveforms 


Clocks 


Output  Strobe 

pi0-pi3   


-  tpST  " 


- *STP  - 


-  V|H 
•  V|L 


 V|H 

—  V|L 


External  Interrupts 

INTO  


-  tlOL 


t|0H 


—  V|H 

—  Vil 


INT1- 


tHL 


f 


t|1H- 


-  V|H 

-  V|L 


Reset 


-tRSL- 


—  V|H 


Data  Retention  Mode 

VDD  


—  tsRS  * 


-Data  Retention  Mode- 


^HRS 


__  V,H 
—  VDDDR 


3-71 


MPD7508A 


Operating  Characteristics 

Typical,  Ta  =  25°C 


Supply  Current 
vs 

Supply  Voltage  (Note  ©) 


Supply  Current 
vs 

Supply  Voltage  (Note  (5) ) 


?  10 
§ 

c 

S  5 

3 

o 
> 

■s. 


|    X1      X2  | 

Ci: 
> 

Ci 

HDH 

I  f 

=  330kQ 
=  20pF 

C2  =  30pF 
Xta)  =  32.768KHZ 

Supply  Voltage  Vdd  (V) 


Notes: 

(f)  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 

(g)  Only  crystal  oscillator  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are  not  active. 


3-72 


Operating  Characteristics  (Cont.) 

Typical,  Ta  =  25  °C 


System  Clock  Oscillation  Frequency 
vs 

Resistance 


SO  100  200 

Resistance  R  (K  ohms) 


MPD7508A 


System  Clock  Oscillation  Frequency 
vs 

Supply  Voltage 


£  200 


|  CL2     CLI  j 

R 

A 

.C 

'  =  33pF 

— =- 

R  =  82kQ 

R  =  160kQ 

Supply  Voltage  Vqd  (V) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  fxPD7508AC 

Plastic  Shrinkdip,  |xPD7508ACU 

Ceramic  Piggyback,  fxPD75CG08E 


3-73 


7508ADS-REV2-7-83-TRIUM-CAT 


NOTES 


3-74 


NEC  Ji 


/  PD7508H 
HIGH  SPEED  CMOS 
4-BIT  SINGLE  CHIP 
MICROCOMPUTER 


Description 

The  /aPD7508H  is  a  high-speed  CMOS  4-bit  single 
chip  microcomputer  which  is  based  upon  the  /xPD7500 
series  architecture. 

The  /itPD7508H  contains  a  4096  x  8-bit  ROM,  and  a  224  x 
4-bit  RAM.  It  contains  four  4-bit  general  purpose  registers 
located  outside  RAM.  The  subroutine  stack  is  implemented 
in  RAM  for  greater  nesting  depth  and  flexibility,  providing 
such  operations  as  the  pushing  and  popping  of  register 
values.  The  /itPD7508H  typically  executes  92  instructions 
of  the  /xPD7500  series  "A"  instruction  set  with  4(jls  instruc- 
tion cycle  time. 

The  ju,PD7508H  has  two  external  and  two  internal  edge- 
triggered  hardware  vectored  interrupts.  It  also  contains  an 
8-bit  timer/event  counter  and  an  8-bit  serial  interface  to  help 
reduce  software  requirements. 

The  /xPD7508H  provides  32  I/O  lines  organized  into  the  4-bit 
input/serial  interface  Port  0,  the  4-bit  input  Port  2,  the  4-bit 
output  Port  3,  and  the  4-bit  I/O  Ports  1 , 4, 5, 6,  and  7.  It  is 
manufactured  with  a  low  power  consumption  CMOS  pro- 
cess, allowing  the  use  of  a  single  power  supply  between 
2.7V  and  5.5V.  Current  consumption  is  less  than  900/uA 
maximum,  and  can  be  lowered  much  further  in  the  HALT 
and  STOP  power-down  modes.  The  /xPD7508H  is  available 
in  a  40-pin  dual-in-line  plastic  package.  The  ju,PD7508H  is 
downward  compatible  with  the  juPD7508  and  the  ^PD7507. 
The  /otPD7508H  is  ideally  suited  as  a  controller  in  the  follow- 
ing applications: 

□  telephone/telecommunication  equipment 

□  portable  instruments 

□  automotive  dashboard  controls 

□  medical  instruments 

□  portable  and  hand-held  computer  terminals 

□  office  equipment 

Development  Tools 

For  software  development,  editing,  debugging,  and  assem- 
bly into  object  code,  you  can  use  the  NEC  Development 
System  (NDS).  Additionally,  for  systems  supporting  either 
the  ISIS-II  (®lntel  Corp.),  CP/M  (®Digital  Research  Corp.) 
operating  systems,  or  Fortran  IV  ANS1 1966  V3.9,  the 
ASM75  Cross-Assembler  is  available. 
During  software  development,  the  code  can  be  completely 
evaluated  and  debugged  with  hardware  by  the  Evakit-7500 
Evaluation  Board.  The  Evakit-7500-RTT  Real-Time  Tracer 
Board  is  an  optional  device  used  to  examine  operation  of 
your  code  in  the  actual  prototype  circuit.  The  SE-7508 
System  Emulation  Board  will  emulate  complete  function- 
ality of  the  /nPD7508H  for  demonstrating  your  final  system 
design.  All  of  these  boards  take  advantage  of  the  capabili- 
ties of  the  //PD7500  ROM-less  evaluation  chip  to  perform 
their  tasks. 

Complete  operation  details  on  the  ^PD7508H  CMOS 
4-bit  Microcomputer  can  be  found  in  the  //PD7506, 
/LtPD7507,  and  /uPD7508  CMOS  4-bit  Microcomputers 
Technical  Manual. 


□ 


□ 


Features 

□  Advanced  4th  Generation  Architecture 
Program  Memory  (ROM)  size:  4K  x  8-bit  bytes 
Data  Memory  (RAM)  size:  224  x  4-bit  nibbles 
RAM  Stack 

Four  General  Purpose  Registers:  D,  E,  H,  and  L 

-  Can  address  Data  Memory  and  I/O  ports 

-  Can  be  stored  to  or  retrieved  from  Stack 

□  92  Powerful  Instructions,  including 

-  Direct/indirect  addressing 

-  Table  look-up 

-  RAM  stack  push/pop 

-  Single  byte  subroutine  calls 

-  RAM  and  I/O  port  single  bit  manipulation 

-  Accumulator  and  I/O  port  logical  operations 

-  4/ixs  instruction  cycle  time,  typically 
Extensive  General  Purpose  I/O  Capability 

-  One  4-bit  input  port 

-  Two  4-bit  latched  tri-state  output  ports 

-  Five  4-bit  input/latched  tri-state  output  ports 

-  Easily  expandable  with  /aPD82C43  CMOS 
I/O  expander 

-  8-bit  parallel  I/O  capacity 
Hardware  Logic  Blocks  -  Reduce  Software 
Requirements 

-  Operation  completely  transparent  to 
instruction  execution 

-  8-bit  Timer/Event  counter 

-  Binary-up  counter  generates  INTT  at 
coincidence 

-  Accurate  Crystal  Clock  or  External  Event  operation 
possible 

-  Vectored,  Prioritized  Interrupt  Controller 

-  Three  external  interrupts  (INT0,  INT,,  INT2) 

-  Two  internal  interrupts  (INTT,  INTS) 

-  8-bit  Serial  Interface 

-  3-line  I/O  configuration  generates  INTS  upon  trans- 
mission of  eighth  bit 

-  Ideal  for  distributed  intelligence  systems  or  commu- 
nication with  peripheral  devices 

-  Complete  operation  possible  in  HALT  and  STOP 
power-down  modes 

Built-in  System  Clock  Generator 
Built-in  Schmidt-Trigger  RESET  Circuitry 
Single  Power  Supply,  Variable  from  2.7V  to  5.5V 
Low  Power  Consumption  Silicon  Gate  CMOS 
Technology 

-  900/xA  max  at  5V,  400/uA  max  at  3V 

-  HALT,  STOP  power-down  instructions  reduce  power 
consumption  to  20/xA  max  at  5V,  10juA  at  3V 
(Stop  Mode) 

Extended  -40°Cto  +85°C  Temperature  Range 
Available 

40-pin  Dual-in-line  Plastic  Package 


□ 


□ 


Rev/1 

3-75 


MPD7508H 


Pin  Configuration 


Pin  Identification 


Clock  Out  \Z 
P20/PSTBC 
P21/PT0UT  C 
P22C 
P23C 
P10C 
P11  C 
P12C 
P13C 
P30C 
P3lCI 
P32C 
P33d 
P70C 
P7lC 
P72C 
P73C 
RESET  □ 

vddC 


AtPD7508H 


□  EVENT 

□  vSs 

□  P43 
JP42 

□  P4i 

□  P40 

□  P53 

□  P52 

□  P51 

□  P50 

□  P63 

□  P62 

□  P61 
IJP60 

□  PO3/SI 

□  P02/SO 

□  PO0/INT0 

□  INT1 

□  x2 


Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

-10°C  to  +70°C 

Storage  Temperature 

-65°Cto+150°C 

Power  Supply  Voltage,  VDD 

-  0.3  V  to  +  7.0V 

All  Input  and  Output  Voltages 

-0.3V  to  VDD  +  0.3V 

Output  Current  (Total,  All  Output  Ports) 

l0H  =  -20mA 

l0L  =  30mA 

Pin 

NO. 

Symbol 

Function 

1 

Clock  Out 

Crystal  Clock  Output  (active  high)  The  Crystal  Oscillator  frequency  is 
divided  by  12,  and  then  output  through  a  buffer 

2-5 

P2o-P23 

P2o/PsT8 

P2i/Ptout 

4-bit  latched  tri-state  output  Port  2  (active  high).  Line  P2„  is  also  shared 
with  PSTB,  the  Port  1  output  strobe  pulse  (active  low).  Line  P2,  is  also 
shared  with  PTouT.  the  timer-out  F/F  signal  (active  high). 

6-9 

PI0-PI3 

4-bit  input/tri-state  output  Port  1  (active  high).  Data  output  to  Port  1  is~ 
strobed  in  synchronization  with  a  P2o/PSTB  pulse. 

10-13  P30-P33 

4-bit  input/latched  tri-state  output  Port  3  (active  high). 

14-17  P70-P73 

4-bit  input/latched  tri-state  output  Port  7  (active  high). 

18 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse  initializes  /xPD7507  or 
/xPD7508  after  power-up. 

19,21 

X„X2 

Crystal  Clock  Oscillator  input  (active  high).  Connect  a  4.19MHz  crystal 
across  X,,andX2. 

20 

VDD 

Power  supply  positive.  Apply  single  voltage  ranging  from  2.7V  to  5.5V 
for  proper  operation. 

22 

INT, 

External  interrupt  INT,  (active  high).  This  is  a  rising  edge-triggered 
interrupt. 

23-26  POq/INTq 
P0,/SCK 
P02/SO 
PO3/SI 

4-bit  input  Port  0/Senal  I/O  interface  (active  high).  This  port  can  be 
configured  either  as  a  4-bit  parallel  input  port,  or  as  the  8-bit  serial  I/O 
interface,  under  control  of  the  serial  mode  select  register.  The  Serial 
Input  SI  (active  high),  Serial  Output  SO  (active  low),  and  the  Serial  Clock 
SCK  (active  low)  used  for  synchronizing  data  transfer  comprise  the  8-bit 
serial  I/O  interface  Line  P00  is  always  shared  with  external  interrupt  INT0 
(active  high)  which  is  a  rising  edge-triggered  interrupt. 

27-30 

P60-P63 

4-bit  input/latched  tri-state  output  Port  6  (active  high).  Individual  lines 
can  be  configured  either  as  inputs  or  as  outputs  under  control  of  the 
Port  6  mode  select  register. 

31-34  P50-P53 

4-bit  input/latched  tri-state  output  Port  5  (active  high).  Can  also  perform 
8-bit  parallel  I/O  in  conjunction  with  Port  4. 

35-38  P40-P43 

4-bit  input/latched  tri-state  output  Port  4  (active  high).  Can  also  perform 
8-bit  parallel  I/O  in  conjunction  with  Port  5. 

39 

Vss 

Ground. 

40 

EVENT 

EVENT  counter  pulse  input  (active  high) 

"COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be  oper- 
ated under  conditions  outside  the  limits  described  in 
the  operational  sections  of  this  specification.  Exposure 
to  absolute  maximum  rating  conditions  for  extended 
periods  may  affect  device  reliability. 


3 


-76 


(PD7508H 


Block  Diagram 


po^SCR  po2/so  PO3/SI 


INT1  INTo 


Clock 
Control 
Circuit 


Timer/Event 
Counter 


Interrupt 
Controller 


Serial  I/O 
Interface 


Program 

Counter  (12) 

Program  Memory 
4096  x  8-bit  ROM  (/xPD7508H) 


ALU 


H 


General  Registers 


A 


E(4) 


Stack  Pointer  (8) 


Data  Memory 
224  x  4-bit  RAM  (MPD7508H) 


System 
Clock 

Standby 
Control 

Generator 

\     t  I 

t  t 


Port  0 
Buffer 


\^  Buffer  P10-P13 

—A  Port  2   \ 

)  Latch  4  ) 
 J/  Buffer   J/ 


Port  4 

,  j  Latch 
\  1/  Buffer 


/  \        Port  5 

[  )  Latch 
\  Y  Buffer 


Port  3 
Latch 
Buffer 


3 


P2Q-P23 


/  P20/PSTB.  \ 

\P21/PT0UT/ 


ft 


P50-P53 


Port  6 
Latch 
Buffer 


AA         Port  7  A— \ 
[        )        Latch       {    4  > 
Buffer  \j-y 


Clock 
Out 


RESET  vdd 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  2.7V  to  5, 


,5V 


Parameter 

Symbol 

Min 

Typ 

Max 

Unit 

Test  Conditions 

V,H 

0.7  VDD 

VDD 

All  Inputs  Other  than  X1 

Input  Voltage  High 

V,H2 

VDD-0.5 

Vdd 

V 

X1 

09VODDR 

Vdddr+0.2 

RESET,  Data  Retention  Mode 

Input  Voltage  Low 

0 

0.3  Vdq 

V 

All  Inputs  Other  than  X1 

N 

0 

0.5 

*1 

Input  Leakage  Current  High 

'L,H 

3 

ItA 

All  Inputs  Other  than  X1 

v,  =  vDD 

'lH2 

10 

*1 

Input  Leakage  Current  Low 

'ul 

-3 

HA 

All  Inputs  Other  than  X1 

V,  =  OV 

'»-2 

-10 

X, 

Output  Voltage  High 

V0H 

vDD  -  1.0 

V 

VDD  =  5V  ±  10%,  l0H  =  -1.0  mA 

VDD  -  0.5 

VDD  =  2.7V  to  5.5V,  l0H  =  - 100  ^ A 

Output  Voltage  Low 

Vol 

0.4 

V 

VDD  =  5V  ±  10%,  l0L  =  1.6  mA 

0.5 

VDD  =  2.7V  to  5.5V,  l0L  =  400  ^A 

Output  Leakage  Current  High 

Iloh 

3 

tiA 

Vo  =  vDD 

Output  Leakage  Current  Low 

'lol 

-3 

Vo  =  0V 

Supply  Voltage 

VDDDR 

2.0 

V 

Data  Retention  Mode 

iDD1 

300 

900 

Normal  Operation 

VDD  =  5V  ±  10% 

150 

400 

VDD  =  3V  ±  10% 

Supply  Current 

•dd2 

2 

20 

^A 

Stop  Mode,  X1  =  0V 

VDD  =  5V  ±  10% 

0.5 

10 

VDD  =  3V  ±  10% 

'dddr 

0.4 

10 

Data  Retention  Mode 

Vdddr  =  2.0V 

3-77 

fiPD7508H 

AC  Characteristics 

Ta  =  -10°C  to  +70°C,  VDD  =  2.7V  to  5.5V 


Limits 


Parameter 

Symbol 

Min 

tvp 

Max 

Unit 

Test  Conditions 

120 

TBD 

TBD 

R  =  120  kH  ±  2% 
C  =  33  pF  ±  5% 

Vqo  =  5V  ±  10% 

fee 

60 

TBD 

TBD 

X,,  X2   

R  =  250  kO  ±  2% 

Vqq  =  3V  ±  10% 

System  Clock  Oscillation  Frequency 

60 

TBD 

KHz 

C  =  33  pF  ±  5% 

VDD  =  2.7V  to  5.5V 

10 

TBD 

TBD 

X1(  External  Clock 

VDD  =  5V  ±  10% 

*c 

10 

TBD 

VDD  =  2.7V  to  5.5V 

25 

32 

50 

X1;X2  Crystal  Oscillator 

EVENT  Frequency 

0 

300 

KHz 

EVENT 

VDD  =  5V  ±  10% 

*EVENT 

0 

135 

Vqq  =  2.7V  to  5.5V 

EVENT  Rise  and  Fall  Times 

tcR>  *cf 

0.2 

^s 

EVENT 

EVENT  Pulse  Width 

1.5 

EVENT 

Vqq  =  5V  ±  10% 

*XH»  hi. 

3.5 

(AS 

Vqq  =  2.7V  to  5.5V 

4.0 

SCK  is  an  input 

Vqq  =  5V  ±  10% 

SCK  Cycle  Time 

7.0 

(i.S 

VDD  =  2.7V  to  5.5V 

^KCY 

6.7 

SCK  is  an  output 

Vqq  =  5V  ±  10% 

14.0 

Vqq  =  2.7V  to  5.5V 

1.8 

SCK  is  an  input 

Vqq  =  5V  ±  10% 

SCK  Pulse  Width 

3.3 

H.S 

VDD  =  2.7V  to  5.5V 

tKH-tKL 

3.0 

SCK  is  an  output 

Vqq  =  5V  ±  10% 

6.5 

Vqq  =  2.7V  to  5.5V 

SI  Setup  Time  to  SCK  T 

*SIK 

300 

ns 

SI  Hold  Time  after  SCK  f 

450 

ns 

SO  Delay  Time  after  SCK  | 

*KSO 

850 

ns 

VDD  =  5V  ±  10% 

1200 

VDD  =  2.7V  to  5.5V 

Port  1  Output  Setup  Time  to  PSTB  | 

*PST 

1/(2^-800) 

ns 

VDD  =  5V  +  10% 

1/(2^-2000) 

VDD  =  2.7V  to  5.5V 

Port  1  Output  Hold  Time  after  PSTB  f 

*STP 

300 

350 

500 

VD0  =  5V  ±  10% 

300 

1500 

ns 

VDD  =  2.7V  to  5.5V 

PSTB  pulse  Width 

f/(2f(f)-800) 

ns 

VDD  =  5V  ±  10% 

tsWL 

f/(2f(j)-2000) 

VDD  =  2.7V  to  5.5V 

INT0  Pulse  Width 

V 

10 

|tS 

INT,  Pulse  Width 

(AS 

RESET  Pulse  Width 

tRSH>  «RSL 

10 

(jlS  - 

Capacitance 

Ta  =  25°C,  VDD  =  OV 


Limits 

Test 

Parameter 

Symbol 

Min  Typ 

Max 

Unit 

Conditions 

Input  Capacitance 

c, 

15 

pF 

f  =  1  MHz 

Output  Capacitance 

Co 

15 

PF 

Unmeasured  pins 

Input/Output  Capacitance 

C|/o 

15 

PF 

returned  to  Vss 

3-78 


^PD7508H 


Timing  Waveforms 

Clocks 


Serial  Interface 


Output  Strobe 


> 


—  V|H 
"—  V|L 


J 


—  V|H 

—  V|L 


External  Interrupts 

INTo  


J 


—  V|H 

—  V|L 


—  V|H 

—  V,L 


3-79 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD7508HC 

Plastic  Shrinkdip,  (xPD7508HCU 


3  -  80  7508HDS-Rev1-7-83-CAT-L 


"  CMOS  4-BIT  SINGLE  CHIP 

MICROCOMPUTER  WITH 
LCD  CONTROLLER/DRIVER 


Description 

The  jxPD7514  CMOS  4-bit  single  chip  microcomputer 
has  the  standard  ^PD750X  architecture.  It  contains  4K  x 
8-bits  of  program  memory  ROM,  256  x  4-bits  of  data 
memory  RAM,  an  8-bit  timer/event  counter,  and  an  8-bit 
serial  interface. 

The  on-chip  LCD  controller/driver  is  capable  of  driving  a 
variety  of  LCD  displays  configured  from  biplexed  to  quad- 
riplexed  (2-4  backplane).  It  can  utilize  up  to  32  segment 
and  4  common  drive  lines  that  are  output  from  a  128-bit 
(32  x  4)  display  data  memory. 

The  |xPD7514  also  features  4  vectored  interrupts  (2  internal 
and  2  external)  and  2  standby  modes.  It  is  available  in  the 
80-pin  plastic  flat  package  to  conserve  space  and  is  man- 
ufactured with  a  low  power  consumption  CMOS  process 
allowing  the  use  of  a  single  5V  power  supply.  A  powerful  92 
instruction  set  (subset  of  ^PD750X  Instruction  Set  A) 
allows  greater  software  flexibility. 
The  |jlPD7514  is  capable  of  forming  a  system  with  a 
minimum  amount  of  additional  circuitry.  It  is  designed  to 
operate  with  low  power  and  can  be  used  for  a  wide  variety 
of  applications  because  the  chip  can  generate  a  reference 
clock  for  timer  operations. 

Features 

□  4-bit  single  chip  microcomputer 

□  92  instructions  (subset  of  |jlPD7500  set  A) 

□  Instruction  cycle:  5|xs/400kHz  at  5V 

□  Program  memory  (ROM):  4096x8  bits 

□  Data  memory  (RAM):  256x4  bits 

□  Vectored  interrupts:  2  externals,  2  internals 

□  8-bit  timer/event  counter 

□  8-bit  serial  interface 

□  On-chip  LCD  controller/driver 
- 1/2  bias:  biplexed,  triplexed 
-1/3  bias:  triplexed,  quadriplexed 

-  Segment  outputs:  32  lines 

-  Common  outputs:  4  lines 

□  Standby  modes  (stop/halt) 

□  Low-power  data  retention  capability 

□  31  I/O  lines 

□  On-chip  RC  oscillator  for  system  clock 

□  On-chip  crystal  oscillator  for  count  clock 

□  CMOS  technology 

□  Single  power  supply 

□  80-pin  plastic  flat  package 


Pin  Configuration 


£  *  « 
t  o  o  _ 
=  (/)</)</) 


X2  [ 


COM3  [ 

COM2  [ 
COWL,  [ 
COWI0[ 
S3i[ 

s30[ 
s29[ 

S28C 
S27[ 


CZZ 


nnnnnnnnnnnnnnm 


80  79  78  77  76  75  74  73  72  71  70  69  68  67  66  65 

1  64 

2  63 

3  62 

4  61 


HPD7514 


25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40 


yyyyyyyyyuyyyyyu 


3  PI, 
]P12 

]P13  

3  P20/PSTB 
3  P21/PTOUT 
]P22 

1  P7i 
]P72 
]P73 
]CL2 
]  CL, 
]  RESET 
]  INT1 
]S0 


]S3 
]  NC 


Pin  Identification 


Pin 

Function 

No. 

Symbol 

1,2 
79,  80 

P40-P43 

I/O 

I/O  pins  (4  bits)  of  Port  4  (4-bit  I/O  port). 

3,4 

Count  Clock  Oscillation  pins  to  be  connected  to 
crystal.  X,  is  for  External  Clock  input. 

5-7 

Vlci-Vlc3 

LCD  bias  voltage  supply  input  pins. 

8-11 

COM0-COM3 

LCD  common  signal  output  pins. 

12-22, 

24-32, 
34-41, 

s0-s31 

LCD  segment  signal  output  pins. 

43-46 

33 

VDd 

Power  supply  positive. 

47 

INT1 

External  Interrupt  input  pin. 

48 

RESET 

Reset  input  pin. 

49,  50 

CL,,  CI-2 

System  Clock  Oscillation  pins  to  be  connected  to  RC. 
CL1  is  for  External  Clock  input. 

51-54 

P70-P73 

I/O 

I/O  pins  (4  bits)  of  Port  7  (4-bit  I/O  port). 

55 
56 
57 

P22 

P2VPTOUT 
P2o/PSTB 

Output  pins  (3  bits)  of  Port  2  (3-bit  output  port).  Com- 
monly used  as  Strobe  output  (PSTB)  for  Port  1  output, 
TOUT  output  (PTOUT). 

58-61 

PI0-PI3 

I/O 

I/O  pins  (4  bits)  of  Port  1  (4-bit  I/O  port),  not  including 
latches. 

62,  63, 
65, 66 

P30-P33 

Output  pins  (4  bits)  of  Port  3  (4-bit  output  port). 

64 

VSs 

Ground. 

67 
68 
69 
70 

PO3/SI 
P02/SO 
PO^SCK 
POq/INTO 

I/O 
I/O 

Input  pins  (4  bits)  of  Port  0  (4-bit  input  port).  Com- 
monly used  as  interrupt  Request  input  (INTO),  Serial 
Clock  I/O  (SCK),  Serial  Data  input  (SI),  Serial  Data  out- 
put (SO). 

71-74 

P60-P63 

I/O 

I/O  pins  (4  bits)  of  Port  6  (programmable  4-bit  I/O  port). 

75-78 

P50-P53 

I/O 

I/O  pins  (4  bits)  of  Port  5  (4-bit  I/O  port). 

3-81 


MPD7514 

Block  Diagram 


SCK/PO,  SI/PO3 
INT1    INTO/P00  SO/P02 


Count 

Clock 
Generator 

Clock 
Control 

Timer/Event 
Counter 

Interrupt 
Control 

Serial 
Interface 

Data  Memory 
256  x  4  Bits 


System 

Clock 

Generator 

Standby 
Control 

LCD  Controller/Driver 


CL,  CL2 


Reset    VDO  V. 


K PortO  / 


P00-P03 


OBCC>pvp,> 


-N" 
V 


Port  2 
Latch 
Buffer 


P5TB/P20 
PTOUT/P2, 


D(4) 

E(4) 

H(4) 

L(4) 

Stack  Pointer  (8) 

P30-P33 


o 


M  Porta  I  \ 

)  Latch  4  > 

y/|  BuffeV  I  y/ 

/  \|  Port  4  \/[  \ 


o 


Port5 
Latch 
Buffer 


OPor.6 

Latch  f  4  >P70-P73 
Buffer  IV^X 


r°°  Vss    VLC1_3      COMo_3  So_31 


3-82 


fxPD7514 


Program  Memory  (ROM) 

Program  Memory  is  a  mask-programmable  ROM  of  4096- 
word  x  8-bit  configuration,  and  is  addressed  by  the  program 
counter.  Program  Memory  stores  programs  and  table  data. 

The  address  locations  of  the  program  memory  are  from 
000H  to  FFFH.  RESET,  Interrupt,  start  address,  and  the 
table  areas  of  LHLT  and  CALT  instructions  have  been  allo- 
cated specific  memory  locations.  When  a  program  is 
generated,  the  aforementioned  memory  locations  must  be 
taken  into  consideration. 


Program  Memory  Map 


01  OH 

020H 

030H 

0C0H 

OCFH 
0D0H 


RESET  Start  Address 


INTT  Start  Address 


INTO/S  Start  Address 


INT1  Start  Address 


Look-up  Table  of 
LHLT  Instruction 


Look-up  Table  of 
CALT  Instruction 
(Call  Address  Table) 


Subroutine 

Entry 

Addresses 


Timer/Event  Counter  Configuration 


7S 


Internal  Bus 

8  H  TAMMOD* 


8-bit  Modulo  Register 


8-bit  Comparator 


7T 


Count  Hold 
Circuit 


8-bit  Count  Register 


5 


Timer 
Out  F  F 


►  (Coincidence  Signal) 
INTT 


Timer 
Reset* 


►  TOUT  (to  Serial  Interface) 


Notes:  0  CP  is  a  count  pulse  selected  by  the  clock  mode  register 
®  CM3  is  used  for  output  designation  of  the  time-out  F/F 
®  *  indicates  execution  of  instruction 


3-83 


(PD7514 


Serial  interface  is  used  to  input/output  serial  data  and  is 
basically  composed  of  an  8-bit  shift  register,  a  4-bit  shift 
mode  register  and  a  3-bit  counter. 

Serial  Interface  Block  Diagram 


POp/INTO  O- 


IP* 
IPL* 


PO3/SI  O  £>- 


POj/SO  o  *  


I  I         8-bit  Shift  Register 

I  I  I  I  I 

LSB  |  ,  ,  ,  , 


I     l  l 


I     i  I 


IE 


Shift  Mode  Register 


i  I 
3-bit  Counter 


-  TOUT 

-  <I> 


R 

RS  F 

F 

Q 

S 

Notes:  ©  4>  indicates  the  internal  clock  signal  (system  clock) 

®  TOUT  is  the  timer-out  F/F  signal 

®  *  indicates  the  execution  of  instruction 

©  SM3  is  to  the  interrupt  controller 


3-84 


,xPD7514 


LCD  Controller! Driver  Block  Diagram 


Data  Memory 


DM3         DM2         DM1  DM0 

Display 

Mode 

Register 

I 

Timing  Controller 

LCD  CL 

Multiplexer 
Note:  *  indicates  instruction  execution 


The  LCD  controller/driver  consists  of  a  4-bit  display  mode 
register  (DMO  -  DM3),  128-bit  (32  x  4)  display  data  memory 
(i.e.,  addresses  from  00H  to  1 FH  in  data  memory),  a  timing 
controller,  multiplexers,  an  LCD  drive-voltage  controller, 
segment  drivers,  and  common  drivers. 
The  LCD  controller/driver  provides  an  LCD  direct  drive 
function  with  1/2  bias  voltage  (biplexed,  triplexed)  and  1/3 
bias  voltage  (triplexed,  quadriplexed)  configurations.  For 
LCD  driver  outputs,  32  segment  lines  (S0  -  S31)  and  4 
common  lines  (COM0  -  COM3)  are  provided. 
Maximum  Segment  Number 


Bias  Multiplexing 

COM  Lines 

Maximum  Segment  Number 

Biplexed 

COM0,  com. 

64  (32  Segments  x  2  Commons) 

1/2   

Triplexed 

Triplexed 

-com0,  com,,  com2 

96  (32  Segments  x  3  Commons) 

1/3   

Quadriplexed 

com0,  com,,  com2,  COM3, 

128  (32  Segments  x  4  Commons) 

3-85 


|xPD7514 

Format  of  Shift  Mode  Register 


SM3  |  SM2  |  SM1  |  SMO  |  Shift  Mode  Register 


Serial  interface  Operation  and 
Mode  Setting  of  Port  0 


SM2 

SM1 

SMO 

P03/Sl 

POa/SO 

PO^SCK 

Serial  Operation 

0 

0 

0 

Port  Input 

0 

1 

0 

Port  Input 

Port  Input 

To  output  <t>  continuously 

Stop 

0 

1 

1 

To  output  TOUT  continuously 

1 

0 

0 

SCK  Input 

To  operate  with 
external  clock 

1 

1 

0 

SI  Input 

SO  Output 

SCK  Output  (<)>  x  8) 

To  operate  with  c)> 

1 

1 

1 

SCK  Output  (TOUT) 

To  operate  with 
TOUT 

Selection  of  INTO  or  INTS 


SM3 

Interrupt  Source 

0 

INTS 

1 

INTO 

Note:  <t>  =  System  Clock 

Interrupt  Controller  Block  Diagram 


Internal  Bus 


Notes:  ©  *  indicates  execution  of  instruction 

®  SM3  is  bit  3  of  the  shift  mode  register  (Selection  of  INTO  or  INTS) 


3-86 


Clock  Control  Circuit 


txPD7514 


To  Timer/Event 
Counter 


Prescaler  1 
(1/4) 


CM3 

CM2 

CM1 

CM0 

Clock  Mode  Register 


Prescaler  2 
(1/8) 


Prescaler  3 
(1/8) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Miniflat,  |xPD7514G 


3-87 


7514DS-7-83-CAT-L 


Notes 


3-88 


\FC  ^PD7519 
^  *  w  CMOS  4-BIT  SINGLE-CHIP 

MICROCOMPUTER  WITH  VACUUM 
FLUORESCENT  DISPLAY 
CONTROLLER/DRIVER 


Description 

The  |jlPD7519  is  a  CMOS  4-bit  single-chip  microcomputer 
which  has  the  |jlPD750x  architecture. 
The  (jlPD7519  contains  a  4096  x  8-bit  ROM,  and  a  256  x 
4-bit  RAM. 

The  |jlPD7519  contains  four  4-bit  general  purpose  registers 
located  outside  RAM.  The  subroutine  stack  is  implemented 
in  RAM  for  greater  nesting  depth  and  flexibility,  providing 
such  operations  as  the  pushing  and  popping  of  register 
values.  The  |jlPD7519  typically  executes  106  instructions 
of  the  |jlPD7500  series  A  instruction  set  with  a  7.637|xs 
instruction  cycle  time. 

The  |jlPD7519  has  two  external  and  two  internal  edge- 
triggered  hardware  vectored  interrupts.  They  also  contain 
an  8-bit  timer/event  counter,  an  8-bit  serial  interface,  and  a 
9-bit  D/A  programmable  pulse  generator,  to  help  reduce 
software  requirements.  The  on-board  vacuum  fluorescent 
display  controller/driver  supervises  all  of  the  timing  required 
by  the  24  Port  S  segment  drivers  either  for  a  16-digit  7- 
segment  vacuum  fluorescent  display,  or  for  an  8-character 
14-segment  vacuum  fluorescent  display. 
The  |xPD7519  provides  28  I/O  lines  organized  into  the 
4-bit  input/serial  interface  Port  0,  the  4-bit  output  Port  2, 
the  4-bit  output  Port  3,  and  the  4-bit  I/O  Ports  1 , 4,  5,  and  6. 
Additionally,  Port  1  can  be  automatically  expanded  to  16  I/O 
lines  through  connection  to  a  |xPD82C43.  The  |xPD7519  is 
manufactured  with  a  low  power  consumption  CMOS  pro- 
cess, allowing  the  use  of  a  single  power  supply  between 
2.5V  and  5.5V.  Current  consumption  is  less  than  2mA 
maximum,  and  can  be  lowered  much  further  in  the  Halt 
and  Stop  power-down  modes.  The  jxPD7519  is  available 
in  a  space-saving  64-pin  flat  plastic  package,  or  a  64-pin 
QUIL  package. 

There  is  also  a  piggyback  EPROM  version  available,  the 
75CG19E,  which  is  pin-compatible  and  functionally  equiv- 
alent to  the  masked  version.  It  is  excellent  for  prototyping 
and  program  development. 
Pin  Configuration 
64-pin  Plastic  Flat  Package 


64-pin  Plastic  QUIL  Package 


>  i—  i—  t—  i—  i 


h  i—  v-  t—  i—  y-  i—      en  co 


51  50  49  48  47  46 

45  44  43  42  41  40  39  38  37  36  35 

34  33 

52 

32 

— IS. 

P30r— 

53 

31 

=)S3 

P31|  

54 

30 

=DS4 

55 

29 

=3S5 

P3a|  

56 

28 

=DS6 

INT1C== 

57 

27 

Z=)S7 

VddCZI 

58 

(jlPD7519 

26 

=3VDD 

P2o/PstbCZ 

59 

25 

=)Vss 

P21/PT0UTCZZ 

60 

24 

 I  X, 

P22/PclCZ 

61 

23 

=)X2 

P23C= 

62 

22 

=ZD  EVENT 

RESET  CZ 

63 

21 

=Z)P43 

PPOIZZ 

64 

20 

=DP42 

1    2  3   4  5  6 

7   8  9  10  11  12  13  14  15  16  17 

18  19 

P43 
EVENT 


Pin  Identification 


Pin  Nos. 

Flat 

QUIL 

Symbol 

Description 

1 

7,  24 

NC 

No  connection 

2 
3 
4 
5 

8 
9 
10 
11 

POn/INTn 
PO^SCK 
POa/SO 
PO3/SI 

4-bit  input  Port  0/serial  I/O  interface  (active 
high).  This  port  can  be  configured  either  as  a 
parallel  input  port,  or  as  the  8-bit  serial  I/O 
interface,  under  control  of  the  serial  mode 
select  register.  The  Serial  Input  SI  (active  high), 
Serial  Output  SO  (active  high),  and  the  Serial 
Clock  SCK  (active  low)  used  for  synchronizing 
data  transfer  comprise  the  8-bit  serial  I/O 
interface.  Line  P00  is  always  shared  with 
external  interrupt  INT0,  which  is  a  rising  edge- 
triggered  interrupt. 

6-9 

12-15 

P60-P63 

4-bit  input/latched  three-state  output  Port  6 
(active  high).  Individual  lines  can  be  config- 
ured either  as  inputs  or  as  outputs  under 
control  of  the  Port  6  mode  select  register. 

10-13 

16-19 

P50-P53 

4-bit  input/latched  three-state  output  Port  5 
(active  high).  Can  also  perform  8-bit  parallel  I/O 
in  conjunction  with  Port  4. 

14-17 

20-23 

PI0-PI3 

4-bit  input/latched  three-state  output  Port  1 
(active  high). 

18-21 

25-28 

P40-P43 

4-bit  input/latched  three-state  output  Port  4 
(active  high).  Can  also  perform  8-bit  parallel  I/O 
in  conjunction  with  Port  5. 

22 

29 

EVENT 

1-bit  external  event  input  for  timer/event 
counter  (active  high). 

23-24 

30-31 

x2,  xn 

Crystal  clock  input  (active  high).  A  crystal 
oscillator  circuit  is  connected  to  input  X-,  and 
output  X2  for  system  clock  operation.  Alter- 
natively, an  external  clock  source  may  be 
connected  to  input  X1  while  output  X2  is  left 
open. 

25 

32 

Vss 

Ground. 

26,  58 

64 

VDD 

Power  supply  positive.  Apply  single  voltage 
ranging  from  2.5V  to  5.5V  for  proper  operation. 

27-34 
35-42 
43-50 

33-40 
41-48 
49-56 

s0-s7 

T8/S8-T15/S15 
T0-T7 

Vacuum  fluorescent  display  outputs  (active 
high).  S0-S7  are  always  segment  driver  out- 
puts, and  T0-T7  are  always  digit  driver 
outputs.  T8/S8-T15/Si5  can  be  configured  as 
either  segment  driver  outputs  or  as  digit  driver 
outputs  under  control  of  the  display  mode 
select  register. 

?  ia  <p  in  tn  j~*  rp 

.    Q_    0.    Q.   Q.    1    H    D.  a. 


Rev/1 
3-89 


fxPD7519 


Pin  Identification  (Cont.)  

 Pin  Hps.  

Wat  QUIL  Symbol  Description   

51  57  VLOAO       Vacuum  fluorescent  display  power  supply 

negative.  Apply  single  voltage  between 
VDO-35.0  and  VDD  for  proper  display 

 operation.  

52  58  VPRE        Power  supply  for  VFD  driver.  

53-56         59-62         P30-P33     4-bit  latched  three-state  output  Port  3 

 (active  high).  

57  63  INT,  External  Interrupt  INT,  (active  high).  This  is  a 
 rising  edge-triggered  interrupt.  

59  1  P2(/Pstb      4-bit  latched  output  Port  2  (active  high).  Line 

60  2  P2i/Ptout     P2° is  a,so  snared  witn  pstb>  tne  port  1  output 

strobe  pulse  (active  low).  Line  P21  is  also 
shared  with  PTn„T,  the  timer-out  F/F  signal 
(active  high).  OUT 

61  3  P22/PCl      Internal  system  clock  output. 

62  4  P23         General  purpose  output.  

63  5  RESET  RESET  input  (active  high).  R/C  circuit  or  pulse 
 initializes  M-PD7502  or  nPD7503.  

64  6              PPO        1-bit  programmable  pulse  generator  output 
 (active  high).  


Operating  Supply  Voltage 

Ta  =  -10°Cto  +70°C  

Limits 

Parameter  Min  Typ  Max  Unit  Teat  Conditions 


CPU  © 

4.0 

6.0 

V 

High-speed  Mode  (EM2  =  1) 

2.5 

6.0 

V 

Low-speed  Mode  (EM2  =  0) 

Crystal  Oscillation 
Circuit 

2.7 

6.0 

V 

C,  =  10pF, 
Crystal               C2  « 10pF 

2.85 

6.0 

V 

Oscillation   ©       rj,  =  10pF, 
C2  «  22pF 

2.5 

6.0 

V 

External  Clock  © 

Display  Controller 

4.0 

6.0 

V 

Programmable  Pulse 
Generator 

4.0 

6.0 

V 

Portl 

2.5 

6.0 

V 

Port  Output  Mode 

4.0 

6.0 

V 

I/O  Expander  Mode 

Notes:  See  notes  ©  and  ©  after  AC  Characteristics  tables 


Block  Diagram 


POa/SO 


P03/Sl 


INT,  POo/INTo 


V 


12-bit  Program  Counter 


5Z 


Program  Memory 
4096  X  8-bit  ROM 


Instruction 
Decoder 


Standby 
Control 

Clock 
Generator 

Programmable 
Pulse 
Generator 

1 1 


Clock 

Timer/Event 

INTT 

Interrupt 

INTS 

Serial  I/O 

Selector 

Counter 

Controller 

Interface 

K PortO  /~ 


c 

A  (4) 

General  Registers 


E(4) 


L(4) 


o 


Data  Memory 
256  x  4-bit  RAM 


Vacuum  Fluorescent  Display 
Controller/Driver 


o 


Port  1 
Buffer 


Port  2 
Latch 
Buffer 


to 


a Port  4  S~\ 


y  x        Port  5 

C  )  Latch 

Vn/1  Buffer 


*\       Port  3  X 
)      Latch  4  y\ 

I  v       Buffer   V 


P30-P33 


O Porte  y1 — \ 


xi     x2  ppO         RESET  Vss  VDD  VPRE  VLOAD  S0-S7 

VS8-Ti5/S15 
T0-T7 


3-90 


,xPD7519 


Absolute  Maximum  Ratings* 

Ta  =  25°C 

VDD  =  -0.3V  to  +  7.0V 

VLOad  =  VDD-40Vto 

Supply  Voltage 

VDD  +  0.3V 

VpRE  =  VDD-12Vto 

VDD  +  0.3V 

Input  Voltage,  V, 

-0.3VtoVDD  +  0.3V 

Output  Voltage 

Outputs  other  than  display  outputs 

V0  =  -0.3V  to 

VDD  +  0.3V 

Display  outputs 

VOD  =  VDD-40Vto 

VDD  +  0.3V 

Output  Current  High,  Iqh 

Per  pin  other  than  display  outputs 

-15mA 

Per  pin,  S0-S7 

-15mA 

Per  pin,  T0-T7,  Ta/Sa-iVS^ 

-30mA 

Total,  all  outputs  other  than  display  outputs                  -  20mA 

Total,  all  display  outputs 

-120mA 

Output  Current  Low,  lOL 

Per  pin 

17mA 

Total,  all  outputs 

60mA 

Total  Power  Consumption,  PT  ® 

Plastic  flat  package 

400mw 

Plastic  QUIL  package 

600mw 

Operating  Temperature,  Tqpt 

-10°Cto  +  70°C 

Storage  Temperature,  TStg 

-40°C  to125°C 

Note:  ©  See  note  ©  after  AC  Characteristics  tables 

*  COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be 
operated  under  conditions  outside  the  limits  described 
in  the  operational  sections  of  this  specification.  Expo- 
sure to  absolute  maximum  rating  conditions  for 
extended  periods  may  affect  device  reliability. 


Capacitance 

Ta  =  25°C;  VpD  =  OV 


Limits 

Test 

Parameter 

Symbol 

Min  Typ  Max 

Unit 

Conditions 

Input  Capacitance 

C|N 

15 

pF 

Output  Capacitance 

15 

PF 

f  =  1MHz 

Other  than  display  outputs 

C0UT 

35 

Unmeasured  pins 

Display  outputs 

PF^ 

returned  to  0V. 

I/O  Capacitance 

C,o 

15 

PF 

DC  Characteristics 

T.  =  -10°Cto  +70°C;  VDD  =  2.5V  to  6.0V 


Limits 

Test 

Parameter 

Symbol    Min  Typ 

Max 

Unit 

Conditions 

Other  than  X,,  X2 

V,hi  0.7VDD 

vDD 

V 

input  Voltage   3 — - 

High  x1(X2 

VIH2  VDD-0.4 

VoD 

V 

© 

Input  Voltage  0*ner  than  X1>  X2 

V.L1           0  t 

•3VDD 

v 

Low  x1fX2 

V,L2  0 

0.4 

V 

© 

Output  Voltage  High 

Vqd  - 1.0 

v 

VDD  =  5V  ±  0.5V; 
l0H  =  -1mA 

v0H   

VDD  -0.5 

V 

l0H=  -100m.A 

Output  Voltage  Low 

Vol 

0.4 

V 

VDD  =  5V  ±  0.5V; 
l0L  =  1.6mA 

0.5 

V 

l0L  =  400(jiA 

Input  Leakage  Other  than  Xi,  X2 

•lihi 

3 

HA 

VIN  =  VDD 

Current  High    ^  Xj 

'LIH2 

20 

|JlA 

Input  Leakage  Other  than  X1f  X2 

'lili 

-3 

VIN  =  OV 

Current  Low    ^  x^ 

'LIL2 

-20 

yA 

Output  Leakage  Current  High 

•loh 

3 

^A 

VOUT  =  VDD 

Output  Leakage  Current  Low 
Other  than  display 
outputs 

'loli 

-3 

(xA 

V0UT  =  0V 

Display  outputs 

'lou 

-10 

V* 

^OUT      ^LOAD  ^DD 

-35V 

-7 

mA 

VDD  =  4V  S0-S7 

-15 

mA 

to6V;           T  x 

Display  Output  Current 

■OD   

mA 

VPRE      VDD     „  „ 

-9  ±  1V©  S0-S7 

-7 

mA 

V0D  =  VDD  T0-T15 
-  2V; 

vPRE  -  OV 

Resistance 

(On-chip,  pull-down  resistor) 

RL        100  150 

200 

kil 

600 

2000 

^A 

Vdd  = 
5V  ± 
0.5V, 
High 
speed 

fx  =  4.19MHz  

VDD  = 
3V  ± 
0.5V, 
Low 

'DD1  onn 
200 

700 

IxA 

Supply  Current  © 

speed 

260 

800 

jxA 

VDD  = 

Halt  Mode     5V  ± 
(Low  speed)  °-5V 

'DD2  120 

400 

M-A* 

C1  =  C2         VDD  = 
=  10pF        3V  ± 
0.5V 

10 

VA 

Stop  Mode 

Notes:  See  notes  ©,  ©,  and  ©  after  AC  Characteristics  tables 

AC  Characteristics 

Ta  =  10°Cto  +70°C 

Clock  Operation  (VDD 

=  2.5V  to  6.0V) 

Limits 

Test 

Parameter 

Symbol    Min  Typ 

Max 

Unit 

Conditions 

System  Clock  Oscillation 
Frequency 

fxx        3.5  4.19 

5.0 

MHz 

Crystal  Oscillation 

®,  © 

System  Clock  Input  Frequency 

fx  0.1 

5.0 

MHz 

X1t  X2  Input  Pulse  Width,  High 
and  Low 

tXH.  tXL  100 

ns 

External  Clock  © 

EVENT  Input  Frequency 

410 

kHz 

VDD  =  4Vto6V 

h 

80 

kHz 

EVENT  Input  Pulse  Width,  High 

1.2 

M-S 

V0D  =  4Vto6V 

and  Low 

tEH'tEL  6.25 

US 

Note:  See  notes  ©  and  ©  after  AC  Characteristics  tables 


3-91 


fxPD7519 

AC  Characteristics  (Cont.) 


Port  1 1/O  Operation  (VDD  = 

2.5V  to  6.0V) 

,  Parameter 

Symbc 

Limits 

il      Min   Tun  Uav 
1      man    my§9  fflo A 

Test 
Conditions 

Port  1  Output  Set-up  Time 
(to  P§T§  t ) 

*PST 

400 

ns 

Port  1  Output  Hold  Time 
(after  P§f5  f ) 

*STP 

100 

ns 

Port  Output  Mode 

P§t§  Pulse  Width  Low 

tsTu 

600 

ns 

Output  Data  Set-up  Time 

<tOP§Tlt) 

tDST 

400 

ns 

Output  Data  Hold  Time 
(after  Pffgt) 

100 

ns 

input  Data  vaiia  Time 
(after  Pgrfl) 

lSTDV 

input  Data  Floating  Time 
(after  P|f5T) 

*STDF 

0 

ns 

I/O  Expander  Mode 
VDD  =  4Vto6V 

Control  Set-up  Time 
(toPsrSl) 

*CST 

400 

ns 

Control  Hold  Time 
Output  Command 
Input  Command 

tSTC 

100 
0  80 

ns 
ns 

P§t§  Pulse  Width  Low 

Wl2 

1200 

ns 

Serial  Interface  Operation  (VDD  = 

2.5V  to  6.0V) 

Limits 

Test 

Parameter 

Symbol 

Min 

Typ  Max 

Unit 

Conditions 

3.0 

(AS 

Input    vdd  =  4V 

SCK  Cycle  Time 

*KCY 

12.5 

(AS 

to6V 

4.9 

(AS 

output  2»;4V 

25 

(AS 

1.3 

(AS 

Input    vdd  =  4V 

SCK  Pulse  Width  High,  Low 

6.5 

us 

H  to6V 

2.2 

(AS 

11.5 

(AS 

SI  Set-up  Time  (to  SCK  f ) 

300 

ns 

VDD  =  4Vt0  6V 

*SIK 

1000 

ns 

SI  Hold  Time  (after  SCK  f) 

*KSI 

450 

ns 

VDD  =  4Vt0  6V 

1000 

ns 

SO  Output  Delay  Time 

*KSO 

850 

ns 

VDD  =  4Vto6V 

(after  SCK  4 ) 

2000 

ns 

Other  Operation  (VDD 

=  2.5V  to  6.0V) 

Limits 

Test 

Parameter 

Symbol 

Min 

Typ  Max 

Unit 

Conditions 

INT0  Pulse  Width  High,  Low 

*I0H»  *I0L 

10 

|AS 

INT,  Pulse  Width  High,  Low 

II1H>  ^IL 

® 

|AS 

RESET  Pulse  Width  High,  Low 

*RSH>  *RSL 

10 

(AS 

Notes:  ©  Calculation  of  Total  Power  Consumption 
The  (xPD7519  has  three  kinds  of  power  consumption,  the  total  for  which 
should  be  less  than  the  total  power  consumption  (PT)  given  in  the  specifi- 
cations. (Use  under  the  condition  that  less  than  80%  of  the  specification 
is  recommended.) 

1.  Power  consumption  of  CPU:  VDD(max)  x  lDD1  (max) 

2.  The  power  consumption  of  output  pins  can  be  classified  as  normal 
output  and  display  output.  The  total  power  consumption  of  each  output  pin 
to  which  the  maximum  current  flows  should  be  calculated. 

3.  The  power  consumption  of  on-chip  pull-down  resistors  (mask  option) 
on  display  output  lines.  See  following  example: 

Example: 

Configuration  9  segments  x  11  digits,  4  LED  outputs 

VDD  =  5V  ±  10% 

Segment  pin    =  5mA  (max) 

Timing  pin      =  1 5mA  (max) 

LED  output  pin  =  10mA  (max) 
Vacuum  Fluorescent  Display  (VL0AD)  =  -30V 
CPU.  5  5V  x  2  0mA  =  11mW  .  .  .  (1) 

Output  Pins 

Segment  pins'  (5/7  x  2V)  x  5mA  x  9  =  64mw 
Timing  pins  2V  x  15mA  =  30mw 
LED  output  pins  (10/15  x  2V)  x  10mA  x  4  =  53mw 
Pull-down  Resistors 
(30  +  55V)2 


©  Except  Crystal  Oscillation  Circuit,  Display  Controller,  Programmable 

Pulse  Generator,  and  Port  1 . 
®  The  following  circuits  are  recommended: 

Crystal 


HQ 


Serial  resistance  equivalent  to 
crystal  is  assumed  less  than  8012. 


External  Clock 


High-speed 
CMOS  inverters 


External  Clock 


The  following  external  circuit  is  recommended: 


Note:  RD91EL  Zener  diode  (NEC) 

Zener  voltage  =  8.29V  to  9  30V 


©  Display  Controller  and  Programmable  Pulse  Generator  are 

not  operated. 
©  Refer  to  Operating  Supply  Voltage. 
©  28/fxor28/fxx. 


x  10  =  126mw 
1000 

Therefore 

PT  =  (1)  +  (2)  +  (3)  =  284mw 


(2) 
(3) 


3 


-92 


Timing  Waveforms 

AC  Test  Points  (Except  XYj 


0-7  VDD  0.7  VDD 

X»DC 

0.3  VDD  Points      0.3  yDD 


Clock  Timing 


X1  Input  - 


EVENT  Timing 


-i/fx- 


-1/fE- 


Strobe  Output  Timing 


P10-  P13  —(Output  Data 

PlTB 


'"*'^STL1*' 


Port  1 1/O  Expander  Timing 


Expander     Port  Control     ^Output  C 

Port  

Output 


Expander 
Port 
Input 

Port  Control' 


,nPut  ""^KtCST*j 


Serial  Interface  Timing 


— W>    lnPut  Data 
SO  X    Output  Data  )( 


Interrupt  Input  Timing 


INT, 

(Rising  Edge  Triggered) 


INT, 

(Falling  Edge  Triggered) 


RESET  Input  Timing 


I 


MPD7519 


Stop  Mode  Low  Voltage  Data  Retention 
Characteristics 

Ta  =  -  10°Cto  +70°C 


Parameter 

Symbol 

Limits 

Unit 

Test 

Min 

Typ  Max 

Conditions 

Data  Retention  Supply  Voltage 

VDDDR 

20 

6.0 

V 

Data  Retention  Supply  Current 

'dddr 

10 

VDdor  =  2  0V 

Reset  Set-up  Time 

tsRS 

0 

|XS 

Data  Retention  Timing 


—Stop  Mode— 


Data 
Retention -i 
Mode 


Execution  of 
Stop  Instruction 


3 


-93 


,.PD7519 


Operating  Characteristics 

Ta  =  25°C,  Typical 


Supply  Current  versus  Supply  Voltage 
lDDvsVDD(fxx  =  4.19MHz) 


Supply  Current  versus  External  Clock  Frequency 
Idd  vs  fx 


Supply  Current, 
lDD(^A) 


Hig 

h-speed  Opera 

mg  Mode^^ 

Low-spe 

id  Operating  M 

ide^^ 4igh- 
<r  Halt-Mode 

speeti^  

Low-speed  Hi 

It  Mode^^ 

|                x2  I 

lOpFljl   419MHz  :j=10pF 
I 

Supply  Current, 
Idd(^A) 

300 


2.0  3.0  4  0 

External  Clock  Frequency,  fx  (MHz) 


3  0  4.0  5  0 

Supply  Voltage,  VDD  (V) 


Supply  Current  versus  Clock  Oscillation  Frequency 

iDDVSfxx 


Segment  Output  Current  versus  Output  Voltage 
ho  vs  (VDD  -  VOD);  (VDd  =  4V  to  6V) 


Supply  Current, 
'dd  (l^A) 


10pF 


Xi  


10pF 


1.0  2.0  3.0  4.0 

Clock  Oscillation  Frequency,  fxx  (MHz) 


Segment  Output  Current, 
lOD  (mA) 


3-94 


Operating  Characteristics  (Cont.) 

Ta  =  25°C,  Typical 


,PD7519 


Timing  Output  Current  versus  Output  Voltage 
Iod  vs  (VDD  -  VOD);  (Vdd  =  4V  to  6V) 


Output  Current  Low  versus  Output  Voltage  Low 
Iol  vs  Vql 


Timing  Output  Current, 
'oD(mA) 


Output  Current  High, 
•oh  (n«A) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Quit,  |jlPD7519G 

Plastic  Shrinkdip,  |xPD7519CW 

QUIL  Ceramic  Piggyback,  |xPD75CG19E 


Output  Current  High  versus  Output  Voltage  High 
I  OH  vs  (VDD  -  VOH) 


Output  Current  Low, 
•ol  (mA) 


VOD  =  6V 

/Dor=  5V 
ZVDD  =  4\ 

/ 

"VDD  =  3V 

 vDD 

=  2.5V 

1.0  2  0  3.0  4.0 

Output  Voltage  Low,  VOL  (V) 


7519DS-REV1-8-83-CATL 

3-95 


Notes 


3-96 


SEC  MPD7520 
^  ^  4-BIT  SINGLE  CHIP 

MICROCOMPUTER  WITH  LED  DISPLAY 
CONTROLLER/DRIVER 


Description 

The  uPD7520  is  a  low-cost  4-bit  single  chip  microcom- 
puter which  shares  the  4th  generation  architecture  of 
the  fiPD7500  series  of  CMOS  4-bit  microcomputers.  It 
contains  a  768  x  8-bit  ROM  and  a  48  x  4-bit  RAM.  It 
has  a  2-level  subroutine  stack,  and  executes  a  47- 
instruction  subset  of  the  ^PD7500  series  instruction  set. 
The  /iPD7520  provides  24  I/O  lines,  organized  into  the 
4-bit  input  Port  1,  the  4-bit  I/O  Port  4,  the  2-bit  output 
Port  3,  the  8-bit  output  Port  S,  and  the  6-bit  output  Port 
T.  Ports  S  and  T  are  controlled  by  the  on-board  pro- 
grammable LED  display  controller/driver  hardware  logic 
block,  which  automatically  directly  drives  either  static  or 
multiplexed  common-anode  7-segment  LED  displays 
totally  transparent  to  program  execution.  The  ^PD7520 
is  manufactured  with  a  low-power  consumption  PMOS 
process,  allowing  use  of  a  single  power  supply  between 
-6V  and  -  10V,  and  is  available  in  a  28-pin  dual-in-line 
plastic  package. 

Pin  Configuration 


P3lC 

1 



28 

3  CLK 

P30C 

2 

27 

□  RESET 

P13C 

3 

26 

□  VQG 

P12C 

25 

□  s0 

P11C 

5 

24 

□  s4 

P1<>C 

6 

23 

□  si 

P*3C 

7 

22 

7520 

P42C 

8 

21 

P41C 

9 

20 

13*6 

P4oC 

10 

19 

3  s3 

T5C 

11 

18 

js7 

T4C 

12 

17 

□  T0 

13 

16 

□  T1 

vssC 

14 

15 

□  T» 

Pin  Names 


S0-S7 

Segment  Drive  Output  Port  S 

T0-T5 

Digit  Drive  Output  Port  T 

P10-P13 

Input  Port  1 

P3Q-P3! 

Output  Port  3 

P40-P43 

Input/Output  Port  4 

CLK 

Clock  Input 

RESET  Reset 

vGG 

Power  Supply  Negative 

vss 

Ground 

Further  details  on  device  operation  can  be  found  in  the 

^PD7520  4-Bit  Single  Chip  Microcomputer  Technical 

Manual. 

Absolute  Maximum  Ratings* 

Ta  =  25°C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Supply  Voltage,  Vqg 

-15Vto  +0.3V 

Input  Voltages 

-15V  to  +0.3V 

Output  Voltages 

-15V  to  +0.3V 

Output  Current  OoH  Total) 

-100mA 

(Iql  Total) 

90mA 

*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


Rev/1 
3-97 


MPD7520 

Block  Diagram 


2-Level  Stack 

7^  


10-Bit  Program  Counter 

<< 

768  x  8-Bit 
Program 


V 


Instruction 
Decoder/ 
Controller 


vgg   »~ 

Clock 

Vss   m~ 

Generator 

H 

(2) 

L 

(4) 

6 

48  x  4-Bit 

RAM  ^ 


v 


Latched 
Output 
Buffer 


2  y  P3Q-1 


In/Out 
Latched 
Buffer 


W  ,T6.7) 


LED  Display  Controller/Driver 


So-7 


3-98 


MPD7520 


DC  Characteristics 


Ta  a  -10°Cto  +70°C,  VGG  = 

-  6V  to  -  10V,  Vjs  =  OV 

Limits 

Parameter 

1                   Mm  Typ 

Max 

Unit 

Test  Conditions 

Input  Voltage  High 

V|H 

V 

Vqg  =  -9V  ±  1V 
Ports  1 ,  4,  RESET   

-1.8 

Vqq  =  -6VtO  -10V 

Input  Voltage  Low 

V|L 

Vqg  +  1-5 

DnrtB  ,  A  ppcct      VGG  =  -9V  ±  1V 
Ports  i ,  4,  HeScT  , 

Vqq  +  0.8 

Vqq  =  -6Vto  -10V 

Clock  Voltage  High 

V*H 

-0.8 

V 

CLK,  External  Clock 

Clock  Voltage  Low 

Vii 

-5.0 

V 

CLK,  External  Clock 

Input  Current  High 

>IH 

45 

200 

MA 

»  _  .  „„„           V|  =  0V,  Vqq  =  -9V  ±  1V 
Port  1,  RESET            1  uu 

40 

200 

V,  =  0V,  Vqq  =  -6Vto  -10V 

Input  Leakage  Current  High 

•lih 

+  5 

ma 

Port  4,  V|  =  0V 

Input  Leakage  Current  Low 

It  11  . 
UL1 

-5 

ma 

Port  1,  RESET,  V|  =  -10V,  Vqq  =  -10V 

'lil2 

-5 

ma 

Port  4,  V|  =  -10V 

Clock  Current  High 

■<|>H 

0.5 

mA 

CLK,  External  Clock,  V+H  =  0V,  Vqq  =  -9V  ±  1V 

Clock  Current  Low 

'<(.L 

-2.1 

mA 

CLK,  External  Clock,  V^_  =  -5V,  Vqq  =  -9V  ±  1V 

Output  Voltage  Low 

vOL 

0  6  Vqq 

V 

Port  3,  No  Load 

lO»i 

-1.0 

V0  =  -1.0V,  Vqq  =  -9V  ±  1V 

-0.6 

V0  =  -1.0V,  Vqg  =  -6V 

'OH2 

-2.0 

V0  =  -1.0V,  Vqq  =  -9V  ±  1V 

-1.2 

V0  =  -1.0V,  Vqg  =  -6V 

Output  Current  High 

-5  -10 

V0  =  -2.0V,  Vqg  =  -9V  ±  1V 

-3  -6 

mA 

Port  S,      V0  «  -2.0V,  Vqg  =  -6V 

-1  -3 

V0  =  -1.0V,  Vqq  =  -6Vto  -10V 

-24  -48 

V0  =  -2.0V,  VQG  =  -9V  ±  1V 

•oh 

4 

-13  -27 

mA 

PortT,      Vo  =  -1.0V,  VGG  =  -9V  ±  1V 

-9  -18 

V0  =  -1.0V,  Vqg  =  -6V 

'OL! 

1.0  2.0 

mA 

Port  a,      V0  =  VQG  +  15V'  VGG  =  _9V  ±  1V<3> 

Output  Current  Low 

0.3  0.6 

V0  =  -4.5V,  Vqq  =  -6V(1) 

•OL2 

4.5  9 

mA 

Vo  =  Vqg  +  5.0V,  Vqg  =  -9V  ±1V 
Port  S,   

1.0  2.0 

V0  =  Vqg  +  3.5V,  Vqq  =  -6Vto  -10V 

Output  Leakage  Current  High 

'loh 

+  5 

mA 

Ports  4,  T,  V0  =  0V 

Output  Leakage  Current  Low 

'LOL! 

-5.0 

pA 

PortT,  V0  =  -10V 

•lol2 

-5.0 

Port  3,  V0  =  Vqg 

Supply  Current 

■gg 

-5(2) 

-9.8 

mA 

No  Load 

Notes: 

(T)  Current  within  2.5  ms  after  turning  to  the  low  level  (Ta  =  25°C). 

®  Ta  =  25°C,  Vqg 

=  -9V 

AC  Characteristics 

Capacitance 

Ta  =  -10°Cto  +70°C,  VGG  = 

-6Vto  -10V 

Ta  =  25  °c 

Limits 

Limits 

Parameter  Symbol 

Min 

Typ 

Max      Unit       Test  Conditions 

Parameter 

Symbol 

Min       Typ      Max      Unit        Test  Conditions 

225 

300 

Rf  =  1MQ, 
375        KHz       Vqq  =  -9V  ±  1V, 
Ta  =  25 »C 

Input 

Capacitance 

C| 

Portl, 

15         "F  RESET 

Clock  f°sc 

Output 
Capacitance 

Ports  3, 
20         pF  S,T 

Frequency 

180 

300 

Rf  =  1MQ, 
450                       Vqq  =  -9V  ±  IV 

c0 

Input/Output 
Capacitance 

100 

330  KHz 

20         pF       Port  4 

Clock  Rise  and 

Fall  Times              p  f 

2  ms 

CLK, 

Clock 

Capacitance 

30         pF  CLK 

Clock  Pulse 

Width  High  f*WH 

1.5 

External  Clock 

3 

Clock  Pulse 

Width  Low  *WL 

1.5 

3  ms 

3-99 


MPD7520 

Clock  Waveform 


vss 

V0H 


Development  Tools 

The  NEC  Electronics  U.S.A.'s  NDS  Development 
System  is  available  for  the  development  of  software 
source  code,  editing,  and  assembly  into  object  code.  In 
addition,  thq  ASM75  Cross  Assembler  is  available  for 
systems  supporting  the  ISIS-II  or  the  CP/M  (®  Digital 
Research  Corp.)  Operating  Systems. 
The  EVAKIT-7520  Evaluation  Board  is  available  for 
production  device  evaluation  and  prototype  system 
debugging. 

The  ASM75-F9T  Cross  Assembler  is  available  for 
systems  supporting  fortran  IV  ANSI  Standard 
1966-V3.9. 


Instruction  Set  Symbol  Definitions 

The  following  abbreviations  are  used  in  the  description  of 
the  mPD7520  instruction  set: 


SYMBOL 


data 


HL 


P(  ) 

~PC~n 


String 


(  ) 


[  ] 


EXPLANATION  AND  USE 


Accumulator 


address     Immediate  address 


Carry  Flag 


Immediate  data 


Bit  "n"  of  immediate  data  or  immediate  address 


Register  H 


Register  pair  HL 


Register  L 


Parallel  Input/Output  Port  addressed  by  the  value 
within  the  brackets 

Bit  "n"  of  Program  Counter 


Zero  when  Skip  Condition  does  not  occur;  the  number 
of  bytes  in  next  instruction  when  Skip  Condition 
occurs 


Stack       Stack  Register 


String  Effect  Skip  Condition,  whereby  succeeding 
instructions  of  the  same  type  are  executed  as  NOP 
instructions 


The  contents  of  RAM  addressed  by  the  value  within 
the  brackets 


The  contents  of  ROM  addressed  by  the  value  within 
the  brackets 


Load,  Store,  or  Transfer 


Exchange 


Complement 


LOGICAL  Exclusive-OR 


Instruction  Set 


INSTRUCTION  CODE  SKIP 


MNEMONIC 

FUNCTION 

DESCRIPTION 

D? 

De 

05 

D4 

D3 

D2 

D1 

D0 

BYTES    CYCLES  CONDITION 

LOAD 

LAI  data 

A  *~  P3-O 

Load  A  with  4  bits  of  imme- 
diate data,  execute  succeeding 
LAI  instructions  as  NOP 
Instructions 

0 

0 

0 

1 

D3 

D2 

01 

DO 

1             1  String 

LHI  data 

H-Dvo 

Load  H  with  2  bits  of  imme- 
diate data 

0 

0 

1 

0 

1 

0 

°1 

DO 

1  1 

LHLI  data 

HL^D4.0 

Load  HL  with  5  bits  of 
immediate  data,  execute 
succeeding  LHLI  instructions 
as  NOP  instructions 

1 

1 

0 

D4 

D3 

D2 

D1 

DO 

1              1  String 

LAMT 

A  «-  [PC9.6,  0,  C,  A]  H 

(HUMPC9.6, 
0,  C,  A]  L 

Load  the  upper  4  bits  of  ROM 
Table  Data  at  address 
PC9.6,  0,  C,  A  to  A 
Load  the  lower  4  bits  of  ROM 
Table  Data  at  address 
PC9-6,  0,  C,  A  to  the  RAM 
location  addressed  by  HL 

0 

1 

0 

1 

1 

1 

1 

0 

1  2 

L 

A  «-  (HL) 

Load  A  with  the  contents  of 
RAM  addressed  by  HL 

0 

1 

0 

1 

0 

0 

1 

0 

1  1 

LIS 

A-(HL) 
L  =  L  +  1 
Skip  if  L  =  OH 

Load  A  with  the  contents  of 
RAM  addressed  by  HL,  incre- 
ment L,  skip  if  L  =  OH 

0 

1 

0 

1 

0 

0 

0 

1 

1           1  +  S       L  =  OH 

LDS 

A  «-  (HL) 
L=  L-1 
Skip  if  L=  FH 

Load  A  with  Ihe  contents  of 
RAM  addressed  by  HL, 
decrement  L,  skip  if  L  =  FH 

0 

1 

0 

1 

0 

0 

0 

0 

1           1 +S       L=  FH 

LADR  address 

A  -  (D5.0) 

Load  A  with  the  contents  of 
RAM  addressed  by  6  bits  of 
immediate  data 

0 
0 

0 
0 

1 

D5 

1 

D4 

1 

D3 

0 

D2 

0 

D1 

0 

D0 

2  2 

3-100 


MPD7520 


Instruction  Set  (Cont.) 


INSTRUCTION  COOE 

SKIP 

MNEMONIC 

FUNCTION 

DESCRIPTION 

Oj 

D6  D5 

D4 

D3 

D2 

Dl 

DO 

BYTES 

CYCLES 

CONDITION 

STORE 

ST 

(HL)  <-A 

Store  A  into  the  RAM  location 
addressed  by  H  L 

0 

1  0 

1 

0 

1 

1 

1 

1 

1 

ST  II  data 

(HL)  «-  D3.0 
L  *-  L  +  1 

Store  4  bits  of  immediate  data 
into  the  RAM  location 
addressed  by  HL;  increment  L 

0 

1  0 

0 

03 

D2 

Dl 

DO 

1 

1 

EXCHANGE 

XAH 

A3.2  «-  OOH 

Exchange  A  with  H 

0 

1  1 

1 

1 

0 

1 

0 

1 

1 

XAL 

A  «■  L 

Exchange  A  with  L 

0 

1  1 

1 

1 

0 

1 

1 

1 

1 

X 

A  -  (HL) 

Exchange  A  with  the  contents 
of  RAM  addressed  by  HL 

0 

1  0 

1 

0 

1 

1 

0 

1 

1 

XIS 

A-  (HL) 
L+-L  +  1 
Skip  if  L  =  OH 

Exchange  A  with  the  contents 
of  RAM  addressed  by  HL; 
increment  L,  skip  if  L  =  OH 

0 

1  0 

1 

0 

1 

0 

1 

1 

1  +S 

L  =  0H 

XDS 

A  -  (HL) 
L<-  L-  1 
Skip  if  L  =  FH 

Exchange  A  with  the  contents 
of  RAM  addressed  by  HL; 
decrement  L;  skip  if  L  =  FH 

0 

1  0 

1 

0 

1 

0 

0 

1 

1  +s 

L=  FH 

XADR  address 

A  -  (D5.0) 

Exchange  A  with  the  contents 
of  RAM  addressed  by  6  bits  of 
immediate  data 

0 
0 

0  1 
0  O5 

1 

D4 

1 

D3 

0 

D2 

0 
Dl 

1 

DO 

2 

2 

ARITHMETIC  AND  LOGICAL 

A  ISC  data 

A  *-  A  +  D3.0 
Skip  if  overflow 

Add  4  bits  of  immediate  data 
to  A,  Skip  if  overflow  is 
generated 

0 

0  0 

0 

D3 

D2 

D1 

Do 

1 

1  +S 

Overflow 

ASC 

A+- A  +  (HL) 
Skip  if  overflow 

Add  the  contents  of  RAM 
addressed  by  HL  to  A;  skip  if 
overflow  is  generated 

0 

1  1 

1 

1 

1 

0 

1 

1 

1  +S 

Overflow 

ACSC 

A,  C  <-  A  +  (HL)  +  C 
Skip  if  C  =  1 

Add  the  contents  of  RAM 
addressed  by  H  L  and  the  carry 
flag  to  A,  skip  if  carry  is 
generated 

0 

1  1 

1 

1 

1 

0 

0 

1 

1  +S 

C  =  1 

EXL 

A  <-  A  V  (HL) 

Perform  a  LOGICAL 
Exclusive— OR  operation 
between  the  contents  of 
RAM  addressed  by  HL  and 
A ,  store  the  result  in  A 

0 

1  1 

1 

1 

1 

1 

0 

1 

1 

ACCUMULATOR  AND  CARRY  FLAG 

CMA 

A  <- A 

Complement  A 

0 

1  1 

1 

1 

1 

1 

1 

1 

1 

RC 

C-0 

Reset  Carry  Flag 

0 

1  1 

1 

1 

0 

0 

0 

1 

1 

SC 

C<-l 

Set  Carry  Flag 

0 

1  1 

1 

1 

0 

0 

1 

1 

1 

INCREMENT  AND  DECREMENT 

ILS 

L+-L  +  1 
Skip  if  L  =  OH 

Increment  L, 
Skip  if  L  =  OH 

0 

1  0 

1 

1 

0 

0 

1 

1 

1  +s 

L  =  0H 

IDRS  address 

<D5_o)  «-  (D5.0)  +  1 
Skip  if  (D5_o)  =  OH 

Increment  the  contents  of 
RAM  addressed  by  6  bits  of 
immediate  data;  Skip  if  the 
contents  =  OH 

0 
0 

0  1 
0  D5 

1 

D4 

1 

D3 

1 

02 

0 
Dl 

1 

Do 

2 

2  +  S 

(D5_o)  =  OH 

DLS 

L  «-  L  -  1 
Skip  if  L  =  FH 

Decrement  L; 
Skip  if  L=  FH 

0 

1  0 

1 

1 

0 

0 

0 

1 

1  +S 

L=  FH 

DDRS  address 

(D5.0)  -  (D5.0)  -  1 
Skip  if  (D^)  =  FH 

Decrement  the  contents  of 
RAM  addressed  by  6  bits  of 
immediate  data,  skip  if  the 
contents  =  FH 

0 
0 

0  1 
0  D5 

1 

D4 

1 

D3 

1 

D2 

0 
Dl 

0 

DO 

2 

2  +  S 

(D5-0)  =  FH 

BIT  MANIPULATION 

RMB  data 

(HL)bit+-0 

Reset  a  single  bit  (denoted  by 
Df  Do)  of  the  RAM  location 
addressed  by  HL  to  zero 

0 

1  1 

0 

1 

0 

Dl 

DO 

1 

1 

SMB  data 

(HL)blt^1 

Set  a  single  bit  (denoted  by 
DjDo)  of  the  RAM  location 
addressed  by  H  L  to  one 

0 

1  1 

0 

1 

1 

Dl 

Do 

1 

1 

JUMP.  CALL,  AND  RETURN 

JMP  address 

PC9-0  *-  Dg_o 

Jump  to  the  address  specified 
by  10  bits  of  immediate  data 

0 

D7 

0  1 
Dfi  D5 

0 

D4 

0 

D3 

0 

D2 

D9 
Di 

D8 
Do 

2 

2 

JAM  data 

PCg^  «-  Dvo 

PC7.4-A 

PC3.0^-(HL) 

Jump  to  the  address  specified 
by  2  bits  of  immediate  data.  A, 
and  the  RAM  contents 
addressed  by  HL 

0 
0 

0  1 
0  0 

1 
1 

1 
0 

1 
0 

1 

Dl 

1 

Do 

2 

2 

3-101 


/iPD7520 

Instruction  Set  (Cont.) 


INSTRUCTION  CODE  SKIP 


MNEMONIC 

FUNCTION 

DESCRIPTION 

O7  De 

°5 

D4 

D3 

D2 

Dl 

Do 

BYTES 

CYCLES 

CONDITION 

JUMP,  CALL.  AND  RETURN 

JCP  address 

PC5-0  *-  D5-O 

Jump  to  the  address  specified 
by  the  higher-order  bits  PCg_£ 
of  the  PC,  and  6  bits  of 
immediate  data 

1  0 

°5 

D4 

03 

O2 

Dl 

Do 

1 

1 

CALL  address 

STACK     PC  +  2 
PC9.0  *-  D9.0 

Store  a  return  address  (PC  +  2) 
in  the  stack;  call  the  subroutine 
program  at  the  location  speci- 
fied by  10  bits  of  immediate 
data 

0  0 
D7  D6 

1 

D5 

1 

0 

D3 

0 

D2 

D9 
D1 

D8 
DO 

2 

2 

CAL  address 

STACK  <-  PC  +  1 
PC9.0-OID4D3 

OOOD2D1D0 

Store  a  return  address  (PC  +  1 ) 
in  the  stack;  call  the  subroutine 
program  at  one  of  the  32  spe- 
cial locations  specified  by  5 
bits  of  immediate  data 

1  1 

1 

D4 

D3 

D2 

D1 

DO 

1 

1 

RT 
RTS 

PC  +-  STACK 

PC -STACK 

Skip  unconditionally 

Return  from  Subroutine 

Return  from  Subroutine;  skip 
unconditionally 

0  1 
0  1 

0 
0 

1 
1 

0 

1 

0 
0 

1 
1 

1 
1 

1 
1 

1 

1  +S 

Unconditional 

SKIP 

SKC 

Skip  if  C  =  1 

Skip  if  carry  flag  is  true 

0  1 

0 

1 

1 

0 

1 

0 

1 

1  +S 

C=  1 

SKMBT  data 

Skip  if  (HL)blt=  1 

Skip  if  the  single  bit  (denoted 
by  D-jDo)  of  the  RAM  loca- 
tion addressed  by  H  L  is  true 

0  1 

1 

0 

0 

1 

Dl 

DO 

1 

1  +S 

(HL)blt=  1 

SKMBF  data 

Skip  if  (HL)bit  =  0 

Skip  if  the  single  bit  (denoted 
by  D1  Do)  of  the  RAM  loca- 
tion addressed  by  H  L  is  false 

0  1 

1 

0 

0 

0 

01 

DO 

1 

1  +S 

(HL)bit  =  0 

SKABT  data 

Skip  if  Ablt  =  1 

Skip  if  the  single  bit  (denoted 
by  D-|Do)  of  A  is  true 

0  1 

1 

1 

0 

1 

D1 

DO 

1 

1  +  S 

Abit  =  1 

SKAEI  data 

Skip  if  A  =  data 

Skip  if  A  equals  4  bits  of 
immediata  data 

0  0 
0  1 

1 
1 

1 

0 

1 

D3 

1 

D2 

1 

D1 

1 

DO 

2 

2  +  S 

A  =  data 

SKAEM 

Skip  if  A=  (HL) 

Skip  if  A  equals  the  RAM  con- 
tents addressed  by  HL 

0  1 

0 

1 

1 

1 

1 

1 

1 

1  +S 

A=  (HL) 

PARALLEL  I/O 

IPL 

A-P(L) 

Input  the  Port  addressed 
by  L  to  A 

0  1 

1 

1 

0 

0 

0 

0 

1 

1 

IP1 

A*-P1 

Input  Port  1  to  A 

0  1 

1 

1 

0 

0 

0 

1 

1 

1 

OPL 

P(L)+-A 

Output  A  to  the  port 
addressed  by  L 

0  1 

1 

1 

0 

0 

1 

0 

1 

1 

OP3 

Output  the  lower  2  bits  of  A 
to  Port  3 

0  1 

1 

1 

0 

0 

1 

1 

1 

1 

CPU  CONTROL 

NOP 

Perform  no  operation;  con- 
sume one  machine  cycle 

0  0 

0 

0 

0 

0 

0 

0 

1 

1 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  nPD7520C 

Plastic  Shrinkdip,  ^PD7520CT 


3-102 


7520DS-REV1  -7-83-TRIUM-CAT 


VFC  |xPD7527/7528/7537/7538 
^  ^  w  CMOS  4-BIT  SINGLE-CHIP 

MICROCOMPUTER  WITH  VACUUM 
FLUORESCENT  DISPLAY 
DRIVE  CAPABILITY 


Description 

The  pPD7527/28  and  the  |xPD7537/38  are  pin-compatible 
CMOS  4-bit  single-chip  microcomputers  which  have  the 
same  (jlPD750X  architecture. 

The  pPD7527/37  contains  a  2048  x  8-bit  ROM,  and  a  128  x 
4-bit  RAM.  The  |xPD7528/38  contains  a  4096  x  8-bit  ROM, 
and  a  160  x  4-bit  RAM. 

Both  the  |jlPD7527/28  and  the  ^PD7537/38  contain  two 
4-bit  general  purpose  registers  located  outside  RAM.  The 
subroutine  stack  is  Implemented  in  RAM  for  greater  depth 
and  flexibility.  The  ^PD7527/28  and  ^PD7537/38  typically 
execute  67  instructions  of  the  |xPD7500  series  A  instruction 
set  with  a  5|xs  instruction  cycle  time. 
The  |xPD7527/28  and  the  |jlPD7537/38  have  one 
external  and  two  internal  edge-triggered  hardware  vec- 
tored interrupts.  They  also  contain  an  8-bit  timer/event 
counter  and  an  8-bit  serial  interface  to  help  reduce  soft- 
ware requirements. 

Both  the  |jlPD7527/28  and  the  |xPD7537/38  provide  31  I/O 
lines  organized  into  the  4-bit  input/serial  interface  Port  0, 
the  3-bit  Port  2,  the  4-bit  Port  3,  and  the  4-bit  I/O  Ports  1, 4, 
5,  8,  9, 10  and  11 .  They  are  manufactured  with  a  low  power 
consumption  CMOS  process,  allowing  the  use  of  a  power 
supply  between  2.7V  and  5.5V.  Current  consumption  is 
less  than  900jxA  maximum,  and  can  be  lowered  much 
further  in  the  Halt  and  Stop  power-down  modes.  The 
|xPD7527/28  and  |xPD7537/38  are  available  in  a  42-pin 
dual-in-line  plastic  package. 

The  |xPD7527/28  and  pPD7537/38  are  upward  compatible 
with  other  members  of  the  |jlPD75xx  product  family. 
For  prototyping  work,  and  as  an  aid  to  program  development, 
there  are  piggyback  EPROM  versions  for  both  devices:  the 
75CG28E  and  75CG38E.  These  are  pin-compatible  and 
functionally  compatible  with  the  final,  masked  versions  of 
the  devices. 


Pin  Configuration 


RESET 
CL, 
CL2 
Vrre 

V|_OAD 

P53 
P52 
P5i 
P50 
P23 
P22 
P2i/Ptout 
P103 
P102 

P10! 

P10o 
PH3 
P112 
P11i 
P110 


jjlPD 
7527/ 
7528/ 
7537/ 
7538/ 


42  2  Vss 
41  3  P0o/INT0 
40  3  PO^SCK 
39  D  P02/SO 
38  3  PO3/SI 
37  3  P30 
36  3  P3t 
35  D  P32 
34  3  P33 
33  3  P40 
32  3  P*i 
31  3  P42 
30  3  P43 
29  3  P80 
28  3  P8i 
27  3  P82 
26  3  P83 
25  DPOo 
24  3  P9i 
23  3  P92 
22  3  P93 


Pin  Identification 


Pin 

No. 

Symbol 

Function 

1 

RESET 

Reset  input  (active  high).  R/C  circuit  or  pulse  initializes 
the  microcomputer  after  power  up. 

2,3 

CLl  CL2 

System  clock  oscillator.  CL1  is  the  input  and  CL2 
the  output. 

4 

Vpre 

Power  supply  input  for  the  high  voltage  output 
predrivers. 

5 

VLOAD 

Power  supply  common  input  for  output  load  resistors. 

6,  7,  8,  9 

P50-P53 

Input/output  Port  5 

10,11,12 

P2-,/Ptout 
P22-P23 

Port  2,  bit  3  output,  and  timer  output. 
Output  Port  2,  bits  2  and  3. 

13,14,15,16 

P10„-P103 

Input/output  Port  10. 

17,18,19,  20 

PH0-PH3 

Input/output  Port  11. 

21 

VDD 

Positive  power  supply. 

22, 23,  24, 25 

P90-P93 

Output  Port  9. 

26,27,28,29 

P80-P83 

Output  Port  8. 

30,31,32,33 

P40-P43 

Output  Port  4. 

34,  35,  36,  37 

P30-P33 

Output  Port  3. 

38, 39,  40, 41 

POo/INTq 
PO^SCK 
P02/SO 
P03/SI 

4-bit  input  Port  0/serial  I/O  interface.  This  port  can  be 
configured  either  as  a  4-bit  parallel  input  port,  or  as  the 
8-bit  serial  I/O  interface,  under  control  of  the  serial  mode 
register.  The  serial  input  SI,  serial  output  SO,  and  the 
serial  clock  SCK  (NOT)  used  for  synchronizing  data 
transfer  comprise  the  8-bit  serial  I/O  interface. 

42 

Vss 

Ground. 

3-103 


fxPD7527/7528/7537/7538 


Block  Diagram 


P0o/INT0 


Program  Counter 


Program  Memory 


P0,/SCK  POa/SI 
POa/SO 


Zero- 
Cross 
Detector 

P00 

Clock 
Control 

CP 

Timer/Event 

Interrupt 

Serial 
Interface 

r 

Counter 

Control 

ft"1-*-  o 


PRE  'tOAl 

I  I 


c 


7\ 


3 


Instruction 
Decoder 


System 

Clock 

Generator 

Standby 
Control 

1 

CL,  CL2 


I    1  I 


n 


Data  Memory 


PortO 
Buffer 


CD' 


IPOo-PO, 


c 

A  (4) 

General  Registers 

H(4) 

L(4) 

Stack  Pointer  (8) 

Buffer    -^-^  PTOUT/P2i 


O  CO"4"-"4' 


I  rv     Port  3   k 


-P3, 


P9.-P9> 


O  £  CO1-™ 


Distinguishing  Features 


|xPD7527 

M*D7528 

(1P07537 

fxPD7538 

Type  of  Oscillator  (CL„  CL2) 

R/C 

R/C 

Crystal 

Crystal 

Program  Counter 

11  bits 

12  bits 

11  bits 

12  bits 

Program  Memory 

2048  x  8 

4096  x8 

2048  x8 

4096  x  8 

Data  Memory 

128x4 

160x4 

128x4 

160x4 

Number  of  Instructions 

67 

67 

66 

66 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  H-PD7527C/28C/37C/38C 

Plastic  Shrinkdip,  ^PD7527C  28C  37C  38C 

Ceramic  Piggyback,  |xPD75CG28E/CG38E 


Mask  Options 

P0o/INTo  This  input,  as  a  mask  option, 

can  be  altered  from  a  standard 
digital  CMOS  input  to  a  zero- 
crossing  detector. 
These  I/O  ports  can 
selectively  be  provided  with 
90-93, 1 00- iu3, 1 1  o — 1 1 3  optional  pull-down  load 
resistors  at  the  bit  level. 


Ports  21-23,  30-33, 
4o—43,  50— 53,  80— 83, 


7527/28/37/38  DS-7-83-CAT-L 


3-104 


MFC  MPD7500 
^  ^  w  CMOS  4-BIT  MICROPROCESSOR 


MPD7500  SERIES  ROM-LESS 
EVALUATION  CHIP 


Description 

The  jL*PD7500  is  a  CMOS  4-bit  microprocessor  which 
has  the  jiPD750x  architecture,  and  also  functions  as  the 
jiPD7500  series  ROM-less  evaluation  chip. 
The  fiPD7500  contains  a  256  x  4-bit  RAM,  and  is 
capable  of  addressing  up  to  8192  x  8-bits  of  external 
program  memory. 

The  jiPD7500  contains  four  4-bit  general  purpose 
registers  located  outside  RAM.  The  subroutine  stack  is 
implemented  in  RAM  for  greater  nesting  depth  and  flex- 
ibility, providing  such  operations  as  the  pushing  and 
popping  of  register  values.  The  jiPD7500  typically  exe- 
cutes either  all  110  instructions  of  the  ^PD7500  series 
"A"  instruction  set,  or  all  70  instructions  of  the 
fiPD7500  series  "B"  instruction  set  with  a  10j*s  instruc- 
tion cycle  time. 

The  juPD7500  has  three  external  and  two  internal  edge- 
triggered  hardware  vectored  interrupts.  It  also  contains 
an  8-bit  timer/event  counter  and  an  8-bit  serial  interface 
to  help  reduce  software  requirements.  A  display  timing 
pulse  is  also  provided  when  emulating  the  /iPD7501, 
MPD7502,  the  jiPD7503,  or  the  mPD7519. 

The  /iPD7500  provides  32  I/O  lines  organized  into  the 
4-bit  input/serial  interface  Port  0,  the  4-bit  output  Port  2, 
the  4-bit  output  Port  3,  and  the  4-bit  I/O  Ports  1 ,  4,  5,  6, 
and  7.  It  is  manufactured  with  a  low  power  consumption 
CMOS  process,  allowing  the  use  of  a  single  +  5V  power 
supply.  Current  consumption  is  less  than  900^A  max- 
imum, and  can  be  lowered  much  further  in  the  HALT 
and  STOP  power-down  modes.  The  fiPD7500  is  avail- 
able in  a  64-pin  quad-in-line  plastic  package. 
Pin  Configuration 


Pin  Names 


X1 

CZ 

1 

X2 

2 

TEST 

CZ 

3 

BUS8 

4 

BUSg 

5 

BUS10 

6 

BUSn 

7 

BUS12 

8 

BUS  13 

CZ 

9 

P4o 

10 

P41 

CZ 

11 

P42 

12 

P43 

CZ 

13 

P50 

14 

P51 

CZ 

15 

P52 

16 

P53 

CZ 

17 

P60 

18 

P61 

CZ 

19 

P62 

(_ 

20 

P63 

CZ 

21 

P70 

22 

P71 

CZ 

23 

P72 

24 

P73 

CZ 

25 

INT1 

26 

INTO 

cz 

27 

INT2 

28 

RESET 

CZ 

29 

CL2 

30 

CL1 

CZ 

31 

VDD 

32 

7500 


64 

vss 

63 

BUS? 

62 

ZD 

BUS6 

61 

BUS5 

60 

BUS4 

59 

BUS3 

58 

BUS2 

57 

BUS1 

56 

ZD 

BUSo 

55 

P13 

54 

P12 

53 

P11 

52 

ZD 

P10 

51 

STB 

50 

ZD 

CSOUT 

49 

 1 

LCD  CL 

48 

PSEN 

47 

P20/PSTB 

46 

P21/PTOUT 

45 

P22 

44 

P23 

43 

P03/SI 

42 

P02/SO 

41 

P01/SCK 

40 

ZD 

P00 

39 

NC 

38 

ZD 

ALE 

37 

DOUT 

36 

ZD 

P33 

35 

P32 

34 

ZD 

P31 

33 

P3o 

No. 

Pin 

Symbol 

Function 

1.  2 

*2>  ^1 

Crystal  clock/external  event  input  Port  X  (active  high).  A 
crystal  oscillator  circuit  is  connected  to  input  X-j  and  output 
X2  for  crystal  clock  operation.  Alternatively,  external  event 
pulses  are  connected  to  input  X-j  while  output  X2  is  left  open 
for  external  event  counting. 

3 

TEST 

Factory  test  pin  (connect  to  Vss). 

4-9,  and 
56-63 

BUS0-BUS13 

External  data  bus  (active  high).  Connected  to  external  pro- 
gram memory. 

10-13 

P40-P43 

4-bit  input/latched  tri-state  output  Port  4  (active  high).  Can 
also  perform  8-bit  parallel  I/O  in  conjunction  with  Port  5. 

14-17 

P50-P53 

4-bit  input/latched  tri-state  output  Port  5  (active  high).  Can 
also  perform  8-bit  parallel  I/O  in  conjunction  with  Port  4. 

18-21 

P60-P63 

4-bit  input/latched  tri-state  output  Port  6  (active  high).  Indi- 
vidual lines  can  be  configured  either  as  inputs  or  as  outputs 
under  control  of  the  Port  6  mode  select  register. 

P7q-P73 

4-bit  input/latched  tri-state  output  Port  7  (active  high). 

27~ — 

,NTl 

External  Interrupt  INT^  (active  high).  This  is  a  rising  edge- 
triggered  interrupt. 

27 

•NT0 

External  Interrupt  INT0  (active  high).  This  is  a  rising  edge- 
triggered  interrupt. 

28 

INT2 

External  Interrupt  INT2  (active  high).  This  is  a  rising  edge- 
triggered  interrupt. 

29 

RESET 

RESET  input  (active  high).  R/C  circuit  or  pulse  initializes 
MPD7500  after  power-up. 

30,  31 

CL-,,  cl2 

System  clock  input  (active  high).  Connect  82KQ  resistor 
across  CL-j  and  CL2,  and  connect  33pF  capacitor  from  CL1  to 
V$s-  Alternatively,  an  external  clock  source  may  be  con- 
nected to  CL-| ,  whereas  CL2  is  left  open. 

32 

VDD 

Power  supply  positive.  Apply  single  voltage  ranging  from 
2.7V  to  5.5V  for  proper  operation. 

33-36 

P30-P33 

4-bit  input/latched  tri-state  output  Port  3  (active  high). 

37 

doOt 

Data  output  (active  low). 

38 

ALE 

Address  latch  enable  (active  high). 

39 

NC 

No  connection. 

40-43 

P00 

PO-j/SCK 

P02/SO 

PO3/SI 

4-bit  input  Port  0/serial  I/O  interface  (active  high).  This  port 
can  be  configured  either  as  a  4-bit  parallel  input  port,  or  as 
the  8-bit  serial  I/O  interface,  under  control  of  the  serial  mode 
select  register.  The  Serial  Input  SI  (active  high),  Serial  Output 
SO  (active  low),  and  the  Serial  Clock  SCK  (active  low)  used 
for  synchronizing  data  transfer  comprise  the  8-bit  serial  I/O 
interface. 

44-47 

P20-P23 

P20/PSTB 

P21/PT0UT 

4-bit  latched  tri-state  output  Port  2  (active  high).  Line  P20  is 
also  shared  with  PstB>  the  Port  1  output  strobe  pulse  (active 
low).  Line  P21  is  also  shared  with  Pinni-' the  *«"ier-out  F/F 
signal  (active  high).  UUI 

48 

PSEN 

Program  store  enable  (active  low). 

49 

DISPLAY 

DISPLAY  timing  pulse  (active  high). 

50 

CSOUT 

Chip  select  output  (active  low).  Connected  to  mPD82C43. 

51 

STB 

STROBE  output  (active  low).  Connected  to  mPD82C43. 

52-55 

P10-P13 

4-bit  input/tri-state  output  Port  1  (active  high).  Data  output  to 
Port  1  is  strobed  in  synchronization  with  a  P2fj/PsTB  Pulse. 

64 

vSs 

Ground. 

Rev/1 
3-105 


MPD7500 

Block  Diagram 


POi/SCK  p03/s, 
PO2/SO 


Display 


J_L  t 


Count 
Clock 
Generator 


Clock 
Control 
Circuit 


H 


Bank  | 
I 

12-BIT 

Program  Counter 

/P2o/PSTB,\ 
P/PT0UT/ 


ALE 
PSEN 
DOUT 


BUS0  -  /  (14)  \ 
BUS13\l  / 


Address  Bus 
Interface 


Register  I  Break 
Dump         1  Controller 


J  L 


System 
Clock 
Generator 


PO0-PO3 


RESET  VDD 


3-106 


MPD7500 


Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Power  Supply  Voltage,  Vpp 

-0.3V  to  +7.0V 

All  Input  and  Output  Voltages 

-0.3VtoVDD  +0.3V 

Output-Current  (Total,  All  Output  Ports) 

Iqh  =  -20mA 

Iql  =  50mA 

AC  Characteristics 

Ta  =  -10°  ~  +70°C,  vDd  =  5V  ±  10% 
Clock  Operation 


*  Comment:  Stress  above  those  listed  under  "Absolute 
Maximum  Ratings"  may  cause  permanent  damage  to 
the  device.  This  is  a  stress  rating  only  and  functional 
operation  of  the  device  at  these  or  any  other  conditions 
above  those  indicated  in  the  operational  sections  of  this 
specification  is  not  implied.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


DC  Characteristics 

Ta  =  -10°Cto  +70°C,  VDD  =  5V  ±  10% 


Limits 

Paramet< 

ir  Symbo 

1  Mbi 

Typ  Max 

Unit 

Test  Conditions 

Input 

Voltage 

High 

V|H1 

0.7  VDD 

vDd 

V 

All  Inputs  Other  than 
CL^Xt 

V|H2 

VDD  -0.5 

vDd 

CLi.Xi 

Input 
Voltage 

V,L1 

0 

0.3  vDD 

V 

All  Inputs  Other  than 
CL^X, 

Low 

V,L2 

0 

0.5 

CL^X! 

Input 
Leakage 
Current 
High 

'"hi 

3 

ma 

All  Inputs  Other  V,  =  VDD 
than  CL-,,  X1 

'L'H2 

10 

CL^X! 

Input 
Leakage 
Current 
Low 

'lil1 

-3 

mA 

All  Inputs  Other  V,  =  0V 
than  CL1(  X-| 

'liL2 

-10 

CL^X! 

Output 
Voltage 
High 

V0H 

VDD  -  1.0 

V 

Output 
Voltage 
Low 

vol 

0.4 

V 

Output 
Leakage 
Current 
High 

•loh 

3 

MA 

V0  =  Vqd 

Output 
Leakage 
Current 
Low 

'lol 

-3 

V0  =  ov 

Supply 
Current 

lDD1 

2 

mA 

Normal  Operation 
All  Output  Pins  Open 
No  BUS  Conflicts 

'dd2 

2  20 

mA 

Stop  Mode,  X-,  =  0V 

'dddr 

0.4  10 

Data  Retention  Mode 
VDDDR  =  20V 

Capacitance 

Ta  =  25»c,  vDD 


ov 


Parameter 

Symbol  ft 

Limits 
lln      Typ  Max 

Unit 

Test  Conditions 

Input  Capacitance 

CIN 

15 

pF 

f  =  1MHZ 

Output  Capacitance 

COUT 

15 

PF 

Unmeasured  pins 

I/O  Capacitance 

C|0 

15 

pF 

returned  to  Vgg 

Parameter 

Symbo 

Mln 

Typ 

Max 

Unit 

Test  Conditions 

System  Clock 
Oscillation  Frequency 

H 

120 

200 

280 

KHz 

R  =  82kQ  ±  2% 
C  =  33pF  ±  5% 

V 

10 

300 

KHz 

CL1t  External  Clock 

CL-)  Input  Rise  Time 

0.2 

|4S 

CL1  Input  Fail  Time 

tCF 

0.2 

MS 

CL1  Input  Clock  Width 
(High) 

lCH 

1.5 

MS 

CL1  Input  Clock  Width 
(Low) 

*CL 

1.5 

MS 

Count  Clock 
Oscillation  Frequency 
(XlXz) 

fxx 

32 

KHz 

Xtal  Oscillation 

Count  Clock 

Input  Frequency  (X-)) 

'x 

0 

300 

KHz 

X-)  Input  Rise  Time 

tXR 

0.2 

MS 

X-,  Input  Fall  Time 

tXF 

0.2 

MS 

X-|  Input  Clock  Width 
(High) 

lXH 

1.5 

MS 

X1  Input  Clock  Width 
(Low) 

»XL 

1.5 

MS 

Bus  I/O  Operation 

Limits 

Parameter 

Symbol 

Mln 

Typ 

Max 

Unit 

Test  Conditions 

ALE  Pulse  Width 
(High) 

*LH 

600 

ns 

Address  Setup  Time 
to  ALE4 

tAL 

200 

ns 

Address  Hold  Time 
after  ALE! 

»LA 

100 

ns 

Output  Data  Setup 
Time  to  DOUTt 

tDDO 

200 

ns 

Output  Data  Hold 
Time  after  DOUTt 

tDOD 

100 

ns 

DOUT  Pulse  Width 
(Low) 

*DOL 

600 

ns 

ALE  -  Data  Input 
Valid  Time 

lLDV 

700 

ns 

Address  -*  Data  Input 
Valid  Time 

lADV 

900 

ns 

PSEN  Pulse  Width 
(Low) 

lPSL 

1200 

ns 

PSEN  -  Data  Input 
Valid  Time 

tpSDV 

600 

ns 

PSEN  -  Data  Float 

*PSDF 

0 

ns 

3-107 


MPD7500 

Port  1  I/O  Operation 


Other  Operations 


Parameter 

Symbol 

M/n      Typ  Max 

Unit 

Test  Conditions 

Parameter 

Symbol 

M/n 

Typ     Max     Unit      Test  Conditions 

Port  1  Output  Setup 
Time  to  STBt 

*PST 

200 

ns 

INTq  Pulse  Width 
High 

!loH 

10 

fiS 

Port  1  Output  Hold 
Time  after  STBt 

*STP 

100 

ns 

Port  Output  Mode 

INT0  Pulse  Width 
Low 

%*- 

10 

MS 

STBPulse  Width 
(Low) 

^STL-j 

600 

ns 

INT1  Pulse  Width 
High 

*'1H 

a/i+ 

MS 

Output  Data  Setup 
Time  to  STBt 

*DST 

300 

ns 

INT1  Pulse  Width 
Low 

2/1$ 

MS 

Output  Data  Hold 
Time  after  STBt 

*STD 

100 

ns 

INT2  Pulse  Width 
High 

!I2H 

2/ty 

MS 

STBi  —  Input  Data 
Valid  Time 

*STDV 

850 

ns 

INT2  Pulse  Width 
Low 

t|2L 

2/fy 

MS 

STBI  -  Input  Data 
Float  Time 

tSTDF 

0 

ns 

RESET  Pulse  Width 
High 

*RSH 

10 

MS 

Control  Setup  Time 
to  STB* 

*CST 

200 

ns 

I/O  Expander  Mode 

RESET  Pulse  Width 
Low 

*RSL 

10 

MS 

Control  Hold  Time 
after  STB* 

*STC 

100 

ns 

STB  Pulse  Width 
(Low) 

lSTL2 

1200 

ns 

CSOUT  Setup  Time 
to  STB* 

lCSST 

200 

ns 

CSOUTHold  Time 
after  STB* 


*STCS 


Serial  Interface  Operation 


Limit* 

Parameter 

Symbol 

M/n 

Typ  Max 

Unit 

Test  Conditions 

SCK  Cycle  Time 

*KCY 

4.0 

MS 

Input 

6.7 

MS 

Output 

SCK  Pulse  Width 
High 

*KH 

1.8 

MS 

Input 

3.0 

MS 

Output 

SCK  Pulse  Width 

*KL 

1.8 

MS 

Input 

Low 

3.0 

MS 

Output 

SI  Setup  Time 
to  SCKt 

*SIK 

300 

ns 

SI  Hold  Time  after 
SCKt 

lKSI 

450 

ns 

SO  Output  Delay  after 
SCKt 

tKSO 

850 

ns 

3 


-108 


Clock  Timing  Waveforms 


Xi  Input  - 


Bus  I/O  Timing  Waveforms 


/ 


MPD7500 


r 

 tcH  

\ 

-  tCF 

BUS0,7  _ 
BUS10-13 


BUS0_7 
BUS10_13" 


X 


V 


f 


3-109 


MPD7500 


Strobe  Output  Timing  Waveforms 


Pl0-p13- 


\  / 


Port  1  I/O  Expander  Port  Timing  Waveforms 


Expander 

Port 

Output 


Expander 

Port 

Input 


X 


Output  Data 


-  lSTL2 


Serial  Interface  Timing  Waveforms 


\ 


^         Input  Data  ^- 


X 


Output  Data 


X 


3-110 


HPD7500 


Interrupt  Input  Timing  Waveforms 


(Rising  Edge  Triggered)  - 


,  INT-j 

(Rising  Edge  Triggered)  _ 


INT-i 

(Falling  Edge  Triggered)- 


f 


f 


INT2 

(Rising  Edge  Triggered) «. 


RESET  Input  Timing 


Note: 

0  Only  R/C  system  clock  is  operating  and  consuming  power.  All  other  internal  logic  blocks  are 
not  active 


3-111 


MPD7500 


Package  Outlines 

For  information,  soo  Package  Outline  Soction  7. 

Plastic  Quil,  »PD7500G  Evaluation  Chip 


3-112 


7500DS-REV1-7-83-CAT 


SEC 


MC-430P 


HYBRID  UV  EPROM 

4-BIT  SINGLE  CHIP  MICROCOMPUTER 

DESCRIPTION     The  MC-430P  is  a  hybrid  chip  containing  a  juPD556B  ROM-less  Evaluation  chip,  a 

juPD2716  2K  x  8-bit  UV  EPROM,  a  //PC7905  3-terminal  voltage  regulator,  and  pull-up 
resistors  on  the  same  ceramic  substrate.  The  MC-430P  is  pin-compatible  with  the 
//PD546C//iPD547C,  and  can  emulate  the  high-voltage  drive  or  CMOS  /xCOM-4  micro- 
computers with  the  corresponding  I/O  line  buffers. 

The  MC-430P  contains  a  2048  x  8-bit  UV  EPROM  and  a  96  x  4-bit  RAM  which 
includes  six  working  registers  and  the  flag  register.  It  has  a  level-triggered  hardware 
interrupt,  a  three-level  stack,  and  a  programmable  6-bit  timer.  The  MC-430P  executes 
all  80  instructions  of  the  extended  //COM-4  family  instruction  set. 


PIN  CONFIGURATION 


The  MC-430P  provides  35  I/O  lines  organized  into  the  4-bit  input  ports  A  and  B,  the 
4-bit  I/O  ports  C  and  D,  the  4-bit  output  ports  E,  F,  G,  and  H,  and  the  3-bit  output 
port  I.  It  typically  executes  its  instructions  with  a  10jus  instruction  cycle  time.  The 
MC-430P  is  manufactured  with  a  standard  PMOS  process,  allowing  use  of  a  single 
-10V  power  supply,  and  is  available  in  a  42-pin  dual-in-line  ceramic  hybrid  package. 


CMC  1 
PC0C  2 
PCiC  3 
PC2C  4 
PC3C  5 
WfC  6 
RESET C  7 
PD0C  8 
PDiC  9 
PD2C  10 
pD3C  11 
PEOC  12 
PE1C  13 
PE2C  14 
PE3C  15 
PFOC  16 
PP1C17 
PF2C  18 
PF3  C  19 
TEST  C  20 
VSSC  21 


MC-430P  (PIN  COMPATIBLE 
WITH  juPD546/juPD547) 


MC- 
430P 


42  3  CLo 

41  3VQG 
40DPB3 
39DPB2 

□  PB1 

□>B0 

□  pa3 

□  pa2 

□  PAi 

□  PA0 
D  Pl2 

□  PI  1 

□  Pl0 
29  2  PH3 
28  □  PH2 
27ZJpHl 
26  3  PH0 
25  □  PG3 
24  3  pG2 
23  3PG1 
22  2  PG0 


EPROM  WRITE  PADS  (mPD2716) 


A70^fTl 
A6  o— f7~] 

A5  0-{T] 
A40_£JJ 

a3  o— -PH 
a2  o—{T] 

At  0—{T] 

aqo-  rn 

Qq  o^fFl 

o2o-ni] 

GND  O — {j2] 


QT) — ovcc 
QT}— -oa8 

[22)  — OA9 
OJJ— OVPp 

l  20  l— ■ QOE 
AlO 

I  18  \  • — O  CE/PGM 

(jT}»*oo7 

I  14  \+~O0A 
[3I3—003 


PA0-PA3 

Input  Port  A 

PB0-PB3 

Input  Port  B 

PC0-PC3 

Input/Output  Port  C 

PD0-PD3 

Input/Output  Port  D 

PE0-PE3 

Output  Port  E 

PF0-PF3 

Output  Port  F 

PG0-PG3 

Output  Port  G 

PH0-PH3 

Output  Port  H 

PI0-PI2 

Output  Port  I 

IN? 

Interrupt  Input 

CLo-CLt 

External  Clock  Signals 

RESET 

Reset 

VQG 

Power  Supply  Negative 

vSs 

Power  Supply  Positive 

TEST 

Factory  Test  Pin 
(Connect  to  Vss) 

Addresses 

Output  Enable 

Oa-07 

Data  Outputs 

CE/PGM 

Chip  Enable/Program 

3-113 


MC-430P 


BLOCK  DIAGRAM 


1  :  juPD556 

2  :  Pull-Up  Resistors 

3  :  MPC7905  (3-Terminal  5  Volt  Voltage  Regulator) 

4  :  MPD2716  (EPROM) 

5  :  mPD546C/mPD547C  Compatible  Pins  (42  Pins) 

6  :  EPROM  Write  Pads  (24  Pads) 


Operating  Temperature  -10°Cto+70°C     ABSOLUTE  MAXIMUM 

Storage  Temperature  -25°Cto+85°C  RATINGS* 

Supply  Voltage,  Vqg  -15to+0.3V 

Input  Voltages  - 15  to  +0.3V 

Output  Voltages  -15to+0.3V 

Output  Current  (Total,  all  ports)  -4  mA 

Ta  =  25°C 

"COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


3-114 


MC-430P 


MC-430P  42-PIN  OPERATING 
SPECIFICATIONS 

DC  CHARACTERISTICS    >  =  -10"  c to  +7o»c. vGG  =  -iov  *  10%. vSs - ov' 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

Input  Voltage  High 

V|H 

0 

-2  0 

V 

RESET 

Input  Voltage  Low 

V|L 

-4  3 

VGG 

V 

Ports  A  through  D,  INT, 
RESET 

Clock  Voltage  High 

V0H 

0 

-0  8 

V 

CLrj  Input,  External  Clock 

Clock  Voltage  Low 

V0L 

-6  0 

VGG 

V 

CLo  Input,  External  Clock 

Input  Leakage  Current  High 

'LIH 

+  10 

MA 

Ports  A  through  D,  HNT, 

OCCCT   \/  •  -     1  V/ 
ntgtl,  V|      — IV 

Input  Leakage  Current  Low 

>LIL 

-10 

MA 

Ports  A  through  D,  INT, 
RESET,  V|  =  -11V 

Clock  Input  Leakage  Current  High 

'L0H 

+200 

MA 

CL0  Input,  V^h  =  0V 

Clock  Input  Leakage  Current  Low 

'L0L 

-200 

ma 

CL0  Input,  V0L  =  -11V 

Output  Voltage  High 

voht 

-1  0 

V 

Ports  C  through  I, 
l0H  =  -1  0  mA 

VOH2 

-2  3 

V 

Ports  C  through  I, 
<OH  =  -3.3  mA 

Output  Leakage  Current  Low 

'LOL 

-10 

MA 

Ports  C  through  I, 
V0  =  -11V 

Supply  Current 

•gg 

-110 

-165 

mA 

AC  CHARACTERISTICS       t3  =  -io°c to  +7o°c, vqg *=  -iov ±  10% 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Oscillator  Frequency 

f 

150 

440 

KHz 

Rise  and  Fall  Times 

tr.  tf 

0 

0.3 

lis 

EXTERNAL  CLOCK 

Clock  Pulse  Width  High 

t0WH 

0.5 

5.6 

MS 

Clock  Pulse  Width  Low 

VWL 

0.5 

5.6 

MS 

CAPACITANCE      Ta  =  25°c 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

C| 

15 

PF 

f  =  1  MHz 

Output  Capacitance 

CO 

40 

PF 

Input/Output  Capacitance 

ClO 

30 

PF 

3-115 


MC-430P 


MC-430P  24-PAD 
A*PD2716  UV-EPROM 
PROGRAMMING  SPECIFICATIONS 

PROGRAM,  PROGRAM  VERIFY  AND  PROGRAM  INHIBIT  MODE  DC  CHARACTERISTICS 

Ta  =  25°C  ±  5°C,  VCC  ©    =  +5V  ±  5%,  Vpp  ©@    =  +25V  ±  1V 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST  CONDITIONS 

MIN. 

TYP 

MAX. 

Input  High  Voltage 

V(H 

+2  0 

V 

Input  Low  Voltage 

VIL 

-0  1 

+0  8 

V 

Input  Leakage  Current 

■lL 

±10 

MA 

V,N  =  5  25V/0.45V 

Vpp  Current 

!PP1 

+5 

mA 

  Program  Verify 

CE/PGM -V,.  * 

Program  Inhibit 

lpp2 

+30 

mA 

CE/PGM  =  V|HPr°9ram  M°de 

VCC  Current' 

'cc 

+  100 

mA 

PROGRAM,  PROGRAM  VERIFY  AND  PROGRAM  INHIBIT  MODE  AC  CHARACTERISTICS 

Ta  =  25°C  ±  5°C,  Vcc©=  +5V  ±  5%,  Vpp©®=  +25V  ±  1V 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Address  Setup  Time 

tAS 

2 

AiS 

OE  Setup  Time 

tOES 

2 

US 

Data  Setup  Time 

*DS 

2 

US 

Address  Hold  Time 

*AH 

2 

JUS 

OTHoldTime 

tOEH 

2 

/js 

Data  Hold  Time 

tDH 

2 

PS 

Output  Enable  to  Output  Float  Delay 

tDF 

0 

120 

ns 

CE/PGM  =  V|L 

Output  Enable  to  Output  Delay 

tOE 

120 

ns 

CE/PGM  =  V|L 

Program  Pulse  Width 

tpw 

45 

50 

55 

ms 

Program  Pulse  Rise  Time 

tPRT 

5 

ns 

Program  Pulse  Fall  Time 

tPFT 

5 

ns 

Test  Conditions 

Input  Pulse  Levels  0  8V  to  2  2V     Output  Timing  Reference  Level     0.8V  and  2V 

Input  Timing  Reference  Level.  .       1V  and  2V 

Notes         Vcc  must  be  applied  simultaneously  or  before  Vpp  and  removed  after  Vpp 

(g)  During  programming,  program  inhibit,  and  program  verify ,4a  maximum  of  +26V 
should  be  applied  to  the  Vpp  pin  Overshoot  voltages  to  be  generated  by  the  Vpp 
power  supply  should  be  limited  to  less  than  +26V 


Ta  =  25°C;f=  1  MHz  CAPACITANCE 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

C|N 

60 

PF 

V|N  =  0V 

Output  Capacitance 

COUT 

45 

PF 

VqUT  =  0V 

3-116 


MC-430P 


PROGRAM  MODE 


TIMING  WAVEFORM 


AO-10 


X 


OQ-7 


X 


f 


PROGRAM  VERIFY 


VALID  INPUT 
ADDRESS  ^ 


lDS 


 v. 

-*-t0ES-*V  ^-*-t0EH— 


>UT      ^             iL     VALID       V  / 
>  <      OUTPUT       >  ( 

IL,  y-       ^  AppFiEss  n  y-  \ 


ADDRESS  N+m 


'  VALID  INPUT 
l  ADDRESS  N  +  m 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Cerdip,  MC-430PD 


3-117 


MC-430Pds-1 2-81  -CAT 


NOTES 


3-118 


NEC 


SINGLE  CHIP  8-BIT  MICROCOMPUTERS 


SEC 


jiPD7800 


HIGH  END  SINGLE  CHIP  8-BIT  MICROCOMPUTER 
ROM-LESS  DEVELOPMENT  DEVICE 


DESCRIPTION    The  NEC  /uPD7800  is  an  advanced  8-bit  general  purpose  single-chip  microcomputer 


fabricated  with  N-channel  Silicon  Gate  MOS  Technology.  Intended  as  a  ROM-less 
development  device  for  NEC  /iPD780 1/7802  designs,  the  juPD7800  can  also  be  used 
as  a  powerful  microprocessor  in  volume  production  enabling  program  memory  flexi- 
bility. Basic  on-chip  functional  blocks  include  128  bytes  of  RAM  data  memory,  8-bit 
ALU,  32  I/O  lines,  Serial  I/O  port,  and  12-bit  timer.  Fully  compatible  with  the 
industry  standard  8080A  bus  structure,  expanded  system  operation  can  be  easily 
implemented  using  any  of  8080A/8085A  peripheral  and  memory  products.  Total 
memory  address  space  is  64 K  bytes. 


F E ATU RES    •  NMOS  Silicon  Gate  Technology  Requiring  Single  +5V  Supply. 


•  Single-Chip  Microcomputer  with  On-Chip  ALU,  RAM  and  I/O 

-  128  Bytes  RAM 

-  32  I/O  Lines 

•  Internal  12-Bit  Programmable  Timer 

•  On-Chip  1  MHz  Serial  Port 

»  Five-Level  Vectored,  Prioritized  Interrupt  Structure 

-  Serial  Port 

-  Timer 

-  3  External  Interrupts 

•  Bus  Expansion  Capabilities 

-  Fully  8080A  Bus  Compatible 

-  64K  Byte  Memory  Address  Range 

•  Wait  State  Capability 

•  Alternate  Z80™  Type  Register  Set 

•  Powerful  140  Instruction  Set 

•  8  Address  Modes;  Including  Auto- Increment/Decrement 

•  Multi-Level  Stack -Capabilities 

•  Fast  2  jus  Cycle  Time 

•  Bus  Sharing  Capabilities 


PIN  CONFIGURATION  \ 


64  Z3 

62  Z3 

60  ZD 
59  — i 
58  ZD 

56  Z3 

54  =1 
53  ZZZJ 
52  =1 


VCC(  +  5V) 


DB7    CZ  3 

db6czz  4 

DB5    CZ  5 

DB4C=  6 

DB3    CZ  7 


AB14 
AB13 
AB12 
ABn 
AB10 


STB  r— — 
X1  CZ 
VSS  (0V)  — 


INTiCZZ  12 

intq  c=i3 


M1    CZ  15 

WRi  16 

KB  c=17 
PCyCZZ  18 
PCg  CZ  19 
PC5CZZ  20 

pc4  cz:  21 

PC3  tZZZ  22 


30 
31 
32 


14 


MPD 
7800 


TM:  Z80  is  a  registered  trademark  of  Zilog,  Inc. 


Rev/2 
4-1 


MPD7800 


PIN  NO 

DESIGNATION 

FUNCTION 

1 , 49-63 

ABn-ABi* 

(Tri-State,  Output)  16-bit  address  bus. 

2 

EXT 

(Output)  EXT  is  used  to  simulate  /iPD7801/7802 
external  memory  reference  operation.  EXT  distin- 
guishes between  internal  and  external  memory 
references,  and  goes  low  when  locations  4096 
through  65407  are  accessed. 

3-10 

DB0-DB7 

(Tri-State  Input/Output,  active  high)  8-bit  true 
bi-directional  data  bus  used  for  external  data 
exchanges  with  I/O  and  memory. 

11 

INTo 

(Input,  active  high)  Level-sensitive  interrupt  input. 

12 

INT1 

(Input,  active  high)  Rising-edge  sensitive  interrupt 
input.  Interrupts  are  initiated  on  low-to-high  transi- 
tions, providing  interrupts  are  enabled. 

13 

INT2 

(Input)  INT2  is  an  edge  sensitive  interrupt  input 
where  the  desired  activation  transition  is  pro- 
grammable. By  setting  the  ES  bit  in  the  Mask 
Register  to  a  1,  INT2  is  rising  edge  sensitive.  When 
ES  is  set  to  0,  INT2  is  falling  edge  sensitive. 

14 

WAIT 

(Input,  active  low)  WAIT,  when  active,  extends 
read  or  write  timing  to  interface  with  slower 
external  memory  or  I/O.  WAIT  is  sampled  at 

tho  onH  r»f  "To  if  a^+ii/o  nmrpcc^r  on+prc  a  wait 

11 IC  CI  IU  *JI    1  £t  II  aullVC  |JI  UUC00UI  CI  1  LCI  O  a  "Oil 

state  TW  and  remains  in  that  state  as  long  as 
WAIT  is  active. 

15 

M1 

(Output,  active  high)  when  active,  M1  indicates 
that  the  current  machine  cycle  is  an  OP  CODE 
FETCH. 

16 

WR 

(Tri-State  Output,  active  low)  WR,  when  active, 
indicates  that  the  data  bus  holds  valid  data.  Used 
as  a  strobe  signal  for  external  memory  or  I/O  write 
operations.  WR  goes  to  the  high  impedance  state 
during  HALT,  HOLD,  or  RESET. 

17 

RD 

(Tri-State  Output,  active  low)  RD  is  used  as  a 
strobe  to  gate  data  from  external  devices  on  the 
data  bus.  RD  goes  to  the  high  impedance  state 
during  HALT,  HOLD,  and  RESET. 

18-25 

PC0-PC7 

(Input/Output)  8-bit  I/O  configured  as  a  nibble 
I/O  port  or  as  control  lines. 

26 

SCK 

(Input/Output)  SCK  provides  control  clocks  for 
Serial  Port  Input/Output  operations.  Data  on  the 
SI  line  is  clocked  into  the  Serial  Register  on  the  ris- 
ing edge.  Contents  of  the  Serial  Register  is  clocked 
onto  SO  line  on  falling  edges. 

27 

SI 

(Input)  Serial  data  is  input  to  the  processor 
through  the  SI  line.  Data  is  clocked  into  the  Serial 
Register  MSB  to  LSB  with  the  rising  edge  of  SCK. 

28 

SO 

(Output)  SO  is  the  Serial  Output  Port.  Serial  data 
is  output  on  this  line  on  the  falling  edge  of  SCK, 
MSB  to  LSB. 

29 

RESET 

(Input,  active  low)  RESET  initializes  the  jLtPD7800. 

30 

STB 

(Output)  Used  to  simulate  AtPD7801/7802  Port  E 
operation,  indicating  that  a  Port  E  operation  is 
being  performed  when  active. 

31 

X1 

(Input)  Clock  Input 

33-40 

PA0-PA7 

(Output)  8-bit  output  port  with  latch  capability. 

41-48 

PB0-PB7 

(Tri-State  Input/Output)  8-bit  programmable  I/O 
port.  Each  line  configurable  independently  as  an 
input  or  output. 

PIN  DESCRIPTION 


4-2 


|iPD7800 


BLOCK  DIAGRAM 


INT0O 


INT,  a 


INT20" 


PC3/SAK  o- 


LATCH 

INC/DEC 

PC 

SP 

V 

A 

B 

C 

D 

E 

H 

L 

V 

A 

B 

C 

D 

E 

H 

L 

BUFFER 

MAIN 

G.R 


ALT 
G.R 


■L 


DATA 
MEMORY 
(128  BYTE) 


BUFFER 

TV" 


8 


51 


|     MOPE  B  I 


I     LATCH     I      I     LATCH     \      |         F  | 


7% 


PC1j0  PC7.2 


]  c 


INST 
DECODER 

HOLD 

READ/WRITE  CONTROL 

TIMING 

SYSTEM 

CONTROL 

CONTROL 

CONTROL 

AB0-7 


CO- 


£T  i  l  l  l  1  I  I  1  I  1  til 


PC7/  PCg/ 
HOLD  HLDA 


WR      PC5/IO/M     M1     WAIT     RESET    STB     EXT  vcc 


4-3 


MPD7800 


Architecturally  consistent  with  //PD7801/7802  devices,  the  /zPD7800  uses  a  slightly        FUNCTIONAL  DESCRIPTION 
different  pin-out  to  accommodate  for  the  address  bus  and  lack  of  on-chip  clock 
generator.  For  complete  /iPD7800  functional  operation,  please  refer  to  juPD7801 
product  information.  Listed  below  are  functional  differences  that  exist  between 
MPD7800  and  juPD7801  devices. 

IUPD7800/7801  Functional  Differences 

1.  The  functionality  of  /2PD7801  Port  E  is  somewhat  different  on  the  //PD7800. 
Because  the  //PD7800  contains  no  program  memory,  the  address  bus  is  made 
accessible  to  address  external  program  memory.  Thus,  lines  normally  used  for  Port 
E  operation  with  the  juPD7801  are  used  as  the  address  bus  on  the  /iPD7800.  ABrj- 
AB15  is  active  during  memory  access  0  through  4095. 

2.  Consequently  Port  E  instructions  (PEX,  PEN,  and  PER)  have  different 
functionality. 

PEX  Instruction  —  The  contents  of  B  and  C  register  are  output  to  the  address  bus. 

The  value  01 H  is  output  to  the  data  bus.  STB  becomes  active. 

PEN  Instruction  —  B  and  C  register  contents  are  output  to  the  address  bus.  The 

value  02H  is  output  to  the  data  bus.  STB  becomes  active. 

PER  Instruction  —  The  address  bus  goes  to  the  high  impedance  state.  The  value 

04H  is  output  to  the  data  bus.  STB  becomes  active. 

3.  ON-CHIP  CLOCK  GENERATOR.  The  juPD7800  contains  no  internal  clock  gener- 
ator. An  external  clock  source  is  input  to  the  X*|  input. 

4.  PIN  30.  This  pin  functions  as  the  X2  crystal  connection  on  the  juPD7801.  On  the 
juPD7800,  pin  30  functions  as  a  strobe  output  (STB)  and  becomes  active  when  a 
Port  E  instruction  is  executed.  This  control  signal  is  useful  in  simulating  juPD7801 
Port  E  operation  —  indicating  that  a  port  E  operation  is  being  performed. 

5.  PIN  2.  Functions  as  the  <I>  out  clock  output  used  for  synchronizing  system  external 
memory  and  I/O  devices,  on  the  //PD7801.  On  the  /iPD7800,  this  pin  is  used  to 
simulate  external  memory  reference  operation  of  the  juPD7801.  EXT  is  used  to 
distinguish  between  internal  and  external  memory  references  and  goes  low  when 
location  4096  through  65407  are  accessed. 


RECOMMENDED  CLOCK  DRIVE  CIRCUIT 

XI 


-  Wv  1  I  Wv — 


LS74 
D  5 


AAA/ — 0+5 

^10K 

 i  21: 


4-4 


fiPD7800 


ABSOLUTE  MAXIMUM     Operating  Temperature  -10°Cto+70°C 

RATINGS*     Storage  Temperature   -65°C  to  +150° C 

Voltage  On  Any  Pin   -0.3V  to  +7.0V 


Ta  =  25°  C 

*COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


DC  CHARACTERISTICS    Ta  =  -io°c  ~  +70°c,  vcc  =  +5.ov  ±  10% 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Low  Voltage 

V|L 

0 

0.8 

V 

Input  High  Voltage 

V|H1 

2.0 

vCc 

V 

Except  SCK,  X1 

VIH2 

3.8 

vCc 

V 

SCK,  X1 

Output  Low  Voltage 

vol 

0.45 

V 

•OL  =  2.0  mA 

Output  High  Voltage 

vOH1 

2.4 

V 

l0H  =-100juA 

vOH2 

2.0 

V 

I  OH  =-500  juA 

Low  Level  Input  Leakage  Current 

ILIL 

-10 

MA 

V|N  =0V 

High  Level  Input  Leakage  Current 

1 LIH 

10 

juA 

V|N  =  VCC 

Low  Level  Output  Leakage  Current 

'LOL 

-10 

MA 

VOUT  =  0  45V 

High  Level  Output  Leakage  Current 

'loh 

10 

MA 

VOUT  =  Vcc 

Vcc  Power  Supply  Current 

'cc 

110 

200 

mA 

CAPACITANCE    Ta  =  25°c,vcc  =  gnd  =  ov 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

C| 

10 

pF 

fc  =  1  MHz 
All  pins  not 
under  test  at  0V 

Output  Capacitance 

c0 

20 

pF 

Input/Output  Capacitance 

C|0 

20 

PF 

4-5 


|iPD7800 


Ta  =  -io°cto+70°c,  vCc  =  +5.ov±  10%  AC  CHARACTERISTICS 

CLOCK  TIMING 


PARAMETER 

SYMBOL 

LIMITS 

TEST 
CONDITIONS 

MIN 

MAX 

UNITS 

XouT  Cycle  Time 

*CYX 

454 

2000 

ns 

tCYX 

XquT  Low  Level  Width 

*XXL 

212 

ns 

*XXL 

XquT  H|9n  Level  Width 

tXXH 

212 

ns 

*XXH 

READ/WRITE  OPERATION 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN         |  MAX 

RDLE.^X0UT  L.E. 

tRX 

20 

ns 

tcYX  =  500  ns 

Address  (PErj-15)  ~*  Data 
Input 

tAD1 

550  +  500  x  N 

ns 

RD  T.E.  ->  Address 

tRA 

200(T3);  700(T4) 

ns 

"RD~L.E.->-  Data  Input 

tRD 

350  +  500  x  N 

ns 

"RD~T.E.^Data  Hold 
Time 

tRDH 

0 

ns 

RD*Low  Level  Width 

tRR 

850  +  500  x  N 

ns 

RD  L.E.-*  WAIT  L.E. 

tRWT 

450 

ns 

Address  (PE0-15)  -*■ 
WAIT  L.E. 

*AWT1 

650 

ns 

WAIT  Set  Up  Time 
(Referenced  from 

XfJUT  L-E-) 

*WTS 

180 

ns 

WAIT  Hold  Time 
(Referenced  from 
X0UT  L.E.) 

*WTH 

0 

120 

ns 

M1  -+RTJL.E. 

tMR 

200 

ns 

RD*T.E.-+M1 

tRM 

200 

ns 

I0/M-*RU  L.E. 

t|R 

200 

ns 

fTUt.e.^  io/M 

tRI 

200 

ns 

X0UT  L.E.-»WR  L.E. 

txw 

270 

ns 

Address  (PErj-1 5)  -* 
xOUTTE- 

tAX 

300 

ns 

Address  (PE0-15)  -> 
Data  Output 

*AD2 

450 

ns 

Data  Output  WR 
T.E. 

*DW 

600  +  500  x  N 

ns 

WR  T.E.  ->  Data 
Stabilization  Time 

*WD 

150 

ns 

Address  (PE0-15)  -»• 
WR  L.E. 

tAW 

400 

ns 

WR  T.E. -Address 
Stabilization  Time 

tWA 

200 

ns 

WR  Low  Level  Width 

tyvw 

600  +  500  x  N 

ns 

IO/M~-»WR  L.E. 

t|W 

500 

ns 

WRT.E.-+  IO/M 

twi 

250 

ns 

4-6 


fiPD7800 


AC  CHARACTERISTICS     SERIAL  I/O  OPERATION 


(CONT.) 


PARAMETER 

SYMBOL 

MIN 

MAX 

UNIT 

CONDITION 

oOn  cycle  I  ime 

tCYK 

800 

ns 

SCK  Input 

900 

4000 

ns 

SCK  Output 

SCK  Low  Level  Width 

*KKL 

350 

ns 

SCK  Input 

400 

ns 

SCK  Output 

SCK  High  Level  Width 

tKKH 

350 

ns 

SCK  Inpgt 

400 

SCK  Output 

SI  Set-Up  Time  (referenced  from  SCK  T.E.) 

*SIS 

80 

SI  Hold  Time  (referenced  from  SCK  T.E.) 

tSIH 

260 

ns 

SCK  L.E.    SO  Delay  Time 

*KO 

180 

ns 

'§CT*High  -*•  SCK  L.E. 

tCSK 

100 

ns 

SCK  T.E.  ->•  SCS  Low 

tKCS 

100 

ns 

SCK  T.E. SAK  Low 

tKSA 

260 

ns 

PEN,  PEX,  PER  OPERATION 

PARAMETER 

SYMBOL 

MIN 

MAX 

UNIT 

CONDITION 

Xt  L.E. -»  EXT 

tXE 

250 

ns 

*CYX  =  500  ns 

Address  (ABo-15)  -*  STB  L.E. 

tAST 

200 

Data  (DBo-7)  -*STB  L.E. 

tDST 

200 

STB  Hold  Time 

tSTST 

300 

STB  ->  Data 

tSTD 

400 

HOLD  OPERATION 

PARAMETER 

SYMBOL 

MIN 

MAX 

UNIT 

CONDITION 

HOLD  Set-Up  Time  (referenced  from 
*OUT  L.E.) 

tHDSi 

100 

ns 

tHDS2 

100 

ns 

HOLD  Hold  Time  (referenced  from  0OUT 
L.E.) 

tHDH 

100 

ns 

X0UT  L.E.  ->  HLDA 

tXHA 

100 

ns 

HLDA  High  -»  Bus  Floating  (High  Z  State) 

tHABF 

-150 

150 

ns 

HLDA  Low-*  Bus  Enable 

tHABE 

350 

ns 

Notes: 

(T)  AC  Signal  waveform  (unless  otherwise  specified) 

2.4  w  j  

NyT-   2.0  MEASURING  20 

/\r    0.8  P0INTS  0.8 

0.45  *  > 

(2)  Output  Timing  is  measured  with  1  TTL  +  200  pF  measuring  points  are  Vqh  =  2.0V 

VOL  =  0.8V 

(3)  L.E.  -  Leading  Edge,  T.E.  =  Trailing  Edge 


4-7 


MPD7800 


tcYX  DEPENDENT  AC  PARAMETERS  AC  CHARACTERISTICS 


PARAMETER 

MIN/MAV 

IVIIIv/IVIM/V 

UNIT 

*RX 

(1/25)  T 

MIN 

ns 

xADi 

(3/2  +  N)T-  200 

MAX 

ns 

tRA  (T3) 

(1/2)  T-  50 

MIN 

ns 

tRA  <T4) 

(3/2)  T-  50 

MIN 

ns 

tRD 

(1  +N)T-  150 

MAX 

ns 

*RR 

(2  +  N)T-  150 

MIN 

ns 

rRWT 

(3/2)  T  -  300 

MAX 

ns 

tAWT1 

(2)T-  350 

MIN 

ns 

*MR 

(1/2)  T-  50 

MIN 

ns 

tRM 

(1/2)  T-  50 

MIN 

ns 

t|R 

(1/2)  T-  50 

MIN 

ns 

tRI 

(1/2)  T-  50 

MIN 

ns 

lXW 

(27/50) T 

MAX 

ns 

tAD2 

T-  50 

MIN 

ns 

XD\N 

(3/2  + N)T-  150 

MIN 

ns 

%D 

(1/2)  T-  100 

MIN 

ns 

lA\N 

T-  100 

MIN 

ns 

X\NA 

(1/2)  T-  50 

MIN 

ns 

tww 

(3/2  +  N)T-  150 

MIN 

ns 

T 

MIN 

ns 

%l 

(1/2) T 

MIN 

ns 

tHABE 

(1/2)  T-  150 

MAX 

ns 

tAST 

(2/5)  T 

MIN 

ns 

XDST 

(2/5)  T 

MIN 

ns 

tSTST 

(3/5)  T 

MIN 

ns 

tSTD 

(4/5)  T 

MIN 

ns 

(CONT.) 


Notes:  (T)  N  =  Number  of  Wait  States 
©  T  =  tCYX 

(3)  Only  above  parameters  are  t^y^  dependent 

(3)  When  a  crystal  frequency  other  than  4  MHz  is  used  (trjyx  =  ^on  ns) 
the  above  equations  can  be  used  to  calculate  AC  parameter 
values. 


4-8 


MPD7800 


4-9 


fiPD7800 


SCK  • 


SERIAL  I/O  OPERATION 


-  ~*  tKKH — »»j 

 4- 


-*tSIS«-  -»tSIH»- 


f  V 


X. 


TIMING  WAVEFORMS 
(CONT.) 


PEN,  PEX,  PER  OPERATION 


\  /  \  /  V 


— ^   INVALID  )  ^ 


-A 


HOLD  OPERATION 


-T2CT,)   m\m           T3(T2)            m\m  T4tT3)  - 

A                /                 \                 i                  \  ' 
tHDSi|»       "»-•  «HDH 

LO 

—  Ti   

ADDRESS  CONTROL 

^  

H        r»  'HABF 

"IF 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 


Plastic  Quit,  (xPD7800G 


4-10 


7800DS-REV2-7-83-CAT 


NEC 


|aPD7801/7802 


HIGH  END  SINGLE  CHIP  8-BIT  MICROCOMPUTER 
WITH  4K  ROM 


PRODUCT  DESCR  IPTION      The  NEC  fjiPD7801/7802  is  an  advanced  8-bit  general  purpose  single-chip  microcomputer  fabricated 

with  N-Channel  Silicon  Gate  MOS  technology 

The  NEC  n,PD7801/7802  is  intended  to  serve  a  broad  spectrum  of  8-bit  designs  ranging  from  enhanced 
single  chip  applications  extending  into  the  multi-chip  microprocessor  range.  All  the  basic  functional 
blocks  -  8-bit  ALU,  48  I/O  lines,  Serial  I/O  port,  12-bit  timer,  and  clock  generator  are  provided  on-chip  to 
enhance  stand-alone  applications.  Fully  compatible  with  the  industry  standard  8080A  bus  structure, 
expanded  system  operation  can  be  easily  implemented  using  any  of  the  8080A/8085A  peripherals  and 
memory  products.  Total  memory  space  can  be  increased  to  64K  bytes. 

The  powerful  140  instruction  set  coupled  with  4K  bytes  of  ROM  program  memory  and  128  bytes  of 
RAM  data  memory  greatly  extends  the  range  of  single  chip  microcomputer  applications.  Five  level  vec- 
tored interrupt  capability  combined  with  a  2  microsecond  cycle  time  enable  the  (xPD7801  to  compete 
with  multi-chip  microprocessor  systems  with  the  advantage  that  most  of  the  support  functions  are  on- 
chip. 


FEATURES      •    NMOS  Silicon  Gate  Technology  Requiring  +5V  Supply 

•  Complete  Smale-Chip  Microcomputer  with  On-Chtp  ROM,  RAM  and  I/O 

-  4K  Bytes  ROM-7801 

-  128  Bytes  RAM 

-  6KBytes-7802 

-  64Bytes-7802 

-  48  I/O  Lines 

•  Internal  12-Bit  Programmable  Timer 

•  On-Chip  1  MHz  Serial  Port 

•  Five  Level  Vectored,  Prioritized  Interrupt  Structure 

-  Serial  Port 

-  Timer 

-  3  External  Interrupts 

•  Bus  Expansion  Capabilities 

-  Fully  8080A  Bus  Compatible 

-  60K  Bytes  External  Memory  Address  Range-7801 

-  58K  Bytes-7802 

•  On-Chip  Clock  Generator 

•  Wait  State  Capability 

•  Alternate  Z80™  Type  Register  Set 

•  Powerful  140  Instruction  Set 

•  8  Address  Modes,  Including  Auto-Increment/Decrement 

•  Multi-Level  Stack  Capabilities 

•  Fast  2  jus  Cycle  Time 

•  Bus  Sharing  Capabilities 


3     VCC  (  +  5V) 
PE14/AB14 
P  PE13/AB13 
PE12/AB12 
P  PEn/ABu 
PE10/AB10 

□  PE9/AB9 
PE8/AB8 

□  PE7/AB7 
PE6/AB6 

□  PE5/AB5 
PE4/AB4 

P  PE3/AB3 
PE2/AB2 
PE-j/ABf 
PE0/AB0 

□  PB7 
PB6 

3  PB5 
PB4 

□  PB3 
PB2 

3  PB1 
IZIPBO 
PA7 
PA6 
J  PA5 
ZZJPA4 
1  PA3 
|PA2 
3  PA1 
ZDPAo 


TM:  Z80  is  a  registered  trademark  of  Zilog,  Inc. 

Rev/2 
4-11 


jjlPD7801/7802 


[  PIN  NO. 

DESIGNATION 

FUNCTION 

49-63 

PE0/AB0- 

(Tri-State,  Output)  16-bit  address  bus. 

1 
2 

PE15/AB15 
0OUT 

(Output)  0OUT  provides  a  prescaled  output  clock 
for  use  with  external  I/O  devices  or  memories. 
0OUT  frequency  is  f XTAI_/2. 

3-10 

DB0-DB7 

(Tri-State  Input/Output,  active  high)  8-bit  true 
bi-directional  data  bus  used  for  external  data 
exchanges  with  I/O  and  memory. 

11 

INTo 

(Input,  active  high)  Level-sensitive  interrupt  input. 

12 

INT1 

(Input,  active  high)  Rising-edge  sensitive  interrupt 
input.  Interrupts  are  initiated  on  low-to-high  transi- 
tions, providing  interrupts  are  enabled. 

13 

INT2 

(Input)  INT2  is  an  edge  sensitive  interrupt  input 
where  the  desired  activation  transition  is  pro- 
grammable. By  setting  the  ES  bit  in  the  Mask 
Register  to  a  1,  INT2  is  rising  edge  sensitive.  When 
ES  is  set  to  0,  INT2  is  falling  edge  sensitive. 

14 

WAIT 

(Input,  active  low)  WAIT,  when  active,  extends 
read  or  write  timing  to  interface  with  slower 
external  memory  or  I/O.  WAIT  is  sampled  at 
the  end  of  T2,  if  active  processor  enters  a  wait 
state  TW  and  remains  in  that  state  as  long  as 
WAIT  is  active. 

15 

M1 

(Output,  active  high)  when  active,  M1  indicates 
that  the  current  machine  cycle  is  an  OP  CODE 
FETCH. 

16 

WR 

(Tri-State  Output,  active  low)  WR,  when  active, 
indicates  that  the  data  bus  holds  valid  data.  Used 
as  a  strobe  signal  for  external  memory  or  I/O  write 
operations.  WR  goes  to  the  high  impedance  state 

Hnrinn  MAI  T  HOI  PJ  r»r  RF9FT 
QUling  nnL  1  ,  nULU,  Ol  nCOt  1  . 

17 

RD 

(Tri-State  Output,  active  low)  RD  is  used  as  a 

SXlODc  XO  gate  (Jala  TfOiTl  CAltJIlldl  UcvllsCo  (JillU  li ic 

data  bus.  RD  goes  to  the  high  impedance  state 
during  HALT,  HOLD,  and  RESET. 

18-25 

PC0-PC7 

(Input/Output)  8-bit  I/O  configured  as  a  nibble 
I/O  port  or  as  control  lines. 

26 

SCK 

(Input/Output)  SCK  provides  control  clocks  for 
Serial  Port  Input/Output  operations.  Data  on  the 
SI  line  is  clocked  into  the  Serial  Register  on  the  ris- 
mg  ecige.  moments  ot  xne  osndi  negiaicr  ia  uuukcu 
onto  SO  line  on  falling  edges. 

27 

SI 

(Input)  Serial  data  is  input  to  the  processor 
through  the  SI  line.  Data  is  clocked  into  the  Serial 
Register  MSB  to  LSB  with  the  rising  edge  of  SCK. 

28 

SO 

(Output)  SO  is  the  Serial  Output  Port.  Serial  data 
is  output  on  this  line  on  the  falling  edge  of  SCK, 
MSB  to  LSB. 

29 

RESET 

(Input,  active  low)  RESET  initializes  the  jLtPD7801. 

30 

X2 

(Output)  Oscillator  output. 

31 

X1 

(Input)  Clock  Input. 

OG-4U 

DAn  PA -7 

(Output)  8-bit  output  port  with  latch  capability. 

41-48 

PB0-PB7 

(Tri-State  Input/Output)  8-bit  programmable  I/O 
port.  Each  line  configurable  independently  as  an 
input  or  output. 

4-12 


JJLPD7801/7802 


BLOCK  DIAGRAM 


PC3/SAKO-  1  f/F  I 


21 


□  c 


8    y     8111  l  11  11  j  u 


FUNCTIONAL 
DESCRIPTION 


Memory  Map 

The  |xPD780 1/7802  can  directly  address  up  to  64K  bytes  of  memory.  Except  for 
the  on-chip  ROM  and  RAM,  any  memory  location  can  be  used  as  either  ROM  or 
RAM.  The  following  memory  map  defines  the  0-64K  byte  memory  space  for  the 
|xPD7801/7802  showing  that  the  Reset  Start  Address,  Interrupt  Start  Address, 
Call  Tables,  etc.,  are  located  in  the  internal  ROM  area. 


65,471 
65,535 


INTERNAL 
ROM 
(0-6144) 


EXTERNAL 
<i  MEMORY 


INTERNAL 
RAM 


4-13 


|xPD7801/7802 


I/O  Ports 


PORT 

FUNCTIONS 

Port  A 
Port  B 
Port  C 
Port  E 

8-bit  output  port  with  latch 

8-bit  programmable  Input/Output  port  w/latch 

8-bit  nibble  I/O  or  Control  port 

16-bit  Address/Output  Port 

FUNCTIONAL 
DESCRIPTION 
(CONT.) 


Port  A 

Port  A  is  an  8-bit  latched  output  port.  Data  can  be  readily  transferred  between  the 
accumulator  and  the  output  latch  buffers.  The  contents  of  the  output  latches  can  be 
modified  using  Arithmetic  and  logic  instructions.  Data  remains  latched  at  Port  A  unless 
acted  on  by  another  Port  A  instruction  or  a  RESET  is  issued. 


Port  B 

Port  B  is  an  8-bit  I/O  port.  Data  is  latched  at  Port  B  in  both  the  Input  or  Output  modes. 
Each  bit  of  Port  B  can  be  independently  set  to  either  Input  or  Output  modes.  The 
Mode  B  register  programs  the  individual  lines  of  Port  B  to  be  either  an  Input 
(Mode  Bn  =  1 )  or  an  Output  (Mode  Bn  _  q). 

Port  C 

Port  C  is  an  8-bit  I/O  port.  The  Mode  C  register  is  used  to  program  the  upper  6  bits  of 
Port  C  to  provide  control  functions  or  to  set  the  I/O  structure  per  the  following  table. 


MODE  Cn  =  o 

MODE  Cn  ==  1 

PC0 

Output 

Input 

PC1 

Output 

Input 

PC2 

SCS  Input 

Input 

PC3 

SAK  Output 

Output 

PC4 

To  Output 

Output 

pc5 

I O/M  Output 

Output 

PC6 

HLDA  Output 

Output 

PC7 

HOLD  Input 

Input 

PortE 

Port  E  is  a  16-bit  address  bus/output  port.  It  can  be  set  to  one  of  three  operating  modes 
using  the  PER,  PEN,  or  PEX  instructions. 

•  16-Bit  Address  Bus  —  the  Per  instruction  sets  this  mode  for  use  with  external  I/O  or 
memory  expansion  (up  to  60K  bytes,  externally). 

•  4-Bit  Output  Port/12  Bit  Address  Bus  —  the  PEN  instruction  sets  this  mode  which 
allows  for  memory  expansion  of  up  to  4K  bytes,  externally,  plus  the  transfer  of  4-bit 
nibbles. 

•  16-Bit  Output  Port  -  the  PEX  instruction  sets  Port  E  to  a  16-bit  output  port.  The  con- 
tents of  B  and  C  registers  appear  on  PEs-15  and  PEq-7,  respectively. 


4-14 


(1PD7801/7802 


FUNCTIONAL 
DESCRIPTION 
(CONT.) 


Timer  Operation 


PRE- 
SCALER 
(4  ms) 


12  BIT  DOWN  COUNTER 


2 


TIMER 

F/F 

BORROW 


TIMER  •  REG  0 


TIMER 
REG  1 


30 


3  INTERNAL  BUS 


TIMER  BLOCK  DIAGRAM 


A  programmable  12-bit  timer  is  provided  on-chip  for  measuring  time  intervals,  generat- 
ing pulses,  and  general  time-related  control  functions.  It  is  capable  of  measuring  time 
intervals  from  4  /is  to  16  /is  in  duration.  The  timer  consists  of  a  prescaler  which 
decrements  a  12-bit  counter  at  a  fixed  4  jj.s  rate.  Count  pulses  are  loaded  into  the 
12-bit  down  counter  through  timer  register  (TMO  and  TM1).  Count-down  operation  is 
initiated  upon  extension  of  the  STM  instruction  when  the  contents  of  the  down 
counter  are  fully  decremented  and  a  borrow  operation  occurs,  an  interval  interrupt 
(INTT)  is  generated.  At  the  same  time,  the  contents  of  TMO  and  TM1  are  reloaded 
into  the  down-counter  and  countdown  operation  is  resumed.  Count  operation  may  be 
restarted  or  initialized  with  the  STM  instruction.  The  duration  of  the  timeout  may  be 
altered  by  loading  new  contents  into  the  down  counter. 

The  timer  flip  flop  is  set  by  the  STM  instruction  and  reset  on  a  countdown  operation. 
Its  output  (TO)  is  available  externally  and  may  be  used  in  a  single  pulse  mode  or  general 
external  synchronization. 

Timer  interrupt  (INTT)  may  be  disabled  through  the  interrupt. 
Serial  Port  Operation 


SERIAL  PORT  BLOCK  DIAGRAM 


4-15 


JJLPD7801/7802 


The  on-chip  serial  port  provides  basic  synchronous  serial  communication  FUNCTIONAL 
functions  allowing  the  NEC  |xPD7801/7802  to  serially  interface  with  external  DESCRIPTION 
devices.  (CONT.) 

Serial  Transfers  are  synchronized  with  either  the  internal  clock  or  an  external  clock 
input  (SCK).  The  transfer  rate  is  fixed  at  1  Mbit/second  if  the  internal  clock  is  used 
or  is  variable  between  DC  and  1  Mbit/second  when  an  external  clock  is  used.  The 
Clock  Source  Select  is  determined  by  the  Mode  C  register.  The  serial  clock  (internal 
or  external  SCK)  is  enabled  when  the  Serial  Chip  Select  Signal  (SCS)  goes  low.  At  this 
time  receive  and  transmit  operations  through  the  Serial  Input  port  (SI )/Serial  Output 
port  (SO)  are  enabled.  Receive  and  transmit  operations  are  performed  MSB  first. 

Serial  Acknowledge  (SAK)  goes  high  when  data  transfers  between  the  accumulator 
and  Serial  Register  is  completed.  SAK  goes  low  when  the  buffer  becomes  full  after 
the  completion  of  serial  data  receive  or  transmit  operations.  While  SAK  is  low,  no 
further  data  can  be  received. 

Interrupt  Structure 

The  (xPD7801/7802  provides  a  maskable  interrupt  structure  capable  of  han- 
dling vectored  prioritized  interrupts.  Interrupts  can  be  generated  from  six  dif- 
ferent sources;  three  external  interrupts,  two  internal  interrupts,  and  non- 
maskable software  interrupt.  Each  interrupt  when  activated  branches  to  a 
designated  memory  vector  location  for  that  interrupt. 


INT 

VECTORED  MEMORY 
LOCATION 

PRIORITY 

TYPE 

I  NTT 

8 

3 

Internal,  Timer 
Overflow 

I  NTS 

64 

6 

Internal,  Serial 
Buffer  Full/Empty 

INTO 

4 

2 

Ext.,  level  sensitive 

INT1 

16 

4 

Ext.,  Rising  edge 
sensitive 

INT2 

32 

5 

Ext.,  Rising/Falling 
edge  sensitive 

SOFTI 

96 

1 

Software  Interrupt 

4-16 


fxPD7801/7802 


FUNCTIONAL 
DESCRIPTION 
(CONT.) 


REGISTERS 


RESET  (Reset) 

An  active  low-signal  on  this  input  for  more  than  4  jus  forces  the  juPD7801 
into  a  Reset  condition.  RESET  affects  the  following  internal  functions: 

•  The  Interrupt  Enable  Flags  are  reset,  and  Interrupts  are  inhibited. 

•  The  Interrupt  Request  Flag  is  reset. 

•  The  HALT  flip  flop  is  reset,  and  the  Halt-state  is  released. 

•  The  contents  of  the  MODE  B  register  are  set  to  FFh,  and  Port  B 
becomes  an  input  port. 

•  The  contents  of  the  MODE  C  register  are  set  to  FFh.  Port  C  becomes 
an  I/O  port  and  output  lines  go  low. 

•  All  Flags  are  reset  to  0. 

•  The  internal  COUNT  register  for  timer  operation  is  set  to  F FFh  and  the 
timer  F/F  is  reset. 

•  The  ACK  F/F  is  set. 

•  The  HLDA  F/F  is  reset. 

•  The  contents  of  the  Program  Counter  are  set  to  OOOQh. 

•  The  Address  Bus  (PEo-15),  Data  Bus  (DBfj-7),  RD,  and  WR  go  to 
a  high  impedance  state. 


Once  the  RESET  input  goes  high,  the  program  is  started  at  location  OOOOh. 
The  /2PD7801  contains  sixteen  8-bit  registers  and  two  16-bit  registers. 

0  15 


PC 


SP 


70 


V 

A 

B 

C 

D 

E 

H 

L 

V 

A' 

Bf 

C 

D' 

E' 

H' 

L' 

•  Main 


►  Alternate 


General  Purpose  Registers  (B,  C,  D,  E,  H,  L) 

There  are  two  sets  of  general  purpose  registers  (Main:  B,  C,  D,  E,  H,  L: 
Alternate:  B',  C\  D',  H',  L').  They  can  function  as  auxiliary  registers  to  the 
accumulator  or  in  pairs  as  data  pointers  (BC,  DE,  HL,  B'C,  D'E',  H'L').  Auto  Incre- 
ment and  Decrement  addressing  mode  capabilities  extend  the  uses  for  the  DE,  HL, 
D'E',  and  H'L'  register-pairs.  The  contents  of  the  BC,  DE,  and  HL  register-pairs 
can  be  exchanged  with  their  Alternate  Register  counterparts  using  the  EXX 
instruction. 


4-17 


fjtPD7801/7802 


Vector  Register  (V) 

When  defining  a  scratch  pad  area  in  the  memory  space,  the  upper  8-bit  memory 
address  is  defined  in  the  V-register  and  the  lower  8-bits  is  defined  by  the  immediate 
data  of  an  instruction.  Also  the  scratch  pad  indicated  by  the  V-register  can  be  used 
as  256  x  8-bit  working  registers  for  storing  software  flags,  parameters  and  counters. 

Accumulator  (A) 

All  data  transfers  between  the  |xPD7801/7802  and  external  memory  or  I/O  are 
done  through  the  accumulator.  The  contents  of  the  Accumulator  and  Vector 
Registers  can  be  exchanged  with  their  Alternate  Registers  using  the  EX 
instruction. 

Program  Counter  (PC) 

The  PC  is  a  16-bit  register  containing  the  address  of  the  next  instruction  to  be 
fetched.  Under  normal  program  flow,  the  PC  is  automatically  incremented.  However, 
in  the  case  of  a  branch  instruction,  the  PC  contents  are  from  another  register  or 
an  instruction's  immediate  data.  A  reset  sets  the  PC  to  OOOOh. 

Stack  Pointer  (SP) 

The  stack  pointer  is  a  16-bit  register  used  to  maintain  the  top  of  the  stack  area  (last- 
in-first-out).  The  contents  of  the  SP  are  decremented  during  a  CALL  or  PUSH 
instruction  or  if  an  interrupt  occurs.  The  SP  is  incremented  during  a  RETURN  or 
POP  instruction. 


FUNCTIONAL 
DESCRIPTION  (CONT.) 


Register  Addressing 
Register  Indirect  Addressing 
Auto- Increment  Addressing 
Auto-Decrement  Addressing 

Register  Addressing 


Working  Register  Addressing 
Direct  Addressing 
Immediate  Addressing 
Immediate  Extended  Addressing 


ADDRESS  MODES 


OPCODE 

OPERAND 

The  instruction  opcode  specifies  a  register  r  which  contains  the  operand. 
Register  Indirect  Addressing 

memory 


OPCODE 


rp 

ADDRESS 

OPERAND 


The  instruction  opcode  specifies  a  register  pair  which  contains  the  memory  address 
of  the  operand.  Mnemonics  with  an  X  suffix  are  ending  this  address  mode. 


Auto-Increment  Addressing 


rp 


memory 


OPCODEh 


1  ADDRESSr 


5 


OPERAND 


The  opcode  specifies  a  register  pair  which  contains  the  memory  address  of  the, 
operand.  The  contents  of  the  register  pair  is  automatically  incremented  to  point  to 
a  new  operand.  This  mode  provides  automatic  sequential  stepping  when  working  with 
a  table,  of  operands. 


4-18 


|xPD7801/7802 


ADDRESS  MODES  (CONT.)     Auto-Decrement  Addressing 


OPCODE 


Working  Register  Addressing 


PC 

PC  +  1 


OPCODE 


displacement 


rp 


ADDRESS 


-1 


V  Register 
Contents 


15 


8  7 


memory 


OPERAND 


memory 


OPERAND 


The  contents  of  the  register  is  linked  with  the  byte  following  the  opcode  to  form  a 
memory  address  whose  contents  is  the  operand.  The  V  register  is  used  to  indicate 
the  memory  page.  This  address  mode  is  useful  as  a  short-offset  address  mode  when 
working  with  operands  in  a  common  memory  page  where  only  1  additional  byte 
is  required  for  the  address.  Mnemonics  with  a  W  suffix  ending  this  address  mode. 


Direct  Addressing 


PC 

OPCODE 

PC  +  1 

Low  Address 

PC +  2 

High  Address 

Memory 


operand 


1  byte 


Low  Operand 


High  Operand 


2  byte 


The  two  bytes  following  the  opcode  specify  an  address  of  a  location  containing  the 
operand. 

Immediate  Addressing 


PC 

OPCODE 

PC  +  1 

OPERAND 

Immediate  Extended  Addressing 

PC 

OPCODE 

PC  +  1 

Low  Operand 

PC +  2 

High  Operand 

4-19 


|xPD7801/7802 


Operand  Description  INSTRUCTION  SET 


OrcRAND 

nCOPDI  DTI  /~VM 

DfcbCKIr  1  lUINI 

r 

V,  A,  B,  C,  D,  E,  H,  L 

r1 

d  p  n   c  u  i 
d,  C,  U,  h,  n,  L 

r2 

ADO 

A,  d,  C 

sr 

DA   DD  DO  ft /I  1/  KJID  A/ir>  Tl\/in  TIV/M  c 

r  A  re  PC  MK  MB  ML  I  MU  I IV!  I  o 

sr1 

OA    DD  DO  ft  V!  1/  C* 

PA  PB  PC  MK  S 

sr2 

PA  PB  PC  MK 

rp 

SP,  B,  D,  H 

rp1 

V,  B,  D,  H 

rpa 

B,  D,  H,  D+,  H+,  D-,  H- 

rpal 

B,  D,  H 

wa 

8  bit  immediate  data 

word 

16  bit  immediate  data 

byte 

8  bit  immediate  data 

bit 

3  bit  immediate  data 

f 

FO,  F1,F2,  FT,  FS, 

Notes:     1.  When  special  register  operands  sr,  sr1,  sr2  are  used;  PA=Pori  A,  PB~Port  B, 
PC=Port  C,  MK=Mask  Register,  MB=Mode  B  Register,  MC=Mode  C 
Register,  TM0=Timer  Register  0,  TM1=Timer  Register  1,S=Serial  Register. 

2.  When  register  pair  operands  rp,  rp1  are  used;  SP=Stack  Pointer,  B=BC, 
D=DE,  H=HL,  V=VA. 

3.  Operands  rPa,  rPal,  wa  are  used  in  indirect  addressing  and  auto-increment/ 
auto-decrement  addressing  modes. 

B=(BC),  D=(DE),  H=(HL) 

D+=(DE)+,  H+=(HL)+  D-=(DE)",  H-=(HL)". 

4.  When  the  interrupt  operand  f  is  used;  F0=INTF0,  F1  =  INTF1,  F2=INTF2, 
FT=INTFT,  FS=INTFS. 


4-20 


JJLPD7801/7802 


INSTRUCTION  GROUPS 


MNEMONIC 

OPERANDS 

NO. 
BYTES 

CLOCK 
CYCLES 

OPERATION 

SKIP 
CONDITION 

FLAGS 

CY 

Z 

8-BIT  DATA  TRANSFER 

MOV 

r1,  A 

1 

4 

r1  -A 

MOV 

A,  M 

1 

4 

A  w1 

MOV 

sr,  A 

2 

10 

sr «-  A 

MOV 

A,  sr1 

2 

10 

A^srl 

MOV 

r,  word 

4 

17 

r  <-  (word) 

MOV 

word,  r 

4 

17 

(word) «-  r 

MVI 

r,  byte 

2 

7 

r  •<-  byte 

MVIW 

wa,  byte 

3 

13 

(V,  wa)  <-byte 

MVIX 

rpal ,  byte 

2 

10 

(rpaD  t-byte 

STAW 

wa 

2 

10 

(V,  wa) «-  A 

LDAW 

wa 

2 

10 

A  -  (V,  wa) 

STAX 

rpa 

7 

(rpa)  «-  A 

LDAX 

rpa 

7 

A  <-  (rpa) 

EXX 

4 

Exchange  register  sets 

EX 

4 

V,  A  «♦  V,  A 

BLOCK 

13  (C+1) 

(DE)+^(HL)+,  C<-C-  1 

16-BIT  DATA  TRANSFER 

SBCD 

word 

4 

20 

(word)  «-C,  (word  +  1)  *- B 

SDED 

word 

4 

20 

(word) «-  E,  (word  +  1 ) «-  D 

SHLD 

word 

4 

20 

(word)  *-  L,  (word  +  1 )  -  H 

SSPD 

word 

4 

20 

(word) «-  SP[_,  (word  +  1 )  <-  SPh 

LBCD 

word 

4 

20 

C  «-  (word),  B     (word  +  1 ) 

LDED 

word 

4 

20 

E  *-  (word),  D  *-  (word  +  1 ) 

LHLD 

word 

4 

20 

L-(word),  H*-(word  +  1) 

LSPD 

word 

4 

20 

SPl  «-  (word),  SPh     (word  +  1 ) 

PUSH 

rp1 

2 

17 

(SP-  1)-rp1H.  (SP-2)  *-rp1L 

POP 

rp1 

2 

15 

rp1L^-  (SP) 

rp1  h  <-  (SP  +  1 ),  SP*-SP  +  2 

LXI 

rp,  word 

3 

10 

rp  *-  word 

TABLE 

1 

19 

C  <-  (PC  +  2  +  A) 
B     (PC  +  2  +  A  +  1 ) 

4-21 


(iPD7801/7802 


NO. 

CLOCK 

SKIP 

FLAGS 

MNEMONIC 

OPERANDS 

BYTES 

CYCLES 

OPERATION 

CONDITION 

CY 

Z 

ARITHMETIC 

ADD 

A,  r 

2 

8 

A^A  +  r 

$ 

t 

ADD 

r,  A 

2 

8 

r  +-  r  +  A 

t 

t 

ADDX 

rpa 

2 

11 

A  *~  A  +  (rpa) 

t 

t 

ADC 

A,  r 

2 

8 

A<- A  +  r  +  CY 

$ 

ADC 

r,  A 

2 

8 

r  <-  r  +  A  +  CY 

$ 

ADCX 

rpa 

2 

11 

A  <-  A  +  (rpa)  +  CY 

t 

SUB 

A,  r 

2 

8 

A<-A-  r 

t 

SUB 

r,  A 

2 

8 

r  w- A 

$ 

SUBX 

rpa 

2 

11 

A<- A-  (rpa) 

t 

SBB 

A,r 

2 

8 

A  +-  A  -  r  -  CY 

t 

SBB 

r,  A 

2 

8 

r  +-  r  -  A  -  CY 

$ 

SBBX 

rpa 

2 

11 

A  -  A  -  (rpa)  -  CY 

t 

ADDNC 

A,  r 

2 

8 

A-A  +  r 

No  Carry 

$ 

ADDNC 

r,  A 

2 

8 

r  *-  r  +  A 

No  Carry 

t 

ADDNCX 

rpa 

2 

11 

A  <-  A  +  (rpa) 

No  Carry 

t 

SUBNB 

A,r 

2 

8 

A<-A-  r 

No  Borrow 

$ 

SUBNB 

r,  A 

2 

8 

r<-r-  A 

No  Borrow 

t 

SUBNBX 

rpa 

2 

11 

A  «-  A  -  (rpa) 

No  Borrow 

t 

LOGICAL 

ANA 

A,  r 

2 

8 

A*- A  A  r 

t 

ANA 

r,  A 

2 

8 

r<-  r  A  A 

$ 

ANAX 

rpa 

2 

11 

A*-  A  A  (rpa) 

t 

ORA 

A,  r 

2 

8 

A*-Ayr 

t 

ORA 

r,  A 

2 

8 

r  <-  r  vA 

t 

ORAX 

rpa 

2 

11 

A  +-  A  v  (rpa) 

t 

XRA 

A,  r 

2 

8 

A*-AVr 

$ 

XRA 

r,A 

2 

8 

A  +-  r  V  A 

t 

XRAX 

rpa 

2 

11 

A  *-  A  V  (rpa) 

t 

GTA 

A,  r 

2 

8 

A-  r  -  1 

No  Borrow 

t 

t 

INSTRUCTION  GROUPS  (CONT.) 


4-22 


|xPD7801/7802 


INSTRUCTION  GROUPS  (CONT.) 


MNEMONIC 

OPERANDS 

NO. 
BYTES 

CLOCK 
CYCLES 

OPERATION 

SKIP 
CONDITION 

FLAGS 

CY 

z 

LOGICAL  (CONT.) 

GTAX 

rpa 

2 

11 

A  -  (rpa)  -  1 

No  Borrow 

X 

t 

LTA 

A,  r 

2 

8 

A-  r 

Borrow 

X 

* 

LTA 

r,  A 

2 

8 

r-  A 

Borrow 

X 

* 

LTAX 

rpa 

2 

11 

A  -  (rpa) 

Borrow 

X 

* 

ONA 

A,  r 

2 

8 

A  A  r 

No  Zero 

* 

ONAX 

rpa 

2 

11 

A  A  (rpa) 

No  Zero 

* 

OFFA 

A,  r 

2 

8 

AAr 

Zero 

OFFAX 

rpa 

2 

11 

A  A  (rpa) 

Zero 

* 

NEA 

A,  r 

2 

8 

A-  r 

No  Zero 

X 

NEA 

r,  A 

2 

8 

r-  A 

No  Zero 

X 

NEAX 

rpa 

2 

11 

A  -  (rpa) 

No  Zero 

X 

EQA 

A,r 

2 

8 

A-  r 

Zero 

X 

EQA 

r,  A 

2 

8 

r-  A 

Zero 

X 

EQAX 

rpa 

2 

11 

A  -  (rpa) 

Zero 

X 

IMMEDIATE  DATA  TRANSFER  (ACCUMULATOR) 

XRI 

A,  byte 

2 

7 

A  •*-  A  V  byte 

ADINC 

A,  byte 

2 

7 

A  *-  A  +  byte 

No  Carry 

X 

SUINB 

A,  byte 

2 

7 

A*-  A- byte 

No  Borrow 

X 

ADI 

A,  byte 

2 

7 

A  «-  A  +  byte 

X 

AC  I 

A,  byte 

2 

7 

A  -  A  +  byte  +  CY 

X 

SUI 

A,  byte 

2 

7 

A «-  A  -  byte 

X 

SBI 

A,  byte 

2 

7 

A  <-  A  -  byte  -  CY 

X 

ANI 

A,  byte 

2 

7 

A<-  AAbyte 

OR  I 

A,  byte 

2 

7 

A*- A  V  byte 

GTI 

A,  byte 

2 

7 

A  -  byte  -  1 

No  Borrow 

X 

LTI 

A,  byte 

2 

7 

A  -  byte 

Borrow 

X 

ONI 

A,  byte 

2 

7 

AAbyte 

No  Zero 

OFFI 

A,  byte 

2 

7 

A  A  byte 

Zero 

NEI 

A,  byte 

2 

7 

A  -  byte 

No  Zero 

X 

EQI 

A,  byte 

2 

7 

A  -  byte 

Zero 

X 

4-23 


(JLPD7801/7802 


INSTRUCTION  GROUPS  (CONT.) 


MNEMONIC 

OPERANDS 

NO. 
BYTES 

CLOCK 
CYCLES 

OPERATION 

SKIP 
CONDITION 

FLAGS 

cy|  z 

IMMEDIATE  DATA  TRANSFER 

XRI 

r,  byte 

3 

11 

r «-  r  V  byte 

* 

ADINC 

r,  byte 

3 

11 

r  —  r  +  byte 

No  Carry 

t. 

* 

SUINB 

r,  byte 

3 

11 

r  <-  r  -  byte 

No  Borrow 

t 

ADI 

r,  byte 

3 

11 

r  *-  r  +  byte 

t 

* 

ACI 

r.byte 

3 

11 

r  <-  r  +  byte  +  CY 

t 

* 

SUI 

r,  byte 

3 

11 

r  <-  r  -  byte 

t 

SBI 

r,  byte 

3 

11 

r-r-byte-CY 

t 

* 

AN  I 

r,  byte 

3 

11 

r  *-  r  A  byte 

t 

* 

ORJ 

r,  byte 

3 

11 

r  *~  r  v  byte 

GTI 

r,  byte 

3 

11 

r  -  byte  -  1 

No  Borrow 

t 

LTI 

r,  byte 

3 

11 

r  -  byte 

Borrow 

t 

ONI 

r,  byte 

3 

11 

r  A  byte 

No  Zero 

OFFI 

r,  byte 

3 

11 

r  a  byte 

Zero 

NEI 

r,  byte 

3 

11 

r  -  byte 

No  Zero 

t 

EQI 

r,  byte 

3 

11 

r  -  byte 

Zero 

t 

IMMEDIATE  DATA  TRANSFER  (SPECIAL  REGISTER) 

XRi 

sr2,  byte 

3 

17 

sr2  «~  sr2  V  byte 

ADINC 

sr2,  byte 

3 

17 

sr2  <-  sr2  +  byte 

No  Carry 

t 

SUINB 

sr2,  byte 

3 

17 

sr2  *-  sr2  -  byte 

No  Borrow 

t 

ADI 

sr2,  byte 

3 

17 

sr2  *-  sr2  +  byte 

t 

ACI 

sr2,  byte 

3 

17 

sr2  +-  sr2  +  byte  +  CY 

t 

SUI 

sr2,  byte 

3 

17 

sr2  <-  sr2  -  byte 

t 

SBI 

sr2,  byte 

3 

17 

sr2  *-  sr2  -  byte  -  CY 

t 

AN  I 

sr2,  byte 

3 

17 

sr2  —  sr2  A  byte 

ORI 

sr2,  byte 

3 

17 

sr2  —  sr2  v  byte 

GTI 

sr2,  byte 

3 

14 

sr2  -  byte  -  i 

No  Borrow 

t 

LTI 

sr2,  byte 

3 

14 

sr2  -  byte 

Borrow 

t 

ONI 

sr2,  byte 

3 

14 

sr2A  byte 

No  Zero 

4-24 


(XPD7801/7802 


INSTRUCTION  GROUPS  (CONT.) 


NO. 

CLOCK 

SKIP 

FLAGS 

MNEMONIC 

OPERANDS 

BYTES 

CYCLES 

OPERATION 

CONDITION 

CY 

z 

IMMEDIATE  DATA  TRANSFER  (SPECIAL  REGISTER)  (CONT.) 

OFFI 

sr2,  byte 

3 

14 

sr2  A  byte 

Zero 

NEI 

sr2,  byte 

3 

14 

sr2  -  byte 

No  Zero 

t 

EQI 

sr2,  byte 

3 

14 

sr2  -  byte 

Zero 

X 

WORKING  REGISTER 

XRAW 

wa 

3 

14 

A*- A  V  (V,wa) 

ADDNCW 

wa 

3 

14 

A  *-  A  +  (V,  wa) 

No  Carry 

X 

• 

SUBNBW 

wa 

3 

14 

A^- A  -  (V,  wa) 

No  Borrow 

X 

t 

ADDW 

wa 

3 

14 

A  -  A  +  (V,  wa) 

X 

• 

ADCW 

wa 

3 

14 

A- A  +  (V,wa)  +CY 

X 

* 

SUBW 

wa 

3 

14 

A  -  A  -  (V,  wa) 

X 

SBBW 

wa 

3 

14 

A  -  A  -  (V,  wa)  -  CW 

X 

ANAW 

wa 

3 

14 

A-AA(V,wa) 

« 

ORAW 

wa 

3 

14 

A  «-  A  V(V,  wa) 

* 

GTAW 

wa 

3 

14 

A  «-  (V,  wa)  -  1 

No  Borrow 

X 

• 

LTAW 

wa 

3 

14 

A  -  (V,  wa) 

Borrow 

X 

* 

ONAW 

wa 

3 

14 

A  A  (V,  wa) 

No  Zero 

OFFAW 

wa 

3 

14 

AA(V,  wa) 

Zero 

NEAW 

wa 

3 

14 

A  -  (V,  wa) 

No  Zero 

X 

1 

EQAW 

wa 

3 

14 

A  -  (V,  wa) 

Zero 

X 

ANIW 

wa,  byte 

3 

16 

(V,  wa)  —  (V,  wa)  a  byte 

ORIW 

wa,  byte 

3 

16 

(V,  wa)  <-  (V,  wa)  vbyte 

GTIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte  -  1 

No  Borrow 

X 

LTIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte 

Borrow 

X 

ONIW 

wa,  byte 

3 

13 

(V,  wa)A  byte 

No  Zero 

OFFIW 

wa,  byte 

3 

13 

(V,  wa)A  byte 

Zero 

NEIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte 

No  Zero 

X 

EQIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte 

Zero 

X 

INCREMENT/DECREMENT 

INR 

r2 

1 

4 

r2  <-  r2  +  1 

Carry 

INRW 

,  wa 

2 

13 

(V,  wa)  *-  (V,wa)  +  1 

Carry 

4-25 


^PD7801/7802 


INSTRUCTION  GROUPS  (CONT.) 


MNEMONIC 

OPERANDS 

NO. 
BYTES 

CLOCK 
CYCLES 

OPERATION 

SKIP 
CONDITION 

FLAGS 

CY 

z 

INCREMENT/DECREMENT  (CONT.) 

DCR 

r2 

1 

4 

r2  -  r2  -  1 

Borrow 

1 

DCRW 

wa 

2 

13 

(V,  wa)  *-  (V,  wa)  -  1 

Borrow 

t 

INX 

rp 

1 

7 

rp  —  rp  +  1 

DCX 

rp 

1 

7 

rp  «-  rp  -  1 

DAA 

1 

4 

Decimal  Adjust  Accumulator 

i 

t 

STC 

2 

8 

CY  -  1 

1 

CLC 

2 

8 

CY  -0 

0 

ROTATE  AND  SHIFT 

RLD 

2 

17 

Rotate  Left  Digit 

RRD 

2 

17 

Rotate  Right  Digit 

RAL 

2 

8 

Am  +  1  -  Am,  Ao  -  CY,  CY  «-  A7 

RCL 

2 

8 

Cm  +  1  -  Cm,  Cq  «-  CY,  CY  -  C7 

RAR 

2 

8 

Am  -  1  «-  Am,  A7  -  CY,  CY  «-  A0 

RCR 

2 

8 

Cm  -  1  «-  Cm,  C7  -  CY,  CY  -  Co 

SHAL 

2 

8 

Am  +  1  «-  Am,  Aq  «-  0,  CY  «-  A7 

SHCL 

2 

8 

Cm  +  1  «-  CM,  C0  -  0,  CY  -  C7 

SHAR 

2 

8 

Am  -  1  -  Am,  A7  -  0,  CY  *-  A0 

SHCR 

2 

8 

Cm  -  1  «-  Cm,  C7  *-  0,  CY  *-  Cq 

JUMP 

JMP 

word 

3 

10 

PC  —  word 

JB 

1 

4 

PCh  -  B,  PC|_-C 

JR 

word 

1 

13 

PC  -  PC  +  1  +  jdtspl 

JRE 

word 

2 

13 

PC     PC  +  2  +  jdisp 

CALL 

CALL 

word 

3 

16 

(SP-1)^(PC-3)H,(SP-2)«- 
(PC-3)|_,  PC  ^  word 

CALB 

1 

13 

(SP  -  1)«-(PC-  Dh.  (SP-2)«- 
(PC-  1)l,PCh  *-B,PCL^C 

CALF 

word 

2 

16 

(SP-1  MPC-2)H.  (SP-2)-(PC-2)L 
PC15-  11  <- 00001,  PC10~0<- fa 

CALT 

word 

1 

19 

(SP-1  MPC-1  )H,(SP-2)-(PC-1 )  L 
PCL*-(128-2ta),  PCH^(129+2ta) 

SOFTI 

1 

19 

(SP  -  1 )  -  PSW,  SP  -  2,  (SP  -  3)  <-  PC 
PC^-0060h,  SIRQ^  1 

4-26 


(XPD7801/7802 


INSTRUCTION  GROUPS  (CONT.) 


NO. 

CLOCK 

SKIP 

FLAGS 

MNEMONIC 

OPERANDS 

BYTES 

CYCLES 

OPERATION 

CONDITION 

CY 

Z 

RETURN 

RET 

1 

11 

PC|_  *-  (SP),  PCh  *-  (SP  +  1) 
SP  -  SP  -  2 

RETS 

1 

11+a 

PCL<-  (SP),PCh  *-  (SP  +  1). 
SP  «-  SP  +  2,  PC  *-  PC  +  n 

RETI 

1 

15 

PC|_-  (SP),PCH  *-  <SP  +  1 ) 
PSWHSP+2),SP-SP+3,SIRQ-0 

SKIP 

BIT 

bit,  wa 

2 

10 

Bit  test 

(V,  wa)bit 
=  1> 

SKC 

2 

8 

Skip  if  Carry 

CY  =  1 

SKNC 

2 

8 

Skip  if  No  Carry 

CY  =0 

SKZ 

2 

8 

Skip  if  Zero 

Z  =  1 

SKNZ 

2 

8 

Skip  if  No  Zero 

Z  =  0 

SKIT 

f 

2 

8 

Skip  if  INT  X  =  1, 
then  reset  INT  X 

f  =  1 

SKNIT 

f 

2 

8 

Skip  if  No  INT  X 
otherwise  reset  INT  X 

f  =  0 

CPU  CONTROL 

NOP 

1 

4 

No  Operation 

El 

2 

8 

Enable  Interrupt 

Dl 

2 

8 

Disable  Interrupt 

HLT 

1 

6 

Halt 

SERIAL  PORT  CONTROL 

SIO 

1 

4 

Start  (Trigger)  Serial  I/O 

STM 

1 

4 

Start  Timer 

INPUT/OUTPUT 

IN 

byte 

2 

10 

ABi5-8-B,AB743^byte 
A-DB7.0 

OUT 

byte 

2 

10 

AB15.8  *~  B.AB7<>  -  byte 
DB7.0-A 

PEX 

2 

11 

PE15.g-B,  PE7-0^C 

PEN 

2 

11 

PE15.12*-B7^ 

PER 

2 

11 

Port  E  AB  Mode 

4-27 


|xPD7801/7802 


Program  Status  Word  (PSW)  Operation 


OPERATION 

D6 

D5 

D4 

D3 

D2 

DO 

REG,  MEMORY 

IMMEDIATE 

SKIP 

Z 

SK 

HC 

L1 

LO 

CY 

ADD 
ADC 
SUB 
SBB 

ADDW 
ADCW 
SUBW 
SBBW 

ADDX 
ADCX 
SUBX 
SBBX 

ADI 
ACI 
SUI 
SBI 

t 

0 

t 

0 

0 

t 

ANA 
ORA 
XRA 

ANAW 
ORAW 
XRAW 

ANAX 
ORAX 
XRAX 

ANI 
OR  I 
XRI 

ANIW 
OR  IW 

t 

0 

• 

0 

0 

• 

ADDNC 
SUBNB 
GTA 
LTA 

ADDNCW 
SUBNBW 
GTAW 
LTAW 

ADDNCX 
SUBNBX 
GTAX 
LTAX 

ADINC 
SUINB 
GTI 
LTI 

GTIW 
LTIW 

$ 

$ 

0 

0 

t 

ONA 
OFFA 

ONAW 
OFFAW 

ONAX 
OFFAX 

ON  I 
OFFI 

ONIW 
OFFIW 

t 

$ 

• 

0 

0 

• 

NEA 
EQA 

NEAW 
EQAW 

NEAX 
EQAX 

NEI 
EQI 

NEIW 
EQIW 

I 

I 

t 

o 

o 

t 

INR 
DCR 

INRW 
DCRW 

t 

t 

t 

0 

0 

• 

DAA 

t 

0 

t 

0 

0 

t 

RAL,  RAR,  RCL,  RCR 
SHAL,  SHAR,  SHCL,  SHCR 

0 

0 

0 

t 

RLD,  RRD 

• 

0 

0 

0 

• 

STC 

0 

• 

0 

0 

1 

CLC 

0 

0 

0 

0 

MVI  A,  byte 

0 

1 

0 

• 

MVI  L,  byte 
LXI  H,  word 

o 

0 

BIT 

SKC 

SKNC 

SKZ 

SKNZ 

SKIT 

SKNIT 

• 

$ 

• 

0 

0 

• 

RETS 

• 

1 

• 

0 

0 

• 

All  other  instructions 

• 

0 

• 

0 

0 

• 

t  Flag  affected  according  to  result  of  operation 

1  Flag  set 

0  Flag  reset 

•  Flag  not  affected 


4-28 


U.PD7801/7802 


ABSOLUTE  MAXIMUM    Operating  Temperature 
RATINGS*    Storage  Temperature  .  , 
Voltage  On  Any  Pin  .  . 

Ta  =  25°  C 

*COMMENT  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


.  -10°Cto+70°C 
-65°Cto  +150°C 
,  .-0.3V  to+7.0V 


DC  CH AR ACTE RISTICS  ~10°c  to  +70°c,  vcc  =  +s.ov  ±  10% 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Low  Voltage 

V|L 

0 

0.8 

V 

Input  High  Voltage 

V|H1 

2.0 

vCc 

V 

Except  SCK,  X1 

V|H2 

3.8 

vCc 

V 

SCK,  X1 

Output  Low  Voltage 

vol 

0.45 

V 

Iql  =  2.0  mA 

Output  High  Voltage 

vom 

2.4 

V 

•oh  =  -100  MA 

vOH2 

2.0 

V 

I  OH  =-500  juA 

Low  Level  Input  Leakage  Current 

ILIL 

-10 

ma 

V,N=0V 

High  Level  Input  Leakage  Current 

•lih 

10 

ma 

V|N  =  Vcc 

Low  Level  Output  Leakage  Current 

•lol 

-10 

ma 

V0UT  =  0.45V 

High  Level  Output  Leakage  Current 

'loh 

10 

ma 

VQUT  =  VCC 

Vcc  Power  Supply  Current 

•cc 

110 

200 

mA 

CAPACITANCE   Ta  =  25°C,VCC  =  GND  =  0V 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Capacitance 

C| 

10 

PF 

fc  =  1  MHz 
All  pins  not 
under  test  at  0V 

Output  Capacitance 

c0 

20 

PF 

Input/Output  Capacitance 

C|0 

20 

PF 

4-29 


MPD7801/7802 


-io°cto+7o°cf  vCc  =  +5.ov±  10%  AC  CHARACTERISTICS 

CLOCK  TIMING 


LIMITS 

TEST 

PARAMETER 

SYMBOL 

MIN 

MAX 

UNITS 

CONDI  l  lOIMo 

XI  Input  Cycle  Time 

*CYX 

227 

1000 

ns 

X1  Input  Low  Level 
Width 

tXXL 

106 

X1  Input  High  Level 
Width 

tXXH 

106 

ns 

0OUT  Cycle  Time 

454 

2000 

ns 

0OUT  Low  Level  Width 

*00L 

150 

ns 

0OUT  HiQh  Level  Width 

t00H 

150 

ns 

0OUT  Rise/Fall  Time 

tr,tf 

40 

ns 

READ/WRITE  OPERATION 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

MAX 

RD"  L.E.  -*•  </>OUT  L.E. 

tR0' 

100 

ns 

tCY«/>.-  500  ns 

Address  (PEq-15)  -+  Data 
Input 

tAD1 

550  +  500  x  N 

ns 

R~D~T.E.  -+  Address 

tRA 

200(T3);  700(T4) 

ns 

RD~L.E.-»-  Data  Input 

tRD 

350  +  500  x  N 

ns 

~R~D"T.E.  -*  Data  Hold 
Time 

tRDH 

0 

ns 

WD"  Low  Level  Width 

tRR 

850  +  500  x  N 

ns 

WD"L.E.-*VVATf  L.E. 

tRWT 

450 

ns 

Address  (PE0-15)  -* 
WAIT  L.E. 

tAWT1 

ODU 

ns 

WAIT  Set  Up  Time 
(Referenced  from 
</>OUT  L.E.) 

tWTS 

290 

ns 

WAIT  Hold  Time 
(Referenced  from 
0OUT  L.E.) 

tWTH 

0 

120 

ns 

M1     RD~  L.E. 

*MR 

200 

ns 

RD"T.E.-*M1 

tRM 

200 

ns 

I0/M*-*R7J  L.E. 

t|R 

200 

ns 

RD"T.E.->  IO/M 

tRI 

200 

ns 

0OUT  L.E.-*WR  L.E. 

t0W 

40 

125 

ns 

Address  (PEq-1  5)  -*• 
0OUT  T-E- 

*A0 

100 

ns 

Address  (PE0-15)-* 
Data  Output 

tAD2 

450 

ns 

Data  Output  -+  WR 
T.E, 

tDW 

600  +  500  x  N 

ns 

"WR  T.E.  -» Data 
Stabilization  Time 

tWD 

150 

ns 

Address  (PEo-15)"* 
WR  L.E. 

tAW 

400 

ns 

WH  T.E.  -  Address 
Stabilization  Time 

tWA 

200 

ns 

WR  Low  Level  Width 

tww 

600  +  500  x  N 

ns 

IO/T-W&L.E. 

t|W 

500 

ns 

twi 

250 

ns 

4-30 


U.PD7801/7802 

AC  CHARACTERISTICS 
(CONT.) 

SERIAL  I/O  OPERATION 


PARAMETER 

SYMBOL 

MIN 

MAX 

UNIT 

CONDITION 

SCK  Cycle  Time 

tCYK 

800 

ns 

SCK  Input 

900 

4000 

ns 

bCls.  Uutput 

SCK  Low  Level  Width 

tKKL 

350 

epK  Innnt 
o v> rx  iiipui 

400 

ns 

SCK  Output 

oL.lv.  nign  Level  wiotn 

tKKH 

350 

ns 

SCK  Input 

400 

ns 

SCK  Output 

SI  Set-Up  Time  (referenced  from  SCK  T.E.) 

tsis 

80 

ns 

SI  Hold  Time  (referenced  from  SCK  T.E.) 

tSIH 

260 

ns 

1SCK"  L.E.    SO  Delay  Time 

tKO 

180 

ns 

S5S~High     SCK  L.E. 

tCSK 

100 

ns 

SCKT.E.-*SCS  Low 

tKCS 

100 

ns 

SCK  T.E.-*  SAK  Low 

tKSA 

260 

ns 

HOLD  OPERATION 

PARAMETER 

SYMBOL 

MIN 

MAX 

UNIT 

CONDITION 

HOLD  Set-Up  Time  (referenced  from 

tHDSi 

200 

ns 

0OUT  L.E.) 

tHDS2 

200 

ns 

HOLD  Hold  Time  (referenced  from  0OUT 
L.E.) 

tHDH 

0 

ns 

tCYtf>  =  500  ns 

0OUT  L.E.  -+  HLDA 

x  DHA 

110 

100 

ns 

HLDA  High  -»•  Bus  Floating  (High  Z  State) 

tHABF 

-150 

150 

ns 

HLDA  Low-*  Bus  Enable 

tHABE 

350 

ns 

Notes : 

(T)  AC  Signal  waveform  (unless  otherwise  specified) 


MEASURING  20 
POINTS      "<^-^  08 


(2)  Output  Timing  is  measured  with  1  TTL  +  200  pF  measuring  points  are  Vqh  =  2.0V 

VOL  =  0.8V 

(3)  L.E.  =  Leading  Edge,  T.E.  =  Trailing  Edge 


4-31 


HPD7801/7802 


DEPENDENT  AC  PARAMETERS  AC  CHARACTERISTICS 


PARAMETER 

EQUATION 

M  IN /MAX 

UNIT 

tR0 

(1/5) T 

MIN 

ns 

tAD-j 

(3/2  +  N)T-  200 

MAX 

ns 

tRA  <T3> 

(1/2)  T-  50 

MIN 

ns 

tRA  (T4) 

(3/2)  T  -  50 

MIN 

ns 

tRD 

(1  +  N)T-  150 

MAX 

ns 

*RR 

(2  +  N)T-  150 

MIN 

ns 

lRWT 

(3/2)  T-  300 

MAX 

ns 

tAWT-, 

(2)T-  350 

MAX 

ns 

*MR 

(1/2)  T-  50 

MIN 

ns 

tRM 

(1/2)  T-  50 

MIN 

ns 

*IR 

(1/2)  T-  50 

MIN 

ns 

tRI 

(1/2)  T-  50 

MIN 

ns 

t0W 

(1/4)  T 

MAX 

ns 

tA0 

(1/5)  T 

MIN 

ns 

tAD2 

T-  50 

MIN 

ns 

tDW 

(3/2+ N)T-  150 

MIN 

ns 

%D 

(1/2)  T-  100 

MIN 

ns 

lAW 

T-  100 

MIN 

ns 

%A 

(1/2)  T-  50 

MIN 

ns 

tWW 

(3/2  +  N)T-  150 

MIN 

ns 

tiw 

T 

MIN 

ns 

*WI 

(1/2)  T 

MIN 

ns 

tHABE 

(1/2)  T-  150 

MAX 

ns 

(CONT.) 


Notes:  ©  N  =  Number  of  Wait  States 

©  T  =  tCY0 

(3)  Only  above  parameters  are  tQY^  dependent 

@  When  a  crystal  frequency  other  than  4  MHz  is  used  (tQY^  "  500  ns) 
the  above  equations  can  be  used  to  calculate  AC  parameter 
values. 


CLOCK  TIMING 


TIMING  WAVEFORMS 


4-32 


(XPD7801/7802 


TIMING  WAVEFORMS 
(CONT.) 


V 


READ  OPERATION 


*OUT 
PE0  15 
°0~7 


J  L 


J  \  /  \  7 


WRITE  OPERATION 


~\  /      \      /  v  / 


015ZDC 


•ACTIVE  ONLY  WHEN  IO/»S  IS  ENABLED 


4-33 


(xPD7801/7802 


SERIAL  I/O  OPERATION 


-»tslS»"-»tSIH*- 


TIMING  WAVEFORMS 
(CONT.) 


HOLD  OPERATION 


ft 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 


Plastic  Quil,  jxPD7801G/02G 

Plastic  Shrinkdip,  lcPD7801CW  liPD7802CW 


4-34 


7801/7802DS-REV2-7-83-CAT-W 


SEC 


|iPD78C06/|xPD78C05 
CMOS  HIGH-END  8-BIT 
SINGLE-CHIP  MICROCOMPUTER 


Description 

The  NEC  ^PD78C06/jjlPD78C05  are  advanced  CMOS 
8-bit  general  purpose  single-chip  microcomputers  intended 
for  applications  requiring  8-bit  microprocessor  control  and 
extremely  low  power  consumption,  and  ideally  suited  for 
portable,  battery-powered/backedup  products.  Subsets  of 
the  ^PD7801,  the  |xPD78C06/05  integrate  an  8-bit  ALU, 
4K-ROM,  128-byte  RAM,  46  I/O  lines,  an  8-bit  timer,  and  a 
serial  I/O  port  on  a  single  die.  Fully  compatible  with  the 
8080A  bus  structure,  expanded  system  operation  can 
easily  be  implemented  using  industry  standard  peripheral 
and  memory  components.  Total  memory  space  can  be 
increased  to  64K-bytes. 

The  jjiPD78C06/05  lend  themselves  well  to  low  power, 
portable  applications  by  featuring  two  power  down  modes 
to  further  conserve  power  when  the  processor  is  not  active. 
The  fjiPD78C06  is  packaged  in  a  64-pin  flat  pack.  The 
|xPD78C05  is  a  ROM-less  version  packaged  in  a  64-pin 
QUIL,  designed  for  prototype  development  and  small 
volume  production. 
Features 

□  CMOS  silicon  gate  technology  +  5V  supply 

□  Complete  single-chip  microcomputer 

-  8-bit  ALU 
-4K-ROM 
-128-Byte  RAM 

□  Low  power  consumption 

□  46  I/O  lines 

□  Expansion  capabilities 

-  8080A  bus-compatible 

-  60K-byte  external  memory  address  range 

□  Serial  I/O  port 

□  101  instruction  set 

-  Multiple  address  modes 

□  Power-down  modes 

-  Halt  mode 

-  Stop  mode 

□  8-bit  timer 

□  Prioritized  interrupt  structure 

-  2  external 
- 1  internal 

□  On-chip  clock  generator 

□  64-pin  flat  pack 

□  ROM-less  version  available  (78C05) 
Pin  Identification 


Pin  Configuration 


Symbol 

Name 

PA7-PAo,  PB7-PB0,  PCS-PC0)  PE15-PE0 

I/O  Ports 

DB7-DB0 

Data  Bus 

WAIT 

Wait  Request 

INT„,  INT, 

Interrupt  Request 

X2,  X, 

Crystal 

SCK 

Serial  Clock  Input/Output 

SI 

Serial  Input 

SO 

Serial  Output 

RESET 

Reset 

RD 

Read  Strobe 

WR 

Write  Strobe 

<i>OUT 

Clock  Output 

AB15  «= 

1 

64 

=3  Vcc 

4>0UT  1 

2 

63 

 ■  AB14 

DB7  = 

3 

62 

=  AB13 

DB6  = 

4 

61 

DB5  e 

5 

60 

DB4t  : 

6 

59 

DB,  t= 

7 

58 

DR3z,  

8 

57 

 1  AB8 

DB,  c 

9 

56 

3  AB7 

DB0c= 

10 

55 

=  AB6 

N.C.  <= 

11 

54 

=  AB5 

12 

53 

=JAB4 

INT0  <= 

13 

52 

=3  AB3 

WAITC= 

14 

51 

==3  AB2 

M,  c 

15 

50 

=3  AB, 

WR  e= 
RD  C 

16 
17 

p.PD7aC05 

49 
48 

=  AB0 
=3  PB7 

PC5c= 

18 

47 

=  PB6 

PC4  E 

19 

46 

=3  PB5 

PC3c== 

20 

45 

=>PB4 

pc2  c 

21 

44 

=3  PB3 

PC,  ■  

22 

43 

=3PB2 

PC0  «= 

23 

42 

=3  PB, 

RELc= 

24 

41 

=JPB0 

TO  C= 

25 

40 

=3  PA7 

SCKC= 

26 

39 

=  PA6 

SI  C 

27 

38 

=3  PA5 

SO  1  

28 

37 

RESET  cq 

29 

36 

=3  PA3 

X2I= 

30 

35 

 1  PA2 

X1  C 

31 

34 

=  PA, 

vss«=: 

32 

33 

=3  PA0 

REV/1 
4-35 


|xPD78C06/78C05 

Block  Diagram 


X1O- 


1NT10- 


Standby 
Control  L*. 


Interrupt 
Control 


Serial 
Clock 


Latch 

INC/DEC 

PC 

SP 

A 

B 

C 

D 

E 

H 

L 

Buffer 

Internal  Data  Bus 


Mode  B 


3£ 


16      >  PEl5-0/AB15.0 


Program 
Memory 
(4K-byte) 
78C06 


8 


P<A>Sl\A>DB7-' 


Inst.  Reg. 


Instruction 
Decoder 


Read/Write 
Control 


Timing 
Control 


System  Control 


iririr  i  i  1  i  1  i  1 


Reset  <t>Out 


VCC  vss 


Table  1.  Halt  and  Stop  Modes 


Function 

Halt  Mode 

Stop  Mode 

Oscillator 

Run 

Internal  System  Clock 

Stop 

Stop 

Timer 

Run 

Timer  Register 

Hold 

Set 

Upcounter,  Prescaler  0, 1 

Run 

Cleared 

Serial  Interface 

Run  © 

Serial  Clock 

Hold 

Hold 

Interrupt  Control  Circuit 

Run 

Stop 

Interrupt  Enable  Flag 

Hold 

Reset 

INT0,  INT,  Input 

Inactive 

INTT 

Active 

T8(INTFS) 

Mask  Register 

Set 

Pending  Interrupts  (INTFX) 

  Hold 

Reset 

REL  Input 

Inactive 

RESET  Input 

Active 

  Active 

Function 

Halt  Mode 

Stop  Mode 

On-chip  RAM 

Output  Latch  in  Ports  A,  B,  E 

Hold 

Program  Counter  (PC) 

Cleared 

Stack  Pointer  (SP) 

General  Registers 

Unknown 

(A,  B,  C,  D,  E,  F,  L) 

Program  Status  Word  (PSW) 

Hold 

Reset 

Mode  B  Register 

Standby  Control  Register  (SC0-SC3) 

Hold 

Standby  Control  Register  (SC4) 

Set 

Timer  Mode  Register  (TMMq-TMM,) 

Hold 

Timer  Mode  Register  (TMM^ 

Set 

Serial  Mode  Register  (SM) 

Hold 

Data  Bus  (DB0-DB7) 

High-Z 

High-Z 

RD,  WR  Output 

High 

High 

Note:  ©  Serial  clock  counter  is  running  and  T8 1 
from  it 

s  generated,  however,  there  a 

e  no  effects 

4 


-36 


Functional  Description 
Memory  map 

The  |jlPD78C06  can  directly  address  up  to  64K  bytes  of 
memory.  Except  for  the  on-chip  ROM  (0-4,095)  and  RAM 
65,408-65,535),  any  memory  location  can  be  used  as 


,  PD78C06  78C05 

either  ROM  or  RAM.  The  following  memory  map  defines 
the  0-64K-byte  memory  space  for  the  |jlPD78C06  showing 
that  the  Reset  Start  Address,  Interrupt  Start  Address,  Call 
Tables,  etc.,  are  located  in  the  internal  ROM  area. 


4,095 
4,096 


65,279 
65,280 


65,407 
65,408 


Internal  ROM 
4,096  x  8 


External 
Memory 
61,312  x  8 


Internal  RAM 
128  x  8 


Reset/Stop  Release 


Low  Address 


Low  Address 


High  Address 


I/O  Ports 


Port 

Functions 

Port  A 

8-bit  output  port  with  latch 

PortB 

8-bit  programmable  Input/Output  port  with  latch 

PortC 

6-bit  nibble  I/O  or  Control  port 

Port  E 

16-bit  Address/Output  port 

Port  A.  Port  A  is  an  8-bit  latched  output  port.  Data  can  be 
readily  transferred  between  the  accumulator  and  the  output 
latch  buffers.  The  contents  of  the  output  latches  can  be 
modified  using  arithmetic  and  logic  instructions.  Data 
remains  latched  at  Port  A  unless  acted  on  by  another  Port  A 
instruction  or  a  RESET  is  issued. 
Port  B.  Port  B  is  an  8-bit  I/O  port.  Data  is  latched  at  Port  B 
in  both  the  Input  or  Output  mode.  Each  bit  of  Port  B  can  be 
independently  set  to  either  Input  or  Output  modes.  The 
Mode  B  register  programs  the  individual  lines  of  Port  B  to 
be  either  an  Input  (Mode  Bn  = .,)  or  an  Output  (Mode  Bn=0) 
Port  C.  Port  C  is  a  6-bit  I/O  port  with  internal  pull-up 
resistors. 


Port  E  (78C06).  Port  E  is  a  16-bit  address  bus/output  port. 
It  can  be  set  to  one  of  two  operating  modes  using  the  PER 
or  PEX  instruction. 

□  1 6-bit  address  bus  —  the  PER  instruction  sets  this 
mode  for  use  with  external  I/O  or  memory  expansion 
(up  to  60K  bytes,  externally). 

□  16-bit  output  port  —  the  PEX  instruction  sets  Port  E  to 
a  16-bit  output  port.  The  contents  of  B  and  C  registers 
appear  on  PE8-PE15  and  PE0-PE-,,  respectively. 

Address  bus  AB15-AB0  (78C05) 
These  lines  are  the  16  bit-to-bit  address  bus  to  the  main 
memory.  The  78C05,  having  no  internal  ROM,  must 
address  the  area  from  0  to  4096  as  external  ROM. 
The  78C05  AB  lines  are  unlike  the  78C06  PE  lines  in  that 
they  have  no  internal  latches.  When  the  Port  E  output 
instruction  PEX  is  executed  in  a  78C05,  the  register  pair 
BC  is  output  to  the  AB  lines  for  only  one  clock  cycle  during 
the  third  machine  cycle.  This  is  provided  to  allow  external 
hardware  to  emulate  the  Port  E  operation  of  the  78C06. 


4-37 


|PD78C06  78C05 

Functional  Description  (Cont.) 


<  PEX  Instruction  ^ 

I  -r 1  "7"  1  "7"  1  "7-  1 " V- 1  "7"  1  "7" 1  "7"  1  "7"  1  "7-'  "r 1  " 1 
M  j  \  

AB~y  1st  Byte  Fetch  X  2nd  Byte  Fetch  X        BC  X 


Timer  Block  Diagram 


INSTRUCTION- 


Prescaler  0 
(4) 


V 


Prescaler  1 

(3) 


System  Clock  =  Oscillation  Frequency  x  1/4 


Upcounter 
(8) 

3E 

Comparator 
(8) 

~TT 

Timer  Rec 
(8) 

~?T~ 


Timer  operation 

A  programmable  8-bit  timer  is  provided  on-chip  for 
measuring  time  intervals,  generating  pulses,  and  general 
time-related  control  functions.  It  is  capable  of  measuring 
time  intervals  from  8|uls  to  32ms  in  duration.  The  timer  con- 
sists of  a  prescaler  which  decrements  an  8-bit  counter  at  a 
fixed  8|jls  or  128fxs  rate.  Count  pulses  are  loaded  into  the 
8-bit  upcounter  through  the  timer  register. 
Countup  operation  is  initiated  upon  execution  of  the  STM 
instruction  when  the  contents  of  the  upcounter  are  fully 


incremented  and  a  coincidence  occurs,  an  interval  interrupt 
(INTT)  is  generated.  Count  operation  may  be  reinitialized 
with  the  STM  instruction.  The  duration  of  the  timeout  may 
be  altered  by  loading  new  contents  into  the  timer  register. 
The  timer  flip-flop  is  set  by  the  STM  instruction  and  reset 
on  a  countup  operation.  Its  output  (T0)  is  available  exter- 
nally and  may  be  used  for  general  external 
synchronization. 

Timer  interrupt  (INTT)  may  be  disabled  through 
the  interrupt. 


Serial  Port  Block  Diagram 


Slo  O- 


Serial  Register  (S/P  Conversion) 
LSB   »  1,1  1  III  MSB 


T8  (INTS) 


4-38 


|iPD78C06  78C05 


Functional  Description  (Cont.) 

Serial  port  operation 

The  on-chip  serial  port  provides  basic  synchronous  serial 
communication  functions  allowing  the  NEC  |jlPD78C06/05 
to  serially  interface  with  external  devices. 
Serial  transfers  are  synchronized  with  either  the  internal 
clock  or  an  external  clock  input  (SCK).  The  transfer  rate  is 
fixed  at  0.5  Mbit/second  if  the  internal  clock  is  used  or  is 
variable  between  DC  and  0.5  Mbit/second  when  an  exter- 
nal clock  is  used.  The  Clock  Source  Select  is  determined 
by  the  Mode  C  register.  The  serial  clock  (internal  or  exter- 
nal  SCK)  is  enabled  when  the  Serial  Chip  Select  signal 
(SCS)  goes  low.  At  this  time  receive  and  transmit  opera- 
tions through  the  Serial  Input  port  (Sl)/Serial  Output  port 
(SO)  are  enabled.  Receive  and  transmit  operations  are 
performed  MSB  first. 

Interrupt  structure 

The  |jlPD78C06/05  provide  a  maskable  interrupt 
structure  capable  of  handling  vectored  prioritized 
interrupts.  Interrupts  can  be  generated  from  six  different 
sources:  two  external  interrupts,  two  internal  interrupts, 
and  nonmaskable  software  interrupt.  When  activated,  each 
interrupt   branches   to   a  designated   memory  vch 
interrupt  branches  to  a  designated  memory  vector  location 
for  that  interrupt. 

Interrupt  Structure 


INT 

Vectored  Memory 
Location 

Priority 

Type 

INTT 

8 

3 

Internal,  Timer 
Overflow 

INT0 

4 

2 

External,  level  sensitive 

INT, 

16 

4 

External,  Rising  edge 
sensitive 

RESET  (Reset) 

An  active-low  signal  on  this  input  for  more  than  4|jls  forces 
the  |jlPD780C06/05  into  a  Reset  condition.  RESET  affects 
the  following  internal  functions: 

□  The  Interrupt  Enable  flags  are  reset,  and  interrupts 
are  inhibited. 

□  The  Interrupt  Request  flag  is  reset. 

□  The  Halt  flip-flop  is  reset,  and  the  Halt  state  is  released. 

□  The  contents  of  the  Mode  B  register  are  set  to  FFH,  and 
Port  B  becomes  an  input  port. 

□  All  flags  are  reset  to  0. 

□  The  internal  Count  register  for  timer  operation  is  set  to 
FFH  and  the  timer  F/F  is  reset. 

□  The  contents  of  the  program  counter  are  set  to  0000H. 

□  Data  bus  (DB0-DB7),  RD,  and  WR  go  to  a  high  imped- 
ance state. 

Once  the  RESET  input  goes  high,  the  program  is  started  at 

location  0000H. 

Registers 

The  |xPD78C06/05  contain  seven  8-bit  registers  and  two 
16-bit  registers. 


General  purpose  registers.  The  general  purpose  regis- 
ters A,  B,  C,  D,  E,  H,  L,  can  function  as  auxiliary  registers  to 
the  accumulator  or  in  pairs  as  data  pointers  (BC,  DE,  HL). 
Automatic  increment  and  decrement  addressing  mode 
capabilities  extend  the  uses  for  the  DE  and  HL  regis- 
ter pairs. 

Accumulator  (A) 

All  data  transfers  between  the  |jlPD78C06/05  and  external 
memory  or  I/O  are  done  through  the  accumulator. 
Program  counter  (PC) 

The  PC  is  a  16-bit  register  containing  the  address  of  the 
next  instruction  to  be  fetched.  Under  normal  program  flow, 
the  PC  is  automatically  incremented.  However,  in  the  case 
of  a  branch  instruction,  the  PC  contents  are  from  another 
register  or  an  instruction's  immediate  data.  A  reset  sets  the 
PC  to  0000H. 
Stack  pointer  (SP) 

The  stack  pointer  is  a  16-bit  register  used  to  maintain  the 
top  of  the  stack  area  (last-in/first-out).  The  contents  of  the 
SP  are  decremented  during  a  Call  or  Push  instruction  or  if 
an  interrupt  occurs.  The  SP  is  incremented  during  a  Return 
or  POP  instruction. 


Address  Modes 

Register  addressing 
Register  indirect 

addressing 
Automatic  increment 

addressing 
Automatic  decrement 

addressing 

Register  addressing 


Working-register 

addressing 
Direct  addressing 
Immediate  addressing 
Immediate  extended 

addressing 


Opcode 

Operand 

The  instruction  opcode  specifies  a  register  r  which  contains 
the  operand. 

Register  indirect  addressing 


Opcode 

Address 

Operand 

The  instruction  opcode  specifies  a  register  pair  which  con- 
tains the  memory  address  of  the  operand.  Mnemonics  with 
an  X  suffix  are  ending  this  address  mode. 


4-39 


PLPD78C06/78C05 

Address  Modes  (Cont.) 

Automatic  increment  addressing 


— I — 
—0 

The  opcode  specifies  a  register  pair  which  contains  the 
memory  address  of  the  operand.  The  contents  of  the  regis- 
ter pair  are  automatically  incremented  to  point  to  a  new 
operand.  This  mode  provides  automatic  sequential  step- 
ping when  working  with  a  table  of  operands. 

Automatic  decrement  addressing 

Memory 


5 


Working-register  addressing 


PC  +  1  Displacement 


Memory 


J 


The  contents  of  the  register  are  linked  with  the  byte  follow- 
ing the  opcode  to  form  a  memory  address  which  contains 
the  operand.  The  V  register  is  used  to  indicate  the  mem- 
ory page.  This  address  mode  is  useful  as  a  short-offset 
address  mode  when  working  with  operands  in  a  common 
memory  page  where  only  one  additional  byte  is  required 
for  the  address.  Mnemonics  with  a  W  suffix  indicate 
this  address  mode.  In  the  78C06/05  the  V  register  is 
always  FFH. 

Direct  addressing 


PC 

Opcode 

PC  +  1 

Low  Address 

PC  +  2 

High  Address 

Memory 


Opcode 


2  Bytes 

The  two  bytes  following  the  opcode  specify  an  address  of  a 
location  containing  the  operand. 

Immediate  addressing 

PC 

PC  +  1 

immediate  extended  addressing 

PC 

PC  +  1' 
PC  +  2 


Low  Operand 


Instruction  Set  Definitions 


Operand 

Description 

r 

A,  B,  C,  D,  E,  H,  L 

li 

B,  C,  D,  E,  H,  L 

r2 

A,  B,  C 

sr 

PA,  PB,  PC,  MK,  MB,  TM0, 
SM,  SC 

TM1s  S, 

sr1 

PA,  PB,  PC,  MK,  S,  TM0,  TMt 

,  SC 

sr2 

PA,  PB,  PC,  MK 

rp 

SP,  B,  D,  H 

rP1 

B,  D,  H 

rpa 

B,  D,  H,D  +  ,H  +  ,D-,H- 

wa 

8-bit  immediate  data 

word 

16-bit  immediate  data 

byte 

8-bit  immediate  data 

bit 

3-bit  immediate  data 

if 

F0,1,FT,FS 

F 

CY,  Z 

Notes:  1 .  When  special  register  operands  sr,  sr1 ,  sr2  are  used,  PA  = 
Port  A,  PB  =  Port  B,  PC  =  Port  C,  MK  =  Mask  register, 
MB  =  Mode  B  register,  MC  =  Mode  C  Register,  TM0  = 
Timer  register  0,  TM-i  =  Timer  register  1 ,  S  =  Serial  register. 

2.  When  register  pair  operands  rp,  rp1  are  used,  SP  =  Stack 
Pointer,  B  =  BC,  D  =  DE,  H  =  HL. 

3.  Operands  rPa,  rPal ,  wa  are  used  in  indirect  addressing  and 
auto-increment/auto-decrement  addressing  modes. 

B  =  (BC),  D  =  (DE),  H  =  (HL) 

D+  =  (DE)  +  ,H+  =  (HL)  +  ,D-  =  (DE)-.H-  =  (HL)-. 

4.  When  the  interrupt  operand  if  is  used,  F0  =  INTFO,  F1  = 
INTF1,  FT  =  INTFT,  FS  =  INTFS. 

5.  When  the  operand  F  is  used,  CY  =  Carry  and  Z  =  Zero. 

6.  The  V  register  is  always  FFHex. 


Instruction  Set 


Mnemonic  Operand 


No.  Clock 
Bytes  Cycles 


Skip 


Condition  CY  Z 


8-bit  Data  Transfer 


MOV 

r1,A 

1 

6 

r1  <- A 

MOV 

A,  r1 

1 

6 

A*-r1 

MOV 

sr,  A 

2 

14 

sr*-A 

MOV 

A,  sr1 

2 

14 

A<-sr1 

MOV 

r,  word 

4 

25 

r  <-  (word) 

MOV 

word,  r 

4 

25 

(word)  *-  r 

MVI 

r,  byte 

2 

11 

r  <-  byte 

STAW 

wa 

2 

14 

(V,  wa) «-  A 

LOAW 

wa 

2 

14 

A «-  (V,  wa) 

STAX 

rpa 

1 

39 

(rpa)<-A 

LOAX 

rpa 

1 

9 

A^(rpa) 

16-bit  Data  Transfer 

SBCD 

word 

4 

28 

(word)  *-  C,  (word  +  1) «-  B 

SDEO 

word 

4 

28 

(word) «-  E,  (word  +  1)^D 

SHLD 

word 

4 

28 

(word)  <-  L,  (word  +  1)*-H 

SSPD 

word 

4 

28 

(word)  «-  SPL> 
(word  +  1)^-SPH 

LBCD 

word 

4 

28 

C «-  (word),       (word  +  1) 

LDED 

word 

4 

28 

E «-  (word),  D «-  (word  +  1 ) 

LHLD 

word 

4 

28 

L «-  (word),  H  «—  (word  +  1) 

LSPD 

word 

4 

28 

SPL-(word), 
SPH<-(word  +  1) 

PUSH 

rpl 

2 

21 

(SP  -  1)«-rp1„, 
(SP-2)«-rp1L 

POP 

rp1 

2 

18 

rP1L^-(SP) 
rp1H«-(SP  +  n 
SP^SP  +  2 

LXI 

rp,  word 

3 

16 

rp«-word 

4-40 


Instruction  Set  (Cont.) 


No. 

Clock 

Skip 
Condition 

Flags 

Mnemonic 

i  Operand  Bytes  Cycles 

Operation 

CY  Z 

Arithmetic 

ADD 

A,  r 

2 

12 

A-A  +  r 

I  I 

ADDX 

rpa 

2 

15 

A  <—  A  +  (rpa) 

I  I 

ADC 

A,  r 

2 

12 

A  —  A  +  r  +  CY 

I  I 

ADCX 

rpa 

2 

15 

A -  A  +  (rpa)  +  CY 

t  t 

SUB 

A,  r 

2 

12 

A-A  -  r 

t  t 

SUBX 

rpa 

2 

15 

A  —  A  -  (rpa) 

I  I 

SBB 

A,  r 

2 

12 

A -  A  -  r  -  CY 

t  t 

SBBX 

rpa 

2 

15 

A  —  A  -  (rpa)  -  CY 

I  t 

ADDNC 

A,r 

2 

12 

A-A  +  r 

No  Carry 

t  t 

ADDNCX 

rpa 

2 

15 

A  «-  A  +  (rpa) 

No  Carry 

I  I 

SUBNB 

A,r 

2 

12 

A-A  -  r 

No  Borrow 

I  1 

SUBNBX 

rpa 

2 

15 

A  «-  A  +  (rpa) 

No  Borrow 

t  I 

Logical 

ANA 

A,  r 

2 

8/12 

A  —  A  \r 

t 

ANAX 

rpa 

2 

11/15 

A —  A  \(rpa) 

I 

ORA 

A,r 

2 

12 

A  —  A  V  r 

I 

ORAX 

rpa 

2 

15 

A  -  A  V  (rpa) 

I 

XRA 

A,r 

2 

12 

A  — AVr 

I 

XRAX 

rpa 

2 

15 

A-AV(rpa) 

I 

GTA 

A,  r 

2 

12 

A  -  r  -  1 

No  Borrow 

t  t 

GTAX 

rpa 

2 

15 

A  -  (rpa)  -  1 

No  Borrow 

I  I 

LTA 

A,  r 

2 

12 

A  -  r 

Borrow 

t  t 

LTAX 

rpa 

2 

15 

A  -  (rpa) 

Borrow 

t  t 

ONA 

A,  r 

2 

12 

A  A  r 

No  Zero 

1 

ONAX 

rpa 

2 

15 

A  A  (rpa) 

No  Zero 

I 

OFFA 

A,  r 

2 

12 

AAr 

Zero 

t 

OFFAX 

rpa 

2 

15 

A  A  (rpa) 

Zero 

I 

NEA 

A,r 

2 

12 

A  -  r 

No  Zero 

I  t 

NEAX 

rpa 

2 

15 

A  -  (rpa) 

No  Zero 

I  I 

EQA 

A,  r 

2 

12 

A  -  r 

Zero 

t  t 

EQAX 

rpa 

2 

15 

A  -  (rpa) 

Zero 

I  I 

Immediate  Data  Transfer  (Accumulator) 

XRI 

A,  byte 

2 

7/11 

A  —  A  V  byte 

I 

ADINC 

A,  byte 

2 

7/11 

A  —  A  +  byte 

No  Carry 

t  I 

SUINB 

A,  byte 

2 

7/11 

A  —  A  -  byte 

No  Borrow 

I  I 

ADI 

A,  byte 

2 

7/11 

A «-  A  +  byte 

I  I 

ACI 

A,  byte 

2 

7/11 

A-A  +  byte  +  CY 

t  I 

SUI 

A,  byte 

2 

7/11 

A  —  A  -  byte 

I  I 

SBI 

A,  byte 

2 

7/11 

A-A  -  byte  -  CY 

I  I 

ANI 

A,  byte 

2 

7/11 

A —  A  A  byte 

I 

ORI 

A,  byte 

2 

7/11 

A  -  A  V  byte 

t 

GTI 

A,  byte 

2 

7/11 

A  -  byte  -  1 

No  Borrow 

I  t 

LT1 

A,  byte 

2 

7/11 

A  -  byte 

Borrow 

I  I 

ONI 

A,  byte 

2 

7/11 

A  A  byte 

No  Zero 

I 

OFFI 

A,  byte 

2 

7/11 

A  A  byte 

Zero 

% 

NEI 

A,  byte 

2 

7/11 

A  -  byte 

No  Zero 

I  t 

EQI 

A,  byte 

2 

7/11 

A  -  byte 

Zero 

I  I 

Immediate  Data  Transfer  (Special  Register) 

ANI 

sr2,  byte 

3 

17 

sr2  — sr2  A  byte 

I 

ORI 

sr2,  byte 

3 

17 

sr2  — sr2Vbyte 

I 

OFFI 

sr2,  byte 

3 

14 

sr2  A  byte 

Zero 

t 

ONI 

sr2,  byte 

3 

14 

sr2  A  byte 

No  Zero 

I 

Working  Register 

ANIW 

wa,  byte 

3 

16 

(V,wa)-(V,wa)Abyte 

I 

ORIW 

wa,  byte 

3 

16 

(V,wa)-(V,wa)Vbyte 

I 

GTIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte  -  1 

No  Borrow 

I  t 

LTIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte 

Borrow 

I  I 

ONIW 

wa,  byte 

3 

13 

(V,  wa)  A  byte 

No  Zero 

I 

OFFIW 

wa,  byte 

3 

13 

(V,  wa)  A  byte 

Zero 

I 

NEIW 

wa,  byte 

3 

13 

(V,  wa)  -  byte 

No  Zero 

I  I 

EQIW       wa,  byte       3        13    (V,  wa)  -  byte  Zero  I  $ 


I.PD78C06  78C05 

Instruction  Set  (Cont.)  


No.  Clock 
Mnemonic  Operand  Bytes  Cycles 

Operation 

Skip 
Condition 

Flags 
CY  Z 

Increment/Decrement 

INR 

r2 

1 

4 

r2  —  r2  +  1 

Carry 

I 

INRW 

wa 

2 

13 

(V,  wa) «-  (V,  wa)  +  1 

Carry 

t 

DCR 

r2 

1 

4 

r2  —  r2  -  1  , 

Borrow 

I 

DCRW 

wa 

2 

13 

(V,  wa)  -  (V,  wa)  -  1 

Borrow 

I 

INX 

••p 

1 

7 

rp  «-  rp  +  1 

DCX 

rp 

1 

7 

rp  -  rp  -  1 

Miscellaneous 

DAA 

1 

4 

Decimal  Adjust 
Accumulator 

t  t 

STC 

2 

8 

CY  — 1 

1 

CLC 

2 

8 

CY<-0 

0 

Rotate  and  Shift 

RLD 

2 

17 

Rotate  Left  Digit 

RRD 

2 

17 

Rotate  Right  Digit 

RAL 

2 

8 

Am  +  1  -Am,A0-CY, 
CY*-A7 

I 

RAR 

2 

8 

Am  -  1  <—  Am,  A7  *-  CY, 
CY-A0 

I 

RAL 

2 

8 

Am  +  1  —  Am,  A0  — CY, 
CY-A7 

I 

Jump 

JMP 

word 

3 

10 

PC  —  word 

JB 

1 

4 

PCH^B,  PCl-C 

JR 

word 

1 

13 

PC  —  PC  +  1  +  jdispl 

JRE 

word 

2 

13 

PC  —  PC  +  2  +  jdisp 

Call 

CALL 

word 

3 

16 

(SP  -  1)-(PC-3)H, 
(SP  -  2) -(PC  -  3)u, 
PC  —  word 

CALF 

word 

2 

16 

(SP  -  1)-(PC-2)H, 
(SP  -  2) -(PC  -  2)u, 
PC15-PCn  —  00001, 
PC10-PC0-fa 

CALT 

word 

1 

19 

(SP-1)-(PC-1)H, 
(SP-2)-(PC-1)L, 
PCL-(128  -  2ta), 
PCH^(129  +  2ta) 

Return 

RET 

1 

11 

PCL-(SP),PCH-(SP  +  1) 
SP  -  SP  -  2 

RETS 

1 

11  +  a 

PCL  —  (SP),  PCH  —  (SP  +  1), 
SP  —  SP  +  2,  PC  —  PC  +  n 

RETI 

1 

15 

PCL-(SP),PCH-(SP  +  1) 
PSW-(SP  +  2), 
SP-SP  +  3,  SIRQ-0 

Skip 

SKNC 

2 

8 

Skip  if  No  Carry 

CY  =  0 

SKNZ 

2 

8 

Skip  if  No  Zero 

Z  =  0 

SKNIT 

f 

2 

8 

Skip  if  No  INT  X 
otherwise  reset  INT  X 

f  =  0 

CPU  Control 

NOP 

1 

4 

No  Operation 

El 

2 

8 

Enable  Interrupt 

Dl 

2 

8 

Disable  Interrupt 

Serial  Port  Control 

SIO 

1 

4 

Start  (Trigger)  Serial  I/O 

STM 

1 

4 

Start  Timer 

Port  E  Control 

PEX 

2 

11 

PE15_8-B,  PE7_0-C 

PER 

2 

11 

Port  E  AB  Mode 

4-41 


I.PD78C06  78C05 

Program  Status  Word  (PSW)  Operation 


Operation 

D6 

D5 

D4 

D3 

D2 

DO 

Reg.  Memory 

Immediate 

Skip 

Z 

SK 

HC 

LI 

LO 

CY 

ADD 
ADC 
SUB 
SBB 

ADDX 
ADCX 
SUBX 
SBBX 

ADI 
ACI 
SUI 
SBI 

I 

0 

I 

0 

0 

I 

ANA 
ORA 
XRA 

ANAX 
ORAX 
XRAX 

ANI 
ORI 
XRI 

ANIW 
ORIW 

I 

0 

• 

0 

0 

m 

ADDNC 
SUBNB 
GTA 

LTA  

ADDNCX 
SUBNBX 
GTAX 



ADINC 
SUINB 
GTI 

GTIW 

~oiwiv — 

t 

I 

o 

o 

I 

OFFAX 

~olii — 

OFFI 

OFFIW 

I 

t 

• 

0 

0 

• 

NEA 
EQA 

NEAX 
EQAX 

NEI 
EQI 

NEIW 
EQIW 

I 

t 

J 

o 

o 

INR  INRW 
DCR  DCRW 

I 

t 

J 

0 

0 

• 

DAA 

I 

0 

I 

0 

0 

I 

• 

0 

m 

0 

0 

I 

nLU  —  nnU 

• 

0 

• 

0 

0 

• 

STC 

o 

o 

o 

1 

CLC 

• 

o 

o 

o 

0 

MVI  A,  byte 

• 

o 

• 

1 

o 

• 

MVI  L,  byte 
LXI  H,  word 

• 

0 

• 

0 

1 

• 

SKNC 
SKNZ 
SKNIT 

• 

I 

• 

0 

0 

• 

RETS 

• 

1 

• 

0 

0 

• 

All  other  instructions 

• 

0 

• 

0 

0 

• 

Notes:  I  Flag  affected  according  to  result  of  operation 

1  Flag  set 

0  Flag  reset 

•  Flag  not  affected 


Absolute  Maximum  Ratings* 

(Ta  =  25°C) 


Supply  Voltage,  Vcc 

-0.3V  to  +7.0V 

Input  Voltage,  V, 

-0.3V  to  Vcc  +0.3V 

Output  Voltage,  VQ 

-0.3V  to  Vcc  +0.3V 

Output  High  Current,  I0h  (Device  Total) 

-5mA 

Output  Low  Current,  IQl  (Device  Total) 

43.5mA 

Operating  Temperature,  Tqpt 

-10°Cto  +70°C 

Storage  Temperature,  TSTG 

-40°C  to  +125°C 

*COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be 
operated  under  conditions  outside  the  limits  described 
in  the  operational  sections  of  this  specification.  Expo- 
sure to  absolute  maximum  rating  conditions  for 
extended  periods  may  affect  device  reliability. 

DC  Characteristics 

Ta  =  -10°C  to  +  70°C;  Vcc  =  5V  ±  10% 


Limits 

Parameter 

Symbol 

Min  Typ 

Max 

Unit 

Test  Conditions 

V|H1 

0.7VCC 

Vcc 

V 

Except  DB0-DB7,  X1 

Input  High  Voltage 

V,H2 

Vcc  -  2.0 

Vcc 

V 

DB0-DB7 

V.H3 

Vcc  -  0.5 

VCC 

V 

X! 

V,L1 

0 

0.3VCC 

V 

Except  DB0-DB7,  X, 

Input  Low  Voltage 

vIL2 

0 

0.8 

V 

DB0-DB7 

V|L3 

0 

0.5 

V 

*1 

V0H1 

2.4 

V 

l0H  =  -IOOmA 

Output  High  Voltage 

V0H2 

Vcc  "  0.5 

V 

l0H  =  -50|xA 

Output  Low  Voltage  V0L 

0.45 

V 

Iql  =  18mA 

Input  High  Current 

!|H1 

8 

90 

pA 

V,n  =  Vcc(REL) 

•|H2 

40 

VA 

V,n  =  VCc(X1) 

DC  Characteristics 


Ta  =  -10°Cto 

+  70°C 

Vcc 

=  5V  ±  10% 

Limits 

Parameter 

Symbol 

Min 

Typ  Max 

Unit 

Test  Conditions 

Input  Low  Current 

•lL1 

V...  —  OV  fWAIT  PC— PC~\ 

'lL2 

-40 

HA 

VIN  =  0V(X1) 

Input  High  Leakage 
Current 

'lih 

3 

V,N  =  Vcc 
(Except  REL,  X,) 

Input  Low  Leakage 

LIL1 

-3 

»A 

VIN  =  0V  Except  WAIT, 
PC0— PC5,  x1 

Current 

'lIL2 

 3  

— T~ 
\x.A 

Vin  =  ov 
(Stop  Mode,  X,) 

Output  High 
Leakage  Current 

LOH 

(i.A 

»0UT  -  VCC 

Output  Low 
Leakage  Current 

'lol 

-3 

*A 

V0UT  =  0V 

'cci 

3.5  6.0 

mA 

Operation  Mode 

Vcc  Supply  Current 

'CC2 

0.8  1.8 

mA 

Halt  Mode 

'CC3 

1  15 

jxA 

Stop  Mode  (Xt  =  0V, 
X2  =  Open) 

Low  Power  Data  Memory  Retention 
Characteristics  for  Stop  Mode  Operation 
Ta  =  -10°Cto  +70°C 

Limits 

Parameter 

Symbol 

Min 

Typ  Max 

Unit 

Test  Conditions 

Data  Retention 
Voltage 

VCCDR 

2.0 

V 

Data  Retention 
Supply  Current 

•cCDR 

0.8  15 

,xA 

Vccdr  =  2.0V,(X1  =0V, 
X2  =  Open) 

Data  Retention  Input 
Low  RES  Voltage 

V|LDR 

0 

0.2VCCDR 

V 

Data  Retention  Input 
High  RESET  Voltage 

V|HDR 

0-8VCCDR  VCCDR 

V 

REL  Input  Delay 
Time 

to 

500 

M« 

REL  Input  High  Time 

lREL 

10 

(XS 

Notes:  In  data  retention  mode,  Input  voltages  to  WAIT  and  PC0-PC5  pins  (with  pull-up  resistors) 
should  be  maintained  same  as  VCCDR  level,  other  input  voltages  should  be  kept  less  than 
Vccdr  level 


DC  Characteristics 
Read/Write  Operation 


Parameter 

Symbol 

Min  Typ 

Max 

Unit 

RD  LE  to  4>OUT  LE 

*R* 

300 

ns 

Address  (PE0-PE15) 
to  Data  Input 

*AD1 

1200 
+  1000 
x  N 

ns 

RD  TE  to  Address 

*RA 

300  (T3) 
1300  (T4) 

ns 

RD  LE  to  Data  Input 

lRD 

700 
+  1000 
x  N 

ns 

RD  TE  to  Data  Hold 
Time 

*RDH 

0 

ns 

RD  Low  Time 

*RR 

1700 
+  1000 
x  N 

ns 

RD  LE  to  WAIT  LE 

^RWT 

700 

ns 

Address  (PE0-PE15) 
to  WAIT  LE 

*AWT1 

1200 

ns 

WAIT  Set-up  Time  to 
^out  LE 

*WTS 

600 

ns 

WAIT  Hold  Time  after 

4>out  LE 

*WTH 

0 

ns 

M1  to  RD  LE  (D 

200 

ns 

RD  TE  to  M1  © 

*RM 

300 

ns 

ct>OUTLEto  WR  LE 

250 

ns 

Address  (PE„-PE15) 

to  <|>out  TE 

150 

ns 

Test  Conditions 


tcv*  =  1000ns 


4 


-42 


I  PD78C06  78C05 


DC  Characteristics  (Cont.) 
Read/Write  Operation 

 Limits  

Parameter        Symbol     Min      Typ     Max     Unit      Test  Conditions 


(PE0-PE15) 

)utput  850 
1200 


Data  Output  to  WR  TE  tDW 

1200 
+  1000 
x  N 

ns 

WR  TEto  Data  Stable 
Time 

*WD 

300 

ns 

Address  (PE0-PE15) 
toWR  LE 

*AW 

800 

ns 

WR  TEto  Address 
Stable  Time 

*WA 

300 

ns 

WR  Low  Time 

^WW 

1200 
+  1000 
x  N 

ns 

WR  LE  to  WAIT  LE 

tWWT 

250 

ns 

Notes:  ©  Applies  only  to  H.PD78C05 
N  is  number  of  TWAn- 

LE  is  leading  edge,  and  TE  is  trailing  edge 


Serial  Operation 


Limits 

Parameter 

Symbol 

Min 

Typ  Max 

Unit 

Test  Conditions 

SCK  Cycle  Time 

1800 

ns 

SCK  Input 

tcYK 

1818 

80000 

ns 

SCK  Output 

SCK  Low  Time 

700 

ns 

SCK  Input 

*KKL 

759 

ns 

SCK  Output 

SCK  High  Time 

700 

ns 

SCK  Input 

*KKH 

759 

ns 

SCK  Output 

SI  Set-up  Time  to 
SCK  TE 

lSIS 

200 

ns 

SI  Hold  Time  after 
SCK  TE 

tsiH 

500 

ns 

SCK  LEtoSO  Delay 
Time 

tKO 

550 

ns 

Notes:  Input  timings  are  measured  at  V,H  mm  and  V,L  max 

Output  timings  are  measured  at  V0H  =  2  4V  and  V0L  =  0  45V  with  1-TTL  +  200pF 
=  load 

LE  is  leading  edge,  TE  is  trailing  edge 


Capacitance 

Ta  =  25°C;  Vcc  =  GND  =  OV 


Limits 


Parameter 

Symbol  Min 

Typ 

__MaX 

Test  Conditions 

Input  Capacitance 

C| 

15 

PF 

fc  =  1MHz 

Output  Capacitance 

Co 

15 

PF 

Unmeasured  pins 

I/O  Capacitance 

ci/o 

— 15  

pF 

returned  to  0V 

AC  Characteristics 

Ta  =  -10°Cto  +70°C;VCC  = 
Clock  Timing 

+  5V 

±  10% 

Limits 

Parameter 

Symbol  Min 

Typ 

Max 

Unit 

Test  Conditions 

X1  input  Cycle  Time 

tcvx  227 

10000 

ns 

X!  Input  Low  Time 

txxL  106 

ns 

Xi  Input  High  Time 

*xxh  106 

ns 

4>out  Cycle  Time 

*CY4  908 

40000 

ns 

<t>OUT  Low  Time 

W  300 

ns 

<t>OUT  Hl9n  Tlme 

*dKbH  300 

ns 

<t>OUT  Rise/Fall  Time 

tR,tF 

150 

ns 

Write  Operation 


Serial  Operation 


— *KKH  »j 

 i 


/ 

 T2  ^ 

*               TWAIT            "|"*                  T3  ""I 

\  ) 

\         /         \  / 

K= 


a  r 


4-43 


|ulPD78C06/78C05 


Timing  Waveforms  (Cont.) 

Read  Operation 


Address 

x 

*AD1 

-  tRA  

— < 

*  *RD 

)    Read  Data 

t  

H  JRDH 

\ 

y 

\ 

•*  *RWT  V   +■ 

'-tAWT1  *-  *WTS 

I"*  lWTH 

— 4 

tRM  K- 

Note:  ©Applies  only  to  |jlPD78C05 


C/ocfc  Timing 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Miniflat,  fiPD78C06G 
Plastic  Quil,  |xPD78C05G 


4-44 


78C06/05DS-Rev  1-7-83-CAT-L 


JVFC  (jLPD7809/aPD7807/^PD78P09 

HIGH  END  SINGLE  CHIP  8-BIT 
MICROCOMPUTER  WITH 
COMPARATOR,  8K  ROM 


Description 

The  |jlPD7809/7807/78P09  single  chip  microcomputer 
augments  the  high-end  in  NEC's  family  of  8-bit  microcom- 
puters with  sophisticated  on-chip  peripheral  functionality. 
Like  its  nearest  relative  in  the  family,  the  |xPD7811,  this 
device  has  a  fast  internal  16-bit  ALU  and  data  paths,  256 
bytes  of  RAM,  multifunction  16-bit  timer/event  counter,  two 
8-bit  timers,  a  USART,  and  two  zero-cross  detect  inputs. 
Features  that  distinguish  this  device  in  the  NEC  8-bit  family 
are:  8K  ROM,  programmable  threshold  comparator  (8 
inputs),  programmable  WAIT  function,  watchdog  timer,  hold 
and  hold  acknowledge  for  DMA  interface,  and  bit  test/write 
instructions  for  both  RAM  and  I/O. 
The  |xPD7809  is  the  mask-ROM  version  with  the  cus- 
tomer's program  on  chip.  The  |jlPD7807  is  the  ROM-less 
version  for  prototyping  and  small  volume  applications.  The 
|xPD78P09  is  an  EPROM  version  of  the  8K  ROM 
|jlPD7809. 

Features 

□  NMOS  silicon  gate  technology  requiring  +  5v  supply 

□  Complete  single  chip  microcomputer 

—  16-bit  ALU 

—  8K  ROM 
256  bytes  RAM 

□  Large  I/O  capability 

—  40  I/O  port  lines  (|xPD7809) 

—  28  I/O  port  lines  (jjlPD7807) 

—  8  input  lines 

□  Two  zero-cross  detect  inputs 

□  Expansion  capability  (total  of  64K  memory  access) 

—  8085A  bus  compatible 

—  56K  bytes  external  memory  address  range 

□  Programmable  threshold  comparator 

—  8  inputs,  1  of  16  software  selectable  levels 

□  Full  duplex  USART 

—  Synchronous  and  asynchronous 

□  165  powerful  instructions 

—  16-bit  arithmetic,  multiply  and  divide 

□  1  |xs  instruction  cycle  time 

□  Prioritized  interrupt  structure 

—  3  external 

—  8  internal 

□  Hold,  hold  acknowledge  for  DMA  interface 

□  Programmable  WAIT  function 

□  Watchdog  timer 

□  Standby  function 

□  On-chip  clock  generator 

□  64-pin  QUIL  package 


Pin  Configuration 


PA0 
PAn  i 


PB1  I 
PB2 
PB3t 
PB4 
PB5  t 


PC4 
PC5  c 
PC6 
PCj  c 
NMI 
INT1  E 
MODE1 
RESET  C 
MODE0 
X2  c 


\  /  

64 
63 

VCc 

vDD 

62 

PD7 

61 
60 

=3 

PD6 
PD5 

59 

PD4 

58 

PD3 

57 

PD2 

55 

PDo 

54 

PFy 

53 

PF6 

52 

PF5 

(jiPD 

51 

PF4 

50 

PF3 

7809/ 

49 

PF? 

7807/ 

48 
47 

PFi 
PF0 

78P09 

46 

=3 

ALE 

45 

WR 

44 

=3 

RD 

43 

HLDA 

42 

HOLD 

41 

PT7 

40 

=3 

PT6 

39 

PT5 

38 

=3 

PT4 

37 

PT3 

36 

=3 

PT2 

35 

PTi 

34 

PT0 

33 

VTH 

Pin  Identification 


No.  Symbol 


Function 


PA0-PA7  Port  A:  (Three-state  input/output)  8-bit 

programmable  I/O  port.  Each  line  independently 
programmable  as  an  input  or  output.  Reset  places  all 
lines  of  Port  A  in  input  mode. 

PB0-PB7  PortB:  (Three-state  input/output)  8-bit 

programmable  I/O  port.  Each  line  independently 
programmable  as  an  input  or  output  Reset  places  all 
lines  of  Port  B  in  input  mode 


PC2 


PortC:  (Three-state 
input/output)  8-bit 
programmable  I/O  port 

— Each  line  independently 
programmable  as  an 
input  or  output. 

—Alternatively,  Port  C  may  - 
be  used  as  control  lines 
for  USART  and  timer 
Reset  puts  Port  C  in  Port 
mode  and  all  lines  in 
input  mode. 


Transmit  Data  (TxD): 
Serial  data  output 
terminal 

Receive  Data 

(RxD):  Serial  data  input 

terminal. 


Serial  Clock 
(SCK):  Serial  clock 
input/output  terminal. 
When  internal  clock  is 
used,  the  output  can 
be  selected;  when  an 
external  clock  is  used, 
the  input  can  be  selected. 
Timer  Input  (Tl)/interrupt 
request  input  (INT2): 
Timer  clock  input 
terminal;  can  also  be 
used  as  falling  edge, 
maskable-interrupt  input 
terminal  and  AC  input 
zero-cross  detection 
terminal. 


21 

PC4 

Timer  Output  (TO):  This 
output  signal  is  a  square 
wave  whose  frequency  is 
determined  by  the 
timer/counter. 

22 

PCs 

Counter  Input  (CI): 

External  pulse  input 

terminal  to  the  timer/ 

event  counter. 

23-24  PC6,  PC7 


Counter  Outputs  0, 1 
(COo-CO-,).  Program- 
mable rectangular  wave 
output  terminal  based  on 
timer/event  counter 


4-45 


I  PD7809/7807/78P09 


Pin  Identification  (Cont.) 


No. 

Pin 

Symbol 

Function 

25 

NMI 

Falling-edge,  nonmaskable  interrupt  (NMI)  input. 

26 

INT, 

This  signal  is  a  rising-edge,  maskable  interrupt  input 
This  input  is  also  used  to  make  the  zero-cross 
detection  AC  input. 

27 

MODE1 

Used  as  input  in  conjunction  with  MODE0  to  select 
appropriate  memory  expansion  mode.  Also  outputs 
M1  Signal  during  each  opcode  fetch 

28 

RESET 

(Input,  active  low),  RESET  initializes  the  |xPD781 1 . 

29 

MODE0 

Used  as  input  in  conjunction  with  MODE1  to  select 
appropriate  memory  expansion  mode.  Also  used  to 
ouput  IO/M. 

30-31 

x2,  X1 
(crystal) 

This  is  a  crystal  connection  terminal  for  system 
clock  oscillation.  When  an  external  clock  is  supplied 
X1  is  the  input. 

32 

VSs 

Power  supply  ground  potential. 

33 

VTh 

VTH  threshold  voltage  input.  Reference  voltage  for 
variable  threshold  input,  Port  T.  Threshold  voltage  to 
each  Port  T  input  is  software  programmable  to  16 
different  levels. 

34-41 

PTi-PT7 

Eight  variable  threshold  input  ports.  Ports  T0-T7 
inputs  are  each  connected  internally  to  comparators 
where  the  other  input  is  the  threshold  voltage. 

42 

HOLD 

HOLD  request  input.  When  high,  CPU  is  in  a  HOLD 
state  until  HOLD  goes  low. 

43 

HLDA 

HOLD  Acknowledge  output  by  CPU  when  HOLD  state 
is  accepted;  goes  low  when  HOLD  is  released. 

44 

RD 

(Three-state  output,  active  low)  RD  is  used  as  a 
strobe  to  gate  data  from  external  devices  onto  the 
data  bus.  RD  goes  high  during  Reset. 

45 

WR 

(Three-state  output,  active  low)  WR,  when  active, 
indicates  that  the  data  bus  holds  valid  data.  Used 
as  a  strobe  signal  for  external  memory  or  I/O  write 
operations.  WR  goes  high  during  Reset. 

46 

ALE 

The  strobe  signal  is  for  latching  the  address  signal 
to  the  output  from  PD7-PD0  when  accessing  external 
expansion  memory. 

PF— PF, 

Port  F:  (Three-state         Address  Bus?  When 
input/output)  8-bit           external  expansion 
programmable  I/O  port.      memory  is  used, 
Each  line  configurable      multiplexed  address/data 
independently  as  an         bus  can  be  selected . 
input  or  output. 

55-62 

DB0-DB7 

Port  D:  8-bit                  Address  Bus:  When 
programmable  I/O  port.     external  expansion 
This  byte  can  be             memory  is  used, 
designated  as  either         multiplexed  address/data 
input  or  output.              bus  can  be  selected. 

63 

VDd 

This  is  a  backup  power  terminal  for  on-chip  RAM. 

64 

VCc 

+  5V  power  supply. 

Instruction  Set 

In  addition  to  the  basic  7800  family  instruction  set,  the  fol- 
lowing instructions  are  incorporated  in  the  jxPD7809/7807/ 
78P09: 

□  16-bit  data  transfers  between  memory,  registers,  and 
extended  accumulator 

□  16-bit  addition  and  subtraction 

□  16-bit  comparison  and  skip 

□  16-bit  and,  or,  ex-or  operation 

□  16-bit  data  shift  and  rotation 

□  Multiply 

8-bit  by  8-bit,  16-bit  product 
Less  than  8|jls  execution 

□  Divide 

16-bit  by  8-bit,  16-bit  quotient,  8-bit  remainder 
Less  than  14|xs  execution 

□  Working  register  instructions  for  efficient  RAM  address- 
ing, testing  and  manipulating 

□  Direct  bit  addressing  for  code-efficient  addressing, 
testing  and  manipulating  bits  in  RAM,  port  lines  and 
mode  registers 


Notes:  1  clock  cycle  =  1  CL  =  3/f 

1  machine  cycle  =  3  or  4  clock  cycles 

1  instruction  cycle  =  1  to  1 9  machine  cycles 

f  System  clock  frequency  (MHz) 


4-46 


MPD7809/7807/78P09 


Block  Diagram 


-  I  I  i  HIP  ! 

HOLD    HLDA      RD     WR        *J>  ^  ^  J§>  VD 
^U   *°  ^ 


Note:  The  |jlPD7807  has  no  on  chip  ROM  (8K  bytes) 


4-47 


IjiPD7809/7807/78P09 


Please  refer  to  the  section  on  jxPD7811  for  description  of 
the  following  functions  which  are  the  same  as  on  this 
device: 

1 .  Memory  expansion  (except  56K  bytes  maximum  for 
MPD7809) 

2.  Timer/event  counter 

3.  USART 

4.  Interrupt  structure 

5.  Standby  function 

6.  Reset 

7.  External  memory  access  and  timing 

8.  Package  information 

Variable  Threshold  Input  Port  (Port  T) 

□  8  input  lines 

□  16  levels  —  from  Vie  of  reference  voltage  (VTH) 

to  16/ieVTH 

□  Level  selected  by  software  write  to  Mode  T  register 

□  Input  at  Port  bit  reads  0  until  voltage  at  pin  exceeds 
selected  level 

□  Comparison  execution  time:  12|xs. 

Block  Diagram  off  Threshold 
Variable  Input  Port 


pt3o- 


3>-t 


Input/Output 

□  40  digital  I/O  lines  —  Five  8-bit  ports  (Port  A,  Port  B, 
Port  C,  Port  D,  Port  F) 

□  Port  operation  for  Ports  A,  B,  C,  and  F: 

Each  line  of  these  ports  can  be  individually  programmed 
as  an  input  or  as  an  output. 

□  Port  D  can  be  programmed  as  a  byte  input  or  a  byte 
output. 

□  Control  lines: 

Under  software  control,  each  line  of  Port  C  can  be  con- 
figured individually  to  provide  control  lines  for  serial 
interface,  timer  and  timer/counter. 

Block  Diagram  off  Threshold 
Variable  Port 


7     6     5     4     3  2  

I  -  I  -  I  -  I  -  |  MT3  |MT2|  MT.! [MToj 

L- J — '  '  '  >  '  i  rzr1 


Format  of  MODE  T  Register 


Specification  of  16  Threshold  Levels 


4-48 


fxPD7809/7807/78P09 


Watchdog  Timer 

□  Used  for  software  safety  check  or  overall  performance 
safety  check.  Watchdog,  if  enabled,  must  be  cleared  at 
regular  intervals  in  program  execution  to  avoid  watchdog 
interrupt.  Intervals  are  software  selectable. 

Block  Diagram  for  Watchdog  Timer 


3> 


Prescaler 
(5) 


Upcounter 
(7) 


7X 


Interval 
Control 

Note:  <)>384  =        x  ^84 

Bit  Address  Instructions 

The  following  bits  may  be  addressed  directly  with  certain 
instructions: 

□  Any  bit  in  a  16-byte  group  in  RAM 

□  Any  bit  in  the  five  8-bit  I/O  ports  (A,  B,  C,  D,  F) 

□  Any  bit  in  the  variable  threshold  port 

□  Any  bit  in  the  following  special  registers: 

9-bit  interrupt  mask  register,  serial  mode  register,  timer 
mode  register,  timer/event  counter  output  register 

An  addressed  bit  may  be  tested,  set,  cleared,  or 

complemented. 

An  addressed  bit  may  be  moved  to  or  from  the  carry  flag. 
An  addressed  bit  may  be  ANDed,  ORed,  X-ORed  with  the 
carry  flag. 


Difference  between  the  |xPD7801,  UJPD7811, 


HPD7801 

MPD7811 

^PD7807 

MPD7809 

Number  of  Instructions 

134 

158 

165 

165 

16-bit  Operation  Instruction 

No 

Yes 

Yes 

Yes 

Multiply/ Divide  Instruction 

No 

Yes 

Yes 

Yes 

Instruction  Cycle 

2P_s/4MHz 

1M.s/ 12MHz 

Vs/12MHz 

1  US/ 12MHz 

Number  of  General-purpose 
Registers 

16 

18 

18 

18 

On-chip  ROM  Capacity 

4K  Bytes 

4K  Bytes 

No 

8K  Bytes 

On-chip  RAM  Capacity 

128  Bytes 

256  Bytes 

256  Bytes 

256  Bytes 

Direct-Addressable  External 
Memory  Capacity 

60K  Bytes 

60K  Bytes 

64K  Bytes 

56K  Bytes 

Interrupt  Internal 

2 

8 

8 

8 

Source  External 

3 

3 

3 

3 

I/O  Lines 

48 

40  +  4 

28* 

40 

Threshold  Variable  Port 

No 

No 

8  Bits 

8  Bits 

Timer 

12  Bits 

8  Bits  x  2 

8  Bits  x  2 

8  Bits  x  2 

Timer/Counter   

Counter 

No 

16  Bits 

16  Bits 

16  Bits 

Watchdog  Timer 

No 

No 

Yes 

Yes 

Asynchronous 

No 

Yes 

Yes 

Yes 

Serial  Interface  Synchronous 

No 

Yes 

Yes 

Yes 

I/O  Interface 

Yes 

Yes 

Yes 

Yes 

A/D  Converter 

No 

Yes 

No 

No 

Standby  Function 

No 

Yes 

Yes 

Yes 

Hold  Function 

Yes 

No 

Yes 

Yes 

Technology 

NMOS 

NMOS 

NMOS 

NMOS 

Package 

64-Pin  Flat 

64-Pin  QUIP 

64-Pin  QUIP 

64-Pin  QUIP 

*  at  4K-byte  Access 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Quil,  ^PD7807G/09G 

Plastic  Shrinkdip,  ^PD7809CW/07CW 


4-49 


7809/7807/78P09DS-7-83-CAT-L 


Notes 


4-50 


SfFC  |jlPD7810/jjlPD7811 
^'  ^  HIGH-END  SINGLE-CHIP 

8-BIT  MICROCOMPUTER 
WITH  A/D  CONVERTER 


Description 

The  NEC  |jiPD7810/VPD7811  is  a  high-performance 
single-chip  microcomputer  integrating  sophisticated  on- 
chip  peripheral  functionality  normally  provided  by  external 
components.  The  device's  internal  16-bit  ALU  and  data 
paths,  combined  with  a  powerful  instruction  set  and 
addressing,  make  the  |mPD781 0/7811  appropriate  in  data 
processing  as  well  as  control  applications.  The  device 
integrates  a  16-bit  ALU,  4K-ROM,  256-byte  RAM  with  an 
8-channel  A/D  converter,  a  multifunction  16-bit  timer/event 
counter,  two  8-bit  timers,  a  USART  and  two  zero-cross 
detect  inputs  on  a  single  die,  to  direct  the  device  into  fast, 
high-end  processing  applications  involving  analog  signal 
interface  and  processing. 

The  |xPD7811  is  the  mask-ROM  high  volume  production 
device  embedded  with  custom  customer  program.  The 
|jlPD7810  is  a  ROM-less  version  for  prototyping  and  small 
volume  production.  The  fxPD78PG11E  is  a  piggy-back 
EPROM  version  for  design  development. 
Features 

□  NMOS  silicon  gate  technology  requiring  +  5V  supply 

□  Complete  single-chip  microcomputer 

-  16-bit  ALU 

-  4K-ROM 

-  256-byte  RAM 

□  44  I/O  lines 

□  Two  zero-cross  detect  inputs 

□  Two  8-bit  timers 

□  Multifunction  16-bit  timer/event  counter 

□  Expansion  capabilities 

-  8085A  bus  compatible 

-  60K-byte  external  memory  address  range 

□  8-channel,  8-bit  A/D  converter 

-  Auto  scan 

-  Channel  select 

□  Full  duplex  USART 

-  Synchronous  and  asynchronous 

□  153  instruction  set 

-  16-bit  arithmetic,  multiply  and  divide 

□  1  |xs  instruction  cycle  time  (12MHz  operation) 

□  Prioritized  interrupt  structure 

-  2  external 

-  4  internal 

□  Standby  function 

□  On-chip  clock  generator 

□  64-quil  package 


Pin  Configuration 


M.PD7810G 
^PD7811G 


1  DB4 
DB3 


1  PF6 


3  PF2 
PFi 

>  PF0 
ALE 

3  WR 
RD 

»  AVCC 


)  AN1 
AN0 
>  AVSS 


Pin  Identification 


No. 

Pin 

Symbol 

Function 

1-8 

PAo-PA7 

Port  A:  (Three-state  input/output)  8-bit 
programmable  I/O  port.  Each  line  independently 
programmable  as  an  input  or  output.  Reset  places  all 
lines  of  Port  A  in  input  mode 

9-16 

PB0-PB7 

Port  B:  (Three-state  input/output)  8-bit 
programmable  I/O  port.  Each  line  independently 
programmable  as  an  input  or  output.  Reset  places  all 
lines  of  Port  B  in  input  mode. 

PC0 


PC, 


PortC:  (Three-state 

input/output)  8-bit 

programmable  I/O  port. 
~Each  line  independently 

programmable  as  an 

input  or  output. 
-Alternatively,  Port  C  may 

be  used  as  control  lines 

for  USART  and  timer. 

Reset  puts  Port  C  in  Port 

mode  and  all  lines  in 

input  mode. 


Transmit  Data  (TxD): 

Serial  data  output 

terminal. 

Receive  Data 

(RxD):  Serial  data  input 

terminal. 

Serial  Clock 
(SCK):  Serial  clock 
input/output  terminal. 
When  internal  clock  is 
used,  the  output  can 
be  selected;  when  an 
external  clock  is  used, 
the  input  can  be  selected. 


20 

PC3 

Timer  Input  (Tl)/interrupt 
request  input  (INT2): 
Timer  clock  input 
terminal;  can  also  be 
used  as  falling  edge, 
maskable-interrupt  input 
terminal  and  AC  input 
zero-cross  detection 
terminal. 

21 

PC4 

Timer  Output  (TO):  This 
output  signal  is  a  square 
wave  whose  frequency  is 
determined  by  the 
timer/counter. 

22 

PCs 

Counter  Input  (CI): 
External  pulse  input 
terminal  to  the  timer/ 
event  counter. 

23-24 

PC6,  PC7 

Counter  Outputs  0, 1 

(COq-CO,):  Program- 
mable rectangular  wave 
output  terminal  based  on 
timer/event  counter. 


4-51 


fxPD7810/7811 

Pin  Identification  (Cont.) 


No. 

Pin 

Symbol 

Function 

25 

NMI 

Falling-edge,  nonmaskable  interrupt  (NMI)  input. 

26 

INT! 

This  signal  is  a  rising-edge,  maskable  interrupt  input 
This  input  is  also  used  to  make  the  zero-cross 
detection  AC  input. 

27 

MODE1 

Used  as  input  in  conjunction  with  MODE0  to  select 
appropriate  memory  expansion  mode.  Also  outputs 
M1  Signal  during  each  opcode  fetch. 

28 

RESET 

(Input,  active  low),  RESET  initializes  the  |xPD7811. 

29 

MODE0 

Used  as  input  in  conjunction  with  MODE1  to  select 
appropriate  memory  expansion  mode.  Also  used  to 
ouput  IO/M. 

30-31 

(crystal) 

This  is  a  crystal  connection  terminal  for  system 
clock  oscillation.  When  an  external  clock  is  supplied 
Xi  is  the  input. 

32 

Vss 

Power  supply  ground  potential. 

33 

AVSS 

A/D  converter  power  supply  ground  potential.  Sets 
conversion  range  lower  limit. 

34-41 

AN0-AN7 

Eight  analog  inputs  to  the  A/D  converter.  AN7-AN4 
can  also  be  used  as  a  digital  input  port  for  falling 
edge  detection. 

42 

Varef 

Reference  voltage  for  A/D  converter.  Sets  conversion 
range  upper  limit. 

43 

AVCC 

Power  supply  voltage  for  A/D  converter. 

No. 

Pin 

Symbol 

Function 

44 

RD 

(Three-state  output,  active  low)  RD  is  used  as  a 
strobe  to  gate  data  from  external  devices  onto  the 
data  bus.  RD  goes  high  during  Reset. 

45 

WR 

(Three-state  output,  active  low)  WR,  when  active, 
indicates  that  the  data  bus  holds  valid  data.  Used 
as  a  strobe  signal  for  external  memory  or  I/O  write 
operations.  WR  goes  high  during  Reset. 

46 

ALE 

The  strobe  signal  is  for  latching  the  address  signal 
to  the  output  from  PD7-PD0  when  accessing  external 
expansion  memory. 

47-54  PF0-PF7 

Port  F:  (Three-state 
input/output)  8-bit 
programmable  I/O  port. 
Each  line  configurable 
independently  as  an 
input  or  output 

Address  Bus:  When 
external  expansion 
memory  is  used, 
multiplexed  address/data 
bus  can  be  selected. 

55-62  DB0-DB7 

Port  D:  8-bit 
programmable  I/O  port. 
This  byte  can  be 
designated  as  either 
input  or  output. 

Address  Bus:  When 
external  expansion 
memory  is  used, 
multiplexed  address/data 
bus  can  be  selected. 

63  VDD 

This  is  a  backup  power  terminal  for  on-chip  RAM. 

64  Vcc 

+  5V  power  supply. 

Notes:  1  clock  cycle  =  1  CL  =  3/f 

1  machine  cycle  =  3  or  4  clock  cycles 

1  instruction  cycle  =  1  to  1 9  machine  cycles 
f  System  clock  frequency  (MHz) 


Block  Diagram 


PC1/TxD 
PC1/RxD 
PC2/SCK 


NMI  ( 
INT1  < 


PC3/TI/INT2  ( 
PC4/T0  < 

PC5/C1  < 
PC6/C00  < 
PC7/C01  < 


INT 

CONTROL 


CO 


TIMER 
---'EVENT 
COUNTER 


varef  ' 

AVcc  1 
AVSS 


7-o  cV; 


A/D 

CONVERTER 


Program 
Memory 
(8K-Byte) 


Of. 


Data 

Memory 

(256-BYTE) 


Internal  Data  Bus 


7S 


Latch  Latch 


3 


KO 


r 


*0: 


OpB-~ 


READ/WRITE 

TIMING 

SYSTEM 

STANDBY 

CONTROL 

CONTROL 

CONTROL 

CONTROL 

6  6 


RD     WR         M1   ALE    MODE    RESET      VDD       VCC  VSS 


4-52 


Functional  Index 

Memory  map 

The  jxPD7811  can  directly  address  up  to  64K-bytes 
of  memory.  Except  for  the  on-chip  ROM (0-4095)  and 
RAM (65280-65535),  any  memory  location  can  be  used 
as  ROM  or  RAM.  The  following  memory  map  defines 
the  0-64K-byte  memory  space  for  the  |xPD7811. 

Memory  Map 


|jPD7810/7811 


OFFFH 
1000H 


Internal  ROM 
4,096  Bytes  x  8 


0  Reset/Standby  Release 


FEFFH 
FF00H 


External 
Memory 
61,184  Bytes  x  8 


Internal  RAM 
256  Bytes  x  8 


High  ADRS 


High  ADRS 


High  ADRS 


OFFFH 


4-53 


,.PD7810/7811 

Input/Output 

8  Analog  Input  Lines 

44  Digital  I/O  Lines:  five  8-bit  ports  (Port  A,  Port  B,  Port  C, 
Port  D,  Port  F)  and  4  input  lines  (AN4-AN7) 

1 .  Analog  Input  Lines 
AN0-AN7  are  confic 
chip  A/D  converter. 

2.  Port  Operation 

-  Port  A,  Port  B,  Port  C,  Port  F 

Each  line  of  these  ports  can  be  individually 
programmed  as  an  input  or  as  an  output.  When 
used  as  I/O  ports,  all  have  latched  outputs,  high- 
impedance  inputs. 

-  Port  D 

Port  D  can  be  programmed  as  a  byte  input  or  a 
byte  output. 

-  AN4-AN7 

The  high-order  analog  input  lines,  AN4-AN7  can  be 
used  as  digital  input  lines  for  falling  edge  detection. 

3.  Control  Lines 

Under  software  control,  each  line  of  Port  C  can  be 
configured  individually  to  provide  control  lines  for 
serial  interface,  timer  and  timer/counter. 

4.  Memory  Expansion 

In  addition  to  the  single-chip  operation  mode 
fxPD781 1  has  4  memory  expansion  modes.  Under 
software  control,  Port  D  can  provide  multiplexed 
low-order  address  and  data  bus  and  Port  F  can  pro- 
vide high-order  address  bus.  The  relation  between 
memory  expansion  modes  and  the  pin  configurations 
of  Port  D  and  Port  F  is  shown  in  the  table  that  follows. 


Memory  Expansion 

Port  Configuration 

None 

Port  D 
PortF 

I/O  Port 
I/O  Port 

256  Bytes 

Port  D 
PortF 

Multiplexed  Address/Data  Bus 
I/O  Port 

4K  Bytes 

PortD 
Port  F0-F3 
Port  F4-F7 

Multiplexed  Address/Data  Bus 
Address  Bus 
I/O  Port 

16K  Bytes 

PortD 
Port  F0-F5 
Port  F6-F7 

Multiplexed  Address/Data  Bus 
Address  Bus 
I/O  Port 

60K  Bytes 

PortD 
PortF 

Multiplexed  Address/Data  Bus 
Address  Bus 

Timers 

The  timer/event  counter  consists  of  two  8-bit  timers.  The 
timers  may  be  programmed  independently  or  may  be  cas- 
caded and  used  as  a  16-bit  timer.  The  timer  can  be  set  in 
software  to  increment  at  intervals  of  4  machine  cycles 
(1  (jls  at  12MHz  operation)  or  128  machine  cycles  (32(xs 
at  12MHz),  or  to  increment  on  receipt  of  a  pulse  at  Tv 

Timer/Event  Counter 

The  16-bit  multifunctional  timer/event  counter  can  be  used 
for  the  following  operations: 

Interval  timer 

External  event  timer 

Frequency  measurement 

Pulse  width  measurement 

Programmable  square-wave  output 


Timer  Block  Diagram 


c3/tio — £> 


8-bit 

Upcounter 


Comparator 


Timer 
Register  0 


8-bit 

Upcounter 


Comparator 


71 


Timer 
Register  1 


)PC4/T0 


Timer/Event 
Counter 


Serial 
Interface 


I  NTT, 


Notes:  1  CL  =  3/f  (250ns  12MHz  operation) 
f  System  clock  frequency  (MHz) 


4-54 


Block  Diagram  for  Timer/Event  Counter 


MPD781 0/7811 


pc5/ci  o- 


\        Internal  Bus  \ 


Timer/Event 
Counter  Register  1 


Timer/Event  Counter 
Capture  Register 


Timer/Event 
Counter  Upcounter 


Reset 
Control 


Comparator 


Timer/Event 
Counter  Register  0 


Edge 
Detect 


Notes:  CL  =  3/f  (250ns  12  MHz  operation) 
f  System  clock  frequency  (MHz) 


-CP, 
►CP0 


Interrupt 
Control 


PC6/C00 


PC^CO, 


8- Bit  A/D  Converter 

8  Input  Channels 

4  Conversion  Result  Registers 

2  Powerful  Operation  Modes 

Auto  Scan  Mode 

Channel  Select  Mode 
Successive  Approximation  Technique 
Absolute  Accuracy  ±1.5  LSB  ( ±  0.6%) 

Conversion  Range  0  ~  5V 

Conversion  Time  50  yis 

Interrupt  Generation 

Analog/Digital  Converter 

The  |xPD7810/7811  features  an  8-bit,  high-speed,  high 
accuracy  A/D  converter.  The  A/D  converter  comprises  a 
256-Resistor  Ladder  and  Successive  Approximation  Regis- 
ter (SAR).  There  are  four  conversion  result  registers 
(CR0-CR3).  The  8-channel  analog  input  may  be  operated 
in  either  of  two  modes.  In  the  select  mode,  the  conversion 
value  of  one  analog  input  is  sequentially  stored  in  CR0-CR3. 
In  the  scan  mode,  the  upper  four  channels  or  the  lower  four 
channels  may  be  specified.  Then  those  four  channels  will 
be  consecutively  selected  and  the  conversion  results 
stored  sequentially  in  the  four  conversion  result  registers. 


A/D  Converter  Block  Diagram 


AVCC  O" 
AVsS  °- 
VAREF  °" 


4-55 


|xPD7810/7811 

Interrupt  Structure 

There  are  11  interrupt  sources.  Three  are  external  interrupts 
and  8  are  internal.  These  11  interrupt  sources  are  divided 
into  6  priority  levels  as  shown  in  the  table  below. 


Interrupt 
Request 

Interrupt 

Type  of  Interrupt 

In/Ext 

IRQO 

4 

NMI  (Non-maskable  interrupt) 

External 

IRQ1 

8 

INTTO  (Coincidence  signal  from  timer  0) 
INTT1  (Coincidence  signal  from  timer  1) 

Internal 

IRQ2 

16 

INT1  (Maskable  interrupt) 
INT2  (Maskable  interrupt) 

External 

IRQ3 

24 

INTEO  (Coincidence  signal  from  timer/ 
event  counter) 

INTE1  (Coincidence  signal  from  timer/ 
event  counter) 

Internal 

IRQ4 

32 

INTEIN  (Falling  signal  of  C1  and  TO 
counter) 

INT  AO  (A/D  converter  interrupt) 

In/External 

IRQ5 

40 

INTSR  (Serial  receive  interrupt) 
INST  (Serial  send  interrupt) 

Internal 

NMI  < 
INTTO 
INTT1 
INT1  1 
INT2  < 
INTEO 
INTE1 
INTEIN 
INTAD 
INTSR 
INTST 

OV 
ER 
SB 

AN7-AN4 


TEST 
CONTROL 


FNM1 
SOFT1 


MASK 
REGISTER 


PRIORITY 
CONTROL 


INTERRUPT 
GENERATED 


Standby  Function 

The  liPD781 0/7811  offers  a  standby  function  that 
allows  the  user  to  save  up  to  32  bytes  of  RAM  with  back- 
up power  (VDD)  if  the  main  power  (Vcc)  fails.  On  powerup 
the  |xPD7811  checks  whether  recovery  was  made  from 
standby  mode  or  from  cold  start. 

Universal  Serial  Interface 

The  serial  interface  can  operate  in  any  of  three 
modes:  synchronous,  asynchronous,  and  I/O  interface. 
The  I/O  interface  mode  transfers  data  MSB  first  for  ease 
of  communication  with  certain  peripheral  devices.  Syn- 
chronous and  asynchronous  modes  transfer  data  LSB  first. 
Synchronous  operation  offers  two  modes  of  data  reception. 
In  the  search  mode,  data  is  transferred  one  bit  at  a  time 
from  serial  register  to  receive  buffer.  This  allows  a  software 
search  for  a  sync  character.  In  the  nonsearch  mode,  data 
transfer  from  serial  register  to  transmit  buffer  occurs  8  bits 
at  a  time. 


Universal  Serial  Interface  Block  Diagram 

INTERNAL  BUS 


RECEIVE 
BUFFER 

SERIAL  REGISTER 
(S-P) 

j 

TRANSMIT 
BUFFER 


SERIAL  REGISTER 
(P-S) 


TRANSFER 
CONTROL 


SR 

INTERRUPT 


TT 


TRANSFER 
CONTROL 


ST 

INTERRUPT 


PC2/SCK  O- 


t 


•  INTERNAL  CLOCK 


Zero-crossing  Detector 

The  INT.,  and  INT2  terminals  (used  common  to  Tl  and  PC3) 
can  be  used  to  detect  the  zero-crossing  point  of  slow  mov- 
ing AC  signals.  When  driven  directly,  these  pins  respond  as 
a  normal  digital  input. 

To  utilize  the  zero-cross  detection  mode,  an  AC  signal  of 
approximately  1-3V  AC  peak-to-peak  magnitude  and  a 
maximum  frequency  of  1kHz  is  coupled  through  an  external 
capacitor  to  these  pins. 

For  the  IN^  pin,  the  internal  digital  state  is  sensed  as  a 
zero  until  the  rising  edge  crosses  the  DC  average  level, 
when  it  becomes  a  one  and  \NTA  interrupt  is  generated. 
For  the  INT2  pin,  the  state  is  sensed  as  a  one  until  the  fall- 
ing edge  crosses  the  DC  average  level,  when  it  becomes 
a  zero  and  INT2  interrupt  is  generated. 
The  zero-cross  detection  capability  allows  the  user  to  make 
the  50-60Hz  power  signal  the  basis  for  system  timing  and 
to  control  voltage  phase  sensitive  devices. 

Zero-crossing  Detection  Circuit 

I 


I  INT, 
^  INTa(PC3) 


OH 


4 


-56 


f.PD7810/7811 


Operand  Format/Description  

Format  Description 


r  V,  A,  B,  C,  D,  E,  H,  L 

r1  EAH,  EAL,  B,  C,  D,  E,  H,  L 

x2  A,  B,  C  

sr  PA,  PB,  PC,  PD,PF,  MKH  MKL,  ANM,  SMH,  SML,  EOM,  ETMM,  TMM,  MM,MCC,  MA,  MB,  MC  MF,  TXB,  TMO,  TM1 

sr1  PA,  PB,  PC,  PD,  PF,  MKH,  MKL,  ANM,  SMH,  EOM,  TMM,  RXB,  CRO,  CR1 ,  CR2,  CR3 

sr2  PA,  PB,  PC,  PD,  PF,  MKH,  MKL,  ANM,  SMH,  EOM,  TMM 

sr3  ETMO,  ETM1 

sr4  ECNT,  ECPT   


rp  SP,  B,  D,  H 

rp1  V,  B,  D,  H,  EA 

rp2  SP,  B,  D,  H,  EA 

rp3  B,  D,H  

rpa  B,D,H,D  +  ,H  +  ,D-,H- 

rpal  B,  D,  H 

rpa2  B,  D,  H,  D  +  ,  H  +  ,  D-,  H-,  D  +  byte,  H  +  A,  H  +  B,  H  +  EA,  H  +  byte 

rpa3  D,  H,  D  +  ,  H+  +  ,  D  +  byte,  H  +  A,  H  +  B,  H  +  EA,  H  +  byte  

wa  8-bit  immediate  data  

word  1 6-bit  immediate  data 

byte  8-bit  immediate  data 

bit  3-bit  immediate  data  

i  CY,  HC,  Z  

irf  FNMI,  FTP,  FT1,  F1,  F2,  FEO,  FE1,  FEIN,  FAD,  FSR,  FST,  ER,  OV,  AN4,  AN5,  AN6,  AN7,  SB 


Remarks 


1 .  sr-sr4  (special  register) 


PA 

=  Port  A 

ECNT 

=  Timer/Event 

PB 

=  Port  B 

Counter  Upcounter 

PC 

=  Port  C 

ECPT 

=  Timer/Event 

PD 

=  Port  D 

Counter  Capture 

PF 

=  Port  F 

ETMM 

=  Timer/Event 

MA 

=  Mode  A 

Counter  Mode 

MB 

=  Mode  B 

EOM 

=  Timer/Event 

MC 

=  Mode  C 

Counter  Output  Mode 

MCC 

=  Mode  Control  C 

ANM 

=  A/D  Channel  Mode 

MF 

=  ModeF 

CRO 

=  A/D  Conversion 

MM 

=  Memory  Mapping 

to 

Result  0-3 

TMO 

=  Timer  Register  0 

CR3 

TM1 

=  Timer  Register  1 

TXB 

=  Tx  Buffer 

TMM 

=  Timer  Mode 

RXB 

=  Rx  Buffer 

ETMO 

=  Timer/Event 

SMH 

=  Serial  Mode  High 

Counter  Register  0 

SML 

=  Serial  Mode  Low 

ETM1 

=  Timer/Event 

MKH 

=  Mask  High 

Counter  Register  1 

MKL 

=  Mask  Low 

2.  rp-rp3  (register  pair) 

SP  = 

Stack  Pointer 

H  = 

HL 

B  = 

BC 

V  = 

VA 

D  = 

DE 

EA  = 

Extended  Accumulator 

3.  rpa -rpa 3  (rp  addressing) 


B 

D+  + 

=  (DE)+  + 

D 

H+  + 

=  (HL)+  + 

H 

D  +  byte 

=  (DE  +  byte) 

D  + 

H  +  A 

=  (HL  +  A) 

H  + 

=  (HL)  + 

H  +  B 

=  (HL  +  B) 

D- 

=  (DE)" 

H  +  EA 

=  (HL  +  EA) 

H- 

=  (HL)- 

H  +  byte 

=  (HL  +  byte) 

4.  f  (flag) 


CY  =  Carry  HC  =  Half  Carry  Z  =  Zero 


5.  irf  (interrupt  flag) 


FNMI 

=  INTFNMI 

FSR 

=  INTFSR 

FTO 

=  INTFTO 

FST 

=  INTFST 

FT1 

= INTFT1 

ER 

=  Error 

F1 

=  INTF1 

OV 

=  Overflow 

F2 

=  INTF2 

AN4 

=  Analog  Input  4-7 

FEO 

=  INTFEO 

to 

FE1 

=  INTFE1 

AN7 

FEIN 

=  INTFEIN 

SB 

=  Standby 

FAD 

=  INTFAD 

4-57 


MPD7810/7811 


Instruction  Groups 

8-bit  Data  Transfer 


OP  Code 

Condition 

Mnem 

onic 

Operand 

B1 

B2  B3 

B 

4 

State 

Operation 

r1,  A 

4 

M  ^A 

A,  r1 

nnnniTTT 

4 

A«-r1 

MOV 

sr,  A 

UlUUl 1  U  I 

1  lOS^gS^So 

10 

sr^A 

A,  sr1 

01001100 

1  1  SsS4S3S2SiS0 

10 

A^sM 

r,  (word) 

01110000 

OHOIRjR^o  LowAdrs 

High  Adrs 

17 

r  <-  (word) 

(word),  r 

01 1 10000 

Oim^RtRg  LowAdrs 

High  Adrs 

17 

(word)  <-  r 

MVI 

* 

r,  byte 

01101  R2R-)R0 

Data 

7 

r <-  byte 

String  skip,  other  r  =  A  or  L 

sr2,  byte 

01100100 

S30  0  0  0  S2S1S0  Data 

14 

sr2  *-  byte 

MVIW 

* 

wa,  byte 

01 1 10001 

Offset  Data 

13 

(V,  wa)  *-  byte 

MVIX 

rpal.byte 

OIOOIOAtAq 

Data 

10 

(rpal)^byte 

STAW 

wa 

011 00011 

Offset 

10 

(V,  wa) «-  A 

LDAW 

wa 

00000001 

Offset 

10 

A<-(V,wa) 

STAX 

rpa2 

A30  1  1  1  AjA^q 

Data*® 

7/13 

(rpa2)^A 

LDAX 

rpa2 

A30 1  0 1  AjA^q 

Data*© 

7/13 

A«-(rpa2) 

EXX 

01001000 

10101111 

8 

B~B',C~C',D<->D' 
E~E',H«->H',L^L' 

EXA 

01001000 

10101100 

8 

V,A~V',A',EA~EA' 

EXH 

01001000 

10101110 

8 

H,  L<h>  H',  L' 

16-bit  Data  Transfer 

BLOCK 

D  + 

00010000 

13 
(C  +  1) 

(DE)  +  ^(HL)  +  ,C^C  -  1 
End  if  borrow 

D- 

00010001 

13 
(C  +  1) 

(DE)  -  *-(HL)-,C«-C  -  1 
End  if  borrow 

rp3,  EA 

lOIIOIP^o 

4 

rp3u  *-  EAL,  rp3H  «-  EAH 

DMOV 

EA,  rp3 

101  001  P^,, 

4 

EAL <-  rp3L,  EAH  «-  rp3H 

sr3,  EA 

01001000 

1101001U0 

14 

sr3*-EA 

EA,  sr4 

1  IOOOOV^q 

14 

EA«-sr4 

SBCD 

(word) 

01 1 10000 

0001  1  1  10  Low 

Adrs 

High 

Adrs 

20 

(word) <-  C,  (word  +  1) <-  B 

SDED 

(word) 

00101110 

20 

(word) <-  E,  (word  +  1)  <-  D 

SHLD 

(word) 

00111110 

20 

(word)  ^L,  (word  +  1)<-H 

SSPD 

(word) 

,  00001110 

20 

(word)  <-  SPL,  (word  +  1) <-  SPH 

STEAX 

rpa3 

01001 

000 

lOOICsCa^Co  Data 

*© 

14/20 

(rpa3) «-  EAL,  (rpa3  +  1)  <-  EAH 

LBCD 

word 

01110 

000 

0001  1  1  1  1  Low 

Adrs  High 

Adrs 

20 

C «-  (word),  B  <-  (word  +  1) 

LDED 

word 

001011 1 1 

20 

E  <-  (word),  D  «-  (word  +  1) 

LHLD 

word 

0011 1111 

20 

L  «-  (word),  H  *-  (word  +  1) 

LSPD  word 

00001111 

20 

SPL  «-  (word),  SPH  «-  (word  +  1) 

LDEAX 

rpa3 

01001 

000 

100  0C3C2C1C0  Data 

*© 

14/20 

EAL  *-(rpa3),  EAH  *-(rpa3  +  1) 

PUSH 

rp1 

1  01  1  OQ^Qq 

13 

(SP-1)«-rp1H«-(SP-2)-rp1L 
SP«-SP  -  2 

POP 

rp1 

IOIOOQ^Qq 

10 

rp1u«-(SP)>rp1H<-(SP  +  1) 
SP^-SP  +  2 

LXI 

rp2,  word 

OP^PqOI  00 

Low  Byte 

High  Byte 

10 

rp2  <-  (word) 

String  skip  when  rp2  =  H 

8-bit  Arithmetic  (Register) 

TABLE 

01001000 

10101000 

17 

C<-(PC  +  3  +  A) 
B^-(PC  +  3  +  A  +  1) 

ADD 

A,r 

01  100 

000 

1  1  OOORaRiRo 

8 

A  ^  A  +  r 

r,A 

01  OOORjR^o 

8 

r<-r  +  A 

ADC 

A,r 

1  1  01  ORjR^o 

8 

A^-A  +  r  +  CY 

r,  A 

01  01  0R2R1R0 

8 

r  <-  r  +  A  +  CY 

ADDNC 

A,  r 

1  01  00R2R1R0 

8 

A <  A  +  r 

No  Carry 

r.  A 

001  OORjR^o 

8 

r  <—  r  +  A 

No  Carry 

SUB 

A,r 

1  1  1  OOR^R,, 

8 

A  <-■  A  -  r 

r,  A 

011  OORzR^o 

8 

r«-r  -  A 

SBB 

A,  r 

1  1  1  1  OR^Rq 

8 

A  <  A  -  r  -  CY 

r,A 

01  1  1  ORaR^o 

8 

r «-  r  -  A  -  CY 

SUBNB 

A,  r 

IOHORjR^o 

8 

A  <  A  -  r 

No  Borrow 

r,A 

001  10R2RiR0 

8 

r«-r  -  A 

No  Borrow 

ANA 

A,  r 

10  0  01  RjRtRo 

8 

A*-A  Ar 

r,A 

00  001  RaR^o 

8 

r «-  r  A  A 

ORA 

A,  r 

10011  R^R,, 

8 

A^AVr 

r,A 

0001  1  R2RiR0 

8 

r«-rVA 

XRA 

A,  r 

1  001  OR^Rq 

8 

A^-AVr 

r,A 

OOOIOR^Ro 

8 

r^-rVA 

GTA 

A,  r 

1  01  01  Rj^Ro 

8 

A  -  r  -  1 

No  Borrow 

r,  A 

0  0101  R2R-|R0 

8 

r  -  A  -  1 

No  Borrow 

4-58 


|iPD7810/7811 


Instruction  Groups  (Cont.) 

8-bit  Arithmetic  (Register)  (Cont.) 


OP  Code 

Skip 
Condition 

Mnemonic 

Operand 

B1 

B2                            B3  B4 

State 

Operation 

LTA 

A,  r 

011 00000 

10111  R2RiR0 

8 

A  -  r 

Borrow 

r,A 

00111  R^Rq 

8 

r  -  A 

Borrow 

NEA 

A,  r 

1  1 1  01  R2RiR0 

8 

A  -  r 

No  Zero 

r,A 

01  1  01  R2RiR0 

8 

r  -  A 

No  Zero 

EQA 

A,r 

11111  R2RiR0 

8 

A  -  r 

Zero 

r,  A 

01111  R^Rq 

8 

r  -  A 

Zero 

ONA 

A,  r 

1  10  01  R^Rq 

8 

AAR 

No  Zero 

OFFA 

A,r 

11011  R^Rq 

8 

AAR 

Zero 

8-bit  Arithmetic  (Memory) 

ADDX 

rpa 

01110 

000 

1  1  OOOA^Aq 

11 

A  <—  A  +  (rpa) 

ADCX 

rpa 

1  1  01  OA^Aq 

11 

A  +-  A  +  (rpa)  +  CY 

ADDNCX 

rpa 

1  01  OOA^Aq 

11 

A  *-  A  +  (rpa) 

No  Carry 

SUBX 

rpa 

1  1  1  OOAa^Ao 

11 

A «-  A  -  (rpa) 

SBBX 

rpa 

1111  OAaA^o 

11 

A<-A  -  (rpa)  -  CY 

SUBNBX 

rpa 

1  01  1  OAjAtAq 

11 

A «-  A  -  (rpa) 

No  Borrow 

ANAX  rpa 

1  0  001  A^Aq 

11 

A «-  A  -  (rpa) 

ORAX 

rpa 

10011  A2A1A0 

11 

A  *-  A  V  (rpa) 

XRAX 

rpa 

1  001  OA^Aq 

11 

A  «-  A  V  (rpa) 

GTAX 

rpa 

10101  A^Aq 

11 

A  -  (rpa)  -  1 

No  Borrow 

LTAX 

rpa 

10111  A2A1A0 

11 

A  -  (rpa) 

Borrow 

Immediate  Data 

NEAX 

rpa 

11101  AjA^q 

11 

A  -  (rpa) 

No  Zero 

EQAX 

rpa 

11111  A2A1A0 

11 

A  -  (rpa) 

Zero 

ONAX 

rpa 

110  01  Aj^Ao 

11 

A^(rpa) 

No  Zero 

OFFAX 

rpa 

11011  A^Aq 

11 

A -(rpa) 

Zero 

A,  byte 

010001 1 0 

«-  Data  -» 

7 

A <-  A  +  byte 

ADI 

r,  byte 

01 1 10100 

OIOOORj^Rq  Data 

11 

r  <—  r  +  byte 

sr2,  byte 

0110 

SalOOOS^Sj,  i 

20 

sr2  «-  sr2  +  byte 

A,  byte 

01010110 

<-  Data  -> 

7 

A     A  +  byte  +  CY 

ACI 

r,  byte 

01110100 

OIOIOR^Rq  Data 

11 

r  *-  r  +  byte  +  CY 

sr2,  byte 

0110 

SalOIOS^So  I 

20 

sr2  —  sr2  +  byte  +  CY 

A,  byte 

00100110 

«-  Data  -» 

7 

A  <—  A  +  byte 

No  Carry 

ADINC 

r,  byte 

01 1 101 00 

OOIOOR^Rq  Data 

11 

r  —  r  +  byte 

No  Carry 

sr2,  byte 

0110 

SgOIOOSaS^o  i 

20 

sr2  «-  sr2  +  byte 

No  Carry 

A,  byte 

01100110 

<-  Data  -> 

7 

A «-  A  -  byte 

SUI 

r,  byte 

01  1  10100 

OIIOORaR^o  Data 

11 

r «-  r  -  byte 

sr2,  byte 

0110 

SgHOOS^So  I 

20 

sr2  <-  sr2  -  byte 

A,  byte 

01110110 

*-  Data  -♦ 

7 

A  «-  A  -  byte  -  CY 

SBI 

r,  byte 

01110100 

OHIORjR^o  Data 

11 

r  —  r  -  byte  -  CY 

sr2,  byte 

0110 

SgHIOS^So  I 

20 

sr2  <-  sr2  -  byte  -  CY 

A,  byte 

001 101 10 

Data 

7 

A <-  A  -  byte 

No  Borrow 

SUINB 

r,  byte 

01110100 

0  0110  R2RiR0 

11 

r  —  r  -  byte 

No  Borrow 

sr2,  byte 

0110 

1 

S301  1  OS^Sq 

20 

sr2  «-  sr2  —  byte 

No  Borrow 

A,  byte 

000001 1 1 

Data 

7 

A  <— A  \  byte 

ANI 

r,  byte 

01110100 

00001  Rj^Rq  Data 

11 

r<-r  \byte 

sr2,  byte 

011 00100 

SaOOOIS^So  i 

20 

sr2*-sr2  \byte 

A,  byte 

000101 1 1 

Data 

7 

A  *-  A  V  byte 

ORI 

r,  byte 

01110100 

OOOHR^Rq  Data 

11 

r  <-  r  V  byte 

sr2,  byte 

0110 

i 

SaOOIISaS^o  J 

20 

sr2  <-  sr2  V  byte 

A,  byte 

000101 10 

Data 

7 

A  <-  A  V  byte 

XRI 

r,  byte 

01110100 

OOOIOR^Rq  Data 

11 

r  —  r  V  byte 

sr2,  byte 

0110 

1 

S3001  0S2S1S0  i 

20 

sr2  —  sr2  V  byte 

A,  byte 

00100111 

Data 

7 

A  -  byte  -  1 

No  Borrow 

GTI 

r,  byte 

01110100 

OOlOIR-^Ro  Data 

11 

r  -  byte  -  1 

No  Borrow 

sr5,  byte 

0110 

1 

SaOIOISzS^o  | 

14 

sr5  -  byte  -  1 

No  Borrow 

A,  byte 

00110111 

Data 

7 

A  -  byte 

Borrow 

LTI 

r,  byte 

01110100 

OOmRjRiRo  Data 

11 

r  -  byte 

Borrow 

sr5,  byte 

0110 

I 

SaOIHS^So  1 

14 

sr5  -  byte 

Borrow 

A,  byte 

01100111 

*-  Data  -> 

7 

A  -  byte 

No  Zero 

NEI 

r,  byte 

01110100 

01101R2R1R0  Data 

11 

r  -  byte 

No  Zero 

sr5,  byte 

0110 

i 

S31  1  0  1  SzS^q  i 

14 

sr5  -  byte 

No  Zero 

A,  byte 

01110111 

«-  Data 

7 

A  -  byte 

Zero 

EQI 

r,  byte 

01110100 

OIHIR^Ro  Data 

11 

r  -  byte 

Zero 

sr5,  byte 

0110 

1 

S31  1  1  1  SaS^o  i 

14 

sr5  -  byte 

Zero 

4-59 


,.PD781 0/7811 


Instruction  Groups  (Cont.) 

Immediate  Data  (Cont.) 


Mnemonic 

Operand 

B1 

B2 

B3 

B4 

State 

Operation 

SKIP 

Condition 

A,  byte 

010001 1 1 

—  Data 

7 

A  \  byte 

No  Zero 

ONI 

r,  byte 

01110100 

01001R2R1R0  Data 

11 

r  \  byte 

No  Zero 

sr5,  byte 

0110 

SglOOISz^So  | 

14 

sr5  \  byte 

No  Zero 

A,  byte 

01010111 

—  Data 

7 

A  \  byte 

Zero 

OFFI 

r,  byte 

01110100 

01011R2RiR0  Data 

11 

r  \  byte 

Zero 

sr5,  byte 

0110 

J 

S31  0  1  1  S 

2S,S0  I 

14 

sr5  \  byte 

Zero 

Working  Register 

ADDW 

wa 

01110 

100 

1  10000 

0  0  Off 

set 

14 

A  —  A  +  (V,  wa) 

ADCW  wa 

1101 

14 

A  —  A  +  (V,  wa)  +  CY 

ADDNCW  wa 

1010 

14 

A  —  A  +  (V,  wa) 

No  Carry 

SUBW 

wa 

1110 

14 

A  —  A  -  (V,  wa) 

SBBW  wa 

1111 

14 

A  —  A  -  (V,  wa)  -  CY 

SUBNBW 

wa 

1011  1 

14 

A  —  A  -  (V,  wa) 

No  Borrow 

ANAW 

wa 

1  0001000 

14 

A  —  A  \  (V,  wa) 

ORAW 

wa 

1001  i 

14 

A  —  A  V  (V,  wa) 

XRAW 

wa 

01110 

100 

10  010  0  0  0  Offset 

14 

A  —  A  V  (V,  wa) 

GTAW 

wa 

10101000 

14 

A  -  (V,  wa)  -  1 

No  Borrow 

LTAW  wa 

1011 

14 

A  -  (V,  wa) 

Borrow 

NEAW 

wa 

1110 

14 

A  -  (V,  wa) 

No  Zero 

EQAW 

wa 

1111 

14 

A  -  (V,  wa) 

Zero 

ONAW 

wa 

1  100 

14 

A  \  (V,  wa) 

No  Zero 

OFFAW 

wa 

1101 

14 

A  \  (V,  wa) 

Zero 

ANIW 

wa,  byte 

00000101 

-Off 

set 

Da 

ta 

19 

(V,  wa)  —  (V,  wa)  [byte] 

ORIW 

wa,  byte 

0001 

19 

(V,  wa) «-  (V,  wa)  V  byte 

GTIW 

wa,  byte 

0010 

13 

(V,  wa)  -  byte  -  1 

No  Borrow 

LTIW 

wa,  byte 

0011 

13 

(V,  wa)  -  byte 

Borrow 

NEIW 

wa,  byte 

0110 

13 

(V,  wa)  -  byte 

No  Zero 

EQIW 

wa,  byte 

0111 

13 

(V,  wa)  -  byte 

Zero 

ONIW 

wa,  byte 

0100 

13 

(V,  wa)  V  byte 

No  Zero 

OFFIW 

wa,  byte 

0101 

13 

(V,  wa)  \  byte 

Zero 

16-bit  Arithmetic 

EADD 

EA,r2 

0111 0000 

01 OOOOR^q 

11 

EA  -  EA  +  r2 

DADD 

EA,  rp3 

0 

100 

1100011 

JiPo 

11 

EA «-  EA  +  rp3 

DADC 

EA,  rp3 

1101 

11 

EA  «-  EA  +  rp3  +  CY 

DADDNC 

EA,  rp3 

1010 

11 

EA  —  EA  +  rp3 

No  Carry 

ESUB 

EA,r2 

0000 

01  1  OOOF^Rq 

11 

EA  -  EA  -  r2 

DSUB 

EA,  rp3 

01110100 

1110011 

JiPo 

11 

EA  —  EA  -  rp3 

DSBB 

EA,  rp3 

1111 

11 

EA  -  EA  -  rp3  -  CY 

DSUBNB 

EA,  rp3 

1011 

11 

EA  -  EA  -  rp3 

No  Borrow 

DAN 

EA,  rp3 

1  0001  1  PjPo 

11 

EA  —  EA  -  rp3 

DOR 

EA,  rp3 

1001 

) 

11 

EA  —  EA  V  rp3 

DXR 

EA,  rp3 

100101 P^o 

11 

EA  —  EA  V  rp3 

DGT 

EA,  rp3 

1010111 

»iPo 

11 

EA  -  rp3  -  1 

No  Borrow 

DLT 

EA,  rp3 

1011 

11 

EA  -  rp3 

Borrow 

DNE 

EA,  rp3 

1110 

11 

EA  -  rp3 

No  Zero 

DEQ 

EA,  rp3 

1111 

11 

EA  -  rp3 

Zero 

DON 

EA,  rp3 

1  100 

11 

EA  A  rp3 

No  Zero 

DOFF 

EA,  rp3 

1101 

11 

EA  A  rp3 

Zero 

Multiply/Divide 

MUL 

r2 

01001000 

001011 R^q 

32 

EA  <—  A  X  r2 

DIV 

r2 

1 

0011 

4 

59 

EA  —  EA  -  r2,  r2  —  Surplus 

Increment/Decrement 

INR 

r2 

OIOOOOR^q 

4 

r2  -  r2  +  1 

Carry 

INRW 

wa 

00100000 

—  Offsets 

16 

(V,  wa)  -  (V,  wa)  +  1 

Carry 

INX 

rp 

OOP^qOOI  0 

7 

rp  —  rp  +  1 

EA 

10101000 

7 

EA  <-  EA  +  1 

DCR 

r2 

01 01 OOR^q 

4 

r2  —  r2  -  1 

Borrow 

DCRW 

wa 

001 1 0000 

<-  Offset-* 

16 

(V,  wa)  —  (V,  wa)  -  1 

Borrow 

DCX 

rp 

OOP^qOOI  1 

7 

rp  -  rp  -  1 

EA 

10101001 

7 

EA  -  EA  -  1 

4-60 


I.PD7810/7811 


Instruction  Groups  (Cont.) 

Others 


Mnemonic 

Operand 

B1 

B2 

B3  B4 

State 

Operation 

Condition 

DAA 

01100001 

4 

Decimal  Adjust  Accumulator 

STC 

01001000 

00101011 

8 

CY  -  1 

CLC 

1 

00101010 

8 

CY  -  o 

CMC 

01001 000 

10101010 

8 

CY  —  CY 

~~NEGA 

1 

00111010 

8 

A-  A  +  1 

Rotate  and  Shift 

RLD 

01001000 

00111 000 

17 

Rotate  Left  Digit 

RRD 

f  1001 

17 

Rotate  Right  Digit 

RLL 

r2 

01001 

000 

00 

1101 R^q 

8 

r2m+1  —  r2m,  r20  —  CY, 
CY  —  r27 

RLR 

r2 

0  0  RtRq 

8 

r2m..,~  r2m,r27<  CY, 
CY  -  r20 

SLL 

r2 

00 

1001 R^q 

8 

r2m  +  1  ^r2m>  r20  —  0, 

CY  —  r27 

SLR 

r2 

0  0  R^ 

8 

r2m_1-r2m,  r27-0, 
CY  -  r20 

SLLC 

r2 

00 

00  01 R^q 

8 

r2m  +  1  ^r2m,  r20-0, 
CY  —  r27 

Carry 

SLRC 

r2 

OORtRq 

8 

r2m_1  —  r2m,  r27  —  0, 
CY  -  r20 

Carry 

DRLL 

EA 

1  0 

110100 

8 

EAn  +  1  —  EAn,  EA0  —  CY, 
CY  -  EA15 

DRLR 

EA 

0000 

8 

EAn_1  —  EAn,  EA15-CY, 
CY  -  EA0 

DSLL 

EA 

1  0 

100100 

8 

EAn  +  1  —  EAn,  EA0  — 0, 
CY-EA15 

DSLR 

EA 

r  oooo 

8 

EA^-EA,,,  EA15-0, 

Jump 

JMP 

word 

01010100 

— 

Low  Adrs  — 

High  Adrs 

10 

PC  —  (word) 

JB 

00100001 

4 

PCH  -  B,  PCL  -  C 

JR 

word 

1 1 

—  jdisp  1  — 

10 

PC  —  PC  +  1  +  jdisp  1 

JRE 

word 

0100111 

jdisp - 

10 

PC  —  PC  +  2  +  jdisp 

JEA 

01001000 

00101000 

8 

PC  — EA 

Call 

CALL 

word 

01000000 

—  Low  Adrs  — 

High  Adrs 

16 

(SP-1)-(PC  +  3)H, 
(SP  -  2) -(PC  +  3)L 
PC  —  (word),  SP  —  SP  -  2 

CALB 

01  001  000 

00101001 

17 

(SP  -  1)-(PC  +  2)H, 
(SP  -  2) -(PC  +  2)L 
PCH— B,  SP  — SP  -  2 

CALF 

word 

01111 

fa- 

13 

(SP-1)-(PC  +  2)H, 
(SP  -  2) -(PC  +  2)L 
PCi  5-11  -00001, 
PC10_o  —  fa,SP-SP  -  2 

CALT 

word 

1  00— ta- 

16 

(SP-1)-(PC  +  1)H, 
(SP  -  2) -(PC  +  1)L 
PCL  — (128  +  2ta),  PCH  — 
(129  +  2ta),  SP  —  SP  -  2 

SOFTI 

01  1  1  001  0 

16 

(SP  -  1)  — PSW,(SP  -  2)  — 
(PC  +  1)H,(SP-3)-(PC  +  1)L, 
PC  -  0060H,  SP  -  SP  -  3 

Return 

RET 

1  0 

1  1  1000 

10 

PC-(SP),PCH-(SP  +  1) 
SP-SP  +  2 

RETS 

I  1001 

10 

PCL-(SP),  PCH-(SP  +  1) 
SP  —  SP  +  2,  PC  —  PC  +  n 

RETI 

01100010 

13 

PCL-(SP),  PCH^(SP  +  1) 
PSW  — (SP  +  2),  SP-SP  +  3 

Uncondi- 
tional 
Skip 

Skip 

BIT 

bit,  wa 

01011 

BzB^o 

-  Offset- 

10 

Bit  Test 

(V,  wa) 
bit  =  1 

4-61 


MPD781 0/7811 


Instruction  Groups  (Cont.) 

CPU  Control 

OP  Code 

Skip 
Condition 

Mnemonic            Operand  B1 

B2  B3 

B4  State 

Operation 

SK                           f  01001 

000 

00001  F2F1F„ 

8 

Skip  iff  =  1 

f  =  1 

SKN  f 

0001  | 

8 

Skip  iff  =  0 

f  =  0 

SKIT  irf 

01  OI4I3I2I1I0 

8 

Skip  if  irf  =  1 ,  then  reset  irf 

irf  =  1 

SKNIT  irf 

011  I4I3I2M0 

8 

Skip  if  irf  =  0 
Reset  irf,  if  irf  =  1 

irf  =  0 

NOP  00000000 

4 

No  Operation 

El  10101010 

4 

Enable  Interrupt 

Dl  10111010 

4 

Disable  Interrupt 

HLT                                               010  01  0  0  0 

00111011 

11 

Halt 

Notes:  *©  B2(Data)  rpa2  =  D  +  byte,  H  +  byte 
*©  B3  (Data)  rpa3  =  D  +  byte,  H  +  byte 

*®  Right  side  of  slash  (/)  in  states  indicates  case  rpa2,  rpa3  =  D  +  byte,  H  +  A,  H  +  B,  H 
*©  In  the  case  of  skip  condition,  the  idle  states  are  as  follows 

1  -byte  instruction  4  states       2-byte  instruction  (with  *)  7  states 

2-  byte  instruction  8  states       3-byte  instruction  (with  *)  1 0  states 

3-  byte  instruction  11  states      4-byte  instruction  14  states 


Absolute  Maximum  Ratings* 

Ta  =  25°C 


Power  Supply  Voltages,  Vcc 

-0.5V  to  +7.0V 

VDD 

-0.5V  to  +7.0V 

AVCC 

-0.5V  to  +7.0V 

Input  Voltage,  V, 

-0.5V  to  +7.0V 

Output  Voltage,  VG 

-0.5V  to  +7.0V 

Reference  Input  Voltage,  VAREF 

-0.5V  to  +7.0V 

Operating  Temperature,  Tqpt 

10MHz  <fXTAL<  12MHz 

-10°Cto  +70°C 

fxTAL  —  10MHz 

-40°C  to  85°C 

Storage  Temperature,  TSTG 

-65°C  to  +150°C 

*COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cau§e 
permanent  damage.  The  device  is  not  meant  to  be 
operated  under  conditions  outside  the  limits  described 
in  the  operational  sections  of  this  specification.  Expo- 
sure to  absolute  maximum  rating  conditions  for 
extended  periods  may  affect  device  reliability. 


EA,  H  +  byte 


Operating  Conditions 


Parameter 
Osc.  Freq. 

Ta 

Vcc,  AVCC 

10MHs<fxTALs12MHz 

-10°Cto  +70°C 

+  5.0V  ±  5% 

Wal  ^  10MHz 

-40°Cto  85°C 

+  5.0V  ±  10% 

Capacitance 

Ta  =  25°C;Vcc  =  VDD  =  Vss 

=  ov 

Limits 

Test 
Conditions 

Parameter        Symbol  M 

in      Typ  Max 

Unit 

Capacitance  C, 

10 

PF 

Afc  =  1MHz 

Output  Capacitance  C0 

20 

PF 

Unmeasured  pin 

I/O  Capacitance  C,0 

20 

PF 

returned  to  0V. 

DC  Characteristics 

Ta  =  -10  C  to  +  70  C;  Vcc  =  -5.0V  ±  5%;  Vss  =  OV; 
Vcc  -  0.8V  <VDD<  Vcc 


Limits 

Parameter  Symbol 

Min 

Typ 

Max 

Unit 

Test  Conditions 

Input  Low  Voltage  V,L 

0 

0.8 

V 

V,H1 

20 

Vcc 

V 

All  except  SCK,  RESET 
and  X1 

V|H2 

0.8VCC 

Vcc 

V 

SCK,  X1 

Input  High  Voltage 

VIH3 

0.8VDD 

Vcc 

V 

RESET 

Output  Low  Voltage  V0L 

0.45 

V 

l0L  =  2.0mA 

Output  High  Voltage  V0H 

2.4 

V 

l0H  =  -200|xA 

Input  Current  l( 

±200 

HA 

INT1t  Tl  (PC3); 

+  0.45V  <VIN<VCC 

Input  Leakage  lLI 
Current 

±10 

All  except  INT,,  Tl  (PC3) 
0V<VIN<Vcc 

Output  Leakage  , 
Current  'L0 

±10 

pA 

+  0.45V  <V0<Vcc 

VDD  Supply  Current  lDD 

1.5® 

3.5 

mA 

Ta  =  -40°Cto  +85°C 

Vcc  Supply  Current  lcc 

110® 

220 

mA 

Ta  =  -40°Cto  +85°C 

Note:  ©  Ta  =  25°C,  Vcc  =  VDD  =  +  5  0V 


4-62 


MPD781 0/7811 


AC  Characteristics 

Ta  =  -10°Cto70°C;  Vcc  =  +  5.0V  ±  5%;  Vss  =  0V; 
Vcc  -0.8V  <  VDD<  Vcc 

Read!  Write  Operation  


Limits 

fXTAL  =  10MHz  f 

XTAL  - 

12  MHz 

Test 

Parameter 

Symbol 

Min 

Max 

Min 

Max 

Unit  Conditions 

X1  input  Cycle  Time 

*CYC 

100 

83 

ns 

Address  Setup 
to  ALE  i 

t.. 
lAL 

100 

65 

ns 

Address  Hold 
after  ALE  1 

tLA 

70 

50 

ns 

Address  to  RD  j 
Delay  Time 

*AR 

200 

150 

ns 

RD  i  to  Address 
Floating 

Wr 

20 

20 

ns 

Address  to 
Data  Input 

*AD 

480 

360 

ns 

ALE  i  to  Data  Input 

ti-DR 

300 

215 

ns 

RD  i  to  Data  Input 

*RD 

250 

180 

ALE  |  toRD  | 
Delay  Time 

tLR 

50 

35 

ns 

Data  Hold  Time 
toRD  t 

*RDH 

0 

0 

ns 

RD  t  to  ALE  t 
Delay  Time 

tRL 

150 

115 

ns 

RD  Width  Low 

*RR 

350 

280 

Data 
ns  Read 

650 

530 

OP  Code 
ns  Fetch 

ALE  Width  High 

*LL 

160 

125 

ns 

Address  to 
WR  1  Delay 

*AW 

200 

150 

ns 

ALE  1  to 
Data  Output 

t|_DW 

210 

195 

ns 

WR  i  to  Data  Output  tWD 

130 

100 

ns 

ALE  |  to 
WR  1  Delay 

*LW 

50 

35 

ns 

Data  Setup  Time 
toWR  t 

tDw 

300 

230 

ns 

Data  Hold  Time 
toWR  t 

*WDH 

130 

95 

ns 

WR  f  to  ALE  | 
Delay  Time 

lWL 

150 

115 

ns 

WR  Width  Low 

350 

280 

ns 

Note:  ©  Load  capacitance 

CL  = 

50pF 

Serial  Operation 

Parameter 

Symbol  Min 

Typ 

~Ma7 

Unit 

Test  Conditions 
 — — °"  '  '°"S 

1 

n,s 

SCK  © 

SCK  Cycle  Time 

*CYK 

500 

ns 

Input  © 

2 

|iS 

SCK  Output 

400 

ns 

SCK  ® 

SCK  Width  Low 

*KKL 

200 

ns 

Input  ® 

900 

ns 

SCK  Output 

400 

ns 

SCK  © 

SCK  Width  High 

lKKH 

200 

ns 

Input  (D 

900 

ns 

SCK  Output 

RxD  Setup  Time  to  SCK  | 

*RXK 

80 

ns 

© 

RxD  Hold  Time  After  SCK  f 

*KRX 

80 

ns 

© 

SCK  1  TxD  Delay  Time 

*KTX 

210 

ns 

© 

Notes:  ©  1x  Baud  rate  in  Asynchronous,  Synchronous,  or  I/O  Interface  mode 
®  16x  Baud  rate  or  64x  Baud  rate  in  Asynchronous  mode 


AC  Characteristics  (Cont.) 

Ta  =  -10°Cto  +70°C;  Vcc  =  +5.0V  ±  5%;  Vss  =  OV; 
Vcc  ~  0.8V  <  VDD  <  Vcc 

Zero-cross  Characteristics  


Limits 

Parameter  Symbol 

Min 

Typ 

Max 

Unit 

Test  Conditions 

Zero-cross  v 
Detection  Input  zx 

1 

3 

VACP.p 

AC  Coupled 

Zero-cross  . 
Accuracy  zx 

±135 

mV 

60Hz  Sine  Wave 

Zero-cross 
Detection  fzx 
Input  Frequency 

0.05 

1 

kHz 

Ta  =  -10°Cto  +70°C;  Vcc  =  AVCC  =  +5.0V  ±  5%; 
Vss  =  AVSS  =  OV;  AVCC  -  0.5V  <  VABEF  <  AVCC 

AID  Converter  Characteristics 

Limits 

Parameter  Symbol 

Min 

Typ 

Max 

Unit 

Test  Conditions 

Resolution 

8 

Bits 

Absolute 

0.4% 

±  Vl 

LSB 

Ta  =  -10°Cto  +50°C 

Accuracy 

0.6% 

±  Vi 

LSB 

Ta  =  -10°Cto  +70°C© 

576 

tcYC 

83ns  <  tCYC  ^  110ns 

Conversion  Time  tC0Nv  ~ 

432 

tcYC 

110ns  <  tCYC  ^  170ns 

Sampling  Time  tSAMP 

96 

tcYC 

83ns  <  tCYC  s  110ns 

72 

tcYC 

110ns  <  tCYC  ^  170ns 

Analog  Input  y 
Voltage  V|A 

0 

Varef 

V 

Note:  ©  In  case  of  fXTAL  <  10MHz,  Ta  =  -  40°C  to  +  85°C. 


Bus  Timing  Depending  on  tCYC 


Symbol 

Calculating  Expression 

Min/Max 

Unit 

tAL 

2T  -  100 

Mm 

ns 

ttA 

T  -  30 

Mm 

ns 

tAR 

3T  -  100 

Mm 

ns 

tAD 

7T  -  220 

Max 

ns 

lLDR 

5T  -  200 

Max 

ns 

lRD 

4T  -  150 

Max 

ns 

tLR 

T  -  50 

Mm 

ns 

tRL 

2T  -  50 

Mm 

ns 

*RR 

4T  -  50  (Data  Read) 
7T  -  50  (OP  Code  Fetch) 

Mm 

ns 

tLU 

2T  -  40 

Mm 

ns 

*AW 

3T  -  100 

Mm 

ns 

lLDW 

T  +  110 

Max 

ns 

lLW 

T  -  50 

Mm 

ns 

*DW 

4T  -  100 

Mm 

ns 

^WDH 

2T  -  70 

Mm 

ns 

*WL 

2T  -  50 

Mm 

ns 

*WW 

4T  -  50 

Mm 

ns 

*CYK 

12T  (SCK  Input)  © 

Mm 

ns 

24T  (SCK  Output) 

lKKL 

6T  -  100  (SCK  Input)  © 
12T  -  100  (SCK  Output) 

Mm 

ns 

^KKH 

6T  -  100 (SCK Input)© 

Mm 

ns 

12T  -  100  (SCK  Output) 

Notes:  ©  1x  Baud  rate  in  Asynchronous,  Synchronous,  or  I/O  Interface  mode 

T  =  fcYC  ~  ^^XTAL 

The  items  out  of  this  list  are  not  dependent  on  oscillating  frequency  (fXTAi_) 


4-63 


MPD7810/7811 


Timing  Waveforms 

Read  Operation 


X  > 

k  ADRS8_F 

<  X 

w//> 

*  *RDH 

Anne 

 tIL.  ► 

— tLA— ^ 

»  WW  //////> 

Data  In 

'////X 

J- 

 W  

"* — *AFR 

\.  «CL  ► 

/ 

 *RD  n 

I  -  L«. 

u.  tAC__ 

-« — tLC— 

1  T 

Transmit/ Receive  Timing 


— ^KTX  — *-| 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic  Quil,  M-PD7810G/11G 
Plastic  Shrinkdip,  ^PD7810CW/11CW 
QUIL  Ceramic  Piggyback,  (xPD78PG11E 


7810/7811 DS-7-83-CAT-L 


4-64 


SEC 


MPD8021 


SINGLE  CHIP  8-BIT 
MICROCOMPUTER 


DESCRIPTION    The  NEC/uPD8021  is  a  stand  alone  8-bit  parallel  microcomputer  incorporating  the 
following  features  usually  found  in  external  peripherals.  The  juPD8021  contains: 
1 K  x  8  bits  of  mask  ROM  program  memory,  64  x  8  bits  of  RAM  data  memory,  21 
I/O  lines,  an  8-bit  interval  timer/event  counter,  and  internal  clock  circuitry. 


FEATURES     •  8-Bit  Processor,  ROM,  RAM,  I/O,  Timer/Counter 

•  Single  +5V  Supply  (+4.5V  to  +6.5V) 

•  NMOS  Silicon  Gate  Technology 

•  8.38  /is  Instruction  Cycle  Time 

•  All  Instructions  1  or  2  Cycles 

•  Instructions  are  Subset  of  jiiPD8048/8748/8035 

•  High  Current  Drive  Capability  -  2  I/O  Pins 

•  Clock  Generation  Using  Crystal  or  Single  Inductor 

•  Zero-Cross  Detection  Capability 

•  Expandable  I/O  Using  ju8243's 

•  Available  in  28-Pin  Plastic  Package 


PIN  CONFIGURATION 


P22 
P23 
PROG 

Pood 
P01C 

P02C 
P03C 

PfJ4 

pobC 

P06C 

P07C 

ALEC 
vssC 


8021 


□  vcc 

□  P21 

□  P20 

□  P17 

□  P16 

□  P15 

□  P14 

□  P13 

□  P12 

□  P11 

□  P10 

□  RESET 
II  XTAL2 

□  XTAL1 


Rev/2 
4-65 


MPD8021 


1024  x  8-BIT 
MASK  ROM 
ROGRAM  MEMORY 


Vi 


1 


8-BIT 
INTERVAL  TIMER/ 
EVENT  COUNTER 


BLOCK  DIAGRAM 


Operating  Temperature   0  C  to  +70  C 

Storage  Temperature  (Ceramic  Package)  -65°  C  to  +150°C 

(Plastic  Package)  -65°C  to  +150°C 

Voltage  on  Any  Pin  -0.5  to  +7  Volts  © 

Power  Dissipation   1  Watt 

Note:    ©    With  Respect  to  Ground. 
Ta  =  25° C 

*COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 

Ta  =  0°C  to  +70°C;  VCC  =  +5.5V  ±  1V;  Vss  =  0V 


ABSOLUTE  MAXIMUM 
RATINGS* 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Low  Voltage 

V|L 

-0.5 

+  0.8 

V 

Input  High  Voltage,  RESET,  T1 
(All  Except  XTAL  1,  XTAL  2) 

V|H 

2.0 

vcc 

V 

Vcc  =  5.0V  ±  10% 

Input  High  Voltage 
(XTAL  1,  XTAL  2) 

V|H1 

3.0 

vcc 

V 

Vcc  =  5.5V  ±  1V 

Output  Low  Voltage 

vol 

0.45 

V 

I0l  =  1.7  mA 

Output  Low  Voltage 

(PiaPn) 

VOL1 

2.5 

V 

lOL  =  7  mA 

Output  High  Voltage 
(All  Unless  Open  Drain) 

V0H 

2.4 

V 

l0H  =  40mA 

Output  Leakage  Current 
(Open  Drain  Option  -  Port  0) 

"OL 

±10 

HA 

VCC>V|N>VSS 
+0.45V 

Vcc  Supply  Current 

•cc 

40 

75 

mA 

Ta  -  0°C  to  +70°C;  VCC  -  5.5V  ±  1 V,  VSs  -  0V  ^ 

DC  CHARACTERISTICS 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST  CONDITIONS 

MIN 

TYP 

MAX 

Cycle  Time 

TCY 

8.38 

50.0 

MS 

3.58  MHz  XTAL 
for  T^y  Min. 

AC  CHARACTERISTICS 


4-66 


fiPD8021 


PIN 

CI  IMPTinM 

NO. 

O  I  IVIDUL 

1-2, 

ZOZ  / 

P20-P23 
^rori  z; 

•  20  "23  comprise  ins  *t-uii  ui  uii cdiuiidi  i/w  pun 
which  is  also  used  as  the  expander  bus  for  the 
MPD8243. 

3 

PROG 

PROG  is  the  output  strobe  pin  for  the  MPD8243. 

4-11 

P00-P07 
(Port  0) 

One  of  the  two  8-bit  quasi  bi-directional  I/O  ports. 

12 

ALE 

Address  Latch  Enable  output  (active-high).  Occurring 
once  every  30  input  clock  periods,  ALE  can  be  used 
as  an  output  clock. 

13 

T1 

Testable  input  using  transfer  functions  JT1  and  JNT1. 
T1  can  be  made  the  counter/timer  input  using  the 
STRT  CNT  instruction.  T1  also  provides  zero-cross 
sensing  for  low-frequency  AC  input  signals. 

14 

Vqq 

Processor's  ground  potential. 

15 

XTAL  1 

One  side  of  frequency  source  input  using  resistor, 
inductor,  crystal  or  external  source. (non-TTL 
compatible  V||-j). 

16 

XTAL  2 

The  other  side  of  frequency  source  input. 

17 

RESET 

Artivp  hinh  innnt  that  initiali7P^  thp  nrnrpwnr  and 

starts  the  program  at  location  zero. 

18-25 

P10-P17 
(Port  1) 

The  second  of  two  8-bit  quasi  bi-directional  I/O  ports. 

28 

vCc 

+5V  power  supply  input. 

FUNCTIONAL  DESCRIPTION    The  NEC  MPD8021  is  a  single  component,  8-bit,  parallel  microprocessor  using 

N-channel  silicon  gate  MOS  technology.  The  self-contained  1K  x  8-bit  ROM, 
64  x  8-bit  RAM,  8-bit  timer/counter,  and  clock  circuitry  allow  the  juPD8021  to 
operate  as  a  single-chip  microcomputer  in  applications  ranging  from  controllers  to 
arithmetic  processors. 

The  instruction  set,  a  subset  of  the  MPD8048/8748/8035,  is  optimum  for  high-volume, 
low  cost  applications  where  I/O  flexibility  and  instruction  set  power  are  required.  The 
juPD8021  instruction  set  is  comprised  mostly  of  single-byte  instructions  with  no 
instructions  over  two  bytes. 


4-67 


MPD8021 


INSTRUCTION  CODE 

FLAG 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7 

D6 

D4 

D3 

D2 

Dl 

DO 

BYTES 

C 

DATA  MOVES 

MOV  A,  -  data 

(A)  i-  data 

Move  Immediate  the  specified  data  into 

0 

0 

0 

0 

0 

2 

2 

the  Accumulator 

d7 

d5 

d4 

d3 

d2 

dl 

MOW  A    D r 

MUV  A,  nr 

(A)  <-  (Rr),  r  =  0  -  7 

Move  the  contents  of  the  designated 
registers  into  the  Accumulator 

1 

1 

1 

1 

1 

r 

r 

r 

1 

1 

MOV  A  @  Rr 

(A)  «-  ((Rr)),  r  =  0  -  1 

Move  Indirect  the  contents  of  data 
memory  location  into  the  Accumulator 

1 

1 

1 

0 

0 

0 

1 

MOV  Rr,  =  data 

(Rr)  *-  data,  r  =  0  -  7 

Move  Immediate  the  specified  data  into 

0 

1 

1 

1 

2 

the  designated  register 

d7 

d6 

d5 

d4 

d3 

d2 

d! 

MOV  R  r,  A 

(Rr)  <-  (A),  r  =  0  -  7 

Move  Accumulator  Contents  into  the 
designated  register 

0 

0 

1 

1 

1 

MOV  @  Rr,  A 

((Rr))  <-  (A),  r  =  0  -  1 

Move  Indirect  Accumulator  Contents 
into  data  memory  location 

1 

0 

1 

0 

0 

0 

0 

r 

1 

1 

MOV  @  Rr,  =  data 

((Rr))  -data,  r  =  0  -  1 

Move  Immediate  the  specified  data  into 

0 

0 

0 

0 

2 

data  memory 

d7 

d6 

d5 

d4 

d3 

d2 

d1 

MOVP  A,  @  A 

(PCO  -  7)  -  (A) 
(A)  «-  ((PC)) 

Move  data  in  the  current  page  into  the 
Accumulator 

1 

0 

1 

0 

0 

0 

1 

2 

XCH  A,  Rr 

(A)  Z  (Rr),  r  =  0  -  7 

Exchange  the  Accumulator  and  desig- 
nated register's  contents 

0 

0 

0 

1 

XCH  A,  @  Rr 

(A)  Z  ((Rr)),  r  =  0  -  1 

Exchange  Indirect  contents  of  Accumu- 
lator and  location  in  data  memory 

0 

0 

1 

0 

0 

0 

0 

XCHD  A,  @  Rr 

(A0-3)2((Rr))0- 
r  =  0  -  1 

3)), 

Exchange  Indirect  4-bit  contents  of 
Accumulator  and  data  memory 

0 

0 

1 

0 

0 

0 

FLAGS 

CPL  C 

(C)  -  NOT  (C) 

Complement  Content  of  carry  bit 

1 

0 

0 

0 

1 

CLR  C 

(C)  «-0 

Clear  content  of  carry  bit  to  0 

1 

0 

0 

0 

1 

INPUT/OUTPUT 

ANLD  Pp,  A 

(Pp)  -  (Pp)  AND  (AO 
p  =  4  -  7 

-3) 

Logical  and  contents  of  Accumulator  witri 
designated  port  (4  -  7). 

0 

0 

1 

1 

p 

P 

2 

IN  A,  Pp 

(A)-(Pp),p=  1  -2 

Input  data  from  designated  port  (1  -  2) 
into  Accumulator 

0 

0 

0 

0 

0 

p 

P 

2 

MOVD  A,  Pp 

<A0-3)<-(Pp),p  =  4 
(A4-7K0 

-  7 

Move  contents  of  designated  port  (4  -  7) 
into  Accumulator 

0 

0 

0 

0 

p 

P 

2 

MOVD  Pp,  A 

(Pp)-A0-3,p  =  4- 

7 

Move  contents  of  Accumulator  to  desig- 
nated port  (4  -  7) 

0 

0 

1 

p 

P 

ORLD  Pp,  A 

(Pp)*-(Pp)OR  (A0- 
p  =  4-7 

3) 

Logical  or  contents  of  Accumulator 
with  designated  port  (4  -  7) 

1 

0 

0 

0 

1 

p 

P 

OUTL  Pp,  A 

(Pp)  «-  (A),p  =  1  -2 

Output  contents  of  Accumulator  to 
designated  port  (1-2) 

0 

0 

1 

1 

0 

p 

P 

REGISTERS 

INC  Rr 

(Rr)-(Rr)  +  1,r  =  0- 

7 

Increment  by  1  contents  of  designated 
register 

0 

0 

0 

1 

INC@  Rr 

((Rr))  -  ((Rr))  +  1, 
r  =  0-  1 

Increment  Indirect  by  1  the  contents  of 
data  memory  location 

0 

0 

0 

0 

0 

0 

SUBROUT 

INE 

CALLaddr 

((SP))  -  (PC),  (PSW4 

7) 

Call  designated  Subroutine 

310 

38 

0 

0 

0 

2 

2 

(SP)     (SP)  +  1 

(PC  8-  10)  -addr8- 

10 

a7 

35 

34 

33 

32 

31 

30 

(PCO-7)-addrO-7 

(PC  11)*- DBF 

RET 

(SP)  «-  (SP)  -  1 
(PC)  -  ((SP)) 

Return  from  Subroutine  without  restor- 
ing Program  Status  Word 

1 

0 

0 

0 

0 

0 

1 

1 

2 

1 

TIMER/COUNTER 

MOV  A,  T 

(A)  *-  (T) 

Move  contents  of  Timer/Counter  into 
Accumulator 

0 

1 

0 

0 

0 

0 

1 

0 

1 

1 

MOV  T,  A 

(T)  «-<A) 

Move  contents  of  Accumulator  into 
Timer/Counter 

0 

1 

1 

0 

0 

0 

1 

0 

1 

1 

STOP  TCNT 

Stop  Count  for  Event  Counter 

0 

1 

1 

0 

0 

0 

1 

1 

1 

STRT  CNT 

Start  Count  for  Event  Counter 

0 

1 

0 

0 

0 

1 

0 

1 

STRTT 

Start  Count  for  Timer 

0 

1 

0 

1 

0 

1 

0 

1 

1 

1 

MISCELLANEOUS 

NOP 

No  Operation  performed 

° 

0 

0 

0 

0 

0 

0 

0 

Notes   (T)  Instruction  Code  Designations  r  and  p  form  the  binary  representation  of  the  Registers  and  Ports  involved 

(2)  The  dot  under  the  appropriate  flag  bit  indicates  that  its  content  is  subject  to  change  by  the  instruction  it  appears  in 
©  References  to  the  address  and  data  are  specified  in  bytes  2  and/or  1  of  the  instruction 

(3)  Numerical.Subscripts  appearing  in  the  FUNCTION  column  reference  the  specific  bits  affected. 


Symbol  Definitions 


SYMBOL 

DESCRIPTION 

A 

The' Accumulator 

addr 

Program  Memory  Address  (12  bits) 

C 

Carry  Flag 

CLK 

Clock  Signal 

CNT 

Event  Counter 

D 

Nibble  Designator  (4  bits) 

data 

Number  or  Expression  (8  bits) 

P 

"In-Page"  Operation  Designator 

PP 

Port  Designator  (p  =  1 ,  2  or  4  -  7) 

Rr 

Register  Designator  (r  =  0,  1  or  0  -  7) 

SYMBOL 

DESCRIPTION 

T 

Timer 

Tl 

Testable  Flag  1 

X 

External  RAM 

Prefix  for  Immediate  Data 

@ 

Prefix  for  Indirect  Address 

$ 

Program  Counter's  Current  Value 

(x) 

Contents  of  External  RA*M  Location 

«x)) 

Contents  of  Memory  Location  Addressed 
by  the  Contents  of  External  RAM  Location 

Replaced  By 

4-68 


INSTRUCTION  SET 


fiPD8021 


INSTRUCTION  CODE 

FLAG 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7 

°6 

D4 

D3 

D2 

D1 

DO 

CYCLES 

BYTES 

C 

ACCUMULATOR 

ADD  A,  =  data 

(A)  -  (A)  +data 

Add  immediate  the  specified  Data  to  the 

0 

0 

0 

0 

0 

0 

1 

2 

2 

Accumulator 

d7 

d6 

d5 

d4 

d3 

d2 

dl 

do 

Add  A,  Rr 

(A)  —  (A)  +  (Rr) 

Add  contents  of  designated  register  to 
the  Accumulator 

0 

1 

1 

0 

1 

r 

r 

f 

ADD  A,  @  Rr 

(A)  —  (A)  +  llHr)) 
for  r  =  0  -  1 

Add  indirect  the  contents  the  data 
memory  location  to  the  Accumulator 

Q 

1 

1 

0 

Q 

1 

1 

ADDC  A,  =  data 

\aj  <—  iaj  +       t  aata 

Add  immediate  with  carry  the  specified 

data  to  the  Accumulator 

d7 

d6 

d°5 

d4 

d3 

d2 

dl 

AUUU  M,  nl 

for  r  =  0  -  7 

designated  register  to  the  Accumulator 

ADDC  A  @  Rr 

(A)  —  (A)  +  (C)  +  ((Rr)) 
for  r  =  0  -  1 

data  memory  location  to  the 
Accumulator 

o 

1 

1 

1 

0 

0 

0 

ANL  A,  =  data 

(A) -(A)  AND  data 

Logical  and  specified  Immediate  Data 

0 

1 

0 

1 

0 

0 

with  Accumulator 

d6 

d5 

d4 

d3 

d2 

dl 

ANL  A,  Rr 

(A)  -  (A)  AND  (Rr) 
for  r  =  0  -  7 

Logical  and  contents  of  designated 
register  with  Accumulator 

0 

1 

0 

1 

r 

! 

ANL  A,  @  Rr 

(A)  -  (A)  AND  ((Rr)) 
for  r  =  0  -  1 

Logical  and  Indirect  the  contents  of  data 
memory  with  Accumulator 

0 

1 

0 

1 

0 

0 

0 

r 

! 

CPL  A 

(A) -NOT  (A) 

Complement  the  contents  of  the 
Accumulator 

0 

0 

1 

1 

0 

1 

1 

1 

1 

1 

CLR  A 

(A)  -0 

CLEAR  the  contents  of  the  Accumulator 

0 

0 

1 

0 

0 

1 

1 

1 

DA  A 

DECIMAL  ADJUST  the  contents  of  the 
Accumulator 

0 

1 

0 

1 

0 

1 

1 

1 

1 

1 

• 

DEC  A 

(A) -(A)  -1 

DECREMENT  by  1  the  Accumulator's 
contents 

0 

0 

0 

0 

0 

1 

1 

1 

1 

1 

(A)  —  (A)  +  1 

Increment  by  1  the  Accumulator's 
contents 

ORL  A,  =  data 

(A) -  (A)  OR  data 

Logical  OR  specified  immediate  data 

0 

1 

0 

0 

0 

0 

1 

1 

with  Accumulator 

d7 

d6 

d5 

d4 

d3 

d2 

dl 

ORL  A,  Rr 

(A) -(A)  OR  (Rr) 

Logical  OR  contents  of  designated 
register  with  Accumulator 

0 

1 

0 

0 

r 

1 

1 

ORL  A  @  Rr 

(A)  -  (A)  OR  ((Rr)) 
for  r  =  0  -  1 

Logical  OR  Indirect  the  contents  of  data 
memory  location  with  Accumulator 

0 

1 

0 

& 

0 

0 

0 

' 

1 

1 

RL  A 

(AN  +  1)-  (AN) 
(Arj)-(Ay) 
for  N  =  0  -  6 

Rotate  Accumulator  left  by  1  -bit  with- 
out carry 

1 

1 

1 

0 

0 

1 

1 

1 

1 

1 

RLC  A 

(AN  +  1)-(AN),N  =  0-6 
(A0)  -  (C) 
(C)  -  (Ay) 

Rotate  Accumulator  left  by  1  -bit  through 
carry 

1 

1 

1 

1 

0 

1 

1 

1 

1 

1 

• 

RR  A 

(AN) —  (AN  +  1),N  =  0-6 
(Ay)  -  (A0) 

Rotate  Accumulator  right  by  1-bit 
without  carry 

0 

1 

1 

1 

0 

1 

1 

RRC  A 

(AN)-(AN+1),N  =  0-6 

(Ay)  -  (C) 

(C)-(A0> 

Rotate  Accumulator  right  by  1  -bit 
through  carry. 

0 

1 

0 

0 

1 

1 

• 

SWAP  A 

(A4.y)  £  (AO  -  3) 

Swap  the  24-bit  nibbles  in  the 
Accumulator 

0 

1 

0 

0 

0 

1 

1 

XRL  A,  =  data 

(A)  -  (A)  XOR  data 

Logical  XOR  specified  immediate  data 

1 

1 

0 

1 

0 

0 

1 

with  Accumulator 

d6 

d5 

d4 

d3 

d2 

di 

XRL  A,  Rr 

(A)  -  (A)  XOR  (Rr) 
for  r  =  0  -  7 

Logical  XOR  contents  of  designated 
register  with  Accumulator 

1 

1 

0 

XRL  A,  @  Rr 

(A) -(A)  XOR  ((Rr)) 
f  or  r  =  0  -  1 

Logical  XOR  Indirect  the  contents  of  data 
memory  location  with  Accumulator 

1 

0 

1 

0 

0 

0 

BRANCH 

DJNZ  Rr,  addr 

(Rr)-(Rr)-1,r  =  0-7 

Decrement  the  specified  register  and 

1 

1 

1 

0 

1 

2 

2 

If  (Rr)  *0 

test  contents 

37 

36 

35 

34 

33 

32 

a1 

30 

(PC  0  -  7)  -  addr 

JC  addr 

(PC  0-7) -addr  if  C  =  1 

Jump  to  specified  address  if  carry  flag 

1 

1 

1 

1 

0 

1 

0 

2 

2 

(PC)-(PC)+2ifC  =  0 

is  set 

37 

36 

35 

34 

33 

32 

a1 

30 

JMP  addr 

(PC  8 -10) -addr  8 -10 

Direct  Jump  to  specified  address  within 

310 

39 

38 

0 

0 

1 

0 

2 

2 

(PC  0  -  7)  -  addr  0-7 

the  2K  address  block 

37 

36 

35 

34 

33 

32 

31 

30 

(PC  11) -DBF 

JMPP  @  A 

(PC  0-7) -((A)) 

Jump  indirect  to  specified  address  with 
address  page 

1 

0 

1 

1 

0 

0 

1 

2 

1 

JNC  addr 

(PC  0-  7)  -  addr  if  C  =  0 

Jump  to  specified  address  if  carry  flag  is 

1 

1 

1 

0 

0 

1 

0 

2 

2 

(PC)  -  (PC)  +  2  if  C  =  1 

low 

37 

36 

35 

34 

33 

32 

a1 

30 

JNT1  addr 

(PC  0  -  7)  -  addr  if  T1  =  0 

Jump  to  specified  address  if  Test  1  is  low 

0 

1 

0 

0 

0 

1 

0 

2 

2 

(PC) -(PC) +2  if  T1  =1 

37 

36 

35 

34 

33 

32 

a1 

30 

JNZ  addr 

(PC  0  -  7)  -  addr  if  A  =  0 

Jump  to  specified  address  if 

1 

0 

0 

1 

0 

1 

0 

2 

2 

(PC)  -  (PC)  +  2  if  A=0 

Accumulator  is  non-zero 

37 

36 

35 

34 

33 

32 

a1 

30 

JTF  addr 

(PC  0  -  7)  -  addr  if  TF  =  1 

Jump  to  specified  address  if  Timer  Flag 

0 

0 

0 

1 

0 

1 

0 

2 

2 

(PC)-(PC)  +  2ifTF=0 

is  set  to  1 

37 

36 

35 

34 

33 

32 

30 

JT1  addr 

(PC  0-7) -addr  if  T1  -  1 

Jump  to  specified  address  if  Test  1  is  a  1 

0 

1 

0 

1 

0 

1 

0 

2 

2 

(PC) -(PC) +  2  if  T1  =0 

37 

36 

35 

34 

33 

32 

a1 

30 

JZ  addr 

(PC  0  -  7)  -  addr  if  A  =  0 

Jump  to  specified  address  if  Accumulator 

1 

1 

0 

0 

0 

1 

0 

2 

2 

(PC)  -  (PC)  +  2  if  A  =  0 

isQ. 

37 

36 

35 

34 

33 

32 

30 

4-69 


MPD8021 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  mPD8021C 
Cerdip,  (xPD8021D 


4-70 


8021 DS-R  EV2-1  -82-CAT 


SEC 


fiPD8041A 
fiPD8741A 


UNIVERSAL  PROGRAMMABLE  PERIPHERAL 
INTERFACE  —  8-BIT  MICROCOMPUTER 

DESCRIPTION    The /IPD8041  A/8741  A  is  a  programmable  peripheral  interface  intended  for  use 
in  a  wide  range  of  microprocessor  systems.  Functioning  as  a  totally  self-sufficient 
controller,  the  juPD8041  A/8741  A  contains  an  8-bit  CPU,  1 K  x  8  program 
memory,  64  x  8  data  memory,  I/O  lines,  counter/timer,  and  clock  generator  in  a 
40-pin  DIP.  The  bus  structure,  data  registers,  and  status  register  enable  easy  interface 
to  8048,  8080A  or  8085A  based  systems.  The  juPD8041  A's  program  memory  is  fac- 
tory mask  programmed,  while  the  juPD8741  A's  program  memory  is  UV  EPROM  to 
enable  user  flexibility. 

FEATURES    •  Fully  Compatible  with  8048,  8080A,  8085A  and  8086  Bus  Structure 

•  8-Bit  CPU  with  1 K  x  8  ROM,  64  x  8  RAM,  8-Bit  Timer/Counter, 
18  I/O  Lines 

•  8-Bit  Status  and  Two  Data  Registers  for  Asynchronous  Slave-to-Master 
Interface 

•  Interchangeable  EPROM  and  ROM  Versions 

•  Interrupt,  DMA  or  Polled  Operation 

•  Expandable  I/O 

•  40-Pin  Plastic  or  Cerdip  DIP  Package 

•  Single  +5V  Supply 


PIN  CONFIGURATION 


T0  C 

1 

xi  C 

2 

x2  C 

3 

RESET  C 

4 

ss  c 

5 

cs  c 

6 

EA  C 

7 

RD  C 

8 

A0  C 

9 

WR  C 

10 

SYNC  C 

11 

D0  C 

12 

D1  C 

13 

D2  C 

14 

D3  C 

15 

D4  C 

16 

D5  C 

17 

D6  C 

18 

D7  C 

19 

vssC 

20 

juPD 
8041  A/ 
8741A 


Rev/3 
4-71 


MPD8041 A/8741  A 


PIN 

FUNCTION 

NO 

SYMBOL 

1,39 

Testable  input  pins  using  conditional  transfer  instructions 
j  l  ur  Jim  i  u,  j  i  i ,  jim  ii.  i  -j  can  Dc  iiiaUc  ine  counter/ iimer 
input  using  the  STRT  CNT  instruction.  The  PROM  pro- 
gramming and  verification  on  the  juPD8741  A  uses  Tq. 

2 

One  side  of  the  crystal  input  for  external  oscillator  or 
frequency  source. 

3 

x2 

The  other  side  of  the  crystal  input. 

4 

RESET 

Active-low  input  for  processor  initialization.  RESET  is  also 
used  for  PROM  programming,  verification,  and  power  down. 

5 

SS 

Single  Step  input  (active-low).  SS  together  with  SYNC  out- 
put allows  the  juPD8741  A  to  "single-step"  through  each 
instruction  in  program  memory. 

6 

CS 

Chip  Select  input  (active-low).  CS  is  used  to  select  the 
appropriate  //PD8041  A/8741  A  on  a  common  data  bus. 

7 

EA 

External  Access  input  (active-high).  A  logic  "1"  at  this  input 

rnmmanfls  thp  //PDRfW-l  A/R741  A  to  nprfnrm  all  nrnnram 
1 1 1 1  lai  HJo  Li  ic  fj.r  L/oui  1  f\/  O  I  '-r  t  f~\  LU  pel  1  CI  1 1 1  all  |JI  vjy  I  dl  1 1 

memory  fetches  from  external  memory. 

8 

RD 

Read  strobe  input  (active-low).  RD  will  pulse  low  when  the 
master  processor  reads  data  and  status  words  from  the  DATA 
BUS  BUFFER  or  Status  Register. 

9 

A0 

Address  input  which  the  master  processor  uses  to  indicate  if 
a  byte  transfer  is  a  command  or  data. 

10 

WR 

Write  strobe  input  (active-low).  WR  will  pulse  low  when  the 
master  processor  writes  data  or  status  words  to  the  DATA 

Rl  19  Rl  IFFFR  or  Statue  Rpnictor 

11 

SYNC 

The  SYNC  output  pulses  once  for  each  /iPD8041  A/8741  A 
instruction  cycle.  It  can  function  as  a  strobe  for  external 

pi  i-pi  i  itr\/   QYMP  pan  alco  he»  iicoH  to  neither  \A/ith  QQ  to 
uiiuuiLiy.  v_>  i  imo  uoi i  aiou  uc  uocu  njycuici  wiui  oo  iu 

"single-step"  through  each  instruction  in  program  memory. 

12-19 

D0-D7  BUS 

The  8-bit,  bi-directional,  tri-state  DATA  BUS  BUFFER  lines 
by  which  the  juPQ804 1  A/874 1 A  interfaces  to  the  8-bit 
master  system  data  bus. 

20 

vSs 

Processor's  ground  potential. 

21-24, 
35-38 

p20p27 

PORT  2  is  the  second  of  two  8-bit,  quasi-bi-directional  I/O 
ports.  P20"p23  contain  the  four  most  significant  bits  of  the 
program  counter  during  external  memory  fetches.  P20p23 
also  serve  as  a  4-bit  I/O  bus  for  the  //PD8243,  INPUT/ 
OU  1  rUT  EXPANDcR.  ^24^27  can  De  usec'  as  Por*  'mes  or 
can  provide  Interrupt  Request  (IBF  and  OBF)  and  DMA 
handshake  lines  (DRQ  and  DACK). 

25 

PROG 

Program  Pulse.  PROG  is  used  in  programming  the  /iPD8741  A. 
It  is  also  used  as  an  output  strobe  for  the  juPD8243. 

26 

Vdd 

Vdd 's  *ne  programming  supply  voltage  for  programming 
the  /iPD8741  A.  It  is  +5V  for  normal  operation  of  the 
jitPD8041  A/8741  A.  VDD  is  also  the  Low  Power  Standby 
input  for  the  ROM  version. 

27-34 

P10-P17 

PORT  1  is  the  first  of  two  8-bit  quasi-bi-directional  I/O  ports. 

40 

vCc 

Primary  power  supply.  Vqc  must  be  +5V  for  programming 
and  operation  of  the  /2PD8741 A  and  for  the  operation  of  the 
MPD8041A. 

4-72 


(iPD8041  A/8741 A 


FUNCTIONAL    The  juPD8041  A/8741  A  is  a  programmable  peripheral  controller  intended  for  use 
DESCRIPTION     in  master/slave  configurations  with  8048,  8080A,  8085A,  8086  -  as  well  as  most 
other  8-bit  and  16-bit  microprocessors.  The  /1PD8041  A/8741  A  functions  as  a 
totally  self-sufficient  controller  with  its  own  program  and  data  memory  to  effectively 
unburden  the  master  CPU  from  I/O  handling  and  peripheral  control  functions.  The 
juPD8041  A/8741  A  is  an  intelligent  peripheral  device  which  connects  directly  to  the 
master  processor  bus  to  perform  control  tasks  which  off  load  main  system  processing 
and  more  efficiently  distribute  processing  functions. 

juPD8041  A/8741  A     The  juPD8041  A/8741  A  features  several  functional  enhancements  to  the  earlier 

FUNCTIONAL  juPD8041  part.  These  enhancements  enable  easier  master/slave  interface  and  increased 
ENHANCEMENTS  functionality. 

1.  Two  Data  Bus  Buffers.  Separate  Input  and  Output  data  bus  buffers  have  been 
provided  to  enable  smoother  data  flow  to  and  from  master  processors. 


2.  8-Bit  Status  Register.  Four  user-definable  status  bits,  ST4-ST7,  have  been 
added  to  the  status  register.  ST4-ST7  bits  are  defined  with  the  MOV  STS,  A 
instruction  which  moves  accumulator  bits  4-7  to  bits  4-7  of  the  status  register. 
ST0-ST3  bits  are  not  affected. 


ST7 

ST6 

ST5 

ST4 

Fl 

FO 

IBF 

OBF 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

00 

MOV  STS,  A  Instruction  OP  Code  90H 

3.  RD  and  WR  inputs  are  edge-sensitive.  Status  bits  IBF,  OBF,  F1  and  FO  are 
affected  on  the  trailing  edge  at  RD  or  WR. 


Flags  affected 


RD  or  WR 


4-73 


jiPD8041 A/8741 A 


4.  P24  and  P25  can  be  used  as  either  port  lines  or  Buffer  Status  Flag  pins.  This 
feature  allows  the  user  to  make  OBF  and  IBF  status  available  externally  to 
interrupt  the  master  processor.  Upon  execution  of  the  EN  Flags  instruction, 
P24  becomes  the  OBF  pin.  When  a  "1"  is  written  to  P24,  the  OBF  pin  is 
enabled  and  the  status  of  OBF  is  output.  A  "0"  written  to  P24  disables  the 
OBF  pin  and  the  pin  remains  low.  This  pin  indicates  valid  data  is  available  from 
the  juPD8041  A/8741  A.  EN  Flags  instruction  execution  also  enables  P25  indi- 
cate that  the  jitPD804 1  A/874 1 A  is  ready  to  accept  data.  A  "1 "  written  to  P25 
enables  the  IBF  pin  and  the  status  of  IBF  is  available  on  P25.  A  "0"  written  to 
P25  disables  the  IBF  pin.  If  OBF  is  not  true,  the  data  at  the  databus  is  invalid. 

EN  Flags  Instruction  Op  code  —  F5H. 

5.  P26  and  P27  can  be  used  as  either  port  lines  or  DMA  handshake  lines  to  allow 
DMA  interface.  The  EN  DMA  instruction  enables  P26  and  P27  to  be  used  as 
DRQ  (DMA  Request)  and  DACK  (DMA  acknowledge)  respectively.  When  a 
"1"  is  written  to  P26,  DRQ  is  activated  and  a  DMA  request  is  issued.  Deacti- 
vation of  DRQ  is  accomplished  by  the  execution  of  the  EN  DMA  instruction, 
DACK  anded  with  RD,  or  DACK  anded  with  WR.  When  EN  DMA  has  been 
executed,  P27  (DACK)  functions  as  a  chip  select  input  for  the  Data  Bus 
Buffer  registers  during  DMA  transfers. 

EN  DMA  Instruction  Op  Code  -  E5H. 


MPD8041  A/8741  A 
FUNCTIONAL 
ENHANCEMENTS  (CONT.) 


CRYSTAL.  LC.  OR  CLOCK 


RlSff   PROG      SS   SYNC  EA 


MASTER  SYSTEM  INTERFACE 

 I  

CS      WR  Do-D7 


CONTROL  LOGIC 


— *V  INSTRUCTION  ^  N 
 ^     DECODER      SSJ  J 


ACCUMULATOR 

c     !  : 

■v 


BLOCK  DIAGRAM 

PERIPHERAL  INTERFACE 


DBB 

STATUS 
REGISTER 


IE 


CONDITIONAL 
BRANCH 

LOGIC 


1  1 


L 


8-BIT 
TIMER/ 
EVENT  COUNTER 


PORT  2 

BUS 
BUFFER 


PORT  4-7 
EXPANDER 
INTERFACE 


8-BIT  INTERNAL  BUS 

 TV 


10  BIT 
PROGRAM 
COUNTER 


3 


RESIDENT 
ROM/PROM 
PROGRAM  MEMORY 
1024x8 


PORT  1 

BUS 
BUFFER 


7y 


TV 


iz 


MULTIPLEXER 


REGISTER  BANK  1 


REGISTER  BANK  0 


DATA  MEMORY 


RESIDENT 
RAM 
84*8 


{VDD  — 
VCC  — 
Vss   — 


PROGRAM  POWER  SUPPLY 
►5V  SUPPLY 
GROUND 


4-74 


//PD8041  A/8741  A 


ABSOLUTE  MAXIMUM 
RATINGS* 


DC  CHARACTERISTICS 


Operating  Temperature   0°C  to +70°C 

Storage  Temperature  (Ceramic  Package)   -65°C  to  +150°C 

Storage  Temperature  (Plastic  Package)   -65°C  to+150°C 

Voltage  on  Any  Pin   -0.5  to +7  Volts  © 

Power  Dissipation  1.5  Watt 

Ta  =  25°C 

*COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  perma- 
nent damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at 
these  or  any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specifica- 
tion is  not  implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may 
affect  device  reliability. 
Note   ©  With  respect  to  ground 

Ta  =  0°Cto  +70°C;  Vcc  =  VpD  =  +5V  ±  10%;  Vss  =  0V 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Input  Low  Voltage 
(All  except  Xi  and  X2) 

V|L 

-0.5 

+0.8 

V 

Input  Low  Voltage 
(X<\  and  X2,  RESET) 

V|L1 

-0.5 

0.6 

V 

Input  High  Voltage 

(All  except  X1#X2,  RESET) 

V|H 

2.0 

vCc 

V 

Input  High  Voltage 
<X1fX2,  RESET) 

V|H1 

3.8 

vCc 

V 

Output  Low  Voltage 
(D0-D7,  SYNC) 

vol 

0.45 

V 

lOL  ~  2.0  mA 

Output  Low  Voltage 

(All  other  outputs  except  PROG) 

VOL1 

0.45 

V 

•OL  =  1-0  mA 

Output  Low  Voltage  (PROG) 

VOL2 

0.45 

V 

lOL  =1.0  mA 

Output  High  Voltage  (D0-D7) 

VOH 

2.4 

V 

'OH  =  -400  mA 

Output  High  Voltage 
(All  other  outputs) 

VOH1 

2.4 

V 

lOH  =-50mA 

Input  Leakage  Current 

(TO,  Ti,RD,WR,CS,  EA,  A0) 

ML 

±10 

ma 

VSS<V|N< 

vCc 

Output  Leakage  Current 
(D0-D7;  High  Z  State) 

lOL 

±10 

ma 

Vss  +  0-45  < 
V|N<VCC 

Vqd  Supply  Current 

•dd 

15 

mA 

Total  Supply  Current 

>CC+  'DD 

125 

mA 

Low  Input  Source  Current 
(P10-P17;P20-P27> 

»LI 

0.5 

mA 

V|L  =  0.8V 

Low  Input  Source  Current 
(SS;  RESET) 

•lm 

0.2 

mA 

V|L  =  0.8V 

4-75 


MPD8041  A/8741  A 


Ta-o°cto+7o°c;vDD=;vCc  =  +5v±  io%;VSS  =  ov  AC  CHARACTERISTICS 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MPD8041A 

MPD8741A 

MIN  |  MAX 

MIN  |.  MAX 

DBB  READ 

CS,  Aq  Setup  to  RD  I 

*AR 

0 

60 

ns 

CS,  Aq  Hold  after  RD  t 

*RA 

0 

30 

ns 

"RD  Pulse  Width 

tRR 

250 

300 

2xtCY 

ns 

tCY  =  2.5  /us 

CS,  Aq  to  Data  Out  Delay 

tAD 

225 

370 

ns 

CL  =  150  pF 

RD  I  to  Data  Out  Delay 

tRD 

225 

200 

ns 

C|_  =  150  pF 

RD  t  to  Data  Float  Delay 

tDF 

100 

140 

ns 

Cycle  Time 

tCY 

2  5 

15 

2.5  ' 

15 

MS 

6  MHz  Crystal 

DBB  WRITE 

CS,  Aq  Setup  to  WR  1 

*AW 

10 

60 

ns 

CS,  Ao  Hold  after  WR  t 

lWA 

10 

30 

ns 

WR  Pulse  Width 

tww 

260 

300 

2  xtCY 

ns 

tCY  =  2.5  ms 

Data  Setup  to  WR  t 

*DW 

150 

250 

ns 

Data  Hold  after  WR  t 

*WD 

10 

30 

ns 

PORT  2 

Port  Control  Setup  before 
falling  edge  of  PROG 

'CP 

110  . 

110 

ns 

Port  Control  Hold  after  Falling 
Edge  of  PROG 

'PC 

100 

100 

ns 

PROG  to  P2  Input  Valid 

'PR 

810 

810 

ns 

Input  Data  Hold  Time 

'PF 

0 

150 

0 

150 

ns 

Output  Data  Setup  Time 

'DP 

250 

250 

ns 

Output  Data  Hold  Time 

'PD 

65 

65 

ns 

PROG  Pulse  Width 

1200 

1200 

ns 

DMA 

DACK  J,  to  RD  |  orWR  j 

'ACC 

0 

0 

ns 

RD  f  or  WR  to  DACK  t 

'CAC 

0 

0 

ns 

DACK  to  Data  Valid 

'ACD 

225 

225 

CL  150pF 

RD  or  WR  to  DRQ  J, 

'CRQ 

225 

225 

ns 

TIMING  WAVEFORMS 

SYSTEM 
ADDRESS  BUS 


READ  CONTROL 


WRITE  OPERATION  -  DATA  BUS  BUFFER  REGISTER 


SYSTEM 
ADDRESS  BUS 


READ  OPERATION  -  DATA  BUS  BUFFER  REGISTER 


K 


-DATA  VALlO  — 


;> 


DATA  CAN  CHANGE 


-DATA  VALID- 


4-76 


jiPD8041  A/8741  A 


DMA  TIMING  DIAGRAM 


J- 


J" 


-kJAC 


\  vaud  >r 


-  *ACD  - 


tCRQ- 


*ACC- 


tCRQ- 


-kjAC 


"X  valid  X~ 


PORT  2  TIMING  DIAGRAM 


EXPANDER 
PORT 


PORT  20  —  23  DATA 


EXPANDER 
PORT 


PORT  20  —  23  DATA 


J  V 


\^  PORT  CONTROL 


-tDp- 


_tPP 


PORT  CONTROL 


lPD 


tcp  L_tPC_ 


_|PF 

HNPUT* 

•  1PP  - 


4-77 


fiPD8041  A/8741  A 


INSTRUCTION  SET 


MNEMONIC 


DESCRIPTION 


INSTRUCTION  CODE 
Q7      D6      D5      O4      D3  P2 


FLAGS 

O0      CYCLES    BYTES    C   AC    FO    F1    IBF   DBF  ST4.7 


ADD  A  -  d.ta 
ADD  A  Fir 
ADD  A  <9>  Rr 
ADDC  A  =  data 
ADDC  A  Rr 
AOOC  A  @Rr 

ANL  A  -  data 

ANL  A  R' 

ANL  A  @  Rr 

CPL  A 

CLR  A 
DA  A 

DEC  A 

INC  A 

ORL  A  =  data 
ORL  A  Rr 
ORL  A  @  Rr 


SWAP  A 
XRL  A  "data 


OJNZ  Rr  addr 


JBb  addr 
JC  addr 
JFOaddr 
JF1  addr 


ADD  A  =  data. 


I  A)  OR  data 

(Al  OR  IRr» 
=  0-7 

IA)  OR  (IRr) 

=  0-1 


for  N  -  0  -  6 
(AN  +  1)  -(AN),  N  =  0-  6 


(AN)*-  (AN  +  1),  N  =  0  -( 
IA7)  IA0) 

(AN)  -(AN  +  1),  N  =  0- 
(A7)  tC) 
(CI  •  (A0) 

(A4.7)-(A0-3) 
(A)  •  (A)  XOR  data 

(A)  •  I  A)  XOR  (Rrl 
for  r  =  0  -  7 
(A)  •   (A)  XOR  ((Rr)) 
for  r  »  0  -  1 

<Rr)-(Rr)-1,r  =  0-7 
If  (Rr)  *0 
(PCO  -  7)  -  addr 
(PC  0  -  7)  -  addr  if  Bb  = 
(PC) -(PC)  +2  if  Bb  =  0 
(PC  0-7) -addr  if  C=  1 
(PC)-(PC)  +  2ifC  =  0 
(PC  0  -  7)  -  addr  if  FO  = 
(PC) -(PC) +  2  if  FO  =  0 
(PC  0  -  7)  —  addr  if  F 1  =  1 
IPC)'  (PC)*2.fF1  =0 
(PC  8-  10) -addr  8  -10 
(PCO  -7)  -addrO  -7 
(PC  11)  —  DBF 
(PC  0-7) -((A)) 


specified  Data  to  the 
Accumulator 

Add  contents  of  designated  register  to 
the  Accumulator 

Add  Indirect  the  contents  the  data 
memory^oeation  to  the  Accumulator 
Add  Immediate  with  carry  the  specified 
data  to  the  Accumulator 
Add  with  carry  the  contents  o*  the 
designated  register  to  the  Accumulator 
Add  Indirect  with  carry  the  contents  of 
data  memory  location  to  the 

Logical  and  specif  iei 
with  Accumulator 
Log.cai  and  content 


Complement 


I  Immediate  Data 


d7      d6      d5  d4 


d6      d5      <*4      d3  d2 


dg      d5      04  d3 


CLEAR 
DECIMAL  ADJUST  tl 
Accumulator 
DECREMENT  by  1  th 


Loqical  OR  or  specified  immediate 
with  Accumulator 
Logical  OR  contents  of  designated 
reqister  with  Accumulator 
Logical  OR  Indirect 


Rotate  Accumuiai 


Rotate  Accirmul 


>ie  contents  of  data 
1  Accumulator 
left  by  1  bit  without 


ilator  right  bv  1  c 
ilator  right  by  1  b 

it  nibbles  m  the 


d5      d4      d3  d2 


Jump  to  specified  address  if 

Jump  to  specified  address  if  Flag  FO 
set 

Jump  to  specified  address  if  Flag  F 1 
set 


lag 


d5      d4      <J3  d? 


Jump  to  specified  address  if  carry  flag  is 


Jump  to  specified  address  if  input  buffer 
full  flag  is  low 


4-78 


j*PD8041 A/8741  A 


INSTRUCTION  SET  (CONT.) 


INSTRUCTION  CODE 

FLAGS 

MNEMONIC 

FUNCTION 

D7 

Dfj 

05 

04 

03 

02 

Dl 

D0 

CYCLES 

BYTES 

C    AC     FO    F1  IB 

F  OBF 

ST4.7 

BRANC 

JNTO  addr 

(PC  0  -  7)  <-  addr  if  TO  =  0 

Jump  to  specified  address  if  Test  0  is  low 

0 

0 

0 

0 

1 

0 

2 

(PC)  -  (PC)  +  2  if  TO  =  1 

»7 

»6 

35 

34 

33 

32 

31 

30 

JNT1  addr 

(PCO-7)Vaddr  if  T1  =  0 
(PC)  -  (PC)  +  2  if  T  1  =  1 

Jump  to  specified  address  if  Test  1  is  low 

0 
»7 

»6 

0 

35 

0 

34 

0 

33 

1 

32 

31 

0 

30 

2 

JNZ  addr 

(PCO-7)<-addrif  A  =  0 

Jump  to  specified  address  if  accumulator 

0 

0 

0 

0 

2 

(PC)  -  (PC)  +  2  if  A  =  0 

is  non  zero 

»7 

36 

•5 

84 

33 

32 

31 

30 

JTF  addr 

(PC0-7)-addrifTF  =  1 

Jump  to  specified  address  if  Timer  Flag 

0 

0 

0 

0 

1 

0 

2 

(PC)  <- (PC)  +  2  if  TF  =  0 

is  set  to  1 

37 

36 

35 

34 

33 

32 

31 

30 

JTO  addr 

(PC  0  -  7)  -  addr  if  TO  =  1 
(PC)  <-  (PC)  +  2  if  TO  =  0 

Jump  to  specified  address  if  Test  0  is  a  t. 

0 
»7 

0 

36 

35 

34 

0 
33 

1 

32 

0 

80 

2 

JT1  addr 

(PC  0 -7) -addr  if  T1  =1 
(PC) -(PC) +  2  if  T1  =0 

Jump  to  specified  address  if  Test  1  >s  a  1 

0 
»7 

36 

0 

35 

34 

0 
33 

32 

0 
80 

2 

JZ  addr 

(PC  0-7)i-  addr  if  A  =  0 

Jump  to  specified  address  if  Accumulator 

0 

0 

0 

1 

0 

2 

(PC)  «-  (PC)  +  2  if  A  =  0 

is  0 

36 

35 

84 

33 

32 

31 

30 

CONTROL 

Enable  the  External  Interrupt  input 

0 

0 

0 

0 

0 

0 

1 

OIS  I 

Disable  the  External  Interrupt  input 

0 

0 

0 

1 

0 

1 

0 

; 

SEL RBO 
SELRB1 

IBS)  -  0 
(BS)  +-  1 

Select  Bank  0  (location*  0  -  7)  of  Data 
Memory 

Select  Bank  0  (locations  24  -  31 )  of 
Data  Memory 

1 

1 

0 
0 

0 

1 

0 
0 

1 

1 

0 
0 

1 

1 

EN  DMA 

Enable  DMA  Handshake 

1 

1 

1 

0 

1 

0 

1 

EN  FLAGS 

Enable  Interrupt  to  Master  Device 

1 

1 

0 

0 

1 

0 

1 

1 

DATA 

MOVES 

MOV  A.  =  data 

(A)  -  data 

Move  Immediate  the  specified  data  into 
the  Accumulator 

0 
07 

0 
<*6 

0 

d4 

0 

13 

0 

d2 

1 

<*1 

dO 

2 

2 

MOV  A,  Rr 

(A)  -  (Rr).  r  =  0  7 

Move  the  contents  of  the  designated 
registers  into  the  Accumulator 

1 

MOV  A.  @>  Rr 

(A)  -  ((Rr))  r  -  0  1 

Move  Indirect  the  contents  of  data 
memory  location  into  the  Accumulator 

1 

0 

0 

0 

1 

MOV  A.  PSW 

(A)  •  (PSW) 

Move  contents  of  the  Program  Status 
Word  into  the  Accumulator 

1 

0 

0 

1 

MOV  Rr.  «  data 

(Rr)  ►  data,  r  =  0  7 

Move  Immediate  the  specified  data  into 
the  designated  register 

d7 

0 
d6 

1 

d4 

1 

°3 

d2 

di 

2 

2 

MOV  Rr  A 

<Rr)-(A).r  =  0  7 

Move  Accumulator  Contents  into  the 
designated  register 

0 

0 

1 

MOV  @  Rr,  A 

«Rr))  -  (A),  r  =  0  1 

Move  Indirect  Accumulator  Contents 
into  data  memory  location 

1 

0 

0 

0 

0 

0 

MOV  <9>  Rr.  u  data 

((Rr))  -  data  r  *  0  1 

Move  Immediate  the  specified  data  into 
data  memory 

d7 

0 

d6 

d4 

0 

13 

0 

d2 

0 

2 

MOV  PSW.  A 

(PSW)  •  (A) 

Move  contents  of  Accumulator  into  the 
program  status  word 

0 

1 

1 

1 

MOVP  A,  @  A 

(PCO    7) -(A) 
(A)  -  ((PCI) 

Mo»e  data  in  the  current  page  into  the 
Accumulator 

1 

0 

0 

0 

0 

2 

MOVP3  A  @  A 

(PC  0    7)  -  (A) 
(PC  8-  10) -011 
(A)  -  (IPO) 

Move  Program  data  in  Page  3  into  the 
Accumulator 

1 

1 

0 

0 

0 

2 

XCH  A,  Rr 

(A)Z  (Rrl.r  »  0-7 

Exchange  the  Accumulator  and 
designated  register's  contents 

0 

0 

0 

XCH  A.  •  Rr 

(A)  C  ((Rr)).  r  ■  0  -  1 

Exchange  Indirect  contents  of  Accumu 
lator  and  location  m  data  memory 

0 

0 

0 

0 

0 

0 

XCHO  A.  •  Rr 

(AO-3)t;((Rr)IO-3». 
r  «0-  1 

Exchange  Indirect  4  bit  contents  of 

0 

0 

0 

0 

0 

1 

CPLC 

(C)  -  NOT  (C) 

Ft 

Complement  Content  of  carry  bit 

0 

0 

0 

1 

CPLFO 

(FO)  -  NOT  (FO) 

Complement  Content  of  Flag  FO 

0 

0 

0 

1 

CPL  F1 

(F1)  -  NOT  (F1) 

Complement  Content  of  Flag  F1 

0 

0 

0 

1 

CLR  C 

(C)  -  C 

Clear  content  of  carry  bit  to  0 

0 

0 

1 

CLR  FO 

(FO)  -  0 

Clear  content  of  Flag  0  to  0. 

0 

0 

0 

0 

CLR  F1 

(FD-0 

Clear  content  of  Flag  1  to  0 

0 

0 

0 

0 

1 

• 

MOV  STS.  A 

ST4-ST7  -  A4-A7 

Move  high  order  4  bits  of  Accum- 

0 

0 

1 

0 

0 

0 

0 

1 

4-79 


/iPD8041  A/8741  A 

INSTRUCTION  SET  (CONT.) 


INSTRUCTION  CODE 

FLAGS 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7  06 

D5 

D4 

D3 

D2 

D1 

DO 

CYCLES 

BYTES 

C   AC    FO    F1    IBF  OBF 

ST4.7 

INPUT/ 

XITPUT 

ANL  Pp.  "  data 

iPp)  •  (Ppl  AND  data" 

Logical  and  Immediate  specified  data 

1 

0 

0 

1 

1 

0 

P 

P 

2 

2 

p  --  1  2 

with  designated  port  (1  or  2) 

<*7 

d<3 

d4 

d3 

d2 

do 

ANLD  Pp.  A 

(Pp)  -  (Pp)  AND  (A  0  3) 

Logical  and  contents  of  Accumulator 

1 

0 

0 

1 

1 

1 

P 

p 

2 

1 

p  *  4  7 

with  detonated  port  (4  —  7). 

IN  A.  Pp 

(A)  -  (Pp),  p  =  1  2 

Input  data  from  designated  port  (1  or  2) 

0 

0 

0 

0 

1 

0 

P 

p 

2 

1 

into  Accumulator 

IN  A.  DBB 

(A)  -  (DBB) 

Input  strobed  DBB  data  into 

0 

0 

1 

0 

0 

0 

1 

0 

1 

1 

Accumulator  and  clear  IBF 

MOVO  A.  Pp 

(AO-3)~(Pp)  p  =  4-  7 

Move  contents  of  designated  port  (4  -  7) 

0 

0 

0 

0 

P 

P 

(A  4  7>-0 

into  Accumulator 

MOVO  Pp.  A 

(Pp)  -  A  0    3  p  =  4  7 

Move  contents  of  Accumulator  to 

0 

0 

1 

1 

P 

p 

1 

1 

designated  port  (4-7) 

ORLD  Pp.  A 

(Pp)  -  (Pp)  OR  (A  0  3) 

Logical  or  contents  of  Accumulator  with 

1 

0 

0 

0 

p 

p 

1 

1 

p  =  4  7 

designated  port  (4-7) 

ORLPp.  =  data 

(Pp)  -  (Pp)  OR  data 

Logical  or  Immediate  specified  data  with 

1 

0 

0 

0 

1 

0 

P 

p  -  1  2 

'designated  port  (1  or  2) 

d7 

d4 

d3 

d2 

dO 

OUT  DBB.  A 

(DBB)  (A) 

Output  contents  of  Accumulator  onto 

0 

0 

0 

0 

0 

0 

1 

0 

DBB  and  set  OBF. 

OUTL  Pp.  A 

(Pp)  •  (A),  p  =  1  2 

Output  contents  of  Accumulator  to 

0 

0 

0 

P 

p 

designated  port  (1  or  2) 

REG 

STERS 

OEC  Rr  (Rr) 

(Rr)  -  (Rr)     1  r  =  0  7 

Decrement  by  1  contents  of  designated 
register 

1 

0 

0 

1 

INC  Rr 

(Rr)  -  (Rr)  +1  r  =  0  7 

Increment  by  1  contents  of  designated 

0 

0 

0 

register 

INC  @  Rr 

((Rr))  -  ((Rr))  +  1 

Increment  Indirect  by  1  the  contents  of 

0 

0 

0 

0 

0 

0 

r  =  0  1 

data  memory  location 

SUBROUTINE 

CALL  addr 

(ISP))  -  (PC).  (PSW4  7) 

Call  designated  Subroutine 

310 

39 

38 

0 

0 

0 

2 

(SP)  •  (SP>  +  1 

37 

36 

as 

a4 

«3 

32 

30 

(PC  8    10)  •  addr  8  10 

(PC  0    7)  -  addr  0  7 

(PC  11)  -  DBF 

RET 

(SP)  -  (SP)  1 

Return  from  Subroutine  without 

0 

0 

0 

0 

0 

2 

(PC)  •  ((SP)) 

restoring  Program  Status  Word 

RETR 

(SP)  •  (SP)  1 

Return  from  Subroutine  restoring 

0 

0 

0 

0 

2 

(PCI  -  HSP» 

Program  Status  Word 

(PSW4    7)~  ((SP)) 

TIMER/ 

COUNTER 

EN  TCNTI 

Enable  Internal  interrupt  Flag  for 

0 

0 

0 

0 

0 

1 

Timer/Counter  output 

OIS  TCNTI 

Disable  Internal  interrupt  Flac  for 

0  • 

0 

0 

1 

0 

1 

Timer/Counter  output 

MOV  A.  T 

(A) •  (T) 

Move  contents  of  Timer/Counter  into 

0 

1 

0 

0 

0 

0 

0 

1 

Accumulator 

MOV  T.  A 

(T)  -  (A) 

Move  contents  of  Accumulator  into 

0 

1 

1 

0 

0 

0 

0 

Timer/Counter 

STOP  TCNT 

Stop  Count  for  Event  Counter 

0 

1 

1 

0 

0 

1 

0 

STRT  CNT 

Start  Count  for  Event  Counter 

0 

1 

0 

0 

0 

1 

0 

1 

STRTT 

Start  Count  for  Timer 

0 

1 

0 

0 

1 

0 

1 

MISCEl 

LANEOUS 

NOP 

No  Operation  performed 

0 

0 

0 

0 

0 

0 

0 

0 

Notes     (T)  Instruction  Code  Designations  r  ana  p  form  the  binary  representation  of  the  Registers  and  Ports  involved. 

(2)  The  dot  under  the  appropriate  flag  bit  indicates  that  its  content  is  subject  to  change  by  the  instruction  it  appears  in. 

(3)  References  to  the  address  and  data  are  specified  in  bytes  2  and  or  1  of  the  instruction. 

0  Numerical  Subscripts  appearing  in  the  FUNCTION  column  reference  the  specific  bits  affected. 


Symbol  Definitions: 


SYMBOL 

DESCRIPTION 

SYMBOL 

DESCRIPTION 

A 

The  Accumulator 

Pd 

Port  Designator  (p  =  1,  2  or  4  -  7) 

AC 

The  Auxiliary  Carry  Flag 

PSW 

Program  Status  Word 

addr 

Program  Memory  Address  (12  bits) 

Rr 

Register  Designator  (r  =  0,  1  or  0  -  7) 

Bb 

Bit  Designator  (b  =  0  -  7) 

SP 

Stack  Pointer 

BS 

The  Bank  Switch 

T 

Timer 

BUS 

The  BUS  Port 

TF 

Timer  Flag 

C 

Carry  Flag 

TQ'T1 

Testable  Inputs  0,  1 

CLK 

Clock  Signal 

X 

External  RAM 

CNT 

Event  Counter 

# 

Prefix  for  Immediate  Data 

D 

Nibble  Designator  (4  bits) 

@ 

Prefix  for  Indirect  Address 

data 

Number  or  Expression  (8  bits) 

$ 

Program  Counter's  Current  Value 

DBF 

Memory  Bank  Flip-Flop 

M 

Contents  of  External  RAM  Location 

F0.Fl 

Flags  0,  1 

((x)) 

Contents  of  Memory  Location  Addressed 

1 

Interrupt 

by  the  Contents  of  External  RAM  Location. 

P 

"In-Page"  Operation  Designator 

Replaced  By 

IBF 

Input  Buffer  Full  Flag 

OBF 

Output  Buffer  Full 

DBB 

Data  Bus  Buffer 

4-80 


jiPD8041  A/8741  A 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  lxPD8041AC 

Ceramic,  fxPD8041AD 

Cerdip,  fxPD8741AD,  has  quartz  window 


4-81 


8041  A/8741  ADS-REV3-7-83-CAT 


Notes 


4-82 


SEC 


|jlPD8048H/|jlPD8035HL 
FAMILY  OF  SINGLE  CHIP 
8-BIT  MICROCOMPUTERS 


Description 

The  |xPD8048H  family  of  single  chip  8-bit  microcomputers  is 
comprised  of  the  uPD8048H  and  the  uPD8035HL  The  pro- 
cessors in  this  family  differ  only  in  their  internal  program 
memory  options:  The  uPD8048H  with  1K  x  8  bytes  of  mask 
ROM  and  the  |xPD8035HL  with  external  memory. 
Features 

□  Fully  Compatible  with  Industry  Standard  8048/8748/8035 

□  HMOS  Silicon  Gate  Technology  Requiring  a  Single 
+  5V  Supply 

□  2.5  fxs  Cycle  Time.  All  Instructions  1  or  2  Bytes 

□  Interval  Timer/Event  Counter 

□  64  x  8  Byte  RAM  Data  Memory 

□  External  and  Timer  Interrupts 

□  96  Instructions:  70%  Single  Byte 

□  27  I/O  Lines 

□  Internal  Clock  Generator 

□  8  Level  Stack 

□  Compatible  with  8080A/8085A  Peripherals 

□  Available  in  Both  Ceramic  and  Plastic  40  Pin  Packages 

Functional  Description 

The  NEC  |xPD8048H  and  llPD8035HL  are  single  compo- 
nent, 8-bit,  parallel  microprocessors  using  N-channel  silicon 
gate  MOS  technology.  The  uPD8048H  family  of  components 
functions  efficiently  in  control  as  well  as  in  arithmetic  applica- 
tions. Standard  logic  function  implementation  is  facilitated  by 
the  large  variety  of  branch  and  table  look-up  instructions. 
The  uPD8048H/8035HL  instruction  set  is  comprised  of  1 
and  2  byte  instructions  with  over  70%  of  them  single-byte 
and  requiring  only  1  or  2  cycles  per  instruction  with  over  50% 
single-cycle. 

The  uPD8048H  series  of  microprocessors  will  function  as 
stand  alone  microcomputers.  Their  functions  can  easily 
be  expanded  using  standard  8080A/8085A  peripherals 
and  memories. 

The  |xPD8048H  contains  the  following  functions  usually  found 
in  external  peripheral  devices:  1024  x  8  bits  of  ROM  program 
memory;  64  x  8  bits  of  RAM  data  memory;  27  I/O  lines;  an 
8-bit  interval  timer/event  counter;  oscillator  and  clock  circuitry. 
The  |xPD8035HL  is  intended  for  applications  using  exter- 
nal program  memory  only.  It  contains  all  the  features  of  the 
uPD8048H  except  the  1024  x  8-bit  internal  ROM.  The  exter- 
nal program  memory  can  be  implemented  using  standard 
8080A/8085A  memory  products. 

Pin  Identification 


Symbol 


Testable  input  using  conditional  transfer  functions  JT0  and 
JNT0.  The  internal  State  Clock  (CLK)  is  available  to  T0  using 
the  ENTO  CLK  instruction.  T0  can  also  be  used  during  pro- 
gramming as  a  testable  flag. 


One  side  of  the  crystal  input  for  external  oscillator  or  fre- 
quency (non-TTL  compatible  V,H). 


The  other  side  of  the  crystal  input. 


Active  low  input  for  processor  initialization.  RESET  is  also 
used  for  PROM  programming  verification  and  power-down 
(non-TTL  compatible  V,H). 


Pin                                              _  iS 

No. 

Symbol 

5 

SS 

Single  Step  input  (active-low).  SS  together  with  ALE  allows 
the  processor  to  "single-step"  through  each  instruction  in 
program  memory. 

6 

IFTf 

Interrupt  input  (active-low).  INT  will  start  an  interrupt  if  an 
enable  interrupt  instruction  has  been  executed.  A  reset  will 
disable  the  interrupt.  INT  can  be  tested  by  issuing  a  condi- 
tional jump  instruction. 

7 

EA 

External  Access  input  (active-high).  A  logic  "1"  at  this  input 
commands  the  processor  to  perform  all  program  memory 
fetches  from  external  memory. 

8 

RD 

READ  strobe  output  (active-low).  RDwill  pulse  low  when  the 
processor  performs  a  BUS  READ.  RD  will  also  enable  data 
onto  the  processor  BUS  from  a  peripheral  device  and  function 
as  a  READ  STROBE  for  external  DATA  MEMORY. 

9 

PSEN 

Program  Store  Enable  output  (active-low).  PSEN  becomes 
active  only  during  an  external  memory  fetch. 

10 

WR 

WRITE  strobe  output  (active-low).  WRwill  pulse  low  when  the 
processor  performs  a  BUS  WRITE.  WR  can  also  function  as  a 
WRITE  STROBE  for  external  DATA  MEMORY. 

11 

ALE 

Address  Latch  Enable  output  (active-high).  Occurring  once 
each  cycle,  the  falling  edge  of  ALE  latches  the  address  for 
external  memory  or  peripherals  ALE  can  also  be  used  as  a 
clock  output. 

12-19  D0-D7BUS 


8-bit,  bidirectional  port.  Synchronous  reads  and  writes  can  be 
performed  on  this  port  using  RD  and  WR  strobes.  The  con- 
tents of  the  D0  -  D7  BUS  can  be  latched  in  a  static  mode. 
During  an  external  memory  fetch,  the  D0  -  D7  BUS  holds  the 
least  significant  bits  of  the  program  counter.  PSEN  controls 
the  incoming  addressed  instruction.  Also,  for  an  external 
RAM  data  store  instruction  the  D0  -  D7  BUS,  controlled  by 
ALE,  RD,  and  WR,  contains  address  and  data  information. 


20 

VSS 

Processor's  GROUND  potential. 

21-24, 
35-38 

P20-P27: 

PORT  2 

Port  2  is  the  second  of  two  8-bit  quasi-bidirectional  ports. 
For  external  data  memory  fetches,  the  four  most  significant 
bits  of  the  program  counter  are  contained  in  P20  -  P23  Bits 
P20  -  P23  are  also  used  as  a  4-bit  I/O  bus  for  the  |j.PD8243, 
INPUT/OUTPUT  EXPANDER. 

25 

PROG 

PROG  is  used  as  an  output  strobe  for  the  jxPD8243. 

26 

Vdd 

VDD  must  be  set  to  +5V  for  normal  operation.  VDD  functions 
as  the  Low  Power  Standby  input  for  the  |xPD8048H. 

27-34 

P10_P17: 

PORT  1 

Port  1  is  one  of  two  8-bit  quasi-bidirectional  ports. 

39 

T1 

Testable  input  using  conditional  transfer  functions  JT1  and 
JNT1.  T1  can  be  made  the  counter/timer  input  using  the  STRT 
CNT  instruction. 

40 

Vcc 

Primary  Power  Supply.  Vcc  must  be  +  5V  for  operation  of  the 
PD8035H  and  |xPD8048H. 

Pin  Configuration 


ToC  1 

XTAL 1 C  2 

XTAL2  C  3 

RESET  C  4 

SS  £  5 

INT  C  6 

EA  C  7 

RD  C  8 

PSEN  C  9 

WR  C  10 

ALE  C  11 

DBQC  12 

DB1  C  13 

DB2  C  14 

DB3C  15 

DB4C  16 

DB5C  17 

DB6C  18 

DB7  C  19 
:C20 


8048H/ 
8035HL 


Rev/3 

4-83 


vss* 


40  ^  vcc 

39  □  T1 

38  □  P27 

37  3P26 

36  □  P25 

35  □  P24 

34  □  P17 

33  □  P16 

32  □  P15 

31  □  P14 

30  □  P13 

29  □  P12 

28  □  P11 

27  □  P10 

26  ^  VDD 

25  □  PROG 

24  □  P23 

23  □  P22 

22  1  P21 

21  □  P20 


,PD8048H/8035HL 

Block  Diagram 


Power  Supply 


|VDD      |VCC  |VSS 
+  5V  Ground 
Supply    (Low  Power 
Standby) 

Oscillator 
Frequency 


Port  2  Latch  (Low  4) 
and  Expander 
Port  I/O 


Bus  Buffer 
Port  2 


Port  2 
Latch 
(High  4) 


Timer  and 
Event  Counter 


Accumulator 
(8) 


Counter  (4) 


Resident  Program  Memory 
ROM  ((xPD8048H  only) 
1024  x  8 


Expansion  to  Additional 
External  Memory  and  I/O 


Lower 
Program 
Counter 


8-Bit  Internal  Bus 


Temporary 
Register  (8) 


Accumulator 
Latch 


Flags 


Arithmetic 
I  Logic  Unit 


(8) 


Bus  Latch 
Low  Program 
Counter's  Temp 
Register 


Program 
Status 
Word 


Instruction 
Register/Decoder 


RAM  Address 
Register 


Adjust 


Conditional 
Branch 
Logic 


-TestO 

-Testl 

-INT 

-FlagO 

-Flagl 

-Timer  Flag 

-Carry 

-Acc 

-Acc  Bit  Test 


Control  and  Timing 

RESET  PROG 

XTAL  XTAL 

INT 

EA           1      2  ALE 

PSEN 

SS 

RD  WR 

>  Initial 


PROM/Expander 
Strobe 


CPU/Memory 
Separate 


Oscillator/ 
Crystal 


Address 

sc«cte  Memory 
SS  Enab,e 


"TTT 


Bus 
Buffer 

and 
Latch 
Portl 


Multiplexer 


Register  3 


Register  7 


8-Level  Stack 
(Variable  Word  Length) 


Optional  Second 
Register  Bank 


Resident  Data  Memory  —  RAM 
(64x8) 


Single 
Step 


Read  Write 
Strobes 


Note:  (iPD8035H  does  not  include  ROM. 


4-84 


DC  Characteristics 

Ta  =  0°Cto  +70°C;  Vcc  =  VPP  =  +5V  ±  10%;  Vss  =  0V 


Limits 

Parameter 

Symbol 

Min 

Typ  Max 

Unit 

Test  Conditions 

Input  Low  Voltage  (All 
Except  XTAL1.XTAL  2) 

V,L 

-05 

0.8 

V 

Input  Low  Voltage  (RESET, 
X1.X2) 

V,L1 

-0.5 

0.8 

V 

Input  High  Voltage  (All 
Except  XTAL1.XTAL  2, 
RESET) 

V,H 

2.0 

VCc 

V 

Input  High  Voltage  (RESET, 
XTAL 1,  XTAL2) 

V|H1 

3.8 

Vcc 

V 

Output  Low  Voltage  (BUS) 

Vol 

0.45 

V 

l0L  =  2.0  mA 

Output  Low  Voltage  (RD, 
WR,  PSEN,  ALE) 

V0L1 

0.45 

V 

l0L  =  2.0  mA 

Output  Low  Voltage  (PROG) 

v0L2 

0.45 

V 

l0L  =  2.0  mA 

Output  Low  Voltage  (All 
Other  Outputs) 

VOL3 

0.45 

V 

Iql  =  20  mA 

Output  High  Voltage  (BUS) 

V0H 

2.4 

V 

l0H  =  -400  ^ A 

Output  High  Voltage  (RD^ 
WR,  PSEN,  ALE) 

V0H1 

2.4 

V 

l0H=  -400  ^A 

Output  High  Voltage  (All 
Other  Outputs) 

V0H2 

2.4 

V 

l0H  =  -40jiA 

Input  Leakage  Current 
(T^INT) 

'lL 

±10 

(xA 

Vss  «  V,N  «  Vcc 

Input  Leakage  Current 
(Pio-Pi7.P2o-P27.EA,SS) 

>IL1 

-500 

M-A 

vcc  55  V,N  s=  Vss  +  0.45V 

Output  Leakage  Current 
(BUS,  T0-  High  Impedance 
State) 

l0L 

±10 

Vcc  >VIN3=VSS  +  0.45V 

Power  Down  Supply  Current 

•dd 

4  8 

mA 

Ta  =  25°C 

Total  Supply  Current 

'dd  +  'cc 

50  80 

mA 

Ta  =  25°C 

RAM  Standby  Voltage 

VDD 

2.2 

5.5 

V 

Standby  Mode. 
Reset  €  0.6V 

Absolute  Maximum  Ratings* 


Ta  =  25C 

Operating  Temperature 

0°Cto  +70°C 

Storage  Temperature  (Ceramic  Package) 

-65°Cto  +150°C 

Storage  Temperature  (Plastic  Package) 

-65°Cto  +150°C 

Voltage  on  Any  Pin 

-0.5V  to  +7V© 

Power  Dissipation 

1.5  W 

Note:  <D  With  respect  to  ground 


MPD8048H/8035HL 


AC  Characteristics 

Ta  =  0°C  to  70°C;  Vcc  =  Vpp  =  5V  ±  10%;  Vss  =  OV 


Limits 

fi»_  i  and 
•l»CY)  ana 

Test  Conditions  © 

Parameter 

Symbol 

Min 

Typ 

Max 

Unit 

ALE  Pulse  Width 

tLL 

410 

ns 

7/30  tCY  -170 

Addr  Setup  to  ALE 

f  AL 

220 

ns 

2/15  tCY  -110 

Addr  Hold  from  ALE 

tLA 

120 

ns 

1/15  tCY  -40 

Control  Pulse  Width 
(RD,  WR) 

lCC1 

Control  Pulse  Width  (PSEN) 

tcC2 

800 

ns 

2/5  tCY  -200 

Data  Setup  WR 

*DW 

880 

ns 

13/30tCY  -200 

Data  Hold  after  WR 

*WD 

110 

ns 

1/15 tCY  -50© 

Data  Hold  (RD,  PSEN) 

*DR 

0 

220 

ns 

1/10 tCY  -30 

RD  to  Data  in 

*RD1 

800 

ns 

2/5  tCY  -200 

PSEN  to  Data  in 

lRD2 

550 

ns 

3/10  tCY  -200 

Addr  Setup  to  WR 

*AW 

680 

ns 

1/3  tCY  -150 

Addr  Setup  to  Data  (RD) 

*AD1 

1570 

ns 

11/15tCY  -250 

Addr  Setup  to  Data  (PSEN) 

*AD2 

1090 

ns 

8/15  tCY  -250 

Addr  Float  to  S5,  WD 

*AFC1 

290 

ns 

2/15  tCY  -40 

Addr  Float  to  PSEN 

WC2 

40 

ns 

1/30  tCY  -40 

ALE  to  Control  (RD,  WR) 

*LAFC1 

420 

ns 

1/5  tCY  -75 

ALE  to  Control  (PSEN) 

*LAFC2 

170 

ns 

1/10  tCY  -75 

Control  to  ALE 
(RD,  WR,  PROG) 

*CA1 

1/15       —  40 

Control  to  ALE  (PSEN) 

*CA2 

620 

ns 

4/15tCY  -40 

Port  Control  Setup  to  PROG 

tCP 

210 

ns 

1/10  tCY  -40 

Port  Control  Hold  to  PROG 

tpC 

460 

ns 

4/15  tCY  -200 

PROG  to  P2  Input  Valid 

tPR 

1300 

ns 

17/30  tCY  -120 

Input  Data  Hold  from  PROG 

tPF 

250 

ns 

1/10  tCY 

Output  Data  Setup 

tDP 

850 

ns 

2/5  tCY  -150 

Output  Data  Hold 

tpo 

200 

ns 

1/10  tCY  -50 

PROG  Pulse  Width 

tpp 

1500 

ns 

7/10  tCY  -250 

Port  2  I/O  Setup  to  ALE 

tpL 

460 

ns 

4/15  tcY  -200 

Port  2  I/O  Hold  to  ALE 

tLP 

150 

ns 

1/10  tCY  -100 

Port  Output  from  ALE 

tpv 

850 

ns 

3/10  tCY  +100 

Cycle  Time 

tcY 

25 

M-S 

6MHz 

TO  Rep  Rate 

*OPRR 

500 

ns 

3/15  tCY 

Notes:  ©  Control  Outputs  CL  =  80pF 
BUS  Outputs  CL  =  150pF 
©  BUS  High  Impedance  Load  20pF 


Logic  Symbol 


*COMMENT:  Exposing  the  device  to  stresses  above  those 
listed  in  Absolute  Maximum  Ratings  could  cause  permanent 
damage.  The  device  is  not  meant  to  be  operated  under 
conditions  outside  the  limits  described  in  the  operational 
sections  of  this  specification.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


Port  Expander 
Strobe 


4-85 


[XPD8048H/8035HL 

Timing  Waveforms 

Instruction  Fetch  from  External  Memory 


ALE   f"" 


8 


J  L 


L 


-J  «■» 


BUS  Floating)  fy»    X  Floating  X   \  X    Floatin9  X 


Bead  from  External  Data  Memory 


|-*-*LAFC1-*>K-  tCC1— "f^CAl*- 


RD 

Address 
Bus  Floatin9> 


\  ~H  Wei  *—  — *J  K~  *i 


Floating 


Write  to  External  Memory 

ALE         I  1 


1_ 


Bus  Floating yj~\     X  Floating  X  Pata  X  Floating 


Port  2  Timing 


Expander 


2 


Expander 
Port 


-r 


\\         PCH  ^lort  2o.3  Data  ^"  Port  Control  )|*    Output  Date 


PCH  Xprt  2„3  Data  J([p^rt"Col^  ^Tj( 


— *|tCP  —t, 


Input  Data 


BUS  Output  High  Voltage  vs.  Source  Current 


Typ 

4- 

l 

VCC  =  4 

\ 

OV  2V  4V 


Port  PI  and  P2  Output  High  Voltage  vs.  Source  Current 


50nA 


vcc  =  6 

Typ 

\ 

OV  2V  4V 


BUS  Output  Low  voltage  vs.  Sink  Current 


'  Vcc  =  4 

Typ 

f 

OV  1V  2V 

Vol 


4-86 


!xPD8048H/8035HL 


Instruction  Set  (for  Symbol  Definitions,  see  page  8.) 


Mnemonic 

Function 

Description 

I>7 

»6 

Instruction  Code 
D5     D4     D3  D2 

Do 

Flags 

Cycles     Bytes      C  AC  FO 

Accumulator 

ADO  A,  #  data 

(A)<-(A)  +  data 

Add  Immediate  the  specified  Data  to  the 
Accumulator. 

0 
d7 

0 
d6 

0 
d5 

0 

d4 

0 
d3 

0 
d2 

1 

di 

2             2  • 

ADD  A,  Rr 

(A)«-(A)  +  (Rr) 
torr  =  0-7 

Add  contents  of  designated  register  to  the 
Accumulator. 

0 

1 

1 

0 

1 

r 

ADD  A,  @  Rr 

(A)*- (A)  +  ((Rr)) 
forr  =  0-1 

Add  Indirect  the  contents  of  the  data  mem- 
ory location  to  the  Accumulator. 

0 

1 

1 

0 

0 

0 

0 

AD  DC  A,  #  data 

(A)*- (A)  +  (C)  +  data 

Add  Immediate  with  carry  the  specified 
data  to  the  Accumulator. 

0 
d7 

0 

0 
d5 

1 

d4 

0 
d3 

0 
d2 

1 

di 

ADDC  A,  Rr 

(A)*- (A)  +  (C)  +  (Rr) 
for  r  =  0-7 

Add  with  carry  the  contents  of  the  desig- 
nated register  to  the  Accumulator. 

0 

1 

1 

1 

1 

r 

r 

r 

1             1  • 

ADDC  A,  @  Rr 

(A)«-(A)  +  (C)  +  ((Rr)) 
forr  =  0-1 

Add  Indirect  with  carry  the  contents  of  data 
memory  location  to  the  Accumulator. 

0 

1 

1 

1 

0 

0 

0 

1 

ANLA,#data 

(A) -(A)  AND  data 

Logical  AND  specified  Immediate  Data  with 
Accumulator. 

0 
d7 

1 

d6 

0 
d5 

1 

d4 

0 
d3 

0 

d2 

1 

di 

i 

ANL  A,  Rr 

(A)  <-(A)  AND(Rr) 
forr  =  0-7 

Logical  AND  contents  of  designated  register 
with  Accumulator. 

0 

1 

0 

1 

1 

r 

r 

r 

1  1 

ANL  A,  @  Rr 

(A)*-(A)AND((Rr)) 
forr  =  0-1 

Logical  AND  Indirect  the  contents  of  data 
memory  with  Accumulator 

0 

1 

0 

1 

0 

0 

0 

1 

CPL  A 

(A) *-  NOT  (A) 

Complement  the  contents  of  the 
Accumulator. 

0 

0 

1 

1 

0 

1 

1 

— - — 



CLRA 

(A)<-0 

CLEAR  the  contents  of  the  Accumulator. 

0 

0 

1 

0 

0 

1 

1 

— 

 _  

DA  A 

DECIMAL  ADJUST  the  contents  of  the 
Accumulator. 

0 

1 

0 

1 

0 

1 

1 

1 

1             1  • 

DEC  A 

(A)*-(A)-1 

DECREMENT  by  1  the  accumulator's 
contents. 

0 

0 

0 

0 

0 

1 

1 

INC  A 

(A)«-(A)  +  1 

Increment  by  1  the  accumulator's  contents. 

0 

0 

0 

1 

0 

1 

1 

1 

1  1 

ORL  A,  #  data 

(A)*- (A)  OR  data 

Logical  OR  specified  immediate  data  with 
Accumulator. 

0 
d7 

1 

d6 

0 
d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

do 

ORL  A,  Rr 

(A)*-(A)OR(Rr) 
forr  =  0-7 

Logical  OR  contents  of  designated  register 
with  Accumulator. 

0 

1 

0 

0 

1 

r 

r 

r 

1  1 

ORL  A,  @  Rr 

(A)«-(A)OR((Rr)) 
forr  =  0-1 

Logical  OR  Indirect  the  contents  of  data 
memory  location  with  Accumulator. 

0 

1 

0 

0 

0 

0 

0 

RL  A 

(AN  +  1)*-(AN) 
(Ao)«-(A7) 
for  N  =  0-6 

Rotate  Accumulator  left  by  1  bit  without 
carry. 

1 

1 

1 

o 

o 

1 

1 

RLC  A 

(AN  +  1)*-(AN);N  =  0-6 

(Ao)-(C) 

(C)*-(A7) 

Rotate  Accumulator  left  by  1  bit  through 
carry. 

1 

1 

1 

1 

0 

1 

1 

1 

1             1  • 

RR  A 

(AN)«-(AN  +  1);N  =  0-6 
(A7)  «-  (Ao) 

Rotate  Accumulator  nght  by  1  bit  without 
carry. 

0 

1 

1 

1 

0 

1 

1 

1 

1  1 

RRC  A 

(AN)<-(AN  +  1);N  =  0-6 

(A7)-(C) 

(C)-(A0) 

Rotate  Accumulator  right  by  1  bit  through 
carry. 

0 

1 

1 

0 

0 

1 

1 

1             1  • 

SWAP  A 

(A4.7)-(Ao.3) 

Swap  the  two  4-brt  nibbles  in  the 
Accumulator. 

0 

1 

0 

0 

0 

1 

1 

XRLA,#data 

(A) «- (A)  XOR  data 

Logical  XOR  specified  immediate  data  with 
Accumulator. 

1 

d7 

1 

d6 

0 
d5 

1 

d4 

0 
d3 

0 
d2 

1 

di 

XRLA,  Rr 

(A)*-(A)XOR(Rr) 
forr  =  0-7 

Logical  XOR  contents  of  designated  register 
with  Accumulator. 

1 

1 

0 

1 

1 

r 

r 

XRL  A,  @  Rr 

(A)«-(A)XOR((Rr)) 
forr  =  0-1 

Logical  XOR  Indirect  the  contents  of  data 
memory  location  with  Accumulator. 

1 

1 

0 

1 

0 

0 

0 

Branch 

DJNZ  Rr,  addr 

(Rr)«-(Rr)-1;r  =  0-7 

lf(Rr)  =  0 

(PC  0-7)*-  addr 

Decrement  the  specified  register  and  test 
contents. 

1 

a7 

1 

a6 

1 

a5 

0 
a4 

1 

a3 

r 

a2 

r 

ai 

a0 

2  2 

JBbaddr 

(PC0-7)*-addrifBb  =  1 
(PC)>^(PC)  +  2ifBb  =  0 

Jump  to  specified  address  if  Accumulator 
bit  is  set. 

b2 
a7 

t>i 
a6 

bo 
a5 

1 

a4 

0 
a3 

0 
a2 

1 

ai 

0 
a0 

2  2 

JCaddr 

(PC  0 -7)*-  addr  if  C  =  1 
(PC)*-(PC)  +  2ifC  =  0 

Jump  to  specified  address  if  carry  flag  is 
set. 

1 

a7 

1 

a6 

1 

a5 

1 

a4 

0 
a3 

1 

a2 

1 

ai 

0 
a0 

2  2 

JFOaddr 

(PC  0 -7)*-  addr  if  F0  =  1 
(PC)*-(PC)  +  2ifF0  =  0 

Jump  to  specified  address  if  Flag  F0  is  set. 

1 

a7 

0 
a6 

1 

a5 

1 

a4 

0 
a3 

1 

a2 

1 

ai 

0 
a0 

2  2 

JF1  addr 

(PC  0 -7)^- addr  if  F1  =  1 
(PQ<-(PC)  +  2ifF1  =0 

Jump  to  specified  address  if  Flag  F1  is  set. 

0 
a? 

1 

a6 

1 

a5 

1 

a4 

0 
a3 

1 

a2 

1 

ai 

0 
a0 

2  2 

JMPaddr 

(PC  8 -10)^-  addr  8 -10 

(PC0-7)«-addr0-7 

(PC11)^DBF 

Direct  Jump  to  specified  address  within 
the  2K  address  block. 

aio 
a7 

a9 
a6 

a8 
a5 

0 
a4 

0 

a3 

1 

a2 

0 
ai 

0 
a0 

2  2 

JMPP  @  A 

(PC  0-7)*- ((A)) 

Jump  indirect  to  specified  address  with 
address  page. 

1 

0 

1 

1 

0 

0 

1 

1 

2  1 

JNC  addr 

(PC  0  -  7) «-  addr  if  C  =  0 
(PC)  ^- (PC)  +  2  if  C  =  1 

Jump  to  specified  address  if  carry  flag  is 
low. 

1 

a7 

1 

a6 

1 

a5 

0 
a4 

0 
a3 

1 

a2 

1 

■1 

0 
a0 

2  2 

JNI  addr 

(PC0-7)*-addrifl  =  0 
(PC) «- (PC)  +  2  if  I  =  1 

Jump  to  specified  address  if  interrupt  is  low. 

1 

a7 

0 
ae 

0 
a5 

0 
a4 

0 
a3 

1 

a2 

1 

ai 

0 
a0 

2  2 

4-87 


.PD8048H/8035HL 


Instruction  Set  (Cont.) 


Mnemonic 

Function 

Description 

o7 

l>6 

Instruction  Code 
D5     D4     D3  D2 

Di 

Do 

Flags 

Cycles     Bytes   C  AC  FO  F1 

Branch  (Cont.) 

JNTOaddr 

(PC  0  -  7)  <—  addr  if  TO  =  0 
(PC)*- (PC)  +  2  if  TO  =  1 

Jump  to  specified  address  if  Test  0  is  low. 

0 

a7 

0 
a6 

1 

a5 

0 
a4 

0 

a3 

a2 

1 

ai 

0 
a0 

2  2 

JNT1  addr 

(PC  0 -7)*- addr  If  T1  =0 
(PC)*-(PC)  +  2ifT1  =1 

Jump  to  specified  address  if  Test  1  is  low. 

0 
a/ 

1 

a6 

0 
a5 

0 
a4 

0 
a3 

a2 

1 

ai 

0 

a0 

2  2 

JNZaddr 

(PC  0-7)*- addr  if  A  =  0 
(PC)*-(PC)  +  2ifA  =  0 

Jump  to  specified  address  if  accumulator 
is  non-zero. 

1 

a7 

0 
a6 

0 
a5 

1 

a4 

0 
a3 

a2 

1 

ai 

0 

a0 

2  2 

JTFaddr 

(PC  0 -7)*- addr  If  TF  =  1 
(PC)*- (PC)  +  2lfTF  =  0 

Jump  to  specified  address  if  Timer  Flag  is 
set  to  1. 

0 

a7 

0 
a6 

0 

a5 

1 

a4 

0 

a3 

a2 

1 

ai 

0 
a0 

2  2 

JTOaddr 

(PC  0  -  7)*- addr  if  TO  =  1 
(PC)*- (PC)  +  2  If  TO  =  0 

Jump  to  specified  address  if  Test  0  is  a  1 . 

0 

a7 

0 
a6 

1 

a5 

1 

a4 

0 
a3 

a2 

1 

ai 

0 

a0 

2  2 

JT1  addr 

(PC  0 -7)*- addr  If  T1  =  1 
(PC)*-(PC)  +  2KT1  =0 

Jump  to  specified  address  if  Jest  1  is  a  1 . 

0 

a7 

1 

a6 

0 

a5 

1 

a4 

0 
a3 

a2 

1 

ai 

0 
a0 

2  2 

JZaddr 

(PC  0-7)^- addr  if  A  =  0 
(PC)*-(PC)  +  2ifA  =  0 

Jump  to  specified  address  if  Accumulator 
isO. 

1 

a7 

1 

a6 

0 

a5 

0 
a4 

0 

a3 

a2 

1 

a1 

0 
a0 

2  2 

Control 

EN  I 

Enable  the  External  Interrupt  input. 

0 

0 

0 

0 

0 

0 

1  1 

DISI 

Disable  the  External  Interrupt  input. 

0 

0 

0 

1 

0 

0 

1  1 

ENTOCLK 

Enable  the  Clock  Output  pin  TO. 

0 

1 

1 

1 

0 

0 

1  1 

SELMBO 

(DBF)*-0 

Select  Bank  0  (locations  0  -  2047)  of 
Program  Memory. 

1 

1 

1 

0 

0 

0 

1  1 

SELMB1 

(DBF)*-1 

Select  Bank  1  (locations  2048  -  4095)  of 
Program  Memory. 

1 

1 

1 

1 

0 

0 

1  1 

SEL  RBO 

(BS)*-0 

Select  Bank  0  (locations  0  -  7)  of  Data 
Memory. 

1 

1 

0 

0 

0 

0 

1  1 

SEL  RBI 

(BS)*-1 

Select  Bank  1  (locations  24  -  31)  of  Data 
Memory. 

1 

1 

0 

1 

0 

0 

1  1 

Data  Moves 

MOV  A,  #  data 

(A)*- data 

Move  Immediate  the  specified  data  into  the 
Accumulator. 

0 

d7 

0 

1 

0 
d4 

0 
d3 

0 
d2 

1 

di 

2  2 

MOV  A,  Rr 

(A)*-(Rr);r  =  0-7 

Move  the  Contents  of  the  designated  regis- 
ters into  the  Accumulator. 

1 

1 

1 

1 

1 

r 

r 

1  1 

MCVA,@Rr 

(A)*-((Rr));r  =  0-1 

Move  Indirect  the  Contents  of  data  memory 
location  into  the  Accumulator. 

1 

1 

1 

1 

0 

0 

0 

1  1 

MOV  A,  PSW 

(A)*- (PSW) 

Move  contents  of  the  Program  Status  Word 
into  the  Accumulator. 

1 

1 

0 

0 

0 

1 

1 

1  1 

MOV  Rr,  #  data 

(Rr)*-data;r  =  0-7 

Move  Immediate  the  specified  data  into  the 
designated  register. 

1 

d7 

0 

1 

1 

d4 

1 

d3 

r 

d2 

r 

di 

2  2 

MOV  Rr,  A 

(Rr)*-(A);r  =  0-7 

Move  Accumulator  Contents  into  the  desig- 
nated register. 

1 

0 

1 

0 

1 

r 

r 

1  1 

MOV  @  Rr,  A 

((Rr))*-(A);r  =  0-1 

Move  Indirect  Accumulator  Contents  into 
data  memory  location. 

1 

0 

1 

0 

0 

0 

0 

1  1 

MOV  @Rr,#  data 

((Rr))*-data;r  =  0-1 

Move  Immediate  the  specified  data  into 
data  memory. 

1 

d7 

0 

1 

% 

1 

d4 

0 
d3 

0 
d2 

0 

2  2 

MOV  PSW,  A 

(PSW)*- (A) 

Move  contents  of  Accumulator  into  the  pro- 
gram status  word. 

1 

1 

0 

1 

0 

1 

1 

1  1 

MOVPA,@A 

(PC0-7)*-(A) 
(A)*- ((PC)) 

Move  data  in  the  current  page  into  the 
Accumulator. 

1 

0 

1 

0 

0 

0 

1 

2  1 

MOVP3A,@A 

(PC0-7)*-(A) 
(PC  8- 10)*- 011 
(A)*-((PC)) 

Move  Program  data  in  Page  3  into  the 
Accumulator. 

1 

1 

1 

0 

0 

0 

1 

2  1 

MOVX  A,  @  R 

(A)*-((Rr));r  =  0-1 

Move  Indirect  the  contents  of  external  data 
memory  into  the  Accumulator. 

1 

0 

0 

0 

0 

0 

0 

2  1 

MOVX@R,A 

«Rr))*-(A);r  =  0-1 

Move  Indirect  the  contents  of  the  Accumula- 
tor into  external  data  memory. 

1 

0 

0 

1 

0 

0 

0 

2  1 

XCH  A,  Rr 

(A)^((Rr));r  =  0-7 

Exchange  the  Accumulator  and  designated 
registers  contents. 

0 

0 

1 

0 

1 

r 

r 

1  1 

XCH  A,  @  Rr 

(A)*±((Rr));r  =  0-1 

Exchange  Indirect  contents  of  Accumulator 
and  location  in  data  memory. 

0 

0 

1 

0 

0 

0 

0 

1  1 

XCHD  A,  @  Rr 

(A0-3)^((Rr)(0-3)); 
r  =  0-1 

Exchange  Indirect  4-bit  contents  of 
Accumulator  and  data  memory. 

0 

0 

1 

1 

0 

0 

0 

1  1 

Flags 

CPLC 

(C)*-NOT(C) 

Complement  Content  of  carry  bit. 

0 

1 

0 

0 

1 

1  1 

CPLFO 

(F0)*-NOT(F0) 

Complement  Content  of  Flag  FO. 

0 

0 

1 

0 

0 

1  1 

CPLF1 

(F1)*-NOT(F1) 

Complement  Content  of  Flag  F1 . 

0 

1 

1 

0 

0 

1  1 

CLRC 

(C)*-0 

Clear  content  of  carry  bit  to  0. 

0 

0 

1 

0 

1 

1  1 

CLRFO 

(F0)*-0 

Clear  content  of  Flag  0  to  0. 

0 

0 

0 

0 

0 

1  1 

CLRF1 

(F1)*-0 

Clear  content  of  Flag  1  to  0. 

0 

1 

0 

0 

0 

1  1 

4-88 


|xPD8048H/8035HL 


Instruction  Set  (Cont.) 


Mnomonic 

Function 

Description 

Dt 

D6 

Instruction  Code 
D5     D4     D3  D2 

»1 

Do 

Cycles 

Flags 

Bytes   C  AC   FO  F1 

Input/Output 

ANL  BUS,  #  data 

(BUS)  ^  (BUS)  AND  data 

Logical  AND  Immediate  specified  data  with 
contents  of  BUS. 

1 

d7 

0 
d6 

0 
d5 

1 

d4 

d3 

0 
d2 

0 
di 

0 
do 

2 

2 

ANLPp,#data 

(Pp) «-  (Pp)  AND  data 
P  =  1-2 

Logical  AND  Immediate  specified  data  with 
designated  port  (1  or  2). 

1 

d7 

0 
d6 

0 
d5 

1 

d4 

d3 

0 
d2 

P 

di 

P 
do 

2 

2 

ANLD  Pp,  A 

(Pp)^(Pp)AND(A0-3) 
p  =  4-7 

Logical  AND  contents  of  Accumulator  with 
designated  port  (4-7). 

1 

0 

0 

1 

1 

1 

P 

P 

2 

1 

IN  A,  Pp 

(A)^(Pp);p  =  1-2 

Input  data  from  designated  port  (1  -  2)  into 
Accumulator. 

0 

0 

0 

0 

1 

0 

P 

P 

2 

1 

INS  A,  BUS 

(A)*- (BUS) 

Input  strobed  BUS  data  into  Accumulator. 

0 

0 

0 

0 

1 

0 

0 

0 

2 

1 

MOVD  A,  Pp 

(A0-3)«-(Pp);ps=4-7 
(A4-7)<--0 

Move  contents  of  designated  port  (4-7) 
into  Accumulator. 

0 

0 

0 

0 

1 

1 

P 

P 

2 

1 

MOVD  Pp,  A 

(Pp)  — AO  =  3;p  =  4-7 

Move  contents  of  Accumulator  to 
designated  port  (4-7). 

0 

0 

1 

1 

1 

P 

P 

2 

1 

ORL  BUS,  #  data 

(BUS) -(BUS)  OR  data 

Logical  OR  Immediate  specified  data  with 
contents  of  BUS. 

1 

d7 

0 
d6 

0 

0 

d3 

0 

d2 

0 
di 

0 
do 

2 

2 

ORLDPp,A 

(Pp)<-(Pp)OR(A0-3) 
p  -  4-7 

Logical  OR  contents  of  Accumulator  with 
designated  port  (4 -7> 

1 

0 

0 

0 

1 

P 

P 

2 

1 

ORL  Pp,  #  data 

(Pp)<-(Pp)ORdata 
p  =  1-2 

Logical  OR  Immediate  specified  data  with 
designated  port  (1-2). 

1 

d7 

0 
d6 

0 

0 
d4 

d3 

0 

d2 

P 
di 

P 

do 

2 

2 

OUTL  BUS,  A  © 

(BUS) -(A) 

Output  contents  of  Accumulator  onto  BUS. 

0 

0 

0 

0 

0 

1 

0 

2 

1 

OUTL  Pp,  A 

(Pp)«-(A);p  =  1-2 

Output  contents  of  Accumulator  to 
designated  port  (1-2). 

0 

0 

1 

1 

0 

P 

P 

2 

1 

Registers 

DECRr  (Rr) 

(Rr)^-(Rr)  +  1;r  =  0-7 

Decrement  by  1  contents  of  designated 
register. 

1 

1 

0 

0 

r 

r 

r 

1 

1 

INC  Rr 

(Rr)<-(Rr)  +  1;r  =  0-7 

Increment  by  1  contents  of  designated 
register. 

0 

0 

0 

1 

r 

r 

r 

1 

1 

INC@Rr 

«Rr))*-((Rr))  +  1; 
r  =  0-1 

Increment  Indirect  by  1  the  contents  of  data 
memory  location. 

0 

0 

0 

1 

0 

0 

0 

r 

1 

1 

Subroutine 

CALL  addr 

((SP))^-(PC),(PSW4-7) 

(SP)^(SP)  +  1 

(PC  8  - 10)  <- addr  8 -10 

(PC0-7)«-addr0-7 

(PC  11)^- DBF 

Call  designated  Subroutine. 

a7 

39 

a6 

H 
a5 

1 

a4 

0 

a3 

1 

a2 

0 

a1 

0 
a0 

2 

2 

RET 

(SP)^(SP)  =  1 
(PC)«-((SP)) 

Return  from  Subroutine  without  restoring 
Program  Status  Word. 

1 

0 

0 

0 

0 

0 

1 

1 

2 

1 

RETR 

(SP)*-(SP)  =  1 

(PC)«-((SP)) 

(PSW4-7)«-((SP)) 

Return  from  Subroutine  restoring  Program 
Status  Word. 

1 

0 

0 

1 

0 

0 

1 

1 

2 

1 

Timer/Counter 

ENTCNT1 

Enable  Internal  interrupt  Flag  for  Timer/ 
Counter  output. 

0 

0 

1 

0 

0 

1 

0 

1 

1 

DISTCNTI 

Disable  Internal  interrupt  Flag  for  Timer/ 
Counter  output. 

0 

0 

1 

1 

0 

1 

0 

1 

1 

MOVA.T 

(A)^-(T) 

Move  contents  of  Timer/Counter  into 
Accumulator. 

0 

1 

0 

0 

0 

0 

1 

0 

1 

MCVT.A 

(T)^-(A) 

Move  contents  of  Accumulator  into  Timer/ 
Counter. 

0 

1 

1 

0 

0 

0 

1 

0 

1 

STOP  TCNT 

Stop  Count  for  Event  Counter. 

0 

1 

1 

0 

0 

1 

0 

1 

1 

STRTCNT 

Start  Count  for  Event  Counter. 

0 

1 

0 

0 

0 

1 

0 

1 

1 

STRTT 

Start  Count  for  Timer. 

0 

1 

0 

1 

0 

1 

0 

1 

1 

NOP 

No  Operation  performed. 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

Notes:  ©  Instruction  Code  Designations  r  and  p  form  the  binary  representation  of  the  Registers  and  Ports  involved 

CD  The  dot  under  the  appropriate  flag  bit  indicates  that  its  content  is  subject  to  change  by  the  instruction  it  appears  in 

®  References  to  the  address  and  data  are  specified  in  bytes  2  and/or  1  of  the  instruction 

©  Numerical  Subscripts  appearing  in  the  FUNCTION  column  reference  the  specific  bits  affected 

©  When  the  Bus  is  written  to,  with  an  OUTL  instruction,  the  Bus  remains  an  Output  Port  until  either  device  is  reset  or  a  MOVX  instruction  is  executed 


4-89 


|xPD8048H/8035HL 


Symbol  Definitions 


Symbol 

Description 

A 

The  Accumulator 

AC 

The  Auxiliary  Carry  Flag 

addr 

Program  Memory  Address  (12  bits) 

Bb 

Bit  Designator  (b  =  0  -  7) 

BS         The  Bank  Switch 

BUS 

The  BUS  Port 

C 

Carry  Flag 

CLK 

Clock  Signal 

CNT 

Event  Counter 

D 

Nibble  Designator  (4  bits) 

data 

Number  of  Expression  (8  bits) 

DBF 

Memory  Bank  Flip-Flop 

F0,  F, 

Flags  0, 1 

1  Interrupt 

P 

"In-Page"  Operation  Designator 

pP 

Port  Designator  (p  -  1 ,  2  or  4  -  7) 

PSW 

Program  Status  Word 

Rr 

Register  Designator  (r  =  0, 1  or  0  -  7) 

SP 

Stack  Pointer 

T 

Timer 

TF 

Timer  Flag 

Testable  Flags  0, 1 

X 

External  RAM 

=          Prefix  for  Immediate  Data 

© 

Prefix  for  Indirect  Address 

$ 

Program  Counter's  Current  Value 

(x) 

Contents  of  External  RAM  Location 

((x)) 

Contents  of  Memory  Location  Addressed 

by  the  Contents  of  External  RAM  Location 

Replaced  By 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  (xPD8048HC/35HLC 
Ceramic,  uPD8048HD/35HLD 


4-90 


8048H/8035HLDS-REV3-7-83-CAT-L 


SEC 


(4PD8748 


/xPD8048  FAMILY  OF  SINGLE  CHIP 
8-BIT  MICROCOMPUTERS 

DESCRIPTION    The  (xPD8748  is  a  member  of  the  fxPD8048  family  of  single-bit  8-chip  microcomputers. 

It  differs  from  the  jjlPD8048H/8035HL  in  that  it  contains  2K  of  on-board  EPROM  rather 
than  math  programmable  ROM.  The  jjiPD8748  uses  N-channel  MOS  technology.  Refer 
to  the  |xPD8048H/8035HL  data  sheet  for  additional  information. 


FEATURES     •  Fully  Compatible  With  Industry  Standard  8048/8748/8035 

•  NMOS  Silicon  Gate  Technology  Requiring  a  Single  +5V  Supply 

•  2.5jus  Cycle  Time.  All  Instruction  1  or  2  Bytes 

•  Interval  Timer/Event  Counter 

•  64  x  8  Byte  RAM  Data  Memory 

•  Single  Level  Interrupt 

•  96  Instructions:  70%  Single  Byte 

•  27  I/O  Lines 

•  Internal  Clock  Generator 

•  8  Level  Stack 

•  Compatible  With  8080A/8085A  Peripherals 

•  Available  in  Both  Ceramic  and  Plastic  40  Pin  Packages 


PIN  CONFIGURATION 


XTAL  1  G 
XTAL  2  C 
RESET  C 
SS  c 

Tnt  c 

RD  C 
PSEN  C 
WR  C 
ALE  C 
DBQC 
DB1  C 
DB2C 
DB3C 
DB4C 
DB5C 
DB6C 
DB?C 

VSSC 


juPD 
8748 


40 
39 
38 
37 
36 
35 
34 
33 
32 
31 
30 
29 
28 
27 
26 
25 
24 
23 
22 
21 


Vcc(  +  5) 
P27 


P26 

P25 

P24 

P17 

P16 
I  P15 
|  P14 
|  P13 
I  P12 
|  P11 
I  P10 

lVDD 
I  PROG 

I  P23 

I  P22 

I  P21 

I  P20 


Rev/2 
4-91 


MPD8748 


The  NEC  |i,PD8748  is  a  single  component,  8-bit,  parallel  microprocessor  using  N-  FUNCTIONAL 
channel  silicon  gate  MOS  technology.  The  8748  efficiently  functions  in  control  as  DESCRIPTION 
well  as  arithmetic  applications.  The  flexibility  of  the  instruction  set  allows  for  the 
direct  set  and  reset  of  individual  data  bits  within  the  accumulator  and  the  I/O  port 
structure.  Standard  logic  function  implementation  is  facilitated  by  the  large  variety 
of  branch  and  table  look-up  instructions. 

The  jjlPD8748  instruction  set  is  comprised  of  1  and  2  byte  instructions  with  over  70% 
single-byte  and  requiring  only  1  or  2  cycles  per  instruction  with  over  50%  single- 
cycle. 

The  |xPD8748  series  of  microprocessors  will  function  as  stand  alone  microcompu- 
ters. Their  functions  can  easily  be  expanded  using  standard  8080A/8085A  peripher- 
als and  memories. 

The  (xPD8748  contains  the  following  functions  usually  found  in  external  peripheral 
devices:  1024  x  8  bits  of  ROM  program  memory;  64  x  8  bits  of  RAM  data  memory; 
27  I/O  lines;  an  8-bit  interval  timer/event  counter;  oscillator  and  clock  circuitry. 

The  //PD8748  differs  from  the  //PD8048  only  in  its  1024  x  8-bit  UV  erasable 
EPROM  program  memory  instead  of  the  1024  x  8-bit  ROM  memory.  It  is  useful  in 
preproduction  or  prototype  applications  where  the  software  design  has  not  yet  been 
finalized  or  in  system  designs  whose  quantities  do  not  require  a  mask  ROM. 


BLOCK  DIAGRAM 


E 


ACCUMULATOR  H 


TX 


INTERRUPT  PROM/EXPANDER 


OSCILLATOR/   AOORESS  PROGRAM  S 
XTAL  LATCH  MEMORY 

STROBE/  ENABLE 


TTT 


4-92 


MPD8748 


PIN  IDENTIFICATION 


PIN 

FUNCTION 

NO. 

SYMBOL 

T0 

Testable  input  using  conditional  transfer  functions  JTO  and 
JNTO  The  internal  State  Clock  (CLK)  is  available  to  Tq 
using  the  ENTO  CLK  instruction  Tq  can  also  be  used 
during  programming  as  a  testable  flag 

2 

XTAL  1 

One  side  of  the  crystal  input  for  external  oscillator  or 
frequency  (non  I  I  L  compatible  V||_j). 

3, 

XTAL  2 

The  other  side  of  the  crystal  input 

4 

RESET 

Active  low  input  for  processor  initialization.  RESET  is 
also  used  for  PROM  programming  verification  and  power- 
down  (non  TTL  compatible  V1LJ). 
 LtL  

5 

SS 

Single  Step  input  (active-low)  SS  together  with  ALE  allows 
the  processor  to  "single-step"  through  each  instruction  in 
program  memory 

6 

INT 

Interrupt  input  (active-low)  INT  will  start  an  interrupt  if 
an  enable  interrupt  instruction  has  been  executed.  A  reset 
will  disable  the  interrupt  INT  can  be  tested  by  issuing  a 
conditional  jump  instruction. 

7 

EA 

External  Access  input  (active-high)  A  logic  "1"  at  this 
input  commands  the  processor  to  perform  all  program 
memory  fetches  from  external  memory. 

8 

RD 

READ  strobe  output  (active-low).  RDj/viJI  pulse  low  when 
the  processor  performs  a  BUS  READ.  RD  will  also  enable 
data  onto  the  processor  BUS  from  a  peripheral  device  and 
function  as  a  READ  STROBE  for  external  DATA  MEMORY. 

9 

PSEN 

Procjrsm  StorG  Endble  output  (sctive'low).  PSEN  becomes 
active  only  during  an  external  memory  fetch 

10 

WR 

WRITE  strobe  output  (active-low).  WR  will  pulse  low  when 
the  processor  performs  a  BUS  WRITE.  WR  can  also  function 
as  a  WRITE  STROBE  for  external  DATA  MEMORY. 

1 1 

ALb 

Address  Latch  Enable  output  (active  high).  Occurring  once 
each  cycle,  the  falling  edge  of  ALE  latches  the  address  for 
external  memory  or  peripherals  ALE  can  also  be  used  as 
a  clock  output. 

12-  19 

D0-  D7  BUS 

8-bit,  bidirectional  port.  Synchronous  reads  and  writes  can 
be  performed  on  this  port  using  RD  and  WR  strobes.  The 
contents  of  the  Do  -  D7  BUS  can  be  latched  in  a  static 
mode. 

During  an  external  memory  fetch,  the  Do  -  D7  BUS  holds 
the  least  significant  bits  of  the  program  counter.  PSEN 
controls  the  incoming  addressed  instruction.  Also,  for  an 
external  RAM  data  store  instruction  the  Do  —  D7  BUS, 
controlled  by  ALE,  RD  and  WR,  contains  address  and  data 
information. 

20 

vSs 

Processor's  GROUND  potential 

21  -  24, 
35-38 

p20  ~~  p27 
PORT  2 

Port  2  is  the  second  of  two  8-bit  quasi-bidirectional  ports. 
For  external  data  memory  fetches,  the  four  most  significant 
bits  of  the  program  counter  are  contained  in  P20  ~  p23-  Bits 
p20  _  p23  are  also  used  as  a  4"blt  I/O  bus  for  the  /uPD8243, 
INPUT/OUTPUT  EXPANDER. 

25 

PROG 

Program  Pulse.  A  +25V  pulse  applied  to  this  input  is  used 
for  programming  the  jupD8748.  PROG  is  also  used  as  an  out- 
put strobe  for  the  juPD8243. 

26 

VDD 

ProQrsmminQ  Power  Supply          must  be  set  to  "^"25V  for 
programming  the  j*PD8748,  and  to  +5V  for  the  ROM  and 
PROM  versions  for  normal  operation.  Vqq  functions  as  the 
Low  Power  Standby  input  for  the  /LtPD8048. 

27  -  34 

P10-P17 
PORT  1 

Port  1  is  one  of  two  8-bit  quasi-bidirectional  ports. 

39 

T1 

Testable  input  using  conditional  transfer  functions  JT1  and 
JNT1.  T1  can  be  made  the  counter/timer  input  using  the 
STRT  CNT  instruction. 

40 

vcc 

Primary  Power  Supply.  Vcc  must  be  +5V  for  programming 
and  operation  of  the  MPD8748,  and  for  operation  of  the 
MPD8035L  and  MPD8048. 

4- 


93 


pPD8748 


Operating  Temperature   0°C  to  +70°C 

Storage  Temperature  (Ceramic  Package)   -65°C  to  +150  C 

Storage  Temperature  ( Plastic  Package)   - 65°C  to  +1 50°C 

Voltage  on  Any  Pin  -  0.5  to  +7  Volts  © 

Power  Dissipation   1.5  W 

Note:  ©  With  respect  to  ground. 

Ta  =  25°C 

*COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 

Ta  -  -0°C  to  +70°C,  Vcc  =  VdD  =  +5V  ±  10%,  Vss  =  0V 


ABSOLUTE  MAXIMUM 
RATINGS* 


DC  CHARACTERISTICS 


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST  CONDITIONS 

MIN 

TYP 

MAX 

Input  Low  Voltage 

(All  Except  XTAL  1,  XTAL  2) 

VlL 

-0.5 

0.8 

V 

Input  High  Voltage 

(All  Except  XTAL  1 ,  XTAL  2,  RESET) 

V|H 

2.0 

vcc 

V 

Input  High  Voltage 
(RESET,  XTAL  1,  XTAL  2) 

V|H1 

38 

vcc 

V 

Output  Low  Voltage  (BUS) 

VOL 

0  45 

V 

lOL  =  2  0  mA 

Output  Low  Voltage  (RD,WR, 
PSEN,  ALE) 

VOL1 

0  45 

V 

'OL  =  18  mA 

Output  Low  Voltage  (PROG) 

VOL2 

0.45 

V 

•OL  =  10  mA 

Output  Low  Voltage 
(All  Other  Outputs) 

vOL3 

0  45 

V 

lOL  "  1  6  mA 

Output  High  Voltage  (BUS) 

VOH 

2.4 

V 

'OH  -  -400  mA 

Output  High  Voltage  (RD,  WR, 
PSEN,  ALE) 

VOH1 

2.4 

V 

'OH  = -100juA 

Output  High  Voltage 
(All  Other  Outputs} 

VOH2 

2.4 

V 

'OH  =  -40  AiA 

Input  Leakage  Current 
<T1(INT) 

'LI 

±10 

ma 

VSS  <  V|N  <  VCC 

Input  Leakage  Current 
<P10-P17.P20-P27.EA,SS) 

'LI1 

-500 

HA 

VCC  >  V|N>  VSS  +  0  45V 

Output  Leakage  Current 

(BUS,  To  -  High  Impedance  State) 

lOL 

±10 

ma 

VCC>  V|fy|>  VSS  +  0  45V 

Power  Down  Supply  Current 

•dd 

7 

15 

mA 

Ta  =  25°C 

Total  Supply  Current 

'DD  +  'CC 

60 

135 

mA 

Ta  -  25°C 

Ta  =  25°C  ±  5°C,  Vcc  "  +5V  ±  10%,  VDD  =  +25V  ±  1 V 

PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST  CONDITIONS 

MIN 

TYP 

MAX 

Vqd  Program  Voltage  High-Levei 

vdoh 

24.0 

26  0 

V 

Vqd  Voltage  Low-Level 

vddl 

4.75 

5.25 

V 

PROG  Voltage  High-Level 

VPH 

21  5 

24.5 

V 

PROG  Voltage  Low-Level 

VPL 

02 

V 

EA  Program  or  Verify  Voltage  High-Level 

veah 

21.5 

24  5 

V 

EA  Voltage  Low-Level 

veal 

5.25 

V 

Vdd  H,9h  Voltage  Supply  Current 

'DD 

30.0 

mA 

PROG  High  Voltage  Supply  Current 

•prog 

16.0 

mA 

EA  High  Voltage  Supply  Current 

iea 

1  0 

mA 

DC  CHARACTERISTICS 
PROGRAMMING  THE 
MPD8748 


4-94 


//PD8748 


READ,  WRITE  AND  INSTRUCTION  FETCH  -  EXTERNAL 
DATA  AND  PROGRAM  MEMORY 
AC  CHARACTERISTICS    t3  =  o°c  to  +70"c,  vcc  -  Vpp -  +5V  ±  10%,  vSs  =  ov  


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST  © 
CONDITIONS 

MIN 

TYP 

MAX 

ALE  Pulse  Width 

*LL 

400 

ns 

Address  Setup  before  ALE 

<AL 

120 

ns 

Address  Hold  from  ALE 

tLA 

80 

ns 

Control  Pulse  Width  (PSEN,  RD,WR) 

*CC 

700 

ns 

Data  Setup  before  WR 

lDW 

500 

ns 

Data  Hold  after  WR 

*WD 

120 

ns 

CL=  20  pF 

Cycle  Time 

tCY 

2  5 

15  0 

MS 

6  MHz  XTAL 

Data  Hold 

*DR 

0 

200 

ns 

PSEN,  RD  to  Data  In 

tRD 

500 

ns 

Address  Setup  before  WR 

*AW 

230 

ns 

Address  Setup  before  Data  In 

*AD 

950 

ns 

Address  F loat  to  RD,  PSEN 

tAFC 

0 

ns 

Control  Pulse  to  ALE 

tCA 

10 

ns 

Notes   ©  For  Control  Outputs  C|_  =  80  pF 
For  Bus  Outputs  CL=150pF 
tCY  ~  2  5  ms 

PORT  2  TIMING 

Ta  =  0°C  to  +70°  C;  Vqc  =  +5V  ±  10%  


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Port  Controi  Setup  oefore  Falling 
Edge  of  PROG 

*CP 

110 

ns 

Port  Control  Hold  after  Falling 
Edge  of  PROG 

tpC 

100 

ns 

PROG  to  Time  P2  Input  must  be 
Valid 

tPR 

810 

ns 

Output  Data  Setup  Time 

*DP 

250 

ns 

Output  Data  Hold  Time 

tpD 

65 

*ns 

Input  Data  Hold  Time 

tPF 

0 

150 

ns 

PROG  Pulse  Width 

tpp 

1200 

ns 

Port  2  I/O  Data  Setup 

tPL 

350 

ns 

Port  2  I/O  Data  Hold 

tLP 

150 

ns 

PROGRAMMING  SPECIFICATIONS  —  /1PD8748 

Ta  =  25° C  ±  5QC;  VCC  =  +5V  ±  10%;  Vpp  =  +25V  ±  1 V  


PARAMETER 

SYMBOL 

LIMITS 

UNIT 

TEST 
CONDITIONS 

MIN 

TYP 

MAX 

Address  Setup  Time  before  RESET  t 

tAW 

4tCY 

Address  Hold  Time  after  RESET  t 

*WA 

4tCY 

Data  In  Setup  Time  before  PROG  t 

tDW 

4tCY 

Data  In  Hold  Time  after  PROG  4- 

tWD 

-4tCY 

RESET  Hold  Time  to  VERIFY 

tPH 

4tcY 

VDD 

tVDDW 

4tCY 

VDd  Hold  Time  after  PROG  I 

tVDDH 

0 

Program  Pulse  Width 

tpw 

50 

60 

ms 

Test  0  Setup  Time  before  Program 
Mode 

tTW 

4tCY 

Test  0  Hold  Time  after  Program 
Mode 

tWT 

4tCY 

Test  0  to  Data  Out  Delay 

tDO 

4tCY 

RESET  Pulse  Width  to  Latch 
Address 

tww 

4tcY 

Vqq  and  PROG  Rise  and  Fall  Times 

tr,tf 

0.5 

2.0 

MS 

Processor  Operation  Cycle  Time 

tCY 

5.0 

lis 

RESET  Setup  Time  before  EA  t 

tRE 

4tCY 

4-95 


pPD8748 


TIMING  WAVEFORMS 


1_ 


floating)!^     XfloatingX     vX    floati"g  X 


-1 


^INSTRUCTION 


INSTRUCTION  FETCH  FROM  EXTERNAL  MEMORY 


1  1 

L 

 *CC  *~ 

tCA 

RD 

—■J  tAFC 

lDRh* 

*RD 


-tAD~ 


r 


READ  FROM  EXTERNAL  DATA  MEMORY 


1  1 

L 

-•—tec — 
— »J  tow 

M/VD 

FLOATING^^ADDRESS^^  FLOATING            DATA  FLOATING 

 tAW  •» 

WRITE  TO  EXTERNAL  MEMORY 


4-96 


MPD8748 


TIMING  WAVEFORMS 
(CONT.) 


><: 


'"Ol       >  ^  INPUT  OAT  A  ^ 


PORT  2  TIMING 


\^  ADDRESS  X/        DATA  TO  BE       \  \/      DATA  NEXT  AOORESSX/ 

 /"""X    MV>ll°A  WOOHAMM6D  VAUD^—  ^  /\       VAL.O       ^  \  7V 


p20-p1  ADDRESS 


X 


ADDRESS  18-91  VALID 


x 


•WD  I 


PROGRAM/VERIFY  TIMING 
(MPD8748  ONLY) 


>-< 


x 


>--< 


x 


>— 


x 


x 


VERIFY  MODE  TIMING 
(MPD8048/8748  ONLY) 


Notes:   

(D  Conditions^  CS  TTL  Logic  "1";  Ao  TTL  Logic  "0"  must  be  met.  (Use  10K  resistor  to 

Vcc  fof  CS,  and  10K  resistor  to  Vss  for  Ao) 
(§)  tCY  5fxs  can  be  achieved  using  a  3  MHz  frequency  source  (LC,  XTAL  or  external)  at  the 

XTAL  1  and  XTAL  2  inputs. 


4-97 


MPD8748 


INSTRUCTION  SET 


INSTRUCTION  CODE 

DO  | 

BYTES  j 

FLAGS 

MNEMONIC 

FUNCTION 

DESCRIPTION  | 

- 

D6 

D5 

D4 

D3 

D2 

D1 

CYCLES 

C   AC    FO  F1 

ACCUMULATOR 

ADD  A,  #  data 

(A)  -  (A)  +data 

Add  Immediate  the  specified  Data  to  the 

0 

0 

0 

0 

0 

0 

1 

2 

2 

Accumulator 

d6 

d5 

d4 

d3 

d2 

dl 

do 

ADD  A,  Rr 

(A)  —  (A)  +  (Rr) 
for  r  =  0  -  7 

Add  contents  of  designated  register  to 

0 

1 

1 

0 

1 

r 

r 

r 

1 

1 

• 

ADD  A,  @  Rr 

(A)-<A)  +  ((Rr)) 

Add  Indirect  the  contents  the  data 

0 

1 

1 

0 

0 

0 

0 

r 

1 

1 

• 

ADDC  A,  *data 

(A)  -  (A)  +  (C)  +  data 

Add  Immediate  with  carry  the  specified 

0 

0 

0 

1 

0 

0 

1 

• 

d7 

d6 

d5 

d4 

d0 

ADDC  A.  Rr 

(A)  ♦  (A)  +  (C)  +  (Rr) 

Add  with  carry  the  contents  of  the 
designated  register  to  the  Accumulator 

0 

1 

1 

1 

r 

r 

1 

1 

• 

a  nrir*  a  /a  Qr 
auul  M,  (i*  nr 

IA/  «-  (A)  +  (v.)  +  unrn 
for  r  =  0  -  1 

Add  Indirect  with  carry  the  contents  of 
data  memory  location  to  the 
Accumulator 

ANL  A,  =data 

(A)  -  (A)  AND  data 

Logical  and  specified  Immediate  Data 

0 

0 

1 

0 

0 

1 

with  Accumulator 

d6 

d5 

d4 

d3 

d2 

dl 

do 

ANL  A.  Rr 

(A)  -  (A)  AND  (Rr) 
for  r  =  0  -  7 

Logical  and  contents  of  designated 
register  with  Accumulator 

0 

0 

1 

1 

1 

1 

ANL  A,  @  Rr 

(A)  -  (A)  AND  ((Rr)) 
for  r  =  0  1 

Logical  and  Indirect  the  contents  of  data 
memory  with  Accumulator 

0 

1 

0 

1 

0 

0 

0 

., 

CPL  A 

(A)  -  NOT  (A) 

Complement  the  contents  of  the 
Accumulator 

0 

0 

1 

1 

0 

1 

1 

1 

1 

1 

CLR  A 

(A)  -  0 

CLEAR  the  contents  of  the  Accumulator 

0 

0 

1 

0 

0 

1 

1 

DA  A 

DECIMAL  ADJUST  the  contents  of  the 
Accumulator 

0 

; 

; 

; 

DEC  A 

(A) •  (A)  1 

DECREMENT  by  1  the  accumulator's 
contents 

0 

0 

0 

0 

0 

1 

1 

1 

1 

1 

INC  A 

(A)  -  (A)  +  1 

Increment  by  1  the  accumulator's 
contents 

0 

0 

0 

1 

0 

1 

1 

1 

1 

1 

ORL  A,  =  data 

(A)  -  (A)  OR  data 

Logical  OR  specified  immediate  data 

0 

1 

0 

0 

0 

0 

with  Accumulator 

d7 

d6 

d5 

d4 

d3 

d2 

dl 

do 

ORL  A,  Rr 

(A)  -  (A)  OR  (Rr) 
for  r  =  0  -  7 

Logical  OR  contents  of  designated 
register  with  Accumulator 

0 

1 

0 

0 

ORL  A.  @  Rr 

(A)  -  (A)  OR  ((Rr)) 
for  r  =  0  -  1 

Logical  OR  Indirect  the  contents  of  data 
memory  location  with  Accumulator 

0 

1 

0 

0 

0 

0 

RL  A 

(AN  +  1 )  —  (AN) 
(A0)  -  <A7) 
f  or  N  =  0  -  6 

Rotate  Accumulator  left  by  1  bit  without 
carry 

1 

1 

1 

0 

0 

1 

1 

1 

1 

1 

RLC  A 

(AN  +  1)  -  (AN),  N  =  0  -  6 
(A0>  -  (C) 
(C)  —  (A7) 

Rotate  Accumulator  left  by  1  -bit  through 
carry 

1 

1 

1 

1 

0 

1 

1 

1 

1 

1 

• 

RR  A 

(AN)~(AN+1);N  =  0-6 
(A7)  -  (Aq) 

Rotate  Accumulator  right  by  1  -bit 
without  carry 

0 

1 

1 

1 

0 

, 

1 

RRC  A 

(AN)  -  (AN  +  1).  N  =  0-6 
(A7)  -  (C) 
(C)  -  (A0) 

Rotate  Accumulator  right  by  1  -bit 
through  carry 

0 

1 

0 

0 

1 

1 

• 

SWAP  A 

(A4.7)  £  (AQ-  3) 

Swap  the  2  4-bit  nibbles  in  the 

0 

1 

0 

0 

0 

1 

Accumulator 

XRL  A,  *  data 

(A)  -  (A)  XOR  data 

Logical  XOR  specified  immediate  data 

1 

1 

0 

0 

0 

with  Accumulator 

d5 

d4 

d3 

d2 

dO 

XRL  A,  Rr 

(A)  -  (A)  XOR  (Rr) 
for  r  =  0  -  7 

Logical  XOR  contents  of  designated 
register  with  Accumulator 

1 

1 

0 

1 

1 

XRL  A,  @  Rr 

(A)  -  (A)  XOR  ((Rr)) 
for  r  =  0  -  1 

Logical  XOR  Indirect  the  contents  of  data 
memory  location  with  Accumulator 

1 

1 

0 

0 

0 

0 

BR> 

\nch 

DJNZ  Rr,  addr 

(Rr)-(Rr)-1,r  =  0-  7 

Decrement  the  specified  register  and 

1 

1 

0 

2 

2 

If  (Rr)  *  0 

test  contents 

37 

36 

35 

a4 

33 

32 

a0 

(PC  0  -  7)  -  addr 

JBb  addr 

(PC  0  -  7) «-  addr  if  Bb  =  1 

Jump  to  specified  address  if 

b2 

bl 

b0 

0 

0 

0 

2 

2 

(PC)  -  (PC)  +  2  if  Bb  =  0 

Accumulator  bit  is  set 

37 

36 

35 

a4 

33 

32 

a1 

30 

JC  addr 

(PCO-  7)~  addr  if  C  =  1 

Jump  to  specified  address  if  carry  flag 

1 

1 

1 

0 

1 

0 

(PC)  -  (PC)  +  2  if  C  =  0 

is  set. 

37 

36 

35 

34 

33 

32 

a1 

a0 

JFOaddr 

(PC  0  -  7)  «-  addr  if  FO  =  1 

Jump  to  specified  address  if  Flag  FO  is 

0 

1 

1 

0 

1 

0 

2 

2 

(PC)  -MPC)  +  2  if  FO  =  0 

37 

36 

35 

34 

33 

32 

a1 

a0 

JF1  addr 

(PCO-  7)  «-addr  if  F 1  =  1 

Jump  to  specified  address  if  Flag  F1  is 

0 

1 

1 

1 

0 

1 

0 

2 

2 

(PC)  —  (PC)  +  2  if  F1  =0 

set 

37 

36 

35 

34 

33 

32 

a1 

a0 

JMP  addr 

(PC  8-  10)  -  addr  8-  10 

Direct  Jump  to  specified  address  within 

310 

39 

a8 

0 

0 

0 

2 

2 

(PC  0  -  7)  -  addr  0-7 

the  2K  address  block 

37 

36 

35 

34 

33 

32 

a1 

30 

(PC  11)  -  DBF 

JMPP  @  A 

(PCO  -  7)- ((A)) 

Jump  indirect  to  specified  address  with 
with  address  page 

1 

0 

1 

1 

0 

0 

2* 

JNC  addr 

(PC  0  -  7)  -  addr  if  C  «  0 

Jump  to  specified  address  if  carry  flag  is 

1 

0 

0 

0 

2 

2 

(PC)  -  (PC)  +  2  if  C  =  1 

low 

37 

36 

35 

34 

33 

32 

a0 

JNI  addr 

(PC  0  -  7)  -  addr  if  1  =  0 

Jump  to  specified  address  if  interrupt 

1 

b 

0 

0 

0 

1 

0 

2 

2 

(PC)  -  (PC)  4  2  if  1  -  1 

is  low 

37 

36 

a5 

34 

33 

32 

a0 

4-98 


INSTRUCTION  SET  (CONT.) 


pPD8748 


INSTRUCTION  CODE 

FLAGS 

MNEMONIC 

FUNCTION 

DESCRIPTION 

07 

D6 

o5 

D4 

D3 

D2 

Di 

DO 

CYCLES 

BYTES 

C   AC     FO  Fl 

BRANCH  (CONT  ) 

JNTO  addr 

(PC  0  -  7)  —  addr  if  TO  =  0 

Jurnp  to  specified  address  if  Test  0  is  low 

0 

0 

1 

0 

0 

1 

1 

0 

2 

2 

(PC)  -  (PC)  +  2  if  TO  =  1 

37 

a6 

a5 

34 

33 

^2 

31 

30 

JNT1  addr 

(PC  0  -  7)  -  addr  if  T1  =  0 

Jump  to  specified  address  if  Test  1  is  low 

0 

1 

0 

0 

0 

0 

2 

2 

(PC) -  (PC)  +  2  if  T1  =  1 

37 

36 

35 

34 

33 

32 

30 

JNZ  addr 

(PC  0  -  7)  -  addr  if  A  =  0 

Jump  to  specified  address  if  accumulator 

1 

0 

0 

0 

0 

2 

2 

(PC)  -  (PC) +  2  if  A  =  0 

is  non  zero 

37 

3G 

35 

34 

33 

32 

30 

JTF  addr 

(PC  0-  7)  -  addr  if  TF  =  1 

Jump  to  specified  address  if  Timer  Flag 

0 

0 

0 

1 

0 

0 

2 

2 

(PC)-(PC)  +  2tfTF  =  0 

is  set  to  1 

a7 

36 

35 

34 

33 

32 

°1 

30 

JTO  addr 

(PC  0  -  7)  -  addr  if  TO  =  1 

Jump  to  specified  address  if  Test  0  is  a 

0 

0 

1 

0 

1 

0 

2 

2 

(PC) -(PC)  +  2  if  T0  =  0 

37 

36 

35 

34 

33 

32 

30 

JT1  addr 

(PC  0-7) -addr  if  T1  =  1 

Jump  to  specified  address  if  Test  1  is  a  1 

0 

0 

0 

0 

2 

2 

•(PC) -(PC) +2  if  T1  =0 

37 

36 

35 

34 

33 

32 

30 

JZ  addr 

(PC  0  -  7)  -  addr  if  A  =  0 

Jump  to  specified  address  if  Accumulator 

1 

0 

0 

0 

0 

2 

2 

(PC) -(PC) +2  if  A  =  0 

is  0 

37 

36 

35 

34 

33 

32 

a1 

30 

CONTROL 

EN  I 

Enable  the  External  Interrupt  input 

0 

0 

0 

0 

0 

0 

DIS  I 

Disable  the  External  Interrupt  input 

0 

0 

0 

0 

0 

1 

ENTO  CLK 

Enable  the  Clock  Output  pin  TO 

0 

1 

1 

0 

0 

1 

1 

SELMBO 

(DBF)  -0 

Select  Bank  0  (locations  0    2047)  of 
Program  Memory 

0 

0 

1 

0 

SEL  MB1 

(DBF1-1 

Select  Bank  1  (locations  2048    4095)  of 
Program  Memorv 

0 

0 

SEL  RBO 

(BS)  —  0 

Select  Bank  0  (locations  0  —  7)  of  Data 
Memory 

1 

1 

0 

0 

0 

0 

1 

SEL  R  1 

Select  Bank  1  (locations  24    31)  of 
Data  Memory 

1 

0 

0 

0 

1 

MOVES 

MOV  A.  data 

(A)  -  data 

Move  Immediate  the  specified  data  into 

0 

0 

0 

0 

0 

1 

2 

2 

the  Accumulator 

d7 

d6 

d5 

d4 

d2 

di 

d0 

MOV  A,  Ri 

(A)-(Rr),r  =  0-7 

Move  the  contents  of  the  designated 
registeis  into  the  Accumulator 

MOV  A,  &  Rr 

(A)-((Rr)),r  =  0-1 

Move  Indirect  the  contents  of  data 
memory  location  into  the  Accumulate 

0 

0 

0 

1 

MOV  A,  PSW 

(A)  -  (PSW) 

Move  contents  of  the  Program  Status 
Word  into  the  Accumulator 

1 

0 

0 

0 

MOV  Rr,  data 

(Rr) -data,  r  =  0-7 

Move  Immediate  the  specified  data  into 

1 

0 

1 

1 

1 

2 

the  designated  iegister 

d7 

d6 

d4 

d3 

d2 

di 

do 

MOV  Ri,  A 

(Rr)-(A),r  =  0-7 

Move  Accumulator  Contents  into  the 
designated  register 

1 

0 

1 

0 

MOV  @  Rr,  A 

((Rr))-(A),r  =  0-  1 

Move  Indirect  Accumulatoi  Contents 
into  data  memory  location 

0 

1 

0 

0 

0 

0 

MOV  @  Rr,  data 

((Rr))  -  data,  r  =  0  -  1 

Move  Immediate  the  specified  data  into 

0 

0 

0 

0 

2 

data  memory 

d7 

d5 

d4 

d3 

d2 

di 

do 

MOV  PSW,  A 

(PSW)  -  (A) 

Move  contents  of  Accumulator  into  the 
program  status  word 

1 

1 

0 

1 

0 

1 

1 

MOVP  A,  @  A 

(PC  0-7) -(A) 
(A) -((PC)) 

Move  data  in  the  current  page  into  the 
Accumulator 

1 

0 

1 

0 

0 

0 

1 

2 

MOVP3  A,@  A 

(PC  0-7) -(A) 
(PC  8-  10)  -011 
(A)  -  ((PC)) 

Move  Piogram  data  in  Page  3  into  the 
Accumulator 

1 

0 

0 

0 

1 

1 

2 

MOVX  A,  @  R 

(A)-((Rr)),r  =  0-  1 

Move  Indirect  the  contents  of  external 

0 

0 

0 

0 

0 

0 

2 

data  memory  into  the  Accumulator 

MOVX  @  R,  A 

((Rr))  -(A),r  =  0-  1 

Move  Indirect  the  contents  of  the 

0 

0 

1 

0 

0 

0 

2 

Accumulator  into  external  data  memory 

XCH  A,  Rr 

(A)?(Rr),r  =  0-7 

Exchangp  the  Accumulator  and 
designated  register's  contents 

0 

0 

1 

0 

1 

1 

XCH  A,  @  Rr 

(A)^((Rr»,r  =  0-  1 

Exchange  Indirect  contents  of  Accumu- 
lator and  location  in  data  memory 

0 

0 

0 

0 

0 

0 

XCHD  A,  @  Rr 

(A0-3)^((Rr))0-3)), 
r  =  0-  1 

Exchange  Indirect  4  bit  contents  of 
Accumulator  and  data  memory 

0 

0 

1 

0 

0 

0 

FL 

AGS 

CPL  C 

(C)     NOT  (C) 

Complement  Content  of  carry  bit 

0 

1 

0 

0 

1 

CPL  FO 

(FO)  •  NOT  (FO) 

Complement  Content  of  Flag  FO 

0 

0 

0 

0 

1 

1 

CPL  F1 

(F1)  NOT(FI) 

Complement  Content  of  Flag  F1 

0 

1 

0 

0 

1 

CLR  C 

(C)  0 

Clear  content  of  carry  bit  to  0 

0 

0 

1 

0 

1 

1 

1 

CLR  FO 

(FO)-  0 

Clear  content  of  Flag  0  to  0 

0 

0 

0 

0 

0 

1 

1 

• 

CLR  F1 

(F1)  0 

Clear  content  of  Flag  1  to  0 

0 

0 

0 

0 

1 

4-99 


MPD8748 


INSTRUCTION  SET  (CONT.) 


INSTRUCTION  CODE 

FLAGS 

MNEMONIC 

FUNCTION 

DESCRIPTION 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

DO 

CYCLES 

BYTES 

C    AC    F0  F1 

INPUT/OUTPUT 

ANL  BUS.  •  data 

(BUS)  -  (BUS)  AND  data 

Logical  and  Immediate  specified  data 

1 

0 

0 

0 

0 

0 

2 

2 

d7 

d6 

d5 

ANL  Pp.  =  data 

(Pp)  <-  (Pp)  AND  data 

Logical  and  Immediate  specified  data 

0 

0 

? 

0 

•  p' 

p 

2 

2 

p  =  1  -  2 

with  designatPd  port   1  or  2) 

d7 

d6 

d5 

d4 

d3 

d2 

c  1 

d0 

ANLD  Pp,  A 

(Pp)  -  (Pp)  AND  (A  0  -  3) 
p  =  4  -  7 

Logical  and  contents  of  Accumulator  with 
designated  port  (4-7) 

1 

0 

0 

1 

1 

1 

p 

P 

2 

1 

IN  A.  Pp 

(A)-(Pp).p=  1  -2 

Input  data  from  designated  port  (1-2) 
into  Accumulator 

0 

0 

0 

0 

1 

0 

p 

P 

2 

1 

INS  A,  BUS 

(A)  *-  (BUS) 

Input  strobed  BUS  data  into  Accumulator 

0 

0 

0 

0 

1 

0 

0 

0 

2 

1 

MOVD  A  Pp 

(A0-3)«-{Pp),p  =  4-7 
(A  4-  7)  *-0 

Move  contents  of  designated  port  (4-7) 
into  Accumulator 

0 

0 

0 

0 

1 

1 

p 

P 

2 

' 

MOVD  Pp,  A 

(Pp)<-AO  =  3,p  =  4-7 

Move  contents  of  Accumulator  to 
designated  port  (4-7) 

0 

0 

1 

1 

1 

1 

p 

P 

2 

1 

ORL  BUS,  data 

(BUS)  <-  (BUS)  OR  data 

Logical  or  Immediate  specified  data  with 

0 

0 

0 

1 

0 

0 

0 

2 

2 

contents  of  BUS 

d7 

d5 

d4 

d3 

d2 

dl 

do 

ORLD  Pp.  A 

(Pp)<-(Pp)OR  (A  0-3) 
p  =  4-  7 

Logical  or  contents  of  Accumulator  with 
designated  port  (4-7) 

1 

0 

0 

0 

P 

2 

ORL  Pp'.  -  data 

(Pp)  -  (Pp)  OR  data 

Logical  or  Immediate  specified  data  with 

0 

0 

0 

0 

P 

2 

2 

p=  1  -  2 

designated  port  (1-2) 

d7 

^6 

d4 

d3 

d2 

di 

do 

OUTL  BUS,  A 

(BUS)  <-  (A) 

Output  contents  of  Accumulator  onto 
BUS 

0 

0 

0 

0 

0 

0 

0 

2 

OUTL  Pp,  A 

(Pp)«-(A).p=  1  -2 

Output  contents  of  Accumulator  to 
designated  port  (1-2) 

0 

0 

1 

1 

0 

P 

P 

2 

REGISTERS 

DEC  Rr  (Rr) 

(Rr)«-(Rr)  +  1.r-0-7 

Decrement  by  1  contents  of  designated 

0 

0 

INC  Rr 

(Rr)<-(Rr)  +  1,r  =  0-7 

Increment  by  1  contents  of  designated 
register 

0 

0 

0 

1 

INC@Ri 

((Rr))  <-  ((Rr))  +  1, 
r  =  0-  1 

Inciement  Indirect  by  1  the  contents  of 
data  memory  location 

0 

0 

0 

0 

0 

0 

SUBROUTINE 

CALL  addr 

«SP))  <-  (PC),  (PSW4-  7) 

(SP)  -  (SP)  +  1 

(PC  8-  10) -addr  8-  10 

<PCO-7)*-addrO-7 

(PC  11)  -  DBF 

Call  designated  Subroutine 

aiO 

37 

39 

a6 

38 

a5 

1 

34 

0 

33 

32 

0 

0 

30 

2 

2 

RET 

(SP)  -  (SP)  =  1 

(PC)  -  ((SP)) 

Return  from  Subroutine  without 
restoring  Program  Status  Word 

0 

0 

0 

0 

0 

2 

RETR 

(SP)  -  (SP)  =  1 
(PC)  -  ((SP)) 
(PSW4-7)*-((SP)) 

Return  from  Subroutine  restoring 
Program  Status  Word 

0 

0 

0 

0 

1 

2 

1 

TIMER/COUNTER 

EN  TCNTI 

Enable  Internal  interrupt  Flag  for 
Timer/Counter  output 

0 

0 

1 

0 

0 

1 

0 

DIS  TCNTI 

Disable  Internal  interrupt  Flag  for 
Timer/Counter  output 

0 

0 

0 

0 

1 

1 

MOV  A.  T 

(A)  (T) 

Move  contents  of  Timer/Counter  into 
Accumulator 

0 

0 

0 

0 

0 

0 

MOV  T,  A 

(T)  (A) 

Move  contents  of  Accumulator  into 
Timer/Counter 

0 

1 

0 

0 

0 

0 

STOP  TCNT 

Stop  Count  for  Event  Counter 

0 

1 

1 

0 

0 

1 

0 

STRT  CNT 

Start  Count  for  Event  Counter 

0 

1 

0 

0 

0 

1 

0 

STRT  T 

Start  Count  for  Timer 

0 

0 

1 

0 

0 

1 

MISCELLANEOUS 

NOP 

No  Operation  performed 

0 

0 

0 

0 

0 

0 

0 

0 

1 

Notes   ©  Instruction  Code  Designations  r  and  p  form  the  binary  representation  of  the  Registers  and  Ports 

(2)  The  dot  under  the  appropriate  flag  bit  indicates  that  its  content  is  subject  to  change  by  the  mstn 
(5)  References  to  the  address  and  data  are  specified  in  bytes  2  and/or  1  of  the  instruction 

(3)  Numerical  Subscripts  appearing  in  the  FUNCTION  column  reference  the  specific  bits  affected 

Symbol  Definitions* 


SYMBOL 

DESCRIPTION 

SYMBOL 

DESCRIPTION 

A 

The  Accumulator 

Pp 

Port  Designator  (p  =  1,  2  or  4  -  7) 

AC 

The  Auxiliary  Carry  Flag 

PSW 

Program  Status  Word 

addr 

Program  Memory  Address  (12  bits) 

Rr 

Register  Designator  (r  =  0,  1  or  0  -  7) 

Bb 

Bit  Designator  (b  =  0  -  7) 

SP 

Stack  Pointer 

BS 

The  Bank  Switch 

T 

Timer 

BUS 

The  BUS  Port 

TF 

Timer  Flag 

C 

Carry  Flag 

To,  "h 

Testable  Flags  0,  1 

CLK 

Clock  Signal 

X 

External  RAM 

CNT 

Event  Counter 

Prefix  for  Immediate  Data 

D 

Nibble  Designator  (4  bits) 

@ 

Prefix  for  Indirect  Address 

data 

Number  or  Expression  (8  bits) 

$ 

Program  Counter's  Current  Value 

DBF 

Memory  Bank  Flip-Fiop 

(x) 

Contents  of  External  RAM  Location 

F0.F1 

Flags  0,  1 

<(x)) 

Contents  of  Memory  Location  Addressed 

1 

Interrupt 

by  the  Contents  of  External  RAM  Location. 

P 

"In-Page"  Operation  Designator 

Replaced  By 

4-100 


fiPD8748 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Cerdip,  |xPD8748D,  has  quartz  window 


4-101 


8748DS-REV2-7-83-CAT 


Notes 


4-102 


SEC 


IPD80C48/HPD80C35 
CMOS  8-BIT  SINGLE-CHIP 
MICROCOMPUTER 


Description 

The  NEC  ^PD80C48  is  a  true  stand-alone  8-bit  micro- 
computer fabricated  using  CMOS  technology.  All  of  the 
functional  blocks  necessary  for  an  integrated  microcom- 
puter are  incorporated,  including  a  1K-byte  ROM,  a  64-byte 
RAM,  27  I/O  lines,  an  8-bit  timer/event  counter,  and  a  clock 
generator.  This  integrated  capability  permits  use  in  stand- 
alone applications.  For  designs  requiring  extra  capability, 
the  |jlPD80C48  can  be  expanded  using  peripherals  and 
memory  compatible  with  industry-standard  8080A/8085A 
processors.  A  version  of  the  jxPD80C48  without  ROM  is 
offered  by  the  |xPD80C35. 

Providing  compatibility  with  industry-standard  8048,  8748, 
and  8035  processors,  the  (xPD80C48  features  significant 
savings  in  power  consumption.  In  addition  to  the  power 
savings  gained  through  CMOS  technology,  the  |xPD80C48 
is  distinct  in  offering  two  standby  modes  (Halt  mode  and 
Stop  mode)  to  further  minimize  power  drain. 
Features 

□  8-bit  CPU  with  ROM,  RAM,  and  I/O  on  a  single  chip 

□  Hardware/software-compatible  with  industry-standard 
8048,  8748,  and  8035  processors 

□  1Kx8ROM 

□  64  x  8  RAM 

□  27  I/O  lines 

□  2.5(jls  cycle  time  (6MHz  crystal) 

□  All  instructions  executable  in  1  or  2  cycles 

□  97  instructions:  70  percent  are  single-byte  instructions 

□  Internal  timer/event  counter 

□  2  interrupts  (an  external  interrupt  and  a  timer  interrupt) 

□  Easily  expandable  memory  and  I/O 

□  Bus  compatible  with  8080A/8085A  peripherals 

□  Power-efficient  CMOS  technology  requiring  a  single 
+  2.5V  to  +  5.5V  power  supply 

□  Available  in  40-pin  DIP,  44-pin  flat  pack,  and  52-pin 
flat  pack 

□  Halt  mode 

- 1  mA  typical  supply  current 

-  Maintenance  of  internal  logic  values  and  control  states 

-  Mode  initialization  via  HALT  instruction 

-  Mode  release  via  external  interrupt  or  reset 

□  Stop  mode 

- 1  (xA  typical  supply  current 

-  Disabling  of  internal  clock  generation  and 
internal  logic 

-  Maintenance  of  RAM  contents 

-  Mode  initialization  via  hardware  (VDD) 

-  Mode  release  via  reset 


Pin  Identification 


Pin 

No.        Symbol         Name  Function 

1  TO  Test  0  Testable  input  using  conditional  jump  instructions 

JT0  and  JNT0.  Also  enables  clock  output  via  the 
 ENTO  CLK  instruction.  

2  XTAL1  Crystal  1        One  of  two  inputs  for  external  crystal  oscillator  or 

LC  circuit  to  generate  internal  clock  signals  May 
also  be  used  as  an  input  for  external  clock  signals 
(Non-TTL-compatible  V,H ) 

3  XTAL2  Crystal  2        One  of  two  inputs  for  external  crystal  oscillator  or 

LC  circuit  to  generate  internal  clock  signals.  (Non- 
TTL-compatible  VIH )  

4  RESET  Reset  Active-low  input  line  that  initializes  the  proces- 

sor Also  used  to  release  both  the  Halt  and  Stop 
modes  © 

5  SS  Single  Step     Active-low  input  line,  that,  in  conjunction  with  ALE, 

causes  the  processor  to  single-step  through  a  pro- 
gram one  instruction  at  a  time 

6  INT  Interrupt        Active-low  input  line  that  causes  an  interrupt  if  an 

enable  instruction  has  been  executed  A  reset  dis- 
ables the  interrupt  May  be  used  as  a  testable  input 
with  a  conditional  jump  instruction  Can  also  be 
used  to  release  the  Halt  mode 

7  EA  External         Input  line  that  inhibits  internal  program  memory 

Access         fetches  and  initiates  access  of  external  program 

memory.  Essential  for  system  testing  and  may  also 
be  used  for  program  debugging 

8  RD  Read  Active-low  output  strobe  line  that  is  used  to  read 

data  from  external  data  memory 

9  PSEN  Program        Active-low  output  line  that  is  used  to  fetch  instruc- 

Store  Enable  tions  from  external  program  memory 

10  WR  Write  Active-low  output  strobe  line  that  is  used  to  write 

data  into  external  data  memory 

11  ALE  Address        Output  line  for  address  latch  enable  At  the  falling 

Latch  Enable  edge  of  ALE,  the  address  of  either  external  data 
memory  or  external  program  memory  is  available 
on  the  bus 

12-19  DB0-DB7       Bus  These  I/O  lines  constitute  an  8-bit  bidirectional 

data/address  bus  Synchronous  read  and  write  

operations  can  be  performed  on  this  bus  using  RD 
and  WR  signals  Data  driven  out  on  the  bus  by  an 
OUTL  BUS  instruction  is  statically  latched 
The  address  of  external  memory  is  available  on  the 
bus  at  the  falling  edge  of  ALE  when  reading  from 
external  program  memory  or  writing  to  and  reading 
from  external  data  memory  During  external  pro- 
gram memory  fetches,  the  least-significant  8  bits  of 
the  external  program  memory  address  are  driven 
out  on  the  bus  and  the  addressed  instruction  is 
fetched  using  PSEN  When  no  external  memory  is 
used,  the  bus  can  serve  as  a  true  bidirectional  8-bit 
port  Information  is  strobed  in  or  out  by  the  RD  and 
WR  signals 


20 

VSs 

Ground 

Ground  potential 

21-24, 
35-38 

^20-^27 

Port  2 

These  lines  constitute  Port  2,  an  8-bit  quasi- 
bidirectional  port  During  external  program 
memory  fetches,  P20-P23  output  the  most- 
signficant  4  bits  of  the  external  program  mem- 
ory address.  Lines  P20-P23  can  also  De  used 
as  a  4-bit  I/O  expander  bus  to  interface  with 
the  optional  M.PD82C43  I/O  expander 

25 

PROG 

Program 
Pulse 

This  line  is  used  as  an  output  strobe  when  interfac- 
ing with  the  optional  jxPD82C43  I/O  expander. 

26 

vDD 

Oscillator 
Control 
Voltage  Line 

This  input  line  is  used  to  control  oscillator  stopping 
and  restarting  in  Stop  mode.  Stop  mode  is  enabled 
by  forcing  VDD  LOW  during  a  reset. 

27-34 

P10-P17 

Portl 

These  lines  constitute  Port  1,  an  8-bit,  general- 
purpose  quasi-bidirectional  port. 

39 

T1 

Test  1 

Testable  input  using  conditional  jump  instruc- 
tions JT1  and  JNT1  Can  also  be  used  as  the  timer/ 
counter  input  line  via  the  STRT  CNT  instruction 

40     Vcc  Primary         Power  supply.  Vcc  must  be  between  +  2  5V  to 

Power  +  5.5V  for  normal  operation  In  Stop  mode,  Vcc 

Supply  must  be  at  least  +  2V  to  ensure  data  retention. 


Note:  ©  The  pulse  width  of  RESET  must  be  a  minimum  of  5  machine  cycles  in  length  following 

oscillator  stabilization  to  reinitialize  the  processor  and  stabilize  CPU  operation  At  power- 
Rev/1  up,  the  states  of  the  output  lines  are  undefined  until  completion  of  reset 


4-103 


MPD80C48/80C35 

Pin  Configuration 


TO 
XTAL1 
XTAL2 
RESET 
SS 
INT 
EA 
RD 
PSEN 
WR 
ALE 
DB0 
DB1 
OB2 
DB3 
DB4 
DB5 


C  1 

C  2 
C  3 
C  4 
C  5 
C  6 
C  7 
C  8 
C  9 
C  10 

C  11 

C  12 
C  13 
C14 

Cis 

C16 

C  17 

Cis 

C  19 
C  20 


8048/ 
8748/ 
8035L 


3 
D 
3 
3 
3 
3 
1 
3 
3 
3 
3 
3 

28  3 
27  1 
3 

3 
3 
3 
3 


PROG 

P23 
P22 

P21 
P2o 


Standby  Function 

HALT  mode 

In  Halt  mode,  the  oscillator  continues  to  operate,  but  the 
internal  clock  is  disabled.  The  status  of  all  internal  logic  just 
prior  to  execution  of  the  HALT  instruction  is  maintained  by 
the  CPU.  In  Halt  mode,  power  consumption  is  less  than 
10  percent  of  normal  llPD80C48  operation  and  less  than 
1  percent  of  normal  8048  operation. 
The  Halt  mode  is  initiated  by  execution  of  the  HALT 
instruction,  and  is  released  by  either  INT  or  RESET  input. 
INT  input:  When  the  INT  pin  receives  a  low-level  input,  if 
interrupts  are  enabled,  the  internal  clock  is  restarted  and 


the  interrupt  is  executed  after  the  first  or  second  instruction 
following  the  HALT  instruction.  However,  if  interrupts  are 
disabled,  program  operation  is  resumed  from  the  next 
address  following  the  HALT  instruction.  The  first  instruc- 
tion following  a  HALT  instruction  should  be  a  NOP 
instruction  to  ensure  proper  program  execution. 
If  the  Halt  mode  is  released  when  interrupts  are  enabled, 
the  interrupt  service  routine  is  usually  executed  after  the 
first  or  second  instruction  following  the  release  of  Halt 
mode.  However,  if  either  a  timer  or  external  interrupt  is 
accepted  within  one  machine  cycle  prior  to  a  HALT  instruc- 
tion, the  corresponding  timer  or  external  interrupt  service 
routine  is  executed  immediately  following  the  release  of 
Halt  mode.  It  is  important  to  note  this  sequence  of  execu- 
tion when  considering  interrupt  service  routine  execution 
following  a  HALT  instruction. 

RESET  input:  When  a  low-level  input  is  received  by  the 
RESET  pin,  Halt  mode  is  released  and  the  normal  reset 
operation  is  activated,  restarting  program  operation  from 
address  0. 
Stop  mode 

In  Stop  mode,  the  oscillator  is  deactivated  and  only  the 
contents  of  RAM  are  maintained.  The  operation  status 
of  the  liPD80C48  resembles  that  of  a  reset  condition. 
Because  only  the  contents  of  RAM  are  maintained,  Stop 
mode  provides  even  lower  power  consumption  than  Halt 
mode,  only  requiring  a  minimum  Vcc  as  low  as  +  2V.  


Stop  mode  is  initiated  by  setting  VDD  to  LOW  when  RESET 
is  LOW,  to  protect  the  contents  of  RAM.  Stop  mode  is 
released  by  first  raising  the  supply  voltage  at  the  Vcc  pin 
from  standby  level  to  correct  operating  level  and  setting 
VDD  to  HIGH  when  RESET  is  LOW.  After  the  oscillator  has 
been  restarted  and  the  oscillation  has  stabilized,  RESET 
must  be  set  to  HIGH,  whereby  program  operation  is  started 
from  address  0. 


Stop  Mode  Circuit 


Voltage 
Regulator 


-W- 


T 


J 


c CLEAR  Q 


rvw — f  fc>o- 
X 


Notes:  ©  D  flip-flops  must  be  CMOS  (74C74  or  equivalent) 

@  Designated  gates  must  be  CMOS  (74C04  or  equivalent) 


Q 

CLEAR 

< 

© 

O 

Q 

1  +  5V 

3  0V  ■=- 
BatteryT 


T 

I 


RESET 


4-104 


Stop  Mode  Timing 


5  Machine  Cycles      Oscillation  Stabilization  Time 


Stop  Mode  Circuit:  Since  VDD  controls  the  restarting 
of  the  oscillator,  it  is  important  that  VDD  be  protected  from 
noise  interference.  The  time  required  to  reset  the  CPU  is 
represented  by  XA  (see  Stop  Mode  Timing  diagram),  which 
is  a  minimum  of  5  machine  cycles.  The  reset  operation  will 
not  be  completed  in  less  than  5  machine  cycles.  In  Stop 
mode,  it  is  important  to  note  that  if  VDD  goes  LOW  before  5 
machine  cycles  have  elapsed,  the  CPU  will  be  deactivated 
and  the  output  of  ALE,  RD,  WR,  PSEN,  and  PROG  will  not 
have  been  stabilized. 


(xPD80C48/80C35 

Oscillation  stabilization  time  is  represented  by  t2  (see  Stop 
Mode  Timing  diagram).  When  VDD  goes  HIGH,  oscillator 
operation  is  reactivated,  but  it  takes  time  before  oscillation 
can  be  stabilized.  In  particular,  such  high  Q  resonators  as 
crystals  require  longer  periods  to  stabilize.  Because  there 
is  a  delay  between  restarting  of  the  oscillator  and  oscillator 
stabilization,  t2  should  be  long  enough  to  ensure  that  the 
oscillator  has  been  fully  stabilized. 
To  facilitate  Stop  mode  control,  an  external  capacitor  can 
be  connected  to  the  RESET  pin  (see  Stop  Mode  Control 
Circuit),  affecting  only  t2,  allowing  control  of  the  oscillator 
stabilization  time.  When  VDD  is  asserted  in  Stop  mode, 
the  capacitor  begins  charging,  pulling  up  RESET.  When 
RESET  reaches  a  threshold  level  equivalent  to  a  logic  1 , 
Stop  mode  is  released.  The  time  it  takes  RESET  to  reach 
the  threshold  level  of  logic  1  determines  the  oscillator  stabi- 
lization time,  which  is  a  function  of  the  capacitance  and 
pull-up  resistance  values. 


Stop  Mode  Control  Circuit 


Note:  ©  Polarized  electrolytic  capacitor 


jp-channel 


Pull-up 
Resistance 


n-channel 


to.  © 


Port  Operation 

A  port-loading  option  is  offered  at  the  time  of  ordering  the 
mask.  Individual  source  current  requirements  for  Port  1 
and  the  upper  and  lower  halves  of  Port  2  may  be  factory 
set  at  either  -  5|jlA  or  -  50jjlA  (see  Port-Loading  Options 
table).  The  -  50|xA  option  is  required  for  interfacing  with 
TTL/NMOS  devices.  The  -  5|xA  option  is  recom- 
mended for  interfacing  to  other  CMOS  devices.  The 
CMOS  option  results  in  lower  power  consumption  and 
greater  noise  immunity. 

Port  lines  P10  to  P17  and  P24  to  P27  include  a  protective 
circuit  "E"  to  prevent  a  signal  conflict  at  the  port.  The  circuit 
prevents  a  logic  1  from  being  written  to  a  line  that  is  being 
pulled  down  externally  (see  Port  Protection  Circuit  "E"  dia- 
gram). When  a  logic  0  is  detected  at  the  port  line  and  a  logic 
1  is  written  from  the  bus,  the  NOR  gate  sends  a  logic  1  to 
the  D  input  of  the  flip-flop.  The  output  is  inverted,  forcing  the 
NAND  gate  to  send  a  high-level  output.  This  turns  off  tran- 
sistor A,  preventing  the  output  of  a  logic  1  from  the  port. 


Port-Loading  Options 

lOH  (min)  Vcc  =  VDD  =  5V  ±  10%;  VOH  =  2.4V  (min) 


Option 
Selected 

P20-P23 

P24_P27 

Unit 

A 

-5 

-5 

-5 

B 

-50 

-5 

-5 

C 

-5 

-50 

-5 

HA 

D 

-50 

-50 

-5 

HA 

E 

-5 

-5 

-50 

HA 

F 

-50 

-5 

-50 

G 

-5 

-50 

-50 

|iA 

H 

-50 

-50 

-50 

HA 

Notes:  ©  The  selection  of  I0h  =  - 
when  used  as  input  port 
®  The  selection  of  l0H  =  - 

5|xA  will  result  in  a 
50^A  will  result  in 

port  source  current  of  l|LP  = 
a  port  source  current  of  l|LP  = 

-  4<VA  max 
-  50(VA 

4-105 


PPD80C48/80C35 

Oscillator  Operation 

The  oscillator  maintains  an  internal  frequency  for  clock 
generation  and  controls  all  system  timing  cycles.  The 
oscillation  is  initiated  by  either  a  self-generating  external 
resonator  or  external  clock  input.  The  oscillator  acts  as  a 
high-gain  amplifier  which  produces  square-wave  pulses 
at  the  frequency  determined  by  the  resonator  or  clock 
source  to  which  it  is  connected. 
To  obtain  the  oscillation  frequency,  an  external  LC  network 


may  be  connected  to  the  oscillator,  or,  a  ceramic  or  crystal 
external  resonator  may  be  connected. 
As  the  crystal  frequency  is  lowered,  there  is  an  equivalent 
reduction  in  series  resistance  (R).  As  the  temperature  of  the. 
crystal  is  lowered,  R  is  increased.  Due  to  this  relationship,  it 
becomes  difficult  to  stabilize  oscillation  when  there  is  low 
power  supply  voltage.  When  Vcc  is  less  than  2.7V  and  the 
oscillator  frequency  is  3MHz  or  less,  Ta  (ambient  tempera- 
ture) should  not  be  less  than  -  10°C. 


Port  Protection  Circuit  "E" 

ORL.ANL 


Pull-up  Resistance 


Write 
Pulse 


Crystal  Frequency  Reference  Circuit 


LC  Frequency  Reference  Circuit 


I 


X 


1  I_ 


L  C  Nominal  f 
45rH     20pF       5  2MHz 

120fiH     20pF      3  2MHz 


Notes:  ©  Crystal  oscillator  constants  of  fosc  =  6MHz 
Rmax  =  son 
CL  =  16  ±  0  2pF 
P  =  1  ±  0  2mW 
©  Operating  frequency  less  than  4MHz 
0  <  Ci  s  20pF 
0  <  C2  s  20pF 
I  Ca  -  C,  |  ^  10pF 
®  Operating  frequency  more  than  4MHz 
0<C!  <  10pF 
0  <  C2  s  10pF 
|  C2  -  C,  |  s  5pF 


Note:  Cpp  =  5-10pF  Pin  to  pin  capacitance  should  be  approximately  20pF,  including 
stray  capacitance 


4-106 


Ceramic  Resonator  Frequency  Reference  Circuit 


uPD80C48/80C35 
Major  Input  and  Output  Signals 


■rrl 

4=r  I  1 


r 


:  Cn  >  C2 

|  C1  -  C2  |  =  20pF 
For  example,  Ct  =  30pF,  and  C2  =  10pF 
Values  of  C|  and  C2  do  not  include  stray  capacitance 


External  Clock  Frequency  Reference  Circuit 


4> 


Open 


Note:  A  minimum  voltage  of  Vcc-1  is  required  for  XTAL1  to  go  HIGH 


Reset 
Single 
Step 
External 
Memory 


Test 


1= 

Interrupt  


80C48/ 
80C35 


Port  #1 
Port  #2 
Read 
Writ* 

Program  Store 
Enable 

Address  Latch 
Enable 


Port  Expander 
Strobe 


Instruction  Set  Symbol  Definitions 


Symbol 

Description 

A 

Accumulator 

AC 

Auxiliary  Carry  Flag 

addr 

Program  or  data  memory  address  (a0-a7)  or  (a0-a10) 

b 

Accumulator  bit  (b  =  0-7) 

BS 

Bank  Switch 

BUS 

Bus 

C 

Carry  Flag 

CLK 

Clock 

CNT 

Counter 

data 

8-bit  binary  data  (d0-d7) 

DBF 

Memory  Bank  Flip-Flop 

FO,  F1 

Flag  0,  Flag  1 

INT 

Interrupt  pin 

n 

Indicates  the  hex  number  of  the  specified  register 

or  port 

PC 

Program  Counter 

PP 

Port  1 ,  Port  2,  or  Port  4-7  (p  =  1 , 2,  or  4-7) 

PSW 

Program  Status  Word 

Rr 

Register  R0-R7  (r  =  0-7) 

SP 

Stack  Pointer 

T 

Timer 

TF 

Timer  Flag 

TO,  T1 

Test  0,  Test  1  pin 

# 

Immediate  data  indication 

@        Indirect  address  indication 

X 

Indicates  the  hex  number  corresponding  to 

the  accumulator  bit  or  page  number  specified 

in  the  operand 

(x) 

Contents  of  RAM 

((x)) 

Contents  of  memory  addressed  by  (x) 

Transfer  direction,  result 

A 

Logical  product  (logical  AND) 

V 

Logical  sum  (logical  OR) 

V 

Exclusive  OR 

Complement 

4-107 


,  PD80C48  80C35 


Instruction  Set 


Hex 

Instruction  Code 

Mnemonic 

Function 

Description 

Code 

i>7 

°6 

Ds 

n3 

D2 

D, 

Do 

Cycles  Bytes 

Accumulator 

ADD  A,  # 
data 

(A)  «-  (A)  +  data 

Adds  immediate  data  d0-d7  to  the  accumulator. 
Sets  or  clears  both  carry  flags.® 

03 

0 
d7 

0 
d6 

0 
d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

1 

do 

2  2 

ADDA,  Rr 

(A)  -  (A)  +  (Rr) 
r  =  0-7 

Adds  the  contents  of  register  Rr  to  the 
accumulator.  Sets  or  clears  both  carry  flags  © 

6n© 

0 

1 

1 

0 

1 

r 

1  1 

ADD  A,  @  Rr 

(A)-(A)  +  «Rr)) 
,  =  0-1 

Adds  the  contents  of  the  internal  data  memory 
location  specified  by  bits  0-5  of  register  Rr  to  the 
accumulator.  Sets  or  clears  both  carry  flags.© 

6n© 

0 

1 

1 

0 

0 

0 

0 

r 

1  1 

ADDC  A,  # 
data 

(A) «-  (A)  +  data  +  (C) 

Adds,  with  carry,  immediate  data  d0-d7  to  the 
accumulator.  Sets  or  clears  both  carry  flags.© 

13 

0 
d7 

0 
d6 

0 

d5 

1 

d4 

0 
d3 

0 

d2 

1 

di 

1 

do 

2  2 

ADDC  A,  Rr 

(A)-(A)  +  (Rr)  +  (C) 
r  =  0-7 

Adds,  with  carry,  the  contents  of  register  Rr  to  the 
accumulator.  Sets  or  clears  both  carry  flags.© 

7n© 

0 

1 

1 

1 

1 

r 

r 

r 

1  1 

ADDC  A, 

@  Rr 

(A)-(A)  +  ((Rr))  +  (C) 
r  =  0-1 

Adds,  with  carry,  the  contents  of  the  internal  data 
memory  location  specified  by  bits  0-5  of  register 
Rr,  to  the  accumulator.  Sets  or  clears  both  carry 
flags.© 

7n© 

0 

1 

1 

1 

0 

0 

0 

r 

1  1 

ANL  A,  # 
data 

(A)  -  (A^\data 

Takes  the  logical  product  (logical  AND)  of 
immediate  data  d0-d7  and  the  contents  of 
the  accumulator,  and  stores  the  result  in  the 
accumulator. 

53 

0 

d7 

1 

d6 

0 
d5 

1 

d4 

0 

d3 

0 
d2 

1 

di 

1 

do 

2  2 

ANL  A,  Rr 

(A)  -  (A)A(Rr) 
r  =  0-7 

Takes  the  logical  product  (logical  AND)  of  the 
contents  of  register  Rr  and  the  accumulator,  and 
stores  the  result  in  the  accumulator 

5n© 

0 

1 

0 

1 

1 

r 

r 

1  1 

ANL  A,  @  Rr 

(A)  -  (A)A«Rr)) 
r  =  0-1 

Takes  the  logical  product  (logical  AND)  of  the 
contents  of  the  internal  data  memory  location 
specified  by  bits  0-5  of  register  Rr,  and  the 
accumulator,  and  stores  the  result  in  the 
accumulator. 

5n© 

0 

1 

0 

1 

0 

0 

0 

' 

1  1 

CPL  A 

(A)  *-  (A) 

Takes  the  complement  of  the  contents  of  the 
accumulator. 

37 

o 

0 

1 

1 

0 

1 

1 

1 

■j  1 

CLRA 

(A)-0 

Clears  the  contents  of  the  accumulator 

27 

0 

0 

1 

0 

0 

1 

1 

1 

1  1 

DA  A 

Converts  the  contents  of  the  accumulator  to  BCD. 
Sets  or  clears  the  carry  flags.  When  the  lower  4 
bits  (Ao_3)  are  greater  than  9,  or  if  the  Auxiliary 
Carry  Flag  has  been  set,  adds  6  to  Aq_3>  When  the 
upper  4  bits  (A^)  are  greater  than  9  or  if  the  Carry 
Flag  (C)  has  been  set,  adds  6  to  A4_7  If  an 
overflow  occurs  at  this  point,  C  is  set.© 

57 

0 

1 

0 

1 

0 

1 

1 

1 

1  1 

DEC  A 

(A) -(A)-  1 

Decrements  the  contents  of  the  accumulator  by  1 . 

07 

0 

0 

0 

0 

0 

1 

1 

1 

1  1 

INC  A 

(A)  -  (A)  +  1 

Increments  the  contents  of  the  accumulator  by  1 . 

17 

0 

0 

0 

1 

0 

1 

1 

1 

1  1 

ORLA,# 
data 

(A)  -  (A)Vdata 

Takes  the  logical  sum  (logical  OR)  of  immediate 
data  d0-d7  and  the  contents  of  the  accumulator, 
and  stores  the  result  in  the  accumulator 

43 

0 
d7 

0 
ds 

0 

d4 

0 

d3 

0 

d2 

1 

di 

1 

do 

2  2 

ORL  A,  Rr 

(A)  -  (A)V(Rr) 
r  =  0-7 

Takes  the  logical  sum  (logical  OR)  of  register  Rr 
and  the  contents  of  the  accumulator,  and  stores 
the  result  in  the  accumulator 

4n@ 

0 

1 

0 

0 

1 

r 

' 

r 

1  1 

ORL  A,  @  Rr 

(A)  -  (A)Vt(Rr)) 
r  =  0-1 

Takes  the  logical  sum  (logical  OR)  of  the  contents 
of  the  internal  data  memory  location  specified  by 
bits  0-5  in  register  Rr,  and  the  contents  of  the 
accumulator,  and  stores  the  result  in  the 
accumulator. 

4n© 

0 

1 

0 

0 

0 

0 

0 

r 

1  1 

RL  A 

(Ab  +  1)-(Ab) 
(Ao)  -  (A7) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  left.  The  MSB  is  rotated  into  the  LSB. 

E7 

1 

1 

1 

0 

0 

1 

1 

1 

1  1 

RLCA 

(Ab  +  1)-(Ab) 
(Ao)-(C) 
(C)-(A7) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  left  through  carry. 

F7 

1 

1 

1 

1 

0 

1 

1 

1 

1  1 

RR  A 

(Ab)-(Ab  +  1) 
(A7)  -  (Ao) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  right.  The  LSB  is  rotated  into  the  MSB 

77 

0 

1 

1 

1 

0 

1 

1 

1 

1  1 

RRCA 

(Ab)-(Ab  +  1) 
(A7)-(C) 
(C)-(Ao) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  right  through  carry 

67 

0 

1 

1 

0 

0 

1 

1 

1 

1  1 

SWAP  A 

(A4_7)  ~  (Ao_3) 

Exchanges  the  contents  of  the  lower  4  bits  of  the 
accumulator  with  the  upper  4  bits  of  the 
accumulator. 

47 

0 

0 

0 

0 

1 

1 

1 

1  1 

XRLA,#data 

(A)-(A)Vdata 

Takes  the  exclusive  OR  of  immediate  data  d0-d7 
and  the  contents  of  the  accumulator,  and  stores 
the  result  in  the  accumulator. 

D3 

1 

d7 

d6 

0 
d5 

1 

d4 

0 
d3 

0 

d2 

1 

di 

1 

do 

.2  2 

XRL  A,  Rr 

(A)  -  (A)y(Rr) 
r  =  0-7 

Takes  the  exclusive  OR  of  the  contents  of  register 
Rr  and  the  accumulator,  and  stores  the  result  in 
the  accumulator. 

Dn© 

1 

0 

1 

1 

r 

1  1 

XRL  A,  @  Rr 

(A)  -  (A)yj(Rr)) 
r  =  0-1 

Takes  the  exclusive  OR  of  the  contents  of  the 
location  in  data  memory  specified  by  bits  0-5  in 
register  Rr,  and  the  accumulator,  and  stores  the 
result  in  the  accumulator. 

Dn© 

1 

0 

1 

0 

0 

0 

r 

1  1 

Branch 

DJNZ  Rr, 
addr 

(Rr)-(Rr)-  1 
If  (Rr)  *  0,  then 
(PCo_7)  -  addr 
,  =  0-7 

Decrements  the  contents  of  register  Rr  by  1,  and  if 
the  result  is  not  equal  to  0,  jumps  to  the  address 
indicated  by  a0-a7. 

En 

1 

a7 

a6 

1 

a5 

0 
a4 

1 

a3 

r 

a2 

ai 

r 

a0 

2  2 

JBb  addr 

(PCo_7)  -  addr  if  b  =  1 
(PC)  =  (PC)  +  2  if  b  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the  bit 
in  the  accumulator  specified  by  b0-b2  is  set. 

x2© 

b2 
a7 

a6 

b0 
a5 

1 

a4 

0 

a3 

0 
a2 

1 

ai 

0 
a0 

2  2 

4-108 


|jlPD80C48/80C35 

Instruction  Set  (Cont.)  


Instruction  Code 


Mnemonic 

Function 

Description 

Code 

D7 

D6 

D8 

D4 

»3 

02 

D1 

Do 

Cycles 

Bytes 

Branch  (Cont.) 

JCaddr 

(PCo_7)-addrifC  =  1 
(PC)-(PC)  +  2ifC  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Carry  Flag  is  set. 

F6 

1 

a7 

1 

a6 

1 

a5 

1 

a4 

0 
a3 

1 

a2 

1 

■1 

0 
a0 

2 

2 

JFO  addr 

(PCo_7)-addrifFO  =  1 
(PC) -(PC)  +  2ifF0  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  FO 
is  set. 

B6 

1 

a7 

0 
a6 

1 

a5 

1 

a4 

0 

a3 

1 

a2 

1 

■1 

0 

a0 

2 

2 

JF1  addr 

(PCo_7)-addrifF1  =  1 
(PC)  -  (PC)  +  2  if  F1  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  F1 
is  set. 

76 

0 

a7 

1 

a6 

1 

a5 

1 

a4 

0 
a3 

1 

a2 

1 

«1 

0 
a0 

2 

2 

JMP  addr 

(PCno) -  addre_10 
(PCo_7)-addro_7 
(PC,,)  -  DBF 

Jumps  directly  to  the  address  specified  by  a0-a10 
and  the  DBF. 

x4© 

■10 

a7 

a9 
a6 

a8 
a5 

0 
a4 

0 
a3 

1 

a2 

0 

a1 

0 

a0 

2 

2 

JMPP  @  A 

(PC*.7)-((A)) 

Replaces  the  lower  8  bits  of  the  Program  Counter 
with  the  contents  of  program  memory  specified 
by  the  contents  of  the  accumulator,  producing 
a  jump  to  the  specified  address  within  the 
current  page. 

B3 

1 

0 

1 

1 

0 

0 

1 

1 

2 

1 

JNC  addr 

(PC0-7)  -  addr  if  C  =  0 
(PC) -  (PC)  +  2  if  C  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Carry  Flag  is  not  set 

E6 

1 

1 

1 

0 

0 
a3 

a2 

1 

0 

ao 

2 

2 

JNI  addr 

(PCo_7)-addrifl  =  0 
(PC)  -  (PC)  +  2  if  I  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Interrupt  Flag  is  not  set. 

86 

1 

0 

0 

0 

0 

1 

0 

2 

2 

JNTOaddr 

(PCo_7)-addrifTO  =  0 
(PC)  -  (PC)  +  2  if  TO  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  Test  0 
is  LOW. 

26 

0 

0 

1 

0 

0 

1 

0 

2 

2 

JNT1 addr 

(PCo_7)-addrifT1  =0 
(PC) -(PC)  +  2  if  T1  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  Test  1 
is  LOW. 

46 

0 
a7 

1 

a6 

0 
a5 

0 
a4 

0 

a3 

a2 

1 

a1 

0 

ao 

2 

2 

JNZ  addr 

(PC0-7) «-  addr  if  A  *  0 
(PC)-(PC)  +  2  if  A  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the 
contents  of  the  accumulator  are  not  equal  to  0. 

96 

1 

a7 

0 

a6 

0 
a5 

1 

a4 

0 

a3 

1 

»1 

0 
a0 

2 

2 

JTFaddr 

(PCo_7)-addrifTF  =  1 
(PC) -(PC)  +  2ifTF  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Timer  Flag  is  set.  The  Timer  Flag  is  cleared  after 
the  instruction  is  executed. 

16 

0 

a7 

0 
a6 

0 

a5 

1 

a4 

0 

a3 

1 

«1 

0 
a0 

2 

2 

JTOaddr 

(PC„_7)-addrifTO  =  1 
(PC) -(PC)  +  2  if  TO  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  Test  0 
is  HIGH. 

36 

0 

a7 

0 

a6 

1 

a5 

1 

a4 

0 

a3 

1 

a1 

0 
a0 

2 

2 

JT1  addr 

(PCo_7)-addrifT1  =  1 
(PC) -(PC)  +  2ifT1  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  Test  1 
is  HIGH. 

56 

0 

a7 

1 

a6 

0 

a5 

1 

a4 

0 
a3 

a2 

1 

a1 

0 
a0 

2 

2 

JZ 

(PCq_7)  —  addr  if  A  =  0 
(PC) -(PC)  +  2  if  A  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  the 
contents  of  the  accumulator  are  equal  to  0. 

C6 

1 

a7 

1 

a6 

0 

a5 

0 
a4 

0 
a3 

1 

■1 

0 
a0 

2 

2 

Control 

EN  I 

Enables  external  interrupts.  When  external 
interrupts  are  enabled,  a  low-level  input  to  the  INT 
pin  causes  the  processor  to  vector  to  the  interrupt 
service  routine. 

05 

0 

0 

0 

0 

0 

0 

DISI 

Disables  external  interrupts.  When  external 
interrupts  are  disabled,  low-level  inputs  to  the  INT 
pin  have  no  effect  on  program  execution. 

15 

0 

0 

0 

1 

0 

0 

ENTOCLK 

Enables  clock  output  to  pin  TO. 

75 

0 

1 

1 

1 

0 

0 

SEL  MBO 

(DBF)  -  0 

Clears  the  Memory  Bank  Flip-Flop,  selecting 
Program  Memory  Bank  0  [program  memory 
addresses  0-2047(10)].  Clears  PC^  after  the  next 
JMP  or  CALL  instruction. 

E5 

1 

1 

1 

0 

0 

0 

SEL  MB1 

(DBF)  -  1 

Sets  the  Memory  Bank  Fiip-Flop,  selecting 
Program  Memory  Bank  1  [program  memory 
addresses  2048-4095(10)].  Sets  PCn  after  the  next 
JMP  or  CALL  instruction. 

F5 

1 

1 

1 

1 

0 

0 

SELRBO 

(BS)  -  0 

Selects  Data  Memory  Bank  0  by  clearing  bit  4 
(Bank  Switch)  of  the  PSW.  Specifies  data  memory 
addresses  0-7(10)  as  registers  0-7  of  Data 
Memory  Bank  0. 

C5 

1 

1 

0 

0 

0 

0 

SELRB1 

(BS)  -  1 

Selects  Data  Memory  Bank  1  by  setting  bit  4 
(Bank  Switch)  of  the  PSW.  Specifies  data  memory 
24-31  (10)  as  registers  0-7  of  Data  Memory  Bank  1. 

D5 

1 

1 

0 

1 

0 

0 

HALT 

Initiates  Halt  mode. 

01 

0 

0 

0 

0 

0 

0 

0 

Data  Moves 

MOVA,# 
data 

(A)  -  data 

Moves  immediate  data  d0-d7  into  the 
accumulator. 

23 

0 
d7 

0 
d6 

1 

d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

MOV  A,  Rr 

(A)  -  (Rr) 
r  =  0-7 

Moves  the  contents  of  register  Rr  into  the 
accumulator. 

Fn© 

1 

1 

1 

1 

1 

r 

r 

MOV  A,  @  Rr 

(A)  -  «Rr)) 
r  =  0-1 

Moves  the  contents  of  internal  data  memory 
specified  by  bits  0-5  in  register  Rr,  into  the 
accumulator. 

Fn© 

1 

1 

1 

1 

t> 

0 

0 

MOV  A,  PSW 

(A) -(PSW) 

Moves  the  contents  of  the  Program  Status  Word 
into  the  accumulator. 

C7 

1 

1 

0 

0 

0 

1 

1 

MOV  Rr,  # 
data 

(Rr)  -  data 
r  =  0-7 

Moves  immediate  data  d0-d7  into  register  Rr. 

Bn© 

1 

d7 

0 
d6 

1 

d5 

1 

d4 

1 

d3 

r 

d2 

r 

di 

MOV  Rr)  A 

(Rr)  -  (A) 
r  =  0-7 

Moves  the  contents  of  the  accumulator  into 
register  Rr 

An© 

1 

0 

1 

0 

1 

r 

r 

MOV  @  Rr,  A 

((Rr))  -  (A) 
r  =  0-1 

Moves  the  contents  of  the  accumulator  into  the 
data  memory  location  specified  by  bits  0-5  in 
register  Rr. 

An© 

1 

0 

1 

0 

0 

0 

0 

MOV  @  Rr,  # 
data 

((Rr))  -  data 

r  =  0-1 

Moves  immediate  data  d0-d7  into  the  data 
memory  location  specified  by  bits  0-5  in 
register  Rr. 

Bn© 

1 

d7 

0 
d6 

1 

d5 

1 

d4 

0 
d3 

0 
d2 

0 
di 

2 

2 

MOV  PSW,  A 

(PSW) -(A) 

Moves  the  contents  of  the  accumulator  into  the 
Program  Status  Word. 

D7 

1 

1 

0 

1 

0 

1 

1 

1 

1 

4-109 


fjiPD80C48/80C35 

Instruction  Set  (Cont.) 


Instruction  Code 


Mft#ntofilc 

Function 

Description 

Code 

o7 

D5 

l>4 

©3 

D2 

Do 

Cycles 

Bytes 

Data  Moves  (Cont.) 

MOVPA,@A 

(PCo-7)-(A) 
(A) «-  ((PC)) 

Moves  the  contents  of  the  program  memory 
location  specified  by  PCg.^  concatenated  witn 
the  contents  of  the  accumulator,  into  the 
accumulator. 

A3 

1 

0 

1 

0 

0 

0 

1 

1 

2 

1 

M0VP3  A, 
@A 

(PCo-7)-(A) 
(PC^-WI 
(A) -((PC)) 

Moves  the  contents  of  the  program  memory 
location  specified  by  001 1  (PCg.,,,  page  3  of 
Program  Memory  Bank  0)  and  the  contents  of  the 
accumulator,  into  the  accumulator. 

E3 

1 

1 

1 

0 

0 

0 

1 

1 

2 

1 

MOVXA,@R 

(A)  -  ((Rr)) 
r  =  0-1 

Moves  the  contents  of  the  external  data  memory 
location  specified  by  register  Rr,  into  the 
accumulator. 

8n© 

1 

0 

0 

0 

0 

0 

0 

r 

2 

1 

MOVX  @  R,  A 

((Rr))  -  (A) 
r  =  0-1 

Moves  the  contents  of  the  accumulator  into  the 
external  data  memory  location  specified  by 
register  Rr. 

9n© 

1 

0 

0 

1 

0 

0 

0 

r 

2 

1 

XCH  A,  Rr 

(A)  -  (Rr) 
,  =  0-7 

Exchanges  the  contents  of  the  accumulator  and 
register  Rr. 

2n@ 

0 

0 

1 

0 

1 

r 

r 

r 

1 

1 

XCHA,  (5  Rr 

(A)  -  ((Rr)) 
r  =  0-1 

Exchanges  the  contents  of  the  accumulator  and 
the  contents  of  the  data  memory  location 
specified  by  bits  0-5  in  register  Rr. 

2n@ 

0 

0 

1 

0 

0 

0 

0 

r 

1 

1 

XCHDA,@ 
Rr 

(A<w)~((Rro_3)) 
,  =  0-1 

Exchanges  the  contents  of  the  lower  4  bits  of  the 
accumulator  with  the  contents  of  the  lower  4  bits 
of  the  internal  data  memory  location  specified  by 
bits  0-5  in  register  Rr. 

3n© 

0 

0 

1 

1 

0 

0 

0 

r 

1 

1 

Flags 

CPLC 

<C)<-(C) 

Takes  the  complement  of  the  Carry  bit. 

A7 

1 

0 

1 

0 

0 

1 

1 

1 

CPLFO 

(F0)-(F0) 

Takes  the  complement  of  Flag  0. 

95 

1 

0 

0 

1 

0 

0 

1 

1 

CPL  F1 

(F1)-(F1) 

Takes  the  complement  of  Flag  1 . 

B5 

1 

0 

1 

1 

0 

0 

1 

1 

CLRC 

(C)-0 

Clears  the  Carry  bit. 

97 

1 

0 

0 

1 

0 

1 

1 

1 

CLRFO 

(FO)-O 

Clears  Flag  0. 

85 

1 

0 

0 

0 

0 

0 

1 

1 

CLR  F1 

(F1)-0 

Clears  Flag  1. 

A5 

1 

0 

1 

0 

0 

0 

1 

1 

Input/Output 

ANLBUS,# 
data 

(BUS)-  (BUS)Adata 

Takes  the  logical  AND  of  the  contents  of  the  bus 
and  immediate  data  d0-d7,  and  sends  the  result  to 
the  bus. 

98 

1 

d7 

0 
d6 

0 
d5 

1 

d4 

0 
d2 

0 
di 

0 
do 

2 

2 

ANL  Pp,  # 
data 

(Pp)-(Pp)Adata 
p  =  1-2 

Takes  the  logical  AND  of  the  contents  of 
designated  port  Pp  and  immediate  data  d0-d7, 
and  sends  the  result  to  port  Pp  for  output. 

9n© 

1 

0 
d6 

0 
d5 

1 

d4 

0 
d2 

P 
di 

P 
do 

2 

2 

ANLD  Pp,  A 

(Pp)-(Pp)A(A<w) 
p  -  4-7 

Takes  the  logical  AND  of  the  contents  of 
designated  port  Pp  and  the  lower  4  bits  of  the 
accumulator,  and  sends  the  result  to  port  Pp  for 
output. 

9n© 

1 

0 

0 

1 

1 

P 

P 

2 

1 

IN  A,  Pp 

(A)-(Pp) 
p.  1-2 

Loads  the  accumulator  with  the  contents  of 
designated  port  Pp. 

On© 

0 

0 

0 

0 

0 

P 

P 

2 

1 

INS  A,  BUS 

(A) -(BUS) 

Loads  the  contents  of  the  bus  into  the 
accumulator  on  the  rising  edge  of  RD. 

08 

0 

0 

0 

0 

0 

0 

0 

2 

1 

MOVD  A,  Pp 

(A0-3)  -  (Pp) 
(Vr)-0 
p  =  4-7 

Moves  the  contents  of  designated  port  Pp  to  the 
lower  4  bits  of  the  accumulator,  and  clears  the 
upper  4  bits. 

On© 

0 

0 

0 

0 

1 

P 

P 

2 

1 

MOVD  Pp,  A 

(Pp)  *~  (Ao-3) 
p  =  4-7 

Moves  the  lower  4  bits  of  the  accumulator  to 
designated  port  Pp.  The  upper  4  bits  of  the 
accumulator  are  not  changed. 

3n© 

0 

0 

1 

1 

1 

P 

P 

2 

1 

ORL  BUS,  # 
data 

(BUS)-  (BUS)Vdata 

Takes  the  logical  OR  of  the  contents  of  the  bus 
and  immediate  data  d0-d7,  and  sends  the  result  to 
the  bus. 

88 

1 

d7 

0 
d6 

0 
d5 

0 
d4 

d3 

0 
d2 

0 

di 

0 
do 

2 

2 

ORLD  Pp,  A 

(Pp)-(Pp)V(A^) 
p  =  4-7 

Takes  the  logical  OR  of  the  contents  of  designated 
port  Pp  and  the  lower  4  bits  of  the  accumulator, 
and  sends  the  result  to  port  Pp  for  output. 

8n© 

1 

0 

0 

0 

1 

P 

P 

2 

1 

ORL  Pp,  # 
data 

(Pp)-(Pp)Vdata 
p  =  1-2 

Takes  the  logical  OR  of  the  contents  of  designated 
port  Pp  and  immediate  data  d0-d7,  and  sends  the 
result  to  port  Pp  for  output. 

9n® 

1 

0 
d6 

0 
d5 

0 
d4 

d3 

0 

d2 

P 

di 

P 

do 

2 

2 

OUTL  BUS,  A 

(BUS) -(A) 

Latches  the  contents  of  the  accumulator  onto  the 

bus  on  the  rising  edge  of  WR. 

Note:  Never  use  the  OUTL  BUS  instruction  when 
using  external  program  memory,  as  this 
will  permanently  latch  the  bus. 

02 

0 

0 

0 

0 

0 

0 

1 

0 

2 

1 

OUTL  Pp,  A 

(Pp)-(A) 
p  =  1-2 

Latches  the  contents  of  the  accumulator  into 
designated  port  Pp  for  output. 

3n® 

0 

0 

1 

1 

1 

0 

P 

P 

2 

1 

Registers 

DEC  Rr 

(Rf)-(Rr)-1 
r  =  0-7 

Decrements  the  contents  of  register  Rr  by  1 . 

Cn® 

1 

1 

0 

0 

1 

r 

r 

r 

1 

1 

INC  Rr 

(Rr)-(Rr)  +  1 
r  =  0-7 

Increments  the  contents  of  register  Rr  by  1 

1n© 

0 

0 

0 

1 

1 

r 

r 

r 

1 

1 

INC  @  Rr 

«Rr))-((Rr))  +  1 
r  =  0-1 

Increments  by  1  the  contents  of  the  data  memory 
location  specified  by  bits  0-5  in  register  Rr. 

1n@ 

0 

0 

0 

1 

0 

0 

0 

r 

1 

1 

4-110 


)jlPD80C48/80C35 


Instruction  Set  (Cont.) 


Instruction  Code 


Mn#ntonic 

Function 

Description 

Code 

D7 

Ds 

Ds 

I>4 

D3 

D2  . 

l>o 

Cycles 

Bytes 

Subroutine 

CALL  addr 

((sp))-(pc),(psw4.7) 

(SP)-(SP)  +  1 
(PCg_10)  <-  addr^o 
(PCo_7)-addro_T 
(PC1t)  DBF 

Stores  the  contents  of  the  Program  Counter 
and  the  upper  4  bits  of  the  PSW  In  the  address 
indicated  by  the  Stack  Pointer,  and  increments  the 
contents  of  the  Stack  Pointer,  calling  the  subrou- 
tine specified  by  address  ao-a10  and  the  DBF. 

x4® 

aio 

a9 
a6 

a8 
a5 

1 

a4 

0 
a3 

1 

a2 

0 
ai 

0 
a0 

2 

2 

RET 

(SP)-(SP)-1 
(PC)-((SP)) 

Decrements  the  contents  of  the  Stack  Pointer 
by  1  and  stores,  in  the  Program  Counter,  the 
contents  of  the  location  specified  by  the  Stack 
Pointer,  executing  a  return  from  subroutine 
without  restoring  the  PSW. 

83 

1 

0 

0 

0 

0 

0 

1 

1 

2 

1 

RETR 

(SP) -  (SP)  -  1 

(PC)^«SP)) 

(PSW4_7)-((SP)) 

Decrements  the  contents  of  the  Stack  Pointer 
by  1  and  stores,  in  the  Program  Counter,  the 
contents  of  the  upper  4  bits  of  the  PSW  and  the 
contents  of  the  location  specified  by  the  Stack 
Pointer,  executing  a  return  from  subroutine  with 
restoration  of  the  PSW. 

93 

1 

0 

0 

1 

0 

0 

1 

1 

2 

1 

Timor/Counter 

ENTCNTI 

Enables  internal  interrupt  of  timer/event  counter. 
If  an  overflow  condition  occurs,  then  an  interrupt 
will  be  generated. 

25 

0 

0 

1 

0 

0 

1 

0 

1 

1 

1 

DIS  TCNTI 

Disables  internal  interrupt  of  timer/event  counter. 

35 

0 

0 

1 

1 

0 

1 

0 

1 

1 

1 

MOV  A,  T 

(A)-(T) 

Moves  the  contents  of  the  timer/counter  into  the 
accumulator. 

42 

0 

1 

0 

0 

0 

0 

1 

0 

1 

1 

MOVT.A 

(T)-(A) 

Moves  the  contents  of  the  accumulator  into  the 
timer/counter. 

62 

0 

1 

1 

0 

0 

0 

1 

0 

1 

1 

STOP  TCNT 

Stops  the  operation  of  the  timer/event  counter. 

65 

0 

1 

1 

0 

0 

1 

0 

1 

1 

1 

STRT  CNT 

Starts  the  event  counter  operation  of  the 
timer/counter  when  T1  changes  from  a  low-level 
input  to  a  high-level  input. 

45 

0 

1 

0 

0 

0 

1 

0 

1 

1 

1 

8TRTT 

Starts  the  timer  operation  of  the  timer/counter. 
The  timer  is  incremented  every  32  machine 
cycles. 

55 

0 

1 

0 

1 

0 

1 

0 

1 

1 

1 

Miscellaneous 

NOP 

Uses  one  machine  cycle  without  performing  any 
operation. 

00 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

Notesi  (D  Binary  instruction  code  designations  r  and  p  represent  encoded  values  or  the  lowest-order  bit  value  of  specified  registers  and  ports,  respectively 

<2>  Execution  of  the  ADD,  ADDC,  and  DA  instructions  affect  the  carry  flags,  which  are  not  shown  in  the  respective  function  equations  These  instructions  set  the  carry  flags  when  there  is  an 

overflow  in  the  accumulator  (the  Auxiliary  Carry  Flag  is  set  when  there  is  an  overflow  of  bit  3  of  the  accumulator)  and  clear  the  carry  flags  when  there  is  no  overflow  Flags  that  are 

specifically  addressed  by  flag  instructions  are  shown  in  the  function  equations  for  those  instructions 
<3>  References  to  addresses  and  data  are  specified  in  byte  1  and/or  2  in  the  opcode  of  the  corresponding  instruction 
<D  The  hex  value  of  n  for  specific  registers  is  as  follows 

a)  Direct  addressing 

Rq.  n  =  8  R2n=A  R4n  =  C  R6n  =  E 
^11  =  9      R3  n  =  B      R5n  =  D      R7n  =  F 

b)  Indirect  addressing 
@R0n  =  0      @R1n  =  1 

®  The  hex  value  of  n  for  specific  ports  is  as  follows 

P1n  =  9      P4    n  =  C      P6n  =  E 

P2  n  =  A      P5    n  =  D      P7n  =  F 
©  The  hex  value  of  x  for  specific  accumulator  or  address  bits  is  as  follows 

a)  JBb  instruction 

B0x  =  1  B2  x  =  5  B4x  =  9  B6x  =  D 
Bi  x  =  3      B3x  =  7      B5x  =  B      B7x  =  F 

b)  JMP  instruction 

PageO  x  =  0  Page  2  x  =  4  Page  4  x  =  8  Page  6  x  =  C 
Page  1  x  =  2      Page  3  x  =  6      Page  5  x  =  A      Page  7  x  =  E 

c)  CALL  instruction 

PageO  x  =  1  Page 2  x  =  5  Page 4  x  =  9  Page 6  x  =  D 
Pagel  x  =  3      Page  3  x  =  7      Page  5  x  =  B      Page  7  x  =  F 


4-111 


|xPD80C48/80C35 

DC  Characteristics:  Standard  Voltage  Range 

T.  =  -40°C  to  +85°C;  Vcc  =  +5V  ±  10%;  Vss  =  0V 


Parameter  Symbol 


Min    Typ  Max 


Test  Conditions 


Input  Low 
Voltage 

V,L 

-0.3 

0.8 

V 

Input  High 

V,H 

Vcc  "2 

Vcc 

V 

Ail  except  XTAL1,  XTAL2,  RESET 

Voltage 

V.H1 

Vcc-1 

VCC 

V 

RESET,  XTAL1 ,  XTAL2 

Output  Low 
Voltage 

Vol 

0.45 

V 

l0L  =  2.0mA 

V0H 

2.4 

V 

Bus,  RD,  WR,  PSEN,  ALE,  PROG, 
T0;lOH  =  -100ft  A 

Output  High 
Voltage 

V0H1© 

2.4 

V 

Port1,Port2;lOH  =  -5\iA 
(TypeO) 

Port1,Port2;lOH  =  -50nA 
(Typel) 

V0H2 

Vcc -0.5 

V 

All  outputs;  l0H  =  -0.2|xA 

l|LP© 

-15 

-40 

Port  1,  Port  2;  V|N<  V,L 
(TypeO) 

Input  Current 

-500 

Portl  Port 2;  VIN<V,L 
(Typel) 

'ILC 

-40 

SS,  RESET;  V,N  <  VIL 

input  Leakage 

Ilii 

±1 

T1,lNT,VDD;VssSVIN<Vcc 

Current 

•lI2 

±3 

HA 

EA,VSS<VIN<VCC 

Output  Leakage 
Current 

«lo 

±1 

(xA 

Bus,  TO,  High-Impedance  State; 

Vss<V0sVcc 

Standby 

•cci 

0.4 

0.8 

mA 

Halt  mode;  tCY  =  2.5(xs 

Current 

'CC2 

1 

20 

Stop  mode  @ 

Supply  Current 

Ice 

4 

8 

mA 

tCY  =  2.5(xs 

Data  Retention 
Voltage 

VCCDR 

2.0 

V 

Stop  mode  (VDD,  RESET  s  0.4V) 

DC  Characteristics:  Extended  Voltage  Range 

Ta  =  -40Cto  +85°C;  Vcc  =  +  2.5V  to  +5.5V;  Vss  =  OV 


Limits 

Parameter 

Symb 

ol  Min   Typ  J 

Max 

Unit 

Test  Conditions 

Input  Low  Voltage 

V,L 

-0.3         0.18  Vcc 

V 

Input  High  Voltage 

(All  Except  XTAL 1 ,  XTAL  2) 

V,H 

0.7VCC 

Vcc 

V 

Input  High  Voltage 
(XTAL  1,  XTAL  2) 

V|H1 

0.8VCC 

Vcc 

V 

Output  Low  Voltage 

Vol 

0.45 

V 

l0L  =  10mA 

Output  High  Voltage  (Bus, 
RD,  WR,  PSiFf,  ALE, 
PROG,  TO 

Voh 

0.75VCC 

v 

I0h  =  -lOO^A 

Output  High  Voltage  (All 
Other  Outputs 

VoH1 

0.7VCC 

Portl,  Port  2; 
'oh  =  ~  VA 
(TypeO) 

Portl,  Port  2; 
IOh=-10^A 
(Type  1) 

Output  High  Voltage 
(All  Outputs) 

VOH2 

Vcc  -  0.5 

V 

•oh  =  -0.2(jlA 

Input  Leakage  Current 

'|LP 

-15 

-40 

rA 

VINsV(L  (TypeO) 

(Portl,  Port 2) 

-500 

|iA 

V,m<  v..  (TvpeD 

Input  Leakage  Current 
(SS,  RESET) 

•iLC 

HA 

V,N  ^  VIL 

Input  Leakage  Current 
(T1,  INT) 

I.L1 

±1 

tiA 

VSS  <  V|N  <  VCc 

Input  Leakage  Current 
(EA) 

»IL2 

±3 

^A 

VSs  <  V,N  <  Vcc 

Output  Leakage  Current 
(Bus,  TO  —  High  Impedance 
State) 

•OL 

±1 

ItA 

VSs<V0<Vcc 

Supply  Current 

Ice 

0.8 

1.6 

mA 

Vcc  =  3V, 
tCY  =  10^,8 

Halt  Mode  Standby 
Current 

•cci 

100 

200 

yA 

Vcc  =  3V, 
tCY  =  10(jlS 

Stop  Mode  Standby  Current 

'CC2 

1 

20 

Notes:  ©  Type  0  and  type  1  options  apply  only  to  the  M-PD80C48,  the  H.PD80C35  is  type  1  only 
©  Input  Pin  Voltage  is  V|N,  V,L,  or  V,N,  V,H 


AC  Characteristics 

Read,  Write  and  Instruction  Fetch:  External  Data  and  Program  Memory 
T,  =  -40°Cto  +85  C;  Vcc  =  VPP  =  +5V  ±  10%;VSs  =  OV  


VCC  = 

+  5V  ±  10% 

v  = 

+  2.5V  to  +5.5V 

Test 

Parameter 

Symbol 

Min 

Typ  Max 

Min 

Typ  Max 

Unit 

Conditions 

ALE  Pulse  Width 

tLL 

400 

2160 

ns 

Address  Setup  before  ALE 

tAL 

120 

1620 

ns 

Address  Hold  from  ALE 

tLA 

80 

330 

ns 

© 

Control  Pulse  Width 
(PSEN,  RD,  WR) 

tee 

700 

3700 

ns 

Data  Setup  before  WR 

*DW 

500 

3500 

ns 

Data  Hold  after  WR 

*WD 

120 

370 

ns 

© 

Cycle  Time 

tCY 

2.5 

150 

10 

150 

piS 

6MHz  XTAL 

Data  Hold 

tDR 

0 

200 

0 

950 

ns 

PSEN,  RD  to  Data  In 

*RD 

500 

2750 

ns 

Address  Setup  before  WR 

*AW 

230 

3230 

ns 

© 

Address  Setup  before  Data  In 

tAD 

950 

5450 

ns 

Address  Float  to  RD,  PSEN 

We 

0 

500 

ns 

Control  Pulse  to  ALE 

tCA 

10 

10 

ns 

4-112 


|xPD80C48/80C35 


Port  2  Timing 

T«  =  -40°Cto  +  85°C;  Vcc  =  +  SV  ±  10% 


V99  = 

4  3V  ±  10% 

+  2.5V  to  +5.5V 

Test 

Conditions 

Parameter 

Symbol 

Mfn 

Typ  Max 

Min 

Typ  Max 

Unit 

Port  Control  Setup  before 

Ealllna  Frin»  nf  PROA 

tcP 

110 

860 

ns 

Part  (Vtntml  HaIH  after  Pulllnn 
rvn  \^onum  rwia  ai  ivvf  railing 

Edge  of  PROG 

0 

80 

0 

200 

ns 

® 

PROG  to  Time  P2  Input  must 
be  Valid 

tpR 

810 

5310 

ns 

Output  Data  Setup  Time 

tDP 

250 

3250 

ns 

Output  Data  Hold  Time 

tpD 

65 

820 

ns 

Input  Data  Hold  Time 

tpF 

0 

150 

0 

900 

ns 

PROG  Pulse  Width 

W 

1200 

6450 

ns 

Port  2  I/O  Data  Setup 

tpL 

350 

2100 

ns 

Port  2  I/O  Data  Hold 

tLP 

150 

1400 

ns 

®  For  Control  Outputs  CL  =  80pF,  for  Bus  Outputs  CL  =  150pF 
®  CL  =  20pF 

®  For  Control  Outputs  CL  =  80pF 

®  Refer  to  the  operating  characteristic  curves  for  Supply  Voltage  and  Port  Control  Hold 


BUS  Timing  Requirements 


Symbol             Timing  Formula            Min          Max  Unit 

111 

(7  /  30)  T- 170 

• 

ns 

tAL 

(1/5)T-380 

• 

ns 

tLA 

(1/30)T 

• 

ns 

tec 

(2/5)T-300 

• 

ns 

*DW 

(2/5)T-500 

• 

ns 

two 

(1/30)T+40 

• 

ns 

ton 

(1/10)T-50 

• 

ns 

tRD 

(3  / 10)  T- 250 

• 

ns 

*AW 

(2/5)T-770 

• 

ns 

tAD 

(3/5)T-550 

• 

ns 

Wc 

(1/15)T-165 

• 

ns 

tCP 

(1/10)T-140 

• 

ns 

tpR 

(3/5)T-690 

• 

ns 

W 

(1  / 10)  T- 100 

• 

ns 

tDP 

(2/5)T-750 

• 

ns 

tpo 

(1/10)T-180 

• 

ns 

tpp 

(7  / 10)  T- 550 

• 

ns 

tpL 

(7  /  30)  T- 230 

• 

ns 

tLP 

(1/6)T-265 

• 

ns 

Notes:  T  =  tcv 

Unlisted  parameters  are  not  affected  by  cycle  time 

Timing  Waveforms 

Instruction  Fetch  From  External  Memory 

  tCV   


J  L 


— L  Wc  I-', 


c   r*~  'cc  m[m  ''ca 


i  r 


BUS  Floating)  X  Floating^    ^    X    Floating  X 


Write  to  External  Memory 
ale      I  1 


"L 


h-tcc-n 


Bus  Floating  ^  V     X  boating  X  Data  j{  Floating 


=1 


twD 


Low  Power  Standby  Operation 
1)  Halt  Mode  (When  El) 


<       1  Instr     X 'NT  Execute 


2)  Stop  Mode 


OSC  Starts 


Port  2  Timing 


Read  From  External  Data  Memory 

P-tlL-H 


J  L 


Address  I  I 

  \   ~H  Wc  k-  — H  K-t[ 

Rm,  Float,ng)pr^(  Floating  X  Data 


Floating 


Expander                  l-'^-l'^h-  J^^It 
Port    jC  PC  H  Xr"'  *m  D*"X'>,X1  Con,ro4  X°u,pu'  0m")C 
Output     fy  fy — 


Output  " 
PROG  ' 


(■•- — <pi 


4-113 


(PD80C48/80C35 
Block  Diagram 


Oscillator 
Frequency 


Bus  Buffer 
Port  2 


Port  2  Latch  (Low  4) 

Port  2 

and  Expander 

Latch 

Port  I/O 

(High  4) 

8 

Timer  and 
Event  Counter 


IC 


Higher  Program 
Counter  (4) 


Resident  Program  Memory 
ROM  |xPD80C48  only 
1024x8 


Expansion  to  Additional 
External  Memory  and  I/O 


8 

Lower 

Program 

Counter 

Bus  Latch 
Low  Program 
Counter's  Temp 
Register 


Program 
Status 
Word 


8-Bit  Internal  Bus 


Accumulator  Temporary 
(8)  Register  (8) 


Accumulator 
Latch 


Power 
Supply 


Arithmetic 
Logic  Unit 


 •►+2  5Vto  +  5  5V 

 +-  Ground 

VDD  Standby  Power  Control 


Instruction 
Register/Decoder 


RAM  Address 
Register 


Decimal 
Adjust 


Conditional 
Branch 
Logic 


-  Test  0 

-  Test  1 

-  INT 

-  Flag  0 

-  Flag  1 

-  Timer  Flag 

-  Carry 

-  ACc 


Control  and  Timing 

XTAL  XTAL 

INT 

RESET  PROG 

EA           1      2  ALE 

PSEN 

SS 

RD  WR 

TT1 


Low     Interrupt  Initialize 
Power  I/O 
Standby  Control  Expander 
Strobe 


CPU/Memory 
Separate 


Address 
Latch 
Strobe/ 
Oscillator/  cycle 
Crystal  clock 


Program  Single 
Memory  Step 
Enable 


TT 

Read/Write 
Strobes 


V 


Bus 
Buffer 

and 
Latch 
Portl 


Multiplexer  I 

Register  0 

Register  1 

Register  2 

Register  3 

Register  4 

0) 

■o 
o 

Register  5 

Q 

Register  6 

Register  7 

8-Level  Stack 
(Variable  Word  Length) 

Optional  Second 
Register  Bank 

Data  Store 

Resident  Data  Memory  —  RAM 
(64  x  8) 


Note:  M.PD80C35  does  not  include  ROM 


Absolute  Maximum  Ratings* 


T.  =  25°C 

Operating  Temperature,  Topt 

-40°Cto  +85°C 

Storage  Temperature  (Cerdip  Package),  Tstg 

-65°Cto  +150°C 

Storage  Temperature  (Plastic  Package),  Tstg 

-65°Cto  +125°C 

Voltage  on  Any  Pin,  Vl/0  Vss 

-0.3V  to  Vcc  +0.3V 

Supply  Voltage,  Vcc 

Vss  -  0.3  to  +  10V 

Power  Dissipation,  PD 

0.35w 

*COMMENT:  Exposing  the  device  to  stresses  above  those 
listed  in  Absolute  Maximum  Ratings  could  cause  perma- 
nent damage.  The  device  is  not  meant  to  be  operated 
under  conditions  outside  the  limits  described  in  the  opera- 
tional sections  of  this  specification.  Exposure  to  absolute 
maximum  rating  conditions  for  extended  periods  may  affect 
device  reliability. 


4-114 


|xPD80C48/80C35 


Operating  Characteristic  Curves 

Output  High  Current  vs.  Output  High  Voltage 


5  -200 
O 


vcc  = 

4  5V 

\  Typ 

Mm 

Output  High  Voltage,  VOH  (V) 

Output  High  Current  vs.  Supply  Voltage 


-150-15 


5  -100-10 


a- 
8 


3  4  5  6 

Supply  Voltage,  Vcc  (V) 


Output  Low  Current  vs.  Supply  Voltage 


2  3  4  5 

Supply  Voltage.  Vcc  (V) 


Output  High  Current  vs.  Output  High  Voltage 


_6  -10 

c 
S 


Vcc  =  4  5V 

\ 

V  Typ 

Min\ 

\ 

Output  High  Voltage,  VOH1  (V) 

Output  High  Current  vs.  Supply  Voltage 


VOH2-Vcc-0  5V 

IL  

Supply  Voltage,  Vcc  (V) 

Output  Low  Current  vs.  Output  Low  Voltage 


Output  Low  Voltage,  VOL  (V) 


4-115 


,.PD80C48/80C35 

Operating  Characteristic  Curves  (Cont.) 

Supply  Current  vs.  Oscillation  Frequency 


0  05 
0  03 


Vcc  =  3V 

•cc  Wax 

/ 

lcc1Max 

'cci  Typ 

01        0  2  0.5         1  2 

Oscillation  Frequency,  f(MHz),  (f  =  15/tCY) 


Cycle  Time  vs.  Supply  Voltage 


Opt 

•ration  G 

jarantee 
Area 

Port  Control  Hold  After  PROG,  tpc  Max  (ixPD80C48),  and  Address  to 
Output  Delay,  tacc  Min  (\xPD82C43),  vs.  Supply  Voltage 


O  J  200 

CC  5^ 

CL  « 

<  3 

•o  a- 150 

O  = 

x  o 

o  8 

ts  w 

c  <o 

3  I  100 


Is 


\ 

fiPD82C< 

s,tacc  Mm 

3: 

M 

PD80C4 
tpc  Max 

j  \  N 

2  3  4  5  6 

Supply  Voltage,  Vcq  (V) 

Current  Consumption  as  a  Function  of  Temperature  —  Normal 
Operating  Mode 


f  =  6MHz 

Vcc  =  5  5V 

 -Jcc 

■   *CC1 

Halt  Mode 

2  3  4  5 

Supply  Voltage,  Vcc  (V) 


-40  0  25 

Temperature,  Ta  (°C) 


Supply  Current  vs.  Oscillation  Frequency® 


Current  Consumption  as  a  Function  of  Operating  Frequency  - 
Normal  Operating  Mode 


0  2  0.5  1  2 

Oscillator  Frequency  (MHz) 


Oscillation  Frequency,  f(MHz),  (f  =  15/tcv) 


Note:    External  oscillation  is  assumed  for  frequency  less  than  1MH7 
Internal  oscillation  requires  more  power 


4-116 


f  PD80C48/80C35 


Operating  Characteristic  Curves  (Cont.) 

Current  Consumption  as  a  Function  of  Temperature  —  Stop  Mode 


10 


Vcc  =  5  5V 

/Max 

Typ 

-40  0       25  85 

Temperature,  Ta  (°C) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |a,PD8048HC/35HLC 
Ceramic,  |xPD8048HD/35HLD 
Plastic  Shrinkdip,  ^PD80C48C 
Plastic  Miniflat,  |jlPD80C48G/C35G 


4-117 


80C48/80C35DS-REV1-10-83-L-8K 


Notes 


4-118 


NEC 


fiPD8049H  f  PD8749H  fxPD8039HL 
HIGH  PERFORMANCE 
SINGLE  CHIP  8-BIT  MICROCOMPUTERS 


Description 

The  NEC  uPD8049H,  uPD8749H  and  uPD8039HL  are  sin- 
gle chip  8-bit  microcomputers.  The  processors  differ  only  in 
their  internal  program  memory  options:  the  uPD8049  has 
2K  x  8  bytes  of  mask  ROM,  the  |xPD8749  has  2K  x  8  of 
UV  erasable  EPROM  and  the  fxPD8039HL  has  external 
program  memory. 

Features 

□  High  performance  11  MHz  operation 

□  Fully  compatible  with  industry  standard  8049/8749/8039 

□  Pin  compatible  with  the  uPD8048/8748/8035 

□  HMOS  silicon  gate  technology  requiring  a  single  +  5V 
±10%  supply 

□  1.36  ijls  cycle  time.  All  instructions  1  or  2  bytes 

□  Programmable  interval  timer/event  counter 

□  2K  x  8  bytes  of  ROM,  128  x  8  bytes  of  RAM 

□  External  and  internal  interrupts 

□  96  instructions:  70  percent  single  byte 

□  27  I/O  lines 

□  Internal  clock  generator 

□  Expandable  with  8080A/8085A  peripherals 

□  Available  in  both  ceramic  and  plastic  40-pin  packages 


Pin  Configuration 


Pin  Identification 


XTAL  1  C  2 
XTAL  2  C  3 
RESET  C  4 
SS  C  & 
Wf  C  6 
EA  C  7 
RD  C  8 
PSEN  C  9 
WR  C  10 
ALE  C  11 
DBQC  12 
DB1  C  13 
DB2C  14 
DB3C 
DB4C 
DB5C 
DBgC  18 
DB?C  19 


15 


-v^ — 

40 

5vcc 

39 

38 

□  P27 

37 

□  P26 

36 

□  P25 

35 

□  P24 

34 

□  P17 

33 

□  P16 

8049H/ 

32 

□  P15 

8749H/ 

31 

□  P14 

8039HL 

30 

□  P13 

29 

□  P12 

28 

□  P11 

27 

□  P10 

26 

=}VDD 

25 

□  PROG 

24 

□  P23 

23 

□  P22 

22 

□  P21 

21 

□  P20 

1 

To 

Testable  input  using  conditional  transfer  functions  JT0  and  JNT0. 
The  internal  State  Clock  (CLK)  is  available  to  T0  using  the  ENTO 
CLK  instruction.  T0  can  also  be  used  during  programming  as  a 
testable  flag. 

2 

XTAL  1 

One  side  of  the  crystal,  LC,  or  external  frequency  source.  (Non-TTL 
compatible  VIH.) 

3 

XTAL  2 

The  other  side  of  the  crystal  or  LC  frequency  source.  For  external 
sources,  XTAL  2  must  be  driven  with  the  logical  complement  of  the 
XTAL  1  input. 

4 

RESET 

Active  low  input  from  processor  initialization.  RESET  is  also  used 
for  PROM  programming  verification  and  power-down  (non-TTL 
compatible  VIH). 

5 

SS 

Single  Step  input  (active-low).  SStogether  with  ALE  allows  the 
processor  to  "single-step"  through  each  instruction  in  program 
memory. 

6 

INT 

Interrupt  input  (active-low).  INT  will  start  an  interrupt  if  an  enable 
interrupt  instruction  has  been  executed.  A  reset  will  disable  the 
interrupt.  INT  can  be  tested  by  issuing  a  conditional  jump 
instruction. 

7 

EA 

External  Access  input  (active-high).  A  logic  "1 "  at  this  input  com- 
mands  the  processor  to  perform  all  program  memory  fetches  from 
external  memory. 

8 

RD 

READ  strobe  outputs  (active-low).  RD  will  pulse  low  when  the  pro- 
cessor performs  a  BUS  READ.  RD  will  also  enable  data  onto  the 
processor  BUS  from  a  peripheral  device  and  function  as  a  READ 
STROBE  for  external  DATA  MEMORY. 

9 

PSEN 

Procjram  Store  Enable  output  (active-low).  PSEN  becomes  active 
only  during  an  external  memory  fetch. 

10 

WR 

WRITE  strobe  output  (active-low).  WR  will  pulse  low  when  the  pro- 
cessor performs  a  BUS  WRITE.  WR  can  also  function  as  a  WRITE 
STROBE  for  external  DATA  MEMORY. 

11 

ALE 

Address  Latch  Enable  output  (active-high).  Occurring  once  each 
cycle,  the  falling  edge  of  ALE  latches  the  address  for  external 
memory  or  peripherals.  ALE  can  also  be  used  as  a  clock  output. 

12-19 

Do-D7  BUS 

8-bit,  bidirectional  port.  Synchronous  reads  and  writes  can  be  per- 
formed  on  this  port  using  RD  and  WR  strobes.  The  contents  of  the 
D0-D7  BUS  can  be  latched  in  a  static  mode. 
During  an  external  memory  fetch,  the  DQ=DLBUS  holds  the  least 
significant  bits  of  the  program  counter.  PSEN  controls  the  incom- 
ing addressed  instruction.  Also,  for  an  external  RAM  data  store 
insiruciion  ine  Uq—Uj  duo,  conxruiiea  Dy  al.c,  nu  ana  wn,  con- 
tains  address  and  data  information. 

20 

Vss 

Processor's  GROUND  potential. 

21-24, 
35-38 

PORT  2 

Port  2  is  the  second  of  two  8-bit  quasi-bidirectional  ports.  For 
external  data  memory  fetches,  the  four  most  significant  bits  of 
the  program  counter  are  contained  in  P2<j-p23- Bits  p20-p23  are 
also  used  as  a  4-bit  I/O  bus  for  the  (xPD8243,  INPUT/OUTPUT 
EXPANDER. 

25 

PROG 

PROG  is  used  as  an  output  strobe  for  jxPD8243s  during  I/O  expan- 
sion. When  the  (xPD8049H  is  used  in  a  stand-alone  mode  the 
PROG  pan  can  be  allowed  to  float. 

26 

Vdd 

VDD  is  used  to  provide  +  5V  to  the  128  x  8-bit  RAM  section  During 
normal  operation  Vcc  must  also  be  +  5V  to  provide  power  to  the 
other  functions  in  the  device.  During  stand-by  operation  VDD  must 
remain  at  +  5V  while  Vcc  is  at  ground  potential. 

27-34 

PiorPi7: 
PORT  1 

Port  1  is  one  of  two  8-bit  quasi-bidirectional  ports 

39 

T1 

Testable  input  using  conditional  transfer  functions  JT1  and  JNT1. 
T1  can  be  made  the  counter/timer  input  using  the  STRT  CNT 
instruction. 

40 

VCC 

Primary  Power  supply.  Vcc  is  +  5V  during  normal  operation 

4-119 


|jlPD8049H/8749H/8039HL 


Functional  Description 

The  NEC  lcPD8049H,  fxPD8749H  and  the  LtPD8039HL  are 
high  performance,  single  component,  8-bit  parallel  microcom- 
puters using  H-channel  silicon  gate  MOS  technology.  The 
|jlPD8049H  family  functions  efficiently  in  control  as  well  as 
arithmetic  applications.  The  powerful  instruction  set  eases  bit 
handling  applications  and  provides  facilities  for  binary  and 
BCD  arithmetic.  Standard  logic  functions  implementation  is 
facilitated  by  the  large  variety  of  branch  and  table  look-up 
instructions. 

The  instruction  set  is  comprised  of  1  and  2  byte  instructions, 
most  of  which  are  single-byte.  The  instruction  set  requires 
only  1  or  2  cycles  per  instruction  with  over  50  percent  of  the 
instructions  single-cycle. 

The  |xPD8049H  family  of  microprocessors  will  function  as 
stand-alone  microcomputers.  Their  functions  can  easily  be 
expanded  using  standard  8080A/8085A  peripherals  and 
memories. 


The  |xPD8049H  contains  the  following  functions  usually  found 
in  external  peripheral  devices:  2048  x  8  bits  of  mask  ROM 
program  memory;  128  x  8  bits  of  RAM  data  memory;  27  I/O 
lines;  an  8-bit  interval  timer/event  counter;  and  oscillator  and 
clock  circuitry. 

The  |xPD8749H  differs  from  the  |jlPD8049H  in  its  2048  x  8-bit 
UV  erasable  EPROM  program  memory  instead  of  the  mask 
ROM  memory.  It  is  useful  in  preproduction  or  prototype 
applications  where  the  software  design  has  not  yet  been  final- 
ized or  in  system  designs  whose  quantities  do  not  require  a 
mask  ROM. 

The  fxPD8039HL  is  intended  for  applications  using  external 
program  memory  only.  It  contains  all  the  features  of  the 
|ulPD8049H  except  for  the  internal  ROM.  The  external  pro- 
gram memory  can  be  implemented  using  standard 
8080A/8085A  memory  products. 


Block  Diagram 


Power  Supply 


1  *VDD  |VCC  fVss 
Program  +5V  Ground 
Supply    (Low  Power 


Expansion  to  Additional 
External  Memory  and  I/O 


INT 

Control  and  Timing 

  XTAL  XTAL 

RESET      PROG       EA           1  2 

ALE 

PSEN 

SS 

RD  WR 

1 

Interrupt 

I 

Initialize 

PROM/E 

Str< 

t 

CPU/Memory 
Separate 
xpander  Oi 
Dbe  ( 

cillat 
Jrystt 

or/ 
H 

\ 

Address 
Latch 

Strobe/ 
Cycle 
Clock 

i. 

Memory 
Enable 

I 

Single 
Step 

II 

Read  Write 
Strobes 

Resident  Data  Memory — RAM 
(128x8) 


Note:  |xPD8039H  does  not  include  ROM. 


4-120 


MPD8049H  8749H  8039HL 


Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

0°Cto  +70°C 

Storage  Temperature  (Ceramic  Package) 

-65°Cto  +150°C 

Storage  Temperature  (Plastic  Package) 

-65°Cto  +  150°C 

Voltage  on  Any  Pin 

-0.5V  to  +7V© 

Power  Dissipation 

1.5W 

Note:  ©  With  respect  to  ground. 

*COMMENT:  Exposing  the  device  to  stresses  above  those 
listed  in  Absolute  Maximum  Ratings  could  cause  permanent 
damage.  The  device  is  not  meant  to  be  operated  under 
conditions  outside  the  limits  described  in  the  operational 
sections  of  this  specification.  Exposure  to  absolute  max- 
imum rating  conditions  for  extended  periods  may  affect 
device  reliability. 


DC  Characteristics 

Ta  =  Q°Cto  +70°C;  Vcc  =  Vpp  =  +5V  ±  10%;  Vss  =  0V 


Limits 

Parameter 

Symbol 

Min   Typ  Max 

Unit 

Test  Conditions 

Input  Low  Voltage 

(All  Except  XTAL 1,  XTAL  2) 

VlL 

-0.5  0.8 

V 

Input  High  Voltage 

(All  Except  XTAL  1,  XTAL  2,  RESET) 

2.0  Vcc 

V 

Input  High  Voltage 
(RESET,  XTAL  1 ,  XTAL  2) 

V,H1 

3.8  Vcc 

V 

Output  Low  Voltage  (BUS,  RD, 
WR,  PSEN,  ALE) 

Vol 

0.45 

V 

l0L  =  2.0  mA 

Output  Low  Voltage  (All  Other 
Outputs  Except  PROG) 

V0L1 

0.45 

V 

Iql  =  2.0  mA 

Output  Low  Voltage  (PROG) 

V0L2 

0.45 

V 

l0L  =  2.0  mA 

Output  High  Voltage  (BUS) 

V0H 

2.4 

V 

l0H  =  -400JXA 

Output  High  Voltage  (RD, 
WR,  PSEN,  ALE) 

V0H1 

2.4 

V 

l0H  =  -400JJLA 

Output  High  Voltage  (All 
Other  Outputs) 

V0H2 

2.4 

V 

l0H  =  "40^ 

Input  Leakage  Current 
(T1(EA,lr4T) 

I.L 

±10 

^A 

VSs^VIN^Vcc 

Input  Leakage  Current 
P10-17,P20-27,EA,SS 

I.L1 

-500 

HA 

Vss  +  .45^V1N=s 
Vcc 

Output  Leakage  Current 

(BUS,  T0  —  High  Impedance  State) 

'OL 

±10 

HA 

Vcc>VINs=Vss  + 
0.45V 

Power  Down  Supply  Current 

'dd 

5  10 

mA 

Ta  =  25°C 

Total  Supply  Current 

'dd  + 
'cc 

80  110 

mA 

Ta  =  25°C 

DC  Characteristics  for  Programming 

Ta  =  25°C  ±  5°C;  Vcc  =  +5V  ±  5%;  VDD  =  +21V  ±  0.5V 

Limits 

Parameter 

Symbol 

Min   Typ  Max 

Unit 

Test  Conditions 

VDD  Program  Voltage  High  Level 

Vddh 

20.5  21.5 

V 

VDD  Voltage  Low  Level 

VDDL 

4.75  5.25 

V 

PROG  Program  Voltage  High  Level 

VpH 

17.5  18.5 

V 

PROG  Voltage  Low  Level 

VPL 

4.0 

V 

EA  Program  or  Verity  Voltage 
High  Level 

VEAH 

17.5  18.5 

V 

VDD  High  Voltage  Supply  Current 

'dd 

20.0 

mA 

PROG  High  Voltage  Supply  Current 

•prog 

1.0 

mA 

EA  High  Voltage  Supply  Current 

'ea 

1.0 

mA 

AC  Characteristics 

Ta  =  0°C  to  +70°C,  Vcc  =  Vpp  =  5V  ±  10%,  Vss  =  OV 


Limits 

f(tCY)  and  Test 
Conditions 

Parameter 

Symbol 

Min 

Typ 

Max 

Unit 

ale  Kuise  wicnn 

*LL 

f/MJ  I(jy      1  f  U 

hoot  oeiup  IO  ML.C 

Ial 

— ^70~ 

2/15tcY  —110 

Arirlr  Unlrl  fmm  Al  P 
MQOr  nOIQ  TlUIII  ALE 

lLA 

 50~ 

IMC  *        —  At) 

ooniroi  iUisc  wiuiri  \nu,  wnj 

*CC1 

— 480~ 

1/2  tpy  —  200 

Pnnknl  Di  ilea  UJlfttki  /DCEkl\ 

tcC2 

— 350~ 

2/5  t@Y  —  200 

Data  Setup  before  WR 

*DW 

1 0/  <3U  \q  y  *w 

rtata  UaM  fiftnr  U/D 

uaia  noio  aner  wn 

*WD 

l/io  icy  (jy 

Hats  Ulnlrl  /DH  DCEM\ 

*DR 

— ^o~ 

Tio~ 

1/Int_   — *jn 

RD  to  Data  in 

*RD1 

2/c  *    ,  _  9f|f| 

£JO  iQY    —  £UU 

PSEN  to  Data  in 

*RD2 

31  1 U  Iqy  fcW 

Addr  Setup  to  WR 

*AW 

— 300~ 

1  /3 1@  y  ~  "1 50 

Addr  Setup  to  Data  (RD) 

*AD1 

~750~ 

I  1/  IO  I^y  *»Dv 

Addr  Setup  to  Data  (PSEN) 

*AD2 

lio" 

11/1 K  t      _  4cn 
Ol  1 0  I(jy  *w 

Addr  Float  to  RD,  WR 

Wei 

 140~ 



2/15  t^Y  40 

Addr  Float  to  PSEN 

Wc2 

— 10~ 

l/OU  Iqy  —  ^* 

ALE  to  Control  (RD.WR) 

lLAFC1 

— 200~ 

1  /5  t@Y  —  75 

ALE  to  Control  (PSEN) 

*LAFC2 

50 

1/10  t^Y  —  75 

Control  to  ALE  (RD,WR,  PROG)  tCA1 

1/15  tpY  —40 

Control  to  ALE  (PSEN) 

*CA2 

— 320~ 

AM C         —  Ah 

Port  Control  Setup  to  PROG 

tCP 

— ioo~ 

l/iu  ipY  w 

Port  Control  Hold  to  PROG 

tpC 

 160~ 

~~ ns — 

AH  K  ♦     _  onn 

*f / 1 0  Iqy  —  fcUU 

PROG  to  P2  Input  Valid 

*PR 

550 

17/30  tCY  -120 

Input  Data  Hold  from  PROG 

tpF 

0 

140 

ns 

1/10  tCY 

Output  Data  Setup 

tDP 

400 

ns 

2/5  tCY  -150 

Output  Data  Hold 

tpD 

90 

ns 

1/10  tCY  -50 

PROG  Pulse  Width 

tpp 

700 

ns 

7/10  tCY  -250 

Port  2  I/O  Setup  to  ALE 

tpL 

180 

ns 

4/15tCY  -200 

Port  2  I/O  Hold  to  ALE 

tu» 

40 

ns 

1/10  tCY  -100 

Port  Output  from  ALE 

tpV 

510 

ns 

3/10  tCY  -100 

Cycle  Time 

tCY 

1.36 

(JiS 

11  MHz 

I/O  Rep  Rate 

lOPRR 

270 

ns 

3/15  tCY 

Notes:  ©  Control  Outputs  CL  =  60pF 
BUS  Outputs  CL  =  150pF 
©  BUS  High  Impedance  Load  20pF 

©  Calculated  values  will  be  equal  to  or  better  than  published  8049  values. 


AC  Characteristics  for  Programming 

Ta  =  25°C  ±  5°C;  Vcc  =  +5V  ±  5%;  VPD  =  +21V  ±  0.5V 


Limits 

Parameter  S 

lymbol 

Min  Typ 

Max 

Unit     Test  Conditions 

Address  Setup  Time  to 
RESET  f 

*AW 

4tCY 

Address  Hold  Time  After 
RESET  f 

*WA 

4tCY 

Data  in  Setup  Time  to  PROG  f 

*DW 

4tCY 

Data  in  Hold  Time  After 
PROG  I 

*WD 

4tCY 

RESET  Hold  Time  to  Verify 

tpH 

4tCY 

VDD 

tVDDW 

0 

1.0 

ms 

VDD  Hold  Time  After  PROG  I 

*VDDH 

0 

1.0 

ms 

Program  Pulse  Width 

W 

50 

60 

ms 

Test  O  Setup  Time  for 
Program  Mode 

*TW 

4tCY 

Test  O  Hold  Time  After 
Program  Mode 

*WT 

4tCY 

Test  O  to  Data  Out  Delay 

tDo 

4tCY 

RESET  Pulse  Width  to  Latch 
Address 

*WW 

4tCY 

VDD  and  PROG  Rise  and  Fall 
Times 

trt, 

0.5 

100 

(JLS 

CPU  Operation  Cycle  Time 

tCY 

4.0 

15 

(XS 

RESET  Setup  Time  before  EA  t 

tRE 

4tCY 

Notes:  ©  Control  Outputs  CL  =  60pF 
BUS  Outputs  CL  =  150pF 
©  BUS  High  Impedance  Load  20pF 

©  Calculated  values  will  be  equal  to  or  better  than  published  8049  values. 


4-121 


,jPD8049H8749H8039HL 

Timing  Waveforms 

Instruction  Fetch  from  External  Memory 

t_ — c  j 


ALE   r 


— H  lAFC2  k-tcCZ  -«4«-tCA2-J 


1- 


    1  -JtpnU.  

BUS  Floating) Cy*    X  Floating"^    ^    X    Floating  )( 


RD2|  Instruction 


Read  from  External  Data  Memory 


H             "  1 

1 

L 

|*-tl_AFC1  "*"h— tcC1— *|*tCA1*- 

Address  I 

  \    -*\  Wei  K-  — H    h—  *i 

Bus  F'oatingY  \  "X  Floating  )fDala"X 


-tAi 


Floating 


BUS  Output  Low  Voltage  vs.  Sink  Current 


OV  2V  4V 

Voh 


Write  to  External  Memory 

ALE         I  1 


J  L 


WR 


Bus  Floating )(   \     ^Floating  )f  Data  )(~ Floating 


Port  2  Timing 

ALE   /  N 


Expander  _ 
Port 
Output  " 

Expander 
Port 
Input 


nder    l-tpt-  'lpK-  h^2£^j,PH»- 

Port  IXI^D^EE?^^E)&3C 


Waveforms  for  Programming  the  H.PD8749H 


DB0-DB7^_. 


/         Data  To  Be 


Programmed  Valid 


(0-7)  V 


—VERIFY  —4-  PROGRAM— 


a  r 


Data  Next  Address 
— *do-H  Valid 


— *do-H  Valid  Valid 

>-<z>cn>-<^yzz 


*VDDW  ~* 


Address  (8-9)  Valid 


'VODH 


"^X  Next  Address 


two 


"  ov  ^- 


Program/Verify  Timing  (ROM/EPROM) 

T0 


DB0-DB7 


\  .       /     Data  Out  V. 

Address  (0-7)Valid  Valid 


--<       *       X    1      >—^Next  Address^ 


_J    Next  Data  \ 
Out  Valid 


Port  P1  &  P2  Output  High  Voltage  vs.  Source  Current 


lOHZ 


100  mA 


Vcc  =  ' 

Typ 

\ 

0V  2V  4V 

VqHz 


BUS  Output  High  Voltage  vs.  Source  Current 


Typ 

f 

VCC  =  4 

0V  1V  2V 

Vol 


4-122 


MPD8049H/8749H8039HL 


Symbol  Definitions 


Symbol  Description 

A 

The  Accumulator 

AC 

The  Auxiliary  Carry  Flag 

addr        Program  Memory  Address  (1 2  bits) 

Bb 

Bit  Designator  (b  =  0  -  7) 

BS         The  Bank  Switch 

BUS 

The  BUS  Port 

C 

Carry  Flag 

CLK 

Clock  Signal 

CNT 

Event  Counter 

D 

Nibble  Designator  (4  bits) 

data        Number  of  Expression  (8  bits) 

DBF        Memory  Bank  Flip-Flop 

F0.F1 

Flags  0,1 

1  Interrupt 

P 

"In-Page"  Operation  Designator 

Port  Designator  (p  =  1, 2  or  4  -  7) 

PSW 

Program  Status  Word 

Rr 

Register  Designator  (r  =  0, 1  or  0  -  7) 

SP         Stack  Pointer 

T 

Timer 

TF 

Timer  Flag 

T„,  IN 

Testable  Flags  0, 1 

X 

External  RAM 

Prefix  for  Immediate  Data 

@         Prefix  for  Indirect  Address 

$ 

Program  Counter's  Current  Value 

(x) 

Contents  of  External  RAM  Location 

«x)) 

Contents  of  Memory  Location  Addressed 

by  the  Contents  of  External  RAM  Location 

Replaced  By 

Logic  Symbol 


Reset 

Single 
Step 
External 
Memory 


8049H/ 
8749H/ 


^Portl 
»  Port  2 
►Read 
►  Write 


_  Program  Store 
Enable 


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4-123 


lxPD8049H/8749H/8039HL 


Instruction  Set 


Mnemonic 

Function 

Description 

D7 

I>6 

Instruction  Code 
D5     D4     D3  D2 

Do 

Flags 

Cycles     Bytes  C    AC    FO  F1 

Accumulator 

ADDA,  =  data 

(A)  «-  (A)  +  data 

Add  Immediate  the  specified  Data  to  the 
Accumulator. 

0 

d7 

0 
d6 

0 
d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

2             2  • 

ADD  A,  Rr 

(A)*- (A)  +  (Rr) 
forr  =  0-7 

Add  contents  of  designated  register  to 
the  Accumulator. 

0 

1 

1 

0 

1 

r 

r 

Add  A,  @  Rr 

(A)^-(A)  +  ((Rr)) 
forr  =  0-1 

Add  Indirect  the  contents  of  the  data 
memory  location  to  the  Accumulator. 

0 

1 

1 

0 

0 

0 

0 

ADDC  A,  =  data 

(A)^(A)  +  (C)  +  data 

Add  Immediate  with  carry  the  specified 
data  to  the  Accumulator. 

0 

d7 

0 
d6 

0 

d5 

1 

d4 

0 
d3 

0 
d2 

1 

di 

2             2  • 

ADDC  A,  Rr 

(A)^(A)  +  (C)  +  (Rr) 
forr  =  0-7 

Add  with  carry  the  contents  of  the 
designated  register  to  the  Accumulator. 

0 

1 

1 

1 

1 

r 

r 

1       1  . 

ADDC  A,  (5  Rr 

<A)«-(A)  +  (C)  +  ((Rr)) 
forr  =  0-1 

Add  Indirect  with  carry  the  contents  of 
data  memory  location  to  the  Accumulator. 

0 

1 

1 

1 

0 

0 

0 

1       1  . 

ANLA,  =  data 

(A)  *-  (A)  AND  data 

Logical  and  specified  Immediate  Data 
with  Accumulator. 

0 
d7 

1 

d6 

0 
d5 

1 

d« 

0 
d3 

0 
d2 

1 

di 

do 

ANLA,  Rr 

(A)  *—  (A)  AND  (Rr) 
for  r  =  0  -  7 

Logical  and  contents  of  designated 
register  with  Accumulator. 

0 

1 

0 

1 

1 

r 

r 

ANL  A,  @  Rr 

(A)*-(A)AND((Rr)) 
forr  =  0-  1 

Logical  and  Indirect  the  contents  of  data 
memory  with  Accumulator. 

0 

1 

0 

1 

0 

0 

0 

CPL  A 

(A)  «-  NOT  (A) 

Complement  the  contents  of  the 
Accumulator. 

0 

0 

1 

1 

0 

1 

1 

CLR  A 

<A)«-0 

CLEAR  the  contents  of  the  Accumulator. 

0 

0 

1 

0 

0 

1 

1 

DA  A 

DECIMAL  ADJUST  the  contents  of  the 
Accumulator. 

0 

1 

0 

1 

0 

1 

1 

1 

1             1  • 

DEC  A 

(A)*-(A)1 

DECREMENT  by  1  the  Accumulator's 
contents. 

0 

0 

0 

0 

0 

1 

1 

INC  A 

(A)«-(A)  +  1 

Increment  by  1  the  Accumulator's 
contents. 

0 

0 

0 

1 

0 

1 

1 

1 

1  1 

ORL  A,  =  data 

(A) «-  (A)  OR  data 

Logical  OR  specified  immediate  data 
with  Accumulator. 

0 
d7 

1 

d6 

0 
d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

ORL  A,  Rr 

(A)<-(A)OR(Rr) 
for  r  =  0  -  7 

Logical  OR  contents  of  designated 
register  with  Accumulator. 

o 

1 

o 

o 

1 

ORL  A,  @  Rr 

(A)«-(A)OR((RD) 
for  r  =  0  -  1 

Logical  OR  Indirect  the  contents  of  data 
memory  location  with  Accumulator. 

o 

1 

o 

o 

o 

0 

0 

RL  A 

(AN  +  1)^(AN) 
(A«)*-(A7) 
f  or  N  =  0  -  6 

Rotate  Accumulator  left  by  1  -bit  without 
carry. 

1 

1 

1 

0 

0 

1 

1 

1 

1  1 

RLC  A 

(AN  +  1)^(AN);N  =  0-6 

(Ao)-(C) 

(C)*-(A7) 

Rotate  Accumulator  left  by  1-bit  through 
carry. 

1 

1 

1 

1 

0 

1 

1 

1             1  • 

RR  A 

(AN) «- (AN  +  1);N  =  0  -  6 
(A7)-(Ao) 

Rotate  Accumulator  right  by  1-bit 
without  carry 

0 

1 

1 

1 

0 

1 

1 

RRC  A 

(AN)<-(AN  +  1);N  =  0-6 

(A7)-(C) 

(C)-(A„) 

Rotate  Accumulator  right  by  1-bit 
through  carry. 

0 

1 

1 

0 

0 

1 

1 

1             1  • 

SWAP  A 

(A4-7)<-(Ao-3) 

Swap  the  2  4-bit  nibbles  in  the 
Accumulator. 

0 

1 

0 

0 

0 

1 

1 

XRL  A,  =  data 

(A)*- (A)  XOR  data 

Logical  XOR  specified  immediate  data 
with  Accumulator. 

1 

d7 

1 

d6 

0 

d5 

1 

d4 

0 

d3 

0 

d2 

1 

XRL  A,  Rr 

(A)^(A)XOR(Rr) 
for  r  =  0  -  7 

Logical  XOR  contents  of  designated 
register  with  Accumulator 

1 

1 

0 

1 

1 

r 

XRL  A,  @  Rr 

(A)«-(A)XOR((Rr)) 
for  r  =  0  -  1 

Logical  XOR  Indirect  the  contents  of  data 
memory  location  with  Accumulator. 

1 

1 

0 

1 

0 

0 

0 

Branch 

DJNZ  Rr,  addr 

(Rr)«-(Rr)-  1;r  =  0-  7 
if  (Rr)  *  0: 
(PC0  -  7)*-  addr 

Decrement  the  specified  register  and 
test  contents. 

1 

a? 

1 

a6 

1 

as 

0 
a4 

1 

a3 

r 

a2 

r 

»1 

a0 

2  2 

JBb  addr 

(PC0  -  7)<-addrifBb  =  1 
(PC)*-(PC)  +  2ifBb  =  0 

Jump  to  specified  address  if  Accumulator 
bit  is  set. 

b2 
a? 

bi 
a6 

bo 
a5 

1 

a4 

0 
a3 

0 
a2 

1 

ai 

0 
a0 

2  2 

JC  addr 

(PC0  -  7) «- addr  if  C  =  1 
(PC)^-(PC)  +  2ifC  =  0 

Jump  to  specified  address  if  carry  flag 
is  set. 

1 

a7 

1 

a6 

1 

a5 

1 

a4 

0 

a3 

1 

a2 

1 

»1 

0 

a0 

2  2 

JFOaddr 

(PC0  -  7)<-addrif  F0  =  1 
(PC)«-(PC)  +  2  if  F0  =  0 

Jump  to  specified  address  if  Flag  F0  is 
set. 

1 

a7 

0 

a6 

1 

a5 

1 

a4 

0 
a3 

1 

a2 

1 

»1 

0 

a0 

2  2 

JF1  addr 

(PC0  -  7)<-addrifF1  =  1 
(PC)*- (PC)  +  2ifF1  =0 

Jump  to  specified  address  if  Flag  F1  is 

set. 

0 

a7 

1 

a6 

1 

a5 

1 

a4 

0 

a3 

1 

a2 

1 

»1 

0 
a0 

2  2 

JMPaddr 

(PC  8  -  10)*- addr 8  -  10 
(PC0-7)«-addr0-7 
(PC  11)^  DBF 

Direct  Jump  to  specified  address  within 
the  2K  address  block. 

■io 

a7 

a9 
a6 

a8 
a5 

0 

a4 

0 

a3 

1 

a2 

0 
«1 

0 

a0 

2  2 

JMPP@A 

(PC  0  —  7)*-  ((A)) 

Jump  indirect  to  specified  address  with 
address  page. 

1 

0 

1 

1 

0 

0 

1 

1 

2  1 

JNC  addr 

(PC0  -  7)*- addr  if  C  =  0 
(PC)^(PC)  +  2ifC  =  1 

Jump  to  specified  address  if  carry  flag 
is  low. 

1 

a7 

1 

a6 

1 

a5 

0 

a4 

0 
a3 

1 

a2 

1 

ai 

0 

a0 

2  2 

JNI  addr 

(PC0  -  7)^  addr  if  I  =  0 
(PC)*- (PC)  +  2  if  I  =  1 

Jump  to  specified  address  if  interrupt 
is  low. 

1 

a7 

0 
a6 

0 

a5 

0 

a4 

0 

as 

1 

a2 

1 

a1 

0 

a0 

2  2 

4-124 


MPD8049H8749H8039HL 


Instruction  Set  (Cont.) 


Mnemonic 

Function 

Description  D7 

«>6 

Instruction  Code 
D5     D4     D3  D2 

i>1 

Do 

Cycles     Bytes  C 

Flags 
AC  FO 

F1 

Branch  (Cont.) 

JNTOaddr 

(PCO  -  7)  —  addr  if  TO  =  0 
(PC)  — (PC)  +  2ifT0  =  1 

Jump  to  specified  address  if  Test  0  is  low.  0 
a? 

0 
a6 

1 

a5 

0 

a4 

0 

a3 

a2 

0 

a0 

2  2 

JNT1 addr 

(PC 0 -7) -addr if  T1  =0 
(PC) -(PC)  +  2ifT1  =  1 

Jump  to  specified  address  if  Test  1  is  low.  0 

a7 

1 

a6 

0 

a5 

0 

a4 

0 

a3 

0 

a0 

2  2 

JNZ  addr 

(PCO  -  7)  —  addr  if  A  *  0 
(PC) -(PC)  +  2  if  A  =  0 

Jump  to  specified  address  if  Accumulator  1 
is  non-zero.  a7 

0 

a6 

0 
a5 

1 

a4 

0 
a3 

0 

a0 

2  2 

JTF  addr 

(PCO  -  7) -addr if  TF  =  1 
(PC)-(PC)  +  2ifTF  =  0 

Jump  to  specified  address  if  Timer  Flag  is  0 
set  to  1.  a7 

0 

a6 

0 

a5 

1 

a4 

0 
a3 

a2 

0 

a0 

2  2 

JTOaddr 

(PCO  -  7)—  addrifTO  =  1 
(PC)  -  (PC) +  2  if  TO  =  0 

Jump  to  specif  led  address  if  Test  0  is  a  1.  0 
a7 

0 

a6 

1 

a5 

1 

a4 

0 

a3 

0 
a0 

2  2 

JT1  addr 

(PCO  -  7)— addr  if  T1  =  1 
(PC)  — (PC)  +  2  if  T1  =  0 

Jump  to  specified  address  if  Test  1  is  a  1 .  0 

a7 

1 

a6 

0 

a5 

1 

a4 

0 

a3 

a2 

0 
a0 

2  2 

JZaddr 

(PCO  -7)  — addr  if  A  =  0 
(PC)-(PC)  +  2ifA  =  0 

Jump  to  specified  address  if  Accumulator  1 
is  0.  a7 

1 

a6 

0 

a5 

0 
a4 

0 

a3 

a1 

0 
a0 

2  2 

Control 

EN  I 

Enable  the  External  Interrupt  input.  0 

0 

0 

0 

0 

0 

1  1 

DISI 

Disable  the  External  Interrupt  input.  0 

0 

0 

1 

0 

0 

1  1 

ENTOCLK 

Enable  the  Clock  Output  pin  TO.  0 

1 

1 

1 

0 

0 

1  1 

SEL  MBO 

(DBF)-0 

Select  Bank  0  (locations  0  -  2047)  of  1 
Program  Memory. 

1 

1 

0 

0 

0 

1  1 

SEL  MB1 

(DBF)  - 1 

Select  Bank  1  (locations  2048  -  4095)  of  1 
Program  Memory 

1 

1 

1 

0 

0 

1  1 

SEL  RBO 

(BS)  —  0 

Select  Bank  0  (locations  0-7)  of  1 
Data  Memory. 

1 

0 

0 

0 

0 

1  1 

SEL  RB1 

(BS)-1 

Select  Bank  1  (locations  24  -  31 )  of  1 
Data  Memory. 

1 

0 

1 

0 

0 

1  1 

Data  Moves 

MOV  A,  =  data 

(A)  —  data 

Move  Immediate  the  specified  data  into  0 
the  Accumulator.  d7 

0 
d6 

1 

d5 

0 
d4 

0 
d3 

0 
d2 

1 

2  2 

MOV  A,  Rr 

(A)-(Rr);r  =  0-7 

Move  the  contents  of  the  designated  1 
registers  into  the  Accumulator. 

1 

1 

1 

1 

r 

1  1 

MOVA,@Rr 

(A)-((Rr));r  =  0-1 

Move  Indirect  the  contents  of  data  1 
memory  location  into  the  Accumulator. 

1 

1 

1 

0 

0 

0 

1  1 

MOV  A,  PSW 

(A) -(PSW) 

Move  contents  of  the  Program  Status  1 
Word  rnto  the  Accumulator. 

1 

0 

0 

0 

1 

1 

1  1 

MOV  Rr,  =  data 

(Rr)— data;r  =  0-7 

Move  Immediate  the  specified  data  into  1 
the  designated  register  d7 

0 
d6 

1 

d5 

1 

d4 

1 

d3 

r 

d2 

di 

2  2 

MOV  Rr,  A 

(Rr)-(A);r  =  0-7 

Move  Accumulator  Contents  into  the  1 
designated  register. 

0 

1 

0 

1 

r 

r 

1  1 

MOV  @  Rr,  A 

((Rr))-(A);r  =  0-1 

Move  Indirect  Accumulator  Contents  1 
into  data  memory  location. 

0 

1 

0 

0 

0 

0 

1  1 

MOV  @  Rr,  =  data 

((Rr))-data;r  =  0-1 

Move  Immediate  the  specified  data  into  1 
data  memory.  d7 

0 
d6 

1 

1 

d4 

0 
d3 

0 
d2 

0 
di 

2  2 

MOV  PSW,  A 

(PSW) -(A) 

Move  contents  of  Accumulator  into  the  1 
program  status  word. 

1 

0 

1 

0 

1 

1 

1  1 

MOVP  A,  @  A 

(PCO -7) -(A) 
(A) -((PC)) 

Move  data  in  the  current  page  into  the  1 
Accumulator. 

0 

1 

0 

0 

0 

1 

2  1 

MOVP3  A,  @  A 

(PC  0-7) -(A) 
(PC 8  -  10)— 011 
(A) -((PC)) 

Move  Program  data  in  Page  3  into  the  1 
Accumulator. 

1 

1 

0 

0 

0 

1 

2  1 

MOVXA,@R 

(A)-((Rr)),r  =  0-1 

Move  Indirect  the  contents  of  external  1 
data  memory  into  the  Accumulator. 

0 

0 

0 

0 

0 

0 

2  1 

MOVX  @  R,  A 

((Rr))-(A);r  =  0-1 

Move  Indirect  the  contents  of  the  1 
Accumulator  into  external  data  memory. 

0 

0 

1 

0 

0 

0 

2  1 

XCH  A,  Rr 

(A)<=*(Rr);r  =  0-7 

Exchange  the  Accumulator  and  0 
designated  register's  contents. 

0 

1 

0 

1 

1  1 

XCH  A,  @  Rr 

(A)^((Rr));r  =  0-1 

Exchange  indirect  contents  of  Accumu-  0 
lator  and  location  in  data  memory. 

0 

1 

0 

0 

0 

0 

1  1 

XCHD  A,  @  Rr 

(A0-3)^((Rr)(0-3)); 
r  =  0-1 

Exchange  Indirect  4-bit  contents  of  0 
Accumulator  and  data  memory. 

0 

1 

1 

0 

0 

0 

1  1 

Flags 

CPLC 

(C)-NOT(C) 

Complement  content  of  carry  bit.  1 

0 

1 

0 

0 

1 

1             1  • 

CPLFO 

(FO)-NOT(FO) 

Complement  content  of  Flag  F0  1 

0 

0 

1 

0 

0 

1  1 

• 

CPL  F1 

(F1)-NOT(F1) 

Complement  content  of  Flag  F1.  1 

0 

1 

1 

0 

0 

1  1 

• 

CLRC 

(C)-0 

Clear  content  of  carry  bit  to  0.  1 

0 

0 

1 

0 

1 

1             1  • 

CLRFO 

(FO)-0 

Clear  content  of  Flag  0  to  0.  1 

0 

0 

0 

0 

0 

1  1 

• 

CLRF1 

(F1)-0 

Clear  content  of  Flag  1  to  0.  1 

0 

1 

0 

0 

0 

1  1 

• 

4-125 


)xPD8049H/8749H/8039HL 


Instruction  Set  (Cont.) 


Mnemonic 

Function 

Description 

«>7 

l>6 

Instruction  Code 
D5     D4     D3  D2 

«>1 

Do 

Flags 

Cycles     Bytes  C    AC    FO  F1 

Input/Output 

ANL  BUa,  =  aata 

/Dl  IC\  ^_  /Dl  IC\  A  KIR  Hata 
(DUO)  <—  (DUO)  AWU  uaia 

Locjical  and  Irnrnocfiat^spccifiGc!  data 
with  contents  of  BUS. 

i 

d6 

d5 

i 

d°2 

di 

d°o 

ANL  rp,  —  data 

/Dn\       IDn\  A  Kin  rlata 
\"P)  * —  \'P)  AWU  Gala 

p  =  1  -2 

Locjical  and  IrnrnodiatG  specified  ddtd 
with  designated  port  (1  or  2\ 

d4 

d2 

P 
d, 

P 

do 

ANLU  rp,  A 

/Dn\  *  /On\  Akin  (A  (1  .  11 

p  =  4  -  7 

Logical  and  contents  of  Accumulator  with 
designated  port  (4  -  7). 

P 

P 

(A)  <— (Pp),  p  -  1  -  ^ 

Input  data  from  designated  port  (1  2) 
into  Accumulator 

P 

P 

IKIC  A    Dl  IC 

INo  A,  duo 

/A\  ^_  /Dl  IC\ 
(A)  <—  (BUS)) 

Input  strobed  BUS  data  into  Accumulator- 

MOVD  A,  Pp 

(A0-3)-(Pp);p  =  4-7 

Move  contents  of  designated  port  (4  -  7) 
into  Accumulator. 

0 

0 

0 

0 

1 

1 

P 

P 

2  1 

MOVD  Pp,  A 

(Pp)^AO  -  3;p  =  4  -  7 

Move  contents  of  Accumulator  to 
designated  port  (4-7). 

0 

0 

1 

1 

1 

1 

P 

P 

1  1 

ORL  BUS,  =  data 

(BUS)-  (BUS)  OR  data 

Logical  or  Immediate  specified  data  with 
contents  of  BUS. 

1 

d7 

0 

0 

0 
d4 

1 

0 

d2 

0 
di 

0 
do 

2  2 

ORLD  Pp,  A 

(Pp)^(Pp)OR(A0-3) 
p  =  4  -  7 

Logical  or  contents  of  Accumulator  with 
designated  port  (4  -  7). 

1 

0 

0 

0 

1 

1 

P 

P 

1  1 

ORL  Pp,  =  data 

(Pp)^(Pp)ORdata 
p  =  1  -2 

Logical  or  Immediate  specified  data  with 
designated  port  (1  -  2). 

1 

d7 

0 
d6 

0 

0 

1 

0 

d2 

P 

di 

P 
do 

2  2 

OUTL  BUS,  A  © 

(BUS)<-(A) 

Output  contents  of  Accumulator  onto 
BUS 

0 

0 

0 

0 

0 

0 

1 

0 

1  1 

OUTL  Pp,  A 

(Pp)-(A);p  =  1  -2 

Output  contents  of  Accumulator  to 
designated  port  (1  -  2). 

0 

0 

1 

1 

1 

0 

P 

P 

1  1 

Registers 

DEC  Rr,  (Rr) 

(Rr)^-(Rr)-1;r  =  0-7 

Decrement  by  1  contents  of  designated 
register. 

1 

1 

0 

0 

1 

r 

r 

1  1 

INC  Rr 

(Rr)«-(Rr)  +  1;r  =  0  -  7 

Increment  by  1  contents  of  designated 
register 

0 

0 

0 

1 

1 

r 

r 

r 

1  1 

INC  («  Rr 

((Rr))-((Rr))  +  1; 
r  =  0  -  1 

Increment  Indirect  by  1  the  contents  of 
data  memory  location. 

0 

0 

0 

1 

0 

0 

0 

r 

1  1 

Subroutine 

CALL  addr 

«SP))*-(PC),(PSW4-7) 
(SP)*-(SP)  +  1 
(PC  8  -  10)^- addr  8  -  10 
(PCO  -  7)<-addr0  -  7 
(PC  11)^  DBF 

Call  designated  Subroutine. 

aio 
a7 

ag 
a6 

a8 
a5 

1 

a4 

0 

a3 

1 

a2 

0 

ai 

0 
a0 

2  2 

RET 

(SP)^(SP)  -  1 
(PC)-((SP)) 

Return  from  Subroutine  without 
restoring  Program  Status  Word. 

1 

0 

0 

0 

0 

0 

1 

1 

2  1 

RETR 

(SP)-(SP)-1 
(PC)-((SP)) 
(PSW4  -  7)^((SP» 

Return  from  Subroutine  restoring 
Program  Status  Word. 

1 

0 

0 

1 

0 

0 

1 

1 

2  1 

Timer/Counter 

ENTCNTI 

Enable  Internal  interrupt  Flag  for 
Timer/Counter  output. 

0 

0 

1 

0 

0 

1 

0 

1 

1  1 

DIS  TCNTI 

Disable  Internal  interrupt  Flag  for 
Timer/Counter  output 

0 

0 

1 

1 

0 

1 

0 

1 

1  1 

MOVA,T 

(A)-(T) 

Move  contents  of  Timer/Counter  into 
Accumulator. 

0 

1 

0 

0 

0 

0 

1 

0 

1  1 

MOV  T,  A 

(T)-(A) 

Move  contents  of  Accumulator  into 
Timer/Counter. 

0 

1 

1 

0 

0 

0 

1 

0 

1  1 

STOP  TCNT 

Stop  Count  for  Event  Counter. 

0 

1 

1 

0 

0 

1 

0 

1 

1  1 

STRT  CNT 

Start  Count  for  Event  Counter. 

0 

1 

0 

0 

0 

1 

0 

1 

1  1 

STRTT 

Start  Count  for  Timer. 

0 

1 

0 

1 

0 

1 

0 

1 

1  1 

Miscellaneous 

NOP 

No  Operation  performed. 

0 

0 

0 

0 

0 

0 

0 

0 

1  1 

Notes:  ©  Instruction  Code  Designations  r  and  p  form  the  binary  representation  of  the  Registers  and  Ports  involved 

©  The  dot  under  the  appropriate  flag  bit  indicates  that  its  content  is  subject  to  change  by  the  instruction  it  appears  in, 

(D  References  to  the  address  and  data  are  specified  in  bytes  2  and/or  1  of  the  instruction 

©  Numerical  Subscripts  appearing  in  the  FUNCTION  column  reference  the  specific  bits  affected 

©  When  the  Bus  is  written  to,  with  an  OUTL  instruction,  the  Bus  remains  an  Output  Port  until  either  device  is  reset  or  a  MOVX  instruction  is  executed 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  mPD8049HC/39HLC 

Ceramic,  uPD8049HD/39HLD 

Cerdip,  fxPD8749HD,  has  quartz  window 

8049H/8749H/8039HLDS-REV1-7-83-CAT-L 


4-126 


SEC 


|.PD80C49/|PD80C39 
CMOS  8-BIT  SINGLE-CHIP 
MICROCOMPUTER 


Description 

The  NEC  fjiPD80C49  is  a  true  stand-alone  8-bit  micro- 
computer fabricated  using  CMOS  technology.  All  of  the 
functional  blocks  necessary  for  an  integrated  microcom- 
puter are  incorporated,  including  a  2K-byte  ROM,  a 
128-byte  RAM,  27  I/O  lines,  an  8-bit  timer/event  counter, 
and  a  clock  generator.  This  integrated  capability  permits 
use  in  stand-alone  applications.  For  designs  requiring 
extra  capability,  the  |xPD80C49  can  be  expanded  using 
peripherals  and  memory  compatible  with  industry-standard 
8080A/8085A  processors.  A  version  of  the  (jlPD80C48 
without  ROM  is  offered  by  the  ^PD80C39. 
Providing  compatibility  with  industry-standard  8049,  8749, 
and  8039  processors,  the  (jlPD80C49  features  significant 
savings  in  power  consumption.  In  addition  to  the  power 
savings  gained  through  CMOS  technology,  the  |xPD80C49 
is  distinct  in  offering  two  standby  modes  (Halt  mode  and 
Stop  mode)  to  further  minimize  power  drain. 

Features 

□  8-bit  CPU  with  ROM,  RAM,  and  I/O  on  a  single  chip 

□  Hardware/software-compatible  with  industry-standard 
8049,  8749,  and  8039  processors 

□  2K  x  8  ROM 

□  128x8  RAM 

□  27  I/O  lines 

□  1 .875fxs  cycle  time  (8MHz  crystal) 

□  All  instructions  executable  in  1  or  2  cycles 

□  97  instructions:  70  percent  are  single-byte  instructions 

□  Internal  timer/event  counter 

□  2  interrupts  (an  external  interrupt  and  a  timer  interrupt) 

□  Easily  expandable  memory  and  I/O 

□  Bus  compatible  with  8080A/8085A  peripherals 

□  Power-efficient  CMOS  technology  requiring  a  single 
+  2.5V  to  +  6V  power  supply 

□  Available  in  40-pin  DIP,  44-pin  flat  pack  (80C49  only), 
and  52-pin  flat  pack 

□  Halt  mode 

- 1  mA  typical  supply  current 

-  Maintenance  of  internal  logic  values  and  control  states 

-  Mode  initialization  via  HALT  instruction 

-  Mode  release  via  external  interrupt  or  reset 

□  Stop  mode 

- 1  |xA  typical  supply  current 

-  Disabling  of  internal  clock  generation  and 
internal  logic 

-  Maintenance  of  RAM  contents 

-  Mode  initialization  via  hardware  (VDD) 

-  Mode  release  via  reset 


Pin  Identification 


Pin 

No. 

Symbol 

Name 

Function 

1 

TO 

Test  0 

Testable  input  using  conditional  jump  instructions 
JT0  and  JNT0  Also  enables  clock  output  via  the 
ENTO  CLK  instruction. 

2 

XTAL1 

Crystal  1 

One  of  two  inputs  for  external  crystal  oscillator  or 
LC  circuit  to  generate  internal  clock  signals.  May 
also  be  used  as  an  input  for  external  clock  signals 
(Non-TTL-compatible  V^.) 

3 

XTAL2 

Crystal  2 

One  of  two  inputs  for  external  crystal  oscillator  or 
LC  circuit  to  generate  internal  clock  signals  (Non- 
TTL-compatible  V,H  ) 

Active-low  input  line  that  initializes  the  proces- 
sor. Also  used  to  release  both  the  Halt  and  Stop 
modes.® 

5 

SS 

Single  Step 

Active-low  input  line,  that,  in  conjunction  with  ALE, 
causes  the  processor  to  single-step  through  a  pro- 
gram one  instruction  at  a  time 

Interrupt 

Active-low  input  line  that  causes  an  interrupt  if  an 
enable  instruction  has  been  executed  A  reset  dis- 
ables the  interrupt  May  be  used  as  a  testable  input 
with  a  conditional  jump  instruction.  Can  also  be 
used  to  release  the  Halt  mode 

7 

EA 

External 
Access 

Input  line  that  inhibits  internal  program  memory 
fetches  and  initiates  access  of  external  program 
memory.  Essential  for  system  testing  and  may  also 
be  used  for  program  debugging. 

8 

RD 

Read 

Active-low  output  strobe  line  that  is  used  to  read 
data  from  external  data  memory 

9 

PSEN 

Program 
Store  Enable 

Active-low  output  line  that  is  used  to  fetch  instruc- 
tions from  external  program  memory 

10 

WR 

Write 

Active-low  output  .strobe  line  that  is  used  to  write 
data  into  external  data  memory. 

11 

ALE 

Address 
Latch  Enable 

Output  line  for  address  latch  enable  At  the  falling 

memory  or  external  program  memory  is  available 
on  the  bus. 

12-19 

DB0-DB7 

Bus 

These  I/O  lines  constitute  an  8-bit  bidirectional 

data/address  bus  Synchronous  read  and  write  

operations  can  be  performed  on  this  bus  using  RD 
and  WR  signals.  Data  driven  out  on  the  bus  by  an 
OUTL  BUS  instruction  is  statically  latched. 
The  address  of  external  memory  is  available  on  the 
bus  at  the  falling  edge  of  ALE  when  reading  from 
external  program  memory  or  writing  to  and  reading 
from  external  data  memory  During  external  pro- 
gram memory  fetches,  the  least-significant  8  bits  of 
the  external  program  memory  address  are  driven 
out  on  the  bus  and  the  addressed  instruction  is 

used,  the  bus  can  serve  as  a  true  bidirectional  8-bit 
port.  Information  is  strobed  in  or  out  by  the  RD  and 
WR~  signals. 

20 

VSs 

Ground 

Ground  potential. 

21-24, 
35-38 

P20-P27 

Port  2 

These  lines  constitute  Port  2,  an  8-bit  quasi- 
bidirectional  port.  During  external  program 
memory  fetches,  P2o~p23  output  the  most- 
signficant  4  bits  of  the  external  program  mem- 
ory address  Lines  P2o-p23  can  also  De  used 
as  a  4-bit  I/O  expander  bus  to  interface  with 
the  optional  ^PD82C43  I/O  expander 

25 

PROG 

Program 
Pulse 

This  line  is  used  as  an  output  strobe  when  interfac- 
ing with  the  optional  (xPD82C43  I/O  expander. 

26 

vDD 

Oscillator 
Control 
Voltage  Line 

This  input  line  is  used  to  control  oscillator  stopping 
and  restarting  in  Stop  mode.  Stop  mode  is  enabled 
by  forcing  VDD  LOW  during  a  reset. 

27-34 

P10-P17 

Portl 

These  lines  constitute  Port  1,  an  8-bit,  general- 
purpose  quasi-bidirectional  port. 

39 

T1 

Test  1 

Testable  input  using  conditional  jump  instruc- 
tions JT1  and  JNT1.  Can  also  be  used  as  the  timer/ 
counter  input  line  via  the  STRT  CNT  instruction. 

40 

Vcc 

Primary 

Power 

Supply 

Power  supply.  Vcc  must  be  between  +2.5V  to  +6V 
for  normal  operation  In  Stop  mode,  Vcc  must  be  at 
least  +  2V  to  ensure  data  retention. 

Note:  ©  The  pulse  width  of  RESET  must  be  a  minimum  of  5  machine  cycles  in  length  following 

oscillator  stabilization  to  reinitialize  the  processor  and  stabilize  CPU  operation  At  power- 
Rev/1  UP'  ^e  states  °* tne  outPut  'Ines  are  undefined  until  completion  of  reset 


4-127 


PD80C49  80C39 

Pin  Configuration 


TO 
XTAL1 
XTAL2 
RESET 
SS 
INT 
EA 
RD 
PSEN 
WR 
ALE 
DB0 


:  1 

L"  2 
C  3 


C  5 


DB, 


DB, 
DB5 


DB7 

VSs 


32 


(jiPD 
80C49/ 
80C39 


24  D 
23  3 
22  D 
21  3 


Pl7 
Pl6 
Pl5 
Pl4 
3  P,3 

29  3  P12 

28  3  pii 

27  3  P10 

26  3  VDD 

25  3  PROG 


Standby  Function 

HALT  mode 

In  Halt  mode,  the  oscillator  continues  to  operate,  but  the 
internal  clock  is  disabled.  The  status  of  all  internal  logic  just 
prior  to  execution  of  the  HALT  instruction  is  maintained  by 
the  CPU.  In  Halt  mode,  power  consumption  is  less  than 
10  percent  of  normal  lcPD80C49  operation  and  less  than 
1  percent  of  normal  8049  operation. 
The  Halt  mode  is  initiated  by  execution  of  the  HALT 
instruction,  and  is  released  by  either  INT  or  RESET  input. 
INT  input:  When  the  INT  pin  receives  a  low-level  input,  if 
interrupts  are  enabled,  the  internal  clock  is  restarted  and 


the  interrupt  is  executed  after  the  first  or  second  instruction 
following  the  HALT  instruction.  However,  if  interrupts  are 
disabled,  program  operation  is  resumed  from  the  next 
address  following  the  HALT  instruction.  The  first  instruc- 
tion following  a  HALT  instruction  should  be  a  NOP 
instruction  to  ensure  proper  program  execution. 
If  the  Halt  mode  is  released  when  interrupts  are  enabled, 
the  interrupt  service  routine  is  usually  executed  after  the 
first  or  second  instruction  following  the  release  of  Halt 
mode.  However,  if  either  a  timer  or  external  interrupt  is 
accepted  within  one  machine  cycle  prior  to  a  HALT  instruc- 
tion, the  corresponding  timer  or  external  interrupt  service 
routine  is  executed  immediately  following  the  release  of 
Halt  mode.  It  is  important  to  note  this  sequence  of  execu- 
tion when  considering  interrupt  service  routine  execution 
following  a  HALT  instruction. 

RESET  input:  When  a  low-level  input  is  received  by  the 
RESET  pin,  Halt  mode  is  released  and  the  normal  reset 
operation  is  activated,  restarting  program  operation  from 
address  0. 
Stop  mode 

In  Stop  mode,  the  oscillator  is  deactivated  and  only  the 
contents  of  RAM  are  maintained.  The  operation  status 
of  the  |jlPD80C49  resembles  that  of  a  reset  condition. 
Because  only  the  contents  of  RAM  are  maintained,  Stop 
mode  provides  even  lower  power  consumption  than  Halt 

mode,  only  requiring  a  minimum  Vcc  as  low  as  +  2V.  

Stop  mode  is  initiated  by  setting  VDD  to  LOW  when  RESET 
is  LOW,  to  protect  the  contents  of  RAM.  Stop  mode  is 
released  by  first  raising  the  supply  voltage  at  the  Vcc  pin 
from  standby  level  to  correct  operating  level  and  setting 
VDD  to  HIGH  when  RESET  is  LOW.  After  the  oscillator  has 
been  restarted  and  the  oscillation  has  stabilized,  RESET 
must  be  set  to  HIGH,  whereby  program  operation  is  started 
from  address  0. 


Stop  Mode  Circuit 


Voltage 
Regulator 


T 


J 


Notes:  ©  D  flip-flops  must  be  CMOS  (74C74  or  equivalent) 

©  Designated  gates  must  be  CMOS  (74C04  or  equivalent) 


I 


■c  CLEAR  Q 


CLEAR  < 

© 


3  0V  — 
BatteryJ" 


4-128 


Stop  Mode  Timing 

Oscillator  Oscillator 
Stops  Restarts 


t, 

V 

r  111 

5  Machine  Cycles      Oscillation  Stabilization  Time 
Mm 


Stop  Mode  Circuit:  Since  VDD  controls  the  restarting 
of  the  oscillator,  it  is  important  that  VDD  be  protected  from 
noise  interference.  The  time  required  to  reset  the  CPU  is 
represented  by  t,  (see  Stop  Mode  Timing  diagram),  which 
is  a  minimum  of  5  machine  cycles.  The  reset  operation  will 
not  be  completed  in  less  than  5  machine  cycles.  In  Stop 
mode,  it  is  important  to  note  that  if  VDD  goes  LOW  before  5 
machine  cycles  have  elapsed,  the  CPU  will  be  deactivated 
and  the  output  of  ALE,  RD,  WR,  PSEN,  and  PROG  will  not 
have  been  stabilized. 


fxPD80C49/80C39 

Oscillation  stabilization  time  is  represented  by  t2  (see  Stop 
Mode  Timing  diagram).  When  VDD  goes  HIGH,  oscillator 
operation  is  reactivated,  but  it  takes  time  before  oscillation 
can  be  stabilized.  In  particular,  such  high  Q  resonators  as 
crystals  require  longer  periods  to  stabilize.  Because  there 
is  a  delay  between  restarting  of  the  oscillator  and  oscillator 
stabilization,  t2  should  be  long  enough  to  ensure  that  the 
oscillator  has  been  fully  stabilized. 
To  facilitate  Stop  mode  control,  an  external  capacitor  can 
be  connected  to  the  RESET  pin  (see  Stop  Mode  Control 
Circuit),  affecting  only  t2,  allowing  control  of  the  oscillator 
stabilization  time.  When  VDD  is  asserted  in  Stop  mode, 
the  capacitor  begins  charging,  pulling  up  RESET.  When 
RESET  reaches  a  threshold  level  equivalent  to  a  logic  1 , 
Stop  mode  is  released.  The  time  it  takes  RESET  to  reach 
the  threshold  level  of  logic  1  determines  the  oscillator  stabi- 
lization time,  which  is  a  function  of  the  capacitance  and 
pull-up  resistance  values. 


Stop  Mode  Control  Circuit 


Note:  ©  Polarized  electrolytic  capacitor 


—J  jp-channel 


Pull-up 
Resistance 


-|  jrvcl 


zz  © 


Port  Operation 

A  port-loading  option  is  offered  at  the  time  of  ordering  the 
mask.  Individual  source  current  requirements  for  Port  1 
and  the  upper  and  lower  halves  of  Port  2  may  be  factory 
set  at  either  -  5(jlA  or  -  50fxA  (see  Port-Loading  Options 
table).  The  -  50|jlA  option  is  required  for  interfacing  with 
TTL/NMOS  devices.  The  -  5|jlA  option  is  recom- 
mended for  interfacing  to  other  CMOS  devices.  The 
CMOS  option  results  in  lower  power  consumption  and 
greater  noise  immunity. 

Port  lines  P10  to  P17  and  P24  to  P27  include  a  protective 
circuit  "E"  to  prevent  a  signal  conflict  at  the  port.  The  circuit 
prevents  a  logic  1  from  being  written  to  a  line  that  is  being 
pulled  down  externally  (see  Port  Protection  Circuit  "E"  dia- 
gram). When  a  logic  0  is  detected  at  the  port  line  and  a  logic 
1  is  written  from  the  bus,  the  NOR  gate  sends  a  logic  1  to 
the  D  input  of  the  flip-flop.  The  output  is  inverted,  forcing  the 
NAND  gate  to  send  a  high-level  output.  This  turns  off  tran- 
sistor A,  preventing  the  output  of  a  logic  1  from  the  port. 


Port-Loading  Options 

lOH  (min)  Vcc  =  VDD  =  5V  ±  10%;  VOH  =  2.4V  (min) 


Option 

Selected  P10"-P17  P20~P23  P24~P27  Unlt 

A  -5  -5  -5  ijlA 

B  -50  -5  -5  (jlA 

C  -5  -50  -5  i^A 

D  -50  -50  -5  ijlA 

E  -5  -5  -50  ijlA 

F  -50  -5  -50  ixA 

G  -5  -50  -50  m-A 

H  -50  -50  -50  txA 


Notes:  ©  The  selection  of  Iqh  =  -  5^A  will  result  in  a  port  source  current  of  l|LP  =  -  4(VA  max 
when  used  as  input  port 
©  The  selection  of  l0H  =  -50jxA  will  result  in  a  port  source  current  of  l|LP  =  -500(aA 
max  when  used  as  input  port 


4-129 


,lPD80C49/80C39 

Oscillator  Operation 

The  oscillator  maintains  an  internal  frequency  for  clock 
generation  and  controls  all  system  timing  cycles.  The 
oscillation  is  initiated  by  either  a  self-generating  external 
resonator  or  external  clock  input.  The  oscillator  acts  as  a 
high-gain  amplifier  which  produces  square-wave  pulses 
at  the  frequency  determined  by  the  resonator  or  clock 
source  to  which  it  is  connected. 


Port  Protection  Circuit  "E" 


To  obtain  the  oscillation  frequency,  an  external  LC  network 
may  be  connected  to  the  oscillator,  or,  a  ceramic  or  crystal 
external  resonator  may  be  connected. 
As  the  crystal  frequency  is  lowered,  there  is  an  equivalent 
reduction  in  series  resistance  (R).  As  the  temperature  of  the 
crystal  is  lowered,  R  is  increased.  Due  to  this  relationship,  it 
becomes  difficult  to  stabilize  oscillation  when  there  is  low 
power  supply  voltage.  When  Vcc  is  less  than  2.7V  and  the 
oscillator  frequency  is  3MHz  or  less,  Ta  (ambient  tempera- 
ture) should  not  be  less  than  -  10°C. 


Internal_ 
Bus  ~ 


Write 
Pulse  " 


r 


t      Pull-up  Resistance 
J  lp-channel| — j  |p-channel 


1        I  9   n-channel 


41 


1  I 
i 


tz: 


P10-P17 


Crystal  Frequency  Reference  Circuit 


LC  Frequency  Reference  Circuit 


r 


r 

T 


X 


1  "L 


'  2irvTcr 


L  C  Nominal  f 
45MH    20pF  5.2MHz 

12<VH    20pF  3.2MHz 


C  ,  C  t  3CPP 
2 


Notes:  ©  Crystal  oscillator  constants  of  fosc  =  6MHz 
R-nax  =  50X1 
CL  =  16  ±  0  2pF 
P  =  1  ±  0  2mW 
®  Operating  frequency  less  than  4MHz 
0  <     <  20pF 
0  <  C2  s  20pF 
|  C2  -  C1  |  <  10pF 
®  Operating  frequency  more  than  4MHz 
0<C!  <  10pF 
0  <  C2  s  10pF 
|  C2  -  C,  |  s  5pF 


Note:  Cpp  =  5-10pF  Pin  to  pin  capacitance  should  be  approximately  20pF,  including 
stray  capacitance 


4-130 


Ceramic  Resonator  Frequency  Reference  Circuit 


,xPD80C49/80C39 

Major  Input  and  Output  Signals 


I 

'I  i 


r 


Note:  C1  >  C2 

(C,  -  C2)  =  20pF 

For  example,     =  30pF,  and  C2  =  10pF 

Values  of  C,  and  C2  do  not  include  stray  capacitance 


External  Clock  Frequency  Reference  Circuit 


-t>- 


Note:  A  minimum  voltage  of  Vcc-1  is  required  for  XTAL1  to  go  HIGH 


Port  Expander 
Strobe 


Instruction  Set  Symbol  Definitions 


Symbol 

Description 

A 

Accumulator 

AC 

Auxiliary  Carry  Flag 

addr 

Program  or  data  memory  address  (a0-a7)  or  (a0-a10) 

b 

Accumulator  bit  (b  =  0-7) 

BS 

Bank  Switch 

BUS 

Bus 

C 

Carry  Flag 

CLK 

Clock 

CNT 

Counter 

data 

8-bit  binary  data  (d0-d7) 

DBF 

Memory  Bank  Flip-Flop 

FO,  F1 

Flag  0,  Flag  1 

INT 

Interrupt  pin 

n 

Indicates  the  hex  number  of  the  specified  register 

or  port 

PC 

Program  Counter 

Pp 

Port  1 ,  Port  2,  or  Port  4-7  (p  =  1 , 2,  or  4-7) 

PSW 

Program  Status  Word 

Rr 

Register  R0-R7  (r  =  0-7) 

SP 

Stack  Pointer 

T 

Timer 

TF 

Timer  Flag 

TO,  T1 

Test  0,  Test  1  pin 

# 

Immediate  data  indication 

@ 

Indirect  address  indication 

X 

Indicates  the  hex  number  corresponding  to 

the  accumulator  bit  or  page  number  specified 

in  the  operand 

(x) 

Contents  of  RAM 

((x)) 

Contents  of  memory  addressed  by  (x) 

Transfer  direction,  result 

A 

Logical  product  (logical  AND) 

V 

Logical  sum  (logical  OR) 

Exclusive  OR 

  Complement 

4-131 


|PD80C49/80C39 

Instruction  Set 


Instruction  Code 


Mnemonic 

Function 

Description 

Code 

l>7 

D6 

Ds 

D4 

D3 

D2 

Di 

D0    Cycles  Bytes 

Accumulator 

ADD  A,  # 
data 

(A)  -  (A)  +  data 

Adds  immediate  data  d0-d7  to  the  accumulator. 
Sets  or  clears  both  carry  flags.® 

03 

0 

d7 

0 
d6 

0 

d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

1          2  2 

ADD  A,  Rr 

(A)  -  (A)  +  (Rr) 
r  =  0-7 

Adds  the  contents  of  register  Rr  to  the 
accumulator  Sets  or  clears  both  carry  flags.© 

6n@ 

0 

1 

1 

0 

1 

r 

r          1  1 

ADD  A,  @  Rr 

(A)  -  (A)  +  ((Rr)) 
,  =  0-1 

Adds  the  contents  of  the  internal  data  memory 
location  specified  by  bits  0-5  of  register  Rr  to  the 
accumulator.  Sets  or  clears  both  carry  flags.© 

6n© 

0 

1 

1 

0 

0 

0 

0 

r          1  1 

AD  DC  A,  # 

data 

(A) «-  (A)  +  data  +  (C) 

Adds,  with  carry,  immediate  data  d0— d7  to  the 
accumulator.  Sets  or  clears  both  carry  flags.© 

d°7 

d6 

dl 

J4 

dl 

dl 

di 

ADDC  A,  Rr 

(A)-(A)  +  (Rr)  +  (C) 
,  =  0-7 

Adds,  with  carry,  the  contents  of  register  Rr  to  the 
accumulator.  Sets  or  clears  both  carry  flags.© 

7n© 

0 

1 

1 

1 

1 

r 

r 

r          1  1 

ADDC  A, 

@Rr 

(A)-(A)  +  ((Rr))  +  (C) 
r  =  0-1 

Adds,  with  carry,  the  contents  of  the  internal  data 
memory  location  specified  by  bits  0-5  of  register 
Rr,  to  the  accumulator.  Sets  or  clears  both  carry 
flags.® 

7n© 

0 

1 

1 

1 

0 

0 

0 

r          1  1 

ANL  A,  # 
data 

(A)<-(A)Adata 

Takes  the  logical  product  (logical  AND)  of 
immediate  data  d0-d7  and  the  contents  of 
the  accumulator,  and  stores  the  result  in  the 
accumulator. 

53 

0 
d7 

1 

d6 

0 
d5 

1 

d4 

0 

d3 

0 
d2 

1 

di 

1          2  2 

ANL  A,  Rr 

(A)  -  (A)A(Rr) 
r  =  0-7 

Takes  the  logical  product  (logical  AND)  of  the 
contents  of  register  Rr  and  the  accumulator,  and 
stores  the  result  in  the  accumulator. 

5n© 

0 

1 

0 

1 

1 

r 

r 

r          1  1 

ANL  A,  @  Rr 

(A)-(A)A((Rr)) 
r  =  0-1 

Takes  the  logical  product  (logical  AND)  of  the 
contents  of  the  internal  data  memory  location 
specified  by  bits  0-5  of  register  Rr,  and  the 
accumulator,  and  stores  the  result  in  the 
accumulator. 

5n@ 

0 

1 

0 

1 

0 

0 

0 

r          1  1 

CPLA 

(A) -(A) 

Takes  the  complement  of  the  contents  of  the 
accumulator. 

37 

0 

0 

1 

,1 

0 

1 

1 

1          1  1 

CLRA 

(A)-0 

Clears  the  contents  of  the  accumulator. 

27 

0 

0 

1 

0 

0 

1 

1 

1          1  1 

Converts  the  contents  of  the  accumulator  to  BCD 
Sets  or  clears  the  carry  flags.  When  the  lower  4 
bits  (Ao_3)  are  greater  than  S,  or  if  the  Auxiliary 
Carry  Flag  has  been  set,  adds  6  to  Aq_3.  When  the 
upper  4  bits  (A4_7)  are  greater  than  9  or  if  the  Carry 
Flag  (C)  has  been  set,  adds  6  to  A4_7.  If  an 
overflow  occurs  at  this  point,  C  is  set.® 

DEC  A 

(A) -(A)-  1 

Decrements  the  contents  of  the  accumulator  by  1 . 

07 

0 

0 

0 

0 

0 

1 

1 

1          1  1 

INC  A 

(A)  <-  (A)  +  1 

Increments  the  contents  of  the  accumulator  by  1 . 

17 

0 

0 

0 

1 

0 

1 

1 

11  1 

ORLA,# 
data 

(A)  -  (A)Vdata 

Takes  the  logical  sum  (logical  OR)  of  immediate 
data  d0-d7  and  the  contents  of  the  accumulator, 
and  stores  the  result  in  the  accumulator. 

43 

0 
d7 

1 

d6 

0 
d5 

0 

d4  . 

0 
d3 

0 
d2 

1 

d1 

1          2  2 

ORL  A,  Rr 

(A)  -  (AV(Rr) 

t  =  0-7 

Takes  the  logical  sum  (logical  OR)  of  register  Rr 
and  the  contents  of  the  accumulator,  and  stores 
the  result  in  the  accumulator 

4n@ 

0 

1 

0 

0 

1 

r 

r 

r          1  1 

ORL  A,  @  Rr 

(A)  -  (A)V((Rr)) 
r  =  0-1 

Takes  the  logical  sum  (logical  OR)  of  the  contents 
of  the  internal  data  memory  location  specified  by 
bits  0-5  in  register  Rr,  and  the  contents  of  the 
accumulator,  and  stores  the  result  in  the 
accumulator. 

4n@ 

0 

1 

0 

0 

0 

0 

0 

r         1  1 

RLA 

(Ab  +  1)*-(Ab) 
(Aq)  -  (A7) 
b  =  0—6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  left.  The  MSB  is  rotated  into  the  LSB. 

E7 

1 

1 

1 

0 

0 

1 

1 

1          1  1 

RLCA 

(Ab  +  1)-(Ab) 
(Aq)-(C) 
(C)  *-  (A7) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  left  through  carry. 

F7 

1 

1 

1 

1 

0 

1 

1 

1          1  1 

RR  A 

(Ab)-(Ab  +  1) 
(A7)  -  (A0) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  right.  The  LSB  is  rotated  into  the  MSB. 

77 

0 

1 

1 

1 

0 

1 

1 

1          1  1 

RRC  A 

(Ab)-(Ab  +  1) 
(A7)  «-  (C) 
(C)-(Ao) 
b  =  0-6 

Rotates  the  contents  of  the  accumulator  one  bit  to 
the  right  through  carry. 

67 

0 

1 

1 

0 

0 

1 

1 

1          1  1 

SWAP  A 

(A4_7)-(Ao_3) 

Exchanges  the  contents  of  the  lower  4  bits  of  the 
accumulator  with  the  upper  4  bits  of  the 
accumulator. 

47 

0 

1 

0 

0 

0 

1 

1 

1          1  1 

XRLA,#data 

(A)  «-  (A)Vdata 

Takes  the  exclusive  OR  of  immediate  data  d0-d7 
and  the  contents  of  the  accumulator,  and  stores 
the  result  in  the  accumulator. 

D3 

1 

d7 

1 

d6 

0 
d5 

1 

d4 

0 
d3 

0 
d2 

1 

di 

1          2  2 

XRL  A,  Rr 

(A)  «-  (A)V(Rr) 
r  =  0-7 

Takes  the  exclusive  OR  of  the  contents  of  register 
Rr  and  the  accumulator,  and  stores  the  result  in 
the  accumulator. 

Dn© 

1 

1 

0 

1 

1 

r 

r 

r         1  1 

XRL  A,  @  Rr 

(A)<-(A)V((Rr)) 
r  =  0-1 

Takes  the  exclusive  OR  of  the  contents  of  the 
location  in  data  memory  specified  by  bits  0-5  in 
register  Rr,  and  the  accumulator,  and  stores  the 
result  in  the  accumulator. 

Dn© 

1 

1 

0 

1 

0 

0 

0 

r         1  1 

Branch 

DJNZ  Rr, 
addr 

(Rr)-(Rr)-  1 
If  (Rr)  *0,then 
(PCq_7)  -  addr 
r  =  0-7 

Decrements  the  contents  of  register  Rr  by  1 ,  and  if 
the  result  is  not  equal  to  0,  jumps  to  the  address 
indicated  by  a„-a7. 

En 

1 

a? 

1 

a6 

1 

as 

0 
a4 

1 

a3 

r 

a2 

r 

ai 

r          2  2 
a0 

JBb  addr        (PCo_7)  <-  addr  if  b  =  1       Jumps  to  the  address  specified  by  a0-a7  if  the  bit      x2©         b2      b1      b0      1  0       0       1       0         2  2 

(PC)  =  (PC)  +  2  if  b  =  0     in  the  accumulator  specified  by  b0-b2  is  set.  a7      a6      a5      a4  a3      a2      a1  a0 


4-132 


,,PD80C49/80C39 


Instruction  Set  (Cont.) 


instruction  Code 


Mnemonic 

Function 

Description 

Code 

D7 

D6 

D5 

l>4 

D3 

i>2 

D1 

Do 

Cycles 

Bytes 

Branch  (Cont.) 

JCaddr 

(PC0-7)  -  addr  if  C  =  1 
(PC)-  (PC)  +  2ifC  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Carry  Flag  is  set. 

F6 

1 

a7 

1 

a6 

1 

a5 

1 

a4 

0 

a3 

1 

a2 

1 

ai 

0 
a0 

2 

2 

JFO  addr 

(PCo_7)  -  addr  if  FO  =  1 
(PC)  -  (PC)  +  2  if  FO  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  FO 
is  set. 

B6 

1 

0 

a6 

1 

a5 

1 

a4 

0 

a3 

1 

a2 

1 

ai 

0 

a0 

2 

2 

JF1  addr 

(PCo_7)  «--  addr  if  F1  =  1 
(PC)  -  (PC)  +  2  if  F1  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  F1 
is  set. 

76 

0 

a7 

1 

a6 

1 

a5 

1 

a4 

0 

a3 

1 

a2 

1 

«1 

0 

a0 

2 

JMP  addr 

(PCb-io)  <-  addr^m 
(PC0-7)-  addro_7 
(PCn1)  -  DBF 

Jumps  directly  to  the  address  specified  by  a0-a10 
and  the  DBF. 

a10 

a7 

a9 
a6 

as 
a5 

a4 

a3 

a2 

ai 

a0 

JMPP  @  A 

(PCo-7)-((A)) 

Replaces  the  lower  8  bits  of  the  Program  Counter 
with  the  contents  of  program  memory  specified 
by  the  contents  of  the  accumulator,  producing 
a  jump  to  the  specified  address  within  the 
current  page. 

B3 

1 

0 

1 

1 

0 

0 

1 

1 

2 

1 

JNC  addr 

(PC0-7)*  addr  if  C  =  0 
(PC)-(PC)  +  2ifC  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Carry  Flag  is  not  set. 

E6 

1 

a7 

1 

a6 

1 

a5 

0 
a4 

0 

a3 

i 

1 

■1 

0 
a0 

2 

2 

JNI addr 

(PCo_7)  -  addr  if  I  =  0 
(PC)  -  (PC)  +  2  if  I  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Interrupt  Flag  is  not  set. 

86 

1 

a7 

0 

a6 

0 

a5 

0 
a4 

0 

a3 

a12 

1 

*i 

0 

a0 

2 

2 

JNTOaddr 

(PC^-addrifTO  =  0 
(PC)  -  (PC)  +  2  if  TO  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  Test  0 
is  LOW. 

26 

0 

a7 

0 

a6 

1 

a5 

0 

a4 

0 

a3 

a2 

1 

»i 

0 

a0 

2 

2 

JNT1 addr 

(PCo_7)<-addrifT1  =  0 
(PC) -(PC)  +  2  if  T1  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  Test  1 
is  LOW. 

46 

0 
a7 

1 

a6 

0 

a5 

0 
a4 

0 

a3 

a2 

1 

«i 

0 

a0 

2 

2 

JNZ  addr 

(PCq_7)  —  addr  if  A  #  0 
(PC)-(PC)  +  2ifA  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the 
contents  of  the  accumulator  are  not  equal  to  0. 

96 

1 

a7 

0 

a6 

0 

a5 

1 

a4 

0 

a3 

a2 

1 

ai 

0 

a0 

2 

2 

JTF  addr 

(PCo-7)^addrifTF  =  1 
(PC) -(PC)  +  2  if  TF  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  the 
Timer  Flag  is  set.  The  Timer  Flag  is  cleared  after 
the  instruction  is  executed. 

16 

0 

a7 

0 
a6 

0 

a5 

1 

a4 

0 

a3 

a2 

1 

a1 

0 

a0 

2 

2 

JTOaddr 

(PCo-7)<-addrifTO  =  1 
(PC)-(PC)  +  2  if  TO  =  0 

Jumps  to  the  address  specified  by  a0-a7  if  Test  0 
is  HIGH. 

36 

0 

a7 

0 

a6 

1 

a5 

1 

a4 

0 

a3 

a2 

1 

a1 

0 

a0 

2 

2 

JT1  addr 

(PCo_7)-addrifT1  =  1 
(PC)-(PC)  +  2ifT1  =0 

Jumps  to  the  address  specified  by  a0-a7  if  Test  1 
is  HIGH. 

56 

0 

a7 

1 

a6 

0 

a5 

1 

a4 

0 

a3 

a2 

1 

■1 

0 
a0 

2 

2 

JZ 

(PC0-7)  -  addr  ifA  =  0 
(PC)-  (PC) +  2 if A  =  1 

Jumps  to  the  address  specified  by  a0-a7  if  the 
contents  of  the  accumulator  are  equal  to  0. 

C6 

1 

a7 

1 

a6 

0 

a5 

0 
a4 

0 

a3 

a2 

1 

a1 

0 

a0 

2 

2 

Control 

EN  I 

Enables  external  interrupts.  When  external 
interrupts  are  enabled,  a  low-level  input  to  the  INT 
pin  causes  the  processor  to  vector  to  the  interrupt 
service  routine. 

05 

0 

0 

0 

0 

0 

0 

DISI 

Disables  external  interrupts.  When  external 
interrupts  are  disabled,  low-level  inputs  to  the  INT 
pin  have  no  effect  on  program  execution. 

15 

0 

0 

0 

1 

0 

0 

ENTOCLK 

Enables  clock  output  to  pin  TO. 

75 

0 

1 

1 

1 

0 

0 

SEL  MBO 

(DBF)  -  0 

Clears  the  Memory  Bank  Flip-Flop,  selecting 
Program  Memory  Bank  0  [program  memory 
addresses  0-2047(10)].  Clears  PC^  after  the  next 
JMP  or  CALL  instruction. 

E5 

1 

1 

1 

0 

0 

0 

SEL  MB1 

(DBF)  -  1 

Sets  the  Memory  Bank  Flip-Flop,  selecting 
Program  Memory  Bank  1  [program  memory 
addresses  2048-4095(10)].  Sets  PCT1  after  the  next 
JMP  or  CALL  instruction. 

F5 

1 

1 

1 

1 

0 

0 

SELRBO 

(BS)  -  0 

Selects  Data  Memory  Bank  0  by  clearing  bit  4 
(Bank  Switch)  of  the  PSW.  Specifies  data  memory 
addresses  0-7(10)  as  registers  0-7  of  Data 
Memory  Bank  0. 

C5 

1 

1 

0 

0 

0 

0 

SELRB1 

(BS)-1 

Selects  Data  Memory  Bank  1  by  setting  bit  4 
(Bank  Switch)  of  the  PSW.  Specifies  data  memory 
24-31  (10)  as  registers  0-7  of  Data  Memory  Bank  1 . 

D5 

1 

1 

0 

1 

0 

0 

HALT 

Initiates  Halt  mode. 

01 

0 

0 

0 

0 

0 

0 

0 

Data  Moves 

MOVA,  # 
data 

(A)  -  data 

Moves  immediate  data  d0-d7  into  the 
accumulator. 

23 

0 

°7 

0 

1 

d5 

0 
d4 

0 
d3 

0 
d2 

1 

di 

MOV  A,  Rr 

(A)  -  (Rr) 
r  =  0-7 

Moves  the  contents  of  register  Rr  into  the 
accumulator. 

Fn© 

1 

1 

1 

1 

r 

r 

MOV  A,  @  Rr 

(A) -WW) 
r  =  0-1 

Moves  the  contents  of  internal  data  memory 
specified  by  bits  0-5  in  register  Rr,  into  the 
accumulator. 

Fn© 

1 

1 

1 

0 

0 

0 

MOVA,  PSW 

(A) -(PSW) 

Moves  the  contents  of  the  Program  Status  Word 
into  the  accumulator. 

C7 

1 

0 

0 

0 

1 

1 

MOV  Rr,  # 
data 

(Rr)  -  data 
r  =  0-7 

Moves  immediate  data  d0-d7  into  register  Rr. 

Bn© 

0 
d6 

1 

d5 

1 

d4 

1 

d3 

r 

d2 

r 

di 

MOV  Rr,  A 

(Rr)  -  (A) 
r  =  0-7 

Moves  the  contents  of  the  accumulator  into 
register  Rr. 

An© 

0 

1 

0 

1 

r 

r 

MOV@Rr,A 

«Rr))-(A) 
r  =  0-1 

Moves  the  contents  of  the  accumulator  into  the 
data  memory  location  specified  by  bits  0-5  in 
register  Rr. 

An© 

0 

1 

0 

0 

0 

0 

MOV  @  Rr,  # 
data 

((Rr))  -  data 
r  =  0-1 

Moves  immediate  data  d0-d7  into  the  data 
memory  location  specified  by  bits  0-5  in 
register  Rr. 

Bn© 

0 
d6 

1 

d5 

1 

d4 

0 
d3 

0 

d2 

0 

di 

2 

2 

MOV  PSW,  A 

(PSW) -(A) 

Moves  the  contents  of  the  accumulator  into  the 
Program  Status  Word. 

D7 

1 

1 

0 

1 

0 

1 

1 

1 

1 

4-133 


,.PD80C49/80C39 

Instruction  Set  (Cont.) 


Instruction  Code 


Mnemonic 

Function 

Description 

Code 

D7 

D6 

D5 

D4 

D3 

D2 

D, 

Do 

Cycles 

Bytes 

Data  Moves  (Cont.) 

MOVP  A,  @  A 

(PCo-7)-(A) 
(A)  -  ((PC)) 

Moves  the  contents  of  the  program  memory 
location  specified  by  PC^  concatenated  with 
the  contents  of  the  accumulator,  into  the 
accumulator. 

A3 

1 

0 

1 

0 

0 

0 

1 

1 

2 

1 

MOVP3  A, 

@A 

(PC„  7)  <-  (A) 

(PCs-nJ-OOl 
(A)  <-  ((PC)) 

Moves  the  contents  of  the  program  memory 
location  specified  by  0011  (PC^,  page  3  of 
Program  Memory  Bank  0)  and  the  contents  of  the 
accumulator,  into  the  accumulator. 

E3 

1 

1 

1 

0 

0 

0 

1 

1 

2 

1 

MOVXA,  @R 

(A)  -  ((Rr)) 
r  =  0-1 

Moves  the  contents  of  the  external  data  memory 
location  specified  by  register  Rr,  into  the 
accumulator. 

8n© 

1 

0 

0 

0 

0 

0 

0 

r 

2 

1 

MOVX  @  R,  A 

((Rr)) «-  (A) 
r  =  0-1 

Moves  the  contents  of  the  accumulator  into  the 
external  data  memory  location  specified  by 
register  Rr. 

9n@ 

1 

0 

0 

1 

0 

0 

0 

r 

2 

1 

XCH  A,  Rr 

(A)  -  (Rr) 
r  =  0-7 

Exchanges  the  contents  of  the  accumulator  and 
register  Rr. 

2n© 

0 

0 

1 

0 

1 

r 

r 

r 

1 

1 

XCH  A,  @  Rr 

(A)  -  ((Rr)) 
r  =  0-1 

Exchanges  the  contents  of  the  accumulator  and 
the  contents  of  the  data  memory  location 
specified  by  bits  0-5  in  register  Rr. 

2n@ 

0 

0 

1 

0 

0 

0 

0 

1 

1 

XCHD  A,  @ 
Rr 

(V3)~((V3» 
r  =  0-1 

Exchanges  the  contents  of  the  lower  4  bits  of  the 
accumulator  with  the  contents  of  the  lower  4  bits 
of  the  internal  data  memory  location  specified  by 
bits  0-5  in  register  Rr. 

3n© 

0 

0 

1 

1 

0 

0 

0 

r 

1 

1 

Flags 

CPLC 

(C)  -  (C) 

Takes  the  complement  of  the  Carry  bit. 

A7 

0 

1 

0 

0 

1 

1 

1 

CPL  FO 

(FO)-(FO) 

Takes  the  complement  of  Flag  0. 

95 

0 

0 

1 

0 

0 

1 

1 

CPL  F1 

(F1)-(F1) 

Takes  the  complement  of  Flag  1 . 

B5 

0 

1 

1 

0 

0 

1 

1 

CLRC 

(C)-0 

Clears  the  Carry  bit. 

97 

0 

0 

1 

0 

1 

1 

1 

CLR  FO 

(FO)-O 

Clears  Flag  0. 

85 

0 

0 

0 

0 

0 

1 

1 

CLR  F1 

(F1)-0 

Clears  Flag  1 . 

A5 

0 

1 

0 

0 

0 

1 

1 

Input/Output 

ANL  BUS,  # 
data 

(BUS)  •  (BUS)Adata 

Takes  the  logical  AND  of  the  contents  of  the  bus 
and  immediate  data  d0-d7,  and  sends  the  result  to 
the  bus. 

98 

0 
d6 

0 
d5 

1 

d4 

d3 

0 

d2 

0 
di 

0 
do 

2 

2 

ANL  Pp,  # 
data 

(Pp)  -  (PP)  Adata 
p  =  1-2 

Takes  the  logical  AND  of  the  contents  of 
designated  port  Pp  and  immediate  data  d0-d7, 
and  sends  the  result  to  port  Pp  for  output. 

9n© 

0 
d6 

0 
d5 

1 

d4 

0 
d2 

P 

di 

P 
do 

2 

2 

ANLD  Pp,  A 

(Pp)-(Pp)A(Ao-3) 
p  =  4-7 

Takes  the  logical  AND  of  the  contents  of 
designated  port  Pp  and  the  lower  4  bits  of  the 
accumulator,  and  sends  the  result  to  port  Pp  for 
output. 

9n© 

1 

0 

0 

1 

1 

P 

P 

2 

1 

IN  A,  Pp 

(A)-(PP) 
p  =  1-2 

Loads  the  accumulator  with  the  contents  of 
designated  port  Pp. 

On© 

0 

0 

0 

0 

0 

P 

P 

2 

1 

INS  A,  BUS 

(A) -(BUS) 

Loads  the  contents  of  the  bus  into  the 
accumulator  on  the  rising  edge  of  RD. 

08 

0 

0 

0 

0 

0 

0 

0 

2 

1 

MOVD  A,  Pp 

(Vs)  -  (PP) 
(A4_7)-0 
p  =  4-7 

Moves  the  contents  of  designated  port  Pp  to  the 
lower  4  bits  of  the  accumulator,  and  clears  the 
upper  4  bits. 

On© 

0 

0 

0 

0 

1 

P 

P 

2 

1 

MOVD  Pp,  A 

(PP)  -  (Ao_3) 
p  =  4-7 

Moves  the  lower  4  bits  of  the  accumulator  to 
designated  port  Pp.  The  upper  4  bits  of  the 
accumulator  are  not  changed. 

3n© 

0 

0 

1 

1 

1 

P 

P 

2 

1 

ORL  BUS,  # 
data 

(BUS)  <-  (BUS)Vdata 

Takes  the  logical  OR  of  the  contents  of  the  bus 
and  immediate  data  d0-d7,  and  sends  the  result  to 
the  bus 

88 

1 

d7 

0 
d6 

0 
d5 

0 

d4 

d3 

0 

d2 

0 
di 

0 
do 

2 

2 

ORLD  Pp,  A 

<Pp)-(Pp)V(Ao-3) 
p  =  4-7 

Takes  the  logical  OR  of  the  contents  of  designated 
port  Pp  and  the  lower  4  bits  of  the  accumulator, 
and  sends  the  result  to  port  Pp  for  output. 

8n© 

1 

0 

0 

0 

1 

P 

P 

2 

1 

ORL  Pp,  # 
data 

(Pp)-(Pp)Vdata 
p=  1-2 

Takes  the  logical  OR  of  the  contents  of  designated 
port  Pp  and  immediate  data  d0-d7,  and  sends  the 
result  to  port  Pp  for  output. 

9n© 

1 

d7 

0 
d6 

0 

d5 

0 
d4 

d3 

0 

d2 

P 

di 

P 
do 

2 

2 

OUTL  BUS,  A 

(BUS) -(A) 

Latches  the  contents  of  the  accumulator  onto  the 

bus  on  the  rising  edge  of  WR. 

Note:  Never  use  the  OUTL  BUS  instruction  when 
using  external  program  memory,  as  this 
will  permanently  latch  the  bus. 

02 

0 

0 

0 

0 

0 

0 

1 

0 

2 

1 

OUTL  Pp,  A 

(Pp)-(A) 
P=1-2 

Latches  the  contents  of  the  accumulator  into 
designated  port  Pp  for  output. 

3n© 

0 

0 

1 

1 

1 

0 

P 

P 

2 

1 

Registers 

DEC  Rr 

(Rr)-(Rr)-  1 
r  =  0-7 

Decrements  the  contents  of  register  Rr  by  1 . 

Cn© 

1 

1 

0 

0 

1 

r 

r 

r 

1 

1 

INC  Rr 

(Rr)-(Rr)  +  1 
r  =  0-7 

Increments  the  contents  of  register  Rr  by  1. 

1n© 

0 

0 

0 

1 

1 

r 

r 

1 

1 

INC  @  Rr 

((Rr))-((Rr))+1 
r  =  0-1 

Increments  by  1  the  contents  of  the  data  memory 
location  specified  by  bits  0-5  in  register  Rr. 

1n© 

0 

0 

0 

1 

0 

0 

0 

1 

1 

4-134 


MPD80C49/80C39 


Instruction  Set  (Cont.) 


Instruction  Code 


Mnemonic 

Function 

Description 

Code 

D7 

°6 

»5 

D4 

D3 

D2 

Di 

Do 

Cycles  Bytes 

Subroutine 

CALL  addr 

((Spwmpcmpsw^) 

(SP)  -  (SP)  +  1 
(PCs-io)  -  addr„_10 
(PC*.?)  «-  addr„_7 
(PC,,)  -  DBF 

Stores  the  contents  of  the  Program  Counter 
and  the  upper  4  bits  of  the  PSW  in  the  address 
indicated  by  the  Stack  Pointer,  and  increments  the 
contents  of  the  Stack  Pointer,  calling  the  subrou- 
tine specified  by  address  a0-a10  and  the  DBF. 

x4© 

a10 

a? 

a9 
a6 

a8 
a5 

1 

a4 

0 
a3 

1 

a2 

0 

a-. 

0 

2  2 

RET 

(SP)  -  (SP)  -  1 
(PC)-((SP)) 

Decrements  the  contents  of  the  Stack  Pointer 
by  1  and  stores,  in  the  Program  Counter,  the 
contents  of  the  location  specified  by  the  Stack 
Pointer,  executing  a  return  from  subroutine 
without  restoring  the  PSW. 

83 

1 

0 

0 

0 

0 

0 

1 

1 

2  1 

RETR 

(SP)  -  (SP)  -  1 

(PC)-((SP)) 

<PSW4_7)<-((SP)) 

Decrements  the  contents  of  the  Stack  Pointer 
by  1  and  stores,  in  the  Program  Counter,  the 
contents  of  the  upper  4  bits  of  the  PSW  and  the 
contents  of  the  location  specified  by  the  Stack 
Pointer,  executing  a  return  from  subroutine  with 
restoration  of  the  PSW. 

93 

1 

0 

0 

1 

0 

0 

1 

1 

2  1 

Timer/Counter 

ENTCNTI 

Enables  internal  interrupt  of  timer/event  counter. 
If  an  overflow  condition  occurs,  then  an  interrupt 
will  be  generated. 

25 

0 

0 

1 

0 

0 

1 

0 

1 

1  1 

DIS  TCNTI 

Disables  internal  interrupt  of  timer/event  counter. 

35 

0 

0 

1 

1 

0 

1 

0 

1 

1  1 

MOV  A,  T 

(A)-(T) 

Moves  the  contents  of  the  timer/counter  into  the 
accumulator. 

42 

0 

1 

0 

0 

0 

0 

1 

0 

1  1 

MOVT,A 

(T)-(A) 

Moves  the  contents  of  the  accumulator  into  the 
timer/counter. 

62 

0 

1 

1 

0 

0 

0 

1 

0 

1  1 

STOPTCNT 

Stops  the  operation  of  the  timer/event  counter. 

65 

0 

1 

1 

0 

0 

1 

0 

1 

1  1 

STRT  CNT 

Starts  the  event  counter  operation  of  the 
timer/counter  when  T1  changes  from  a  low-level 
input  to  a  high-level  input. 

45 

0 

1 

0 

0 

0 

1 

0 

1 

1  1 

STRTT 

Starts  the  timer  operation  of  the  timer/counter. 
The  timer  is  incremented  every  32  machine 
cycles. 

55 

0 

1 

0 

1 

0 

1 

0 

1 

1  1 

Miscellaneous 

NOP 

Uses  one  machine  cycle  without  performing  any 
operation. 

00 

0 

0 

0 

0 

0 

0 

0 

0 

1  1 

Notes:  ©  Binary  instruction  code  designations  r  and  p  represent  encoded  values  or  the  lowest-order  bit  value  of  specified  registers  and  ports,  respectively 

©  Execution  of  the  ADD,  ADDC,  and  DA  instructions  affect  the  carry  flags,  which  are  not  shown  in  the  respective  function  equations  These  instructions  set  the  carry  flags  when  there  is  an 

overflow  in  the  accumulator  (the  Auxiliary  Carry  Flag  is  set  when  there  is  an  overflow  of  bit  3  of  the  accumulator)  and  clear  the  carry  flags  when  there  is  no  overflow  Flags  that  are 

specifically  addressed  by  flag  instructions  are  shown  in  the  function  equations  for  those  instructions 
®  References  to  addresses  and  data  are  specified  in  byte  1  and/or  2  in  the  opcode  of  the  corresponding  instruction 
©  The  hex  value  of  n  for  specific  registers  is  as  follows 

a)  Direct  addressing 

Ft0n  =  8  R2n=A  R4n  =  C  R6n  =  E 
R,  n  =  9      R3n  =  B      R5n  =  D      R7n  =  F 

b)  Indirect  addressing 
@R0n  =  0      @R,  n  =  1 

©  The  hex  value  of  n  for  specific  ports  is  as  follows 

P1n  =  9      P4    n  =  C      P6n  =  E 

P2n  =  A      P5    n  =  D      P7n  =  F 
©  The  hex  value  of  x  for  specific  accumulator  or  address  bits  is  as  follows 

a)  JBb  instruction 

B0  x  =  1  B2x  =  5  B4  x  =  9  B6x  =  D 
Bi  x  =  3      B3x  =  7      B5x  =  B      B7x  =  F 

b)  JMP  instruction 

Page  0  x  =  0  Page  2  x  =  4  Page  4  x  =  8  Page  6  x  =  C 
Page  1  x  =  2      Page  3  x  =  6      Page  5  x  =  A      Page  7  x  =  E 

c)  CALL  instruction 

PageO  x  =  1  Page  2  x  =  5  Page  4  x  =  9  Page  6  x  =  D 
Page  1  x  =  3      Page  3  x  =  7      Page  5  x  =  B      Page  7  x  =  F 


4-135 


fxPD80C49/80C39 


DC  Characteristics:  Standard  Voltage  Range 

Ta  =  -40°C  to  +85°C;  Vcc  =  +5V  ±  10%;  Vss  =  0V 


Parameter 

Symbol 

Limits 

Unit 

Test  Conditions 

Min  Typ 

Max 

Input  Low 
Voltage 

V,L 

-0.3 

0.8 

V 

Input  High 

V,H 

VCC-2 

VCC 

V 

All  except  XTAL1,  XTAL2,  RESET 

Voltage 

V.H1 

Vcc-1 

Vcc 

V 

RESET,  XTAL1,XTAL2 

Output  Low 
Voltage 

Vol 

0.45 

V 

l0L  =  2.0mA 

V0H 

2.4 

V 

Bus,  RD,  WR,  PSEN,  ALE,  PROG, 
T0;lOH=  -100(jiA 

Output  High 
Voltage 

Vohi© 

2.4 

V 

Port1,Port2;lOH  =  -5p.A 
(TypeO) 

Port  1 ,  Port  2;  I0h  =  -  50  p. A 
(Typel) 

V0H2 

Vcc-0.5 

V 

All  outputs;  I0h  =  -0.2|xA 

l|LP© 

-15 

-40 

Port1,Port2;V,Ns  V|L 
(TypeO) 

Input  Current 

-500 

|xA 

Portl  Port2;V|N<VIL 
(Typel) 

I.LC 

-40 

HA 

SS,  RESET;  V,N  £  V,L 

Input  Leakage 

«LI1 

±1 

pA 

T1,INT,VDD;VSS<VIN<VCC 

Current 

IU2 

±3 

^A 

EA;VsssVIN<Vcc 

Output  Leakage 
Current 

!  . 

■lo 

±1 

|iA 

Bus,  TO,  High-Impedance  State; 

VssSVo^Vcc 

Standby 

•cci 

0.4 

0.8 

mA 

Halt  mode;  tCY  =  2.5|xs 

Current 

'CC2 

1 

20 

MA 

Stop  mode  @ 

Supply  Current 

Ice 

4 

8 

mA 

tCY  =  2.5|xs 

Data  Retention 
Voltage 

VcCDR 

2.0 

V 

Stop  mode  (VDD,  RESET  <  0.4V) 

DC  Characteristics:  Extended  Voltage  Range 

Ta  =  -40°Cto  +  85C;  Vcc  =  +  2.5V  to  +5.5V;  Vss  =  OV 


Limits 

Parameter 

Symb 

ol  Min  Typ  Max 

Unit 

Test  Conditions 

Input  Low  Voltage 

V,L 

-0.3         0.18  Vcc 

V 

Input  High  Voltage 

(All  Except  XTAL 1,  XTAL  2) 

V,H 

0.7VCC  Vcc 

V 

Input  High  Voltage 
(XTAL  1,  XTAL  2) 

V.H1 

0.8VCC  Vcc 

V 

Output  Low  VoltsQG 

vol 

|QL  l.wfllM 

Output  High  Voltage  (Bus, 
PROG,  TO 

vOH 

0.75VCC 

V 

'OH  =  —  100fiA 

Output  High  Voltage  (All 
Other  Outputs 

V0H1 

0.7VCC 

V 

Portl,  Port  2; 
•oh  =  -VA 
(TypeO) 

Portl,  Port  2; 
Ioh=-10hA 
(Type  1) 

Output  High  Voltage 
(All  Outputs) 

VOH2 

Vcc  ~  0.5 

V 

l0H  =  -0.2jtA 

Input  Leakage  Current 

!ILP 

-15  -40 

nA 

V,n^Vil  (TypeO) 

(Portl  .Port  2) 

-500 

HA 

V,NsVIL  (Typel) 

input  Leakage  Current 
(SS,  RESET) 

•iLC 

-40 

yA 

V,n  s  VIL 

Input  Leakage  Current 
(T1,INT) 

'lL1 

±1 

MA 

Vss<VIN<VCc 

Input  Leakage  Current 
(EA) 

•lL2 

±3 

(xA 

Vc«t  <  V,N  <  Vrr 

Output  Leakage  Current 
(Bus,  TO — High  Impedance 
State) 

'OL 

±1 

?A 

VSs<V0<Vcc 

Supply  Current 

•cc 

0.8  1.6 

mA 

Vcc  =  3V, 

tcv  =  10|XS 

Halt  Mode  Standby 
Current 

•cci 

100  200 

HA 

Vcc  =  3V, 
tCY  =  10|xS 

Stop  Mode  Standby  Current 

*CC2 

1  20 

HA 

Notes:  ©  Type  0  and  type  1  options  apply  only  to  the  H.PD80C48,  the  nPD80C35  is  type  1  only 
©  Input  Pin  Voltage  is  VtN,  V,L,  or  V,N,  V,H 


AC  Characteristics 

Read,  Write  and  Instruction  Fetch:  External  Data  and  Program  Memory 

Ta  =  -40°C to  +85  C;  Vcc  =  VDP  =  +5V  ±  10%;  VSs  =  OV  


V95  = 

+5V  ±  10% 

V99  = 

+  2.5V  to  +  5.5V 

Test 

Parameter 

Symbol 

Min 

Typ  Max 

Min 

Typ  Max 

Unit 

Conditions 

ALE  Pulse  Width 

tLL 

400 

2160 

ns 

Address  Setup  before  ALE 

*AL 

120 

1620 

ns 

Address  Hold  from  ALE 

tLA 

80 

330 

ns 

© 

Control  Pulse  Width 
(PSEN,  RD,  WR) 

tec 

700 

3700 

ns 

Data  Setup  before  WR 

*DW 

500 

3500 

ns 

Data  Hold  after  WR 

*WD 

120 

370 

ns 

® 

Cycle  Time 

tCY 

2.5 

150 

10 

150 

|XS 

6MHz  XTAL 

Data  Hold 

tDR 

0 

200 

0 

950 

ns 

PSEN,  RD  to  Data  in 

*RD 

500 

2750 

ns 

Address  Setup  before  WR 

*AW 

230 

3230 

ns 

© 

Address  Setup  before  Data  In 

tAD 

950 

5450 

ns 

Address  Float  to  RD,  PSEN 

lAFC 

0 

500 

ns 

Control  Pulse  to  ALE 

10 

10 

ns 

4-136 


|iPD80C49/80C39 


Port  2  Timing 

T,  =  -40°C  to  +85  C;  Vcc  =  +5V  ±  10% 


Vcc  = 

+  5V  ±  10% 

VCc=  + 

2.5V  to  +5.SV 

Test 

Parameter 

Symbol 

M/n 

Typ  Max 

Min 

Typ  Max 

Unit 

Conditions 

Port  Control  Setup  before 
Falling  Edge  of  PROG 

tCp 

110 

860 

ns 

Port  Control  Hold  after  Falling 
Edge  of  PROG 

tPC 

0 

80 

0 

200 

ns 

® 

PROG  to  Tim©  P2  input  must 
be  Valid 

tpR 

810 

5310 

ns 

Output  Data  Setup  Time 

tDP 

250 

3250 

ns 

® 

Output  Data  Hold  Time 

tpD 

65 

820 

ns 

Input  Data  Hold  Time 

tPF 

0 

150 

0 

900 

ns 

PROG  Pulse  Width 

tpp 

1200 

6450 

ns 

Port  2  I/O  Data  Setup 

tpL 

350 

2100 

ns 

Port  2  I/O  Data  Hold 

tLP 

150 

1400 

ns 

Notes:  ®  For  Control  Outputs  CL  =  80pF,  for  Bus  Outputs-  CL  =  150pF 
®  CL  =  20pF 

®  For  Control  Outputs  CL  =  80pF 

®  Refer  to  the  operating  characteristic  curves  for  Supply  Voltage  and  Port  Control  Hold 


BUS  Timing  Requirements 


Symbol 

Timing  Formula 

Min 

Max 

Unit 

tLL 

(7  /  30)  T- 167 

• 

ns 

tAL 

(1/5)T-285 

• 

ns 

tLA 

(1/30)T 

• 

ns 

tec 

(2/5)T-300 

• 

ns 

*DW 

(2/5)T-500 

• 

ns 

*WD 

(1/30)T  +  40 

• 

ns 

tDR 

(1/10)T-50 

• 

ns 

*RD 

(3  / 10)  T-  250 

• 

ns 

*AW 

(2/5)T-600 

• 

ns 

tAD 

(3/5)T-550 

• 

ns 

tAFC 

(1/15)T-125 

• 

ns 

tCP 

(1/10)T-87 

• 

ns 

tpR 

(3/5)T-475 

• 

ns 

tPF 

(1/10)T-100 

• 

ns 

tDP 

(2/5)T-550 

• 

ns 

tpD 

(1/10)T-167 

• 

ns 

tpp 

(7/ 10)  T- 550 

• 

ns 

tpL 

(7  /  30)  T- 230 

• 

ns 

tLP 

(1/6)T-265 

• 

ns 

T  =  toy 

Unlisted  parameters  are  not  affected  by  cycle  time 

Timing  Waveforms 

Instruction  Fetch  From  External  Memory 


ft 


J  L 


BUS  Floating;  f"^    X  Floating^    e,    )f~  Floating  )( 


Write  to  External  Memory 

ALE        I  1 


WR 


h-tcc-H 


T 


Bus  Floating 


r-  h 


V  Floating  )f 


|tow  H  H 


Low  Power  Standby  Operation 
1)  Halt  Mode  (When  El) 


-<      1  Instr     X 'NT  Execute 


cpu^Xj^""^- 

Internal 
Clock 


Halt 
Mode 


— V  \ 

f 

t  \ 

2)  Stop  Mode 


OSC  Starts 

iv^jinjinnnji.._rL 


ADRS  0000(H) 


Port  2  Timing 


Read  From  External  Data  Memory 


J  L 


Port  X  PCH  fa  in 
Output   ,y  


Expander 
Port 
Output 


bus  Floating, 


\  -H  ^fc  k-    — H  h-t. 


r 


Floating 


4-137 


,  PD80C49/80C39 

Block  Diagram 


Oscillator 
Frequency 


Port  2  Latch  (Low  4) 
and  Expander 
Port  I/O 


Bus  Buffer 
Port  2 


Port  2 
Latch 
(High  4) 


Timer  and 
Event  Counter 


1C 


Higher  Program 
Counter  (4)  "*-J 


BUS 

Resident  Program  Memory 
ROM  |xPD80C49  only 
2048  x  8 


Expansion  to  Additional 
External  Memory  and  I/O 


Decode 


8 

Lower 

Program 

Counter 

Bus  Latch 
Low  Program 
Counter's  Temp 
Register 


Program 
Status 
Word 


8-Bit  Internal  Bus 


Accumulator 
(8) 


Temporary 
Register  (8) 


Accumulator 
Latch 


Power 
Supply 


Flags 

n 


Arithmetic 
Logic  Unit 


 ^+2  5Vto  +  6  0V 

Vss 

— Ground 
Vqq  Standby  Power  Control 


Instruction 
Register/Decoder 


RAM  Address 
Register 


Decimal 
Adjust 


Conditional 
Branch 
Logic 


-  Test  0 

-  Test  1 
■  iNT 

-  Flag  0 

-  Flag  1 

-  Timer  Flag 

-  Carry 

-  Acc 


Control  and  Timing 

XTAL  XTAL 

INT 

RESET  PROG 

EA           1      2  ALE 

PSEN 

SS 

RD  WR 

m 


Low      Interrupt  Initialize 
Power  I/O 
Standby  Control  Expander 
Strobe 


CPU/Memory 
Separate 


Address 
Latch 
Strobe/ 
Oscillator/  Cycle 
Crystal  clock 


Program  Single 
Memory  Step 
Enable 


TT 

Read/Write 
Strobes 


Multiplexer  | 

Register  0 

Register  1 

Register  2 

Register  3 

Register  4 

a> 
■a 

8 

Register  5 

0) 

a 

Register  6 

Register  7 

8- Level  Stack 
(Variable  Word  Length) 

Optional  Second 
Register  Bank 

Data  Store 

Resident  Data  Memory  —  RAM 
(128  x  8) 


Note:  nPD80C39  does  not  include  ROM 


Absolute  Maximum  Ratings* 


Ta  =  25C 

Operating  Temperature,  Topt 

-40°Cto  +85°C 

storage  Temperature  (Cerdip  Package),  Tstg 

-65°Cto  +150°C 

Storage  Temperature  (Plastic  Package),  Tstg 

-65°Cto  +125°C 

Voltage  on  Any  Pin,  V|/0  VSs 

-0.3VtoVcc  +0.3V 

Supply  Voltage,  VCc 

Vss  -0.3  to  +10V 

Power  Dissipation,  PD 

0.35w 

"COMMENT:  Exposing  the  device  to  stresses  above  those 
listed  in  Absolute  Maximum  Ratings  could  cause  perma- 
nent damage.  The  device  is  not  meant  to  be  operated 
under  conditions  outside  the  limits  described  in  the  opera- 
tional sections  of  this  specification.  Exposure  to  absolute 
maximum  rating  conditions  for  extended  periods  may  affect 
device  reliability. 


4-138 


Operating  Characteristic  Curves 

Output  High  Current  vs.  Output  High  Voltage 


VCc  = 

1 — 
4  5V 

Mm 

2  3  4 

Output  High  Voltage,  VOH  (V) 


Output  High  Current  vs.  Supply  Voltage 


£  -100-10 


0  o 

1  f 


Supply  Voltage,  Vcc  (V) 
Output  Low  Current  vs.  Supply  Voltage 


Supply  Voltage,  Vcc  (V) 


,xPD80C49/80C39 

Output  High  Current  vs.  Output  High  Voltage 


O  -5 


Vcc  =  4  5V 

\ 

\  Typ 

Min\ 

\ 

1  2  3  4  5 

Output  High  Voltage,  VOH1  (V) 


Output  High  Current  vs.  Supply  Voltage 


Supply  Voltage,  Vcc  (V) 

Output  Low  Current  vs.  Output  Low  Voltage 


Output  Low  Voltage,  VOL  (V) 


4-139 


PD80C49  80C39 

Operating  Characteristic  Curves  (Cont.) 

Supply  Current  vs.  Oscillation  Frequency 


0  05 
0  03 


Vcc  =  3V 

lcc  Max 

/ 

^Typ 

tcc1Max 

•cci  Typ 

0.1         0  2  0  5  t  2 

Oscillation  Frequency,  f(MHz),  (f  =  15  tCY) 


Cycle  Time  vs.  Supply  Voltage 


Op 

'ration  G 

jarantee 
Area 

Port  Control  Hold  After  PROG,  tpc  Max  foPD80C49),  and  Address  to 
Output  Delay,  tacc  Min  (\xPD82C43),  vs.  Supply  Voltage 


<  a  150 
2  a 
oo 


jjtPD82C^ 

\*acc  Mm 

3 

PD80C4S 
tpc  Max 

\  \, 

Supply  Voltage,  Vcc  (V) 


Current  Consumption  as  a  Function  of  Temperature  —  Normal 
Operating  Mode 


t  =  6MHz 

fee  =  55V 


3  4  5  6 

Supply  Voltage,  Vcc  (V) 


-40  0       25  85 

Temperature,  Ta  (°C) 


Supply  Current  vs.  Oscillation  Frequency® 


Current  Consumption  as  a  Function  of  Operating  Frequency  - 
Normal  Operating  Mode 


£  4 


Note:  ©External  oscillation  is  assumed  for  frequency  less  than  1  MHz.  Internal  oscillation 
requires  more  power. 


Oscillation  Frequency.  f(MHz).  (f  =  15  tCY) 


4-140 


|xPD80C49/80C39 


Operating  Characteristic  Curves  (Cont.) 

Current  Consumption  as  a  Function  of  Temperature  —  Stop  Mode 


10 


Vcc  =  5.5V 

/Max 

Typ 

-40  0       25  85 

Temperature,  Ta  (°C) 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  fxPD80C49C/C39C 
Plastic  Shrinkdip,  |xPD80C49HC 
Plastic  Miniflat.  fxPD80C49G/C39G 


4-141 


80C49/80C39DS-Rev/1-7-8-83-CAT-L 


MICROPROCESSORS 


STFC  (xPD780/(xPD780-1/|jJ»D780-2 
"  HIGH-PERFORMANCE 

CP/M  -COMPATIBLE  NMOS 
8-BIT  MICROPROCESSOR 


Description 

The  fxPD780  microprocessor  utilizes  a  highly  con- 
sistent architectural  organization,  a  comprehensive 
instruction  set  that  is  a  superset  of  the  industry-standard 
8080A  instruction  set,  and  third-generation  technology,  to 
provide  a  flexible,  high-performance,  efficient  CPU  easily 
adaptable  to  a  very  broad  range  of  industrial  and  commer- 
cial applications. 

All  software  developed  on  8080A-based  systems  may 
be  run  on  780-based  systems  as  a  subset  of  the  full  780 
instruction  set.  In  addition,  the  NEC  liPD780  is  fully 
pin-compatible  and  software-compatible  with  the  Z80® 
microprocessor  and  is  therefore  perfectly  suited  for 
CP/M®  designs.  The  NEC  liPD780  provides  system 
designers  with  powerful,  wide-range  logic  capability  that 
requires  minimal  additional  circuitry  to  complete  a  micro- 
computer system. 

The  output  signals  of  the  liPD780  are  fully  decoded  and 
signal  timing  is  fully  compatible  with  industry-standard 
memory  and  peripheral  devices.  Two  faster  versions  of  the 
basic  |jlPD780  (2.5MHz  master  clock  rate)  are  offered  by 
the  fxPD780-1  (4MHz  master  clock  rate)  and  the  liPD780-2 
(6MHz  master  clock  rate).  Other  than  clock  rates,  all  three 
versions  are  identical. 
Features 

□  Powerful,  wide-range  logic  capability  requiring  minimal 
support  circuitry 

□  Fully  Z80®-compatible 

□  Industry-standard  8080A  software  compatibility 

□  CP/M®-compatible 

□  Comprehensive,  powerful  instruction  set  featuring  158 
instruction  types 

□  Vectored,  multilevel  interrupt  structure 

□  Highly  consistent  architectural  structure  featuring  dual 
register  set 

□  Foreground/background  programming 

□  Automatic  refreshing  of  external  dynamic  memory 

□  Signal  timing  compatible  with  industry-standard  mem- 
ory and  peripheral  devices 

□  TTL-compatible  signals 

□  Single-phase  +  5V  clock  and  +  5VDC  power  supply 

□  Available  in  plastic  package 

®Z80  is  a  registered  trademark  of  Zilog,  Inc 

®CP/M  is  a  registered  trademark  of  Digital  Research  Corporation 


Pin  Configuration 


D7 
D0 

D± 
INT 
NMI 
HALT 
MREQ 
lORQ 


C 

c 

C15 
C16 
C  17 
C18 
L"  19 
C  20 


(jiPD 
780/ 
780-1/ 
780-2 


40  2  A« 
39  J  A9 
38  D  A8 
37  J  A7 
36  3  A6 
35  3  A5 
]A4 
33  P  A3 
32 
31 
30 


3  A2 
3  A1 
D  A0 
3  GND 
3  RFSH 

□  ^  

3  RESET 
3  BUSRQ 
3  WATT 
3  BUSAK 
3  WR 
3  RD 


Pin  Identification 


Pin 

Name 

Function 

No. 

Symbol 

1-5 
30-40 

A0-A15 

Address  Bus 

These  three-state  output  lines  constitute  a 
16-bit  address  bus.  Lines  A0-A6  output 
the  external  memory  address  during 
refresh  operations 

6 

Clock 

This  line  is  used  as  an  input  for  external 
clock  sources. 

7-10 
12-15 

D0-D7 

Data  Bus 

These  three-state  I/O  lines  constitute  an 
8-bit  bidirectional  data  bus 

11 

+  5V 

Power  Supply 

Single  +  5V  power  supply. 

Interrupt  Request    This  active-low  input  line  is  used  for  inter- 
rupt requests  by  external  I/O  devices. 
Interrupts  are  serviced  upon  completion 
of  the  current  instruction  if  the  Interrupt 
Enable  Fhp-Flop  (IFF)  has  been  turned  on 
by  the  software.  There  are  three  interrupt 
response  modes:  the  mode-0  response  is 
equivalent  to  an  8080  interrupt  response, 
mode  1  uses  location  0038(H)  as  a  restart 
address,  and  mode  2  is  a  simple  vectoring 
to  an  interrupt-service  routine  that  can  be 
located  anywhere  in  memory. 

Nonmaskable      This  active-low  input  line  is  used  for  non- 
Interrupt         maskable  interrupts.  A  nonmaskable 

interrupt  is  always  acknowledged  at  the 
end  of  the  current  instruction,  regardless 
of  whether  or  not  the  Interrupt  Enable  Flip- 
Flop  has  been  turned  on,  except  when  the 
BUSRQ  signal  is  asserted.  Because  of  the 
higher  priority  of  the  BUSRQ  signal,  it  is 
acknowledged  before  the  NMI  signal. 
When  NMI  is  acknowledged,  program 
execution  automatically  restarts  from 
location  0066(H). 


18  HALT  Halt  State 


This  active-low  input  line  is  used  with  the 
HALT  instruction  to  initiate  a  halt  state. 
When  HALT  is  asserted,  program  execu- 
tion stops  and  does  not  resume  until  an 
interrupt  is  generated.  During  the  halt 
state,  NOPs  are  executed  in  order  to  con- 
tinue memory  refresh  operations. 


19  MREQ        Memory  Request 


This  three-state  active-low  output  line  is 
used  to  indicate  that  the  address  specified 
for  the  memory  read  or  write  operation 
is  valid. 


REV/2 
5-1 


MPD780/780-1/780-2 

Pin  Identification  (Cont.) 


Pin 

'  Name  Function 

No.  Symbol 

20  I0RQ  I/O  Request       This  three-state  active-low  output  line  is 

used  to  indicate  that  the  lower  half  of 
the  address  bus  holds  a  valid  address  for 
an  I/O  read  or  write  operation.  During 
interrupt  acknowledge  cycles,  IORQ 
and  M-|  are  asserted  together  to  indicate 
that  a  vector  address  can  be  sent  to  the 
data  bus. 

21  RD  Read  This  three-state  active-low  output  line  is 

used  to  strobe  data  from  external  memory 
or  I/O  devices  onto  the  data  bus.  RD  is 
asserted  to  indicate  that  the  CPU  is 
requesting  data  from  external  memory  or 
I/O  devices  This  line  is  three-stated  dur- 
ing halt  or  reset  conditions. 

22  WR  Write  This  three-state  active-low  output  line  is 

used  to  strobe  data  from  the  data  bus  to 
external  memory  or  I/O  devices  WR  is 
asserted  to  indicate  that  the  data  bus 
holds  valid  data.  This  line  is  three-stated 
during  halt  or  reset  conditions. 

23  BUSAK       Bus  Acknowledge   This  active-low  output  line  is  used  to 

inform  the  device  requesting  bus  control 
that  the  data  bus,  address  bus,  and  all 
three-state  bus  control  signals  (RD,  WR, 
IORQ,  and  MREQ)  are  in  a  high-impedance 
state  and  the  requesting  device  can  now 
assume  control. 

24  WAIT  Wait  State        This  active-low  input  line  is  used  to  indi- 

cate that  external  memory  or  I/O  devices 
addressed  by  the  CPU  are  not  ready  to 
transfer  data.  When  WAIT  is  asserted,  the 
CPU  is  placed  in  a  wait  condition 

25  BUSRQ  Bus  Request      This  active-low  input  signal  is  used  to 

place  the  data  bus,  address  bus,  and  all 
three-state  bus  control  signals  (WR,  RD, 
IORQ,  and  MREQ)  in  a  high-impedance 
state  to  allow  a  requesting  device  to 
assume  bus  control.  The  BUSRQ  signal 
has  a  higher  priority  than  the  NMI  signal 
and  is  always  honored  at  the  end  of  the 
current  machine  cycle  © 

26  RESET  Reset  This  active-low  input  signal  is  used  to  ini- 

tialize the  CPU.  When  RESET  is  asserted, 
the  Interrupt  Enable  Flip-Flop  is  reset,  the 
program  counter  and  the  I  and  R  registers 
are  cleared,  and  interrupt  response  mode 
0  is  enabled.  In  a  reset  condition,  the 
address  and  data  buses  are  three-stated 
and  all  output  control  signals  are  inactive, 
after  which  program  execution  begins 
from  address  0000  © 


27  M1  Machine  Cycle  1     This  active-low  output  line  is  used  to  indi- 

cate that  the  current  machine  cycle  is  the 
opcode  fetch  phase  of  an  instruction 
execution. 

28  RFSH  Refresh  This  active-low  output  line  is  used  in  con- 

junction with  the  MREQ  signal  to  initiate  a 
refresh  read  of  all  external  dynamic  mem- 
ory. RFSH  and  MREQ  are  both  asserted 
when  the  least-significant  7  bits  of  the 
address  on  the  address  bus  hold  a  valid 
external  dynamic  memory  address. 

29  GND  Ground  Ground  potential 

Notes:  ©  Excessive  DMA  operations  resulting  in  long  periods  in  which  BUSRQ  is  asserted 
can  impair  the  CPU's  ability  to  adequately  refresh  the  dynamic  RAMs 
BUSRQ  does  not  have  an  internal  pull-up  resistor  For  input  signals  to  this  pin  in  a  wire- 
OR'ed  configuration,  an  external  pull-up  resistor  should  be  used 
©  The  pulse  width  of  RESET  must  be  a  minimum  of  3  clock  cycles  in  length  to  reinitialize 
the  CPU  and  stabilize  operation 


Architecture 

The  architecture  includes  a  dual  set  of  six  8-bit  general- 
purpose  registers  and  two  8-bit  accumulators  and  flag 
registers.  A  flexible  vectored  interrupt  structure  is  sup- 
ported by  an  8-bit  interrupt  vector  register  that  provides 
the  most-significant  8  bits  of  a  pointer  to  a  table  of  vector 
addresses,  while  the  requesting  device  generates  the 
least-significant  8  bits  of  the  pointer.  Two  16-bit  index 
registers  enable  the  manipulation  of  tabular  data  as 
well  as  facilitating  code  relocation. 
Multilevel  interrupts  as  well  as  virtually  unlimited  subroutine 
nesting  are  supported  by  a  16-bit  stack  pointer  and  compli- 
mentary 16-bit  program  counter,  enhancing  the  speed  and 
efficiency  of  a  wide  variety  of  data-handling  operations. 
Processing  efficiency  is  additionally  supported  by  a  special 
memory  refresh  register  that  enables  automatic  refreshing 
of  all  external  dynamic  memory  with  minimal  processor 
overhead. 

The  dual  set  of  general-purpose  registers  may  be  used 
as  individual  8-bit  registers  or  paired  as  16-bit  registers. 
The  dual  register  set  (including  a  dual  accumulator  and  flag 
register)  not  only  allows  more  powerful  addressing  and  data 
transfer  operations,  but  also  permits  programming  in  fore- 
ground/background mode  for  vastly  improved  throughput. 


5-2 


,PD780/780-1/780-2 


Block  Diagram 


Main  General-Purpose 
Register  Set 


NMI 
INT 


Alternative  General-Purpose 
Register  Set 


Accumulator 
A 

Flag 
F 

Accumulator 
A 

Flag 
F 

-  General-Purpose  Registers 

B 

C 

B 

C 

D 

E 

D 

E 

H 

L 

H 

L' 

Interrupt 
Vector  ' 

Memory 
Refresh  R 

Index  Register  IX 

-Special  Purpose  Registers 

Index  Register  IY 

Stack  Pointer  SP 

Program  Counter  PC 

^^8^)   DB  Buffer  ^^^^D| 


Bus  Control 

Read/Write  Control 

Timing  Control 

System  Control 

i  I 

BUSRQ  BUSAK 

I  I  I  I 

WR         IORQ        RD  MREO 

I   I  i 

M,        HALT  WAIT 

i  I 

RESET  RFSH 

Instruction  Set 

The  instruction  set  of  the  |jlPD780  consists  of  158  types  of 
instructions  divided  into  16  categories  as  follows: 


8-bit  load  operations 
register  exchanges 
memory  block  searches 
1 6-bit  arithmetic  operations 
rotate  and  shift  operations 
jump  operations 
restart  operations 
miscellaneous  operations 
1 6-bit  load  operations 
memory  block  transfers 


8-bit  arithmetic  and  logic 

operations 
bit  set,  reset,  and  test 

operations 
I/O  operations 
call  operations 
return  operations 
general-purpose 

accumulator  and  flag 

operations 


This  comprehensive  instruction  set  is  made  more  pow- 
erful by  the  array  of  addressing  modes  implemented  by  the 
architecture,  as  follows: 


bit  addressing 
register-indirect  addressing 
immediate  addressing 
extended  addressing 
implied  addressing 
register  addressing 


relative  addressing 
immediate-extended 

addressing 
indexed  addressing 
modified  page  zero 

addressing 


5-3 


(xPD780/780-1 /780-2 

Instruction  Set  (Cont.) 


MNEMONIC 

SYMBOLIC 
OPERATION 

DESCRIPTION 

NO. 
BYTES 

NO.T 
STATES 

C 

z 

FLAGS 
P/V  s 

N 

H 

OPCODE 
76   543  210 

ADC  HL,  ss 

HL^-  HL  +  ss  +  CY 

Add  with  carry  reg  pair  ss  to  HL 

1 

15 

X 

X 

V 

X 

0 

X 

11 

01 

101 

ss1 

101® 
010 

ADC  A,  r 

A*- A  +  r  +  CY 

Ado'  with  carry  Reg  r  to  ACC 

1 

4 

X 

X 

V 

X 

0 

X 

10 

001 

rrr® 

ADC  A,n 

A  *-  A  +  n  +  CY 

Add  with  carry  value  n  to  ACC 

7 

X 

X 

V 

X 

0 

X 

11 

001 

110 

ADC  A,  (HL) 

A*-A  +  (HL)  +CY 

Add  with  carry  loc  (HL)  to  ACC 

7 

X 

X 

V 

X 

0 

X 

10 

001 

110 

ADC  A,  (IX  +  d) 

A<-  A  +  (IX  +d)  +  CY 

Add  with  carry  loc  (IX  +  d)  to  ACC 

19 

X 

X 

V 

X 

0 

X 

11 

10 

dd 

011 
001 
ddd 

101 
110 
ddd 

ADC  A,  (lY  +  d) 

A«-A  +  (IY  +d)  +  CY 

Add  with  carry  loc  (IY  +  d)  to  ACC 

19 

X 

X 

V 

X 

0 

X 

11 

10 

dd 

111 
001 
ddd 

101 
110 

ddd 

ADD  A,  n 

A  <-  A  +  n 

Add  value  n  to  ACC 

2 

7 

X 

X 

V 

X 

0 

X 

11 
nn 

000 
nnn 

110 

nnn 

ADDA,  r 

A- A  +  r 

Add  Reg.  r  to  ACC 

1 

4 

X 

X 

0 

x 

rrr® 

ADDA,  (HL) 

A^  A  +  (HL) 

Add  location  (HL)  to  ACC 

1 

7 

X 

X 

V 

X 

0 

X 

10 

000 

110 

ADD  A  (IX  +  d) 

A  ■<—  A  +  (I X  +  d) 

f\ao  location  ua  +  a)  to  auv> 

X 

X 

V 

X 

0 

1 

11 
10 
dd 

011 
000 
ddd 

101 
110 
ddd 

ADD  A,  (I Y  +  d) 

A  ■«-  A  +  (I  Y  +  d) 

Add  location  (1 Y  +  d)  to  ACC 

1 

X 

X 

0 

X 

1 1 
10 

dd 

1 1 1 
000 
ddd 

1 01 
110 
ddd 

ADD  HL,  ss 

HL^  HL  +  ss 

Add  Reg.  pair  ss  to  HL 

1 

11 

X 

• 

• 

• 

0 

X 

00 

ss1 

001^ 

ADD  IX,  pp 

IX  -  IX  +  pp 

Add  Reg.  pair  pp  to  IX 

2 

15 

X 

• 

• 

• 

0 

X 

11 
00 

011 
pp1 

101© 
001 

ADD  IY,  p- 

IY  «-  !Y  +  t 

Add  Reg.  pair  rr  to  IY 

2 

15 

X 

• 

• 

• 

0 

X 

11 
00 

111 

r  r  1 

101® 
001 

AND  r 

A  *-  AAr 

Logical  'AND'  of  Reg  r  A  ACC 

4 

0 

X 

p 

X 

0 

X 

10 

100 

rrr® 

AND  n 

A  «-  AAn 

Logical  'AND'  of  value  n  A  ACC 

7 

0 

X 

p 

X 

0 

X 

11 

100 

110 

Logical  'AND'  of  loc  (HL)  A  ACC 

nnn 

nnn 

AND  (HL) 

A  -  AA(HL) 

7 

0 

X 

p 

X 

0 

X 

10 

100 

110 

AND  (IX  +d) 

A  <-AA(IX  +  d) 

Logical  'AND'  of  loc  (IX  +  d)  A  ACC 

19 

0 

X 

p 

X 

0 

X 

11 

10 

dd 

011 
100 
ddd 

101 
110 

ddd 

AND  (IY  +d) 

A  <-AA(IY  +  d) 

Logical  'AND'  of  loc  (IY  +  d)  A  ACC 

19 

0 

X 

p 

X 

0 

X 

11 
1 0 
dd 

111 
100 
ddd 

101 
110 
ddd 

BIT  b,  (HL) 

Z  *-  (HL)  b 

Test  BIT  b of  location  (HL) 

2 

12 

• 

X 

0 

1 

01 

bbb 

011© 
110 

BIT  b,  (IX  +d) 

Z  <-  (IX  +d)  b 

Test  BIT  b  at  location  (IX  +d) 

4 

20 

• 

X 

X 

X 

0 

1 

11 

dd 
01 

011 

ddd 
bbb 

101© 

ddd 
110 

BIT  b,  (IY  +d) 

Z-  (lYTd)  b 

Test  BIT  b  at  location  (IY  +  d) 

4 

20 

• 

X 

x 

x 

0 

1 

1 1 
11 
dd 
01 

111 
001 
ddd 
bbb 

101  v-/ 
011 
ddd 
110 

BITb,  r 

z  *~  rb 

Test  BIT  of  Reg.  r 

2 

8 

• 

X 

x 

x 

0 

1 

1 1 
01 

001 

011—,—. 
rrr®® 

CALL  cc,  nn 

If  condition  cc  false  continue, 
else  same  as  CALL  nn 

Call  subroutine  at  location  nn  if 
condition  cc  is  true 

3 

10 

• 

• 

o 

• 

• 

• 

11 

nn 
nn 

<-cc— ► 
nnn 
nnn 

100® 

nnn 
nnn 

CALL  nn 

(SP  -  1 )  «-  pch 
(SP-  2)  +-PC 
PC  «-  nn 

Unconditional  call  subroutine  at 
location  nn 

3 

17 

11 

nn 
nn 

001 

nnn 
nnn 

101 

nnn 

CCF 

CY  *-  CY 

Complement  carry  flag 

1 

4 

I 

• 

* 

0 

X 

00 

CP  r 

A  -  r 

Compare  Reg  r  with  ACC 

4 

X 

X 

V 

1 

X 

10 

1 1 1 

rrr® 

CP  n 

A-  n 

Compare  value  n  with  ACC 

7 

X 

X 

V 

X 

1 

t 

1 1 

111 

110 

CP  (HL) 

nn 

nnn 

A  -  (HL) 

Compare  loc  (HL)  with  ACC 

7 

X 

X 

V 

X 

1 

X 

10 

111 

110 

CP  (IX  +d) 

A  -  (IX  +  d) 

Compare  loc  (IX  +  d)  with  ACC 

19 

X 

X 

V 

X 

1 

X 

11 
10 
dd 

011 
111 
ddd 

101 
110 
ddd 

CP  (IY  +  d) 

11 

111 

101 

Compare  loc  (IY  +  d)  with  ACC 

19 

X 

X 

V 

X 

1 

X 

10 

111 

110 

,® 

,© 

dd 

ddd 

ddd 

CPD 

A  -  (HL) 
HL  -  HL  -1 

Compare  location  (HL)  and  ACC, 
decrement  HL  and  BC 

2 

16 

• 

X 

1 

X 

11 
10 

101 
101 

101 
001 

BC  -  BC  1 

,© 

CPDR 

A  -  (HL) 
HL  -  HL  -  1 
BC  «-  BC  -  1 

until  A  =  (HL)  or  BC  =  0 

Compare  location  (HL)  and  ACC, 
decrement  HL  and  BC,  repeat  until 
BC  =  0 

2 

21  if  BC  -  0 
and  A  *  (HL) 
16  if  BC  =  0 
or  A  =  (HL) 

,© 

X 

11 
10 

101 
111 

101 
001 

5-4 


(XPD780/780-1/780-2 


Instruction  Set  (Cont.) 


MNEMONIC 

SYMBOLIC 
OPERATION 

DESCRIPTION 

NO. 
BYTES 

NO.  T 
STATES 

C 

z 

FLAGS 
P/V  S 

N 

H 

OPCODE 
76   543  210 

CP  I 

A-  (HL) 

Compare  location  (HL)  and  ACC, 

2 

16 

• 

X® 

1 

t 

1 1 

101 

1 01 

HL  —  HL  +  1 

increment  HL  and  decrement  BC 

10 

100 

001 

BC  —  BC  -  1 

t® 

CPIR 

A-  (HL) 
HL- HL+ 1 
BC-BC-  1 
until 

A  =  (HL)  or  BC  =  0 

Compare  location  (HL)  and  ACC, 
increment  HL,  decrement  BC 
Repeat  until  BC  =  C 

2 

21  if  BC  =  0 
and  A  *  (HL) 
16  if  BC  =  0 
or  A  =  (HL) 

• 

1 

I 

11 
10 

101 
110 

101 
001 

CPL 

A  -  A 

Complement  ACC  (1's  comp  ) 

1 

4 

• 

1 

1 

00 

101 

111 

DAA 

Decimal  adjust  ACC 

1 

4 

t 

i 

P  t 

• 

X 

00 

100 

111 

DEC  r 

r  —  r  -  1 

Decrement  Reg  r 

4 

X 

V  X 

1 

X 

00 

rrr 

101® 

DEC  (HL) 

(HL)<-(HL)  -  1 

Decrement  loc  (HL) 

11 

• 

t 

v  t 

1 

X 

00 

110 

101 

DEC  (IX  +  d) 

(IX  +  d)  +-  (IX  +  d)  -  1 

Decrement  loc  (IX  +  d) 

X 

V  X 

1 

x 

11 

00 
dd 

011 
110 

ddd 

101 
101 
ddd 

DEC  (IY  +  d) 

(IY  +  d)  —  (IY  +  d)  -  1 

Decrement  loc  (IY  4  d) 

23 

X 

v  t 

1 

* 

11 
00 
dd 

111 
110 
ddd 

101 
101 
ddd 

DEC  IX 

IX  <-  ix  -  1 

Decrement  IX 

2 

10 

11 

00 

011 
101 

101 
011 

DEC  IY 

IY  -  IY  -  1 

Decrement  IY 

2 

10 

11 
00 

111 
101 

101 
011 

DEC  ss 

ss  —  ss  -  1 

Decrement  Reg  pair  ss 

1 

6 

00 

ss1 

011® 

Dl 

IFF  -0 

Disable  interrupts 

1 

4 

11 

110 

011 

DJNZ,  e 

B-B-1.fB  =  0 

Decrement  B  and  jump  relative  if 

2 

8 

00 

010 

000 

continue  if  B  ^  0 

B  =  0 

PC  —  PC  +  e 

El 

IFF  -  1 

Enable  interrupts 

1 

4 

1 1 

111 

011 

EX  (SP),  HL 

H  -  (SP  +  1 ) 
L-  (SP) 

Exchange  the  location  (SP)  and  HL 

1 

19 

11 

100 

011 

EX  (SP),  IX 

ixH  -  (SP  +  1) 
IXL~  (SP) 

Exchange  the  location  (SP)  and  IX 

2 

23 

1 1 
11 

01 1 
100 

101 
011 

EX  (SP),  IY 

IY,.-  (SP+  1) 
IY"«(SP) 

Exchange  the  location  (SP)  and  IY 

2 

23 

11 

111 

101 

11 

100 

011 

EX  AF,  AF  ' 

AF  -  AF' 

Exchange  the  contents  of  AF,  AF 

1 

4 

00 

001 

000 

EX  DE,  HL 

DE  —  HL 

11 

101 

011 

EXX 

BC  —  BC ' 
DE  —  DE ' 
HL  -  HL' 

Exchange  the  contents  of  BC,  DE,  HL 
with  contents  of  BC  '  DE'  HL' 
respectively 

1 

4 

11 

011 

001 

HALT 

Processor  Halted 

HALT  (wait  for  interrupt  or  reset) 

1 

4 

01 

110 

110 

IM  0 

Set  Interrupt  mode  0 

2 

8 

11 

01 

101 

000 

101 
110 

IM  1 

Set  mterrupt  mode  1 

2 

11 

01 

101 
010 

101 
110 

IM  2 

Set  Interrupt  mode  2 

2 

8 

11 

01 

101 
011 

101 
110 

IN  A,  (n) 

A  —  (n) 

Load  ACC  with  input  from  device  n 

2 

11 

11 

011 

011 

nn 

nnn 

nnn 

101® 

000 

IN  r,  (C) 

r-(C) 

Load  Reg  r  with  input  from  device 
(C) 

2 

12 

• 

X 

p  x 

0 

* 

11 
01 

101 

INC  (HL) 

(HL)  -  (HL)  +  1 

Increment  location  (HL) 

1 

11 

• 

X 

V  X 

0 

X 

00 

110 

100 

INC  IX 

IX  -  IX  +  1 

Increment  IX 

2 

10 

11 
00 

011 
100 

101 
011 

INC  (IX  +  d) 

(IX  +  d)  —  (IX  +d)  +  1 

Increment  location  (IX  +  d) 

3 

23 

• 

X 

V  X 

0 

X 

11 
00 
dd 

011 
110 
ddd 

101 
100 
ddd 

INC  IY 

IY  -  IY  +  1 

Increment  IY 

2 

10 

11 
00 

111 
100 

101 
011 

INC  (IY  +d) 

(IY  +d)  -(IY  +  d)  +  1 

Increment  location  (IY  +  d) 

3 

23 

• 

X 

V  x 

0 

X 

11 
00 
dd 

111 
110 
ddd 

101 
100 
ddd 

INC  r 

r  — r  +  1 

Increment  Reg  r 

1 

4 

• 

X 

V  x 

0 

X 

00 

100® 

INC  ss 

ss  —  ss  +  1 

Increment  Reg.  pair  ss 

1 

6 

00 

ssO 

011® 

IND 

(HL)  -  (C) 
B  —  B  -  1 
HL-HL-  1 

Load  location  (HL)  with  input  from 
port  (C),  decrement  HL  and  B 

2 

16 

• 

X  X 

1 

X 

11 
10 

101 
101 

101 
010 

5-5 


|iPD780/780-1/780-2 

Instruction  Set  (Cont.) 


MNEMONIC 

SYMBOLIC 
OPERATION 

DESCRIPTION 

NO 
BYTES 

NO  T 
STATES 

C 

FLAGS 
Z     P/V  S 

N 

H 

OPCODE 
76   543  210 

INDR 
INI 

(HL)  -  (C) 
B  -  B  -  1 

HL  -  HL  -  1  until  B  =  0 

(HL)  -  (C) 
B  -  B  -  1 
HL  —  HL  +  1 

Load  location  (HL)  with  input  from 
port  (C),  decrement  HL  and  decre 
ment  B,  repeat  until  B  =  0 
Load  location  (HL)  with  input  from 
port  (C),  and  increment  HL  and 

2 
2 

21 
16 

• 
• 

:©  x 

X 

1 
1 

X 
X 

10 

1 1 
10 

111 

101 
100 

010 

101 

010 

INIR 

(HL)  -  (C) 
B  -  B  -  1 

HL  —  HL  +  1  until  B  =  0 

Load  location  (HL)  with  input  from 
port  (C),  increment  HL  and  decre- 
ment B,  repeat  until  B  -  0 

2 

21 

• 

1  x 

X 

1 

X 

11 

10 

101 
110 

101 
010 

JP  (HL) 

PC  -  HL 

Unconditional  jump  to  (HL) 

1 

4 

1 1 

101 

001 

JP  (IX) 

PC  -  IX 

Unconditional  jump  to  (IX) 

2 

8 

11 
1 1 

011 
101 

101 
001 

JP  (IY) 

PC*  IY 

Unconditional  jump  to  (IY) 

2 

8 

11 
11 

111 

101 

101 
001 

JP  cc,  nn 

If  cc  true  PC  •   nn  else  continue 

Juitid  to  location  nn  if  condition  cc 
is  true 

3 

10 

11 

nn 

*-cc— 
nnn 
nnn 

010® 

nnn 

JP  nn 

PC  -  nn 

Unconditional  jump  to  location  nn 

3 

10 

1 1 

000 

011 

nnn 
nnn 

JR  C,  e 

If  C  -  0  continue 
If  C  =  1  PC  -  PC  +  e 

Jump  relative  to  PC  +  e,  if  carry  1 

2 

7  if  condition 
met  12,  if 

00   111  000 

jp  e 

PC  -  PC  +  e 

Unconditional  jump  relative  to  PC  +  e 

00   011  000 

JR  IMC,  e 

If  C  =  1  continue 
If  C  =  0  PC  -  PC  +  e 

Jump  relative  to  PC  +  e  if  carry  =  0 

2 

7 

00   110  000 

JR  NZ,  e 

If  Z  =  1  continue 

Jump  relative  to  PC  +  e  if  non-zero 
(Z  -  0) 

2 

7 

00   100  000 

JR  Z,  e 

If  Z  =  0  continue 

Jump  relative  to  PC  +  e  if  zero 
(Z  =  1) 

2 

7 

00    101  000 

LD  A,  (BC) 

A  «-  (BC) 

Load  ACC  with  location  (BC) 

1 

00 

001 

010 

LD  A,  (DE) 

A  *~  (DE) 

Load  ACC  with  location  (DE) 

00 

011 

010 

LD  A,  I 

A  *-  I 

Load  ACC  with  I 

2 

g 

1  IFF 

t 

o 

11 

01 

101 
010 

101 

111 

LD  A,  (nn) 

A  -  (nn) 

Load  ACC  with  location  nn 

3 

13 

00 

111 

nnn 

010 
nnn 

LD  A,  R 

A  -  R 

Load  ACC  with  Reg  R 

2 

g 

J 

o 

o 

11 

01 

101 
011 

101 
111 

LD  (BC),  A  ' 

(BC)  -  A 

Load  location  (BC)  with  ACC 

7 

00 

000 

010 

LD  (DE),  A 

(DE)  *-  A 

Load  location  (DE)  with  ACC 

1 

7 

010 

010 

LD  (HL),  n 

(HL)  -  n 

Load  location  (HL)  with  value  n 

2 

10 

00 

110 

nnn 

110 

LD  ss,  nn 

ss  i-  nn 

Load  Reg  pair  ss  with  value  nn 

4 

20 

00 

nn 

ssO 
nnn 
nnn 

001® 

LD  HL,  (nn) 

H  -  (nn  +  1 ) 
L  -  (nn) 

Load  HL  with  location  (nn) 

3 

16 

00 

101 

nnn 

010 

LD  (HL),  r 

(HL)  -  r 

Load  location  (HL)  with  Reg  r 

1 

7 

01 

110 

rrr® 

LD  I,  A 

I  <-  A 

Load  I  with  ACC 

2 

9 

11 

01 

101 
000 

101 
111 

LD  IX,  nn 

IX  -  nn 

Load  IX  with  value  nn 

4 

19 

11 

00 

nn 

011 
100 

101 
001 

nnn 

LD  IX,  (nn) 

IXH  -  (nn  +  1) 

IX,  -  (nn) 
L 

Load  IX  with  location  (nn) 

4 

20 

00 
nn 
nn 

011 
101 

nnn 
nnn 

101 
010 
nnn 

LD  (IX  +  d),  n 

(IX  +  d)  «-  n 

Load  location  (IX  +  d)  with  value  n 

4 

19 

11 
00 
dd 
nn 

011 
110 
ddd 
nnn 

101 
1 10 
ddd 
nnn 

LD  (IX  +d),  r 

(IX  +d)  -  r 

Load  location  (IX  +  d)  with  Reg  r 

3 

19 

11 
01 
dd 

011 
110 
ddd 

101® 
ddd 

5-6 


|xPD780/780-1/780-2 


Instruction  Set  (Cont.) 


MNEMONIC 

SYMBOLIC 

DESCRIPTION 

NO 

NO  T 

FLAGS 

OPCODE 

OPERATION 

BYTES 

STATES 

C 

z 

P/V    S  N 

H 

76 

543 

210 

LD  IY, nn 

IY  -  nn 

Load  IY  with  value  nn 

4 

14 

101 

00 

100 

001 

LD  IY,  (nn) 

I Y        (nn  +  1 ) 

Load  IY  with  location  (nn) 

4 

20 

nn 
1  1 

nnn 
111 

101 

IY*-  (nn) 

00 

101 

010 

LD  ss,  (nn) 

ss    «-  (nn  +  1 ) 

Load  Re      air  dd  with  location  (nn) 
oa      eg  pair      wit  ocation 

4 

20 

1 1 

1 01 

101® 

ss,  <-  (nn) 
L 

01 

ss  1 

011 

LD  (IY  +  d),  n 

(IY  +  d)  *  n 

Load  (I  Y  +  d)  with  value  n 

4 

19 

nn 

nnn 

nnn 

00 

1 10 

1 10 

dd 

ddd 

ddd 

LD  (I  Y  +  d),  r 

(IY  +  d)  •  r 

Load  location  (IY  +  d)  with  Reg  r 

3 

19 

1 1 

111 

101® 

01 

110 

dd 

ddd 

ddd 

LD  (nn),  A 

(nn)  -  A 

Load  location  (nn)  with  ACC 

3 

13 

Z 

z 

z 

LD  (nn),  ss 

(nn  +  1)  ♦  ssH 

Load  location  (nn)  with  Reg  pairdd 

4 

20 

1 1 

101 

101® 

(nn)  <-  ssL 

01 

nnr? 

01 1 

nn 

nnn 

nnn 

LD  (nn),  HL 

(nn  +  1)  -  H 
(nn)  —  L 

Load  location  (nn)  with  HL 

3 

16 

00 

100 

010 

LD  (nn),  IX 

(nn  +  1)  -  IX 

Load  location  (nn)  with  IX 

4 

20 

nn 
1 1 

nnn 
011 

nnn 
101 

(nn)  -  IXL 

00 
nn 

100 

nnn 

010 
nnn 

LD  (nn),  IY 

(nn  +  1)  ~  IYH 

Load  location  (nn)  with  IY 

4 

20 

nn 
1  1 

nnn 
111 

nnn 
101 

(nn)  -  IYL 

00 

100 

010 

nn 
nn 

nnn 
nnn 

nnn 
nnn 

LD  R,  A 

R  <-  A 

Load  R  with  ACC 

2 

y 

1 1 

101 

101 

01 

001 

1 1  1 

LD  r,  (HL) 

r  *-  (HL) 

Load  Reg  r  with  location  (HL) 

1 

7 

01 

r  r  r 

1  10^ 

LD  r,  (IX  +  d) 

r  -  (IX  +  d) 

Load  Reg  r  with  location  (IX  +  d) 

3 

19 

1 1 

01 1 

101^ 

01 

1 1  o 

dd 

ddd 

ddd 

LD  r,  (IY  +  d) 

r  -  (IY  +  d) 

Load  Reg  r  with  location  (IY  +  d) 

3 

19 

101® 

01 

W 

1 1 0 

dd 

ddd 

ddd 

LD  r,  n 

r  «~  n 

Load  Reg  r  with  value  n 

2 

7 

00 

r  r  r 

nn® 

1 10^ 

nn 

nnn 

r  *-  r 

Load  Reg  r  with  Reg  r 

1 

4 

# 

• 

•      •  • 

• 

01 

rrr 

r  r  r'v^ 

LD  SP,  HL 

SP  -  HL 

Load  SP  with  HL 

1 

6 

11 

1 1 1 

001 

LD  SP,  IX 

SP  -  IX 

Load  SP  with  IX 

2 

10 

01 1 

101 

1 1 

1 1 1 

001 

LD  SP,  IY 

SP  -  IY 

Load  SP  with  IY 

2 

10 

11 

1 1 1 

nm 

LDD 

(DE)  <-  (HL) 

Load  location  (DE)  with  location 

2 

16 

# 

•  0 

_ 

1 1 

101 

101 

DE  «-  DE  -  1 

(HL)  decrement  DE  HL  and  BC 

10 

101 

000 

HL  «-  HL  -  1 

BC  -  BC  -  1 

LDDR 

(DE)  -  (HL) 

Load  location  (DE)  with  location 

2 

21 

o     •  o 

o 

11 

101 

101 

DE  <-  DE  -  1 

(HL) 

1 0 

1 1 1 

000 

HL  -  HL  -  1 

BC  -  BC     1  until  BC  =  0 

I®.  0 

LDI 

(DE)  -  (HL) 

Load  location  (DE)  with  location 

2 

16 

• 

• 

0 

11 

101 

101 

DE  -  DE  +  1 

(HL),  increment  DE,  HL,  decrement 

10 

100 

000 

HL  <-  HL  +  1 

BC 

BC  «-  BC  -  1 

LDIR 

(DE)  -  (HL) 

Load  location  (DE)  with  location 

2 

21  if  BC  ^0 

• 

• 

0     •  0 

0 

11 

101 

101 

DE  -  DE  +  1 

(HL),  increment  DE,  HL,  decrement 

16  if  BC  =  0 

10 

110 

000 

HL  —  HL  +  1 

BC  and  repeat  until  BC  =  0 

BC  -  BC  -  1  until  BC  =  0 

NEG 

A  «-  0-  A 

Negate  ACC  (2's  complement) 

2 

8 

t 

t 

V      t  1 

I 

11 

101 

101 

01 

000 

100 

5-7 


,PD780/780-1/780-2 

Instruction  Set  (Cont.) 


SYMBOLIC 
OPERATION 


DESCRIPTION 


NO 
BYTES 


NO  T 
STATES 


FLAGS 
P/V  S 


00 

000 

000 

rrr( 

1 1 

110 

110 

nn 

10 

110 

110 

11 

011 

101 

dd 

ddd 

ddd 

1 1 

1 1 1 

101 

10 

1 10 

110 

dd 

ddd 

ddd 

1 1 

101 

101 

10 

111 

011 

1 1 

101 

101 

10 

110 

011 

1 1 

101 

101  ^ 

001 

1 1 

010 

01 1 

11 

101 

101 

10 

101 

011 

101 

10 

100 

01 1 

1 1 

011 

101 

1 1 

1 1 1 

101 

1 1 

100 

001 

1 1 

qqO 

001  ( 

1 1 

011 

101 

1 1 

100 

101 

1 1 

1 1 1 

101 

1 1 

100 

101 

1 1 

qqO 

10/ 

1 1 

001 

vi 

1 0 

1 1 

001 

011 

10 

bbb 

110 

11 

001 

011 

dd 

ddd 

ddd 

10 

bbb 

110 

1 1 

1 1 1 

101 

1 1 

001 

011 

10 

bbb 

110 

1 1 

001 

001 

11 

-cc  - 

000C 

1 1 

101 

101 

01 

001 

101 

1 1 

101 

101 

01 

000 

101 

1 1 

001 

011C 

00 

010 

11 

001 

011 

00 

010 

1 10 

1 1 

011 

101 

1 1 

001 

011 

dd 

ddd 

ddd 

00 

010 

110 

1 1 

111 

101 

1 1 

001 

011 

dd 

ddd 

ddd 

00 

010 

110 

00 

010 

1 1 1 

NOP 
OR  r 
OR  n 

OR  (HL) 
OR  (IX  +  d) 


OTIR 

OUT  (C),  1 
OUT  (n).  A 


A  -  AV  r 
A  -  AV  n 


A-  AV  (HL) 
A  -  (IX  +d) 


(C)<  (HL) 
B  -  B  1 

HL  •   HL     1  until  B  =  0 

(O-  (HL) 
B  -  B  -  1 

HL  •  HL  +  1  until  B  =  0 
(C)  -  r 

(n)  •  A 


OUTD 

(C)  - 

-  (HL) 

B  • 

B-  1 

HL 

HL  -  1 

OUTI 

(C)  • 

-  (HL) 

B  • 

B  1 

HL 

HL  +  1 

POP  IX 

IXH 

-  (SP  +  1) 

>< 

•  (SP) 

POP  IY 

IYH 

•-  (SP  +  1) 

'  YL 

•  (SP) 

POPqq 

ddH 

-  (SP  +  1) 

qqL 

•-  (SP) 

PUSH  IX 

(SP 

2)  -  IX 

(SP 

PUSH  IY 

(SP 

-2)-  IY 

(SP 

1).  IYH 

push  qq 

(SP 

2)  -  qqL 

(SP 

1 )  •  qqH 

RES  b,  r 

sb- 

0 

RES  b,  (HL) 

sb- 

0.  (HL) 

RES  b,  (IX  +  d) 

sb- 

0,  (IX  +  d) 

RES  b,  (IY  +  d) 

RET 
RET  cc 

RETI 

RETN 

RL  r 
RL  (HL) 
RL  (IX  +  d) 


Sb-  0,  (lY  +  d) 


PC,-  (SP) 
PCH  -  (SP  +  1) 

If  condition  cc  is  false 
cont  else  (PCl  •  (SP) 
PCH  -   (SP  +  1) 


m     r,  (HL), 
(IX  +  d), 
(IY  +  d),  A 


Logical  'OR'  of  Reg  r  and  ACC 
Logical  'OR'  of  value  n  and  ACC 


Logical  'OR'  of  loc  (HL)  and  ACC 
Logical  'OR'  of  loc  (IX  +  d)  A  ACC 


Logical  'OR'  of  loc  (IY  +  d)  A  ACC 

Load  output  port  (C)  with  contents 

of  location  (HL),  decrement  HL 

and  B,  repeat  until  B  =  0 

Load  output  port  (C)  with  location 

(HL),  increment  HL,  decrement  B, 

lepeat  until  B  -  0 

Load  output  port  (C)  with  Req  r 

Load  output  port  (n)  with  ACC 

Load  output  port  (C)  with  location 
(HL),  increment  HL  and 
decrement  B 

Load  output  port  (C)  with  locution 
(HL),  mciement  HL  and 
decrement  B 

Load  IX  with  top  of  stack 

Load  IY  with  top  of  stack 

Load  Reg  pair  qq  with  top  of  stack 

Load  IX  onto  stack 

Load  IY  onto  stack 

Load  Reg  pair  qq  onto  stack 

Reset  Bit  b  of  Reg  r 
Reset  Bit  b  of  loc  (HL) 
Reset  Bit  bof  loc  (IX  +  d) 

Reset  Bit  b  of  loc  (IY  +  d) 

Return  from  subroutine 

Return  from  subroutine  if  condition 
cc  is  true 

Return  from  interrupt 
Return  from  non  maskable  interrupt 
Rotate  left  through  carry  Reg  r 
Rotate  left  through  carry  loc  (HL) 
Rotate  left  through  carry  loc  (IX  +  d) 

Rotate  left  through  carry  loc  (IY  +  d) 
Rotate  left  ACC  through  carry 


7 
19 


21  if  B  /  0 
16  if  B  C 


21  if  B  *  0 
16  if  B  C 


5  if  CC  false 
1 1  if  CC  true 


.  CD 


1       X     X       1  X 


X      X       1  X 


X      X       1  X 


5-8 


|xPD780/780-1/780-2 


Instruction  Set  (Cont.) 


MNEMONIC 


SYMBOLIC 
OPERATION 


DESCRIPTION 


NO 
BYTES 


NO  T 
STATES 


FLAGS 

P/V    S      N  H 


76 

543 

210 

1 1 

001 

01 1 

00 

000 

110 

11 

011 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

000 

110 

11 

111 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

000 

110 

RLC  (HL) 
RLC  (IX  +  d) 


RLC  r 

RLCA 
RLD 

RR  r 
RR  (HL) 
RR  (IX  +  d) 


RR  A 

RRC  r 
RRC  (HL) 
RRC  (IX  +  d) 

RRC  (IY  +  d) 


SBC  A,  r 
SBC  A,  n 


SBC  A,  (HL) 
SBC  A,  (IX  +  d) 


SBC  A,  (IY  +  d) 


SCF 

SET  b,  (HL) 
SET  b,  (IX  +  d) 


[c^J-fTTlJ 

m-  r,  (HL), 

(IX  +  d),  (IY  +  d),  A 


A|7  4|3  Of       |7  4h  ol(HL) 


m  -  r,  (HL), 

(IX  +  d),  (IY  +  d),  A 


L^~7]X^y] 

m  -  r,  (HL), 

(IX  +d),  (IY  +d),  A 


A  |7  4|3  0| 


TLEZL 


|7  4|  3  o|(HL) 


(SP  1)«-PCH 
(SP  2)<-PCL 
PCH  -  0,  PCL-  T 

A  -  A  -  r  CY 
A  -  A  -  n  -  CY 

A  -  A     (HL)  -  CY 
A  -  A  -  (IX  +  d)  -  CY 


A -A     (lY  +  d)  CY 


HL  «   HL    ss  CY 


CY  -  1 
(HLL  -1 


Rotate  location  (HL)  left  circular 
Rotate  location  (IX  +  d)  left  circular 


Rotate  location  (IY  +  d)  left  circular 


Rotate  Reg  r  left  circular 
Rotate  left  circular  ACC 


Rotate  digit  left  and  right  between 
ACC  and  location  (HL) 


Rotate  right  through  carry  Reg  r 
Rotate  right  through  carry  loc  (HL) 


Rotate  right  through  carry  loc 
(IX  +  d) 


Rotate  right  through  carry  loc 
(IY  +  d) 


Rotate  right  ACC  through  carry 

Rotate  Reg  r  right  circular 
Rotate  loc  (HL)  right  circular 
Rotate  loc  ( I X  +  d)  right  circular 

Rotate  loc  (I Y  +  d)  right  circular 
Rotate  right  circular  ACC 


Rotate  digit  right  and  left  between 
ACC  and  location  (HL) 


Restart  to  location  T 


Subtract  Reg  r  from  ACC  w/carry 
Subtract  value  n  from  ACC  with 
carry 

Sub  loc  (HL)  from  ACC  w/carry 
Subtract  loc  (IX  +  d)  from 
ACC  with  carry 

Subtract  loc  (IY  +  d)from 
ACC  with  carry 

Subtract  Reg  pair  ss  from  HL  with 
carry 

Set  carry  flag  (C  =-  1 ) 
Set  Bit  b  of  location  (HL) 

Set  Bit  b  of  location  (IX  +  d) 


7 
19 


15 
23 


!  t 
I  I 


p  :  0  0 
p    1     0  0 


p  I 

0 

0 

11 

101 

101 

01 

101 

111 

p  1 

0 

0 

11 

001 

011^ 

00 

011 

P  ! 

0 

0 

11 

001 

011 

00 

011 

1 10 

P  1 

0 

0 

11 

01 1 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

011 

110 

P  1 

0 

0 

11 

111 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

011 

1 10 

•  • 

0 

0 

00 

011 

111 

P  i 

0 

0 

11 

001 

01  A 

00 

001 

P  I 

0 

0 

11 

001 

011 

00 

001 

110 

P  ! 

0 

0 

11 

011 

101 

001 

011 

dd 

ddd 

ddd 

00 

001 

1 10 

P  ! 

0 

0 

1 1 1 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

001 

110 

•  • 

0 

0 

00 

001 

111 

p  : 

0 

0 

1 1 

101 

101 

01 

100 

111 

1 1 

1 1 1 

111 

11  001  011 
00  000 


00   000  111 


® 


,® 


1® 


10 

011 

rrr® 

11 

011 

110 

nnn 

10 

011 

110 

11 

011 

101 

10 

011 

110 

da 

ddd 

ddd 

11 

111 

101 

10 

011 

110 

dd 

ddd 

ddd 

11 

101 

101® 

01 

ssO 

010 

00 

110 

111 

11 

001 

011® 

11 

bbb 

110 

11 

011 

101© 

11 

001 

011 

dd 

ddd 

ddd 

11 

bbb 

110 

5-9 


,xPD780/780-1/780-2 

Instruction  Set  (Cont.) 


MNEMONIC 


SYMBOLIC 
OPERATION 


DESCRIPTION 

NO 

NO  T 

FLAGS 

OPCODE 

BYTES 

STATES 

C     Z     P/V  S 

N 

H 

76 

543 

210 

Set  Bit  b  of  location  (IY  +  d) 

4 

23 

1 1 

1 1 1 

101  ^-^ 

1 1 

001 

01 1 

dd 

ddd 

ddd 

1 1 

bbb 

110 

Set  Bit  b  of  Reg  r 

2 

8 

11 

001 

011® 

11 

bbb 

rrr 

011® 

Shift  Reg  r  left  arithmetic 

8 

P 

1 1 

001 

00 

100 

Shift  loc  (HL)  left  arithmetic 

15 

It  PI 

o 

o 

11 

001 

011 

00 

100 

110 

Shift  loc  (IX  +  d)  left  arithmetic 

23 

!      1       P  1 

0 

0 

11 

011 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

100 

110 

Shift  loc  (lY  +  d)  left  arithmetic 

23 

1      1       P  1 

0 

0 

11 

111 

101 

11 

001 

01 1 

dd 

ddd 

ddd 

00 

100 

110 

Shift  Reg  r  right  arithmetic 

I      1       P  I 

0 

0 

1 1 

001 

mi® 
01 1v 

Shift  loc  (HL)  right  arithmetic 

15 

IIP! 

11 

001 

011 

00 

101 

110 

Shift  loc  (IX  +  d)  right  arithmetic 

23 

I      I       P  1 

0 

0 

11 

011 

101 

11 

001 

011 

dd 

HHd 

ddd 

00 

101 

110 

Shift  loc  (IY  +  d)  right  arithmetic 

23 

1      I       P  I 

0 

0 

11 

111 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

101 

110 

Shift  R      r  r   h   I     i  I 
it    eg  r  rig  t  ogica 

8 

I      1       P  I 

1 1 

001 

011® 

00 

1 1 1 

Shift  loc  (HL)  right  logical 

15 

11  PI 

o 

o 

11 

001 

011 

00 

111 

110 

Shift  loc  (IX  +  d)  right  logical 

23 

1      1       P  I 

0 

0 

11 

011 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

111 

110 

Shift  loc  (IY  +  d)  right  logical 

23 

I      I       P  1 

0 

0 

11 

111 

101 

11 

001 

011 

dd 

ddd 

ddd 

00 

111 

110 

Subtract  Reg  r  from  ACC 

4 

J      I  VI 

1 

J 

10 

010 

rrr® 

Subtract  value  n  from  ACC 

7 

:    i  vi 

1 

I 

11 

010 

110 

nn 

nnn 

nnn 

Subtract  loc  (HL)  from  ACC 

7 

1      t       V  1 

1 

I 

10 

010 

110 

Subtract  loc  (IX  +  d)  from  ACC 

19 

II       V  J 

1 

I 

11 

011 

101 

10 

010 

110 

dd 

ddd 

ddd 

Subtract  loc  (IY  +  d)  from  ACC 

19 

II       V  I 

1 

I 

11 

1 1 1 

101 

10 

010 

110 

dd 

ddd 

ddd 

Exclusive 'OR' Reg  r  and  ACC 

4 

IIP] 

1 

I 

10 

101 

rrr® 

Exclusive  'OR'  value  n  and  ACC 

7 

I      I       p  I 

1 

11 

101 

110 

nnn 

nnn 

Exclusive 'OR' loc  (HL)  and  ACC 

7 

I    I     p  I 

1 

I 

10 

101 

110 

Exclusive 'OR' loc  (IX  +  d)  and  ACC 

19 

1    I     p  I 

1 

I 

11 

011 

101 

10 

101 

110 

dd 

ddd 

ddd 

Exclusive 'OR' loc  (IY+d)andACC 

19 

t      I      p  I 

1 

I 

11 

111 

101 

10 

101 

110 

dd 

ddd 

ddd 

SET  b,  (IY  +  d) 

SET  b,  r 

SLA  r 
SLA  (HL) 
SLA  (IX  +  d) 


SRA  r 
SRA  (HL) 
SRA  (IX  +  d) 


SRL  r 
SRL  (HL) 
SRL  (IX  +  d) 


SUB  r 
SUB  n 


SUB  (HL) 
SUB  (IX  +  d) 


XOR  r 
XOR  n 


XOR  (HL) 
XOR  (IX  +  d) 


XOR  (IY  +  d) 


[cy]^-|~7  -  0  |^-0 
=  r,  (HL),  (IX  +d),  (IY  +d) 


ms  r,  (HL),  (IX  +  d).  (IY  +  d) 


0-H  7-0 


r,  (HL),  (IX  +  d),  (IY  +  d) 


A  «-  A  -  (HL) 
A  «-  A  -  (IX  +  d) 


A  «-  A  -  (IY  +d) 


A  <-  AVr 
A  *-  AVn 


A  *~  AY  (HL) 
A  -  AVOX  +d) 


FLAG  NOTES. 


(2)  Z=1  if  A=(HL),else  Z=0 

(3)  If  B-1=0,  Z  flag  set,  else  reset 
FLAG  DEFINITIONS 

•  =  Flag  not  affected 

0  =  Flag  reset 

1  =  Flag  set 
X  =  Flag  unknown 

t  =  Flag  affected  according  to  result  of  operation 
V  =  Overflow  set 

P  =  Parity  set 
IFF  =  Interrupt  flip-flop  set 


® 

® 

© 

© 

© 

© 

© 

CD 

Reg  s  s 

Reg  r 

Reg  pp 

Reg  r  r 

Bit  b 

Reg  r,r' 

Reg  qq 

cc 

Condition 

Relevant  Flag 

Reg  r 

BC  00 

A 

111 

BC  00 

BC  00 

0 

000 

A 

111 

BC  00 

000 

NZ 

Non  Zero 

Z 

B 

000 

DE  01 

B 

000 

DE  01 

DE  01 

1 

001 

B 

000 

DE  01 

001 

Z 

Zero 

Z 

C 

001 

HL  10 

C 

001 

IX  10 

IY  10 

2 

010 

C 

001 

HL  10 

010 

NC 

IMon  Carry 

c 

D 

010 

SP  11 

D 

010 

SP  11 

SP    1 1 

3 

011 

D 

010 

AF  11 

011 

C 

Carry 

c 

E 

011 

E 

011 

4 

100 

E 

011 

100 

PO 

Parity  Odd 

P/V 

H 

100 

H 

100 

5 

101 

H 

100 

101 

PE 

Parity  Even 

P/V 

L 

101 

L 

101 

6 

110 

L 

101 

110 

P 

Sign  Positive 

S 

F 

110 

7 

111 

111 

M 

Sign  Negative 

S 

A 

111 

FLAG  DESCRIPTION 

C  =  Carry/Link 
Z  =  Zero 
P/V  =  Parity/Overflow 


S  =  Sign 

N  =  Add/Subtract 
H  =  Half  Carry 


5-10 


Timing  Waveforms 

Input  and  output  cycles 

In  I/O  operations,  a  single  wait  state  (Tw)  is  automatically 
included  to  provide  adequate  time  for  an  I/O  port  to  decode 
the  address  from  the  port  address  lines  and  initiate  a  wait 
condition  if  needed. 

Input  Cycle 


A„-A7 


IORQ  - 


D0-D7- 


■*""*■  tDL<l>(RD) 


Output  Cycle 


A0-A7_ 
IORQ - 

WR  - 


M. 


fjiPD780/780-1/780-2 


Opcode  fetch  instruction  cycle 

At  the  beginning  of  the  cycle,  the  contents  of  the  program 
counter  are  placed  on  the  address  bus.  After  approximately 
one-half  cycle,  MREQ  is  asserted  and  its  falling  edge  can 
be  used  directly  by  the  external  memory  as  a  chip  enable 
signal.  The  data  from  the  external  memory  can  be  gated 
onto  the  data  bus  when  RD  is  asserted.  The  CPU  reads 
the  data  at  the  rising  edge  of  T3.  During  T3  and  T4,  exter- 
nal dynamic  memory  is  refreshed  while  the  instruction  is 
decoded  and  executed.  The  assertion  of  RFSH  indicates 
that  the  external  dynamic  memory  requires  a  refresh  read. 


M1  Cycle 


J — \ 


»D(AD)  tACM 


Ao_Ai5_ 
MREQ  - 

RD  - 

D0-D7. 
H,- 

RFSH- 


-M.,  Cycle- 


1  u-t, 

WT)U-d 

TT. 


^DH<t>(MR)  ■ 


ts<J>(D)L 


Refresh  Address  X" 


V(MRL)  •yf' 


J 


D0-D7- 


5- 


11 


,PD 780/780-1  780-2 

Timing  Waveforms  (Cont.) 

Memory  read  or  write  cycles 


In  read  and  write  operations,  the  MREQ  and  RD  signals 
function  the  same  as  they  do  in  opcode  fetch  operations. 
In  a  write  operation  MREQ  is  asserted  and  can  be  used 
directly  by  external  memory  as  a  chip  enable  signal  when 


information  on  the  address  bus  is  stable.  The  WR  signal 
is  used  as  a  write  strobe  to  almost  any  type  of  semicon- 
ductor memory,  and  is  asserted  when  data  on  the  data 
bus  is  stable. 


Ao-A, 


Interrupt  request/acknowledge  cycle 

The  interrupt  signal  is  sampled  at  the  rising  edge  of  the  final  address  can  be  placed  on  the  data  bus  by  the  interrupting 

clock  pulse  at  the  end  of  an  instruction.  When  an  interrupt  device.  This  cycle  includes  the  automatic  addition  of  two 

is  accepted,  an  M1  cycle  is  begun.  Instead  of  MREQ,  IORQ  wait  states  to  facilitate  the  implementation  of  a  daisy-chain 

is  asserted  during  this  cycle  to  indicate  that  an  8-bit  vector  priority  interrupt  protocol . 


Last  M  Cycle  of  instruction  - 


WO}*-* 

INT  "A 


/  


~)(Befresh  Address 


J. 


ts*(D)U 


ntDHc|><IF 
'  


tDH<MO 


5-12 


Standard  Test  Conditions 

The  standard  test  conditions  reference  all  voltages  to 
ground  (OV)  and  follow  the  convention  that  positive  current 
flows  into  the  referenced  pin.  The  listing  of  AC  parameters 
is  based  on  a  load  capacitance  of  50pF  unless  explicitly 
stated  otherwise.  For  every  50pF  increase  in  load  capaci- 
tance there  is  a  10ns  delay,  up  to  a  maximum  increase  of 
200pF  for  the  data  bus  and  100pF  for  the  address  bus  and 
the  bus  control  lines. 

The  operating  temperature  range  is:   0°C  to  +  70°C; 
+  4.75V  <  Vcc<  +  5.25V. 


Absolute  Maximum  Ratings* 


Ta  =  25°C 

Operating  Temperature 

0°Cto  +70°C 

Storage  Temperature 

-65°Cto  +150°C 

Voltage  on  any  Pin 

-0.3V  to  +7V© 

Power  Dissipation 

1.5w 

Note:  ©  With  respect  to  ground 

*  COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be 
operated  under  conditions  outside  the  limits  described 
in  the  operational  sections  of  this  specification.  Expo- 
sure to  absolute  maximum  rating  conditions  for 
extended  periods  may  affect  device  reliability. 

DC  Characteristics 

Ta  =  0°C  to  +70°C;  Vcc  = 

+  5V  ± 

5%  unless 

otherwise  specified. 

Limits 

Parameter  Symba 

1  Min 

Typ  Max 

Unit  Test  Conditions 

Clock  Input  Low  Voltage  V,LC 

-0.3 

0.45 

V 

Clock  Input  High  Voltage  V,HC 

Vcc 
-0.6 

Vcc 
+0.3 

V 

Input  Low  Voltage  VIL 

-0.3 

0.8 

V 

Input  High  Voltage  V,H 

2.0 

Vcc 

V 

Output  Low  Voltage  VOL 

0.4 

V    lOL  =  1.8mA 

Output  High  Voltage  VOH 

2.4 

V    lOH  =  -250ftA 

Power  Supply  nPD780  lcc 

150 

mA  tc  =  400ns 

Current          ^PD780-1  lcc 

90  200 

mA  tc  =  250ns 

Input  Leakage  Current  lu 

10 

^A   V1N  =  0toVcc 

Three-state  Output  Leakage  , 
Current  in  Float  'loh 

10 

„A  VOOT  =  2.4 
toVcc 

Three-state  Output  Leakage  . 
Current  in  Float  lol 

-10 

M-A    VOUT  =  0.4V 

Data  Bus  Leakage  Current  . 
in  Input  Mode  LD 

±10 

-  vcc 

liPD780/780-1/780-2 

Load  Circuit  for  Output 


FROM  OU 
UNDER 


Capacitance 

Ta  =  25°C 


Parameter 

Symbol  M 

Limits 
in  Typ 

Max 

Unit 

Test  Conditions 

Clock  Capacitance 

35 

PF 

fc  =  1MHz 

Input  Capacitance 

5 

PF 

Unmeasured  pins 

Output  Capacitance 

Cqot 

10 

pF 

returned  to  ground. 

5-13 


,PD780/780-1/780-2 


AC  Characteristics 

=  0°C  to  +  70°C:  Vcc  —  +  5V  ±  5%,  unless  otherwise  specified. 

  Limits 


yPD780  MPD780-f  MPD780-2 


Parameter 

Symbol 

Min 

Max 

Min 

Max 

Min 

Max 

Unit 

Test  Conditions 

Clock  Period 

0.4 

© 

0.25 

© 

0.165 

© 

(AS 

Clock  Pulse  Width,  Clock  High 

tw(4>H) 

180 

© 

110 

© 

65 

© 

ns 

Clock  Pulse  Width,  Clock  Low 

tw(<J>L) 

180 

2000 

110 

2000 

65 

2000 

ns 

Clock  Rise  and  Fall  Time 

tRf 

30 

30 

20 

ns 

Address  Output  Delay 

*D(AD) 

145 

110 

90 

ns 

Delay  to  Float 

*F(AD) 

110 

90 

80 

ns 

Address  Stable  Prior  to  MREQ  (Memory  Cycle) 

*ACM 

® 

® 

© 

ns 

Address  Stable  Prior  to  IORQ,  RD  or  WR  (I/O  Cycle) 

lACI 

© 

© 

© 

ns 

CL  =  50pF 

Address  Stable  from  RD  or  WR 

tCA 

© 

© 

© 

ns 

Address  Stable  from  RD  or  WR  during  Float 

*CAF 

© 

© 

© 

ns 

Data  Output  Delay 

^(D) 

230 

150 

130 

ns 

Delay  to  Float  during  Write  Cycle 

*F(D) 

90 

90 

80 

ns 

Data  Setup  Time  to  Rising  Edge  of  Clock  during  M1  Cycle 

lS<t>(D) 

50 

35 

30 

ns 

Data  Setup  Time  to  Failing  Edge  of  Clock  during  M2  to  M5  Cycles 

lS*(D) 

60 

50 

40 

ns 

Cu  =  200pF 

Data  Stable  prior  to  WR  (Memory  Cycle) 

*DCM 

® 

® 

© 

ns 

Data  Stable  prior  to  WR  (I/O  Cycle) 

lDCI 

® 

© 

© 

ns 

Data  Stable  from  WR 

lCDF 

® 

© 

© 

ns 

BUSRQ  Setup  Time  to  Rising  Edge  of  Clock 

lS(BQ) 

80 

50 

50 

ns 

BUSAK  Delay  from  Rising  Edge  of  Clock  to  BUSAK  Low 

^DL(BA) 

120 

100 

90 

ns 

CL  =  50pF 

BUSAK  Delay  from  Falling  Edge  of  Clock  to  BUSAK  High 

^DH(BA) 

110 

100 

90 

ns 

Delay  to  Float  (MREQ,  IORQ,  RD  and  WR) 

*F(C) 

100 

80 

70 

ns 

Mi  Stable  Prior  to  IORQ  (Interrupt  Ack.) 

*MR 

® 

® 

® 

ns 

Any  Hold  Time  for  Setup  Time 

*H 

0 

0 

0 

ns 

HALT  Delay  Time  from  Falling  Edge  of  Clock 

tD(HT) 

300 

300 

260 

ns 

CL  =  50pF 

INT  Setup  Time  to  Rising  Edge  of  Clock 

^(IT) 

80 

80 

70 

ns 

IORQ  Delay  from  Rising  Edge  of  Clock  to  IORQ  Low 

*DL<MIR) 

90 

75 

65 

ns 

IORQ  Delay  from  Falling  Edge  of  Clock  to  IORQ  Low 

lDL^(IR) 

110 

85 

70 

ns 

IORQ  Delay  from  Rising  Edge  of  Clock  to  IORQ  High 

*DH<t>(IR) 

100 

85 

70 

ns 

IORQ  Delay  from  Falling  Edge  of  Clock  to  IORQ  High 

*Dh£(IR) 

110 

85 

70 

ns 

CL  =  50pF 

Mi  Delay  from  Rising  Edge  of  Clock  to  Ml,  Low 

tDL(Mi) 

130 

100 

80 

ns 

Delay  from  Rising  Edge  of  Clock  to  High 

tDH(M-i) 

130 

100 

80 

ns 

MREQ  Delay  from  Falling  Edge  of  Clock  to  MREQ  Low 

^DL<j>(MR) 

100 

85 

70 

ns 

MREQ  Delay  from  Rising  Edge  of  Clock  to  MREQ  High 

tDHcMMR) 

100 

85 

70 

ns 

MREQ  Delay  from  Falling  Edge  of  Clock  to  MREQ  High 

*Dh£(MR) 

100 

85 

70 

ns 

Pulse  Width,  MREQ  Low 

*w(MRL) 

© 

© 

© 

ns 

Pulse  Width,  MREQ  High 

lw(MRH) 

© 

© 

© 

ns 

Pulse  Width,  NMI  Low 

*W(NMI) 

80 

80 

70 

ns 

RESET  Setup  Time  to  Rising  Edge  of  Clock 

*S(RS) 

90 

60 

60 

ns 

RD  Delay  from  Rising  Edge  of  Clock  to  RD  Low 

*DL<MRD) 

100 

85 

70 

ns 

RD  Delay  from  Falling  Edge  of  Clock  to  RD  Low 

*DL*(RD) 

130 

95 

80 

ns 

RD  Delay  from  Rising  Edge  of  Clock  to  RD  High 

*DH<t>(RD) 

100 

85 

70 

ns 

RD  Delay  from  Falling  Edge  of  Clock  to  RD  High 

^DH<j>(RD) 

110 

85 

70 

ns 

RFSH  Delay  from  Rising  Edge  of  Clock  to  RFSH  Low 

tDL(RF) 

180 

130 

110 

ns 

CL  =  30pF 

RFSH  Delay  from  Rising  Edge  of  Clock  to  RFSH  High 

*DH(RF) 

150 

120 

100 

ns 

WAIT  Setup  Time  to  Falling  Edge  of  Clock 

^(WT) 

70 

70 

60 

ns 

WR  Delay  from  Rising  Edge  of  Clock  to  WR  Low 

^DL<)>(WR) 

80 

65 

60 

ns 

WR  Delay  from  Falling  Edge  of  Clock  to  WR  Low 

tDL^CWR) 

90 

80 

70 

ns 

WR  Delay  from  Falling  Edge  of  Clock  to  WR  High 

^DH<j>(WR) 

100 

80 

70 

ns 

Pulse  Width  to  WR  Low 

tw(WRL) 

@ 

© 

© 

ns 

®  tc  =  tw(<f>H)  +  tw(cf>L)  +  tR  +  tF 

©  Though  the  structure  of  the  780  is  static,  200(xs  is  a  guaranteed  maximum 

®  *ACM  =  U*H)  +  tF  -  65  (75)*  (50)** 

®  tACi  =  ^  ~  70  (80)*  (55)** 

®  kjA  =  W*L)  +  tR  -  50  (40)*  (50)** 

®  tcAF  =  tw(<t>L)  +  tR  -45  (60)*  (40)** 

®  tDCM  =  tc-  170(210)*(140)** 

®  tuci  =  tw(<W  +  tR  -  170  (210)*  (140)** 

®  tcDF  =  tw(W  +  tR  -  70  (80)*  (55)** 

®  tMR  =  2tc  +  tw(<})H)  +  tF  -  65  (80)*  (50)** 

©  tw(MRL)  =  tc  -  30  (40)*  (30)** 

©  tw(MRH)  =  tw(<j)H)  +  tF  -  20  (30)*  (20)** 

©  tw(WR)  =  tc  -  30  (40)*  (30)** 

*  These  values  apply  to  the  |xPD780 

**  These  values  apply  to  the  (xPD780-2 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD780C 
Ceramic,  fxPD780D 


780/780-1/780-2DS-Rev  2-7-83-CAT-L 


5-14 


MPD8085AH 
MPD8085A-2 


/1PD8085A  SINGLE  CHIP  8-BIT 
N-CHANNEL  MICROPROCESSOR 


DESCR IPTION     The  /iPD8085A  is  a  single  chip  8-bit  microprocessor  which  is  100  percent  software 
compatible  with  the  industry  standard  8080A.  It  has  the  ability  of  increasing  system 
performance  of  the  industry  standard  8080A  by  operating  at  a  higher  speed  Using 
the  juPD8085A  in  conjunction  with  its  family  of  ICs  allows  the  designer  complete 
flexibility  with  minimum  chip  count. 

FEATURES     •  Single  Power  Supply:  +5  Volt,  ±10% 

•  Internal  Clock  Generation  and 
System  Control 

•  Internal  Serial  In/Out  Port. 

•  Fully  TTL  Compatible 

•  Internal  4-Level  Interrupt  Structure 

•  Multiplexed  Address/Data  Bus  for 
Increased  System  Performance 

•  Complete  Family  of  Components  for 
Design  Flexibility 

•  Software  Compatible  with  Industry  Standard  8080A 

•  Higher  Throughput.  juPD8085AH  -  3  MHz 

juPD8085A-2-5MHz 

•  Available  in  Either  Plastic  or  Ceramic  Package 


PIN  CONFIGURATION 


Xi  C 
x2C 

ROC 

sodC 

SID  C 
TRAP  C 
RST  7  5  C 
RST  6.5  C 
RST  5  5  C 
INTR  C 
INTA  C 
ADqC 
AD,  c 

AD2C 
AD3C 
AD4C 
AD5C 
AD6C 
AD7C 

vssC 


flPD 
8085A 


40  □ 
□ 
□ 
□ 
□ 
□ 

3 


39 
38 
37 
36 
35 
34 
33 

32  p 

31 
30 
29 
28 
27 
26 

25  D 
24 

23 
22 
21 


VCC 

HOLD 

HLDA 

CLK  (OUT) 

RESET  IN 

READY 

IO/M 

Sj_ 

RD 

WR 

ALE 

S0 

A15 

A14 

A13 
A12 
A11 
A10 

Ag 

A8 


Rev/5 


5-15 


MPD8085A 


The  AtPD8085A  contains  six  8-bit  data  registers,  an  8-bit  accumulator,  four  testable  FUNCTIONAL 
flag  bits,  and  an  8-bit  parallel  binary  arithmetic  unit.  The  AiPD8085A  also  provides  DESCRIPTION 
decimal  arithmetic  capability  and  it  includes  16-bit  arithmetic  and  immediate  operators 
which  greatly  simplify  memory  address  calculations,  and  high  speed  arithmetic 
operations. 

The  //PD8085A  has  a  stack  architecture  wherein  any  portion  of  the  external  memory 
can  be  used  as  a  last  in/first  out  (LIFO)  stack  to  store/retrieve  the  contents  of  the 
accumulator,  the  flags,  or  any  of  the  data  registers. 

The  //PD8085A  also  contains  a  16-bit  stack  pointer  to  control  the  addressing  of  this 
external  stack.  One  of  the  major  advantages  of  the  stack  is  that  multiple  level  inter- 
rupts can  easily  be  handled  since  complete  system  status  can  be  saved  when  an  inter- 
rupt occurs  and  then  restored  after  the  interrupt  is  complete.  Another  major  advantage 
is  that  almost  unlimited  subroutine  nesting  is  possible. 

The/iPD8085A  was  designed  with  speed  and  simplicity  of  the  overall  system  in  mind. 
The  multiplexed  address/data  bus  increases  available  pins  for  advanced  functions  in  the 
processor  and  peripheral  chips  while  providing  increased  system  speed  and  less  critical 
timing  functions.  All  signals  to  and  from  the  juPD8085A  are  fully  TTL  compatible. 

The  internal  interrupt  structure  of  the  /iPD8085A  features  4  levels  of  prioritized 
interrupt  with  three  levels  internally  maskable. 

Communication  on  both  the  address  lines  and  the  data  lines  can  be  interlocked  by  using 
the  HOLD  input.  When  the  Hold  Acknowledge  (HLDA)  signal  is  issued  by  the  pro- 
cessor, its  operation  is  suspended  and  the  address,  data  and  control  lines  are  forced  to  be 
in  the  FLOATING  state.  This  permits  other  devices,  such  as  direct  memory  access 
channels  (DMA),  to  be  connected  to  the  address  and  data  busses. 

The  //PD8085A  features  internal  clock  generation  with  status  outputs  available  for 
advanced  read/write  timing  and  memory/IO  instruction  indications.  The  clock  may  be 
crystal  controlled,  RC  controlled,  or  driven  by  an  external  signal. 

On  chip  serial  in/out  port  is  available  and  controlled  by  the  newly  added  RIM  and  SIM 
instructions. 


5-16 


MPD8085A 


PIN  IDENTIFICATION 


PIN 

NO 

SYMBOL 

NAME 

FUNCTION 

1.  2 

XL  x2 

Crystal  In 

Crystal,  RC,  or  external  clock  input  , 

3 

RO 

Reset  Out 

Acknowledge  that  the  processor  is  being  reset  to  be  ' 
used  as  a  system  reset 

4 

SOD 

Serial  Out  Data 

1  bit  data  out  by  the  SIM  instruction 

5           ]  SID 

Serial  In  Data 

1  bit  data  into  ACC  bit  7  by  the  RIM  instruction 

6  Trap 

Trap  Interrupt 
Input 

Highest  priority  nonmaskable  restart  interrupt 

7  RST  7  5 

8  |      RST 6 5 

9  RST  5  5 

Restart 
Interrupts 

Priority  restart  interrupt  inputs,  of  which  7  5  is  the 
highest  and  5  5  the  lowest  priority 

10 

INTR 

Interrupt 
Request  In 

A  general  interrupt  input  wh.ch  stops  the  PC  from 
incrementing,  generates  INTA,  and  samples  the  data 
bus  for  a  restart  or  call  instruction 

11 

INTA 

Interrupt 
Acknowledge 

An  output  which  indicates  that  the  processor  has 
responded  to  INTR 

12-19  AD0-AD7 

Low 

Address/Data  Bus 

Multiplexed  low  address  and  data  bus 

20  VSS 

Ground 

Ground  Reference 

21-28  Ag-A15 

High  Address  Bus 

Nonmultiplexed  high  8-bits  of  the  address  bus 

29,  33           S0,  Si 

Status  Outputs 

Outputs  which  indicate  data  bus  status    Halt,  Write, 
Read,  Fetch 

30  ALE 

Address  Latch 
Enable  Out 

A  signal  which  indicates  that  the  lower  8-bits  of 

31,  32 

WR,  RD 

Write/Read 
Strobes  Out 

Signals  out  which  are  used  as  write  and  read  strobes 
for  memory  and  I/O  devices 

34 

IO/M 

I/O  or  Memory 
Indicator 

A  signal  out  which  indicates  whether  RD  or  WR 
strobes  are  for  I/O  or  memory  devices 

35  Ready 

I 

Ready  Input 

An  input  which  is  used  to  increase  the  data  and 
address  bus  access  times  (can  be  used  for  slow 
memory) 

36 

Reset  In 

Reset  Input 

An  input  which  is  used  to  start  the  processor  activity 
at  address  0,  resetting  IE  and  HLDA  flip  flops 

•-2Z  j 

CLK 

Clock  Out                !     System  Clock  Output 

38,  39 

HLDA,  HOLD 

Hold  Acknowledge 
Out  and  Hold 
Input  Request 

Used  to  request  and  indicate  that  the  processor  should 
relinquish  the  bu,s  for  DMA  activity  When  hold  is 
acknowledged,  RD,  WR,  IO/M,  Address  and  Data 
busses  are  all  3  stated 

40 

vCc 

5V  Supply 

Power  Supply  Input 

ABSOLUTE  MAXIMUM 
RATINGS* 


Operating  Temperature . 
Storage  Temperature 


Voltage  on  Any  Pin 
Power  Dissipation 


0  C  to  +70  C 
-65°Cto  +150°C 


-0.5  to  +7  Volts 
.  1.5W 


DC  CHARACTERISTICS 


Ta  =  25  C;  VCC  =  ±5V  ±  5%,  8085A-2 

"COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 

Ta  =  0°C  to  +70°C,  Vcc  =  +5V  ±  10%,  Vss  =  GND,  unless  otherwise  specified 


LIMITS 

TEST 

PARAMETER 

SYMBOL 

MIN 

MAX 

UNIT 

CONDITIONS 

Input  Low  Voltage 

VlL 

VSs  -  0  5 

VSS  +  0  8 

V 

Input  High  Voltage 

VlH 

20 

VCC  +  0  5 

V 

Output  Low  Voltage 

VOL 

0  45 

V 

 — 

Iql  =  2  mA  on  all  outputs 

Output  High  Voltage 

V0H 

24 

V 

Iqh  =  "4°0  MS  © 

Power  Supply  Current  (Vcc' 

ICC  <AV) 

170 

mA 

tCY  mm  (8085A-2) 

Maximum  Unit  Test 

135 

mA 

tCY  mm  (8085AH) 

Input  Leakage 

'IL 

,10© 

MA 

0  <  V|n  <  Vcc 

Output  Leakage 

'LO 

,10© 

*iA 

0  45V  <  V0UT  <  VCC 

Input  Low  Level,  Reset 

VlLR 

-0  5 

+0  8 

V 

Input  High  Level,  Reset 

V|HR 

24 

VCC  +  0  5 

V 

Hysteresis,  Reset 

VHY 

0  25 

V 

X1(  X2  Input  Voltage  High 

VIHX 

4.0 

Vcc  +  05 

V 

Note   ©  Minus  (-)  designates  current  flow  out  of  the  devic 

5-17 


MPD8085A 

Ta  =  0°Cto  +70°C;VCC  = 


5V  ±  5%,  8085A-2 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

D8085AH 

MPD8085A-2 

MIN 

MAX 

MIN 

MAX 

CLK  Cycle  Period 

'CYC 

320 

2000 

200 

2000 

ns 

CLK  Time  Low 

'1 

80 

40 

ns 

CLK  Time  High 

«2 

120 

70 

ns 

CLK  Rise  and  Fall  Time 

tr,tf 

30 

30 

ns 

Xi  Rising  to  CLK  Rising 

'XKR 

30 

120 

50 

ns 

Xi  Rising  to  CLK  Falling 

'XKF 

30 

150 

80 

ns 

As- 15  Valid  to  Leading  Edge  of  CONTROL  (D 

'AC 

^~ 

ns 

A70  Valid  to  Leading  Edge  of  CONTROL 

'ACL 

60 

ns 

^0-15  Valid  to  Data  in 

|AD  

 - 

Address  Float  after  Leading  Edge  of  R~D(INTA) 

^FR  

— — 

~350" 

— ^  

tht 

— — 

— — 

Ao  rvah7beto?er  TLTn'^EdgrorALE6  ^  



_ALL  

~~ 90~~ 

READY  Valid  from  Address  Valid 

j^RY  

^8-15  Valid  after  CONTROL 

_CA  

lio" 

60 

Width  of  Control  Low  (RD,  WR,  INTA) 

_cc  

w 

230 

Trailing  Edge  of  CONTROL  to  Leading  Edge 
of  ALE 

CL 

"so" 

25 

ns 

Data  Valid  to  Trailing  Edge  of  WR" 

<DW 

ns 

HLDA  to  Bus  Enable 

'HABE 

210 

150 

ns 

Bus  Float  After  HLDA 

210 

150 

HLDA  Valid  to  Trailing  Edge  of  CLK 

t 

"TTo" 

_ 40- 

ns 

HOLD  Hold  Time 

t"A^K 

— - 

ns 

HOLD  Setup  Time  to  Trailing  Edge  of  CLK 

<HD 

_HD  

170 

' — ns  

INTR  Hold  Time 

JNH  

INTR.RST.TRAP  Setup  Time  to  Failing  Edge  of  CLK 

JN§  

"7io~ 

lio" 

' — ns  

Address  Hold  Time  After  ALE 

100 

115 

ns 

CONTROL9 

<LC  

130 

120 

— —  

ALE  Low  Time  during  CLK  High 

|LCK  

~iob~ 

— ^— 

— ^  

ALE  to  Valid  Data  in  during  Read 

460 

270 

— ^  

ALE  to  Valid  Data  during  Write 

<LDW  

200 

0 

ALE  Pulse  Width 

t|j_ 

ns 

ALE  to  READY  stable 

'lry 

110 

30 

110 

'rae 

150 

20 

RD  (or  INTA)  to  Valid  Data 

'RD 

300 

50 

ns 

Trailing  Edge  of  CONTROL  to  Leading  Edge  of 
next  CONTROL 

<RV 

400 

50 

ns 

Data  Hold  Time  after  RD  (INTA)(7) 

'RDH 

0 

120 

READY  Hold  Time 

'RYH 

0 

30 

READY  Set  up  Time  to  Leading  Edge  of  CLK 

'RYS 

110 

115 

Leading  Edge  Data  Valid  After  Trailing  Edge 
of  WR 

'WD 

100 

40 

ns 

Leading  Edge  of  WR  to  Data  Valid 

'WDL 

40 

AC  CHARACTERISTICS 


Notes:  ®  A8-A15  address  specs  apply  to  IO/M  SO  and  S1  except  A8-A15  are  undefined  during  T4-T6 
of  OF  cycle  whereas  IO/M,  SO  and  S1  are  stable 

(2)  Test  Conditions  tCYc  =  320  ns  (8085AH)/200  ns  (8085A-2) 
CL  =  150  pF 

(D  For  all  output  timing  where  except  C|_  =  150  pF  use  the  following  correction  factors 
25  pF   CL   150  pF  -0  10ns/pF 

150  pF   CL   300  pF  +0  3  ns/pF 
<$)  Output  Timings  are  measured  with  purely  capacitive  load 
(f)  All  timings  are  measured  as  the  following, 

Output  Voltage  VL  =  0  8V,  VH  =  2  0V 

Input  Voltage     1  5V,  tr,  tf  =  20  ns 
©  To  calculate  timing  specifications  at  other  values  of  t^yc  use  Table  1 
(2)  Data  hold  time  is  guaranteed  under  all  loading  conditions 


Tcyc  as  a  dependent  BUS  TIMING  SPECIFICATIONS 


M.PD8085AH 

(xPD808A-2 

tAL 

(1/2)T  -  45 

(1/2)T  -  50 

tLA 

(1/2)T  -  60 

(1/2)T  -  50 

tLL 

(1/2)T  -  20 

(1/2)T  -  20 

tLCK 

(1/2)T  -  60 

(1/2)T  -  50 

Tlx 

(1/2)T  -  30 

(1/2)T  -  40 

tAD 

(5/2  +  N)T  -  225 

(5/2  +  N)T  -  150 

max 

tRD 

(3/2  +  N)T  -  180 

(3/2+  N)T  -  150 

tRAE 

(1/2)T  -  10 

(1/2)T  -  10 

mm 

tCA 

(1/2)T  -  40 

(1/2)T  -  40 

tow 

(3/2  +  N)T  -  60 

(3/2  +  N)T  -  70 

tWD 

(1/2)T  -  60 

(1/2)T  -  40 

tec 

(3/2  +  N)T  -  80 

(3/2  +  N)T  -  70 

tCL 

(1/2)T  -  110 

(1/2)T  -  75 

tARY 

(3/2)T  -  260 

(3/2  )T  -  200 

tHACK 

(1/2)T  -  50 

(1/2)T  -  60 

tHABF 

(1/2)T  +  50 

(1/2)T  -  50 

tHABE 

(1/2)T  +  50 

(1/2)T  -  50 

max 

tAC 

(2/2  )T  -  50 

(2/2)T  -  85 

t1 

(1/2)T  -  80 

(1  /2)T  -  60 

t2 

(1/2)T  -  40 

(1/2)T  -  30 

mm 

tRV 

(3/2)T  -  80 

(3/2  )T  -  80 

tLDR 

(4/2  +  N)T  -  180 

(4/2  +  N)T  -  130 

Note  N  =  Number  of  WAIT  State 
T  =  tcYC 


5-18 


TIMING  WAVEFORMS 
Clock  Timing  Waveform 

X1  Input 
CLK  Output 


8085AH  Bus  Timing 

Read  Operation 


c  

*LCK 

Jca)  / 

X 

Address 
 1 

Address 

AD  * 

i — mm 

lRDH— »- 

^  Data  In 

;<  

^RAE*- 

*tCL^ — 

tAL 

'afr- *" 

*LUH 

 —tCc  

 -L 

— tLC-* 
tAC — » 

r  f 

T2  |  T3  |  T, 


A8"A15  Address 

-*-ti_Dw-*" 
D0-AD7  ^  r    Address       j  [ 


Hold  Timing 


CLK 
HOLD 


MPD8085A 


HLDA 


\  /    \  t    \  r 


Address  Controls 


Interrupt  and  Hold  Timing 

|     T,     |     T2     |     T3    |     T4     |     T5     |     T6    |  THOLD  |     T,     |  T2 


AD0.7"""X  )  (  Ca  I  INST  ] 

ALE    /  \ 


INTA  \_ 
2*  


tINS  |*W  tINH 
HOLD 


-Bus  Floating- 


Read  Operation  with  Wait  Cycle 

Same  Ready  Timing  Applies  To  Write  Operation 


vao; 

AD0-AD73[ 


ALE 
RD/INTA- 


~\  /  V 


Note:  ©READY  must  remain  stable  during  tRYs  and  tRYH 
(DIO/M  is  also  floating  during  this  time 


5-19 


MPD8085A 


PROCESSOR  STATE 
TRANSITION  DIAGRAM 


SET 
I  NT  A  FF 
RESET 
t!MTE  FF 


Notes:        (T)  Bl  indicates  that  the  bus  is  idle  during  this  machine  cycle. 

(2)  CK  indicates  the  number  of  clock  cycles  in  this  machine  cycle. 


5-20 


MPD8085A 


CLOCK  INPUTS© 


As  stated,  the  timing  for  the  juPD8085A  may  be  generated  in  one  of  three  ways; 
crystal,  RC,  or  external  clock.  Recommendations  for  these  methods  are  shown 
below. 


RC 

X 

1  x2 

< 

■  WA,  1 

_  10K 

20  pF 


^3  MHz  Input  Frequency 
RC  Resonance 


CRYSTAL 


Clock 
In 


*2 


JrHBhl 


+5V 


470  ( 


Clock 
In 


EXTERNAL 


1-6  MHz  Input  Frequency 
Parallel  Resonant  Crystal 

For  1-6  MHz  Input  Frequency, 
C1  =  C2  =  10  pF  max. 

For  6-10  MHz  Input  Frequency, 
C1  =  C2  =  5  pF  max. 


X1 


*2 


4— VW  +5V 

470 


X1 


H>l-M> 


+5V 


1-6  MHz  25-50%  DC 
X2  not  used 


1-6  MHz  >  50%  DC 


Note         Input  frequency  must  be  twice  the  internal  operating  frequency 


STATUS  OUTPUTS     The  Status  Outputs  are  valid  during  ALE  time  and  have  the  following  meaning: 


S1  SO 

Halt  0  0 

Write  0  1 

Read  1  0 

Fetch  1  1 


These  pins  may  be  decoded  to  portray  the  processor's  data  bus  status. 


5-21 


MPD8085A 


The /iPD8085A  has  five  interrupt  pins  available  to  the  user.  INTR  is  operationally  the  INTERRUPTS 
same  as  the  8080  interrupt  request,  three  (3)  internally  maskable  restart  interrupts: 
RESTART  5.5,  6.5  and  7.5,  and  TRAP,  a  non-maskable  restart. 


RESTART 

PRIORITY 

INTERRUPT 

ADDRESS 

Highest 

TRAP 

2416 

1 

RST  7.5 

3C16 

1 

RST  6.5 

3416 

1 

RST  5.5 

2C16 

Lowest 

INTR 

INTR,  RST  5.5  and  RST  6.5  are  all  level  sensing  inputs  while  RST  7.5  is  set  on  a  rising 
edge.  TRAP,  the  highest  priority  interrupt,  is  non-maskable  and  is  set  on  the  rising  edge 
or  positive  level.  It  must  make  a  low  to  high  transition  and  remain  high  to  be  seen,  but 
it  will  not  be  generated  again  until  it  makes  another  low  to  high  transition. 


Serial  input  and  output  is  accomplished  with  two  new  instructions  not  included  in  the 
8080:  RIM  and  SIM.  These  instructions  serve  several  purposes:  serial  I/O,  and  reading 
or  setting  the  interrupt  mask. 


SERIAL  I/O 


The  RIM  (Read  Interrupt  Mask)  instruction  is  used  for  reading  the  interrupt  mask  and 
for  reading  serial  data.  After  execution  of  the  RIM  instruction  the  ACC  content  is  as 
follows: 


SID 

I 

I 

I 

M 

M 

M 

7.5 

6.5 

5.5 

IE 

7.5 

6.5 

5.5 

I  L 


SERIAL 
DATA 
IN 


PENDING 
INTERRUPTS 


INTERRUPT 
MASKS 


INTERRUPT 
ENABLE 


Note:  After  the  TRAP  interrupt,  the  RIM  instruction  must  be  executed  to  preserve  the 
status  of  IE. 


The  SIM  (Set  Interrupt  Mask)  instruction  is  used  to  program  the  interrupt  mask  and  to 
output  serial  data.  Presetting  the  ACC  for  the  SIM  instruction  has  the  following 
meaning: 


SOD 

SOE 

X 

R 

MSE 

M 

M 

M 

7.5 

7.5 

6.5 

5.5 

SERIAL 
OUT 
DATA 


SERIAL 
OUT 
DATA 
ENABLE 
(1  =  ENABLE) 


RESET 
RST  7.5 
ENABLE 


MASK 
SET 
ENABLE 
(1  =  ENABLE) 


 1  

RST 
MASKS 
(1  =SET) 


5-22 


MPD8085A 


INSTRUCTION  SET 


DATA  AND  INSTRUCTION 
FORMATS 


The  instruction  set  includes  arithmetic  and  logical  operators  with  direct,  register, 
indirect,  and  immediate  addressing  modes. 

Move,  load,  and  store  instruction  groups  provide  the  ability  to  move  either  8  or  16  bits 
of  data  between  memory,  the  six  working  registers  and  the  accumulator  using  direct, 
register,  indirect,  and  immediate  addressing  modes. 

The  ability  to  branch  to  different  portions  of  the  program  is  provided  with  direct,  con- 
ditional, or  computed  jumps.  Also,  the  ability  to  call  and  return  from  subroutines  is 
provided  both  conditionally  and  unconditionally.  The  RESTART  (or  single  byte  call 
instruction)  is  useful  for  interrupt  vector  operation. 

Conditional  jumps,  calls  and  returns  execute  based  on  the  state  of  the  four  testable 
flags  (Sign,  Zero,  Parity  and  Carry).  The  state  of  each  flag  is  determined  by  the  result 
of  the  last  instruction  executed  that  affected  flags.  (See  Instruction  Set  Table.) 

The  Sign  flag  is  set  (High)  if  bit  7  of  the  result  is  a  "1";  otherwise  it  is  reset  (Low).  The 
Zero  flag  is  set  if  the  result  is  "0";  otherwise  it  is  reset.  The  Parity  flag  is  set  if  the 
modulo  2  sum  of  the  bits  of  the  result  is  "0"  (Even  Parity);  otherwise  (Odd  Parity)  it 
is  reset.  The  Carry  flag  is  set  if  the  last  instruction  resulted  in  a  carry  or  a  borrow  out 
of  the  most  significant  bit  (bit  7)  of  the  result;  otherwise  it  is  reset. 

In  addition  to  the  four  testable  flags,  the  juPD8085A  has  another  flag  (ACY)  that  is 
not  directly  testable.  It  is  used  for  multiple  precision  arithmetic  operations  with  the 
DAA  instruction.  The  Auxiliary  Carry  flag  is  set  if  the  last  instruction  resulted  in  a 
carry  or  a  borrow  from  bit  3  into  bit  4;  otherwise  it  is  reset. 

Double  precision  operators  such  as  stack  manipulation  and  double  add  instructions 
extend  both  the  arithmetic  and  interrupt  handling  capability  of  the  )uPD8085A.  The 
ability  to  increment  and  decrement  memory,  the  six  general  registers  and  the  accumu- 
lator are  provided  as  well  as  extended  increment  and  decrement  instructions  to 
operate  on  the  register  pairs  and  stack  pointer.  Further  capability  is  provided  by  the 
ability  to  rotate  the  accumulator  left  or  right  through  or  around  the  carry  bit. 

Input  and  output  may  be  accomplished  using  memory  addresses  as  I/O  ports  or  the 
directly  addressed  I/O  provided  for  in  the  juPD8085A  instruction  set. 

Two  instructions,  RIM  and  SIM,  are  used  for  reading  and  setting  the  internal  interrupt 
mask  as  well  as  input  and  output  to  the  serial  I/O  port. 

The  special  instruction  group  completes  the  juPD8085A  instruction  set:  NOP,  HALT 
stop  processor  execution;  DAA  provides  decimal  arithmetic  capability;  STC  sets  the 
carry  flag;  CMC  complements  it;  CMA  complements  the  contents  of  the  accumulator; 
and  XCHG  exchanges  the  contents  of  two  16-bit  register  pairs  directly. 

Data  in  the  juPD8085A  is  stored  as  8-bit  binary  integers.  All  data/instruction  transfers 
to  the  system  data  bus  are  in  the  following  format: 


|  P7  I  P6  I  P5  |  D4[D3  I  P2  |pi  I  pq| 
MSB  DATA  WORD  LSB 

Instructions  are  one,  two,  or  three  bytes  long.  Multiple  byte  instructions  must  be 
stored  in  successive  locations  of  program  memory.  The  address  of  the  first  byte  is  used 
as  the  address  of  the  instruction. 


One  Byte  Instructions 
|D7|D6|d5|D4  |P3  [D2  |Pl  |  Dp  [ 

Two  Byte  Instructions 


D7 

D6 

D5 

D4  |D3 

|d2Jdi 

□0  | 

t>7 

D6 

D5 

D4  |D3 

|D2  |  D! 

Do] 

Three  Byte  Instructions 


°7 

06 

05 

04 

03 

:o2 

0, 

|o„| 

05 

04 

03 

02 

0, 

|oo| 

07 

°6 

OS 

04 

03 

02 

0, 

|ool 

OP  CODE 

operand 


TYPICAL  INSTRUCTIONS 
Register  to  register,  memory 
reference,  arithmetic  or  logical 
rotate,  return,  push,  pop,  enable, 
or  disable  interrupt  instructions 

Immediate  mode  or  I/O  instruc- 
tions 


no  /-one      JumP<  ca"  or  d,rect  load  and 
LUUt      store  instructions 

LOW  ADDRESS  OR  OPERAND  1 
HIGH  ADDRESS  OR  OPERAND  2 


5-23 


MPD8085A 


INSTRUCTION  SET 
TABLE 


INSTRUCTION  CODE 
D7    D6    O5    D4    D3    D2    D1  O0 


INSTRUCTION  CODE' 


DESCRIPTION 


D7    Dg   D5   D4    D3   O2    D,    Dq   Cycles3  R 


LOAD  REGISTER  PAIR 


MOV  d  s 
MOV  Ms 
MOV  d.M 
MVI  d.D8 
MVI  M.D8 


re  memory  to  regist 


I  B  D16 
I  D.D16 


Load  immedidi 


INCREMENT /DECREMENT 


ALU  -  REGISTER  TO  ACCUMULATOR 


Add  register  10  A 
Subtract  register  I 


MEMORY  TO  ACCUMULATOR 


PUSH  B 
PUSH  D 
PUSH  H 
PUSH  PSW 


>r  pdir  BC 
si  pan  DE 


Pop  regisiei  f. 
Pop  leqisiei  f 


DOUBLE  ADD 


DAD  B 
DAD  U 
DAD  H 
DAD  SP 


Add  BCto  HL 


INCREMENT  REGISTER  PAIR 


IMMEDIATE  TO  ACCUMULATOR 


Inciement  Slack  Pom 


DECREMENT  REGISTER  PAIR 


i  immediate  to  A  with 


DCX  B 
OCX  D 
DCX  H 
DCX  SP 


Deciement  BC 
Decrement  DE 


REGISTER  INDIRECT 


ALU  ROTATE 


RAL 
RAR 


JMP  ADDR 
JN2  ADDR 
JZ  ADDR 
JNC  ADDR 
JC  ADDR 
JPO  ADDR 
JPE  ADDR 
JP  ADDR 
JM  ADDR 


CALL  ADDR 
CNZ  ADDR 
CZ  ADDR 
CNC  ADDR 
CC  ADDR 
CPO  ADDR 
CPE  ADDR 
CP  ADDR 
CM  ADDR 


Rotate  A  left  MSB  to 

carry  18-bit) 
Rotate  A  right  LSB  to 

carry  18-bll) 

Rotate  A  left  through 

carry  (9-bit) 
Rotate  A  right  through 


Jump  unconditional 

Jump  on  parity  odd 
Jump  on  parity  even 
Jump  on  positive 


Call  unconditional 

Call  on  zero 
Call  on  no  carry 
Call  on  carry 
Call  on  parity  odd 


STAX  B 
STAX  D 
LDAX  B 
LDAX  D 


STA  ADDR 
LDA  ADDR 
SHLD  ADDR 
LHLD  ADDR 


at  ADDR  in  BC 
at  ADDR  in  DE 
it  ADDR  in  BC 
il  ADDR  m  DE 


Return  on  zero 
Return  on  no  carry 

Return  on  parity  odd 
Return  on  parity  even 
Return  on  positive 


7/10 
7/10 
7/10 
7/10 
7/10 
7/10 
7/10 
7/10 


9/18 
9/18 
9/18 
9/18 
9/18 
9/18 
9/18 
9/18 


6/12 
6/12 
6/12 
6/12 
6/12 
6/12 
6/12 
6/12 


Exchange  DE  and  HL 

register  pairs 
Exchange  top  of  stack 

and  HL 

HL  to  Stack  Pointer 
HL  to  Program  Countei 


Disable  interrupts 
Read  Interrupt  Mask 
Set  Interrupt  Mask 


MOVE  REGISTER  PAIR 


INPUT/OUTPUT 


MISCELLANEOUS 


CMC 
DA  A 
NOP 
HLT 


Complement  can 
Decimal  adjust  A 


Operand  Symbols  used 

A    8  bit  address  or  expression 
s  -  source  register 
d  -  destination  register 
PSW  =  Processor  Status  Word 
SP  -  Slack  Pointer 
D8  -~  8  bit  data  quantity  expression 
constant,  always  82  of  mstruc 
D16  =  16  bit  data  quantity,  expressic 
constant,  always  B3B2  of  instr 
ADDR  =  16  bit  Memory  address  expres< 


3Two  possible  cycle  times  (7/10)  indicate 
instruction  cycles  dependent  on  condition 
flags 

4*    flag  affected 

flag  not  affected 
0  =  flag  reset 


5-24 


MPD8085A 


INSTRUCTION  CYCLE     One  to  five  machine  cycles  (M-|  —  M5)  are  required  to  execute  an  instruction.  Each 

TIMES     machine  cycle  involves  the  transfer  of  an  instruction  or  data  byte  into  the  processor  or 
a  transfer  of  a  data  byte  out  of  the  processor  (the  sole  exception  being  the  double  add 
instruction).  The  first  one,  two  or  three  machine  cycles  obtain  the  instruction  from  the 
memory  or  an  interrupting  I/O  controller.  The  remaining  cycles  are  used  to  execute  the 
instruction.  Each  machine  cycle  requires  from  three  to  five  clock  times  (T1  -  T5). 


Machine  cycles  and  clock  states  used  for  each  type  of  instruction  are  shown  below. 


INSTRUCTION 

MACHINE  CYCLES  EXECUTED 

CLOCK  STATUS 

TYPE 

MIN/MAX 

MIN/MAX 

ALU  R 

1 

4 

CMC 

1 

4 

CMA 

1 

4 

DAA 

1 

4 

DCR  R 

1 

4 

Dl 

1 

4 

El 

1 

4 

INR  R 

1 

4 

MOV  R,  R 

1 

4 

NOP 

1 

4 

ROTATE 

1 

4 

RIM 

1 

4 

SIM 

1 

4 

STC 

1 

4 

XCHG 

1 

4 

HLT 

1 

5 

DCX 

1 

6 

INX 

1 

6 

PCHL 

1 

6 

RET  COND. 

1/3 

6/12 

SPHL 

1 

6 

ALU  I 

2 

7 

ALU  M 

2 

7 

JNC 

2/3 

7/10 

LDAX 

2 

7 

MVI 

2 

7 

MOV  M,  R 

2 

7 

MOV  R,  M 

2 

7 

STAX 

2 

7 

CALL  COND. 

2/5 

9/18 

DAD 

3 

10 

DCR  M 

3 

10 

IN 

3 

10 

1  M  D  ft/I 

0 

1U 

JMP 

3 

10 

LOAD  PAIR 

3 

10 

MVI  M 

3 

10 

OUT 

3 

10 

POP 

3 

10 

RET 

3 

10 

PUSH 

3 

12 

RST 

3 

12 

LDA 

4 

13 

STA 

4 

13 

LHLD 

5 

16 

SHLD 

5 

16 

XTHL 

5 

16 

CALL 

5 

18 

5-25 


MPD8085A 


A  minimum  computer  system  consisting  of  a  processor,  ROM,  RAM,  and       juPD8085A  FAMILY  MINIMUM 
I/O  can  be  built  with  only  3-40  pin  packs.  This  system  is  shown  below  with    SYSTEM  CONFIGURATION 
its  address,  data,  control  busses  and  I/O  ports. 


vcc 


AD0- 
ADt  _ 
AD2  - 
AD3  - 
AD4  - 
AD5  - 
AD6  - 
AD7  - 

A8  - 
A9  - 
A10  - 
An  - 
A12  " 
A13  " 
A14  ~ 
A15  * 

ALE  - 
RD  - 
WR  - 
lO/ffi  - 
RDY  - 
CLK  - 
RESET  - 

HOLD  - 
HLDA  - 
INTR  - 
I  NT  A  - 


INTERRUPTS 

 !  


4 


mi 


PORT  A 
 I  


PORTC 
 I  


PORT  B 

 I  


RST  7  5  RST  6  5  RST  5.5  TRAP  RESET  IN 

X1 

MPD8085A  PROCESSOR 

X2 

APp  - 


SID  SOD   S1  SO 


w  ir\  ICC  ~  £    x   V*    X  D   H  H 
AD7  A8-  A15  <  IS  IS  2  g  [j  ec  I  I  ?  I? 


-  PA7    PC0  - 


-PC5  PBo  - 


-PB7 


APp  - 


MPD8156  RAM-I/O  (256  X  8) 
-  AD7  o  <lc|g°c 


TIMER 
*  OUT 


FEATURES  OF  /uPD8085A 
MINIMUM  SYSTEM 


2K  -  BYTE  ROM 
256  -  BYTE  RAM 

1  -  INTERVAL  TIMER 
4  -  8  BIT  I/O  PORTS 
1  -  6-BIT  l/O-STATUS 
4-  INTERRUPT  LEVELS 


ALE  AD0- 


MPD8355  ROM-I/O 
uPD8755A  PROM-I/O  2K  X  8 


-AD7 


PA0- 


PA7 


PB0  PB7 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD8085AC/AHC 
Ceramic,  |xPD8085AD 
Cerdip,  |xPD8085AD  AHD 

8085ADS-REV4-7-83-CAT 


5-26 


SEC 


MPD8086 
pPD8086-2* 


16-BIT  MICROPROCESSOR 

DESCRIPTION     The  juPD8086  is  a  16-bit  microprocessor  that  has  both  8-bit  and  16-bit  attributes.  It 
has  a  16-bit  wide  physical  path  to  memory  for  high  performance.  Its  architecture 
allows  higher  throughput  than  the  5  MHz  /iPD8085A-2. 


FEATURES    •  Can  Directly  Address  1  Megabyte  of  Memory 

•  Fourteen  16-Bit  Registers  with  Symmetrical  Operations 

•  Bit,  Byte,  Word,  and  Block  Operations 

•  8-. and  16-Bit  Signed  and  Unsigned  Arithmetic  Operations  in  Binary  or  Decimal 

•  Multiply  and  Divide  Instructions 

•  24  Operand  Addressing  Modes 

•  Assembly  Language  Compatible  with  the  //PD8080/8085 

•  Complete  Family  of  Components  for  Design  Flexibility 


PIN  CONFIGURATION 


GND 
AD14 
AD13 
AD12 
AD11 
AD10 
AD9 
AD8 
AD7 
AD6 
AD5 
AD4 
AD3 
AD2 
AD1 
ADO 
NIVll 
INTR 
CLK 
GND 


MPD8086 
CPU 


(RQ/GTO) 

(RQ/GT1) 

(LOCK) 

(§2) 

(SI) 

(SO) 

(QSO) 

(QS1) 


*  Preliminary 


Rev/1 
5-27 


f*PD8086 


NO. 

SYMBOL 

NAME 

FUNCTION 

2-1 6,  39 

ADO-AD  15 

Address/Data  Bus 

Multiplexed  address  (T^ )  and  data  (T2,  T3,  Tyy,  T4)  bus. 
8-bit  peripherals  tied  to  the  lower  8  bits,  use  AO  to  condition 
chip  select  functions.  These  lines  are  tri-state  during  interrupt 
acknowledge  and  hold  states. 

Interrupt 

This  is  3n  edge  triggered  input  causing  a  type  2  interrupt.  A 
look-up  table  is  used  by  the  processor  for  vectoring 
information. 

18 

INTR 

Interrupt  Request 

A  level  triggered  input  sampled  on  the  last  clock  cycle  of 
each  instruction.  Vectoring  is  via  an  interrupt  look-up  table. 
INTR  can  mask  in  software  by  resetting  the  interrupt  enable 
bit. 

19 

CLK 

Clock 

The  clock  input  is  a  1/3  duty  cycle  input  basic  timing  for  the 
processor  and  bus  controller. 

21 

RESET 

Reset 

This  active  high  signal  must  be  high  for  4  clock  cycles.  When 
it  returns  low,  the  processor  restarts  execution. 

transferred.  Synchronization  is  done  by  the  /uPD8284  clock 
generator. 

23 

TEST 

Test 

This  input  is  examined  by  the  "WAIT"  instruction,  and  if 
low,  execution  continues.  Otherwise  the  processor  waits  in  an 
"Idle"  state.  Synchronized  by  the  processor  on  the  leading 
edge  of  CLK. 

24 

INTA 

Interrupt 
Acknowledge 

This  is  a  read  strobe  for  reading  vectoring  information. 
During  T2,  T3,  and  Tyy  of  each  interrupt  acknowledge 
cycle  it  is  low. 

Address  Latch  Enable 

1  nio  is  useo  in  conjunction  wnn  tne  f*«  uo£0£/oa(m  laidic* 
to  latch  the  address,  during  T1  of  any  bus  cycle. 

26 

DEN 

Data  Enable 

This  is  the  output  enable  for  the  MPD8282/8287  transceivers. 
It  is  active  low  during  each  memory  and  I/O  access  and 
INTA  cycles. 

27 

DT/R 

Data  Transmit/Receive 

Used  to  control  the  direction  of  data  flow  through  the 
transceivers,  

28 

M/T6 

Memory /1 0  Status 

This  is  used  to  separate  memory  access  from  I/O  access. 

29 

WR 

Write 

Depending  on  the  state  of  the  M/IO  line,  the  processor  is 
either  writing  to  I/O  or  memory. 

30 

HLDA 

Hold  Acknowledge 

A  response  to  the  HOLD  input,  causing  the  processor  to 
tri-state  the  local  bus.  The  bus  return  active  one  cycle  after 
HOLD  goes  back  low. 

31 

HOLD 

Hold 

When  another  device  requests  the  local  bus,  driving  HOLD 
high,  will  cause  the  jxPD8086  to  issue  a  H  LDA. 

32 

RD 

Read 

Depending  on  the  state  of  the  M/h5"line,  the  processor  is 
reading  from  either  memory  or  I/O. 

33 

MN/MX 

Minimum/Maximum 

This  input  is  to  tell  the  processor  which  mode  it  is  to  be  used 
in.  This  effects  some  of  the  pin  descriptions. 

34 

BHE/S7 

Bus/High  Enable 

This  is  used  in  conjunction  with  the  most  significant  half  of 
the  data  bus.  Peripheral  devices  on  this  half  of  the  bus  use 
BHE  to  condition  chip  select  functions. 

35-38 

A16-A19 

Most  Significant 
Address  Bits 

The  four  most  significant  address  bits  for  memory  opera- 
tions. Low  during  I/O  operations. 

26, 27, 28 

S0-S7 

Status  Outputs 

These  are  the  status  outputs  from  the  processor.  They  are 
used  by  the  juPD8288  to  generate  bus  control  signals. 

24, 25 

QS-|,QSo 

Que  Status 

Used  to  track  the  internal  /xPD8086  instruction  que. 

29 

LOCK 

Lock 

This  output  is  set  by  the  "LOCK"  instruction  to  prevent 
other  system  bus  masters  from  gaining  control. 

30,31 

RQ/STq 
RQ/GTt 

Request/Grant 

Other  local  bus  masters  can  force  the  processor  to  rebase 
the  local  bus  at  the  end  of  the  current  bus  cycle. 

PIN  IDENTIFICATION 


5-28 


/iPD8086 


BLOCK  DIAGRAM 


EXECUTION  UNIT 


REGISTER  FILE 


BUS  INTERFACE  UNIT 

~]       I     RELOCATION  I 
REGISTER  FILE  1 


DATA, 
POINTER,  AND 
INDEX  REGS 
(8  WORDS) 


16-BIT  ALU 


TEST- 
INT- 
NMI  - 


RO/GTqj 


HOLD- 
HLDA- 


SEGMENT 
REGISTERS 
AND 
INSTRUCTION 
POINTER 
(5  WORDS) 


7 
2k 


BUS 
INTERFACE 
UNIT 


BHE/S7 
_K  A19/S6 

*  A16/S3 
16")  AD15-AD0 


3T 


h 


INTA,  RD,  WR 


DT/R,  DEN,  ALE 


6-BYTE 
INSTRUCTION 
QUEUE 


CONTROL  &  TIMING 


-LOCK 


s0 


CLK      RESET  READY  MN/MX  GND 

V r.c. 


5-29 


MPD8086 


Operating  Temperature  0  C  to  70  C 

Storage  Temperature   -65°C  to  +150°C 

Voltage  on  Any  Pin  with  Respect  to  Ground  - 1 .0  to  +7V 

Power  Dissipation  2.5W 


ABSOLUTE  MAXIMUM 
RATINGS* 


Ta  =  25°  C 


•COMMENT:  Stress  above  those  listed  under  "Absolute  Maximum  Ratings"  may  cause  permanent 
damage  to  the  device.  This  is  a  stress  rating  only  and  functional  operation  of  the  device  at  these  or 
any  other  conditions  above  those  indicated  in  the  operational  sections  of  this  specification  is  not 
implied.  Exposure  to  absolute  maximum  rating  conditions  for  extended  periods  may  affect  device 
reliability. 


Ta  =  0°C  to  70°C;  VfjC  =  5V  ±  10% 


PARAMETER 

SYMBOL 

LIMITS 

UNITS 

TEST 
CONDITIONS 

MIN 

MAX 

Input  Low  Voltage 

V|L 

-0.5 

+0.8 

V 

Input  High  Voltage 

V|H 

2.0 

Vcc  +  0.5 

V 

Output  Low  Voltage 

vol 

0.45 

V 

Iql  =  2-5  mA 

Output  High  Voltage 

VOH 

2.4 

V 

•OH  =-400/iA 

Power  Supply  Current 

JUPD8086/ 

MPD8086-2 

ice 

340 
350 

mA 
mA 

Ta  =  25°C 

Input  Leakage  Current 

«LI 

±10 

HA 

0V<V|N<VCC 

Output  Leakage  Current 

lLO 

±10 

juA 

0.45V  <  VOUT  <  VCC 

Clock  Input  Low  Voltage 

VCL 

-0.5 

+0.6 

V 

Clock  Input  High  Voltage 

VCH. 

3.9 

vcc  + 1 .0 

V 

Capacitance  of  Input  Buffer 
(All  input  except 
AD0-AD15,  RQ/GT) 

ClN 

15 

pF 

fc  =  1  MHz 

Capacitance  of  I/O  Buffer 
(AD0-AD15,  RQ/GT) 

C|0 

15 

PF 

fc=  1  MHz 

DC  CHARACTERISTICS 


5-30 


fiPD8086 


AC  CHARACTERISTICS 

MINIMUM  COMPLEXITY 
SYSTEM 


MPD8086:  Ta  =  0°C  to  70° C;  VCc  =  5V  +  10% 

TIMING  REQUIREMENTS 


MPD8086 

pPD8086-2  (Preliminary) 

PARAMETER 

SYMBOL 

MIN 

MAX 

MIN 

MAX 

UNITS 

CONDITIONS 

CLK  Cycle  Period  -/1PD8O86 

TCLCL 

200 

500 

125 

500 

ns 

CLK  Low  Time 

TCLCH 

(2/3  TCLCL) -15 

(2/3  TCLCL) -15 

ns 

CLK  High  Time 

TCHCL 

WIS  \  ULOL| 

(1  /3  TCLCL)  +2 

CLK  Rise  Time 

TCH1CH2 

10 

10 

From  1.0V  to  3.5V 

CLK  Fall  Time 

TCL2CL1 

10 

10 

ns 

From  3.5V  to  1  0V 

Data  In  Setup  Time 

TDVCL 

30 

20 

ns 

Data  In  Hold  Time 

10 

RDY  Setup  Time  into  MPD8284 
©© 

TR1VCL 

35 

35 

ns 

RDY  Hold  Time  into  juPD8284 
.©  © 

0 

0 

READY  Setup  Time  into  mPD8086 

TRYHCH 

(2/3  TCLCL) -15 

(2/3  TCLCL) -15 

ns 

READY  Hold  Time  intoMPD8086 

TCHRYX 

30 

20 

READY  Inactive  to  CLK 

© 

TRYLCL 

-8 

-8 

HOLD  Setup  Time 

THVCH 

35 

20 

INTR,  NMI,  TEST  Setup  Time 
© 

TINVCH 

30 

15 

Input  Rise  Time 

TILIH 

20 

From  0  8V  to  2  0V 

Input  Fall  Time 

TIHIL 

12 

From  2  0V  to  0  8V 

TIMING  RESPONSES 


TIMING  RESPONSES 


PARAMETER 

SYMBOL 

UPD8086 

MPD8086-2  (Preliminary) 

UNITS 

TEST 
CONDITIONS 

MIN 

MAX 

MIN 

MAX 

Address  Valid  Delay 

TCLAV 

10 

110 

10 

60 

CL  =  20-100  pF  for 

Address  Hold  Time 

TCLAX 

10 

10 

Address  Float  Delay 

TCLAZ 

TCLAX 

80 

TCLAX 

50 

ALE  Width 

TLHLL 

TCLCH-20 

TCLCH-10 

ALE  Active  Delay 

TCLLH 

80 

50 

ALE  Inactive  Delay 

TCHLL 

85 

55 

Address  Hold  Time  to  ALE  Inactive 

TLLAX 

TCHCL-10 

TCHCL-10 

Data  Valid  Delay 

TCLDV 

10 

110 

10 

60 

Data  Hold  Time 

TCHDX 

10 

10 

all  juPD8086  Outputs 
(In  addition  to 
MPD8086  self-load) 

Data  Hold  Time  After  WR 

TWHDX 

TCLCH-30 

TCLCH-30 

Control  Active  Delay  1 

TCVCTV 

10 

110 

10 

70 

ns 

Control  Active  Delay  2 

TCHCTV 

10 

110 

10 

60 

Control  Active  Delay 

TCVCTX 

10 

110 

10 

70 

Address  Float  to  READ  Active 

TAZRL 

0 

0 

RD  Active  Delay 

TCLRL 

10 

165 

10 

100 

ns 

RD  Inactive  Delay 

TCLRH 

10 

150 

10 

80 

ns 

RD  Inactive  to  Next  Address  Active 

TRHAV 

TCLCL-45 

TCLCL-40 

ns 

HLDA  Valid  Delay 

TCLHAV 

10 

160 

10 

100 

RD  Width 

TRLRH 

2TCLCL-75 

2TCLCL-50 

WR  Width 

TWLWH 

2TCLCL-60 

2TCLCL-40 

Address  Valid  to  ALE  Low 

TAVAL 

TCLCH-60 

TCLCH-40 

Output  Rise  Time 

TOLOH 

20 

From  0  8V  to  2  0V 

Output  Fall  Time 

TOHOL 

12 

From  2  0V  to  0  8V 

NOTES:  ©  Signal  at  |tPD8284  shown  for  reference  only 

©  Setup  requirement  for  asynchronous  signal  only  to  guarantee  recognition  ai 
©  Applies  only  to  T2  state  (8  ns  into  T3) 


5-31 


PPD8086 


TIMING  WAVEFORMS 


CLK  (8284  Output) 


BHE/S7,Ai9/S6-A16/S3 


RDY  (8284  Input) 


READY  (8086  Input) 


X 


X 


Tl 

-TCLCU- 


 r~\ 


•— |«*-tclpi: 


Minimum  Complexity 
Systems  ® 


READ  CYCLE 

 © 

(WR.  INTA  =  V0H> 


X 


X 


_y  


5-32 


TIMING  WAVEFORMS 


MPD8086 


Minimum  Complexity 
Systems  (Con't.)  (S) 


CLK(8284  OUTPUT) 


BHI/S7,  Alg/S6-Ai6/S3 


L  »-TCH1CH2»»j  U    -*J  Urn-  TCL2CL1  f 


T3  TW 


WHITE  CYCLE  I  DEN 
©    ' 

(RD,  INTA, 
DT/R  =  Vqh) 


INTA  CYCLE 
©®_ 

(RD,  WR  =  V0H 
BHE  =  Vql> 


SOFTWARE  HALT 
DEN,RD,WR,INTA  =  VQH 


SOFTWARE  HALT 


TCLAV  -H  r-" 


NOTES:  ®  All  signals  switch  between  Voh  and  Vol  unless  otherwise  specified. 
@  RDY  is  sampled  near  the  end  of  T2,  T3,  Tyy  to  determine  if  Tyy 

machines  states  are  to  be  inserted. 
(D  Two  INTA  cycles  run  back-to-back.  The/iPD8086  local  ADDR/Data  Bus  is 

floating  during  both  INTA  cycles.  Control  signals  shown  for  second  INTA 

cycle. 

®  Signals  at  mPD8284  are  shown  for  reference  only. 

(5)  All  timing  measurements  are  made  at  1 .5V  unless  otherwise  noted. 


5-33 


jiPD8086 


TIMING  WITH  juPB8288  BUS  CONTROLLER 


TIMING  REQUIREMENTS 


MPD8086 

jjPD8086-2  (Preliminary) 

TEST 

PARAMETER 

SYMBOL 

MIN 

MAX 

MIN 

MAX 

UNITS 

CONDITIONS 

CLK  Cycle  Period  —  juPD8086 

200 

500 

125 

500 

CLK  Low  Time 

TCLCH 

(2/3  TCLCL)  -15 

(2/3  TCLCL)  -15 

ns 

CLK  High  Time 

TCHCL 

(1/3  TCLCL)  +2 

(1/3  TCLCL)  +2 

ns 

CLK  Rise  Time 

TCH1 CH2 

10 

10 

 F-m  l°V_to3.?V  . 

CLM  Fall  Time 

TCL2CL1 

10 

10 

From  3  5V  to  1  0V 

Data  in  Setup  Time 

TDVCL 

30 

20 

ns 

Data  in  Hold  Time 

TCLDX 

10 

10 

ns 

RDY  Setup  Time  into  /nPD8284 
©@ 

TR1VCL 

35 

35 

RDY  Hold  Time  into  mPD8284 
©-© 

TCLR1X 

0 

0 

ns 

READY  Setup  Time  into  juPD8086 

TRYHCH 

(2/3  TCLCL)  -15 

(2/3  TCLCL)  -15 

ns 

READY  Hold  Time  irho  /jPD8086 

TCHRYX 

30 

20 

ns 

READY  inactive  to  CLK 
(4) 

-8 

-8 

Setup  Time  for  Recognition 
(INTR,  NMI,  TEST)  © 

TINVCH 

30 

15 

RQ/GT  Setup  Time 

TGVCH 

30 

15 

RQ  Hold  Time  into  mPD8086 

TCHGX 

40 

30 

Input  Rise  Time 

TILIH 

20 

From  0  8V  to  2  0V 

Input  Fall  Time 

TIHIL 

12 

From  2  0V  to  0  8V 

MAXIMUM  MODE  SYSTEM 
With  /xPB8288 
Bus  Controller 


TIMING  RESPONSES 


MPD8086 

MPD8086-2  (Preliminary) 

TEST 
CONDITIONS 

PARAMETER 

SYMBOL 

MIN 

MAX 

MIN 

MAX 

UNITS 

Command  Active  Delay 
(See  Note  1 ) 

TCLML 

10 

35 

10 

35 

Command  Inactive  Delay 
(See  Note  1 ) 

TCLMH 

10 

35 

10 

35 

ns 

READY  Active  to  Status  Passive 
(See  Note  3) 

TRYHSH 

110 

65 

Status  Active  Delay 

TCHSV 

10 

110 

10 

60 

Status  Inactive  Delay 

TCLSH 

10 

130 

10 

70 

Address  Valid  Delay 

TCLAV 

10 

110 

10 

60 

ns 

Address  Hold  Time  - 

TCLAX 

10 

10 

Address  Float  Delay 

TCLAZ 

TCLAX 

80 

TCLAX 

50 

Status  Valid  to  ALE  High 
(See  Note  1 ) 

TSVLH 

15 

15 

Status  Valid  to  MCE  High 
(See  Note  1 ) 

TSVMCH 

15 

15 

CLK  Low  to  ALE  Valid 
(See  Note  1 ) 

TCLLH 

15 

15 

CLK  Low  to  MCE  High 
(See  Note  1) 

TCLMCH 

15 

15 

ALE  Inactive  Delay  (See  Note  1 ) 

TCHLL 

15 

15 

CL  =  20-100  pF  for 

MCE  Inactive  Delay  (See  Note  1) 

TCLMCL 

15 

15 

all  MPD8086  Outputs 
(In  addition  to 
MPD8086  self-load) 

Data  Valid  Delay 

TCLDV 

10 

110 

10 

60 

Data  Hold  Time 

TCHDX 

10 

10 

Control  Active  Delay  (See  Note  1 ) 

TCVNV 

5 

45 

5 

45 

Control  Inactive  Delay 
(See  Note  1 ) 

TCVNX 

10 

45 

10 

45 

Address  Float  to  Read  Active 

TAZRL 

0 

0 

RD  Active  Delay 

TCLRL 

10 

165 

10 

100 

RD  Inactive  Delay 

TCLRH 

10 

150 

10 

80 

RD  Inactive  to  Next  Address  Active 

TRHAV 

TCLCL-45 

TCLCL-40 

Direction  Control  Active  Delay 
(See  Note  1 ) 

TCHDTL 

50 

50 

ns 

Direction  Control  Inactive  Delay 
(See  Note  1) 

TCHDTH 

30 

30 

GT  Active  Delay 

TCLGL 

0 

85 

0 

50 

GT  Inactive  Delay 

TCLGH 

0 

85 

0 

50 

RD  Width 

TRLRH 

2TCLCL-50 

2TCLCL-50 

Output  Rise  Time 

TOLOH 

20 

From  0  8V  to  2  0V 

Output  Fall  Time 

TOHOL 

12 

From  2  0V  to  0  8V 

NOTES  ©  Signal  at  juPB8284  or  juPB8288  shown  for  reference  only. 

§ Setup  requirement  for  asynchronous  signal  only  to  guarantee  recognition  at  next  CLK 
Applies  only  to  T3  and  wait  states 
Applies  only  to  T2  state  (8  ns  into  T3) 


5-34 


MPD8086 


TIMING  WAVEFORMS 


Maximum  Mode 
System  Usinq 
MPB8288  Controller  Q) 


CLK 
VCL~ 


§2,Si.lo  (EXCEPT  HALT) 


'V. 


IBHE/S7,  A19/S6-A16/S3 


TSVLH 
TCLLH* 


ALE  (8288  OUTPUT) 


RDY  (8284  INPUT)  ( 


READ  CYCLE  (T) 


X 


X 


2 


-■TCL2CL1 


X 


r 


x 


X 


X 


X 


YLCL— 

1\ 


TW 


X 


mw 


TRYHSH- 
I 

— TCLAX 


7- 


MRDC  OR  IORC 


A. 


8288  OUTPUTS 


X 


x: 


x 


FLOAT 
-TRHAV— 


Jr 


c 


5-35 


pPD8086 


TIMING  WAVEFORMS 
Maximum  Mode 
System  Using 
/xPB8288  Controller 
(Con't.)  ® 


VCH  t— 
L— ' 


S2,Sl,So  (EXCEPT  HALT) 


WRITE  CYCLE  © 


8288  OUTPUTS  (§)  ©  < 


INTA  CYCLE© 


AMWC  OR  AIOWC 


AD15-AD0 

(SEE  NOTES  3  &  4) 


MCE/ 
PDEN 


8288  OUTPUTS 


SOFTWARE  HALT—  

(DEN  -  Vql.  RD»  MRDC,  lORC,  MWTC,  AMWC.  IOWC, 


AIOWC.  INTA,  =  VQH) 


INVALID  ADDRESS 


NOTES  0  All  signals  switch  between  Vqh  and  Vql  unless  otherwise  specified. 
(§)  RDY  is  sampled  near  the  and  of  T2,  T3,  Tyy  to  determine  if  Tyy 

machines  states  are  to  be  inserted. 
(D  Cascade  address  is  valid  between  first  and  second  INTA  cycle. 
©  Two  INTA  cycles  run  back-to-back.  The  8086  local  ADDR/Data  Bus  is 

floating  during  both  INTA  cycles.  Control  for  pointer  address 

is  shown  for  second  INTA  cycle. 
(D  Signals  at  8284  or  8288  are  shown  for  reference  only. 
(5)  The  issuance  of  the  8288  command  and  control  signals  (MRDC. 

MWTC.  AMWC.  IORC.  IOWC.  AIOWC,  INTA  and  DEN)  lags  the  active  high 

8288  CEN 

(D  All  timing  measurements  are  made  at  1  5V  unless  otherwise  noted, 
(f)  Status  inactive  in  state  lust  prior  to  T4. 


5-36 


fiPD8086 


ASYNCHRONOUS  SIGNAL 
RECOGNITION 


TEST 

NOTE :    ®  Setup  requirements  for  asynchronous  signals  only  to  guarantee  recognition 
at  next  CLK. 


BUS  LOCK  SIGNAL  TIMING 


CLK  -1 


CYCLE 


LK  H  H  ANY  CLK — m4 

E  I  CYCLE  I 


-TCLAV 


-TCLAV 


REQUEST/GRANT  SEQUENCE 
TIMING* 


NOTE:    (T)  The  coprocessor  may  not  drive  the  buses  outside  the  region  shown  without 
risking  contention. 

*for  Maximum  Mode  only 


5-37 


fiPD8086 


HOLD/HOLD  ACKNOWLEDGE 
TIMING* 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Cerdip,  fxPD8086D 


5-38 


8086DS-REV1-82-CAT 


SEC 


MPD8088 
HIGH-PERFORMANCE 
8-BIT  MICROPROCESSOR 


Description 

The  mPD8088  is  a  powerful  8-bit  microprocessor  that  is 
software-compatible  with  the  juPD8086.  The  jiPD8088 
has  the  same  bus  interface  signals  as  the  /iPD8085A, 
allowing  it  to  interface  directly  with  multiplexed  bus 
peripherals.  The  jiPD8088  has  a  20-bit  address  space 
which  can  be  divided  into  four  segments  of  up  to  64K 
bytes  each. 
Features 

□  8-bit  data  bus  interface 

□  16-bit  internal  architecture 

□  Addresses  1  M-byte  of  memory 

□  Software-compatible  with  the  8086 

□  Provides  byte,  word,  and  block  operations 

□  Performs  8-  and  16-bit  signed  and  unsigned  arith- 
metic in  binary  and  decimal 

□  Multiply  and  divide  instruction 

□  Directly  interfaces  to  8155,  8355,  and  8755A  multi- 
plexed peripherals 

□  40-pin  DIP 


Pin  Identification 


Pin  Configuration 


GNDd  1 
A14C  2 
A13C  3 
A12Q  4 
A11C  5 
A10Q  6 
A9C  7 
A8C  8 
AD7(Z  9 
AD6C  10 
AD5C  11 
AD4C  12 
AD3Q  13 
AD2C  14 
AD1Q 
ADOC  16 
NMIC  17 
INTRQ  18 
CLK\~  19 
GND(Z  20 


Mm 
Mode 


15 


40 


36 


34 


29 


26 


22 


j  Max  ) 
)  Mode  \ 


□  vcc 

□  A15 

□  A16/S3 

□  A17/S4 

□  A18/S5 

□  A19/S6 

□  sso 

□  MN/MX 

□  RD 
31  □  HOLD 

□  hlda 

□  WR 

□  lO/M 

□  DT/R 
JDEN 

□  ale 

□  iNTA 

□  TEST 

□  READY 

□  RESET 


(RQ/GTO) 

(RQ/GT1) 

(LOCK) 

(S2) 

(ST) 

(SO) 

(QSO) 

(QS1) 


No. 

Symbol 

Name 

Function 

1,  20 

GND 

Ground 

2-8, 
35-39 

Most  significant 
address  bits 

Most  significant  bits  for  memory  operations. 

9-16 

AD7-AD0 

Address/Data  bus 

Multiplexed  address  and  data  bus.  8-bit  periph- 
erals tied  to  these  bits  use  Ag  to  condition  chip 
select  functions.  These  lines  are  tri-state  during 
hold  and  interrupt  acknowledge  states. 

17 

NMI 

Non-maskable 
interrupt 

This  edge-triggered  input  cause's  a  type  2  inter- 
rupt. The  processor  uses  a  lookup  table  for  vec- 
toring information. 

18 

INTR  . 

Interrupt  request 

This  is  a  level-triggered  interrupt  sampled  on  the 
last  clock  cycle  of  each  instruction.  A  lookup 
table  is  used  for  vectoring.  INTR  can  be  masked 
by  software  by  resetting  the  interrupt  enable  bit. 

19 

CLK 

Clock 

The  clock  Is  a  1/3  duty  cycle  input  providing 
basic  timing  for  the  processor  and  bus 
controller. 

21 

RESET 

Reset 

This  active  high  signal  must  be  high  for  4  clock 
cycles.  When  it  returns  low,  the  processor 
restarts  execution. 

22 

READY 

Ready 

An  acknowledgement  from  memory  or  I/O  that 
data  will  be  transferred.  Synchronization  is  done 
by  the  fiPD8284  clock  generator. 

23 

TEST 

Test 

This  input  is  examined  by  the  "WAIT"  instruc- 
tion and  if  low,  execution  continues.  Otherwise 
the  processor  waits  in  an  "idle"  state.  Synchro- 
nized by  the  processor  on  the  leading  edge  of 
CLK. 

24 

iNTA 

Interrupt 
Acknowledge 

This  is  a  read  strobe  for  reading  vectoring  infor- 
mation. During  T2,  T3,  and  Tw  of  each  interrupt 
acknowledge  cycle  it  is  low. 

25 

ALE 

Address  Latch 
Enable 

Used  with  the  yPD8282/8283  latches  to  latch  the 
address  during  T-j  of  any  bus  cycle. 

24,  25 

QS-\,  QSo 

Queue  Status 

(Max  Mode)  Tracks  the  internal  mPD8088  instruc- 
tion queue. 

26 

DEN 

Data  Enable 

This  is  the  output  enable  for  the  fPD8286/8287 
transceivers.  It  is  active  low  during  memory  and 
I/O  access  and  INTA  cycles. 

27 

DT/R 

Data  Transmit/ 
Receive 

Controls  the  direction  of  data  flow  through  the 
transceivers. 

28 

IO/M 

I/O/Memory 
Status 

Separates  memory  access  from  I/O  access. 

29 

WR 

Write 

The  processor  is  writing  to  memory  or  I/O, 
depending  on  the  state  of  the  IO/M  line. 

29 

LOCK 

Lock 

(Max  Mode)  This  output  is  set  by  the  lock  instruc- 
tion to  prevent  other  system  bus  masters  from 
gaining  control. 

30 

HLDA 

Hold 

Acknowledge 

A  response  to  the  HOLD  input,  causing  the 
processor  to  tri-state  the  local  bus.  The  bus 
becomes  active  one  cycle  after  HOLD  returns 
low. 

31 

HOLD 

Hold 

When  another  device  requests  the  local  bus, 
HOLD  is  driven  high,  causing  the  ^PD8088  to 
issue  a  HLDA. 

30,  31 

RQ/GTn 
RQ/GT-j 

Request/Grant 

(Max  Mode)  Other  local  bus  masters  can  force 
the  processor  to  rebase  the  local  bus  at  the  end 
of  the  current  bus  cycle. 

32 

RD 

Read 

Depending  on  the  state  of  the  IO/M  line,  the 
processor  is  reading  from  memory  or  I/O. 

33 

MN/MX 

Minimum/ 
Maximum 

This  input  tells  the  processor  in  which  mode  it 
is  to  be  used.  This  affects  some  of  the  pin 
descriptions. 

34 

ssb" 

Status  Line 

Equivalent  to  Sg  in  Max  Mode. 

26-28 

Sg-S2 

Status  Outputs 

(Max  Mode) 

35-38 

S3-S5 

Status  Outputs 

These  outputs  from  the  processor  are  used  by 
the  uPD828£  to  generate  bus  control  signals. 

40 

vCc 

Power  Supply 

5V  power  input. 

Rev/1 


5-39 


MPD8088 

Block  Diagram 


Bus 
Interface 

ES 

CS 

SS 

Unit 

DS 

IP 

Execution  Unit 
Control 
System 


Execution 
Unit 


AH 

AL 

BH 

BL 

CH 

CL 

PH  1 
S 

PL 

P 

BP 

SI 

Dl 

\  Arithmetic/  / 
\  Logic  Unit  / 


Absolute  Maximum  Ratings* 

Ta  =  25°C 

Tentative 

Ambient  Temperature  under  Bias 

0°Cto70°C 

Storage  Temperature 

-65°Cto  +150°C 

Voltage  on  any  Pin  with  respect  to  Ground 

-0.5V  to  +7V 

Power  Dissipation 

2.5  Watt 

*  COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be  oper- 
ated under  conditions  outside  the  limits  described  in 
the  operational  sections  of  this  specification.  Exposure 
to  absolute  maximum  rating  conditions  for  extended 
periods  may  affect  device  reliability. 

DC  Characteristics 

Ta  =  0°C  to  +70°C,  Vcc  =  +5V  ±  10% 


Unit     Tort  Conditions 


Symbol  *Hn  Typ 


Clock  Input  Low  Voltage 

VCL 

-0.5 

+0.6 

V 

Clock  Input  High  Voltage 

VCH 

3.9 

Vcc  +  10 

V 

Input  Low  Voltage 

V|L 

-0.5 

+0.8 

V 

Input  High  Voltage 

V|H 

2.0 

VCC  +  0.5 

V 

Output  Low  Voltage 

vol 

0.45 

V 

lOL  =  2-0  mA 

Output  High  Voltage 

V0H 

2.4 

V 

lOH  =  400  jiA 

Power  Supply  Current 

ice 

340 

mA 

Input  Leakage 

<LI 

±10 

pA 

ov<vIN<vcc 

Output  Leakage 

«L0 

±10 

MA 

0.45V  <  V0UT<  VCC 

Capacitance 


Symbol  Mb*  Typ      Max      Unit      Tost  Conditions 


Capacitance  of  Input 
Buffer  (All  input  except 
ADo-AD7  RQ/GT) 


CIN 


pF    fc  =  1  I 


Capacitance  of  I/O  Buffer 
(AD0-AD7  RQ/GT) 


C|0 


pF    fc  =  1  II 


AC  Characteristics 

Minimum  Mode  Timing  Requirements 

Ta  =  O'CtO  +70°C,  VCC  a  »gV  ±  10% 


Mln         Typ  Mmx   Unit    Test  Conditions 


Notes: 

(1    Signal  at  fiPD8284  shown  for  reference  only. 

(2   Setup  requirement  for  asynchronous  signal  guarantees 
recognition  at  next  CLK. 

Applies  to  T2  state  (8  ns  into  T3  state). 


CLK  Period 

*CLCL 

200 

500 

ns 

CLK  Low  Time 

*CLCH 

f2/3t/«i  a  )-15 

CLK  High  Time 

*CHCL 

(1/3tCLCL)  +  2 

ns 

CLK  Rise  Time 

*CH1CH2 

10 

ns 

1.0V  to  3.5V 

CLK  Fall  Time 

*CL2CL1 

10 

ns 

3.5V  to  1.0V 

Data  In  Setup  Time 

*DVCL 

30 

ns 

Data  In  Hnlri  Time 
umfl  in  noiu  1 111  it? 

*CLDX 

10 

hdy  setup  Time 
MPD8284  ©(f) 

*R1VCL 

35 

ns 

RDY  Hold  Time  into 
/iPD8284  ©  (2) 

*CLR1X 

0 

ns 

READY  Setup  Time 
into  jJ>D8088 

»RYHCH 

(2/3tCLCL)-15 

ns 

READY  Hold  Time 
into  MPD8088 

*CHRYX 

30 

ns 

READY  Inactive  to 
CLK  (D 

*RYLCL 

-8 

ns 

HOLD  Setup  Time 

*HVCH 

35 

ns 

INTR,  NMI.TEST 
Setup  Time  (§) 

»INVCH 

30 

ns 

Input  Rise  Time 
(Except  CLK) 

*ILIH 

20 

ns 

0.8V  to  2.0V 

Input  Fall  Time 
(Except  CLK) 

*IHIL 

12 

ns 

2.0V  to  0.8V 

Timing  Responses 


Symbol 

Mln 

Typ  Max 

Units   Tost  Conditions 

Address  Valid  Delay 

*CLAV 

15 

110 

ns 

Address  Hold  Time 

*CLAX 

10 

ns 

Address  Float  Delay 

*CLAZ 

*CLAX 

80 

ns 

ALE  Width 

lLHLL 

tCLCH-20 

ns 

ALE  Active  Delay 

*CLLH 

80 

ns 

ALE  Inactive  Delay 

*CHLL 

85 

ns 

Address  Hold  Time 
to  ALE  Inactive 

*LLAX 

*CHCL~10 

ns 

Data  Valid  Delay 

*CLDV 

10 

110 

ns    Cj_  =  20-100  pF  for 

Data  Hold  Time 

<CHDX 

10 

n8    all  8088  outputs 

Data  Hold  Time 
After  WR 

*WHDX 

*CLCH~30 

  and  internal  loads 

ns 

Control  Active 
Delay  1 

tcvCTV 

10 

110 

ns 

Control  Active 
Delay  2 

*CHCTV 

10 

110 

ns 

Control  Inactive 
Delay 

*CVCTX 

10 

110 

ns 

Address  Float  to 
READ  Active 

fAZRL 

0 

ns 

RD  Active  Delay 

*CLRL 

10 

165 

ns 

RD  Inactive  Delay 

*CLRH 

10 

150 

ns 

RD  Inactive  to  Next 
Address  Active 

*RHAV 

tcLCL-45 

ns 

HLDA  Valid  Delay 

*CLHAV 

10 

160 

ns 

RD  Width 

*RLRH 

2»CLCL-75 

ns 

WR  Width 

*WLWH 

2tCLCL-«0 

ns 

Address  Valid  to 
ALE  Low 

*AVAL 

*CLCH"60 

ns 

Output  Rise  Time 

*OLOH 

20 

ns        0.8V  to  2.0V 

Output  Fall  Time 

*OHOL 

12 

ns        2.0V  to  0.8V 

5-40 


MPD8088 


AC  Characteristics  (Cont.) 
Max  Mode  System  Timing  Requirements 
(Using  8288  Bus  Controller) 


Timing  Responses 


Typ  Max  Units   Test  Conditions 


Parameter 

Symbol 

Mm  Typ 

Max 

Unit 

Test  Conditions 

CLK  Period 

*CLCL 

200 

500 

ns 

CLK  Low  Time 

(2/3tnn)-15 

ns 

CLK  High  Time 

*CHCL 

(1/3tCLC|J  +  2 

ns 

CLK  Rise  Time 

*CH1CH2 

10 

ns 

1.0V  to  3.5V 

CLK  Fall  Time 

tCL2CL1 

10 

ns 

3.5V  to  1.0V 

Data  In  Setup  Time 

*DVCL 

30 

ns 

Data  in  nolo  Time 

*CLDX 

10 

ns 

RDY  Setup  Time 
into  mPD8284  (J)  (2) 

*R1VCL 

35 

ns 

RDY  Hold  Time  into 
pPD8284  (J)  ® 

*CLR1X 

0 

ns 

READY  Setup  Time 
into  pPD8088 

*RYHCH 

<2/3tCLCL>-15 

ns 

READY  Hold  Time 
into  mPD8088 

*CHRYX 

30 

ns 

READY  Inactive  to 

CLK  (§) 

tRYLCL 

-8 

ns 

Setup  Time  for 
Recognition  (INTR, 
NMl,  TEST)  (2) 

*INVCH 

30 

ns 

RQ/GT  Setup  Time 

*GVCH 

30 

ns 

RQ  Hold  Time  into 
MPD8088 

<CHGX 

40 

ns 

Input  Rise  Time 
(Except  CLK) 

*ILIH 

20 

ns 

0.8V  to  2.0V 

Input  Fall  Time 
(Except  CLK) 

*IHIL 

12 

ns 

2.0V  to  0.8V 

Command  Active 
Delay  0 

tCLML 

10 

35 

ns 

Command  Inactive 
Delay  CD 

*CLMH 

READY  Active  to 
Status  Passive  (§) 

tRYHSH 

110 

ns 

Status  Active  Delay 

kJHSV 

10 

110 

ns 

Status  Inactive 

*CLSH 

10 

130 

ns 

Delay 

Address  Valid  Delay 

*CLAV 

15 

110 

ns 

Address  Hold  Time 

*CLAX 

10 

ns 

Address  Float  Delay 

*CLAZ 

*CLAX 

80 

ns 

Status  Valid  to  ALE 
High  (J) 

15 

ns 

Status  Valid  to  MCE 
High  ® 

*SVMCH 

15 

ns 

CLK  Low  to  ALE 
Valid  CD 

*CLLH 

15 

ns 

CLK  Low  to  MCE 
High  0 

'CLMCH 

15 

ns 

ALE  Inactive 
Delay  0 

«CHLL 

15 

ns 

CL  =  20-100  pF  for 
all  8088  outputs 

MCE  Inactive 
Delay  0 

*CLMCL 

15 

ns 

and  internal  loads 

Data  Valid  Delay 

*CLDV 

15 

110 

Data  Hold  Time 

*CHDX 

10 

Control  Active 
Delay  0 

lCVNV 

5 

45 

ns 

Control  inactive 
ueiay  \jj 

*CVNX 

10 

45 

ns 

Address  Float  to 
READ  Active 

tAZRL 

0 

ns 

RD  Active  Delay 

tCLRL 

10 

165 

ns 

RD  Inactive  Delay 

*CLRH 

RD  Inactive  to  Next 
Address  Active 

*RHAV 

 ~S  

tCLCL-  45 

Direction  Control 
Active  Delay  0 

*CHDTL 

50 

ns 

Direction  Control 
Inactive  Delay  0 

kJHDTH 

30 

ns 

1ST  Active  Delay 

!CLGL 

85 

ns 

GT  Inactive  Delay 

*CLGH 

85 

ns 

RB  Width 

lRLRH 

»CLCL-75 

ns 

Output  Rise  Time 

*OLOH 

20 

ns 

0.8V  to  2.0V 

Output  Fall  Time 

*OHOL 

12 

ns 

2.0V  to  0.8V 

Notes: 

®  Signal  at  nPD8284  or  |*PD8288  shown  for  reference  only. 
(2)  Setup  requirement  for  asynchronous  signal  guarantees 

recognition  at  next  CLK. 
(§)  Applies  to  T3  and  wait  states. 
(J)  Applies  to  T2  state  (8  ns  into  T3  state). 


5-41 


MPD8088 

Timing  Waveforms 


CLK  (MPD8284  Output) 


A19/S8-A18/S3 


RDY  (MPD8284  Input) 


RDY  (MPD8088  Input) 


Read  Cycle 

 © 

(WR,  INTA  =  VOH) 


AD7-AD0 


Y  -/ 


Ti 

-tCLCL" 


X 


X 


X 


1 


—  tCHCL  — 


c  > 


T3  TWAIT 

— tCL2CL1  I 


A15-A8  (Float  During  INTA) 


X 


—  tCLCH  ~ 


S6-S3 


X 


3C 


5-42 


MPD8088 


Timing  Waveforms  (Cont.) 


K  (mPD8284  Output)  /  \ 


Write  Cycle 


AD7-AD0 


INTA  Cycle 

®<3> 

(RD,  WR  =  VOH) 


Software  Halt 

DEN,  RD,  WR,  TRTA  =  VOH 

AD7-AD0 


INTA 


Notes: 

(D  All  signals  switch  between  Vqh  and  Vol  unless  otherwise  specified. 
@  RDY  is  sampled  near  the  end  of  T2, 13,  TyvAIT  to  determine  if  T\a/AIT  machine  states  are 
inserted. 

(§)  Two  INTA  cycles  run  back-to-back.  The  mPD8088  local  Address/  Data  bus  floats  during  both 

INTA  cycles.  The  control  signals  shown  are  for  the  second  INTA  cycle. 
(D  Signals  at  the  mPD8284  are  shown  for  reference. 
(!)  All  timing  measurements  are  taken  at  1 .5V  unless  otherwise  specified. 


5-43 


MPD8088 


Timing  Waveforms  (Cont.) 


Maximum  Mode  System  Bus  Timing 
(using  8288  Bus  Controller) 


VCH 


VCL" 


S2.  S^Sq  (Except  Halt)  - 


A15"A8 


A19/s6-A16/S3 


'  ALE  (MPD8288  Output) 


0  <  RDY  (MPD8284  Input) 


Ready  (pPD8088  Input)  / 


Read  Cycle 


AD7-AD0 


MRDC  OR  IORC 


MPD8288  Outputs 

©© 


 r 


tCLAV 


tCHSV 


lCLAV 


*CLLH 


X 


tSVLH 


tCLCL- 


tCH1CH2 


tCHCL 


*cldv 

*CLAX 


A19-A16 


*CHLL 


X 


3C 


mm 


A15-A8 


tRIVCL 


T3 

tCL2CL1  TWAIT 


x 


tCLSH 


*CLR1X 


® 


lCLCH 


X 


X 


X 


*CHDX 


3C 


5-44 


MPD8088 


Timing  Waveforms  (Cont.)  vch 

CLK 

"S2,  S-| ,  Sq  (Except  Halt) 


MPD8288  Outputs 

©© 


AMWC  OR  AIOWC 


MWTC  OR  IOWC 


MPD8288  Outputs 

©© 


Software 
Halt  -  (DEN 


V0L;  RD,  MRDC,  IORC,  MWTC,  AMWC,  IOWC,  AIOWC,  INTA, 
AD7-AD0,  A15-A8  


tCLAV 


Invalid  Address 


S2,  $1>  Sq 


V 


Notes: 

©  All  signals  switch  between  Vqh  and  Vol  unless  otherwise  specified. 

®  RDY  is  sampled  near  the  end  of  T2,  T3,  TwAIT  to  determine  if  TwAIT  machine  states  are 
inserted. 

(§)  The  cascade  address  is  valid  between  the  first  and  second  INTA  cycles. 

(§)  Two  INTA  cycles  run  back-to-back.  The  ptPD8088  local  Address/Data  bus  floats  during  both 

INTA  cycles.  The  control  signals  shown  are  for  the  second  INTA  cycle. 
(§)  Signals  at  the  nPD8284  and  nPD8288  are  shown  for  reference. 

®  The  nPD8288  active-high  CEN  lags  when  the  nPD8288  issues  command  and  control  signals 

(MRDC,  MWTC,  AMWC,  IORC,  IOWC,  AIOWC,  INTA,  and  DEN). 
(2)  All  timing  measurements  are  taken  at  1 .5V  unless  otherwise  specified. 


Status  is  inactive  prior  to  T4. 


5-45 


MPD8088 

Timing  Waveforms  (Cont.) 

Asynchronous  Input  Recognition 


I 


Y 


tINVCH  © 


Signal 


x 


Note: 

®  Setup  requirements  for  asynchronous  signals  guarantee  recognition  at  next  CLK. 


Maximum  Mode  Bus  Lock  Signal  Timing 


-  Any  CLK  Cycle  - 


y 


-Any  CLK  Cycle- 


S 


J' 


Maximum  Mode  Request/Grant  Sequence  Timing 

Any  CLK  Cycle 


yi 


RO/GT 


A19/S6-A16/S3 
A15-A8 
AD7-AD0 
S2.  Sj.So 

rd,  Cock 


-0  CLK  Cycle—* 


tGVCH 
— tCHGX— 
Pulse  1 


~\     Coprocessor  £ 

-  A 


Pulse  2 
MPD8088  GT 


Previous  Grant 


Pulse  3 
Coprocessor 


A. 


_A_ 


Coprocessor  © 


y\_jfV'VM\ 

U  tCLGH 


*GVCH 


X 


Note: 

(D  The  coprocessor  risks  bus  contention  if  it  drives  the  buses  outside  the  areas  shown. 


5-46 


MPD8088 


Timing  Waveforms  (Cont.) 

Mimimum  Mode  Hold  Acknowledge  Timing 


Holes 

®  All  signals  switch  between  Vqh  and  vOL  unless  otherwise  specified. 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Cerdip,  |xPD8088D 


5-47 


8088DS-REV1  -7-83-CAT 


Notes 


5-48 


PERIPHERALS 


SEC 


|xPD765A  VPD7265 
SINGLE/DOUBLE  DENSITY 
FLOPPY  DISK  CONTROLLER 


Description 

The  fxPD765A  is  an  LSI  Floppy  Disk  Controller  (FDC)  chip 
which  contains  the  circuitry  and  control  functions  for  inter- 
facing a  processor  to  4  floppy-disk  drives.  It  is  capable  of 
supporting  either  IBM  3740  Single  Density  format  (FM),  or 
IBM  System  34  Double  Density  format  (MFM)  including 
double-sided  recording.  The  |jlPD765A  provides  control 
signals  which  simplify  the  design  of  an  external  phase 
locked  loop  and  write  precompensation  circuitry.  The  FDC 
simplifies  and  handles  most  of  the  burdens  associated  with 
implementing  a  floppy-disk  interface. 
The  ^jlPD7265  is  an  addition  to  the  FDC  family  that  has 
been  designed  specifically  for  the  Sony  Micro  Floppydisk® 
drive.  The  |jlPD7265  is  pin-compatible  and  electrically 
equivalent  to  the  765A  but  utilizes  the  Sony  recording  for- 
mat. The  |jlPD7265  can  read  a  diskette  that  has  been 
formatted  by  the  |jlPD765A. 

Hand-shaking  signals  are  provided  in  the  |xPD765A/ 
fxPD7265  which  make  DMA  operation  easy  to  incorporate 
with  the  aid  of  an  external  DMA  Controller  chip,  such  as  the 
|jlPD8257.  The  FDC  will  operate  in  either  the  DMA  or  non- 
DMA  mode.  In  the  non-DMA  mode  the  FDC  generates 
interrupts  to  the  processor  every  time  a  data  byte  is  to  be 
transferred.  In  the  DMA  mode,  the  processor  need  only 
load  the  command  into  the  FDC  and  all  data  transfers 
occur  under  control  of  the  FDC  and  DMA  controllers. 
There  are  15  commands  which  the  |xPD765A/(xPD7265 
will  execute.  Each  of  these  commands  requires  multiple 
8-bit  bytes  to  fully  specify  the  operation  which  the  proces- 
sor wishes  the  FDC  to  perform.  The  following  commands 
are  available: 


Features 

Address  Mark  detection  circuitry  is  internal  to  the  FDC 
which  simplifies  the  phase  locked  loop  and  read  elec- 
tronics. The  track  stepping  rate,  head  load  time,  and 
head  unload  time  are  user-programmable.  The  |jlPD765A/ 
|jlPD7265  offers  additional  features  such  as  multitrack  and 
multiside  read  and  write  commands  and  single  and  double 
density  capabilities. 

□  Sony  (EMCA)  Compatible  Recording  Format 
(uPD7265) 

□  IBM-compatible  Format  (Single  and  Double  Density) 
(uPD765A) 

□  Multisector  and  Multitrack  Transfer  Capability 

□  Drive  Up  to  4  Floppy  or  Micro  Floppydisk®  Drives 

□  Data  Scan  Capability— Will  scan  a  single  sector  or  an 
entire  cylinder  comparing  byte-for-byte  host  memory 
and  disk  data 


□  Data  Transfers  in  DMA  or  Non-DMA  Mode 

□  Parallel  Seek  Operations  on  Up  to  Four  Drives 

□  Compatible  with  uPD8080/85,  |jlPD8086/88  and 
|aPD780  (Z80™)  Microprocessors 

□  Single  Phase  Clock  (8  MHz) 

□  +5VOnly 

□  40-Pin  Plastic  Package 

™Z80  is  a  registered  trademark  of  Zilog  Inc 
Micro  Floppydisk®  is  a  registered  trademark  of  Sony  Corporation 

Block  Diagram 


O  Re9'SterS 


Terminal 
Count 

DRQ  - 

DACK  - 

INT  - 

RD  _ 

WR  - 

A0 

Reset  — 


Read/ 
Write/ 
DMA 
Control 
Logic 


0 


READ  DATA 

SCAN  HIGH  OR  EQUAL 

WRITE  DELETED  DATA 

CLK 

READ  ID 

SCAN  LOW  OR  EQUAL 

SEEK 

SPECIFY 

READ  DELETED  DATA 

RECALIBRATE 

VCC 

READ  TRACK 

WRITE  DATA 

SENSE  INTERRUPT  STATUS 

GND 

SCAN  EQUAL 

FORMAT  TRACK 

SENSE  DRIVE  STATUS 

Serial 
Interface 
Controller 


-  WR  Clock 

*  WR  Data 

-  WR  Enable 

►  PreshiftO 

►  Preshift  1 

-  RD  Data 

-  Read  Data  Window 

•  VCOSync 


Drive 
Interface 
Controller 


Input 
Port 


A- \  Output 
V-y  Port 


-  Ready 

_  Write  Protect/ 
Two  Side 

-  Index 

-  Fault/Track  0 

►  Unit  Select  0 

-  Unit  Select  1 

►  MFM  Mode 

►  RW  Seek 

►  Head  Load 

►  Head  Select 
„  Low  Current/ 

Direction 

-  Fault  Reset/Step 


Absolute  Maximum  Ratings* 


Ta  =  25X 

Operating  Temperature 

-10°Cto  +70°C 

Storage  Temperature 

-40°Cto  +125°C 

All  Output  Voltages 

-0.5  to  +7V 

All  Input  Voltages 

-0.5  to  +  7V 

Supply  Voltage  Vcc 

-0.5  to  +  7V 

Power  Dissipation 

1W 

*COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be 
operated  under  conditions  outside  the  limits  described 
in  the  operational  sections  of  this  specification.  Expo- 
sure to  absolute  maximum  rating  conditions  for 
extended  periods  may  affect  device  reliability. 


Rev/1 
6-1 


|PD765A/7265 

Pin  Configuration 


Pin  Identification 


RESET 

c 

1 

RD 

c 

2 

WR 

c 

3 

cs 

c 

4 

A0 

c 

5 

DB0 

c 

6 

DB, 

c 

7 

DB2 

c 

8 

DB3 

c 

9 

DB4 

c 

10 

DB5 

c 

11 

DB6 

c 

12 

DB7 

c 

13 

DRQ 

c 

14 

DACK 

c 

15 

TC 

c 

16 

IDX 

c 

17 

INT 

c 

18 

CLK 

c 

19 

GND 

c 

20 

(XPD765A 
|xPD7265 


34  □ 
33  □ 
32  □ 


□  PS, 


30  □ 

29  □ 

28  □ 

27  □ 

26  □ 

25  □ 

24  □ 

23  □ 

22  □ 

21  □ 


*cc 

RW/SEEK 

LCT/DIR 

FR/STP 

HDL 

RDY 

WP/TS 

FLT/TR0 

PS0 


WDA 

US0 

US, 

HD 

MFM 

WE 

VCO 

RD 

RPW 

WCK 


DC  Characteristics 

Ta  =  -10°Cto  +70°C; 

VCc  =  +  5V  ±  5%  unless  otherwise  specified 


Limits 

Unit 

Test 

Min 

TVp  ©  Max 

Conditions 

Input  Low  Voltage  V)L 

-0.5 

08 

V 

Input  High  Voltage  VIH 

2.0 

Vcc  +  0.5 

V 

Output  Low  Voltage  V0L 

0.45 

V 

l0L  =  2  0  mA 

Output  High  Voltage  V0H 

2.4 

Vcc 

V 

Ioh  =  -200  ^ 

Input  Low  Voltage 

(CLK  +  WR  Clock)  V,L(<J>) 

-0.5 

0.65 

V 

Input  High  Voltage 

(CLK  +  WR  Clock)  VIH(<t>) 

24 

Vcc  +  0  5 

V 

Vcc  Supply  Current  lcc 

150 

rtiA 

Input  Load  Current  , 

10 

txA 

V,N  =  Vcc 

(All  Input  Pins)  U 

-10 

^A 

v,N  =  ov 

High  Level  Output 
Leakage  Current  lLOH 

10 

txA 

VOUT  =  VCC 

Low  Level  Output 
Leakage  Current  lL0L 

-10 

HA 

Vqut  =  +  0.45V 

Note:  ©  Typical  values  for  Ta  =  25°C  and  nominal  supply  voltage 


Capacitance 

Ta  =  25°C;  fc  =  1MHz;  Vcc  =  OV 


Limits 

Test 

Parameter 

Symbol 

Min  TVp  Max 

Unit 

Conditions 

Clock  Input 
Capacitance 

CIN(d>) 

20 

PF 

All  pins  except 
pin  under  test 
tied  to  AC 
Ground 

Input  Capacitance 

10 

PF 

Output  Capacitance 

C0UT 

20 

PF 

Pin 

1  O 

Connects  To 

Function 

No. 

Symbol 

Name 

1 

RST 

Reset 

1 

Processor 

Places  FDC  in  idle  state  Resets 
output  lines  to  FDD  to  0  (low) 
Does  not  affect  SRT,  HUT  or 
HLT  in  Specify  command  If 
RDY  pin  is  held  high  during 
Reset,  FDC  will  generate  an 
interrupt  within  1  024  msec  To 
clear  this  interrupt  use  Sense 
Interrupt  Status  command 

2 

1  © 

Processor 

Control  signal  for  transfer  of 
data  from  FDC  to  Data  Bus, 
when  0  (low) 

3 

1  j. 

Processor 

Control  signal  for  transfer  of 
data  to  FDC  via  Data  Bus,  when 
0  (low) 

4 

CS 

Chip  Select 

1 

Processor 

IC  selected  when  0  (low),  allow- 
ing RD  and  WR  to  be  enabled 

5 

A„ 

Data  Status 
Reg  Select 

1  h 

Processor 

Selects  Data  Reg  (A0  =  1)  or 
Status  Reg  (A0  =  0)  contents  of 
the  FDC  to  be  sent  to  Data  Bus 

6-13 

DB0- 
DB7 

Data  Bus 

I/O! 

Processor 

Bidirectional  8-bit  Data  Bus 

14 

DRQ 

Data  DMA 
Request 

O 

DMA 

DMA  Request  is  being  made  by 
FDC  when  DRQ  =  1 

15 

DACK 

Acknowledge 

1 

DMA 

DMA  cycle  is  active  when  0 
(low)  and  controller  is  perform- 
ing DMA  transfer. 

16 

TC 

Terminal  Count 

1 

DMA 

Indicates  the  termination  of  a 
DMA  transfer  when  1  (high)  It 
terminates  data  transfer  during 
Read/Write/ Scan  command  in 
DMA  or  Interrupt  mode 

17 

' 

FDD 

Indicates  the  beginning  of  a 
disk  track 

18 

INT 

Interrupt 

O 

Processor 

Interrupt  Request  generated 
by  FDC 

19 

CLK 

Clock 

1 

Single  phase  8  MHz  square- 
wave  clock 

20 

GND 

Ground 

DC  power  return 

21 

WCK 

Write  Clock 

1 

Write  data  rate  to  FDD  FM  — 
500  KHz,  MFM  =  1  MHz,  with  a 
pulse  width  of  250  ns  for  both 
FM  and  MFM 

22 

RDW 

Read  Data 
Window 

1 

Phase 
Lock  Loop 

Generated  by  PLL,  and  used  to 
sample  data  from  FDD 

23 

1 

FDD 

Read  data  from  FDD,  containing 
clock  and  data  bits 

24 

VCO/ 
Sync 

VCO/Sync 

O 

Phase 

Locked  Loop 

Inhibits  VCO  in  PLL  when  0 
(low),  enables  VCO  when  1 

25 

WE 

Write  Enable 

0 

FDD 

Enables  write  data  into  FDD 

MFM 

MFM  Mode 

Phase 
Lock  Loop 

MFM  mode  when  1,  FM  mode 
when  0 

HD 

Head  Select 

Head  1  selected  when  1  (high), 
Head  0  selected  when  0  (low) 

28,29 

USi, 
US0 

Unit  Select 

O 

FDD 

FDD  Unit  selected 

30 

WDA 

Write  Data 

O 

FDD 

Serial  clock  and  data  bits 
to  FDD 

31,  32 

PS„  PS0 

Precompen- 

sation 

(preshift) 

O 

FDD 

Write  precompensation  status 
during  MFM  mode  Determines 
early,  late,  and  normal  times 

33 

FLT/TRq 

Fault/Track  0 

1 

FDD 

Senses  FDD  fault  condition  in 
Read/Write  mode,  and  Track  0 
condition  in  Seek  mode. 

34 

WP/TS 

Write  Protect/ 
Two  Side 

1 

FDD 

Senses  Write  Protect  status  in 
Read/Write  mode,  and  Two-Side 
Media  in  Seek  mode 

35 

RDY 

Ready 

1 

FDD 

Indicates  FDD  is  ready  to  send 
or  receive  data 

HDL 

Head  Load 

Command  which  causes  read 
diskette 

37 

FR/STP 

Fit  Reset/Step 

0 

FDD 

Resets  fault  FF  in  FDD  in  Read 
Write  mode,  contains  step 
pulses  to  move  head  to  another 
cylinder  in  Seek  mode 

38 

LU  \iU\H 

Low  Current/ 
Direction 

0 

FDD 

Lowers  Write  current  on  inner 
tracks  in  Read/Write  mode, 
determines  direction  head  will 
step  in  Seek  mode  A  fault  reset 
pulse  is  issued  at  the  beginning 
of  each  Read  or  Write  command 
prior  to  the  occurrence  of  the 
Head  Load  signal 

39 

RW/ 
SEEK 

Read  Write, 
Seek 

0 

FDD 

When  1  (high)  Seek  mode 
selected  and  when  0  (low) 
Read/Write  mode  selected 

40 

Vcc 

+  5V 

DC  power. 

Note:  ©  Disabled  when  CS  = 


6-2 


AC  Characteristics 

Ta  =  -10°Cto  +70°C; 

Vcc  =  +5V  ±  5%  unless  otherwise  specified 


|PD765A/7265 


Limits 

Test 

Parameter 

Symbol 

Min 

Typ® 

Max 

Conditions 

120 

500 

Clock  Period 

(f>CY 

125 

8  FDD 

250 

ns 

5V4"  FDD 

125 

31/2"  Sony 

Clock  Active  (High) 

<t>0 

40 

ns 

Clock  Rise  Time 

20 

ns 

Clock  Fall  Time 

<t>f 

20 

ns 

Aq,  CS,  DACK  Setup  Time 

*AR 

Aq,  CS,  DACK  Hold  Time 
from  RD  f 

W 

RD  Width 

*RR 

250 

ns 

Data  Access  Time  from 
RD  | 

t 

— 5?  

200 

ns 

CL  =  100  pf 

DB  to  Float  Delay  Time 
from  RD  \ 

tDF 

20 

100 

ns 

CL  =  100  pF 

Aq,  CS,  DACK  Setup  Time 
toWR  I 

*AW 

0 

ns 

Aq,  CS,  DACK  Hold  Time 
to  WR  t 

*WA 

0 

ns 

WR  Width 

*WW 

250 

ns 

Data  Setup  Time  to  WR  t 

*DW 

150 

ns 

Data  Hold  Time  from  WR  f 

*WD 

5 

ns 

INT  Delay  Time  from  RD  t 

*RI 

500 

ns 

INT  Delay  Time  from  WR  | 

*WI 

500 

ns 

DRQ  Cycle  Time 

*MCY 

13 

(0.S 

DACK  1  — >  DRQ  I  Delay 

*AM 

200 

DRQ  t  -  DACK  1  Delay 

*MA 

200 

ns 

4«cy  =  1 25  ns 

DACK  Width 

*AA 

2 

4>cy 

TC  Width 

tTC 

1 

4>CY 

Reset  Width 

*RST 

14 

c|>CY 

— 4 — 

MEM  —  A  Cl/V 

MrM  —  u  0  74 

2 

MEM         1  K1/V 

MrM  —  1    O  74 

WCK  Cycle  Time 

tCY 

jiS 

MFM  =  0  8" 

1 

MFM  =  1  8" 

2 
1 

MFM  =  0  3V2"@ 
MFM  =  1  3V2"® 

WCK  Active  Time  (High) 

»0 

80 

250 

350 

ns 

WCK  Rise  Time 

tr 

20 

ns 

WCK  Fall  Time 

tf 

20 

ns 

Preshift  Delay  Time 
from  WCK  f 

tCp 

20 

100 

ns 

WCK  1  -*  WE  t  Delay 

20 

100 

ns 

WDA  Delay  Time  from 
WCK  t 

tCD 

20 

100 

ns 

RDD  Active  Time  (High) 

lRDD 

40 

ns 

4 

MFM  =  0  5V4" 

2 
2 

MFM  =  1  5V4" 

Window  Cycle  Time 

*WCY 

1 

|XS 

MFM  =  0  8 

MFM  =  1  8 

1 

MFM  =  0  3V2" 

MFM  =  1  31/2" 

Window  Hold  Time 
to/from  RDD 

lRDW 
*WRD 

15 

ns 

US01  Hold  Time  to  RW  SEEK  :  tus 

12 

|xS 

RWVSEEK  Hold  Time  to  LOW 
CURRENT/DIRECTION  | 

tSD 

7 

LOW  CURRENT/DIRECTION 
Hold  Time  to  FAULT  RESET/ 
STEP  f 

lDST 

1.0 

(XS 

US0>1  Hold  Time  from  FAULT 
RESET/STEP  1 

tsTU 

5.0 

jiS 

8  MHz  Clock 
Period  © 

STEP  Active  Time  (High) 

tSTP 

6 

7 

8 

fiS 

© 

STEP  Cycle  Time 

tsc 

33 

© 

© 

^S 

© 

FAULT  RESET  Active  Time 
(High) 

tFR 

8.0 

10 

(IS 

© 

Write  Data  Width 

lWDD 

T0-50 

US01  Hold  Time  After  SEEK 

tsu 

15 

fiS 

O  MnZ  VslOCK 

Period 

Seek  Hold  Time  from  DIR 

tDS 

30 

(AS 

DIR  Hold  Time  after  STEP 

tsTD 

24 

|XS 

Index  Pulse  Width 

W 

10 

<))CY 

RD  i  Delay  from  DRQ 

*MR 

800 

jiS 

WR  j  Delay  from  DRQ 

*MW 

250 

jtS 

8  MHz  Clock 

WE  or  RD  Response  Time 
from  DRQ  t 

*MRW 

12 

Period 

Timing  Waveforms 

Processor  Read  Operation 

A0  CS,  DACK  )t 


— »-|  r* — 'ar  — *■ 

— it— ^rr— y 

*rd[* — -  —*■ 


k— tDF 

cn--- 


Processor  Write  Operation 


A0  CS.DACK  ^ 

WR 
Data 
INT 


Clock 


DMA  Operation 


FDD  Write  Operation 


Notes:  ©  Typical  values  for  Ta  =  25°C  and  nominal  supply  voltage 

©  Under  Software  Control  The  range  is  from  1  ms  to  16  ms  at  8  MHz  clock  period,  and  2 

to  32  ms  at  4  MHz  clock  period 
®  Sony  Micro  Floppydisk®  31/2"  drive 
©  Double  these  values  for  a  4  MHz  clock  period 


Preshift  0  or  1  )(" 


Preshift  0 

Preshift  1 

Normal 

0 

0 

Late 

0 

1 

Early 

1 

0 

Invalid                                                          1  1 

6 


-3 


,.PD765A/7265 


Timing  Waveforms  (Cont.) 

Seek  Operation 

US°'1      )t  Stable 


RW/Seek 
Direction 
Step 


A  


FLT  Reset 


Index 


Fault  Reset  -  >  k. 

File  Unsafe  Reset  —^1  P — 


FDD  Read  Operation 


Jrk.  jti 


Read  Data  Window 


Note:  Either  polarity  data  window  is  valid 


Terminal  Count 


Reset 


:  J\\   Reset  A  

-H  k-tTC  -*\  H— W 


Internal  Registers 

The  |jlPD765A/|jlPD7265  contains  two  registers  which  may 
be  accessed  by  the  main  system  processor:  a  Status  Reg- 
ister and  a  Data  Register  The  8-bit  Main  Status  Register 
contains  the  status  information  of  the  FDC,  and  may  be 
accessed  at  any  time.  The  8-bit  Data  Register  (which  actu- 
ally consists  of  several  registers  in  a  stack  with  only  one 
register  presented  to  the  data  bus  at  a  time),  stores  data, 
commands,  parameters,  and  FDD  status  information  Data 
bytes  are  read  out  of,  or  written  into,  the  Data  Register  in 
order  to  program  or  obtain  the  results  after  a  particular 
command.  Only  the  Status  Register  may  be  read  and  used 
to  facilitate  the  transfer  of  data  between  the  processor  and 
|jPD765/|jiPD7265. 

The  relationship  between  the  Status/Data  registers  and  the 
signals  RD,  WR,  and  A0  is  shown  below. 


Internal  Registers  (Cont.) 

The  bits  in  the  Main  Status  Register  are  defined  as  follows: 


Bit 

Description 

No. 

Name 

Symbol 

DB0 

FDD  0  Busy 

D0B 

FDD  number  0  is  in  the  Seek  mode.  If  any  of  the  bits  is 
set  FDC  will  not  accept  read  or  write  command 

DB1 

FDD  1  Busy 

D,B 

FDD  number  1  is  in  the  Seek  mode.  If  any  of  the  bits  is 
set  FDC  will  not  accept  read  or  write  command. 

DB2 

FDD  2  Busy 

D2B 

FDD  number  2  is  in  the  Seek  mode.  If  any  of  the  bits  is 
set  FDC  will  not  accept  read  or  write  command. 

DB3 

FDD  3  Busy 

D3B 

FDD  number  3  is  in  the  Seek  mode.  If  any  of  the  bits  is 

DB4 

FDC  Busy 

CB 

A  read  or  write  command  is  in  process.  FDC  will  not 
accept  any  other  command. 

DB5 

Execution 
Mode 

EXM 

This  bit  is  set  only  during  execution  phase  in  non-DMA 
mode  When  DBS  goes  low,  execution  phase  has  ended 
and  result  phase  has  started.  It  operates  only  during 
non-DMA  mode  of  operation. 

DB6 

Data  Input/ 
Output 

DIO 

Indicates  direction  of  data  transfer  between  FDC  and 
Data  Register  If  DIO  =  1 ,  then  transfer  is  from  Data 
Register  to  the  processor  If  DIO  =  0,  then  transfer  is 
from  the  processor  to  Data  Register. 

DB7 

Request 
for  Master 

RQM 

Indicates  Data  Register  is  ready  to  send  or  receive  data 
to  or  from  the  processor.  Both  bits  DIO  and  RQM  should 
be  used  to  perform  the  hand-shaking  functions  of 
"ready"  and  "direction"  to  the  processor. 

The  DIO  and  RQM  bits  in  the  Status  Register  indicate  when 
data  is  ready  and  in  which  direction  data  will  be  transferred 
on  the  data  bus.  The  maximum  time  between  the  last  RD  or 
WR  during  a  command  or  result  phase  and  DIO  and  RQM 
getting  set  or  reset  is  12  (jls.  For  this  reason  every  time  the 
Main  Status  Register  is  read  the  CPU  should  wait  12 jxs. 
The  maximum  time  from  the  trailing  edge  of  the  last  RD 
in  the  result  phase  to  when  DB4  (FDC  busy)  goes  low 
is  12  |xs. 


Data  In/Out  Out  FDC  and  Into  Processor 

(DIO)  Out  Processor  and  Into  FDC  I  I 


Request  for  Master 
(RQM) 


Notes:  H  —  Data  register  ready  to  be  written  into  by  processor 

IB  —  Data  register  not  ready  to  be  written  into  by  processor 

E  —  Data  register  ready  for  next  data  byte  to  be  read  by  processor 

E  —  Data  register  not  ready  to  be  read  by  processor 


A0 

RD 

WR 

Function 

0 

0 

1 

Read  Mam  Status  Register 

0 

1 

0 

Illegal 

0 

0 

0 

Illegal 

1 

0 

0 

Illegal 

1 

0 

1 

Read  from  Data  Register 

1 

1 

0 

Write  into  Data  Register 

6-4 


|PD765A/7265 


Status  Register  Identification 


Status  Register  Identification  (Cont.) 


Symbol 


Description 


Status  Register  0 


D7  =  0  and  D6  =  0 

Normal  Termination  of  command,  (NT).  Command  was 
completed  and  properly  executed. 
D7  =  0  and  D6  =  1 

Abnormal  Termination  of  command,  (AT).  Execution  of 
command  was  started  but  was  not  successfully 

Interrupt  Code        IC  completed.  

D7  =  1  and  D6  =  0 

Invalid  Command  issue,  (IC).  Command  which  was 
issued  was  never  started. 
D7  =  1  and  D6  =  1 

Abnormal  Termination  because  during  command  execu- 
tion  the  ready  signal  from  FDD  changed  state. 


D5 

Seek  End 

SE 

When  the  FDC  completes  the  SEEK  command,  this  flag 
is  set  to  1  (high). 

°4 

Equipment 
Check 

EC 

If  a  fault  signal  is  received  from  the  FDD,  or  if  the  Track  0 
signal  fails  to  occur  after  77  step  pulses  (Recalibrate 
Command)  then  this  flag  is  set. 

D3 

Not  Ready 

NR 

When  the  FDD  is  in  the  not-ready  state  and  a  read  or 
write  command  is  issued,  this  flag  is  set.  If  a  read  or 
write  command  is  issued  to  Side  1  of  a  single-sided 
drive,  then  this  flag  is  set. 

D2 

Head  Address 

HD 

This  flag  is  used  to  indicate  the  state  of  the  head  at 
Interrupt. 

Unit  Select  1 

US, 

These  flags  are  used  to  indicate  a  Drive  Unit  Number 

DQ 

Unit  Select  0 

US0 

at  Interrupt. 

Status  Register  1 

D7 

End  of  Cylinder 

EN 

When  the  FDC  tries  to  access  a  sector  beyond  the  final 
sector  of  a  cylinder,  this  flag  is  set. 

D6 

Not  used.  This  bit  is  always  0  (low). 

D5 

Data  Error 

DE 

When  the  FDC  detects  a  CRC©  error  in  either  the  ID  field 
or  the  data  field,  this  flag  is  set. 

D4 

Overrun 

OR 

If  the  FDC  is  not  serviced  by  the  host  system  during  data 
transfers  within  a  certain  time  interval,  this  flag 
is  set. 

D3 

Not  used.  This  bit  always  0  (low). 

During  execution  of  READ  DATA,  WRITE  DELETED  DATA 
or  SCAN  command,  if  the  FDC  cannot  find  the  sector 
specified  in  the  IDR©  Register,  this  flag  is  set. 

D2 

No  Data 

ND 

During  execution  of  the  READ  ID  command,  if  the  FDC 
cannot  read  the  ID  field  without  an  error,  then  this  flag 
is  set. 

During  execution  of  the  READ  A  cylinder  command,  if 
the  starting  sector  cannot  be  found,  then  this  flag  is  set. 

D1 

Not  Writable 

NW 

During  execution  of  WRITE  DATA,  WRITE  DELETED 
DATA  or  Format  A  cylinder  command,  if  the  FDC  detects 
a  write  protect  signal  from  the  FDD,  then  this  flag  is  set. 

If  the  FDC  cannot  detect  the  ID  Address  Mark  after 
encountering  the  index  hole  twice,  then  this  flag  is  set. 

Do 

Missing  Address 
Mark 

MA 

if  the  FDC  cannot  detect  the  Data  Address  Mark  or 
Deleted  Data  Address  Mark,  this  flag  is  set.  Also  at  the 
same  time,  the  MD  (Missing  Address  Mark  in  data  field) 
of  Status  Register  2  is  set. 

Status  Register  2 

D7 

Not  used.  This  bit  is  always  0  (low). 

D6 

Control  Mark 

CM 

During  execution  of  the  READ  DATA  or  SCAN  command, 
if  the  FDC  encounters  a  sector  which  contains  a  Deleted 
Data  Address  Mark,  this  flag  is  set. 

D5 

Data  Error  in 
Data  Field 

DD 

If  the  FDC  detects  a  CRC  error  in  the  data  field  then  this 
flag  is  set. 

D4 

Wrong  Cylinder 

WC 

This  bit  is  related  to  the  ND  bit,  and  when  the  contents  of 
C®  on  the  medium  is  different  from  that  stored  in  the 
IDR,  this  flag  is  set. 

D3 

Scan  Equal  Hit 

SH 

During  execution  of  the  SCAN  command,  if  the  condition 
of  "equal"  is  satisfied,  this  flag  is  set. 

D2 

Scan  Not  Satisfied 

SN 

During  execution  of  the  SCAN  command,  if  the  FDC  can- 
not find  a  sector  on  the  cylinder  which  meets  the 
condition,  then  this  flag  is  set. 

D1 

Bad  Cylinder 

BC 

This  bit  is  related  to  the  ND  bit,  and  when  the  contents  of 
C  on  the  medium  is  different  from  that  stored  in  the  IDR 
and  the  contents  of  C  is  FF(16),  then  this  flag  is  set. 

Do 

Missing 
Address  Mark 
in  Data  Field 

MD 

When  data  is  read  from  the  medium,  if  the  FDC  cannot 
find  a  Data  Address  Mark  or  Deleted  Data  Address  Mark, 
then  this  flag  is  set. 

Bit 

Description 

No. 

Name 

Symbol 

Status  Register  3 

D7 

Fault 

FT 

This  bit  is  used  to  indicate  the  status  of  the  Fault  signal 
from  the  FDD. 

D6 

Write  Protected 

WP 

This  bit  is  used  to  indicate  the  status  of  the  Write  Pro- 
tected signal  from  the  FDD. 

D5 

Ready 

RY 

This  bit  is  used  to  indicate  the  status  of  the  Ready  signal 
from  the  FDD. 

D4 

Track  0 

TO 

This  bit  is  used  to  indicate  the  status  of  the  Track  0 
signal  from  the  FDD. 

D3 

Two  Side 

TS 

This  bit  is  used  to  indicate  the  status  of  the  Two  Side 
signal  from  the  FDD. 

D2 

Head  Address 

HD 

This  bit  is  used  to  indicate  the  status  of  the  Side  Select 
signal  to  the  FDD 

D1 

Unit  Select  1 

US, 

This  bit  is  used  to  indicate  the  status  of  the  Unit  Select  1 
signal  to  the  FDD. 

Do 

Unit  Select  0 

US0 

This  bit  is  used  to  indicate  the  status  of  the  Unit  Select  0 
signal  to  the  FDD. 

Notes:  ©  CRC  =  Cyclic  Redundancy  Check 
©  IDR  =  Internal  Data  Register 

®  Cylinder  (C)  is  described  more  fully  in  the  Command  Symbol  Descnpton  on  page  7 


Command  Sequence 

The  (jlPD765A/|jlPD7265  is  capable  of  performing  15  differ- 
ent commands.  Each  command  is  initiated  by  a  multibyte 
transfer  from  the  processor,  and  the  result  after  execution 
of  the  command  may  also  be  a  multibyte  transfer  back  to 
the  processor.  Because  of  this  multibyte  interchange  of 
information  between  the  |jlPD765A/|jlPD7265  and  the 
processor,  it  is  convenient  to  consider  each  command 
as  consisting  of  three  phases: 

Command        The  FDC  receives  all  information 

Phase:  required  to  perform  a  particular  opera- 

tion from  the  processor. 

Execution        The  FDC  performs  the  operation  it  was 

Phase.  instructed  to  do. 

Result  Phase.   After  completion  of  the  operation,  status 
and  other  housekeeping  information  are 
made  available  to  the  processor 
Following  are  shown  the  required  preset  parameters  and 
results  for  each  command.  Most  commands  require  9  com- 
mand bytes  and  return  7  bytes  during  the  result  phase  The 
"W"  to  the  left  of  each  byte  indicates  a  command  phase 
byte  to  be  written,  and  an  "R"  indicates  a  result  byte 


6-5 


,PD765A/7265 

Instruction  Set  ©  ©  

 Data  Bus 

Phase     R/W    P7   D6   D5   P4   P3   P2   D1    D0  Remarks 


 Bead  Data  

Command     W  MT  MF  SK    0     0     1     1     0    Command  Codes 
W       X     X     X     X     X    HD  US,  US„  ® 

yy  t  C  *  Sector  ID  information  prior 

W  <  H  »  to  command  execution.  The 

W  *  R  »  4  bytes  are  commanded 

W  <  N  >  against  header  on  Floppy 

w  «   EOT   ►  Disk. 

W  *   GPL   > 

yy  <   DTL  > 


Execution  Data  transfer  between  the 

FDD  and  main  system 

Result  R  <   ST  0   *  Status  information  after 

R  <   ST  1   *  command  execution 

R  *   ST  2   > 

R  *  C  *  Sector  ID  information  after 

R  *  H  *  command  execution 

R  «  R  ► 

 R  ■  N   >   


 Read  Deleted  Data  

Command     W  MT  MF  SK    0     1     1     0     0    Command  Codes 
W       X     X     X     X     X    HD  US,  US0 

W  *  C  »  Sector  ID  information  prior 

yy  <  h  »  to  command  execution.  The 

W  <  R  *  4  bytes  are  commanded 

yy  <  n  »  against  header  on  Floppy 

W  «   EOT   >  Disk. 

W  «   GPL   * 

W  «   DTL   > 


Execution  Data  transfer  between  the 

FDD  and  mam  system 

Result  R  *   STO   »  Status  information  after 

R  *   ST  1   >  command  execution 

R  «   ST  2   > 

R  *  C  »  Sector  ID  information  after 

R  *  H  »  command  execution 

R  «  R  » 

 R  *  N  ► 


 Write  Data  

Command     WMTMF    000     1     0     1    Command  Codes 
W       X     X     X     X     X    HD  US1  US„ 

yy    «  c  »  Sector  ID  information  prior 

yy    <  h  *  to  command  execution.  The 

W    *  R  »  4  bytes  are  commanded 

yy    <  n  *  against  header  on  Floppy 

W     «   EOT   ►  Disk. 

yy     «  GPL   > 

yy     «   DTL  > 


Execution  Data  transfer  between  the 

 main  system  and  FDD 

Result  R  *   STO   *  Status  information  after 

R  *   ST  1   *  command  execution 

R  «   ST  2   > 

R  *  C  *  Sector  ID  information  after 

p  (  h  »  command  execution 

R  «  R  » 

R  «  N  ► 


Notes:  ®  Symbols  used  in  this  table  are  described  at  the  end  of  this  section 
®  A0  should  equal  binary  1  for  all  operations 
(D  X  =  Don't  care,  usually  made  to  equal  binary  0 


Instruction  Set  

 Data  Bus  

Phase     R/W    P7   P6  Ps   D4   P3   P2   Pt   P0  Remarks 


 Write  Deleted  Data  

Command     W      MTMF    001     00     1    Command  Codes 
W       X     X     X     X     X    HD  US!  US0 

yy  «  c  >  Sector  ID  information  prior 

W  <  H  »  to  command  execution.  The 

W  «  R  *  4  bytes  are  commanded 

yy  «  ^  >.  agajnst  header  on  Floppy 

yy  «   EOT   »  Disk. 

yy  <   QPL   » 

W  <   DTL   * 


Execution  Data  transfer  between  the 

FDD  and  mam  system 

Result  R  <—   ST  0   *  Status  information  after 

R  *  ST  1   »  command  execution 

R  <   ST  2   > 

R  «  C  *  Sector  ID  information  after 

R  «  H  »  command  execution 

R  <  R  , 

R  <  N   > 


 Read  A  Track  

Command     W       0MFSK    00     0     1     0    Command  Codes 
W       X     X     X     X     X    HD  US,  US0 

W  *  C  *  Sector  ID  information  prior 

W  *  H  >  to  command  execution 

yy  <  R  , 

yy  «   N   ► 

W  *   EOT   > 

yy  <   QPL   ► 

W  <   DTL   » 


Execution  Data  transfer  between  the 

FDD  and  main  system  FDC 
reads  all  data  fields  from 

  index  hole  to  EOT. 

Result  R     *   ST  0   *  Status  information  after 

R     *   ST  1   *  command  execution 

R     *   ST  2   > 

R     *  C  *  Sector  ID  information  after 

R     *  H  »  command  execution 

R     *  R  » 

R     «  N  * 


 Read  ID  

Command     W       0    MF    0     0     10     10    Command  Codes 

 W       X     X     X     X     X    HD  US,  US0  

Execution  The  first  correct  ID 

information  on  the  cylinder 
is  stored  in  Data  Register. 

Result  R     *   ST  0   »  Status  information  after 

R     *   ST  1   >  command  execution 

R     «   ST  2   ► 

R     *  C  »  Sector  ID  information  read 

R     *  H  »•  during  Execution  phase  from 

p     <  p  „  Floppy  Disk. 

 R     *  N  > 


 Format  A  Track  

Command     W       0MF001101    Command  Codes 
W       X     X     X     X     X    HD  US,  US0 

yy  <  n  *  Bytes/Sector 

yy  <   sc   »  Sectors/Track 

yy    GPL   »  Gap  3 

 W  <  D  >  Filler  byte 


Execution  FDC  formats  an  entire  track. 


Result  R  *   ST  0   *  Status  information  after 

R  *   ST  1   *  command  execution 

p  <  ST  2  > 

R  <  C  >  In  this  case,  the  ID 

p  <  H  *  information  has  no  meaning. 

p  <  p  „ 

 R  *   N   ► 


Scan  Equal  

Command     W  MT  MF  SK    1     0     0     0     1    Command  Codes 

W  X     X     X     X     X    HD  US,  US„ 

yy  «  c  *  Sector  ID  information  prior 

W  *  H  - — —  »  to  command  execution 

yy  *  R  > 

yy  <   N  > 

W  «   EOT  

yy  <   GPL   > 

yy  <   STP   ► 


Execution  Data  compared  between  the 

 FDD  and  main  system 

Result  R  <   ST  0  *  Status  information  after 

p  «   ST  1   »  command  execution 

p  «   ST  2   » 

p  <  C  - — —  *  Sector  ID  information  after 

p  <   h  »  command  execution 

p  «  p  „ 

R  «  .  .  N   , 


6 


-6 


|PD765A/7265 


Instruction  Set  (Cont.) 


Data  Bus 

Phase     R/W     D7   D6   Ds   D4   D3   D2   D1  D0 

Remarks 

Scan  Low  or  Equal 

Command  W 


MT  MF  SK  1  1  0  0  1 
X     X     X     X     X    HD  US,  US0 

«  c  > 

«   H  > 

«   R   » 


Command  Codes 


Sector  ID  information  prior  to 
command  execution 


-  N  — 
EOT 
GPL 
STP 


Data  compared  between  the 
FDD  and  main  system 


STO 
ST  1 
ST  2 

-  C  — 

-  H  — 

-  R  — 

-  N  — 


•  Status  information  after 

•  command  execution 


>  Sector  ID  information  after 
*  command  execution 


Scan  High  or  Equal 


MT  MF  SK  1 


1    Command  Codes 


X    HD  US,  US„ 


•  Sector  ID  information  prior  to 
>  command  execution 


EOT 
GPL 
STP 


Data  compared  between  the 
FDD  and  mam  system 


STO 
ST  1 
ST  2 

-  C  — 


•  Status  information  after 
>  command  execution 


•  Sector  ID  information  after 
>  command  execution 


0  0 
X  X 


o  us,  US0 


Command  Codes 


Head  retracted  to  Track  0 


Sense  Interrupt  Status 


0    Command  Codes 


STO 
PCN 


>  Status  information  about 
•  the  FDC  at  the  end  of  seek 
operation  


Command  W 
W 


1    Command  Codes 


Sense  Drive  Status 


Command  W 
W 


0  0 
X  X 


0  10  0  Command  Codes 
X    HD  US,  US0  


>  Status  information  about 
FDD 


Command  W 
W 
W 


0  0  1111 
X     X     X    HD  US,  US0 

  NCN   > 


Command  Codes 


Head  is  positioned  over 
proper  cylinder  on  diskette. 


Command  Symbol  Description 


Symbol 

Name 

Description 

A0 

Address  Line  0 

An  controls  selection  of  Main  Status  Register 
(An  =  0)  or  Data  Register  (An  =  1) 

C 

Cylinder  Number 

C  stands  for  the  current/selected  cylinder  (track) 
numbers  0  through  76  of  the  medium. 

D 

Data 

D  stands  for  the  data  pattern  which  is  going  to  be 
written  into  a  sector. 

D7-D0 

Data  Bus 

8-bit  Data  Bus,  where  D7  stands  for  a  most 
significant  bit,  and  D0  stands  for  a  least 
significant  bit. 

DTL 

Data  Length 

When  N  is  defined  as  00,  DTL  stands  for  the  data 
length  which  users  are  going  to  read  out  or  write  into 
the  sector. 

EOT 

End  of  Track 

EOT  stands  for  the  final  sector  number  on  a  cylinder. 
During  Read  or  Write  operations,  FDC  will  stop  data 
transfer  after  a  sector  number  equal  to  EOT. 

GPL 

Gap  Length 

GPL  stands  for  the  length  of  Gap  3.  During 
Read/Write  commands  this  value  determines  the 
number  of  bytes  that  VCOs  will  stay  low  after  two 
CRC  bytes.  During  Format  command  it  determines 
the  size  of  Gap  3. 

H 

Head  Address 

H  stands  for  head  number  0  or  1 ,  as  specified  in 
ID  field. 

HD 

Head 

HD  stands  for  a  selected  head  number  0  or  1  and 
controls  the  polarity  of  pin  27.  (H  =  HD  in  all 
command  words.) 

HLT 

Head  Load  Time 

HLT  stands  for  the  head  load  time  in  the  FDD  (2  to 
254  ms  in  2  ms  increments). 

neao  unioaa  nme 

HUT  stands  for  the  head  unload  time  after  a  Read 
or  Write  operation  has  occurred  (16  to  240  ms  in 
16  ms  increments). 

MF 

CM  m  MCtl 

rm  or  MrM 

Mode 

14  UC  ie  Inui  CM  mnWa  la  ealaMaH  anil  If  It  ie  klnh 

it  Mr  is  low,  rin  moae  is  seieciea,  ana  11 11  is  nign, 
MFM  mode  is  selected. 

MT 

Multitrack 

If  MT  is  high,  a  Multitrack  operation  is  performed,  if 
MT  =  1  after  finishing  Read/Write  operation  on  side 
0,  FDC  will  automatically  start  searching  for  sector  1 
on  sidel. 

N 

Number 

N  stands  for  the  Number  of  data  bytes  written 
in  a  sector. 

NCN 

New  Cylinder 
Number 

NCN  stands  for  a  New  Cylinder  Number  which  is 
going  to  be  reached  as  a  result  of  the  Seek  operation. 
Desired  position  of  head. 

ND 

Non-DMA  Mode 

ND  stands  for  operation  in  the  Non-DMA  mode. 

PCN 

Present  Cylinder 
Number 

PCN  stands  for  the  cylinder  number  at  the 
completion  of  Sense  Interrupt  Status  command. 
Position  of  Head  at  present  time. 

R 

Record 

R  stands  for  the  sector  number  which  will  be  read 
or  written. 

R/W 

Read/Write 

R/W  stands  for  either  Read  (R)  or  Write  (W)  signal. 

SC 

Sector 

SC  indicates  the  number  of  Sectors  per  Cylinder. 

SK 

Skip 

SK  stands  for  Skip  Deleted  Data  Address  mark. 

SRT 

Step  Rate  Time 

SRT  stands  for  the  Stepping  Rate  for  the  FDD  (1  to  16 
ms  in  1  ms  increments).  Stepping  Rate  applies  to  all 
drives  (F  =  1  ms,  E  =  2  ms,  etc.). 

STO 
ST1 
ST2 
ST3 

Status  0 
Status  1 
Status  2 
Status  3 

ST  0-3  stands  for  one  of  four  registers  which  store 
the  status  information  after  a  command  has  been 
executed.  This  information  is  available  during  the 
result  phase  after  command  execution.  These 
registers  should  not  be  confused  with  the  main 
status  register  (selected  by  An  =  0).  ST  0-3  may  be 
read  only  after  a  command  has  been  executed  and 
contains  information  relevant  to  that  particular 
command. 

STP 

During  a  Scan  operation,  if  STP  =  1,  the  data  in 
contiguous  sectors  is  compared  byte  by  byte  with 
data  sent  from  the  processor  (or  DMA);  and  if  STP  = 
2,  then  alternate  sectors  are  read  and  compared. 

US0,  US1 

Unit  Select 

US  stands  for  a  selected  drive  number  0  or  1 . 

Command  W 


>  Invalid  Command  Codes 
(NoOp  —  FDC  goes  into 
Standby  state.) 


6-7 


MPD765A/7265 


System  Configuration 


8080  System  Bus 


TV 


S2. 


DB0-7 
MEMR 
IOR 
MEMW 

iow 

CS 
HRQ 
HLDA 


HPD8257 

DMA 
Controller 


Ao 

DB0_7 

RD 

WR 

CS 

INT 

RESET 


fiPD7265A 
FDC 


Read 
Data 
Window 


c 


Drive 
Interface 


Processor  Interface 

During  Command  or  Result  phases  the  Main  Status  Regis- 
ter (described  earlier)  must  be  read  by  the  processor  before 
each  byte  of  information  is  written  into  or  read  from  the  Data 
Register.  After  each  byte  of  data  read  or  written  to  the  Data 
Register,  CPU  should  wait  for  12|xs  before  reading  Main 
Status  Register.  Bits  D6  and  D7  in  the  Main  Status  Register 
must  be  in  a  0  and  1  state,  respectively,  before  each  byte 
of  the  command  word  may  be  written  into  the  |jlPD765A/ 
(jlPD7265.  Many  of  the  commands  require  multiple  bytes 
and,  as  a  result,  the  Main  Status  Register  must  be  read 
prior  to  each  byte  transfer  to  the  |jlPD765A/|jlPD7265.  On 
the  other  hand,  during  the  Result  phase,  D6  and  D7  in  the 
Main  Status  Register  must  both  be  Ys  (D6  =  1  and  D7  =  1) 
before  reading  each  byte  from  the  Data  Register.  Note  that 
this  reading  of  the  Main  Status  Register  before  each  byte 
transfer  to  the  |ulPD765A/|jlPD7265  is  required  only  in  the 
Command  and  Result  phases,  and  not  during  the  Execu- 
tion phase. 

During  the  Execution  phase,  the  Main  Status  Register  need 
not  be  read.  If  the  (jlPD765A/|jlPD7265  is  in  the  non-DMA 
mode,  then  the  receipt  of  each  data  byte  (if  fxPD765A/ 
|jlPD7265  is  reading  data  from  FDD)  is  indicated  by  an 
Interrupt  signal  on  pin  18  (INT  =  1).  The  generation  of  a 
Read  signal  (RD  =  0)  or  Write  signal  (WR  =  0)  will  clear 
the  Interrupt  as  well  as  output  the  data  onto  the  data  bus.  If 
the  processor  cannot  handle  Interrupts  fast  enough  (every 
13  )uls  for  the  MFM  mode  and  27  (jls  for  the  FM  mode),  then 
it  may  poll  the  Main  Status  Register  and  bit  D7  (RQM) 
functions  as  the  Interrupt  signal.  If  a  Write  command  is  in 
process  then  the  WR  signal  negates  the  reset  to  the  Inter- 
rupt signal. 

Note  that  in  the  non-DMA  mode  it  is  necessary  to  examine 
the  Main  Status  Register  to  determine  the  cause  of  the 
interrupt,  since  it  could  be  a  data  interrupt  or  a  command 
termination  interrupt,  either  normal  or  abnormal. 
If  the  (xPD765A/|jlPD7265  is  in  the  DMA  mode,  no  Inter- 
rupts are  generated  during  the  Execution  phase.  The 
|jlPD765A/|xPD7265  generates  DRQs  (DMA  Requests) 
when  each  byte  of  data  is  available.  The  DMA  Controller 


responds  to  this  request  with  both  aDACK  =  0  (DMA 
Acknowledge)  and  an  RD  =  0  (Read  signal).  When  the 
DMA  Acknowledge  signal  goes  low  (DACK  =  0),  then  the 
DMA  Request  is  cleared  (DRQ  =  0).  If  a  Write  command 
has  been  issued  then  a  WR  signal  will  appear  instead  of 
RD.  After  the  Execution  phase  has  been  completed  (Termi- 
nal Count  has  occurred)  or  the  EOT  sector  read/written, 
then  an  Interrupt  will  occur  (INT  =  1).  This  signifies  the 
beginning  of  the  Result  phase.  When  the  first  byte  of  data  is 
read  during  the  Result  phase,  the  Interrupt  is  automatically 

cleared  (INT  0).   

The  RD  or  WR  signals  should  be  asserted  while  DACK  is 
true.  The  CS  signal  is  used  in  conjunction  with  RD  and  WR 
as  a  gating  function  during  programmed  I/O  operations.  CS 
has  no  effect  during  DMA  operations.  If  the  non-DMA  mode 
is  chosen,  the  DACK  signal  should  be  pulled  up  to  Vcc. 
It  is  important  to  note  that  during  the  Result  phase  all 
bytes  shown  in  the  Command  Table  must  be  read.  The 
Read  Data  command,  for  example,  has  seven  bytes  of  data 
in  the  Result  phase.  All  seven  bytes  must  be  read  in  order 
to  successfully  complete  the  Read  Data  command.  The 
|xPD765A/|jlPD7265  will  not  accept  a  new  command  until 
all  seven  bytes  have  been  read.  Other  commands  may 
require  fewer  bytes  to  be  read  during  the  Result  phase. 
The  (jlPD765A/|ulPD7265  contains  five  Status  Registers. 
The  Main  Status  Register  mentioned  above  may  be  read 
by  the  processor  at  any  time.  The  other  four  Status  Regis- 
ters (ST0,  ST1 ,  ST2,  and  ST3)  are  available  only  during 
the  Result  phase  and  may  be  read  only  after  completing 
a  command.  The  particular  command  that  has  been 
executed  determines  how  many  of  the  Status  Registers 
will  be  read. 

The  bytes  of  data  which  are  sent  to  the  fxPD765A/ 
|ulPD7265  to  form  the  Command  phase  and  are  read  out 
of  the  |ULPD765A/fxPD7265  in  the  Result  phase  must 
occur  in  the  order  shown  in  the  Command  Table.  That 
is,  the  Command  Code  must  be  sent  first  and  the  other 
bytes  sent  in  the  prescribed  sequence.  No  foreshortening 
of  the  Command  or  Result  phases  is  allowed.  After  the  last 
byte  of  data  in  the  Command  phase  is  sent  to  the  (jlPD765A/ 
|ulPD7265,  the  Execution  phase  automatically  starts.  In  a 
similar  fashion,  when  the  last  byte  of  data  is  read  out  in  the 
Result  phase,  the  command  is  automatically  ended  and  the 
|jlPD765A/|jlPD7265  is  ready  for  a  new  command. 
Polling  Feature  of  the  |.  PD765A  ,  PD7265 
After  Reset  has  been  sent  to  the  (jlPD765A/|jlPD7265,  the 
Unit  Select  lines  US0  and  US1  will  automatically  go  into  a 
polling  mode.  In  between  commands  (and  between  step 
pulses  in  the  Seek  command)  the  fxPD765A/|jiPD7265 
polls  all  four  FDDs  looking  for  a  change  in  the  Ready  line 
from  any  of  the  drives.  If  the  Ready  line  changes  state 
(usually  due  to  a  door  opening  or  closing),  then  the 
(jlPD765A/|jlPD7265  will  generate  an  interrupt.  When  Sta- 
tus Register  0  (ST0)  is  read  (after  Sense  Interrupt  Status  is 
issued),  Not  Ready  (NR)  will  be  indicated.  The  polling  of  the 
Ready  line  by  the  (xPD765A/(jlPD7265  occurs  continuously 
between  commands,  thus  notifying  the  processor  which 
drives  are  on  or  off  line.  Each  drive  is  polled  every  1.024  ms 
except  during  the  Read/Write  commands.  When  used  with 
a  4  MHz  clock  for  interfacing  to  minifloppies,  the  polling  rate 
is  2.048  ms. 


6-8 


,PD765A/7265 


-  Approx  1.0  msec- 


figure  1.    (polling  feature) 

Read  Data 

A  set  of  nine  (9)  byte  words  are  required  to  place  the  FDC 
into  the  Read  Data  Mode.  After  the  Read  Data  command 
has  been  issued  the  FDC  loads  the  head  (if  it  is  in  the 
unloaded  state),  waits  the  specified  head  settling  time 
(defined  in  the  Specify  Command),  and  begins  reading 
ID  Address  Marks  and  ID  fields.  When  the  current  sector 
number  ("R")  stored  in  the  ID  Register  (IDR)  compares 
with  the  sector  number  read  off  the  diskette,  then  the  FDC 
outputs  data  (from  the  data  field)  byte-to-byte  to  the  main 
system  via  the  data  bus. 

After  completion  of  the  read  operation  from  the  current 
sector,  the  Sector  Number  is  incremented  by  one,  and  the 
data  from  the  next  sector  is  read  and  output  on  the  data 
bus.  This  continuous  read  function  is  called  a  "Multi- 
Sector  Read  Operation'.'  The  Read  Data  Command  may 
be  terminated  by  the  receipt  of  a  Terminal  Count  signal. 
TC  should  be  issued  at  the  same  time  that  the  DACK  for 
the  last  byte  of  data  is  sent.  Upon  receipt  of  this  signal, 
the  FDC  stops  outputting  data  to  the  processor,  but  will 
continue  to  read  data  from  the  current  sector,  check 
CRC  (Cyclic  Redundancy  Count)  bytes,  and  then  at  the 
end  of  the  sector  terminate  the  Read  Data  Command. 
The  amount  of  data  which  can  be  handled  with  a  single 
command  to  the  FDC  depends  upon  MT  (multitrack),  MF 
(MFM/FM),  and  N  (Number  of  Bytes/Sector).  Table  1  below 
shows  the  Transfer  Capacity. 

Transfer  Capacity 


Multi- 
Track 
MT 

MFM/ 
FM 
MF 

Bytes/ 
Sector 
N 

Maximum  Transfer  Capacity 
(Bytes/Sector) 
(Number  of  Sectors) 

Final  Sector 
Read  from 
Diskettes 

0 
0 

0 
1 

00 
01 

(128)  (26) 
(256)  (26) 

3,328 
6,656 

26  at  Side  0 
or  26  at  Side  1 

1 
1 

0 

1 

00 
01 

(128)  (52) 
(256)  (52) 

6,656 
13,312 

26  at  Side  1 

0 

.  0 

0 

1 

01 
02 

(256)  (15) 
(512)  (15) 

3,840 
7,680 

15  at  SideO 
or  15  at  Side  1 

1 
1 

0 

1 

01 
02 

(256)  (30) 
(512)  (30) 

7,680 
15,360 

15  at  Side  1 

0 
0 

0 

1 

02 
03 

(512)  (8) 
(1024)  (8) 

4,096 
8,192 

8  at  Side  0 
or  8  at  Side  1 

1 
1 

0 

1 

02 
03 

(512)  (16) 
(1024)  (16) 

8,192 
16,384 

8  at  Side  1 

The  "multi-track"  function  (MT)  allows  the  FDC  to  read 
data  from  both  sides  of  the  diskette.  For  a  particular  cylin- 
der, data  will  be  transferred  starting  at  Sector  1 ,  Side  0  and 
completing  at  Sector  L,  Side  1  (Sector  L  =  last  sector  on 
the  side).  Note,  this  function  pertains  to  only  one  cylinder 
(the  same  track)  on  each  side  of  the  diskette. 
When  N  =  0,  then  DTL  defines  the  data  length  which 
the  FDC  must  treat  as  a  sector.  If  DTL  is  smaller  than  the 
actual  data  length  in  a  Sector,  the  data  beyond  DTL- in  the 
Sector,  is  not  sent  to  the  Data  Bus.  The  FDC  reads  (inter- 
nally) the  complete  Sector  performing  the  CRC  check,  and 


depending  upon  the  manner  of  command  termination,  may 
perform  a  Multi-Sector  Read  Operation.  When  N  is  non- 
zero, then  DTL  has  no  meaning  and  should  be  set  to 
FF  Hexidecimal. 

At  the  completion  of  the  Read  Data  Command,  the  head 
is  not  unloaded  until  after  Head  Unload  Time  Interval 
(specified  in  the  Specify  Command)  has  elapsed.  If  the 
processor  issues  another  command  before  the  head 
unloads  then  the  head  settling  time  may  be  saved  between 
subsequent  reads.  This  time  out  is  particularly  valuable 
when  a  diskette  is  copied  from  one  drive  to  another. 
If  the  FDC  detects  the  Index  Hole  twice  without  finding 
the  right  sector,  (indicated  in  "R"),  then  the  FDC  sets  the 
ND  (No  Data)  flag  in  Status  Register  1  to  a  1  (high),  and 
terminates  the  Read  Data  Command.  (Status  Register  0 
also  has  bits  7  and  6  set  to  0  and  1  respectively.) 
After  reading  the  ID  and  Data  Fields  in  each  sector,  the 
FDC  checks  the  CRC  bytes.  If  a  read  error  is  detected 
(incorrect  CRC  in  ID  field),  the  FDC  sets  the  DE  (Data 
Error)  flag  in  Status  Register  1  to  a  1  (high),  and  if  a  CRC 
error  occurs  in  the  Data  Field  the  FDC  also  sets  the  DD 
(Data  Error  in  Data  Field)  flag  in  Status  Register  2  to  a  1 
(high),  and  terminates  the  Read  Data  Command.  (Status 
Register  0  also  has  bits  7  and  6  set  to  0  and  1  respectively ) 
If  the  FDC  reads  a  Deleted  Data  Address  Mark  off  the 
diskette,  and  the  SK  bit  (bit  D5  in  the  first  Command  Word) 
is  not  set  (SK  =  0),  then  the  FDC  sets  the  CM  (Control 
Mark)  flag  in  Status  Register  2  to  a  1  (high),  and  terminates 
the  Read  Data  Command,  after  reading  all  the  data  in  the 
Sector  If  SK  =  1 ,  the  FDC  skips  the  sector  with  the  Deleted 
Data  Address  Mark  and  reads  the  next  sector.  The  CRC 
bits  in  the  deleted  data  field  are  not  checked  when  SK  =  1 
During  disk  data  transfers  between  the  FDC  and  the  pro- 
cessor, via  the  data  bus,  the  FDC  must  be  serviced  by  the 
processor  every  27  lis  in  the  FM  Mode,  and  every  13  \xs  in 
the  MFM  Mode,  or  the  FDC  sets  the  OR  (Overrun)  flag  in 
Status  Register  1  to  a  1  (high),  and  terminates  the  Read 
Data  Command. 

If  the  processor  terminates  a  read  (or  write)  operation 
in  the  FDC,  then  the  ID  information  in  the  Result  Phase 
is  dependent  upon  the  state  of  the  MT  bit  and  EOT  byte. 
Table  2  shows  the  values  for  C,  H,  R,  and  N,  when  the 
processor  terminates  the  Command. 

Functional  Description  of  Commands 


Final  Sector  Transferred  to 

ID  Information  at  Result  Phase 

MT 

HD 

Processor 

C 

H 

R 

N 

0 

Less  than  EOT 

NC 

NC 

R  +  1 

NC 

0 

0 

Equal  to  EOT 

C  +  1 

NC 

R  =  01 

NC 

1 

Less  than  EOT 

NC 

NC 

R  +  1 

NC 

1 

Equal  to  EOT 

C  +  1 

NC 

R  =  01 

NC 

0 

Less  than  EOT 

NC 

NC 

R  +  1 

NC 

1 

0 

Equal  to  EOT 

NC 

LSB 

R  =  01 

NC 

1 

Less  than  EOT 

NC 

NC 

R  +  1 

NC 

1 

Equal  to  EOT 

C  +  1 

LSB 

R  =  01 

NC 

Notes:   NC  (No  Change)  The  same  value  as  the  one  at  the  beginning  of  command  execution 
LSB  (Least  Significant  Bit)  The  least  significant  bit  of  H  is  complemented 

Write  Data 

A  set  of  nine  (9)  bytes  is  required  to  set  the  FDC  into  the 
Write  Data  mode.  After  the  Write  Data  command  has  been 
issued  the  FDC  loads  the  head  (if  it  is  in  the  unloaded 
state),  waits  the  specified  head  settling  time  (defined  in  the 
Specify  command),  and  begins  reading  ID  fields.  When  all 
four  bytes  loaded  during  the  command  (C,  H,  R,  N)  match 


6-9 


,.PD765A/7265 


the  four  bytes  of  the  ID  field  from  the  diskette,  the  FDC 
takes  data  from  the  processor  byte-by-byte  via  the  data  bus 
and  outputs  it  to  the  FDD. 

After  writing  data  into  the  current  sector,  the  sector  number 
stored  in  "R"  is  incremented  by  one,  and  the  next  data  field 
is  written  into.  The  FDC  continues  this  "Multi sector  Write 
Operation"  until  the  issuance  of  a  Terminal  Count  signal. 
If  a  Terminal  Count  signal  is  sent  to  the  FDC  it  continues 
writing  into  the  current  sector  to  complete  the  data  field.  If 
the  Terminal  Count  signal  is  received  while  a  data  field  is 
being  written  then  the  remainder  of  the  data  field  is  filled 
with  zeros. 

The  FDC  reads  the  ID  field  of  each  sector  and  checks  the 
CRC  bytes.  If  the  FDC  detects  a  read  error  (CRC  error) 
in  one  of  the  ID  fields,  it  sets  the  DE  (Data  Error)  flag  of 
Status  Register  1  to  a  1  (high)  and  terminates  the  Write 
Data  command.  (Status  Register  0  also  has  bits  7  and  6 
set  to  0  and  1  respectively.) 

The  Write  command  operates  in  much  the  same  manner  as 
the  Read  command.  The  following  items  are  the  same,  and 
one  should  refer  to  the  Read  Data  command  for  details: 

•  Transfer  Capacity 

•  EN  (End  of  Cylinder)  Flag 

•  ND  (No  Data)  Flag 

•  Head  Unload  Time  Interval 

•  ID  Information  when  the  processor  terminates  command 

•  Definition  of  DTL  when  N  =  0  and  when  N  =h  0 

In  the  Write  Data  mode,  data  transfers  between  the  pro- 
cessor and  FDC,  via  the  data  bus,  must  occur  every  27  jjls 
in  the  FM  mode  and  every  1 3  (jls  in  the  MFM  mode.  If  the 
time  interval  between  data  transfers  is  longer  than  this, 
then  the  FDC  sets  the  OR  (Overrun)  flag  in  Status  Reg- 
ister 1  to  a  1  (high)  and  terminates  the  Write  Data  com- 
mand. (Status  Register  0  also  has  bits  7  and  6  set  to  0  and 
1  respectively.) 

Write  Deleted  Data 

This  command  is  the  same  as  the  Write  Data  com- 
mand except  a  Deleted  Data  Address  mark  is  written  at 
the  beginning  of  the  data  field  instead  of  the  normal  Data 
Address  mark. 

Read  Deleted  Data 

This  command  is  the  same  as  the  Read  Data  command 
except  that  when  the  FDC  detects  a  Data  Address  mark 
at  the  beginning  of  a  data  field  (and  SK  =  0  (low)),  it  will 
read  all  the  data  in  the  sector  and  set  the  CM  flag  in  Status 
Register  2  to  a  1  (high),  and  then  terminate  the  command. 
If  SK  =  1,  then  the  FDC  skips  the  sector  with  the  Data 
Address  mark  and  reads  the  next  sector. 
Read  A  Track 

This  command  is  similar  to  the  Read  Data  command 
except  that  this  is  a  continuous  Read  operation  where  the 
entire  data  field  from  each  of  the  sectors  is  read.  Immedi- 
ately after  sensing  the  index  hole,  the  FDC  starts  reading 
all  data  fields  on  the  track  as  continuous  blocks  of  data.  If 
the  FDC  finds  an  error  in  the  ID  or  Data  CRC  check  bytes,  it 
continues  to  read  data  from  the  track.  The  FDC  compares 
the  ID  information  read  from  each  sector  with  the  value 
stored  in  the  IDR  and  sets  the  ND  flag  of  Status  Register  1 
to  a  1  (high)  if  there  is  no  comparison.  Multitrack  or  skip 
operations  are  not  allowed  with  this  command. 
This  command  terminates  when  the  number  of  sectors 
read  is  equal  to  EOT.  If  the  FDC  does  not  find  an  ID 


Address  mark  on  the  diskette  after  it  senses  the  index 
hole  for  the  second  time,  it  sets  the  MA  (Missing  Address 
mark)  flag  in  Status  Register  1  to  a  1  (high)  and  terminates 
the  command.  (Status  Register  0  has  bits  7  and  6  set  to 
0  and  1  respectively.) 

Read  ID 

The  Read  ID  command  is  used  to  give  the  present  position 
of  the  recording  head.  The  FDC  stores  the  values  from  the 
first  ID  field  it  is  able  to  read  If  no  proper  ID  Address  mark 
is  found  on  the  diskette  before  the  index  hole  is  encoun- 
tered for  the  second  time,  then  the  MA  (Missing  Address 
mark)  flag  in  Status  Register  1  is  set  to  a  1  (high),  and  if 
no  data  is  found  then  the  ND  (No  Data)  flag  is  also  set  in 
Status  Register  1  to  a  1  (high).  The  command  is  then  termi- 
nated with  bits  7  and  6  in  Status  Register  0  set  to  0  and  1 
respectively.  During  this  command  there  is  no  data  transfer 
between  FDC  and  the  CPU  except  during  the  result  phase. 

Format  A  Track 

The  Format  command  allows  an  entire  track  to  be  format- 
ted. After  the  index  hole  is  detected,  data  is  written  on  the 
diskette;  Gaps,  Address  marks,  ID  fields  and  data  fields, 
all  per  the  IBM  System  34  (Double  Density)  or  System 
3740  (Single  Density)  format  are  recorded.  The  particular 
format  which  wHI  be  written  is  controlled  by  the  values  pro- 
grammed into  N  (Number  of  bytes/sector),  SC  (Sectors/ 
Cylinder),  GPL  (Gap  Length),  and  D  (Data  pattern)  which 
are  supplied  by  the  processor  during  the  Command  phase. 
The  data  field  is  filled  with  the  byte  of  data  stored  in  D.  The 
ID  field  for  each  sector  is  supplied  by  the  processor;  that  is, 
four  data  requests  per  sector  are  made  by  the  FDC  for  C 
(Cylinder  number),  H  (Head  number),  R  (Sector  number) 
and  N  (Number  of  bytes/sector).  This  allows  the  diskette  to 
be  formatted  with  nonsequential  sector  numbers,  if  desired. 
The  processor  must  send  new  values  for  C,  H,  R,  and 
N  to  the  |jlPD765A/|jlPD7265  for  each  sector  on  the  track 
If  FDC  is  set  for  the  DMA  mode,  it  will  issue  four  DMA 
requests  per  sector.  If  it  is  set  for  the  Interrupt  mode,  it  will 
issue  four  interrupts  per  sector  and  the  processor  must 
supply  C,  H,  R,  and  N  loads  for  each  sector.  The  contents 
of  the  R  register  are  incremented  by  1  after  each  sector  is 
formatted;  thus,  the  R  register  contains  a  value  of  R  when 
it  is  read  during  the  Result  phase.  This  incrementing  and 
formatting  continues  for  the  whole  track  until  the  FDC 
detects  the  index  hole  for  the  second  time,  whereupon  it 
terminates  the  command. 

If  a  Fault  signal  is  received  from  the  FDD  at  the  end  of  a 
Write  operation,  then  the  FDC  sets  the  EC  flag  of  Status 
Register  0  to  a  1  (high)  and  terminates  the  command  after 
setting  bits  7  and  6  of  Status  Register  0  to  0  and  1  respec- 
tively. Also  the  loss  of  a  Ready  signal  at  the  beginning  of 
a  command  execution  phase  causes  bits  7  and  6  of  Status 
Register  0  to  be  set  to  0  and  1  respectively. 
Table  1  shows  the  relationship  between  N,  SC,  and  GPL 
for  various  sector  sizes. 


6-10 


I.PD765A/7265 


Functional  Description  of  Commands  (Cont.) 


Format 

Sector  Size 

N 

SC 

GPL® 

GPL@® 

8"  Standard  Floppy 



— ?Z — 

~bT  



FM  Mode 

512 

02 

08 

1B 

3A 

1024 

03 

04 

47 

8A 

2048 

04 

02 

C8 

FF 

4096 

05 

01 

C8 

FF 

256 

01 

1A 

0E 

36 

512 

02 

OF 

1B 

54 

MFM 

1024 

03 

08 

35 

74 

Mode® 

2048 

04 

04 

99 

FF 

4096 

05 

02 

C8 

FF 

8192 

06 

01 

C8 

FF 

5V4"  Minifloppy 

128  bytes/sector 

00 

12 

07 

09 

128 

00 

10 

10 

19 

FM  Mode 

256 

01 

08 

18 

30 

512 

02 

04 

46 

87 

1024 

03 

02 

C8 

FF 

2048 

04 

01 

C8 

FF 

256 

01 

12 

OA 

OC 

256 

01 

10 

20 

32 

MFM 

512 

02 

08 

2A 

50 

Mode® 

1024 

03 

04 

80 

F0 

2048 

04 

02 

C8 

FF 

4096 

05 

01 

C8 

FF 

3W  Sony  Microfloppy 

128  bytes/sector 

0 

OF 

07 

1B 

FM  Mode 

256 

1 

09 

0E 

2A 

512 

2 

05 

1B 

3A 

256 

1 

OF 

0E 

36 

MFM 

Mode® 

512 

2 

09 

1B 

54 

1024 

3 

05 

35 

74 

shows  the  status  of  bits  SH  and  SN  under  various  condi- 
tions of  Scan. 


Table  1 

Notes:  ©  Suggested  values  of  GPL  in  Read  or  Write  commands  to  avoid  splice  point  between 
data  field  and  ID  field  of  contiguous  sections 
®  Suggested  values  of  GPL  in  format  command 
®  All  values  except  sector  size  are  hexidecimal 

®  In  MFM  mode  FDC  cannot  perform  a  Read/Write/format  operation  with  128  bytes/ 
sector  (N  =  00) 


Scan  Commands 

The  Scan  commands  allow  data  which  is  being  read  from 
the  diskette  to  be  compared  against  data  which  is  being 
supplied  from  the  main  system.  The  FDC  compares  the 
data  on  a  byte-by-byte  basis  and  looks  for  a  sector  of  data 


which  meets  the  conditions  of  DF 


D, 


Processor 


,  or  D, 


FDD  ; 


DP 

.  The  hexidecimal  byte 


of  FF  either  from  memory  or  from  FDD  can  be  used  as  a 
mask  byte  because  it  always  meets  the  condition  of  the 
comparison.  One's  complement  arithmetic  is  used  for  com- 
parison (FF  =  largest  number,  00  =  smallest  number). 
After  a  whole  sector  of  data  is  compared,  if  the  conditions 
are  not  met,  the  sector  number  is  incremented  (R  +  STP  — > 
R),  and  the  scan  operation  is  continued.  The  scan  opera- 
tion continues  until  one  of  the  following  conditions  occur: 
the  conditions  for  scan  are  met  (equal,  low,  or  high),  the  last 
sector  on  the  track  is  reached  (EOT),  or  the  terminal  count 
signal  is  received. 

If  the  conditions  for  scan  are  met,  then  the  FDC  sets  the 
SH  (Scan  Hit)  flag  of  Status  Register  2  to  a  1  (high)  and 
terminates  the  Scan  command.  If  the  conditions  for  scan 
are  not  met  between  the  starting  sector  (as  specified  by  R) 
and  the  last  sector  on  the  cylinder  (EOT),  then  the  FDC 
sets  the  SN  (Scan  Not  Satisfied)  flag  of  Status  Register  2  to 
a  1  (high)  and  terminates  the  Scan  command.  The  receipt 
of  a  Terminal  Count  signal  from  the  processor  or  DMA  con- 
troller during  the  scan  operation  will  cause  the  FDC  to 
complete  the  comparison  of  the  particular  byte  which  is  in 
process  and  then  to  terminate  the  command.  Table  2 


Status  Register  2 

Command 

Bit  2  =  SN 

Bit  3  =  SH 

Comments 

Scan  Equal 

0 

1 

DFDD  =  DProcessor 

1 

0 

DFDD  *  DProcessor 

Scan  Low 
or  Equal 

0 

1 

Dpoo  =  Dproce8Sor 

0 

0 

DFDD  <  Processor 

1 

0 

DFDD  >  DProcessor 

Scan  High 
or  Equaf 

0 

1 

DFDD  =  DProcessor 

0 

0 

DFDD  >  DProcessor 

1 

0 

DFDD  <  DProcessor 

Table  2 

6- 


If  the  FDC  encounters  a  Deleted  Data  Address  mark  on 
one  of  the  sectors  (and  SK  =  0),  then  it  regards  the  sector 
as  the  last  sector  on  the  cylinder,  sets  the  CM  (Control 
Mark)  flag  of  Status  Register  2  to  a  1  (high)  and  terminates 
the  command.  If  SK  =  1 ,  the  FDC  skips  the  sector  with  the 
Deleted  Address  mark  and  reads  the  next  sector.  In  the 
second  case  (SK  =  1),  the  FDC  sets  the  CM  (Control  Mark) 
flag  of  Status  Register  2  to  a  1  (high)  in  order  to  show  tnat  a 
Deleted  sector  had  been  encountered. 
When  either  the  STP  (contiguous  sectors  =  01 ,  or  alter- 
nate sectors  =  02)  sectors  are  read  or  the  MT  (Multitrack) 
is  programmed,  it  is  necessary  to  remember  that  the  last 
sector  on  the  track  must  be  read.  For  example,  if  STP  = 
02,  MT  =  0,  the  sectors  are  numbered  sequentially  1 
through  26  and  the  Scan  command  is  started  at  sector  21 , 
the  following  will  happen:  Sectors  21,  23,  and  25  will  be 
read,  then  the  next  sector  (26)  will  be  skipped  and  the  index 
hole  will  be  encountered  before  the  EOT  value  of  26  can 
be  read.  This  will  result  in  an  abnormal  termination  of  the 
command.  If  the  EOT  had  been  set  at  25  or  the  scanning 
started  at  sector  20,  then  the  Scan  command  would  be 
completed  in  a  normal  manner. 

During  the  Scan  command,  data  is  supplied  by  either  the 
processor  or  DMA  Controller  for  comparison  against  the 
data  read  from  the  diskette.  In  order  to  avoid  having  the  OR 
(Overrun)  flag  set  in  Status  Register  1 ,  it  is  necessary  to 
have  the  data  available  in  less  than  27  lls  (FM  mode)  or  13 
lis  (MFM  mode).  If  an  Overrun  occurs,  the  FDC  ends  the 
command  with  bits  7  and  6  of  Status  Register  0  set  to  0 
and  1 ,  respectively. 

Seek 

The  Read/Write  head  within  the  FDD  is  moved  from  cylin- 
der to  cylinder  under  control  of  the  Seek  command.  FDC 
has  four  independent  Present  Cylinder  Registers  for  each 
drive.  They  are  cleared  only  after  the  Recalibrate  com- 
mand. The  FDC  compares  the  PCN  (Present  Cylinder 
Number)  which  is  the  current  head  position  with  the  NCN 
(New  Cylinder  Number),  and  if  there  is  a  difference,  per- 
forms the  following  operations: 

PCN  <  NCN:  Direction  signal  to  FDD  set  to  a  1  (high),  and 

Step  Pulses  are  issued.  (Step  In) 
PCN  >  NCN:  Direction  signal  to  FDD  set  to  a  0  (low),  and 

Step  Pulses  are  issued.  (Step  Out) 
The  rate  at  which  Step  pulses  are  issued  is  controlled  by 
SRT  (Stepping  Rate  Time)  in  the  Specify  command.  After 
each  Step  pulse  is  issued  NCN  is  compared  against  PCN, 
and  when  NCN  =  PCN,  the  SE  (Seek  End)  flag  is  set  in 
Status  Register  0  to  a  1  (high),  and  the  command  is  termi- 
nated. At  this  point  FDC  interrupt  goes  high.  Bits  D0B-D3B 
in  the  Main  Status  Register  are  set  during  the  Seek  opera- 
tion and  are  cleared  by  the  Sense  Interrupt  Status 
command. 
11 


MPD765 A/7265 

During  the  command  phase  of  the  Seek  operation  the 
FDC  is  in  the  FDC  Busy  state,  but  during  the  execution 
phase  it  is  in  the  Nonbusy  state.  While  the  FDC  is  in  the 
Nonbusy  state,  another  Seek  command  may  be  issued, 
and  in  this  manner  parallel  Seek  operations  may  be  done 
on  up  to  four  drives  at  once.  No  other  command  can  be 
issued  for  as  long  as  the  FDC  is  in  the  process  of  sending 
step  pulses  to  any  drive. 

If  an  FDD  is  in  a  Not  Ready  state  at  the  beginning  of  the 
command  execution  phase  or  during  the  Seek  operation, 
then  the  NR  (Not  Ready)  flag  is  set  in  Status  Register  0  to  a 
1  (high),  and  the  command  is  terminated  after  bits  7  and  6 
of  Status  Register  0  are  set  to  0  and  1  respectively. 
If  the  time  to  write  three  bytes  of  Seek  command  exceeds 
150jxs,  the  timing  between  the  first  two  step  pulses  may 
be  shorter  than  set  in  the  Specify  command  by  as  much 
as  1ms. 
Recalibrate 

The  function  of  this  command  is  to  retract  the  Read/Write 
head  within  the  FDD  to  the  Track  0  position.  The  FDC 
clears  the  contents  of  the  PCN  counter  and  checks  the 
status  of  the  Track  0  signal  from  the  FDD.  As  long  as  the 
Track  0  signal  is  low,  the  Direction  signal  remains  0  (low) 
and  step  pulses  are  issued.  When  the  Track  0  signal  goes 
high,  the  SE  (Seek  End)  flag  in  Status  Register  0  is  set  to 
a  1  (high)  and  the  command  is  terminated.  If  the  Track  0 
signal  is  still  low  after  77  step  pulses  have  been  issued,  the 
FDC  sets  the  SE  (Seek  End)  and  EC  (Equipment  Check) 
flags  of  Status  Register  0  to  both  1s  (highs)  and  terminates 
the  command  after  bits  7  and  6  of  Status  Register  0  are  set 
to  0  and  1  respectively. 

The  ability  to  do  overlap  Recalibrate  commands  to  multiple 
FDDs  and  the  loss  of  the  Ready  signal,  as  described  in  the 
Seek  command,  also  applies  to  the  Recalibrate  command. 
If  the  Diskette  has  more  than  77  tracks,  then  Recalibrate 
command  should  be  issued  twice,  in  order  to  position  the 
Read/Write  head  to  the  Track  0. 


Sense  Interrupt  Status 

An  Interrupt  signal  is  generated  by  the  FDC  for  one  of  the 
following  reasons: 

1 .  Upon  entering  the  Result  phase  of: 

a.  Read  Data  command 

b.  Read  A  Track  command 

c.  Read  ID  command 

d.  Read  Deleted  Data  command 

e.  Write  Data  command 

f.  Format  A  Cylinder  command 

g.  Write  Deleted  Data  command 

h.  Scan  commands 

2.  Ready  Line  of  FDD  changes  state 

3.  End  of  Seek  or  Recalibrate  command 

4.  During  Execution  phase  in  the  non-DMA  mode 
Interrupts  caused  by  reasons  1  and  4  above  occur  during 
normal  command  operations  and  are  easily  discernible  by 
the  processor.  During  an  execution  phase  in  non-DMA 
mode,  DB5  in  the  Main  Status  Register  is  high.  Upon  enter- 
ing the  Result  phase  this  bit  gets  cleared.  Reasons  1  and  4 
do  not  require  Sense  Interrupt  Status  commands.  The  inter- 
rupt is  cleared  by  Reading/Writing  data  to  the  FDC.  Inter- 
rupts caused  by  reasons  2  and  3  above  may  be  uniquely 
identified  with  the  aid  of  the  Sense  Interrupt  Status  com- 
mand. This  command  when  issued  resets  the  Interrupt 
signal  and  via  bits  5, 6,  and  7  of  Status  Register  0  identifies 
the  cause  of  the  interrupt. 


Seek  End 

Interrupt  Code 

Bit  5 

Bit  6            Bit  7 

Cause 

0 

1  1 

Ready  Line  changed  state,  either  polarity 

1 

0  0 

Normal  Termination  of  Seek  or  Recalibrate 
command 

1 

1  0 

Abnormal  Termination  of  Seek  or  Recali- 
brate command 

Table  3 


The  Sense  interrupt  Status  command  is  used  in  conjunc- 
tion with  the  Seek  and  Recalibrate  commands  which  have 
no  result  phase.  When  the  disk  drive  has  reached  the 
desired  head  position  the  |jiPD765A/fxPD7265  will  set  the 
Interrupt  line  true.  The  host  CPU  must  then  issue  a  Sense 
Interrupt  Status  command  to  determine  the  actual  cause 
of  the  interrupt,  which  could  be  Seek  End  or  a  change  in 
ready  status  from  one  of  the  drives.  A  graphic  example 
is  shown  : 


Seek,  Recalibrate,  and  Sense  Interrupt  Status 


 Seek  (or  Recalibrate)  Command  

-  Command  Phase  ^ —  Execution  Phase  - 


i —  Sense  Interrupt  Status  Command  — »-| 
y-  Command  Phase  »|«  Result  Phase  — **j 


^"XTLTLfLrLTLLr 

A.-irnijnLrm 


~ULT 


i_iri  uri 


RD 

U 

U  U 

I 
I 

U 

WR 

u 

u 

U 

U 

DIO 

u 

u  u 

u 

JL 

JL 

RQM 

n 

n  n 

n 

I!   

i 

Op  Code  for 
Instruction 
Written 
into  765 A 

HD/Drive  Not 
Written  — 
into  765A 

NCN  Written 
into  765A  ""*" 

Op  Code  for 

Instruction   ^ 

Written 
into  765 A 

Status 

Register  STO  ^ 

Read  by 
Processor 

RCN  Read  by  „ 
Processor 

6-12 


Specify 

The  Specify  command  sets  the  initial  values  for  each  of  the 
three  internal  timers.  The  HUT  (Head  Unload  Time)  defines 
the  time  from  the  end  of  the  execution  phase  of  one  of  the 
Read/Write  commands  to  the  head  unload  state.  This  timer 
is  programmable  from  16  to  240ms  in  increments  of  16ms 
(01  =  16ms,  02  -  32ms . . .  0F16  -  240ms).  The  SRT 
(Step  Rate  Time)  defines  the  time  interval  between  adja- 
cent step  pulses.  This  timer  is  programmable  from  1  to  16 
ms  in  increments  of  1  ms  (F  =  1ms,  E  =  2ms,  D  =  3ms, 
etc.).  The  HLT  (Head  Load  Time)  defines  the  time  between 
when  the  Head  Load  signal  goes  high  and  the  Read/Write 
operation  starts.  This  timer  is  programmable  from  2  to  254 
ms  in  increments  of  2  ms  (01  =  2ms,  02  =  4ms,  03  = 
6ms . . .  7F  =  254ms). 

The  time  intervals  mentioned  above  are  a  direct  function  of 
the  clock  (CLK  on  pin  19).  Times  indicated  above  are  for  an 
8MHz  clock;  if  the  clock  was  reduced  to  4MHz  (minifloppy 
application)  then  all  time  intervals  are  increased  by  a  factor 
of  2. 

The  choice  of  a  DMA  or  non-DMA  operation  is  made  by 
the  ND  (Non-DMA)  bit.  When  this  bit  is  high  (ND  =  1)  the 
Non-DMA  mode  is  selected,  and  when  ND  =  0  the  DMA 
mode  is  selected. 


(  PD765A/7265 

Sense  Drive  Status 

This  command  may  be  used  by  the  processor  whenever  it 
wishes  to  obtain  the  status  of  the  FDDs.  Status  Register  3 
contains  the  Drive  Status  information  stored  internally  in 
FDC  registers. 
Invalid 

If  an  Invalid  command  is  sent  to  the  FDC  (a  command  not 
defined  above),  then  the  FDC  will  terminate  the  command 
after  bits  7  and  6  of  Status  Register  0  are  set  to  1  and  0 
respectively.  No  interrupt  is  generated  by  the  jjlPD765A/ 
fxPD7265  during  this  condition.  Bits  6  and  7  (DIO  and 
RQM)  in  the  Main  Status  Register  are  both  high  (1),  indicat- 
ing to  the  processor  that  the  fjuPD765A/^PD7265  is  in  the 
Result  phase  and  the  contents  of  Status  Register  0  (ST0) 
must  be  read.  When  the  processor  reads  Status  Register 
0  it  will  find  an  80  hex,  indicating  an  Invalid  command 
was  received. 

A  Sense  Interrupt  Status  command  must  be  sent  after 
a  Seek  or  Recalibrate  Interrupt,  otherwise  the  FDC  will 
consider  the  next  command  to  be  an  Invalid  command. 
In  some  applications  the  user  may  wish  to  use  this  com- 
mand as  a  No-Op  command  to  place  the  FDC  in  a  standby 
or  No  Operation  state. 


V.PD765A  (FM  Mode) 


GAP  4a 

SYNC 

IAM 

GAP  1 

SYNC 

IDAM 

C 

S 

N 

C 

GAP  2 

SYNC 

DATA  AM 

DATA 

C 

GAP  3 

GAP  4b 

40x 

6x 

26x 

6x 

Y 

H 

E 

R 

11x 

6x 

© 

R 

© 

FF 

00 

FC 

FF 

00 

FE 

L 

D 

C 

O 

C 

FF 

00 

FB  or  F8 

C 

-  Repeat  N  Times  - 


txPD7265  (FM  Mode) 


GAP  1 

SYNC 

IDAM 

C 

H 

S 

N 
O 

C 

GAP  2 

SYNC 

DATA  AM 

DATA 

C 

GAP  3 

GAP  4 

16x 

6x 

Y 

D 

E 

R 

11x 

6x 

FB  or  F8 

© 

R 

© 

FF 

00 

FE 

L 

C 

C 

FF 

00 

C 

-  Repeat  N  Times  - 


[x,PD765A  (MFM  Mode) 


GAP  4a 

SYNC 

IAM 

GAP  1 

SYNC 

IDAM 

C 

S 

r. 

GAP  2 

SYNC 

DATA  AM 

C 

GAP  3 

GAP  4b 

80x 
4E 

12x 
00 

3x 
C2 

FC 

50x 
4E 

12x 
00 

3x 
A1 

FE 

Y 
L 

H 
D 

E 
C 

N 
O 

>cco  | 

22x 
4E 

12x 
00 

3x 
A1 

FB 
F8 

DATA 

R 
C 

© 

-  Repeat  N  Times- 


\xPD7265  (MFM  Mode) 


GAP  1 

SYNC 

IDAM 

C 

H 
D 

S 

N 

O 

C 

GAP  2 

SYNC 

DATA  AM 

DATA 

© 

|     ooco  j 

GAP  3 

GAP  4 

32x 
4E 

12x 
00 

3x 
A1 

FE 

Y 
L 

E 
C 

R 
C 

22x 
4E 

12x 
00 

3x 
A1 

FB 
F8 

© 

-  Repeat  N  Times  - 


6-13 


|iPD765A/7265 

HPD765A 


GAP  4a 

1AM 

GAP1 

ID 

GAP  2 

DATA 

GAP  3  I 

ID 

GAP  4b 

Vco  SYNC 


i  \ 


uPD7265 


a  r 


z\  r 


  Read 

 Write 


Notes:  It  is  suggested  that  the  user  refer  to  the  following  application  notes 

©,#8  — for  an  example  of  an  actual  interface  as  well  as  a  theoretical  data  separator 
©'  #10  —  for  a  well  documented  example  of  a  working  phase  -  locked  loop 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD765AC/7265C 
Ceramic,  |xPD765AD/7265D 


6-14 


765A/7265DS-REV1-7-83-CAT-L 


SEC 


,PD7201A 
MULTIPROTOCOL  SERIAL 
COMMUNICATION  CONTROLLER 


Description 

The  |xPD7201  A  is  a  dual-channel  multifunction  peripheral 
communication  controller  designed  to  satisfy  a  wide  variety 
of  serial  data  communication  requirements  in  computer 
systems.  Its  basic  function  is  a  serial-to-parallel,  parallel- 
to-serial  converter/controller  and  within  that  role  it  is 
configurable  by  systems  software  so  its  "personality" 
can  be  optimized  for  a  given  serial  data  communica- 
tions application. 

The  |xPD7201A  is  capable  of  handling  asynchronous  and 
synchronous  byte-oriented  protocols  such  as  IBM  Bisync, 
and  synchronous  bit-oriented  protocols  such  as  HDLC  and 
IBM  SDLC.  This  versatile  device  can  also  be  used  to  sup- 
port virtually  any  other  serial  protocol  for  applications  other 
than  data  communications. 

The  |xPD7201  A  can  generate  and  check  CRC  codes  in  any 
synchronous  mode  and  can  be  programmed  to  check  data 
integrity  in  various  modes.  The  device  also  has  facilities  for 
modem  controls  in  both  channels.  In  applications  where 
these  controls  are  not  needed  the  modem  controls  can  be 
used  for  general-purpose  I/O. 


Pin  Configuration 

clkC  1 

RESET  C  2 
DCDAC  3 
RxCBC  4 
DCDBC  5 
CTSBC  6 
TxCB[  7 
TxDBC  8 
RxDBC  9 
RTSB/SYNCB  C  10 
WAITB/DRQTxA  C  11 
D7C  12 
D6C  13 
D5C  14 
D4C  15 
D3L~  16 
D2C  17 
D,  C  18 
D0C  19 
VSSC  20 


40  3  vcc 


,jiPD 
7201 A 


UCTSA 

□  RTSA 

□  TxDA 

□  TxCA 

□  RxCA 
3  RxDA 

□  SYNCA 

3  WAITA/DRQRxA 
3  DTRA/HAO 

□  PRO/DRQTxB 

□  PRT/DRQRxB 
3  INT 

3  INTA 

□  dtrb/hai 

□  b/a 
Dc/d 

□  cs 

□  rd 

□  wr 


Features 

□  Two  fully  independent  duplex  serial  channels 

□  Four  independent  DMA  channels  for  send/received  data 
for  both  serial  inputs/outputs 

□  Programmable  interrupt  vectors  and  interrupt  priorities 

□  Modem  controls  signals 

□  Variable  software  programmable  data  rate,  up  to  1.25M 
baud  at  5MHz  clock 

□  Double  buffered  transmitter  data  and  quadruply  buff- 
ered received  data 

□  Programmable  CRC  algorithm 

□  Selection  of  Interrupt,  DMA  or  Polling  mode  of  operation 

□  Asynchronous  operation 

-  Character  length:  5,  6,  7,  or  8  bits 
-Stop  bits:  1,  V/2,  2 

-Transmission  speed:  x1,  x16,  x32,  or  x64 
clock  frequency 

-  Parity:  odd,  even,  or  disable 

-  Break  generation  and  detection 

-  Interrupt  on  parity,  overrun,  or  framing  errors 

□  Monosync,  bisync,  and  external  sync  operations 

-  Software  selectable  sync  characters 

-  Automatic  sync  insertion 

-  CRC  generation  and  checking 

□  HDLC  and  SDLC  operations 

-  Abort  sequence  generation  and  detection 

-  Automatic  zero  insertion  and  detection 

-  Address  field  recognition 

-  CRC  generation  and  checking 

-  l-field  residue  handling 

□  N-channel  MOS  technology 

□  Single  +  5V  power  supply;  interface  to  most  micro- 
processors including  8080,  8085,  8086,  and  others. 

□  Single-phase  TTL  clock 

□  Available  in  plastic  and  ceramic  dual-in-line  packages 


Pin  Identification 


Pin 

No.        Symbol  Name 

I/O 

Description 

1           CLK           System  Clock 

I 

A  TTL-level  system  clock  signal  is 
applied  to  this  input  The  system 
clock  frequency  must  be  at  least  4.5 
times  the  data  clock  frequency 
applied  to  any  of  the  data  clock  inputs 
(TxC"A,  TxCB,  RxCa",  or  LRxCB). 

A  low  on  this  input  (one  complete  CLK 
cycle  minimum)  initializes  the  MPSC2 
to  the  following  conditions-  disables 
the  receivers  and  transmitters;  sets 
TxDA  and  TxDB  to  marking  (high); 
and  sets  the  modem  control  outputs 
(DTRA,  DTRB,  RTSA,  RTSB)  high. 
Additionally,  all  interrupts  are  dis- 
abled and  all  interrupt  and  DMA 
requests  are  cleared.  All  control  regis- 
ters must  be  rewritten  after  a  reset 
and  before  a  restart.  (Active  low) 


PCDA, 
DCDB 


Data  Carrier  Detect  I 


Data  carrier  detect  generally  indicates 
the  presence  of  valid  serial  data  at 
RxD.  The  MPSC2  may  be  programmed 
so  that  the  receiver  is  enabled  only 
when  DCD  is  low,  and  also  so  that  any 
change  in  state  that  lasts  longer  than 
the  minimum  specified  pulse  width 
causes  an  interrupt  and  latches  the 
DCD  status  bit  to  the  new  state. 
(Active  low) 


RxCA, 
RxCB 


Receiver  Clocks 


The  receiver  clock  controls  the  sam- 
pling and  shifting  of  serial  data  at 
RxD.  The  MPSC2  may  be  programmed 
so  that  the  clock  rate  is  1x,  16x,  32x,  or 
64x  the  data  rate.  RxD  is  sampled  on 
the  rising  edge  of  RxC.  RxC  features  a 
Schmitt-trigger  input  for  relaxed  rise 
and  fall  time  requirements.  (Active 
low)  


CJSA, 
CTSB 


Clear  to  send  generally  indicates  that 
the  receiving  modem  or  peripheral  is 
ready  to  receive  data  from  the  MPSC? 
The  MPSC2  may  be  programmed  so 
that  the  transmitter  is  enabled  only 
when  CTS  is  low.  As  with  DCD,  the 
MPSC2  may  be  programmed  to  cause 
an  interrupt  and  latch  the  new  state 
when  CTS  changes  state  for  longer 
than  the  minimum  specified  pulse 
width.  (Active  low) 


REV/1 
6-15 


|iPD7201A 

Pin  Identification 


Symbol 

Name  I/O 

Description 

7, 36 

TxCA, 
TxCB 

Transmitter  Clocks  I 

The  transmitter  clock  controls  the  rate 
at  which  data  is  shifted  out  at  TxD. 
The  MPSC2  may  be  programmed  so 
that  the  clock  rate  is  1x,  16x,  32x,  or 
64x  the  data  rate.  Data  changes  on  the 
falling  edge  of  TxC.  TxC  features  a 
Schmitt-trigger  input  for  relaxed  rise 
and  fall  time  requirements.  (Active 
low) 

8, 37 

TxDA, 
TxDB 

Transmit  Data  0 

Serial  data  from  the  MPSC2  is  output 
on  these  pins.  (Marking  high) 

9, 34 

RxDA, 
RxDB 

Receive  Data  I 

Serial  data  to  the  MPSC2  is  input  on 
these  pins.  (Marking  high) 

10,33     SYNCA,      Synchronization  I/O 
SYNCB  (Sync) 


The  function  of  the  Sync  pin  depends 
on  the  MPSC2  operating  mode.  In 
asynchronous  mode,  Sync  is  an  input 
that  the  processor  can  read.  It  can  be 
programmed  to  generate  an  interrupt 
in  the  same  manner  as  DCD  or  CTS. 
In  external  sync  mode,  SYNC  is  also 
an  input  that  notifies  the  MPSC2  that 
synchronization  has  been  achieved. 
(See  the  timing  waveforms  for  details). 
Once  synchronization  is  achieved, 
SYNC  should  be  held  low  until  syn- 
chronization is  lost  or  a  new  message 
is  about  to  start. 

In  internal  synchronization  modes 
(monosync,  bisync,  SDLC),  SYNC  is 
an  output  which  is  active  wherever  a 
Sync  character  match  is  made.  There 
is  no  qualifying  logic  associated  with 
this  function.  Regardless  of  character 
boundaries,  SYNC  is  active  on  any 
match.  (Active  low) 


10,38     RTSA,        Request  to  Send  0 
RTSB 


When  the  MPSC2  is  operated  in  one 
of  the  synchronous  modes,  RTSA 
and  RTSB  are  general-purpose  out- 
puts that  may  be  set  or  reset  with 
commands  to  the  MPSC2.  In  asyn- 
chronous mode,  RTS  is  active 
immediately  as  soon  as  it  is  pro- 
grammed on.  However,  when  pro- 
grammed off,  RTS  remains  active 
until  the  transmitter  is  completely 
empty.  This  feature  simplifies  the  pro- 
gramming required  to  perform  modem 
control.  (Active  low) 


11,29,  DRQTxA,  DMA  Request 
30,  32,  DRQTxB, 

DRQRxA, 

DRQRxB 


When  these  lines  are  active,  they  indi- 
cate to  a  DMA  controller  that  a 
transmitter  or  receiver  is  requesting  a 
DMA  data  transfer.  (Active  high) 


11,  32  WAITA 
WAITB 


Wait 


These  outputs  synchronize  the  pro- 
cessor with  the  MPSC2  when  block 
transfer  mode  is  used.  It  may  be  pro- 
grammed to  operate  with  either  the 
receiver  or  transmitter,  but  not  both 
simultaneously.  WAIT  is  normally 
inactive.  For  example,  if  the  processor 
tries  to  perform  an  inappropriate  data 
transfer  such  as  write  to  the  transmit- 
ter when  the  transmitter  buffer  is  full, 
the  WAIT  output  for  the  channel  is 

active  until  the  MPSC2  is  ready  to  

accept  the  data.  The  CS,  C/D,  B/A,  RD 
and  WR  inputs  must  remain  stable 
while  WAIT  is  active.  (Open  drain) 


12-19 

D0-D7 

Data  Bus 

I/O 

The  data  bus  lines  are  connected  to 
the  system  data  bus.  Data  or  status 
from  the  MPSC2  is  output  on  these 
lines  when  CS  and  RD  are  active;  data 
or  commands  are  latched  into  the 
MPSC2  on  the  rising  edge  of  WR  when 
CS  is  active.  (Three-state) 

20 

VSS 

Ground 

Ground. 

21 

WR 

Write 

This  input  (with  either  CS  during  a 
read  cycle  or  HAI  during  a  DMA  cycle) 
notifies  the  MPSC2  to  write  data  or 
control  information  to  the  device. 
(Active  low) 

22 

RD 

Read 

I 

This  input  (with  either  CS  during  a 
read  cycle  or  HAI  during  a  DMA  cycle) 
notifies  the  MPSC2  to  read  data  or  sta- 
tus from  the  device.  (Active  low) 

23 

CS 

Chip  Select 

I 

Chip  select  allows  the  MPSC2  to  trans- 
fer data  or  commands  during  a  read  or 
write  cycle.  (Active  low) 

Pin  Identification 


Pin 

No. 

Symbol 

Name  I/O 

Description 

24 

cm 

Control/Data  I 
Select 

This  input,  with  RD,  WR.  andB/A 
selects  the  data  register  (C/D  =  0)  or 
the_control  and  status  registers 
(C/D = 1 )  for  access  over  the  data  bus. 

25 

B/A 

Channel  Select  I 

A  low  selects  channel  A  and  a  high 
selects  channel  B  for  access  during  a 
read  or  write  cycle. 

26 

HAI 

Hold  Acknowledge  I 
In 

This  input  notifies  the  MPSC2  that  the 
host  processor  has  acknowledged  the 
DMA  request  and  has  placed  itself  in 
the  hold  state.  The  MPSC2  then  per- 
forms a  DMA  cycle  for  the  highest 
priority  outstanding  DMA  request,  if 
any.  (Active  low) 

26  ,31 

DTRA, 
DTRB 

Data  Terminal  0 
Ready 

The  DTR  pins  are  general-purpose 
outputs  which  may  be  set  or  reset 
with  commands  to  the  MPSC?  (Active 
low) 

27*        INTA  Interrupt  I 

Acknowledge 


The  processor  generates  two  or  three 
INTA  pulses  (depending  on  the  pro- 
cessor type)  to  signal  all  peripheral 
devices  that  an  interrupt  acknowledge 
sequence  is  taking  place.  During  the 
interrupt  acknowledge  sequence,  the 
MPSC2,  if  so  programmed,  places 
information  on  the  data  bus  to  vector 
the  processor  to  the  appropriate  inter- 
rupt service  location.  (Active  low) 


28         INT  Interrupt  Request  O 


INT  is  pulled  low  when  an  internal 
interrupt  request  is  accepted.  (Active 
low,  open  drain) 


interrupt  Priority  In  I 


This  input  informs  the  MPSC2  that  the 
highest  priority  device  is  requesting 
interrupt  and  is  used  with  PRO  to 
implement  a  priority  resolution  daisy 
chain  when  there  is  more  than  one 
interrupting  device.  The  state  of  PRI 
and  the  programmed  interrupt  mode 
determine  the  MPSC2's  response  to  an 
interrupt  acknowledge  sequence. 
(Active  low) 


Interrupt  Priority  O 
Out 


This  output  is  active  when  HAI  is 
active  and  the  MPSC2  is  not  request- 
ing interrupt  (INT  is  inactive).  The 
active  state  informs  the  next  lower  pri- 
ority device  that  there  are  no  higher 
priority  interrupt  requests  pending 
during  an  interrupt  acknowledge 
sequence.  (Active  low) 


Hold  Acknowledge  O 
Out 


This  output,  with  HAI  implements  a 
priority  daisychain  for  multiple  DMA 
devices.  HAO  is  active  when  HAI  is 
active  and  there  are  no  DMA  requests 
pending  in  the  MPSC2.  (Active  low) 


6-16 


I 


WAIT  A 
WAIT  B 
C/D 
B/A 


DATA 
BUS 


CS 
RD 
WR 


Bus 
Control 
Logic 


Control  and 
Status  Registers 


Internal  Data  and  Control  Bus 


Interrupt  Control 
Logic 


HAI  HAO 


4  DMA  Request 
Lines 


PRI  PRO 


INT  INTA 


Channel 
A 
Serial 
Data 
and 
Control 
Logic 

o 

j>  Serial  Data 

1  Serial  Data 
j  Clocks 


Modem  and  Sync 
Controls 


Channel 
B 

Serial 
Data 
and 
Control 
Logic 

:} 


Serial  Data 


1  Serial  Data 
.  [Clocks 


Modem  and  Sync 
Controls 


I.PD7201A 


Programming  the  MPSC2 

The  software  operation  of  the  MPSC2  is  very  straightfor- 
ward. Its  consistent  register  organization  and  high-level 
command  structure  help  minimize  the  number  of  opera- 
tions required  to  implement  complex  protocol  designs. 
Programming  is  further  simplified  by  the  MPSC2's  exten- 
sive interrupt  and  status  reporting  capabilities.  This  section 
is  divided  into  two  parts. 

The  MPSC2  Registers 

The  MPSC2  interfaces  to  the  system  software  with  a  num- 
ber of  control  and  status  registers  associated  with  each 
channel.  Commonly  used  commands  and  status  bits  are 
accessed  directly  through  control  and  status  registers  0. 
Other  functions  are  accessed  indirectly  with  a  register 
pointer  to  minimize  the  address  space  that  must  be  dedi- 
cated to  the  MPSC2. 


Control  Register 


Control 

Register 

Function 

0 

Frequently  used  commands  and  register  pointer  control 

1             Interrupt  control 

2 

Processor/bus  interface  control 

3 

Receiver  control 

4 

Mode  control 

5 

Transmitter  control 

6            Sync/address  character 

7 

Sync  character 

Status  Register 

Status 

Register 

Function 

0 

Buffer  and  "external/status"  status 

1             Received  character  error  and  special  condition  status 

2 

(Channel 

Interrupt  vector 

B  only) 

3 

Tx  byte  count  register,  low  byte 

4 

Tx  byte  count  register,  high  byte 

All  control  and  status  registers  except  CR2  are  sepa- 
rately maintained  for  each  channel.  Control  and  status 
registers  2  are  linked  with  the  overall  operation  of  the 
MPSC2  and  have  different  meanings  when  addressed 
through  different  channels. 

When  initializing  the  MPSC2  control  register  2A  (and  2B 
if  desired)  should  be  programmed  first  to  establish  the 
MPSC2  processor/bus  interface  mode.  Each  channel 
may  then  be  programmed  to  be  used  separately,  begin- 
ning with  control  register  4  to  set  the  protocol  mode  for 
that  channel.  The  remaining  registers  may  then  be 
programmed  in  any  order. 


Control  Register  0 


D7 

D6 

D5 

D4 

D3 

D2 

Di 

D0 

CRC  Control 
Command 

Command 

Register  Pointer 

Register  pointer  (D0  -  D2) 

The  register  pointer  specifies  which  register  number  is 
accessed  at  the  next  control  register  write  or  status  register 
read.  After  a  hardware  or  software  reset  the  register  pointer 
is  set  to  zero.  Therefore,  the  first  control  byte  goes  to  con- 
trol register  0.  When  the  register  pointer  is  set  to  a  value 
other  than  zero  the  next  control  or  status  (C/D  =  1)  access 
is  to  the  specified  register,  after  which  the  pointer  is  reset  to 
zero.  Other  commands  can  be  freely  combined  in  control 
register  0  by  setting  the  register  pointer. 

Commands  (D3  -  D5) 

Commands  commonly  used  during  the  operation  of  the 
MPSC2  are  grouped  in  control  register  0.  They  include 
the  following: 

Null  (000):  This  command  has  no  effect  and  is  used  only 
to  set  the  register  pointer  or  issue  a  CRC  command. 
Send  abort  (001):  When  operating  in  the  SDLC  mode  this 
command  causes  the  MPSC2  to  transmit  the  SDLC  abort 
code,  issuing  8  to  13  consecutive  ones.  Any  data 
currently  in  the  transmitter  or  the  transmitter  buffer  is 
destroyed.  After  sending  the  abort  the  transmitter  reverts 
to  the  idle  phase  (flags).  When  using  the  Tx  byte  count 
mode  enable  (D6  of  CR1),  and  an  underrun  condition 
occurs,  the  |jlPD7201  A  will  automatically  issue  the  send 
abort  command. 

Reset  external  status  interrupts  (010):  When  the 
external/status  change  flag  is  set,  the  condition  of  bits 
D3  -  D7  of  status  register  0  are  latched  to  allow  the  cap- 
ture of  the  short  pulses  that  may  occur.  The  reset  external/ 
status  interrupts  command  reenables  the  latches  so 
that  new  interrupts  may  be  sensed. 

Channel  reset  (011):  This  command  has  the  same  effect 
on  a  single  channel  as  an  external  reset  at  pin  2.  A  channel 
reset  command  to  channel  A  resets  the  internal  interrupt 
prioritization  logic.  This  does  not  occur  when  a  channel 
reset  command  is  issued  to  channel  B.  All  control 
registers  associated  with  the  channel  to  be  reset  must  be 
reinitialized.  After  a  channel  reset,  wait  at  least  four  system 
clock  cycles  before  writing  new  commands  or  controls  to 
that  channel. 

Enable  interrupt  on  next  character  (100):  When  operat- 
ing the  MPSC2  in  an  interrupt  on  first  received  character 
mode  this  command  may  be  issued  at  any  time.  This  com- 
mand must  be  issued  at  the  end  of  a  message  to  reenable 
the  interrupt  logic  for  the  next  received  character  (the  first 
character  of  the  next  message). 

Reset  pending  transmitter  interrupt/DMA  request 
(101):  A  pending  transmitter  buffer  becoming  empty  inter- 
rupt or  DMA  request  can  be  reset  without  sending  another 
character  by  issuing  this  command  (typically  at  the  end  of  a 
message).  A  new  transmitter  buffer  becoming  empty  inter- 
rupt or  DMA  request  is  not  made  until  another  character 
has  been  loaded  and  transferred  to  the  transmitter  shift 
register  or  when,  if  operating  in  the  synchronous  or  SDLC 
modes,  the  first  CRC  character  has  been  sent. 

Error  Reset  (110):  This  command  resets  a  special  receive 
condition  interrupt.  It  also  reenables  the  parity  and  overrun 
error  latches  that  allow  errors  at  the  end  of  a  message  to 
be  checked. 


6-18 


MPD7201A 


End  of  interrupt  (111)  (channel  A  only):  Once  an  inter- 
rupt request  has  been  issued  by  the  MPSC2  all  lower 
priority  internal  and  external  interrupts  in  the  daisychain  are 
held  off  to  permit  the  current  interrupt  to  be  serviced  while 
allowing  higher  priority  interrupts  to  occur.  At  some  point  in 
the  interrupt  service  routine  (generally  at  the  end),  the 
end  of  interrupt  command  must  be  issued  to  channel  A  to 
reenable  the  daisychain  and  allow  any  pending  lower  pri- 
ority internal  interrupt  requests  to  occur.  The  EOI  command 
must  be  sent  to  channel  A  for  interrupts  that  occurred  on 
either  channel. 

CRC  Control  Commands  (D6  -  D7) 

The  following  commands  control  the  operation  of  the  CRC 
generator/checker  logic. 

Null  (00):  This  command  has  no  effect  and  is  used  when 
issuing  other  commands  or  setting  the  register  pointer. 
Reset  receiver  CRC  checker  (01):  This  command  resets 
the  CRC  checker  to  zero  when  the  channel  is  in  a  syn- 
chronous mode  and  resets  to  all  ones  when  in  an  SDLC 
mode. 

Reset  transmitter  CRC  generator  (10):  This  command 
resets  the  CRC  generator  to  zero  when  the  channel  is  in 
a  synchronous  mode  and  resets  to  all  ones  when  in  an 
SDLC  mode. 

Reset  idle/CRC  latch  (11):  This  command  resets  the  idle/ 
CRC  latch  so  that  when  a  transmitter  underrun  condition 
occurs  (that  is,  the  transmitter  has  no  more  characters  to 
send),  the  transmitter  enters  the  CRC  phase  of  operation 
and  begins  to  send  the  16-bit  CRC  character  calculated  up 
to  that  point.  The  latch  is  then  set  so  that  if  the  underrun 
condition  persists,  idle  characters  are  sent  following  the 
CRC.  After  a  hardware  or  software  reset  the  latch  is  in 
the  set  state.  This  latch  is  automatically  reset  after  the 
first  character  has  been  loaded  into  the  Tx  buffer  in  the 
SDLC  mode. 


Control  Register  1 


D7 

D6 

D5 

D4 

D3 

D2 

Di 

D0 

Wait 
Function 
Enable 

Tx  Byte 
Count 
Mode 
Enable 

Wait  on 
Receiver 
Transmitter 

Receiver 
interrupt 
Mode 

Condition 
Affects 
Vector 

Transmitter 
Interrupt 
Enable 

Ext /Status 
INT 
Enable 

D7 

D4 

D3 

D2 

Do 

Low  Byte 

Dy 

D6 

D5 

D4 

D3 

D2 

D0 

High  Byte 


External/status  interrupt  enable  (D0) 

When  this  bit  is  set  to  one  the  MPSC2  issues  an  interrupt 
whenever  any  of  the  following  conditions  occur: 
Transition  of  the  PCD  input  pin 
Transition  of  the  CTS  input  pin 
Transition  of  the  SYNC  input  pin 
Entering  or  leaving  synchronous  hunt  phase, 

break  detection  or  termination 
SDLC  abort  detection  or  termination 
Idle/CRC  latch  becoming  set  (CRC  being  sent) 
After  ending  flag  is  sent  in  the  SDLC  mode 


Transmitter  interrupt  enable  (D^ 

When  this  bit  is  set  to  one  the  MPSC2  issues  an  inter- 
rupt when: 

1 )  The  character  currently  in  the  transmitter  buffer  is 

transferred  to  the  shift  register  (transmitter  buffer 
becoming  empty)  or, 

2)  The  transmitter  enters  the  idle  phase  and  begins 

transmitting  sync  or  flag  characters. 

3)  The  Tx  byte  mode  enable  bit  is  set  (CR1  -  D6  =  1). 

The  7201 A  will  automatically  issue  a  Tx  interrupt 
or  DMA  request  when  the  transmitter  becomes 
enabled  (CR5  -  D3  =  1). 

Condition  affects  vector  (D2)  (programmed 
in  channel  B  for  both  channels) 

When  this  bit  is  set  to  zero  the  fixed  vector  programmed 
in  CR2B  during  MPSC2  initialization  is  returned  in  an 
interrupt  acknowledge  sequence.  When  this  bit  is  set  to 
one  the  vector  is  modified  to  reflect  the  condition  that 
caused  the  interrupt. 

Receiver  interrupt  mode  (D3  -  D4) 

This  field  controls  how  the  MPSC2's  interrupt/DMA  logic 
handles  the  character  received  condition. 

Receiver  interrupts/DMA  request  disabled 
(00) 

The  MPSC2  does  not  issue  an  interrupt  or  a  DMA  request 
when  a  character  has  been  received. 

Interrupt/DMA  on  first  received  character 
only  (01) 

In  this  mode  the  MPSC2  issues  an  interrupt  only  for  the  first 
character  received  after  an  enable  interrupt/DMA  on  first 
character  command  (CR0)  has  been  given.  If  the  channel 
is  in  a  DMA  mode,  a  DMA  request  is  issued  for  each  charac- 
ter received  including  the  first.  This  mode  generally  is  used 
whenever  the  MPSC2  is  in  a  DMA  or  block  transfer  mode . 
This  will  signal  the  processor  that  the  beginning  of  an 
incoming  message  has  been  received. 

Interrupt  (and  issue  a  DMA  request)  on  all 
received  characters  (10) 

In  this  mode  an  interrupt  (and  DMA  request  if  the  DMA 
mode  is  selected)  is  issued  whenever  there  is  a  character 
present  in  the  receiver  buffer.  A  parity  error  is  considered 
a  special  receive  condition. 
Interrupt  (and  issue  a  DMA  request)  on  all 
received  characters  (11) 

This  mode  is  the  same  as  the  one  above  except  that  a 
parity  error  is  not  considered  a  special  receive  condition. 
The  following  are  considered  special  receive  conditions: 

Receiver  overrun  factor 

Asynchronous  framing  error 

Parity  error  (if  specified) 

SDLC  end  of  message  (final  flag  received) 

Wait  on  receiver/transmitter  (D5) 

If  the  wait  function  is  enabled  for  block  mode  transfers, 
setting  this  bit  to  zero  causes  the  MPSC2  to  issue  a  wait 
(WAIT  output  goes  low)  when  the  processor  attempts  to 
write  a  character  to  the  transmitter  while  the  transmitter 
buffer  is  full.  Setting  this  bit  to  one  causes  the  MPSC2  to 
issue  a  wait  when  the  processor  attempts  to  read  a  charac- 
ter from  the  receiver  while  the  receiver  buffer  is  empty. 


6-19 


;iPD7201A 

Tx  byte  count  mode  enable  (D6) 

Each  channel  has  a  16-bit  Tx  byte  count  register  used  for 
automatic  transmit  termination.  When  this  bit  is  set  to  one 
the  next  two  consecutive  command  cycle  writes  will  be  to 
the  byte  count  register.  The  first  byte  is  loaded  into  the 
lower  8  bits  and  the  second  to  the  upper  8  bits  of  the  byte 
count  register.  The  byte  count  register  holds  the  number  of 
transfers  to  be  performed  by  the  transmitter.  A  byte  counter 
is  incremented  each  time  a  transfer  is  performed  until  the 
value  of  the  byte  counter  is  equal  to  the  value  in  the  byte 
count  register.  When  equal,  interrupts  or  DMA  requests  will 
be  stopped  until  the  byte  count  enable  bit  is  issued  and  a 
new  byte  count  is  loaded  into  the  byte  count  register.  If  a 
transmit  underrun  occurs  in  the  SDLC  mode,  and  the  byte 
count  is  not  equal  to  the  byte  count  register,  the  abort 
sequence  will  be  sent  automatically. 
Also,  when  using  the  Tx  byte  count  mode,  a  transmit  inter- 
rupt or  DMA  request  will  automatically  become  active  after 
issuing  the  Tx  enable  command  to  CR5. 
The  Tx  byte  count  mode  can  be  cleared  by  either  a  channel 
reset  command  or  a  hardware  reset. 

Wait  function  enable  (D7) 

Setting  this  bit  to  one  enables  the  wait  function  which  is 
described  in  CR1. 

Control  Register  2  (Channel  A) 


D7 

D6 

D5 

°4 

D3 

D2 

D0 

Pin  10 
SYNCB/RTSB 

Rx  INT 
Mask 

Interrupt  Vector  Mode 

Priority 

DMA  Mode 
Select 

DMA  mode  select  (D0  -  Dt) 

Setting  this  field  determines  whether  channel  A  or  B  is 
used  in  a  DMA  mode  (i.e.,  data  transfers  are  performed  by 
a  DMA  controller)  or  in  a  non-DMA  mode  where  transfers 
are  performed  by  the  processor  in  either  a  polled,  interrupt, 
or  block  transfer  mode.  The  functions  of  some  MPSC2  pins 
are  also  controlled  by  this  field. 


DMA  Mode  Selection 


Channel 

Pin  Function 

Do 

A  B 

11 

26 

29 

30 

31 

32 

0 

0 

Non-DMA  Non-DMA 

WAITB 

DTRB 

PRI 

PRO 

DTRA 

WAITA 

0 

1 

DMA  Non-DMA 

DRQTxA 

HAI 

PRI 

PRO 

HAO 

DRQRxA 

1 

0 

DMA  DMA 

DRQTxA 

HAI 

DRQRxB 

DRQTxB 

HAO 

DRQRxA 

1 

1 

DMA  DMA 

DRQTxA 

DTRB 

DRQRxB 

DRQTxB 

DTRA 

DRQRxA 

Priority  (D2) 

This  bit  selects  the  relative  priorities  of  the  various  interrupt 
and  DMA  conditions  according  to  the  application 
requirements. 


DMA/Interrupt  Priorities 


Mode 

DMA  Priority 
Relation 

D2    Channel  A  Channel  B 

Interrupt  Priority  Relation 

SRxA,  RxA  >  TxA  >  SRxB,  RxB  > 

0 

  INT 

1 

INT 

TxB  >  ExTA  >  ExTB 

SRxA,  RxA  >  SRxB,  RxB  >  TxA  > 
TxB  >  ExTA  >  ExTB 

SRxA,  RxA  >  SRxB,  RxB  >  TxB  > 

0 

  DMA 

1 

INT 

RxA  >  TxA 

ExTA  >  ExTB 

RxA  >  TxA 

SRxA,  RxA  >  SRxB,  RxB  >  TxB  > 
ExTA  >  ExTB 

RxA  >  TxA  >  RxB  > 

SRxA,  RxA  >  SRxB,  RxB  >  ExTA  > 

0 

  DMA 

1 

DMA 

TxB 

ExTB 

RxA  >  RxB  >  TxA  > 
TxB 

SRxA,  RxA  >  SRxB,  RxB  >  ExTA  > 
ExTB 

6 


Interrupt  vector  mode  (D3  -  D5) 

This  field  determines  how  the  MPSC2  responds  to  an  inter- 
rupt acknowledge  sequence  from  the  processor. 


Interrupt  Acknowledge  Sequence  Response 


D5 

D4 

D3 

Mode 

Status  Register  2B  and  Interrupt  Vector 
Bits  Affected  When  Condition  Affects  Vector 
Is  Enabled 

0 

0 

0 

Nonvectored 

D4  D3  D2 

0 

0 

1 

Nonvectored 

D4  D3  D2 

0 

1 

0 

Nonvectored 

D2  Dt  D0 

0 

1 

1 

Illegal 

1 

0 

0 

8085  Master 

D4  D3  D2 

1 

0 

1 

8085  Slave 

D4  D3  D2 

1 

1 

0 

8086 

D2  Dt  D0 

1 

1 

1 

8085/8259A  Slave 

D4  D3  D2 

Rx  INT  mask  (D6) 

This  option  is  generally  used  in  the  DMA  modes.  Enabling 
this  bit  inhibits  the  interrupt  from  occurring  when  the  inter- 
rupt/DMA Request  On  First  Received  Character  mode  is 
selected.  In  other  words,  only  a  DMA  request  will  be  gener- 
ated when  the  first  character  is  received. 


Pin  10  SYNCB/RTSB  select  (D7) 

Programming  a  zero  into  this  bit  selects  RTSB  as  the 
function  of  pin  10.  A  one  selects  SYNCB  as  the  function. 

Control  Register  2  (Channel  B) 


D6 

D4 

D3 

D2 

Di 

D0 

Interrupt  Vector 

Interrupt  vector  (D0  -  D7) 

When  the  MPSC2  is  used  in  the  vectored  interrupt  mode 
the  contents  of  this  register  is  placed  on  the  bus  during  the 
appropriate  portion  of  the  interrupt  acknowledge  sequence. 
Its  value  is  modified  if  status  affects  vector  is  enabled.  The 
value  of  SR2B  can  be  read  at  any  time.  This  feature  is 
particularly  useful  in  determining  the  cause  of  an  interrupt 
when  using  the  MPSC2  in  a  nonvectored  interrupt  mode. 

Control  Register  3 


D7 

D6 

D5 

D4 

D3 

D2 

Di 

D0 

Number  of  Received 
Bits  per  Character 

Auto 
Enables 

Enter 
Hunt 
Phase 

Receiver 
CRC  Enable 

Address 
Search 
Mode 

Sync 
Character 
Load 
Inhibit 

Receiver 
Enable 

Receiver  enable  (D0) 

After  the  channel  has  been  completely  initialized,  setting 
this  bit  to  one  allows  the  receiver  to  begin  operation.  This 
bit  may  be  set  to  zero  at  any  time  to  disable  the  receiver. 

Sync  character  load  inhibit  (Dt) 

In  the  character  synchronous  modes,  this  bit  inhibits  the 
transfer  of  sync  characters  to  the  receiver  buffer  thus  per- 
forming a  "sync-stripping"  operation.  When  using  the 
MPSC2's  CRC  checking  ability  this  feature  should  be  used 
only  to  strip  leading  sync  characters  preceding  a  message 
since  the  load  inhibit  does  not  exclude  sync  characters 
embedded  in  the  message  from  the  CRC  calculation.  Syn- 
chronous protocols  using  other  types  of  block  checking 
such  as  checksum  or  LRC  are  free  to  strip  embedded  sync 
characters  with  this  bit. 


20 


MPD7201A 


Address  search  mode  (D2) 

In  the  SDLC  mode,  setting  this  bit  places  the  MPSC2 
in  an  address  search  mode.  Character  assembly  does 
not  begin  until  the  8-bit  character  (secondary  address 
field)  following  the  starting  flag  of  a  message  matches 
either  the  address  programmed  into  CR6  or  the  global 
address  11111111. 

Receiver  CRC  enable  (D3) 

This  bit  enables  and  disables  (1  =  enable)  the  CRC 
checker  in  the  COP  mode  allowing  characters  from  the 
CRC  calculation  to  be  selectively  included  or  excluded. 
The  MPSC2  features  a  one-character  delay  between  the 
receiver  shift  register  and  the  CRC  checker  so  that  the 
enabling  or  disabling  takes  effect  with  the  last  character 
transferred  from  the  shift  register  to  the  receiver  buffer. 
Therefore,  there  is  one  full  character  time  in  which  to 
read  the  character  and  decide  whether  or  not  it  should 
be  included  in  the  CRC  calculation.  In  the  SDLC  mode, 
there  is  no  8-bit  delay. 

Enter  hunt  phase  (D4) 

Although  the  MPSC2  receiver  automatically  enters  the  sync 
hunt  phase  after  a  reset,  there  are  times  when  reentry  may 
be  desired,  such  as  when  it  has  been  determined  that  syn- 
chronization has  been  lost  or,  in  an  SDLC  mode,  to  ignore 
the  current  incoming  message.  Writing  a  one  into  this  bit  at 
any  time  after  initialization  causes  the  MPSC2  to  reenter 
the  hunt  phase. 

Auto  enables  (D5) 

Setting  this  bit  to  one  causes  the  DCD  and  CTS 
inputs  to  act  as  enable  inputs  to  the  receiver  and  trans- 
mitter, respectively. 

Number  of  received  bits  per  character 
(D6-D7) 

This  field  specifies  the  number  of  data  bits  assembled  to 
make  each  character.  The  value  may  be  changed  on  the  fly 
while  a  character  is  being  assembled  and,  if  the  change  is 
made  before  the  new  number  of  bits  has  been  reached  it 
affects  that  character.  Otherwise  the  new  specifications 
take  effect  on  the  next  character  received. 

Received  Bits  per  Character  


P7  Dg  Bits  per  Character 

J)  0  5  

J)  1  7  

J  0  6  

1  1  8 


Control  Register  4 


D7 

D6 

D5 

D4 

D3 

D2 

Di 

D0 

Clock  Rate 

Sync  Mode 

Number  of  Stop  Bits 
per  Sync  Mode 

Parity 
Even/Odd 

Parity 
Enable 

Parity  enable  (D0) 

Setting  this  bit  to  one  adds  an  extra  data  bit  containing 
parity  information  to  each  transmitted  character.  Each 
received  character  is  expected  to  contain  this  extra  bit 
and  the  receiver  parity  checker  is  enabled. 


Parity  even/odd  (Dn) 

Programming  a  zero  into  this  bit  when  parity  is  enabled 
causes  the  transmitted  parity  bit  to  take  on  the  value 
required  for  odd  parity.  The  received  character  is  checked 
for  odd  parity.  Conversely,  a  one  in  this  bit  signifies  even 
parity  generation  and  checking. 

Number  of  stop  bits  per  sync  mode  (D2  -  D3) 

This  field  specifies  whether  the  channel  is  used  in  a 
synchronous  (SDLC)  or  an  asynchronous  mode.  In  an 
asynchronous  mode  this  field  also  specifies  the  number  of 
bit  times  used  as  the  stop  bit  length  by  the  transmitter.  The 
receiver  always  checks  for  one  stop  bit. 

Stop  Bits  


D3 

D2 

Mode 

0 

0 

Synchronous  modes 

0 

1 

Asynchronous  1 -bit  time  (1  stop  bit) 

1 

0 

Asynchronous  11 2  bit  times  (11,2  stop  bits) 

1             1                 Asynchronous  2-bit  times  (2  stop  bits) 

Sync  mode  (D4  -  D5) 

When  the  stop  bits/sync  mode  field  is  programmed  for 
synchronous  modes  (D2,  D3  =  00),  this  field  specifies 
the  particular  synchronous  format  to  be  used.  This  field 
is  ignored  in  an  asynchronous  mode. 


Synchronous  Formats 


Sync  Sync 
Mode  1    Mode  2 

D5  D4 

Mode 

0  0 

8-bit  internal  synchronization  character  (monosync) 

0  1 

16-bit  internal  synchronization  character  (bisync) 

1  0 

SDLC 

1             1                 External  synchronization  (SYNC  pin  becomes  an  input) 

Clock  rate(D6- 

D7) 

This  field  specifies  the  relationship  between  the  transmitter 
and  receiver  clock  inputs  (TxC,  RxC)  and  the  actual  data 
rates  at  TxD  and  RxD.  When  operating  in  a  synchronous 
mode  a  1x  clock  rate  must  be  specified.  In  asynchronous 
modes  any  of  the  rates  may  be  specified,  however,  with  a  1x 
clock  rate  the  receiver  cannot  determine  the  center  of  the 
start  bit.  In  this  mode,  the  sampling  (rising)  edge  of 
RxC  must  be  externally  synchronized  with  the  data. 

Clock  Rates  

Clock  Clock 

Rate  1  Rate  2 

D7  Dg  Clock  Rate  

0  0  Clock  Rate  =  1x  Data  Rate 

0  1  Clock  Rate  =  16x  Data  Rate 

1  0  Clock  Rate  =  32x  Data  Rate 
1  1  Clock  Rate  =  64x  Data  Rate 


Control  Register  5 


D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

DTR 

Number  of  Transmitted 
Bits  per  Character 

Send 
Break 

Transmitter 
Enable 

CRC 
Polynomial 
Select 

RTS 

Transmitter 
CRC 
Enable 

Transmitter  CRC  enable  (D0) 

A  one  or  a  zero  enables  or  disables  respectively,  the  CRC 
generator  calculation.  The  enable  or  disable  does  not  take 
effect  until  the  next  character  is  transferred  from  the  trans- 
mitter buffer  to  the  shift  register,  thus  allowing  specific 
characters  to  be  included  or  excluded  from  the  CRC  cal- 
culation. By  setting  or  resetting  this  bit  just  before  loading 


6-21 


|xPD7201A 


the  next  character,  it  and  subsequent  characters  are 
included  or  excluded  from  the  calculation.  If  this  bit  is  zero 
when  the  transmitter  becomes  empty  the  MPSC2  goes  to 
the  idle  phase  regardless  of  the  state  of  the  idle/CRC  latch. 

RTS  (D^ 

In  synchronous  and  SDLC  modes  setting  this  bit  to  one 
causes  the  RTS  pin  to  go  low  while  a  zero  causes  it  to  go 
high.  In  an  asynchronous  mode  setting  this  bit  to  zero  does 
not  cause  RTS  to  go  high  until  the  transmitter  is  completely 
empty.  This  feature  facilitates  programming  the  MPSC2  for 
use  with  asynchronous  modems. 

CRC  polynomial  select  (D2) 

This  bit  selects  the  polynomial  used  by  the  transmitter  and 
receiver  for  CRC  generation  and  checking.  A  one  selects 
the  CRC-16  polynomial  (x16  +  x15  +  x2  +  1).  A  zero 
selects  the  CRC-CCITT  polynomial  (x16  +  x12  +  x5  +  1). 
In  an  SDLC  mode  CRC-CCITT  must  be  selected.  Either 
polynomial  may  be  used  in  other  synchronous  modes. 

Transmitter  enable  (D3) 

After  a  reset  the  transmitted  data  output  (TxD)  is  held  high 
(marking)  and  the  transmitter  is  disabled  until  this  bit  is  set. 
In  an  asynchronous  mode  TxD  remains  high  until  data  is 
loaded  for  transmission. 

In  synchronous  and  SDLC  modes  the  MPSC2  automati- 
cally enters  the  idle  phase  and  sends  the  programmed 
sync  or  flag  characters. 

When  the  transmitter  is  disabled  in  an  asynchronous  mode 
any  character  currently  being  sent  is  completed  before  TxD 
returns  to  the  marking  state. 

If  the  transmitter  is  disabled  during  the  data  phase  in  a 
synchronous  mode  the  current  character  is  sent.  TxD  then 
goes  high  (marking).  In  an  SDLC  mode  the  current  charac- 
ter is  sent,  but  the  marking  line  following  is  zero-inserted. 
That  is,  the  line  goes  low  for  one  bit  time  out  of  every  five. 
The  transmitter  should  never  be  disabled  during  the  SDLC 
data  phase  unless  a  reset  is  to  follow  immediately.  In  either 
case,  any  character  in  the  buffer  register  is  held. 
Disabling  the  transmitter  during  the  CRC  phase  causes  the 
remainder  of  the  CRC  character  to  be  bit-substituted  with 
the  sync  (or  flag).  The  total  number  of  bits  transmitted  is 
correct  and  TxD  goes  high  after  they  are  sent. 
If  the  transmitter  is  disabled  during  the  idle  phase  the 
remainder  of  the  sync  (flag)  character  is  sent.  TxD  then 
goes  high. 

Send  break  (D4) 

Setting  this  bit  to  one  immediately  forces  the  transmitter 
output  (TxD)  low  (spacing).  This  function  overrides  the 
normal  transmitter  output  and  destroys  any  data  being 
transmitted  although  the  transmitter  is  still  in  operation. 
Resetting  this  bit  releases  the  transmitter  output. 

Transmitted  bits  per  character  (D5  -  D6) 

This  field  controls  the  number  of  data  bits  transmitted  in 
each  character.  The  number  of  bits  per  character  may  be 
changed  by  rewriting  this  field  just  before  the  first  character 
is  loaded  to  use  the  new  specification. 


Transmitted  Bits  per  Character 


Transmitted 

Bits  per 
Character  1 

Transmitted 
Bits  per 
Character 

D6 

Ds 

Bitsp 

er  Character 

0 

0 

5  or  les 

»s  (see  below) 

0 

1 

7 

1                             0  6 

1                             1  8 

Normally  each  character  is  sent  to  the  MPSC2  right- 
justified  and  the  unused  bits  are  ignored.  However,  when 
sending  five  bits  or  less  the  data  should  be  formatted  as 
shown  below  to  inform  the  MPSC2  of  the  precise  number  x 
of  bits  to  be  sent. 


Transmitted  Bits  per  Character  for 
5  Characters  or  Less  


D7  D6 

°5 

»4 

D3 

»2 

Di 

Do 

Number  of  Bits  per  Character 

1  1 

1 

1 

0 

0 

0 

Do 

1 

1  1 

1 

0 

0 

0 

Di 

Do 

2 

1  1 

0 

0 

0 

D2 

Di 

D0 

3 

1  0 

0 

0 

D3 

D2 

Di 

Do 

4 

0  0 

0 

D4 

D3 

D2 

Di 

D0 

5 

DTR  (data  terminal  ready)  (D7) 

When  this  bit  is  one  the  DTR  output  is  low  (active).  Con 
versely,  when  this  bit  is  zero  DTR  is  high. 

Control  Register  6 


D7 

D6 

D5 

D4 

D3 

D2 

D, 

D0 

Sync  Byte  1 

Sync  byte  1  (D0  -  D7) 

Sync  byte  1  is  used  in  the  following  modes: 

Monosync       8-bit  sync  character  transmitted 

during  the  idle  phase 
Bisync  Least  significant  (first)  8  bits  of 

the  1 6-bit  transmit  and  receive 

sync  character 
External  Sync  Sync  character  transmitted  during  the 

idle  phase 

SDLC  Secondary  address  value  matched  to 

secondary  address  field  of  the  SDLC 
frame  when  the  MPSC2  is  in  the 
address  search  mode 


Control  Register  7 


D7 

D6 

D5 

D4 

D2 

Di 

D0 

Sync  Byte  2 

Sync  byte2(D0-D7) 

Sync  byte  2  is  used  in  the  following  modes: 

Monosync   8-bit  sync  character  matched  by 
the  receiver 

Bisync        Most  significant  (second)  8  bits  of  the  1 6- 
bit  transmit  and  receive  sync  characters 

SDLC        The  flag  character,  01111110,  must  be 

programmed  into  control  register  7  for  flag 
matching  by  the  MPSC2  receiver 


6-22 


Status  Register  0 


D7 

D6 

D5 

D4 

D3 

D2 

Di 

Do 

Break/ 
Abort 

Idle/CRC 

CTS 

Sync 
Status 

DCD 

Transmitter 
Buffer 
Empty 

Interrupt 
Pending 

Received 
Character 
Available 

Received  character  available  (D0) 

When  this  bit  is  set  it  indicates  that  one  or  more  charac- 
ters in  the  receiver  buffer  is  available  for  the  processor  to 
read.  Once  all  the  available  characters  have  been  read  the 
MPSC2  resets  this  bit  until  a  new  character  is  received. 

Interrupt  pending  (D1  —  channel  A  only) 

The  interrupt  pending  bit  is  used  with  the  interrupt  vector 
register  (status  register  2)  to  make  it  easier  to  determine 
the  MPSC2's  interrupt  status,  particularly  in  a  nonvectored 
interrupt  mode  where  the  processor  must  poll  each  device 
to  determine  the  interrupt  source.  In  this  mode  interrupt 
pending  is  set  when  status  register  2B  is  read,  the  PRI 
input  is  active  (low),  and  the  MPSC2  is  requesting  inter- 
rupt service. 

The  status  registers  of  both  channels  need  not  be  analyzed 
to  determine  if  an  interrupt  is  pending.  If  the  status  affects 
vector  is  enabled  and  the  interrupt  pending  is  set  the  vector 
read  from  SR2  contains  valid  condition  information. 
In  a  vectored  interrupt  mode  interrupt  pending  is  set  during 
the  interrupt  acknowledge  cycle  (on  the  leading  edge  of  the 
second  INTA  pulse)  when  the  MPSC2  is  the  highest  priority 
device  requesting  interrupt  service  (PRI  is  active).  In  either 
mode  if  there  are  no  other  pending  interrupt  requests  inter- 
rupt pending  is  reset  when  the  end  of  the  interrupt 
command  is  issued. 

Transmitter  buffer  empty  (D2) 

This  bit  is  set  whenever  the  transmitter  buffer  is  empty 
except  during  the  transmission  of  CRC.  (The  MPSC2  uses 
the  buffer  to  facilitate  this  function.)  After  a  reset  the  buffer 
is  considered  empty  and  transmit  buffer  empty  is  set. 

External/status  flags  (D3-D7) 

The  following  status  bits  reflect  the  state  of  the  various  con- 
ditions that  cause  an  external/status  interrupt.  The  MPSC2 
latches  all  external/status  bits  whenever  a  change  occurs 
that  would  cause  an  external/status  interrupt  (regardless  of 
whether  this  interrupt  is  enabled).  This  allows  transient 
status  changes  on  these  lines  to  be  captured  with  relaxed 
software  timing  requirements. 

When  the  MPSC2  is  operated  in  an  interrupt-driven  mode 
for  external/status  interrupts,  status  register  0  should  be 
read  when  this  interrupt  occurs  and  a  reset  external/status 
interrupt  command  issued  to  reenable  the  interrupt  and 
the  latches.  To  poll  these  bits  without  interrupts,  the  reset 
external/status  interrupt  command  can  be  issued  to  first 
update  the  status  to  reflect  the  current  values. 
DCD  (D3):  This  bit  reflects  the  inverted  state  of  the 
DCD  input.  When  DCD  is  low  the  DCD  status  bit  is  high. 
Any  transition  on  this  bit  causes  an  external/status  inter- 
rupt request. 

Sync  status  (D4):  The  meaning  of  this  bit  depends  on  the 
operating  mode  of  the  MPSC2. 
Asynchronous  mode:  Sync  status  reflects  the  inverted 
state  of  the  SYNC  input.  When  SYNC  is  low,  sync  status 
is  high.  Any  transition  on  this  bit  causes  an  external/status 
interrupt  request. 


|xPD7201A 

External  synchronization  mode:  Sync  status  operates  in 
the  same  manner  as  an  asynchronous  mode.  The  MPSC2's 
receiver  synchronization  logic  is  also  tied  to  the  sync  status 
bit  in  an  external  synchronization  mode  and  a  low-to-high 
transition  (SYNC  input  going  low)  informs  the  receiver  that 
synchronization  has  been  achieved  and  character  assem- 
bly begins. 

A  low-to-high  transition  on  the  SYNC  input  indicates 
that  synchronization  has  been  lost  and  is  reflected  both 
in  the  sync  status  becoming  zero  and  the  generation  of 
an  external/status  interrupt.  The  receiver  remains  in  the 
receive  data  phase  until  the  enter  hunt  phase  bit  in 
control  register  3  is  set. 

Monosync,  bisync,  SDLC  modes:  In  these  modes,  sync 
status  indicates  whether  the  MPSC2  receiver  is  in  the  sync 
hunt  or  receive  data  phase  of  operation.  A  zero  indicates 
that  the  MPSC2  is  in  the  receive  data  phase  and  a  one 
indicates  that  the  MPSC2  is  in  the  sync  hunt  phase  (as  after 
a  reset  or  a  setting  of  the  enter  sync  hunt  phase  bit).  As  in 
the  other  modes  a  transition  on  this  bit  causes  an  external/ 
status  interrupt  to  be  issued.  It  should  be  noted  that  enter- 
ing a  sync  hunt  phase  after  either  a  reset  or  when 
programmed  causes  an  external/status  interrupt  request 
which  may  be  cleared  immediately  with  a  reset  external/ 
status  interrupt  command. 
CTS  (D5):  This  bit  reflects  the  inverted  state  of  the 
CTS  input.  When  CTS  is  low,  the  CTS  status  bit  is  high. 
Any  transition  on  this  bit  causes  an  external/status  inter- 
rupt request. 

Idle/CRC  (D6)  (Tx  underrun/EOM):  This  bit  indicates  the 
state  of  the  idle/CRC  latch  used  in  the  synchronous  and 
SDLC  modes.  After  a  hardware  reset  this  bit  is  set  to  one, 
indicating  that  the  transmitter  is  completely  empty.  When 
the  MPSC2  enters  idle  phase  it  automatically  transmits  I 
sync  or  flag  characters. 

In  the  SDLC  mode  the  MPSC2  automatically  resets  this 
latch  after  the  first  byte  of  a  frame  is  written  to  the  Tx  buffer.  ' 
When  the  transmitter  is  completely  empty,  the  MPSC2 
sends  the  16-bit  CRC  character  and  sets  the  latch  again. 
An  external/status  interrupt  is  issued  when  the  latch  is  set, 
indicating  that  CRC  is  being  sent.  No  interrupt  is  issued 
when  the  latch  is  reset. 

Break/abort  (D7):  In  the  asynchronous  mode  this  bit  indi- 
cates the  detection  of  a  break  sequence  (a  null  character 
plus  framing  error  that  occurs  when  the  RxD  input  is  held 
low,  spacing,  for  more  than  one  character  time).  Break/ 
abort  is  reset  when  RxD  returns  high  (marking). 
In  the  SDLC  mode,  Break/abort  indicates  the  detection  of 
an  abort  sequence  when  seven  or  more  ones  are  received 
in  sequence.  It  is  reset  when  a  zero  is  received. 
Any  transition  of  the  break/abort  bit  causes  an  external/ 
status  interrupt. 

Status  Register  1 


D6 

D5 

°4 

D3 

D2 

D0 

End  of 
SDLC  Frame 

CRC 
Framing 
Error 

Overrun 
Error 

Parity 
Error 

SDLC  Residue  Code 

All  Sent 

6-23 


lxPD7201A 


All  sent  (D0) 

This  bit  is  set  when  the  transmitter  is  empty  and  reset  when 
a  character  is  present  in  the  transmitter  buffer  or  shift  regis- 
ter. This  feature  simplifies  the  modem  control  software 
routines.  In  the  bit  synchronous  mode,  this  bit  will  be  set 
when  the  ending  flag  pattern  is  sent. 

SDLC  residue  code  (D1  -  D3) 

Since  the  data  portion  of  an  SDLC  message  can  consist  of 
any  number  of  bits  and  not  necessarily  an  integral  number 
of  characters,  the  MPSC2  features  special  logic  to  deter- 
mine and  report  when  the  end  of  frame  flag  has  been 
received,  the  boundary  between  the  data  field  and  the  CRC 
character  in  the  last  few  data  characters  that  were  just  read. 
When  the  end  of  frame  condition  is  indicated,  that  is,  status 
register  1  D7  =  1  and  special  receive  condition  interrupt  (if 
enabled),  the  last  bits  of  the  CRC  character  are  in  the 
receiver  buffer.  The  residue  code  for  the  frame  is  valid  in  the 
status  register  1  byte  associated  with  that  data  character. 
(SR1  tracks  the  received  data  in  its  own  buffer.) 
The  meaning  of  the  residue  code  depends  upon  the  num- 
ber of  bits  per  character  specified  for  the  receiver.  The 
previous  character  refers  to  the  last  character  read  before 
the  end  of  frame,  and  so  forth. 

Residue  Codes  


8  Bits  per  Character 

D3 

D2 

Previous  Character 

2nd  Previous  Character 

1 

0 

0 

cccccccc 

CCCCCDDD 

0 

1 

0 

cccccccc 

CCCCDDDD 

1 

1 

0 

cccccccc 

CCCDDDDD 

0 

0 

1 

cccccccc 

CCDDDDDD 

1 

0 

1 

cccccccc 

CDDDDDDD 

0 

1 

1 

cccccccc 

DDDDDDDD       (no  residue) 

1 

1 

1 

CCCCCCCD 

DDDDDDDD 

0 

0 

0 

CCCCCCDD 

DODDDDDD 

7  Bits  per  Character 

o3 

D2 

D, 

Previous  Character 

2nd  Previous  Character 

1 

0 

0 

ccccccc 

CCCCCDD 

0 

1 

0 

ccccccc 

C  C  C  C  D  D  D 

1 

1 

0 

ccccccc 

CCCDDDD 

0 

0 

1 

ccccccc 

C  C  D  D  D  D  0 

1 

0 

1 

ccccccc 

C  D  D  D  D  D  D 

0 

1 

1 

ccccccc 

D  D  D  D  D  D  D        (no  residue) 

0 

0 

0 

CCCCCCD 

D  0  D  D  0  D  D 

6  Bits  pei 

Character 

°3 

D2 

Di 

Previous  Character 

2nd  Previous  Character 

1 

0 

0 

cccccc 

CCCCCD 

0 

1 

0 

cccccc 

C  C  C  C  D  D 

1 

1 

0 

cccccc 

CCCDDD 

0 

0 

1 

cccccc 

CCDDDD 

1 

0 

1 

cccccc 

CODDDD 

0 

0 

0 

cccccc 

D  D  D  D  D  D         (no  residue) 

5  Bits  pe 

r  Character 

°3 

D2 

Di 

2nd  Previous  Character      3rd  Previous  Character 

1 

0 

0 

ccccc 

0  D  D  D  D          (no  residue) 

0 

1 

0 

CCCC  D 

D  D  D  D  D 

1 

1 

0 

CC  C  D  D 

D  D  D  D  D 

0 

0 

1 

CCDDD 

DDDDO 

000  CDDDO  DDDDD 


When  any  of  these  conditions  occur  and  interrupts  are 
enabled,  the  MPSC2  issues  an  interrupt  request.  In  addi- 
tion, if  a  condition  affects  vector  mode  is  enabled,  the 
vector  generated  (and  the  contents  of  SR2B  for  nonvec- 
tored  interrupts)  is  different  from  that  of  a  received 
character  available  condition.  Thus,  it  is  not  necessary  to 
analyze  SR1  with  each  character  to  determine  if  an  error 
has  occurred. 

As  a  further  convenience,  the  parity  error  and  receiver  over- 
run error  flags  are  latched.  That  is,  once  one  of  these  errors 
occurs,  the  flag  remains  set  for  all  subsequent  characters 
until  reset  by  the  error  reset  command.  With  this  facility  SR1 
need  only  be  read  at  the  end  of  a  message  to  determine  if 
either  of  these  errors  occurred  anywhere  in  the  message. 
The  other  flags  are  not  latched  and  follow  each  character 
available  in  the  receiver  buffer. 

Parity  error  (D4):  This  bit  is  set  and  latched  when  parity 
is  enabled  and  the  received  parity  bit  does  not  match  the 
sense  (odd  or  even)  calculated  from  the  data  bits. 
Receiver  overrun  error  (D5):  This  error  occurs  and  is 
latched  when  the  receiver  buffer  already  contains  three 
characters  and  a  fourth  character  is  completely  received, 
overwriting  the  last  character  in  the  buffer. 
CRC/framing  error  (D6):  In  the  asynchronous  mode  a 
framing  error  is  flagged  (but  not  latched)  when  no  stop  bit  is 
detected  at  the  end  of  a  character  (i.e.,  RxD  is  low  one  bit 
time  after  the  center  of  the  last  data  or  parity  bit).  When  this 
condition  occurs,  the  MPSC2  waits  an  additional  one-half 
bit  time  before  sampling  again  so  that  the  framing  error  is 
not  interpreted  as  a  new  start  bit. 
In  the  synchronous  and  SDLC  modes  this  bit  indicates  the 
result  of  the  comparison  between  the  current  CRC  result 
and  the  appropriate  check  value  and  is  usually  set  to  one 
since  a  message  rarely  indicates  a  correct  CRC  result  until 
correctly  completed  with  the  CRC  check  character.  Note 
that  a  CRC  error  does  not  result  in  a  special  receive  condi- 
tion interrupt. 

End  of  SDLC  frame  (EOF)  (D7):  This  status  bit  is  used 
only  in  the  bit  synchronous  mode  to  indicate  that  the  end  of 
frame  flag  has  been  received  and  that  the  CRC  error  flag 
and  residue  code  are  valid.  This  flag  can  be  reset  at  any 
time  by  issuing  an  error  reset  command.  The  MPSC2  also 
automatically  resets  this  bit  when  the  first  character  of  the 
next  message  frame  is  sent. 

Status  Register  2B 


D7 

D6 

D5 

D4 

D3 

D2 

°1 

D0 

Interrupt  Vector 

Interrupt  vector  (D0  -  D7  —  channel  B  only) 

Reading  status  register  2B  returns  the  interrupt  vector  that 
is  programmed  into  control  register  2B.  If  a  condition  affects 
vector  mode  is  enabled  the  value  of  the  vector  is  modified 
as  shown  in  the  following  table. 


Special  receive  condition  flags 

The  status  bits  described  below  —  parity  error  (if  parity  as  a 
special  receive  condition  is  enabled),  receiver  overrun  error, 
CRC/framing  error,  and  end  of  SDLC  frame  —  all  represent 
special  receive  conditions. 


6-24 


Condition  Affects  Vector  Modifications 


IntormDt          ana  a 

OU09  MO) 

D3 

D2 

Pending  (SRO,  D1   

Channel  A)       «°86  Mod 

es  D2 

Di 

">o 

Condition 

0 

1 

1 

1 

No  interrupt  pending 

1 

0 

0 

0 

Channel  B  transmitter  buffer  empty 

1 

0 

0 

1 

Channel  B  external /status  change 

1 

0 

1 

0 

Channel  B  received  character  available 

1 

0 

1 

1 

Channel  B  special  receive  condition 

1 

1 

0 

0 

Channel  A  transmitter  buffer  empty 

1 

1 

0 

1 

Channel  A  external/status  change 

1 

1 

1 

0 

Channel  A  received  character  available 

1 

1 

1 

1 

Channel  A  special  receive  condition 

As  can  be  seen  code  111  can  mean  either  channel  A  spe- 
cial receive  condition  or  no  interrupt  pending.  They  can  be 
easily  distinguished  by  examining  the  interrupt  pending  bit 
(D.,)  of  status  register  0,  channel  A.  In  a  nonvectored  inter- 
rupt mode  the  vector  register  must  be  read  first  for  the 
interrupt  pending  to  be  valid. 


fPD7201A 


Read  Register  Bit  Functions 

Read  Register  0 


Read  Register  1® 


°4  D3 


-  Rx  Character  Available 

-  INT  Pending  (Channel  A  Only) 

-  Tx  Buffer  Empty 

-  DCD 

-  Sync/Hunt 

-  Tx  Underrun/EOM 

-  Break/Abort 


Used  with 
External/Status 
Interrupt  Mode 


All  Sent  —  Used  with  External/Status 
Interrupt  Mode 


l-Field 
Bits  in 


l-Field 
Bits  in 
Second 


Previous  Previous 
Byte  Byte 
0 
0 
0 


-  Parity  Error 

-  Rx  Overrun  Error 

-  CRC/Frammg  Error 

-  End  of  Frame  (SDLC) 


Residue  Data  for 
I    Eight  Rx  Bits  per 
Character 
Programmed 


Read  Register  2 


D1  D0 


Interrupt 
Vector 


Notes:  ©  Used  with  special  receive  condition  mode 

©  Variable  if  Status  Affects  Vector  is  programmed 


Write  Register  Bit  Functions 

Write  Register  0 


D7      D6      D5      D4      D3      D2      D,  D0 


0  0  0  Register  0 

0  0  1  Register  1 

0  1  0  Register  2         Pointer  for 

0  1  1  Register  3     I   the  Selection  of 

1  0  0  Register  4     [    a  Read/Write 
1  0  1  Registers  Register 

1  1  0  Register  6 

1  1  1  Register  7  J 


0 

0 

0 

Null  Code 

0 

0 

1 

Send  Abort  (SDLC) 

0 

1 

0 

Reset  EXT/Status  Interrupts 

0 

1 

1 

Channel  Reset 

1 

0 

0 

Enable  INT  on  Next  Rx  Character 

1 

0 

1 

Reset  Tx  INT/DMA  Pending 

1 

1 

0 

Error  Reset 

1 

1 

1 

End  of  Interrupt  (EOI  —  Channel  A  only) 

0  0  Null  Code 

0  1  Reset  Rx  CRC  Checker 

1  0  Reset  Tx  CRC  Generator 

1  1  Reset  Tx  Underrun/EOM  Latch 


6-25 


,.PD7201A 

Write  Register  Bit  Functions  (Cont.) 

Write  Register  1 


Write  Register  3 


L 


EXT  INT  Enable 
Tx  INT  Enable 
Status  Affects  Vector 


(Channel  B  only) 
Rx  INT  and  DMA  Disable 

0  1       Rx  INT  on  First  Character 

1  0       INT  on  All  Rx  Characters 

(Parity  Affects  Vector) 
1        1       INT  on  All  Rx  Characters 
(Parity  Does  Not  Affect 
Vector) 

-  Wait  on  Receiver/Transmitter 

-  Tx  Byte  Count  Enable 

-  Wait  Enable 


-  Rx  Enable 

-  Sync  Character  Load  Inhibit 

-  Address  Search  Mode  (SDLC) 

-  RxCRC  Enable 

-  Enter  Hunt  Phase 

-  Auto  Enables 


OR  Interrupt  on 
Special  Receive 
Condition 


Rx5  Bits/Character 
Rx7  Bits/Character 
Rx6  Bits/Character 
Rx8  Bits/Character 


Write  Register  4 


Write  Register  2  (Channel  B) 


-  V5 

-  V6 


Tx  Byte  Count  Register 


-  vo 

-  V1 


y  Interrupt 
Vector 


n 


Parity  Enable 

0  Parity  =  Odd 

1  Parity  =  Even 


1 


1 


Sync  Modes  Enable 

1  Stop  Bit/Character 

1 1/2  Stop  Bits/Character 

2  Stop  Bits/Character 


0       0      8-bit  Sync  Character 

0  1      16-bit  Sync  Character 

1  0  SDLC  Mode  (01111110  Flag) 
1       1      External  Sync  Mode 

X1  Clock  Mode 
X1 6  Clock  Mode 
X32  Clock  Mode 
X64  Clock  Mode 


D4     D3  D: 


-BitO 
-Bit  1 
-Bit  2 
-Bit  3 
-Bit  4 
-Bit  5 
-Bit  6 
-Bit  7 


Tx  Byte  Count  Register 


D2  D1 


Write  Register  2  (Channel  A) 


D5      D4  D3 


Write  Register  5 


Low 
Byte 


-Tx  CRC  Enable 
-RTS 

-CRC-16/CRC-CCITT 
-Tx  Enable 
-  Send  Break 


Tx5  Bits  (or  Less)/Character 
Tx7  Bits/Character 
Tx6  Bits/Character 
Tx8  Bits/Character 


Write  Register  6 


-Bit  8 
-Bit  9 
-Bit  10 
-Bit  11 
-Bit  12 
-Bit  13 
-Bit  14 
-Bit  15 


High 
Byte 


D5  D4 


D2  D1 


-  Sync  Bit  0  ^ 

-  Sync  Bit  1 

-  Sync  Bit  2 

-  Sync  Bit  3 

-  Sync  Bit  4 

-  Sync  Bit  5 

-  Sync  Bit  6 

-  Sync  Bit  7  J 


Also  SDLC 
Address  Field 


0  0  Both  Channels  Interrupt 

0  1  Channel  A  DMA,  Channel  B  INT 

1  0  Both  Channels  DMA-  Internal  Priority  Mode 
1  1  Both  Channels  DMA- External  Priority  Mode 

-  0  Priority  RxA  >  TxA  >  RxB  >  TxB 
1  Priority  RxA  >  RxB  >  TxA  >  TxB 

8085  Master  Mode 
8085  Slave  Mode 
8086/88  Mode 
8085/8259A  Slave  Mode 


Write  Register  7 


-  Interrupt  Vectored/Nonvectored 
Receive  Interrupt  Mask 


-  Sync  Bit  8  ^ 

-  Sync  Bit  9 
-Sync  Bit  10 
-Sync  Bit  11 
-Sync  Bit  12 
-Sync  Bit  13 
-Sync  Bit  14 
-Sync  Bit  15  J 


RTSB  Pin  10 
SYNCB  Pin  10 


Note:  ©  For  SDLC  it  must  be  programmed  to  01 1 1 1 1 1 0  for  flag  recognition 


6-26 


f  PD7201A 


Timing  Waveforms 

Read  Cycle 

C/D,  B/A,  CS  X~ 


tRA  I—- 


Other  Timing 


CTS,  DCD,  SYNC 


C/oc/c 


Write  Cycle 

C/D,  B/A,  CS 
WR 


> 

LtAW— i 

  tww  +\ 

'wa  r 

\ 

-*—  lDW  — *" 

'wo  I 

Read/Write  Cycle 

(Software  Block  Transfer  Mode) 


INTA  Cycle 

INTA  0 ~ 


-trt 


V — \ 


C/D,  B/A,  CS 
RD/WR 


DB 

X  X 

X       X  > 

PR^ 

S 

WAITA/B 


DMA  Cycle 


DRQ 
HAI 
RD/WR 
HAO 


\ 

■^*HIHO"H 

\  r 


Sync  Pulse  Generation 
(External  Sync  Mode) 


RxC  f~ 


Last  Bit  of  First  Bit  of 

Sync  Character     Data  Character 


Transmit  Data  Cycle 


TxC   / 

TxD 


INT 


Notes:  ©  INTA  signal  acts  as  RD  signal 

©  PRI  and  HAI  signals  act  as  CS  signal 


Receive  Data  Cycle 


RxC 
RxD 
INT 


6-27 


,.PD7201A 


AC  Characteristics 

Ta  =  0°C  to  +70°C;  Vcc  =  +5V  ±  10% 


Limits 

Parameter 

Symbol 

Min  Typ 

Max 

Unit 

Test  Conditions 

Clock  Cycle 

tCY 

200 

4000 

ns 

Clock  High  Width 

tCH 

70 

2000 

ns 

Clock  Low  Width 

tCL 

70 

2000 

ns 

Clock  Rise  Time 

tr 

0 

30 

ns 

Clock  Fall  Time 

t, 

0 

30 

ns 

Address  Setup  to  RD 

tAR 

0 

Address  Hold  from  RD 

tRA 

0 

ns 

RD  Pulse  Width 

tRR 

200 

ns 

Data  Output  Delay  from  Address 

tAD 

140 

ns 

Data  Output  Delay  from  RD 

140 

Data  Float  Delay  from  RD 

tDF 

0 

70 

ns 

Address  Setup  to  WR 

0 

ns 

Address  Hold  from  WR 

t 

0 

WR  Pulse  Width 

t 

200 

ns 

Data  Setup  to  WR 

130 

ns 

Data  Hold  from  WR 

*WD 

0 

PRO  Delay  from  PRI 

100 

ns 

PRO  Delay  from  INTA 

tlAPO 

200 

ns 

PRI  Setup  to  INTA 

tpiN 

0 

PRI  Hold  from  INTA 

t,p 

20 

ns 

INTA  Pulse  Width 

t„ 

200 

ns 

End  of  INTA  to  Next  INTA 

300 

ns 

Data  Output  Delay  from  INTA 

t,D 

140 

ns 

Data  Float  Delay  from  INTA 

tDF 

0 

70 

Request  Hold  from  RD/WR 

*CQ 

60 

ns 

HAI  Setup  to  RD/WR 

tLR 

300 

HAI  Hold  from  RD/WR 

tRL 

0 

ns 

HAO  Delay  from  HAI 

100 

ns 

Data  Clock  Cycle 

t 

400 

ns 

RxC,  TxC 

Data  Clock  High  Width 

*DCH 

180 

RxC,  TxC 

Data  Clock  Low  Width 

*DCL 

180 

ns 

RxC,  TxC 

Tx  Data  Delay  from  TxC 

tTD 

300 

ns 

x1  Mode 

1000 

x16,  32,  64 

Rx  Data  Setup  to  RxC 

tos 

0 

ns 

Rx  Data  Hold  from  RxC 

ton 

140 

ns 

INT  Delay  Time  from  Tx  Data 

t|TD 

4-6 

*CY 

INT  Delay  Time  from  RxC 

t|RD 

7-11 

*CY 

CTS,  DCD,  SYNC  High 
Pulse  Width 

tpH 

CTS,  DCD,  SYNC  Low 
Pulse  Width 

tpL 

200 

ns 

External  INT  from  CTS, 
DCD,  SYNC 

*IPD 

500 

ns 

Recovery  Time  Between  Controls  tRV 

300 

ns 

WAIT  Delay  Time  from  Address 

*CW 

80 

ns 

SYNC  Setup  to  RxC 

*DRxC 

100 

ns 

Notes:  1  RESET  must  be  active  for  a  minimum  of  one  complete  CLK  cycle 
2  In  all  modes  system  clock  rate  must  be  4  5  times  data  rate 


AC  Waveform  Measurement  Points 

2  4   20  2J)   


0  45  0.8  0  8 


|xPD7201A  Target  Specifications 
Absolute  Maximum  Ratings 


Ta  =  25°C 

Power  Supply,  Vcc 

-0.5V  to  +  7.0V 

Input  Voltages,  V, 

-0.5V  to  +7.0V 

Output  Voltages,  VQ 

-0.5V  to  +7.0V 

Operating  Temperature,  TOPT 

0°Cto  +70°C 

Storage  Temperature,  TSTG 

-65°Cto  +125°C 

*COMMENT:  Exposing  the  device  to  stresses  above 
those  listed  in  Absolute  Maximum  Ratings  could  cause 
permanent  damage.  The  device  is  not  meant  to  be 
operated  under  conditions  outside  the  limits  described 
in  the  operational  sections  of  this  specification.  Expo- 
sure to  absolute  maximum  rating  conditions  for 
extended  periods  may  affect  device  reliability. 


DC  Characteristics 

Ta  =  OC  to  +70°C;  Vcc  =  +5V  ±  10% 


Limits 

Parameter 

Symbol 

Min 

Typ 

Max 

Unit 

Test  Conditions 

Input  Low  Voltage 

V,L 

-0.5 

+  0.8 

V 

Input  High  Voltage 

V,H 

+  2.0 

Vcc  +  0.5 

V 

Output  Low  Voltage 

Vol 

+  0.45 

V 

l0L  =  +2  0mA 

Output  High  Voltage 

Vqh 

+  2.4 

V 

Ioh  =  200^A 

Input  Leakage  Current 

I.L 

±10 

M.A 

V|N  =  Vccto0V 

Output  Leakage  Current 

'OL 

±10 

ttA 

Vout  =  Vccto0V 

Vcc  Supply  Current 

Ice 

180 

mA 

Capacitance 

Ta  =  25°C;Vcc  = 

GND  =  OV 

Limits 

Parameter 

Symbol 

Min 

Typ 

Max 

Unit 

Test  Conditions 

Input  Capacitance 

10 

PF 

fc  =  1MHz 

Output  Capacitance 

Cqut 

15 

pF 

Unmeasured  pins 

I/O  Capacitance 

C|/o 

20 

PF 

returned  to  GND. 

6-28 


(PD7201A 

Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  jjiPD7201AC 
Ceramic,  |xPD7201AD 


6-29 


7201ADS-REV1-7-83-CAT-L 


Notes 


6-30 


fiPD7210 
INTELLIGENT  GPIB 
INTERFACE  CONTROLLER 


DESCRIPTION     The  /1PD7210  TLC  is  an  intelligent  GPIB  Interface  Controller  designed  to  meet  all  of 


the  functional  requirements  for  Talkers,  Listeners,  and  Controllers  as  specified  by  the 
IEEE  Standard  488-1978.  Connected  between  a  processor  bus  and  the  GPIB,  the  TLC 
provides  high  level  management  of  the  GPIB  to  unburden  the  processor  and  to  simplify 
both  hardware  and  software  design.  Fully  compatible  with  most  processor  architectures, 
Bus  Driver/Receivers  are  the  only  additional  components  required  to  implement  any 
type  of  GPIB  interface. 


FEATURES    •  All  Functional  Interface  Capability  Meeting  IEEE  Standard  488-1978. 


—  SH1  (Source  Handshake) 

—  AH1  (Acceptor  Handshake) 

—  T5  or  TE5  (Talker  or  Extended  Talker) 

—  L3  or  LE3  (Listener  or  Extended  Listener) 

—  SR1  (Service  Request) 

—  R.L1  (Remote  Local) 

—  PP1  or  PP2  ((Parallel  Poll)  (Remote  or  Local  Configuration)) 

—  DC1  (Device  Clear) 

—  DT1  (Device  Trigger) 

—  C1-5  ((Controller)  (All  Functions)) 

•  Programmable  Data  Transfer  Rate 

•  16  MPU  Accessible  Registers  -  8  Read/8  Write 

•  2  Address  Registers 

—  Detection  of  MTA,  MLA,  MSA  (My  Talk/Listen/Secondary  Address) 

—  2  Device  Addresses 

•  EOS  Message  Automatic  Detection 

•  Command  (IEEE  Standard  488-78)  Automatic  Processing  and  Undefined  Command 
Read  Capability 

•  DMA  Capability 

•  Programmable  Bus  Transceiver  I/O  Specification  (Works  with  T.I./Motorola/lntel) 

•  1  to  8  MHz  Clock  Range 

•  TTL  Compatible 

•  N  Channel  MOS 

•  +5V  Single  Power  Supply 

•  40-Pin  Plastic  DIP 

•  8080/85/86  Compatible 


PIN  CONFIGURATION 


REV/2  GND 
6-31 


T/R  1 
T/R  2 
CLOCK 
RESET 
T/R  3 
DMAREQ 
DMAACK 


CS 
RD 
WR 
INT 
D  0 
D  1 
D  2 
D  3 
D4 
D  5 
D  6 
D  7 


C  1 

C  2 
C  3 

c  4 

C  5 

C  6 

C  7 

C  8 

C  9 

C  10 
C  11 

C  12 
C  13 
C  14 
C  15 
C  16 
C  17 
C  18 
C  19 
C  20 


1 7  24 
8  23 


4  27 

5  26 

6  25 


7  34 

8  33 

9  32 

o    juPD7210  31 

11  30 

12  29 

13  28 


4  37 

5  36 

6  35 


3  38 


2  39 


22 
21 


□  VCC 
D  EOI 

□  NDAC 
3  NRFD 
D  DAV 

□  DIP  8 

□  DIP  7 
3  DIP  6 
3  DIP  5 

□  DIP  4 

□  DIP  3 

□  DIP  2 
3  DIP  1 

□  SRP 

□  AJN 

□  REN 

□  IFC 

□  RS2 

□  RS  1 

□  Rso 


PPD7210 


PIN    I  NAME 

I/O 

DESCRIPTION 

1 

T/R1 

0 

Transmit/Receive  Control  —  Input/Output  Control  Signal 
for  the  GPIB  Bus  Transceivers. 

2 

T/R9 

0 

Transmit/Receive  Control  —  The  functions  of  T/R2,  T/R3 
are  determined  by  the  values  of  TRM1,  TRMO  of  the 
address  mode  register. 

3 

CLK 

I 

Clock  —  (1-8  MHz)  Reference  Clock  for  generating  the 
state  change  prohibit  times  T1 ,  T6,  T7,  T9  specified  in 
IEEE  Standard  488-1978. 

4 

RST 

I 

Reset  —  Resets  721 0  to  an  idle  state  when  high  (active  high). 

5 

T/R3 

0 

Transmit/Receive  Control  —  Function  determined  by 
TRM1  and  TRMO  of  address  mode  register  (See  T/R2). 

6 

DRQ 

0 

DMA  Request  —  7210  requests  data  transfer  to  the  com- 
puter system,  becomes  low  on  input  of  DMA  acknowledge 
signal  DACK. 

7 

DACK 

I 

DMA  Acknowledge  —  (Active  Low)  Signal  connects  the 
computer  system  data  bus  to  the  data  register  of  the  721 0. 

p 
o 

PC 

I 

Chip  Select  —  (Active  Low)  Enables  access  to  the  register 
selected  by  RS0-2  (read  or  write  operation). 

9 

RD 

I 

Read  —  (Active  Low)  Places  contents  of  read  register 
specified  by  RS0-2  -  on  DO-7  (Computer  Bus). 

10 

WR 

I 

Write  —  (Active  Low)  writes  data  on  DO-7  into  the  write 
register  specified  by  RS0-2. 

1 1 

INT  / 
/ INT 

0 

Interrupt  Request  —  (Active  High/Low)  Becomes  active 
due  to  any  1  of  13  internal  interrupt  factors  (unmasked) 
active  state  software  configurable,  active  high  on  chip  reset. 

12-19 

DO-7 

I/O 

Data  Bus  —  8-bit  bidirectional  data  bus,  for  interface  to 
computer  system. 

20 

GND 

Ground. 

21  -23 

RSO-2 

I 

Register  Select  —  These  lines  select  one  of  eight  read 
(write)  registers  during  a  read  (write)  operation. 

I  en 

I/O 

Interface  Clear  —  Control  line  used  for  clearing  the  inter- 
face functions. 

25 

REN 

I/O 

Remote  Enable  —  Control  line  used  to  select  remote  or 
local  control  of  the  devices. 

26 

ATN 

I/O 

Attention  —  Control  line  which  indicates  whether  data  on 
DIO  lines  is  an  interface  message  or  device  dependent  message. 

27 

SRQ 

I/O 

Service  Request  —  Control  line  used  to  request  the  con- 
troller for  service. 

28-35 

DI01  -8 

I/O 

Data  Input/Output  —  8-bit  bidirectional  bus  for  transfer 
of  message  on  the  GPIB. 

36 

DAV 

I/O 

Data  Valid  —  Handshake  line  indicating  that  data  on  DIO 
lines  is  valid. 

37 

NRFD 

I/O 

Ready  for  Data  —  Handshake  line  indicating  that  device  is 
ready  for  data. 

38 

NDAC 

I/O 

Data  Accepted  —  Handshake  line  indicating  completion  of 
message  reception. 

39 

EOT 

I/O 

End  or  Identify  —  Control  line  used  to  indicate  the  end  of 
multiple  byte  transfer  sequence  or  to  execute  a  parallel 
polling  in  conjunction  with  ATN. 

40 

vec 

+5V  DC  -  Technical  Specifications:  +5V;  NMOS; 
500  MW;  40  Pins;  TTL  Compatible;  1-8  MHz. 

PIN  IDENTIFICATION 


6-32 


/iPD7210 


BLOCK  DIAGRAM 


REGISTERS 


READ 
WRITE 
CONTROL 


COMMAND  PASS 
THROUGH 


=> 


ADDRESS  STATUS 


ADDRESS  MODE 


ADDRESS  0/1 


END  OF  STRING 


INTERRUPT  MASK  l/2 


<= 

INTERRUPT  STATUS  1/2 

o 

SERIAL  POLL 

PARALLEL  POLL 


=4 


AUX  (A)/(B)/(E) 


INTERNAL 
COUNTER 


3T 


AUX  COMMAND 
DECODER 


2£ 


MESSAGE 
DECODER 


V 

INTERFACE 
FUNCTIONS 


A 
V 


0 


IT 


GPIB  CONTROL 


6-33 


MPD7210 


The  IEEE  Standard  488  describes  a  "Standard  Digital  Interface  for  Programmable  INTRODUCTION 
Instrumentation"  which,  since  its  introduction  in  1975,  has  become  the  most 
popular  means  of  interconnecting  instruments  and  controllers  in  laboratory,  auto- 
matic test  and  even  industrial  applications.  Refined  over  several  years,  the  488-1978 
Standard,  also  known  as  the  General  Purpose  Interface  Bus  (GPIB),  is  a  highly 
sophisticated  standard  providing  a  high  degree  of  flexibility  to  meet  virtually  most 
all  instrumentation  requirements.  The  jLtPD7210  TLC  implements  all  of  the  func- 
tions that  are  required  to  interface  to  the  GPIB.  While  it  is  beyond  the  scope  of 
this  document  to  provide  a  complete  explanation  of  the  IEEE  488  Standard,  a 
basic  description  follows: 

The  GPIB  interconnects  up  to  15  devices  over  a  common  set  of  data  control  lines. 
Three  types  of  devices  are  defined  by  the  standard:  Talkers,  Listeners,  and  Con- 
trollers, although  some  devices  may  combine  functions  such  as  Talker/Listener  or 
Talker/Controller. 

Data  on  the  GPIB  is  transferred  in  a  bit  parallel,  byte  serial  fashion  over  8  Data  I/O 
lines  (D101  —  D108).  A  3  wire  handshake  is  used  to  ensure  synchronization  of 
transmission  and  reception.  In  order  to  permit  more  than  one  device  to  receive  data 
at  the  same  time,  these  control  lines  are  "Open  Collector"  so  that  the  slowest 
device  controls  the  data  rate.  A  number  of  other  control  lines  perform  a  variety  of 
functions  such  as  device  addressing,  interrupt  generation,  etc. 

The  juPD7210  TLC  implements  all  functional  aspects  of  Talker,  Listener  and  Con- 
troller functions  as  defined  by  the  488-1978  Standard.and  on  a  single  chip. 


The  /iPD7210  TLC  is  an  intelligent  controller  designed  to  provide  high  level  protocol 
management  of  the  GPIB,  freeing  the  host  processor  for  other  tasks.  Control  of  the 
TLC  is  accomplished  via  16  internal  registers.  Data  may  be  transferred  either  under 
program  control  or  via  DMA  using  the  TLC's  DMA  control  facilities  to  further  reduce 
processor  overhead.  The  processor  interface  of  the  TLC  is  general  in  nature  and  may 
be  readily  interfaced  to  most  processor  lines. 

In  addition  to  providing  all  control  and  data  lines  necessary  for  a  complete  GPIB 
implementation,  the  TLC  also  provides  a  unique  set  of  bus  transceiver  controls 
permitting  the  use  of  a  variety  of  different  transceiver  configurations  for  maximum 
flexibility. 


GENERAL 


INTERNAL  REGISTERS 

The  TLC  has  16  registers,  8  of  which  are  read  and  8  write. 


REGISTER  NAME 


ADDRESSING 


SPECIFICATION 


Data  In  [OR] 
Interrupt  Status  1  [1R] 
Interrupt  Status  2  [2R] 
Serial  Poll  Status  [3R] 
Address  Status  [4R] 
Command  Pass  Through  [5R] 
Address  0  [6R] 
Address  1  [7R] 

Byte  Out  [OW] 
Interrupt  Mask  1  [1W] 
Interrupt  Mask  2  [2W] 
Serial  Poll  Mode  [3W] 
Address  Mode  [4W] 
Auxiliary  Mode  [5W] 
Address  0/1  [6W] 
End  of  String  [7WJ 


INT     |  SROT 


S8      |  PEND" 


|  EQI 


ton 


ATN 


I  CPT7    |  CPT6" 


I  DTP 


B07     |  B06~ 


CPT     |  APT~ 


I     0       |  SRQI 


Ion 


I  ARS     I  DT 


|  DI3 


PET    |    END     I  DEC 


LQK    |    REM     I  CO 


S6      |     S5       |  S4 


SPMS    I    LPAS    I  TPAS 


CPT5    |   CPT4    |  CPT3~ 


DLO    I  AD5-0    I  AD4-6~ 


AD5-1    I  AD4-1 


B05 


B04 


B03 


PET    |    END     |  DEC 


DMAO  I   DMA  I 


S6  | 


j: 


TRM1    |  TRMO    |  0 


I  CNT2    I  CNT1    |  CNTO   1  COM4    |  COM3 


PL     |  AD5~ 


AD4 


EC7     |    EC6     |    EC5  ~|~ 


HQ 


MJMN| 


CPTO  | 


AP1-0I 


BOO  | 


ID 


APMOl 


COMOl 


6-34 


HPD7210 


DATA  REGISTERS 

The  data  registers  are  used  for  data  and  command  transfers  between  the  GPIB  and  the 
microcomputer  system. 


DI7 


DI6 


DI5 


DI4    |  DI3    |    DI2  |  DI1     |  DIP  ] 


DATA  IN  (OR) 

Holds  data  sent  from  the  GPIB  to  the  computer 

BYTE  OUT  (OW)        |  BQ7  |  B06  |  B05  |  B04  {  BQ3  [  B02  |  BQ1  |  BQOl 
Holds  information  written  into  it  for  transfer  to  the  GPIB 
INTERRUPT  REGISTERS 

The  interrupt  registers  are  composed  of  interrupt  status  bits,  interrupt  mask  bits, 
and  some  other  noninterrupt  related  bits. 


INTERRUPT 
STATUS  1  [1R] 

INTERRUPT 
STATUS  2  [2R] 


INTERRUPT 
MASK  1  [1W] 

INTERRUPT 
MASK  2  [2W] 


READ 

[CPT   ]  APT  I   PET   I  END  [  DEC  |    ERR  |    DQ     |    PI  | 
I  INT   |  SRQI  |    LOK  ]  REM  [    CO    [  LOKC  \  REMC  \  APSC  | 
WRITE 

|  CPT  |  APT  |  PET  I  ENP  |  PEC  |  ERR  |  DO  |  PI  | 
|    0     |  SRQI  |  PMAO|  PMAI  |    CO    |  LOKC  |  REMC  |  APSC  | 


There  are  thirteen  factors  which  can  generate  an  interrupt  from  the  juPD7210,  each 
with  their  own  status  bit  and  mask  bit. 

The  interrupt  status  bits  are  always  set  to  one  if  the  interrupt  condition  is  met. 
The  interrupt  mask  bits  decide  whether  the  INT  bit  and  the  interrupt  pin  will  be 
active  for  that  condition. 

Interrupt  Status  Bits 


INT 

OR  of  All  Unmasked  Interrupt  Status  Bits 

CPT 

Command  Pass  Through 

APT 

Address  Pass  Through 

DET 

Device  Trigger 

END 

End  (END  or  EOS  Message  Received) 

DEC 

Device  Clear 

ERR 

Error 

DO 

Data  Out 

Dl 

Data  In 

SRQI 

Service  Request  Input 

LOKC 

Lockout  Change 

REMC 

Remote  Change 

ADSC 

Address  Status  Change 

CO 

Command  Output 

Noninterrupt  Related  Bits 


LOK 

Lockout 

REM 

Remote/ Local 

DMAO 

Enable/Disable  DMA  Out 

DMAI 

Enable/Disable  DMA  In 

6-35 


fiPD7210 


SERIAL  POLL  REGISTERS 

READ 

SERIAL  POLL  

STATUS  [3R]  |  S8    [  PEND  [    S6    ]    S5     ]   S4      j  S3     \    S2     |    SI  | 

WRITE 

SERIAL  POLL  _______  

MODE  [3W]  |  S8     |   rSV    |    S6     |    S5      |   S4      |  S3     \    S2     |    SI  | 

The  Serial  Poll  Mode  register  holds  the  STB  (status  byte:  S8,  S6-S1)  sent  over  the 
GPIB  and  the  local  message rsv  (request  service).  The  Serial  Poll  Mode  register 
may  be  read  through  the  Serial  Poll  Status  register.  The  PEND  is  set  byrsv=  1,  and 
cleared  by  NPRS*iPsv=  1  (NPRS  =  Negative  Poll  Response  State). 

ADDRESS  MODE/STATUS  REGISTERS 

ADDRESS  STATUS  [4R]  |  CIC  [  ATN  [  SPMS  [  LPAS  I  TP  AS  |  LA  I  TA  |  MJMnI 
ADDRESS  MODE  [4W]  |  ton    [    Ion    1  TRM1  |  TRMO  |    0       |   0     |  ADM1  |  ADMp] 

The  Address  Mode  register  selects  the  address  mode  of  the  device  and  also  sets  the 
mode  for  T/R3  and  T/R2  the  transceiver  control  lines. 


The  functions  of  T/R2,  T/R3  terminals  (2  and  5)  are  determined  as  below  by 
the  TRM1,  TRMO  values  of  the  address  mode  register. 


T/R2 

T/R3 

TRM1 

TRMO 

EOIOE 

TRIG 

0 

0 

CIC 

TRIG 

0 

1 

CIC 

EOIOE 

1 

0 

CIC 

PE 

1 

1 

EOIOE  =  TAGS  +  SPAS  +  CIC  ■  CSBS 

This  denotes  the  input/output  of  EOI  terminal. 

When  "1":  Output 
When  "0":  Input 

CIC  =CIDS  + CADS 

This  denotes  if  the  controller  inteface  function  is  active  or  not. 

When  "1":  ATN  =  output,  SRQ  =  input 
When  "0":  ATN  =  input,  SRQ  =  output 

PE  =  CIC+PPAS 

This  indicates  the  type  of  bus  driver  connected  to  DI08  to  DI01  and  DAV  lines. 

When  "1":  3  state  type 

When  "0":  Open  collector  type 

TRIG:  When  DTAS  state  is  initiated  or  when  a  trigger  auxiliary  command  is 
issued,  a  high  pulse  is  generated. 

Upon  RESET,  TRMO  and  TRM1  become  "0"  (TRMO  =  TRM1  =  0)  and  local 
message  port  is  provided,  so  that  T/R2  and  T/R3  both  become  "LOW." 


6-36 


MPD7210 

ADDRESS  MODES 


ton 

Ion 

ADM1 

ADMO 

ADDRESS 
MODE 

CONTENTS  OF 
ADDRESS  (0) 
REGISTER 

CONTENTS  OF 
ADDRESS  (1) 
REGISTER 

1 

0 

0 

0 

Talk  only 
mode 

Address  Identification  Not  Necessary 
(No  controller  on  the  GPIB) 
Not  Used 

0 

1 

0 

0 

Listen  only 
mode 

0 

0 

0 

1 

Address  mode  1 
/Ok 

Major  talk  address 
or  Major  listen 
address 

Minor  talk  address 
or  Minor  listen 
address 

0 

0 

1 

0 

Address  mode  2 

© 

Primary  address 
(talk  or  listen) 

Secondary  address 
(talk  or  listen) 

0 

0 

1 

1 

Address  mode  3 

© 

Primary  address 
(major  talk  or 
major  listen) 

Primary  address 
(minor  talk  or 
minor  listen) 

Combinations  other  than  above 
indicated  Prohibited. 

Notes:  (Aj)—  Either  MTA  or  MLA  reception  is  indicated  by  coincidence  of  either  address  with  the 
received  address.  Interface  function  T  or  L. 

^2)—  Address  register  0  =  primary,  Address  register  1  =  secondary,  interface  function  TE 
or  LE. 

^3)—  CPU  must  read  secondary  address  via  Command  Pass  Through  Register  interface 
function  (TE  or  LE). 

ADDRESS  STATUS  BITS 


ATN  Data  Transfer  Cycle  (device  in  CSBS) 

LPAS  Listener  Primary  Addressed  State 

TPAS  Talker  Primary  Addressed  State 

CIC  Controller  Active 

LA  Listener  Addressed 

TA  Talker  Addressed 

MJMN  Sets  minor  T/L  address  Reset  =  Major  T/L  address 

SPMS  Serial  Poll  Mode  State 

ADDRESS  REGISTERS 

ADDRESS  0  [6R]  \    X     I   DTP  )  DLO  I  AD5-0  I AD4-0  \  AD3-0  I  AD2-0  I  AD1 

ADDRESS  1  [7R]  |  EQI    I    DTI    |  DL1   l  AD5-1  l  AD4-1  I  AD3-1  |  AD2-1  j  AD1-1  | 

ADDRESS  0/1  [6W]  I  ARS  I    DT    |    PL    |  AD5   I  AD4  |  AD3   I  AD2  |  AD1  | 


The  TLC  is  able  to  automatically  detect  two  types  of  addresses  which  are  held  in 
address  registers  0  and  1.  The  addressing  modes  are  outlined  below. 
Address  settings  are  made  by  writing  into  the  address  0/1  register.  The  function 
of  each  bit  is  described  below. 

ADDRESS  0/1  REGISTER  BIT  SELECTIONS 

ARS  —  Selects  which  address  register  0  or  1 

DT    —  Permits  or  Prohibits  address  to  be  detected  as  Talk 

DL    —  Permits  or  Prohibits  address  to  be  detected  as  Listen 

AD5  —  AD1  —  Device  address  value 

EOI  —  Holds  the  value  of  EOI  line  when  data  is  received 

COMMAND  PASS  THROUGH  REGISTER 

COMMAND  PASS  

THROUGH  [5R]         |  CPT7   |  CPT6  [  CPT5  [  CPT4  [  CPT3  |  CPT2   |  CPT1  [  CPTOj 

The  CPT  register  is  used  such  that  the  CPU  may  read  the  DIO  lines  in  the  cases  of 
undefined  command,  secondary  address,  or  parallel  poll  response. 


6-37 


HPD7210 

END  OF  STRING  REGISTER 

END  OF  __.  

STRING  [7W]  |EC7    |   EC6    |  EC5  |    EC4    |   EC3  |    EC2    |   EC1    [    ECO  | 

This  register  holds  either  a  7-  or  8-bit  EOS  message  byte  used  in  the  GPIB  system  to 
detect  the  end  of  a  data  block.  Aux  Mode  Register  A  controls  the  specific  use  of 
this  register. 

AUXILIARY  MODE  REGISTER 

AUXILIARY  •  

MODE  [5W]         |  CNT2  |  CNT1  |  CNTO  |  COM4  [  COM3  |   COM2  |  COM1  |  COMO  | 

This  is  a  multipurpose  register.  A  write  to  this  register  generates  one  of  the  following 
operations  according  to  the  values  of  the  CNT  bits. 


2 

CNT 
1 

0 

4 

3 

COM 
2 

1 

0 

OPERATION 

0 

0 

0 

C4 

c3 

c2 

Ci 

c0 

Issues  an  auxiliary  command  specified  by 
C4  to  Co. 

The  reference  clock  frequency  is  specified 

0 

0 

1 

0 

F3 

F2 

F1 

FO 

and  T-],  Tq,  Tj,  Tg  are  determined  as  a 
result. 

0      1  1 

u 

S 

P3 

P2 

Pi 

Makes  write  operation  to  the  parallel  poll 
register. 

1 

0 

0 

A4 

A3 

A2 

Ai 

A0 

Makes  write  operation  to  the  aux.  (A) 
register. 

1 

0 

1 

B4 

B3 

B2 

B1 

BO 

Makes  write  operation  to  the  aux.  (B) 
register. 

1 

1 

0 

0 

0 

0 

El 

E0 

Makes  write  operation  to  the  aux.  (E) 
register. 

AUXILIARY  COMMANDS    0  0  0  C4  C3  C2  C<\  C0 


COM 

43210 
00000 

00010 
00011 
00100 
00101 
00110 
00111 

01111 

0X001 
10000 
10001 
10010 
11010 


iepon  -    Immediate  Execute  pon  -  Generate  local 
pon  Message 

erst     —    Chip  Reset  —  Same  as  External  Reset 
rrfd     -    Release  RFD 
trig      -  Trigger 

rtl       —    Return  to  Local  Message  Generation 
seoi     -    Send  EOI  Message 

nvld     -    Non  Valid  (OSA  reception)  -  Release  DAC 
Holdoff 

vld      -    Valid  (MSA  reception,  CPT,  DEC,  DET)  - 

Release  DAC  Holdoff 
sppf     -    Set/Reset  Parallel  Poll  Flag 
gts      —    Go  To  Standby 
tea      —    Take  Control  Asynchronously 
tcs      —    Take  Control  Synchronously 
tcse     —    Take  Control  Synchronously  on  End 


10011 

Itn 

—  Listen 

11011 

Itnc 

—    Listen  with  Continuous  Mode 

11100 

lun 

—    Local  Unlisten 

11101 

epp 

-    Execute  Parallel  Poll 

1X110 

sifc 

-    Set/ Reset  I FC 

1X111 

sren 

-    Set/ Reset  REN 

10100 

dsc 

—    Disable  System  Control 

6-38 


MPD7210 


INTERNAL  COUNTER    0  0  1  0  F3  F2  F«|  F0 

The  internal  counter  generates  the  state  change  prohibit  times  (T<|,  Tq,  T7,  Tg) 
specified  in  the  IEEE  std  488-1978  with  reference  to  the  clock  frequency. 

AUXILIARY  A  REGISTER    1  0  0  A4  A3  A2  A<\  A0 

Of  the  5  bits  that  may  be  specified  as  part  of  its  access  word,  2  bits  control  the 
GPIB  data  receiving  modes  of  the  7210  and  3  bits  control  how  the  EOS  message  is 
used. 


A1 

AO 

DATA  RECEIVING  MODE 

0 

0 

Normal  Handshake  Mode 

0 

1 

RFD  Holdoff  on  all  Data  Modes 

1 

0 

RFD  Holdoff  on  End  Mode 

1 

1 

Continuous  Mode 

BIT 
NAME 

FUNCTION 

A2 

0 

Prohibit 

Permits  (prohibits)  the  setting  of  the  END  bit 
by  reception  of  the  EOS  message. 

Permits  (prohibits)  automatic  transmission  of 
END  message  simultaneously  with  the  trans- 
mission of  EOS  message  TACS. 

Makes  the  8  bits/7  bits  of  EOS  register  the 
valid  EOS  message. 

1 

Permit 

A3 

0 

Prohibit 

1 

Permit 

A4 

0 

7  bit  EOS 

1 

8  bit  EOS 

AUXILIARY  B  REGISTER    1  0  1  B4  B3  B2  Bt  Bq 

The  Auxiliary  B  Register  is  much  like  the  A  Register  in  that  it  controls  the  special 
operating  features  of  the  device. 


BIT 
NAME 

FUNCTION 

BO 

1 

Permit 

Permits  (prohibits)  the  detection  of  undefined 
command.  In  other  words,  it  permits  (pro- 
hibits) the  setting  of  the  CPT  bit  on  reception 
of  an  undefined  command. 

0 

Prohibit 

B1 

1 

Permit 

Permits  (prohibits)  the  transmission  of  the 
END  message  when  in  serial  poll  active  state 
(SPAS). 

0 

Prohibit 

B2 

1 

T1 

(high-speed) 

T1  (high  speed)  as  T1  of  handshake  after 
transmission  of  2nd  byte  following  data 
transmission. 

0 

T1 

(low-speed) 

B3 

1 

INT- 

Specifies  the  active  level  of  INT  pin. 

0 

INT 

B4 

1 

ist  =  SRQS 

SRQS  indicates  the  value  of  ist  level  local 
message  (the  value  of  the  parallel  poll  flag 
is  ignored). 

SRQS=  1  ...  ist  =  1. 

SRQS  =  0  . .  .  ist  =  0. 

0 

ist  =  Parallel 
Poll  Flag 

The  value  of  the  parallel  poll  flag  is  taken 
as  the  ist  local  message. 

6-39 


j*PD7210 


AUXILIARY  E  REGISTER    1  1  0  0  0  0  E|  Eq 

This  register  controls  the  Data  Acceptance  Modes  of  the  TLC. 


BIT 

FUNCTION 

EO 

1 

Enable 

DAC  Holdoff  by  initiation  of  DCAS 

0 

Disable 

1 

Enable 

DAC  Holdoff  by  initiation  of  DTAS 

0 

Disable 

Parallel  Poll  Register  0       1        1       U       S       P3       ?2  Pi 

The  Parallel  Poll  Register  defines  the  parallel  poll  response  of  the  ;uPD7210. 


0 

1 

1|U 

s  I  p3 

P2 

P1 

SPECIFYING  STATUS  BIT 
OUTPUT  LINE  (DI01  TO  DI08) 

SPECIFYING  STATUS  BIT 
POLARITY 

S  =  1  :  IN  PHASE 

S  =  0  :  REVERSE  PHASE 

U  =  1  :  NO  RESPONSE  TO  PARALLEL  POLL 
U  =  0  •  RESPONSE  TO  PARALLEL  POLL 


6-40 


jiPD7210 


MINIMUM  8085  SYSTEM 
WITH  MPD7210 


CE 

TIMER  IN 
RESET  12 


ALE 
WR 
RD 
IO/M 

AD7.8 


in 


 ^  s 


XI 


cs  g 

CLOCK      <  v 
RESET  II 
WR       o  P 
RD 


*s  RS2-o 


*  a 
in 

< 
2 


00 

< 


12  |Q  IDC 
??  Ice  IBS 


<  o  o 


6-41 


/iPD7210 


MPD7210 


DIP 

'^5 


D106 
DICT 


DIO4 

DToj 

DI02 


DIO! 


-t>-H> 


T/R3  (EOIOE) 
"EOT 

DAV 

NRFD 

NDAC 


T/R2  (CIO 
SlTO" 

ATN* 

REN 


MC3448AX4 

DATA  A  BUS  A 

DATA  B  BUS  B 

DATA  C  BUS  C 

DATA  D  BUS  D 

s/Ra-d     PEA-D  |"~ 


GPIB 

-DlOg 
-DIO7 
-DI06 
-DIO5 


PATA  A  BUS  A 
DATA  B  BUS  B 
DATA  C  BUS  C 
DATA  D  BUS  D 
S/Ra-D  peA-d 


S/RA 

DATA  A 

BUS  A 

S/RB 

DATA  B 

BUS  B 

S/RC 

DATA  C 

BUSC 

S/RD 

DATA  D 

BUS  D 

pea-d 

S/RA 

DATA  A 

BUS  A 

S/RB 

DATA  B 

BUS  B 

S/RC 

DATA  C 

BUS  C 

S/RD 

DATA  D 

BUS  D 

PEA-D 

MINIMUM  8085  SYSTEM 
WITH  mPD7210(CONT.) 


-D104 
-D103 

-DI02 
-DlO-i 


-EOI 
-DAV 
-NRFD 
-NDAC 


-SRQ 

-  ATN 
-REN 

-  IFC 


TT 

"H""L"  "L" 

Note:   In  this  example,  high-speed  data  transfer  cannot  be  made  since  the  bus 
transceiver  is  of  the  open  collector  type  (Set  B2  =  0). 


DI08 

DT07 
5To£ 

Diol 

DIO^ 

5l0l 

DlO] 
T/R3  (PE) 

MPD7210  T/R-| 


T/R2  (CIC) 
SRQ 
ATN 

EOTt- 
DAV 
NRFD 
NDAC 
TPC 
REN 


B7 
B6 
B5 

SN75160  84 
B3 
B2 
B1 


>QPIB 


-o- 


TE 

DC 

SRQ 

ATN 

E01  SN75161 

DAV 

NRFD 

NDAC 

IFC 

REN 


Note:   In  the  case  of  low-speed  data  transfer  (B2  =  0),  the  T/R3  pin  can  be  used  as  a 
TRIG  output.  The  PE  input  of  SN75160  should  be  cleared  to  "0." 


6-42 


MPD7210 


ABSOLUTE  MAXIMUM     (Ta  =  25°c) 


RATINGS 


Parameter 

Symbol 

Test  Conditions 

Ratings 

Unit 

Supply  Voltage 

vCc 

-0.5  ~  +  7.0 

V 

Input  Voltage 

V| 

-0.5  ~  +7.0 

V 

Output  Voltage 

v0 

-0.5  ~  +7.0 

V 

Operating  Temperature 

Topt 

0~+70 

°c 

Storage  Temperature 

Tstg 

-65- +125 

°c 

D  C  C  H  A  R  ACT  E  R I  ST  I CS    <Ta  =  o  ~  +70°  c,  vcc  =  5V  ±  1  o%) 


Parameter 

Symbol 

Test  Conditions 

Limits 

Unit 

Min 

Typ 

Max 

Input  Low  Voltage 

V|L 

-0.5 

+0.8 

V 

Input  High  Voltage 

V|H 

+2.0 

VCC  +  0-5 

V 

Low  Level 

Output  Voltage 

vol 

'OL  =  2  mA 

(4  mA  :  T/R1  Pin) 

+0.45 

V 

High  Level 

Output  Voltage 

vOH1 

I  OH  =-400  mA 
(Except  INT) 

+2.4 

V 

High  Level 

Output  Voltage 
(INT  Pin) 

vOH2 

•OH  =  -400  MA 
lOH  =-50  mA 

+2.4 
+3.5 

V 

Input  Leakage 
Current 

'IL 

V|N  =  0V  ~  VCC 

-10 

+10 

HA 

Output  Leakage 
Current 

»OL 

V0UT  =  0.45V  ~  VCC 

-10 

+10 

MA 

Supply  Current 

•cc 

+180 

mA 

CAPACITANCE   (Ta  =  25°  c,  vcc  -  gnd  =  ov) 


Parameter 

Symbol 

Test  Conditions 

Limits 

Unit 

Min. 

Typ 

Max 

Input  Capacitance 

C|N 

f  =  1  MHz 

All  Pins  Except  Pin  Under 
Test  Tied  to  AC  Ground 

10 

pF 

Output  Capacitance 

cOUT 

15 

PF 

I/O  Capacitance 

C|/0 

20 

pF 

6-43 


MPD7210 


(Ta-o~70°c.vCc-sv±io%>  AC  CHARACTERISTICS 


Parameter 

Symbol 

Conditions 

Limits 

Unit 

Min 

Max 

EOTl  -*  DIO 

tEODI 

PPSS     PPAS,  ATN  =  True 

250 

ns 

i0U^T/R1t 

tEOT1 1 

PPSS    PPAS,  ATN  =  True 

1 55 

ns 

E07t-*T/R1>j 

*EOT12 

PPAS  -*  PPSS,  ATN  =  False 

200 

ns 

ATN4  -+  NDACl 

*ATND 

AIDS-*  AN RS,  LIDS 

155 

ns 

ATN4  -*T/RH 

*ATT1 

TACS  +  SPAS  -►  TADS,  CIDS 

155 

ns 

ATN4  T/R2I 

tATT2 

TACS  +  SPAS  -*  TADS,  C IDS 

200 

ns 

DAV4  DMAREQ 

tDVRQ 

ACRS     ACDS,  LACS 

600 

ns 

DAV4  -*■  NRFD4 

*DVNR1 

ACRS-+  ACDS 

350 

ns 

DAVI  -*  NDACt 

tDVNDI 

ACRS-*  ACDS  AWNS 

Rtzr\ 

DOU 

ns 

DAVt  -+  NDAC4 

tDVND2 

AWNS-»- ANRS 

350 

ns 

DAVt  ->  NRFDt 

tDVNR2 

AWNS  ->  ANRS  -*  ACRS 

350 

ns 

RD4  ->  NRFDt 

*RNR 

ANRS-*  ACRS 
LACS,  Dl  reg.  selected 

500 

ns 

NDACt  -*  DMAREQt 

t|\JDRQ 

STRS     SWNS  -»  SGNS,  TACS 

400 

ns 

NDACt  DAVt 

*NDDV 

STRS -*SWNS-+ SGNS 

350 

ns 

WRt  -*"Di0 

twbi 

SGNS-*  SDYS,  BO 
reg.  selected 

250 

ns 

NRFDt  -*  DAV4 

tNRDV 

SDYS  -»  STRS,  T-j  =  True 

350 

ns 

WRt  -+*DAV4 

*WDV 

SGNS  ->  SDYS  ->  STRS 
BO  reg,  selected,  RFD  =  True 
NF  =  fc  =  8MHz, 
T-j  (High  Speed) 

830 

+*SYNC 

ns 

TRIG 
Pulse  Width 

tTRIG 

50 

ns 

6-44 


MPD7210 


AC  CHAR ACTER ISTICS      <Ta  =  o  ~ 70°c,  vCc -  bv  ±  10%) 


Parameter 

Symbol 

Test  Conditions 

Limits 

Unit 

Min 

Max 

Address  Setup  to  RD 

*AR 

RSO  ~  RS2 

85 

ns 

CS 

0 

ns 

Address  Hold  from  RD 

tRA 

0 

ns 

RD  Pulse  Width 

tRR 

170 

ns 

Data  Delay  from  Address 

tAD 

250 

ns 

Data  Delay  from  RD4- 

tRD 

150 

ns 

Output  Float  Delay  from  RDt 

tDF 

0 

80 

ns 

RD  Recovery  Time 

tRV 

250 

ns 

Address  Setup  to  WR 

*AW 

0 

ns 

Address  Hold  from  WR 

*WA 

0 

ns 

WR  Pulse  Width 

tww 

170 

ns 

Data  Setup  to  WR 

*DW 

150 

ns 

Data  Hold  from  WR 

*WD 

0 

ns 

WR  Recovery  Time 

tRV 

250 

ns 

DMARECU Delay  from  DMAACK 

tAKRQ 

130 

ns 

Data  Delay  from  DMAACK 

tAKD 

200 

ns 

6-45 


jiPD7210 


TIMING  WAVEFORMS 


CS,  RS2  ~  0 


D7  ~  0 


> 

-*  tRR  to- 

i 

^  J 

—  tRD  

 tRV   fc- 

tDF  |-*- 

/// 

High  Impedance ^ / / f7 

!^         Valid            ^C/y///rH'9h  ,mPedance'///y//^/ 

-«  *AD  *- 

-*  tAKD  *~ 

-tAKRQ- 


DMAREQ 


s 


CS,  RS2  ~  0 


WR 


D7  ~  0 


-tAW- 


-tww- 


■tQW- 


-tWA- 


-tRV" 


Package  Outlines 

For  information,  see  Package  Outline  Section  7. 

Plastic,  |xPD7210C 
Ceramic,  |xPD7210D 


6-46 


7210DS-REV2-7-83-CAT 


STfTC  fxPD7220/GDC 
^  ^  w  fxPD7220-1/fxPD7220-2 

GRAPHICS  DISPLAY 
CONTROLLER 


Description 

The  ^iPD7220  Graphics  Display  Controller  (GDC)  is  an 
intelligent  microprocessor  peripheral  designed  to  be  the 
heart  of  a  high-performance  raster-scan  computer  graphics 
and  character  display  system.  Positioned  between  the 
video  display  memory  and  the  microprocessor  bus,  the 
GDC  performs  the  tasks  needed  to  generate  the  raster 
display  and  manage  the  display  memory.  Processor  soft- 
ware overhead  is  minimized  by  the  GDC's  sophisticated 
instruction  set,  graphics  figure  drawing,  and  DMA  transfer 
capabilities.  The  display  memory  supported  by  the  GDC 
can  be  configured  in  any  number  of  formats  and  sizes  up  to 
256K  16-bit  words.  The  display  can  be  zoomed  and  pan- 
ned, while  partitioned  screen  areas  can  be  independently 
scrolled.  With  its  light  pen  input  and  multiple  controller 
capability,  the  GDC  is  ideal  for  advanced  computer 
graphics  applications. 

For  a  more  detailed  description  of  the  GDC's  operation, 
please  refer  to  the  GDC  Design  Manual. 
System  Considerations 

The  GDC  is  designed  to  work  with  a  general  purpose 
microprocessor  to  implement  a  high-performance 
comjputer  graphics  system.  Through  the  division  of  labor 
established  by  the  GDC's  design,  each  of  the  system  com- 
ponents is  used  to  the  maximum  extent  through  six-level 
hierarchy  of  simultaneous  tasks.  At  the  lowest  level,  the 
GDC  generates  the  basic  video  raster  timing,  including 
sync  and  blanking  signals.  Partitioned  areas  on  the  screen 
and  zooming  are  also  accomplished  at  this  level.  At  the 
next  level,  video  display  memory  is  modified  during  the 
figure  drawing  operations  and  data  moves.  Third,  display 
memory  addresses  are  calculated  pixel  by  pixel  as  drawing 
progresses.  Outside  the  GDC  at  the  next  level,  preliminary 
calculations  are  done  to  prepare  drawing  parameters.  At 
the  fifth  level,  the  picture  must  be  represented  as  a  list  of 
graphics  figures  drawable  by  the  GDC.  Finally,  this  repre- 
sentation must  be  manipulated,  stored,  and  communi- 
cated. By  handling  the  first  three  levels,  the  GDC  takes 
care  of  the  high-speed  and  repetitive  tasks  required  to 
implement  a  graphics  system . 


Features 

□  Microprocessor  Interface 

DMA  transfers  with  8257-  or  8237-type  controllers 
FIFO  Command  Buffering 

□  Display  Memory  Interface 
Up  to  256K  words  of  16  bits 

Read-Modify- Write  (RMW)  Display  Memory  cycles 
in  under  800ns 

Dynamic  RAM  refresh  cycles  for  nonaccessed  memory 

□  Light  Pen  Input 

□  External  video  synchronization  mode 

□  Graphics  Mode 

Four  megabit,  bit-mapped  display  memory 

□  Character  Mode 

8K  character  code  and  attributes  display  memory 

□  Mixed  Graphics  and  Character  Mode 
64K  if  all  characters 

1  megapixel  if  all  graphics 

□  Graphics  Capabilities 

Figure  drawing  of  lines,  arc/circles,  rectangles,  and 
graphics  characters  in  800ns  per  pixel 
Display  1024-by-1024  pixels  with  4  planes  of  color 
or  grayscale 

Two  independently  scrollable  areas 

□  Character  Capabilities 
Auto  cursor  advance 

Four  independently  scrollable  areas 
Programmable  cursor  height 
Characters  per  row:  up  to  256 
Character  rows  per  screen:  up  to  100 

□  Video  Display  Format 

Zoom  magnification  factors  of  1  to  16 
Panning 

Command-settable  video  raster  parameters 

□  Technology 

Single  +5  volt,  NMOS,  40-pin  DIP 

□  DMA  Capability 
Bytes  or  word  transfers 

4  clock  periods  per  byte  transferred 


Rev/4 
6-47 


|xPD7220 


Pin  Configuration 


2xWCLK 

C 

1 

»2 

3 

Vcc 

DBIN 

2 

39 

^ 

HSYNC 

3 

Aie 

V/EXT  SYNC 

~ 

7220 

z. 

Aril  a 

BLANK 

5 

ALE 

C 

6 

35 

□ 

Am  4 
Inio 

DRQ 

C 

7 

DACK 

C 

8 

33 

AD11 

"15" 
"WR 

c 

g 

32 

AD10 

c 

10 

31 

□ 

AD9 

AO 

c 

11 

30 

ADS 

DBO 

c 

12 

29 

AD7 

OB1 

c 

13 

28 

□ 

AD6 

DB2 

c 

14 

27 

3 

AD5 

DB3 

c 

15 

26 

1 

AD4 

DB4 

c 

16 

25 

2 

AD3 

DB5 

c 

17 

24 

□ 

AD2 

DB6 

c 

18 

23 

AD1 

DB7 

c 

19 

22 

□ 

ADO 

GND 

c 

20 

21 

□ 

LPEN 

Pin  Identification 


Character  Mode  Pin  Utilization 


No. 

Pin 

Symbol 

Direction 

Function 

1 

2XWCLK 

IN 

Clock  Input 

2 

DBIN 

OUT 

Display  Memory  Read  Input  Flag 

3 

HSYNC 

OUT 

Horizontal  Video  Sync  Output 

4 

V/EXT  SYNC 

IN/OUT 

Vertical  Video  Sync  Output  or  External  VSYNC  Input 

5 

BLANK 

OUT 

CRT  Blanking  Output 

6 

ALE  (RES) 

OUT 

Address  Latch  Enable  Output 

7 

DRQ 

OUT 

DMA  Request  Output 

8 

DACK 

IN 

DMA  Acknowledge  Input 

9 

m 

IN 

Read  Strobe  Input  for  Microprocessor  Interface 

10 

WR 

IN 

Write  Strobe  Input  for  Microprocessor  Interface 

11 

AO 

IN 

Address  Select  Input  for  Microprocessor  Interface 

12-19 

DBO  to  7 

IN/OUT 

Bidirectional  Data  Bus  to  Host  Microprocessor 

20 

GND 

Ground 

21 

LPEN 

IN 

Light  Pen  Detect  Input 

22-34 

ADO  to  12 

IN/OUT 

Address  and  Data  Lines  to  Display  Memory 

35-37 

AD13tOl5 

IN/OUT 

Utilization  Varies  with  Mode  of  Operation 

38 

A16 

OUT 

Utilization  Varies  with  Mode  of  Operation 

39 

A17 

OUT 

Utilization  Varies  with  Mode  of  Operation 

40 

Vcc 

+  5V  ±  10% 

35-37  AD13tOl5 


Line  Counter  Bits  0  to  2  Outputs 


Line  Counter  Bit  3  Output 


Cursor  Output  and  Line  Counter  Bit  4* 


Mixed  Mode  Pin  Utilization 


35-37  AD13to15 


Address  and  Data  Bits  13  to  15 


k  and  Clear  Line  Counter*  Output 


Cursor  and  Bit-Map  Area*  Flag  Output 


'Output  10  clock  cycles  after  trailing  edge  of  HSYNC.  See  figure  for 
timing  example. 


Graphics  Mode  Pin  Utilization 


Pin 

No.  Name 

Direction 

Function 

35-37  AD13tOl5 

IN/OUT 

Address  and  Data  Bits  13  to  15 

38  A16 

OUT 

Address  Bit  16  Output 

39  A17 

OUT 

Address  Bit  17  Output 

Block  Diagram 


DREQi 
DACKO-* 


DMA 

Control 


DB-0to7^f£) 

A-Oo-* 
RDO-* 
WR 


Microprocessor 
Interface 


Status  Reg 
DATA  READ  Reg. 


FIFO 
Buffer 
16x9 


ma     c  HSYNC 

--OV/EXTSYNC 


Command 
Processor 
with 
Control  ROM 
128x14 


Memory 
-*]  Timing 
Generator 


-*OALE 
DBIN 


Zoom  &  Pan 
Controller 


Parameter 
RAM 
16x8 


+  5VO- 
GNDo- 
xWCLKO 


Display 
Memory 
Controller 
with 
Refresh  Counter 
Line  Counter 
RMW  Data  Path 


A-17 
A-16 
•*oAD-15 
AD-14 
••OAD-13 


G3>a 


Light  Pen 
Deglitch  and 
Register 
Logic 


6-48 


HPD7220 


GDC  Components 

Microprocessor  Bus  Interface 

Control  of  the  GDC  by  the  system  microprocessor  is 
achieved  through  an  8-bit  bidirectional  interface.  The  status 
register  is  readable  at  any  time.  Access  to  the  FIFO  buffer 
is  coordinated  through  flags  in  the  status  register  and  oper- 
ates independently  of  the  various  internal  GDC  operations, 
due  to  the  separate  data  bus  connecting  the  interface  and 
the  FIFO  buffer. 

Command  Processor 

The  contents  of  the  FIFO  are  interpreted  by  the  command 
processor.  The  command  bytes  are  decoded,  and  the 
succeeding  parameters  are  distributed  to  their  proper 
destinations  within  the  GDC.  The  command  processor 
yields  to  the  bus  interface  when  both  access  the  FIFO 
simultaneously. 

DMA  Control 

The  DMA  control  circuitry  in  the  GDC  coordinates  trans- 
fers over  the  microprocessor  interface  when  using  an  exter- 
nal DMA  controller.  The  DMA  Request  and  Acknowledge 
handshake  lines  directly  interface  with  a  /uPD8257  or 
juPD8237  DMA  controller,  so  that  display  data  can  be 
moved  between  the  microprocessor  memory  and  the  dis- 
play memory. 

Parameter  RAM 

The  16-byte  RAM  stores  parameters  that  are  used 
repetitively  during  the  display  and  drawing  processes.  In 
character  mode,  this  RAM  holds  four  sets  of  partitioned 
display  area  parameters;  in  graphics  mode,  the  drawing 
pattern  and  graphics  character  take  the  place  of  two  of  the 
sets  of  parameters. 

Video  Sync  Generator 

Based  on  the  clock  input,  the  sync  logic  generates 
the  raster  timing  signals  for  almost  any  interlaced,  non- 
interlaced, or  "repeat  field"  interlaced  video  format.  The 
generator  is  programmed  during  the  idle  period  following 
a  reset.  In  video  sync  slave  mode,  it  coordinates  timing 
between  multiple  GDCs. 

Memory  Timing  Generator 

The  memory  timing  circuitry  provides  two  memory  cycle 
types:  a  two-clock  period  refresh  cycle  and  the  read- 
modify-write  (RMW)  cycle  which  takes  four  clock  periods. 
The  memory  control  signals  needed  to  drive  the  display 
memory  devices  are  easily  generated  from  the  GDC's  ALE 
and  DBIN  outputs. 

Zoom  &  Pan  Controller 

Based  on  the  programmable  zoom  display  factor  and  the 
display  area  entries  in  the  parameter  RAM,  the  zoom  and 
pan  controller  determines  when  to  advance  to  the  next 
memory  address  for  display  refresh  and  when  to  go  on  to 
the  next  display  area.  A  horizontal  zoom  is  produced  by 
slowing  down  the  display  refresh  rate  while  maintaining  the 
video  sync  rates.  Vertical  zoom  is  accomplished  by  repeat- 
edly accessing  each  line  a  number  of  times  equal  to  the 
horizontal  repeat.  Once  the  line  count  for  a  display  area  is 


exhausted,  the  controller  accesses  the  starting  address 
and  line  count  of  the  next  display  area  from  the  parameter 
RAM.  The  system  microprocessor,  by  modifying  a  display 
area  starting  address,  can  pan  in  any  direction,  indepen- 
dently of  the  other  display  areas. 

Drawing  Controller 

The  drawing  processor  contains  the  logic  necessary  to 
calculate  the  addresses  and  positions  of  the  pixels  of  the 
various  graphics  figures.  Given  a  starting  point  and  the 
appropriate  drawing  parameters,  the  drawing  controller 
needs  no  further  assistance  to  complete  the  figure  drawing. 

Display  Memory  Controller 

The  display  memory  controller's  tasks  are  numerous.  Its 
primary  purpose  is  to  multiplex  the  address  and  data  infor- 
mation in  and  out  of  the  display  memory.  It  also  contains 
the  16-bit  logic  unit  used  to  modify  the  display  memory 
contents  during  RMW  cycles,  the  character  mode  line 
counter,  and  the  refresh  counter  for  dynamic  RAMs.  The 
memory  controller  apportions  the  video  field  time  between 
the  various  types  of  cycles. 

Light  Pen  Deglitcher 

Only  if  two  rising  edges  on  the  light  pen  input  occur  at  the 
same  point  during  successive  video  fields  are  the  pulses 
accepted  as  a  valid  light  pen  detection.  A  status  bit  indi- 
cates to  the  system  microprocessor  that  the  light  pen 
register  contains  a  valid  address. 

Programmer's  View  of  GDC 

The  GDC  occupies  two  addresses  on  the  system  micro- 
processor bus  through  which  the  GDC's  status  register  and 
FIFO  are  accessed.  Commands  and  parameters  are  writ- 
ten into  the  GDC's  FIFO  and  are  differentiated  based  on 
address  bit  AO.  The  status  register  or  the  FIFO  can  be  read 
as  selected  by  the  address  line. 


AO 

READ 

WRITE 

0 

Status  Register 

Parameter  Into  FIFO 

I     I     I     I     I     I  I 

I     I     I     I     I     I  I 

1 

FIFO  Read 

Command  Into  FIFO 

I     I     I     I     I     I     I     I  I 

I     I     1     I     I     I     I     I  I 

GDC  Microprocessor  Bus  Interface  Registers 


Commands  to  the  GDC  take  the  form  of  a  command  byte 
followed  by  a  series  of  parameter  bytes  as  needed  for 
specifying  the  details  of  the  command.  The  command  pro- 
cessor decodes  the  commands,  unpacks  the  parameters, 
loads  them  into  the  appropriate  registers  within  the  GDC, 
and  initiates  the  required  operations. 

The  commands  available  in  the  GDC  can  be  organized  into 
five  categories  as  described  in  the  following  section. 


6-49 


fPD7220 


GDC  Command  Summary 

Video  Control  Commands 

1.  RESET     Resets  the  GDC  to  its  idle  state. 

2.  SYNC       Specifies  the  video  display  format. 

3.  VSYNC     Selects  master  or  slave  video  synchro- 

nization mode. 

4.  CCHAR     Specifies  the  cursor  and  character  row 

heights. 

Display  Control  Commands 

1 .  START     Ends  Idle  mode  and  unblanks 

the  display. 

2.  BCTRL     Controls  the  blanking  and  unblanking  of 

the  display. 

3.  ZOOM      Specifies  zoom  factors  for  the  display 

and  graphics  characters  writing. 

4.  CURS      Sets  the  position  of  the  cursor  in 

display  memory. 

5.  PRAM      Defines  starting  addresses  and  lengths 

of  the  display  areas  and  specifies  the 
eight  bytes  for  the  graphics  character. 

6.  PITCH      Specifies  the  width  of  the  X  dimension 

of  display  memory. 

Drawing  Control  Commands 

1.  WDAT      Writes  data  words  or  bytes  into 

display  memory. 

2.  MASK      Sets  the  mask  register  contents. 

3.  FIGS       Specifies  the  parameters  for  the 

drawing  controller. 

4.  FIGD       Draws  the  figure  as  specified  above. 

5.  GCHRD    Draws  the  graphics  character  into 

display  memory. 

Data  Read  Commands 

1.  RDAT:      Reads  data  words  or  bytes  from 

display  memory. 

2.  CURD:     Reads  the  cursor  position. 

3.  LPRD:      Reads  the  light  pen  address. 

DMA  Control  Commands 

1.  DMAR      Requests  a  DMA  read  transfer. 

2.  DMAW      Requests  a  DMA  write  transfer. 


Status  Register  Flags 


7  6  5  4  3  2  1  0 


a  n  n  t — Data  Ready 

I  FIFO  Full 

I  FIFO  Empty 

<  Drawing  in  Progress 

•  DMA  Execu